1 /*
2 * Low-level PXA250/210 sleep/wakeUp support
3 *
4 * Initial SA1110 code:
5 * Copyright (c) 2001 Cliff Brake <cbrake@accel
6 *
7 * Adapted for PXA by Nicolas Pitre:
8 * Copyright (c) 2002 Monta Vista Software, In
9 *
10 * This program is free software; you can redi
11 * modify it under the terms of the GNU Genera
12 */
13
14 #include <linux/linkage.h>
15 #include <asm/assembler.h>
16 #include "smemc.h"
17 #include "pxa2xx-regs.h"
18
19 #define MDREFR_KDIV 0x200a4000 // all
20 #define CCCR_SLEEP 0x00000107 // L=7
21 #define CCCR_N_MASK 0x00000380
22 #define CCCR_M_MASK 0x00000060
23 #define CCCR_L_MASK 0x0000001f
24 .text
25
26 #ifdef CONFIG_PXA3xx
27 /*
28 * pxa3xx_finish_suspend() - forces CPU into s
29 */
30 ENTRY(pxa3xx_finish_suspend)
31 mov r0, #0x06 @ S2D3
32 mcr p14, 0, r0, c7, c0, 0 @ ente
33
34 20: b 20b @ wait
35 #endif /* CONFIG_PXA3xx */
36
37 #ifdef CONFIG_PXA27x
38 /*
39 * pxa27x_finish_suspend()
40 *
41 * Forces CPU into sleep state.
42 *
43 * r0 = value for PWRMODE M field for desired
44 */
45 ENTRY(pxa27x_finish_suspend)
46 @ Put the processor to sleep
47 @ (also workaround for sighting 28071)
48
49 @ prepare value for sleep mode
50 mov r1, r0
51
52 @ prepare pointer to physical address
53 mov r2, #UNCACHED_PHYS_0
54
55 @ prepare SDRAM refresh settings
56 ldr r4, =MDREFR
57 ldr r5, [r4]
58
59 @ enable SDRAM self-refresh mode
60 orr r5, r5, #MDREFR_SLFRSH
61
62 @ set SDCLKx divide-by-2 bits (this is
63 ldr r6, =MDREFR_KDIV
64 orr r5, r5, r6
65
66 @ Intel PXA270 Specification Update no
67 @ with core operating above 91 MHz
68 @ (see Errata 50, ...processor does no
69
70 ldr r6, =CCCR
71 ldr r8, [r6] @ keep
72
73 ldr r7, =CCCR_SLEEP @ prep
74 mov r0, #0x2 @ prep
75
76 @ align execution to a cache line
77 b pxa_cpu_do_suspend
78 #endif
79
80 #ifdef CONFIG_PXA25x
81 /*
82 * pxa25x_finish_suspend()
83 *
84 * Forces CPU into sleep state.
85 *
86 * r0 = value for PWRMODE M field for desired
87 */
88
89 ENTRY(pxa25x_finish_suspend)
90 @ prepare value for sleep mode
91 mov r1, r0
92
93 @ prepare pointer to physical address
94 mov r2, #UNCACHED_PHYS_0
95
96 @ prepare SDRAM refresh settings
97 ldr r4, =MDREFR
98 ldr r5, [r4]
99
100 @ enable SDRAM self-refresh mode
101 orr r5, r5, #MDREFR_SLFRSH
102
103 @ Intel PXA255 Specification Update no
104 @ about suspending with PXBus operatin
105 @ (see Errata 31, GPIO output signals,
106 @
107 @ We keep the change-down close to the
108 @ as possible to eliminate messing abo
109 @ as the system will restore with the
110 @
111 @ Ben Dooks, 13-Sep-2004
112
113 ldr r6, =CCCR
114 ldr r8, [r6] @ keep
115
116 @ ensure x1 for run and turbo mode wit
117 bic r7, r8, #CCCR_M_MASK | CCCR_N_
118 orr r7, r7, #(1<<5) | (2<<7)
119
120 @ check that the memory frequency is w
121 and r14, r7, #CCCR_L_MASK
122 teq r14, #1
123 bicne r7, r7, #CCCR_L_MASK
124 orrne r7, r7, #1
125
126 @ get ready for the change
127
128 @ note, turbo is not preserved over sl
129 @ point in preserving it here. we save
130 @ other CP registers instead.
131 mov r0, #0
132 mcr p14, 0, r0, c6, c0, 0
133 orr r0, r0, #2
134 b pxa_cpu_do_suspend
135 #endif
136
137 .ltorg
138 .align 5
139 pxa_cpu_do_suspend:
140
141 @ All needed values are now in registe
142 @ These last instructions should be in
143
144 @ initiate the frequency change...
145 str r7, [r6]
146 mcr p14, 0, r0, c6, c0, 0
147
148 @ restore the original cpu speed value
149 str r8, [r6]
150
151 @ need 6 13-MHz cycles before changing
152 @ just set frequency to 91-MHz... 6*91
153
154 mov r0, #42
155 10: subs r0, r0, #1
156 bne 10b
157
158 @ Do not reorder...
159 @ Intel PXA270 Specification Update no
160 @ external accesses after SDRAM is put
161 @ (see Errata 38 ...hangs when enterin
162
163 @ force address lines low by reading a
164 ldr r3, [r2]
165
166 @ put SDRAM into self-refresh
167 str r5, [r4]
168
169 @ enter sleep mode
170 mcr p14, 0, r1, c7, c0, 0
171
172 20: b 20b
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