1 /* SPDX-License-Identifier: GPL-2.0 */ 1 2 /* linux/arch/arm/plat-s3c64xx/include/mach/re 3 * 4 * Copyright 2008 Openmoko, Inc. 5 * Copyright 2008 Simtec Electronics 6 * Ben Dooks <ben@simtec.co.uk> 7 * http://armlinux.simtec.co.uk/ 8 * 9 * S3C64XX - GPIO register definitions 10 */ 11 12 #ifndef __ASM_PLAT_S3C64XX_REGS_GPIO_H 13 #define __ASM_PLAT_S3C64XX_REGS_GPIO_H __FILE_ 14 15 /* Base addresses for each of the banks */ 16 17 #define S3C64XX_GPIOREG(reg) (S3C64XX_VA_GP 18 19 #define S3C64XX_GPA_BASE S3C64XX_GPIORE 20 #define S3C64XX_GPB_BASE S3C64XX_GPIORE 21 #define S3C64XX_GPC_BASE S3C64XX_GPIORE 22 #define S3C64XX_GPD_BASE S3C64XX_GPIORE 23 #define S3C64XX_GPE_BASE S3C64XX_GPIORE 24 #define S3C64XX_GPF_BASE S3C64XX_GPIORE 25 #define S3C64XX_GPG_BASE S3C64XX_GPIORE 26 #define S3C64XX_GPH_BASE S3C64XX_GPIORE 27 #define S3C64XX_GPI_BASE S3C64XX_GPIORE 28 #define S3C64XX_GPJ_BASE S3C64XX_GPIORE 29 #define S3C64XX_GPK_BASE S3C64XX_GPIORE 30 #define S3C64XX_GPL_BASE S3C64XX_GPIORE 31 #define S3C64XX_GPM_BASE S3C64XX_GPIORE 32 #define S3C64XX_GPN_BASE S3C64XX_GPIORE 33 #define S3C64XX_GPO_BASE S3C64XX_GPIORE 34 #define S3C64XX_GPP_BASE S3C64XX_GPIORE 35 #define S3C64XX_GPQ_BASE S3C64XX_GPIORE 36 37 /* SPCON */ 38 39 #define S3C64XX_SPCON S3C64XX_GPIORE 40 41 #define S3C64XX_SPCON_DRVCON_CAM_MASK 42 #define S3C64XX_SPCON_DRVCON_CAM_SHIFT 43 #define S3C64XX_SPCON_DRVCON_CAM_2mA 44 #define S3C64XX_SPCON_DRVCON_CAM_4mA 45 #define S3C64XX_SPCON_DRVCON_CAM_7mA 46 #define S3C64XX_SPCON_DRVCON_CAM_9mA 47 48 #define S3C64XX_SPCON_DRVCON_HSSPI_MASK 49 #define S3C64XX_SPCON_DRVCON_HSSPI_SHIFT 50 #define S3C64XX_SPCON_DRVCON_HSSPI_2mA 51 #define S3C64XX_SPCON_DRVCON_HSSPI_4mA 52 #define S3C64XX_SPCON_DRVCON_HSSPI_7mA 53 #define S3C64XX_SPCON_DRVCON_HSSPI_9mA 54 55 #define S3C64XX_SPCON_DRVCON_HSMMC_MASK 56 #define S3C64XX_SPCON_DRVCON_HSMMC_SHIFT 57 #define S3C64XX_SPCON_DRVCON_HSMMC_2mA 58 #define S3C64XX_SPCON_DRVCON_HSMMC_4mA 59 #define S3C64XX_SPCON_DRVCON_HSMMC_7mA 60 #define S3C64XX_SPCON_DRVCON_HSMMC_9mA 61 62 #define S3C64XX_SPCON_DRVCON_LCD_MASK 63 #define S3C64XX_SPCON_DRVCON_LCD_SHIFT 64 #define S3C64XX_SPCON_DRVCON_LCD_2mA 65 #define S3C64XX_SPCON_DRVCON_LCD_4mA 66 #define S3C64XX_SPCON_DRVCON_LCD_7mA 67 #define S3C64XX_SPCON_DRVCON_LCD_9mA 68 69 #define S3C64XX_SPCON_DRVCON_MODEM_MASK 70 #define S3C64XX_SPCON_DRVCON_MODEM_SHIFT 71 #define S3C64XX_SPCON_DRVCON_MODEM_2mA 72 #define S3C64XX_SPCON_DRVCON_MODEM_4mA 73 #define S3C64XX_SPCON_DRVCON_MODEM_7mA 74 #define S3C64XX_SPCON_DRVCON_MODEM_9mA 75 76 #define S3C64XX_SPCON_nRSTOUT_OEN 77 78 #define S3C64XX_SPCON_DRVCON_SPICLK1_MASK 79 #define S3C64XX_SPCON_DRVCON_SPICLK1_SHIFT 80 #define S3C64XX_SPCON_DRVCON_SPICLK1_2mA 81 #define S3C64XX_SPCON_DRVCON_SPICLK1_4mA 82 #define S3C64XX_SPCON_DRVCON_SPICLK1_7mA 83 #define S3C64XX_SPCON_DRVCON_SPICLK1_9mA 84 85 #define S3C64XX_SPCON_MEM1_DQS_PUD_MASK 86 #define S3C64XX_SPCON_MEM1_DQS_PUD_SHIFT 87 #define S3C64XX_SPCON_MEM1_DQS_PUD_DISABLED 88 #define S3C64XX_SPCON_MEM1_DQS_PUD_DOWN 89 #define S3C64XX_SPCON_MEM1_DQS_PUD_UP 90 91 #define S3C64XX_SPCON_MEM1_D_PUD1_MASK 92 #define S3C64XX_SPCON_MEM1_D_PUD1_SHIFT 93 #define S3C64XX_SPCON_MEM1_D_PUD1_DISABLED 94 #define S3C64XX_SPCON_MEM1_D_PUD1_DOWN 95 #define S3C64XX_SPCON_MEM1_D_PUD1_UP 96 97 #define S3C64XX_SPCON_MEM1_D_PUD0_MASK 98 #define S3C64XX_SPCON_MEM1_D_PUD0_SHIFT 99 #define S3C64XX_SPCON_MEM1_D_PUD0_DISABLED 100 #define S3C64XX_SPCON_MEM1_D_PUD0_DOWN 101 #define S3C64XX_SPCON_MEM1_D_PUD0_UP 102 103 #define S3C64XX_SPCON_MEM0_D_PUD_MASK 104 #define S3C64XX_SPCON_MEM0_D_PUD_SHIFT 105 #define S3C64XX_SPCON_MEM0_D_PUD_DISABLED 106 #define S3C64XX_SPCON_MEM0_D_PUD_DOWN 107 #define S3C64XX_SPCON_MEM0_D_PUD_UP 108 109 #define S3C64XX_SPCON_USBH_DMPD 110 #define S3C64XX_SPCON_USBH_DPPD 111 #define S3C64XX_SPCON_USBH_PUSW2 112 #define S3C64XX_SPCON_USBH_PUSW1 113 #define S3C64XX_SPCON_USBH_SUSPND 114 115 #define S3C64XX_SPCON_LCD_SEL_MASK 116 #define S3C64XX_SPCON_LCD_SEL_SHIFT 117 #define S3C64XX_SPCON_LCD_SEL_HOST 118 #define S3C64XX_SPCON_LCD_SEL_RGB 119 #define S3C64XX_SPCON_LCD_SEL_606_656 120 121 122 /* External interrupt registers */ 123 124 #define S3C64XX_EINT12CON S3C64XX_GPIORE 125 #define S3C64XX_EINT34CON S3C64XX_GPIORE 126 #define S3C64XX_EINT56CON S3C64XX_GPIORE 127 #define S3C64XX_EINT78CON S3C64XX_GPIORE 128 #define S3C64XX_EINT9CON S3C64XX_GPIORE 129 130 #define S3C64XX_EINT12FLTCON S3C64XX_GPIORE 131 #define S3C64XX_EINT34FLTCON S3C64XX_GPIORE 132 #define S3C64XX_EINT56FLTCON S3C64XX_GPIORE 133 #define S3C64XX_EINT78FLTCON S3C64XX_GPIORE 134 #define S3C64XX_EINT9FLTCON S3C64XX_GPIORE 135 136 #define S3C64XX_EINT12MASK S3C64XX_GPIORE 137 #define S3C64XX_EINT34MASK S3C64XX_GPIORE 138 #define S3C64XX_EINT56MASK S3C64XX_GPIORE 139 #define S3C64XX_EINT78MASK S3C64XX_GPIORE 140 #define S3C64XX_EINT9MASK S3C64XX_GPIORE 141 142 #define S3C64XX_EINT12PEND S3C64XX_GPIORE 143 #define S3C64XX_EINT34PEND S3C64XX_GPIORE 144 #define S3C64XX_EINT56PEND S3C64XX_GPIORE 145 #define S3C64XX_EINT78PEND S3C64XX_GPIORE 146 #define S3C64XX_EINT9PEND S3C64XX_GPIORE 147 148 #define S3C64XX_PRIORITY S3C64XX_GPIORE 149 #define S3C64XX_PRIORITY_ARB(x) (1 << (x)) 150 151 #define S3C64XX_SERVICE S3C64XX_GPIORE 152 #define S3C64XX_SERVICEPEND S3C64XX_GPIORE 153 154 #define S3C64XX_EINT0CON0 S3C64XX_GPIORE 155 #define S3C64XX_EINT0CON1 S3C64XX_GPIORE 156 #define S3C64XX_EINT0FLTCON0 S3C64XX_GPIORE 157 #define S3C64XX_EINT0FLTCON1 S3C64XX_GPIORE 158 #define S3C64XX_EINT0FLTCON2 S3C64XX_GPIORE 159 #define S3C64XX_EINT0FLTCON3 S3C64XX_GPIORE 160 161 #define S3C64XX_EINT0MASK S3C64XX_GPIORE 162 #define S3C64XX_EINT0PEND S3C64XX_GPIORE 163 164 /* GPIO sleep configuration */ 165 166 #define S3C64XX_SPCONSLP S3C64XX_GPIORE 167 168 #define S3C64XX_SPCONSLP_TDO_PULLDOWN (1 << 169 #define S3C64XX_SPCONSLP_CKE1INIT (1 << 170 171 #define S3C64XX_SPCONSLP_RSTOUT_MASK (0x3 < 172 #define S3C64XX_SPCONSLP_RSTOUT_OUT0 (0x0 < 173 #define S3C64XX_SPCONSLP_RSTOUT_OUT1 (0x1 < 174 #define S3C64XX_SPCONSLP_RSTOUT_HIZ (0x2 < 175 176 #define S3C64XX_SPCONSLP_KPCOL_MASK (0x3 < 177 #define S3C64XX_SPCONSLP_KPCOL_OUT0 (0x0 < 178 #define S3C64XX_SPCONSLP_KPCOL_OUT1 (0x1 < 179 #define S3C64XX_SPCONSLP_KPCOL_INP (0x2 < 180 181 182 #define S3C64XX_SLPEN S3C64XX_GPIORE 183 184 #define S3C64XX_SLPEN_USE_xSLP (1 << 185 #define S3C64XX_SLPEN_CFG_BYSLPEN (1 << 186 187 #endif /* __ASM_PLAT_S3C64XX_REGS_GPIO_H */ 188 189
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