1 /* SPDX-License-Identifier: GPL-2.0-only */ 1 2 /* 3 * Copyright 2008 Openmoko, Inc. 4 * Copyright 2008 Simtec Electronics 5 * http://armlinux.simtec.co.uk/ 6 * Ben Dooks <ben@simtec.co.uk> 7 * 8 * S3C64XX - syscon power and sleep control re 9 */ 10 11 #ifndef __MACH_S3C64XX_REGS_SYSCON_POWER_H 12 #define __MACH_S3C64XX_REGS_SYSCON_POWER_H __F 13 14 #define S3C64XX_PWR_CFG 15 16 #define S3C64XX_PWRCFG_OSC_OTG_DISABLE 17 #define S3C64XX_PWRCFG_MMC2_DISABLE 18 #define S3C64XX_PWRCFG_MMC1_DISABLE 19 #define S3C64XX_PWRCFG_MMC0_DISABLE 20 #define S3C64XX_PWRCFG_HSI_DISABLE 21 #define S3C64XX_PWRCFG_TS_DISABLE 22 #define S3C64XX_PWRCFG_RTC_TICK_DISABLE 23 #define S3C64XX_PWRCFG_RTC_ALARM_DISABLE 24 #define S3C64XX_PWRCFG_MSM_DISABLE 25 #define S3C64XX_PWRCFG_KEY_DISABLE 26 #define S3C64XX_PWRCFG_BATF_DISABLE 27 28 #define S3C64XX_PWRCFG_CFG_WFI_MASK 29 #define S3C64XX_PWRCFG_CFG_WFI_SHIFT 30 #define S3C64XX_PWRCFG_CFG_WFI_IGNORE 31 #define S3C64XX_PWRCFG_CFG_WFI_IDLE 32 #define S3C64XX_PWRCFG_CFG_WFI_STOP 33 #define S3C64XX_PWRCFG_CFG_WFI_SLEEP 34 35 #define S3C64XX_PWRCFG_CFG_BATFLT_MASK 36 #define S3C64XX_PWRCFG_CFG_BATFLT_SHIFT 37 #define S3C64XX_PWRCFG_CFG_BATFLT_IGNORE 38 #define S3C64XX_PWRCFG_CFG_BATFLT_IRQ 39 #define S3C64XX_PWRCFG_CFG_BATFLT_SLEEP 40 41 #define S3C64XX_PWRCFG_CFG_BAT_WAKE 42 #define S3C64XX_PWRCFG_OSC27_EN 43 44 #define S3C64XX_EINT_MASK 45 46 #define S3C64XX_NORMAL_CFG 47 48 #define S3C64XX_NORMALCFG_IROM_ON 49 #define S3C64XX_NORMALCFG_DOMAIN_ETM_ON 50 #define S3C64XX_NORMALCFG_DOMAIN_S_ON 51 #define S3C64XX_NORMALCFG_DOMAIN_F_ON 52 #define S3C64XX_NORMALCFG_DOMAIN_P_ON 53 #define S3C64XX_NORMALCFG_DOMAIN_I_ON 54 #define S3C64XX_NORMALCFG_DOMAIN_G_ON 55 #define S3C64XX_NORMALCFG_DOMAIN_V_ON 56 57 #define S3C64XX_STOP_CFG 58 59 #define S3C64XX_STOPCFG_MEMORY_ARM_ON 60 #define S3C64XX_STOPCFG_TOP_MEMORY_ON 61 #define S3C64XX_STOPCFG_ARM_LOGIC_ON 62 #define S3C64XX_STOPCFG_TOP_LOGIC_ON 63 #define S3C64XX_STOPCFG_OSC_EN 64 65 #define S3C64XX_SLEEP_CFG 66 67 #define S3C64XX_SLEEPCFG_OSC_EN 68 69 #define S3C64XX_STOP_MEM_CFG 70 71 #define S3C64XX_STOPMEMCFG_MODEMIF_RETAIN 72 #define S3C64XX_STOPMEMCFG_HOSTIF_RETAIN 73 #define S3C64XX_STOPMEMCFG_OTG_RETAIN 74 #define S3C64XX_STOPMEMCFG_HSMCC_RETAIN 75 #define S3C64XX_STOPMEMCFG_IROM_RETAIN 76 #define S3C64XX_STOPMEMCFG_IRDA_RETAIN 77 #define S3C64XX_STOPMEMCFG_NFCON_RETAIN 78 79 #define S3C64XX_OSC_STABLE 80 #define S3C64XX_PWR_STABLE 81 82 #define S3C64XX_WAKEUP_STAT 83 84 #define S3C64XX_WAKEUPSTAT_MMC2 85 #define S3C64XX_WAKEUPSTAT_MMC1 86 #define S3C64XX_WAKEUPSTAT_MMC0 87 #define S3C64XX_WAKEUPSTAT_HSI 88 #define S3C64XX_WAKEUPSTAT_BATFLT 89 #define S3C64XX_WAKEUPSTAT_MSM 90 #define S3C64XX_WAKEUPSTAT_KEY 91 #define S3C64XX_WAKEUPSTAT_TS 92 #define S3C64XX_WAKEUPSTAT_RTC_TICK 93 #define S3C64XX_WAKEUPSTAT_RTC_ALARM 94 #define S3C64XX_WAKEUPSTAT_EINT 95 96 #define S3C64XX_BLK_PWR_STAT 97 98 #define S3C64XX_BLKPWRSTAT_G 99 #define S3C64XX_BLKPWRSTAT_ETM 100 #define S3C64XX_BLKPWRSTAT_S 101 #define S3C64XX_BLKPWRSTAT_F 102 #define S3C64XX_BLKPWRSTAT_P 103 #define S3C64XX_BLKPWRSTAT_I 104 #define S3C64XX_BLKPWRSTAT_V 105 #define S3C64XX_BLKPWRSTAT_TOP 106 107 #define S3C64XX_INFORM0 108 #define S3C64XX_INFORM1 109 #define S3C64XX_INFORM2 110 #define S3C64XX_INFORM3 111 112 #endif /* __MACH_S3C64XX_REGS_SYSCON_POWER_H * 113
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