1 /* SPDX-License-Identifier: GPL-2.0 */ 1 2 /* 3 * Copyright (c) 2010 Samsung Electronics Co., 4 * http://www.samsung.com/ 5 * 6 * S5PV210 - Clock register definitions 7 */ 8 9 #ifndef __ASM_ARCH_REGS_CLOCK_H 10 #define __ASM_ARCH_REGS_CLOCK_H __FILE__ 11 12 #define S3C_ADDR_BASE 0xF6000000 13 #define S3C_ADDR(x) ((void __iomem 14 #define S3C_VA_SYS S3C_ADDR(0x001 15 16 #define S5P_CLKREG(x) (S3C_VA_SYS + 17 18 #define S5P_APLL_LOCK S5P_CLKREG(0x0 19 #define S5P_MPLL_LOCK S5P_CLKREG(0x0 20 #define S5P_EPLL_LOCK S5P_CLKREG(0x1 21 #define S5P_VPLL_LOCK S5P_CLKREG(0x2 22 23 #define S5P_APLL_CON S5P_CLKREG(0x1 24 #define S5P_MPLL_CON S5P_CLKREG(0x1 25 #define S5P_EPLL_CON S5P_CLKREG(0x1 26 #define S5P_EPLL_CON1 S5P_CLKREG(0x1 27 #define S5P_VPLL_CON S5P_CLKREG(0x1 28 29 #define S5P_CLK_SRC0 S5P_CLKREG(0x2 30 #define S5P_CLK_SRC1 S5P_CLKREG(0x2 31 #define S5P_CLK_SRC2 S5P_CLKREG(0x2 32 #define S5P_CLK_SRC3 S5P_CLKREG(0x2 33 #define S5P_CLK_SRC4 S5P_CLKREG(0x2 34 #define S5P_CLK_SRC5 S5P_CLKREG(0x2 35 #define S5P_CLK_SRC6 S5P_CLKREG(0x2 36 37 #define S5P_CLK_SRC_MASK0 S5P_CLKREG(0x2 38 #define S5P_CLK_SRC_MASK1 S5P_CLKREG(0x2 39 40 #define S5P_CLK_DIV0 S5P_CLKREG(0x3 41 #define S5P_CLK_DIV1 S5P_CLKREG(0x3 42 #define S5P_CLK_DIV2 S5P_CLKREG(0x3 43 #define S5P_CLK_DIV3 S5P_CLKREG(0x3 44 #define S5P_CLK_DIV4 S5P_CLKREG(0x3 45 #define S5P_CLK_DIV5 S5P_CLKREG(0x3 46 #define S5P_CLK_DIV6 S5P_CLKREG(0x3 47 #define S5P_CLK_DIV7 S5P_CLKREG(0x3 48 49 #define S5P_CLKGATE_MAIN0 S5P_CLKREG(0x4 50 #define S5P_CLKGATE_MAIN1 S5P_CLKREG(0x4 51 #define S5P_CLKGATE_MAIN2 S5P_CLKREG(0x4 52 53 #define S5P_CLKGATE_PERI0 S5P_CLKREG(0x4 54 #define S5P_CLKGATE_PERI1 S5P_CLKREG(0x4 55 56 #define S5P_CLKGATE_SCLK0 S5P_CLKREG(0x4 57 #define S5P_CLKGATE_SCLK1 S5P_CLKREG(0x4 58 #define S5P_CLKGATE_IP0 S5P_CLKREG(0x4 59 #define S5P_CLKGATE_IP1 S5P_CLKREG(0x4 60 #define S5P_CLKGATE_IP2 S5P_CLKREG(0x4 61 #define S5P_CLKGATE_IP3 S5P_CLKREG(0x4 62 #define S5P_CLKGATE_IP4 S5P_CLKREG(0x4 63 64 #define S5P_CLKGATE_BLOCK S5P_CLKREG(0x4 65 #define S5P_CLKGATE_BUS0 S5P_CLKREG(0x4 66 #define S5P_CLKGATE_BUS1 S5P_CLKREG(0x4 67 #define S5P_CLK_OUT S5P_CLKREG(0x5 68 69 /* DIV/MUX STATUS */ 70 #define S5P_CLKDIV_STAT0 S5P_CLKREG(0x1 71 #define S5P_CLKDIV_STAT1 S5P_CLKREG(0x1 72 #define S5P_CLKMUX_STAT0 S5P_CLKREG(0x1 73 #define S5P_CLKMUX_STAT1 S5P_CLKREG(0x1 74 75 /* CLKSRC0 */ 76 #define S5P_CLKSRC0_MUX200_SHIFT (16) 77 #define S5P_CLKSRC0_MUX200_MASK (0x1 < 78 #define S5P_CLKSRC0_MUX166_MASK (0x1<< 79 #define S5P_CLKSRC0_MUX133_MASK (0x1<< 80 81 /* CLKSRC2 */ 82 #define S5P_CLKSRC2_G3D_SHIFT (0) 83 #define S5P_CLKSRC2_G3D_MASK (0x3 < 84 #define S5P_CLKSRC2_MFC_SHIFT (4) 85 #define S5P_CLKSRC2_MFC_MASK (0x3 < 86 87 /* CLKSRC6*/ 88 #define S5P_CLKSRC6_ONEDRAM_SHIFT (24) 89 #define S5P_CLKSRC6_ONEDRAM_MASK (0x3 < 90 91 /* CLKDIV0 */ 92 #define S5P_CLKDIV0_APLL_SHIFT (0) 93 #define S5P_CLKDIV0_APLL_MASK (0x7 < 94 #define S5P_CLKDIV0_A2M_SHIFT (4) 95 #define S5P_CLKDIV0_A2M_MASK (0x7 < 96 #define S5P_CLKDIV0_HCLK200_SHIFT (8) 97 #define S5P_CLKDIV0_HCLK200_MASK (0x7 < 98 #define S5P_CLKDIV0_PCLK100_SHIFT (12) 99 #define S5P_CLKDIV0_PCLK100_MASK (0x7 < 100 #define S5P_CLKDIV0_HCLK166_SHIFT (16) 101 #define S5P_CLKDIV0_HCLK166_MASK (0xF < 102 #define S5P_CLKDIV0_PCLK83_SHIFT (20) 103 #define S5P_CLKDIV0_PCLK83_MASK (0x7 < 104 #define S5P_CLKDIV0_HCLK133_SHIFT (24) 105 #define S5P_CLKDIV0_HCLK133_MASK (0xF < 106 #define S5P_CLKDIV0_PCLK66_SHIFT (28) 107 #define S5P_CLKDIV0_PCLK66_MASK (0x7 < 108 109 /* CLKDIV2 */ 110 #define S5P_CLKDIV2_G3D_SHIFT (0) 111 #define S5P_CLKDIV2_G3D_MASK (0xF < 112 #define S5P_CLKDIV2_MFC_SHIFT (4) 113 #define S5P_CLKDIV2_MFC_MASK (0xF < 114 115 /* CLKDIV6 */ 116 #define S5P_CLKDIV6_ONEDRAM_SHIFT (28) 117 #define S5P_CLKDIV6_ONEDRAM_MASK (0xF < 118 119 #define S5P_SWRESET S5P_CLKREG(0x2 120 121 #define S5P_ARM_MCS_CON S5P_CLKREG(0x6 122 123 /* Registers related to power management */ 124 #define S5P_PWR_CFG S5P_CLKREG(0xC 125 #define S5P_EINT_WAKEUP_MASK S5P_CLKREG(0xC 126 #define S5P_WAKEUP_MASK S5P_CLKREG(0xC 127 #define S5P_PWR_MODE S5P_CLKREG(0xC 128 #define S5P_NORMAL_CFG S5P_CLKREG(0xC 129 #define S5P_IDLE_CFG S5P_CLKREG(0xC 130 #define S5P_STOP_CFG S5P_CLKREG(0xC 131 #define S5P_STOP_MEM_CFG S5P_CLKREG(0xC 132 #define S5P_SLEEP_CFG S5P_CLKREG(0xC 133 134 #define S5P_OSC_FREQ S5P_CLKREG(0xC 135 #define S5P_OSC_STABLE S5P_CLKREG(0xC 136 #define S5P_PWR_STABLE S5P_CLKREG(0xC 137 #define S5P_MTC_STABLE S5P_CLKREG(0xC 138 #define S5P_CLAMP_STABLE S5P_CLKREG(0xC 139 140 #define S5P_WAKEUP_STAT S5P_CLKREG(0xC 141 #define S5P_BLK_PWR_STAT S5P_CLKREG(0xC 142 143 #define S5P_OTHERS S5P_CLKREG(0xE 144 #define S5P_OM_STAT S5P_CLKREG(0xE 145 #define S5P_HDMI_PHY_CONTROL S5P_CLKREG(0xE 146 #define S5P_USB_PHY_CONTROL S5P_CLKREG(0xE 147 #define S5P_DAC_PHY_CONTROL S5P_CLKREG(0xE 148 149 #define S5P_INFORM0 S5P_CLKREG(0xF 150 #define S5P_INFORM1 S5P_CLKREG(0xF 151 #define S5P_INFORM2 S5P_CLKREG(0xF 152 #define S5P_INFORM3 S5P_CLKREG(0xF 153 #define S5P_INFORM4 S5P_CLKREG(0xF 154 #define S5P_INFORM5 S5P_CLKREG(0xF 155 #define S5P_INFORM6 S5P_CLKREG(0xF 156 #define S5P_INFORM7 S5P_CLKREG(0xF 157 158 #define S5P_RST_STAT S5P_CLKREG(0xA 159 #define S5P_OSC_CON S5P_CLKREG(0x8 160 #define S5P_MDNIE_SEL S5P_CLKREG(0x7 161 #define S5P_MIPI_PHY_CON0 S5P_CLKREG(0x7 162 #define S5P_MIPI_PHY_CON1 S5P_CLKREG(0x7 163 164 #define S5P_IDLE_CFG_TL_MASK (3 << 30) 165 #define S5P_IDLE_CFG_TM_MASK (3 << 28) 166 #define S5P_IDLE_CFG_TL_ON (2 << 30) 167 #define S5P_IDLE_CFG_TM_ON (2 << 28) 168 #define S5P_IDLE_CFG_DIDLE (1 << 0) 169 170 #define S5P_CFG_WFI_CLEAN (~(3 < 171 #define S5P_CFG_WFI_IDLE (1 << 172 #define S5P_CFG_WFI_STOP (2 << 173 #define S5P_CFG_WFI_SLEEP (3 << 174 175 #define S5P_OTHER_SYS_INT 24 176 #define S5P_OTHER_STA_TYPE 23 177 #define S5P_OTHER_SYSC_INTOFF (1 << 178 #define STA_TYPE_EXPON 0 179 #define STA_TYPE_SFR 1 180 181 #define S5P_PWR_STA_EXP_SCALE 0 182 #define S5P_PWR_STA_CNT 4 183 184 #define S5P_PWR_STABLE_COUNT 85500 185 186 #define S5P_SLEEP_CFG_OSC_EN (1 << 187 #define S5P_SLEEP_CFG_USBOSC_EN (1 << 188 189 /* OTHERS Resgister */ 190 #define S5P_OTHERS_USB_SIG_MASK (1 << 191 192 /* S5P_DAC_CONTROL */ 193 #define S5P_DAC_ENABLE (1) 194 #define S5P_DAC_DISABLE (0) 195 196 #endif /* __ASM_ARCH_REGS_CLOCK_H */ 197
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