1 /* SPDX-License-Identifier: GPL-2.0-only */ 1 2 /* 3 * Copyright (C) 2010 Google, Inc. 4 * 5 * Author: 6 * Colin Cross <ccross@google.com> 7 * Erik Gilling <konkers@google.com> 8 */ 9 10 #ifndef __MACH_TEGRA_IOMAP_H 11 #define __MACH_TEGRA_IOMAP_H 12 13 #include <linux/pgtable.h> 14 #include <linux/sizes.h> 15 16 #define TEGRA_IRAM_BASE 0x4000 17 #define TEGRA_IRAM_SIZE SZ_256 18 19 #define TEGRA_ARM_PERIF_BASE 0x5004 20 #define TEGRA_ARM_PERIF_SIZE SZ_8K 21 22 #define TEGRA_ARM_INT_DIST_BASE 0x5004 23 #define TEGRA_ARM_INT_DIST_SIZE SZ_4K 24 25 #define TEGRA_TMR1_BASE 0x6000 26 #define TEGRA_TMR1_SIZE SZ_8 27 28 #define TEGRA_TMR2_BASE 0x6000 29 #define TEGRA_TMR2_SIZE SZ_8 30 31 #define TEGRA_TMRUS_BASE 0x6000 32 #define TEGRA_TMRUS_SIZE SZ_64 33 34 #define TEGRA_TMR3_BASE 0x6000 35 #define TEGRA_TMR3_SIZE SZ_8 36 37 #define TEGRA_TMR4_BASE 0x6000 38 #define TEGRA_TMR4_SIZE SZ_8 39 40 #define TEGRA_CLK_RESET_BASE 0x6000 41 #define TEGRA_CLK_RESET_SIZE SZ_4K 42 43 #define TEGRA_FLOW_CTRL_BASE 0x6000 44 #define TEGRA_FLOW_CTRL_SIZE 20 45 46 #define TEGRA_SB_BASE 0x6000 47 #define TEGRA_SB_SIZE 256 48 49 #define TEGRA_EXCEPTION_VECTORS_BASE 0x6000 50 #define TEGRA_EXCEPTION_VECTORS_SIZE SZ_4K 51 52 #define TEGRA_APB_MISC_BASE 0x7000 53 #define TEGRA_APB_MISC_SIZE SZ_4K 54 55 #define TEGRA_UARTA_BASE 0x7000 56 #define TEGRA_UARTA_SIZE SZ_64 57 58 #define TEGRA_UARTB_BASE 0x7000 59 #define TEGRA_UARTB_SIZE SZ_64 60 61 #define TEGRA_UARTC_BASE 0x7000 62 #define TEGRA_UARTC_SIZE SZ_256 63 64 #define TEGRA_UARTD_BASE 0x7000 65 #define TEGRA_UARTD_SIZE SZ_256 66 67 #define TEGRA_UARTE_BASE 0x7000 68 #define TEGRA_UARTE_SIZE SZ_256 69 70 #define TEGRA_PMC_BASE 0x7000 71 #define TEGRA_PMC_SIZE SZ_256 72 73 #define TEGRA_EMC_BASE 0x7000 74 #define TEGRA_EMC_SIZE SZ_1K 75 76 #define TEGRA_EMC0_BASE 0x7001 77 #define TEGRA_EMC0_SIZE SZ_2K 78 79 #define TEGRA_EMC1_BASE 0x7001 80 #define TEGRA_EMC1_SIZE SZ_2K 81 82 #define TEGRA124_EMC_BASE 0x7001 83 #define TEGRA124_EMC_SIZE SZ_2K 84 85 #define TEGRA_CSITE_BASE 0x7004 86 #define TEGRA_CSITE_SIZE SZ_256 87 88 /* On TEGRA, many peripherals are very closely 89 * two 256MB io windows (that actually only us 90 * at the start of each). 91 * 92 * We will just map the first MMU section of e 93 * pt entries needed) and provide a macro to t 94 * io addresses to an appropriate void __iomem 95 */ 96 97 #define IO_IRAM_PHYS 0x40000000 98 #define IO_IRAM_VIRT IOMEM(0xFE400000) 99 #define IO_IRAM_SIZE SZ_256K 100 101 #define IO_CPU_PHYS 0x50040000 102 #define IO_CPU_VIRT IOMEM(0xFE440000) 103 #define IO_CPU_SIZE SZ_16K 104 105 #define IO_PPSB_PHYS 0x60000000 106 #define IO_PPSB_VIRT IOMEM(0xFE200000) 107 #define IO_PPSB_SIZE SECTION_SIZE 108 109 #define IO_APB_PHYS 0x70000000 110 #define IO_APB_VIRT IOMEM(0xFE000000) 111 #define IO_APB_SIZE SECTION_SIZE 112 113 #define IO_TO_VIRT_BETWEEN(p, st, sz) ((p) > 114 #define IO_TO_VIRT_XLATE(p, pst, vst) (((p) 115 116 #define IO_TO_VIRT(n) ( \ 117 IO_TO_VIRT_BETWEEN((n), IO_PPSB_PHYS, 118 IO_TO_VIRT_XLATE((n), IO_PPSB_ 119 IO_TO_VIRT_BETWEEN((n), IO_APB_PHYS, I 120 IO_TO_VIRT_XLATE((n), IO_APB_P 121 IO_TO_VIRT_BETWEEN((n), IO_CPU_PHYS, I 122 IO_TO_VIRT_XLATE((n), IO_CPU_P 123 IO_TO_VIRT_BETWEEN((n), IO_IRAM_PHYS, 124 IO_TO_VIRT_XLATE((n), IO_IRAM_ 125 NULL) 126 127 #define IO_ADDRESS(n) (IO_TO_VIRT(n)) 128 129 #endif 130
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