1 // SPDX-License-Identifier: GPL-2.0-only 1
2 /*
3 *
4 * arch/arm/probes/decode-arm.c
5 *
6 * Some code moved here from arch/arm/kernel/k
7 *
8 * Copyright (C) 2006, 2007 Motorola Inc.
9 */
10
11 #include <linux/kernel.h>
12 #include <linux/module.h>
13 #include <linux/stddef.h>
14 #include <linux/ptrace.h>
15
16 #include "decode.h"
17 #include "decode-arm.h"
18
19 #define sign_extend(x, signbit) ((x) | (0 - ((
20
21 #define branch_displacement(insn) sign_extend(
22
23 /*
24 * To avoid the complications of mimicing sing
25 * processor without a Next-PC or a single-ste
26 * avoid having to deal with the side-effects
27 * simulate or emulate (almost) all ARM instru
28 *
29 * "Simulation" is where the instruction's beh
30 * C code. "Emulation" is where the original
31 * and executed, often by altering its registe
32 *
33 * By having all behavior of the kprobe'd inst
34 * returning from the kprobe_handler(), all lo
35 * interrupt) can safely be released. There i
36 * breakpoints, no race with MP or preemptable
37 * clean up resources counts at a later time i
38 * performance. By rewriting the instruction,
39 * need to be loaded and saved back optimizing
40 *
41 * Calling the insnslot_*_rwflags version of a
42 * anything even when the CPSR flags aren't up
43 * instruction. It's just a little slower in
44 * a little space by not having a duplicate fu
45 * update the flags. (The same optimization c
46 * instructions that do or don't perform regis
47 * Also, instructions can either read the flag
48 * flags, or read and write the flags. To sav
49 * rather than for sheer performance, flag fun
50 * read and write of flags.
51 */
52
53 void __kprobes simulate_bbl(probes_opcode_t in
54 struct arch_probes_insn *asi,
55 {
56 long iaddr = (long) regs->ARM_pc - 4;
57 int disp = branch_displacement(insn);
58
59 if (insn & (1 << 24))
60 regs->ARM_lr = iaddr + 4;
61
62 regs->ARM_pc = iaddr + 8 + disp;
63 }
64
65 void __kprobes simulate_blx1(probes_opcode_t i
66 struct arch_probes_insn *asi,
67 {
68 long iaddr = (long) regs->ARM_pc - 4;
69 int disp = branch_displacement(insn);
70
71 regs->ARM_lr = iaddr + 4;
72 regs->ARM_pc = iaddr + 8 + disp + ((in
73 regs->ARM_cpsr |= PSR_T_BIT;
74 }
75
76 void __kprobes simulate_blx2bx(probes_opcode_t
77 struct arch_probes_insn *asi,
78 {
79 int rm = insn & 0xf;
80 long rmv = regs->uregs[rm];
81
82 if (insn & (1 << 5))
83 regs->ARM_lr = (long) regs->AR
84
85 regs->ARM_pc = rmv & ~0x1;
86 regs->ARM_cpsr &= ~PSR_T_BIT;
87 if (rmv & 0x1)
88 regs->ARM_cpsr |= PSR_T_BIT;
89 }
90
91 void __kprobes simulate_mrs(probes_opcode_t in
92 struct arch_probes_insn *asi,
93 {
94 int rd = (insn >> 12) & 0xf;
95 unsigned long mask = 0xf8ff03df; /* Ma
96 regs->uregs[rd] = regs->ARM_cpsr & mas
97 }
98
99 void __kprobes simulate_mov_ipsp(probes_opcode
100 struct arch_probes_insn *asi,
101 {
102 regs->uregs[12] = regs->uregs[13];
103 }
104
105 /*
106 * For the instruction masking and comparisons
107 * functions below, Do _not_ rearrange the ord
108 * you're very, very sure of what you are doin
109 * efficiency, the masks for some tests someti
110 * have been done prior to them so the number
111 * for an instruction set can be as broad as p
112 * number of tests needed.
113 */
114
115 static const union decode_item arm_1111_table[
116 /* Unconditional instructions
117
118 /* memory hint 1111 0100 x001
119 /* PLDI (immediate) 1111 0100 x101
120 /* PLDW (immediate) 1111 0101 x001
121 /* PLD (immediate) 1111 0101 x101
122 DECODE_SIMULATE (0xfe300000, 0xf410000
123
124 /* memory hint 1111 0110 x001
125 /* PLDI (register) 1111 0110 x101
126 /* PLDW (register) 1111 0111 x001
127 /* PLD (register) 1111 0111 x101
128 DECODE_SIMULATE (0xfe300010, 0xf610000
129
130 /* BLX (immediate) 1111 101x xxxx
131 DECODE_SIMULATE (0xfe000000, 0xfa00000
132
133 /* CPS 1111 0001 0000
134 /* SETEND 1111 0001 0000
135 /* SRS 1111 100x x1x0
136 /* RFE 1111 100x x0x1
137
138 /* Coprocessor instructions... */
139 /* MCRR2 1111 1100 0100
140 /* MRRC2 1111 1100 0101
141 /* LDC2 1111 110x xxx1
142 /* STC2 1111 110x xxx0
143 /* CDP2 1111 1110 xxxx
144 /* MCR2 1111 1110 xxx0
145 /* MRC2 1111 1110 xxx1
146
147 /* Other unallocated instructions...
148 DECODE_END
149 };
150
151 static const union decode_item arm_cccc_0001_0
152 /* Miscellaneous instructions
153
154 /* MRS cpsr cccc 0001 0000
155 DECODE_SIMULATEX(0x0ff000f0, 0x0100000
156
157
158 /* BX cccc 0001 0010
159 DECODE_SIMULATE (0x0ff000f0, 0x0120001
160
161 /* BLX (register) cccc 0001 0010
162 DECODE_SIMULATEX(0x0ff000f0, 0x0120003
163
164
165 /* CLZ cccc 0001 0110
166 DECODE_EMULATEX (0x0ff000f0, 0x0160001
167
168
169 /* QADD cccc 0001 0000
170 /* QSUB cccc 0001 0010
171 /* QDADD cccc 0001 0100
172 /* QDSUB cccc 0001 0110
173 DECODE_EMULATEX (0x0f9000f0, 0x0100005
174
175
176 /* BXJ cccc 0001 0010
177 /* MSR cccc 0001 0x10
178 /* MRS spsr cccc 0001 0100
179 /* BKPT 1110 0001 0010
180 /* SMC cccc 0001 0110
181 /* And unallocated instructions...
182 DECODE_END
183 };
184
185 static const union decode_item arm_cccc_0001_0
186 /* Halfword multiply and multiply-accu
187
188 /* SMLALxy cccc 0001 0100
189 DECODE_EMULATEX (0x0ff00090, 0x0140008
190
191
192 /* SMULWy cccc 0001 0010
193 DECODE_OR (0x0ff000b0, 0x012000a
194 /* SMULxy cccc 0001 0110
195 DECODE_EMULATEX (0x0ff00090, 0x0160008
196
197
198 /* SMLAxy cccc 0001 0000
199 DECODE_OR (0x0ff00090, 0x0100008
200 /* SMLAWy cccc 0001 0010
201 DECODE_EMULATEX (0x0ff000b0, 0x0120008
202
203
204 DECODE_END
205 };
206
207 static const union decode_item arm_cccc_0000__
208 /* Multiply and multiply-accumulate
209
210 /* MUL cccc 0000 0000
211 /* MULS cccc 0000 0001
212 DECODE_EMULATEX (0x0fe000f0, 0x0000009
213
214
215 /* MLA cccc 0000 0010
216 /* MLAS cccc 0000 0011
217 DECODE_OR (0x0fe000f0, 0x0020009
218 /* MLS cccc 0000 0110
219 DECODE_EMULATEX (0x0ff000f0, 0x0060009
220
221
222 /* UMAAL cccc 0000 0100
223 DECODE_OR (0x0ff000f0, 0x0040009
224 /* UMULL cccc 0000 1000
225 /* UMULLS cccc 0000 1001
226 /* UMLAL cccc 0000 1010
227 /* UMLALS cccc 0000 1011
228 /* SMULL cccc 0000 1100
229 /* SMULLS cccc 0000 1101
230 /* SMLAL cccc 0000 1110
231 /* SMLALS cccc 0000 1111
232 DECODE_EMULATEX (0x0f8000f0, 0x0080009
233
234
235 DECODE_END
236 };
237
238 static const union decode_item arm_cccc_0001__
239 /* Synchronization primitives
240
241 #if __LINUX_ARM_ARCH__ < 6
242 /* Deprecated on ARMv6 and may be UNDE
243 /* SMP/SWPB cccc 0001 0x00
244 DECODE_EMULATEX (0x0fb000f0, 0x0100009
245
246 #endif
247 /* LDREX/STREX{,D,B,H} cccc 0001 1xxx
248 /* And unallocated instructions...
249 DECODE_END
250 };
251
252 static const union decode_item arm_cccc_000x__
253 /* Extra load/store instructions
254
255 /* STRHT cccc 0000 xx10
256 /* ??? cccc 0000 xx10
257 /* LDRHT cccc 0000 xx11
258 /* LDRSBT cccc 0000 xx11
259 /* LDRSHT cccc 0000 xx11
260 DECODE_REJECT (0x0f200090, 0x0020009
261
262 /* LDRD/STRD lr,pc,{... cccc 000x x0x0
263 DECODE_REJECT (0x0e10e0d0, 0x0000e0d
264
265 /* LDRD (register) cccc 000x x0x0
266 /* STRD (register) cccc 000x x0x0
267 DECODE_EMULATEX (0x0e5000d0, 0x000000d
268
269
270 /* LDRD (immediate) cccc 000x x1x0
271 /* STRD (immediate) cccc 000x x1x0
272 DECODE_EMULATEX (0x0e5000d0, 0x004000d
273
274
275 /* STRH (register) cccc 000x x0x0
276 DECODE_EMULATEX (0x0e5000f0, 0x000000b
277
278
279 /* LDRH (register) cccc 000x x0x1
280 /* LDRSB (register) cccc 000x x0x1
281 /* LDRSH (register) cccc 000x x0x1
282 DECODE_EMULATEX (0x0e500090, 0x0010009
283
284
285 /* STRH (immediate) cccc 000x x1x0
286 DECODE_EMULATEX (0x0e5000f0, 0x004000b
287
288
289 /* LDRH (immediate) cccc 000x x1x1
290 /* LDRSB (immediate) cccc 000x x1x1
291 /* LDRSH (immediate) cccc 000x x1x1
292 DECODE_EMULATEX (0x0e500090, 0x0050009
293
294
295 DECODE_END
296 };
297
298 static const union decode_item arm_cccc_000x_t
299 /* Data-processing (register)
300
301 /* <op>S PC, ... cccc 000x xxx1
302 DECODE_REJECT (0x0e10f000, 0x0010f00
303
304 /* MOV IP, SP 1110 0001 1010
305 DECODE_SIMULATE (0xffffffff, 0xe1a0c00
306
307 /* TST (register) cccc 0001 0001
308 /* TEQ (register) cccc 0001 0011
309 /* CMP (register) cccc 0001 0101
310 /* CMN (register) cccc 0001 0111
311 DECODE_EMULATEX (0x0f900010, 0x0110000
312
313
314 /* MOV (register) cccc 0001 101x
315 /* MVN (register) cccc 0001 111x
316 DECODE_EMULATEX (0x0fa00010, 0x01a0000
317
318
319 /* AND (register) cccc 0000 000x
320 /* EOR (register) cccc 0000 001x
321 /* SUB (register) cccc 0000 010x
322 /* RSB (register) cccc 0000 011x
323 /* ADD (register) cccc 0000 100x
324 /* ADC (register) cccc 0000 101x
325 /* SBC (register) cccc 0000 110x
326 /* RSC (register) cccc 0000 111x
327 /* ORR (register) cccc 0001 100x
328 /* BIC (register) cccc 0001 110x
329 DECODE_EMULATEX (0x0e000010, 0x0000000
330
331
332 /* TST (reg-shift reg) cccc 0001 0001
333 /* TEQ (reg-shift reg) cccc 0001 0011
334 /* CMP (reg-shift reg) cccc 0001 0101
335 /* CMN (reg-shift reg) cccc 0001 0111
336 DECODE_EMULATEX (0x0f900090, 0x0110001
337
338
339 /* MOV (reg-shift reg) cccc 0001 101x
340 /* MVN (reg-shift reg) cccc 0001 111x
341 DECODE_EMULATEX (0x0fa00090, 0x01a0001
342
343
344 /* AND (reg-shift reg) cccc 0000 000x
345 /* EOR (reg-shift reg) cccc 0000 001x
346 /* SUB (reg-shift reg) cccc 0000 010x
347 /* RSB (reg-shift reg) cccc 0000 011x
348 /* ADD (reg-shift reg) cccc 0000 100x
349 /* ADC (reg-shift reg) cccc 0000 101x
350 /* SBC (reg-shift reg) cccc 0000 110x
351 /* RSC (reg-shift reg) cccc 0000 111x
352 /* ORR (reg-shift reg) cccc 0001 100x
353 /* BIC (reg-shift reg) cccc 0001 110x
354 DECODE_EMULATEX (0x0e000090, 0x0000001
355
356
357 DECODE_END
358 };
359
360 static const union decode_item arm_cccc_001x_t
361 /* Data-processing (immediate)
362
363 /* MOVW cccc 0011 0000
364 /* MOVT cccc 0011 0100
365 DECODE_EMULATEX (0x0fb00000, 0x0300000
366
367
368 /* YIELD cccc 0011 0010
369 DECODE_OR (0x0fff00ff, 0x0320000
370 /* SEV cccc 0011 0010
371 DECODE_EMULATE (0x0fff00ff, 0x0320000
372 /* NOP cccc 0011 0010
373 /* WFE cccc 0011 0010
374 /* WFI cccc 0011 0010
375 DECODE_SIMULATE (0x0fff00fc, 0x0320000
376 /* DBG cccc 0011 0010
377 /* unallocated hints cccc 0011 0010
378 /* MSR (immediate) cccc 0011 0x10
379 DECODE_REJECT (0x0fb00000, 0x0320000
380
381 /* <op>S PC, ... cccc 001x xxx1
382 DECODE_REJECT (0x0e10f000, 0x0210f00
383
384 /* TST (immediate) cccc 0011 0001
385 /* TEQ (immediate) cccc 0011 0011
386 /* CMP (immediate) cccc 0011 0101
387 /* CMN (immediate) cccc 0011 0111
388 DECODE_EMULATEX (0x0f900000, 0x0310000
389
390
391 /* MOV (immediate) cccc 0011 101x
392 /* MVN (immediate) cccc 0011 111x
393 DECODE_EMULATEX (0x0fa00000, 0x03a0000
394
395
396 /* AND (immediate) cccc 0010 000x
397 /* EOR (immediate) cccc 0010 001x
398 /* SUB (immediate) cccc 0010 010x
399 /* RSB (immediate) cccc 0010 011x
400 /* ADD (immediate) cccc 0010 100x
401 /* ADC (immediate) cccc 0010 101x
402 /* SBC (immediate) cccc 0010 110x
403 /* RSC (immediate) cccc 0010 111x
404 /* ORR (immediate) cccc 0011 100x
405 /* BIC (immediate) cccc 0011 110x
406 DECODE_EMULATEX (0x0e000000, 0x0200000
407
408
409 DECODE_END
410 };
411
412 static const union decode_item arm_cccc_0110__
413 /* Media instructions
414
415 /* SEL cccc 0110 1000
416 DECODE_EMULATEX (0x0ff000f0, 0x068000b
417
418
419 /* SSAT cccc 0110 101x
420 /* USAT cccc 0110 111x
421 DECODE_OR(0x0fa00030, 0x06a00010),
422 /* SSAT16 cccc 0110 1010
423 /* USAT16 cccc 0110 1110
424 DECODE_EMULATEX (0x0fb000f0, 0x06a0003
425
426
427 /* REV cccc 0110 1011
428 /* REV16 cccc 0110 1011
429 /* RBIT cccc 0110 1111
430 /* REVSH cccc 0110 1111
431 DECODE_EMULATEX (0x0fb00070, 0x06b0003
432
433
434 /* ??? cccc 0110 0x00
435 DECODE_REJECT (0x0fb00010, 0x0600001
436 /* ??? cccc 0110 0xxx
437 DECODE_REJECT (0x0f8000f0, 0x060000b
438 /* ??? cccc 0110 0xxx
439 DECODE_REJECT (0x0f8000f0, 0x060000d
440 /* SADD16 cccc 0110 0001
441 /* SADDSUBX cccc 0110 0001
442 /* SSUBADDX cccc 0110 0001
443 /* SSUB16 cccc 0110 0001
444 /* SADD8 cccc 0110 0001
445 /* SSUB8 cccc 0110 0001
446 /* QADD16 cccc 0110 0010
447 /* QADDSUBX cccc 0110 0010
448 /* QSUBADDX cccc 0110 0010
449 /* QSUB16 cccc 0110 0010
450 /* QADD8 cccc 0110 0010
451 /* QSUB8 cccc 0110 0010
452 /* SHADD16 cccc 0110 0011
453 /* SHADDSUBX cccc 0110 0011
454 /* SHSUBADDX cccc 0110 0011
455 /* SHSUB16 cccc 0110 0011
456 /* SHADD8 cccc 0110 0011
457 /* SHSUB8 cccc 0110 0011
458 /* UADD16 cccc 0110 0101
459 /* UADDSUBX cccc 0110 0101
460 /* USUBADDX cccc 0110 0101
461 /* USUB16 cccc 0110 0101
462 /* UADD8 cccc 0110 0101
463 /* USUB8 cccc 0110 0101
464 /* UQADD16 cccc 0110 0110
465 /* UQADDSUBX cccc 0110 0110
466 /* UQSUBADDX cccc 0110 0110
467 /* UQSUB16 cccc 0110 0110
468 /* UQADD8 cccc 0110 0110
469 /* UQSUB8 cccc 0110 0110
470 /* UHADD16 cccc 0110 0111
471 /* UHADDSUBX cccc 0110 0111
472 /* UHSUBADDX cccc 0110 0111
473 /* UHSUB16 cccc 0110 0111
474 /* UHADD8 cccc 0110 0111
475 /* UHSUB8 cccc 0110 0111
476 DECODE_EMULATEX (0x0f800010, 0x0600001
477
478
479 /* PKHBT cccc 0110 1000
480 /* PKHTB cccc 0110 1000
481 DECODE_EMULATEX (0x0ff00030, 0x0680001
482
483
484 /* ??? cccc 0110 1001
485 /* ??? cccc 0110 1101
486 DECODE_REJECT (0x0fb000f0, 0x0690007
487
488 /* SXTB16 cccc 0110 1000
489 /* SXTB cccc 0110 1010
490 /* SXTH cccc 0110 1011
491 /* UXTB16 cccc 0110 1100
492 /* UXTB cccc 0110 1110
493 /* UXTH cccc 0110 1111
494 DECODE_EMULATEX (0x0f8f00f0, 0x068f007
495
496
497 /* SXTAB16 cccc 0110 1000
498 /* SXTAB cccc 0110 1010
499 /* SXTAH cccc 0110 1011
500 /* UXTAB16 cccc 0110 1100
501 /* UXTAB cccc 0110 1110
502 /* UXTAH cccc 0110 1111
503 DECODE_EMULATEX (0x0f8000f0, 0x0680007
504
505
506 DECODE_END
507 };
508
509 static const union decode_item arm_cccc_0111__
510 /* Media instructions
511
512 /* UNDEFINED cccc 0111 1111
513 DECODE_REJECT (0x0ff000f0, 0x07f000f
514
515 /* SMLALD cccc 0111 0100
516 /* SMLSLD cccc 0111 0100
517 DECODE_EMULATEX (0x0ff00090, 0x0740001
518
519
520 /* SMUAD cccc 0111 0000
521 /* SMUSD cccc 0111 0000
522 DECODE_OR (0x0ff0f090, 0x0700f01
523 /* SMMUL cccc 0111 0101
524 DECODE_OR (0x0ff0f0d0, 0x0750f01
525 /* USAD8 cccc 0111 1000
526 DECODE_EMULATEX (0x0ff0f0f0, 0x0780f01
527
528
529 /* SMLAD cccc 0111 0000
530 /* SMLSD cccc 0111 0000
531 DECODE_OR (0x0ff00090, 0x0700001
532 /* SMMLA cccc 0111 0101
533 DECODE_OR (0x0ff000d0, 0x0750001
534 /* USADA8 cccc 0111 1000
535 DECODE_EMULATEX (0x0ff000f0, 0x0780001
536
537
538 /* SMMLS cccc 0111 0101
539 DECODE_EMULATEX (0x0ff000d0, 0x075000d
540
541
542 /* SBFX cccc 0111 101x
543 /* UBFX cccc 0111 111x
544 DECODE_EMULATEX (0x0fa00070, 0x07a0005
545
546
547 /* BFC cccc 0111 110x
548 DECODE_EMULATEX (0x0fe0007f, 0x07c0001
549
550
551 /* BFI cccc 0111 110x
552 DECODE_EMULATEX (0x0fe00070, 0x07c0001
553
554
555 DECODE_END
556 };
557
558 static const union decode_item arm_cccc_01xx_t
559 /* Load/store word and unsigned byte
560
561 /* LDRB/STRB pc,[...] cccc 01xx x0xx
562 DECODE_REJECT (0x0c40f000, 0x0440f00
563
564 /* STRT cccc 01x0 x010
565 /* LDRT cccc 01x0 x011
566 /* STRBT cccc 01x0 x110
567 /* LDRBT cccc 01x0 x111
568 DECODE_REJECT (0x0d200000, 0x0420000
569
570 /* STR (immediate) cccc 010x x0x0
571 /* STRB (immediate) cccc 010x x1x0
572 DECODE_EMULATEX (0x0e100000, 0x0400000
573
574
575 /* LDR (immediate) cccc 010x x0x1
576 /* LDRB (immediate) cccc 010x x1x1
577 DECODE_EMULATEX (0x0e100000, 0x0410000
578
579
580 /* STR (register) cccc 011x x0x0
581 /* STRB (register) cccc 011x x1x0
582 DECODE_EMULATEX (0x0e100000, 0x0600000
583
584
585 /* LDR (register) cccc 011x x0x1
586 /* LDRB (register) cccc 011x x1x1
587 DECODE_EMULATEX (0x0e100000, 0x0610000
588
589
590 DECODE_END
591 };
592
593 static const union decode_item arm_cccc_100x_t
594 /* Block data transfer instructions
595
596 /* LDM cccc 100x x0x1
597 /* STM cccc 100x x0x0
598 DECODE_CUSTOM (0x0e400000, 0x0800000
599
600 /* STM (user registers) cccc 100x x1x0
601 /* LDM (user registers) cccc 100x x1x1
602 /* LDM (exception ret) cccc 100x x1x1
603 DECODE_END
604 };
605
606 const union decode_item probes_decode_arm_tabl
607 /*
608 * Unconditional instructions
609 * 1111 xxxx xxxx
610 */
611 DECODE_TABLE (0xf0000000, 0xf000000
612
613 /*
614 * Miscellaneous instructions
615 * cccc 0001 0xx0
616 */
617 DECODE_TABLE (0x0f900080, 0x0100000
618
619 /*
620 * Halfword multiply and multiply-accu
621 * cccc 0001 0xx0
622 */
623 DECODE_TABLE (0x0f900090, 0x0100008
624
625 /*
626 * Multiply and multiply-accumulate
627 * cccc 0000 xxxx
628 */
629 DECODE_TABLE (0x0f0000f0, 0x0000009
630
631 /*
632 * Synchronization primitives
633 * cccc 0001 xxxx
634 */
635 DECODE_TABLE (0x0f0000f0, 0x0100009
636
637 /*
638 * Extra load/store instructions
639 * cccc 000x xxxx
640 */
641 DECODE_TABLE (0x0e000090, 0x0000009
642
643 /*
644 * Data-processing (register)
645 * cccc 000x xxxx
646 * Data-processing (register-shifted r
647 * cccc 000x xxxx
648 */
649 DECODE_TABLE (0x0e000000, 0x0000000
650
651 /*
652 * Data-processing (immediate)
653 * cccc 001x xxxx
654 */
655 DECODE_TABLE (0x0e000000, 0x0200000
656
657 /*
658 * Media instructions
659 * cccc 011x xxxx
660 */
661 DECODE_TABLE (0x0f000010, 0x0600001
662 DECODE_TABLE (0x0f000010, 0x0700001
663
664 /*
665 * Load/store word and unsigned byte
666 * cccc 01xx xxxx
667 */
668 DECODE_TABLE (0x0c000000, 0x0400000
669
670 /*
671 * Block data transfer instructions
672 * cccc 100x xxxx
673 */
674 DECODE_TABLE (0x0e000000, 0x0800000
675
676 /* B cccc 1010 xxxx
677 /* BL cccc 1011 xxxx
678 DECODE_SIMULATE (0x0e000000, 0x0a00000
679
680 /*
681 * Supervisor Call, and coprocessor in
682 */
683
684 /* MCRR cccc 1100 0100
685 /* MRRC cccc 1100 0101
686 /* LDC cccc 110x xxx1
687 /* STC cccc 110x xxx0
688 /* CDP cccc 1110 xxxx
689 /* MCR cccc 1110 xxx0
690 /* MRC cccc 1110 xxx1
691 /* SVC cccc 1111 xxxx
692 DECODE_REJECT (0x0c000000, 0x0c00000
693
694 DECODE_END
695 };
696 #ifdef CONFIG_ARM_KPROBES_TEST_MODULE
697 EXPORT_SYMBOL_GPL(probes_decode_arm_table);
698 #endif
699
700 static void __kprobes arm_singlestep(probes_op
701 struct arch_probes_insn *asi,
702 {
703 regs->ARM_pc += 4;
704 asi->insn_handler(insn, asi, regs);
705 }
706
707 /* Return:
708 * INSN_REJECTED If instruction is one n
709 * INSN_GOOD If instruction is suppo
710 * INSN_GOOD_NO_SLOT If instruction is suppo
711 *
712 * For instructions we don't want to kprobe (I
713 * These are generally ones that modify the
714 * them "hard" to simulate such as switches
715 * make accesses in alternate modes. Any of
716 * if the work was put into it, but low retu
717 * should also be very rare.
718 */
719 enum probes_insn __kprobes
720 arm_probes_decode_insn(probes_opcode_t insn, s
721 bool emulate, const uni
722 const struct decode_che
723 {
724 asi->insn_singlestep = arm_singlestep;
725 asi->insn_check_cc = probes_condition_
726 return probes_decode_insn(insn, asi, p
727 emulate, act
728 }
729
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