1 # SPDX-License-Identifier: GPL-2.0-only !! 1 config MIPS
2 config ARM64 <<
3 def_bool y <<
4 select ACPI_APMT if ACPI <<
5 select ACPI_CCA_REQUIRED if ACPI <<
6 select ACPI_GENERIC_GSI if ACPI <<
7 select ACPI_GTDT if ACPI <<
8 select ACPI_HOTPLUG_CPU if ACPI_PROCES <<
9 select ACPI_IORT if ACPI <<
10 select ACPI_REDUCED_HARDWARE_ONLY if A <<
11 select ACPI_MCFG if (ACPI && PCI) <<
12 select ACPI_SPCR_TABLE if ACPI <<
13 select ACPI_PPTT if ACPI <<
14 select ARCH_HAS_DEBUG_WX <<
15 select ARCH_BINFMT_ELF_EXTRA_PHDRS <<
16 select ARCH_BINFMT_ELF_STATE <<
17 select ARCH_CORRECT_STACKTRACE_ON_KRET <<
18 select ARCH_ENABLE_HUGEPAGE_MIGRATION <<
19 select ARCH_ENABLE_MEMORY_HOTPLUG <<
20 select ARCH_ENABLE_MEMORY_HOTREMOVE <<
21 select ARCH_ENABLE_SPLIT_PMD_PTLOCK if <<
22 select ARCH_ENABLE_THP_MIGRATION if TR <<
23 select ARCH_HAS_CACHE_LINE_SIZE <<
24 select ARCH_HAS_CURRENT_STACK_POINTER <<
25 select ARCH_HAS_DEBUG_VIRTUAL <<
26 select ARCH_HAS_DEBUG_VM_PGTABLE <<
27 select ARCH_HAS_DMA_OPS if XEN <<
28 select ARCH_HAS_DMA_PREP_COHERENT <<
29 select ARCH_HAS_ACPI_TABLE_UPGRADE if <<
30 select ARCH_HAS_FAST_MULTIPLIER <<
31 select ARCH_HAS_FORTIFY_SOURCE <<
32 select ARCH_HAS_GCOV_PROFILE_ALL <<
33 select ARCH_HAS_GIGANTIC_PAGE <<
34 select ARCH_HAS_KCOV <<
35 select ARCH_HAS_KERNEL_FPU_SUPPORT if <<
36 select ARCH_HAS_KEEPINITRD <<
37 select ARCH_HAS_MEMBARRIER_SYNC_CORE <<
38 select ARCH_HAS_MEM_ENCRYPT <<
39 select ARCH_HAS_NMI_SAFE_THIS_CPU_OPS <<
40 select ARCH_HAS_NON_OVERLAPPING_ADDRES <<
41 select ARCH_HAS_PTE_DEVMAP <<
42 select ARCH_HAS_PTE_SPECIAL <<
43 select ARCH_HAS_HW_PTE_YOUNG <<
44 select ARCH_HAS_SETUP_DMA_OPS <<
45 select ARCH_HAS_SET_DIRECT_MAP <<
46 select ARCH_HAS_SET_MEMORY <<
47 select ARCH_STACKWALK <<
48 select ARCH_HAS_STRICT_KERNEL_RWX <<
49 select ARCH_HAS_STRICT_MODULE_RWX <<
50 select ARCH_HAS_SYNC_DMA_FOR_DEVICE <<
51 select ARCH_HAS_SYNC_DMA_FOR_CPU <<
52 select ARCH_HAS_SYSCALL_WRAPPER <<
53 select ARCH_HAS_TICK_BROADCAST if GENE <<
54 select ARCH_HAS_ZONE_DMA_SET if EXPERT <<
55 select ARCH_HAVE_ELF_PROT <<
56 select ARCH_HAVE_NMI_SAFE_CMPXCHG <<
57 select ARCH_HAVE_TRACE_MMIO_ACCESS <<
58 select ARCH_INLINE_READ_LOCK if !PREEM <<
59 select ARCH_INLINE_READ_LOCK_BH if !PR <<
60 select ARCH_INLINE_READ_LOCK_IRQ if !P <<
61 select ARCH_INLINE_READ_LOCK_IRQSAVE i <<
62 select ARCH_INLINE_READ_UNLOCK if !PRE <<
63 select ARCH_INLINE_READ_UNLOCK_BH if ! <<
64 select ARCH_INLINE_READ_UNLOCK_IRQ if <<
65 select ARCH_INLINE_READ_UNLOCK_IRQREST <<
66 select ARCH_INLINE_WRITE_LOCK if !PREE <<
67 select ARCH_INLINE_WRITE_LOCK_BH if !P <<
68 select ARCH_INLINE_WRITE_LOCK_IRQ if ! <<
69 select ARCH_INLINE_WRITE_LOCK_IRQSAVE <<
70 select ARCH_INLINE_WRITE_UNLOCK if !PR <<
71 select ARCH_INLINE_WRITE_UNLOCK_BH if <<
72 select ARCH_INLINE_WRITE_UNLOCK_IRQ if <<
73 select ARCH_INLINE_WRITE_UNLOCK_IRQRES <<
74 select ARCH_INLINE_SPIN_TRYLOCK if !PR <<
75 select ARCH_INLINE_SPIN_TRYLOCK_BH if <<
76 select ARCH_INLINE_SPIN_LOCK if !PREEM <<
77 select ARCH_INLINE_SPIN_LOCK_BH if !PR <<
78 select ARCH_INLINE_SPIN_LOCK_IRQ if !P <<
79 select ARCH_INLINE_SPIN_LOCK_IRQSAVE i <<
80 select ARCH_INLINE_SPIN_UNLOCK if !PRE <<
81 select ARCH_INLINE_SPIN_UNLOCK_BH if ! <<
82 select ARCH_INLINE_SPIN_UNLOCK_IRQ if <<
83 select ARCH_INLINE_SPIN_UNLOCK_IRQREST <<
84 select ARCH_KEEP_MEMBLOCK <<
85 select ARCH_MHP_MEMMAP_ON_MEMORY_ENABL <<
86 select ARCH_USE_CMPXCHG_LOCKREF <<
87 select ARCH_USE_GNU_PROPERTY <<
88 select ARCH_USE_MEMTEST <<
89 select ARCH_USE_QUEUED_RWLOCKS <<
90 select ARCH_USE_QUEUED_SPINLOCKS <<
91 select ARCH_USE_SYM_ANNOTATIONS <<
92 select ARCH_SUPPORTS_DEBUG_PAGEALLOC <<
93 select ARCH_SUPPORTS_HUGETLBFS <<
94 select ARCH_SUPPORTS_MEMORY_FAILURE <<
95 select ARCH_SUPPORTS_SHADOW_CALL_STACK <<
96 select ARCH_SUPPORTS_LTO_CLANG if CPU_ <<
97 select ARCH_SUPPORTS_LTO_CLANG_THIN <<
98 select ARCH_SUPPORTS_CFI_CLANG <<
99 select ARCH_SUPPORTS_ATOMIC_RMW <<
100 select ARCH_SUPPORTS_INT128 if CC_HAS_ <<
101 select ARCH_SUPPORTS_NUMA_BALANCING <<
102 select ARCH_SUPPORTS_PAGE_TABLE_CHECK <<
103 select ARCH_SUPPORTS_PER_VMA_LOCK <<
104 select ARCH_SUPPORTS_HUGE_PFNMAP if TR <<
105 select ARCH_SUPPORTS_RT <<
106 select ARCH_WANT_BATCHED_UNMAP_TLB_FLU <<
107 select ARCH_WANT_COMPAT_IPC_PARSE_VERS <<
108 select ARCH_WANT_DEFAULT_BPF_JIT <<
109 select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_ <<
110 select ARCH_WANT_FRAME_POINTERS <<
111 select ARCH_WANT_HUGE_PMD_SHARE if ARM <<
112 select ARCH_WANT_LD_ORPHAN_WARN <<
113 select ARCH_WANTS_EXECMEM_LATE if EXEC <<
114 select ARCH_WANTS_NO_INSTR <<
115 select ARCH_WANTS_THP_SWAP if ARM64_4K <<
116 select ARCH_HAS_UBSAN <<
117 select ARM_AMBA <<
118 select ARM_ARCH_TIMER <<
119 select ARM_GIC <<
120 select AUDIT_ARCH_COMPAT_GENERIC <<
121 select ARM_GIC_V2M if PCI <<
122 select ARM_GIC_V3 <<
123 select ARM_GIC_V3_ITS if PCI <<
124 select ARM_PSCI_FW <<
125 select BUILDTIME_TABLE_SORT <<
126 select CLONE_BACKWARDS <<
127 select COMMON_CLK <<
128 select CPU_PM if (SUSPEND || CPU_IDLE) <<
129 select CPUMASK_OFFSTACK if NR_CPUS > 2 <<
130 select CRC32 <<
131 select DCACHE_WORD_ACCESS <<
132 select DYNAMIC_FTRACE if FUNCTION_TRAC <<
133 select DMA_BOUNCE_UNALIGNED_KMALLOC <<
134 select DMA_DIRECT_REMAP <<
135 select EDAC_SUPPORT <<
136 select FRAME_POINTER <<
137 select FUNCTION_ALIGNMENT_4B <<
138 select FUNCTION_ALIGNMENT_8B if DYNAMI <<
139 select GENERIC_ALLOCATOR <<
140 select GENERIC_ARCH_TOPOLOGY <<
141 select GENERIC_CLOCKEVENTS_BROADCAST <<
142 select GENERIC_CPU_AUTOPROBE <<
143 select GENERIC_CPU_DEVICES <<
144 select GENERIC_CPU_VULNERABILITIES <<
145 select GENERIC_EARLY_IOREMAP <<
146 select GENERIC_IDLE_POLL_SETUP <<
147 select GENERIC_IOREMAP <<
148 select GENERIC_IRQ_IPI <<
149 select GENERIC_IRQ_PROBE <<
150 select GENERIC_IRQ_SHOW <<
151 select GENERIC_IRQ_SHOW_LEVEL <<
152 select GENERIC_LIB_DEVMEM_IS_ALLOWED <<
153 select GENERIC_PCI_IOMAP <<
154 select GENERIC_PTDUMP <<
155 select GENERIC_SCHED_CLOCK <<
156 select GENERIC_SMP_IDLE_THREAD <<
157 select GENERIC_TIME_VSYSCALL <<
158 select GENERIC_GETTIMEOFDAY <<
159 select GENERIC_VDSO_TIME_NS <<
160 select HARDIRQS_SW_RESEND <<
161 select HAS_IOPORT <<
162 select HAVE_MOVE_PMD <<
163 select HAVE_MOVE_PUD <<
164 select HAVE_PCI <<
165 select HAVE_ACPI_APEI if (ACPI && EFI) <<
166 select HAVE_ALIGNED_STRUCT_PAGE <<
167 select HAVE_ARCH_AUDITSYSCALL <<
168 select HAVE_ARCH_BITREVERSE <<
169 select HAVE_ARCH_COMPILER_H <<
170 select HAVE_ARCH_HUGE_VMALLOC <<
171 select HAVE_ARCH_HUGE_VMAP <<
172 select HAVE_ARCH_JUMP_LABEL <<
173 select HAVE_ARCH_JUMP_LABEL_RELATIVE <<
174 select HAVE_ARCH_KASAN <<
175 select HAVE_ARCH_KASAN_VMALLOC <<
176 select HAVE_ARCH_KASAN_SW_TAGS <<
177 select HAVE_ARCH_KASAN_HW_TAGS if ARM6 <<
178 # Some instrumentation may be unsound, <<
179 select HAVE_ARCH_KCSAN if EXPERT <<
180 select HAVE_ARCH_KFENCE <<
181 select HAVE_ARCH_KGDB <<
182 select HAVE_ARCH_MMAP_RND_BITS <<
183 select HAVE_ARCH_MMAP_RND_COMPAT_BITS <<
184 select HAVE_ARCH_PREL32_RELOCATIONS <<
185 select HAVE_ARCH_RANDOMIZE_KSTACK_OFFS <<
186 select HAVE_ARCH_SECCOMP_FILTER <<
187 select HAVE_ARCH_STACKLEAK <<
188 select HAVE_ARCH_THREAD_STRUCT_WHITELI <<
189 select HAVE_ARCH_TRACEHOOK <<
190 select HAVE_ARCH_TRANSPARENT_HUGEPAGE <<
191 select HAVE_ARCH_VMAP_STACK <<
192 select HAVE_ARM_SMCCC <<
193 select HAVE_ASM_MODVERSIONS <<
194 select HAVE_EBPF_JIT <<
195 select HAVE_C_RECORDMCOUNT <<
196 select HAVE_CMPXCHG_DOUBLE <<
197 select HAVE_CMPXCHG_LOCAL <<
198 select HAVE_CONTEXT_TRACKING_USER <<
199 select HAVE_DEBUG_KMEMLEAK <<
200 select HAVE_DMA_CONTIGUOUS <<
201 select HAVE_DYNAMIC_FTRACE <<
202 select HAVE_DYNAMIC_FTRACE_WITH_ARGS \ <<
203 if (GCC_SUPPORTS_DYNAMIC_FTRAC <<
204 CLANG_SUPPORTS_DYNAMIC_FTR <<
205 select HAVE_DYNAMIC_FTRACE_WITH_DIRECT <<
206 if DYNAMIC_FTRACE_WITH_ARGS && <<
207 select HAVE_DYNAMIC_FTRACE_WITH_CALL_O <<
208 if (DYNAMIC_FTRACE_WITH_ARGS & <<
209 (CC_IS_CLANG || !CC_OPTIMI <<
210 select FTRACE_MCOUNT_USE_PATCHABLE_FUN <<
211 if DYNAMIC_FTRACE_WITH_ARGS <<
212 select HAVE_SAMPLE_FTRACE_DIRECT <<
213 select HAVE_SAMPLE_FTRACE_DIRECT_MULTI <<
214 select HAVE_EFFICIENT_UNALIGNED_ACCESS <<
215 select HAVE_GUP_FAST <<
216 select HAVE_FTRACE_MCOUNT_RECORD <<
217 select HAVE_FUNCTION_TRACER <<
218 select HAVE_FUNCTION_ERROR_INJECTION <<
219 select HAVE_FUNCTION_GRAPH_TRACER <<
220 select HAVE_FUNCTION_GRAPH_RETVAL <<
221 select HAVE_GCC_PLUGINS <<
222 select HAVE_HARDLOCKUP_DETECTOR_PERF i <<
223 HW_PERF_EVENTS && HAVE_PERF_EV <<
224 select HAVE_HW_BREAKPOINT if PERF_EVEN <<
225 select HAVE_IOREMAP_PROT <<
226 select HAVE_IRQ_TIME_ACCOUNTING <<
227 select HAVE_MOD_ARCH_SPECIFIC <<
228 select HAVE_NMI <<
229 select HAVE_PERF_EVENTS <<
230 select HAVE_PERF_EVENTS_NMI if ARM64_P <<
231 select HAVE_PERF_REGS <<
232 select HAVE_PERF_USER_STACK_DUMP <<
233 select HAVE_PREEMPT_DYNAMIC_KEY <<
234 select HAVE_REGS_AND_STACK_ACCESS_API <<
235 select HAVE_POSIX_CPU_TIMERS_TASK_WORK <<
236 select HAVE_FUNCTION_ARG_ACCESS_API <<
237 select MMU_GATHER_RCU_TABLE_FREE <<
238 select HAVE_RSEQ <<
239 select HAVE_RUST if RUSTC_SUPPORTS_ARM <<
240 select HAVE_STACKPROTECTOR <<
241 select HAVE_SYSCALL_TRACEPOINTS <<
242 select HAVE_KPROBES <<
243 select HAVE_KRETPROBES <<
244 select HAVE_GENERIC_VDSO <<
245 select HOTPLUG_CORE_SYNC_DEAD if HOTPL <<
246 select IRQ_DOMAIN <<
247 select IRQ_FORCED_THREADING <<
248 select KASAN_VMALLOC if KASAN <<
249 select LOCK_MM_AND_FIND_VMA <<
250 select MODULES_USE_ELF_RELA <<
251 select NEED_DMA_MAP_STATE <<
252 select NEED_SG_DMA_LENGTH <<
253 select OF <<
254 select OF_EARLY_FLATTREE <<
255 select PCI_DOMAINS_GENERIC if PCI <<
256 select PCI_ECAM if (ACPI && PCI) <<
257 select PCI_SYSCALL if PCI <<
258 select POWER_RESET <<
259 select POWER_SUPPLY <<
260 select SPARSE_IRQ <<
261 select SWIOTLB <<
262 select SYSCTL_EXCEPTION_TRACE <<
263 select THREAD_INFO_IN_TASK <<
264 select HAVE_ARCH_USERFAULTFD_MINOR if <<
265 select HAVE_ARCH_USERFAULTFD_WP if USE <<
266 select TRACE_IRQFLAGS_SUPPORT <<
267 select TRACE_IRQFLAGS_NMI_SUPPORT <<
268 select HAVE_SOFTIRQ_ON_OWN_STACK <<
269 select USER_STACKTRACE_SUPPORT <<
270 select VDSO_GETRANDOM <<
271 help <<
272 ARM 64-bit (AArch64) Linux support. <<
273 <<
274 config RUSTC_SUPPORTS_ARM64 <<
275 def_bool y <<
276 depends on CPU_LITTLE_ENDIAN <<
277 # Shadow call stack is only supported <<
278 # <<
279 # When using the UNWIND_PATCH_PAC_INTO <<
280 # required due to use of the -Zfixed-x <<
281 # <<
282 # Otherwise, rustc version 1.82+ is re <<
283 # -Zsanitizer=shadow-call-stack flag. <<
284 depends on !SHADOW_CALL_STACK || RUSTC <<
285 <<
286 config CLANG_SUPPORTS_DYNAMIC_FTRACE_WITH_ARGS <<
287 def_bool CC_IS_CLANG <<
288 # https://github.com/ClangBuiltLinux/l <<
289 depends on AS_IS_GNU || (AS_IS_LLVM && <<
290 <<
291 config GCC_SUPPORTS_DYNAMIC_FTRACE_WITH_ARGS <<
292 def_bool CC_IS_GCC <<
293 depends on $(cc-option,-fpatchable-fun <<
294 <<
295 config 64BIT <<
296 def_bool y <<
297 <<
298 config MMU <<
299 def_bool y <<
300 <<
301 config ARM64_CONT_PTE_SHIFT <<
302 int <<
303 default 5 if PAGE_SIZE_64KB <<
304 default 7 if PAGE_SIZE_16KB <<
305 default 4 <<
306 <<
307 config ARM64_CONT_PMD_SHIFT <<
308 int <<
309 default 5 if PAGE_SIZE_64KB <<
310 default 5 if PAGE_SIZE_16KB <<
311 default 4 <<
312 <<
313 config ARCH_MMAP_RND_BITS_MIN <<
314 default 14 if PAGE_SIZE_64KB <<
315 default 16 if PAGE_SIZE_16KB <<
316 default 18 <<
317 <<
318 # max bits determined by the following formula <<
319 # VA_BITS - PAGE_SHIFT - 3 <<
320 config ARCH_MMAP_RND_BITS_MAX <<
321 default 19 if ARM64_VA_BITS=36 <<
322 default 24 if ARM64_VA_BITS=39 <<
323 default 27 if ARM64_VA_BITS=42 <<
324 default 30 if ARM64_VA_BITS=47 <<
325 default 29 if ARM64_VA_BITS=48 && ARM6 <<
326 default 31 if ARM64_VA_BITS=48 && ARM6 <<
327 default 33 if ARM64_VA_BITS=48 <<
328 default 14 if ARM64_64K_PAGES <<
329 default 16 if ARM64_16K_PAGES <<
330 default 18 <<
331 <<
332 config ARCH_MMAP_RND_COMPAT_BITS_MIN <<
333 default 7 if ARM64_64K_PAGES <<
334 default 9 if ARM64_16K_PAGES <<
335 default 11 <<
336 <<
337 config ARCH_MMAP_RND_COMPAT_BITS_MAX <<
338 default 16 <<
339 <<
340 config NO_IOPORT_MAP <<
341 def_bool y if !PCI <<
342 <<
343 config STACKTRACE_SUPPORT <<
344 def_bool y <<
345 <<
346 config ILLEGAL_POINTER_VALUE <<
347 hex <<
348 default 0xdead000000000000 <<
349 <<
350 config LOCKDEP_SUPPORT <<
351 def_bool y <<
352 <<
353 config GENERIC_BUG <<
354 def_bool y <<
355 depends on BUG <<
356 <<
357 config GENERIC_BUG_RELATIVE_POINTERS <<
358 def_bool y <<
359 depends on GENERIC_BUG <<
360 <<
361 config GENERIC_HWEIGHT <<
362 def_bool y <<
363 <<
364 config GENERIC_CSUM <<
365 def_bool y <<
366 <<
367 config GENERIC_CALIBRATE_DELAY <<
368 def_bool y <<
369 <<
370 config SMP <<
371 def_bool y <<
372 <<
373 config KERNEL_MODE_NEON <<
374 def_bool y <<
375 <<
376 config FIX_EARLYCON_MEM <<
377 def_bool y <<
378 <<
379 config PGTABLE_LEVELS <<
380 int <<
381 default 2 if ARM64_16K_PAGES && ARM64_ <<
382 default 2 if ARM64_64K_PAGES && ARM64_ <<
383 default 3 if ARM64_64K_PAGES && (ARM64 <<
384 default 3 if ARM64_4K_PAGES && ARM64_V <<
385 default 3 if ARM64_16K_PAGES && ARM64_ <<
386 default 4 if ARM64_16K_PAGES && (ARM64 <<
387 default 4 if !ARM64_64K_PAGES && ARM64 <<
388 default 5 if ARM64_4K_PAGES && ARM64_V <<
389 <<
390 config ARCH_SUPPORTS_UPROBES <<
391 def_bool y <<
392 <<
393 config ARCH_PROC_KCORE_TEXT <<
394 def_bool y <<
395 <<
396 config BROKEN_GAS_INST <<
397 def_bool !$(as-instr,1:\n.inst 0\n.rep <<
398 <<
399 config BUILTIN_RETURN_ADDRESS_STRIPS_PAC <<
400 bool <<
401 # Clang's __builtin_return_address() s <<
402 # https://github.com/llvm/llvm-project <<
403 default y if CC_IS_CLANG <<
404 # GCC's __builtin_return_address() str <<
405 # and this was backported to 10.2.0, 9 <<
406 # https://gcc.gnu.org/bugzilla/show_bu <<
407 default y if CC_IS_GCC && (GCC_VERSION <<
408 default y if CC_IS_GCC && (GCC_VERSION <<
409 default y if CC_IS_GCC && (GCC_VERSION <<
410 default y if CC_IS_GCC && (GCC_VERSION <<
411 default n <<
412 <<
413 config KASAN_SHADOW_OFFSET <<
414 hex <<
415 depends on KASAN_GENERIC || KASAN_SW_T <<
416 default 0xdfff800000000000 if (ARM64_V <<
417 default 0xdfffc00000000000 if (ARM64_V <<
418 default 0xdffffe0000000000 if ARM64_VA <<
419 default 0xdfffffc000000000 if ARM64_VA <<
420 default 0xdffffff800000000 if ARM64_VA <<
421 default 0xefff800000000000 if (ARM64_V <<
422 default 0xefffc00000000000 if (ARM64_V <<
423 default 0xeffffe0000000000 if ARM64_VA <<
424 default 0xefffffc000000000 if ARM64_VA <<
425 default 0xeffffff800000000 if ARM64_VA <<
426 default 0xffffffffffffffff <<
427 <<
428 config UNWIND_TABLES <<
429 bool <<
430 <<
431 source "arch/arm64/Kconfig.platforms" <<
432 <<
433 menu "Kernel Features" <<
434 <<
435 menu "ARM errata workarounds via the alternati <<
436 <<
437 config AMPERE_ERRATUM_AC03_CPU_38 <<
438 bool "AmpereOne: AC03_CPU_38: Certain <<
439 default y <<
440 help <<
441 This option adds an alternative code <<
442 errata AC03_CPU_38 and AC04_CPU_10 o <<
443 <<
444 The affected design reports FEAT_HAF <<
445 ID_AA64MMFR1_EL1.HAFDBS, but (V)TCR_ <<
446 as required by the architecture. The <<
447 implementation suffers from an addit <<
448 A/D updates can occur after a PTE ha <<
449 <<
450 The workaround forces KVM to explici <<
451 which avoids enabling unadvertised h <<
452 at stage-2. <<
453 <<
454 If unsure, say Y. <<
455 <<
456 config ARM64_WORKAROUND_CLEAN_CACHE <<
457 bool 2 bool
458 <<
459 config ARM64_ERRATUM_826319 <<
460 bool "Cortex-A53: 826319: System might <<
461 default y 3 default y
462 select ARM64_WORKAROUND_CLEAN_CACHE <<
463 help <<
464 This option adds an alternative code <<
465 erratum 826319 on Cortex-A53 parts u <<
466 AXI master interface and an L2 cache <<
467 4
468 If a Cortex-A53 uses an AMBA AXI4 AC !! 5 config MIPS64
469 and is unable to accept a certain wr !! 6 bool "64-bit kernel"
470 not progress on read data presented <<
471 system can deadlock. <<
472 <<
473 The workaround promotes data cache c <<
474 data cache clean-and-invalidate. <<
475 Please note that this does not neces <<
476 as it depends on the alternative fra <<
477 the kernel if an affected CPU is det <<
478 <<
479 If unsure, say Y. <<
480 <<
481 config ARM64_ERRATUM_827319 <<
482 bool "Cortex-A53: 827319: Data cache c <<
483 default y <<
484 select ARM64_WORKAROUND_CLEAN_CACHE <<
485 help 7 help
486 This option adds an alternative code !! 8 Select this option if you want to build a 64-bit kernel. You should
487 erratum 827319 on Cortex-A53 parts u !! 9 only select this option if you have hardware that actually has a
488 master interface and an L2 cache. !! 10 32-bit processor and if your application will actually benefit from
489 !! 11 64-bit processing, otherwise say N. You must say Y for kernels for
490 Under certain conditions this erratu !! 12 SGI IP27 (Origin 200 and 2000). If in doubt say N.
491 to occur at the same time as another <<
492 on the AMBA 5 CHI interface, which c <<
493 interconnect reorders the two transa <<
494 <<
495 The workaround promotes data cache c <<
496 data cache clean-and-invalidate. <<
497 Please note that this does not neces <<
498 as it depends on the alternative fra <<
499 the kernel if an affected CPU is det <<
500 13
501 If unsure, say Y. !! 14 config 64BIT
>> 15 def_bool MIPS64
502 16
503 config ARM64_ERRATUM_824069 !! 17 config MIPS32
504 bool "Cortex-A53: 824069: Cache line m !! 18 bool
>> 19 depends on MIPS64 = 'n'
505 default y 20 default y
506 select ARM64_WORKAROUND_CLEAN_CACHE <<
507 help <<
508 This option adds an alternative code <<
509 erratum 824069 on Cortex-A53 parts u <<
510 to a coherent interconnect. <<
511 <<
512 If a Cortex-A53 processor is executi <<
513 write instruction at the same time a <<
514 cluster is executing a cache mainten <<
515 address, then this erratum might cau <<
516 incorrectly marked as dirty. <<
517 <<
518 The workaround promotes data cache c <<
519 data cache clean-and-invalidate. <<
520 Please note that this option does no <<
521 workaround, as it depends on the alt <<
522 only patch the kernel if an affected <<
523 21
524 If unsure, say Y. !! 22 mainmenu "Linux/MIPS Kernel Configuration"
525 23
526 config ARM64_ERRATUM_819472 !! 24 source "init/Kconfig"
527 bool "Cortex-A53: 819472: Store exclus <<
528 default y <<
529 select ARM64_WORKAROUND_CLEAN_CACHE <<
530 help <<
531 This option adds an alternative code <<
532 erratum 819472 on Cortex-A53 parts u <<
533 present when it is connected to a co <<
534 <<
535 If the processor is executing a load <<
536 the same time as a processor in anot <<
537 maintenance operation to the same ad <<
538 cause data corruption. <<
539 <<
540 The workaround promotes data cache c <<
541 data cache clean-and-invalidate. <<
542 Please note that this does not neces <<
543 as it depends on the alternative fra <<
544 the kernel if an affected CPU is det <<
545 25
546 If unsure, say Y. !! 26 menu "Machine selection"
547 27
548 config ARM64_ERRATUM_832075 !! 28 config ACER_PICA_61
549 bool "Cortex-A57: 832075: possible dea !! 29 bool "Support for Acer PICA 1 chipset (EXPERIMENTAL)"
550 default y !! 30 depends on EXPERIMENTAL
551 help 31 help
552 This option adds an alternative code !! 32 This is a machine with a R4400 133/150 MHz CPU. To compile a Linux
553 erratum 832075 on Cortex-A57 parts u !! 33 kernel that runs on these, say Y here. For details about Linux on
554 !! 34 the MIPS architecture, check out the Linux/MIPS FAQ on the WWW at
555 Affected Cortex-A57 parts might dead !! 35 <http://oss.sgi.com/mips/>.
556 instructions to Write-Back memory ar <<
557 <<
558 The workaround is to promote device <<
559 semantics. <<
560 Please note that this does not neces <<
561 as it depends on the alternative fra <<
562 the kernel if an affected CPU is det <<
563 36
564 If unsure, say Y. !! 37 config BAGET_MIPS
565 !! 38 bool "Support for BAGET MIPS series (EXPERIMENTAL)"
566 config ARM64_ERRATUM_834220 !! 39 depends on MIPS32 && EXPERIMENTAL
567 bool "Cortex-A57: 834220: Stage 2 tran <<
568 depends on KVM <<
569 help <<
570 This option adds an alternative code <<
571 erratum 834220 on Cortex-A57 parts u <<
572 <<
573 Affected Cortex-A57 parts might repo <<
574 fault as the result of a Stage 1 fau <<
575 page boundary when there is a permis <<
576 alignment fault at Stage 1 and a tra <<
577 <<
578 The workaround is to verify that the <<
579 doesn't generate a fault before hand <<
580 Please note that this does not neces <<
581 as it depends on the alternative fra <<
582 the kernel if an affected CPU is det <<
583 <<
584 If unsure, say N. <<
585 <<
586 config ARM64_ERRATUM_1742098 <<
587 bool "Cortex-A57/A72: 1742098: ELR rec <<
588 depends on COMPAT <<
589 default y <<
590 help 40 help
591 This option removes the AES hwcap fo !! 41 This enables support for the Baget, a Russian embedded system. For
592 workaround erratum 1742098 on Cortex !! 42 more details about the Baget see the Linux/MIPS FAQ on
593 !! 43 <http://oss.sgi.com/mips/>.
594 Affected parts may corrupt the AES s <<
595 taken between a pair of AES instruct <<
596 are only present if the cryptography <<
597 All software should have a fallback <<
598 that don't implement the cryptograph <<
599 44
600 If unsure, say Y. !! 45 config CASIO_E55
601 !! 46 bool "Support for CASIO CASSIOPEIA E-10/15/55/65"
602 config ARM64_ERRATUM_845719 <<
603 bool "Cortex-A53: 845719: a load might <<
604 depends on COMPAT <<
605 default y <<
606 help <<
607 This option adds an alternative code <<
608 erratum 845719 on Cortex-A53 parts u <<
609 <<
610 When running a compat (AArch32) user <<
611 part, a load at EL0 from a virtual a <<
612 bits of the virtual address used by <<
613 might return incorrect data. <<
614 <<
615 The workaround is to write the conte <<
616 return to a 32-bit task. <<
617 Please note that this does not neces <<
618 as it depends on the alternative fra <<
619 the kernel if an affected CPU is det <<
620 <<
621 If unsure, say Y. <<
622 <<
623 config ARM64_ERRATUM_843419 <<
624 bool "Cortex-A53: 843419: A load or st <<
625 default y <<
626 help <<
627 This option links the kernel with '- <<
628 enables PLT support to replace certa <<
629 cause subsequent memory accesses to <<
630 Cortex-A53 parts up to r0p4. <<
631 47
632 If unsure, say Y. !! 48 config MIPS_COBALT
>> 49 bool "Support for Cobalt Server (EXPERIMENTAL)"
>> 50 depends on EXPERIMENTAL
633 51
634 config ARM64_LD_HAS_FIX_ERRATUM_843419 !! 52 config DECSTATION
635 def_bool $(ld-option,--fix-cortex-a53- !! 53 bool "Support for DECstations"
>> 54 depends on MIPS32 || EXPERIMENTAL
>> 55 ---help---
>> 56 This enables support for DEC's MIPS based workstations. For details
>> 57 see the Linux/MIPS FAQ on <http://oss.sgi.com/mips/> and the
>> 58 DECstation porting pages on <http://decstation.unix-ag.org/>.
636 59
637 config ARM64_ERRATUM_1024718 !! 60 If you have one of the following DECstation Models you definitely
638 bool "Cortex-A55: 1024718: Update of D !! 61 want to choose R4xx0 for the CPU Type:
639 default y <<
640 help <<
641 This option adds a workaround for AR <<
642 62
643 Affected Cortex-A55 cores (all revis !! 63 DECstation 5000/50
644 update of the hardware dirty bit whe !! 64 DECstation 5000/150
645 without a break-before-make. The wor !! 65 DECstation 5000/260
646 of hardware DBM locally on the affec !! 66 DECsystem 5900/260
647 this erratum will continue to use th <<
648 67
649 If unsure, say Y. !! 68 otherwise choose R3000.
650 69
651 config ARM64_ERRATUM_1418040 !! 70 config MIPS_EV64120
652 bool "Cortex-A76/Neoverse-N1: MRC read !! 71 bool "Support for Galileo EV64120 Evaluation board (EXPERIMENTAL)"
653 default y !! 72 depends on EXPERIMENTAL
654 depends on COMPAT <<
655 help 73 help
656 This option adds a workaround for AR !! 74 This is an evaluation board based on the Galileo GT-64120
657 errata 1188873 and 1418040. !! 75 single-chip system controller that contains a MIPS R5000 compatible
>> 76 core running at 75/100MHz. Their website is located at
>> 77 <http://www.galileot.com/>. Say Y here if you wish to build a
>> 78 kernel for this platform.
658 79
659 Affected Cortex-A76/Neoverse-N1 core !! 80 config EVB_PCI1
660 cause register corruption when acces !! 81 bool "Enable Second PCI (PCI1)"
661 from AArch32 userspace. !! 82 depends on MIPS_EV64120
662 83
663 If unsure, say Y. !! 84 if MOMENCO_OCELOT_G || MOMENCO_OCELOT
664 85
665 config ARM64_WORKAROUND_SPECULATIVE_AT !! 86 config SYSCLK_100
666 bool 87 bool
667 <<
668 config ARM64_ERRATUM_1165522 <<
669 bool "Cortex-A76: 1165522: Speculative <<
670 default y 88 default y
671 select ARM64_WORKAROUND_SPECULATIVE_AT <<
672 help <<
673 This option adds a workaround for AR <<
674 89
675 Affected Cortex-A76 cores (r0p0, r1p !! 90 endif
676 corrupted TLBs by speculating an AT !! 91 if MIPS_EV64120
677 context switch. <<
678 92
679 If unsure, say Y. !! 93 choice
>> 94 prompt "Galileo Chip Clock"
>> 95 default SYSCLK_83
680 96
681 config ARM64_ERRATUM_1319367 !! 97 config SYSCLK_75
682 bool "Cortex-A57/A72: 1319537: Specula !! 98 bool "75"
683 default y <<
684 select ARM64_WORKAROUND_SPECULATIVE_AT <<
685 help <<
686 This option adds work arounds for AR <<
687 and A72 erratum 1319367 <<
688 99
689 Cortex-A57 and A72 cores could end-u !! 100 config SYSCLK_83
690 speculating an AT instruction during !! 101 bool "83.3"
691 102
692 If unsure, say Y. !! 103 config SYSCLK_100
>> 104 bool "100" if MIPS_EV64120
693 105
694 config ARM64_ERRATUM_1530923 !! 106 endchoice
695 bool "Cortex-A55: 1530923: Speculative <<
696 default y <<
697 select ARM64_WORKAROUND_SPECULATIVE_AT <<
698 help <<
699 This option adds a workaround for AR <<
700 <<
701 Affected Cortex-A55 cores (r0p0, r0p <<
702 corrupted TLBs by speculating an AT <<
703 context switch. <<
704 <<
705 If unsure, say Y. <<
706 107
707 config ARM64_WORKAROUND_REPEAT_TLBI !! 108 endif
708 bool <<
709 109
710 config ARM64_ERRATUM_2441007 !! 110 config MIPS_EV96100
711 bool "Cortex-A55: Completion of affect !! 111 bool "Support for Galileo EV96100 Evaluation board (EXPERIMENTAL)"
712 select ARM64_WORKAROUND_REPEAT_TLBI !! 112 depends on EXPERIMENTAL
713 help 113 help
714 This option adds a workaround for AR !! 114 This is an evaluation board based on the Galielo GT-96100 LAN/WAN
715 !! 115 communications controllers containing a MIPS R5000 compatible core
716 Under very rare circumstances, affec !! 116 running at 83MHz. Their website is <http://www.galileot.com/>. Say Y
717 may not handle a race between a brea !! 117 here if you wish to build a kernel for this platform.
718 CPU, and another CPU accessing the s <<
719 store to a page that has been unmapp <<
720 <<
721 Work around this by adding the affec <<
722 TLB sequences to be done twice. <<
723 <<
724 If unsure, say N. <<
725 <<
726 config ARM64_ERRATUM_1286807 <<
727 bool "Cortex-A76: Modification of the <<
728 select ARM64_WORKAROUND_REPEAT_TLBI <<
729 help <<
730 This option adds a workaround for AR <<
731 <<
732 On the affected Cortex-A76 cores (r0 <<
733 address for a cacheable mapping of a <<
734 accessed by a core while another cor <<
735 address to a new physical page using <<
736 break-before-make sequence, then und <<
737 TLBI+DSB completes before a read usi <<
738 invalidated has been observed by oth <<
739 workaround repeats the TLBI+DSB oper <<
740 <<
741 If unsure, say N. <<
742 118
743 config ARM64_ERRATUM_1463225 !! 119 config MIPS_IVR
744 bool "Cortex-A76: Software Step might !! 120 bool "Support for Globespan IVR board"
745 default y <<
746 help 121 help
747 This option adds a workaround for Ar !! 122 This is an evaluation board built by Globespan to showcase thir
>> 123 iVR (Internet Video Recorder) design. It utilizes a QED RM5231
>> 124 R5000 MIPS core. More information can be found out their website
>> 125 located at <http://www.globespan.net/products/product4.html>P. Say Y
>> 126 here if you wish to build a kernel for this platform.
748 127
749 On the affected Cortex-A76 cores (r0 !! 128 config LASAT
750 of a system call instruction (SVC) c !! 129 bool "Support for LASAT Networks platforms"
751 subsequent interrupts when software <<
752 exception handler of the system call <<
753 is enabled or VHE is in use. <<
754 130
755 Work around the erratum by triggerin !! 131 config PICVUE
756 when handling a system call from a t !! 132 tristate "PICVUE LCD display driver"
757 in a VHE configuration of the kernel !! 133 depends on LASAT
758 134
759 If unsure, say Y. !! 135 config PICVUE_PROC
>> 136 tristate "PICVUE LCD display driver /proc interface"
>> 137 depends on PICVUE
760 138
761 config ARM64_ERRATUM_1542419 !! 139 config DS1603
762 bool "Neoverse-N1: workaround mis-orde !! 140 bool "DS1603 RTC driver"
763 help !! 141 depends on LASAT
764 This option adds a workaround for AR <<
765 1542419. <<
766 142
767 Affected Neoverse-N1 cores could exe !! 143 config LASAT_SYSCTL
768 modified by another CPU. The workaro !! 144 bool "LASAT sysctl interface"
769 counterpart. !! 145 depends on LASAT
770 146
771 Workaround the issue by hiding the D !! 147 config HP_LASERJET
772 forces user-space to perform cache m !! 148 bool "Support for Hewlett Packard LaserJet board"
773 149
774 If unsure, say N. !! 150 config IBM_WORKPAD
>> 151 bool "Support for IBM WorkPad z50"
775 152
776 config ARM64_ERRATUM_1508412 !! 153 config MIPS_ITE8172
777 bool "Cortex-A77: 1508412: workaround !! 154 bool "Support for ITE 8172G board"
778 default y <<
779 help 155 help
780 This option adds a workaround for Ar !! 156 Ths is an evaluation board made by ITE <http://www.ite.com.tw/>
781 !! 157 with ATX form factor that utilizes a MIPS R5000 to work with its
782 Affected Cortex-A77 cores (r0p0, r1p !! 158 ITE8172G companion internet appliance chip. The MIPS core can be
783 of a store-exclusive or read of PAR_ !! 159 either a NEC Vr5432 or QED RM5231. Say Y here if you wish to build
784 non-cacheable memory attributes. The !! 160 a kernel for this platform.
785 counterpart. <<
786 <<
787 KVM guests must also have the workar <<
788 deadlock the system. <<
789 161
790 Work around the issue by inserting D !! 162 config IT8172_REVC
791 register reads and warning KVM users !! 163 bool "Support for older IT8172 (Rev C)"
792 to prevent a speculative PAR_EL1 rea !! 164 depends on MIPS_ITE8172
793 <<
794 If unsure, say Y. <<
795 <<
796 config ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MO <<
797 bool <<
798 <<
799 config ARM64_ERRATUM_2051678 <<
800 bool "Cortex-A510: 2051678: disable Ha <<
801 default y <<
802 help 165 help
803 This options adds the workaround for !! 166 Say Y here to support the older, Revision C version of the Integrated
804 Affected Cortex-A510 might not respe !! 167 Technology Express, Inc. ITE8172 SBC. Vendor page at
805 hardware update of the page table's !! 168 <http://www.ite.com.tw/ia/brief_it8172bsp.htm>; picture of the
806 is to not enable the feature on affe !! 169 board at <http://www.mvista.com/allies/semiconductor/ite.html>.
807 170
808 If unsure, say Y. !! 171 config MIPS_ATLAS
809 !! 172 bool "Support for MIPS Atlas board"
810 config ARM64_ERRATUM_2077057 <<
811 bool "Cortex-A510: 2077057: workaround <<
812 default y <<
813 help 173 help
814 This option adds the workaround for !! 174 This enables support for the QED R5231-based MIPS Atlas evaluation
815 Affected Cortex-A510 may corrupt SPS !! 175 board.
816 expected, but a Pointer Authenticati <<
817 erratum causes SPSR_EL1 to be copied <<
818 EL1 to cause a return to EL2 with a <<
819 176
820 This can only happen when EL2 is ste !! 177 config MIPS_MAGNUM_4000
>> 178 bool "Support for MIPS Magnum 4000"
>> 179 help
>> 180 This is a machine with a R4000 100 MHz CPU. To compile a Linux
>> 181 kernel that runs on these, say Y here. For details about Linux on
>> 182 the MIPS architecture, check out the Linux/MIPS FAQ on the WWW at
>> 183 <http://oss.sgi.com/mips/>.
821 184
822 When these conditions occur, the SPS !! 185 config MIPS_MALTA
823 previous guest entry, and can be res !! 186 bool "Support for MIPS Malta board"
>> 187 help
>> 188 This enables support for the VR5000-based MIPS Malta evaluation
>> 189 board.
824 190
825 If unsure, say Y. !! 191 config MIPS_SEAD
>> 192 bool "Support for MIPS SEAD board (EXPERIMENTAL)"
>> 193 depends on EXPERIMENTAL
826 194
827 config ARM64_ERRATUM_2658417 !! 195 config MOMENCO_OCELOT
828 bool "Cortex-A510: 2658417: remove BF1 !! 196 bool "Support for Momentum Ocelot board"
829 default y <<
830 help 197 help
831 This option adds the workaround for !! 198 The Ocelot is a MIPS-based Single Board Computer (SBC) made by
832 Affected Cortex-A510 (r0p0 to r1p1) !! 199 Momentum Computer <http://www.momenco.com/>.
833 BFMMLA or VMMLA instructions in rare <<
834 A510 CPUs are using shared neon hard <<
835 discoverable by the kernel, hide the <<
836 user-space should not be using these <<
837 200
838 If unsure, say Y. !! 201 config MOMENCO_OCELOT_G
>> 202 bool "Support for Momentum Ocelot-G board"
>> 203 help
>> 204 The Ocelot is a MIPS-based Single Board Computer (SBC) made by
>> 205 Momentum Computer <http://www.momenco.com/>.
839 206
840 config ARM64_ERRATUM_2119858 !! 207 config MOMENCO_OCELOT_C
841 bool "Cortex-A710/X2: 2119858: workaro !! 208 bool "Support for Momentum Ocelot-C board"
842 default y <<
843 depends on CORESIGHT_TRBE <<
844 select ARM64_WORKAROUND_TRBE_OVERWRITE <<
845 help 209 help
846 This option adds the workaround for !! 210 The Ocelot is a MIPS-based Single Board Computer (SBC) made by
>> 211 Momentum Computer <http://www.momenco.com/>.
847 212
848 Affected Cortex-A710/X2 cores could !! 213 config DDB5074
849 data at the base of the buffer (poin !! 214 bool "Support for NEC DDB Vrc-5074 (EXPERIMENTAL)"
850 the event of a WRAP event. !! 215 depends on EXPERIMENTAL
>> 216 help
>> 217 This enables support for the VR5000-based NEC DDB Vrc-5074
>> 218 evaluation board.
851 219
852 Work around the issue by always maki !! 220 config DDB5476
853 256 bytes before enabling the buffer !! 221 bool "Support for NEC DDB Vrc-5476"
854 the buffer with ETM ignore packets u !! 222 help
>> 223 This enables support for the R5432-based NEC DDB Vrc-5476
>> 224 evaluation board.
855 225
856 If unsure, say Y. !! 226 Features : kernel debugging, serial terminal, NFS root fs, on-board
>> 227 ether port USB, AC97, PCI, PCI VGA card & framebuffer console,
>> 228 IDE controller, PS2 keyboard, PS2 mouse, etc.
857 229
858 config ARM64_ERRATUM_2139208 !! 230 config DDB5477
859 bool "Neoverse-N2: 2139208: workaround !! 231 bool "Support for NEC DDB Vrc-5477"
860 default y <<
861 depends on CORESIGHT_TRBE <<
862 select ARM64_WORKAROUND_TRBE_OVERWRITE <<
863 help 232 help
864 This option adds the workaround for !! 233 This enables support for the R5432-based NEC DDB Vrc-5477,
>> 234 or Rockhopper/SolutionGear boards with R5432/R5500 CPUs.
865 235
866 Affected Neoverse-N2 cores could ove !! 236 Features : kernel debugging, serial terminal, NFS root fs, on-board
867 data at the base of the buffer (poin !! 237 ether port USB, AC97, PCI, etc.
868 the event of a WRAP event. <<
869 238
870 Work around the issue by always maki !! 239 config DDB5477_BUS_FREQUENCY
871 256 bytes before enabling the buffer !! 240 int "bus frequency (in kHZ, 0 for auto-detect)"
872 the buffer with ETM ignore packets u !! 241 depends on DDB5477
>> 242 default 0
>> 243
>> 244 config NEC_OSPREY
>> 245 bool "Support for NEC Osprey board"
873 246
874 If unsure, say Y. !! 247 config NEC_EAGLE
>> 248 bool "Support for NEC Eagle/Hawk board"
875 249
876 config ARM64_WORKAROUND_TSB_FLUSH_FAILURE !! 250 config OLIVETTI_M700
877 bool !! 251 bool "Support for Olivetti M700-10"
>> 252 help
>> 253 This is a machine with a R4000 100 MHz CPU. To compile a Linux
>> 254 kernel that runs on these, say Y here. For details about Linux on
>> 255 the MIPS architecture, check out the Linux/MIPS FAQ on the WWW at
>> 256 <http://oss.sgi.com/mips/>.
878 257
879 config ARM64_ERRATUM_2054223 !! 258 config SGI_IP22
880 bool "Cortex-A710: 2054223: workaround !! 259 bool "Support for SGI IP22 (Indy/Indigo2)"
881 default y <<
882 select ARM64_WORKAROUND_TSB_FLUSH_FAIL <<
883 help 260 help
884 Enable workaround for ARM Cortex-A71 !! 261 This are the SGI Indy, Challenge S and Indigo2, as well as certain
>> 262 OEM variants like the Tandem CMN B006S. To compile a Linux kernel
>> 263 that runs on these, say Y here.
885 264
886 Affected cores may fail to flush the !! 265 config SGI_IP27
887 the PE is in trace prohibited state. !! 266 bool "Support for SGI IP27 (Origin200/2000)"
888 of the trace cached. !! 267 depends on MIPS64
>> 268 help
>> 269 This are the SGI Origin 200, Origin 2000 and Onyx 2 Graphics
>> 270 workstations. To compile a Linux kernel that runs on these, say Y
>> 271 here.
889 272
890 Workaround is to issue two TSB conse !! 273 #config SGI_SN0_XXL
>> 274 # bool "IP27 XXL"
>> 275 # depends on SGI_IP27
>> 276 # This options adds support for userspace processes upto 16TB size.
>> 277 # Normally the limit is just .5TB.
891 278
892 If unsure, say Y. !! 279 config SGI_SN0_N_MODE
>> 280 bool "IP27 N-Mode"
>> 281 depends on SGI_IP27
>> 282 help
>> 283 The nodes of Origin 200, Origin 2000 and Onyx 2 systems can be
>> 284 configured in either N-Modes which allows for more nodes or M-Mode
>> 285 which allows for more memory. Your system is most probably
>> 286 running in M-Mode, so you should say N here.
893 287
894 config ARM64_ERRATUM_2067961 !! 288 config DISCONTIGMEM
895 bool "Neoverse-N2: 2067961: workaround !! 289 bool "Discontiguous Memory Support"
896 default y !! 290 depends on SGI_IP27
897 select ARM64_WORKAROUND_TSB_FLUSH_FAIL <<
898 help 291 help
899 Enable workaround for ARM Neoverse-N !! 292 Say Y to upport efficient handling of discontiguous physical memory,
>> 293 for architectures which are either NUMA (Non-Uniform Memory Access)
>> 294 or have huge holes in the physical address space for other reasons.
>> 295 See <file:Documentation/vm/numa> for more.
900 296
901 Affected cores may fail to flush the !! 297 config NUMA
902 the PE is in trace prohibited state. !! 298 bool "NUMA Support"
903 of the trace cached. !! 299 depends on SGI_IP27
>> 300 help
>> 301 Say Y to compile the kernel to support NUMA (Non-Uniform Memory
>> 302 Access). This option is for configuring high-end multiprocessor
>> 303 server machines. If in doubt, say N.
904 304
905 Workaround is to issue two TSB conse !! 305 config MAPPED_KERNEL
>> 306 bool "Mapped kernel support"
>> 307 depends on SGI_IP27
>> 308 help
>> 309 Change the way a Linux kernel is loaded unto memory on a MIPS64
>> 310 machine. This is required in order to support text replication and
>> 311 NUMA. If you need to undersatand it, read the source code.
906 312
907 If unsure, say Y. !! 313 config REPLICATE_KTEXT
>> 314 bool "Kernel text replication support"
>> 315 depends on SGI_IP27
>> 316 help
>> 317 Say Y here to enable replicating the kernel text across multiple
>> 318 nodes in a NUMA cluster. This trades memory for speed.
908 319
909 config ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANG !! 320 config REPLICATE_EXHANDLERS
910 bool !! 321 bool "Exception handler replication support"
>> 322 depends on SGI_IP27
>> 323 help
>> 324 Say Y here to enable replicating the kernel exception handlers
>> 325 across multiple nodes in a NUMA cluster. This trades memory for
>> 326 speed.
911 327
912 config ARM64_ERRATUM_2253138 !! 328 config SGI_IP32
913 bool "Neoverse-N2: 2253138: workaround !! 329 bool "Support for SGI IP32 (O2) (EXPERIMENTAL)"
914 depends on CORESIGHT_TRBE !! 330 depends on EXPERIMENTAL
915 default y <<
916 select ARM64_WORKAROUND_TRBE_WRITE_OUT <<
917 help 331 help
918 This option adds the workaround for !! 332 If you want this kernel to run on SGI O2 workstation, say Y here.
919 333
920 Affected Neoverse-N2 cores might wri !! 334 config SOC_AU1X00
921 for TRBE. Under some conditions, the !! 335 depends on MIPS32
922 virtually addressed page following t !! 336 bool "Support for AMD/Alchemy Au1X00 SOCs"
923 (i.e., the TRBLIMITR_EL1.LIMIT), ins <<
924 337
925 Work around this in the driver by al !! 338 choice
926 page beyond the TRBLIMITR_EL1.LIMIT, !! 339 prompt "Au1X00 SOC Type"
>> 340 depends on SOC_AU1X00
>> 341 help
>> 342 Say Y here to enable support for one of three AMD/Alchemy
>> 343 SOCs. For additional documentation see www.amd.com.
>> 344
>> 345 config SOC_AU1000
>> 346 bool "SOC_AU1000"
>> 347 config SOC_AU1100
>> 348 bool "SOC_AU1100"
>> 349 config SOC_AU1500
>> 350 bool "SOC_AU1500"
927 351
928 If unsure, say Y. !! 352 endchoice
929 353
930 config ARM64_ERRATUM_2224489 !! 354 choice
931 bool "Cortex-A710/X2: 2224489: workaro !! 355 prompt "AMD/Alchemy Pb1x and Db1x board support"
932 depends on CORESIGHT_TRBE !! 356 depends on SOC_AU1X00
933 default y !! 357 help
934 select ARM64_WORKAROUND_TRBE_WRITE_OUT !! 358 These are evaluation boards built by AMD/Alchemy to
935 help !! 359 showcase their Au1X00 Internet Edge Processors. The SOC design
936 This option adds the workaround for !! 360 is based on the MIPS32 architecture running at 266/400/500MHz
>> 361 with many integrated peripherals. Further information can be
>> 362 found at their website, <http://www.amd.com/>. Say Y here if you
>> 363 wish to build a kernel for this platform.
>> 364
>> 365 config MIPS_PB1000
>> 366 bool "PB1000 board"
>> 367 depends on SOC_AU1000
>> 368
>> 369 config MIPS_PB1100
>> 370 bool "PB1100 board"
>> 371 depends on SOC_AU1100
>> 372
>> 373 config MIPS_PB1500
>> 374 bool "PB1500 board"
>> 375 depends on SOC_AU1500
>> 376
>> 377 config MIPS_DB1000
>> 378 bool "DB1000 board"
>> 379 depends on SOC_AU1000
>> 380
>> 381 config MIPS_DB1100
>> 382 bool "DB1100 board"
>> 383 depends on SOC_AU1100
>> 384
>> 385 config MIPS_DB1500
>> 386 bool "DB1500 board"
>> 387 depends on SOC_AU1500
937 388
938 Affected Cortex-A710/X2 cores might !! 389 endchoice
939 for TRBE. Under some conditions, the <<
940 virtually addressed page following t <<
941 (i.e., the TRBLIMITR_EL1.LIMIT), ins <<
942 390
943 Work around this in the driver by al !! 391 config SIBYTE_SB1xxx_SOC
944 page beyond the TRBLIMITR_EL1.LIMIT, !! 392 bool "Support for Broadcom BCM1xxx SOCs (EXPERIMENTAL)"
>> 393 depends on EXPERIMENTAL
945 394
946 If unsure, say Y. !! 395 choice
>> 396 prompt "BCM1xxx SOC Type"
>> 397 depends on SIBYTE_SB1xxx_SOC
>> 398 default SIBYTE_SB1250
947 399
948 config ARM64_ERRATUM_2441009 !! 400 config SIBYTE_SB1250
949 bool "Cortex-A510: Completion of affec !! 401 bool "BCM1250"
950 select ARM64_WORKAROUND_REPEAT_TLBI <<
951 help <<
952 This option adds a workaround for AR <<
953 <<
954 Under very rare circumstances, affec <<
955 may not handle a race between a brea <<
956 CPU, and another CPU accessing the s <<
957 store to a page that has been unmapp <<
958 402
959 Work around this by adding the affec !! 403 endchoice
960 TLB sequences to be done twice. <<
961 404
962 If unsure, say N. !! 405 config SIMULATION
>> 406 bool "Running under simulation"
>> 407 depends on SIBYTE_SB1xxx_SOC
>> 408
>> 409 config SIBYTE_CFE
>> 410 bool "Booting from CFE"
>> 411 depends on SIBYTE_SB1xxx_SOC
>> 412
>> 413 config SIBYTE_CFE_CONSOLE
>> 414 bool "Use firmware console"
>> 415 depends on SIBYTE_CFE
963 416
964 config ARM64_ERRATUM_2064142 !! 417 config SIBYTE_STANDALONE
965 bool "Cortex-A510: 2064142: workaround !! 418 bool
966 depends on CORESIGHT_TRBE !! 419 depends on SIBYTE_SB1xxx_SOC && !SIBYTE_CFE
967 default y 420 default y
968 help <<
969 This option adds the workaround for <<
970 421
971 Affected Cortex-A510 core might fail !! 422 config SIBYTE_STANDALONE_RAM_SIZE
972 TRBE has been disabled. Under some c !! 423 int "Memory size (in megabytes)"
973 writes into TRBE registers TRBLIMITR !! 424 depends on SIBYTE_SB1xxx_SOC && !SIBYTE_CFE
974 and TRBTRG_EL1 will be ignored and w !! 425 default "32"
975 426
976 Work around this in the driver by ex !! 427 config SIBYTE_BUS_WATCHER
977 is stopped and before performing a s !! 428 bool "Support for Bus Watcher statistics"
978 registers. !! 429 depends on SIBYTE_SB1xxx_SOC
979 430
980 If unsure, say Y. !! 431 config SIBYTE_SB1250_PROF
>> 432 bool "Support for SB1/SOC profiling - SB1/SCD perf counters"
>> 433 depends on SIBYTE_SB1xxx_SOC
981 434
982 config ARM64_ERRATUM_2038923 !! 435 config SIBYTE_TBPROF
983 bool "Cortex-A510: 2038923: workaround !! 436 bool "Support for ZBbus profiling"
984 depends on CORESIGHT_TRBE !! 437 depends on SIBYTE_SB1xxx_SOC
985 default y <<
986 help <<
987 This option adds the workaround for <<
988 <<
989 Affected Cortex-A510 core might caus <<
990 prohibited within the CPU. As a resu <<
991 might be corrupted. This happens aft <<
992 TRBLIMITR_EL1.E, followed by just a <<
993 execution changes from a context, in <<
994 isn't, or vice versa. In these menti <<
995 is prohibited is inconsistent betwee <<
996 the trace buffer state might be corr <<
997 <<
998 Work around this in the driver by pr <<
999 trace is prohibited or not based on <<
1000 change to TRBLIMITR_EL1.E with at l <<
1001 two ISB instructions if no ERET is <<
1002 438
1003 If unsure, say Y. !! 439 config SIBYTE_SWARM
>> 440 bool "Support for SWARM board"
>> 441 depends on SIBYTE_SB1250
1004 442
1005 config ARM64_ERRATUM_1902691 !! 443 config SIBYTE_BOARD
1006 bool "Cortex-A510: 1902691: workaroun !! 444 bool
1007 depends on CORESIGHT_TRBE !! 445 depends on SIBYTE_SWARM
1008 default y 446 default y
1009 help <<
1010 This option adds the workaround for <<
1011 <<
1012 Affected Cortex-A510 core might cau <<
1013 into the memory. Effectively TRBE i <<
1014 trace data. <<
1015 447
1016 Work around this problem in the dri !! 448 config SNI_RM200_PCI
1017 affected cpus. The firmware must ha !! 449 bool "Support for SNI RM200 PCI"
1018 on such implementations. This will <<
1019 do this already. <<
1020 <<
1021 If unsure, say Y. <<
1022 <<
1023 config ARM64_ERRATUM_2457168 <<
1024 bool "Cortex-A510: 2457168: workaroun <<
1025 depends on ARM64_AMU_EXTN <<
1026 default y <<
1027 help 450 help
1028 This option adds the workaround for !! 451 The SNI RM200 PCI was a MIPS-based platform manufactured by Siemens
1029 !! 452 Nixdorf Informationssysteme (SNI), parent company of Pyramid
1030 The AMU counter AMEVCNTR01 (constan !! 453 Technology and now in turn merged with Fujitsu. Say Y here to
1031 as the system counter. On affected !! 454 support this machine type.
1032 incorrectly giving a significantly <<
1033 <<
1034 Work around this problem by returni <<
1035 key locations that results in disab <<
1036 is the same to firmware disabling a <<
1037 455
1038 If unsure, say Y. !! 456 config TANBAC_TB0226
>> 457 bool "Support for TANBAC TB0226 (Mbase)"
>> 458 help
>> 459 The TANBAC TB0226 (Mbase) is a MIPS-based platform manufactured by TANBAC.
>> 460 Please refer to <http://www.tanbac.co.jp/> about Mbase.
1039 461
1040 config ARM64_ERRATUM_2645198 !! 462 config TANBAC_TB0229
1041 bool "Cortex-A715: 2645198: Workaroun !! 463 bool "Support for TANBAC TB0229 (VR4131DIMM)"
1042 default y <<
1043 help 464 help
1044 This option adds the workaround for !! 465 The TANBAC TB0229 (VR4131DIMM) is a MIPS-based platform manufactured by TANBAC.
>> 466 Please refer to <http://www.tanbac.co.jp/> about VR4131DIMM.
1045 467
1046 If a Cortex-A715 cpu sees a page ma !! 468 config TOSHIBA_JMR3927
1047 to non-executable, it may corrupt t !! 469 bool "Support for Toshiba JMR-TX3927 board"
1048 next instruction abort caused by pe !! 470 depends on MIPS32
1049 471
1050 Only user-space does executable to !! 472 config TOSHIBA_RBTX4927
1051 mprotect() system call. Workaround !! 473 bool "Support for Toshiba TBTX49[23]7 board"
1052 TLB invalidation, for all changes t !! 474 depends on MIPS32
1053 475
1054 If unsure, say Y. !! 476 config VICTOR_MPC30X
>> 477 bool "Support for Victor MP-C303/304"
1055 478
1056 config ARM64_WORKAROUND_SPECULATIVE_UNPRIV_LO !! 479 config ZAO_CAPCELLA
1057 bool !! 480 bool "Support for ZAO Networks Capcella"
1058 481
1059 config ARM64_ERRATUM_2966298 !! 482 config RWSEM_GENERIC_SPINLOCK
1060 bool "Cortex-A520: 2966298: workaroun !! 483 bool
1061 select ARM64_WORKAROUND_SPECULATIVE_U <<
1062 default y 484 default y
1063 help <<
1064 This option adds the workaround for <<
1065 485
1066 On an affected Cortex-A520 core, a !! 486 config RWSEM_XCHGADD_ALGORITHM
1067 load might leak data from a privile !! 487 bool
1068 <<
1069 Work around this problem by executi <<
1070 <<
1071 If unsure, say Y. <<
1072 488
1073 config ARM64_ERRATUM_3117295 !! 489 #
1074 bool "Cortex-A510: 3117295: workaroun !! 490 # Select some configuration options automatically based on user selections.
1075 select ARM64_WORKAROUND_SPECULATIVE_U !! 491 #
>> 492 config ARC
>> 493 bool
>> 494 depends on SNI_RM200_PCI || SGI_IP32 || SGI_IP27 || SGI_IP22 || MIPS_MAGNUM_4000 || OLIVETTI_M700 || ACER_PICA_61
1076 default y 495 default y
1077 help <<
1078 This option adds the workaround for <<
1079 <<
1080 On an affected Cortex-A510 core, a <<
1081 load might leak data from a privile <<
1082 <<
1083 Work around this problem by executi <<
1084 496
1085 If unsure, say Y. !! 497 config GENERIC_ISA_DMA
1086 !! 498 bool
1087 config ARM64_ERRATUM_3194386 !! 499 depends on SNI_RM200_PCI || MIPS_MAGNUM_4000 || OLIVETTI_M700 || ACER_PICA_61
1088 bool "Cortex-*/Neoverse-*: workaround <<
1089 default y 500 default y
1090 help <<
1091 This option adds the workaround for <<
1092 <<
1093 * ARM Cortex-A76 erratum 3324349 <<
1094 * ARM Cortex-A77 erratum 3324348 <<
1095 * ARM Cortex-A78 erratum 3324344 <<
1096 * ARM Cortex-A78C erratum 3324346 <<
1097 * ARM Cortex-A78C erratum 3324347 <<
1098 * ARM Cortex-A710 erratam 3324338 <<
1099 * ARM Cortex-A715 errartum 3456084 <<
1100 * ARM Cortex-A720 erratum 3456091 <<
1101 * ARM Cortex-A725 erratum 3456106 <<
1102 * ARM Cortex-X1 erratum 3324344 <<
1103 * ARM Cortex-X1C erratum 3324346 <<
1104 * ARM Cortex-X2 erratum 3324338 <<
1105 * ARM Cortex-X3 erratum 3324335 <<
1106 * ARM Cortex-X4 erratum 3194386 <<
1107 * ARM Cortex-X925 erratum 3324334 <<
1108 * ARM Neoverse-N1 erratum 3324349 <<
1109 * ARM Neoverse N2 erratum 3324339 <<
1110 * ARM Neoverse-N3 erratum 3456111 <<
1111 * ARM Neoverse-V1 erratum 3324341 <<
1112 * ARM Neoverse V2 erratum 3324336 <<
1113 * ARM Neoverse-V3 erratum 3312417 <<
1114 <<
1115 On affected cores "MSR SSBS, #0" in <<
1116 subsequent speculative instructions <<
1117 speculative store bypassing. <<
1118 <<
1119 Work around this problem by placing <<
1120 Instruction Synchronization Barrier <<
1121 SSBS. The presence of the SSBS spec <<
1122 from hwcaps and EL0 reads of ID_AA6 <<
1123 will use the PR_SPEC_STORE_BYPASS p <<
1124 <<
1125 If unsure, say Y. <<
1126 501
1127 config CAVIUM_ERRATUM_22375 !! 502 config CONFIG_GT64120
1128 bool "Cavium erratum 22375, 24313" !! 503 bool
>> 504 depends on MIPS_EV64120 || MOMENCO_OCELOT
1129 default y 505 default y
1130 help <<
1131 Enable workaround for errata 22375 <<
1132 <<
1133 This implements two gicv3-its errat <<
1134 with a small impact affecting only <<
1135 506
1136 erratum 22375: only alloc 8MB tab !! 507 config I8259
1137 erratum 24313: ignore memory acce !! 508 bool
1138 !! 509 depends on SNI_RM200_PCI || DDB5477 || DDB5476 || DDB5074 || MIPS_MALTA || MIPS_MAGNUM_4000 || OLIVETTI_M700 || MIPS_COBALT || ACER_PICA_61
1139 The fixes are in ITS initialization <<
1140 type and table size provided by the <<
1141 <<
1142 If unsure, say Y. <<
1143 <<
1144 config CAVIUM_ERRATUM_23144 <<
1145 bool "Cavium erratum 23144: ITS SYNC <<
1146 depends on NUMA <<
1147 default y 510 default y
1148 help <<
1149 ITS SYNC command hang for cross nod <<
1150 511
1151 If unsure, say Y. !! 512 config MIPS_JAZZ
1152 !! 513 bool
1153 config CAVIUM_ERRATUM_23154 !! 514 depends on MIPS_MAGNUM_4000 || OLIVETTI_M700 || ACER_PICA_61
1154 bool "Cavium errata 23154 and 38545: <<
1155 default y 515 default y
1156 help <<
1157 The ThunderX GICv3 implementation r <<
1158 reading the IAR status to ensure da <<
1159 (access to icc_iar1_el1 is not sync <<
1160 516
1161 It also suffers from erratum 38545 !! 517 config NONCOHERENT_IO
1162 OcteonTX and OcteonTX2), resulting !! 518 bool
1163 spuriously presented to the CPU int !! 519 depends on ZAO_CAPCELLA || VICTOR_MPC30X || TOSHIBA_JMR3927 || TOSHIBA_RBTX4927 || SNI_RM200_PCI || SGI_IP32 || SGI_IP22 || NEC_EAGLE || NEC_OSPREY || DDB5477 || DDB5476 || DDB5074 || MOMENCO_OCELOT || MOMENCO_OCELOT_C || MOMENCO_OCELOT_G || MIPS_SEAD || MIPS_MALTA || MIPS_MAGNUM_4000 || OLIVETTI_M700 || MIPS_ATLAS || LASAT || MIPS_ITE8172 || IBM_WORKPAD || HP_LASERJET || MIPS_IVR || MIPS_EV96100 || MIPS_EV64120 || DECSTATION || MIPS_COBALT || MIPS_PB1500 || MIPS_PB1100 || MIPS_PB1000 || CASIO_E55 || ACER_PICA_61 || TANBAC_TB0226 || TANBAC_TB0229
>> 520 default y if ZAO_CAPCELLA || VICTOR_MPC30X || TOSHIBA_JMR3927 || TOSHIBA_RBTX4927 || SNI_RM200_PCI || SGI_IP32 || SGI_IP22 || NEC_EAGLE || NEC_OSPREY || DDB5477 || DDB5476 || DDB5074 || MOMENCO_OCELOT_G || MOMENCO_OCELOT || MIPS_SEAD || MIPS_MALTA || MIPS_MAGNUM_4000 || OLIVETTI_M700 || MIPS_ATLAS || LASAT || MIPS_ITE8172 || IBM_WORKPAD || HP_LASERJET || MIPS_IVR || MIPS_EV96100 || MIPS_EV64120 || DECSTATION || MIPS_COBALT || MIPS_PB1500 || MIPS_PB1100 || MIPS_PB1000 || CASIO_E55 || ACER_PICA_61 || TANBAC_TB0226 || TANBAC_TB0229
>> 521 default n if (SIBYTE_SB1250 || SGI_IP27)
1164 522
1165 If unsure, say Y. !! 523 config CPU_LITTLE_ENDIAN
>> 524 bool "Generate little endian code"
>> 525 default y if ACER_PICA_61 || CASIO_E55 || DDB5074 || DDB5476 || DDB5477 || DECSTATION || HP_LASERJET || IBM_WORKPAD || LASAT || MIPS_COBALT || MIPS_ITE8172 || MIPS_IVR || MIPS_PB1000 || MIPS_PB1100 || MIPS_PB1500 || NEC_OSPREY || NEC_EAGLE || OLIVETTI_M700 || SNI_RM200_PCI || VICTOR_MPC30X || ZAO_CAPCELLA
>> 526 default n if BAGET_MIPS || MIPS_EV64120 || MIPS_EV96100 || MOMENCO_OCELOT || MOMENCO_OCELOT_G || SGI_IP22 || SGI_IP27 || SGI_IP32 || TOSHIBA_JMR3927
>> 527 help
>> 528 Some MIPS machines can be configured for either little or big endian
>> 529 byte order. These modes require different kernels. Say Y if your
>> 530 machine is little endian, N if it's a big endian machine.
1166 531
1167 config CAVIUM_ERRATUM_27456 !! 532 config IRQ_CPU
1168 bool "Cavium erratum 27456: Broadcast !! 533 bool
>> 534 depends on ZAO_CAPCELLA || VICTOR_MPC30X || SGI_IP22 || NEC_EAGLE || NEC_OSPREY || DDB5477 || DDB5476 || DDB5074 || IBM_WORKPAD || HP_LASERJET || DECSTATION || CASIO_E55 || TANBAC_TB0226 || TANBAC_TB0229
1169 default y 535 default y
1170 help <<
1171 On ThunderX T88 pass 1.x through 2. <<
1172 instructions may cause the icache t <<
1173 contains data for a non-current ASI <<
1174 invalidate the icache when changing <<
1175 <<
1176 If unsure, say Y. <<
1177 536
1178 config CAVIUM_ERRATUM_30115 !! 537 config VR41XX_TIME_C
1179 bool "Cavium erratum 30115: Guest may !! 538 bool
>> 539 depends on ZAO_CAPCELLA || VICTOR_MPC30X || NEC_EAGLE || IBM_WORKPAD || CASIO_E55 || TANBAC_TB0226 || TANBAC_TB0229
1180 default y 540 default y
1181 help <<
1182 On ThunderX T88 pass 1.x through 2. <<
1183 1.2, and T83 Pass 1.0, KVM guest ex <<
1184 interrupts in host. Trapping both G <<
1185 accesses sidesteps the issue. <<
1186 541
1187 If unsure, say Y. !! 542 config DUMMY_KEYB
>> 543 bool
>> 544 depends on ZAO_CAPCELLA || VICTOR_MPC30X || SIBYTE_SB1250 || NEC_EAGLE || NEC_OSPREY || DDB5477 || IBM_WORKPAD || CASIO_E55 || TANBAC_TB0226 || TANBAC_TB0229
>> 545 default y
1188 546
1189 config CAVIUM_TX2_ERRATUM_219 !! 547 config VR41XX_COMMON
1190 bool "Cavium ThunderX2 erratum 219: P !! 548 bool
>> 549 depends on NEC_EAGLE || ZAO_CAPCELLA || VICTOR_MPC30X || IBM_WORKPAD || CASIO_E55 || TANBAC_TB0226 || TANBAC_TB0229
1191 default y 550 default y
1192 help <<
1193 On Cavium ThunderX2, a load, store <<
1194 TTBR update and the corresponding c <<
1195 cause a spurious Data Abort to be d <<
1196 the CPU core. <<
1197 <<
1198 Work around the issue by avoiding t <<
1199 trapping KVM guest TTBRx_EL1 writes <<
1200 trap handler performs the correspon <<
1201 instruction and ensures context syn <<
1202 exception return. <<
1203 551
1204 If unsure, say Y. !! 552 config VRC4173
>> 553 tristate "NEC VRC4173 Support"
>> 554 depends on NEC_EAGLE || VICTOR_MPC30X
1205 555
1206 config FUJITSU_ERRATUM_010001 !! 556 config DDB5XXX_COMMON
1207 bool "Fujitsu-A64FX erratum E#010001: !! 557 bool
>> 558 depends on DDB5074 || DDB5476 || DDB5477
1208 default y 559 default y
1209 help <<
1210 This option adds a workaround for F <<
1211 On some variants of the Fujitsu-A64 <<
1212 accesses may cause undefined fault <<
1213 This fault occurs under a specific <<
1214 load/store instruction performs an <<
1215 case-1 TTBR0_EL1 with TCR_EL1.NFD0 <<
1216 case-2 TTBR0_EL2 with TCR_EL2.NFD0 <<
1217 case-3 TTBR1_EL1 with TCR_EL1.NFD1 <<
1218 case-4 TTBR1_EL2 with TCR_EL2.NFD1 <<
1219 <<
1220 The workaround is to ensure these b <<
1221 The workaround only affects the Fuj <<
1222 560
1223 If unsure, say Y. !! 561 config MIPS_BOARDS_GEN
>> 562 bool
>> 563 depends on MIPS_ATLAS || MIPS_MALTA || MIPS_SEAD
>> 564 default y
1224 565
1225 config HISILICON_ERRATUM_161600802 !! 566 config ITE_BOARD_GEN
1226 bool "Hip07 161600802: Erroneous redi !! 567 bool
>> 568 depends on MIPS_IVR || MIPS_ITE8172
1227 default y 569 default y
1228 help <<
1229 The HiSilicon Hip07 SoC uses the wr <<
1230 when issued ITS commands such as VM <<
1231 a 128kB offset to be applied to the <<
1232 570
1233 If unsure, say Y. !! 571 config NEW_PCI
>> 572 bool
>> 573 depends on ZAO_CAPCELLA || VICTOR_MPC30X || TOSHIBA_JMR3927 || TOSHIBA_RBTX4927 || NEC_EAGLE || DDB5477 || DDB5476 || DDB5074 || MIPS_ITE8172 || HP_LASERJET || MIPS_IVR || MIPS_EV96100 || MIPS_PB1500 || MIPS_PB1100 || MIPS_PB1000 || TANBAC_TB0226 || TANBAC_TB0229
>> 574 default y
1234 575
1235 config QCOM_FALKOR_ERRATUM_1003 !! 576 config SWAP_IO_SPACE
1236 bool "Falkor E1003: Incorrect transla !! 577 bool "Support for paging of anonymous memory"
>> 578 depends on TOSHIBA_JMR3927 || TOSHIBA_RBTX4927 || SIBYTE_SB1250 || SGI_IP22 || MOMENCO_OCELOT_C || MOMENCO_OCELOT_G || MOMENCO_OCELOT || MIPS_MALTA || MIPS_ATLAS || MIPS_EV96100 || MIPS_PB1100 || MIPS_PB1000
1237 default y 579 default y
1238 help 580 help
1239 On Falkor v1, an incorrect ASID may !! 581 This option allows you to choose whether you want to have support
1240 and BADDR are changed together in T !! 582 for socalled swap devices or swap files in your kernel that are
1241 in TTBR1_EL1, this situation only o !! 583 used to provide more virtual memory than the actual RAM present
1242 then only for entries in the walk c !! 584 in your computer. If unusre say Y.
1243 is unchanged. Work around the errat <<
1244 entries for the trampoline before e <<
1245 585
1246 config QCOM_FALKOR_ERRATUM_1009 !! 586 config SIBYTE_HAS_LDT
1247 bool "Falkor E1009: Prematurely compl !! 587 bool
>> 588 depends on SIBYTE_SB1xxx_SOC && PCI
1248 default y 589 default y
1249 select ARM64_WORKAROUND_REPEAT_TLBI <<
1250 help <<
1251 On Falkor v1, the CPU may premature <<
1252 TLBI xxIS invalidate maintenance op <<
1253 one more time to fix the issue. <<
1254 590
1255 If unsure, say Y. !! 591 config AU1000_USB_DEVICE
>> 592 bool
>> 593 depends on MIPS_PB1500 || MIPS_PB1100 || MIPS_PB1000
>> 594 default n
1256 595
1257 config QCOM_QDF2400_ERRATUM_0065 !! 596 config COBALT_LCD
1258 bool "QDF2400 E0065: Incorrect GITS_T !! 597 bool
>> 598 depends on MIPS_COBALT
1259 default y 599 default y
1260 help <<
1261 On Qualcomm Datacenter Technologies <<
1262 ITE size incorrectly. The GITS_TYPE <<
1263 been indicated as 16Bytes (0xf), no <<
1264 600
1265 If unsure, say Y. !! 601 config MIPS_GT64120
>> 602 bool
>> 603 depends on MIPS_EV64120
>> 604 default y
1266 605
1267 config QCOM_FALKOR_ERRATUM_E1041 !! 606 config MIPS_GT96100
1268 bool "Falkor E1041: Speculative instr !! 607 bool
>> 608 depends on MIPS_EV96100
1269 default y 609 default y
1270 help 610 help
1271 Falkor CPU may speculatively fetch !! 611 Say Y here to support the Galileo Technology GT96100 communications
1272 memory location when MMU translatio !! 612 controller card. There is a web page at <http://www.galileot.com/>.
1273 to SCTLR_ELn[M]=0. Prefix an ISB in <<
1274 <<
1275 If unsure, say Y. <<
1276 613
1277 config NVIDIA_CARMEL_CNP_ERRATUM !! 614 config IT8172_CIR
1278 bool "NVIDIA Carmel CNP: CNP on Carme !! 615 bool
>> 616 depends on MIPS_ITE8172 || MIPS_IVR
1279 default y 617 default y
1280 help <<
1281 If CNP is enabled on Carmel cores, <<
1282 invalidate shared TLB entries insta <<
1283 on standard ARM cores. <<
1284 618
1285 If unsure, say Y. !! 619 config IT8712
>> 620 bool
>> 621 depends on MIPS_ITE8172
>> 622 default y
1286 623
1287 config ROCKCHIP_ERRATUM_3588001 !! 624 config BOOT_ELF32
1288 bool "Rockchip 3588001: GIC600 can no !! 625 bool
>> 626 depends on DECSTATION || MIPS_ATLAS || MIPS_MALTA || SIBYTE_SB1250 || SGI_IP32 || SGI_IP22 || SNI_RM200_PCI
1289 default y 627 default y
1290 help <<
1291 The Rockchip RK3588 GIC600 SoC inte <<
1292 This means, that its sharability fe <<
1293 is supported by the IP itself. <<
1294 628
1295 If unsure, say Y. !! 629 config L1_CACHE_SHIFT
>> 630 int
>> 631 default "4" if DECSTATION
>> 632 default "5" if SGI_IP32 || SGI_IP22 || MIPS_SEAD || MIPS_MALTA || MIPS_ATLAS
>> 633 default "7" if SGI_IP27
1296 634
1297 config SOCIONEXT_SYNQUACER_PREITS !! 635 config ARC32
1298 bool "Socionext Synquacer: Workaround !! 636 bool
>> 637 depends on SNI_RM200_PCI || SGI_IP32 || SGI_IP22 || MIPS_MAGNUM_4000 || OLIVETTI_M700
1299 default y 638 default y
1300 help <<
1301 Socionext Synquacer SoCs implement <<
1302 MSI doorbell writes with non-zero v <<
1303 639
1304 If unsure, say Y. !! 640 config FB
>> 641 bool
>> 642 depends on MIPS_MAGNUM_4000 || OLIVETTI_M700
>> 643 default y
>> 644 ---help---
>> 645 The frame buffer device provides an abstraction for the graphics
>> 646 hardware. It represents the frame buffer of some video hardware and
>> 647 allows application software to access the graphics hardware through
>> 648 a well-defined interface, so the software doesn't need to know
>> 649 anything about the low-level (hardware register) stuff.
>> 650
>> 651 Frame buffer devices work identically across the different
>> 652 architectures supported by Linux and make the implementation of
>> 653 application programs easier and more portable; at this point, an X
>> 654 server exists which uses the frame buffer device exclusively.
>> 655 On several non-X86 architectures, the frame buffer device is the
>> 656 only way to use the graphics hardware.
>> 657
>> 658 The device is accessed through special device nodes, usually located
>> 659 in the /dev directory, i.e. /dev/fb*.
>> 660
>> 661 You need an utility program called fbset to make full use of frame
>> 662 buffer devices. Please read <file:Documentation/fb/framebuffer.txt>
>> 663 and the Framebuffer-HOWTO at
>> 664 <http://www.tahallah.demon.co.uk/programming/prog.html> for more
>> 665 information.
>> 666
>> 667 Say Y here and to the driver for your graphics board below if you
>> 668 are compiling a kernel for a non-x86 architecture.
>> 669
>> 670 If you are compiling for the x86 architecture, you can say Y if you
>> 671 want to play with it, but it is not essential. Please note that
>> 672 running graphical applications that directly touch the hardware
>> 673 (e.g. an accelerated X server) and that are not frame buffer
>> 674 device-aware may cause unexpected results. If unsure, say N.
1305 675
1306 endmenu # "ARM errata workarounds via the alt !! 676 config FB_G364
>> 677 bool
>> 678 depends on MIPS_MAGNUM_4000 || OLIVETTI_M700
>> 679 default y
1307 680
1308 choice !! 681 config HAVE_STD_PC_SERIAL_PORT
1309 prompt "Page size" !! 682 bool
1310 default ARM64_4K_PAGES !! 683 depends on DDB5476 || DDB5074 || MIPS_MALTA
1311 help !! 684 default y
1312 Page size (translation granule) con <<
1313 685
1314 config ARM64_4K_PAGES !! 686 config VR4181
1315 bool "4KB" !! 687 bool
1316 select HAVE_PAGE_SIZE_4KB !! 688 depends on NEC_OSPREY
1317 help !! 689 default y
1318 This feature enables 4KB pages supp <<
1319 690
1320 config ARM64_16K_PAGES !! 691 config ARC_CONSOLE
1321 bool "16KB" !! 692 bool "ARC console support"
1322 select HAVE_PAGE_SIZE_16KB !! 693 depends on SGI_IP22 || SNI_RM200_PCI
1323 help <<
1324 The system will use 16KB pages supp <<
1325 requires applications compiled with <<
1326 aligned segments. <<
1327 694
1328 config ARM64_64K_PAGES !! 695 config ARC_MEMORY
1329 bool "64KB" !! 696 bool
1330 select HAVE_PAGE_SIZE_64KB !! 697 depends on SNI_RM200_PCI || SGI_IP32
1331 help !! 698 default y
1332 This feature enables 64KB pages sup <<
1333 allowing only two levels of page ta <<
1334 look-up. AArch32 emulation requires <<
1335 with 64K aligned segments. <<
1336 699
1337 endchoice !! 700 config ARC_PROMLIB
>> 701 bool
>> 702 depends on SNI_RM200_PCI || SGI_IP32 || SGI_IP22
>> 703 default y
1338 704
1339 choice !! 705 config BOARD_SCACHE
1340 prompt "Virtual address space size" !! 706 bool
1341 default ARM64_VA_BITS_52 !! 707 depends on MIPS_EV96100 || MOMENCO_OCELOT || SGI_IP22
1342 help !! 708 default y
1343 Allows choosing one of multiple pos <<
1344 space sizes. The level of translati <<
1345 a combination of page size and virt <<
1346 <<
1347 config ARM64_VA_BITS_36 <<
1348 bool "36-bit" if EXPERT <<
1349 depends on PAGE_SIZE_16KB <<
1350 <<
1351 config ARM64_VA_BITS_39 <<
1352 bool "39-bit" <<
1353 depends on PAGE_SIZE_4KB <<
1354 <<
1355 config ARM64_VA_BITS_42 <<
1356 bool "42-bit" <<
1357 depends on PAGE_SIZE_64KB <<
1358 <<
1359 config ARM64_VA_BITS_47 <<
1360 bool "47-bit" <<
1361 depends on PAGE_SIZE_16KB <<
1362 <<
1363 config ARM64_VA_BITS_48 <<
1364 bool "48-bit" <<
1365 <<
1366 config ARM64_VA_BITS_52 <<
1367 bool "52-bit" <<
1368 depends on ARM64_PAN || !ARM64_SW_TTB <<
1369 help <<
1370 Enable 52-bit virtual addressing fo <<
1371 requested via a hint to mmap(). The <<
1372 virtual addresses for its own mappi <<
1373 this feature is available, otherwis <<
1374 <<
1375 NOTE: Enabling 52-bit virtual addre <<
1376 ARMv8.3 Pointer Authentication will <<
1377 reduced from 7 bits to 3 bits, whic <<
1378 impact on its susceptibility to bru <<
1379 709
1380 If unsure, select 48-bit virtual ad !! 710 config ARC64
>> 711 bool
>> 712 depends on SGI_IP27
>> 713 default y
1381 714
1382 endchoice !! 715 config BOOT_ELF64
>> 716 bool
>> 717 depends on SGI_IP27
>> 718 default y
1383 719
1384 config ARM64_FORCE_52BIT !! 720 #config MAPPED_PCI_IO y
1385 bool "Force 52-bit virtual addresses !! 721 # bool
1386 depends on ARM64_VA_BITS_52 && EXPERT !! 722 # depends on SGI_IP27
1387 help !! 723 # default y
1388 For systems with 52-bit userspace V <<
1389 to maintain compatibility with olde <<
1390 unless a hint is supplied to mmap. <<
1391 <<
1392 This configuration option disables <<
1393 forces all userspace addresses to b <<
1394 should only enable this configurati <<
1395 memory management code. If unsure s <<
1396 724
1397 config ARM64_VA_BITS !! 725 config QL_ISP_A64
1398 int !! 726 bool
1399 default 36 if ARM64_VA_BITS_36 !! 727 depends on SGI_IP27
1400 default 39 if ARM64_VA_BITS_39 !! 728 default y
1401 default 42 if ARM64_VA_BITS_42 <<
1402 default 47 if ARM64_VA_BITS_47 <<
1403 default 48 if ARM64_VA_BITS_48 <<
1404 default 52 if ARM64_VA_BITS_52 <<
1405 729
1406 choice !! 730 config TOSHIBA_BOARDS
1407 prompt "Physical address space size" !! 731 bool
1408 default ARM64_PA_BITS_48 !! 732 depends on TOSHIBA_JMR3927 || TOSHIBA_RBTX4927
1409 help !! 733 default y
1410 Choose the maximum physical address <<
1411 support. <<
1412 734
1413 config ARM64_PA_BITS_48 !! 735 config TANBAC_TB0219
1414 bool "48-bit" !! 736 bool "Added TANBAC TB0219 Base board support"
1415 depends on ARM64_64K_PAGES || !ARM64_ !! 737 depends on TANBAC_TB0229
1416 <<
1417 config ARM64_PA_BITS_52 <<
1418 bool "52-bit" <<
1419 depends on ARM64_64K_PAGES || ARM64_V <<
1420 depends on ARM64_PAN || !ARM64_SW_TTB <<
1421 help <<
1422 Enable support for a 52-bit physica <<
1423 part of the ARMv8.2-LPA extension. <<
1424 <<
1425 With this enabled, the kernel will <<
1426 do not support ARMv8.2-LPA, but wit <<
1427 minor performance overhead). <<
1428 738
1429 endchoice !! 739 endmenu
1430 740
1431 config ARM64_PA_BITS <<
1432 int <<
1433 default 48 if ARM64_PA_BITS_48 <<
1434 default 52 if ARM64_PA_BITS_52 <<
1435 741
1436 config ARM64_LPA2 !! 742 menu "CPU selection"
1437 def_bool y <<
1438 depends on ARM64_PA_BITS_52 && !ARM64 <<
1439 743
1440 choice 744 choice
1441 prompt "Endianness" !! 745 prompt "CPU type"
1442 default CPU_LITTLE_ENDIAN !! 746 default CPU_R4X00
1443 help <<
1444 Select the endianness of data acces <<
1445 applications will need to be compil <<
1446 that is selected here. <<
1447 <<
1448 config CPU_BIG_ENDIAN <<
1449 bool "Build big-endian kernel" <<
1450 # https://github.com/llvm/llvm-projec <<
1451 depends on AS_IS_GNU || AS_VERSION >= <<
1452 help <<
1453 Say Y if you plan on running a kern <<
1454 747
1455 config CPU_LITTLE_ENDIAN !! 748 config CPU_MIPS32
1456 bool "Build little-endian kernel" !! 749 bool "MIPS32"
1457 help <<
1458 Say Y if you plan on running a kern <<
1459 This is usually the case for distri <<
1460 750
1461 endchoice !! 751 config CPU_MIPS64
>> 752 bool "MIPS64"
1462 753
1463 config SCHED_MC !! 754 config CPU_R3000
1464 bool "Multi-core scheduler support" !! 755 bool "R3000"
>> 756 depends on MIPS32
1465 help 757 help
1466 Multi-core scheduler support improv !! 758 Please make sure to pick the right CPU type. Linux/MIPS is not
1467 making when dealing with multi-core !! 759 designed to be generic, i.e. Kernels compiled for R3000 CPUs will
1468 increased overhead in some places. !! 760 *not* work on R4000 machines and vice versa. However, since most
1469 !! 761 of the supported machines have an R4000 (or similar) CPU, R4x00
1470 config SCHED_CLUSTER !! 762 might be a safe bet. If the resulting kernel does not work,
1471 bool "Cluster scheduler support" !! 763 try to recompile with R3000.
1472 help <<
1473 Cluster scheduler support improves <<
1474 making when dealing with machines t <<
1475 Cluster usually means a couple of C <<
1476 by sharing mid-level caches, last-l <<
1477 busses. <<
1478 <<
1479 config SCHED_SMT <<
1480 bool "SMT scheduler support" <<
1481 help <<
1482 Improves the CPU scheduler's decisi <<
1483 MultiThreading at a cost of slightl <<
1484 places. If unsure say N here. <<
1485 764
1486 config NR_CPUS !! 765 config CPU_TX39XX
1487 int "Maximum number of CPUs (2-4096)" !! 766 bool "R39XX"
1488 range 2 4096 !! 767 depends on MIPS32
1489 default "512" <<
1490 <<
1491 config HOTPLUG_CPU <<
1492 bool "Support for hot-pluggable CPUs" <<
1493 select GENERIC_IRQ_MIGRATION <<
1494 help <<
1495 Say Y here to experiment with turni <<
1496 can be controlled through /sys/devi <<
1497 768
1498 # Common NUMA Features !! 769 config CPU_VR41XX
1499 config NUMA !! 770 bool "R41xx"
1500 bool "NUMA Memory Allocation and Sche <<
1501 select GENERIC_ARCH_NUMA <<
1502 select OF_NUMA <<
1503 select HAVE_SETUP_PER_CPU_AREA <<
1504 select NEED_PER_CPU_EMBED_FIRST_CHUNK <<
1505 select NEED_PER_CPU_PAGE_FIRST_CHUNK <<
1506 select USE_PERCPU_NUMA_NODE_ID <<
1507 help 771 help
1508 Enable NUMA (Non-Uniform Memory Acc !! 772 The options selects support for the NEC VR41xx series of processors.
1509 !! 773 Only choose this option if you have one of these processors as a
1510 The kernel will try to allocate mem !! 774 kernel built with this option will not run on any other type of
1511 local memory of the CPU and add som !! 775 processor or vice versa.
1512 NUMA awareness to the kernel. <<
1513 776
1514 config NODES_SHIFT !! 777 config CPU_R4300
1515 int "Maximum NUMA Nodes (as a power o !! 778 bool "R4300"
1516 range 1 10 <<
1517 default "4" <<
1518 depends on NUMA <<
1519 help 779 help
1520 Specify the maximum number of NUMA !! 780 MIPS Technologies R4300-series processors.
1521 system. Increases memory reserved <<
1522 781
1523 source "kernel/Kconfig.hz" !! 782 config CPU_R4X00
1524 !! 783 bool "R4x00"
1525 config ARCH_SPARSEMEM_ENABLE <<
1526 def_bool y <<
1527 select SPARSEMEM_VMEMMAP_ENABLE <<
1528 select SPARSEMEM_VMEMMAP <<
1529 <<
1530 config HW_PERF_EVENTS <<
1531 def_bool y <<
1532 depends on ARM_PMU <<
1533 <<
1534 # Supported by clang >= 7.0 or GCC >= 12.0.0 <<
1535 config CC_HAVE_SHADOW_CALL_STACK <<
1536 def_bool $(cc-option, -fsanitize=shad <<
1537 <<
1538 config PARAVIRT <<
1539 bool "Enable paravirtualization code" <<
1540 help 784 help
1541 This changes the kernel so it can m !! 785 MIPS Technologies R4000-series processors other than 4300, including
1542 under a hypervisor, potentially imp !! 786 the R4000, R4400, R4600, and 4700.
1543 over full virtualization. <<
1544 <<
1545 config PARAVIRT_TIME_ACCOUNTING <<
1546 bool "Paravirtual steal time accounti <<
1547 select PARAVIRT <<
1548 help <<
1549 Select this option to enable fine g <<
1550 accounting. Time spent executing ot <<
1551 the current vCPU is discounted from <<
1552 that, there can be a small performa <<
1553 <<
1554 If in doubt, say N here. <<
1555 <<
1556 config ARCH_SUPPORTS_KEXEC <<
1557 def_bool PM_SLEEP_SMP <<
1558 <<
1559 config ARCH_SUPPORTS_KEXEC_FILE <<
1560 def_bool y <<
1561 <<
1562 config ARCH_SELECTS_KEXEC_FILE <<
1563 def_bool y <<
1564 depends on KEXEC_FILE <<
1565 select HAVE_IMA_KEXEC if IMA <<
1566 <<
1567 config ARCH_SUPPORTS_KEXEC_SIG <<
1568 def_bool y <<
1569 <<
1570 config ARCH_SUPPORTS_KEXEC_IMAGE_VERIFY_SIG <<
1571 def_bool y <<
1572 <<
1573 config ARCH_DEFAULT_KEXEC_IMAGE_VERIFY_SIG <<
1574 def_bool y <<
1575 787
1576 config ARCH_SUPPORTS_CRASH_DUMP !! 788 config CPU_TX49XX
1577 def_bool y !! 789 bool "R49XX"
1578 790
1579 config ARCH_HAS_GENERIC_CRASHKERNEL_RESERVATI !! 791 config CPU_R5000
1580 def_bool CRASH_RESERVE !! 792 bool "R5000"
1581 <<
1582 config TRANS_TABLE <<
1583 def_bool y <<
1584 depends on HIBERNATION || KEXEC_CORE <<
1585 <<
1586 config XEN_DOM0 <<
1587 def_bool y <<
1588 depends on XEN <<
1589 <<
1590 config XEN <<
1591 bool "Xen guest support on ARM64" <<
1592 depends on ARM64 && OF <<
1593 select SWIOTLB_XEN <<
1594 select PARAVIRT <<
1595 help 793 help
1596 Say Y if you want to run Linux in a !! 794 MIPS Technologies R5000-series processors other than the Nevada.
1597 795
1598 # include/linux/mmzone.h requires the followi !! 796 config CPU_R5432
1599 # !! 797 bool "R5432"
1600 # MAX_PAGE_ORDER + PAGE_SHIFT <= SECTION_SI <<
1601 # <<
1602 # so the maximum value of MAX_PAGE_ORDER is S <<
1603 # <<
1604 # | SECTION_SIZE_BITS | PAGE_SHIFT | m <<
1605 # ----+-------------------+--------------+--- <<
1606 # 4K | 27 | 12 | <<
1607 # 16K | 27 | 14 | <<
1608 # 64K | 29 | 16 | <<
1609 config ARCH_FORCE_MAX_ORDER <<
1610 int <<
1611 default "13" if ARM64_64K_PAGES <<
1612 default "11" if ARM64_16K_PAGES <<
1613 default "10" <<
1614 help <<
1615 The kernel page allocator limits th <<
1616 contiguous allocations. The limit i <<
1617 defines the maximal power of two of <<
1618 allocated as a single contiguous bl <<
1619 overriding the default setting when <<
1620 large blocks of physically contiguo <<
1621 <<
1622 The maximal size of allocation cann <<
1623 section, so the value of MAX_PAGE_O <<
1624 <<
1625 MAX_PAGE_ORDER + PAGE_SHIFT <= SE <<
1626 798
1627 Don't change if unsure. !! 799 config CPU_R6000
1628 !! 800 bool "R6000"
1629 config UNMAP_KERNEL_AT_EL0 !! 801 depends on MIPS32 && EXPERIMENTAL
1630 bool "Unmap kernel when running in us <<
1631 default y <<
1632 help 802 help
1633 Speculation attacks against some hi !! 803 MIPS Technologies R6000 and R6000A series processors. Note these
1634 be used to bypass MMU permission ch !! 804 processors are extremly rare and the support for them is incomplete.
1635 userspace. This can be defended aga <<
1636 when running in userspace, mapping <<
1637 via a trampoline page in the vector <<
1638 <<
1639 If unsure, say Y. <<
1640 805
1641 config MITIGATE_SPECTRE_BRANCH_HISTORY !! 806 config CPU_NEVADA
1642 bool "Mitigate Spectre style attacks !! 807 bool "R52xx"
1643 default y <<
1644 help 808 help
1645 Speculation attacks against some hi !! 809 MIPS Technologies R52x0-series ("Nevada") processors.
1646 make use of branch history to influ <<
1647 When taking an exception from user- <<
1648 or a firmware call overwrites the b <<
1649 810
1650 config RODATA_FULL_DEFAULT_ENABLED !! 811 config CPU_R8000
1651 bool "Apply r/o permissions of VM are !! 812 bool "R8000"
1652 default y !! 813 depends on MIPS64 && EXPERIMENTAL
1653 help 814 help
1654 Apply read-only attributes of VM ar !! 815 MIPS Technologies R8000 processors. Note these processors are
1655 the backing pages as well. This pre !! 816 uncommon and the support for them is incomplete.
1656 from being modified (inadvertently <<
1657 mapping of the same memory page. Th <<
1658 be turned off at runtime by passing <<
1659 with rodata=full if this option is <<
1660 <<
1661 This requires the linear region to <<
1662 which may adversely affect performa <<
1663 817
1664 config ARM64_SW_TTBR0_PAN !! 818 config CPU_R10000
1665 bool "Emulate Privileged Access Never !! 819 bool "R10000"
1666 depends on !KCSAN <<
1667 help 820 help
1668 Enabling this option prevents the k !! 821 MIPS Technologies R10000-series processors.
1669 user-space memory directly by point <<
1670 zeroed area and reserved ASID. The <<
1671 restore the valid TTBR0_EL1 tempora <<
1672 822
1673 config ARM64_TAGGED_ADDR_ABI !! 823 config CPU_RM7000
1674 bool "Enable the tagged user addresse !! 824 bool "RM7000"
1675 default y <<
1676 help <<
1677 When this option is enabled, user a <<
1678 relaxed ABI via prctl() allowing ta <<
1679 to system calls as pointer argument <<
1680 Documentation/arch/arm64/tagged-add <<
1681 825
1682 menuconfig COMPAT !! 826 config CPU_SB1
1683 bool "Kernel support for 32-bit EL0" !! 827 bool "SB1"
1684 depends on ARM64_4K_PAGES || EXPERT <<
1685 select HAVE_UID16 <<
1686 select OLD_SIGSUSPEND3 <<
1687 select COMPAT_OLD_SIGACTION <<
1688 help <<
1689 This option enables support for a 3 <<
1690 kernel at EL1. AArch32-specific com <<
1691 the user helper functions, VFP supp <<
1692 handled appropriately by the kernel <<
1693 828
1694 If you use a page size other than 4 !! 829 endchoice
1695 that you will only be able to execu <<
1696 with page size aligned segments. <<
1697 830
1698 If you want to execute 32-bit users !! 831 config R5000_CPU_SCACHE
>> 832 bool
>> 833 depends on CPU_NEVADA || CPU_R5000
>> 834 default y if SGI_IP22 || SGI_IP32 || LASAT
1699 835
1700 if COMPAT !! 836 config BOARD_SCACHE
>> 837 bool
>> 838 depends on CPU_NEVADA || CPU_R4X00 || CPU_R5000
>> 839 default y if SGI_IP22 || (SGI_IP32 && CPU_R5000) || R5000_CPU_SCACHE
1701 840
1702 config KUSER_HELPERS !! 841 config SIBYTE_DMA_PAGEOPS
1703 bool "Enable kuser helpers page for 3 !! 842 bool "Use DMA to clear/copy pages"
1704 default y !! 843 depends on CPU_SB1
1705 help !! 844 help
1706 Warning: disabling this option may !! 845 Instead of using the CPU to zero and copy pages, use a Data Mover
>> 846 channel. These DMA channels are otherwise unused by the standard
>> 847 SiByte Linux port. Seems to give a small performance benefit.
>> 848
>> 849 config CPU_HAS_PREFETCH
>> 850 bool "Enable prefetches" if CPU_SB1 && !CPU_SB1_PASS_2
>> 851 default y if CPU_RM7000 || CPU_MIPS64 || CPU_MIPS32
>> 852
>> 853 config VTAG_ICACHE
>> 854 bool "Support for Virtual Tagged I-cache" if CPU_MIPS64 || CPU_MIPS32
>> 855 default y if CPU_SB1
1707 856
1708 Provide kuser helpers to compat tas !! 857 choice
1709 helper code to userspace in read on !! 858 prompt "SB1 Pass"
1710 to allow userspace to be independen !! 859 depends on CPU_SB1
1711 the system. This permits binaries t !! 860 default CPU_SB1_PASS_1
1712 to ARMv8 without modification. <<
1713 861
1714 See Documentation/arch/arm/kernel_u !! 862 config CPU_SB1_PASS_1
>> 863 bool "Pass1"
1715 864
1716 However, the fixed address nature o !! 865 config CPU_SB1_PASS_2
1717 by ROP (return orientated programmi !! 866 bool "Pass2"
1718 exploits. <<
1719 867
1720 If all of the binaries and librarie !! 868 config CPU_SB1_PASS_2_2
1721 are built specifically for your pla !! 869 bool "Pass2.2"
1722 these helpers, then you can turn th <<
1723 such exploits. However, in that cas <<
1724 relying on those helpers is run, it <<
1725 870
1726 Say N here only if you are absolute !! 871 endchoice
1727 need these helpers; otherwise, the <<
1728 872
1729 config COMPAT_VDSO !! 873 config SB1_PASS_1_WORKAROUNDS
1730 bool "Enable vDSO for 32-bit applicat !! 874 bool
1731 depends on !CPU_BIG_ENDIAN !! 875 depends on CPU_SB1_PASS_1
1732 depends on (CC_IS_CLANG && LD_IS_LLD) <<
1733 select GENERIC_COMPAT_VDSO <<
1734 default y 876 default y
1735 help <<
1736 Place in the process address space <<
1737 ELF shared object providing fast im <<
1738 and clock_gettime. <<
1739 <<
1740 You must have a 32-bit build of gli <<
1741 to seamlessly take advantage of thi <<
1742 877
1743 config THUMB2_COMPAT_VDSO !! 878 config SB1_PASS_2_WORKAROUNDS
1744 bool "Compile the 32-bit vDSO for Thu !! 879 bool
1745 depends on COMPAT_VDSO !! 880 depends on CPU_SB1 && (CPU_SB1_PASS_2_2 || CPU_SB1_PASS_2)
1746 default y 881 default y
1747 help <<
1748 Compile the compat vDSO with '-mthu <<
1749 otherwise with '-marm'. <<
1750 <<
1751 config COMPAT_ALIGNMENT_FIXUPS <<
1752 bool "Fix up misaligned multi-word lo <<
1753 882
1754 menuconfig ARMV8_DEPRECATED !! 883 # Avoid prefetches on Pass 2 (before 2.2)
1755 bool "Emulate deprecated/obsolete ARM !! 884 # XXXKW for now, let 2.2 use same WORKAROUNDS flag as pre-2.2
1756 depends on SYSCTL !! 885 config SB1_CACHE_ERROR
1757 help !! 886 bool "Support for SB1 Cache Error handler"
1758 Legacy software support may require !! 887 depends on CPU_SB1
1759 that have been deprecated or obsole <<
1760 888
1761 Enable this config to enable select !! 889 config SB1_CERR_IGNORE_RECOVERABLE
1762 features. !! 890 bool "Ignore recoverable cache errors"
>> 891 depends on SB1_CACHE_ERROR
1763 892
1764 If unsure, say Y !! 893 config SB1_CERR_SPIN
>> 894 bool "Spin instead of running handler"
>> 895 depends on SB1_CACHE_ERROR
1765 896
1766 if ARMV8_DEPRECATED !! 897 config 64BIT_PHYS_ADDR
>> 898 bool "Support for 64-bit physical address space"
>> 899 depends on (CPU_R4X00 || CPU_R5000 || CPU_RM7000 || CPU_R10000 || CPU_SB1 || CPU_MIPS32 || CPU_MIPS64) && MIPS32
1767 900
1768 config SWP_EMULATION !! 901 config CPU_ADVANCED
1769 bool "Emulate SWP/SWPB instructions" !! 902 bool "Override CPU Options"
>> 903 depends on MIPS32
1770 help 904 help
1771 ARMv8 obsoletes the use of A32 SWP/ !! 905 Saying yes here allows you to select support for various features
1772 they are always undefined. Say Y he !! 906 your CPU may or may not have. Most people should say N here.
1773 emulation of these instructions for <<
1774 This feature can be controlled at r <<
1775 sysctl which is disabled by default <<
1776 <<
1777 In some older versions of glibc [<= <<
1778 trylock() operations with the assum <<
1779 be preempted. This invalid assumpti <<
1780 with SWP emulation enabled, leading <<
1781 application. <<
1782 <<
1783 NOTE: when accessing uncached share <<
1784 on an external transaction monitori <<
1785 monitor to maintain update atomicit <<
1786 implement a global monitor, this op <<
1787 perform SWP operations to uncached <<
1788 <<
1789 If unsure, say Y <<
1790 907
1791 config CP15_BARRIER_EMULATION !! 908 config CPU_HAS_LLSC
1792 bool "Emulate CP15 Barrier instructio !! 909 bool "ll/sc Instructions available" if CPU_ADVANCED
>> 910 default y if !CPU_ADVANCED && !CPU_R3000 && !CPU_VR41XX && !CPU_TX39XX
1793 help 911 help
1794 The CP15 barrier instructions - CP1 !! 912 MIPS R4000 series and later provide the Load Linked (ll)
1795 CP15DMB - are deprecated in ARMv8 ( !! 913 and Store Conditional (sc) instructions. More information is
1796 strongly recommended to use the ISB !! 914 available at <http://www.go-ecs.com/mips/miptek1.htm>.
1797 instructions instead. <<
1798 915
1799 Say Y here to enable software emula !! 916 Say Y here if your CPU has the ll and sc instructions. Say Y here
1800 instructions for AArch32 userspace !! 917 for better performance, N if you don't know. You must say Y here
1801 enabled, CP15 barrier usage is trac !! 918 for multiprocessor machines.
1802 identify software that needs updati <<
1803 controlled at runtime with the abi. <<
1804 919
1805 If unsure, say Y !! 920 config CPU_HAS_LLDSCD
1806 !! 921 bool "lld/scd Instructions available" if CPU_ADVANCED
1807 config SETEND_EMULATION !! 922 default y if !CPU_ADVANCED && !CPU_R3000 && !CPU_VR41XX && !CPU_TX39XX && !CPU_MIPS32
1808 bool "Emulate SETEND instruction" <<
1809 help 923 help
1810 The SETEND instruction alters the d !! 924 Say Y here if your CPU has the lld and scd instructions, the 64-bit
1811 AArch32 EL0, and is deprecated in A !! 925 equivalents of ll and sc. Say Y here for better performance, N if
1812 !! 926 you don't know. You must say Y here for multiprocessor machines.
1813 Say Y here to enable software emula <<
1814 for AArch32 userspace code. This fe <<
1815 at runtime with the abi.setend sysc <<
1816 <<
1817 Note: All the cpus on the system mu <<
1818 for this feature to be enabled. If <<
1819 endian - is hotplugged in after thi <<
1820 be unexpected results in the applic <<
1821 927
1822 If unsure, say Y !! 928 config CPU_HAS_WB
1823 endif # ARMV8_DEPRECATED !! 929 bool "Writeback Buffer available" if CPU_ADVANCED
1824 !! 930 default y if !CPU_ADVANCED && (CPU_R3000 || CPU_VR41XX || CPU_TX39XX) && DECSTATION
1825 endif # COMPAT <<
1826 <<
1827 menu "ARMv8.1 architectural features" <<
1828 <<
1829 config ARM64_HW_AFDBM <<
1830 bool "Support for hardware updates of <<
1831 default y <<
1832 help 931 help
1833 The ARMv8.1 architecture extensions !! 932 Say N here for slightly better performance. You must say Y here for
1834 hardware updates of the access and !! 933 machines which require flushing of write buffers in software. Saying
1835 table entries. When enabled in TCR_ !! 934 Y is the safe option; N may result in kernel malfunction and crashes.
1836 capable processors, accesses to pag <<
1837 set this bit instead of raising an <<
1838 Similarly, writes to read-only page <<
1839 clear the read-only bit (AP[2]) ins <<
1840 permission fault. <<
1841 935
1842 Kernels built with this configurati !! 936 config CPU_HAS_SYNC
1843 to work on pre-ARMv8.1 hardware and <<
1844 minimal. If unsure, say Y. <<
1845 <<
1846 config ARM64_PAN <<
1847 bool "Enable support for Privileged A <<
1848 default y <<
1849 help <<
1850 Privileged Access Never (PAN; part <<
1851 prevents the kernel or hypervisor f <<
1852 memory directly. <<
1853 <<
1854 Choosing this option will cause any <<
1855 copy_to_user et al) memory access t <<
1856 <<
1857 The feature is detected at runtime, <<
1858 instruction if the cpu does not imp <<
1859 <<
1860 config AS_HAS_LSE_ATOMICS <<
1861 def_bool $(as-instr,.arch_extension l <<
1862 <<
1863 config ARM64_LSE_ATOMICS <<
1864 bool 937 bool
1865 default ARM64_USE_LSE_ATOMICS !! 938 depends on !CPU_R3000
1866 depends on AS_HAS_LSE_ATOMICS <<
1867 <<
1868 config ARM64_USE_LSE_ATOMICS <<
1869 bool "Atomic instructions" <<
1870 default y 939 default y
1871 help <<
1872 As part of the Large System Extensi <<
1873 atomic instructions that are design <<
1874 very large systems. <<
1875 940
1876 Say Y here to make use of these ins !! 941 #
1877 atomic routines. This incurs a smal !! 942 # - Highmem only makes sense for the 32-bit kernel.
1878 not support these instructions and !! 943 # - The current highmem code will only work properly on physically indexed
1879 built with binutils >= 2.25 in orde !! 944 # caches such as R3000, SB1, R7000 or those that look like they're virtually
1880 to be used. !! 945 # indexed such as R4000/R4400 SC and MC versions or R10000. So for the
1881 !! 946 # moment we protect the user and offer the highmem option only on machines
1882 endmenu # "ARMv8.1 architectural features" !! 947 # where it's known to be safe. This will not offer highmem on a few systems
1883 !! 948 # such as MIPS32 and MIPS64 CPUs which may have virtual and physically
1884 menu "ARMv8.2 architectural features" !! 949 # indexed CPUs but we're playing safe.
1885 !! 950 # - We should not offer highmem for system of which we already know that they
1886 config AS_HAS_ARMV8_2 !! 951 # don't have memory configurations that could gain from highmem support in
1887 def_bool $(cc-option,-Wa$(comma)-marc !! 952 # the kernel because they don't support configurations with RAM at physical
>> 953 # addresses > 0x20000000.
>> 954 #
>> 955 config HIGHMEM
>> 956 bool "High Memory Support"
>> 957 depends on MIPS32 && (CPU_R3000 || CPU_SB1 || CPU_R7000 || CPU_R10000) && !(BAGET_MIPS || DECSTATION)
1888 958
1889 config AS_HAS_SHA3 !! 959 config SMP
1890 def_bool $(as-instr,.arch armv8.2-a+s !! 960 bool "Multi-Processing support"
>> 961 depends on SIBYTE_SB1xxx_SOC && SIBYTE_SB1250 && !SIBYTE_STANDALONE || SGI_IP27
>> 962 ---help---
>> 963 This enables support for systems with more than one CPU. If you have
>> 964 a system with only one CPU, like most personal computers, say N. If
>> 965 you have a system with more than one CPU, say Y.
>> 966
>> 967 If you say N here, the kernel will run on single and multiprocessor
>> 968 machines, but will use only one CPU of a multiprocessor machine. If
>> 969 you say Y here, the kernel will run on many, but not all,
>> 970 singleprocessor machines. On a singleprocessor machine, the kernel
>> 971 will run faster if you say N here.
>> 972
>> 973 People using multiprocessor machines who say Y here should also say
>> 974 Y to "Enhanced Real Time Clock Support", below.
>> 975
>> 976 See also the <file:Documentation/smp.tex>,
>> 977 <file:Documentation/smp.txt> and the SMP-HOWTO available at
>> 978 <http://www.tldp.org/docs.html#howto>.
1891 979
1892 config ARM64_PMEM !! 980 If you don't know what to do here, say N.
1893 bool "Enable support for persistent m <<
1894 select ARCH_HAS_PMEM_API <<
1895 select ARCH_HAS_UACCESS_FLUSHCACHE <<
1896 help <<
1897 Say Y to enable support for the per <<
1898 ARMv8.2 DCPoP feature. <<
1899 981
1900 The feature is detected at runtime, !! 982 config NR_CPUS
1901 operations if DC CVAP is not suppor !! 983 int "Maximum number of CPUs (2-32)"
1902 DC CVAP itself if the system does n !! 984 depends on SMP
>> 985 default "32"
>> 986 help
>> 987 This allows you to specify the maximum number of CPUs which this
>> 988 kernel will support. The maximum supported value is 32 and the
>> 989 minimum value which makes sense is 2.
>> 990
>> 991 This is purely to save memory - each supported CPU adds
>> 992 approximately eight kilobytes to the kernel image.
>> 993
>> 994 config PREEMPT
>> 995 bool "Preemptible Kernel"
>> 996 help
>> 997 This option reduces the latency of the kernel when reacting to
>> 998 real-time or interactive events by allowing a low priority process to
>> 999 be preempted even if it is in kernel mode executing a system call.
>> 1000 This allows applications to run more reliably even when the system is
>> 1001 under load.
>> 1002
>> 1003 config DEBUG_SPINLOCK_SLEEP
>> 1004 bool "Sleep-inside-spinlock checking"
>> 1005 help
>> 1006 If you say Y here, various routines which may sleep will become very
>> 1007 noisy if they are called with a spinlock held.
>> 1008
>> 1009 config RTC_DS1742
>> 1010 bool "DS1742 BRAM/RTC support"
>> 1011 depends on TOSHIBA_JMR3927 || TOSHIBA_RBTX4927
>> 1012
>> 1013 config MIPS_INSANE_LARGE
>> 1014 bool "Support for large 64-bit configurations"
>> 1015 depends on CPU_R10000 && MIPS64
>> 1016 help
>> 1017 MIPS R10000 does support a 44 bit / 16TB address space as opposed to
>> 1018 previous 64-bit processors which only supported 40 bit / 1TB. If you
>> 1019 need processes of more than 1TB virtual address space, say Y here.
>> 1020 This will result in additional memory usage, so it is not
>> 1021 recommended for normal users.
1903 1022
1904 config ARM64_RAS_EXTN !! 1023 config RWSEM_GENERIC_SPINLOCK
1905 bool "Enable support for RAS CPU Exte !! 1024 bool
1906 default y 1025 default y
1907 help <<
1908 CPUs that support the Reliability, <<
1909 (RAS) Extensions, part of ARMv8.2 a <<
1910 errors, classify them and report th <<
1911 1026
1912 On CPUs with these extensions syste !! 1027 endmenu
1913 barriers to determine if faults are <<
1914 classification from a new set of re <<
1915 1028
1916 Selecting this feature will allow t !! 1029 menu "Bus options (PCI, PCMCIA, EISA, ISA, TC)"
1917 and access the new registers if the <<
1918 Platform RAS features may additiona <<
1919 <<
1920 config ARM64_CNP <<
1921 bool "Enable support for Common Not P <<
1922 default y <<
1923 depends on ARM64_PAN || !ARM64_SW_TTB <<
1924 help <<
1925 Common Not Private (CNP) allows tra <<
1926 be shared between different PEs in <<
1927 domain, so the hardware can use thi <<
1928 caching of such entries in the TLB. <<
1929 1030
1930 Selecting this option allows the CN !! 1031 config PCI
1931 at runtime, and does not affect PEs !! 1032 bool "Support for PCI controller"
1932 this feature. !! 1033 depends on MIPS_DB1000 || DDB5074 || DDB5476 || DDB5477 || HP_LASERJET || LASAT || MIPS_IVR || MIPS_ATLAS || MIPS_COBALT || MIPS_EV64120 || MIPS_EV96100 || MIPS_ITE8172 || MIPS_MALTA || MOMENCO_OCELOT || MOMENCO_OCELOT_C || MOMENCO_OCELOT_G || MIPS_PB1000 || MIPS_PB1100 || MIPS_PB1500 || NEC_EAGLE || SGI_IP27 || SGI_IP32 || SIBYTE_SB1250 || SNI_RM200_PCI || TANBAC_TB0226 || TANBAC_TB0229 || TOSHIBA_JMR3927 || TOSHIBA_RBTX4927 || VICTOR_MPC30X || ZAO_CAPCELLA
>> 1034 help
>> 1035 Find out whether you have a PCI motherboard. PCI is the name of a
>> 1036 bus system, i.e. the way the CPU talks to the other stuff inside
>> 1037 your box. Other bus systems are ISA, EISA, or VESA. If you have PCI,
>> 1038 say Y, otherwise N.
>> 1039
>> 1040 The PCI-HOWTO, available from
>> 1041 <http://www.tldp.org/docs.html#howto>, contains valuable
>> 1042 information about which PCI hardware does work under Linux and which
>> 1043 doesn't.
>> 1044
>> 1045 source "drivers/pci/Kconfig"
>> 1046
>> 1047 config ISA
>> 1048 bool "ISA bus support"
>> 1049 depends on ACER_PICA_61 || SGI_IP22 || MIPS_MAGNUM_4000 || OLIVETTI_M700 || SNI_RM200_PCI
>> 1050 default y if TOSHIBA_RBTX4927 || DDB5476 || DDB5074 || IBM_WORKPAD || CASIO_E55
>> 1051 help
>> 1052 Find out whether you have ISA slots on your motherboard. ISA is the
>> 1053 name of a bus system, i.e. the way the CPU talks to the other stuff
>> 1054 inside your box. Other bus systems are PCI, EISA, or VESA. ISA is
>> 1055 an older system, now being displaced by PCI; newer boards don't
>> 1056 support it. If you have ISA, say Y, otherwise N.
1933 1057
1934 endmenu # "ARMv8.2 architectural features" !! 1058 #
>> 1059 # The SCSI bits are needed to get the SCSI code to link ...
>> 1060 #
>> 1061 config GENERIC_ISA_DMA
>> 1062 bool
>> 1063 default y if ACER_PICA_61 || MIPS_MAGNUM_4000 || OLIVETTI_M700 || SNI_RM200_PCI || SCSI
1935 1064
1936 menu "ARMv8.3 architectural features" !! 1065 config EISA
>> 1066 bool "EISA support"
>> 1067 depends on ISA && (SGI_IP22 || SNI_RM200_PCI)
>> 1068 ---help---
>> 1069 The Extended Industry Standard Architecture (EISA) bus was
>> 1070 developed as an open alternative to the IBM MicroChannel bus.
>> 1071
>> 1072 The EISA bus provided some of the features of the IBM MicroChannel
>> 1073 bus while maintaining backward compatibility with cards made for
>> 1074 the older ISA bus. The EISA bus saw limited use between 1988 and
>> 1075 1995 when it was made obsolete by the PCI bus.
>> 1076
>> 1077 Say Y here if you are building a kernel for an EISA-based machine.
>> 1078
>> 1079 Otherwise, say N.
>> 1080
>> 1081 source "drivers/eisa/Kconfig"
>> 1082
>> 1083 config TC
>> 1084 bool "TURBOchannel support"
>> 1085 depends on DECSTATION
>> 1086 help
>> 1087 TurboChannel is a DEC (now Compaq (now HP)) bus for Alpha and MIPS
>> 1088 processors. Documentation on writing device drivers for TurboChannel
>> 1089 is available at:
>> 1090 <http://www.cs.arizona.edu/computer.help/policy/DIGITAL_unix/AA-PS3HD-TET1_html/TITLE.html>.
>> 1091
>> 1092 #config ACCESSBUS
>> 1093 # bool "Access.Bus support"
>> 1094 # depends on TC
1937 1095
1938 config ARM64_PTR_AUTH !! 1096 config MMU
1939 bool "Enable support for pointer auth !! 1097 bool
1940 default y 1098 default y
1941 help <<
1942 Pointer authentication (part of the <<
1943 instructions for signing and authen <<
1944 keys, which can be used to mitigate <<
1945 and other attacks. <<
1946 1099
1947 This option enables these instructi !! 1100 config MCA
1948 Choosing this option will cause the !! 1101 bool
1949 for each process at exec() time, wi <<
1950 context-switched along with the pro <<
1951 1102
1952 The feature is detected at runtime. !! 1103 config SBUS
1953 hardware it will not be advertised !! 1104 bool
1954 be enabled. <<
1955 1105
1956 If the feature is present on the bo !! 1106 config HOTPLUG
1957 the late CPU will be parked. Also, !! 1107 bool "Support for hot-pluggable devices"
1958 address auth and the late CPU has t !! 1108 ---help---
1959 but with the feature disabled. On s !! 1109 Say Y here if you want to plug devices into your computer while
1960 not be selected. !! 1110 the system is running, and be able to use them quickly. In many
>> 1111 cases, the devices can likewise be unplugged at any time too.
1961 1112
1962 config ARM64_PTR_AUTH_KERNEL !! 1113 One well known example of this is PCMCIA- or PC-cards, credit-card
1963 bool "Use pointer authentication for !! 1114 size devices such as network cards, modems or hard drives which are
1964 default y !! 1115 plugged into slots found on all modern laptop computers. Another
1965 depends on ARM64_PTR_AUTH !! 1116 example, used on modern desktops as well as laptops, is USB.
1966 depends on (CC_HAS_SIGN_RETURN_ADDRES <<
1967 # Modern compilers insert a .note.gnu <<
1968 # which is only understood by binutil <<
1969 depends on LD_IS_LLD || LD_VERSION >= <<
1970 depends on !CC_IS_CLANG || AS_HAS_CFI <<
1971 depends on (!FUNCTION_GRAPH_TRACER || <<
1972 help <<
1973 If the compiler supports the -mbran <<
1974 -msign-return-address flag (e.g. GC <<
1975 will cause the kernel itself to be <<
1976 protection. In this case, and if th <<
1977 support pointer authentication, the <<
1978 disabled with minimal loss of prote <<
1979 1117
1980 This feature works with FUNCTION_GR !! 1118 Enable HOTPLUG and KMOD, and build a modular kernel. Get agent
1981 DYNAMIC_FTRACE_WITH_ARGS is enabled !! 1119 software (at <http://linux-hotplug.sourceforge.net/>) and install it.
>> 1120 Then your kernel will automatically call out to a user mode "policy
>> 1121 agent" (/sbin/hotplug) to load modules and set up software needed
>> 1122 to use devices as you hotplug them.
1982 1123
1983 config CC_HAS_BRANCH_PROT_PAC_RET !! 1124 source "drivers/pcmcia/Kconfig"
1984 # GCC 9 or later, clang 8 or later <<
1985 def_bool $(cc-option,-mbranch-protect <<
1986 1125
1987 config CC_HAS_SIGN_RETURN_ADDRESS !! 1126 source "drivers/pci/hotplug/Kconfig"
1988 # GCC 7, 8 <<
1989 def_bool $(cc-option,-msign-return-ad <<
1990 1127
1991 config AS_HAS_ARMV8_3 !! 1128 endmenu
1992 def_bool $(cc-option,-Wa$(comma)-marc <<
1993 1129
1994 config AS_HAS_CFI_NEGATE_RA_STATE !! 1130 menu "Executable file formats"
1995 def_bool $(as-instr,.cfi_startproc\n. <<
1996 1131
1997 config AS_HAS_LDAPR !! 1132 source "fs/Kconfig.binfmt"
1998 def_bool $(as-instr,.arch_extension r <<
1999 1133
2000 endmenu # "ARMv8.3 architectural features" !! 1134 config TRAD_SIGNALS
>> 1135 bool
>> 1136 default y if MIPS32
2001 1137
2002 menu "ARMv8.4 architectural features" !! 1138 config BINFMT_IRIX
>> 1139 bool "Include IRIX binary compatibility"
>> 1140 depends on !CPU_LITTLE_ENDIAN && MIPS32
2003 1141
2004 config ARM64_AMU_EXTN !! 1142 config MIPS32_COMPAT
2005 bool "Enable support for the Activity !! 1143 bool "Kernel support for Linux/MIPS 32-bit binary compatibility"
2006 default y !! 1144 depends on MIPS64
2007 help 1145 help
2008 The activity monitors extension is !! 1146 Select this option if you want Linux/MIPS 32-bit binary
2009 by the ARMv8.4 CPU architecture. Th !! 1147 compatibility. Since all software available for Linux/MIPS is
2010 of the activity monitors architectu !! 1148 currently 32-bit you should say Y here.
2011 <<
2012 To enable the use of this extension <<
2013 1149
2014 Note that for architectural reasons !! 1150 config COMPAT
2015 support when running on CPUs that p !! 1151 bool
2016 extension. The required support is !! 1152 depends on MIPS32_COMPAT
2017 * Version 1.5 and later of the AR !! 1153 default y
2018 1154
2019 For kernels that have this configur !! 1155 config MIPS32_O32
2020 firmware, you may need to say N her !! 1156 bool "Kernel support for o32 binaries"
2021 Otherwise you may experience firmwa !! 1157 depends on MIPS32_COMPAT
2022 accessing the counter registers. Ev !! 1158 help
2023 symptoms, the values returned by th !! 1159 Select this option if you want to run o32 binaries. These are pure
2024 correctly reflect reality. Most com !! 1160 32-bit binaries as used by the 32-bit Linux/MIPS port. Most of
2025 indicating that the counter is not !! 1161 existing binaries are in this format.
2026 1162
2027 config AS_HAS_ARMV8_4 !! 1163 If unsure, say Y.
2028 def_bool $(cc-option,-Wa$(comma)-marc <<
2029 1164
2030 config ARM64_TLB_RANGE !! 1165 config MIPS32_N32
2031 bool "Enable support for tlbi range f !! 1166 bool "Kernel support for n32 binaries"
2032 default y !! 1167 depends on MIPS32_COMPAT
2033 depends on AS_HAS_ARMV8_4 <<
2034 help 1168 help
2035 ARMv8.4-TLBI provides TLBI invalida !! 1169 Select this option if you want to run n32 binaries. These are
2036 range of input addresses. !! 1170 64-bit binaries using 32-bit quantities for addressing and certain
2037 !! 1171 data that would normally be 64-bit. They are used in special
2038 The feature introduces new assembly !! 1172 cases.
2039 support when binutils >= 2.30. <<
2040 1173
2041 endmenu # "ARMv8.4 architectural features" !! 1174 If unsure, say N.
2042 1175
2043 menu "ARMv8.5 architectural features" !! 1176 config BINFMT_ELF32
>> 1177 bool
>> 1178 default y if MIPS32_O32 || MIPS32_N32
2044 1179
2045 config AS_HAS_ARMV8_5 !! 1180 config PM
2046 def_bool $(cc-option,-Wa$(comma)-marc !! 1181 bool "Power Management support (EXPERIMENTAL)"
>> 1182 depends on EXPERIMENTAL && SOC_AU1X00
2047 1183
2048 config ARM64_BTI !! 1184 endmenu
2049 bool "Branch Target Identification su <<
2050 default y <<
2051 help <<
2052 Branch Target Identification (part <<
2053 provides a mechanism to limit the s <<
2054 branch instructions such as BR or B <<
2055 1185
2056 To make use of BTI on CPUs that sup !! 1186 source "drivers/mtd/Kconfig"
2057 1187
2058 BTI is intended to provide compleme !! 1188 source "drivers/parport/Kconfig"
2059 flow integrity protection mechanism <<
2060 authentication mechanism provided a <<
2061 For this reason, it does not make s <<
2062 also enabling support for pointer a <<
2063 enabling this option you should als <<
2064 1189
2065 Userspace binaries must also be spe !! 1190 source "drivers/pnp/Kconfig"
2066 this mechanism. If you say N here <<
2067 BTI, such binaries can still run, b <<
2068 enforcement of branch destinations. <<
2069 1191
2070 config ARM64_BTI_KERNEL !! 1192 source "drivers/base/Kconfig"
2071 bool "Use Branch Target Identificatio <<
2072 default y <<
2073 depends on ARM64_BTI <<
2074 depends on ARM64_PTR_AUTH_KERNEL <<
2075 depends on CC_HAS_BRANCH_PROT_PAC_RET <<
2076 # https://gcc.gnu.org/bugzilla/show_b <<
2077 depends on !CC_IS_GCC || GCC_VERSION <<
2078 # https://gcc.gnu.org/bugzilla/show_b <<
2079 depends on !CC_IS_GCC <<
2080 depends on (!FUNCTION_GRAPH_TRACER || <<
2081 help <<
2082 Build the kernel with Branch Target <<
2083 and enable enforcement of this for <<
2084 is enabled and the system supports <<
2085 modular code must have BTI enabled. <<
2086 1193
2087 config CC_HAS_BRANCH_PROT_PAC_RET_BTI !! 1194 source "drivers/block/Kconfig"
2088 # GCC 9 or later, clang 8 or later <<
2089 def_bool $(cc-option,-mbranch-protect <<
2090 1195
2091 config ARM64_E0PD <<
2092 bool "Enable support for E0PD" <<
2093 default y <<
2094 help <<
2095 E0PD (part of the ARMv8.5 extension <<
2096 that EL0 accesses made via TTBR1 al <<
2097 providing similar benefits to KASLR <<
2098 with lower overhead and without dis <<
2099 kernel memory such as SPE. <<
2100 1196
2101 This option enables E0PD for TTBR1 !! 1197 menu "MIPS initrd options"
>> 1198 depends on BLK_DEV_INITRD
2102 1199
2103 config ARM64_AS_HAS_MTE !! 1200 config EMBEDDED_RAMDISK
2104 # Initial support for MTE went in bin !! 1201 bool "Embed root filesystem ramdisk into the kernel"
2105 # ".arch armv8.5-a+memtag" below. How <<
2106 # as a late addition to the final arc <<
2107 # is only supported in the newer 2.32 <<
2108 # versions, hence the extra "stgm" in <<
2109 def_bool $(as-instr,.arch armv8.5-a+m <<
2110 1202
2111 config ARM64_MTE !! 1203 config EMBEDDED_RAMDISK_IMAGE
2112 bool "Memory Tagging Extension suppor !! 1204 string "Filename of gziped ramdisk image"
2113 default y !! 1205 depends on EMBEDDED_RAMDISK
2114 depends on ARM64_AS_HAS_MTE && ARM64_ !! 1206 default "ramdisk.gz"
2115 depends on AS_HAS_ARMV8_5 <<
2116 depends on AS_HAS_LSE_ATOMICS <<
2117 # Required for tag checking in the ua <<
2118 depends on ARM64_PAN <<
2119 select ARCH_HAS_SUBPAGE_FAULTS <<
2120 select ARCH_USES_HIGH_VMA_FLAGS <<
2121 select ARCH_USES_PG_ARCH_2 <<
2122 select ARCH_USES_PG_ARCH_3 <<
2123 help 1207 help
2124 Memory Tagging (part of the ARMv8.5 !! 1208 This is the filename of the ramdisk image to be built into the
2125 architectural support for run-time, !! 1209 kernel. Relative pathnames are relative to arch/mips/ramdisk/.
2126 various classes of memory error to !! 1210 The ramdisk image is not part of the kernel distribution; you must
2127 to eliminate vulnerabilities arisin !! 1211 provide one yourself.
2128 languages. <<
2129 1212
2130 This option enables the support for !! 1213 endmenu
2131 Extension at EL0 (i.e. for userspac <<
2132 1214
2133 Selecting this option allows the fe !! 1215 source "drivers/ide/Kconfig"
2134 runtime. Any secondary CPU not impl <<
2135 not be allowed a late bring-up. <<
2136 1216
2137 Userspace binaries that want to use !! 1217 source "drivers/scsi/Kconfig"
2138 explicitly opt in. The mechanism fo <<
2139 described in: <<
2140 1218
2141 Documentation/arch/arm64/memory-tag !! 1219 source "drivers/cdrom/Kconfig"
2142 1220
2143 endmenu # "ARMv8.5 architectural features" !! 1221 source "drivers/md/Kconfig"
2144 1222
2145 menu "ARMv8.7 architectural features" !! 1223 source "drivers/message/fusion/Kconfig"
2146 1224
2147 config ARM64_EPAN !! 1225 source "drivers/ieee1394/Kconfig"
2148 bool "Enable support for Enhanced Pri <<
2149 default y <<
2150 depends on ARM64_PAN <<
2151 help <<
2152 Enhanced Privileged Access Never (E <<
2153 Access Never to be used with Execut <<
2154 1226
2155 The feature is detected at runtime, !! 1227 source "drivers/message/i2o/Kconfig"
2156 if the cpu does not implement the f <<
2157 endmenu # "ARMv8.7 architectural features" <<
2158 1228
2159 menu "ARMv8.9 architectural features" !! 1229 source "net/Kconfig"
2160 1230
2161 config ARM64_POE !! 1231 source "drivers/isdn/Kconfig"
2162 prompt "Permission Overlay Extension" <<
2163 def_bool y <<
2164 select ARCH_USES_HIGH_VMA_FLAGS <<
2165 select ARCH_HAS_PKEYS <<
2166 help <<
2167 The Permission Overlay Extension is <<
2168 Protection Keys. Memory Protection <<
2169 enforcing page-based protections, b <<
2170 of the page tables when an applicat <<
2171 1232
2172 For details, see Documentation/core !! 1233 source "drivers/telephony/Kconfig"
2173 1234
2174 If unsure, say y. !! 1235 #
>> 1236 # input before char - char/joystick depends on it. As does USB.
>> 1237 #
>> 1238 source "drivers/input/Kconfig"
2175 1239
2176 config ARCH_PKEY_BITS !! 1240 source "drivers/char/Kconfig"
2177 int <<
2178 default 3 <<
2179 1241
2180 endmenu # "ARMv8.9 architectural features" !! 1242 #source drivers/misc/Config.in
2181 1243
2182 config ARM64_SVE !! 1244 source "drivers/media/Kconfig"
2183 bool "ARM Scalable Vector Extension s <<
2184 default y <<
2185 help <<
2186 The Scalable Vector Extension (SVE) <<
2187 execution state which complements a <<
2188 of the base architecture to support <<
2189 additional vectorisation opportunit <<
2190 1245
2191 To enable use of this extension on !! 1246 source "fs/Kconfig"
2192 1247
2193 On CPUs that support the SVE2 exten !! 1248 source "drivers/video/Kconfig"
2194 those too. <<
2195 1249
2196 Note that for architectural reasons <<
2197 support when running on SVE capable <<
2198 is present in: <<
2199 1250
2200 * version 1.5 and later of the AR !! 1251 menu "Sound"
2201 * the AArch64 boot wrapper since <<
2202 ("bootwrapper: SVE: Enable SVE <<
2203 1252
2204 For other firmware implementations, !! 1253 config SOUND
2205 or vendor. !! 1254 tristate "Sound card support"
>> 1255 ---help---
>> 1256 If you have a sound card in your computer, i.e. if it can say more
>> 1257 than an occasional beep, say Y. Be sure to have all the information
>> 1258 about your sound card and its configuration down (I/O port,
>> 1259 interrupt and DMA channel), because you will be asked for it.
2206 1260
2207 If you need the kernel to boot on S !! 1261 You want to read the Sound-HOWTO, available from
2208 firmware, you may need to say N her !! 1262 <http://www.tldp.org/docs.html#howto>. General information about
2209 fixed. Otherwise, you may experien !! 1263 the modular sound system is contained in the files
2210 booting the kernel. If unsure and !! 1264 <file:Documentation/sound/Introduction>. The file
2211 symptoms, you should assume that it !! 1265 <file:Documentation/sound/README.OSS> contains some slightly
>> 1266 outdated but still useful information as well.
2212 1267
2213 config ARM64_SME !! 1268 If you have a PnP sound card and you want to configure it at boot
2214 bool "ARM Scalable Matrix Extension s !! 1269 time using the ISA PnP tools (read
2215 default y !! 1270 <http://www.roestock.demon.co.uk/isapnptools/>), then you need to
2216 depends on ARM64_SVE !! 1271 compile the sound card support as a module and load that module
2217 depends on BROKEN !! 1272 after the PnP configuration is finished. To do this, choose M here
2218 help !! 1273 and read <file:Documentation/sound/README.modules>; the module
2219 The Scalable Matrix Extension (SME) !! 1274 will be called soundcore.
2220 execution state which utilises a su <<
2221 instruction set, together with the <<
2222 register state capable of holding t <<
2223 enable various matrix operations. <<
2224 1275
2225 config ARM64_PSEUDO_NMI !! 1276 I'm told that even without a sound card, you can make your computer
2226 bool "Support for NMI-like interrupts !! 1277 say more than an occasional beep, by programming the PC speaker.
2227 select ARM_GIC_V3 !! 1278 Kernel patches and supporting utilities to do that are in the pcsp
2228 help !! 1279 package, available at <ftp://ftp.infradead.org/pub/pcsp/>.
2229 Adds support for mimicking Non-Mask <<
2230 GIC interrupt priority. This suppor <<
2231 ARM GIC. <<
2232 1280
2233 This high priority configuration fo !! 1281 source "sound/Kconfig"
2234 explicitly enabled by setting the k <<
2235 "irqchip.gicv3_pseudo_nmi" to 1. <<
2236 1282
2237 If unsure, say N !! 1283 endmenu
2238 1284
2239 if ARM64_PSEUDO_NMI !! 1285 source "drivers/usb/Kconfig"
2240 config ARM64_DEBUG_PRIORITY_MASKING <<
2241 bool "Debug interrupt priority maskin <<
2242 help <<
2243 This adds runtime checks to functio <<
2244 interrupts when using priority mask <<
2245 the validity of ICC_PMR_EL1 when ca <<
2246 1286
2247 If unsure, say N <<
2248 endif # ARM64_PSEUDO_NMI <<
2249 1287
2250 config RELOCATABLE !! 1288 menu "Kernel hacking"
2251 bool "Build a relocatable kernel imag <<
2252 select ARCH_HAS_RELR <<
2253 default y <<
2254 help <<
2255 This builds the kernel as a Positio <<
2256 which retains all relocation metada <<
2257 kernel binary at runtime to a diffe <<
2258 address it was linked at. <<
2259 Since AArch64 uses the RELA relocat <<
2260 relocation pass at runtime even if <<
2261 same address it was linked at. <<
2262 1289
2263 config RANDOMIZE_BASE !! 1290 config CROSSCOMPILE
2264 bool "Randomize the address of the ke !! 1291 bool "Are you using a crosscompiler"
2265 select RELOCATABLE <<
2266 help 1292 help
2267 Randomizes the virtual address at w !! 1293 Say Y here if you are compiling the kernel on a different
2268 loaded, as a security feature that !! 1294 architecture than the one it is intended to run on.
2269 relying on knowledge of the locatio <<
2270 <<
2271 It is the bootloader's job to provi <<
2272 random u64 value in /chosen/kaslr-s <<
2273 <<
2274 When booting via the UEFI stub, it <<
2275 EFI_RNG_PROTOCOL implementation (if <<
2276 to the kernel proper. In addition, <<
2277 location of the kernel Image as wel <<
2278 <<
2279 If unsure, say N. <<
2280 1295
2281 config RANDOMIZE_MODULE_REGION_FULL !! 1296 config DEBUG_KERNEL
2282 bool "Randomize the module region ove !! 1297 bool "Kernel debugging"
2283 depends on RANDOMIZE_BASE <<
2284 default y <<
2285 help <<
2286 Randomizes the location of the modu <<
2287 covering the core kernel. This way, <<
2288 to leak information about the locat <<
2289 but it does imply that function cal <<
2290 kernel will need to be resolved via <<
2291 <<
2292 When this option is not set, the mo <<
2293 a limited range that contains the [ <<
2294 core kernel, so branch relocations <<
2295 the region is exhausted. In this pa <<
2296 exhaustion, modules might be able t <<
2297 <<
2298 config CC_HAVE_STACKPROTECTOR_SYSREG <<
2299 def_bool $(cc-option,-mstack-protecto <<
2300 <<
2301 config STACKPROTECTOR_PER_TASK <<
2302 def_bool y <<
2303 depends on STACKPROTECTOR && CC_HAVE_ <<
2304 <<
2305 config UNWIND_PATCH_PAC_INTO_SCS <<
2306 bool "Enable shadow call stack dynami <<
2307 # needs Clang with https://github.com <<
2308 depends on CC_IS_CLANG && CLANG_VERSI <<
2309 depends on ARM64_PTR_AUTH_KERNEL && C <<
2310 depends on SHADOW_CALL_STACK <<
2311 select UNWIND_TABLES <<
2312 select DYNAMIC_SCS <<
2313 <<
2314 config ARM64_CONTPTE <<
2315 bool "Contiguous PTE mappings for use <<
2316 depends on TRANSPARENT_HUGEPAGE <<
2317 default y <<
2318 help <<
2319 When enabled, user mappings are con <<
2320 bit, for any mappings that meet the <<
2321 This reduces TLB pressure and impro <<
2322 <<
2323 endmenu # "Kernel Features" <<
2324 <<
2325 menu "Boot options" <<
2326 <<
2327 config ARM64_ACPI_PARKING_PROTOCOL <<
2328 bool "Enable support for the ARM64 AC <<
2329 depends on ACPI <<
2330 help <<
2331 Enable support for the ARM64 ACPI p <<
2332 the kernel will not allow booting t <<
2333 protocol even if the corresponding <<
2334 MADT table. <<
2335 <<
2336 config CMDLINE <<
2337 string "Default kernel command string <<
2338 default "" <<
2339 help <<
2340 Provide a set of default command-li <<
2341 entering them here. As a minimum, y <<
2342 root device (e.g. root=/dev/nfs). <<
2343 <<
2344 choice <<
2345 prompt "Kernel command line type" <<
2346 depends on CMDLINE != "" <<
2347 default CMDLINE_FROM_BOOTLOADER <<
2348 help <<
2349 Choose how the kernel will handle t <<
2350 command line string. <<
2351 <<
2352 config CMDLINE_FROM_BOOTLOADER <<
2353 bool "Use bootloader kernel arguments <<
2354 help <<
2355 Uses the command-line options passe <<
2356 the boot loader doesn't provide any <<
2357 string provided in CMDLINE will be <<
2358 <<
2359 config CMDLINE_FORCE <<
2360 bool "Always use the default kernel c <<
2361 help <<
2362 Always use the default kernel comma <<
2363 loader passes other arguments to th <<
2364 This is useful if you cannot or don <<
2365 command-line options your boot load <<
2366 <<
2367 endchoice <<
2368 <<
2369 config EFI_STUB <<
2370 bool <<
2371 1298
2372 config EFI !! 1299 config KGDB
2373 bool "UEFI runtime support" !! 1300 bool "Remote GDB kernel debugging"
2374 depends on OF && !CPU_BIG_ENDIAN !! 1301 depends on DEBUG_KERNEL
2375 depends on KERNEL_MODE_NEON <<
2376 select ARCH_SUPPORTS_ACPI <<
2377 select LIBFDT <<
2378 select UCS2_STRING <<
2379 select EFI_PARAMS_FROM_FDT <<
2380 select EFI_RUNTIME_WRAPPERS <<
2381 select EFI_STUB <<
2382 select EFI_GENERIC_STUB <<
2383 imply IMA_SECURE_AND_OR_TRUSTED_BOOT <<
2384 default y <<
2385 help 1302 help
2386 This option provides support for ru !! 1303 If you say Y here, it will be possible to remotely debug the MIPS
2387 by UEFI firmware (such as non-volat !! 1304 kernel using gdb. This enlarges your kernel image disk size by
2388 clock, and platform reset). A UEFI !! 1305 several megabytes and requires a machine with more than 16 MB,
2389 allow the kernel to be booted as an !! 1306 better 32 MB RAM to avoid excessive linking time. This is only
2390 is only useful on systems that have !! 1307 useful for kernel hackers. If unsure, say N.
2391 1308
2392 config COMPRESSED_INSTALL !! 1309 config GDB_CONSOLE
2393 bool "Install compressed image by def !! 1310 bool "Console output to GDB"
>> 1311 depends on KGDB
2394 help 1312 help
2395 This makes the regular "make instal !! 1313 If you are using GDB for remote debugging over a serial port and
2396 image we built, not the legacy unco !! 1314 would like kernel messages to be formatted into GDB $O packets so
2397 !! 1315 that GDB prints them as program output, say 'Y'.
2398 You can check that a compressed ima <<
2399 "make zinstall" first, and verifyin <<
2400 in your environment before making " <<
2401 you. <<
2402 1316
2403 config DMI !! 1317 config RUNTIME_DEBUG
2404 bool "Enable support for SMBIOS (DMI) !! 1318 bool "Enable run-time debugging"
2405 depends on EFI !! 1319 depends on DEBUG_KERNEL
2406 default y <<
2407 help 1320 help
2408 This enables SMBIOS/DMI feature for !! 1321 If you say Y here, some debugging macros will do run-time checking.
2409 !! 1322 If you say N here, those macros will mostly turn to no-ops. See
2410 This option is only useful on syste !! 1323 include/asm-mips/debug.h for debuging macros.
2411 However, even with this option, the !! 1324 If unsure, say N.
2412 continue to boot on existing non-UE <<
2413 <<
2414 endmenu # "Boot options" <<
2415 <<
2416 menu "Power management options" <<
2417 <<
2418 source "kernel/power/Kconfig" <<
2419 <<
2420 config ARCH_HIBERNATION_POSSIBLE <<
2421 def_bool y <<
2422 depends on CPU_PM <<
2423 <<
2424 config ARCH_HIBERNATION_HEADER <<
2425 def_bool y <<
2426 depends on HIBERNATION <<
2427 <<
2428 config ARCH_SUSPEND_POSSIBLE <<
2429 def_bool y <<
2430 <<
2431 endmenu # "Power management options" <<
2432 <<
2433 menu "CPU Power Management" <<
2434 1325
2435 source "drivers/cpuidle/Kconfig" <<
2436 1326
2437 source "drivers/cpufreq/Kconfig" !! 1327 config MAGIC_SYSRQ
>> 1328 bool "Magic SysRq key"
>> 1329 depends on DEBUG_KERNEL
>> 1330 help
>> 1331 If you say Y here, you will have some control over the system even
>> 1332 if the system crashes for example during kernel debugging (e.g., you
>> 1333 will be able to flush the buffer cache to disk, reboot the system
>> 1334 immediately or dump some status information). This is accomplished
>> 1335 by pressing various keys while holding SysRq (Alt+PrintScreen). It
>> 1336 also works on a serial console (on PC hardware at least), if you
>> 1337 send a BREAK and then within 5 seconds a command keypress. The
>> 1338 keys are documented in <file:Documentation/sysrq.txt>. Don't say Y
>> 1339 unless you really know what this hack does.
>> 1340
>> 1341 config MIPS_UNCACHED
>> 1342 bool "Run uncached"
>> 1343 depends on DEBUG_KERNEL && !SMP && !SGI_IP27
>> 1344 help
>> 1345 If you say Y here there kernel will disable all CPU caches. This will
>> 1346 reduce the system's performance dramatically but can help finding
>> 1347 otherwise hard to track bugs. It can also useful if you're doing
>> 1348 hardware debugging with a logic analyzer and need to see all traffic
>> 1349 on the bus.
>> 1350
>> 1351 config DEBUG_HIGHMEM
>> 1352 bool "Highmem debugging"
>> 1353 depends on DEBUG_KERNEL && HIGHMEM
2438 1354
2439 endmenu # "CPU Power Management" !! 1355 endmenu
2440 1356
2441 source "drivers/acpi/Kconfig" !! 1357 source "security/Kconfig"
2442 1358
2443 source "arch/arm64/kvm/Kconfig" !! 1359 source "crypto/Kconfig"
2444 1360
>> 1361 source "lib/Kconfig"
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