1 # SPDX-License-Identifier: GPL-2.0-only !! 1 config MIPS
2 config ARM64 !! 2 bool
3 def_bool y !! 3 default y
4 select ACPI_APMT if ACPI !! 4 select HAVE_GENERIC_DMA_COHERENT
5 select ACPI_CCA_REQUIRED if ACPI !! 5 select HAVE_IDE
6 select ACPI_GENERIC_GSI if ACPI !! 6 select HAVE_OPROFILE
7 select ACPI_GTDT if ACPI <<
8 select ACPI_HOTPLUG_CPU if ACPI_PROCES <<
9 select ACPI_IORT if ACPI <<
10 select ACPI_REDUCED_HARDWARE_ONLY if A <<
11 select ACPI_MCFG if (ACPI && PCI) <<
12 select ACPI_SPCR_TABLE if ACPI <<
13 select ACPI_PPTT if ACPI <<
14 select ARCH_HAS_DEBUG_WX <<
15 select ARCH_BINFMT_ELF_EXTRA_PHDRS <<
16 select ARCH_BINFMT_ELF_STATE <<
17 select ARCH_CORRECT_STACKTRACE_ON_KRET <<
18 select ARCH_ENABLE_HUGEPAGE_MIGRATION <<
19 select ARCH_ENABLE_MEMORY_HOTPLUG <<
20 select ARCH_ENABLE_MEMORY_HOTREMOVE <<
21 select ARCH_ENABLE_SPLIT_PMD_PTLOCK if <<
22 select ARCH_ENABLE_THP_MIGRATION if TR <<
23 select ARCH_HAS_CACHE_LINE_SIZE <<
24 select ARCH_HAS_CURRENT_STACK_POINTER <<
25 select ARCH_HAS_DEBUG_VIRTUAL <<
26 select ARCH_HAS_DEBUG_VM_PGTABLE <<
27 select ARCH_HAS_DMA_OPS if XEN <<
28 select ARCH_HAS_DMA_PREP_COHERENT <<
29 select ARCH_HAS_ACPI_TABLE_UPGRADE if <<
30 select ARCH_HAS_FAST_MULTIPLIER <<
31 select ARCH_HAS_FORTIFY_SOURCE <<
32 select ARCH_HAS_GCOV_PROFILE_ALL <<
33 select ARCH_HAS_GIGANTIC_PAGE <<
34 select ARCH_HAS_KCOV <<
35 select ARCH_HAS_KERNEL_FPU_SUPPORT if <<
36 select ARCH_HAS_KEEPINITRD <<
37 select ARCH_HAS_MEMBARRIER_SYNC_CORE <<
38 select ARCH_HAS_MEM_ENCRYPT <<
39 select ARCH_HAS_NMI_SAFE_THIS_CPU_OPS <<
40 select ARCH_HAS_NON_OVERLAPPING_ADDRES <<
41 select ARCH_HAS_PTE_DEVMAP <<
42 select ARCH_HAS_PTE_SPECIAL <<
43 select ARCH_HAS_HW_PTE_YOUNG <<
44 select ARCH_HAS_SETUP_DMA_OPS <<
45 select ARCH_HAS_SET_DIRECT_MAP <<
46 select ARCH_HAS_SET_MEMORY <<
47 select ARCH_STACKWALK <<
48 select ARCH_HAS_STRICT_KERNEL_RWX <<
49 select ARCH_HAS_STRICT_MODULE_RWX <<
50 select ARCH_HAS_SYNC_DMA_FOR_DEVICE <<
51 select ARCH_HAS_SYNC_DMA_FOR_CPU <<
52 select ARCH_HAS_SYSCALL_WRAPPER <<
53 select ARCH_HAS_TICK_BROADCAST if GENE <<
54 select ARCH_HAS_ZONE_DMA_SET if EXPERT <<
55 select ARCH_HAVE_ELF_PROT <<
56 select ARCH_HAVE_NMI_SAFE_CMPXCHG <<
57 select ARCH_HAVE_TRACE_MMIO_ACCESS <<
58 select ARCH_INLINE_READ_LOCK if !PREEM <<
59 select ARCH_INLINE_READ_LOCK_BH if !PR <<
60 select ARCH_INLINE_READ_LOCK_IRQ if !P <<
61 select ARCH_INLINE_READ_LOCK_IRQSAVE i <<
62 select ARCH_INLINE_READ_UNLOCK if !PRE <<
63 select ARCH_INLINE_READ_UNLOCK_BH if ! <<
64 select ARCH_INLINE_READ_UNLOCK_IRQ if <<
65 select ARCH_INLINE_READ_UNLOCK_IRQREST <<
66 select ARCH_INLINE_WRITE_LOCK if !PREE <<
67 select ARCH_INLINE_WRITE_LOCK_BH if !P <<
68 select ARCH_INLINE_WRITE_LOCK_IRQ if ! <<
69 select ARCH_INLINE_WRITE_LOCK_IRQSAVE <<
70 select ARCH_INLINE_WRITE_UNLOCK if !PR <<
71 select ARCH_INLINE_WRITE_UNLOCK_BH if <<
72 select ARCH_INLINE_WRITE_UNLOCK_IRQ if <<
73 select ARCH_INLINE_WRITE_UNLOCK_IRQRES <<
74 select ARCH_INLINE_SPIN_TRYLOCK if !PR <<
75 select ARCH_INLINE_SPIN_TRYLOCK_BH if <<
76 select ARCH_INLINE_SPIN_LOCK if !PREEM <<
77 select ARCH_INLINE_SPIN_LOCK_BH if !PR <<
78 select ARCH_INLINE_SPIN_LOCK_IRQ if !P <<
79 select ARCH_INLINE_SPIN_LOCK_IRQSAVE i <<
80 select ARCH_INLINE_SPIN_UNLOCK if !PRE <<
81 select ARCH_INLINE_SPIN_UNLOCK_BH if ! <<
82 select ARCH_INLINE_SPIN_UNLOCK_IRQ if <<
83 select ARCH_INLINE_SPIN_UNLOCK_IRQREST <<
84 select ARCH_KEEP_MEMBLOCK <<
85 select ARCH_MHP_MEMMAP_ON_MEMORY_ENABL <<
86 select ARCH_USE_CMPXCHG_LOCKREF <<
87 select ARCH_USE_GNU_PROPERTY <<
88 select ARCH_USE_MEMTEST <<
89 select ARCH_USE_QUEUED_RWLOCKS <<
90 select ARCH_USE_QUEUED_SPINLOCKS <<
91 select ARCH_USE_SYM_ANNOTATIONS <<
92 select ARCH_SUPPORTS_DEBUG_PAGEALLOC <<
93 select ARCH_SUPPORTS_HUGETLBFS <<
94 select ARCH_SUPPORTS_MEMORY_FAILURE <<
95 select ARCH_SUPPORTS_SHADOW_CALL_STACK <<
96 select ARCH_SUPPORTS_LTO_CLANG if CPU_ <<
97 select ARCH_SUPPORTS_LTO_CLANG_THIN <<
98 select ARCH_SUPPORTS_CFI_CLANG <<
99 select ARCH_SUPPORTS_ATOMIC_RMW <<
100 select ARCH_SUPPORTS_INT128 if CC_HAS_ <<
101 select ARCH_SUPPORTS_NUMA_BALANCING <<
102 select ARCH_SUPPORTS_PAGE_TABLE_CHECK <<
103 select ARCH_SUPPORTS_PER_VMA_LOCK <<
104 select ARCH_SUPPORTS_HUGE_PFNMAP if TR <<
105 select ARCH_SUPPORTS_RT <<
106 select ARCH_WANT_BATCHED_UNMAP_TLB_FLU <<
107 select ARCH_WANT_COMPAT_IPC_PARSE_VERS <<
108 select ARCH_WANT_DEFAULT_BPF_JIT <<
109 select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_ <<
110 select ARCH_WANT_FRAME_POINTERS <<
111 select ARCH_WANT_HUGE_PMD_SHARE if ARM <<
112 select ARCH_WANT_LD_ORPHAN_WARN <<
113 select ARCH_WANTS_EXECMEM_LATE if EXEC <<
114 select ARCH_WANTS_NO_INSTR <<
115 select ARCH_WANTS_THP_SWAP if ARM64_4K <<
116 select ARCH_HAS_UBSAN <<
117 select ARM_AMBA <<
118 select ARM_ARCH_TIMER <<
119 select ARM_GIC <<
120 select AUDIT_ARCH_COMPAT_GENERIC <<
121 select ARM_GIC_V2M if PCI <<
122 select ARM_GIC_V3 <<
123 select ARM_GIC_V3_ITS if PCI <<
124 select ARM_PSCI_FW <<
125 select BUILDTIME_TABLE_SORT <<
126 select CLONE_BACKWARDS <<
127 select COMMON_CLK <<
128 select CPU_PM if (SUSPEND || CPU_IDLE) <<
129 select CPUMASK_OFFSTACK if NR_CPUS > 2 <<
130 select CRC32 <<
131 select DCACHE_WORD_ACCESS <<
132 select DYNAMIC_FTRACE if FUNCTION_TRAC <<
133 select DMA_BOUNCE_UNALIGNED_KMALLOC <<
134 select DMA_DIRECT_REMAP <<
135 select EDAC_SUPPORT <<
136 select FRAME_POINTER <<
137 select FUNCTION_ALIGNMENT_4B <<
138 select FUNCTION_ALIGNMENT_8B if DYNAMI <<
139 select GENERIC_ALLOCATOR <<
140 select GENERIC_ARCH_TOPOLOGY <<
141 select GENERIC_CLOCKEVENTS_BROADCAST <<
142 select GENERIC_CPU_AUTOPROBE <<
143 select GENERIC_CPU_DEVICES <<
144 select GENERIC_CPU_VULNERABILITIES <<
145 select GENERIC_EARLY_IOREMAP <<
146 select GENERIC_IDLE_POLL_SETUP <<
147 select GENERIC_IOREMAP <<
148 select GENERIC_IRQ_IPI <<
149 select GENERIC_IRQ_PROBE <<
150 select GENERIC_IRQ_SHOW <<
151 select GENERIC_IRQ_SHOW_LEVEL <<
152 select GENERIC_LIB_DEVMEM_IS_ALLOWED <<
153 select GENERIC_PCI_IOMAP <<
154 select GENERIC_PTDUMP <<
155 select GENERIC_SCHED_CLOCK <<
156 select GENERIC_SMP_IDLE_THREAD <<
157 select GENERIC_TIME_VSYSCALL <<
158 select GENERIC_GETTIMEOFDAY <<
159 select GENERIC_VDSO_TIME_NS <<
160 select HARDIRQS_SW_RESEND <<
161 select HAS_IOPORT <<
162 select HAVE_MOVE_PMD <<
163 select HAVE_MOVE_PUD <<
164 select HAVE_PCI <<
165 select HAVE_ACPI_APEI if (ACPI && EFI) <<
166 select HAVE_ALIGNED_STRUCT_PAGE <<
167 select HAVE_ARCH_AUDITSYSCALL <<
168 select HAVE_ARCH_BITREVERSE <<
169 select HAVE_ARCH_COMPILER_H <<
170 select HAVE_ARCH_HUGE_VMALLOC <<
171 select HAVE_ARCH_HUGE_VMAP <<
172 select HAVE_ARCH_JUMP_LABEL <<
173 select HAVE_ARCH_JUMP_LABEL_RELATIVE <<
174 select HAVE_ARCH_KASAN <<
175 select HAVE_ARCH_KASAN_VMALLOC <<
176 select HAVE_ARCH_KASAN_SW_TAGS <<
177 select HAVE_ARCH_KASAN_HW_TAGS if ARM6 <<
178 # Some instrumentation may be unsound, <<
179 select HAVE_ARCH_KCSAN if EXPERT <<
180 select HAVE_ARCH_KFENCE <<
181 select HAVE_ARCH_KGDB 7 select HAVE_ARCH_KGDB
182 select HAVE_ARCH_MMAP_RND_BITS !! 8 # Horrible source of confusion. Die, die, die ...
183 select HAVE_ARCH_MMAP_RND_COMPAT_BITS !! 9 select EMBEDDED
184 select HAVE_ARCH_PREL32_RELOCATIONS !! 10 select RTC_LIB if !LEMOTE_FULOONG2E
185 select HAVE_ARCH_RANDOMIZE_KSTACK_OFFS <<
186 select HAVE_ARCH_SECCOMP_FILTER <<
187 select HAVE_ARCH_STACKLEAK <<
188 select HAVE_ARCH_THREAD_STRUCT_WHITELI <<
189 select HAVE_ARCH_TRACEHOOK <<
190 select HAVE_ARCH_TRANSPARENT_HUGEPAGE <<
191 select HAVE_ARCH_VMAP_STACK <<
192 select HAVE_ARM_SMCCC <<
193 select HAVE_ASM_MODVERSIONS <<
194 select HAVE_EBPF_JIT <<
195 select HAVE_C_RECORDMCOUNT <<
196 select HAVE_CMPXCHG_DOUBLE <<
197 select HAVE_CMPXCHG_LOCAL <<
198 select HAVE_CONTEXT_TRACKING_USER <<
199 select HAVE_DEBUG_KMEMLEAK <<
200 select HAVE_DMA_CONTIGUOUS <<
201 select HAVE_DYNAMIC_FTRACE <<
202 select HAVE_DYNAMIC_FTRACE_WITH_ARGS \ <<
203 if (GCC_SUPPORTS_DYNAMIC_FTRAC <<
204 CLANG_SUPPORTS_DYNAMIC_FTR <<
205 select HAVE_DYNAMIC_FTRACE_WITH_DIRECT <<
206 if DYNAMIC_FTRACE_WITH_ARGS && <<
207 select HAVE_DYNAMIC_FTRACE_WITH_CALL_O <<
208 if (DYNAMIC_FTRACE_WITH_ARGS & <<
209 (CC_IS_CLANG || !CC_OPTIMI <<
210 select FTRACE_MCOUNT_USE_PATCHABLE_FUN <<
211 if DYNAMIC_FTRACE_WITH_ARGS <<
212 select HAVE_SAMPLE_FTRACE_DIRECT <<
213 select HAVE_SAMPLE_FTRACE_DIRECT_MULTI <<
214 select HAVE_EFFICIENT_UNALIGNED_ACCESS <<
215 select HAVE_GUP_FAST <<
216 select HAVE_FTRACE_MCOUNT_RECORD <<
217 select HAVE_FUNCTION_TRACER <<
218 select HAVE_FUNCTION_ERROR_INJECTION <<
219 select HAVE_FUNCTION_GRAPH_TRACER <<
220 select HAVE_FUNCTION_GRAPH_RETVAL <<
221 select HAVE_GCC_PLUGINS <<
222 select HAVE_HARDLOCKUP_DETECTOR_PERF i <<
223 HW_PERF_EVENTS && HAVE_PERF_EV <<
224 select HAVE_HW_BREAKPOINT if PERF_EVEN <<
225 select HAVE_IOREMAP_PROT <<
226 select HAVE_IRQ_TIME_ACCOUNTING <<
227 select HAVE_MOD_ARCH_SPECIFIC <<
228 select HAVE_NMI <<
229 select HAVE_PERF_EVENTS <<
230 select HAVE_PERF_EVENTS_NMI if ARM64_P <<
231 select HAVE_PERF_REGS <<
232 select HAVE_PERF_USER_STACK_DUMP <<
233 select HAVE_PREEMPT_DYNAMIC_KEY <<
234 select HAVE_REGS_AND_STACK_ACCESS_API <<
235 select HAVE_POSIX_CPU_TIMERS_TASK_WORK <<
236 select HAVE_FUNCTION_ARG_ACCESS_API <<
237 select MMU_GATHER_RCU_TABLE_FREE <<
238 select HAVE_RSEQ <<
239 select HAVE_RUST if RUSTC_SUPPORTS_ARM <<
240 select HAVE_STACKPROTECTOR <<
241 select HAVE_SYSCALL_TRACEPOINTS <<
242 select HAVE_KPROBES <<
243 select HAVE_KRETPROBES <<
244 select HAVE_GENERIC_VDSO <<
245 select HOTPLUG_CORE_SYNC_DEAD if HOTPL <<
246 select IRQ_DOMAIN <<
247 select IRQ_FORCED_THREADING <<
248 select KASAN_VMALLOC if KASAN <<
249 select LOCK_MM_AND_FIND_VMA <<
250 select MODULES_USE_ELF_RELA <<
251 select NEED_DMA_MAP_STATE <<
252 select NEED_SG_DMA_LENGTH <<
253 select OF <<
254 select OF_EARLY_FLATTREE <<
255 select PCI_DOMAINS_GENERIC if PCI <<
256 select PCI_ECAM if (ACPI && PCI) <<
257 select PCI_SYSCALL if PCI <<
258 select POWER_RESET <<
259 select POWER_SUPPLY <<
260 select SPARSE_IRQ <<
261 select SWIOTLB <<
262 select SYSCTL_EXCEPTION_TRACE <<
263 select THREAD_INFO_IN_TASK <<
264 select HAVE_ARCH_USERFAULTFD_MINOR if <<
265 select HAVE_ARCH_USERFAULTFD_WP if USE <<
266 select TRACE_IRQFLAGS_SUPPORT <<
267 select TRACE_IRQFLAGS_NMI_SUPPORT <<
268 select HAVE_SOFTIRQ_ON_OWN_STACK <<
269 select USER_STACKTRACE_SUPPORT <<
270 select VDSO_GETRANDOM <<
271 help <<
272 ARM 64-bit (AArch64) Linux support. <<
273 <<
274 config RUSTC_SUPPORTS_ARM64 <<
275 def_bool y <<
276 depends on CPU_LITTLE_ENDIAN <<
277 # Shadow call stack is only supported <<
278 # <<
279 # When using the UNWIND_PATCH_PAC_INTO <<
280 # required due to use of the -Zfixed-x <<
281 # <<
282 # Otherwise, rustc version 1.82+ is re <<
283 # -Zsanitizer=shadow-call-stack flag. <<
284 depends on !SHADOW_CALL_STACK || RUSTC <<
285 <<
286 config CLANG_SUPPORTS_DYNAMIC_FTRACE_WITH_ARGS <<
287 def_bool CC_IS_CLANG <<
288 # https://github.com/ClangBuiltLinux/l <<
289 depends on AS_IS_GNU || (AS_IS_LLVM && <<
290 <<
291 config GCC_SUPPORTS_DYNAMIC_FTRACE_WITH_ARGS <<
292 def_bool CC_IS_GCC <<
293 depends on $(cc-option,-fpatchable-fun <<
294 <<
295 config 64BIT <<
296 def_bool y <<
297 <<
298 config MMU <<
299 def_bool y <<
300 <<
301 config ARM64_CONT_PTE_SHIFT <<
302 int <<
303 default 5 if PAGE_SIZE_64KB <<
304 default 7 if PAGE_SIZE_16KB <<
305 default 4 <<
306 <<
307 config ARM64_CONT_PMD_SHIFT <<
308 int <<
309 default 5 if PAGE_SIZE_64KB <<
310 default 5 if PAGE_SIZE_16KB <<
311 default 4 <<
312 <<
313 config ARCH_MMAP_RND_BITS_MIN <<
314 default 14 if PAGE_SIZE_64KB <<
315 default 16 if PAGE_SIZE_16KB <<
316 default 18 <<
317 <<
318 # max bits determined by the following formula <<
319 # VA_BITS - PAGE_SHIFT - 3 <<
320 config ARCH_MMAP_RND_BITS_MAX <<
321 default 19 if ARM64_VA_BITS=36 <<
322 default 24 if ARM64_VA_BITS=39 <<
323 default 27 if ARM64_VA_BITS=42 <<
324 default 30 if ARM64_VA_BITS=47 <<
325 default 29 if ARM64_VA_BITS=48 && ARM6 <<
326 default 31 if ARM64_VA_BITS=48 && ARM6 <<
327 default 33 if ARM64_VA_BITS=48 <<
328 default 14 if ARM64_64K_PAGES <<
329 default 16 if ARM64_16K_PAGES <<
330 default 18 <<
331 <<
332 config ARCH_MMAP_RND_COMPAT_BITS_MIN <<
333 default 7 if ARM64_64K_PAGES <<
334 default 9 if ARM64_16K_PAGES <<
335 default 11 <<
336 11
337 config ARCH_MMAP_RND_COMPAT_BITS_MAX !! 12 mainmenu "Linux/MIPS Kernel Configuration"
338 default 16 <<
339 13
340 config NO_IOPORT_MAP !! 14 menu "Machine selection"
341 def_bool y if !PCI <<
342 15
343 config STACKTRACE_SUPPORT !! 16 config ZONE_DMA
344 def_bool y !! 17 bool
345 <<
346 config ILLEGAL_POINTER_VALUE <<
347 hex <<
348 default 0xdead000000000000 <<
349 <<
350 config LOCKDEP_SUPPORT <<
351 def_bool y <<
352 <<
353 config GENERIC_BUG <<
354 def_bool y <<
355 depends on BUG <<
356 <<
357 config GENERIC_BUG_RELATIVE_POINTERS <<
358 def_bool y <<
359 depends on GENERIC_BUG <<
360 <<
361 config GENERIC_HWEIGHT <<
362 def_bool y <<
363 <<
364 config GENERIC_CSUM <<
365 def_bool y <<
366 18
367 config GENERIC_CALIBRATE_DELAY !! 19 choice
368 def_bool y !! 20 prompt "System type"
>> 21 default SGI_IP22
369 22
370 config SMP !! 23 config MACH_ALCHEMY
371 def_bool y !! 24 bool "Alchemy processor based machines"
372 25
373 config KERNEL_MODE_NEON !! 26 config AR7
374 def_bool y !! 27 bool "Texas Instruments AR7"
>> 28 select BOOT_ELF32
>> 29 select DMA_NONCOHERENT
>> 30 select CEVT_R4K
>> 31 select CSRC_R4K
>> 32 select IRQ_CPU
>> 33 select NO_EXCEPT_FILL
>> 34 select SWAP_IO_SPACE
>> 35 select SYS_HAS_CPU_MIPS32_R1
>> 36 select SYS_HAS_EARLY_PRINTK
>> 37 select SYS_SUPPORTS_32BIT_KERNEL
>> 38 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 39 select GENERIC_GPIO
>> 40 select GCD
>> 41 select VLYNQ
>> 42 help
>> 43 Support for the Texas Instruments AR7 System-on-a-Chip
>> 44 family: TNETD7100, 7200 and 7300.
>> 45
>> 46 config BASLER_EXCITE
>> 47 bool "Basler eXcite smart camera"
>> 48 select CEVT_R4K
>> 49 select CSRC_R4K
>> 50 select DMA_COHERENT
>> 51 select HW_HAS_PCI
>> 52 select IRQ_CPU
>> 53 select IRQ_CPU_RM7K
>> 54 select IRQ_CPU_RM9K
>> 55 select MIPS_RM9122
>> 56 select SYS_HAS_CPU_RM9000
>> 57 select SYS_SUPPORTS_32BIT_KERNEL
>> 58 select SYS_SUPPORTS_BIG_ENDIAN
>> 59 help
>> 60 The eXcite is a smart camera platform manufactured by
>> 61 Basler Vision Technologies AG.
>> 62
>> 63 config BCM47XX
>> 64 bool "BCM47XX based boards"
>> 65 select CEVT_R4K
>> 66 select CSRC_R4K
>> 67 select DMA_NONCOHERENT
>> 68 select HW_HAS_PCI
>> 69 select IRQ_CPU
>> 70 select SYS_HAS_CPU_MIPS32_R1
>> 71 select SYS_SUPPORTS_32BIT_KERNEL
>> 72 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 73 select SSB
>> 74 select SSB_DRIVER_MIPS
>> 75 select SSB_DRIVER_EXTIF
>> 76 select SSB_EMBEDDED
>> 77 select SSB_PCICORE_HOSTMODE if PCI
>> 78 select GENERIC_GPIO
>> 79 select SYS_HAS_EARLY_PRINTK
>> 80 select CFE
>> 81 help
>> 82 Support for BCM47XX based boards
>> 83
>> 84 config BCM63XX
>> 85 bool "Broadcom BCM63XX based boards"
>> 86 select CEVT_R4K
>> 87 select CSRC_R4K
>> 88 select DMA_NONCOHERENT
>> 89 select IRQ_CPU
>> 90 select SYS_HAS_CPU_MIPS32_R1
>> 91 select SYS_SUPPORTS_32BIT_KERNEL
>> 92 select SYS_SUPPORTS_BIG_ENDIAN
>> 93 select SYS_HAS_EARLY_PRINTK
>> 94 select SWAP_IO_SPACE
>> 95 select ARCH_REQUIRE_GPIOLIB
>> 96 help
>> 97 Support for BCM63XX based boards
>> 98
>> 99 config MIPS_COBALT
>> 100 bool "Cobalt Server"
>> 101 select CEVT_R4K
>> 102 select CSRC_R4K
>> 103 select CEVT_GT641XX
>> 104 select DMA_NONCOHERENT
>> 105 select HW_HAS_PCI
>> 106 select I8253
>> 107 select I8259
>> 108 select IRQ_CPU
>> 109 select IRQ_GT641XX
>> 110 select PCI_GT64XXX_PCI0
>> 111 select PCI
>> 112 select SYS_HAS_CPU_NEVADA
>> 113 select SYS_HAS_EARLY_PRINTK
>> 114 select SYS_SUPPORTS_32BIT_KERNEL
>> 115 select SYS_SUPPORTS_64BIT_KERNEL
>> 116 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 117
>> 118 config MACH_DECSTATION
>> 119 bool "DECstations"
>> 120 select BOOT_ELF32
>> 121 select CEVT_DS1287
>> 122 select CEVT_R4K
>> 123 select CSRC_IOASIC
>> 124 select CSRC_R4K
>> 125 select CPU_DADDI_WORKAROUNDS if 64BIT
>> 126 select CPU_R4000_WORKAROUNDS if 64BIT
>> 127 select CPU_R4400_WORKAROUNDS if 64BIT
>> 128 select DMA_NONCOHERENT
>> 129 select NO_IOPORT
>> 130 select IRQ_CPU
>> 131 select SYS_HAS_CPU_R3000
>> 132 select SYS_HAS_CPU_R4X00
>> 133 select SYS_SUPPORTS_32BIT_KERNEL
>> 134 select SYS_SUPPORTS_64BIT_KERNEL if EXPERIMENTAL
>> 135 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 136 select SYS_SUPPORTS_128HZ
>> 137 select SYS_SUPPORTS_256HZ
>> 138 select SYS_SUPPORTS_1024HZ
>> 139 help
>> 140 This enables support for DEC's MIPS based workstations. For details
>> 141 see the Linux/MIPS FAQ on <http://www.linux-mips.org/> and the
>> 142 DECstation porting pages on <http://decstation.unix-ag.org/>.
>> 143
>> 144 If you have one of the following DECstation Models you definitely
>> 145 want to choose R4xx0 for the CPU Type:
>> 146
>> 147 DECstation 5000/50
>> 148 DECstation 5000/150
>> 149 DECstation 5000/260
>> 150 DECsystem 5900/260
>> 151
>> 152 otherwise choose R3000.
>> 153
>> 154 config MACH_JAZZ
>> 155 bool "Jazz family of machines"
>> 156 select ARC
>> 157 select ARC32
>> 158 select ARCH_MAY_HAVE_PC_FDC
>> 159 select CEVT_R4K
>> 160 select CSRC_R4K
>> 161 select DEFAULT_SGI_PARTITION if CPU_BIG_ENDIAN
>> 162 select GENERIC_ISA_DMA
>> 163 select IRQ_CPU
>> 164 select I8253
>> 165 select I8259
>> 166 select ISA
>> 167 select SYS_HAS_CPU_R4X00
>> 168 select SYS_SUPPORTS_32BIT_KERNEL
>> 169 select SYS_SUPPORTS_64BIT_KERNEL if EXPERIMENTAL
>> 170 select SYS_SUPPORTS_100HZ
>> 171 help
>> 172 This a family of machines based on the MIPS R4030 chipset which was
>> 173 used by several vendors to build RISC/os and Windows NT workstations.
>> 174 Members include the Acer PICA, MIPS Magnum 4000, MIPS Millennium and
>> 175 Olivetti M700-10 workstations.
>> 176
>> 177 config LASAT
>> 178 bool "LASAT Networks platforms"
>> 179 select CEVT_R4K
>> 180 select CSRC_R4K
>> 181 select DMA_NONCOHERENT
>> 182 select SYS_HAS_EARLY_PRINTK
>> 183 select HW_HAS_PCI
>> 184 select IRQ_CPU
>> 185 select PCI_GT64XXX_PCI0
>> 186 select MIPS_NILE4
>> 187 select R5000_CPU_SCACHE
>> 188 select SYS_HAS_CPU_R5000
>> 189 select SYS_SUPPORTS_32BIT_KERNEL
>> 190 select SYS_SUPPORTS_64BIT_KERNEL if BROKEN
>> 191 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 192
>> 193 config MACH_LOONGSON
>> 194 bool "Loongson family of machines"
>> 195 help
>> 196 This enables the support of Loongson family of machines.
>> 197
>> 198 Loongson is a family of general-purpose MIPS-compatible CPUs.
>> 199 developed at Institute of Computing Technology (ICT),
>> 200 Chinese Academy of Sciences (CAS) in the People's Republic
>> 201 of China. The chief architect is Professor Weiwu Hu.
>> 202
>> 203 config MIPS_MALTA
>> 204 bool "MIPS Malta board"
>> 205 select ARCH_MAY_HAVE_PC_FDC
>> 206 select BOOT_ELF32
>> 207 select BOOT_RAW
>> 208 select CEVT_R4K
>> 209 select CSRC_R4K
>> 210 select DMA_NONCOHERENT
>> 211 select GENERIC_ISA_DMA
>> 212 select IRQ_CPU
>> 213 select IRQ_GIC
>> 214 select HW_HAS_PCI
>> 215 select I8253
>> 216 select I8259
>> 217 select MIPS_BOARDS_GEN
>> 218 select MIPS_BONITO64
>> 219 select MIPS_CPU_SCACHE
>> 220 select PCI_GT64XXX_PCI0
>> 221 select MIPS_MSC
>> 222 select SWAP_IO_SPACE
>> 223 select SYS_HAS_CPU_MIPS32_R1
>> 224 select SYS_HAS_CPU_MIPS32_R2
>> 225 select SYS_HAS_CPU_MIPS64_R1
>> 226 select SYS_HAS_CPU_NEVADA
>> 227 select SYS_HAS_CPU_RM7000
>> 228 select SYS_HAS_EARLY_PRINTK
>> 229 select SYS_SUPPORTS_32BIT_KERNEL
>> 230 select SYS_SUPPORTS_64BIT_KERNEL
>> 231 select SYS_SUPPORTS_BIG_ENDIAN
>> 232 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 233 select SYS_SUPPORTS_MIPS_CMP
>> 234 select SYS_SUPPORTS_MULTITHREADING
>> 235 select SYS_SUPPORTS_SMARTMIPS
>> 236 help
>> 237 This enables support for the MIPS Technologies Malta evaluation
>> 238 board.
>> 239
>> 240 config MIPS_SIM
>> 241 bool 'MIPS simulator (MIPSsim)'
>> 242 select CEVT_R4K
>> 243 select CSRC_R4K
>> 244 select DMA_NONCOHERENT
>> 245 select SYS_HAS_EARLY_PRINTK
>> 246 select IRQ_CPU
>> 247 select BOOT_RAW
>> 248 select SYS_HAS_CPU_MIPS32_R1
>> 249 select SYS_HAS_CPU_MIPS32_R2
>> 250 select SYS_HAS_EARLY_PRINTK
>> 251 select SYS_SUPPORTS_32BIT_KERNEL
>> 252 select SYS_SUPPORTS_BIG_ENDIAN
>> 253 select SYS_SUPPORTS_MULTITHREADING
>> 254 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 255 help
>> 256 This option enables support for MIPS Technologies MIPSsim software
>> 257 emulator.
>> 258
>> 259 config NEC_MARKEINS
>> 260 bool "NEC EMMA2RH Mark-eins board"
>> 261 select SOC_EMMA2RH
>> 262 select HW_HAS_PCI
>> 263 help
>> 264 This enables support for the NEC Electronics Mark-eins boards.
>> 265
>> 266 config MACH_VR41XX
>> 267 bool "NEC VR4100 series based machines"
>> 268 select CEVT_R4K
>> 269 select CSRC_R4K
>> 270 select SYS_HAS_CPU_VR41XX
>> 271 select ARCH_REQUIRE_GPIOLIB
>> 272
>> 273 config NXP_STB220
>> 274 bool "NXP STB220 board"
>> 275 select SOC_PNX833X
>> 276 help
>> 277 Support for NXP Semiconductors STB220 Development Board.
>> 278
>> 279 config NXP_STB225
>> 280 bool "NXP 225 board"
>> 281 select SOC_PNX833X
>> 282 select SOC_PNX8335
>> 283 help
>> 284 Support for NXP Semiconductors STB225 Development Board.
>> 285
>> 286 config PNX8550_JBS
>> 287 bool "NXP PNX8550 based JBS board"
>> 288 select PNX8550
>> 289 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 290
>> 291 config PNX8550_STB810
>> 292 bool "NXP PNX8550 based STB810 board"
>> 293 select PNX8550
>> 294 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 295
>> 296 config PMC_MSP
>> 297 bool "PMC-Sierra MSP chipsets"
>> 298 depends on EXPERIMENTAL
>> 299 select DMA_NONCOHERENT
>> 300 select SWAP_IO_SPACE
>> 301 select NO_EXCEPT_FILL
>> 302 select BOOT_RAW
>> 303 select SYS_HAS_CPU_MIPS32_R1
>> 304 select SYS_HAS_CPU_MIPS32_R2
>> 305 select SYS_SUPPORTS_32BIT_KERNEL
>> 306 select SYS_SUPPORTS_BIG_ENDIAN
>> 307 select IRQ_CPU
>> 308 select SERIAL_8250
>> 309 select SERIAL_8250_CONSOLE
>> 310 help
>> 311 This adds support for the PMC-Sierra family of Multi-Service
>> 312 Processor System-On-A-Chips. These parts include a number
>> 313 of integrated peripherals, interfaces and DSPs in addition to
>> 314 a variety of MIPS cores.
>> 315
>> 316 config PMC_YOSEMITE
>> 317 bool "PMC-Sierra Yosemite eval board"
>> 318 select CEVT_R4K
>> 319 select CSRC_R4K
>> 320 select DMA_COHERENT
>> 321 select HW_HAS_PCI
>> 322 select IRQ_CPU
>> 323 select IRQ_CPU_RM7K
>> 324 select IRQ_CPU_RM9K
>> 325 select SWAP_IO_SPACE
>> 326 select SYS_HAS_CPU_RM9000
>> 327 select SYS_HAS_EARLY_PRINTK
>> 328 select SYS_SUPPORTS_32BIT_KERNEL
>> 329 select SYS_SUPPORTS_64BIT_KERNEL
>> 330 select SYS_SUPPORTS_BIG_ENDIAN
>> 331 select SYS_SUPPORTS_HIGHMEM
>> 332 select SYS_SUPPORTS_SMP
>> 333 help
>> 334 Yosemite is an evaluation board for the RM9000x2 processor
>> 335 manufactured by PMC-Sierra.
>> 336
>> 337 config SGI_IP22
>> 338 bool "SGI IP22 (Indy/Indigo2)"
>> 339 select ARC
>> 340 select ARC32
>> 341 select BOOT_ELF32
>> 342 select CEVT_R4K
>> 343 select CSRC_R4K
>> 344 select DEFAULT_SGI_PARTITION
>> 345 select DMA_NONCOHERENT
>> 346 select HW_HAS_EISA
>> 347 select I8253
>> 348 select I8259
>> 349 select IP22_CPU_SCACHE
>> 350 select IRQ_CPU
>> 351 select GENERIC_ISA_DMA_SUPPORT_BROKEN
>> 352 select SGI_HAS_I8042
>> 353 select SGI_HAS_INDYDOG
>> 354 select SGI_HAS_HAL2
>> 355 select SGI_HAS_SEEQ
>> 356 select SGI_HAS_WD93
>> 357 select SGI_HAS_ZILOG
>> 358 select SWAP_IO_SPACE
>> 359 select SYS_HAS_CPU_R4X00
>> 360 select SYS_HAS_CPU_R5000
>> 361 #
>> 362 # Disable EARLY_PRINTK for now since it leads to overwritten prom
>> 363 # memory during early boot on some machines.
>> 364 #
>> 365 # See http://www.linux-mips.org/cgi-bin/mesg.cgi?a=linux-mips&i=20091119164009.GA15038%40deprecation.cyrius.com
>> 366 # for a more details discussion
>> 367 #
>> 368 # select SYS_HAS_EARLY_PRINTK
>> 369 select SYS_SUPPORTS_32BIT_KERNEL
>> 370 select SYS_SUPPORTS_64BIT_KERNEL
>> 371 select SYS_SUPPORTS_BIG_ENDIAN
>> 372 help
>> 373 This are the SGI Indy, Challenge S and Indigo2, as well as certain
>> 374 OEM variants like the Tandem CMN B006S. To compile a Linux kernel
>> 375 that runs on these, say Y here.
>> 376
>> 377 config SGI_IP27
>> 378 bool "SGI IP27 (Origin200/2000)"
>> 379 select ARC
>> 380 select ARC64
>> 381 select BOOT_ELF64
>> 382 select DEFAULT_SGI_PARTITION
>> 383 select DMA_COHERENT
>> 384 select SYS_HAS_EARLY_PRINTK
>> 385 select HW_HAS_PCI
>> 386 select NR_CPUS_DEFAULT_64
>> 387 select SYS_HAS_CPU_R10000
>> 388 select SYS_SUPPORTS_64BIT_KERNEL
>> 389 select SYS_SUPPORTS_BIG_ENDIAN
>> 390 select SYS_SUPPORTS_NUMA
>> 391 select SYS_SUPPORTS_SMP
>> 392 help
>> 393 This are the SGI Origin 200, Origin 2000 and Onyx 2 Graphics
>> 394 workstations. To compile a Linux kernel that runs on these, say Y
>> 395 here.
>> 396
>> 397 config SGI_IP28
>> 398 bool "SGI IP28 (Indigo2 R10k) (EXPERIMENTAL)"
>> 399 depends on EXPERIMENTAL
>> 400 select ARC
>> 401 select ARC64
>> 402 select BOOT_ELF64
>> 403 select CEVT_R4K
>> 404 select CSRC_R4K
>> 405 select DEFAULT_SGI_PARTITION
>> 406 select DMA_NONCOHERENT
>> 407 select GENERIC_ISA_DMA_SUPPORT_BROKEN
>> 408 select IRQ_CPU
>> 409 select HW_HAS_EISA
>> 410 select I8253
>> 411 select I8259
>> 412 select SGI_HAS_I8042
>> 413 select SGI_HAS_INDYDOG
>> 414 select SGI_HAS_HAL2
>> 415 select SGI_HAS_SEEQ
>> 416 select SGI_HAS_WD93
>> 417 select SGI_HAS_ZILOG
>> 418 select SWAP_IO_SPACE
>> 419 select SYS_HAS_CPU_R10000
>> 420 #
>> 421 # Disable EARLY_PRINTK for now since it leads to overwritten prom
>> 422 # memory during early boot on some machines.
>> 423 #
>> 424 # See http://www.linux-mips.org/cgi-bin/mesg.cgi?a=linux-mips&i=20091119164009.GA15038%40deprecation.cyrius.com
>> 425 # for a more details discussion
>> 426 #
>> 427 # select SYS_HAS_EARLY_PRINTK
>> 428 select SYS_SUPPORTS_64BIT_KERNEL
>> 429 select SYS_SUPPORTS_BIG_ENDIAN
>> 430 help
>> 431 This is the SGI Indigo2 with R10000 processor. To compile a Linux
>> 432 kernel that runs on these, say Y here.
>> 433
>> 434 config SGI_IP32
>> 435 bool "SGI IP32 (O2)"
>> 436 select ARC
>> 437 select ARC32
>> 438 select BOOT_ELF32
>> 439 select CEVT_R4K
>> 440 select CSRC_R4K
>> 441 select DMA_NONCOHERENT
>> 442 select HW_HAS_PCI
>> 443 select IRQ_CPU
>> 444 select R5000_CPU_SCACHE
>> 445 select RM7000_CPU_SCACHE
>> 446 select SYS_HAS_CPU_R5000
>> 447 select SYS_HAS_CPU_R10000 if BROKEN
>> 448 select SYS_HAS_CPU_RM7000
>> 449 select SYS_HAS_CPU_NEVADA
>> 450 select SYS_SUPPORTS_64BIT_KERNEL
>> 451 select SYS_SUPPORTS_BIG_ENDIAN
>> 452 help
>> 453 If you want this kernel to run on SGI O2 workstation, say Y here.
>> 454
>> 455 config SIBYTE_CRHINE
>> 456 bool "Sibyte BCM91120C-CRhine"
>> 457 depends on EXPERIMENTAL
>> 458 select BOOT_ELF32
>> 459 select DMA_COHERENT
>> 460 select SIBYTE_BCM1120
>> 461 select SWAP_IO_SPACE
>> 462 select SYS_HAS_CPU_SB1
>> 463 select SYS_SUPPORTS_BIG_ENDIAN
>> 464 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 465
>> 466 config SIBYTE_CARMEL
>> 467 bool "Sibyte BCM91120x-Carmel"
>> 468 depends on EXPERIMENTAL
>> 469 select BOOT_ELF32
>> 470 select DMA_COHERENT
>> 471 select SIBYTE_BCM1120
>> 472 select SWAP_IO_SPACE
>> 473 select SYS_HAS_CPU_SB1
>> 474 select SYS_SUPPORTS_BIG_ENDIAN
>> 475 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 476
>> 477 config SIBYTE_CRHONE
>> 478 bool "Sibyte BCM91125C-CRhone"
>> 479 depends on EXPERIMENTAL
>> 480 select BOOT_ELF32
>> 481 select DMA_COHERENT
>> 482 select SIBYTE_BCM1125
>> 483 select SWAP_IO_SPACE
>> 484 select SYS_HAS_CPU_SB1
>> 485 select SYS_SUPPORTS_BIG_ENDIAN
>> 486 select SYS_SUPPORTS_HIGHMEM
>> 487 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 488
>> 489 config SIBYTE_RHONE
>> 490 bool "Sibyte BCM91125E-Rhone"
>> 491 depends on EXPERIMENTAL
>> 492 select BOOT_ELF32
>> 493 select DMA_COHERENT
>> 494 select SIBYTE_BCM1125H
>> 495 select SWAP_IO_SPACE
>> 496 select SYS_HAS_CPU_SB1
>> 497 select SYS_SUPPORTS_BIG_ENDIAN
>> 498 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 499
>> 500 config SIBYTE_SWARM
>> 501 bool "Sibyte BCM91250A-SWARM"
>> 502 select BOOT_ELF32
>> 503 select DMA_COHERENT
>> 504 select NR_CPUS_DEFAULT_2
>> 505 select SIBYTE_SB1250
>> 506 select SWAP_IO_SPACE
>> 507 select SYS_HAS_CPU_SB1
>> 508 select SYS_SUPPORTS_BIG_ENDIAN
>> 509 select SYS_SUPPORTS_HIGHMEM
>> 510 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 511 select ZONE_DMA32 if 64BIT
>> 512
>> 513 config SIBYTE_LITTLESUR
>> 514 bool "Sibyte BCM91250C2-LittleSur"
>> 515 depends on EXPERIMENTAL
>> 516 select BOOT_ELF32
>> 517 select DMA_COHERENT
>> 518 select NR_CPUS_DEFAULT_2
>> 519 select SIBYTE_SB1250
>> 520 select SWAP_IO_SPACE
>> 521 select SYS_HAS_CPU_SB1
>> 522 select SYS_SUPPORTS_BIG_ENDIAN
>> 523 select SYS_SUPPORTS_HIGHMEM
>> 524 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 525
>> 526 config SIBYTE_SENTOSA
>> 527 bool "Sibyte BCM91250E-Sentosa"
>> 528 depends on EXPERIMENTAL
>> 529 select BOOT_ELF32
>> 530 select DMA_COHERENT
>> 531 select NR_CPUS_DEFAULT_2
>> 532 select SIBYTE_SB1250
>> 533 select SWAP_IO_SPACE
>> 534 select SYS_HAS_CPU_SB1
>> 535 select SYS_SUPPORTS_BIG_ENDIAN
>> 536 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 537
>> 538 config SIBYTE_BIGSUR
>> 539 bool "Sibyte BCM91480B-BigSur"
>> 540 select BOOT_ELF32
>> 541 select DMA_COHERENT
>> 542 select NR_CPUS_DEFAULT_4
>> 543 select SIBYTE_BCM1x80
>> 544 select SWAP_IO_SPACE
>> 545 select SYS_HAS_CPU_SB1
>> 546 select SYS_SUPPORTS_BIG_ENDIAN
>> 547 select SYS_SUPPORTS_HIGHMEM
>> 548 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 549 select ZONE_DMA32 if 64BIT
>> 550
>> 551 config SNI_RM
>> 552 bool "SNI RM200/300/400"
>> 553 select ARC if CPU_LITTLE_ENDIAN
>> 554 select ARC32 if CPU_LITTLE_ENDIAN
>> 555 select SNIPROM if CPU_BIG_ENDIAN
>> 556 select ARCH_MAY_HAVE_PC_FDC
>> 557 select BOOT_ELF32
>> 558 select CEVT_R4K
>> 559 select CSRC_R4K
>> 560 select DEFAULT_SGI_PARTITION if CPU_BIG_ENDIAN
>> 561 select DMA_NONCOHERENT
>> 562 select GENERIC_ISA_DMA
>> 563 select HW_HAS_EISA
>> 564 select HW_HAS_PCI
>> 565 select IRQ_CPU
>> 566 select I8253
>> 567 select I8259
>> 568 select ISA
>> 569 select SWAP_IO_SPACE if CPU_BIG_ENDIAN
>> 570 select SYS_HAS_CPU_R4X00
>> 571 select SYS_HAS_CPU_R5000
>> 572 select SYS_HAS_CPU_R10000
>> 573 select R5000_CPU_SCACHE
>> 574 select SYS_HAS_EARLY_PRINTK
>> 575 select SYS_SUPPORTS_32BIT_KERNEL
>> 576 select SYS_SUPPORTS_64BIT_KERNEL if EXPERIMENTAL
>> 577 select SYS_SUPPORTS_BIG_ENDIAN
>> 578 select SYS_SUPPORTS_HIGHMEM
>> 579 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 580 help
>> 581 The SNI RM200/300/400 are MIPS-based machines manufactured by
>> 582 Siemens Nixdorf Informationssysteme (SNI), parent company of Pyramid
>> 583 Technology and now in turn merged with Fujitsu. Say Y here to
>> 584 support this machine type.
>> 585
>> 586 config MACH_TX39XX
>> 587 bool "Toshiba TX39 series based machines"
>> 588
>> 589 config MACH_TX49XX
>> 590 bool "Toshiba TX49 series based machines"
>> 591
>> 592 config MIKROTIK_RB532
>> 593 bool "Mikrotik RB532 boards"
>> 594 select CEVT_R4K
>> 595 select CSRC_R4K
>> 596 select DMA_NONCOHERENT
>> 597 select HW_HAS_PCI
>> 598 select IRQ_CPU
>> 599 select SYS_HAS_CPU_MIPS32_R1
>> 600 select SYS_SUPPORTS_32BIT_KERNEL
>> 601 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 602 select SWAP_IO_SPACE
>> 603 select BOOT_RAW
>> 604 select ARCH_REQUIRE_GPIOLIB
>> 605 help
>> 606 Support the Mikrotik(tm) RouterBoard 532 series,
>> 607 based on the IDT RC32434 SoC.
>> 608
>> 609 config WR_PPMC
>> 610 bool "Wind River PPMC board"
>> 611 select CEVT_R4K
>> 612 select CSRC_R4K
>> 613 select IRQ_CPU
>> 614 select BOOT_ELF32
>> 615 select DMA_NONCOHERENT
>> 616 select HW_HAS_PCI
>> 617 select PCI_GT64XXX_PCI0
>> 618 select SWAP_IO_SPACE
>> 619 select SYS_HAS_CPU_MIPS32_R1
>> 620 select SYS_HAS_CPU_MIPS32_R2
>> 621 select SYS_HAS_CPU_MIPS64_R1
>> 622 select SYS_HAS_CPU_NEVADA
>> 623 select SYS_HAS_CPU_RM7000
>> 624 select SYS_SUPPORTS_32BIT_KERNEL
>> 625 select SYS_SUPPORTS_64BIT_KERNEL
>> 626 select SYS_SUPPORTS_BIG_ENDIAN
>> 627 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 628 help
>> 629 This enables support for the Wind River MIPS32 4KC PPMC evaluation
>> 630 board, which is based on GT64120 bridge chip.
>> 631
>> 632 config CAVIUM_OCTEON_SIMULATOR
>> 633 bool "Cavium Networks Octeon Simulator"
>> 634 select CEVT_R4K
>> 635 select 64BIT_PHYS_ADDR
>> 636 select DMA_COHERENT
>> 637 select SYS_SUPPORTS_64BIT_KERNEL
>> 638 select SYS_SUPPORTS_BIG_ENDIAN
>> 639 select SYS_SUPPORTS_HIGHMEM
>> 640 select SYS_SUPPORTS_HOTPLUG_CPU
>> 641 select SYS_HAS_CPU_CAVIUM_OCTEON
>> 642 help
>> 643 The Octeon simulator is software performance model of the Cavium
>> 644 Octeon Processor. It supports simulating Octeon processors on x86
>> 645 hardware.
>> 646
>> 647 config CAVIUM_OCTEON_REFERENCE_BOARD
>> 648 bool "Cavium Networks Octeon reference board"
>> 649 select CEVT_R4K
>> 650 select 64BIT_PHYS_ADDR
>> 651 select DMA_COHERENT
>> 652 select SYS_SUPPORTS_64BIT_KERNEL
>> 653 select SYS_SUPPORTS_BIG_ENDIAN
>> 654 select SYS_SUPPORTS_HIGHMEM
>> 655 select SYS_SUPPORTS_HOTPLUG_CPU
>> 656 select SYS_HAS_EARLY_PRINTK
>> 657 select SYS_HAS_CPU_CAVIUM_OCTEON
>> 658 select SWAP_IO_SPACE
>> 659 select HW_HAS_PCI
>> 660 select ARCH_SUPPORTS_MSI
>> 661 help
>> 662 This option supports all of the Octeon reference boards from Cavium
>> 663 Networks. It builds a kernel that dynamically determines the Octeon
>> 664 CPU type and supports all known board reference implementations.
>> 665 Some of the supported boards are:
>> 666 EBT3000
>> 667 EBH3000
>> 668 EBH3100
>> 669 Thunder
>> 670 Kodama
>> 671 Hikari
>> 672 Say Y here for most Octeon reference boards.
375 673
376 config FIX_EARLYCON_MEM !! 674 endchoice
377 def_bool y <<
378 675
379 config PGTABLE_LEVELS !! 676 source "arch/mips/alchemy/Kconfig"
380 int !! 677 source "arch/mips/basler/excite/Kconfig"
381 default 2 if ARM64_16K_PAGES && ARM64_ !! 678 source "arch/mips/bcm63xx/Kconfig"
382 default 2 if ARM64_64K_PAGES && ARM64_ !! 679 source "arch/mips/jazz/Kconfig"
383 default 3 if ARM64_64K_PAGES && (ARM64 !! 680 source "arch/mips/lasat/Kconfig"
384 default 3 if ARM64_4K_PAGES && ARM64_V !! 681 source "arch/mips/pmc-sierra/Kconfig"
385 default 3 if ARM64_16K_PAGES && ARM64_ !! 682 source "arch/mips/sgi-ip27/Kconfig"
386 default 4 if ARM64_16K_PAGES && (ARM64 !! 683 source "arch/mips/sibyte/Kconfig"
387 default 4 if !ARM64_64K_PAGES && ARM64 !! 684 source "arch/mips/txx9/Kconfig"
388 default 5 if ARM64_4K_PAGES && ARM64_V !! 685 source "arch/mips/vr41xx/Kconfig"
>> 686 source "arch/mips/cavium-octeon/Kconfig"
>> 687 source "arch/mips/loongson/Kconfig"
389 688
390 config ARCH_SUPPORTS_UPROBES !! 689 endmenu
391 def_bool y <<
392 690
393 config ARCH_PROC_KCORE_TEXT !! 691 config RWSEM_GENERIC_SPINLOCK
394 def_bool y !! 692 bool
>> 693 default y
395 694
396 config BROKEN_GAS_INST !! 695 config RWSEM_XCHGADD_ALGORITHM
397 def_bool !$(as-instr,1:\n.inst 0\n.rep !! 696 bool
398 697
399 config BUILTIN_RETURN_ADDRESS_STRIPS_PAC !! 698 config ARCH_HAS_ILOG2_U32
400 bool 699 bool
401 # Clang's __builtin_return_address() s <<
402 # https://github.com/llvm/llvm-project <<
403 default y if CC_IS_CLANG <<
404 # GCC's __builtin_return_address() str <<
405 # and this was backported to 10.2.0, 9 <<
406 # https://gcc.gnu.org/bugzilla/show_bu <<
407 default y if CC_IS_GCC && (GCC_VERSION <<
408 default y if CC_IS_GCC && (GCC_VERSION <<
409 default y if CC_IS_GCC && (GCC_VERSION <<
410 default y if CC_IS_GCC && (GCC_VERSION <<
411 default n 700 default n
412 701
413 config KASAN_SHADOW_OFFSET !! 702 config ARCH_HAS_ILOG2_U64
414 hex <<
415 depends on KASAN_GENERIC || KASAN_SW_T <<
416 default 0xdfff800000000000 if (ARM64_V <<
417 default 0xdfffc00000000000 if (ARM64_V <<
418 default 0xdffffe0000000000 if ARM64_VA <<
419 default 0xdfffffc000000000 if ARM64_VA <<
420 default 0xdffffff800000000 if ARM64_VA <<
421 default 0xefff800000000000 if (ARM64_V <<
422 default 0xefffc00000000000 if (ARM64_V <<
423 default 0xeffffe0000000000 if ARM64_VA <<
424 default 0xefffffc000000000 if ARM64_VA <<
425 default 0xeffffff800000000 if ARM64_VA <<
426 default 0xffffffffffffffff <<
427 <<
428 config UNWIND_TABLES <<
429 bool <<
430 <<
431 source "arch/arm64/Kconfig.platforms" <<
432 <<
433 menu "Kernel Features" <<
434 <<
435 menu "ARM errata workarounds via the alternati <<
436 <<
437 config AMPERE_ERRATUM_AC03_CPU_38 <<
438 bool "AmpereOne: AC03_CPU_38: Certain <<
439 default y <<
440 help <<
441 This option adds an alternative code <<
442 errata AC03_CPU_38 and AC04_CPU_10 o <<
443 <<
444 The affected design reports FEAT_HAF <<
445 ID_AA64MMFR1_EL1.HAFDBS, but (V)TCR_ <<
446 as required by the architecture. The <<
447 implementation suffers from an addit <<
448 A/D updates can occur after a PTE ha <<
449 <<
450 The workaround forces KVM to explici <<
451 which avoids enabling unadvertised h <<
452 at stage-2. <<
453 <<
454 If unsure, say Y. <<
455 <<
456 config ARM64_WORKAROUND_CLEAN_CACHE <<
457 bool 703 bool
>> 704 default n
458 705
459 config ARM64_ERRATUM_826319 !! 706 config ARCH_SUPPORTS_OPROFILE
460 bool "Cortex-A53: 826319: System might !! 707 bool
461 default y !! 708 default y if !MIPS_MT_SMTC
462 select ARM64_WORKAROUND_CLEAN_CACHE <<
463 help <<
464 This option adds an alternative code <<
465 erratum 826319 on Cortex-A53 parts u <<
466 AXI master interface and an L2 cache <<
467 <<
468 If a Cortex-A53 uses an AMBA AXI4 AC <<
469 and is unable to accept a certain wr <<
470 not progress on read data presented <<
471 system can deadlock. <<
472 <<
473 The workaround promotes data cache c <<
474 data cache clean-and-invalidate. <<
475 Please note that this does not neces <<
476 as it depends on the alternative fra <<
477 the kernel if an affected CPU is det <<
478 <<
479 If unsure, say Y. <<
480 709
481 config ARM64_ERRATUM_827319 !! 710 config GENERIC_FIND_NEXT_BIT
482 bool "Cortex-A53: 827319: Data cache c !! 711 bool
483 default y 712 default y
484 select ARM64_WORKAROUND_CLEAN_CACHE <<
485 help <<
486 This option adds an alternative code <<
487 erratum 827319 on Cortex-A53 parts u <<
488 master interface and an L2 cache. <<
489 <<
490 Under certain conditions this erratu <<
491 to occur at the same time as another <<
492 on the AMBA 5 CHI interface, which c <<
493 interconnect reorders the two transa <<
494 <<
495 The workaround promotes data cache c <<
496 data cache clean-and-invalidate. <<
497 Please note that this does not neces <<
498 as it depends on the alternative fra <<
499 the kernel if an affected CPU is det <<
500 <<
501 If unsure, say Y. <<
502 713
503 config ARM64_ERRATUM_824069 !! 714 config GENERIC_HWEIGHT
504 bool "Cortex-A53: 824069: Cache line m !! 715 bool
505 default y 716 default y
506 select ARM64_WORKAROUND_CLEAN_CACHE <<
507 help <<
508 This option adds an alternative code <<
509 erratum 824069 on Cortex-A53 parts u <<
510 to a coherent interconnect. <<
511 <<
512 If a Cortex-A53 processor is executi <<
513 write instruction at the same time a <<
514 cluster is executing a cache mainten <<
515 address, then this erratum might cau <<
516 incorrectly marked as dirty. <<
517 <<
518 The workaround promotes data cache c <<
519 data cache clean-and-invalidate. <<
520 Please note that this option does no <<
521 workaround, as it depends on the alt <<
522 only patch the kernel if an affected <<
523 <<
524 If unsure, say Y. <<
525 717
526 config ARM64_ERRATUM_819472 !! 718 config GENERIC_CALIBRATE_DELAY
527 bool "Cortex-A53: 819472: Store exclus !! 719 bool
528 default y 720 default y
529 select ARM64_WORKAROUND_CLEAN_CACHE <<
530 help <<
531 This option adds an alternative code <<
532 erratum 819472 on Cortex-A53 parts u <<
533 present when it is connected to a co <<
534 <<
535 If the processor is executing a load <<
536 the same time as a processor in anot <<
537 maintenance operation to the same ad <<
538 cause data corruption. <<
539 <<
540 The workaround promotes data cache c <<
541 data cache clean-and-invalidate. <<
542 Please note that this does not neces <<
543 as it depends on the alternative fra <<
544 the kernel if an affected CPU is det <<
545 721
546 If unsure, say Y. !! 722 config GENERIC_CLOCKEVENTS
547 !! 723 bool
548 config ARM64_ERRATUM_832075 <<
549 bool "Cortex-A57: 832075: possible dea <<
550 default y 724 default y
551 help <<
552 This option adds an alternative code <<
553 erratum 832075 on Cortex-A57 parts u <<
554 <<
555 Affected Cortex-A57 parts might dead <<
556 instructions to Write-Back memory ar <<
557 <<
558 The workaround is to promote device <<
559 semantics. <<
560 Please note that this does not neces <<
561 as it depends on the alternative fra <<
562 the kernel if an affected CPU is det <<
563 <<
564 If unsure, say Y. <<
565 <<
566 config ARM64_ERRATUM_834220 <<
567 bool "Cortex-A57: 834220: Stage 2 tran <<
568 depends on KVM <<
569 help <<
570 This option adds an alternative code <<
571 erratum 834220 on Cortex-A57 parts u <<
572 <<
573 Affected Cortex-A57 parts might repo <<
574 fault as the result of a Stage 1 fau <<
575 page boundary when there is a permis <<
576 alignment fault at Stage 1 and a tra <<
577 <<
578 The workaround is to verify that the <<
579 doesn't generate a fault before hand <<
580 Please note that this does not neces <<
581 as it depends on the alternative fra <<
582 the kernel if an affected CPU is det <<
583 <<
584 If unsure, say N. <<
585 725
586 config ARM64_ERRATUM_1742098 !! 726 config GENERIC_TIME
587 bool "Cortex-A57/A72: 1742098: ELR rec !! 727 bool
588 depends on COMPAT <<
589 default y 728 default y
590 help <<
591 This option removes the AES hwcap fo <<
592 workaround erratum 1742098 on Cortex <<
593 <<
594 Affected parts may corrupt the AES s <<
595 taken between a pair of AES instruct <<
596 are only present if the cryptography <<
597 All software should have a fallback <<
598 that don't implement the cryptograph <<
599 <<
600 If unsure, say Y. <<
601 <<
602 config ARM64_ERRATUM_845719 <<
603 bool "Cortex-A53: 845719: a load might <<
604 depends on COMPAT <<
605 default y <<
606 help <<
607 This option adds an alternative code <<
608 erratum 845719 on Cortex-A53 parts u <<
609 <<
610 When running a compat (AArch32) user <<
611 part, a load at EL0 from a virtual a <<
612 bits of the virtual address used by <<
613 might return incorrect data. <<
614 <<
615 The workaround is to write the conte <<
616 return to a 32-bit task. <<
617 Please note that this does not neces <<
618 as it depends on the alternative fra <<
619 the kernel if an affected CPU is det <<
620 729
621 If unsure, say Y. !! 730 config GENERIC_CMOS_UPDATE
622 !! 731 bool
623 config ARM64_ERRATUM_843419 <<
624 bool "Cortex-A53: 843419: A load or st <<
625 default y 732 default y
626 help <<
627 This option links the kernel with '- <<
628 enables PLT support to replace certa <<
629 cause subsequent memory accesses to <<
630 Cortex-A53 parts up to r0p4. <<
631 733
632 If unsure, say Y. !! 734 config SCHED_OMIT_FRAME_POINTER
633 !! 735 bool
634 config ARM64_LD_HAS_FIX_ERRATUM_843419 <<
635 def_bool $(ld-option,--fix-cortex-a53- <<
636 <<
637 config ARM64_ERRATUM_1024718 <<
638 bool "Cortex-A55: 1024718: Update of D <<
639 default y 736 default y
640 help <<
641 This option adds a workaround for AR <<
642 <<
643 Affected Cortex-A55 cores (all revis <<
644 update of the hardware dirty bit whe <<
645 without a break-before-make. The wor <<
646 of hardware DBM locally on the affec <<
647 this erratum will continue to use th <<
648 737
649 If unsure, say Y. !! 738 config GENERIC_HARDIRQS_NO__DO_IRQ
>> 739 def_bool y
650 740
651 config ARM64_ERRATUM_1418040 !! 741 #
652 bool "Cortex-A76/Neoverse-N1: MRC read !! 742 # Select some configuration options automatically based on user selections.
653 default y !! 743 #
654 depends on COMPAT !! 744 config ARC
655 help !! 745 bool
656 This option adds a workaround for AR <<
657 errata 1188873 and 1418040. <<
658 746
659 Affected Cortex-A76/Neoverse-N1 core !! 747 config ARCH_MAY_HAVE_PC_FDC
660 cause register corruption when acces !! 748 bool
661 from AArch32 userspace. <<
662 749
663 If unsure, say Y. !! 750 config BOOT_RAW
>> 751 bool
664 752
665 config ARM64_WORKAROUND_SPECULATIVE_AT !! 753 config CEVT_BCM1480
666 bool 754 bool
667 755
668 config ARM64_ERRATUM_1165522 !! 756 config CEVT_DS1287
669 bool "Cortex-A76: 1165522: Speculative !! 757 bool
670 default y <<
671 select ARM64_WORKAROUND_SPECULATIVE_AT <<
672 help <<
673 This option adds a workaround for AR <<
674 758
675 Affected Cortex-A76 cores (r0p0, r1p !! 759 config CEVT_GT641XX
676 corrupted TLBs by speculating an AT !! 760 bool
677 context switch. <<
678 761
679 If unsure, say Y. !! 762 config CEVT_R4K_LIB
>> 763 bool
680 764
681 config ARM64_ERRATUM_1319367 !! 765 config CEVT_R4K
682 bool "Cortex-A57/A72: 1319537: Specula !! 766 select CEVT_R4K_LIB
683 default y !! 767 bool
684 select ARM64_WORKAROUND_SPECULATIVE_AT <<
685 help <<
686 This option adds work arounds for AR <<
687 and A72 erratum 1319367 <<
688 768
689 Cortex-A57 and A72 cores could end-u !! 769 config CEVT_SB1250
690 speculating an AT instruction during !! 770 bool
691 771
692 If unsure, say Y. !! 772 config CEVT_TXX9
>> 773 bool
693 774
694 config ARM64_ERRATUM_1530923 !! 775 config CSRC_BCM1480
695 bool "Cortex-A55: 1530923: Speculative !! 776 bool
696 default y <<
697 select ARM64_WORKAROUND_SPECULATIVE_AT <<
698 help <<
699 This option adds a workaround for AR <<
700 777
701 Affected Cortex-A55 cores (r0p0, r0p !! 778 config CSRC_IOASIC
702 corrupted TLBs by speculating an AT !! 779 bool
703 context switch. <<
704 780
705 If unsure, say Y. !! 781 config CSRC_R4K_LIB
>> 782 bool
706 783
707 config ARM64_WORKAROUND_REPEAT_TLBI !! 784 config CSRC_R4K
>> 785 select CSRC_R4K_LIB
708 bool 786 bool
709 787
710 config ARM64_ERRATUM_2441007 !! 788 config CSRC_SB1250
711 bool "Cortex-A55: Completion of affect !! 789 bool
712 select ARM64_WORKAROUND_REPEAT_TLBI <<
713 help <<
714 This option adds a workaround for AR <<
715 790
716 Under very rare circumstances, affec !! 791 config GPIO_TXX9
717 may not handle a race between a brea !! 792 select GENERIC_GPIO
718 CPU, and another CPU accessing the s !! 793 select ARCH_REQUIRE_GPIOLIB
719 store to a page that has been unmapp !! 794 bool
720 795
721 Work around this by adding the affec !! 796 config CFE
722 TLB sequences to be done twice. !! 797 bool
723 798
724 If unsure, say N. !! 799 config DMA_COHERENT
>> 800 bool
725 801
726 config ARM64_ERRATUM_1286807 !! 802 config DMA_NONCOHERENT
727 bool "Cortex-A76: Modification of the !! 803 bool
728 select ARM64_WORKAROUND_REPEAT_TLBI !! 804 select DMA_NEED_PCI_MAP_STATE
729 help <<
730 This option adds a workaround for AR <<
731 <<
732 On the affected Cortex-A76 cores (r0 <<
733 address for a cacheable mapping of a <<
734 accessed by a core while another cor <<
735 address to a new physical page using <<
736 break-before-make sequence, then und <<
737 TLBI+DSB completes before a read usi <<
738 invalidated has been observed by oth <<
739 workaround repeats the TLBI+DSB oper <<
740 805
741 If unsure, say N. !! 806 config DMA_NEED_PCI_MAP_STATE
>> 807 bool
742 808
743 config ARM64_ERRATUM_1463225 !! 809 config EARLY_PRINTK
744 bool "Cortex-A76: Software Step might !! 810 bool "Early printk" if EMBEDDED && DEBUG_KERNEL
>> 811 depends on SYS_HAS_EARLY_PRINTK
745 default y 812 default y
746 help 813 help
747 This option adds a workaround for Ar !! 814 This option enables special console drivers which allow the kernel
748 !! 815 to print messages very early in the bootup process.
749 On the affected Cortex-A76 cores (r0 <<
750 of a system call instruction (SVC) c <<
751 subsequent interrupts when software <<
752 exception handler of the system call <<
753 is enabled or VHE is in use. <<
754 <<
755 Work around the erratum by triggerin <<
756 when handling a system call from a t <<
757 in a VHE configuration of the kernel <<
758 <<
759 If unsure, say Y. <<
760 <<
761 config ARM64_ERRATUM_1542419 <<
762 bool "Neoverse-N1: workaround mis-orde <<
763 help <<
764 This option adds a workaround for AR <<
765 1542419. <<
766 816
767 Affected Neoverse-N1 cores could exe !! 817 This is useful for kernel debugging when your machine crashes very
768 modified by another CPU. The workaro !! 818 early before the console code is initialized. For normal operation,
769 counterpart. !! 819 it is not recommended because it looks ugly on some machines and
>> 820 doesn't cooperate with an X server. You should normally say N here,
>> 821 unless you want to debug such a crash.
770 822
771 Workaround the issue by hiding the D !! 823 config SYS_HAS_EARLY_PRINTK
772 forces user-space to perform cache m !! 824 bool
773 <<
774 If unsure, say N. <<
775 825
776 config ARM64_ERRATUM_1508412 !! 826 config HOTPLUG_CPU
777 bool "Cortex-A77: 1508412: workaround !! 827 bool "Support for hot-pluggable CPUs"
778 default y !! 828 depends on SMP && HOTPLUG && SYS_SUPPORTS_HOTPLUG_CPU
779 help 829 help
780 This option adds a workaround for Ar !! 830 Say Y here to allow turning CPUs off and on. CPUs can be
781 !! 831 controlled through /sys/devices/system/cpu.
782 Affected Cortex-A77 cores (r0p0, r1p !! 832 (Note: power management support will enable this option
783 of a store-exclusive or read of PAR_ !! 833 automatically on SMP systems. )
784 non-cacheable memory attributes. The !! 834 Say N if you want to disable CPU hotplug.
785 counterpart. <<
786 835
787 KVM guests must also have the workar !! 836 config SYS_SUPPORTS_HOTPLUG_CPU
788 deadlock the system. !! 837 bool
789 <<
790 Work around the issue by inserting D <<
791 register reads and warning KVM users <<
792 to prevent a speculative PAR_EL1 rea <<
793 838
794 If unsure, say Y. !! 839 config I8259
>> 840 bool
795 841
796 config ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MO !! 842 config MIPS_BONITO64
797 bool 843 bool
798 844
799 config ARM64_ERRATUM_2051678 !! 845 config MIPS_MSC
800 bool "Cortex-A510: 2051678: disable Ha !! 846 bool
801 default y <<
802 help <<
803 This options adds the workaround for <<
804 Affected Cortex-A510 might not respe <<
805 hardware update of the page table's <<
806 is to not enable the feature on affe <<
807 847
808 If unsure, say Y. !! 848 config MIPS_NILE4
>> 849 bool
809 850
810 config ARM64_ERRATUM_2077057 !! 851 config MIPS_DISABLE_OBSOLETE_IDE
811 bool "Cortex-A510: 2077057: workaround !! 852 bool
812 default y <<
813 help <<
814 This option adds the workaround for <<
815 Affected Cortex-A510 may corrupt SPS <<
816 expected, but a Pointer Authenticati <<
817 erratum causes SPSR_EL1 to be copied <<
818 EL1 to cause a return to EL2 with a <<
819 853
820 This can only happen when EL2 is ste !! 854 config SYNC_R4K
>> 855 bool
821 856
822 When these conditions occur, the SPS !! 857 config NO_IOPORT
823 previous guest entry, and can be res !! 858 def_bool n
824 859
825 If unsure, say Y. !! 860 config GENERIC_ISA_DMA
>> 861 bool
>> 862 select ZONE_DMA if GENERIC_ISA_DMA_SUPPORT_BROKEN=n
826 863
827 config ARM64_ERRATUM_2658417 !! 864 config GENERIC_ISA_DMA_SUPPORT_BROKEN
828 bool "Cortex-A510: 2658417: remove BF1 !! 865 bool
829 default y !! 866 select GENERIC_ISA_DMA
830 help <<
831 This option adds the workaround for <<
832 Affected Cortex-A510 (r0p0 to r1p1) <<
833 BFMMLA or VMMLA instructions in rare <<
834 A510 CPUs are using shared neon hard <<
835 discoverable by the kernel, hide the <<
836 user-space should not be using these <<
837 867
838 If unsure, say Y. !! 868 config GENERIC_GPIO
>> 869 bool
839 870
840 config ARM64_ERRATUM_2119858 !! 871 #
841 bool "Cortex-A710/X2: 2119858: workaro !! 872 # Endianess selection. Sufficiently obscure so many users don't know what to
842 default y !! 873 # answer,so we try hard to limit the available choices. Also the use of a
843 depends on CORESIGHT_TRBE !! 874 # choice statement should be more obvious to the user.
844 select ARM64_WORKAROUND_TRBE_OVERWRITE !! 875 #
>> 876 choice
>> 877 prompt "Endianess selection"
845 help 878 help
846 This option adds the workaround for !! 879 Some MIPS machines can be configured for either little or big endian
847 !! 880 byte order. These modes require different kernels and a different
848 Affected Cortex-A710/X2 cores could !! 881 Linux distribution. In general there is one preferred byteorder for a
849 data at the base of the buffer (poin !! 882 particular system but some systems are just as commonly used in the
850 the event of a WRAP event. !! 883 one or the other endianness.
851 884
852 Work around the issue by always maki !! 885 config CPU_BIG_ENDIAN
853 256 bytes before enabling the buffer !! 886 bool "Big endian"
854 the buffer with ETM ignore packets u !! 887 depends on SYS_SUPPORTS_BIG_ENDIAN
855 <<
856 If unsure, say Y. <<
857 888
858 config ARM64_ERRATUM_2139208 !! 889 config CPU_LITTLE_ENDIAN
859 bool "Neoverse-N2: 2139208: workaround !! 890 bool "Little endian"
860 default y !! 891 depends on SYS_SUPPORTS_LITTLE_ENDIAN
861 depends on CORESIGHT_TRBE <<
862 select ARM64_WORKAROUND_TRBE_OVERWRITE <<
863 help 892 help
864 This option adds the workaround for <<
865 <<
866 Affected Neoverse-N2 cores could ove <<
867 data at the base of the buffer (poin <<
868 the event of a WRAP event. <<
869 <<
870 Work around the issue by always maki <<
871 256 bytes before enabling the buffer <<
872 the buffer with ETM ignore packets u <<
873 893
874 If unsure, say Y. !! 894 endchoice
875 895
876 config ARM64_WORKAROUND_TSB_FLUSH_FAILURE !! 896 config SYS_SUPPORTS_APM_EMULATION
877 bool 897 bool
878 898
879 config ARM64_ERRATUM_2054223 !! 899 config SYS_SUPPORTS_BIG_ENDIAN
880 bool "Cortex-A710: 2054223: workaround !! 900 bool
881 default y <<
882 select ARM64_WORKAROUND_TSB_FLUSH_FAIL <<
883 help <<
884 Enable workaround for ARM Cortex-A71 <<
885 <<
886 Affected cores may fail to flush the <<
887 the PE is in trace prohibited state. <<
888 of the trace cached. <<
889 <<
890 Workaround is to issue two TSB conse <<
891 901
892 If unsure, say Y. !! 902 config SYS_SUPPORTS_LITTLE_ENDIAN
>> 903 bool
893 904
894 config ARM64_ERRATUM_2067961 !! 905 config SYS_SUPPORTS_HUGETLBFS
895 bool "Neoverse-N2: 2067961: workaround !! 906 bool
>> 907 depends on CPU_SUPPORTS_HUGEPAGES && 64BIT
896 default y 908 default y
897 select ARM64_WORKAROUND_TSB_FLUSH_FAIL <<
898 help <<
899 Enable workaround for ARM Neoverse-N <<
900 909
901 Affected cores may fail to flush the !! 910 config IRQ_CPU
902 the PE is in trace prohibited state. !! 911 bool
903 of the trace cached. <<
904 912
905 Workaround is to issue two TSB conse !! 913 config IRQ_CPU_RM7K
>> 914 bool
906 915
907 If unsure, say Y. !! 916 config IRQ_CPU_RM9K
>> 917 bool
908 918
909 config ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANG !! 919 config IRQ_MSP_SLP
910 bool 920 bool
911 921
912 config ARM64_ERRATUM_2253138 !! 922 config IRQ_MSP_CIC
913 bool "Neoverse-N2: 2253138: workaround !! 923 bool
914 depends on CORESIGHT_TRBE <<
915 default y <<
916 select ARM64_WORKAROUND_TRBE_WRITE_OUT <<
917 help <<
918 This option adds the workaround for <<
919 924
920 Affected Neoverse-N2 cores might wri !! 925 config IRQ_TXX9
921 for TRBE. Under some conditions, the !! 926 bool
922 virtually addressed page following t <<
923 (i.e., the TRBLIMITR_EL1.LIMIT), ins <<
924 927
925 Work around this in the driver by al !! 928 config IRQ_GT641XX
926 page beyond the TRBLIMITR_EL1.LIMIT, !! 929 bool
927 930
928 If unsure, say Y. !! 931 config IRQ_GIC
>> 932 bool
929 933
930 config ARM64_ERRATUM_2224489 !! 934 config IRQ_CPU_OCTEON
931 bool "Cortex-A710/X2: 2224489: workaro !! 935 bool
932 depends on CORESIGHT_TRBE <<
933 default y <<
934 select ARM64_WORKAROUND_TRBE_WRITE_OUT <<
935 help <<
936 This option adds the workaround for <<
937 936
938 Affected Cortex-A710/X2 cores might !! 937 config MIPS_BOARDS_GEN
939 for TRBE. Under some conditions, the !! 938 bool
940 virtually addressed page following t <<
941 (i.e., the TRBLIMITR_EL1.LIMIT), ins <<
942 939
943 Work around this in the driver by al !! 940 config PCI_GT64XXX_PCI0
944 page beyond the TRBLIMITR_EL1.LIMIT, !! 941 bool
945 942
946 If unsure, say Y. !! 943 config NO_EXCEPT_FILL
>> 944 bool
947 945
948 config ARM64_ERRATUM_2441009 !! 946 config MIPS_RM9122
949 bool "Cortex-A510: Completion of affec !! 947 bool
950 select ARM64_WORKAROUND_REPEAT_TLBI !! 948 select SERIAL_RM9000
951 help <<
952 This option adds a workaround for AR <<
953 <<
954 Under very rare circumstances, affec <<
955 may not handle a race between a brea <<
956 CPU, and another CPU accessing the s <<
957 store to a page that has been unmapp <<
958 949
959 Work around this by adding the affec !! 950 config SOC_EMMA2RH
960 TLB sequences to be done twice. !! 951 bool
>> 952 select CEVT_R4K
>> 953 select CSRC_R4K
>> 954 select DMA_NONCOHERENT
>> 955 select IRQ_CPU
>> 956 select SWAP_IO_SPACE
>> 957 select SYS_HAS_CPU_R5500
>> 958 select SYS_SUPPORTS_32BIT_KERNEL
>> 959 select SYS_SUPPORTS_64BIT_KERNEL
>> 960 select SYS_SUPPORTS_BIG_ENDIAN
961 961
962 If unsure, say N. !! 962 config SOC_PNX833X
>> 963 bool
>> 964 select CEVT_R4K
>> 965 select CSRC_R4K
>> 966 select IRQ_CPU
>> 967 select DMA_NONCOHERENT
>> 968 select SYS_HAS_CPU_MIPS32_R2
>> 969 select SYS_SUPPORTS_32BIT_KERNEL
>> 970 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 971 select SYS_SUPPORTS_BIG_ENDIAN
>> 972 select GENERIC_GPIO
>> 973 select CPU_MIPSR2_IRQ_VI
963 974
964 config ARM64_ERRATUM_2064142 !! 975 config SOC_PNX8335
965 bool "Cortex-A510: 2064142: workaround !! 976 bool
966 depends on CORESIGHT_TRBE !! 977 select SOC_PNX833X
967 default y <<
968 help <<
969 This option adds the workaround for <<
970 978
971 Affected Cortex-A510 core might fail !! 979 config PNX8550
972 TRBE has been disabled. Under some c !! 980 bool
973 writes into TRBE registers TRBLIMITR !! 981 select SOC_PNX8550
974 and TRBTRG_EL1 will be ignored and w <<
975 982
976 Work around this in the driver by ex !! 983 config SOC_PNX8550
977 is stopped and before performing a s !! 984 bool
978 registers. !! 985 select DMA_NONCOHERENT
>> 986 select HW_HAS_PCI
>> 987 select SYS_HAS_CPU_MIPS32_R1
>> 988 select SYS_HAS_EARLY_PRINTK
>> 989 select SYS_SUPPORTS_32BIT_KERNEL
>> 990 select GENERIC_GPIO
979 991
980 If unsure, say Y. !! 992 config SWAP_IO_SPACE
>> 993 bool
981 994
982 config ARM64_ERRATUM_2038923 !! 995 config SERIAL_RM9000
983 bool "Cortex-A510: 2038923: workaround !! 996 bool
984 depends on CORESIGHT_TRBE <<
985 default y <<
986 help <<
987 This option adds the workaround for <<
988 <<
989 Affected Cortex-A510 core might caus <<
990 prohibited within the CPU. As a resu <<
991 might be corrupted. This happens aft <<
992 TRBLIMITR_EL1.E, followed by just a <<
993 execution changes from a context, in <<
994 isn't, or vice versa. In these menti <<
995 is prohibited is inconsistent betwee <<
996 the trace buffer state might be corr <<
997 <<
998 Work around this in the driver by pr <<
999 trace is prohibited or not based on <<
1000 change to TRBLIMITR_EL1.E with at l <<
1001 two ISB instructions if no ERET is <<
1002 997
1003 If unsure, say Y. !! 998 config SGI_HAS_INDYDOG
>> 999 bool
1004 1000
1005 config ARM64_ERRATUM_1902691 !! 1001 config SGI_HAS_HAL2
1006 bool "Cortex-A510: 1902691: workaroun !! 1002 bool
1007 depends on CORESIGHT_TRBE <<
1008 default y <<
1009 help <<
1010 This option adds the workaround for <<
1011 1003
1012 Affected Cortex-A510 core might cau !! 1004 config SGI_HAS_SEEQ
1013 into the memory. Effectively TRBE i !! 1005 bool
1014 trace data. <<
1015 1006
1016 Work around this problem in the dri !! 1007 config SGI_HAS_WD93
1017 affected cpus. The firmware must ha !! 1008 bool
1018 on such implementations. This will <<
1019 do this already. <<
1020 1009
1021 If unsure, say Y. !! 1010 config SGI_HAS_ZILOG
>> 1011 bool
1022 1012
1023 config ARM64_ERRATUM_2457168 !! 1013 config SGI_HAS_I8042
1024 bool "Cortex-A510: 2457168: workaroun !! 1014 bool
1025 depends on ARM64_AMU_EXTN <<
1026 default y <<
1027 help <<
1028 This option adds the workaround for <<
1029 1015
1030 The AMU counter AMEVCNTR01 (constan !! 1016 config DEFAULT_SGI_PARTITION
1031 as the system counter. On affected !! 1017 bool
1032 incorrectly giving a significantly <<
1033 1018
1034 Work around this problem by returni !! 1019 config ARC32
1035 key locations that results in disab !! 1020 bool
1036 is the same to firmware disabling a <<
1037 1021
1038 If unsure, say Y. !! 1022 config SNIPROM
>> 1023 bool
1039 1024
1040 config ARM64_ERRATUM_2645198 !! 1025 config BOOT_ELF32
1041 bool "Cortex-A715: 2645198: Workaroun !! 1026 bool
1042 default y <<
1043 help <<
1044 This option adds the workaround for <<
1045 1027
1046 If a Cortex-A715 cpu sees a page ma !! 1028 config MIPS_L1_CACHE_SHIFT
1047 to non-executable, it may corrupt t !! 1029 int
1048 next instruction abort caused by pe !! 1030 default "4" if MACH_DECSTATION || MIKROTIK_RB532 || PMC_MSP4200_EVAL
>> 1031 default "6" if MIPS_CPU_SCACHE
>> 1032 default "7" if SGI_IP22 || SGI_IP27 || SGI_IP28 || SNI_RM || CPU_CAVIUM_OCTEON
>> 1033 default "5"
1049 1034
1050 Only user-space does executable to !! 1035 config HAVE_STD_PC_SERIAL_PORT
1051 mprotect() system call. Workaround !! 1036 bool
1052 TLB invalidation, for all changes t <<
1053 1037
1054 If unsure, say Y. !! 1038 config ARC_CONSOLE
>> 1039 bool "ARC console support"
>> 1040 depends on SGI_IP22 || SGI_IP28 || (SNI_RM && CPU_LITTLE_ENDIAN)
1055 1041
1056 config ARM64_WORKAROUND_SPECULATIVE_UNPRIV_LO !! 1042 config ARC_MEMORY
1057 bool 1043 bool
1058 !! 1044 depends on MACH_JAZZ || SNI_RM || SGI_IP32
1059 config ARM64_ERRATUM_2966298 <<
1060 bool "Cortex-A520: 2966298: workaroun <<
1061 select ARM64_WORKAROUND_SPECULATIVE_U <<
1062 default y 1045 default y
1063 help <<
1064 This option adds the workaround for <<
1065 <<
1066 On an affected Cortex-A520 core, a <<
1067 load might leak data from a privile <<
1068 <<
1069 Work around this problem by executi <<
1070 1046
1071 If unsure, say Y. !! 1047 config ARC_PROMLIB
1072 !! 1048 bool
1073 config ARM64_ERRATUM_3117295 !! 1049 depends on MACH_JAZZ || SNI_RM || SGI_IP22 || SGI_IP28 || SGI_IP32
1074 bool "Cortex-A510: 3117295: workaroun <<
1075 select ARM64_WORKAROUND_SPECULATIVE_U <<
1076 default y 1050 default y
1077 help <<
1078 This option adds the workaround for <<
1079 <<
1080 On an affected Cortex-A510 core, a <<
1081 load might leak data from a privile <<
1082 1051
1083 Work around this problem by executi !! 1052 config ARC64
1084 !! 1053 bool
1085 If unsure, say Y. <<
1086 <<
1087 config ARM64_ERRATUM_3194386 <<
1088 bool "Cortex-*/Neoverse-*: workaround <<
1089 default y <<
1090 help <<
1091 This option adds the workaround for <<
1092 1054
1093 * ARM Cortex-A76 erratum 3324349 !! 1055 config BOOT_ELF64
1094 * ARM Cortex-A77 erratum 3324348 !! 1056 bool
1095 * ARM Cortex-A78 erratum 3324344 <<
1096 * ARM Cortex-A78C erratum 3324346 <<
1097 * ARM Cortex-A78C erratum 3324347 <<
1098 * ARM Cortex-A710 erratam 3324338 <<
1099 * ARM Cortex-A715 errartum 3456084 <<
1100 * ARM Cortex-A720 erratum 3456091 <<
1101 * ARM Cortex-A725 erratum 3456106 <<
1102 * ARM Cortex-X1 erratum 3324344 <<
1103 * ARM Cortex-X1C erratum 3324346 <<
1104 * ARM Cortex-X2 erratum 3324338 <<
1105 * ARM Cortex-X3 erratum 3324335 <<
1106 * ARM Cortex-X4 erratum 3194386 <<
1107 * ARM Cortex-X925 erratum 3324334 <<
1108 * ARM Neoverse-N1 erratum 3324349 <<
1109 * ARM Neoverse N2 erratum 3324339 <<
1110 * ARM Neoverse-N3 erratum 3456111 <<
1111 * ARM Neoverse-V1 erratum 3324341 <<
1112 * ARM Neoverse V2 erratum 3324336 <<
1113 * ARM Neoverse-V3 erratum 3312417 <<
1114 <<
1115 On affected cores "MSR SSBS, #0" in <<
1116 subsequent speculative instructions <<
1117 speculative store bypassing. <<
1118 <<
1119 Work around this problem by placing <<
1120 Instruction Synchronization Barrier <<
1121 SSBS. The presence of the SSBS spec <<
1122 from hwcaps and EL0 reads of ID_AA6 <<
1123 will use the PR_SPEC_STORE_BYPASS p <<
1124 1057
1125 If unsure, say Y. !! 1058 menu "CPU selection"
1126 1059
1127 config CAVIUM_ERRATUM_22375 !! 1060 choice
1128 bool "Cavium erratum 22375, 24313" !! 1061 prompt "CPU type"
1129 default y !! 1062 default CPU_R4X00
1130 help <<
1131 Enable workaround for errata 22375 <<
1132 1063
1133 This implements two gicv3-its errat !! 1064 config CPU_LOONGSON2E
1134 with a small impact affecting only !! 1065 bool "Loongson 2E"
>> 1066 depends on SYS_HAS_CPU_LOONGSON2E
>> 1067 select CPU_LOONGSON2
>> 1068 help
>> 1069 The Loongson 2E processor implements the MIPS III instruction set
>> 1070 with many extensions.
>> 1071
>> 1072 config CPU_MIPS32_R1
>> 1073 bool "MIPS32 Release 1"
>> 1074 depends on SYS_HAS_CPU_MIPS32_R1
>> 1075 select CPU_HAS_PREFETCH
>> 1076 select CPU_SUPPORTS_32BIT_KERNEL
>> 1077 select CPU_SUPPORTS_HIGHMEM
>> 1078 help
>> 1079 Choose this option to build a kernel for release 1 or later of the
>> 1080 MIPS32 architecture. Most modern embedded systems with a 32-bit
>> 1081 MIPS processor are based on a MIPS32 processor. If you know the
>> 1082 specific type of processor in your system, choose those that one
>> 1083 otherwise CPU_MIPS32_R1 is a safe bet for any MIPS32 system.
>> 1084 Release 2 of the MIPS32 architecture is available since several
>> 1085 years so chances are you even have a MIPS32 Release 2 processor
>> 1086 in which case you should choose CPU_MIPS32_R2 instead for better
>> 1087 performance.
>> 1088
>> 1089 config CPU_MIPS32_R2
>> 1090 bool "MIPS32 Release 2"
>> 1091 depends on SYS_HAS_CPU_MIPS32_R2
>> 1092 select CPU_HAS_PREFETCH
>> 1093 select CPU_SUPPORTS_32BIT_KERNEL
>> 1094 select CPU_SUPPORTS_HIGHMEM
>> 1095 help
>> 1096 Choose this option to build a kernel for release 2 or later of the
>> 1097 MIPS32 architecture. Most modern embedded systems with a 32-bit
>> 1098 MIPS processor are based on a MIPS32 processor. If you know the
>> 1099 specific type of processor in your system, choose those that one
>> 1100 otherwise CPU_MIPS32_R1 is a safe bet for any MIPS32 system.
>> 1101
>> 1102 config CPU_MIPS64_R1
>> 1103 bool "MIPS64 Release 1"
>> 1104 depends on SYS_HAS_CPU_MIPS64_R1
>> 1105 select CPU_HAS_PREFETCH
>> 1106 select CPU_SUPPORTS_32BIT_KERNEL
>> 1107 select CPU_SUPPORTS_64BIT_KERNEL
>> 1108 select CPU_SUPPORTS_HIGHMEM
>> 1109 select CPU_SUPPORTS_HUGEPAGES
>> 1110 help
>> 1111 Choose this option to build a kernel for release 1 or later of the
>> 1112 MIPS64 architecture. Many modern embedded systems with a 64-bit
>> 1113 MIPS processor are based on a MIPS64 processor. If you know the
>> 1114 specific type of processor in your system, choose those that one
>> 1115 otherwise CPU_MIPS64_R1 is a safe bet for any MIPS64 system.
>> 1116 Release 2 of the MIPS64 architecture is available since several
>> 1117 years so chances are you even have a MIPS64 Release 2 processor
>> 1118 in which case you should choose CPU_MIPS64_R2 instead for better
>> 1119 performance.
>> 1120
>> 1121 config CPU_MIPS64_R2
>> 1122 bool "MIPS64 Release 2"
>> 1123 depends on SYS_HAS_CPU_MIPS64_R2
>> 1124 select CPU_HAS_PREFETCH
>> 1125 select CPU_SUPPORTS_32BIT_KERNEL
>> 1126 select CPU_SUPPORTS_64BIT_KERNEL
>> 1127 select CPU_SUPPORTS_HIGHMEM
>> 1128 select CPU_SUPPORTS_HUGEPAGES
>> 1129 help
>> 1130 Choose this option to build a kernel for release 2 or later of the
>> 1131 MIPS64 architecture. Many modern embedded systems with a 64-bit
>> 1132 MIPS processor are based on a MIPS64 processor. If you know the
>> 1133 specific type of processor in your system, choose those that one
>> 1134 otherwise CPU_MIPS64_R1 is a safe bet for any MIPS64 system.
>> 1135
>> 1136 config CPU_R3000
>> 1137 bool "R3000"
>> 1138 depends on SYS_HAS_CPU_R3000
>> 1139 select CPU_HAS_WB
>> 1140 select CPU_SUPPORTS_32BIT_KERNEL
>> 1141 select CPU_SUPPORTS_HIGHMEM
>> 1142 help
>> 1143 Please make sure to pick the right CPU type. Linux/MIPS is not
>> 1144 designed to be generic, i.e. Kernels compiled for R3000 CPUs will
>> 1145 *not* work on R4000 machines and vice versa. However, since most
>> 1146 of the supported machines have an R4000 (or similar) CPU, R4x00
>> 1147 might be a safe bet. If the resulting kernel does not work,
>> 1148 try to recompile with R3000.
>> 1149
>> 1150 config CPU_TX39XX
>> 1151 bool "R39XX"
>> 1152 depends on SYS_HAS_CPU_TX39XX
>> 1153 select CPU_SUPPORTS_32BIT_KERNEL
>> 1154
>> 1155 config CPU_VR41XX
>> 1156 bool "R41xx"
>> 1157 depends on SYS_HAS_CPU_VR41XX
>> 1158 select CPU_SUPPORTS_32BIT_KERNEL
>> 1159 select CPU_SUPPORTS_64BIT_KERNEL
>> 1160 help
>> 1161 The options selects support for the NEC VR4100 series of processors.
>> 1162 Only choose this option if you have one of these processors as a
>> 1163 kernel built with this option will not run on any other type of
>> 1164 processor or vice versa.
>> 1165
>> 1166 config CPU_R4300
>> 1167 bool "R4300"
>> 1168 depends on SYS_HAS_CPU_R4300
>> 1169 select CPU_SUPPORTS_32BIT_KERNEL
>> 1170 select CPU_SUPPORTS_64BIT_KERNEL
>> 1171 help
>> 1172 MIPS Technologies R4300-series processors.
>> 1173
>> 1174 config CPU_R4X00
>> 1175 bool "R4x00"
>> 1176 depends on SYS_HAS_CPU_R4X00
>> 1177 select CPU_SUPPORTS_32BIT_KERNEL
>> 1178 select CPU_SUPPORTS_64BIT_KERNEL
>> 1179 help
>> 1180 MIPS Technologies R4000-series processors other than 4300, including
>> 1181 the R4000, R4400, R4600, and 4700.
>> 1182
>> 1183 config CPU_TX49XX
>> 1184 bool "R49XX"
>> 1185 depends on SYS_HAS_CPU_TX49XX
>> 1186 select CPU_HAS_PREFETCH
>> 1187 select CPU_SUPPORTS_32BIT_KERNEL
>> 1188 select CPU_SUPPORTS_64BIT_KERNEL
>> 1189
>> 1190 config CPU_R5000
>> 1191 bool "R5000"
>> 1192 depends on SYS_HAS_CPU_R5000
>> 1193 select CPU_SUPPORTS_32BIT_KERNEL
>> 1194 select CPU_SUPPORTS_64BIT_KERNEL
>> 1195 help
>> 1196 MIPS Technologies R5000-series processors other than the Nevada.
>> 1197
>> 1198 config CPU_R5432
>> 1199 bool "R5432"
>> 1200 depends on SYS_HAS_CPU_R5432
>> 1201 select CPU_SUPPORTS_32BIT_KERNEL
>> 1202 select CPU_SUPPORTS_64BIT_KERNEL
>> 1203
>> 1204 config CPU_R5500
>> 1205 bool "R5500"
>> 1206 depends on SYS_HAS_CPU_R5500
>> 1207 select CPU_SUPPORTS_32BIT_KERNEL
>> 1208 select CPU_SUPPORTS_64BIT_KERNEL
>> 1209 select CPU_SUPPORTS_HUGEPAGES
>> 1210 help
>> 1211 NEC VR5500 and VR5500A series processors implement 64-bit MIPS IV
>> 1212 instruction set.
>> 1213
>> 1214 config CPU_R6000
>> 1215 bool "R6000"
>> 1216 depends on EXPERIMENTAL
>> 1217 depends on SYS_HAS_CPU_R6000
>> 1218 select CPU_SUPPORTS_32BIT_KERNEL
>> 1219 help
>> 1220 MIPS Technologies R6000 and R6000A series processors. Note these
>> 1221 processors are extremely rare and the support for them is incomplete.
>> 1222
>> 1223 config CPU_NEVADA
>> 1224 bool "RM52xx"
>> 1225 depends on SYS_HAS_CPU_NEVADA
>> 1226 select CPU_SUPPORTS_32BIT_KERNEL
>> 1227 select CPU_SUPPORTS_64BIT_KERNEL
>> 1228 help
>> 1229 QED / PMC-Sierra RM52xx-series ("Nevada") processors.
>> 1230
>> 1231 config CPU_R8000
>> 1232 bool "R8000"
>> 1233 depends on EXPERIMENTAL
>> 1234 depends on SYS_HAS_CPU_R8000
>> 1235 select CPU_HAS_PREFETCH
>> 1236 select CPU_SUPPORTS_64BIT_KERNEL
>> 1237 help
>> 1238 MIPS Technologies R8000 processors. Note these processors are
>> 1239 uncommon and the support for them is incomplete.
>> 1240
>> 1241 config CPU_R10000
>> 1242 bool "R10000"
>> 1243 depends on SYS_HAS_CPU_R10000
>> 1244 select CPU_HAS_PREFETCH
>> 1245 select CPU_SUPPORTS_32BIT_KERNEL
>> 1246 select CPU_SUPPORTS_64BIT_KERNEL
>> 1247 select CPU_SUPPORTS_HIGHMEM
>> 1248 help
>> 1249 MIPS Technologies R10000-series processors.
>> 1250
>> 1251 config CPU_RM7000
>> 1252 bool "RM7000"
>> 1253 depends on SYS_HAS_CPU_RM7000
>> 1254 select CPU_HAS_PREFETCH
>> 1255 select CPU_SUPPORTS_32BIT_KERNEL
>> 1256 select CPU_SUPPORTS_64BIT_KERNEL
>> 1257 select CPU_SUPPORTS_HIGHMEM
>> 1258
>> 1259 config CPU_RM9000
>> 1260 bool "RM9000"
>> 1261 depends on SYS_HAS_CPU_RM9000
>> 1262 select CPU_HAS_PREFETCH
>> 1263 select CPU_SUPPORTS_32BIT_KERNEL
>> 1264 select CPU_SUPPORTS_64BIT_KERNEL
>> 1265 select CPU_SUPPORTS_HIGHMEM
>> 1266 select WEAK_ORDERING
>> 1267
>> 1268 config CPU_SB1
>> 1269 bool "SB1"
>> 1270 depends on SYS_HAS_CPU_SB1
>> 1271 select CPU_SUPPORTS_32BIT_KERNEL
>> 1272 select CPU_SUPPORTS_64BIT_KERNEL
>> 1273 select CPU_SUPPORTS_HIGHMEM
>> 1274 select WEAK_ORDERING
>> 1275
>> 1276 config CPU_CAVIUM_OCTEON
>> 1277 bool "Cavium Octeon processor"
>> 1278 depends on SYS_HAS_CPU_CAVIUM_OCTEON
>> 1279 select IRQ_CPU
>> 1280 select IRQ_CPU_OCTEON
>> 1281 select CPU_HAS_PREFETCH
>> 1282 select CPU_SUPPORTS_64BIT_KERNEL
>> 1283 select SYS_SUPPORTS_SMP
>> 1284 select NR_CPUS_DEFAULT_16
>> 1285 select WEAK_ORDERING
>> 1286 select WEAK_REORDERING_BEYOND_LLSC
>> 1287 select CPU_SUPPORTS_HIGHMEM
>> 1288 select CPU_SUPPORTS_HUGEPAGES
>> 1289 help
>> 1290 The Cavium Octeon processor is a highly integrated chip containing
>> 1291 many ethernet hardware widgets for networking tasks. The processor
>> 1292 can have up to 16 Mips64v2 cores and 8 integrated gigabit ethernets.
>> 1293 Full details can be found at http://www.caviumnetworks.com.
1135 1294
1136 erratum 22375: only alloc 8MB tab !! 1295 endchoice
1137 erratum 24313: ignore memory acce <<
1138 1296
1139 The fixes are in ITS initialization !! 1297 config CPU_LOONGSON2
1140 type and table size provided by the !! 1298 bool
>> 1299 select CPU_SUPPORTS_32BIT_KERNEL
>> 1300 select CPU_SUPPORTS_64BIT_KERNEL
>> 1301 select CPU_SUPPORTS_HIGHMEM
1141 1302
1142 If unsure, say Y. !! 1303 config SYS_HAS_CPU_LOONGSON2E
>> 1304 bool
1143 1305
1144 config CAVIUM_ERRATUM_23144 !! 1306 config SYS_HAS_CPU_MIPS32_R1
1145 bool "Cavium erratum 23144: ITS SYNC !! 1307 bool
1146 depends on NUMA <<
1147 default y <<
1148 help <<
1149 ITS SYNC command hang for cross nod <<
1150 1308
1151 If unsure, say Y. !! 1309 config SYS_HAS_CPU_MIPS32_R2
>> 1310 bool
1152 1311
1153 config CAVIUM_ERRATUM_23154 !! 1312 config SYS_HAS_CPU_MIPS64_R1
1154 bool "Cavium errata 23154 and 38545: !! 1313 bool
1155 default y <<
1156 help <<
1157 The ThunderX GICv3 implementation r <<
1158 reading the IAR status to ensure da <<
1159 (access to icc_iar1_el1 is not sync <<
1160 1314
1161 It also suffers from erratum 38545 !! 1315 config SYS_HAS_CPU_MIPS64_R2
1162 OcteonTX and OcteonTX2), resulting !! 1316 bool
1163 spuriously presented to the CPU int <<
1164 1317
1165 If unsure, say Y. !! 1318 config SYS_HAS_CPU_R3000
>> 1319 bool
1166 1320
1167 config CAVIUM_ERRATUM_27456 !! 1321 config SYS_HAS_CPU_TX39XX
1168 bool "Cavium erratum 27456: Broadcast !! 1322 bool
1169 default y <<
1170 help <<
1171 On ThunderX T88 pass 1.x through 2. <<
1172 instructions may cause the icache t <<
1173 contains data for a non-current ASI <<
1174 invalidate the icache when changing <<
1175 1323
1176 If unsure, say Y. !! 1324 config SYS_HAS_CPU_VR41XX
>> 1325 bool
1177 1326
1178 config CAVIUM_ERRATUM_30115 !! 1327 config SYS_HAS_CPU_R4300
1179 bool "Cavium erratum 30115: Guest may !! 1328 bool
1180 default y <<
1181 help <<
1182 On ThunderX T88 pass 1.x through 2. <<
1183 1.2, and T83 Pass 1.0, KVM guest ex <<
1184 interrupts in host. Trapping both G <<
1185 accesses sidesteps the issue. <<
1186 1329
1187 If unsure, say Y. !! 1330 config SYS_HAS_CPU_R4X00
>> 1331 bool
1188 1332
1189 config CAVIUM_TX2_ERRATUM_219 !! 1333 config SYS_HAS_CPU_TX49XX
1190 bool "Cavium ThunderX2 erratum 219: P !! 1334 bool
1191 default y <<
1192 help <<
1193 On Cavium ThunderX2, a load, store <<
1194 TTBR update and the corresponding c <<
1195 cause a spurious Data Abort to be d <<
1196 the CPU core. <<
1197 <<
1198 Work around the issue by avoiding t <<
1199 trapping KVM guest TTBRx_EL1 writes <<
1200 trap handler performs the correspon <<
1201 instruction and ensures context syn <<
1202 exception return. <<
1203 1335
1204 If unsure, say Y. !! 1336 config SYS_HAS_CPU_R5000
>> 1337 bool
1205 1338
1206 config FUJITSU_ERRATUM_010001 !! 1339 config SYS_HAS_CPU_R5432
1207 bool "Fujitsu-A64FX erratum E#010001: !! 1340 bool
1208 default y <<
1209 help <<
1210 This option adds a workaround for F <<
1211 On some variants of the Fujitsu-A64 <<
1212 accesses may cause undefined fault <<
1213 This fault occurs under a specific <<
1214 load/store instruction performs an <<
1215 case-1 TTBR0_EL1 with TCR_EL1.NFD0 <<
1216 case-2 TTBR0_EL2 with TCR_EL2.NFD0 <<
1217 case-3 TTBR1_EL1 with TCR_EL1.NFD1 <<
1218 case-4 TTBR1_EL2 with TCR_EL2.NFD1 <<
1219 1341
1220 The workaround is to ensure these b !! 1342 config SYS_HAS_CPU_R5500
1221 The workaround only affects the Fuj !! 1343 bool
1222 1344
1223 If unsure, say Y. !! 1345 config SYS_HAS_CPU_R6000
>> 1346 bool
1224 1347
1225 config HISILICON_ERRATUM_161600802 !! 1348 config SYS_HAS_CPU_NEVADA
1226 bool "Hip07 161600802: Erroneous redi !! 1349 bool
1227 default y <<
1228 help <<
1229 The HiSilicon Hip07 SoC uses the wr <<
1230 when issued ITS commands such as VM <<
1231 a 128kB offset to be applied to the <<
1232 1350
1233 If unsure, say Y. !! 1351 config SYS_HAS_CPU_R8000
>> 1352 bool
1234 1353
1235 config QCOM_FALKOR_ERRATUM_1003 !! 1354 config SYS_HAS_CPU_R10000
1236 bool "Falkor E1003: Incorrect transla !! 1355 bool
1237 default y <<
1238 help <<
1239 On Falkor v1, an incorrect ASID may <<
1240 and BADDR are changed together in T <<
1241 in TTBR1_EL1, this situation only o <<
1242 then only for entries in the walk c <<
1243 is unchanged. Work around the errat <<
1244 entries for the trampoline before e <<
1245 1356
1246 config QCOM_FALKOR_ERRATUM_1009 !! 1357 config SYS_HAS_CPU_RM7000
1247 bool "Falkor E1009: Prematurely compl !! 1358 bool
1248 default y <<
1249 select ARM64_WORKAROUND_REPEAT_TLBI <<
1250 help <<
1251 On Falkor v1, the CPU may premature <<
1252 TLBI xxIS invalidate maintenance op <<
1253 one more time to fix the issue. <<
1254 1359
1255 If unsure, say Y. !! 1360 config SYS_HAS_CPU_RM9000
>> 1361 bool
1256 1362
1257 config QCOM_QDF2400_ERRATUM_0065 !! 1363 config SYS_HAS_CPU_SB1
1258 bool "QDF2400 E0065: Incorrect GITS_T !! 1364 bool
1259 default y <<
1260 help <<
1261 On Qualcomm Datacenter Technologies <<
1262 ITE size incorrectly. The GITS_TYPE <<
1263 been indicated as 16Bytes (0xf), no <<
1264 1365
1265 If unsure, say Y. !! 1366 config SYS_HAS_CPU_CAVIUM_OCTEON
>> 1367 bool
1266 1368
1267 config QCOM_FALKOR_ERRATUM_E1041 !! 1369 #
1268 bool "Falkor E1041: Speculative instr !! 1370 # CPU may reorder R->R, R->W, W->R, W->W
1269 default y !! 1371 # Reordering beyond LL and SC is handled in WEAK_REORDERING_BEYOND_LLSC
1270 help !! 1372 #
1271 Falkor CPU may speculatively fetch !! 1373 config WEAK_ORDERING
1272 memory location when MMU translatio !! 1374 bool
1273 to SCTLR_ELn[M]=0. Prefix an ISB in <<
1274 1375
1275 If unsure, say Y. !! 1376 #
>> 1377 # CPU may reorder reads and writes beyond LL/SC
>> 1378 # CPU may reorder R->LL, R->LL, W->LL, W->LL, R->SC, R->SC, W->SC, W->SC
>> 1379 #
>> 1380 config WEAK_REORDERING_BEYOND_LLSC
>> 1381 bool
>> 1382 endmenu
1276 1383
1277 config NVIDIA_CARMEL_CNP_ERRATUM !! 1384 #
1278 bool "NVIDIA Carmel CNP: CNP on Carme !! 1385 # These two indicate any level of the MIPS32 and MIPS64 architecture
1279 default y !! 1386 #
1280 help !! 1387 config CPU_MIPS32
1281 If CNP is enabled on Carmel cores, !! 1388 bool
1282 invalidate shared TLB entries insta !! 1389 default y if CPU_MIPS32_R1 || CPU_MIPS32_R2
1283 on standard ARM cores. <<
1284 1390
1285 If unsure, say Y. !! 1391 config CPU_MIPS64
>> 1392 bool
>> 1393 default y if CPU_MIPS64_R1 || CPU_MIPS64_R2
1286 1394
1287 config ROCKCHIP_ERRATUM_3588001 !! 1395 #
1288 bool "Rockchip 3588001: GIC600 can no !! 1396 # These two indicate the revision of the architecture, either Release 1 or Release 2
1289 default y !! 1397 #
1290 help !! 1398 config CPU_MIPSR1
1291 The Rockchip RK3588 GIC600 SoC inte !! 1399 bool
1292 This means, that its sharability fe !! 1400 default y if CPU_MIPS32_R1 || CPU_MIPS64_R1
1293 is supported by the IP itself. <<
1294 1401
1295 If unsure, say Y. !! 1402 config CPU_MIPSR2
>> 1403 bool
>> 1404 default y if CPU_MIPS32_R2 || CPU_MIPS64_R2 || CPU_CAVIUM_OCTEON
1296 1405
1297 config SOCIONEXT_SYNQUACER_PREITS !! 1406 config SYS_SUPPORTS_32BIT_KERNEL
1298 bool "Socionext Synquacer: Workaround !! 1407 bool
1299 default y !! 1408 config SYS_SUPPORTS_64BIT_KERNEL
1300 help !! 1409 bool
1301 Socionext Synquacer SoCs implement !! 1410 config CPU_SUPPORTS_32BIT_KERNEL
1302 MSI doorbell writes with non-zero v !! 1411 bool
>> 1412 config CPU_SUPPORTS_64BIT_KERNEL
>> 1413 bool
>> 1414 config CPU_SUPPORTS_HUGEPAGES
>> 1415 bool
1303 1416
1304 If unsure, say Y. !! 1417 #
>> 1418 # Set to y for ptrace access to watch registers.
>> 1419 #
>> 1420 config HARDWARE_WATCHPOINTS
>> 1421 bool
>> 1422 default y if CPU_MIPSR1 || CPU_MIPSR2
1305 1423
1306 endmenu # "ARM errata workarounds via the alt !! 1424 menu "Kernel type"
1307 1425
1308 choice 1426 choice
1309 prompt "Page size" <<
1310 default ARM64_4K_PAGES <<
1311 help <<
1312 Page size (translation granule) con <<
1313 1427
1314 config ARM64_4K_PAGES !! 1428 prompt "Kernel code model"
1315 bool "4KB" <<
1316 select HAVE_PAGE_SIZE_4KB <<
1317 help 1429 help
1318 This feature enables 4KB pages supp !! 1430 You should only select this option if you have a workload that
1319 !! 1431 actually benefits from 64-bit processing or if your machine has
1320 config ARM64_16K_PAGES !! 1432 large memory. You will only be presented a single option in this
1321 bool "16KB" !! 1433 menu if your system does not support both 32-bit and 64-bit kernels.
1322 select HAVE_PAGE_SIZE_16KB !! 1434
>> 1435 config 32BIT
>> 1436 bool "32-bit kernel"
>> 1437 depends on CPU_SUPPORTS_32BIT_KERNEL && SYS_SUPPORTS_32BIT_KERNEL
>> 1438 select TRAD_SIGNALS
1323 help 1439 help
1324 The system will use 16KB pages supp !! 1440 Select this option if you want to build a 32-bit kernel.
1325 requires applications compiled with !! 1441 config 64BIT
1326 aligned segments. !! 1442 bool "64-bit kernel"
1327 !! 1443 depends on CPU_SUPPORTS_64BIT_KERNEL && SYS_SUPPORTS_64BIT_KERNEL
1328 config ARM64_64K_PAGES !! 1444 select HAVE_SYSCALL_WRAPPERS
1329 bool "64KB" <<
1330 select HAVE_PAGE_SIZE_64KB <<
1331 help 1445 help
1332 This feature enables 64KB pages sup !! 1446 Select this option if you want to build a 64-bit kernel.
1333 allowing only two levels of page ta <<
1334 look-up. AArch32 emulation requires <<
1335 with 64K aligned segments. <<
1336 1447
1337 endchoice 1448 endchoice
1338 1449
1339 choice 1450 choice
1340 prompt "Virtual address space size" !! 1451 prompt "Kernel page size"
1341 default ARM64_VA_BITS_52 !! 1452 default PAGE_SIZE_4KB
1342 help <<
1343 Allows choosing one of multiple pos <<
1344 space sizes. The level of translati <<
1345 a combination of page size and virt <<
1346 <<
1347 config ARM64_VA_BITS_36 <<
1348 bool "36-bit" if EXPERT <<
1349 depends on PAGE_SIZE_16KB <<
1350 <<
1351 config ARM64_VA_BITS_39 <<
1352 bool "39-bit" <<
1353 depends on PAGE_SIZE_4KB <<
1354 <<
1355 config ARM64_VA_BITS_42 <<
1356 bool "42-bit" <<
1357 depends on PAGE_SIZE_64KB <<
1358 <<
1359 config ARM64_VA_BITS_47 <<
1360 bool "47-bit" <<
1361 depends on PAGE_SIZE_16KB <<
1362 <<
1363 config ARM64_VA_BITS_48 <<
1364 bool "48-bit" <<
1365 <<
1366 config ARM64_VA_BITS_52 <<
1367 bool "52-bit" <<
1368 depends on ARM64_PAN || !ARM64_SW_TTB <<
1369 help <<
1370 Enable 52-bit virtual addressing fo <<
1371 requested via a hint to mmap(). The <<
1372 virtual addresses for its own mappi <<
1373 this feature is available, otherwis <<
1374 <<
1375 NOTE: Enabling 52-bit virtual addre <<
1376 ARMv8.3 Pointer Authentication will <<
1377 reduced from 7 bits to 3 bits, whic <<
1378 impact on its susceptibility to bru <<
1379 1453
1380 If unsure, select 48-bit virtual ad !! 1454 config PAGE_SIZE_4KB
>> 1455 bool "4kB"
>> 1456 depends on !CPU_LOONGSON2
>> 1457 help
>> 1458 This option select the standard 4kB Linux page size. On some
>> 1459 R3000-family processors this is the only available page size. Using
>> 1460 4kB page size will minimize memory consumption and is therefore
>> 1461 recommended for low memory systems.
>> 1462
>> 1463 config PAGE_SIZE_8KB
>> 1464 bool "8kB"
>> 1465 depends on (EXPERIMENTAL && CPU_R8000) || CPU_CAVIUM_OCTEON
>> 1466 help
>> 1467 Using 8kB page size will result in higher performance kernel at
>> 1468 the price of higher memory consumption. This option is available
>> 1469 only on R8000 and cnMIPS processors. Note that you will need a
>> 1470 suitable Linux distribution to support this.
>> 1471
>> 1472 config PAGE_SIZE_16KB
>> 1473 bool "16kB"
>> 1474 depends on !CPU_R3000 && !CPU_TX39XX
>> 1475 help
>> 1476 Using 16kB page size will result in higher performance kernel at
>> 1477 the price of higher memory consumption. This option is available on
>> 1478 all non-R3000 family processors. Note that you will need a suitable
>> 1479 Linux distribution to support this.
>> 1480
>> 1481 config PAGE_SIZE_32KB
>> 1482 bool "32kB"
>> 1483 depends on CPU_CAVIUM_OCTEON
>> 1484 help
>> 1485 Using 32kB page size will result in higher performance kernel at
>> 1486 the price of higher memory consumption. This option is available
>> 1487 only on cnMIPS cores. Note that you will need a suitable Linux
>> 1488 distribution to support this.
>> 1489
>> 1490 config PAGE_SIZE_64KB
>> 1491 bool "64kB"
>> 1492 depends on EXPERIMENTAL && !CPU_R3000 && !CPU_TX39XX
>> 1493 help
>> 1494 Using 64kB page size will result in higher performance kernel at
>> 1495 the price of higher memory consumption. This option is available on
>> 1496 all non-R3000 family processor. Not that at the time of this
>> 1497 writing this option is still high experimental.
1381 1498
1382 endchoice 1499 endchoice
1383 1500
1384 config ARM64_FORCE_52BIT !! 1501 config BOARD_SCACHE
1385 bool "Force 52-bit virtual addresses !! 1502 bool
1386 depends on ARM64_VA_BITS_52 && EXPERT <<
1387 help <<
1388 For systems with 52-bit userspace V <<
1389 to maintain compatibility with olde <<
1390 unless a hint is supplied to mmap. <<
1391 <<
1392 This configuration option disables <<
1393 forces all userspace addresses to b <<
1394 should only enable this configurati <<
1395 memory management code. If unsure s <<
1396 1503
1397 config ARM64_VA_BITS !! 1504 config IP22_CPU_SCACHE
1398 int !! 1505 bool
1399 default 36 if ARM64_VA_BITS_36 !! 1506 select BOARD_SCACHE
1400 default 39 if ARM64_VA_BITS_39 <<
1401 default 42 if ARM64_VA_BITS_42 <<
1402 default 47 if ARM64_VA_BITS_47 <<
1403 default 48 if ARM64_VA_BITS_48 <<
1404 default 52 if ARM64_VA_BITS_52 <<
1405 1507
1406 choice !! 1508 #
1407 prompt "Physical address space size" !! 1509 # Support for a MIPS32 / MIPS64 style S-caches
1408 default ARM64_PA_BITS_48 !! 1510 #
1409 help !! 1511 config MIPS_CPU_SCACHE
1410 Choose the maximum physical address !! 1512 bool
1411 support. !! 1513 select BOARD_SCACHE
1412 1514
1413 config ARM64_PA_BITS_48 !! 1515 config R5000_CPU_SCACHE
1414 bool "48-bit" !! 1516 bool
1415 depends on ARM64_64K_PAGES || !ARM64_ !! 1517 select BOARD_SCACHE
1416 <<
1417 config ARM64_PA_BITS_52 <<
1418 bool "52-bit" <<
1419 depends on ARM64_64K_PAGES || ARM64_V <<
1420 depends on ARM64_PAN || !ARM64_SW_TTB <<
1421 help <<
1422 Enable support for a 52-bit physica <<
1423 part of the ARMv8.2-LPA extension. <<
1424 <<
1425 With this enabled, the kernel will <<
1426 do not support ARMv8.2-LPA, but wit <<
1427 minor performance overhead). <<
1428 1518
1429 endchoice !! 1519 config RM7000_CPU_SCACHE
>> 1520 bool
>> 1521 select BOARD_SCACHE
1430 1522
1431 config ARM64_PA_BITS !! 1523 config SIBYTE_DMA_PAGEOPS
1432 int !! 1524 bool "Use DMA to clear/copy pages"
1433 default 48 if ARM64_PA_BITS_48 !! 1525 depends on CPU_SB1
1434 default 52 if ARM64_PA_BITS_52 !! 1526 help
>> 1527 Instead of using the CPU to zero and copy pages, use a Data Mover
>> 1528 channel. These DMA channels are otherwise unused by the standard
>> 1529 SiByte Linux port. Seems to give a small performance benefit.
1435 1530
1436 config ARM64_LPA2 !! 1531 config CPU_HAS_PREFETCH
1437 def_bool y !! 1532 bool
1438 depends on ARM64_PA_BITS_52 && !ARM64 <<
1439 1533
1440 choice 1534 choice
1441 prompt "Endianness" !! 1535 prompt "MIPS MT options"
1442 default CPU_LITTLE_ENDIAN <<
1443 help <<
1444 Select the endianness of data acces <<
1445 applications will need to be compil <<
1446 that is selected here. <<
1447 1536
1448 config CPU_BIG_ENDIAN !! 1537 config MIPS_MT_DISABLED
1449 bool "Build big-endian kernel" !! 1538 bool "Disable multithreading support."
1450 # https://github.com/llvm/llvm-projec <<
1451 depends on AS_IS_GNU || AS_VERSION >= <<
1452 help 1539 help
1453 Say Y if you plan on running a kern !! 1540 Use this option if your workload can't take advantage of
1454 !! 1541 MIPS hardware multithreading support. On systems that don't have
1455 config CPU_LITTLE_ENDIAN !! 1542 the option of an MT-enabled processor this option will be the only
1456 bool "Build little-endian kernel" !! 1543 option in this menu.
>> 1544
>> 1545 config MIPS_MT_SMP
>> 1546 bool "Use 1 TC on each available VPE for SMP"
>> 1547 depends on SYS_SUPPORTS_MULTITHREADING
>> 1548 select CPU_MIPSR2_IRQ_VI
>> 1549 select CPU_MIPSR2_IRQ_EI
>> 1550 select MIPS_MT
>> 1551 select NR_CPUS_DEFAULT_2
>> 1552 select SMP
>> 1553 select SYS_SUPPORTS_SCHED_SMT if SMP
>> 1554 select SYS_SUPPORTS_SMP
>> 1555 select SMP_UP
>> 1556 help
>> 1557 This is a kernel model which is also known a VSMP or lately
>> 1558 has been marketesed into SMVP.
>> 1559
>> 1560 config MIPS_MT_SMTC
>> 1561 bool "SMTC: Use all TCs on all VPEs for SMP"
>> 1562 depends on CPU_MIPS32_R2
>> 1563 #depends on CPU_MIPS64_R2 # once there is hardware ...
>> 1564 depends on SYS_SUPPORTS_MULTITHREADING
>> 1565 select CPU_MIPSR2_IRQ_VI
>> 1566 select CPU_MIPSR2_IRQ_EI
>> 1567 select MIPS_MT
>> 1568 select NR_CPUS_DEFAULT_8
>> 1569 select SMP
>> 1570 select SYS_SUPPORTS_SMP
>> 1571 select SMP_UP
1457 help 1572 help
1458 Say Y if you plan on running a kern !! 1573 This is a kernel model which is known a SMTC or lately has been
1459 This is usually the case for distri !! 1574 marketesed into SMVP.
1460 1575
1461 endchoice 1576 endchoice
1462 1577
1463 config SCHED_MC !! 1578 config MIPS_MT
1464 bool "Multi-core scheduler support" !! 1579 bool
1465 help <<
1466 Multi-core scheduler support improv <<
1467 making when dealing with multi-core <<
1468 increased overhead in some places. <<
1469 <<
1470 config SCHED_CLUSTER <<
1471 bool "Cluster scheduler support" <<
1472 help <<
1473 Cluster scheduler support improves <<
1474 making when dealing with machines t <<
1475 Cluster usually means a couple of C <<
1476 by sharing mid-level caches, last-l <<
1477 busses. <<
1478 1580
1479 config SCHED_SMT 1581 config SCHED_SMT
1480 bool "SMT scheduler support" !! 1582 bool "SMT (multithreading) scheduler support"
1481 help !! 1583 depends on SYS_SUPPORTS_SCHED_SMT
1482 Improves the CPU scheduler's decisi !! 1584 default n
1483 MultiThreading at a cost of slightl <<
1484 places. If unsure say N here. <<
1485 <<
1486 config NR_CPUS <<
1487 int "Maximum number of CPUs (2-4096)" <<
1488 range 2 4096 <<
1489 default "512" <<
1490 <<
1491 config HOTPLUG_CPU <<
1492 bool "Support for hot-pluggable CPUs" <<
1493 select GENERIC_IRQ_MIGRATION <<
1494 help <<
1495 Say Y here to experiment with turni <<
1496 can be controlled through /sys/devi <<
1497 <<
1498 # Common NUMA Features <<
1499 config NUMA <<
1500 bool "NUMA Memory Allocation and Sche <<
1501 select GENERIC_ARCH_NUMA <<
1502 select OF_NUMA <<
1503 select HAVE_SETUP_PER_CPU_AREA <<
1504 select NEED_PER_CPU_EMBED_FIRST_CHUNK <<
1505 select NEED_PER_CPU_PAGE_FIRST_CHUNK <<
1506 select USE_PERCPU_NUMA_NODE_ID <<
1507 help <<
1508 Enable NUMA (Non-Uniform Memory Acc <<
1509 <<
1510 The kernel will try to allocate mem <<
1511 local memory of the CPU and add som <<
1512 NUMA awareness to the kernel. <<
1513 <<
1514 config NODES_SHIFT <<
1515 int "Maximum NUMA Nodes (as a power o <<
1516 range 1 10 <<
1517 default "4" <<
1518 depends on NUMA <<
1519 help 1585 help
1520 Specify the maximum number of NUMA !! 1586 SMT scheduler support improves the CPU scheduler's decision making
1521 system. Increases memory reserved !! 1587 when dealing with MIPS MT enabled cores at a cost of slightly
1522 !! 1588 increased overhead in some places. If unsure say N here.
1523 source "kernel/Kconfig.hz" <<
1524 1589
1525 config ARCH_SPARSEMEM_ENABLE !! 1590 config SYS_SUPPORTS_SCHED_SMT
1526 def_bool y !! 1591 bool
1527 select SPARSEMEM_VMEMMAP_ENABLE <<
1528 select SPARSEMEM_VMEMMAP <<
1529 1592
1530 config HW_PERF_EVENTS <<
1531 def_bool y <<
1532 depends on ARM_PMU <<
1533 1593
1534 # Supported by clang >= 7.0 or GCC >= 12.0.0 !! 1594 config SYS_SUPPORTS_MULTITHREADING
1535 config CC_HAVE_SHADOW_CALL_STACK !! 1595 bool
1536 def_bool $(cc-option, -fsanitize=shad <<
1537 1596
1538 config PARAVIRT !! 1597 config MIPS_MT_FPAFF
1539 bool "Enable paravirtualization code" !! 1598 bool "Dynamic FPU affinity for FP-intensive threads"
1540 help !! 1599 default y
1541 This changes the kernel so it can m !! 1600 depends on MIPS_MT_SMP || MIPS_MT_SMTC
1542 under a hypervisor, potentially imp <<
1543 over full virtualization. <<
1544 1601
1545 config PARAVIRT_TIME_ACCOUNTING !! 1602 config MIPS_VPE_LOADER
1546 bool "Paravirtual steal time accounti !! 1603 bool "VPE loader support."
1547 select PARAVIRT !! 1604 depends on SYS_SUPPORTS_MULTITHREADING
>> 1605 select CPU_MIPSR2_IRQ_VI
>> 1606 select CPU_MIPSR2_IRQ_EI
>> 1607 select MIPS_MT
>> 1608 help
>> 1609 Includes a loader for loading an elf relocatable object
>> 1610 onto another VPE and running it.
>> 1611
>> 1612 config MIPS_MT_SMTC_IM_BACKSTOP
>> 1613 bool "Use per-TC register bits as backstop for inhibited IM bits"
>> 1614 depends on MIPS_MT_SMTC
>> 1615 default n
1548 help 1616 help
1549 Select this option to enable fine g !! 1617 To support multiple TC microthreads acting as "CPUs" within
1550 accounting. Time spent executing ot !! 1618 a VPE, VPE-wide interrupt mask bits must be specially manipulated
1551 the current vCPU is discounted from !! 1619 during interrupt handling. To support legacy drivers and interrupt
1552 that, there can be a small performa !! 1620 controller management code, SMTC has a "backstop" to track and
1553 !! 1621 if necessary restore the interrupt mask. This has some performance
1554 If in doubt, say N here. !! 1622 impact on interrupt service overhead.
1555 !! 1623
1556 config ARCH_SUPPORTS_KEXEC !! 1624 config MIPS_MT_SMTC_IRQAFF
1557 def_bool PM_SLEEP_SMP !! 1625 bool "Support IRQ affinity API"
1558 !! 1626 depends on MIPS_MT_SMTC
1559 config ARCH_SUPPORTS_KEXEC_FILE !! 1627 default n
1560 def_bool y <<
1561 <<
1562 config ARCH_SELECTS_KEXEC_FILE <<
1563 def_bool y <<
1564 depends on KEXEC_FILE <<
1565 select HAVE_IMA_KEXEC if IMA <<
1566 <<
1567 config ARCH_SUPPORTS_KEXEC_SIG <<
1568 def_bool y <<
1569 <<
1570 config ARCH_SUPPORTS_KEXEC_IMAGE_VERIFY_SIG <<
1571 def_bool y <<
1572 <<
1573 config ARCH_DEFAULT_KEXEC_IMAGE_VERIFY_SIG <<
1574 def_bool y <<
1575 <<
1576 config ARCH_SUPPORTS_CRASH_DUMP <<
1577 def_bool y <<
1578 <<
1579 config ARCH_HAS_GENERIC_CRASHKERNEL_RESERVATI <<
1580 def_bool CRASH_RESERVE <<
1581 <<
1582 config TRANS_TABLE <<
1583 def_bool y <<
1584 depends on HIBERNATION || KEXEC_CORE <<
1585 <<
1586 config XEN_DOM0 <<
1587 def_bool y <<
1588 depends on XEN <<
1589 <<
1590 config XEN <<
1591 bool "Xen guest support on ARM64" <<
1592 depends on ARM64 && OF <<
1593 select SWIOTLB_XEN <<
1594 select PARAVIRT <<
1595 help 1628 help
1596 Say Y if you want to run Linux in a !! 1629 Enables SMP IRQ affinity API (/proc/irq/*/smp_affinity, etc.)
1597 !! 1630 for SMTC Linux kernel. Requires platform support, of which
1598 # include/linux/mmzone.h requires the followi !! 1631 an example can be found in the MIPS kernel i8259 and Malta
1599 # !! 1632 platform code. Adds some overhead to interrupt dispatch, and
1600 # MAX_PAGE_ORDER + PAGE_SHIFT <= SECTION_SI !! 1633 should be used only if you know what you are doing.
1601 # !! 1634
1602 # so the maximum value of MAX_PAGE_ORDER is S !! 1635 config MIPS_VPE_LOADER_TOM
1603 # !! 1636 bool "Load VPE program into memory hidden from linux"
1604 # | SECTION_SIZE_BITS | PAGE_SHIFT | m !! 1637 depends on MIPS_VPE_LOADER
1605 # ----+-------------------+--------------+--- !! 1638 default y
1606 # 4K | 27 | 12 | !! 1639 help
1607 # 16K | 27 | 14 | !! 1640 The loader can use memory that is present but has been hidden from
1608 # 64K | 29 | 16 | !! 1641 Linux using the kernel command line option "mem=xxMB". It's up to
1609 config ARCH_FORCE_MAX_ORDER !! 1642 you to ensure the amount you put in the option and the space your
1610 int !! 1643 program requires is less or equal to the amount physically present.
1611 default "13" if ARM64_64K_PAGES !! 1644
1612 default "11" if ARM64_16K_PAGES !! 1645 # this should possibly be in drivers/char, but it is rather cpu related. Hmmm
1613 default "10" !! 1646 config MIPS_VPE_APSP_API
>> 1647 bool "Enable support for AP/SP API (RTLX)"
>> 1648 depends on MIPS_VPE_LOADER
>> 1649 help
>> 1650
>> 1651 config MIPS_APSP_KSPD
>> 1652 bool "Enable KSPD"
>> 1653 depends on MIPS_VPE_APSP_API
>> 1654 default y
>> 1655 help
>> 1656 KSPD is a kernel daemon that accepts syscall requests from the SP
>> 1657 side, actions them and returns the results. It also handles the
>> 1658 "exit" syscall notifying other kernel modules the SP program is
>> 1659 exiting. You probably want to say yes here.
>> 1660
>> 1661 config MIPS_CMP
>> 1662 bool "MIPS CMP framework support"
>> 1663 depends on SYS_SUPPORTS_MIPS_CMP
>> 1664 select SYNC_R4K
>> 1665 select SYS_SUPPORTS_SMP
>> 1666 select SYS_SUPPORTS_SCHED_SMT if SMP
>> 1667 select WEAK_ORDERING
>> 1668 default n
1614 help 1669 help
1615 The kernel page allocator limits th !! 1670 This is a placeholder option for the GCMP work. It will need to
1616 contiguous allocations. The limit i !! 1671 be handled differently...
1617 defines the maximal power of two of <<
1618 allocated as a single contiguous bl <<
1619 overriding the default setting when <<
1620 large blocks of physically contiguo <<
1621 <<
1622 The maximal size of allocation cann <<
1623 section, so the value of MAX_PAGE_O <<
1624 <<
1625 MAX_PAGE_ORDER + PAGE_SHIFT <= SE <<
1626 <<
1627 Don't change if unsure. <<
1628 1672
1629 config UNMAP_KERNEL_AT_EL0 !! 1673 config SB1_PASS_1_WORKAROUNDS
1630 bool "Unmap kernel when running in us !! 1674 bool
>> 1675 depends on CPU_SB1_PASS_1
1631 default y 1676 default y
1632 help <<
1633 Speculation attacks against some hi <<
1634 be used to bypass MMU permission ch <<
1635 userspace. This can be defended aga <<
1636 when running in userspace, mapping <<
1637 via a trampoline page in the vector <<
1638 1677
1639 If unsure, say Y. !! 1678 config SB1_PASS_2_WORKAROUNDS
1640 !! 1679 bool
1641 config MITIGATE_SPECTRE_BRANCH_HISTORY !! 1680 depends on CPU_SB1 && (CPU_SB1_PASS_2_2 || CPU_SB1_PASS_2)
1642 bool "Mitigate Spectre style attacks <<
1643 default y 1681 default y
1644 help <<
1645 Speculation attacks against some hi <<
1646 make use of branch history to influ <<
1647 When taking an exception from user- <<
1648 or a firmware call overwrites the b <<
1649 1682
1650 config RODATA_FULL_DEFAULT_ENABLED !! 1683 config SB1_PASS_2_1_WORKAROUNDS
1651 bool "Apply r/o permissions of VM are !! 1684 bool
>> 1685 depends on CPU_SB1 && CPU_SB1_PASS_2
1652 default y 1686 default y
1653 help <<
1654 Apply read-only attributes of VM ar <<
1655 the backing pages as well. This pre <<
1656 from being modified (inadvertently <<
1657 mapping of the same memory page. Th <<
1658 be turned off at runtime by passing <<
1659 with rodata=full if this option is <<
1660 <<
1661 This requires the linear region to <<
1662 which may adversely affect performa <<
1663 1687
1664 config ARM64_SW_TTBR0_PAN !! 1688 config 64BIT_PHYS_ADDR
1665 bool "Emulate Privileged Access Never !! 1689 bool
1666 depends on !KCSAN <<
1667 help <<
1668 Enabling this option prevents the k <<
1669 user-space memory directly by point <<
1670 zeroed area and reserved ASID. The <<
1671 restore the valid TTBR0_EL1 tempora <<
1672 <<
1673 config ARM64_TAGGED_ADDR_ABI <<
1674 bool "Enable the tagged user addresse <<
1675 default y <<
1676 help <<
1677 When this option is enabled, user a <<
1678 relaxed ABI via prctl() allowing ta <<
1679 to system calls as pointer argument <<
1680 Documentation/arch/arm64/tagged-add <<
1681 1690
1682 menuconfig COMPAT !! 1691 config CPU_HAS_SMARTMIPS
1683 bool "Kernel support for 32-bit EL0" !! 1692 depends on SYS_SUPPORTS_SMARTMIPS
1684 depends on ARM64_4K_PAGES || EXPERT !! 1693 bool "Support for the SmartMIPS ASE"
1685 select HAVE_UID16 !! 1694 help
1686 select OLD_SIGSUSPEND3 !! 1695 SmartMIPS is a extension of the MIPS32 architecture aimed at
1687 select COMPAT_OLD_SIGACTION !! 1696 increased security at both hardware and software level for
1688 help !! 1697 smartcards. Enabling this option will allow proper use of the
1689 This option enables support for a 3 !! 1698 SmartMIPS instructions by Linux applications. However a kernel with
1690 kernel at EL1. AArch32-specific com !! 1699 this option will not work on a MIPS core without SmartMIPS core. If
1691 the user helper functions, VFP supp !! 1700 you don't know you probably don't have SmartMIPS and should say N
1692 handled appropriately by the kernel !! 1701 here.
1693 1702
1694 If you use a page size other than 4 !! 1703 config CPU_HAS_WB
1695 that you will only be able to execu !! 1704 bool
1696 with page size aligned segments. <<
1697 1705
1698 If you want to execute 32-bit users !! 1706 #
>> 1707 # Vectored interrupt mode is an R2 feature
>> 1708 #
>> 1709 config CPU_MIPSR2_IRQ_VI
>> 1710 bool
1699 1711
1700 if COMPAT !! 1712 #
>> 1713 # Extended interrupt mode is an R2 feature
>> 1714 #
>> 1715 config CPU_MIPSR2_IRQ_EI
>> 1716 bool
1701 1717
1702 config KUSER_HELPERS !! 1718 config CPU_HAS_SYNC
1703 bool "Enable kuser helpers page for 3 !! 1719 bool
>> 1720 depends on !CPU_R3000
1704 default y 1721 default y
1705 help <<
1706 Warning: disabling this option may <<
1707 1722
1708 Provide kuser helpers to compat tas !! 1723 config GENERIC_CLOCKEVENTS_BROADCAST
1709 helper code to userspace in read on !! 1724 bool
1710 to allow userspace to be independen <<
1711 the system. This permits binaries t <<
1712 to ARMv8 without modification. <<
1713 <<
1714 See Documentation/arch/arm/kernel_u <<
1715 1725
1716 However, the fixed address nature o !! 1726 #
1717 by ROP (return orientated programmi !! 1727 # CPU non-features
1718 exploits. !! 1728 #
>> 1729 config CPU_DADDI_WORKAROUNDS
>> 1730 bool
1719 1731
1720 If all of the binaries and librarie !! 1732 config CPU_R4000_WORKAROUNDS
1721 are built specifically for your pla !! 1733 bool
1722 these helpers, then you can turn th !! 1734 select CPU_R4400_WORKAROUNDS
1723 such exploits. However, in that cas <<
1724 relying on those helpers is run, it <<
1725 1735
1726 Say N here only if you are absolute !! 1736 config CPU_R4400_WORKAROUNDS
1727 need these helpers; otherwise, the !! 1737 bool
1728 1738
1729 config COMPAT_VDSO !! 1739 #
1730 bool "Enable vDSO for 32-bit applicat !! 1740 # Use the generic interrupt handling code in kernel/irq/:
1731 depends on !CPU_BIG_ENDIAN !! 1741 #
1732 depends on (CC_IS_CLANG && LD_IS_LLD) !! 1742 config GENERIC_HARDIRQS
1733 select GENERIC_COMPAT_VDSO !! 1743 bool
1734 default y 1744 default y
1735 help <<
1736 Place in the process address space <<
1737 ELF shared object providing fast im <<
1738 and clock_gettime. <<
1739 <<
1740 You must have a 32-bit build of gli <<
1741 to seamlessly take advantage of thi <<
1742 1745
1743 config THUMB2_COMPAT_VDSO !! 1746 config GENERIC_IRQ_PROBE
1744 bool "Compile the 32-bit vDSO for Thu !! 1747 bool
1745 depends on COMPAT_VDSO <<
1746 default y 1748 default y
1747 help <<
1748 Compile the compat vDSO with '-mthu <<
1749 otherwise with '-marm'. <<
1750 1749
1751 config COMPAT_ALIGNMENT_FIXUPS !! 1750 config IRQ_PER_CPU
1752 bool "Fix up misaligned multi-word lo !! 1751 bool
1753 <<
1754 menuconfig ARMV8_DEPRECATED <<
1755 bool "Emulate deprecated/obsolete ARM <<
1756 depends on SYSCTL <<
1757 help <<
1758 Legacy software support may require <<
1759 that have been deprecated or obsole <<
1760 <<
1761 Enable this config to enable select <<
1762 features. <<
1763 <<
1764 If unsure, say Y <<
1765 1752
1766 if ARMV8_DEPRECATED !! 1753 #
>> 1754 # - Highmem only makes sense for the 32-bit kernel.
>> 1755 # - The current highmem code will only work properly on physically indexed
>> 1756 # caches such as R3000, SB1, R7000 or those that look like they're virtually
>> 1757 # indexed such as R4000/R4400 SC and MC versions or R10000. So for the
>> 1758 # moment we protect the user and offer the highmem option only on machines
>> 1759 # where it's known to be safe. This will not offer highmem on a few systems
>> 1760 # such as MIPS32 and MIPS64 CPUs which may have virtual and physically
>> 1761 # indexed CPUs but we're playing safe.
>> 1762 # - We use SYS_SUPPORTS_HIGHMEM to offer highmem only for systems where we
>> 1763 # know they might have memory configurations that could make use of highmem
>> 1764 # support.
>> 1765 #
>> 1766 config HIGHMEM
>> 1767 bool "High Memory Support"
>> 1768 depends on 32BIT && CPU_SUPPORTS_HIGHMEM && SYS_SUPPORTS_HIGHMEM
1767 1769
1768 config SWP_EMULATION !! 1770 config CPU_SUPPORTS_HIGHMEM
1769 bool "Emulate SWP/SWPB instructions" !! 1771 bool
1770 help <<
1771 ARMv8 obsoletes the use of A32 SWP/ <<
1772 they are always undefined. Say Y he <<
1773 emulation of these instructions for <<
1774 This feature can be controlled at r <<
1775 sysctl which is disabled by default <<
1776 1772
1777 In some older versions of glibc [<= !! 1773 config SYS_SUPPORTS_HIGHMEM
1778 trylock() operations with the assum !! 1774 bool
1779 be preempted. This invalid assumpti <<
1780 with SWP emulation enabled, leading <<
1781 application. <<
1782 1775
1783 NOTE: when accessing uncached share !! 1776 config SYS_SUPPORTS_SMARTMIPS
1784 on an external transaction monitori !! 1777 bool
1785 monitor to maintain update atomicit <<
1786 implement a global monitor, this op <<
1787 perform SWP operations to uncached <<
1788 1778
1789 If unsure, say Y !! 1779 config ARCH_FLATMEM_ENABLE
>> 1780 def_bool y
>> 1781 depends on !NUMA && !CPU_LOONGSON2
1790 1782
1791 config CP15_BARRIER_EMULATION !! 1783 config ARCH_DISCONTIGMEM_ENABLE
1792 bool "Emulate CP15 Barrier instructio !! 1784 bool
>> 1785 default y if SGI_IP27
1793 help 1786 help
1794 The CP15 barrier instructions - CP1 !! 1787 Say Y to support efficient handling of discontiguous physical memory,
1795 CP15DMB - are deprecated in ARMv8 ( !! 1788 for architectures which are either NUMA (Non-Uniform Memory Access)
1796 strongly recommended to use the ISB !! 1789 or have huge holes in the physical address space for other reasons.
1797 instructions instead. !! 1790 See <file:Documentation/vm/numa> for more.
1798 1791
1799 Say Y here to enable software emula !! 1792 config ARCH_POPULATES_NODE_MAP
1800 instructions for AArch32 userspace !! 1793 def_bool y
1801 enabled, CP15 barrier usage is trac <<
1802 identify software that needs updati <<
1803 controlled at runtime with the abi. <<
1804 1794
1805 If unsure, say Y !! 1795 config ARCH_SPARSEMEM_ENABLE
>> 1796 bool
>> 1797 select SPARSEMEM_STATIC
1806 1798
1807 config SETEND_EMULATION !! 1799 config NUMA
1808 bool "Emulate SETEND instruction" !! 1800 bool "NUMA Support"
>> 1801 depends on SYS_SUPPORTS_NUMA
1809 help 1802 help
1810 The SETEND instruction alters the d !! 1803 Say Y to compile the kernel to support NUMA (Non-Uniform Memory
1811 AArch32 EL0, and is deprecated in A !! 1804 Access). This option improves performance on systems with more
1812 !! 1805 than two nodes; on two node systems it is generally better to
1813 Say Y here to enable software emula !! 1806 leave it disabled; on single node systems disable this option
1814 for AArch32 userspace code. This fe !! 1807 disabled.
1815 at runtime with the abi.setend sysc <<
1816 1808
1817 Note: All the cpus on the system mu !! 1809 config SYS_SUPPORTS_NUMA
1818 for this feature to be enabled. If !! 1810 bool
1819 endian - is hotplugged in after thi <<
1820 be unexpected results in the applic <<
1821 1811
1822 If unsure, say Y !! 1812 config NODES_SHIFT
1823 endif # ARMV8_DEPRECATED !! 1813 int
>> 1814 default "6"
>> 1815 depends on NEED_MULTIPLE_NODES
1824 1816
1825 endif # COMPAT !! 1817 source "mm/Kconfig"
1826 1818
1827 menu "ARMv8.1 architectural features" !! 1819 config SMP
>> 1820 bool "Multi-Processing support"
>> 1821 depends on SYS_SUPPORTS_SMP
>> 1822 select IRQ_PER_CPU
>> 1823 select USE_GENERIC_SMP_HELPERS
>> 1824 help
>> 1825 This enables support for systems with more than one CPU. If you have
>> 1826 a system with only one CPU, like most personal computers, say N. If
>> 1827 you have a system with more than one CPU, say Y.
>> 1828
>> 1829 If you say N here, the kernel will run on single and multiprocessor
>> 1830 machines, but will use only one CPU of a multiprocessor machine. If
>> 1831 you say Y here, the kernel will run on many, but not all,
>> 1832 singleprocessor machines. On a singleprocessor machine, the kernel
>> 1833 will run faster if you say N here.
>> 1834
>> 1835 People using multiprocessor machines who say Y here should also say
>> 1836 Y to "Enhanced Real Time Clock Support", below.
1828 1837
1829 config ARM64_HW_AFDBM !! 1838 See also the SMP-HOWTO available at
1830 bool "Support for hardware updates of !! 1839 <http://www.tldp.org/docs.html#howto>.
1831 default y <<
1832 help <<
1833 The ARMv8.1 architecture extensions <<
1834 hardware updates of the access and <<
1835 table entries. When enabled in TCR_ <<
1836 capable processors, accesses to pag <<
1837 set this bit instead of raising an <<
1838 Similarly, writes to read-only page <<
1839 clear the read-only bit (AP[2]) ins <<
1840 permission fault. <<
1841 1840
1842 Kernels built with this configurati !! 1841 If you don't know what to do here, say N.
1843 to work on pre-ARMv8.1 hardware and <<
1844 minimal. If unsure, say Y. <<
1845 1842
1846 config ARM64_PAN !! 1843 config SMP_UP
1847 bool "Enable support for Privileged A !! 1844 bool
1848 default y <<
1849 help <<
1850 Privileged Access Never (PAN; part <<
1851 prevents the kernel or hypervisor f <<
1852 memory directly. <<
1853 1845
1854 Choosing this option will cause any !! 1846 config SYS_SUPPORTS_MIPS_CMP
1855 copy_to_user et al) memory access t !! 1847 bool
1856 1848
1857 The feature is detected at runtime, !! 1849 config SYS_SUPPORTS_SMP
1858 instruction if the cpu does not imp !! 1850 bool
1859 1851
1860 config AS_HAS_LSE_ATOMICS !! 1852 config NR_CPUS_DEFAULT_1
1861 def_bool $(as-instr,.arch_extension l !! 1853 bool
1862 1854
1863 config ARM64_LSE_ATOMICS !! 1855 config NR_CPUS_DEFAULT_2
1864 bool 1856 bool
1865 default ARM64_USE_LSE_ATOMICS <<
1866 depends on AS_HAS_LSE_ATOMICS <<
1867 1857
1868 config ARM64_USE_LSE_ATOMICS !! 1858 config NR_CPUS_DEFAULT_4
1869 bool "Atomic instructions" !! 1859 bool
1870 default y <<
1871 help <<
1872 As part of the Large System Extensi <<
1873 atomic instructions that are design <<
1874 very large systems. <<
1875 1860
1876 Say Y here to make use of these ins !! 1861 config NR_CPUS_DEFAULT_8
1877 atomic routines. This incurs a smal !! 1862 bool
1878 not support these instructions and <<
1879 built with binutils >= 2.25 in orde <<
1880 to be used. <<
1881 1863
1882 endmenu # "ARMv8.1 architectural features" !! 1864 config NR_CPUS_DEFAULT_16
>> 1865 bool
1883 1866
1884 menu "ARMv8.2 architectural features" !! 1867 config NR_CPUS_DEFAULT_32
>> 1868 bool
1885 1869
1886 config AS_HAS_ARMV8_2 !! 1870 config NR_CPUS_DEFAULT_64
1887 def_bool $(cc-option,-Wa$(comma)-marc !! 1871 bool
1888 1872
1889 config AS_HAS_SHA3 !! 1873 config NR_CPUS
1890 def_bool $(as-instr,.arch armv8.2-a+s !! 1874 int "Maximum number of CPUs (2-64)"
>> 1875 range 1 64 if NR_CPUS_DEFAULT_1
>> 1876 depends on SMP
>> 1877 default "1" if NR_CPUS_DEFAULT_1
>> 1878 default "2" if NR_CPUS_DEFAULT_2
>> 1879 default "4" if NR_CPUS_DEFAULT_4
>> 1880 default "8" if NR_CPUS_DEFAULT_8
>> 1881 default "16" if NR_CPUS_DEFAULT_16
>> 1882 default "32" if NR_CPUS_DEFAULT_32
>> 1883 default "64" if NR_CPUS_DEFAULT_64
>> 1884 help
>> 1885 This allows you to specify the maximum number of CPUs which this
>> 1886 kernel will support. The maximum supported value is 32 for 32-bit
>> 1887 kernel and 64 for 64-bit kernels; the minimum value which makes
>> 1888 sense is 1 for Qemu (useful only for kernel debugging purposes)
>> 1889 and 2 for all others.
>> 1890
>> 1891 This is purely to save memory - each supported CPU adds
>> 1892 approximately eight kilobytes to the kernel image. For best
>> 1893 performance should round up your number of processors to the next
>> 1894 power of two.
1891 1895
1892 config ARM64_PMEM !! 1896 source "kernel/time/Kconfig"
1893 bool "Enable support for persistent m <<
1894 select ARCH_HAS_PMEM_API <<
1895 select ARCH_HAS_UACCESS_FLUSHCACHE <<
1896 help <<
1897 Say Y to enable support for the per <<
1898 ARMv8.2 DCPoP feature. <<
1899 1897
1900 The feature is detected at runtime, !! 1898 #
1901 operations if DC CVAP is not suppor !! 1899 # Timer Interrupt Frequency Configuration
1902 DC CVAP itself if the system does n !! 1900 #
1903 1901
1904 config ARM64_RAS_EXTN !! 1902 choice
1905 bool "Enable support for RAS CPU Exte !! 1903 prompt "Timer frequency"
1906 default y !! 1904 default HZ_250
1907 help 1905 help
1908 CPUs that support the Reliability, !! 1906 Allows the configuration of the timer frequency.
1909 (RAS) Extensions, part of ARMv8.2 a <<
1910 errors, classify them and report th <<
1911 1907
1912 On CPUs with these extensions syste !! 1908 config HZ_48
1913 barriers to determine if faults are !! 1909 bool "48 HZ" if SYS_SUPPORTS_48HZ || SYS_SUPPORTS_ARBIT_HZ
1914 classification from a new set of re <<
1915 1910
1916 Selecting this feature will allow t !! 1911 config HZ_100
1917 and access the new registers if the !! 1912 bool "100 HZ" if SYS_SUPPORTS_100HZ || SYS_SUPPORTS_ARBIT_HZ
1918 Platform RAS features may additiona <<
1919 1913
1920 config ARM64_CNP !! 1914 config HZ_128
1921 bool "Enable support for Common Not P !! 1915 bool "128 HZ" if SYS_SUPPORTS_128HZ || SYS_SUPPORTS_ARBIT_HZ
1922 default y <<
1923 depends on ARM64_PAN || !ARM64_SW_TTB <<
1924 help <<
1925 Common Not Private (CNP) allows tra <<
1926 be shared between different PEs in <<
1927 domain, so the hardware can use thi <<
1928 caching of such entries in the TLB. <<
1929 1916
1930 Selecting this option allows the CN !! 1917 config HZ_250
1931 at runtime, and does not affect PEs !! 1918 bool "250 HZ" if SYS_SUPPORTS_250HZ || SYS_SUPPORTS_ARBIT_HZ
1932 this feature. <<
1933 1919
1934 endmenu # "ARMv8.2 architectural features" !! 1920 config HZ_256
>> 1921 bool "256 HZ" if SYS_SUPPORTS_256HZ || SYS_SUPPORTS_ARBIT_HZ
1935 1922
1936 menu "ARMv8.3 architectural features" !! 1923 config HZ_1000
>> 1924 bool "1000 HZ" if SYS_SUPPORTS_1000HZ || SYS_SUPPORTS_ARBIT_HZ
1937 1925
1938 config ARM64_PTR_AUTH !! 1926 config HZ_1024
1939 bool "Enable support for pointer auth !! 1927 bool "1024 HZ" if SYS_SUPPORTS_1024HZ || SYS_SUPPORTS_ARBIT_HZ
1940 default y <<
1941 help <<
1942 Pointer authentication (part of the <<
1943 instructions for signing and authen <<
1944 keys, which can be used to mitigate <<
1945 and other attacks. <<
1946 1928
1947 This option enables these instructi !! 1929 endchoice
1948 Choosing this option will cause the <<
1949 for each process at exec() time, wi <<
1950 context-switched along with the pro <<
1951 1930
1952 The feature is detected at runtime. !! 1931 config SYS_SUPPORTS_48HZ
1953 hardware it will not be advertised !! 1932 bool
1954 be enabled. <<
1955 1933
1956 If the feature is present on the bo !! 1934 config SYS_SUPPORTS_100HZ
1957 the late CPU will be parked. Also, !! 1935 bool
1958 address auth and the late CPU has t <<
1959 but with the feature disabled. On s <<
1960 not be selected. <<
1961 1936
1962 config ARM64_PTR_AUTH_KERNEL !! 1937 config SYS_SUPPORTS_128HZ
1963 bool "Use pointer authentication for !! 1938 bool
1964 default y <<
1965 depends on ARM64_PTR_AUTH <<
1966 depends on (CC_HAS_SIGN_RETURN_ADDRES <<
1967 # Modern compilers insert a .note.gnu <<
1968 # which is only understood by binutil <<
1969 depends on LD_IS_LLD || LD_VERSION >= <<
1970 depends on !CC_IS_CLANG || AS_HAS_CFI <<
1971 depends on (!FUNCTION_GRAPH_TRACER || <<
1972 help <<
1973 If the compiler supports the -mbran <<
1974 -msign-return-address flag (e.g. GC <<
1975 will cause the kernel itself to be <<
1976 protection. In this case, and if th <<
1977 support pointer authentication, the <<
1978 disabled with minimal loss of prote <<
1979 1939
1980 This feature works with FUNCTION_GR !! 1940 config SYS_SUPPORTS_250HZ
1981 DYNAMIC_FTRACE_WITH_ARGS is enabled !! 1941 bool
1982 1942
1983 config CC_HAS_BRANCH_PROT_PAC_RET !! 1943 config SYS_SUPPORTS_256HZ
1984 # GCC 9 or later, clang 8 or later !! 1944 bool
1985 def_bool $(cc-option,-mbranch-protect <<
1986 1945
1987 config CC_HAS_SIGN_RETURN_ADDRESS !! 1946 config SYS_SUPPORTS_1000HZ
1988 # GCC 7, 8 !! 1947 bool
1989 def_bool $(cc-option,-msign-return-ad <<
1990 1948
1991 config AS_HAS_ARMV8_3 !! 1949 config SYS_SUPPORTS_1024HZ
1992 def_bool $(cc-option,-Wa$(comma)-marc !! 1950 bool
1993 1951
1994 config AS_HAS_CFI_NEGATE_RA_STATE !! 1952 config SYS_SUPPORTS_ARBIT_HZ
1995 def_bool $(as-instr,.cfi_startproc\n. !! 1953 bool
>> 1954 default y if !SYS_SUPPORTS_48HZ && !SYS_SUPPORTS_100HZ && \
>> 1955 !SYS_SUPPORTS_128HZ && !SYS_SUPPORTS_250HZ && \
>> 1956 !SYS_SUPPORTS_256HZ && !SYS_SUPPORTS_1000HZ && \
>> 1957 !SYS_SUPPORTS_1024HZ
1996 1958
1997 config AS_HAS_LDAPR !! 1959 config HZ
1998 def_bool $(as-instr,.arch_extension r !! 1960 int
>> 1961 default 48 if HZ_48
>> 1962 default 100 if HZ_100
>> 1963 default 128 if HZ_128
>> 1964 default 250 if HZ_250
>> 1965 default 256 if HZ_256
>> 1966 default 1000 if HZ_1000
>> 1967 default 1024 if HZ_1024
>> 1968
>> 1969 source "kernel/Kconfig.preempt"
>> 1970
>> 1971 config MIPS_INSANE_LARGE
>> 1972 bool "Support for large 64-bit configurations"
>> 1973 depends on CPU_R10000 && 64BIT
>> 1974 help
>> 1975 MIPS R10000 does support a 44 bit / 16TB address space as opposed to
>> 1976 previous 64-bit processors which only supported 40 bit / 1TB. If you
>> 1977 need processes of more than 1TB virtual address space, say Y here.
>> 1978 This will result in additional memory usage, so it is not
>> 1979 recommended for normal users.
>> 1980
>> 1981 config KEXEC
>> 1982 bool "Kexec system call (EXPERIMENTAL)"
>> 1983 depends on EXPERIMENTAL
>> 1984 help
>> 1985 kexec is a system call that implements the ability to shutdown your
>> 1986 current kernel, and to start another kernel. It is like a reboot
>> 1987 but it is independent of the system firmware. And like a reboot
>> 1988 you can start any kernel with it, not just Linux.
>> 1989
>> 1990 The name comes from the similarity to the exec system call.
>> 1991
>> 1992 It is an ongoing process to be certain the hardware in a machine
>> 1993 is properly shutdown, so do not be surprised if this code does not
>> 1994 initially work for you. It may help to enable device hotplugging
>> 1995 support. As of this writing the exact hardware interface is
>> 1996 strongly in flux, so no good recommendation can be made.
>> 1997
>> 1998 config SECCOMP
>> 1999 bool "Enable seccomp to safely compute untrusted bytecode"
>> 2000 depends on PROC_FS
>> 2001 default y
>> 2002 help
>> 2003 This kernel feature is useful for number crunching applications
>> 2004 that may need to compute untrusted bytecode during their
>> 2005 execution. By using pipes or other transports made available to
>> 2006 the process as file descriptors supporting the read/write
>> 2007 syscalls, it's possible to isolate those applications in
>> 2008 their own address space using seccomp. Once seccomp is
>> 2009 enabled via /proc/<pid>/seccomp, it cannot be disabled
>> 2010 and the task is only allowed to execute a few safe syscalls
>> 2011 defined by each seccomp mode.
1999 2012
2000 endmenu # "ARMv8.3 architectural features" !! 2013 If unsure, say Y. Only embedded should say N here.
2001 2014
2002 menu "ARMv8.4 architectural features" !! 2015 endmenu
2003 2016
2004 config ARM64_AMU_EXTN !! 2017 config LOCKDEP_SUPPORT
2005 bool "Enable support for the Activity !! 2018 bool
2006 default y 2019 default y
2007 help <<
2008 The activity monitors extension is <<
2009 by the ARMv8.4 CPU architecture. Th <<
2010 of the activity monitors architectu <<
2011 <<
2012 To enable the use of this extension <<
2013 2020
2014 Note that for architectural reasons !! 2021 config STACKTRACE_SUPPORT
2015 support when running on CPUs that p !! 2022 bool
2016 extension. The required support is <<
2017 * Version 1.5 and later of the AR <<
2018 <<
2019 For kernels that have this configur <<
2020 firmware, you may need to say N her <<
2021 Otherwise you may experience firmwa <<
2022 accessing the counter registers. Ev <<
2023 symptoms, the values returned by th <<
2024 correctly reflect reality. Most com <<
2025 indicating that the counter is not <<
2026 <<
2027 config AS_HAS_ARMV8_4 <<
2028 def_bool $(cc-option,-Wa$(comma)-marc <<
2029 <<
2030 config ARM64_TLB_RANGE <<
2031 bool "Enable support for tlbi range f <<
2032 default y 2023 default y
2033 depends on AS_HAS_ARMV8_4 <<
2034 help <<
2035 ARMv8.4-TLBI provides TLBI invalida <<
2036 range of input addresses. <<
2037 <<
2038 The feature introduces new assembly <<
2039 support when binutils >= 2.30. <<
2040 <<
2041 endmenu # "ARMv8.4 architectural features" <<
2042 <<
2043 menu "ARMv8.5 architectural features" <<
2044 2024
2045 config AS_HAS_ARMV8_5 !! 2025 source "init/Kconfig"
2046 def_bool $(cc-option,-Wa$(comma)-marc <<
2047 2026
2048 config ARM64_BTI !! 2027 config PROBE_INITRD_HEADER
2049 bool "Branch Target Identification su !! 2028 bool "Probe initrd header created by addinitrd"
2050 default y !! 2029 depends on BLK_DEV_INITRD
2051 help 2030 help
2052 Branch Target Identification (part !! 2031 Probe initrd header at the last page of kernel image.
2053 provides a mechanism to limit the s !! 2032 Say Y here if you are using arch/mips/boot/addinitrd.c to
2054 branch instructions such as BR or B !! 2033 add initrd or initramfs image to the kernel image.
>> 2034 Otherwise, say N.
2055 2035
2056 To make use of BTI on CPUs that sup !! 2036 source "kernel/Kconfig.freezer"
2057 2037
2058 BTI is intended to provide compleme !! 2038 menu "Bus options (PCI, PCMCIA, EISA, ISA, TC)"
2059 flow integrity protection mechanism <<
2060 authentication mechanism provided a <<
2061 For this reason, it does not make s <<
2062 also enabling support for pointer a <<
2063 enabling this option you should als <<
2064 2039
2065 Userspace binaries must also be spe !! 2040 config HW_HAS_EISA
2066 this mechanism. If you say N here !! 2041 bool
2067 BTI, such binaries can still run, b !! 2042 config HW_HAS_PCI
2068 enforcement of branch destinations. !! 2043 bool
2069 2044
2070 config ARM64_BTI_KERNEL !! 2045 config PCI
2071 bool "Use Branch Target Identificatio !! 2046 bool "Support for PCI controller"
2072 default y !! 2047 depends on HW_HAS_PCI
2073 depends on ARM64_BTI !! 2048 select PCI_DOMAINS
2074 depends on ARM64_PTR_AUTH_KERNEL !! 2049 help
2075 depends on CC_HAS_BRANCH_PROT_PAC_RET !! 2050 Find out whether you have a PCI motherboard. PCI is the name of a
2076 # https://gcc.gnu.org/bugzilla/show_b !! 2051 bus system, i.e. the way the CPU talks to the other stuff inside
2077 depends on !CC_IS_GCC || GCC_VERSION !! 2052 your box. Other bus systems are ISA, EISA, or VESA. If you have PCI,
2078 # https://gcc.gnu.org/bugzilla/show_b !! 2053 say Y, otherwise N.
2079 depends on !CC_IS_GCC <<
2080 depends on (!FUNCTION_GRAPH_TRACER || <<
2081 help <<
2082 Build the kernel with Branch Target <<
2083 and enable enforcement of this for <<
2084 is enabled and the system supports <<
2085 modular code must have BTI enabled. <<
2086 2054
2087 config CC_HAS_BRANCH_PROT_PAC_RET_BTI !! 2055 config PCI_DOMAINS
2088 # GCC 9 or later, clang 8 or later !! 2056 bool
2089 def_bool $(cc-option,-mbranch-protect <<
2090 2057
2091 config ARM64_E0PD !! 2058 source "drivers/pci/Kconfig"
2092 bool "Enable support for E0PD" <<
2093 default y <<
2094 help <<
2095 E0PD (part of the ARMv8.5 extension <<
2096 that EL0 accesses made via TTBR1 al <<
2097 providing similar benefits to KASLR <<
2098 with lower overhead and without dis <<
2099 kernel memory such as SPE. <<
2100 2059
2101 This option enables E0PD for TTBR1 !! 2060 #
>> 2061 # ISA support is now enabled via select. Too many systems still have the one
>> 2062 # or other ISA chip on the board that users don't know about so don't expect
>> 2063 # users to choose the right thing ...
>> 2064 #
>> 2065 config ISA
>> 2066 bool
2102 2067
2103 config ARM64_AS_HAS_MTE !! 2068 config EISA
2104 # Initial support for MTE went in bin !! 2069 bool "EISA support"
2105 # ".arch armv8.5-a+memtag" below. How !! 2070 depends on HW_HAS_EISA
2106 # as a late addition to the final arc !! 2071 select ISA
2107 # is only supported in the newer 2.32 !! 2072 select GENERIC_ISA_DMA
2108 # versions, hence the extra "stgm" in !! 2073 ---help---
2109 def_bool $(as-instr,.arch armv8.5-a+m !! 2074 The Extended Industry Standard Architecture (EISA) bus was
>> 2075 developed as an open alternative to the IBM MicroChannel bus.
>> 2076
>> 2077 The EISA bus provided some of the features of the IBM MicroChannel
>> 2078 bus while maintaining backward compatibility with cards made for
>> 2079 the older ISA bus. The EISA bus saw limited use between 1988 and
>> 2080 1995 when it was made obsolete by the PCI bus.
>> 2081
>> 2082 Say Y here if you are building a kernel for an EISA-based machine.
>> 2083
>> 2084 Otherwise, say N.
>> 2085
>> 2086 source "drivers/eisa/Kconfig"
>> 2087
>> 2088 config TC
>> 2089 bool "TURBOchannel support"
>> 2090 depends on MACH_DECSTATION
>> 2091 help
>> 2092 TurboChannel is a DEC (now Compaq (now HP)) bus for Alpha and MIPS
>> 2093 processors. Documentation on writing device drivers for TurboChannel
>> 2094 is available at:
>> 2095 <http://www.cs.arizona.edu/computer.help/policy/DIGITAL_unix/AA-PS3HD-TET1_html/TITLE.html>.
>> 2096
>> 2097 #config ACCESSBUS
>> 2098 # bool "Access.Bus support"
>> 2099 # depends on TC
2110 2100
2111 config ARM64_MTE !! 2101 config MMU
2112 bool "Memory Tagging Extension suppor !! 2102 bool
2113 default y 2103 default y
2114 depends on ARM64_AS_HAS_MTE && ARM64_ <<
2115 depends on AS_HAS_ARMV8_5 <<
2116 depends on AS_HAS_LSE_ATOMICS <<
2117 # Required for tag checking in the ua <<
2118 depends on ARM64_PAN <<
2119 select ARCH_HAS_SUBPAGE_FAULTS <<
2120 select ARCH_USES_HIGH_VMA_FLAGS <<
2121 select ARCH_USES_PG_ARCH_2 <<
2122 select ARCH_USES_PG_ARCH_3 <<
2123 help <<
2124 Memory Tagging (part of the ARMv8.5 <<
2125 architectural support for run-time, <<
2126 various classes of memory error to <<
2127 to eliminate vulnerabilities arisin <<
2128 languages. <<
2129 <<
2130 This option enables the support for <<
2131 Extension at EL0 (i.e. for userspac <<
2132 2104
2133 Selecting this option allows the fe !! 2105 config I8253
2134 runtime. Any secondary CPU not impl !! 2106 bool
2135 not be allowed a late bring-up. <<
2136 <<
2137 Userspace binaries that want to use <<
2138 explicitly opt in. The mechanism fo <<
2139 described in: <<
2140 <<
2141 Documentation/arch/arm64/memory-tag <<
2142 <<
2143 endmenu # "ARMv8.5 architectural features" <<
2144 <<
2145 menu "ARMv8.7 architectural features" <<
2146 2107
2147 config ARM64_EPAN !! 2108 config ZONE_DMA32
2148 bool "Enable support for Enhanced Pri !! 2109 bool
2149 default y <<
2150 depends on ARM64_PAN <<
2151 help <<
2152 Enhanced Privileged Access Never (E <<
2153 Access Never to be used with Execut <<
2154 2110
2155 The feature is detected at runtime, !! 2111 source "drivers/pcmcia/Kconfig"
2156 if the cpu does not implement the f <<
2157 endmenu # "ARMv8.7 architectural features" <<
2158 2112
2159 menu "ARMv8.9 architectural features" !! 2113 source "drivers/pci/hotplug/Kconfig"
2160 2114
2161 config ARM64_POE !! 2115 endmenu
2162 prompt "Permission Overlay Extension" <<
2163 def_bool y <<
2164 select ARCH_USES_HIGH_VMA_FLAGS <<
2165 select ARCH_HAS_PKEYS <<
2166 help <<
2167 The Permission Overlay Extension is <<
2168 Protection Keys. Memory Protection <<
2169 enforcing page-based protections, b <<
2170 of the page tables when an applicat <<
2171 2116
2172 For details, see Documentation/core !! 2117 menu "Executable file formats"
2173 2118
2174 If unsure, say y. !! 2119 source "fs/Kconfig.binfmt"
2175 2120
2176 config ARCH_PKEY_BITS !! 2121 config TRAD_SIGNALS
2177 int !! 2122 bool
2178 default 3 <<
2179 2123
2180 endmenu # "ARMv8.9 architectural features" !! 2124 config MIPS32_COMPAT
>> 2125 bool "Kernel support for Linux/MIPS 32-bit binary compatibility"
>> 2126 depends on 64BIT
>> 2127 help
>> 2128 Select this option if you want Linux/MIPS 32-bit binary
>> 2129 compatibility. Since all software available for Linux/MIPS is
>> 2130 currently 32-bit you should say Y here.
2181 2131
2182 config ARM64_SVE !! 2132 config COMPAT
2183 bool "ARM Scalable Vector Extension s !! 2133 bool
>> 2134 depends on MIPS32_COMPAT
2184 default y 2135 default y
2185 help <<
2186 The Scalable Vector Extension (SVE) <<
2187 execution state which complements a <<
2188 of the base architecture to support <<
2189 additional vectorisation opportunit <<
2190 <<
2191 To enable use of this extension on <<
2192 <<
2193 On CPUs that support the SVE2 exten <<
2194 those too. <<
2195 <<
2196 Note that for architectural reasons <<
2197 support when running on SVE capable <<
2198 is present in: <<
2199 <<
2200 * version 1.5 and later of the AR <<
2201 * the AArch64 boot wrapper since <<
2202 ("bootwrapper: SVE: Enable SVE <<
2203 <<
2204 For other firmware implementations, <<
2205 or vendor. <<
2206 2136
2207 If you need the kernel to boot on S !! 2137 config SYSVIPC_COMPAT
2208 firmware, you may need to say N her !! 2138 bool
2209 fixed. Otherwise, you may experien !! 2139 depends on COMPAT && SYSVIPC
2210 booting the kernel. If unsure and <<
2211 symptoms, you should assume that it <<
2212 <<
2213 config ARM64_SME <<
2214 bool "ARM Scalable Matrix Extension s <<
2215 default y 2140 default y
2216 depends on ARM64_SVE <<
2217 depends on BROKEN <<
2218 help <<
2219 The Scalable Matrix Extension (SME) <<
2220 execution state which utilises a su <<
2221 instruction set, together with the <<
2222 register state capable of holding t <<
2223 enable various matrix operations. <<
2224 <<
2225 config ARM64_PSEUDO_NMI <<
2226 bool "Support for NMI-like interrupts <<
2227 select ARM_GIC_V3 <<
2228 help <<
2229 Adds support for mimicking Non-Mask <<
2230 GIC interrupt priority. This suppor <<
2231 ARM GIC. <<
2232 2141
2233 This high priority configuration fo !! 2142 config MIPS32_O32
2234 explicitly enabled by setting the k !! 2143 bool "Kernel support for o32 binaries"
2235 "irqchip.gicv3_pseudo_nmi" to 1. !! 2144 depends on MIPS32_COMPAT
2236 <<
2237 If unsure, say N <<
2238 <<
2239 if ARM64_PSEUDO_NMI <<
2240 config ARM64_DEBUG_PRIORITY_MASKING <<
2241 bool "Debug interrupt priority maskin <<
2242 help 2145 help
2243 This adds runtime checks to functio !! 2146 Select this option if you want to run o32 binaries. These are pure
2244 interrupts when using priority mask !! 2147 32-bit binaries as used by the 32-bit Linux/MIPS port. Most of
2245 the validity of ICC_PMR_EL1 when ca !! 2148 existing binaries are in this format.
2246 <<
2247 If unsure, say N <<
2248 endif # ARM64_PSEUDO_NMI <<
2249 2149
2250 config RELOCATABLE !! 2150 If unsure, say Y.
2251 bool "Build a relocatable kernel imag <<
2252 select ARCH_HAS_RELR <<
2253 default y <<
2254 help <<
2255 This builds the kernel as a Positio <<
2256 which retains all relocation metada <<
2257 kernel binary at runtime to a diffe <<
2258 address it was linked at. <<
2259 Since AArch64 uses the RELA relocat <<
2260 relocation pass at runtime even if <<
2261 same address it was linked at. <<
2262 2151
2263 config RANDOMIZE_BASE !! 2152 config MIPS32_N32
2264 bool "Randomize the address of the ke !! 2153 bool "Kernel support for n32 binaries"
2265 select RELOCATABLE !! 2154 depends on MIPS32_COMPAT
2266 help 2155 help
2267 Randomizes the virtual address at w !! 2156 Select this option if you want to run n32 binaries. These are
2268 loaded, as a security feature that !! 2157 64-bit binaries using 32-bit quantities for addressing and certain
2269 relying on knowledge of the locatio !! 2158 data that would normally be 64-bit. They are used in special
2270 !! 2159 cases.
2271 It is the bootloader's job to provi <<
2272 random u64 value in /chosen/kaslr-s <<
2273 <<
2274 When booting via the UEFI stub, it <<
2275 EFI_RNG_PROTOCOL implementation (if <<
2276 to the kernel proper. In addition, <<
2277 location of the kernel Image as wel <<
2278 2160
2279 If unsure, say N. 2161 If unsure, say N.
2280 2162
2281 config RANDOMIZE_MODULE_REGION_FULL !! 2163 config BINFMT_ELF32
2282 bool "Randomize the module region ove <<
2283 depends on RANDOMIZE_BASE <<
2284 default y <<
2285 help <<
2286 Randomizes the location of the modu <<
2287 covering the core kernel. This way, <<
2288 to leak information about the locat <<
2289 but it does imply that function cal <<
2290 kernel will need to be resolved via <<
2291 <<
2292 When this option is not set, the mo <<
2293 a limited range that contains the [ <<
2294 core kernel, so branch relocations <<
2295 the region is exhausted. In this pa <<
2296 exhaustion, modules might be able t <<
2297 <<
2298 config CC_HAVE_STACKPROTECTOR_SYSREG <<
2299 def_bool $(cc-option,-mstack-protecto <<
2300 <<
2301 config STACKPROTECTOR_PER_TASK <<
2302 def_bool y <<
2303 depends on STACKPROTECTOR && CC_HAVE_ <<
2304 <<
2305 config UNWIND_PATCH_PAC_INTO_SCS <<
2306 bool "Enable shadow call stack dynami <<
2307 # needs Clang with https://github.com <<
2308 depends on CC_IS_CLANG && CLANG_VERSI <<
2309 depends on ARM64_PTR_AUTH_KERNEL && C <<
2310 depends on SHADOW_CALL_STACK <<
2311 select UNWIND_TABLES <<
2312 select DYNAMIC_SCS <<
2313 <<
2314 config ARM64_CONTPTE <<
2315 bool "Contiguous PTE mappings for use <<
2316 depends on TRANSPARENT_HUGEPAGE <<
2317 default y <<
2318 help <<
2319 When enabled, user mappings are con <<
2320 bit, for any mappings that meet the <<
2321 This reduces TLB pressure and impro <<
2322 <<
2323 endmenu # "Kernel Features" <<
2324 <<
2325 menu "Boot options" <<
2326 <<
2327 config ARM64_ACPI_PARKING_PROTOCOL <<
2328 bool "Enable support for the ARM64 AC <<
2329 depends on ACPI <<
2330 help <<
2331 Enable support for the ARM64 ACPI p <<
2332 the kernel will not allow booting t <<
2333 protocol even if the corresponding <<
2334 MADT table. <<
2335 <<
2336 config CMDLINE <<
2337 string "Default kernel command string <<
2338 default "" <<
2339 help <<
2340 Provide a set of default command-li <<
2341 entering them here. As a minimum, y <<
2342 root device (e.g. root=/dev/nfs). <<
2343 <<
2344 choice <<
2345 prompt "Kernel command line type" <<
2346 depends on CMDLINE != "" <<
2347 default CMDLINE_FROM_BOOTLOADER <<
2348 help <<
2349 Choose how the kernel will handle t <<
2350 command line string. <<
2351 <<
2352 config CMDLINE_FROM_BOOTLOADER <<
2353 bool "Use bootloader kernel arguments <<
2354 help <<
2355 Uses the command-line options passe <<
2356 the boot loader doesn't provide any <<
2357 string provided in CMDLINE will be <<
2358 <<
2359 config CMDLINE_FORCE <<
2360 bool "Always use the default kernel c <<
2361 help <<
2362 Always use the default kernel comma <<
2363 loader passes other arguments to th <<
2364 This is useful if you cannot or don <<
2365 command-line options your boot load <<
2366 <<
2367 endchoice <<
2368 <<
2369 config EFI_STUB <<
2370 bool 2164 bool
>> 2165 default y if MIPS32_O32 || MIPS32_N32
2371 2166
2372 config EFI !! 2167 endmenu
2373 bool "UEFI runtime support" <<
2374 depends on OF && !CPU_BIG_ENDIAN <<
2375 depends on KERNEL_MODE_NEON <<
2376 select ARCH_SUPPORTS_ACPI <<
2377 select LIBFDT <<
2378 select UCS2_STRING <<
2379 select EFI_PARAMS_FROM_FDT <<
2380 select EFI_RUNTIME_WRAPPERS <<
2381 select EFI_STUB <<
2382 select EFI_GENERIC_STUB <<
2383 imply IMA_SECURE_AND_OR_TRUSTED_BOOT <<
2384 default y <<
2385 help <<
2386 This option provides support for ru <<
2387 by UEFI firmware (such as non-volat <<
2388 clock, and platform reset). A UEFI <<
2389 allow the kernel to be booted as an <<
2390 is only useful on systems that have <<
2391 <<
2392 config COMPRESSED_INSTALL <<
2393 bool "Install compressed image by def <<
2394 help <<
2395 This makes the regular "make instal <<
2396 image we built, not the legacy unco <<
2397 <<
2398 You can check that a compressed ima <<
2399 "make zinstall" first, and verifyin <<
2400 in your environment before making " <<
2401 you. <<
2402 <<
2403 config DMI <<
2404 bool "Enable support for SMBIOS (DMI) <<
2405 depends on EFI <<
2406 default y <<
2407 help <<
2408 This enables SMBIOS/DMI feature for <<
2409 <<
2410 This option is only useful on syste <<
2411 However, even with this option, the <<
2412 continue to boot on existing non-UE <<
2413 <<
2414 endmenu # "Boot options" <<
2415 2168
2416 menu "Power management options" 2169 menu "Power management options"
2417 2170
2418 source "kernel/power/Kconfig" <<
2419 <<
2420 config ARCH_HIBERNATION_POSSIBLE 2171 config ARCH_HIBERNATION_POSSIBLE
2421 def_bool y 2172 def_bool y
2422 depends on CPU_PM !! 2173 depends on SYS_SUPPORTS_HOTPLUG_CPU || !SMP
2423 <<
2424 config ARCH_HIBERNATION_HEADER <<
2425 def_bool y <<
2426 depends on HIBERNATION <<
2427 2174
2428 config ARCH_SUSPEND_POSSIBLE 2175 config ARCH_SUSPEND_POSSIBLE
2429 def_bool y 2176 def_bool y
>> 2177 depends on SYS_SUPPORTS_HOTPLUG_CPU || !SMP
>> 2178
>> 2179 source "kernel/power/Kconfig"
2430 2180
2431 endmenu # "Power management options" !! 2181 endmenu
2432 2182
2433 menu "CPU Power Management" !! 2183 source "net/Kconfig"
2434 2184
2435 source "drivers/cpuidle/Kconfig" !! 2185 source "drivers/Kconfig"
2436 2186
2437 source "drivers/cpufreq/Kconfig" !! 2187 source "fs/Kconfig"
2438 2188
2439 endmenu # "CPU Power Management" !! 2189 source "arch/mips/Kconfig.debug"
2440 2190
2441 source "drivers/acpi/Kconfig" !! 2191 source "security/Kconfig"
2442 2192
2443 source "arch/arm64/kvm/Kconfig" !! 2193 source "crypto/Kconfig"
2444 2194
>> 2195 source "lib/Kconfig"
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