1 # SPDX-License-Identifier: GPL-2.0-only !! 1 config MIPS
2 config ARM64 !! 2 bool
3 def_bool y !! 3 default y
4 select ACPI_APMT if ACPI !! 4 select HAVE_GENERIC_DMA_COHERENT
5 select ACPI_CCA_REQUIRED if ACPI !! 5 select HAVE_IDE
6 select ACPI_GENERIC_GSI if ACPI !! 6 select HAVE_OPROFILE
7 select ACPI_GTDT if ACPI !! 7 select HAVE_PERF_EVENTS
8 select ACPI_HOTPLUG_CPU if ACPI_PROCES !! 8 select PERF_USE_VMALLOC
9 select ACPI_IORT if ACPI <<
10 select ACPI_REDUCED_HARDWARE_ONLY if A <<
11 select ACPI_MCFG if (ACPI && PCI) <<
12 select ACPI_SPCR_TABLE if ACPI <<
13 select ACPI_PPTT if ACPI <<
14 select ARCH_HAS_DEBUG_WX <<
15 select ARCH_BINFMT_ELF_EXTRA_PHDRS <<
16 select ARCH_BINFMT_ELF_STATE <<
17 select ARCH_CORRECT_STACKTRACE_ON_KRET <<
18 select ARCH_ENABLE_HUGEPAGE_MIGRATION <<
19 select ARCH_ENABLE_MEMORY_HOTPLUG <<
20 select ARCH_ENABLE_MEMORY_HOTREMOVE <<
21 select ARCH_ENABLE_SPLIT_PMD_PTLOCK if <<
22 select ARCH_ENABLE_THP_MIGRATION if TR <<
23 select ARCH_HAS_CACHE_LINE_SIZE <<
24 select ARCH_HAS_CURRENT_STACK_POINTER <<
25 select ARCH_HAS_DEBUG_VIRTUAL <<
26 select ARCH_HAS_DEBUG_VM_PGTABLE <<
27 select ARCH_HAS_DMA_OPS if XEN <<
28 select ARCH_HAS_DMA_PREP_COHERENT <<
29 select ARCH_HAS_ACPI_TABLE_UPGRADE if <<
30 select ARCH_HAS_FAST_MULTIPLIER <<
31 select ARCH_HAS_FORTIFY_SOURCE <<
32 select ARCH_HAS_GCOV_PROFILE_ALL <<
33 select ARCH_HAS_GIGANTIC_PAGE <<
34 select ARCH_HAS_KCOV <<
35 select ARCH_HAS_KERNEL_FPU_SUPPORT if <<
36 select ARCH_HAS_KEEPINITRD <<
37 select ARCH_HAS_MEMBARRIER_SYNC_CORE <<
38 select ARCH_HAS_MEM_ENCRYPT <<
39 select ARCH_HAS_NMI_SAFE_THIS_CPU_OPS <<
40 select ARCH_HAS_NON_OVERLAPPING_ADDRES <<
41 select ARCH_HAS_PTE_DEVMAP <<
42 select ARCH_HAS_PTE_SPECIAL <<
43 select ARCH_HAS_HW_PTE_YOUNG <<
44 select ARCH_HAS_SETUP_DMA_OPS <<
45 select ARCH_HAS_SET_DIRECT_MAP <<
46 select ARCH_HAS_SET_MEMORY <<
47 select ARCH_STACKWALK <<
48 select ARCH_HAS_STRICT_KERNEL_RWX <<
49 select ARCH_HAS_STRICT_MODULE_RWX <<
50 select ARCH_HAS_SYNC_DMA_FOR_DEVICE <<
51 select ARCH_HAS_SYNC_DMA_FOR_CPU <<
52 select ARCH_HAS_SYSCALL_WRAPPER <<
53 select ARCH_HAS_TICK_BROADCAST if GENE <<
54 select ARCH_HAS_ZONE_DMA_SET if EXPERT <<
55 select ARCH_HAVE_ELF_PROT <<
56 select ARCH_HAVE_NMI_SAFE_CMPXCHG <<
57 select ARCH_HAVE_TRACE_MMIO_ACCESS <<
58 select ARCH_INLINE_READ_LOCK if !PREEM <<
59 select ARCH_INLINE_READ_LOCK_BH if !PR <<
60 select ARCH_INLINE_READ_LOCK_IRQ if !P <<
61 select ARCH_INLINE_READ_LOCK_IRQSAVE i <<
62 select ARCH_INLINE_READ_UNLOCK if !PRE <<
63 select ARCH_INLINE_READ_UNLOCK_BH if ! <<
64 select ARCH_INLINE_READ_UNLOCK_IRQ if <<
65 select ARCH_INLINE_READ_UNLOCK_IRQREST <<
66 select ARCH_INLINE_WRITE_LOCK if !PREE <<
67 select ARCH_INLINE_WRITE_LOCK_BH if !P <<
68 select ARCH_INLINE_WRITE_LOCK_IRQ if ! <<
69 select ARCH_INLINE_WRITE_LOCK_IRQSAVE <<
70 select ARCH_INLINE_WRITE_UNLOCK if !PR <<
71 select ARCH_INLINE_WRITE_UNLOCK_BH if <<
72 select ARCH_INLINE_WRITE_UNLOCK_IRQ if <<
73 select ARCH_INLINE_WRITE_UNLOCK_IRQRES <<
74 select ARCH_INLINE_SPIN_TRYLOCK if !PR <<
75 select ARCH_INLINE_SPIN_TRYLOCK_BH if <<
76 select ARCH_INLINE_SPIN_LOCK if !PREEM <<
77 select ARCH_INLINE_SPIN_LOCK_BH if !PR <<
78 select ARCH_INLINE_SPIN_LOCK_IRQ if !P <<
79 select ARCH_INLINE_SPIN_LOCK_IRQSAVE i <<
80 select ARCH_INLINE_SPIN_UNLOCK if !PRE <<
81 select ARCH_INLINE_SPIN_UNLOCK_BH if ! <<
82 select ARCH_INLINE_SPIN_UNLOCK_IRQ if <<
83 select ARCH_INLINE_SPIN_UNLOCK_IRQREST <<
84 select ARCH_KEEP_MEMBLOCK <<
85 select ARCH_MHP_MEMMAP_ON_MEMORY_ENABL <<
86 select ARCH_USE_CMPXCHG_LOCKREF <<
87 select ARCH_USE_GNU_PROPERTY <<
88 select ARCH_USE_MEMTEST <<
89 select ARCH_USE_QUEUED_RWLOCKS <<
90 select ARCH_USE_QUEUED_SPINLOCKS <<
91 select ARCH_USE_SYM_ANNOTATIONS <<
92 select ARCH_SUPPORTS_DEBUG_PAGEALLOC <<
93 select ARCH_SUPPORTS_HUGETLBFS <<
94 select ARCH_SUPPORTS_MEMORY_FAILURE <<
95 select ARCH_SUPPORTS_SHADOW_CALL_STACK <<
96 select ARCH_SUPPORTS_LTO_CLANG if CPU_ <<
97 select ARCH_SUPPORTS_LTO_CLANG_THIN <<
98 select ARCH_SUPPORTS_CFI_CLANG <<
99 select ARCH_SUPPORTS_ATOMIC_RMW <<
100 select ARCH_SUPPORTS_INT128 if CC_HAS_ <<
101 select ARCH_SUPPORTS_NUMA_BALANCING <<
102 select ARCH_SUPPORTS_PAGE_TABLE_CHECK <<
103 select ARCH_SUPPORTS_PER_VMA_LOCK <<
104 select ARCH_SUPPORTS_HUGE_PFNMAP if TR <<
105 select ARCH_SUPPORTS_RT <<
106 select ARCH_WANT_BATCHED_UNMAP_TLB_FLU <<
107 select ARCH_WANT_COMPAT_IPC_PARSE_VERS <<
108 select ARCH_WANT_DEFAULT_BPF_JIT <<
109 select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_ <<
110 select ARCH_WANT_FRAME_POINTERS <<
111 select ARCH_WANT_HUGE_PMD_SHARE if ARM <<
112 select ARCH_WANT_LD_ORPHAN_WARN <<
113 select ARCH_WANTS_EXECMEM_LATE if EXEC <<
114 select ARCH_WANTS_NO_INSTR <<
115 select ARCH_WANTS_THP_SWAP if ARM64_4K <<
116 select ARCH_HAS_UBSAN <<
117 select ARM_AMBA <<
118 select ARM_ARCH_TIMER <<
119 select ARM_GIC <<
120 select AUDIT_ARCH_COMPAT_GENERIC <<
121 select ARM_GIC_V2M if PCI <<
122 select ARM_GIC_V3 <<
123 select ARM_GIC_V3_ITS if PCI <<
124 select ARM_PSCI_FW <<
125 select BUILDTIME_TABLE_SORT <<
126 select CLONE_BACKWARDS <<
127 select COMMON_CLK <<
128 select CPU_PM if (SUSPEND || CPU_IDLE) <<
129 select CPUMASK_OFFSTACK if NR_CPUS > 2 <<
130 select CRC32 <<
131 select DCACHE_WORD_ACCESS <<
132 select DYNAMIC_FTRACE if FUNCTION_TRAC <<
133 select DMA_BOUNCE_UNALIGNED_KMALLOC <<
134 select DMA_DIRECT_REMAP <<
135 select EDAC_SUPPORT <<
136 select FRAME_POINTER <<
137 select FUNCTION_ALIGNMENT_4B <<
138 select FUNCTION_ALIGNMENT_8B if DYNAMI <<
139 select GENERIC_ALLOCATOR <<
140 select GENERIC_ARCH_TOPOLOGY <<
141 select GENERIC_CLOCKEVENTS_BROADCAST <<
142 select GENERIC_CPU_AUTOPROBE <<
143 select GENERIC_CPU_DEVICES <<
144 select GENERIC_CPU_VULNERABILITIES <<
145 select GENERIC_EARLY_IOREMAP <<
146 select GENERIC_IDLE_POLL_SETUP <<
147 select GENERIC_IOREMAP <<
148 select GENERIC_IRQ_IPI <<
149 select GENERIC_IRQ_PROBE <<
150 select GENERIC_IRQ_SHOW <<
151 select GENERIC_IRQ_SHOW_LEVEL <<
152 select GENERIC_LIB_DEVMEM_IS_ALLOWED <<
153 select GENERIC_PCI_IOMAP <<
154 select GENERIC_PTDUMP <<
155 select GENERIC_SCHED_CLOCK <<
156 select GENERIC_SMP_IDLE_THREAD <<
157 select GENERIC_TIME_VSYSCALL <<
158 select GENERIC_GETTIMEOFDAY <<
159 select GENERIC_VDSO_TIME_NS <<
160 select HARDIRQS_SW_RESEND <<
161 select HAS_IOPORT <<
162 select HAVE_MOVE_PMD <<
163 select HAVE_MOVE_PUD <<
164 select HAVE_PCI <<
165 select HAVE_ACPI_APEI if (ACPI && EFI) <<
166 select HAVE_ALIGNED_STRUCT_PAGE <<
167 select HAVE_ARCH_AUDITSYSCALL <<
168 select HAVE_ARCH_BITREVERSE <<
169 select HAVE_ARCH_COMPILER_H <<
170 select HAVE_ARCH_HUGE_VMALLOC <<
171 select HAVE_ARCH_HUGE_VMAP <<
172 select HAVE_ARCH_JUMP_LABEL <<
173 select HAVE_ARCH_JUMP_LABEL_RELATIVE <<
174 select HAVE_ARCH_KASAN <<
175 select HAVE_ARCH_KASAN_VMALLOC <<
176 select HAVE_ARCH_KASAN_SW_TAGS <<
177 select HAVE_ARCH_KASAN_HW_TAGS if ARM6 <<
178 # Some instrumentation may be unsound, <<
179 select HAVE_ARCH_KCSAN if EXPERT <<
180 select HAVE_ARCH_KFENCE <<
181 select HAVE_ARCH_KGDB 9 select HAVE_ARCH_KGDB
182 select HAVE_ARCH_MMAP_RND_BITS !! 10 select ARCH_HAVE_CUSTOM_GPIO_H
183 select HAVE_ARCH_MMAP_RND_COMPAT_BITS !! 11 select HAVE_FUNCTION_TRACER
184 select HAVE_ARCH_PREL32_RELOCATIONS !! 12 select HAVE_FUNCTION_TRACE_MCOUNT_TEST
185 select HAVE_ARCH_RANDOMIZE_KSTACK_OFFS <<
186 select HAVE_ARCH_SECCOMP_FILTER <<
187 select HAVE_ARCH_STACKLEAK <<
188 select HAVE_ARCH_THREAD_STRUCT_WHITELI <<
189 select HAVE_ARCH_TRACEHOOK <<
190 select HAVE_ARCH_TRANSPARENT_HUGEPAGE <<
191 select HAVE_ARCH_VMAP_STACK <<
192 select HAVE_ARM_SMCCC <<
193 select HAVE_ASM_MODVERSIONS <<
194 select HAVE_EBPF_JIT <<
195 select HAVE_C_RECORDMCOUNT <<
196 select HAVE_CMPXCHG_DOUBLE <<
197 select HAVE_CMPXCHG_LOCAL <<
198 select HAVE_CONTEXT_TRACKING_USER <<
199 select HAVE_DEBUG_KMEMLEAK <<
200 select HAVE_DMA_CONTIGUOUS <<
201 select HAVE_DYNAMIC_FTRACE 13 select HAVE_DYNAMIC_FTRACE
202 select HAVE_DYNAMIC_FTRACE_WITH_ARGS \ <<
203 if (GCC_SUPPORTS_DYNAMIC_FTRAC <<
204 CLANG_SUPPORTS_DYNAMIC_FTR <<
205 select HAVE_DYNAMIC_FTRACE_WITH_DIRECT <<
206 if DYNAMIC_FTRACE_WITH_ARGS && <<
207 select HAVE_DYNAMIC_FTRACE_WITH_CALL_O <<
208 if (DYNAMIC_FTRACE_WITH_ARGS & <<
209 (CC_IS_CLANG || !CC_OPTIMI <<
210 select FTRACE_MCOUNT_USE_PATCHABLE_FUN <<
211 if DYNAMIC_FTRACE_WITH_ARGS <<
212 select HAVE_SAMPLE_FTRACE_DIRECT <<
213 select HAVE_SAMPLE_FTRACE_DIRECT_MULTI <<
214 select HAVE_EFFICIENT_UNALIGNED_ACCESS <<
215 select HAVE_GUP_FAST <<
216 select HAVE_FTRACE_MCOUNT_RECORD 14 select HAVE_FTRACE_MCOUNT_RECORD
217 select HAVE_FUNCTION_TRACER !! 15 select HAVE_C_RECORDMCOUNT
218 select HAVE_FUNCTION_ERROR_INJECTION <<
219 select HAVE_FUNCTION_GRAPH_TRACER 16 select HAVE_FUNCTION_GRAPH_TRACER
220 select HAVE_FUNCTION_GRAPH_RETVAL <<
221 select HAVE_GCC_PLUGINS <<
222 select HAVE_HARDLOCKUP_DETECTOR_PERF i <<
223 HW_PERF_EVENTS && HAVE_PERF_EV <<
224 select HAVE_HW_BREAKPOINT if PERF_EVEN <<
225 select HAVE_IOREMAP_PROT <<
226 select HAVE_IRQ_TIME_ACCOUNTING <<
227 select HAVE_MOD_ARCH_SPECIFIC <<
228 select HAVE_NMI <<
229 select HAVE_PERF_EVENTS <<
230 select HAVE_PERF_EVENTS_NMI if ARM64_P <<
231 select HAVE_PERF_REGS <<
232 select HAVE_PERF_USER_STACK_DUMP <<
233 select HAVE_PREEMPT_DYNAMIC_KEY <<
234 select HAVE_REGS_AND_STACK_ACCESS_API <<
235 select HAVE_POSIX_CPU_TIMERS_TASK_WORK <<
236 select HAVE_FUNCTION_ARG_ACCESS_API <<
237 select MMU_GATHER_RCU_TABLE_FREE <<
238 select HAVE_RSEQ <<
239 select HAVE_RUST if RUSTC_SUPPORTS_ARM <<
240 select HAVE_STACKPROTECTOR <<
241 select HAVE_SYSCALL_TRACEPOINTS <<
242 select HAVE_KPROBES 17 select HAVE_KPROBES
243 select HAVE_KRETPROBES 18 select HAVE_KRETPROBES
244 select HAVE_GENERIC_VDSO !! 19 select HAVE_DEBUG_KMEMLEAK
245 select HOTPLUG_CORE_SYNC_DEAD if HOTPL !! 20 select ARCH_BINFMT_ELF_RANDOMIZE_PIE
246 select IRQ_DOMAIN !! 21 select HAVE_ARCH_TRANSPARENT_HUGEPAGE if CPU_SUPPORTS_HUGEPAGES && 64BIT
>> 22 select RTC_LIB if !MACH_LOONGSON
>> 23 select GENERIC_ATOMIC64 if !64BIT
>> 24 select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
>> 25 select HAVE_DMA_ATTRS
>> 26 select HAVE_DMA_API_DEBUG
>> 27 select HAVE_GENERIC_HARDIRQS
>> 28 select GENERIC_IRQ_PROBE
>> 29 select GENERIC_IRQ_SHOW
>> 30 select GENERIC_PCI_IOMAP
>> 31 select HAVE_ARCH_JUMP_LABEL
>> 32 select ARCH_WANT_IPC_PARSE_VERSION
247 select IRQ_FORCED_THREADING 33 select IRQ_FORCED_THREADING
248 select KASAN_VMALLOC if KASAN !! 34 select HAVE_MEMBLOCK
249 select LOCK_MM_AND_FIND_VMA !! 35 select HAVE_MEMBLOCK_NODE_MAP
250 select MODULES_USE_ELF_RELA !! 36 select ARCH_DISCARD_MEMBLOCK
251 select NEED_DMA_MAP_STATE !! 37 select GENERIC_SMP_IDLE_THREAD
252 select NEED_SG_DMA_LENGTH !! 38 select BUILDTIME_EXTABLE_SORT
253 select OF !! 39 select GENERIC_CLOCKEVENTS
254 select OF_EARLY_FLATTREE !! 40 select GENERIC_CMOS_UPDATE
255 select PCI_DOMAINS_GENERIC if PCI !! 41 select HAVE_MOD_ARCH_SPECIFIC
256 select PCI_ECAM if (ACPI && PCI) !! 42 select VIRT_TO_BUS
257 select PCI_SYSCALL if PCI !! 43 select MODULES_USE_ELF_REL if MODULES
258 select POWER_RESET !! 44 select MODULES_USE_ELF_RELA if MODULES && 64BIT
259 select POWER_SUPPLY !! 45 select CLONE_BACKWARDS
260 select SPARSE_IRQ <<
261 select SWIOTLB <<
262 select SYSCTL_EXCEPTION_TRACE <<
263 select THREAD_INFO_IN_TASK <<
264 select HAVE_ARCH_USERFAULTFD_MINOR if <<
265 select HAVE_ARCH_USERFAULTFD_WP if USE <<
266 select TRACE_IRQFLAGS_SUPPORT <<
267 select TRACE_IRQFLAGS_NMI_SUPPORT <<
268 select HAVE_SOFTIRQ_ON_OWN_STACK <<
269 select USER_STACKTRACE_SUPPORT <<
270 select VDSO_GETRANDOM <<
271 help <<
272 ARM 64-bit (AArch64) Linux support. <<
273 <<
274 config RUSTC_SUPPORTS_ARM64 <<
275 def_bool y <<
276 depends on CPU_LITTLE_ENDIAN <<
277 # Shadow call stack is only supported <<
278 # <<
279 # When using the UNWIND_PATCH_PAC_INTO <<
280 # required due to use of the -Zfixed-x <<
281 # <<
282 # Otherwise, rustc version 1.82+ is re <<
283 # -Zsanitizer=shadow-call-stack flag. <<
284 depends on !SHADOW_CALL_STACK || RUSTC <<
285 <<
286 config CLANG_SUPPORTS_DYNAMIC_FTRACE_WITH_ARGS <<
287 def_bool CC_IS_CLANG <<
288 # https://github.com/ClangBuiltLinux/l <<
289 depends on AS_IS_GNU || (AS_IS_LLVM && <<
290 <<
291 config GCC_SUPPORTS_DYNAMIC_FTRACE_WITH_ARGS <<
292 def_bool CC_IS_GCC <<
293 depends on $(cc-option,-fpatchable-fun <<
294 <<
295 config 64BIT <<
296 def_bool y <<
297 <<
298 config MMU <<
299 def_bool y <<
300 <<
301 config ARM64_CONT_PTE_SHIFT <<
302 int <<
303 default 5 if PAGE_SIZE_64KB <<
304 default 7 if PAGE_SIZE_16KB <<
305 default 4 <<
306 <<
307 config ARM64_CONT_PMD_SHIFT <<
308 int <<
309 default 5 if PAGE_SIZE_64KB <<
310 default 5 if PAGE_SIZE_16KB <<
311 default 4 <<
312 <<
313 config ARCH_MMAP_RND_BITS_MIN <<
314 default 14 if PAGE_SIZE_64KB <<
315 default 16 if PAGE_SIZE_16KB <<
316 default 18 <<
317 <<
318 # max bits determined by the following formula <<
319 # VA_BITS - PAGE_SHIFT - 3 <<
320 config ARCH_MMAP_RND_BITS_MAX <<
321 default 19 if ARM64_VA_BITS=36 <<
322 default 24 if ARM64_VA_BITS=39 <<
323 default 27 if ARM64_VA_BITS=42 <<
324 default 30 if ARM64_VA_BITS=47 <<
325 default 29 if ARM64_VA_BITS=48 && ARM6 <<
326 default 31 if ARM64_VA_BITS=48 && ARM6 <<
327 default 33 if ARM64_VA_BITS=48 <<
328 default 14 if ARM64_64K_PAGES <<
329 default 16 if ARM64_16K_PAGES <<
330 default 18 <<
331 <<
332 config ARCH_MMAP_RND_COMPAT_BITS_MIN <<
333 default 7 if ARM64_64K_PAGES <<
334 default 9 if ARM64_16K_PAGES <<
335 default 11 <<
336 <<
337 config ARCH_MMAP_RND_COMPAT_BITS_MAX <<
338 default 16 <<
339 <<
340 config NO_IOPORT_MAP <<
341 def_bool y if !PCI <<
342 <<
343 config STACKTRACE_SUPPORT <<
344 def_bool y <<
345 <<
346 config ILLEGAL_POINTER_VALUE <<
347 hex <<
348 default 0xdead000000000000 <<
349 <<
350 config LOCKDEP_SUPPORT <<
351 def_bool y <<
352 <<
353 config GENERIC_BUG <<
354 def_bool y <<
355 depends on BUG <<
356 <<
357 config GENERIC_BUG_RELATIVE_POINTERS <<
358 def_bool y <<
359 depends on GENERIC_BUG <<
360 <<
361 config GENERIC_HWEIGHT <<
362 def_bool y <<
363 46
364 config GENERIC_CSUM !! 47 menu "Machine selection"
365 def_bool y <<
366 48
367 config GENERIC_CALIBRATE_DELAY !! 49 config ZONE_DMA
368 def_bool y !! 50 bool
369 51
370 config SMP !! 52 choice
371 def_bool y !! 53 prompt "System type"
>> 54 default SGI_IP22
372 55
373 config KERNEL_MODE_NEON !! 56 config MIPS_ALCHEMY
374 def_bool y !! 57 bool "Alchemy processor based machines"
>> 58 select 64BIT_PHYS_ADDR
>> 59 select CEVT_R4K
>> 60 select CSRC_R4K
>> 61 select IRQ_CPU
>> 62 select SYS_HAS_CPU_MIPS32_R1
>> 63 select SYS_SUPPORTS_32BIT_KERNEL
>> 64 select SYS_SUPPORTS_APM_EMULATION
>> 65 select ARCH_REQUIRE_GPIOLIB
>> 66 select SYS_SUPPORTS_ZBOOT
>> 67 select USB_ARCH_HAS_OHCI
>> 68 select USB_ARCH_HAS_EHCI
>> 69
>> 70 config AR7
>> 71 bool "Texas Instruments AR7"
>> 72 select BOOT_ELF32
>> 73 select DMA_NONCOHERENT
>> 74 select CEVT_R4K
>> 75 select CSRC_R4K
>> 76 select IRQ_CPU
>> 77 select NO_EXCEPT_FILL
>> 78 select SWAP_IO_SPACE
>> 79 select SYS_HAS_CPU_MIPS32_R1
>> 80 select SYS_HAS_EARLY_PRINTK
>> 81 select SYS_SUPPORTS_32BIT_KERNEL
>> 82 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 83 select SYS_SUPPORTS_ZBOOT_UART16550
>> 84 select ARCH_REQUIRE_GPIOLIB
>> 85 select VLYNQ
>> 86 select HAVE_CLK
>> 87 help
>> 88 Support for the Texas Instruments AR7 System-on-a-Chip
>> 89 family: TNETD7100, 7200 and 7300.
>> 90
>> 91 config ATH79
>> 92 bool "Atheros AR71XX/AR724X/AR913X based boards"
>> 93 select ARCH_REQUIRE_GPIOLIB
>> 94 select BOOT_RAW
>> 95 select CEVT_R4K
>> 96 select CSRC_R4K
>> 97 select DMA_NONCOHERENT
>> 98 select HAVE_CLK
>> 99 select IRQ_CPU
>> 100 select MIPS_MACHINE
>> 101 select SYS_HAS_CPU_MIPS32_R2
>> 102 select SYS_HAS_EARLY_PRINTK
>> 103 select SYS_SUPPORTS_32BIT_KERNEL
>> 104 select SYS_SUPPORTS_BIG_ENDIAN
>> 105 help
>> 106 Support for the Atheros AR71XX/AR724X/AR913X SoCs.
>> 107
>> 108 config BCM47XX
>> 109 bool "Broadcom BCM47XX based boards"
>> 110 select ARCH_WANT_OPTIONAL_GPIOLIB
>> 111 select BOOT_RAW
>> 112 select CEVT_R4K
>> 113 select CSRC_R4K
>> 114 select DMA_NONCOHERENT
>> 115 select FW_CFE
>> 116 select HW_HAS_PCI
>> 117 select IRQ_CPU
>> 118 select NO_EXCEPT_FILL
>> 119 select SYS_SUPPORTS_32BIT_KERNEL
>> 120 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 121 select SYS_HAS_EARLY_PRINTK
>> 122 help
>> 123 Support for BCM47XX based boards
>> 124
>> 125 config BCM63XX
>> 126 bool "Broadcom BCM63XX based boards"
>> 127 select CEVT_R4K
>> 128 select CSRC_R4K
>> 129 select DMA_NONCOHERENT
>> 130 select IRQ_CPU
>> 131 select SYS_HAS_CPU_MIPS32_R1
>> 132 select SYS_SUPPORTS_32BIT_KERNEL
>> 133 select SYS_SUPPORTS_BIG_ENDIAN
>> 134 select SYS_HAS_EARLY_PRINTK
>> 135 select SWAP_IO_SPACE
>> 136 select ARCH_REQUIRE_GPIOLIB
>> 137 select HAVE_CLK
>> 138 help
>> 139 Support for BCM63XX based boards
>> 140
>> 141 config MIPS_COBALT
>> 142 bool "Cobalt Server"
>> 143 select CEVT_R4K
>> 144 select CSRC_R4K
>> 145 select CEVT_GT641XX
>> 146 select DMA_NONCOHERENT
>> 147 select HW_HAS_PCI
>> 148 select I8253
>> 149 select I8259
>> 150 select IRQ_CPU
>> 151 select IRQ_GT641XX
>> 152 select PCI_GT64XXX_PCI0
>> 153 select PCI
>> 154 select SYS_HAS_CPU_NEVADA
>> 155 select SYS_HAS_EARLY_PRINTK
>> 156 select SYS_SUPPORTS_32BIT_KERNEL
>> 157 select SYS_SUPPORTS_64BIT_KERNEL
>> 158 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 159
>> 160 config MACH_DECSTATION
>> 161 bool "DECstations"
>> 162 select BOOT_ELF32
>> 163 select CEVT_DS1287
>> 164 select CEVT_R4K
>> 165 select CSRC_IOASIC
>> 166 select CSRC_R4K
>> 167 select CPU_DADDI_WORKAROUNDS if 64BIT
>> 168 select CPU_R4000_WORKAROUNDS if 64BIT
>> 169 select CPU_R4400_WORKAROUNDS if 64BIT
>> 170 select DMA_NONCOHERENT
>> 171 select NO_IOPORT
>> 172 select IRQ_CPU
>> 173 select SYS_HAS_CPU_R3000
>> 174 select SYS_HAS_CPU_R4X00
>> 175 select SYS_SUPPORTS_32BIT_KERNEL
>> 176 select SYS_SUPPORTS_64BIT_KERNEL
>> 177 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 178 select SYS_SUPPORTS_128HZ
>> 179 select SYS_SUPPORTS_256HZ
>> 180 select SYS_SUPPORTS_1024HZ
>> 181 help
>> 182 This enables support for DEC's MIPS based workstations. For details
>> 183 see the Linux/MIPS FAQ on <http://www.linux-mips.org/> and the
>> 184 DECstation porting pages on <http://decstation.unix-ag.org/>.
>> 185
>> 186 If you have one of the following DECstation Models you definitely
>> 187 want to choose R4xx0 for the CPU Type:
>> 188
>> 189 DECstation 5000/50
>> 190 DECstation 5000/150
>> 191 DECstation 5000/260
>> 192 DECsystem 5900/260
>> 193
>> 194 otherwise choose R3000.
>> 195
>> 196 config MACH_JAZZ
>> 197 bool "Jazz family of machines"
>> 198 select FW_ARC
>> 199 select FW_ARC32
>> 200 select ARCH_MAY_HAVE_PC_FDC
>> 201 select CEVT_R4K
>> 202 select CSRC_R4K
>> 203 select DEFAULT_SGI_PARTITION if CPU_BIG_ENDIAN
>> 204 select GENERIC_ISA_DMA
>> 205 select HAVE_PCSPKR_PLATFORM
>> 206 select IRQ_CPU
>> 207 select I8253
>> 208 select I8259
>> 209 select ISA
>> 210 select SYS_HAS_CPU_R4X00
>> 211 select SYS_SUPPORTS_32BIT_KERNEL
>> 212 select SYS_SUPPORTS_64BIT_KERNEL
>> 213 select SYS_SUPPORTS_100HZ
>> 214 help
>> 215 This a family of machines based on the MIPS R4030 chipset which was
>> 216 used by several vendors to build RISC/os and Windows NT workstations.
>> 217 Members include the Acer PICA, MIPS Magnum 4000, MIPS Millennium and
>> 218 Olivetti M700-10 workstations.
>> 219
>> 220 config MACH_JZ4740
>> 221 bool "Ingenic JZ4740 based machines"
>> 222 select SYS_HAS_CPU_MIPS32_R1
>> 223 select SYS_SUPPORTS_32BIT_KERNEL
>> 224 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 225 select SYS_SUPPORTS_ZBOOT_UART16550
>> 226 select DMA_NONCOHERENT
>> 227 select IRQ_CPU
>> 228 select ARCH_REQUIRE_GPIOLIB
>> 229 select SYS_HAS_EARLY_PRINTK
>> 230 select HAVE_PWM
>> 231 select HAVE_CLK
>> 232 select GENERIC_IRQ_CHIP
>> 233
>> 234 config LANTIQ
>> 235 bool "Lantiq based platforms"
>> 236 select DMA_NONCOHERENT
>> 237 select IRQ_CPU
>> 238 select CEVT_R4K
>> 239 select CSRC_R4K
>> 240 select SYS_HAS_CPU_MIPS32_R1
>> 241 select SYS_HAS_CPU_MIPS32_R2
>> 242 select SYS_SUPPORTS_BIG_ENDIAN
>> 243 select SYS_SUPPORTS_32BIT_KERNEL
>> 244 select SYS_SUPPORTS_MULTITHREADING
>> 245 select SYS_HAS_EARLY_PRINTK
>> 246 select ARCH_REQUIRE_GPIOLIB
>> 247 select SWAP_IO_SPACE
>> 248 select BOOT_RAW
>> 249 select HAVE_MACH_CLKDEV
>> 250 select CLKDEV_LOOKUP
>> 251 select USE_OF
>> 252 select PINCTRL
>> 253 select PINCTRL_LANTIQ
>> 254
>> 255 config LASAT
>> 256 bool "LASAT Networks platforms"
>> 257 select CEVT_R4K
>> 258 select CSRC_R4K
>> 259 select DMA_NONCOHERENT
>> 260 select SYS_HAS_EARLY_PRINTK
>> 261 select HW_HAS_PCI
>> 262 select IRQ_CPU
>> 263 select PCI_GT64XXX_PCI0
>> 264 select MIPS_NILE4
>> 265 select R5000_CPU_SCACHE
>> 266 select SYS_HAS_CPU_R5000
>> 267 select SYS_SUPPORTS_32BIT_KERNEL
>> 268 select SYS_SUPPORTS_64BIT_KERNEL if BROKEN
>> 269 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 270
>> 271 config MACH_LOONGSON
>> 272 bool "Loongson family of machines"
>> 273 select SYS_SUPPORTS_ZBOOT
>> 274 help
>> 275 This enables the support of Loongson family of machines.
>> 276
>> 277 Loongson is a family of general-purpose MIPS-compatible CPUs.
>> 278 developed at Institute of Computing Technology (ICT),
>> 279 Chinese Academy of Sciences (CAS) in the People's Republic
>> 280 of China. The chief architect is Professor Weiwu Hu.
>> 281
>> 282 config MACH_LOONGSON1
>> 283 bool "Loongson 1 family of machines"
>> 284 select SYS_SUPPORTS_ZBOOT
>> 285 help
>> 286 This enables support for the Loongson 1 based machines.
>> 287
>> 288 Loongson 1 is a family of 32-bit MIPS-compatible SoCs developed by
>> 289 the ICT (Institute of Computing Technology) and the Chinese Academy
>> 290 of Sciences.
>> 291
>> 292 config MIPS_MALTA
>> 293 bool "MIPS Malta board"
>> 294 select ARCH_MAY_HAVE_PC_FDC
>> 295 select BOOT_ELF32
>> 296 select BOOT_RAW
>> 297 select CEVT_R4K
>> 298 select CSRC_R4K
>> 299 select CSRC_GIC
>> 300 select DMA_NONCOHERENT
>> 301 select GENERIC_ISA_DMA
>> 302 select HAVE_PCSPKR_PLATFORM
>> 303 select IRQ_CPU
>> 304 select IRQ_GIC
>> 305 select HW_HAS_PCI
>> 306 select I8253
>> 307 select I8259
>> 308 select MIPS_BONITO64
>> 309 select MIPS_CPU_SCACHE
>> 310 select PCI_GT64XXX_PCI0
>> 311 select MIPS_MSC
>> 312 select SWAP_IO_SPACE
>> 313 select SYS_HAS_CPU_MIPS32_R1
>> 314 select SYS_HAS_CPU_MIPS32_R2
>> 315 select SYS_HAS_CPU_MIPS64_R1
>> 316 select SYS_HAS_CPU_MIPS64_R2
>> 317 select SYS_HAS_CPU_NEVADA
>> 318 select SYS_HAS_CPU_RM7000
>> 319 select SYS_HAS_EARLY_PRINTK
>> 320 select SYS_SUPPORTS_32BIT_KERNEL
>> 321 select SYS_SUPPORTS_64BIT_KERNEL
>> 322 select SYS_SUPPORTS_BIG_ENDIAN
>> 323 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 324 select SYS_SUPPORTS_MIPS_CMP
>> 325 select SYS_SUPPORTS_MULTITHREADING
>> 326 select SYS_SUPPORTS_SMARTMIPS
>> 327 select SYS_SUPPORTS_ZBOOT
>> 328 help
>> 329 This enables support for the MIPS Technologies Malta evaluation
>> 330 board.
>> 331
>> 332 config MIPS_SEAD3
>> 333 bool "MIPS SEAD3 board"
>> 334 select BOOT_ELF32
>> 335 select BOOT_RAW
>> 336 select CEVT_R4K
>> 337 select CSRC_R4K
>> 338 select CSRC_GIC
>> 339 select CPU_MIPSR2_IRQ_VI
>> 340 select CPU_MIPSR2_IRQ_EI
>> 341 select DMA_NONCOHERENT
>> 342 select IRQ_CPU
>> 343 select IRQ_GIC
>> 344 select MIPS_CPU_SCACHE
>> 345 select MIPS_MSC
>> 346 select SYS_HAS_CPU_MIPS32_R1
>> 347 select SYS_HAS_CPU_MIPS32_R2
>> 348 select SYS_HAS_CPU_MIPS64_R1
>> 349 select SYS_HAS_EARLY_PRINTK
>> 350 select SYS_SUPPORTS_32BIT_KERNEL
>> 351 select SYS_SUPPORTS_64BIT_KERNEL
>> 352 select SYS_SUPPORTS_BIG_ENDIAN
>> 353 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 354 select SYS_SUPPORTS_SMARTMIPS
>> 355 select SYS_SUPPORTS_MICROMIPS
>> 356 select USB_ARCH_HAS_EHCI
>> 357 select USB_EHCI_BIG_ENDIAN_DESC
>> 358 select USB_EHCI_BIG_ENDIAN_MMIO
>> 359 select USE_OF
>> 360 help
>> 361 This enables support for the MIPS Technologies SEAD3 evaluation
>> 362 board.
>> 363
>> 364 config NEC_MARKEINS
>> 365 bool "NEC EMMA2RH Mark-eins board"
>> 366 select SOC_EMMA2RH
>> 367 select HW_HAS_PCI
>> 368 help
>> 369 This enables support for the NEC Electronics Mark-eins boards.
>> 370
>> 371 config MACH_VR41XX
>> 372 bool "NEC VR4100 series based machines"
>> 373 select CEVT_R4K
>> 374 select CSRC_R4K
>> 375 select SYS_HAS_CPU_VR41XX
>> 376 select ARCH_REQUIRE_GPIOLIB
>> 377
>> 378 config NXP_STB220
>> 379 bool "NXP STB220 board"
>> 380 select SOC_PNX833X
>> 381 help
>> 382 Support for NXP Semiconductors STB220 Development Board.
>> 383
>> 384 config NXP_STB225
>> 385 bool "NXP 225 board"
>> 386 select SOC_PNX833X
>> 387 select SOC_PNX8335
>> 388 help
>> 389 Support for NXP Semiconductors STB225 Development Board.
>> 390
>> 391 config PMC_MSP
>> 392 bool "PMC-Sierra MSP chipsets"
>> 393 select CEVT_R4K
>> 394 select CSRC_R4K
>> 395 select DMA_NONCOHERENT
>> 396 select SWAP_IO_SPACE
>> 397 select NO_EXCEPT_FILL
>> 398 select BOOT_RAW
>> 399 select SYS_HAS_CPU_MIPS32_R1
>> 400 select SYS_HAS_CPU_MIPS32_R2
>> 401 select SYS_SUPPORTS_32BIT_KERNEL
>> 402 select SYS_SUPPORTS_BIG_ENDIAN
>> 403 select IRQ_CPU
>> 404 select SERIAL_8250
>> 405 select SERIAL_8250_CONSOLE
>> 406 select USB_EHCI_BIG_ENDIAN_MMIO
>> 407 select USB_EHCI_BIG_ENDIAN_DESC
>> 408 help
>> 409 This adds support for the PMC-Sierra family of Multi-Service
>> 410 Processor System-On-A-Chips. These parts include a number
>> 411 of integrated peripherals, interfaces and DSPs in addition to
>> 412 a variety of MIPS cores.
>> 413
>> 414 config POWERTV
>> 415 bool "Cisco PowerTV"
>> 416 select BOOT_ELF32
>> 417 select CEVT_R4K
>> 418 select CPU_MIPSR2_IRQ_VI
>> 419 select CPU_MIPSR2_IRQ_EI
>> 420 select CSRC_POWERTV
>> 421 select DMA_NONCOHERENT
>> 422 select HW_HAS_PCI
>> 423 select SYS_HAS_EARLY_PRINTK
>> 424 select SYS_HAS_CPU_MIPS32_R2
>> 425 select SYS_SUPPORTS_32BIT_KERNEL
>> 426 select SYS_SUPPORTS_BIG_ENDIAN
>> 427 select SYS_SUPPORTS_HIGHMEM
>> 428 select USB_OHCI_LITTLE_ENDIAN
>> 429 help
>> 430 This enables support for the Cisco PowerTV Platform.
>> 431
>> 432 config RALINK
>> 433 bool "Ralink based machines"
>> 434 select CEVT_R4K
>> 435 select CSRC_R4K
>> 436 select BOOT_RAW
>> 437 select DMA_NONCOHERENT
>> 438 select IRQ_CPU
>> 439 select USE_OF
>> 440 select SYS_HAS_CPU_MIPS32_R1
>> 441 select SYS_HAS_CPU_MIPS32_R2
>> 442 select SYS_SUPPORTS_32BIT_KERNEL
>> 443 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 444 select SYS_HAS_EARLY_PRINTK
>> 445 select HAVE_MACH_CLKDEV
>> 446 select CLKDEV_LOOKUP
>> 447
>> 448 config SGI_IP22
>> 449 bool "SGI IP22 (Indy/Indigo2)"
>> 450 select FW_ARC
>> 451 select FW_ARC32
>> 452 select BOOT_ELF32
>> 453 select CEVT_R4K
>> 454 select CSRC_R4K
>> 455 select DEFAULT_SGI_PARTITION
>> 456 select DMA_NONCOHERENT
>> 457 select HW_HAS_EISA
>> 458 select I8253
>> 459 select I8259
>> 460 select IP22_CPU_SCACHE
>> 461 select IRQ_CPU
>> 462 select GENERIC_ISA_DMA_SUPPORT_BROKEN
>> 463 select SGI_HAS_I8042
>> 464 select SGI_HAS_INDYDOG
>> 465 select SGI_HAS_HAL2
>> 466 select SGI_HAS_SEEQ
>> 467 select SGI_HAS_WD93
>> 468 select SGI_HAS_ZILOG
>> 469 select SWAP_IO_SPACE
>> 470 select SYS_HAS_CPU_R4X00
>> 471 select SYS_HAS_CPU_R5000
>> 472 #
>> 473 # Disable EARLY_PRINTK for now since it leads to overwritten prom
>> 474 # memory during early boot on some machines.
>> 475 #
>> 476 # See http://www.linux-mips.org/cgi-bin/mesg.cgi?a=linux-mips&i=20091119164009.GA15038%40deprecation.cyrius.com
>> 477 # for a more details discussion
>> 478 #
>> 479 # select SYS_HAS_EARLY_PRINTK
>> 480 select SYS_SUPPORTS_32BIT_KERNEL
>> 481 select SYS_SUPPORTS_64BIT_KERNEL
>> 482 select SYS_SUPPORTS_BIG_ENDIAN
>> 483 help
>> 484 This are the SGI Indy, Challenge S and Indigo2, as well as certain
>> 485 OEM variants like the Tandem CMN B006S. To compile a Linux kernel
>> 486 that runs on these, say Y here.
>> 487
>> 488 config SGI_IP27
>> 489 bool "SGI IP27 (Origin200/2000)"
>> 490 select FW_ARC
>> 491 select FW_ARC64
>> 492 select BOOT_ELF64
>> 493 select DEFAULT_SGI_PARTITION
>> 494 select DMA_COHERENT
>> 495 select SYS_HAS_EARLY_PRINTK
>> 496 select HW_HAS_PCI
>> 497 select NR_CPUS_DEFAULT_64
>> 498 select SYS_HAS_CPU_R10000
>> 499 select SYS_SUPPORTS_64BIT_KERNEL
>> 500 select SYS_SUPPORTS_BIG_ENDIAN
>> 501 select SYS_SUPPORTS_NUMA
>> 502 select SYS_SUPPORTS_SMP
>> 503 help
>> 504 This are the SGI Origin 200, Origin 2000 and Onyx 2 Graphics
>> 505 workstations. To compile a Linux kernel that runs on these, say Y
>> 506 here.
>> 507
>> 508 config SGI_IP28
>> 509 bool "SGI IP28 (Indigo2 R10k)"
>> 510 select FW_ARC
>> 511 select FW_ARC64
>> 512 select BOOT_ELF64
>> 513 select CEVT_R4K
>> 514 select CSRC_R4K
>> 515 select DEFAULT_SGI_PARTITION
>> 516 select DMA_NONCOHERENT
>> 517 select GENERIC_ISA_DMA_SUPPORT_BROKEN
>> 518 select IRQ_CPU
>> 519 select HW_HAS_EISA
>> 520 select I8253
>> 521 select I8259
>> 522 select SGI_HAS_I8042
>> 523 select SGI_HAS_INDYDOG
>> 524 select SGI_HAS_HAL2
>> 525 select SGI_HAS_SEEQ
>> 526 select SGI_HAS_WD93
>> 527 select SGI_HAS_ZILOG
>> 528 select SWAP_IO_SPACE
>> 529 select SYS_HAS_CPU_R10000
>> 530 #
>> 531 # Disable EARLY_PRINTK for now since it leads to overwritten prom
>> 532 # memory during early boot on some machines.
>> 533 #
>> 534 # See http://www.linux-mips.org/cgi-bin/mesg.cgi?a=linux-mips&i=20091119164009.GA15038%40deprecation.cyrius.com
>> 535 # for a more details discussion
>> 536 #
>> 537 # select SYS_HAS_EARLY_PRINTK
>> 538 select SYS_SUPPORTS_64BIT_KERNEL
>> 539 select SYS_SUPPORTS_BIG_ENDIAN
>> 540 help
>> 541 This is the SGI Indigo2 with R10000 processor. To compile a Linux
>> 542 kernel that runs on these, say Y here.
>> 543
>> 544 config SGI_IP32
>> 545 bool "SGI IP32 (O2)"
>> 546 select FW_ARC
>> 547 select FW_ARC32
>> 548 select BOOT_ELF32
>> 549 select CEVT_R4K
>> 550 select CSRC_R4K
>> 551 select DMA_NONCOHERENT
>> 552 select HW_HAS_PCI
>> 553 select IRQ_CPU
>> 554 select R5000_CPU_SCACHE
>> 555 select RM7000_CPU_SCACHE
>> 556 select SYS_HAS_CPU_R5000
>> 557 select SYS_HAS_CPU_R10000 if BROKEN
>> 558 select SYS_HAS_CPU_RM7000
>> 559 select SYS_HAS_CPU_NEVADA
>> 560 select SYS_SUPPORTS_64BIT_KERNEL
>> 561 select SYS_SUPPORTS_BIG_ENDIAN
>> 562 help
>> 563 If you want this kernel to run on SGI O2 workstation, say Y here.
>> 564
>> 565 config SIBYTE_CRHINE
>> 566 bool "Sibyte BCM91120C-CRhine"
>> 567 select BOOT_ELF32
>> 568 select DMA_COHERENT
>> 569 select SIBYTE_BCM1120
>> 570 select SWAP_IO_SPACE
>> 571 select SYS_HAS_CPU_SB1
>> 572 select SYS_SUPPORTS_BIG_ENDIAN
>> 573 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 574
>> 575 config SIBYTE_CARMEL
>> 576 bool "Sibyte BCM91120x-Carmel"
>> 577 select BOOT_ELF32
>> 578 select DMA_COHERENT
>> 579 select SIBYTE_BCM1120
>> 580 select SWAP_IO_SPACE
>> 581 select SYS_HAS_CPU_SB1
>> 582 select SYS_SUPPORTS_BIG_ENDIAN
>> 583 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 584
>> 585 config SIBYTE_CRHONE
>> 586 bool "Sibyte BCM91125C-CRhone"
>> 587 select BOOT_ELF32
>> 588 select DMA_COHERENT
>> 589 select SIBYTE_BCM1125
>> 590 select SWAP_IO_SPACE
>> 591 select SYS_HAS_CPU_SB1
>> 592 select SYS_SUPPORTS_BIG_ENDIAN
>> 593 select SYS_SUPPORTS_HIGHMEM
>> 594 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 595
>> 596 config SIBYTE_RHONE
>> 597 bool "Sibyte BCM91125E-Rhone"
>> 598 select BOOT_ELF32
>> 599 select DMA_COHERENT
>> 600 select SIBYTE_BCM1125H
>> 601 select SWAP_IO_SPACE
>> 602 select SYS_HAS_CPU_SB1
>> 603 select SYS_SUPPORTS_BIG_ENDIAN
>> 604 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 605
>> 606 config SIBYTE_SWARM
>> 607 bool "Sibyte BCM91250A-SWARM"
>> 608 select BOOT_ELF32
>> 609 select DMA_COHERENT
>> 610 select HAVE_PATA_PLATFORM
>> 611 select NR_CPUS_DEFAULT_2
>> 612 select SIBYTE_SB1250
>> 613 select SWAP_IO_SPACE
>> 614 select SYS_HAS_CPU_SB1
>> 615 select SYS_SUPPORTS_BIG_ENDIAN
>> 616 select SYS_SUPPORTS_HIGHMEM
>> 617 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 618 select ZONE_DMA32 if 64BIT
>> 619
>> 620 config SIBYTE_LITTLESUR
>> 621 bool "Sibyte BCM91250C2-LittleSur"
>> 622 select BOOT_ELF32
>> 623 select DMA_COHERENT
>> 624 select HAVE_PATA_PLATFORM
>> 625 select NR_CPUS_DEFAULT_2
>> 626 select SIBYTE_SB1250
>> 627 select SWAP_IO_SPACE
>> 628 select SYS_HAS_CPU_SB1
>> 629 select SYS_SUPPORTS_BIG_ENDIAN
>> 630 select SYS_SUPPORTS_HIGHMEM
>> 631 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 632
>> 633 config SIBYTE_SENTOSA
>> 634 bool "Sibyte BCM91250E-Sentosa"
>> 635 select BOOT_ELF32
>> 636 select DMA_COHERENT
>> 637 select NR_CPUS_DEFAULT_2
>> 638 select SIBYTE_SB1250
>> 639 select SWAP_IO_SPACE
>> 640 select SYS_HAS_CPU_SB1
>> 641 select SYS_SUPPORTS_BIG_ENDIAN
>> 642 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 643
>> 644 config SIBYTE_BIGSUR
>> 645 bool "Sibyte BCM91480B-BigSur"
>> 646 select BOOT_ELF32
>> 647 select DMA_COHERENT
>> 648 select NR_CPUS_DEFAULT_4
>> 649 select SIBYTE_BCM1x80
>> 650 select SWAP_IO_SPACE
>> 651 select SYS_HAS_CPU_SB1
>> 652 select SYS_SUPPORTS_BIG_ENDIAN
>> 653 select SYS_SUPPORTS_HIGHMEM
>> 654 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 655 select ZONE_DMA32 if 64BIT
>> 656
>> 657 config SNI_RM
>> 658 bool "SNI RM200/300/400"
>> 659 select FW_ARC if CPU_LITTLE_ENDIAN
>> 660 select FW_ARC32 if CPU_LITTLE_ENDIAN
>> 661 select FW_SNIPROM if CPU_BIG_ENDIAN
>> 662 select ARCH_MAY_HAVE_PC_FDC
>> 663 select BOOT_ELF32
>> 664 select CEVT_R4K
>> 665 select CSRC_R4K
>> 666 select DEFAULT_SGI_PARTITION if CPU_BIG_ENDIAN
>> 667 select DMA_NONCOHERENT
>> 668 select GENERIC_ISA_DMA
>> 669 select HAVE_PCSPKR_PLATFORM
>> 670 select HW_HAS_EISA
>> 671 select HW_HAS_PCI
>> 672 select IRQ_CPU
>> 673 select I8253
>> 674 select I8259
>> 675 select ISA
>> 676 select SWAP_IO_SPACE if CPU_BIG_ENDIAN
>> 677 select SYS_HAS_CPU_R4X00
>> 678 select SYS_HAS_CPU_R5000
>> 679 select SYS_HAS_CPU_R10000
>> 680 select R5000_CPU_SCACHE
>> 681 select SYS_HAS_EARLY_PRINTK
>> 682 select SYS_SUPPORTS_32BIT_KERNEL
>> 683 select SYS_SUPPORTS_64BIT_KERNEL
>> 684 select SYS_SUPPORTS_BIG_ENDIAN
>> 685 select SYS_SUPPORTS_HIGHMEM
>> 686 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 687 help
>> 688 The SNI RM200/300/400 are MIPS-based machines manufactured by
>> 689 Siemens Nixdorf Informationssysteme (SNI), parent company of Pyramid
>> 690 Technology and now in turn merged with Fujitsu. Say Y here to
>> 691 support this machine type.
>> 692
>> 693 config MACH_TX39XX
>> 694 bool "Toshiba TX39 series based machines"
>> 695
>> 696 config MACH_TX49XX
>> 697 bool "Toshiba TX49 series based machines"
>> 698
>> 699 config MIKROTIK_RB532
>> 700 bool "Mikrotik RB532 boards"
>> 701 select CEVT_R4K
>> 702 select CSRC_R4K
>> 703 select DMA_NONCOHERENT
>> 704 select HW_HAS_PCI
>> 705 select IRQ_CPU
>> 706 select SYS_HAS_CPU_MIPS32_R1
>> 707 select SYS_SUPPORTS_32BIT_KERNEL
>> 708 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 709 select SWAP_IO_SPACE
>> 710 select BOOT_RAW
>> 711 select ARCH_REQUIRE_GPIOLIB
>> 712 help
>> 713 Support the Mikrotik(tm) RouterBoard 532 series,
>> 714 based on the IDT RC32434 SoC.
>> 715
>> 716 config WR_PPMC
>> 717 bool "Wind River PPMC board"
>> 718 select CEVT_R4K
>> 719 select CSRC_R4K
>> 720 select IRQ_CPU
>> 721 select BOOT_ELF32
>> 722 select DMA_NONCOHERENT
>> 723 select HW_HAS_PCI
>> 724 select PCI_GT64XXX_PCI0
>> 725 select SWAP_IO_SPACE
>> 726 select SYS_HAS_CPU_MIPS32_R1
>> 727 select SYS_HAS_CPU_MIPS32_R2
>> 728 select SYS_HAS_CPU_MIPS64_R1
>> 729 select SYS_HAS_CPU_NEVADA
>> 730 select SYS_HAS_CPU_RM7000
>> 731 select SYS_SUPPORTS_32BIT_KERNEL
>> 732 select SYS_SUPPORTS_64BIT_KERNEL
>> 733 select SYS_SUPPORTS_BIG_ENDIAN
>> 734 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 735 help
>> 736 This enables support for the Wind River MIPS32 4KC PPMC evaluation
>> 737 board, which is based on GT64120 bridge chip.
>> 738
>> 739 config CAVIUM_OCTEON_SIMULATOR
>> 740 bool "Cavium Networks Octeon Simulator"
>> 741 select CEVT_R4K
>> 742 select 64BIT_PHYS_ADDR
>> 743 select DMA_COHERENT
>> 744 select SYS_SUPPORTS_64BIT_KERNEL
>> 745 select SYS_SUPPORTS_BIG_ENDIAN
>> 746 select SYS_SUPPORTS_HOTPLUG_CPU
>> 747 select SYS_HAS_CPU_CAVIUM_OCTEON
>> 748 select HOLES_IN_ZONE
>> 749 help
>> 750 The Octeon simulator is software performance model of the Cavium
>> 751 Octeon Processor. It supports simulating Octeon processors on x86
>> 752 hardware.
>> 753
>> 754 config CAVIUM_OCTEON_REFERENCE_BOARD
>> 755 bool "Cavium Networks Octeon reference board"
>> 756 select CEVT_R4K
>> 757 select 64BIT_PHYS_ADDR
>> 758 select DMA_COHERENT
>> 759 select SYS_SUPPORTS_64BIT_KERNEL
>> 760 select SYS_SUPPORTS_BIG_ENDIAN
>> 761 select EDAC_SUPPORT
>> 762 select SYS_SUPPORTS_HOTPLUG_CPU
>> 763 select SYS_HAS_EARLY_PRINTK
>> 764 select SYS_HAS_CPU_CAVIUM_OCTEON
>> 765 select SWAP_IO_SPACE
>> 766 select HW_HAS_PCI
>> 767 select ARCH_SUPPORTS_MSI
>> 768 select ZONE_DMA32
>> 769 select USB_ARCH_HAS_OHCI
>> 770 select USB_ARCH_HAS_EHCI
>> 771 select HOLES_IN_ZONE
>> 772 help
>> 773 This option supports all of the Octeon reference boards from Cavium
>> 774 Networks. It builds a kernel that dynamically determines the Octeon
>> 775 CPU type and supports all known board reference implementations.
>> 776 Some of the supported boards are:
>> 777 EBT3000
>> 778 EBH3000
>> 779 EBH3100
>> 780 Thunder
>> 781 Kodama
>> 782 Hikari
>> 783 Say Y here for most Octeon reference boards.
>> 784
>> 785 config NLM_XLR_BOARD
>> 786 bool "Netlogic XLR/XLS based systems"
>> 787 select BOOT_ELF32
>> 788 select NLM_COMMON
>> 789 select SYS_HAS_CPU_XLR
>> 790 select SYS_SUPPORTS_SMP
>> 791 select HW_HAS_PCI
>> 792 select SWAP_IO_SPACE
>> 793 select SYS_SUPPORTS_32BIT_KERNEL
>> 794 select SYS_SUPPORTS_64BIT_KERNEL
>> 795 select 64BIT_PHYS_ADDR
>> 796 select SYS_SUPPORTS_BIG_ENDIAN
>> 797 select SYS_SUPPORTS_HIGHMEM
>> 798 select DMA_COHERENT
>> 799 select NR_CPUS_DEFAULT_32
>> 800 select CEVT_R4K
>> 801 select CSRC_R4K
>> 802 select IRQ_CPU
>> 803 select ARCH_SUPPORTS_MSI
>> 804 select ZONE_DMA32 if 64BIT
>> 805 select SYNC_R4K
>> 806 select SYS_HAS_EARLY_PRINTK
>> 807 select USB_ARCH_HAS_OHCI if USB_SUPPORT
>> 808 select USB_ARCH_HAS_EHCI if USB_SUPPORT
>> 809 help
>> 810 Support for systems based on Netlogic XLR and XLS processors.
>> 811 Say Y here if you have a XLR or XLS based board.
>> 812
>> 813 config NLM_XLP_BOARD
>> 814 bool "Netlogic XLP based systems"
>> 815 select BOOT_ELF32
>> 816 select NLM_COMMON
>> 817 select SYS_HAS_CPU_XLP
>> 818 select SYS_SUPPORTS_SMP
>> 819 select HW_HAS_PCI
>> 820 select SYS_SUPPORTS_32BIT_KERNEL
>> 821 select SYS_SUPPORTS_64BIT_KERNEL
>> 822 select 64BIT_PHYS_ADDR
>> 823 select SYS_SUPPORTS_BIG_ENDIAN
>> 824 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 825 select SYS_SUPPORTS_HIGHMEM
>> 826 select DMA_COHERENT
>> 827 select NR_CPUS_DEFAULT_32
>> 828 select CEVT_R4K
>> 829 select CSRC_R4K
>> 830 select IRQ_CPU
>> 831 select ZONE_DMA32 if 64BIT
>> 832 select SYNC_R4K
>> 833 select SYS_HAS_EARLY_PRINTK
>> 834 select USE_OF
>> 835 help
>> 836 This board is based on Netlogic XLP Processor.
>> 837 Say Y here if you have a XLP based board.
375 838
376 config FIX_EARLYCON_MEM !! 839 endchoice
377 def_bool y <<
378 840
379 config PGTABLE_LEVELS !! 841 source "arch/mips/alchemy/Kconfig"
380 int !! 842 source "arch/mips/ath79/Kconfig"
381 default 2 if ARM64_16K_PAGES && ARM64_ !! 843 source "arch/mips/bcm47xx/Kconfig"
382 default 2 if ARM64_64K_PAGES && ARM64_ !! 844 source "arch/mips/bcm63xx/Kconfig"
383 default 3 if ARM64_64K_PAGES && (ARM64 !! 845 source "arch/mips/jazz/Kconfig"
384 default 3 if ARM64_4K_PAGES && ARM64_V !! 846 source "arch/mips/jz4740/Kconfig"
385 default 3 if ARM64_16K_PAGES && ARM64_ !! 847 source "arch/mips/lantiq/Kconfig"
386 default 4 if ARM64_16K_PAGES && (ARM64 !! 848 source "arch/mips/lasat/Kconfig"
387 default 4 if !ARM64_64K_PAGES && ARM64 !! 849 source "arch/mips/pmcs-msp71xx/Kconfig"
388 default 5 if ARM64_4K_PAGES && ARM64_V !! 850 source "arch/mips/powertv/Kconfig"
>> 851 source "arch/mips/ralink/Kconfig"
>> 852 source "arch/mips/sgi-ip27/Kconfig"
>> 853 source "arch/mips/sibyte/Kconfig"
>> 854 source "arch/mips/txx9/Kconfig"
>> 855 source "arch/mips/vr41xx/Kconfig"
>> 856 source "arch/mips/cavium-octeon/Kconfig"
>> 857 source "arch/mips/loongson/Kconfig"
>> 858 source "arch/mips/loongson1/Kconfig"
>> 859 source "arch/mips/netlogic/Kconfig"
389 860
390 config ARCH_SUPPORTS_UPROBES !! 861 endmenu
391 def_bool y <<
392 862
393 config ARCH_PROC_KCORE_TEXT !! 863 config RWSEM_GENERIC_SPINLOCK
394 def_bool y !! 864 bool
>> 865 default y
395 866
396 config BROKEN_GAS_INST !! 867 config RWSEM_XCHGADD_ALGORITHM
397 def_bool !$(as-instr,1:\n.inst 0\n.rep !! 868 bool
398 869
399 config BUILTIN_RETURN_ADDRESS_STRIPS_PAC !! 870 config ARCH_HAS_ILOG2_U32
400 bool 871 bool
401 # Clang's __builtin_return_address() s <<
402 # https://github.com/llvm/llvm-project <<
403 default y if CC_IS_CLANG <<
404 # GCC's __builtin_return_address() str <<
405 # and this was backported to 10.2.0, 9 <<
406 # https://gcc.gnu.org/bugzilla/show_bu <<
407 default y if CC_IS_GCC && (GCC_VERSION <<
408 default y if CC_IS_GCC && (GCC_VERSION <<
409 default y if CC_IS_GCC && (GCC_VERSION <<
410 default y if CC_IS_GCC && (GCC_VERSION <<
411 default n 872 default n
412 873
413 config KASAN_SHADOW_OFFSET !! 874 config ARCH_HAS_ILOG2_U64
414 hex <<
415 depends on KASAN_GENERIC || KASAN_SW_T <<
416 default 0xdfff800000000000 if (ARM64_V <<
417 default 0xdfffc00000000000 if (ARM64_V <<
418 default 0xdffffe0000000000 if ARM64_VA <<
419 default 0xdfffffc000000000 if ARM64_VA <<
420 default 0xdffffff800000000 if ARM64_VA <<
421 default 0xefff800000000000 if (ARM64_V <<
422 default 0xefffc00000000000 if (ARM64_V <<
423 default 0xeffffe0000000000 if ARM64_VA <<
424 default 0xefffffc000000000 if ARM64_VA <<
425 default 0xeffffff800000000 if ARM64_VA <<
426 default 0xffffffffffffffff <<
427 <<
428 config UNWIND_TABLES <<
429 bool <<
430 <<
431 source "arch/arm64/Kconfig.platforms" <<
432 <<
433 menu "Kernel Features" <<
434 <<
435 menu "ARM errata workarounds via the alternati <<
436 <<
437 config AMPERE_ERRATUM_AC03_CPU_38 <<
438 bool "AmpereOne: AC03_CPU_38: Certain <<
439 default y <<
440 help <<
441 This option adds an alternative code <<
442 errata AC03_CPU_38 and AC04_CPU_10 o <<
443 <<
444 The affected design reports FEAT_HAF <<
445 ID_AA64MMFR1_EL1.HAFDBS, but (V)TCR_ <<
446 as required by the architecture. The <<
447 implementation suffers from an addit <<
448 A/D updates can occur after a PTE ha <<
449 <<
450 The workaround forces KVM to explici <<
451 which avoids enabling unadvertised h <<
452 at stage-2. <<
453 <<
454 If unsure, say Y. <<
455 <<
456 config ARM64_WORKAROUND_CLEAN_CACHE <<
457 bool 875 bool
>> 876 default n
458 877
459 config ARM64_ERRATUM_826319 !! 878 config GENERIC_HWEIGHT
460 bool "Cortex-A53: 826319: System might !! 879 bool
461 default y <<
462 select ARM64_WORKAROUND_CLEAN_CACHE <<
463 help <<
464 This option adds an alternative code <<
465 erratum 826319 on Cortex-A53 parts u <<
466 AXI master interface and an L2 cache <<
467 <<
468 If a Cortex-A53 uses an AMBA AXI4 AC <<
469 and is unable to accept a certain wr <<
470 not progress on read data presented <<
471 system can deadlock. <<
472 <<
473 The workaround promotes data cache c <<
474 data cache clean-and-invalidate. <<
475 Please note that this does not neces <<
476 as it depends on the alternative fra <<
477 the kernel if an affected CPU is det <<
478 <<
479 If unsure, say Y. <<
480 <<
481 config ARM64_ERRATUM_827319 <<
482 bool "Cortex-A53: 827319: Data cache c <<
483 default y <<
484 select ARM64_WORKAROUND_CLEAN_CACHE <<
485 help <<
486 This option adds an alternative code <<
487 erratum 827319 on Cortex-A53 parts u <<
488 master interface and an L2 cache. <<
489 <<
490 Under certain conditions this erratu <<
491 to occur at the same time as another <<
492 on the AMBA 5 CHI interface, which c <<
493 interconnect reorders the two transa <<
494 <<
495 The workaround promotes data cache c <<
496 data cache clean-and-invalidate. <<
497 Please note that this does not neces <<
498 as it depends on the alternative fra <<
499 the kernel if an affected CPU is det <<
500 <<
501 If unsure, say Y. <<
502 <<
503 config ARM64_ERRATUM_824069 <<
504 bool "Cortex-A53: 824069: Cache line m <<
505 default y 880 default y
506 select ARM64_WORKAROUND_CLEAN_CACHE <<
507 help <<
508 This option adds an alternative code <<
509 erratum 824069 on Cortex-A53 parts u <<
510 to a coherent interconnect. <<
511 <<
512 If a Cortex-A53 processor is executi <<
513 write instruction at the same time a <<
514 cluster is executing a cache mainten <<
515 address, then this erratum might cau <<
516 incorrectly marked as dirty. <<
517 <<
518 The workaround promotes data cache c <<
519 data cache clean-and-invalidate. <<
520 Please note that this option does no <<
521 workaround, as it depends on the alt <<
522 only patch the kernel if an affected <<
523 <<
524 If unsure, say Y. <<
525 881
526 config ARM64_ERRATUM_819472 !! 882 config GENERIC_CALIBRATE_DELAY
527 bool "Cortex-A53: 819472: Store exclus !! 883 bool
528 default y 884 default y
529 select ARM64_WORKAROUND_CLEAN_CACHE <<
530 help <<
531 This option adds an alternative code <<
532 erratum 819472 on Cortex-A53 parts u <<
533 present when it is connected to a co <<
534 <<
535 If the processor is executing a load <<
536 the same time as a processor in anot <<
537 maintenance operation to the same ad <<
538 cause data corruption. <<
539 <<
540 The workaround promotes data cache c <<
541 data cache clean-and-invalidate. <<
542 Please note that this does not neces <<
543 as it depends on the alternative fra <<
544 the kernel if an affected CPU is det <<
545 <<
546 If unsure, say Y. <<
547 885
548 config ARM64_ERRATUM_832075 !! 886 config SCHED_OMIT_FRAME_POINTER
549 bool "Cortex-A57: 832075: possible dea !! 887 bool
550 default y 888 default y
551 help <<
552 This option adds an alternative code <<
553 erratum 832075 on Cortex-A57 parts u <<
554 <<
555 Affected Cortex-A57 parts might dead <<
556 instructions to Write-Back memory ar <<
557 889
558 The workaround is to promote device !! 890 #
559 semantics. !! 891 # Select some configuration options automatically based on user selections.
560 Please note that this does not neces !! 892 #
561 as it depends on the alternative fra !! 893 config FW_ARC
562 the kernel if an affected CPU is det !! 894 bool
563 <<
564 If unsure, say Y. <<
565 895
566 config ARM64_ERRATUM_834220 !! 896 config ARCH_MAY_HAVE_PC_FDC
567 bool "Cortex-A57: 834220: Stage 2 tran !! 897 bool
568 depends on KVM <<
569 help <<
570 This option adds an alternative code <<
571 erratum 834220 on Cortex-A57 parts u <<
572 <<
573 Affected Cortex-A57 parts might repo <<
574 fault as the result of a Stage 1 fau <<
575 page boundary when there is a permis <<
576 alignment fault at Stage 1 and a tra <<
577 <<
578 The workaround is to verify that the <<
579 doesn't generate a fault before hand <<
580 Please note that this does not neces <<
581 as it depends on the alternative fra <<
582 the kernel if an affected CPU is det <<
583 898
584 If unsure, say N. !! 899 config BOOT_RAW
>> 900 bool
585 901
586 config ARM64_ERRATUM_1742098 !! 902 config CEVT_BCM1480
587 bool "Cortex-A57/A72: 1742098: ELR rec !! 903 bool
588 depends on COMPAT <<
589 default y <<
590 help <<
591 This option removes the AES hwcap fo <<
592 workaround erratum 1742098 on Cortex <<
593 <<
594 Affected parts may corrupt the AES s <<
595 taken between a pair of AES instruct <<
596 are only present if the cryptography <<
597 All software should have a fallback <<
598 that don't implement the cryptograph <<
599 904
600 If unsure, say Y. !! 905 config CEVT_DS1287
>> 906 bool
601 907
602 config ARM64_ERRATUM_845719 !! 908 config CEVT_GT641XX
603 bool "Cortex-A53: 845719: a load might !! 909 bool
604 depends on COMPAT <<
605 default y <<
606 help <<
607 This option adds an alternative code <<
608 erratum 845719 on Cortex-A53 parts u <<
609 <<
610 When running a compat (AArch32) user <<
611 part, a load at EL0 from a virtual a <<
612 bits of the virtual address used by <<
613 might return incorrect data. <<
614 <<
615 The workaround is to write the conte <<
616 return to a 32-bit task. <<
617 Please note that this does not neces <<
618 as it depends on the alternative fra <<
619 the kernel if an affected CPU is det <<
620 910
621 If unsure, say Y. !! 911 config CEVT_R4K
>> 912 bool
622 913
623 config ARM64_ERRATUM_843419 !! 914 config CEVT_GIC
624 bool "Cortex-A53: 843419: A load or st !! 915 bool
625 default y <<
626 help <<
627 This option links the kernel with '- <<
628 enables PLT support to replace certa <<
629 cause subsequent memory accesses to <<
630 Cortex-A53 parts up to r0p4. <<
631 916
632 If unsure, say Y. !! 917 config CEVT_SB1250
>> 918 bool
633 919
634 config ARM64_LD_HAS_FIX_ERRATUM_843419 !! 920 config CEVT_TXX9
635 def_bool $(ld-option,--fix-cortex-a53- !! 921 bool
636 922
637 config ARM64_ERRATUM_1024718 !! 923 config CSRC_BCM1480
638 bool "Cortex-A55: 1024718: Update of D !! 924 bool
639 default y <<
640 help <<
641 This option adds a workaround for AR <<
642 925
643 Affected Cortex-A55 cores (all revis !! 926 config CSRC_IOASIC
644 update of the hardware dirty bit whe !! 927 bool
645 without a break-before-make. The wor <<
646 of hardware DBM locally on the affec <<
647 this erratum will continue to use th <<
648 928
649 If unsure, say Y. !! 929 config CSRC_POWERTV
>> 930 bool
650 931
651 config ARM64_ERRATUM_1418040 !! 932 config CSRC_R4K
652 bool "Cortex-A76/Neoverse-N1: MRC read !! 933 bool
653 default y <<
654 depends on COMPAT <<
655 help <<
656 This option adds a workaround for AR <<
657 errata 1188873 and 1418040. <<
658 934
659 Affected Cortex-A76/Neoverse-N1 core !! 935 config CSRC_GIC
660 cause register corruption when acces !! 936 bool
661 from AArch32 userspace. <<
662 937
663 If unsure, say Y. !! 938 config CSRC_SB1250
>> 939 bool
664 940
665 config ARM64_WORKAROUND_SPECULATIVE_AT !! 941 config GPIO_TXX9
>> 942 select ARCH_REQUIRE_GPIOLIB
666 bool 943 bool
667 944
668 config ARM64_ERRATUM_1165522 !! 945 config FW_CFE
669 bool "Cortex-A76: 1165522: Speculative !! 946 bool
670 default y <<
671 select ARM64_WORKAROUND_SPECULATIVE_AT <<
672 help <<
673 This option adds a workaround for AR <<
674 947
675 Affected Cortex-A76 cores (r0p0, r1p !! 948 config ARCH_DMA_ADDR_T_64BIT
676 corrupted TLBs by speculating an AT !! 949 def_bool (HIGHMEM && 64BIT_PHYS_ADDR) || 64BIT
677 context switch. <<
678 950
679 If unsure, say Y. !! 951 config DMA_COHERENT
>> 952 bool
680 953
681 config ARM64_ERRATUM_1319367 !! 954 config DMA_NONCOHERENT
682 bool "Cortex-A57/A72: 1319537: Specula !! 955 bool
683 default y !! 956 select NEED_DMA_MAP_STATE
684 select ARM64_WORKAROUND_SPECULATIVE_AT <<
685 help <<
686 This option adds work arounds for AR <<
687 and A72 erratum 1319367 <<
688 957
689 Cortex-A57 and A72 cores could end-u !! 958 config NEED_DMA_MAP_STATE
690 speculating an AT instruction during !! 959 bool
691 960
692 If unsure, say Y. !! 961 config SYS_HAS_EARLY_PRINTK
>> 962 bool
693 963
694 config ARM64_ERRATUM_1530923 !! 964 config HOTPLUG_CPU
695 bool "Cortex-A55: 1530923: Speculative !! 965 bool "Support for hot-pluggable CPUs"
696 default y !! 966 depends on SMP && HOTPLUG && SYS_SUPPORTS_HOTPLUG_CPU
697 select ARM64_WORKAROUND_SPECULATIVE_AT <<
698 help 967 help
699 This option adds a workaround for AR !! 968 Say Y here to allow turning CPUs off and on. CPUs can be
700 !! 969 controlled through /sys/devices/system/cpu.
701 Affected Cortex-A55 cores (r0p0, r0p !! 970 (Note: power management support will enable this option
702 corrupted TLBs by speculating an AT !! 971 automatically on SMP systems. )
703 context switch. !! 972 Say N if you want to disable CPU hotplug.
704 973
705 If unsure, say Y. !! 974 config SYS_SUPPORTS_HOTPLUG_CPU
>> 975 bool
706 976
707 config ARM64_WORKAROUND_REPEAT_TLBI !! 977 config I8259
708 bool 978 bool
709 979
710 config ARM64_ERRATUM_2441007 !! 980 config MIPS_BONITO64
711 bool "Cortex-A55: Completion of affect !! 981 bool
712 select ARM64_WORKAROUND_REPEAT_TLBI <<
713 help <<
714 This option adds a workaround for AR <<
715 982
716 Under very rare circumstances, affec !! 983 config MIPS_MSC
717 may not handle a race between a brea !! 984 bool
718 CPU, and another CPU accessing the s <<
719 store to a page that has been unmapp <<
720 985
721 Work around this by adding the affec !! 986 config MIPS_NILE4
722 TLB sequences to be done twice. !! 987 bool
723 988
724 If unsure, say N. !! 989 config SYNC_R4K
>> 990 bool
725 991
726 config ARM64_ERRATUM_1286807 !! 992 config MIPS_MACHINE
727 bool "Cortex-A76: Modification of the !! 993 def_bool n
728 select ARM64_WORKAROUND_REPEAT_TLBI <<
729 help <<
730 This option adds a workaround for AR <<
731 <<
732 On the affected Cortex-A76 cores (r0 <<
733 address for a cacheable mapping of a <<
734 accessed by a core while another cor <<
735 address to a new physical page using <<
736 break-before-make sequence, then und <<
737 TLBI+DSB completes before a read usi <<
738 invalidated has been observed by oth <<
739 workaround repeats the TLBI+DSB oper <<
740 994
741 If unsure, say N. !! 995 config NO_IOPORT
>> 996 def_bool n
742 997
743 config ARM64_ERRATUM_1463225 !! 998 config GENERIC_ISA_DMA
744 bool "Cortex-A76: Software Step might !! 999 bool
745 default y !! 1000 select ZONE_DMA if GENERIC_ISA_DMA_SUPPORT_BROKEN=n
746 help !! 1001 select ISA_DMA_API
747 This option adds a workaround for Ar <<
748 1002
749 On the affected Cortex-A76 cores (r0 !! 1003 config GENERIC_ISA_DMA_SUPPORT_BROKEN
750 of a system call instruction (SVC) c !! 1004 bool
751 subsequent interrupts when software !! 1005 select GENERIC_ISA_DMA
752 exception handler of the system call <<
753 is enabled or VHE is in use. <<
754 1006
755 Work around the erratum by triggerin !! 1007 config ISA_DMA_API
756 when handling a system call from a t !! 1008 bool
757 in a VHE configuration of the kernel <<
758 1009
759 If unsure, say Y. !! 1010 config HOLES_IN_ZONE
>> 1011 bool
760 1012
761 config ARM64_ERRATUM_1542419 !! 1013 #
762 bool "Neoverse-N1: workaround mis-orde !! 1014 # Endianness selection. Sufficiently obscure so many users don't know what to
>> 1015 # answer,so we try hard to limit the available choices. Also the use of a
>> 1016 # choice statement should be more obvious to the user.
>> 1017 #
>> 1018 choice
>> 1019 prompt "Endianness selection"
763 help 1020 help
764 This option adds a workaround for AR !! 1021 Some MIPS machines can be configured for either little or big endian
765 1542419. !! 1022 byte order. These modes require different kernels and a different
>> 1023 Linux distribution. In general there is one preferred byteorder for a
>> 1024 particular system but some systems are just as commonly used in the
>> 1025 one or the other endianness.
766 1026
767 Affected Neoverse-N1 cores could exe !! 1027 config CPU_BIG_ENDIAN
768 modified by another CPU. The workaro !! 1028 bool "Big endian"
769 counterpart. !! 1029 depends on SYS_SUPPORTS_BIG_ENDIAN
770 <<
771 Workaround the issue by hiding the D <<
772 forces user-space to perform cache m <<
773 <<
774 If unsure, say N. <<
775 1030
776 config ARM64_ERRATUM_1508412 !! 1031 config CPU_LITTLE_ENDIAN
777 bool "Cortex-A77: 1508412: workaround !! 1032 bool "Little endian"
778 default y !! 1033 depends on SYS_SUPPORTS_LITTLE_ENDIAN
779 help 1034 help
780 This option adds a workaround for Ar <<
781 <<
782 Affected Cortex-A77 cores (r0p0, r1p <<
783 of a store-exclusive or read of PAR_ <<
784 non-cacheable memory attributes. The <<
785 counterpart. <<
786 <<
787 KVM guests must also have the workar <<
788 deadlock the system. <<
789 1035
790 Work around the issue by inserting D !! 1036 endchoice
791 register reads and warning KVM users <<
792 to prevent a speculative PAR_EL1 rea <<
793 1037
794 If unsure, say Y. !! 1038 config EXPORT_UASM
>> 1039 bool
795 1040
796 config ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MO !! 1041 config SYS_SUPPORTS_APM_EMULATION
797 bool 1042 bool
798 1043
799 config ARM64_ERRATUM_2051678 !! 1044 config SYS_SUPPORTS_BIG_ENDIAN
800 bool "Cortex-A510: 2051678: disable Ha !! 1045 bool
801 default y <<
802 help <<
803 This options adds the workaround for <<
804 Affected Cortex-A510 might not respe <<
805 hardware update of the page table's <<
806 is to not enable the feature on affe <<
807 1046
808 If unsure, say Y. !! 1047 config SYS_SUPPORTS_LITTLE_ENDIAN
>> 1048 bool
809 1049
810 config ARM64_ERRATUM_2077057 !! 1050 config SYS_SUPPORTS_HUGETLBFS
811 bool "Cortex-A510: 2077057: workaround !! 1051 bool
>> 1052 depends on CPU_SUPPORTS_HUGEPAGES && 64BIT
812 default y 1053 default y
813 help <<
814 This option adds the workaround for <<
815 Affected Cortex-A510 may corrupt SPS <<
816 expected, but a Pointer Authenticati <<
817 erratum causes SPSR_EL1 to be copied <<
818 EL1 to cause a return to EL2 with a <<
819 1054
820 This can only happen when EL2 is ste !! 1055 config MIPS_HUGE_TLB_SUPPORT
>> 1056 def_bool HUGETLB_PAGE || TRANSPARENT_HUGEPAGE
821 1057
822 When these conditions occur, the SPS !! 1058 config IRQ_CPU
823 previous guest entry, and can be res !! 1059 bool
824 1060
825 If unsure, say Y. !! 1061 config IRQ_CPU_RM7K
>> 1062 bool
826 1063
827 config ARM64_ERRATUM_2658417 !! 1064 config IRQ_MSP_SLP
828 bool "Cortex-A510: 2658417: remove BF1 !! 1065 bool
829 default y <<
830 help <<
831 This option adds the workaround for <<
832 Affected Cortex-A510 (r0p0 to r1p1) <<
833 BFMMLA or VMMLA instructions in rare <<
834 A510 CPUs are using shared neon hard <<
835 discoverable by the kernel, hide the <<
836 user-space should not be using these <<
837 1066
838 If unsure, say Y. !! 1067 config IRQ_MSP_CIC
>> 1068 bool
839 1069
840 config ARM64_ERRATUM_2119858 !! 1070 config IRQ_TXX9
841 bool "Cortex-A710/X2: 2119858: workaro !! 1071 bool
842 default y <<
843 depends on CORESIGHT_TRBE <<
844 select ARM64_WORKAROUND_TRBE_OVERWRITE <<
845 help <<
846 This option adds the workaround for <<
847 1072
848 Affected Cortex-A710/X2 cores could !! 1073 config IRQ_GT641XX
849 data at the base of the buffer (poin !! 1074 bool
850 the event of a WRAP event. <<
851 1075
852 Work around the issue by always maki !! 1076 config IRQ_GIC
853 256 bytes before enabling the buffer !! 1077 bool
854 the buffer with ETM ignore packets u <<
855 1078
856 If unsure, say Y. !! 1079 config PCI_GT64XXX_PCI0
>> 1080 bool
857 1081
858 config ARM64_ERRATUM_2139208 !! 1082 config NO_EXCEPT_FILL
859 bool "Neoverse-N2: 2139208: workaround !! 1083 bool
860 default y <<
861 depends on CORESIGHT_TRBE <<
862 select ARM64_WORKAROUND_TRBE_OVERWRITE <<
863 help <<
864 This option adds the workaround for <<
865 1084
866 Affected Neoverse-N2 cores could ove !! 1085 config SOC_EMMA2RH
867 data at the base of the buffer (poin !! 1086 bool
868 the event of a WRAP event. !! 1087 select CEVT_R4K
>> 1088 select CSRC_R4K
>> 1089 select DMA_NONCOHERENT
>> 1090 select IRQ_CPU
>> 1091 select SWAP_IO_SPACE
>> 1092 select SYS_HAS_CPU_R5500
>> 1093 select SYS_SUPPORTS_32BIT_KERNEL
>> 1094 select SYS_SUPPORTS_64BIT_KERNEL
>> 1095 select SYS_SUPPORTS_BIG_ENDIAN
869 1096
870 Work around the issue by always maki !! 1097 config SOC_PNX833X
871 256 bytes before enabling the buffer !! 1098 bool
872 the buffer with ETM ignore packets u !! 1099 select CEVT_R4K
>> 1100 select CSRC_R4K
>> 1101 select IRQ_CPU
>> 1102 select DMA_NONCOHERENT
>> 1103 select SYS_HAS_CPU_MIPS32_R2
>> 1104 select SYS_SUPPORTS_32BIT_KERNEL
>> 1105 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 1106 select SYS_SUPPORTS_BIG_ENDIAN
>> 1107 select CPU_MIPSR2_IRQ_VI
873 1108
874 If unsure, say Y. !! 1109 config SOC_PNX8335
>> 1110 bool
>> 1111 select SOC_PNX833X
875 1112
876 config ARM64_WORKAROUND_TSB_FLUSH_FAILURE !! 1113 config SWAP_IO_SPACE
877 bool 1114 bool
878 1115
879 config ARM64_ERRATUM_2054223 !! 1116 config SGI_HAS_INDYDOG
880 bool "Cortex-A710: 2054223: workaround !! 1117 bool
881 default y <<
882 select ARM64_WORKAROUND_TSB_FLUSH_FAIL <<
883 help <<
884 Enable workaround for ARM Cortex-A71 <<
885 1118
886 Affected cores may fail to flush the !! 1119 config SGI_HAS_HAL2
887 the PE is in trace prohibited state. !! 1120 bool
888 of the trace cached. <<
889 1121
890 Workaround is to issue two TSB conse !! 1122 config SGI_HAS_SEEQ
>> 1123 bool
891 1124
892 If unsure, say Y. !! 1125 config SGI_HAS_WD93
>> 1126 bool
893 1127
894 config ARM64_ERRATUM_2067961 !! 1128 config SGI_HAS_ZILOG
895 bool "Neoverse-N2: 2067961: workaround !! 1129 bool
896 default y <<
897 select ARM64_WORKAROUND_TSB_FLUSH_FAIL <<
898 help <<
899 Enable workaround for ARM Neoverse-N <<
900 1130
901 Affected cores may fail to flush the !! 1131 config SGI_HAS_I8042
902 the PE is in trace prohibited state. !! 1132 bool
903 of the trace cached. <<
904 1133
905 Workaround is to issue two TSB conse !! 1134 config DEFAULT_SGI_PARTITION
>> 1135 bool
906 1136
907 If unsure, say Y. !! 1137 config FW_ARC32
>> 1138 bool
908 1139
909 config ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANG !! 1140 config FW_SNIPROM
910 bool 1141 bool
911 1142
912 config ARM64_ERRATUM_2253138 !! 1143 config BOOT_ELF32
913 bool "Neoverse-N2: 2253138: workaround !! 1144 bool
914 depends on CORESIGHT_TRBE <<
915 default y <<
916 select ARM64_WORKAROUND_TRBE_WRITE_OUT <<
917 help <<
918 This option adds the workaround for <<
919 1145
920 Affected Neoverse-N2 cores might wri !! 1146 config MIPS_L1_CACHE_SHIFT
921 for TRBE. Under some conditions, the !! 1147 int
922 virtually addressed page following t !! 1148 default "4" if MACH_DECSTATION || MIKROTIK_RB532 || PMC_MSP4200_EVAL || SOC_RT288X
923 (i.e., the TRBLIMITR_EL1.LIMIT), ins !! 1149 default "6" if MIPS_CPU_SCACHE
>> 1150 default "7" if SGI_IP22 || SGI_IP27 || SGI_IP28 || SNI_RM || CPU_CAVIUM_OCTEON
>> 1151 default "5"
924 1152
925 Work around this in the driver by al !! 1153 config HAVE_STD_PC_SERIAL_PORT
926 page beyond the TRBLIMITR_EL1.LIMIT, !! 1154 bool
927 1155
928 If unsure, say Y. !! 1156 config ARC_CONSOLE
>> 1157 bool "ARC console support"
>> 1158 depends on SGI_IP22 || SGI_IP28 || (SNI_RM && CPU_LITTLE_ENDIAN)
929 1159
930 config ARM64_ERRATUM_2224489 !! 1160 config ARC_MEMORY
931 bool "Cortex-A710/X2: 2224489: workaro !! 1161 bool
932 depends on CORESIGHT_TRBE !! 1162 depends on MACH_JAZZ || SNI_RM || SGI_IP32
933 default y 1163 default y
934 select ARM64_WORKAROUND_TRBE_WRITE_OUT <<
935 help <<
936 This option adds the workaround for <<
937 <<
938 Affected Cortex-A710/X2 cores might <<
939 for TRBE. Under some conditions, the <<
940 virtually addressed page following t <<
941 (i.e., the TRBLIMITR_EL1.LIMIT), ins <<
942 <<
943 Work around this in the driver by al <<
944 page beyond the TRBLIMITR_EL1.LIMIT, <<
945 <<
946 If unsure, say Y. <<
947 <<
948 config ARM64_ERRATUM_2441009 <<
949 bool "Cortex-A510: Completion of affec <<
950 select ARM64_WORKAROUND_REPEAT_TLBI <<
951 help <<
952 This option adds a workaround for AR <<
953 <<
954 Under very rare circumstances, affec <<
955 may not handle a race between a brea <<
956 CPU, and another CPU accessing the s <<
957 store to a page that has been unmapp <<
958 1164
959 Work around this by adding the affec !! 1165 config ARC_PROMLIB
960 TLB sequences to be done twice. !! 1166 bool
961 !! 1167 depends on MACH_JAZZ || SNI_RM || SGI_IP22 || SGI_IP28 || SGI_IP32
962 If unsure, say N. <<
963 <<
964 config ARM64_ERRATUM_2064142 <<
965 bool "Cortex-A510: 2064142: workaround <<
966 depends on CORESIGHT_TRBE <<
967 default y 1168 default y
968 help <<
969 This option adds the workaround for <<
970 <<
971 Affected Cortex-A510 core might fail <<
972 TRBE has been disabled. Under some c <<
973 writes into TRBE registers TRBLIMITR <<
974 and TRBTRG_EL1 will be ignored and w <<
975 1169
976 Work around this in the driver by ex !! 1170 config FW_ARC64
977 is stopped and before performing a s !! 1171 bool
978 registers. <<
979 <<
980 If unsure, say Y. <<
981 <<
982 config ARM64_ERRATUM_2038923 <<
983 bool "Cortex-A510: 2038923: workaround <<
984 depends on CORESIGHT_TRBE <<
985 default y <<
986 help <<
987 This option adds the workaround for <<
988 <<
989 Affected Cortex-A510 core might caus <<
990 prohibited within the CPU. As a resu <<
991 might be corrupted. This happens aft <<
992 TRBLIMITR_EL1.E, followed by just a <<
993 execution changes from a context, in <<
994 isn't, or vice versa. In these menti <<
995 is prohibited is inconsistent betwee <<
996 the trace buffer state might be corr <<
997 <<
998 Work around this in the driver by pr <<
999 trace is prohibited or not based on <<
1000 change to TRBLIMITR_EL1.E with at l <<
1001 two ISB instructions if no ERET is <<
1002 <<
1003 If unsure, say Y. <<
1004 <<
1005 config ARM64_ERRATUM_1902691 <<
1006 bool "Cortex-A510: 1902691: workaroun <<
1007 depends on CORESIGHT_TRBE <<
1008 default y <<
1009 help <<
1010 This option adds the workaround for <<
1011 1172
1012 Affected Cortex-A510 core might cau !! 1173 config BOOT_ELF64
1013 into the memory. Effectively TRBE i !! 1174 bool
1014 trace data. <<
1015 1175
1016 Work around this problem in the dri !! 1176 menu "CPU selection"
1017 affected cpus. The firmware must ha <<
1018 on such implementations. This will <<
1019 do this already. <<
1020 1177
1021 If unsure, say Y. !! 1178 choice
>> 1179 prompt "CPU type"
>> 1180 default CPU_R4X00
1022 1181
1023 config ARM64_ERRATUM_2457168 !! 1182 config CPU_LOONGSON2E
1024 bool "Cortex-A510: 2457168: workaroun !! 1183 bool "Loongson 2E"
1025 depends on ARM64_AMU_EXTN !! 1184 depends on SYS_HAS_CPU_LOONGSON2E
1026 default y !! 1185 select CPU_LOONGSON2
>> 1186 help
>> 1187 The Loongson 2E processor implements the MIPS III instruction set
>> 1188 with many extensions.
>> 1189
>> 1190 It has an internal FPGA northbridge, which is compatible to
>> 1191 bonito64.
>> 1192
>> 1193 config CPU_LOONGSON2F
>> 1194 bool "Loongson 2F"
>> 1195 depends on SYS_HAS_CPU_LOONGSON2F
>> 1196 select CPU_LOONGSON2
>> 1197 select ARCH_REQUIRE_GPIOLIB
>> 1198 help
>> 1199 The Loongson 2F processor implements the MIPS III instruction set
>> 1200 with many extensions.
>> 1201
>> 1202 Loongson2F have built-in DDR2 and PCIX controller. The PCIX controller
>> 1203 have a similar programming interface with FPGA northbridge used in
>> 1204 Loongson2E.
>> 1205
>> 1206 config CPU_LOONGSON1B
>> 1207 bool "Loongson 1B"
>> 1208 depends on SYS_HAS_CPU_LOONGSON1B
>> 1209 select CPU_LOONGSON1
>> 1210 help
>> 1211 The Loongson 1B is a 32-bit SoC, which implements the MIPS32
>> 1212 release 2 instruction set.
>> 1213
>> 1214 config CPU_MIPS32_R1
>> 1215 bool "MIPS32 Release 1"
>> 1216 depends on SYS_HAS_CPU_MIPS32_R1
>> 1217 select CPU_HAS_PREFETCH
>> 1218 select CPU_SUPPORTS_32BIT_KERNEL
>> 1219 select CPU_SUPPORTS_HIGHMEM
>> 1220 help
>> 1221 Choose this option to build a kernel for release 1 or later of the
>> 1222 MIPS32 architecture. Most modern embedded systems with a 32-bit
>> 1223 MIPS processor are based on a MIPS32 processor. If you know the
>> 1224 specific type of processor in your system, choose those that one
>> 1225 otherwise CPU_MIPS32_R1 is a safe bet for any MIPS32 system.
>> 1226 Release 2 of the MIPS32 architecture is available since several
>> 1227 years so chances are you even have a MIPS32 Release 2 processor
>> 1228 in which case you should choose CPU_MIPS32_R2 instead for better
>> 1229 performance.
>> 1230
>> 1231 config CPU_MIPS32_R2
>> 1232 bool "MIPS32 Release 2"
>> 1233 depends on SYS_HAS_CPU_MIPS32_R2
>> 1234 select CPU_HAS_PREFETCH
>> 1235 select CPU_SUPPORTS_32BIT_KERNEL
>> 1236 select CPU_SUPPORTS_HIGHMEM
>> 1237 select HAVE_KVM
>> 1238 help
>> 1239 Choose this option to build a kernel for release 2 or later of the
>> 1240 MIPS32 architecture. Most modern embedded systems with a 32-bit
>> 1241 MIPS processor are based on a MIPS32 processor. If you know the
>> 1242 specific type of processor in your system, choose those that one
>> 1243 otherwise CPU_MIPS32_R1 is a safe bet for any MIPS32 system.
>> 1244
>> 1245 config CPU_MIPS64_R1
>> 1246 bool "MIPS64 Release 1"
>> 1247 depends on SYS_HAS_CPU_MIPS64_R1
>> 1248 select CPU_HAS_PREFETCH
>> 1249 select CPU_SUPPORTS_32BIT_KERNEL
>> 1250 select CPU_SUPPORTS_64BIT_KERNEL
>> 1251 select CPU_SUPPORTS_HIGHMEM
>> 1252 select CPU_SUPPORTS_HUGEPAGES
>> 1253 help
>> 1254 Choose this option to build a kernel for release 1 or later of the
>> 1255 MIPS64 architecture. Many modern embedded systems with a 64-bit
>> 1256 MIPS processor are based on a MIPS64 processor. If you know the
>> 1257 specific type of processor in your system, choose those that one
>> 1258 otherwise CPU_MIPS64_R1 is a safe bet for any MIPS64 system.
>> 1259 Release 2 of the MIPS64 architecture is available since several
>> 1260 years so chances are you even have a MIPS64 Release 2 processor
>> 1261 in which case you should choose CPU_MIPS64_R2 instead for better
>> 1262 performance.
>> 1263
>> 1264 config CPU_MIPS64_R2
>> 1265 bool "MIPS64 Release 2"
>> 1266 depends on SYS_HAS_CPU_MIPS64_R2
>> 1267 select CPU_HAS_PREFETCH
>> 1268 select CPU_SUPPORTS_32BIT_KERNEL
>> 1269 select CPU_SUPPORTS_64BIT_KERNEL
>> 1270 select CPU_SUPPORTS_HIGHMEM
>> 1271 select CPU_SUPPORTS_HUGEPAGES
>> 1272 help
>> 1273 Choose this option to build a kernel for release 2 or later of the
>> 1274 MIPS64 architecture. Many modern embedded systems with a 64-bit
>> 1275 MIPS processor are based on a MIPS64 processor. If you know the
>> 1276 specific type of processor in your system, choose those that one
>> 1277 otherwise CPU_MIPS64_R1 is a safe bet for any MIPS64 system.
>> 1278
>> 1279 config CPU_R3000
>> 1280 bool "R3000"
>> 1281 depends on SYS_HAS_CPU_R3000
>> 1282 select CPU_HAS_WB
>> 1283 select CPU_SUPPORTS_32BIT_KERNEL
>> 1284 select CPU_SUPPORTS_HIGHMEM
>> 1285 help
>> 1286 Please make sure to pick the right CPU type. Linux/MIPS is not
>> 1287 designed to be generic, i.e. Kernels compiled for R3000 CPUs will
>> 1288 *not* work on R4000 machines and vice versa. However, since most
>> 1289 of the supported machines have an R4000 (or similar) CPU, R4x00
>> 1290 might be a safe bet. If the resulting kernel does not work,
>> 1291 try to recompile with R3000.
>> 1292
>> 1293 config CPU_TX39XX
>> 1294 bool "R39XX"
>> 1295 depends on SYS_HAS_CPU_TX39XX
>> 1296 select CPU_SUPPORTS_32BIT_KERNEL
>> 1297
>> 1298 config CPU_VR41XX
>> 1299 bool "R41xx"
>> 1300 depends on SYS_HAS_CPU_VR41XX
>> 1301 select CPU_SUPPORTS_32BIT_KERNEL
>> 1302 select CPU_SUPPORTS_64BIT_KERNEL
>> 1303 help
>> 1304 The options selects support for the NEC VR4100 series of processors.
>> 1305 Only choose this option if you have one of these processors as a
>> 1306 kernel built with this option will not run on any other type of
>> 1307 processor or vice versa.
>> 1308
>> 1309 config CPU_R4300
>> 1310 bool "R4300"
>> 1311 depends on SYS_HAS_CPU_R4300
>> 1312 select CPU_SUPPORTS_32BIT_KERNEL
>> 1313 select CPU_SUPPORTS_64BIT_KERNEL
>> 1314 help
>> 1315 MIPS Technologies R4300-series processors.
>> 1316
>> 1317 config CPU_R4X00
>> 1318 bool "R4x00"
>> 1319 depends on SYS_HAS_CPU_R4X00
>> 1320 select CPU_SUPPORTS_32BIT_KERNEL
>> 1321 select CPU_SUPPORTS_64BIT_KERNEL
>> 1322 select CPU_SUPPORTS_HUGEPAGES
>> 1323 help
>> 1324 MIPS Technologies R4000-series processors other than 4300, including
>> 1325 the R4000, R4400, R4600, and 4700.
>> 1326
>> 1327 config CPU_TX49XX
>> 1328 bool "R49XX"
>> 1329 depends on SYS_HAS_CPU_TX49XX
>> 1330 select CPU_HAS_PREFETCH
>> 1331 select CPU_SUPPORTS_32BIT_KERNEL
>> 1332 select CPU_SUPPORTS_64BIT_KERNEL
>> 1333 select CPU_SUPPORTS_HUGEPAGES
>> 1334
>> 1335 config CPU_R5000
>> 1336 bool "R5000"
>> 1337 depends on SYS_HAS_CPU_R5000
>> 1338 select CPU_SUPPORTS_32BIT_KERNEL
>> 1339 select CPU_SUPPORTS_64BIT_KERNEL
>> 1340 select CPU_SUPPORTS_HUGEPAGES
>> 1341 help
>> 1342 MIPS Technologies R5000-series processors other than the Nevada.
>> 1343
>> 1344 config CPU_R5432
>> 1345 bool "R5432"
>> 1346 depends on SYS_HAS_CPU_R5432
>> 1347 select CPU_SUPPORTS_32BIT_KERNEL
>> 1348 select CPU_SUPPORTS_64BIT_KERNEL
>> 1349 select CPU_SUPPORTS_HUGEPAGES
>> 1350
>> 1351 config CPU_R5500
>> 1352 bool "R5500"
>> 1353 depends on SYS_HAS_CPU_R5500
>> 1354 select CPU_SUPPORTS_32BIT_KERNEL
>> 1355 select CPU_SUPPORTS_64BIT_KERNEL
>> 1356 select CPU_SUPPORTS_HUGEPAGES
>> 1357 help
>> 1358 NEC VR5500 and VR5500A series processors implement 64-bit MIPS IV
>> 1359 instruction set.
>> 1360
>> 1361 config CPU_R6000
>> 1362 bool "R6000"
>> 1363 depends on SYS_HAS_CPU_R6000
>> 1364 select CPU_SUPPORTS_32BIT_KERNEL
>> 1365 help
>> 1366 MIPS Technologies R6000 and R6000A series processors. Note these
>> 1367 processors are extremely rare and the support for them is incomplete.
>> 1368
>> 1369 config CPU_NEVADA
>> 1370 bool "RM52xx"
>> 1371 depends on SYS_HAS_CPU_NEVADA
>> 1372 select CPU_SUPPORTS_32BIT_KERNEL
>> 1373 select CPU_SUPPORTS_64BIT_KERNEL
>> 1374 select CPU_SUPPORTS_HUGEPAGES
>> 1375 help
>> 1376 QED / PMC-Sierra RM52xx-series ("Nevada") processors.
>> 1377
>> 1378 config CPU_R8000
>> 1379 bool "R8000"
>> 1380 depends on SYS_HAS_CPU_R8000
>> 1381 select CPU_HAS_PREFETCH
>> 1382 select CPU_SUPPORTS_64BIT_KERNEL
>> 1383 help
>> 1384 MIPS Technologies R8000 processors. Note these processors are
>> 1385 uncommon and the support for them is incomplete.
>> 1386
>> 1387 config CPU_R10000
>> 1388 bool "R10000"
>> 1389 depends on SYS_HAS_CPU_R10000
>> 1390 select CPU_HAS_PREFETCH
>> 1391 select CPU_SUPPORTS_32BIT_KERNEL
>> 1392 select CPU_SUPPORTS_64BIT_KERNEL
>> 1393 select CPU_SUPPORTS_HIGHMEM
>> 1394 select CPU_SUPPORTS_HUGEPAGES
>> 1395 help
>> 1396 MIPS Technologies R10000-series processors.
>> 1397
>> 1398 config CPU_RM7000
>> 1399 bool "RM7000"
>> 1400 depends on SYS_HAS_CPU_RM7000
>> 1401 select CPU_HAS_PREFETCH
>> 1402 select CPU_SUPPORTS_32BIT_KERNEL
>> 1403 select CPU_SUPPORTS_64BIT_KERNEL
>> 1404 select CPU_SUPPORTS_HIGHMEM
>> 1405 select CPU_SUPPORTS_HUGEPAGES
>> 1406
>> 1407 config CPU_SB1
>> 1408 bool "SB1"
>> 1409 depends on SYS_HAS_CPU_SB1
>> 1410 select CPU_SUPPORTS_32BIT_KERNEL
>> 1411 select CPU_SUPPORTS_64BIT_KERNEL
>> 1412 select CPU_SUPPORTS_HIGHMEM
>> 1413 select CPU_SUPPORTS_HUGEPAGES
>> 1414 select WEAK_ORDERING
>> 1415
>> 1416 config CPU_CAVIUM_OCTEON
>> 1417 bool "Cavium Octeon processor"
>> 1418 depends on SYS_HAS_CPU_CAVIUM_OCTEON
>> 1419 select ARCH_SPARSEMEM_ENABLE
>> 1420 select CPU_HAS_PREFETCH
>> 1421 select CPU_SUPPORTS_64BIT_KERNEL
>> 1422 select SYS_SUPPORTS_SMP
>> 1423 select NR_CPUS_DEFAULT_16
>> 1424 select WEAK_ORDERING
>> 1425 select CPU_SUPPORTS_HIGHMEM
>> 1426 select CPU_SUPPORTS_HUGEPAGES
>> 1427 select LIBFDT
>> 1428 select USE_OF
>> 1429 select USB_EHCI_BIG_ENDIAN_MMIO
1027 help 1430 help
1028 This option adds the workaround for !! 1431 The Cavium Octeon processor is a highly integrated chip containing
1029 !! 1432 many ethernet hardware widgets for networking tasks. The processor
1030 The AMU counter AMEVCNTR01 (constan !! 1433 can have up to 16 Mips64v2 cores and 8 integrated gigabit ethernets.
1031 as the system counter. On affected !! 1434 Full details can be found at http://www.caviumnetworks.com.
1032 incorrectly giving a significantly !! 1435
1033 !! 1436 config CPU_BMIPS3300
1034 Work around this problem by returni !! 1437 bool "BMIPS3300"
1035 key locations that results in disab !! 1438 depends on SYS_HAS_CPU_BMIPS3300
1036 is the same to firmware disabling a !! 1439 select CPU_BMIPS
1037 !! 1440 help
1038 If unsure, say Y. !! 1441 Broadcom BMIPS3300 processors.
1039 !! 1442
1040 config ARM64_ERRATUM_2645198 !! 1443 config CPU_BMIPS4350
1041 bool "Cortex-A715: 2645198: Workaroun !! 1444 bool "BMIPS4350"
1042 default y !! 1445 depends on SYS_HAS_CPU_BMIPS4350
>> 1446 select CPU_BMIPS
>> 1447 select SYS_SUPPORTS_SMP
>> 1448 select SYS_SUPPORTS_HOTPLUG_CPU
>> 1449 help
>> 1450 Broadcom BMIPS4350 ("VIPER") processors.
>> 1451
>> 1452 config CPU_BMIPS4380
>> 1453 bool "BMIPS4380"
>> 1454 depends on SYS_HAS_CPU_BMIPS4380
>> 1455 select CPU_BMIPS
>> 1456 select SYS_SUPPORTS_SMP
>> 1457 select SYS_SUPPORTS_HOTPLUG_CPU
>> 1458 help
>> 1459 Broadcom BMIPS4380 processors.
>> 1460
>> 1461 config CPU_BMIPS5000
>> 1462 bool "BMIPS5000"
>> 1463 depends on SYS_HAS_CPU_BMIPS5000
>> 1464 select CPU_BMIPS
>> 1465 select CPU_SUPPORTS_HIGHMEM
>> 1466 select MIPS_CPU_SCACHE
>> 1467 select SYS_SUPPORTS_SMP
>> 1468 select SYS_SUPPORTS_HOTPLUG_CPU
>> 1469 help
>> 1470 Broadcom BMIPS5000 processors.
>> 1471
>> 1472 config CPU_XLR
>> 1473 bool "Netlogic XLR SoC"
>> 1474 depends on SYS_HAS_CPU_XLR
>> 1475 select CPU_SUPPORTS_32BIT_KERNEL
>> 1476 select CPU_SUPPORTS_64BIT_KERNEL
>> 1477 select CPU_SUPPORTS_HIGHMEM
>> 1478 select CPU_SUPPORTS_HUGEPAGES
>> 1479 select WEAK_ORDERING
>> 1480 select WEAK_REORDERING_BEYOND_LLSC
>> 1481 help
>> 1482 Netlogic Microsystems XLR/XLS processors.
>> 1483
>> 1484 config CPU_XLP
>> 1485 bool "Netlogic XLP SoC"
>> 1486 depends on SYS_HAS_CPU_XLP
>> 1487 select CPU_SUPPORTS_32BIT_KERNEL
>> 1488 select CPU_SUPPORTS_64BIT_KERNEL
>> 1489 select CPU_SUPPORTS_HIGHMEM
>> 1490 select WEAK_ORDERING
>> 1491 select WEAK_REORDERING_BEYOND_LLSC
>> 1492 select CPU_HAS_PREFETCH
>> 1493 select CPU_MIPSR2
1043 help 1494 help
1044 This option adds the workaround for !! 1495 Netlogic Microsystems XLP processors.
1045 !! 1496 endchoice
1046 If a Cortex-A715 cpu sees a page ma <<
1047 to non-executable, it may corrupt t <<
1048 next instruction abort caused by pe <<
1049 <<
1050 Only user-space does executable to <<
1051 mprotect() system call. Workaround <<
1052 TLB invalidation, for all changes t <<
1053 1497
1054 If unsure, say Y. !! 1498 if CPU_LOONGSON2F
>> 1499 config CPU_NOP_WORKAROUNDS
>> 1500 bool
1055 1501
1056 config ARM64_WORKAROUND_SPECULATIVE_UNPRIV_LO !! 1502 config CPU_JUMP_WORKAROUNDS
1057 bool 1503 bool
1058 1504
1059 config ARM64_ERRATUM_2966298 !! 1505 config CPU_LOONGSON2F_WORKAROUNDS
1060 bool "Cortex-A520: 2966298: workaroun !! 1506 bool "Loongson 2F Workarounds"
1061 select ARM64_WORKAROUND_SPECULATIVE_U <<
1062 default y 1507 default y
>> 1508 select CPU_NOP_WORKAROUNDS
>> 1509 select CPU_JUMP_WORKAROUNDS
1063 help 1510 help
1064 This option adds the workaround for !! 1511 Loongson 2F01 / 2F02 processors have the NOP & JUMP issues which
1065 !! 1512 require workarounds. Without workarounds the system may hang
1066 On an affected Cortex-A520 core, a !! 1513 unexpectedly. For more information please refer to the gas
1067 load might leak data from a privile !! 1514 -mfix-loongson2f-nop and -mfix-loongson2f-jump options.
>> 1515
>> 1516 Loongson 2F03 and later have fixed these issues and no workarounds
>> 1517 are needed. The workarounds have no significant side effect on them
>> 1518 but may decrease the performance of the system so this option should
>> 1519 be disabled unless the kernel is intended to be run on 2F01 or 2F02
>> 1520 systems.
1068 1521
1069 Work around this problem by executi !! 1522 If unsure, please say Y.
>> 1523 endif # CPU_LOONGSON2F
1070 1524
1071 If unsure, say Y. !! 1525 config SYS_SUPPORTS_ZBOOT
>> 1526 bool
>> 1527 select HAVE_KERNEL_GZIP
>> 1528 select HAVE_KERNEL_BZIP2
>> 1529 select HAVE_KERNEL_LZMA
>> 1530 select HAVE_KERNEL_LZO
1072 1531
1073 config ARM64_ERRATUM_3117295 !! 1532 config SYS_SUPPORTS_ZBOOT_UART16550
1074 bool "Cortex-A510: 3117295: workaroun !! 1533 bool
1075 select ARM64_WORKAROUND_SPECULATIVE_U !! 1534 select SYS_SUPPORTS_ZBOOT
1076 default y <<
1077 help <<
1078 This option adds the workaround for <<
1079 1535
1080 On an affected Cortex-A510 core, a !! 1536 config CPU_LOONGSON2
1081 load might leak data from a privile !! 1537 bool
>> 1538 select CPU_SUPPORTS_32BIT_KERNEL
>> 1539 select CPU_SUPPORTS_64BIT_KERNEL
>> 1540 select CPU_SUPPORTS_HIGHMEM
>> 1541 select CPU_SUPPORTS_HUGEPAGES
1082 1542
1083 Work around this problem by executi !! 1543 config CPU_LOONGSON1
>> 1544 bool
>> 1545 select CPU_MIPS32
>> 1546 select CPU_MIPSR2
>> 1547 select CPU_HAS_PREFETCH
>> 1548 select CPU_SUPPORTS_32BIT_KERNEL
>> 1549 select CPU_SUPPORTS_HIGHMEM
1084 1550
1085 If unsure, say Y. !! 1551 config CPU_BMIPS
>> 1552 bool
>> 1553 select CPU_MIPS32
>> 1554 select CPU_SUPPORTS_32BIT_KERNEL
>> 1555 select DMA_NONCOHERENT
>> 1556 select IRQ_CPU
>> 1557 select SWAP_IO_SPACE
>> 1558 select WEAK_ORDERING
1086 1559
1087 config ARM64_ERRATUM_3194386 !! 1560 config SYS_HAS_CPU_LOONGSON2E
1088 bool "Cortex-*/Neoverse-*: workaround !! 1561 bool
1089 default y <<
1090 help <<
1091 This option adds the workaround for <<
1092 1562
1093 * ARM Cortex-A76 erratum 3324349 !! 1563 config SYS_HAS_CPU_LOONGSON2F
1094 * ARM Cortex-A77 erratum 3324348 !! 1564 bool
1095 * ARM Cortex-A78 erratum 3324344 !! 1565 select CPU_SUPPORTS_CPUFREQ
1096 * ARM Cortex-A78C erratum 3324346 !! 1566 select CPU_SUPPORTS_ADDRWINCFG if 64BIT
1097 * ARM Cortex-A78C erratum 3324347 !! 1567 select CPU_SUPPORTS_UNCACHED_ACCELERATED
1098 * ARM Cortex-A710 erratam 3324338 <<
1099 * ARM Cortex-A715 errartum 3456084 <<
1100 * ARM Cortex-A720 erratum 3456091 <<
1101 * ARM Cortex-A725 erratum 3456106 <<
1102 * ARM Cortex-X1 erratum 3324344 <<
1103 * ARM Cortex-X1C erratum 3324346 <<
1104 * ARM Cortex-X2 erratum 3324338 <<
1105 * ARM Cortex-X3 erratum 3324335 <<
1106 * ARM Cortex-X4 erratum 3194386 <<
1107 * ARM Cortex-X925 erratum 3324334 <<
1108 * ARM Neoverse-N1 erratum 3324349 <<
1109 * ARM Neoverse N2 erratum 3324339 <<
1110 * ARM Neoverse-N3 erratum 3456111 <<
1111 * ARM Neoverse-V1 erratum 3324341 <<
1112 * ARM Neoverse V2 erratum 3324336 <<
1113 * ARM Neoverse-V3 erratum 3312417 <<
1114 <<
1115 On affected cores "MSR SSBS, #0" in <<
1116 subsequent speculative instructions <<
1117 speculative store bypassing. <<
1118 <<
1119 Work around this problem by placing <<
1120 Instruction Synchronization Barrier <<
1121 SSBS. The presence of the SSBS spec <<
1122 from hwcaps and EL0 reads of ID_AA6 <<
1123 will use the PR_SPEC_STORE_BYPASS p <<
1124 1568
1125 If unsure, say Y. !! 1569 config SYS_HAS_CPU_LOONGSON1B
>> 1570 bool
1126 1571
1127 config CAVIUM_ERRATUM_22375 !! 1572 config SYS_HAS_CPU_MIPS32_R1
1128 bool "Cavium erratum 22375, 24313" !! 1573 bool
1129 default y <<
1130 help <<
1131 Enable workaround for errata 22375 <<
1132 1574
1133 This implements two gicv3-its errat !! 1575 config SYS_HAS_CPU_MIPS32_R2
1134 with a small impact affecting only !! 1576 bool
1135 1577
1136 erratum 22375: only alloc 8MB tab !! 1578 config SYS_HAS_CPU_MIPS64_R1
1137 erratum 24313: ignore memory acce !! 1579 bool
1138 1580
1139 The fixes are in ITS initialization !! 1581 config SYS_HAS_CPU_MIPS64_R2
1140 type and table size provided by the !! 1582 bool
1141 1583
1142 If unsure, say Y. !! 1584 config SYS_HAS_CPU_R3000
>> 1585 bool
1143 1586
1144 config CAVIUM_ERRATUM_23144 !! 1587 config SYS_HAS_CPU_TX39XX
1145 bool "Cavium erratum 23144: ITS SYNC !! 1588 bool
1146 depends on NUMA <<
1147 default y <<
1148 help <<
1149 ITS SYNC command hang for cross nod <<
1150 1589
1151 If unsure, say Y. !! 1590 config SYS_HAS_CPU_VR41XX
>> 1591 bool
1152 1592
1153 config CAVIUM_ERRATUM_23154 !! 1593 config SYS_HAS_CPU_R4300
1154 bool "Cavium errata 23154 and 38545: !! 1594 bool
1155 default y <<
1156 help <<
1157 The ThunderX GICv3 implementation r <<
1158 reading the IAR status to ensure da <<
1159 (access to icc_iar1_el1 is not sync <<
1160 1595
1161 It also suffers from erratum 38545 !! 1596 config SYS_HAS_CPU_R4X00
1162 OcteonTX and OcteonTX2), resulting !! 1597 bool
1163 spuriously presented to the CPU int <<
1164 1598
1165 If unsure, say Y. !! 1599 config SYS_HAS_CPU_TX49XX
>> 1600 bool
1166 1601
1167 config CAVIUM_ERRATUM_27456 !! 1602 config SYS_HAS_CPU_R5000
1168 bool "Cavium erratum 27456: Broadcast !! 1603 bool
1169 default y <<
1170 help <<
1171 On ThunderX T88 pass 1.x through 2. <<
1172 instructions may cause the icache t <<
1173 contains data for a non-current ASI <<
1174 invalidate the icache when changing <<
1175 1604
1176 If unsure, say Y. !! 1605 config SYS_HAS_CPU_R5432
>> 1606 bool
1177 1607
1178 config CAVIUM_ERRATUM_30115 !! 1608 config SYS_HAS_CPU_R5500
1179 bool "Cavium erratum 30115: Guest may !! 1609 bool
1180 default y <<
1181 help <<
1182 On ThunderX T88 pass 1.x through 2. <<
1183 1.2, and T83 Pass 1.0, KVM guest ex <<
1184 interrupts in host. Trapping both G <<
1185 accesses sidesteps the issue. <<
1186 1610
1187 If unsure, say Y. !! 1611 config SYS_HAS_CPU_R6000
>> 1612 bool
1188 1613
1189 config CAVIUM_TX2_ERRATUM_219 !! 1614 config SYS_HAS_CPU_NEVADA
1190 bool "Cavium ThunderX2 erratum 219: P !! 1615 bool
1191 default y <<
1192 help <<
1193 On Cavium ThunderX2, a load, store <<
1194 TTBR update and the corresponding c <<
1195 cause a spurious Data Abort to be d <<
1196 the CPU core. <<
1197 <<
1198 Work around the issue by avoiding t <<
1199 trapping KVM guest TTBRx_EL1 writes <<
1200 trap handler performs the correspon <<
1201 instruction and ensures context syn <<
1202 exception return. <<
1203 1616
1204 If unsure, say Y. !! 1617 config SYS_HAS_CPU_R8000
>> 1618 bool
1205 1619
1206 config FUJITSU_ERRATUM_010001 !! 1620 config SYS_HAS_CPU_R10000
1207 bool "Fujitsu-A64FX erratum E#010001: !! 1621 bool
1208 default y <<
1209 help <<
1210 This option adds a workaround for F <<
1211 On some variants of the Fujitsu-A64 <<
1212 accesses may cause undefined fault <<
1213 This fault occurs under a specific <<
1214 load/store instruction performs an <<
1215 case-1 TTBR0_EL1 with TCR_EL1.NFD0 <<
1216 case-2 TTBR0_EL2 with TCR_EL2.NFD0 <<
1217 case-3 TTBR1_EL1 with TCR_EL1.NFD1 <<
1218 case-4 TTBR1_EL2 with TCR_EL2.NFD1 <<
1219 1622
1220 The workaround is to ensure these b !! 1623 config SYS_HAS_CPU_RM7000
1221 The workaround only affects the Fuj !! 1624 bool
1222 1625
1223 If unsure, say Y. !! 1626 config SYS_HAS_CPU_SB1
>> 1627 bool
1224 1628
1225 config HISILICON_ERRATUM_161600802 !! 1629 config SYS_HAS_CPU_CAVIUM_OCTEON
1226 bool "Hip07 161600802: Erroneous redi !! 1630 bool
1227 default y <<
1228 help <<
1229 The HiSilicon Hip07 SoC uses the wr <<
1230 when issued ITS commands such as VM <<
1231 a 128kB offset to be applied to the <<
1232 1631
1233 If unsure, say Y. !! 1632 config SYS_HAS_CPU_BMIPS3300
>> 1633 bool
1234 1634
1235 config QCOM_FALKOR_ERRATUM_1003 !! 1635 config SYS_HAS_CPU_BMIPS4350
1236 bool "Falkor E1003: Incorrect transla !! 1636 bool
1237 default y <<
1238 help <<
1239 On Falkor v1, an incorrect ASID may <<
1240 and BADDR are changed together in T <<
1241 in TTBR1_EL1, this situation only o <<
1242 then only for entries in the walk c <<
1243 is unchanged. Work around the errat <<
1244 entries for the trampoline before e <<
1245 1637
1246 config QCOM_FALKOR_ERRATUM_1009 !! 1638 config SYS_HAS_CPU_BMIPS4380
1247 bool "Falkor E1009: Prematurely compl !! 1639 bool
1248 default y <<
1249 select ARM64_WORKAROUND_REPEAT_TLBI <<
1250 help <<
1251 On Falkor v1, the CPU may premature <<
1252 TLBI xxIS invalidate maintenance op <<
1253 one more time to fix the issue. <<
1254 1640
1255 If unsure, say Y. !! 1641 config SYS_HAS_CPU_BMIPS5000
>> 1642 bool
1256 1643
1257 config QCOM_QDF2400_ERRATUM_0065 !! 1644 config SYS_HAS_CPU_XLR
1258 bool "QDF2400 E0065: Incorrect GITS_T !! 1645 bool
1259 default y <<
1260 help <<
1261 On Qualcomm Datacenter Technologies <<
1262 ITE size incorrectly. The GITS_TYPE <<
1263 been indicated as 16Bytes (0xf), no <<
1264 1646
1265 If unsure, say Y. !! 1647 config SYS_HAS_CPU_XLP
>> 1648 bool
1266 1649
1267 config QCOM_FALKOR_ERRATUM_E1041 !! 1650 #
1268 bool "Falkor E1041: Speculative instr !! 1651 # CPU may reorder R->R, R->W, W->R, W->W
1269 default y !! 1652 # Reordering beyond LL and SC is handled in WEAK_REORDERING_BEYOND_LLSC
1270 help !! 1653 #
1271 Falkor CPU may speculatively fetch !! 1654 config WEAK_ORDERING
1272 memory location when MMU translatio !! 1655 bool
1273 to SCTLR_ELn[M]=0. Prefix an ISB in <<
1274 1656
1275 If unsure, say Y. !! 1657 #
>> 1658 # CPU may reorder reads and writes beyond LL/SC
>> 1659 # CPU may reorder R->LL, R->LL, W->LL, W->LL, R->SC, R->SC, W->SC, W->SC
>> 1660 #
>> 1661 config WEAK_REORDERING_BEYOND_LLSC
>> 1662 bool
>> 1663 endmenu
1276 1664
1277 config NVIDIA_CARMEL_CNP_ERRATUM !! 1665 #
1278 bool "NVIDIA Carmel CNP: CNP on Carme !! 1666 # These two indicate any level of the MIPS32 and MIPS64 architecture
1279 default y !! 1667 #
1280 help !! 1668 config CPU_MIPS32
1281 If CNP is enabled on Carmel cores, !! 1669 bool
1282 invalidate shared TLB entries insta !! 1670 default y if CPU_MIPS32_R1 || CPU_MIPS32_R2
1283 on standard ARM cores. <<
1284 1671
1285 If unsure, say Y. !! 1672 config CPU_MIPS64
>> 1673 bool
>> 1674 default y if CPU_MIPS64_R1 || CPU_MIPS64_R2
1286 1675
1287 config ROCKCHIP_ERRATUM_3588001 !! 1676 #
1288 bool "Rockchip 3588001: GIC600 can no !! 1677 # These two indicate the revision of the architecture, either Release 1 or Release 2
1289 default y !! 1678 #
1290 help !! 1679 config CPU_MIPSR1
1291 The Rockchip RK3588 GIC600 SoC inte !! 1680 bool
1292 This means, that its sharability fe !! 1681 default y if CPU_MIPS32_R1 || CPU_MIPS64_R1
1293 is supported by the IP itself. <<
1294 1682
1295 If unsure, say Y. !! 1683 config CPU_MIPSR2
>> 1684 bool
>> 1685 default y if CPU_MIPS32_R2 || CPU_MIPS64_R2 || CPU_CAVIUM_OCTEON
1296 1686
1297 config SOCIONEXT_SYNQUACER_PREITS !! 1687 config SYS_SUPPORTS_32BIT_KERNEL
1298 bool "Socionext Synquacer: Workaround !! 1688 bool
1299 default y !! 1689 config SYS_SUPPORTS_64BIT_KERNEL
1300 help !! 1690 bool
1301 Socionext Synquacer SoCs implement !! 1691 config CPU_SUPPORTS_32BIT_KERNEL
1302 MSI doorbell writes with non-zero v !! 1692 bool
>> 1693 config CPU_SUPPORTS_64BIT_KERNEL
>> 1694 bool
>> 1695 config CPU_SUPPORTS_CPUFREQ
>> 1696 bool
>> 1697 config CPU_SUPPORTS_ADDRWINCFG
>> 1698 bool
>> 1699 config CPU_SUPPORTS_HUGEPAGES
>> 1700 bool
>> 1701 config CPU_SUPPORTS_UNCACHED_ACCELERATED
>> 1702 bool
>> 1703 config MIPS_PGD_C0_CONTEXT
>> 1704 bool
>> 1705 default y if 64BIT && CPU_MIPSR2 && !CPU_XLP
1303 1706
1304 If unsure, say Y. !! 1707 #
>> 1708 # Set to y for ptrace access to watch registers.
>> 1709 #
>> 1710 config HARDWARE_WATCHPOINTS
>> 1711 bool
>> 1712 default y if CPU_MIPSR1 || CPU_MIPSR2
1305 1713
1306 endmenu # "ARM errata workarounds via the alt !! 1714 menu "Kernel type"
1307 1715
1308 choice 1716 choice
1309 prompt "Page size" !! 1717 prompt "Kernel code model"
1310 default ARM64_4K_PAGES <<
1311 help 1718 help
1312 Page size (translation granule) con !! 1719 You should only select this option if you have a workload that
1313 !! 1720 actually benefits from 64-bit processing or if your machine has
1314 config ARM64_4K_PAGES !! 1721 large memory. You will only be presented a single option in this
1315 bool "4KB" !! 1722 menu if your system does not support both 32-bit and 64-bit kernels.
1316 select HAVE_PAGE_SIZE_4KB !! 1723
>> 1724 config 32BIT
>> 1725 bool "32-bit kernel"
>> 1726 depends on CPU_SUPPORTS_32BIT_KERNEL && SYS_SUPPORTS_32BIT_KERNEL
>> 1727 select TRAD_SIGNALS
1317 help 1728 help
1318 This feature enables 4KB pages supp !! 1729 Select this option if you want to build a 32-bit kernel.
1319 !! 1730 config 64BIT
1320 config ARM64_16K_PAGES !! 1731 bool "64-bit kernel"
1321 bool "16KB" !! 1732 depends on CPU_SUPPORTS_64BIT_KERNEL && SYS_SUPPORTS_64BIT_KERNEL
1322 select HAVE_PAGE_SIZE_16KB <<
1323 help <<
1324 The system will use 16KB pages supp <<
1325 requires applications compiled with <<
1326 aligned segments. <<
1327 <<
1328 config ARM64_64K_PAGES <<
1329 bool "64KB" <<
1330 select HAVE_PAGE_SIZE_64KB <<
1331 help 1733 help
1332 This feature enables 64KB pages sup !! 1734 Select this option if you want to build a 64-bit kernel.
1333 allowing only two levels of page ta <<
1334 look-up. AArch32 emulation requires <<
1335 with 64K aligned segments. <<
1336 1735
1337 endchoice 1736 endchoice
1338 1737
1339 choice !! 1738 config KVM_GUEST
1340 prompt "Virtual address space size" !! 1739 bool "KVM Guest Kernel"
1341 default ARM64_VA_BITS_52 <<
1342 help 1740 help
1343 Allows choosing one of multiple pos !! 1741 Select this option if building a guest kernel for KVM (Trap & Emulate) mode
1344 space sizes. The level of translati <<
1345 a combination of page size and virt <<
1346 <<
1347 config ARM64_VA_BITS_36 <<
1348 bool "36-bit" if EXPERT <<
1349 depends on PAGE_SIZE_16KB <<
1350 <<
1351 config ARM64_VA_BITS_39 <<
1352 bool "39-bit" <<
1353 depends on PAGE_SIZE_4KB <<
1354 <<
1355 config ARM64_VA_BITS_42 <<
1356 bool "42-bit" <<
1357 depends on PAGE_SIZE_64KB <<
1358 <<
1359 config ARM64_VA_BITS_47 <<
1360 bool "47-bit" <<
1361 depends on PAGE_SIZE_16KB <<
1362 <<
1363 config ARM64_VA_BITS_48 <<
1364 bool "48-bit" <<
1365 <<
1366 config ARM64_VA_BITS_52 <<
1367 bool "52-bit" <<
1368 depends on ARM64_PAN || !ARM64_SW_TTB <<
1369 help <<
1370 Enable 52-bit virtual addressing fo <<
1371 requested via a hint to mmap(). The <<
1372 virtual addresses for its own mappi <<
1373 this feature is available, otherwis <<
1374 <<
1375 NOTE: Enabling 52-bit virtual addre <<
1376 ARMv8.3 Pointer Authentication will <<
1377 reduced from 7 bits to 3 bits, whic <<
1378 impact on its susceptibility to bru <<
1379 <<
1380 If unsure, select 48-bit virtual ad <<
1381 <<
1382 endchoice <<
1383 1742
1384 config ARM64_FORCE_52BIT !! 1743 config KVM_HOST_FREQ
1385 bool "Force 52-bit virtual addresses !! 1744 int "KVM Host Processor Frequency (MHz)"
1386 depends on ARM64_VA_BITS_52 && EXPERT !! 1745 depends on KVM_GUEST
1387 help !! 1746 default 500
1388 For systems with 52-bit userspace V !! 1747 help
1389 to maintain compatibility with olde !! 1748 Select this option if building a guest kernel for KVM to skip
1390 unless a hint is supplied to mmap. !! 1749 RTC emulation when determining guest CPU Frequency. Instead, the guest
1391 !! 1750 processor frequency is automatically derived from the host frequency.
1392 This configuration option disables <<
1393 forces all userspace addresses to b <<
1394 should only enable this configurati <<
1395 memory management code. If unsure s <<
1396 <<
1397 config ARM64_VA_BITS <<
1398 int <<
1399 default 36 if ARM64_VA_BITS_36 <<
1400 default 39 if ARM64_VA_BITS_39 <<
1401 default 42 if ARM64_VA_BITS_42 <<
1402 default 47 if ARM64_VA_BITS_47 <<
1403 default 48 if ARM64_VA_BITS_48 <<
1404 default 52 if ARM64_VA_BITS_52 <<
1405 1751
1406 choice 1752 choice
1407 prompt "Physical address space size" !! 1753 prompt "Kernel page size"
1408 default ARM64_PA_BITS_48 !! 1754 default PAGE_SIZE_4KB
1409 help <<
1410 Choose the maximum physical address <<
1411 support. <<
1412 1755
1413 config ARM64_PA_BITS_48 !! 1756 config PAGE_SIZE_4KB
1414 bool "48-bit" !! 1757 bool "4kB"
1415 depends on ARM64_64K_PAGES || !ARM64_ !! 1758 depends on !CPU_LOONGSON2
1416 !! 1759 help
1417 config ARM64_PA_BITS_52 !! 1760 This option select the standard 4kB Linux page size. On some
1418 bool "52-bit" !! 1761 R3000-family processors this is the only available page size. Using
1419 depends on ARM64_64K_PAGES || ARM64_V !! 1762 4kB page size will minimize memory consumption and is therefore
1420 depends on ARM64_PAN || !ARM64_SW_TTB !! 1763 recommended for low memory systems.
1421 help !! 1764
1422 Enable support for a 52-bit physica !! 1765 config PAGE_SIZE_8KB
1423 part of the ARMv8.2-LPA extension. !! 1766 bool "8kB"
1424 !! 1767 depends on CPU_R8000 || CPU_CAVIUM_OCTEON
1425 With this enabled, the kernel will !! 1768 help
1426 do not support ARMv8.2-LPA, but wit !! 1769 Using 8kB page size will result in higher performance kernel at
1427 minor performance overhead). !! 1770 the price of higher memory consumption. This option is available
>> 1771 only on R8000 and cnMIPS processors. Note that you will need a
>> 1772 suitable Linux distribution to support this.
>> 1773
>> 1774 config PAGE_SIZE_16KB
>> 1775 bool "16kB"
>> 1776 depends on !CPU_R3000 && !CPU_TX39XX
>> 1777 help
>> 1778 Using 16kB page size will result in higher performance kernel at
>> 1779 the price of higher memory consumption. This option is available on
>> 1780 all non-R3000 family processors. Note that you will need a suitable
>> 1781 Linux distribution to support this.
>> 1782
>> 1783 config PAGE_SIZE_32KB
>> 1784 bool "32kB"
>> 1785 depends on CPU_CAVIUM_OCTEON
>> 1786 help
>> 1787 Using 32kB page size will result in higher performance kernel at
>> 1788 the price of higher memory consumption. This option is available
>> 1789 only on cnMIPS cores. Note that you will need a suitable Linux
>> 1790 distribution to support this.
>> 1791
>> 1792 config PAGE_SIZE_64KB
>> 1793 bool "64kB"
>> 1794 depends on !CPU_R3000 && !CPU_TX39XX
>> 1795 help
>> 1796 Using 64kB page size will result in higher performance kernel at
>> 1797 the price of higher memory consumption. This option is available on
>> 1798 all non-R3000 family processor. Not that at the time of this
>> 1799 writing this option is still high experimental.
1428 1800
1429 endchoice 1801 endchoice
1430 1802
1431 config ARM64_PA_BITS !! 1803 config FORCE_MAX_ZONEORDER
1432 int !! 1804 int "Maximum zone order"
1433 default 48 if ARM64_PA_BITS_48 !! 1805 range 14 64 if HUGETLB_PAGE && PAGE_SIZE_64KB
1434 default 52 if ARM64_PA_BITS_52 !! 1806 default "14" if HUGETLB_PAGE && PAGE_SIZE_64KB
>> 1807 range 13 64 if HUGETLB_PAGE && PAGE_SIZE_32KB
>> 1808 default "13" if HUGETLB_PAGE && PAGE_SIZE_32KB
>> 1809 range 12 64 if HUGETLB_PAGE && PAGE_SIZE_16KB
>> 1810 default "12" if HUGETLB_PAGE && PAGE_SIZE_16KB
>> 1811 range 11 64
>> 1812 default "11"
>> 1813 help
>> 1814 The kernel memory allocator divides physically contiguous memory
>> 1815 blocks into "zones", where each zone is a power of two number of
>> 1816 pages. This option selects the largest power of two that the kernel
>> 1817 keeps in the memory allocator. If you need to allocate very large
>> 1818 blocks of physically contiguous memory, then you may need to
>> 1819 increase this value.
>> 1820
>> 1821 This config option is actually maximum order plus one. For example,
>> 1822 a value of 11 means that the largest free memory block is 2^10 pages.
>> 1823
>> 1824 The page size is not necessarily 4KB. Keep this in mind
>> 1825 when choosing a value for this option.
>> 1826
>> 1827 config CEVT_GIC
>> 1828 bool "Use GIC global counter for clock events"
>> 1829 depends on IRQ_GIC && !(MIPS_SEAD3 || MIPS_MT_SMTC)
>> 1830 help
>> 1831 Use the GIC global counter for the clock events. The R4K clock
>> 1832 event driver is always present, so if the platform ends up not
>> 1833 detecting a GIC, it will fall back to the R4K timer for the
>> 1834 generation of clock events.
1435 1835
1436 config ARM64_LPA2 !! 1836 config BOARD_SCACHE
1437 def_bool y !! 1837 bool
1438 depends on ARM64_PA_BITS_52 && !ARM64 <<
1439 1838
1440 choice !! 1839 config IP22_CPU_SCACHE
1441 prompt "Endianness" !! 1840 bool
1442 default CPU_LITTLE_ENDIAN !! 1841 select BOARD_SCACHE
1443 help <<
1444 Select the endianness of data acces <<
1445 applications will need to be compil <<
1446 that is selected here. <<
1447 1842
1448 config CPU_BIG_ENDIAN !! 1843 #
1449 bool "Build big-endian kernel" !! 1844 # Support for a MIPS32 / MIPS64 style S-caches
1450 # https://github.com/llvm/llvm-projec !! 1845 #
1451 depends on AS_IS_GNU || AS_VERSION >= !! 1846 config MIPS_CPU_SCACHE
1452 help !! 1847 bool
1453 Say Y if you plan on running a kern !! 1848 select BOARD_SCACHE
1454 1849
1455 config CPU_LITTLE_ENDIAN !! 1850 config R5000_CPU_SCACHE
1456 bool "Build little-endian kernel" !! 1851 bool
1457 help !! 1852 select BOARD_SCACHE
1458 Say Y if you plan on running a kern <<
1459 This is usually the case for distri <<
1460 1853
1461 endchoice !! 1854 config RM7000_CPU_SCACHE
>> 1855 bool
>> 1856 select BOARD_SCACHE
1462 1857
1463 config SCHED_MC !! 1858 config SIBYTE_DMA_PAGEOPS
1464 bool "Multi-core scheduler support" !! 1859 bool "Use DMA to clear/copy pages"
>> 1860 depends on CPU_SB1
1465 help 1861 help
1466 Multi-core scheduler support improv !! 1862 Instead of using the CPU to zero and copy pages, use a Data Mover
1467 making when dealing with multi-core !! 1863 channel. These DMA channels are otherwise unused by the standard
1468 increased overhead in some places. !! 1864 SiByte Linux port. Seems to give a small performance benefit.
1469 1865
1470 config SCHED_CLUSTER !! 1866 config CPU_HAS_PREFETCH
1471 bool "Cluster scheduler support" !! 1867 bool
1472 help <<
1473 Cluster scheduler support improves <<
1474 making when dealing with machines t <<
1475 Cluster usually means a couple of C <<
1476 by sharing mid-level caches, last-l <<
1477 busses. <<
1478 1868
1479 config SCHED_SMT !! 1869 config CPU_GENERIC_DUMP_TLB
1480 bool "SMT scheduler support" !! 1870 bool
1481 help !! 1871 default y if !(CPU_R3000 || CPU_R6000 || CPU_R8000 || CPU_TX39XX)
1482 Improves the CPU scheduler's decisi <<
1483 MultiThreading at a cost of slightl <<
1484 places. If unsure say N here. <<
1485 1872
1486 config NR_CPUS !! 1873 config CPU_R4K_FPU
1487 int "Maximum number of CPUs (2-4096)" !! 1874 bool
1488 range 2 4096 !! 1875 default y if !(CPU_R3000 || CPU_R6000 || CPU_TX39XX || CPU_CAVIUM_OCTEON)
1489 default "512" <<
1490 1876
1491 config HOTPLUG_CPU !! 1877 config CPU_R4K_CACHE_TLB
1492 bool "Support for hot-pluggable CPUs" !! 1878 bool
1493 select GENERIC_IRQ_MIGRATION !! 1879 default y if !(CPU_R3000 || CPU_R8000 || CPU_SB1 || CPU_TX39XX || CPU_CAVIUM_OCTEON)
1494 help <<
1495 Say Y here to experiment with turni <<
1496 can be controlled through /sys/devi <<
1497 1880
1498 # Common NUMA Features !! 1881 choice
1499 config NUMA !! 1882 prompt "MIPS MT options"
1500 bool "NUMA Memory Allocation and Sche <<
1501 select GENERIC_ARCH_NUMA <<
1502 select OF_NUMA <<
1503 select HAVE_SETUP_PER_CPU_AREA <<
1504 select NEED_PER_CPU_EMBED_FIRST_CHUNK <<
1505 select NEED_PER_CPU_PAGE_FIRST_CHUNK <<
1506 select USE_PERCPU_NUMA_NODE_ID <<
1507 help <<
1508 Enable NUMA (Non-Uniform Memory Acc <<
1509 <<
1510 The kernel will try to allocate mem <<
1511 local memory of the CPU and add som <<
1512 NUMA awareness to the kernel. <<
1513 1883
1514 config NODES_SHIFT !! 1884 config MIPS_MT_DISABLED
1515 int "Maximum NUMA Nodes (as a power o !! 1885 bool "Disable multithreading support."
1516 range 1 10 <<
1517 default "4" <<
1518 depends on NUMA <<
1519 help 1886 help
1520 Specify the maximum number of NUMA !! 1887 Use this option if your workload can't take advantage of
1521 system. Increases memory reserved !! 1888 MIPS hardware multithreading support. On systems that don't have
1522 !! 1889 the option of an MT-enabled processor this option will be the only
1523 source "kernel/Kconfig.hz" !! 1890 option in this menu.
1524 !! 1891
1525 config ARCH_SPARSEMEM_ENABLE !! 1892 config MIPS_MT_SMP
1526 def_bool y !! 1893 bool "Use 1 TC on each available VPE for SMP"
1527 select SPARSEMEM_VMEMMAP_ENABLE !! 1894 depends on SYS_SUPPORTS_MULTITHREADING
1528 select SPARSEMEM_VMEMMAP !! 1895 select CPU_MIPSR2_IRQ_VI
>> 1896 select CPU_MIPSR2_IRQ_EI
>> 1897 select MIPS_MT
>> 1898 select NR_CPUS_DEFAULT_2
>> 1899 select SMP
>> 1900 select SYS_SUPPORTS_SCHED_SMT if SMP
>> 1901 select SYS_SUPPORTS_SMP
>> 1902 select SMP_UP
>> 1903 select MIPS_PERF_SHARED_TC_COUNTERS
>> 1904 help
>> 1905 This is a kernel model which is known a VSMP but lately has been
>> 1906 marketesed into SMVP.
>> 1907 Virtual SMP uses the processor's VPEs to implement virtual
>> 1908 processors. In currently available configuration of the 34K processor
>> 1909 this allows for a dual processor. Both processors will share the same
>> 1910 primary caches; each will obtain the half of the TLB for it's own
>> 1911 exclusive use. For a layman this model can be described as similar to
>> 1912 what Intel calls Hyperthreading.
>> 1913
>> 1914 For further information see http://www.linux-mips.org/wiki/34K#VSMP
>> 1915
>> 1916 config MIPS_MT_SMTC
>> 1917 bool "SMTC: Use all TCs on all VPEs for SMP"
>> 1918 depends on CPU_MIPS32_R2
>> 1919 #depends on CPU_MIPS64_R2 # once there is hardware ...
>> 1920 depends on SYS_SUPPORTS_MULTITHREADING
>> 1921 select CPU_MIPSR2_IRQ_VI
>> 1922 select CPU_MIPSR2_IRQ_EI
>> 1923 select MIPS_MT
>> 1924 select NR_CPUS_DEFAULT_8
>> 1925 select SMP
>> 1926 select SYS_SUPPORTS_SMP
>> 1927 select SMP_UP
>> 1928 help
>> 1929 This is a kernel model which is known a SMTC or lately has been
>> 1930 marketesed into SMVP.
>> 1931 is presenting the available TC's of the core as processors to Linux.
>> 1932 On currently available 34K processors this means a Linux system will
>> 1933 see up to 5 processors. The implementation of the SMTC kernel differs
>> 1934 significantly from VSMP and cannot efficiently coexist in the same
>> 1935 kernel binary so the choice between VSMP and SMTC is a compile time
>> 1936 decision.
1529 1937
1530 config HW_PERF_EVENTS !! 1938 For further information see http://www.linux-mips.org/wiki/34K#SMTC
1531 def_bool y <<
1532 depends on ARM_PMU <<
1533 1939
1534 # Supported by clang >= 7.0 or GCC >= 12.0.0 !! 1940 endchoice
1535 config CC_HAVE_SHADOW_CALL_STACK <<
1536 def_bool $(cc-option, -fsanitize=shad <<
1537 1941
1538 config PARAVIRT !! 1942 config MIPS_MT
1539 bool "Enable paravirtualization code" !! 1943 bool
1540 help <<
1541 This changes the kernel so it can m <<
1542 under a hypervisor, potentially imp <<
1543 over full virtualization. <<
1544 1944
1545 config PARAVIRT_TIME_ACCOUNTING !! 1945 config SCHED_SMT
1546 bool "Paravirtual steal time accounti !! 1946 bool "SMT (multithreading) scheduler support"
1547 select PARAVIRT !! 1947 depends on SYS_SUPPORTS_SCHED_SMT
>> 1948 default n
1548 help 1949 help
1549 Select this option to enable fine g !! 1950 SMT scheduler support improves the CPU scheduler's decision making
1550 accounting. Time spent executing ot !! 1951 when dealing with MIPS MT enabled cores at a cost of slightly
1551 the current vCPU is discounted from !! 1952 increased overhead in some places. If unsure say N here.
1552 that, there can be a small performa <<
1553 <<
1554 If in doubt, say N here. <<
1555 <<
1556 config ARCH_SUPPORTS_KEXEC <<
1557 def_bool PM_SLEEP_SMP <<
1558 <<
1559 config ARCH_SUPPORTS_KEXEC_FILE <<
1560 def_bool y <<
1561 <<
1562 config ARCH_SELECTS_KEXEC_FILE <<
1563 def_bool y <<
1564 depends on KEXEC_FILE <<
1565 select HAVE_IMA_KEXEC if IMA <<
1566 <<
1567 config ARCH_SUPPORTS_KEXEC_SIG <<
1568 def_bool y <<
1569 <<
1570 config ARCH_SUPPORTS_KEXEC_IMAGE_VERIFY_SIG <<
1571 def_bool y <<
1572 <<
1573 config ARCH_DEFAULT_KEXEC_IMAGE_VERIFY_SIG <<
1574 def_bool y <<
1575 <<
1576 config ARCH_SUPPORTS_CRASH_DUMP <<
1577 def_bool y <<
1578 1953
1579 config ARCH_HAS_GENERIC_CRASHKERNEL_RESERVATI !! 1954 config SYS_SUPPORTS_SCHED_SMT
1580 def_bool CRASH_RESERVE !! 1955 bool
1581 1956
1582 config TRANS_TABLE !! 1957 config SYS_SUPPORTS_MULTITHREADING
1583 def_bool y !! 1958 bool
1584 depends on HIBERNATION || KEXEC_CORE <<
1585 1959
1586 config XEN_DOM0 !! 1960 config MIPS_MT_FPAFF
1587 def_bool y !! 1961 bool "Dynamic FPU affinity for FP-intensive threads"
1588 depends on XEN !! 1962 default y
>> 1963 depends on MIPS_MT_SMP || MIPS_MT_SMTC
1589 1964
1590 config XEN !! 1965 config MIPS_VPE_LOADER
1591 bool "Xen guest support on ARM64" !! 1966 bool "VPE loader support."
1592 depends on ARM64 && OF !! 1967 depends on SYS_SUPPORTS_MULTITHREADING
1593 select SWIOTLB_XEN !! 1968 select CPU_MIPSR2_IRQ_VI
1594 select PARAVIRT !! 1969 select CPU_MIPSR2_IRQ_EI
>> 1970 select MIPS_MT
>> 1971 help
>> 1972 Includes a loader for loading an elf relocatable object
>> 1973 onto another VPE and running it.
>> 1974
>> 1975 config MIPS_MT_SMTC_IM_BACKSTOP
>> 1976 bool "Use per-TC register bits as backstop for inhibited IM bits"
>> 1977 depends on MIPS_MT_SMTC
>> 1978 default n
1595 help 1979 help
1596 Say Y if you want to run Linux in a !! 1980 To support multiple TC microthreads acting as "CPUs" within
1597 !! 1981 a VPE, VPE-wide interrupt mask bits must be specially manipulated
1598 # include/linux/mmzone.h requires the followi !! 1982 during interrupt handling. To support legacy drivers and interrupt
1599 # !! 1983 controller management code, SMTC has a "backstop" to track and
1600 # MAX_PAGE_ORDER + PAGE_SHIFT <= SECTION_SI !! 1984 if necessary restore the interrupt mask. This has some performance
1601 # !! 1985 impact on interrupt service overhead.
1602 # so the maximum value of MAX_PAGE_ORDER is S !! 1986
1603 # !! 1987 config MIPS_MT_SMTC_IRQAFF
1604 # | SECTION_SIZE_BITS | PAGE_SHIFT | m !! 1988 bool "Support IRQ affinity API"
1605 # ----+-------------------+--------------+--- !! 1989 depends on MIPS_MT_SMTC
1606 # 4K | 27 | 12 | !! 1990 default n
1607 # 16K | 27 | 14 | <<
1608 # 64K | 29 | 16 | <<
1609 config ARCH_FORCE_MAX_ORDER <<
1610 int <<
1611 default "13" if ARM64_64K_PAGES <<
1612 default "11" if ARM64_16K_PAGES <<
1613 default "10" <<
1614 help 1991 help
1615 The kernel page allocator limits th !! 1992 Enables SMP IRQ affinity API (/proc/irq/*/smp_affinity, etc.)
1616 contiguous allocations. The limit i !! 1993 for SMTC Linux kernel. Requires platform support, of which
1617 defines the maximal power of two of !! 1994 an example can be found in the MIPS kernel i8259 and Malta
1618 allocated as a single contiguous bl !! 1995 platform code. Adds some overhead to interrupt dispatch, and
1619 overriding the default setting when !! 1996 should be used only if you know what you are doing.
1620 large blocks of physically contiguo !! 1997
1621 !! 1998 config MIPS_VPE_LOADER_TOM
1622 The maximal size of allocation cann !! 1999 bool "Load VPE program into memory hidden from linux"
1623 section, so the value of MAX_PAGE_O !! 2000 depends on MIPS_VPE_LOADER
1624 !! 2001 default y
1625 MAX_PAGE_ORDER + PAGE_SHIFT <= SE !! 2002 help
1626 !! 2003 The loader can use memory that is present but has been hidden from
1627 Don't change if unsure. !! 2004 Linux using the kernel command line option "mem=xxMB". It's up to
1628 !! 2005 you to ensure the amount you put in the option and the space your
1629 config UNMAP_KERNEL_AT_EL0 !! 2006 program requires is less or equal to the amount physically present.
1630 bool "Unmap kernel when running in us !! 2007
1631 default y !! 2008 # this should possibly be in drivers/char, but it is rather cpu related. Hmmm
>> 2009 config MIPS_VPE_APSP_API
>> 2010 bool "Enable support for AP/SP API (RTLX)"
>> 2011 depends on MIPS_VPE_LOADER
>> 2012 help
>> 2013
>> 2014 config MIPS_CMP
>> 2015 bool "MIPS CMP framework support"
>> 2016 depends on SYS_SUPPORTS_MIPS_CMP
>> 2017 select SYNC_R4K
>> 2018 select SYS_SUPPORTS_SMP
>> 2019 select SYS_SUPPORTS_SCHED_SMT if SMP
>> 2020 select WEAK_ORDERING
>> 2021 default n
1632 help 2022 help
1633 Speculation attacks against some hi !! 2023 This is a placeholder option for the GCMP work. It will need to
1634 be used to bypass MMU permission ch !! 2024 be handled differently...
1635 userspace. This can be defended aga <<
1636 when running in userspace, mapping <<
1637 via a trampoline page in the vector <<
1638 2025
1639 If unsure, say Y. !! 2026 config SB1_PASS_1_WORKAROUNDS
1640 !! 2027 bool
1641 config MITIGATE_SPECTRE_BRANCH_HISTORY !! 2028 depends on CPU_SB1_PASS_1
1642 bool "Mitigate Spectre style attacks <<
1643 default y 2029 default y
1644 help <<
1645 Speculation attacks against some hi <<
1646 make use of branch history to influ <<
1647 When taking an exception from user- <<
1648 or a firmware call overwrites the b <<
1649 2030
1650 config RODATA_FULL_DEFAULT_ENABLED !! 2031 config SB1_PASS_2_WORKAROUNDS
1651 bool "Apply r/o permissions of VM are !! 2032 bool
>> 2033 depends on CPU_SB1 && (CPU_SB1_PASS_2_2 || CPU_SB1_PASS_2)
1652 default y 2034 default y
1653 help <<
1654 Apply read-only attributes of VM ar <<
1655 the backing pages as well. This pre <<
1656 from being modified (inadvertently <<
1657 mapping of the same memory page. Th <<
1658 be turned off at runtime by passing <<
1659 with rodata=full if this option is <<
1660 <<
1661 This requires the linear region to <<
1662 which may adversely affect performa <<
1663 2035
1664 config ARM64_SW_TTBR0_PAN !! 2036 config SB1_PASS_2_1_WORKAROUNDS
1665 bool "Emulate Privileged Access Never !! 2037 bool
1666 depends on !KCSAN !! 2038 depends on CPU_SB1 && CPU_SB1_PASS_2
1667 help <<
1668 Enabling this option prevents the k <<
1669 user-space memory directly by point <<
1670 zeroed area and reserved ASID. The <<
1671 restore the valid TTBR0_EL1 tempora <<
1672 <<
1673 config ARM64_TAGGED_ADDR_ABI <<
1674 bool "Enable the tagged user addresse <<
1675 default y 2039 default y
1676 help <<
1677 When this option is enabled, user a <<
1678 relaxed ABI via prctl() allowing ta <<
1679 to system calls as pointer argument <<
1680 Documentation/arch/arm64/tagged-add <<
1681 <<
1682 menuconfig COMPAT <<
1683 bool "Kernel support for 32-bit EL0" <<
1684 depends on ARM64_4K_PAGES || EXPERT <<
1685 select HAVE_UID16 <<
1686 select OLD_SIGSUSPEND3 <<
1687 select COMPAT_OLD_SIGACTION <<
1688 help <<
1689 This option enables support for a 3 <<
1690 kernel at EL1. AArch32-specific com <<
1691 the user helper functions, VFP supp <<
1692 handled appropriately by the kernel <<
1693 2040
1694 If you use a page size other than 4 <<
1695 that you will only be able to execu <<
1696 with page size aligned segments. <<
1697 2041
1698 If you want to execute 32-bit users !! 2042 config 64BIT_PHYS_ADDR
>> 2043 bool
1699 2044
1700 if COMPAT !! 2045 config ARCH_PHYS_ADDR_T_64BIT
>> 2046 def_bool 64BIT_PHYS_ADDR
1701 2047
1702 config KUSER_HELPERS !! 2048 config CPU_HAS_SMARTMIPS
1703 bool "Enable kuser helpers page for 3 !! 2049 depends on SYS_SUPPORTS_SMARTMIPS
1704 default y !! 2050 bool "Support for the SmartMIPS ASE"
>> 2051 help
>> 2052 SmartMIPS is a extension of the MIPS32 architecture aimed at
>> 2053 increased security at both hardware and software level for
>> 2054 smartcards. Enabling this option will allow proper use of the
>> 2055 SmartMIPS instructions by Linux applications. However a kernel with
>> 2056 this option will not work on a MIPS core without SmartMIPS core. If
>> 2057 you don't know you probably don't have SmartMIPS and should say N
>> 2058 here.
>> 2059
>> 2060 config CPU_MICROMIPS
>> 2061 depends on SYS_SUPPORTS_MICROMIPS
>> 2062 bool "Build kernel using microMIPS ISA"
1705 help 2063 help
1706 Warning: disabling this option may !! 2064 When this option is enabled the kernel will be built using the
>> 2065 microMIPS ISA
1707 2066
1708 Provide kuser helpers to compat tas !! 2067 config CPU_HAS_WB
1709 helper code to userspace in read on !! 2068 bool
1710 to allow userspace to be independen <<
1711 the system. This permits binaries t <<
1712 to ARMv8 without modification. <<
1713 <<
1714 See Documentation/arch/arm/kernel_u <<
1715 <<
1716 However, the fixed address nature o <<
1717 by ROP (return orientated programmi <<
1718 exploits. <<
1719 <<
1720 If all of the binaries and librarie <<
1721 are built specifically for your pla <<
1722 these helpers, then you can turn th <<
1723 such exploits. However, in that cas <<
1724 relying on those helpers is run, it <<
1725 2069
1726 Say N here only if you are absolute !! 2070 config XKS01
1727 need these helpers; otherwise, the !! 2071 bool
1728 2072
1729 config COMPAT_VDSO !! 2073 #
1730 bool "Enable vDSO for 32-bit applicat !! 2074 # Vectored interrupt mode is an R2 feature
1731 depends on !CPU_BIG_ENDIAN !! 2075 #
1732 depends on (CC_IS_CLANG && LD_IS_LLD) !! 2076 config CPU_MIPSR2_IRQ_VI
1733 select GENERIC_COMPAT_VDSO !! 2077 bool
1734 default y <<
1735 help <<
1736 Place in the process address space <<
1737 ELF shared object providing fast im <<
1738 and clock_gettime. <<
1739 2078
1740 You must have a 32-bit build of gli !! 2079 #
1741 to seamlessly take advantage of thi !! 2080 # Extended interrupt mode is an R2 feature
>> 2081 #
>> 2082 config CPU_MIPSR2_IRQ_EI
>> 2083 bool
1742 2084
1743 config THUMB2_COMPAT_VDSO !! 2085 config CPU_HAS_SYNC
1744 bool "Compile the 32-bit vDSO for Thu !! 2086 bool
1745 depends on COMPAT_VDSO !! 2087 depends on !CPU_R3000
1746 default y 2088 default y
1747 help <<
1748 Compile the compat vDSO with '-mthu <<
1749 otherwise with '-marm'. <<
1750 2089
1751 config COMPAT_ALIGNMENT_FIXUPS !! 2090 #
1752 bool "Fix up misaligned multi-word lo !! 2091 # CPU non-features
>> 2092 #
>> 2093 config CPU_DADDI_WORKAROUNDS
>> 2094 bool
1753 2095
1754 menuconfig ARMV8_DEPRECATED !! 2096 config CPU_R4000_WORKAROUNDS
1755 bool "Emulate deprecated/obsolete ARM !! 2097 bool
1756 depends on SYSCTL !! 2098 select CPU_R4400_WORKAROUNDS
1757 help <<
1758 Legacy software support may require <<
1759 that have been deprecated or obsole <<
1760 2099
1761 Enable this config to enable select !! 2100 config CPU_R4400_WORKAROUNDS
1762 features. !! 2101 bool
1763 2102
1764 If unsure, say Y !! 2103 #
>> 2104 # - Highmem only makes sense for the 32-bit kernel.
>> 2105 # - The current highmem code will only work properly on physically indexed
>> 2106 # caches such as R3000, SB1, R7000 or those that look like they're virtually
>> 2107 # indexed such as R4000/R4400 SC and MC versions or R10000. So for the
>> 2108 # moment we protect the user and offer the highmem option only on machines
>> 2109 # where it's known to be safe. This will not offer highmem on a few systems
>> 2110 # such as MIPS32 and MIPS64 CPUs which may have virtual and physically
>> 2111 # indexed CPUs but we're playing safe.
>> 2112 # - We use SYS_SUPPORTS_HIGHMEM to offer highmem only for systems where we
>> 2113 # know they might have memory configurations that could make use of highmem
>> 2114 # support.
>> 2115 #
>> 2116 config HIGHMEM
>> 2117 bool "High Memory Support"
>> 2118 depends on 32BIT && CPU_SUPPORTS_HIGHMEM && SYS_SUPPORTS_HIGHMEM
1765 2119
1766 if ARMV8_DEPRECATED !! 2120 config CPU_SUPPORTS_HIGHMEM
>> 2121 bool
1767 2122
1768 config SWP_EMULATION !! 2123 config SYS_SUPPORTS_HIGHMEM
1769 bool "Emulate SWP/SWPB instructions" !! 2124 bool
1770 help <<
1771 ARMv8 obsoletes the use of A32 SWP/ <<
1772 they are always undefined. Say Y he <<
1773 emulation of these instructions for <<
1774 This feature can be controlled at r <<
1775 sysctl which is disabled by default <<
1776 2125
1777 In some older versions of glibc [<= !! 2126 config SYS_SUPPORTS_SMARTMIPS
1778 trylock() operations with the assum !! 2127 bool
1779 be preempted. This invalid assumpti <<
1780 with SWP emulation enabled, leading <<
1781 application. <<
1782 2128
1783 NOTE: when accessing uncached share !! 2129 config SYS_SUPPORTS_MICROMIPS
1784 on an external transaction monitori !! 2130 bool
1785 monitor to maintain update atomicit <<
1786 implement a global monitor, this op <<
1787 perform SWP operations to uncached <<
1788 2131
1789 If unsure, say Y !! 2132 config ARCH_FLATMEM_ENABLE
>> 2133 def_bool y
>> 2134 depends on !NUMA && !CPU_LOONGSON2
1790 2135
1791 config CP15_BARRIER_EMULATION !! 2136 config ARCH_DISCONTIGMEM_ENABLE
1792 bool "Emulate CP15 Barrier instructio !! 2137 bool
>> 2138 default y if SGI_IP27
1793 help 2139 help
1794 The CP15 barrier instructions - CP1 !! 2140 Say Y to support efficient handling of discontiguous physical memory,
1795 CP15DMB - are deprecated in ARMv8 ( !! 2141 for architectures which are either NUMA (Non-Uniform Memory Access)
1796 strongly recommended to use the ISB !! 2142 or have huge holes in the physical address space for other reasons.
1797 instructions instead. !! 2143 See <file:Documentation/vm/numa> for more.
1798 <<
1799 Say Y here to enable software emula <<
1800 instructions for AArch32 userspace <<
1801 enabled, CP15 barrier usage is trac <<
1802 identify software that needs updati <<
1803 controlled at runtime with the abi. <<
1804 2144
1805 If unsure, say Y !! 2145 config ARCH_SPARSEMEM_ENABLE
>> 2146 bool
>> 2147 select SPARSEMEM_STATIC
1806 2148
1807 config SETEND_EMULATION !! 2149 config NUMA
1808 bool "Emulate SETEND instruction" !! 2150 bool "NUMA Support"
>> 2151 depends on SYS_SUPPORTS_NUMA
1809 help 2152 help
1810 The SETEND instruction alters the d !! 2153 Say Y to compile the kernel to support NUMA (Non-Uniform Memory
1811 AArch32 EL0, and is deprecated in A !! 2154 Access). This option improves performance on systems with more
1812 !! 2155 than two nodes; on two node systems it is generally better to
1813 Say Y here to enable software emula !! 2156 leave it disabled; on single node systems disable this option
1814 for AArch32 userspace code. This fe !! 2157 disabled.
1815 at runtime with the abi.setend sysc <<
1816 <<
1817 Note: All the cpus on the system mu <<
1818 for this feature to be enabled. If <<
1819 endian - is hotplugged in after thi <<
1820 be unexpected results in the applic <<
1821 <<
1822 If unsure, say Y <<
1823 endif # ARMV8_DEPRECATED <<
1824 2158
1825 endif # COMPAT !! 2159 config SYS_SUPPORTS_NUMA
>> 2160 bool
1826 2161
1827 menu "ARMv8.1 architectural features" !! 2162 config NODES_SHIFT
>> 2163 int
>> 2164 default "6"
>> 2165 depends on NEED_MULTIPLE_NODES
1828 2166
1829 config ARM64_HW_AFDBM !! 2167 config HW_PERF_EVENTS
1830 bool "Support for hardware updates of !! 2168 bool "Enable hardware performance counter support for perf events"
>> 2169 depends on PERF_EVENTS && !MIPS_MT_SMTC && OPROFILE=n && (CPU_MIPS32 || CPU_MIPS64 || CPU_R10000 || CPU_SB1 || CPU_CAVIUM_OCTEON || CPU_XLP)
1831 default y 2170 default y
1832 help 2171 help
1833 The ARMv8.1 architecture extensions !! 2172 Enable hardware performance counter support for perf events. If
1834 hardware updates of the access and !! 2173 disabled, perf events will use software events only.
1835 table entries. When enabled in TCR_ <<
1836 capable processors, accesses to pag <<
1837 set this bit instead of raising an <<
1838 Similarly, writes to read-only page <<
1839 clear the read-only bit (AP[2]) ins <<
1840 permission fault. <<
1841 2174
1842 Kernels built with this configurati !! 2175 source "mm/Kconfig"
1843 to work on pre-ARMv8.1 hardware and <<
1844 minimal. If unsure, say Y. <<
1845 2176
1846 config ARM64_PAN !! 2177 config SMP
1847 bool "Enable support for Privileged A !! 2178 bool "Multi-Processing support"
1848 default y !! 2179 depends on SYS_SUPPORTS_SMP
>> 2180 select USE_GENERIC_SMP_HELPERS
1849 help 2181 help
1850 Privileged Access Never (PAN; part !! 2182 This enables support for systems with more than one CPU. If you have
1851 prevents the kernel or hypervisor f !! 2183 a system with only one CPU, like most personal computers, say N. If
1852 memory directly. !! 2184 you have a system with more than one CPU, say Y.
1853 <<
1854 Choosing this option will cause any <<
1855 copy_to_user et al) memory access t <<
1856 2185
1857 The feature is detected at runtime, !! 2186 If you say N here, the kernel will run on single and multiprocessor
1858 instruction if the cpu does not imp !! 2187 machines, but will use only one CPU of a multiprocessor machine. If
>> 2188 you say Y here, the kernel will run on many, but not all,
>> 2189 singleprocessor machines. On a singleprocessor machine, the kernel
>> 2190 will run faster if you say N here.
1859 2191
1860 config AS_HAS_LSE_ATOMICS !! 2192 People using multiprocessor machines who say Y here should also say
1861 def_bool $(as-instr,.arch_extension l !! 2193 Y to "Enhanced Real Time Clock Support", below.
1862 2194
1863 config ARM64_LSE_ATOMICS !! 2195 See also the SMP-HOWTO available at
1864 bool !! 2196 <http://www.tldp.org/docs.html#howto>.
1865 default ARM64_USE_LSE_ATOMICS <<
1866 depends on AS_HAS_LSE_ATOMICS <<
1867 2197
1868 config ARM64_USE_LSE_ATOMICS !! 2198 If you don't know what to do here, say N.
1869 bool "Atomic instructions" <<
1870 default y <<
1871 help <<
1872 As part of the Large System Extensi <<
1873 atomic instructions that are design <<
1874 very large systems. <<
1875 2199
1876 Say Y here to make use of these ins !! 2200 config SMP_UP
1877 atomic routines. This incurs a smal !! 2201 bool
1878 not support these instructions and <<
1879 built with binutils >= 2.25 in orde <<
1880 to be used. <<
1881 <<
1882 endmenu # "ARMv8.1 architectural features" <<
1883 2202
1884 menu "ARMv8.2 architectural features" !! 2203 config SYS_SUPPORTS_MIPS_CMP
>> 2204 bool
1885 2205
1886 config AS_HAS_ARMV8_2 !! 2206 config SYS_SUPPORTS_SMP
1887 def_bool $(cc-option,-Wa$(comma)-marc !! 2207 bool
1888 2208
1889 config AS_HAS_SHA3 !! 2209 config NR_CPUS_DEFAULT_1
1890 def_bool $(as-instr,.arch armv8.2-a+s !! 2210 bool
1891 2211
1892 config ARM64_PMEM !! 2212 config NR_CPUS_DEFAULT_2
1893 bool "Enable support for persistent m !! 2213 bool
1894 select ARCH_HAS_PMEM_API <<
1895 select ARCH_HAS_UACCESS_FLUSHCACHE <<
1896 help <<
1897 Say Y to enable support for the per <<
1898 ARMv8.2 DCPoP feature. <<
1899 2214
1900 The feature is detected at runtime, !! 2215 config NR_CPUS_DEFAULT_4
1901 operations if DC CVAP is not suppor !! 2216 bool
1902 DC CVAP itself if the system does n <<
1903 2217
1904 config ARM64_RAS_EXTN !! 2218 config NR_CPUS_DEFAULT_8
1905 bool "Enable support for RAS CPU Exte !! 2219 bool
1906 default y <<
1907 help <<
1908 CPUs that support the Reliability, <<
1909 (RAS) Extensions, part of ARMv8.2 a <<
1910 errors, classify them and report th <<
1911 2220
1912 On CPUs with these extensions syste !! 2221 config NR_CPUS_DEFAULT_16
1913 barriers to determine if faults are !! 2222 bool
1914 classification from a new set of re <<
1915 2223
1916 Selecting this feature will allow t !! 2224 config NR_CPUS_DEFAULT_32
1917 and access the new registers if the !! 2225 bool
1918 Platform RAS features may additiona <<
1919 2226
1920 config ARM64_CNP !! 2227 config NR_CPUS_DEFAULT_64
1921 bool "Enable support for Common Not P !! 2228 bool
1922 default y <<
1923 depends on ARM64_PAN || !ARM64_SW_TTB <<
1924 help <<
1925 Common Not Private (CNP) allows tra <<
1926 be shared between different PEs in <<
1927 domain, so the hardware can use thi <<
1928 caching of such entries in the TLB. <<
1929 2229
1930 Selecting this option allows the CN !! 2230 config NR_CPUS
1931 at runtime, and does not affect PEs !! 2231 int "Maximum number of CPUs (2-64)"
1932 this feature. !! 2232 range 1 64 if NR_CPUS_DEFAULT_1
>> 2233 depends on SMP
>> 2234 default "1" if NR_CPUS_DEFAULT_1
>> 2235 default "2" if NR_CPUS_DEFAULT_2
>> 2236 default "4" if NR_CPUS_DEFAULT_4
>> 2237 default "8" if NR_CPUS_DEFAULT_8
>> 2238 default "16" if NR_CPUS_DEFAULT_16
>> 2239 default "32" if NR_CPUS_DEFAULT_32
>> 2240 default "64" if NR_CPUS_DEFAULT_64
>> 2241 help
>> 2242 This allows you to specify the maximum number of CPUs which this
>> 2243 kernel will support. The maximum supported value is 32 for 32-bit
>> 2244 kernel and 64 for 64-bit kernels; the minimum value which makes
>> 2245 sense is 1 for Qemu (useful only for kernel debugging purposes)
>> 2246 and 2 for all others.
>> 2247
>> 2248 This is purely to save memory - each supported CPU adds
>> 2249 approximately eight kilobytes to the kernel image. For best
>> 2250 performance should round up your number of processors to the next
>> 2251 power of two.
1933 2252
1934 endmenu # "ARMv8.2 architectural features" !! 2253 config MIPS_PERF_SHARED_TC_COUNTERS
>> 2254 bool
1935 2255
1936 menu "ARMv8.3 architectural features" !! 2256 #
>> 2257 # Timer Interrupt Frequency Configuration
>> 2258 #
1937 2259
1938 config ARM64_PTR_AUTH !! 2260 choice
1939 bool "Enable support for pointer auth !! 2261 prompt "Timer frequency"
1940 default y !! 2262 default HZ_250
1941 help 2263 help
1942 Pointer authentication (part of the !! 2264 Allows the configuration of the timer frequency.
1943 instructions for signing and authen <<
1944 keys, which can be used to mitigate <<
1945 and other attacks. <<
1946 <<
1947 This option enables these instructi <<
1948 Choosing this option will cause the <<
1949 for each process at exec() time, wi <<
1950 context-switched along with the pro <<
1951 <<
1952 The feature is detected at runtime. <<
1953 hardware it will not be advertised <<
1954 be enabled. <<
1955 2265
1956 If the feature is present on the bo !! 2266 config HZ_48
1957 the late CPU will be parked. Also, !! 2267 bool "48 HZ" if SYS_SUPPORTS_48HZ || SYS_SUPPORTS_ARBIT_HZ
1958 address auth and the late CPU has t <<
1959 but with the feature disabled. On s <<
1960 not be selected. <<
1961 2268
1962 config ARM64_PTR_AUTH_KERNEL !! 2269 config HZ_100
1963 bool "Use pointer authentication for !! 2270 bool "100 HZ" if SYS_SUPPORTS_100HZ || SYS_SUPPORTS_ARBIT_HZ
1964 default y <<
1965 depends on ARM64_PTR_AUTH <<
1966 depends on (CC_HAS_SIGN_RETURN_ADDRES <<
1967 # Modern compilers insert a .note.gnu <<
1968 # which is only understood by binutil <<
1969 depends on LD_IS_LLD || LD_VERSION >= <<
1970 depends on !CC_IS_CLANG || AS_HAS_CFI <<
1971 depends on (!FUNCTION_GRAPH_TRACER || <<
1972 help <<
1973 If the compiler supports the -mbran <<
1974 -msign-return-address flag (e.g. GC <<
1975 will cause the kernel itself to be <<
1976 protection. In this case, and if th <<
1977 support pointer authentication, the <<
1978 disabled with minimal loss of prote <<
1979 2271
1980 This feature works with FUNCTION_GR !! 2272 config HZ_128
1981 DYNAMIC_FTRACE_WITH_ARGS is enabled !! 2273 bool "128 HZ" if SYS_SUPPORTS_128HZ || SYS_SUPPORTS_ARBIT_HZ
1982 2274
1983 config CC_HAS_BRANCH_PROT_PAC_RET !! 2275 config HZ_250
1984 # GCC 9 or later, clang 8 or later !! 2276 bool "250 HZ" if SYS_SUPPORTS_250HZ || SYS_SUPPORTS_ARBIT_HZ
1985 def_bool $(cc-option,-mbranch-protect <<
1986 2277
1987 config CC_HAS_SIGN_RETURN_ADDRESS !! 2278 config HZ_256
1988 # GCC 7, 8 !! 2279 bool "256 HZ" if SYS_SUPPORTS_256HZ || SYS_SUPPORTS_ARBIT_HZ
1989 def_bool $(cc-option,-msign-return-ad <<
1990 2280
1991 config AS_HAS_ARMV8_3 !! 2281 config HZ_1000
1992 def_bool $(cc-option,-Wa$(comma)-marc !! 2282 bool "1000 HZ" if SYS_SUPPORTS_1000HZ || SYS_SUPPORTS_ARBIT_HZ
1993 2283
1994 config AS_HAS_CFI_NEGATE_RA_STATE !! 2284 config HZ_1024
1995 def_bool $(as-instr,.cfi_startproc\n. !! 2285 bool "1024 HZ" if SYS_SUPPORTS_1024HZ || SYS_SUPPORTS_ARBIT_HZ
1996 2286
1997 config AS_HAS_LDAPR !! 2287 endchoice
1998 def_bool $(as-instr,.arch_extension r <<
1999 2288
2000 endmenu # "ARMv8.3 architectural features" !! 2289 config SYS_SUPPORTS_48HZ
>> 2290 bool
2001 2291
2002 menu "ARMv8.4 architectural features" !! 2292 config SYS_SUPPORTS_100HZ
>> 2293 bool
2003 2294
2004 config ARM64_AMU_EXTN !! 2295 config SYS_SUPPORTS_128HZ
2005 bool "Enable support for the Activity !! 2296 bool
2006 default y <<
2007 help <<
2008 The activity monitors extension is <<
2009 by the ARMv8.4 CPU architecture. Th <<
2010 of the activity monitors architectu <<
2011 2297
2012 To enable the use of this extension !! 2298 config SYS_SUPPORTS_250HZ
>> 2299 bool
2013 2300
2014 Note that for architectural reasons !! 2301 config SYS_SUPPORTS_256HZ
2015 support when running on CPUs that p !! 2302 bool
2016 extension. The required support is <<
2017 * Version 1.5 and later of the AR <<
2018 2303
2019 For kernels that have this configur !! 2304 config SYS_SUPPORTS_1000HZ
2020 firmware, you may need to say N her !! 2305 bool
2021 Otherwise you may experience firmwa <<
2022 accessing the counter registers. Ev <<
2023 symptoms, the values returned by th <<
2024 correctly reflect reality. Most com <<
2025 indicating that the counter is not <<
2026 2306
2027 config AS_HAS_ARMV8_4 !! 2307 config SYS_SUPPORTS_1024HZ
2028 def_bool $(cc-option,-Wa$(comma)-marc !! 2308 bool
2029 2309
2030 config ARM64_TLB_RANGE !! 2310 config SYS_SUPPORTS_ARBIT_HZ
2031 bool "Enable support for tlbi range f !! 2311 bool
2032 default y !! 2312 default y if !SYS_SUPPORTS_48HZ && !SYS_SUPPORTS_100HZ && \
2033 depends on AS_HAS_ARMV8_4 !! 2313 !SYS_SUPPORTS_128HZ && !SYS_SUPPORTS_250HZ && \
2034 help !! 2314 !SYS_SUPPORTS_256HZ && !SYS_SUPPORTS_1000HZ && \
2035 ARMv8.4-TLBI provides TLBI invalida !! 2315 !SYS_SUPPORTS_1024HZ
2036 range of input addresses. <<
2037 2316
2038 The feature introduces new assembly !! 2317 config HZ
2039 support when binutils >= 2.30. !! 2318 int
>> 2319 default 48 if HZ_48
>> 2320 default 100 if HZ_100
>> 2321 default 128 if HZ_128
>> 2322 default 250 if HZ_250
>> 2323 default 256 if HZ_256
>> 2324 default 1000 if HZ_1000
>> 2325 default 1024 if HZ_1024
>> 2326
>> 2327 source "kernel/Kconfig.preempt"
>> 2328
>> 2329 config KEXEC
>> 2330 bool "Kexec system call"
>> 2331 help
>> 2332 kexec is a system call that implements the ability to shutdown your
>> 2333 current kernel, and to start another kernel. It is like a reboot
>> 2334 but it is independent of the system firmware. And like a reboot
>> 2335 you can start any kernel with it, not just Linux.
>> 2336
>> 2337 The name comes from the similarity to the exec system call.
>> 2338
>> 2339 It is an ongoing process to be certain the hardware in a machine
>> 2340 is properly shutdown, so do not be surprised if this code does not
>> 2341 initially work for you. It may help to enable device hotplugging
>> 2342 support. As of this writing the exact hardware interface is
>> 2343 strongly in flux, so no good recommendation can be made.
>> 2344
>> 2345 config CRASH_DUMP
>> 2346 bool "Kernel crash dumps"
>> 2347 help
>> 2348 Generate crash dump after being started by kexec.
>> 2349 This should be normally only set in special crash dump kernels
>> 2350 which are loaded in the main kernel with kexec-tools into
>> 2351 a specially reserved region and then later executed after
>> 2352 a crash by kdump/kexec. The crash dump kernel must be compiled
>> 2353 to a memory address not used by the main kernel or firmware using
>> 2354 PHYSICAL_START.
>> 2355
>> 2356 config PHYSICAL_START
>> 2357 hex "Physical address where the kernel is loaded"
>> 2358 default "0xffffffff84000000" if 64BIT
>> 2359 default "0x84000000" if 32BIT
>> 2360 depends on CRASH_DUMP
>> 2361 help
>> 2362 This gives the CKSEG0 or KSEG0 address where the kernel is loaded.
>> 2363 If you plan to use kernel for capturing the crash dump change
>> 2364 this value to start of the reserved region (the "X" value as
>> 2365 specified in the "crashkernel=YM@XM" command line boot parameter
>> 2366 passed to the panic-ed kernel).
>> 2367
>> 2368 config SECCOMP
>> 2369 bool "Enable seccomp to safely compute untrusted bytecode"
>> 2370 depends on PROC_FS
>> 2371 default y
>> 2372 help
>> 2373 This kernel feature is useful for number crunching applications
>> 2374 that may need to compute untrusted bytecode during their
>> 2375 execution. By using pipes or other transports made available to
>> 2376 the process as file descriptors supporting the read/write
>> 2377 syscalls, it's possible to isolate those applications in
>> 2378 their own address space using seccomp. Once seccomp is
>> 2379 enabled via /proc/<pid>/seccomp, it cannot be disabled
>> 2380 and the task is only allowed to execute a few safe syscalls
>> 2381 defined by each seccomp mode.
2040 2382
2041 endmenu # "ARMv8.4 architectural features" !! 2383 If unsure, say Y. Only embedded should say N here.
2042 2384
2043 menu "ARMv8.5 architectural features" !! 2385 config USE_OF
>> 2386 bool
>> 2387 select OF
>> 2388 select OF_EARLY_FLATTREE
>> 2389 select IRQ_DOMAIN
2044 2390
2045 config AS_HAS_ARMV8_5 !! 2391 endmenu
2046 def_bool $(cc-option,-Wa$(comma)-marc <<
2047 2392
2048 config ARM64_BTI !! 2393 config LOCKDEP_SUPPORT
2049 bool "Branch Target Identification su !! 2394 bool
2050 default y 2395 default y
2051 help <<
2052 Branch Target Identification (part <<
2053 provides a mechanism to limit the s <<
2054 branch instructions such as BR or B <<
2055 2396
2056 To make use of BTI on CPUs that sup !! 2397 config STACKTRACE_SUPPORT
2057 !! 2398 bool
2058 BTI is intended to provide compleme <<
2059 flow integrity protection mechanism <<
2060 authentication mechanism provided a <<
2061 For this reason, it does not make s <<
2062 also enabling support for pointer a <<
2063 enabling this option you should als <<
2064 <<
2065 Userspace binaries must also be spe <<
2066 this mechanism. If you say N here <<
2067 BTI, such binaries can still run, b <<
2068 enforcement of branch destinations. <<
2069 <<
2070 config ARM64_BTI_KERNEL <<
2071 bool "Use Branch Target Identificatio <<
2072 default y 2399 default y
2073 depends on ARM64_BTI <<
2074 depends on ARM64_PTR_AUTH_KERNEL <<
2075 depends on CC_HAS_BRANCH_PROT_PAC_RET <<
2076 # https://gcc.gnu.org/bugzilla/show_b <<
2077 depends on !CC_IS_GCC || GCC_VERSION <<
2078 # https://gcc.gnu.org/bugzilla/show_b <<
2079 depends on !CC_IS_GCC <<
2080 depends on (!FUNCTION_GRAPH_TRACER || <<
2081 help <<
2082 Build the kernel with Branch Target <<
2083 and enable enforcement of this for <<
2084 is enabled and the system supports <<
2085 modular code must have BTI enabled. <<
2086 2400
2087 config CC_HAS_BRANCH_PROT_PAC_RET_BTI !! 2401 source "init/Kconfig"
2088 # GCC 9 or later, clang 8 or later <<
2089 def_bool $(cc-option,-mbranch-protect <<
2090 2402
2091 config ARM64_E0PD !! 2403 source "kernel/Kconfig.freezer"
2092 bool "Enable support for E0PD" <<
2093 default y <<
2094 help <<
2095 E0PD (part of the ARMv8.5 extension <<
2096 that EL0 accesses made via TTBR1 al <<
2097 providing similar benefits to KASLR <<
2098 with lower overhead and without dis <<
2099 kernel memory such as SPE. <<
2100 2404
2101 This option enables E0PD for TTBR1 !! 2405 menu "Bus options (PCI, PCMCIA, EISA, ISA, TC)"
2102 2406
2103 config ARM64_AS_HAS_MTE !! 2407 config HW_HAS_EISA
2104 # Initial support for MTE went in bin !! 2408 bool
2105 # ".arch armv8.5-a+memtag" below. How !! 2409 config HW_HAS_PCI
2106 # as a late addition to the final arc !! 2410 bool
2107 # is only supported in the newer 2.32 <<
2108 # versions, hence the extra "stgm" in <<
2109 def_bool $(as-instr,.arch armv8.5-a+m <<
2110 <<
2111 config ARM64_MTE <<
2112 bool "Memory Tagging Extension suppor <<
2113 default y <<
2114 depends on ARM64_AS_HAS_MTE && ARM64_ <<
2115 depends on AS_HAS_ARMV8_5 <<
2116 depends on AS_HAS_LSE_ATOMICS <<
2117 # Required for tag checking in the ua <<
2118 depends on ARM64_PAN <<
2119 select ARCH_HAS_SUBPAGE_FAULTS <<
2120 select ARCH_USES_HIGH_VMA_FLAGS <<
2121 select ARCH_USES_PG_ARCH_2 <<
2122 select ARCH_USES_PG_ARCH_3 <<
2123 help <<
2124 Memory Tagging (part of the ARMv8.5 <<
2125 architectural support for run-time, <<
2126 various classes of memory error to <<
2127 to eliminate vulnerabilities arisin <<
2128 languages. <<
2129 2411
2130 This option enables the support for !! 2412 config PCI
2131 Extension at EL0 (i.e. for userspac !! 2413 bool "Support for PCI controller"
>> 2414 depends on HW_HAS_PCI
>> 2415 select PCI_DOMAINS
>> 2416 select NO_GENERIC_PCI_IOPORT_MAP
>> 2417 help
>> 2418 Find out whether you have a PCI motherboard. PCI is the name of a
>> 2419 bus system, i.e. the way the CPU talks to the other stuff inside
>> 2420 your box. Other bus systems are ISA, EISA, or VESA. If you have PCI,
>> 2421 say Y, otherwise N.
2132 2422
2133 Selecting this option allows the fe !! 2423 config PCI_DOMAINS
2134 runtime. Any secondary CPU not impl !! 2424 bool
2135 not be allowed a late bring-up. <<
2136 2425
2137 Userspace binaries that want to use !! 2426 source "drivers/pci/Kconfig"
2138 explicitly opt in. The mechanism fo <<
2139 described in: <<
2140 2427
2141 Documentation/arch/arm64/memory-tag !! 2428 source "drivers/pci/pcie/Kconfig"
2142 2429
2143 endmenu # "ARMv8.5 architectural features" !! 2430 #
>> 2431 # ISA support is now enabled via select. Too many systems still have the one
>> 2432 # or other ISA chip on the board that users don't know about so don't expect
>> 2433 # users to choose the right thing ...
>> 2434 #
>> 2435 config ISA
>> 2436 bool
2144 2437
2145 menu "ARMv8.7 architectural features" !! 2438 config EISA
>> 2439 bool "EISA support"
>> 2440 depends on HW_HAS_EISA
>> 2441 select ISA
>> 2442 select GENERIC_ISA_DMA
>> 2443 ---help---
>> 2444 The Extended Industry Standard Architecture (EISA) bus was
>> 2445 developed as an open alternative to the IBM MicroChannel bus.
>> 2446
>> 2447 The EISA bus provided some of the features of the IBM MicroChannel
>> 2448 bus while maintaining backward compatibility with cards made for
>> 2449 the older ISA bus. The EISA bus saw limited use between 1988 and
>> 2450 1995 when it was made obsolete by the PCI bus.
>> 2451
>> 2452 Say Y here if you are building a kernel for an EISA-based machine.
>> 2453
>> 2454 Otherwise, say N.
>> 2455
>> 2456 source "drivers/eisa/Kconfig"
>> 2457
>> 2458 config TC
>> 2459 bool "TURBOchannel support"
>> 2460 depends on MACH_DECSTATION
>> 2461 help
>> 2462 TURBOchannel is a DEC (now Compaq (now HP)) bus for Alpha and MIPS
>> 2463 processors. TURBOchannel programming specifications are available
>> 2464 at:
>> 2465 <ftp://ftp.hp.com/pub/alphaserver/archive/triadd/>
>> 2466 and:
>> 2467 <http://www.computer-refuge.org/classiccmp/ftp.digital.com/pub/DEC/TriAdd/>
>> 2468 Linux driver support status is documented at:
>> 2469 <http://www.linux-mips.org/wiki/DECstation>
2146 2470
2147 config ARM64_EPAN !! 2471 config MMU
2148 bool "Enable support for Enhanced Pri !! 2472 bool
2149 default y 2473 default y
2150 depends on ARM64_PAN <<
2151 help <<
2152 Enhanced Privileged Access Never (E <<
2153 Access Never to be used with Execut <<
2154 <<
2155 The feature is detected at runtime, <<
2156 if the cpu does not implement the f <<
2157 endmenu # "ARMv8.7 architectural features" <<
2158 2474
2159 menu "ARMv8.9 architectural features" !! 2475 config I8253
2160 !! 2476 bool
2161 config ARM64_POE !! 2477 select CLKSRC_I8253
2162 prompt "Permission Overlay Extension" !! 2478 select CLKEVT_I8253
2163 def_bool y !! 2479 select MIPS_EXTERNAL_TIMER
2164 select ARCH_USES_HIGH_VMA_FLAGS <<
2165 select ARCH_HAS_PKEYS <<
2166 help <<
2167 The Permission Overlay Extension is <<
2168 Protection Keys. Memory Protection <<
2169 enforcing page-based protections, b <<
2170 of the page tables when an applicat <<
2171 <<
2172 For details, see Documentation/core <<
2173 2480
2174 If unsure, say y. !! 2481 config ZONE_DMA32
>> 2482 bool
2175 2483
2176 config ARCH_PKEY_BITS !! 2484 source "drivers/pcmcia/Kconfig"
2177 int <<
2178 default 3 <<
2179 2485
2180 endmenu # "ARMv8.9 architectural features" !! 2486 source "drivers/pci/hotplug/Kconfig"
2181 2487
2182 config ARM64_SVE !! 2488 config RAPIDIO
2183 bool "ARM Scalable Vector Extension s !! 2489 bool "RapidIO support"
2184 default y !! 2490 depends on PCI
>> 2491 default n
2185 help 2492 help
2186 The Scalable Vector Extension (SVE) !! 2493 If you say Y here, the kernel will include drivers and
2187 execution state which complements a !! 2494 infrastructure code to support RapidIO interconnect devices.
2188 of the base architecture to support <<
2189 additional vectorisation opportunit <<
2190 2495
2191 To enable use of this extension on !! 2496 source "drivers/rapidio/Kconfig"
2192 2497
2193 On CPUs that support the SVE2 exten !! 2498 endmenu
2194 those too. <<
2195 2499
2196 Note that for architectural reasons !! 2500 menu "Executable file formats"
2197 support when running on SVE capable <<
2198 is present in: <<
2199 2501
2200 * version 1.5 and later of the AR !! 2502 source "fs/Kconfig.binfmt"
2201 * the AArch64 boot wrapper since <<
2202 ("bootwrapper: SVE: Enable SVE <<
2203 2503
2204 For other firmware implementations, !! 2504 config TRAD_SIGNALS
2205 or vendor. !! 2505 bool
2206 2506
2207 If you need the kernel to boot on S !! 2507 config MIPS32_COMPAT
2208 firmware, you may need to say N her !! 2508 bool "Kernel support for Linux/MIPS 32-bit binary compatibility"
2209 fixed. Otherwise, you may experien !! 2509 depends on 64BIT
2210 booting the kernel. If unsure and !! 2510 help
2211 symptoms, you should assume that it !! 2511 Select this option if you want Linux/MIPS 32-bit binary
>> 2512 compatibility. Since all software available for Linux/MIPS is
>> 2513 currently 32-bit you should say Y here.
2212 2514
2213 config ARM64_SME !! 2515 config COMPAT
2214 bool "ARM Scalable Matrix Extension s !! 2516 bool
>> 2517 depends on MIPS32_COMPAT
>> 2518 select ARCH_WANT_OLD_COMPAT_IPC
2215 default y 2519 default y
2216 depends on ARM64_SVE <<
2217 depends on BROKEN <<
2218 help <<
2219 The Scalable Matrix Extension (SME) <<
2220 execution state which utilises a su <<
2221 instruction set, together with the <<
2222 register state capable of holding t <<
2223 enable various matrix operations. <<
2224 <<
2225 config ARM64_PSEUDO_NMI <<
2226 bool "Support for NMI-like interrupts <<
2227 select ARM_GIC_V3 <<
2228 help <<
2229 Adds support for mimicking Non-Mask <<
2230 GIC interrupt priority. This suppor <<
2231 ARM GIC. <<
2232 <<
2233 This high priority configuration fo <<
2234 explicitly enabled by setting the k <<
2235 "irqchip.gicv3_pseudo_nmi" to 1. <<
2236 2520
2237 If unsure, say N !! 2521 config SYSVIPC_COMPAT
2238 !! 2522 bool
2239 if ARM64_PSEUDO_NMI !! 2523 depends on COMPAT && SYSVIPC
2240 config ARM64_DEBUG_PRIORITY_MASKING <<
2241 bool "Debug interrupt priority maskin <<
2242 help <<
2243 This adds runtime checks to functio <<
2244 interrupts when using priority mask <<
2245 the validity of ICC_PMR_EL1 when ca <<
2246 <<
2247 If unsure, say N <<
2248 endif # ARM64_PSEUDO_NMI <<
2249 <<
2250 config RELOCATABLE <<
2251 bool "Build a relocatable kernel imag <<
2252 select ARCH_HAS_RELR <<
2253 default y 2524 default y
2254 help <<
2255 This builds the kernel as a Positio <<
2256 which retains all relocation metada <<
2257 kernel binary at runtime to a diffe <<
2258 address it was linked at. <<
2259 Since AArch64 uses the RELA relocat <<
2260 relocation pass at runtime even if <<
2261 same address it was linked at. <<
2262 2525
2263 config RANDOMIZE_BASE !! 2526 config MIPS32_O32
2264 bool "Randomize the address of the ke !! 2527 bool "Kernel support for o32 binaries"
2265 select RELOCATABLE !! 2528 depends on MIPS32_COMPAT
2266 help 2529 help
2267 Randomizes the virtual address at w !! 2530 Select this option if you want to run o32 binaries. These are pure
2268 loaded, as a security feature that !! 2531 32-bit binaries as used by the 32-bit Linux/MIPS port. Most of
2269 relying on knowledge of the locatio !! 2532 existing binaries are in this format.
2270 2533
2271 It is the bootloader's job to provi !! 2534 If unsure, say Y.
2272 random u64 value in /chosen/kaslr-s <<
2273 2535
2274 When booting via the UEFI stub, it !! 2536 config MIPS32_N32
2275 EFI_RNG_PROTOCOL implementation (if !! 2537 bool "Kernel support for n32 binaries"
2276 to the kernel proper. In addition, !! 2538 depends on MIPS32_COMPAT
2277 location of the kernel Image as wel !! 2539 help
>> 2540 Select this option if you want to run n32 binaries. These are
>> 2541 64-bit binaries using 32-bit quantities for addressing and certain
>> 2542 data that would normally be 64-bit. They are used in special
>> 2543 cases.
2278 2544
2279 If unsure, say N. 2545 If unsure, say N.
2280 2546
2281 config RANDOMIZE_MODULE_REGION_FULL !! 2547 config BINFMT_ELF32
2282 bool "Randomize the module region ove <<
2283 depends on RANDOMIZE_BASE <<
2284 default y <<
2285 help <<
2286 Randomizes the location of the modu <<
2287 covering the core kernel. This way, <<
2288 to leak information about the locat <<
2289 but it does imply that function cal <<
2290 kernel will need to be resolved via <<
2291 <<
2292 When this option is not set, the mo <<
2293 a limited range that contains the [ <<
2294 core kernel, so branch relocations <<
2295 the region is exhausted. In this pa <<
2296 exhaustion, modules might be able t <<
2297 <<
2298 config CC_HAVE_STACKPROTECTOR_SYSREG <<
2299 def_bool $(cc-option,-mstack-protecto <<
2300 <<
2301 config STACKPROTECTOR_PER_TASK <<
2302 def_bool y <<
2303 depends on STACKPROTECTOR && CC_HAVE_ <<
2304 <<
2305 config UNWIND_PATCH_PAC_INTO_SCS <<
2306 bool "Enable shadow call stack dynami <<
2307 # needs Clang with https://github.com <<
2308 depends on CC_IS_CLANG && CLANG_VERSI <<
2309 depends on ARM64_PTR_AUTH_KERNEL && C <<
2310 depends on SHADOW_CALL_STACK <<
2311 select UNWIND_TABLES <<
2312 select DYNAMIC_SCS <<
2313 <<
2314 config ARM64_CONTPTE <<
2315 bool "Contiguous PTE mappings for use <<
2316 depends on TRANSPARENT_HUGEPAGE <<
2317 default y <<
2318 help <<
2319 When enabled, user mappings are con <<
2320 bit, for any mappings that meet the <<
2321 This reduces TLB pressure and impro <<
2322 <<
2323 endmenu # "Kernel Features" <<
2324 <<
2325 menu "Boot options" <<
2326 <<
2327 config ARM64_ACPI_PARKING_PROTOCOL <<
2328 bool "Enable support for the ARM64 AC <<
2329 depends on ACPI <<
2330 help <<
2331 Enable support for the ARM64 ACPI p <<
2332 the kernel will not allow booting t <<
2333 protocol even if the corresponding <<
2334 MADT table. <<
2335 <<
2336 config CMDLINE <<
2337 string "Default kernel command string <<
2338 default "" <<
2339 help <<
2340 Provide a set of default command-li <<
2341 entering them here. As a minimum, y <<
2342 root device (e.g. root=/dev/nfs). <<
2343 <<
2344 choice <<
2345 prompt "Kernel command line type" <<
2346 depends on CMDLINE != "" <<
2347 default CMDLINE_FROM_BOOTLOADER <<
2348 help <<
2349 Choose how the kernel will handle t <<
2350 command line string. <<
2351 <<
2352 config CMDLINE_FROM_BOOTLOADER <<
2353 bool "Use bootloader kernel arguments <<
2354 help <<
2355 Uses the command-line options passe <<
2356 the boot loader doesn't provide any <<
2357 string provided in CMDLINE will be <<
2358 <<
2359 config CMDLINE_FORCE <<
2360 bool "Always use the default kernel c <<
2361 help <<
2362 Always use the default kernel comma <<
2363 loader passes other arguments to th <<
2364 This is useful if you cannot or don <<
2365 command-line options your boot load <<
2366 <<
2367 endchoice <<
2368 <<
2369 config EFI_STUB <<
2370 bool 2548 bool
>> 2549 default y if MIPS32_O32 || MIPS32_N32
2371 2550
2372 config EFI !! 2551 endmenu
2373 bool "UEFI runtime support" <<
2374 depends on OF && !CPU_BIG_ENDIAN <<
2375 depends on KERNEL_MODE_NEON <<
2376 select ARCH_SUPPORTS_ACPI <<
2377 select LIBFDT <<
2378 select UCS2_STRING <<
2379 select EFI_PARAMS_FROM_FDT <<
2380 select EFI_RUNTIME_WRAPPERS <<
2381 select EFI_STUB <<
2382 select EFI_GENERIC_STUB <<
2383 imply IMA_SECURE_AND_OR_TRUSTED_BOOT <<
2384 default y <<
2385 help <<
2386 This option provides support for ru <<
2387 by UEFI firmware (such as non-volat <<
2388 clock, and platform reset). A UEFI <<
2389 allow the kernel to be booted as an <<
2390 is only useful on systems that have <<
2391 <<
2392 config COMPRESSED_INSTALL <<
2393 bool "Install compressed image by def <<
2394 help <<
2395 This makes the regular "make instal <<
2396 image we built, not the legacy unco <<
2397 <<
2398 You can check that a compressed ima <<
2399 "make zinstall" first, and verifyin <<
2400 in your environment before making " <<
2401 you. <<
2402 <<
2403 config DMI <<
2404 bool "Enable support for SMBIOS (DMI) <<
2405 depends on EFI <<
2406 default y <<
2407 help <<
2408 This enables SMBIOS/DMI feature for <<
2409 <<
2410 This option is only useful on syste <<
2411 However, even with this option, the <<
2412 continue to boot on existing non-UE <<
2413 <<
2414 endmenu # "Boot options" <<
2415 2552
2416 menu "Power management options" 2553 menu "Power management options"
2417 2554
2418 source "kernel/power/Kconfig" <<
2419 <<
2420 config ARCH_HIBERNATION_POSSIBLE 2555 config ARCH_HIBERNATION_POSSIBLE
2421 def_bool y 2556 def_bool y
2422 depends on CPU_PM !! 2557 depends on SYS_SUPPORTS_HOTPLUG_CPU || !SMP
2423 <<
2424 config ARCH_HIBERNATION_HEADER <<
2425 def_bool y <<
2426 depends on HIBERNATION <<
2427 2558
2428 config ARCH_SUSPEND_POSSIBLE 2559 config ARCH_SUSPEND_POSSIBLE
2429 def_bool y 2560 def_bool y
>> 2561 depends on SYS_SUPPORTS_HOTPLUG_CPU || !SMP
2430 2562
2431 endmenu # "Power management options" !! 2563 source "kernel/power/Kconfig"
2432 2564
2433 menu "CPU Power Management" !! 2565 endmenu
2434 2566
2435 source "drivers/cpuidle/Kconfig" !! 2567 config MIPS_EXTERNAL_TIMER
>> 2568 bool
2436 2569
>> 2570 if CPU_SUPPORTS_CPUFREQ && MIPS_EXTERNAL_TIMER
>> 2571 menu "CPU Power Management"
2437 source "drivers/cpufreq/Kconfig" 2572 source "drivers/cpufreq/Kconfig"
>> 2573 endmenu
>> 2574 endif
>> 2575
>> 2576 source "net/Kconfig"
>> 2577
>> 2578 source "drivers/Kconfig"
>> 2579
>> 2580 source "drivers/firmware/Kconfig"
>> 2581
>> 2582 source "fs/Kconfig"
>> 2583
>> 2584 source "arch/mips/Kconfig.debug"
2438 2585
2439 endmenu # "CPU Power Management" !! 2586 source "security/Kconfig"
2440 2587
2441 source "drivers/acpi/Kconfig" !! 2588 source "crypto/Kconfig"
2442 2589
2443 source "arch/arm64/kvm/Kconfig" !! 2590 source "lib/Kconfig"
2444 2591
>> 2592 source "arch/mips/kvm/Kconfig"
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