1 # SPDX-License-Identifier: GPL-2.0-only !! 1 config MIPS
2 config ARM64 !! 2 bool
3 def_bool y !! 3 default y
4 select ACPI_APMT if ACPI !! 4 select ARCH_SUPPORTS_UPROBES
5 select ACPI_CCA_REQUIRED if ACPI !! 5 select ARCH_MIGHT_HAVE_PC_PARPORT
6 select ACPI_GENERIC_GSI if ACPI !! 6 select ARCH_MIGHT_HAVE_PC_SERIO
7 select ACPI_GTDT if ACPI !! 7 select ARCH_USE_CMPXCHG_LOCKREF if 64BIT
8 select ACPI_HOTPLUG_CPU if ACPI_PROCES !! 8 select ARCH_USE_BUILTIN_BSWAP
9 select ACPI_IORT if ACPI !! 9 select HAVE_CONTEXT_TRACKING
10 select ACPI_REDUCED_HARDWARE_ONLY if A !! 10 select HAVE_GENERIC_DMA_COHERENT
11 select ACPI_MCFG if (ACPI && PCI) !! 11 select HAVE_IDE
12 select ACPI_SPCR_TABLE if ACPI !! 12 select HAVE_IRQ_EXIT_ON_IRQ_STACK
13 select ACPI_PPTT if ACPI !! 13 select HAVE_OPROFILE
14 select ARCH_HAS_DEBUG_WX !! 14 select HAVE_PERF_EVENTS
15 select ARCH_BINFMT_ELF_EXTRA_PHDRS !! 15 select PERF_USE_VMALLOC
16 select ARCH_BINFMT_ELF_STATE <<
17 select ARCH_CORRECT_STACKTRACE_ON_KRET <<
18 select ARCH_ENABLE_HUGEPAGE_MIGRATION <<
19 select ARCH_ENABLE_MEMORY_HOTPLUG <<
20 select ARCH_ENABLE_MEMORY_HOTREMOVE <<
21 select ARCH_ENABLE_SPLIT_PMD_PTLOCK if <<
22 select ARCH_ENABLE_THP_MIGRATION if TR <<
23 select ARCH_HAS_CACHE_LINE_SIZE <<
24 select ARCH_HAS_CURRENT_STACK_POINTER <<
25 select ARCH_HAS_DEBUG_VIRTUAL <<
26 select ARCH_HAS_DEBUG_VM_PGTABLE <<
27 select ARCH_HAS_DMA_OPS if XEN <<
28 select ARCH_HAS_DMA_PREP_COHERENT <<
29 select ARCH_HAS_ACPI_TABLE_UPGRADE if <<
30 select ARCH_HAS_FAST_MULTIPLIER <<
31 select ARCH_HAS_FORTIFY_SOURCE <<
32 select ARCH_HAS_GCOV_PROFILE_ALL <<
33 select ARCH_HAS_GIGANTIC_PAGE <<
34 select ARCH_HAS_KCOV <<
35 select ARCH_HAS_KERNEL_FPU_SUPPORT if <<
36 select ARCH_HAS_KEEPINITRD <<
37 select ARCH_HAS_MEMBARRIER_SYNC_CORE <<
38 select ARCH_HAS_MEM_ENCRYPT <<
39 select ARCH_HAS_NMI_SAFE_THIS_CPU_OPS <<
40 select ARCH_HAS_NON_OVERLAPPING_ADDRES <<
41 select ARCH_HAS_PTE_DEVMAP <<
42 select ARCH_HAS_PTE_SPECIAL <<
43 select ARCH_HAS_HW_PTE_YOUNG <<
44 select ARCH_HAS_SETUP_DMA_OPS <<
45 select ARCH_HAS_SET_DIRECT_MAP <<
46 select ARCH_HAS_SET_MEMORY <<
47 select ARCH_STACKWALK <<
48 select ARCH_HAS_STRICT_KERNEL_RWX <<
49 select ARCH_HAS_STRICT_MODULE_RWX <<
50 select ARCH_HAS_SYNC_DMA_FOR_DEVICE <<
51 select ARCH_HAS_SYNC_DMA_FOR_CPU <<
52 select ARCH_HAS_SYSCALL_WRAPPER <<
53 select ARCH_HAS_TICK_BROADCAST if GENE <<
54 select ARCH_HAS_ZONE_DMA_SET if EXPERT <<
55 select ARCH_HAVE_ELF_PROT <<
56 select ARCH_HAVE_NMI_SAFE_CMPXCHG <<
57 select ARCH_HAVE_TRACE_MMIO_ACCESS <<
58 select ARCH_INLINE_READ_LOCK if !PREEM <<
59 select ARCH_INLINE_READ_LOCK_BH if !PR <<
60 select ARCH_INLINE_READ_LOCK_IRQ if !P <<
61 select ARCH_INLINE_READ_LOCK_IRQSAVE i <<
62 select ARCH_INLINE_READ_UNLOCK if !PRE <<
63 select ARCH_INLINE_READ_UNLOCK_BH if ! <<
64 select ARCH_INLINE_READ_UNLOCK_IRQ if <<
65 select ARCH_INLINE_READ_UNLOCK_IRQREST <<
66 select ARCH_INLINE_WRITE_LOCK if !PREE <<
67 select ARCH_INLINE_WRITE_LOCK_BH if !P <<
68 select ARCH_INLINE_WRITE_LOCK_IRQ if ! <<
69 select ARCH_INLINE_WRITE_LOCK_IRQSAVE <<
70 select ARCH_INLINE_WRITE_UNLOCK if !PR <<
71 select ARCH_INLINE_WRITE_UNLOCK_BH if <<
72 select ARCH_INLINE_WRITE_UNLOCK_IRQ if <<
73 select ARCH_INLINE_WRITE_UNLOCK_IRQRES <<
74 select ARCH_INLINE_SPIN_TRYLOCK if !PR <<
75 select ARCH_INLINE_SPIN_TRYLOCK_BH if <<
76 select ARCH_INLINE_SPIN_LOCK if !PREEM <<
77 select ARCH_INLINE_SPIN_LOCK_BH if !PR <<
78 select ARCH_INLINE_SPIN_LOCK_IRQ if !P <<
79 select ARCH_INLINE_SPIN_LOCK_IRQSAVE i <<
80 select ARCH_INLINE_SPIN_UNLOCK if !PRE <<
81 select ARCH_INLINE_SPIN_UNLOCK_BH if ! <<
82 select ARCH_INLINE_SPIN_UNLOCK_IRQ if <<
83 select ARCH_INLINE_SPIN_UNLOCK_IRQREST <<
84 select ARCH_KEEP_MEMBLOCK <<
85 select ARCH_MHP_MEMMAP_ON_MEMORY_ENABL <<
86 select ARCH_USE_CMPXCHG_LOCKREF <<
87 select ARCH_USE_GNU_PROPERTY <<
88 select ARCH_USE_MEMTEST <<
89 select ARCH_USE_QUEUED_RWLOCKS <<
90 select ARCH_USE_QUEUED_SPINLOCKS <<
91 select ARCH_USE_SYM_ANNOTATIONS <<
92 select ARCH_SUPPORTS_DEBUG_PAGEALLOC <<
93 select ARCH_SUPPORTS_HUGETLBFS <<
94 select ARCH_SUPPORTS_MEMORY_FAILURE <<
95 select ARCH_SUPPORTS_SHADOW_CALL_STACK <<
96 select ARCH_SUPPORTS_LTO_CLANG if CPU_ <<
97 select ARCH_SUPPORTS_LTO_CLANG_THIN <<
98 select ARCH_SUPPORTS_CFI_CLANG <<
99 select ARCH_SUPPORTS_ATOMIC_RMW <<
100 select ARCH_SUPPORTS_INT128 if CC_HAS_ <<
101 select ARCH_SUPPORTS_NUMA_BALANCING <<
102 select ARCH_SUPPORTS_PAGE_TABLE_CHECK <<
103 select ARCH_SUPPORTS_PER_VMA_LOCK <<
104 select ARCH_SUPPORTS_HUGE_PFNMAP if TR <<
105 select ARCH_SUPPORTS_RT <<
106 select ARCH_WANT_BATCHED_UNMAP_TLB_FLU <<
107 select ARCH_WANT_COMPAT_IPC_PARSE_VERS <<
108 select ARCH_WANT_DEFAULT_BPF_JIT <<
109 select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_ <<
110 select ARCH_WANT_FRAME_POINTERS <<
111 select ARCH_WANT_HUGE_PMD_SHARE if ARM <<
112 select ARCH_WANT_LD_ORPHAN_WARN <<
113 select ARCH_WANTS_EXECMEM_LATE if EXEC <<
114 select ARCH_WANTS_NO_INSTR <<
115 select ARCH_WANTS_THP_SWAP if ARM64_4K <<
116 select ARCH_HAS_UBSAN <<
117 select ARM_AMBA <<
118 select ARM_ARCH_TIMER <<
119 select ARM_GIC <<
120 select AUDIT_ARCH_COMPAT_GENERIC <<
121 select ARM_GIC_V2M if PCI <<
122 select ARM_GIC_V3 <<
123 select ARM_GIC_V3_ITS if PCI <<
124 select ARM_PSCI_FW <<
125 select BUILDTIME_TABLE_SORT <<
126 select CLONE_BACKWARDS <<
127 select COMMON_CLK <<
128 select CPU_PM if (SUSPEND || CPU_IDLE) <<
129 select CPUMASK_OFFSTACK if NR_CPUS > 2 <<
130 select CRC32 <<
131 select DCACHE_WORD_ACCESS <<
132 select DYNAMIC_FTRACE if FUNCTION_TRAC <<
133 select DMA_BOUNCE_UNALIGNED_KMALLOC <<
134 select DMA_DIRECT_REMAP <<
135 select EDAC_SUPPORT <<
136 select FRAME_POINTER <<
137 select FUNCTION_ALIGNMENT_4B <<
138 select FUNCTION_ALIGNMENT_8B if DYNAMI <<
139 select GENERIC_ALLOCATOR <<
140 select GENERIC_ARCH_TOPOLOGY <<
141 select GENERIC_CLOCKEVENTS_BROADCAST <<
142 select GENERIC_CPU_AUTOPROBE <<
143 select GENERIC_CPU_DEVICES <<
144 select GENERIC_CPU_VULNERABILITIES <<
145 select GENERIC_EARLY_IOREMAP <<
146 select GENERIC_IDLE_POLL_SETUP <<
147 select GENERIC_IOREMAP <<
148 select GENERIC_IRQ_IPI <<
149 select GENERIC_IRQ_PROBE <<
150 select GENERIC_IRQ_SHOW <<
151 select GENERIC_IRQ_SHOW_LEVEL <<
152 select GENERIC_LIB_DEVMEM_IS_ALLOWED <<
153 select GENERIC_PCI_IOMAP <<
154 select GENERIC_PTDUMP <<
155 select GENERIC_SCHED_CLOCK <<
156 select GENERIC_SMP_IDLE_THREAD <<
157 select GENERIC_TIME_VSYSCALL <<
158 select GENERIC_GETTIMEOFDAY <<
159 select GENERIC_VDSO_TIME_NS <<
160 select HARDIRQS_SW_RESEND <<
161 select HAS_IOPORT <<
162 select HAVE_MOVE_PMD <<
163 select HAVE_MOVE_PUD <<
164 select HAVE_PCI <<
165 select HAVE_ACPI_APEI if (ACPI && EFI) <<
166 select HAVE_ALIGNED_STRUCT_PAGE <<
167 select HAVE_ARCH_AUDITSYSCALL <<
168 select HAVE_ARCH_BITREVERSE <<
169 select HAVE_ARCH_COMPILER_H <<
170 select HAVE_ARCH_HUGE_VMALLOC <<
171 select HAVE_ARCH_HUGE_VMAP <<
172 select HAVE_ARCH_JUMP_LABEL <<
173 select HAVE_ARCH_JUMP_LABEL_RELATIVE <<
174 select HAVE_ARCH_KASAN <<
175 select HAVE_ARCH_KASAN_VMALLOC <<
176 select HAVE_ARCH_KASAN_SW_TAGS <<
177 select HAVE_ARCH_KASAN_HW_TAGS if ARM6 <<
178 # Some instrumentation may be unsound, <<
179 select HAVE_ARCH_KCSAN if EXPERT <<
180 select HAVE_ARCH_KFENCE <<
181 select HAVE_ARCH_KGDB 16 select HAVE_ARCH_KGDB
182 select HAVE_ARCH_MMAP_RND_BITS <<
183 select HAVE_ARCH_MMAP_RND_COMPAT_BITS <<
184 select HAVE_ARCH_PREL32_RELOCATIONS <<
185 select HAVE_ARCH_RANDOMIZE_KSTACK_OFFS <<
186 select HAVE_ARCH_SECCOMP_FILTER 17 select HAVE_ARCH_SECCOMP_FILTER
187 select HAVE_ARCH_STACKLEAK <<
188 select HAVE_ARCH_THREAD_STRUCT_WHITELI <<
189 select HAVE_ARCH_TRACEHOOK 18 select HAVE_ARCH_TRACEHOOK
190 select HAVE_ARCH_TRANSPARENT_HUGEPAGE !! 19 select HAVE_CBPF_JIT if !CPU_MICROMIPS
191 select HAVE_ARCH_VMAP_STACK !! 20 select HAVE_FUNCTION_TRACER
192 select HAVE_ARM_SMCCC <<
193 select HAVE_ASM_MODVERSIONS <<
194 select HAVE_EBPF_JIT <<
195 select HAVE_C_RECORDMCOUNT <<
196 select HAVE_CMPXCHG_DOUBLE <<
197 select HAVE_CMPXCHG_LOCAL <<
198 select HAVE_CONTEXT_TRACKING_USER <<
199 select HAVE_DEBUG_KMEMLEAK <<
200 select HAVE_DMA_CONTIGUOUS <<
201 select HAVE_DYNAMIC_FTRACE 21 select HAVE_DYNAMIC_FTRACE
202 select HAVE_DYNAMIC_FTRACE_WITH_ARGS \ <<
203 if (GCC_SUPPORTS_DYNAMIC_FTRAC <<
204 CLANG_SUPPORTS_DYNAMIC_FTR <<
205 select HAVE_DYNAMIC_FTRACE_WITH_DIRECT <<
206 if DYNAMIC_FTRACE_WITH_ARGS && <<
207 select HAVE_DYNAMIC_FTRACE_WITH_CALL_O <<
208 if (DYNAMIC_FTRACE_WITH_ARGS & <<
209 (CC_IS_CLANG || !CC_OPTIMI <<
210 select FTRACE_MCOUNT_USE_PATCHABLE_FUN <<
211 if DYNAMIC_FTRACE_WITH_ARGS <<
212 select HAVE_SAMPLE_FTRACE_DIRECT <<
213 select HAVE_SAMPLE_FTRACE_DIRECT_MULTI <<
214 select HAVE_EFFICIENT_UNALIGNED_ACCESS <<
215 select HAVE_GUP_FAST <<
216 select HAVE_FTRACE_MCOUNT_RECORD 22 select HAVE_FTRACE_MCOUNT_RECORD
217 select HAVE_FUNCTION_TRACER !! 23 select HAVE_C_RECORDMCOUNT
218 select HAVE_FUNCTION_ERROR_INJECTION <<
219 select HAVE_FUNCTION_GRAPH_TRACER 24 select HAVE_FUNCTION_GRAPH_TRACER
220 select HAVE_FUNCTION_GRAPH_RETVAL <<
221 select HAVE_GCC_PLUGINS <<
222 select HAVE_HARDLOCKUP_DETECTOR_PERF i <<
223 HW_PERF_EVENTS && HAVE_PERF_EV <<
224 select HAVE_HW_BREAKPOINT if PERF_EVEN <<
225 select HAVE_IOREMAP_PROT <<
226 select HAVE_IRQ_TIME_ACCOUNTING <<
227 select HAVE_MOD_ARCH_SPECIFIC <<
228 select HAVE_NMI <<
229 select HAVE_PERF_EVENTS <<
230 select HAVE_PERF_EVENTS_NMI if ARM64_P <<
231 select HAVE_PERF_REGS <<
232 select HAVE_PERF_USER_STACK_DUMP <<
233 select HAVE_PREEMPT_DYNAMIC_KEY <<
234 select HAVE_REGS_AND_STACK_ACCESS_API <<
235 select HAVE_POSIX_CPU_TIMERS_TASK_WORK <<
236 select HAVE_FUNCTION_ARG_ACCESS_API <<
237 select MMU_GATHER_RCU_TABLE_FREE <<
238 select HAVE_RSEQ <<
239 select HAVE_RUST if RUSTC_SUPPORTS_ARM <<
240 select HAVE_STACKPROTECTOR <<
241 select HAVE_SYSCALL_TRACEPOINTS <<
242 select HAVE_KPROBES 25 select HAVE_KPROBES
243 select HAVE_KRETPROBES 26 select HAVE_KRETPROBES
244 select HAVE_GENERIC_VDSO !! 27 select HAVE_SYSCALL_TRACEPOINTS
245 select HOTPLUG_CORE_SYNC_DEAD if HOTPL !! 28 select HAVE_DEBUG_KMEMLEAK
246 select IRQ_DOMAIN !! 29 select HAVE_SYSCALL_TRACEPOINTS
>> 30 select ARCH_HAS_ELF_RANDOMIZE
>> 31 select HAVE_ARCH_TRANSPARENT_HUGEPAGE if CPU_SUPPORTS_HUGEPAGES && 64BIT
>> 32 select RTC_LIB if !MACH_LOONGSON64
>> 33 select GENERIC_ATOMIC64 if !64BIT
>> 34 select HAVE_DMA_CONTIGUOUS
>> 35 select HAVE_DMA_API_DEBUG
>> 36 select GENERIC_IRQ_PROBE
>> 37 select GENERIC_IRQ_SHOW
>> 38 select GENERIC_PCI_IOMAP
>> 39 select HAVE_ARCH_JUMP_LABEL
>> 40 select ARCH_WANT_IPC_PARSE_VERSION
247 select IRQ_FORCED_THREADING 41 select IRQ_FORCED_THREADING
248 select KASAN_VMALLOC if KASAN !! 42 select HAVE_MEMBLOCK
249 select LOCK_MM_AND_FIND_VMA !! 43 select HAVE_MEMBLOCK_NODE_MAP
250 select MODULES_USE_ELF_RELA !! 44 select ARCH_DISCARD_MEMBLOCK
251 select NEED_DMA_MAP_STATE !! 45 select GENERIC_SMP_IDLE_THREAD
252 select NEED_SG_DMA_LENGTH !! 46 select BUILDTIME_EXTABLE_SORT
253 select OF !! 47 select GENERIC_CLOCKEVENTS
254 select OF_EARLY_FLATTREE !! 48 select GENERIC_SCHED_CLOCK if !CAVIUM_OCTEON_SOC
255 select PCI_DOMAINS_GENERIC if PCI !! 49 select GENERIC_CMOS_UPDATE
256 select PCI_ECAM if (ACPI && PCI) !! 50 select HAVE_MOD_ARCH_SPECIFIC
257 select PCI_SYSCALL if PCI !! 51 select HAVE_NMI
258 select POWER_RESET !! 52 select VIRT_TO_BUS
259 select POWER_SUPPLY !! 53 select MODULES_USE_ELF_REL if MODULES
260 select SPARSE_IRQ !! 54 select MODULES_USE_ELF_RELA if MODULES && 64BIT
261 select SWIOTLB !! 55 select CLONE_BACKWARDS
>> 56 select HAVE_DEBUG_STACKOVERFLOW
>> 57 select HAVE_CC_STACKPROTECTOR
>> 58 select CPU_PM if CPU_IDLE
>> 59 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
>> 60 select ARCH_BINFMT_ELF_STATE
262 select SYSCTL_EXCEPTION_TRACE 61 select SYSCTL_EXCEPTION_TRACE
263 select THREAD_INFO_IN_TASK !! 62 select HAVE_VIRT_CPU_ACCOUNTING_GEN
264 select HAVE_ARCH_USERFAULTFD_MINOR if !! 63 select HAVE_IRQ_TIME_ACCOUNTING
265 select HAVE_ARCH_USERFAULTFD_WP if USE !! 64 select GENERIC_TIME_VSYSCALL
266 select TRACE_IRQFLAGS_SUPPORT !! 65 select ARCH_CLOCKSOURCE_DATA
267 select TRACE_IRQFLAGS_NMI_SUPPORT !! 66 select HANDLE_DOMAIN_IRQ
268 select HAVE_SOFTIRQ_ON_OWN_STACK !! 67 select HAVE_EXIT_THREAD
269 select USER_STACKTRACE_SUPPORT !! 68 select HAVE_REGS_AND_STACK_ACCESS_API
270 select VDSO_GETRANDOM !! 69 select HAVE_ARCH_HARDENED_USERCOPY
271 help <<
272 ARM 64-bit (AArch64) Linux support. <<
273 <<
274 config RUSTC_SUPPORTS_ARM64 <<
275 def_bool y <<
276 depends on CPU_LITTLE_ENDIAN <<
277 # Shadow call stack is only supported <<
278 # <<
279 # When using the UNWIND_PATCH_PAC_INTO <<
280 # required due to use of the -Zfixed-x <<
281 # <<
282 # Otherwise, rustc version 1.82+ is re <<
283 # -Zsanitizer=shadow-call-stack flag. <<
284 depends on !SHADOW_CALL_STACK || RUSTC <<
285 <<
286 config CLANG_SUPPORTS_DYNAMIC_FTRACE_WITH_ARGS <<
287 def_bool CC_IS_CLANG <<
288 # https://github.com/ClangBuiltLinux/l <<
289 depends on AS_IS_GNU || (AS_IS_LLVM && <<
290 <<
291 config GCC_SUPPORTS_DYNAMIC_FTRACE_WITH_ARGS <<
292 def_bool CC_IS_GCC <<
293 depends on $(cc-option,-fpatchable-fun <<
294 <<
295 config 64BIT <<
296 def_bool y <<
297 <<
298 config MMU <<
299 def_bool y <<
300 <<
301 config ARM64_CONT_PTE_SHIFT <<
302 int <<
303 default 5 if PAGE_SIZE_64KB <<
304 default 7 if PAGE_SIZE_16KB <<
305 default 4 <<
306 <<
307 config ARM64_CONT_PMD_SHIFT <<
308 int <<
309 default 5 if PAGE_SIZE_64KB <<
310 default 5 if PAGE_SIZE_16KB <<
311 default 4 <<
312 <<
313 config ARCH_MMAP_RND_BITS_MIN <<
314 default 14 if PAGE_SIZE_64KB <<
315 default 16 if PAGE_SIZE_16KB <<
316 default 18 <<
317 <<
318 # max bits determined by the following formula <<
319 # VA_BITS - PAGE_SHIFT - 3 <<
320 config ARCH_MMAP_RND_BITS_MAX <<
321 default 19 if ARM64_VA_BITS=36 <<
322 default 24 if ARM64_VA_BITS=39 <<
323 default 27 if ARM64_VA_BITS=42 <<
324 default 30 if ARM64_VA_BITS=47 <<
325 default 29 if ARM64_VA_BITS=48 && ARM6 <<
326 default 31 if ARM64_VA_BITS=48 && ARM6 <<
327 default 33 if ARM64_VA_BITS=48 <<
328 default 14 if ARM64_64K_PAGES <<
329 default 16 if ARM64_16K_PAGES <<
330 default 18 <<
331 <<
332 config ARCH_MMAP_RND_COMPAT_BITS_MIN <<
333 default 7 if ARM64_64K_PAGES <<
334 default 9 if ARM64_16K_PAGES <<
335 default 11 <<
336 <<
337 config ARCH_MMAP_RND_COMPAT_BITS_MAX <<
338 default 16 <<
339 <<
340 config NO_IOPORT_MAP <<
341 def_bool y if !PCI <<
342 <<
343 config STACKTRACE_SUPPORT <<
344 def_bool y <<
345 <<
346 config ILLEGAL_POINTER_VALUE <<
347 hex <<
348 default 0xdead000000000000 <<
349 70
350 config LOCKDEP_SUPPORT !! 71 menu "Machine selection"
351 def_bool y <<
352 72
353 config GENERIC_BUG !! 73 choice
354 def_bool y !! 74 prompt "System type"
355 depends on BUG !! 75 default SGI_IP22
356 <<
357 config GENERIC_BUG_RELATIVE_POINTERS <<
358 def_bool y <<
359 depends on GENERIC_BUG <<
360 76
361 config GENERIC_HWEIGHT !! 77 config MIPS_GENERIC
362 def_bool y !! 78 bool "Generic board-agnostic MIPS kernel"
>> 79 select BOOT_RAW
>> 80 select BUILTIN_DTB
>> 81 select CEVT_R4K
>> 82 select CLKSRC_MIPS_GIC
>> 83 select COMMON_CLK
>> 84 select CPU_MIPSR2_IRQ_VI
>> 85 select CPU_MIPSR2_IRQ_EI
>> 86 select CSRC_R4K
>> 87 select DMA_PERDEV_COHERENT
>> 88 select HW_HAS_PCI
>> 89 select IRQ_MIPS_CPU
>> 90 select LIBFDT
>> 91 select MIPS_CPU_SCACHE
>> 92 select MIPS_GIC
>> 93 select MIPS_L1_CACHE_SHIFT_7
>> 94 select NO_EXCEPT_FILL
>> 95 select PCI_DRIVERS_GENERIC
>> 96 select PINCTRL
>> 97 select SMP_UP if SMP
>> 98 select SYS_HAS_CPU_MIPS32_R1
>> 99 select SYS_HAS_CPU_MIPS32_R2
>> 100 select SYS_HAS_CPU_MIPS32_R6
>> 101 select SYS_HAS_CPU_MIPS64_R1
>> 102 select SYS_HAS_CPU_MIPS64_R2
>> 103 select SYS_HAS_CPU_MIPS64_R6
>> 104 select SYS_SUPPORTS_32BIT_KERNEL
>> 105 select SYS_SUPPORTS_64BIT_KERNEL
>> 106 select SYS_SUPPORTS_BIG_ENDIAN
>> 107 select SYS_SUPPORTS_HIGHMEM
>> 108 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 109 select SYS_SUPPORTS_MICROMIPS
>> 110 select SYS_SUPPORTS_MIPS_CPS
>> 111 select SYS_SUPPORTS_MIPS16
>> 112 select SYS_SUPPORTS_MULTITHREADING
>> 113 select SYS_SUPPORTS_RELOCATABLE
>> 114 select SYS_SUPPORTS_SMARTMIPS
>> 115 select USB_EHCI_BIG_ENDIAN_DESC if BIG_ENDIAN
>> 116 select USB_EHCI_BIG_ENDIAN_MMIO if BIG_ENDIAN
>> 117 select USB_OHCI_BIG_ENDIAN_DESC if BIG_ENDIAN
>> 118 select USB_OHCI_BIG_ENDIAN_MMIO if BIG_ENDIAN
>> 119 select USB_UHCI_BIG_ENDIAN_DESC if BIG_ENDIAN
>> 120 select USB_UHCI_BIG_ENDIAN_MMIO if BIG_ENDIAN
>> 121 select USE_OF
>> 122 help
>> 123 Select this to build a kernel which aims to support multiple boards,
>> 124 generally using a flattened device tree passed from the bootloader
>> 125 using the boot protocol defined in the UHI (Unified Hosting
>> 126 Interface) specification.
>> 127
>> 128 config MIPS_ALCHEMY
>> 129 bool "Alchemy processor based machines"
>> 130 select ARCH_PHYS_ADDR_T_64BIT
>> 131 select CEVT_R4K
>> 132 select CSRC_R4K
>> 133 select IRQ_MIPS_CPU
>> 134 select DMA_MAYBE_COHERENT # Au1000,1500,1100 aren't, rest is
>> 135 select SYS_HAS_CPU_MIPS32_R1
>> 136 select SYS_SUPPORTS_32BIT_KERNEL
>> 137 select SYS_SUPPORTS_APM_EMULATION
>> 138 select GPIOLIB
>> 139 select SYS_SUPPORTS_ZBOOT
>> 140 select COMMON_CLK
363 141
364 config GENERIC_CSUM !! 142 config AR7
365 def_bool y !! 143 bool "Texas Instruments AR7"
>> 144 select BOOT_ELF32
>> 145 select DMA_NONCOHERENT
>> 146 select CEVT_R4K
>> 147 select CSRC_R4K
>> 148 select IRQ_MIPS_CPU
>> 149 select NO_EXCEPT_FILL
>> 150 select SWAP_IO_SPACE
>> 151 select SYS_HAS_CPU_MIPS32_R1
>> 152 select SYS_HAS_EARLY_PRINTK
>> 153 select SYS_SUPPORTS_32BIT_KERNEL
>> 154 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 155 select SYS_SUPPORTS_MIPS16
>> 156 select SYS_SUPPORTS_ZBOOT_UART16550
>> 157 select GPIOLIB
>> 158 select VLYNQ
>> 159 select HAVE_CLK
>> 160 help
>> 161 Support for the Texas Instruments AR7 System-on-a-Chip
>> 162 family: TNETD7100, 7200 and 7300.
>> 163
>> 164 config ATH25
>> 165 bool "Atheros AR231x/AR531x SoC support"
>> 166 select CEVT_R4K
>> 167 select CSRC_R4K
>> 168 select DMA_NONCOHERENT
>> 169 select IRQ_MIPS_CPU
>> 170 select IRQ_DOMAIN
>> 171 select SYS_HAS_CPU_MIPS32_R1
>> 172 select SYS_SUPPORTS_BIG_ENDIAN
>> 173 select SYS_SUPPORTS_32BIT_KERNEL
>> 174 select SYS_HAS_EARLY_PRINTK
>> 175 help
>> 176 Support for Atheros AR231x and Atheros AR531x based boards
>> 177
>> 178 config ATH79
>> 179 bool "Atheros AR71XX/AR724X/AR913X based boards"
>> 180 select ARCH_HAS_RESET_CONTROLLER
>> 181 select BOOT_RAW
>> 182 select CEVT_R4K
>> 183 select CSRC_R4K
>> 184 select DMA_NONCOHERENT
>> 185 select GPIOLIB
>> 186 select HAVE_CLK
>> 187 select COMMON_CLK
>> 188 select CLKDEV_LOOKUP
>> 189 select IRQ_MIPS_CPU
>> 190 select MIPS_MACHINE
>> 191 select SYS_HAS_CPU_MIPS32_R2
>> 192 select SYS_HAS_EARLY_PRINTK
>> 193 select SYS_SUPPORTS_32BIT_KERNEL
>> 194 select SYS_SUPPORTS_BIG_ENDIAN
>> 195 select SYS_SUPPORTS_MIPS16
>> 196 select SYS_SUPPORTS_ZBOOT_UART_PROM
>> 197 select USE_OF
>> 198 help
>> 199 Support for the Atheros AR71XX/AR724X/AR913X SoCs.
>> 200
>> 201 config BMIPS_GENERIC
>> 202 bool "Broadcom Generic BMIPS kernel"
>> 203 select BOOT_RAW
>> 204 select NO_EXCEPT_FILL
>> 205 select USE_OF
>> 206 select CEVT_R4K
>> 207 select CSRC_R4K
>> 208 select SYNC_R4K
>> 209 select COMMON_CLK
>> 210 select BCM6345_L1_IRQ
>> 211 select BCM7038_L1_IRQ
>> 212 select BCM7120_L2_IRQ
>> 213 select BRCMSTB_L2_IRQ
>> 214 select IRQ_MIPS_CPU
>> 215 select DMA_NONCOHERENT
>> 216 select SYS_SUPPORTS_32BIT_KERNEL
>> 217 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 218 select SYS_SUPPORTS_BIG_ENDIAN
>> 219 select SYS_SUPPORTS_HIGHMEM
>> 220 select SYS_HAS_CPU_BMIPS32_3300
>> 221 select SYS_HAS_CPU_BMIPS4350
>> 222 select SYS_HAS_CPU_BMIPS4380
>> 223 select SYS_HAS_CPU_BMIPS5000
>> 224 select SWAP_IO_SPACE
>> 225 select USB_EHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
>> 226 select USB_EHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 227 select USB_OHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
>> 228 select USB_OHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 229 help
>> 230 Build a generic DT-based kernel image that boots on select
>> 231 BCM33xx cable modem chips, BCM63xx DSL chips, and BCM7xxx set-top
>> 232 box chips. Note that CONFIG_CPU_BIG_ENDIAN/CONFIG_CPU_LITTLE_ENDIAN
>> 233 must be set appropriately for your board.
>> 234
>> 235 config BCM47XX
>> 236 bool "Broadcom BCM47XX based boards"
>> 237 select BOOT_RAW
>> 238 select CEVT_R4K
>> 239 select CSRC_R4K
>> 240 select DMA_NONCOHERENT
>> 241 select HW_HAS_PCI
>> 242 select IRQ_MIPS_CPU
>> 243 select SYS_HAS_CPU_MIPS32_R1
>> 244 select NO_EXCEPT_FILL
>> 245 select SYS_SUPPORTS_32BIT_KERNEL
>> 246 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 247 select SYS_SUPPORTS_MIPS16
>> 248 select SYS_HAS_EARLY_PRINTK
>> 249 select USE_GENERIC_EARLY_PRINTK_8250
>> 250 select GPIOLIB
>> 251 select LEDS_GPIO_REGISTER
>> 252 select BCM47XX_NVRAM
>> 253 select BCM47XX_SPROM
>> 254 help
>> 255 Support for BCM47XX based boards
>> 256
>> 257 config BCM63XX
>> 258 bool "Broadcom BCM63XX based boards"
>> 259 select BOOT_RAW
>> 260 select CEVT_R4K
>> 261 select CSRC_R4K
>> 262 select SYNC_R4K
>> 263 select DMA_NONCOHERENT
>> 264 select IRQ_MIPS_CPU
>> 265 select SYS_SUPPORTS_32BIT_KERNEL
>> 266 select SYS_SUPPORTS_BIG_ENDIAN
>> 267 select SYS_HAS_EARLY_PRINTK
>> 268 select SWAP_IO_SPACE
>> 269 select GPIOLIB
>> 270 select HAVE_CLK
>> 271 select MIPS_L1_CACHE_SHIFT_4
>> 272 help
>> 273 Support for BCM63XX based boards
>> 274
>> 275 config MIPS_COBALT
>> 276 bool "Cobalt Server"
>> 277 select CEVT_R4K
>> 278 select CSRC_R4K
>> 279 select CEVT_GT641XX
>> 280 select DMA_NONCOHERENT
>> 281 select HW_HAS_PCI
>> 282 select I8253
>> 283 select I8259
>> 284 select IRQ_MIPS_CPU
>> 285 select IRQ_GT641XX
>> 286 select PCI_GT64XXX_PCI0
>> 287 select PCI
>> 288 select SYS_HAS_CPU_NEVADA
>> 289 select SYS_HAS_EARLY_PRINTK
>> 290 select SYS_SUPPORTS_32BIT_KERNEL
>> 291 select SYS_SUPPORTS_64BIT_KERNEL
>> 292 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 293 select USE_GENERIC_EARLY_PRINTK_8250
>> 294
>> 295 config MACH_DECSTATION
>> 296 bool "DECstations"
>> 297 select BOOT_ELF32
>> 298 select CEVT_DS1287
>> 299 select CEVT_R4K if CPU_R4X00
>> 300 select CSRC_IOASIC
>> 301 select CSRC_R4K if CPU_R4X00
>> 302 select CPU_DADDI_WORKAROUNDS if 64BIT
>> 303 select CPU_R4000_WORKAROUNDS if 64BIT
>> 304 select CPU_R4400_WORKAROUNDS if 64BIT
>> 305 select DMA_NONCOHERENT
>> 306 select NO_IOPORT_MAP
>> 307 select IRQ_MIPS_CPU
>> 308 select SYS_HAS_CPU_R3000
>> 309 select SYS_HAS_CPU_R4X00
>> 310 select SYS_SUPPORTS_32BIT_KERNEL
>> 311 select SYS_SUPPORTS_64BIT_KERNEL
>> 312 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 313 select SYS_SUPPORTS_128HZ
>> 314 select SYS_SUPPORTS_256HZ
>> 315 select SYS_SUPPORTS_1024HZ
>> 316 select MIPS_L1_CACHE_SHIFT_4
>> 317 help
>> 318 This enables support for DEC's MIPS based workstations. For details
>> 319 see the Linux/MIPS FAQ on <http://www.linux-mips.org/> and the
>> 320 DECstation porting pages on <http://decstation.unix-ag.org/>.
>> 321
>> 322 If you have one of the following DECstation Models you definitely
>> 323 want to choose R4xx0 for the CPU Type:
>> 324
>> 325 DECstation 5000/50
>> 326 DECstation 5000/150
>> 327 DECstation 5000/260
>> 328 DECsystem 5900/260
>> 329
>> 330 otherwise choose R3000.
>> 331
>> 332 config MACH_JAZZ
>> 333 bool "Jazz family of machines"
>> 334 select FW_ARC
>> 335 select FW_ARC32
>> 336 select ARCH_MAY_HAVE_PC_FDC
>> 337 select CEVT_R4K
>> 338 select CSRC_R4K
>> 339 select DEFAULT_SGI_PARTITION if CPU_BIG_ENDIAN
>> 340 select GENERIC_ISA_DMA
>> 341 select HAVE_PCSPKR_PLATFORM
>> 342 select IRQ_MIPS_CPU
>> 343 select I8253
>> 344 select I8259
>> 345 select ISA
>> 346 select SYS_HAS_CPU_R4X00
>> 347 select SYS_SUPPORTS_32BIT_KERNEL
>> 348 select SYS_SUPPORTS_64BIT_KERNEL
>> 349 select SYS_SUPPORTS_100HZ
>> 350 help
>> 351 This a family of machines based on the MIPS R4030 chipset which was
>> 352 used by several vendors to build RISC/os and Windows NT workstations.
>> 353 Members include the Acer PICA, MIPS Magnum 4000, MIPS Millennium and
>> 354 Olivetti M700-10 workstations.
>> 355
>> 356 config MACH_INGENIC
>> 357 bool "Ingenic SoC based machines"
>> 358 select SYS_SUPPORTS_32BIT_KERNEL
>> 359 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 360 select SYS_SUPPORTS_ZBOOT_UART16550
>> 361 select DMA_NONCOHERENT
>> 362 select IRQ_MIPS_CPU
>> 363 select GPIOLIB
>> 364 select COMMON_CLK
>> 365 select GENERIC_IRQ_CHIP
>> 366 select BUILTIN_DTB
>> 367 select USE_OF
>> 368 select LIBFDT
366 369
367 config GENERIC_CALIBRATE_DELAY !! 370 config LANTIQ
368 def_bool y !! 371 bool "Lantiq based platforms"
>> 372 select DMA_NONCOHERENT
>> 373 select IRQ_MIPS_CPU
>> 374 select CEVT_R4K
>> 375 select CSRC_R4K
>> 376 select SYS_HAS_CPU_MIPS32_R1
>> 377 select SYS_HAS_CPU_MIPS32_R2
>> 378 select SYS_SUPPORTS_BIG_ENDIAN
>> 379 select SYS_SUPPORTS_32BIT_KERNEL
>> 380 select SYS_SUPPORTS_MIPS16
>> 381 select SYS_SUPPORTS_MULTITHREADING
>> 382 select SYS_HAS_EARLY_PRINTK
>> 383 select GPIOLIB
>> 384 select SWAP_IO_SPACE
>> 385 select BOOT_RAW
>> 386 select CLKDEV_LOOKUP
>> 387 select USE_OF
>> 388 select PINCTRL
>> 389 select PINCTRL_LANTIQ
>> 390 select ARCH_HAS_RESET_CONTROLLER
>> 391 select RESET_CONTROLLER
>> 392
>> 393 config LASAT
>> 394 bool "LASAT Networks platforms"
>> 395 select CEVT_R4K
>> 396 select CRC32
>> 397 select CSRC_R4K
>> 398 select DMA_NONCOHERENT
>> 399 select SYS_HAS_EARLY_PRINTK
>> 400 select HW_HAS_PCI
>> 401 select IRQ_MIPS_CPU
>> 402 select PCI_GT64XXX_PCI0
>> 403 select MIPS_NILE4
>> 404 select R5000_CPU_SCACHE
>> 405 select SYS_HAS_CPU_R5000
>> 406 select SYS_SUPPORTS_32BIT_KERNEL
>> 407 select SYS_SUPPORTS_64BIT_KERNEL if BROKEN
>> 408 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 409
>> 410 config MACH_LOONGSON32
>> 411 bool "Loongson-1 family of machines"
>> 412 select SYS_SUPPORTS_ZBOOT
>> 413 help
>> 414 This enables support for the Loongson-1 family of machines.
>> 415
>> 416 Loongson-1 is a family of 32-bit MIPS-compatible SoCs developed by
>> 417 the Institute of Computing Technology (ICT), Chinese Academy of
>> 418 Sciences (CAS).
>> 419
>> 420 config MACH_LOONGSON64
>> 421 bool "Loongson-2/3 family of machines"
>> 422 select SYS_SUPPORTS_ZBOOT
>> 423 help
>> 424 This enables the support of Loongson-2/3 family of machines.
>> 425
>> 426 Loongson-2 is a family of single-core CPUs and Loongson-3 is a
>> 427 family of multi-core CPUs. They are both 64-bit general-purpose
>> 428 MIPS-compatible CPUs. Loongson-2/3 are developed by the Institute
>> 429 of Computing Technology (ICT), Chinese Academy of Sciences (CAS)
>> 430 in the People's Republic of China. The chief architect is Professor
>> 431 Weiwu Hu.
>> 432
>> 433 config MACH_PISTACHIO
>> 434 bool "IMG Pistachio SoC based boards"
>> 435 select BOOT_ELF32
>> 436 select BOOT_RAW
>> 437 select CEVT_R4K
>> 438 select CLKSRC_MIPS_GIC
>> 439 select COMMON_CLK
>> 440 select CSRC_R4K
>> 441 select DMA_NONCOHERENT
>> 442 select GPIOLIB
>> 443 select IRQ_MIPS_CPU
>> 444 select LIBFDT
>> 445 select MFD_SYSCON
>> 446 select MIPS_CPU_SCACHE
>> 447 select MIPS_GIC
>> 448 select PINCTRL
>> 449 select REGULATOR
>> 450 select SYS_HAS_CPU_MIPS32_R2
>> 451 select SYS_SUPPORTS_32BIT_KERNEL
>> 452 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 453 select SYS_SUPPORTS_MIPS_CPS
>> 454 select SYS_SUPPORTS_MULTITHREADING
>> 455 select SYS_SUPPORTS_RELOCATABLE
>> 456 select SYS_SUPPORTS_ZBOOT
>> 457 select SYS_HAS_EARLY_PRINTK
>> 458 select USE_GENERIC_EARLY_PRINTK_8250
>> 459 select USE_OF
>> 460 help
>> 461 This enables support for the IMG Pistachio SoC platform.
>> 462
>> 463 config MACH_XILFPGA
>> 464 bool "MIPSfpga Xilinx based boards"
>> 465 select BOOT_ELF32
>> 466 select BOOT_RAW
>> 467 select BUILTIN_DTB
>> 468 select CEVT_R4K
>> 469 select COMMON_CLK
>> 470 select CSRC_R4K
>> 471 select GPIOLIB
>> 472 select IRQ_MIPS_CPU
>> 473 select LIBFDT
>> 474 select MIPS_CPU_SCACHE
>> 475 select SYS_HAS_EARLY_PRINTK
>> 476 select SYS_HAS_CPU_MIPS32_R2
>> 477 select SYS_SUPPORTS_32BIT_KERNEL
>> 478 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 479 select SYS_SUPPORTS_ZBOOT_UART16550
>> 480 select USE_OF
>> 481 select USE_GENERIC_EARLY_PRINTK_8250
>> 482 help
>> 483 This enables support for the IMG University Program MIPSfpga platform.
>> 484
>> 485 config MIPS_MALTA
>> 486 bool "MIPS Malta board"
>> 487 select ARCH_MAY_HAVE_PC_FDC
>> 488 select BOOT_ELF32
>> 489 select BOOT_RAW
>> 490 select BUILTIN_DTB
>> 491 select CEVT_R4K
>> 492 select CSRC_R4K
>> 493 select CLKSRC_MIPS_GIC
>> 494 select COMMON_CLK
>> 495 select DMA_MAYBE_COHERENT
>> 496 select GENERIC_ISA_DMA
>> 497 select HAVE_PCSPKR_PLATFORM
>> 498 select IRQ_MIPS_CPU
>> 499 select MIPS_GIC
>> 500 select HW_HAS_PCI
>> 501 select I8253
>> 502 select I8259
>> 503 select MIPS_BONITO64
>> 504 select MIPS_CPU_SCACHE
>> 505 select MIPS_L1_CACHE_SHIFT_6
>> 506 select PCI_GT64XXX_PCI0
>> 507 select MIPS_MSC
>> 508 select SMP_UP if SMP
>> 509 select SWAP_IO_SPACE
>> 510 select SYS_HAS_CPU_MIPS32_R1
>> 511 select SYS_HAS_CPU_MIPS32_R2
>> 512 select SYS_HAS_CPU_MIPS32_R3_5
>> 513 select SYS_HAS_CPU_MIPS32_R5
>> 514 select SYS_HAS_CPU_MIPS32_R6
>> 515 select SYS_HAS_CPU_MIPS64_R1
>> 516 select SYS_HAS_CPU_MIPS64_R2
>> 517 select SYS_HAS_CPU_MIPS64_R6
>> 518 select SYS_HAS_CPU_NEVADA
>> 519 select SYS_HAS_CPU_RM7000
>> 520 select SYS_SUPPORTS_32BIT_KERNEL
>> 521 select SYS_SUPPORTS_64BIT_KERNEL
>> 522 select SYS_SUPPORTS_BIG_ENDIAN
>> 523 select SYS_SUPPORTS_HIGHMEM
>> 524 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 525 select SYS_SUPPORTS_MICROMIPS
>> 526 select SYS_SUPPORTS_MIPS_CMP
>> 527 select SYS_SUPPORTS_MIPS_CPS
>> 528 select SYS_SUPPORTS_MIPS16
>> 529 select SYS_SUPPORTS_MULTITHREADING
>> 530 select SYS_SUPPORTS_SMARTMIPS
>> 531 select SYS_SUPPORTS_ZBOOT
>> 532 select SYS_SUPPORTS_RELOCATABLE
>> 533 select USE_OF
>> 534 select LIBFDT
>> 535 select ZONE_DMA32 if 64BIT
>> 536 select BUILTIN_DTB
>> 537 select LIBFDT
>> 538 help
>> 539 This enables support for the MIPS Technologies Malta evaluation
>> 540 board.
369 541
370 config SMP !! 542 config MACH_PIC32
371 def_bool y !! 543 bool "Microchip PIC32 Family"
>> 544 help
>> 545 This enables support for the Microchip PIC32 family of platforms.
372 546
373 config KERNEL_MODE_NEON !! 547 Microchip PIC32 is a family of general-purpose 32 bit MIPS core
374 def_bool y !! 548 microcontrollers.
>> 549
>> 550 config NEC_MARKEINS
>> 551 bool "NEC EMMA2RH Mark-eins board"
>> 552 select SOC_EMMA2RH
>> 553 select HW_HAS_PCI
>> 554 help
>> 555 This enables support for the NEC Electronics Mark-eins boards.
>> 556
>> 557 config MACH_VR41XX
>> 558 bool "NEC VR4100 series based machines"
>> 559 select CEVT_R4K
>> 560 select CSRC_R4K
>> 561 select SYS_HAS_CPU_VR41XX
>> 562 select SYS_SUPPORTS_MIPS16
>> 563 select GPIOLIB
>> 564
>> 565 config NXP_STB220
>> 566 bool "NXP STB220 board"
>> 567 select SOC_PNX833X
>> 568 help
>> 569 Support for NXP Semiconductors STB220 Development Board.
>> 570
>> 571 config NXP_STB225
>> 572 bool "NXP 225 board"
>> 573 select SOC_PNX833X
>> 574 select SOC_PNX8335
>> 575 help
>> 576 Support for NXP Semiconductors STB225 Development Board.
>> 577
>> 578 config PMC_MSP
>> 579 bool "PMC-Sierra MSP chipsets"
>> 580 select CEVT_R4K
>> 581 select CSRC_R4K
>> 582 select DMA_NONCOHERENT
>> 583 select SWAP_IO_SPACE
>> 584 select NO_EXCEPT_FILL
>> 585 select BOOT_RAW
>> 586 select SYS_HAS_CPU_MIPS32_R1
>> 587 select SYS_HAS_CPU_MIPS32_R2
>> 588 select SYS_SUPPORTS_32BIT_KERNEL
>> 589 select SYS_SUPPORTS_BIG_ENDIAN
>> 590 select SYS_SUPPORTS_MIPS16
>> 591 select IRQ_MIPS_CPU
>> 592 select SERIAL_8250
>> 593 select SERIAL_8250_CONSOLE
>> 594 select USB_EHCI_BIG_ENDIAN_MMIO
>> 595 select USB_EHCI_BIG_ENDIAN_DESC
>> 596 help
>> 597 This adds support for the PMC-Sierra family of Multi-Service
>> 598 Processor System-On-A-Chips. These parts include a number
>> 599 of integrated peripherals, interfaces and DSPs in addition to
>> 600 a variety of MIPS cores.
>> 601
>> 602 config RALINK
>> 603 bool "Ralink based machines"
>> 604 select CEVT_R4K
>> 605 select CSRC_R4K
>> 606 select BOOT_RAW
>> 607 select DMA_NONCOHERENT
>> 608 select IRQ_MIPS_CPU
>> 609 select USE_OF
>> 610 select SYS_HAS_CPU_MIPS32_R1
>> 611 select SYS_HAS_CPU_MIPS32_R2
>> 612 select SYS_SUPPORTS_32BIT_KERNEL
>> 613 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 614 select SYS_SUPPORTS_MIPS16
>> 615 select SYS_HAS_EARLY_PRINTK
>> 616 select CLKDEV_LOOKUP
>> 617 select ARCH_HAS_RESET_CONTROLLER
>> 618 select RESET_CONTROLLER
>> 619
>> 620 config SGI_IP22
>> 621 bool "SGI IP22 (Indy/Indigo2)"
>> 622 select FW_ARC
>> 623 select FW_ARC32
>> 624 select BOOT_ELF32
>> 625 select CEVT_R4K
>> 626 select CSRC_R4K
>> 627 select DEFAULT_SGI_PARTITION
>> 628 select DMA_NONCOHERENT
>> 629 select HW_HAS_EISA
>> 630 select I8253
>> 631 select I8259
>> 632 select IP22_CPU_SCACHE
>> 633 select IRQ_MIPS_CPU
>> 634 select GENERIC_ISA_DMA_SUPPORT_BROKEN
>> 635 select SGI_HAS_I8042
>> 636 select SGI_HAS_INDYDOG
>> 637 select SGI_HAS_HAL2
>> 638 select SGI_HAS_SEEQ
>> 639 select SGI_HAS_WD93
>> 640 select SGI_HAS_ZILOG
>> 641 select SWAP_IO_SPACE
>> 642 select SYS_HAS_CPU_R4X00
>> 643 select SYS_HAS_CPU_R5000
>> 644 #
>> 645 # Disable EARLY_PRINTK for now since it leads to overwritten prom
>> 646 # memory during early boot on some machines.
>> 647 #
>> 648 # See http://www.linux-mips.org/cgi-bin/mesg.cgi?a=linux-mips&i=20091119164009.GA15038%40deprecation.cyrius.com
>> 649 # for a more details discussion
>> 650 #
>> 651 # select SYS_HAS_EARLY_PRINTK
>> 652 select SYS_SUPPORTS_32BIT_KERNEL
>> 653 select SYS_SUPPORTS_64BIT_KERNEL
>> 654 select SYS_SUPPORTS_BIG_ENDIAN
>> 655 select MIPS_L1_CACHE_SHIFT_7
>> 656 help
>> 657 This are the SGI Indy, Challenge S and Indigo2, as well as certain
>> 658 OEM variants like the Tandem CMN B006S. To compile a Linux kernel
>> 659 that runs on these, say Y here.
>> 660
>> 661 config SGI_IP27
>> 662 bool "SGI IP27 (Origin200/2000)"
>> 663 select FW_ARC
>> 664 select FW_ARC64
>> 665 select BOOT_ELF64
>> 666 select DEFAULT_SGI_PARTITION
>> 667 select DMA_COHERENT
>> 668 select SYS_HAS_EARLY_PRINTK
>> 669 select HW_HAS_PCI
>> 670 select NR_CPUS_DEFAULT_64
>> 671 select SYS_HAS_CPU_R10000
>> 672 select SYS_SUPPORTS_64BIT_KERNEL
>> 673 select SYS_SUPPORTS_BIG_ENDIAN
>> 674 select SYS_SUPPORTS_NUMA
>> 675 select SYS_SUPPORTS_SMP
>> 676 select MIPS_L1_CACHE_SHIFT_7
>> 677 help
>> 678 This are the SGI Origin 200, Origin 2000 and Onyx 2 Graphics
>> 679 workstations. To compile a Linux kernel that runs on these, say Y
>> 680 here.
>> 681
>> 682 config SGI_IP28
>> 683 bool "SGI IP28 (Indigo2 R10k)"
>> 684 select FW_ARC
>> 685 select FW_ARC64
>> 686 select BOOT_ELF64
>> 687 select CEVT_R4K
>> 688 select CSRC_R4K
>> 689 select DEFAULT_SGI_PARTITION
>> 690 select DMA_NONCOHERENT
>> 691 select GENERIC_ISA_DMA_SUPPORT_BROKEN
>> 692 select IRQ_MIPS_CPU
>> 693 select HW_HAS_EISA
>> 694 select I8253
>> 695 select I8259
>> 696 select SGI_HAS_I8042
>> 697 select SGI_HAS_INDYDOG
>> 698 select SGI_HAS_HAL2
>> 699 select SGI_HAS_SEEQ
>> 700 select SGI_HAS_WD93
>> 701 select SGI_HAS_ZILOG
>> 702 select SWAP_IO_SPACE
>> 703 select SYS_HAS_CPU_R10000
>> 704 #
>> 705 # Disable EARLY_PRINTK for now since it leads to overwritten prom
>> 706 # memory during early boot on some machines.
>> 707 #
>> 708 # See http://www.linux-mips.org/cgi-bin/mesg.cgi?a=linux-mips&i=20091119164009.GA15038%40deprecation.cyrius.com
>> 709 # for a more details discussion
>> 710 #
>> 711 # select SYS_HAS_EARLY_PRINTK
>> 712 select SYS_SUPPORTS_64BIT_KERNEL
>> 713 select SYS_SUPPORTS_BIG_ENDIAN
>> 714 select MIPS_L1_CACHE_SHIFT_7
>> 715 help
>> 716 This is the SGI Indigo2 with R10000 processor. To compile a Linux
>> 717 kernel that runs on these, say Y here.
>> 718
>> 719 config SGI_IP32
>> 720 bool "SGI IP32 (O2)"
>> 721 select FW_ARC
>> 722 select FW_ARC32
>> 723 select BOOT_ELF32
>> 724 select CEVT_R4K
>> 725 select CSRC_R4K
>> 726 select DMA_NONCOHERENT
>> 727 select HW_HAS_PCI
>> 728 select IRQ_MIPS_CPU
>> 729 select R5000_CPU_SCACHE
>> 730 select RM7000_CPU_SCACHE
>> 731 select SYS_HAS_CPU_R5000
>> 732 select SYS_HAS_CPU_R10000 if BROKEN
>> 733 select SYS_HAS_CPU_RM7000
>> 734 select SYS_HAS_CPU_NEVADA
>> 735 select SYS_SUPPORTS_64BIT_KERNEL
>> 736 select SYS_SUPPORTS_BIG_ENDIAN
>> 737 help
>> 738 If you want this kernel to run on SGI O2 workstation, say Y here.
>> 739
>> 740 config SIBYTE_CRHINE
>> 741 bool "Sibyte BCM91120C-CRhine"
>> 742 select BOOT_ELF32
>> 743 select DMA_COHERENT
>> 744 select SIBYTE_BCM1120
>> 745 select SWAP_IO_SPACE
>> 746 select SYS_HAS_CPU_SB1
>> 747 select SYS_SUPPORTS_BIG_ENDIAN
>> 748 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 749
>> 750 config SIBYTE_CARMEL
>> 751 bool "Sibyte BCM91120x-Carmel"
>> 752 select BOOT_ELF32
>> 753 select DMA_COHERENT
>> 754 select SIBYTE_BCM1120
>> 755 select SWAP_IO_SPACE
>> 756 select SYS_HAS_CPU_SB1
>> 757 select SYS_SUPPORTS_BIG_ENDIAN
>> 758 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 759
>> 760 config SIBYTE_CRHONE
>> 761 bool "Sibyte BCM91125C-CRhone"
>> 762 select BOOT_ELF32
>> 763 select DMA_COHERENT
>> 764 select SIBYTE_BCM1125
>> 765 select SWAP_IO_SPACE
>> 766 select SYS_HAS_CPU_SB1
>> 767 select SYS_SUPPORTS_BIG_ENDIAN
>> 768 select SYS_SUPPORTS_HIGHMEM
>> 769 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 770
>> 771 config SIBYTE_RHONE
>> 772 bool "Sibyte BCM91125E-Rhone"
>> 773 select BOOT_ELF32
>> 774 select DMA_COHERENT
>> 775 select SIBYTE_BCM1125H
>> 776 select SWAP_IO_SPACE
>> 777 select SYS_HAS_CPU_SB1
>> 778 select SYS_SUPPORTS_BIG_ENDIAN
>> 779 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 780
>> 781 config SIBYTE_SWARM
>> 782 bool "Sibyte BCM91250A-SWARM"
>> 783 select BOOT_ELF32
>> 784 select DMA_COHERENT
>> 785 select HAVE_PATA_PLATFORM
>> 786 select SIBYTE_SB1250
>> 787 select SWAP_IO_SPACE
>> 788 select SYS_HAS_CPU_SB1
>> 789 select SYS_SUPPORTS_BIG_ENDIAN
>> 790 select SYS_SUPPORTS_HIGHMEM
>> 791 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 792 select ZONE_DMA32 if 64BIT
>> 793
>> 794 config SIBYTE_LITTLESUR
>> 795 bool "Sibyte BCM91250C2-LittleSur"
>> 796 select BOOT_ELF32
>> 797 select DMA_COHERENT
>> 798 select HAVE_PATA_PLATFORM
>> 799 select SIBYTE_SB1250
>> 800 select SWAP_IO_SPACE
>> 801 select SYS_HAS_CPU_SB1
>> 802 select SYS_SUPPORTS_BIG_ENDIAN
>> 803 select SYS_SUPPORTS_HIGHMEM
>> 804 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 805
>> 806 config SIBYTE_SENTOSA
>> 807 bool "Sibyte BCM91250E-Sentosa"
>> 808 select BOOT_ELF32
>> 809 select DMA_COHERENT
>> 810 select SIBYTE_SB1250
>> 811 select SWAP_IO_SPACE
>> 812 select SYS_HAS_CPU_SB1
>> 813 select SYS_SUPPORTS_BIG_ENDIAN
>> 814 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 815
>> 816 config SIBYTE_BIGSUR
>> 817 bool "Sibyte BCM91480B-BigSur"
>> 818 select BOOT_ELF32
>> 819 select DMA_COHERENT
>> 820 select NR_CPUS_DEFAULT_4
>> 821 select SIBYTE_BCM1x80
>> 822 select SWAP_IO_SPACE
>> 823 select SYS_HAS_CPU_SB1
>> 824 select SYS_SUPPORTS_BIG_ENDIAN
>> 825 select SYS_SUPPORTS_HIGHMEM
>> 826 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 827 select ZONE_DMA32 if 64BIT
>> 828
>> 829 config SNI_RM
>> 830 bool "SNI RM200/300/400"
>> 831 select FW_ARC if CPU_LITTLE_ENDIAN
>> 832 select FW_ARC32 if CPU_LITTLE_ENDIAN
>> 833 select FW_SNIPROM if CPU_BIG_ENDIAN
>> 834 select ARCH_MAY_HAVE_PC_FDC
>> 835 select BOOT_ELF32
>> 836 select CEVT_R4K
>> 837 select CSRC_R4K
>> 838 select DEFAULT_SGI_PARTITION if CPU_BIG_ENDIAN
>> 839 select DMA_NONCOHERENT
>> 840 select GENERIC_ISA_DMA
>> 841 select HAVE_PCSPKR_PLATFORM
>> 842 select HW_HAS_EISA
>> 843 select HW_HAS_PCI
>> 844 select IRQ_MIPS_CPU
>> 845 select I8253
>> 846 select I8259
>> 847 select ISA
>> 848 select SWAP_IO_SPACE if CPU_BIG_ENDIAN
>> 849 select SYS_HAS_CPU_R4X00
>> 850 select SYS_HAS_CPU_R5000
>> 851 select SYS_HAS_CPU_R10000
>> 852 select R5000_CPU_SCACHE
>> 853 select SYS_HAS_EARLY_PRINTK
>> 854 select SYS_SUPPORTS_32BIT_KERNEL
>> 855 select SYS_SUPPORTS_64BIT_KERNEL
>> 856 select SYS_SUPPORTS_BIG_ENDIAN
>> 857 select SYS_SUPPORTS_HIGHMEM
>> 858 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 859 help
>> 860 The SNI RM200/300/400 are MIPS-based machines manufactured by
>> 861 Siemens Nixdorf Informationssysteme (SNI), parent company of Pyramid
>> 862 Technology and now in turn merged with Fujitsu. Say Y here to
>> 863 support this machine type.
>> 864
>> 865 config MACH_TX39XX
>> 866 bool "Toshiba TX39 series based machines"
>> 867
>> 868 config MACH_TX49XX
>> 869 bool "Toshiba TX49 series based machines"
>> 870
>> 871 config MIKROTIK_RB532
>> 872 bool "Mikrotik RB532 boards"
>> 873 select CEVT_R4K
>> 874 select CSRC_R4K
>> 875 select DMA_NONCOHERENT
>> 876 select HW_HAS_PCI
>> 877 select IRQ_MIPS_CPU
>> 878 select SYS_HAS_CPU_MIPS32_R1
>> 879 select SYS_SUPPORTS_32BIT_KERNEL
>> 880 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 881 select SWAP_IO_SPACE
>> 882 select BOOT_RAW
>> 883 select GPIOLIB
>> 884 select MIPS_L1_CACHE_SHIFT_4
>> 885 help
>> 886 Support the Mikrotik(tm) RouterBoard 532 series,
>> 887 based on the IDT RC32434 SoC.
>> 888
>> 889 config CAVIUM_OCTEON_SOC
>> 890 bool "Cavium Networks Octeon SoC based boards"
>> 891 select CEVT_R4K
>> 892 select ARCH_PHYS_ADDR_T_64BIT
>> 893 select DMA_COHERENT
>> 894 select SYS_SUPPORTS_64BIT_KERNEL
>> 895 select SYS_SUPPORTS_BIG_ENDIAN
>> 896 select EDAC_SUPPORT
>> 897 select EDAC_ATOMIC_SCRUB
>> 898 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 899 select SYS_SUPPORTS_HOTPLUG_CPU if CPU_BIG_ENDIAN
>> 900 select SYS_HAS_EARLY_PRINTK
>> 901 select SYS_HAS_CPU_CAVIUM_OCTEON
>> 902 select HW_HAS_PCI
>> 903 select ZONE_DMA32
>> 904 select HOLES_IN_ZONE
>> 905 select GPIOLIB
>> 906 select LIBFDT
>> 907 select USE_OF
>> 908 select ARCH_SPARSEMEM_ENABLE
>> 909 select SYS_SUPPORTS_SMP
>> 910 select NR_CPUS_DEFAULT_16
>> 911 select BUILTIN_DTB
>> 912 select MTD_COMPLEX_MAPPINGS
>> 913 help
>> 914 This option supports all of the Octeon reference boards from Cavium
>> 915 Networks. It builds a kernel that dynamically determines the Octeon
>> 916 CPU type and supports all known board reference implementations.
>> 917 Some of the supported boards are:
>> 918 EBT3000
>> 919 EBH3000
>> 920 EBH3100
>> 921 Thunder
>> 922 Kodama
>> 923 Hikari
>> 924 Say Y here for most Octeon reference boards.
>> 925
>> 926 config NLM_XLR_BOARD
>> 927 bool "Netlogic XLR/XLS based systems"
>> 928 select BOOT_ELF32
>> 929 select NLM_COMMON
>> 930 select SYS_HAS_CPU_XLR
>> 931 select SYS_SUPPORTS_SMP
>> 932 select HW_HAS_PCI
>> 933 select SWAP_IO_SPACE
>> 934 select SYS_SUPPORTS_32BIT_KERNEL
>> 935 select SYS_SUPPORTS_64BIT_KERNEL
>> 936 select ARCH_PHYS_ADDR_T_64BIT
>> 937 select SYS_SUPPORTS_BIG_ENDIAN
>> 938 select SYS_SUPPORTS_HIGHMEM
>> 939 select DMA_COHERENT
>> 940 select NR_CPUS_DEFAULT_32
>> 941 select CEVT_R4K
>> 942 select CSRC_R4K
>> 943 select IRQ_MIPS_CPU
>> 944 select ZONE_DMA32 if 64BIT
>> 945 select SYNC_R4K
>> 946 select SYS_HAS_EARLY_PRINTK
>> 947 select SYS_SUPPORTS_ZBOOT
>> 948 select SYS_SUPPORTS_ZBOOT_UART16550
>> 949 help
>> 950 Support for systems based on Netlogic XLR and XLS processors.
>> 951 Say Y here if you have a XLR or XLS based board.
>> 952
>> 953 config NLM_XLP_BOARD
>> 954 bool "Netlogic XLP based systems"
>> 955 select BOOT_ELF32
>> 956 select NLM_COMMON
>> 957 select SYS_HAS_CPU_XLP
>> 958 select SYS_SUPPORTS_SMP
>> 959 select HW_HAS_PCI
>> 960 select SYS_SUPPORTS_32BIT_KERNEL
>> 961 select SYS_SUPPORTS_64BIT_KERNEL
>> 962 select ARCH_PHYS_ADDR_T_64BIT
>> 963 select GPIOLIB
>> 964 select SYS_SUPPORTS_BIG_ENDIAN
>> 965 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 966 select SYS_SUPPORTS_HIGHMEM
>> 967 select DMA_COHERENT
>> 968 select NR_CPUS_DEFAULT_32
>> 969 select CEVT_R4K
>> 970 select CSRC_R4K
>> 971 select IRQ_MIPS_CPU
>> 972 select ZONE_DMA32 if 64BIT
>> 973 select SYNC_R4K
>> 974 select SYS_HAS_EARLY_PRINTK
>> 975 select USE_OF
>> 976 select SYS_SUPPORTS_ZBOOT
>> 977 select SYS_SUPPORTS_ZBOOT_UART16550
>> 978 help
>> 979 This board is based on Netlogic XLP Processor.
>> 980 Say Y here if you have a XLP based board.
>> 981
>> 982 config MIPS_PARAVIRT
>> 983 bool "Para-Virtualized guest system"
>> 984 select CEVT_R4K
>> 985 select CSRC_R4K
>> 986 select DMA_COHERENT
>> 987 select SYS_SUPPORTS_64BIT_KERNEL
>> 988 select SYS_SUPPORTS_32BIT_KERNEL
>> 989 select SYS_SUPPORTS_BIG_ENDIAN
>> 990 select SYS_SUPPORTS_SMP
>> 991 select NR_CPUS_DEFAULT_4
>> 992 select SYS_HAS_EARLY_PRINTK
>> 993 select SYS_HAS_CPU_MIPS32_R2
>> 994 select SYS_HAS_CPU_MIPS64_R2
>> 995 select SYS_HAS_CPU_CAVIUM_OCTEON
>> 996 select HW_HAS_PCI
>> 997 select SWAP_IO_SPACE
>> 998 help
>> 999 This option supports guest running under ????
375 1000
376 config FIX_EARLYCON_MEM !! 1001 endchoice
377 def_bool y <<
378 1002
379 config PGTABLE_LEVELS !! 1003 source "arch/mips/alchemy/Kconfig"
380 int !! 1004 source "arch/mips/ath25/Kconfig"
381 default 2 if ARM64_16K_PAGES && ARM64_ !! 1005 source "arch/mips/ath79/Kconfig"
382 default 2 if ARM64_64K_PAGES && ARM64_ !! 1006 source "arch/mips/bcm47xx/Kconfig"
383 default 3 if ARM64_64K_PAGES && (ARM64 !! 1007 source "arch/mips/bcm63xx/Kconfig"
384 default 3 if ARM64_4K_PAGES && ARM64_V !! 1008 source "arch/mips/bmips/Kconfig"
385 default 3 if ARM64_16K_PAGES && ARM64_ !! 1009 source "arch/mips/generic/Kconfig"
386 default 4 if ARM64_16K_PAGES && (ARM64 !! 1010 source "arch/mips/jazz/Kconfig"
387 default 4 if !ARM64_64K_PAGES && ARM64 !! 1011 source "arch/mips/jz4740/Kconfig"
388 default 5 if ARM64_4K_PAGES && ARM64_V !! 1012 source "arch/mips/lantiq/Kconfig"
>> 1013 source "arch/mips/lasat/Kconfig"
>> 1014 source "arch/mips/pic32/Kconfig"
>> 1015 source "arch/mips/pistachio/Kconfig"
>> 1016 source "arch/mips/pmcs-msp71xx/Kconfig"
>> 1017 source "arch/mips/ralink/Kconfig"
>> 1018 source "arch/mips/sgi-ip27/Kconfig"
>> 1019 source "arch/mips/sibyte/Kconfig"
>> 1020 source "arch/mips/txx9/Kconfig"
>> 1021 source "arch/mips/vr41xx/Kconfig"
>> 1022 source "arch/mips/cavium-octeon/Kconfig"
>> 1023 source "arch/mips/loongson32/Kconfig"
>> 1024 source "arch/mips/loongson64/Kconfig"
>> 1025 source "arch/mips/netlogic/Kconfig"
>> 1026 source "arch/mips/paravirt/Kconfig"
>> 1027 source "arch/mips/xilfpga/Kconfig"
389 1028
390 config ARCH_SUPPORTS_UPROBES !! 1029 endmenu
391 def_bool y <<
392 1030
393 config ARCH_PROC_KCORE_TEXT !! 1031 config RWSEM_GENERIC_SPINLOCK
394 def_bool y !! 1032 bool
>> 1033 default y
395 1034
396 config BROKEN_GAS_INST !! 1035 config RWSEM_XCHGADD_ALGORITHM
397 def_bool !$(as-instr,1:\n.inst 0\n.rep !! 1036 bool
398 1037
399 config BUILTIN_RETURN_ADDRESS_STRIPS_PAC !! 1038 config ARCH_HAS_ILOG2_U32
400 bool 1039 bool
401 # Clang's __builtin_return_address() s <<
402 # https://github.com/llvm/llvm-project <<
403 default y if CC_IS_CLANG <<
404 # GCC's __builtin_return_address() str <<
405 # and this was backported to 10.2.0, 9 <<
406 # https://gcc.gnu.org/bugzilla/show_bu <<
407 default y if CC_IS_GCC && (GCC_VERSION <<
408 default y if CC_IS_GCC && (GCC_VERSION <<
409 default y if CC_IS_GCC && (GCC_VERSION <<
410 default y if CC_IS_GCC && (GCC_VERSION <<
411 default n 1040 default n
412 1041
413 config KASAN_SHADOW_OFFSET !! 1042 config ARCH_HAS_ILOG2_U64
414 hex <<
415 depends on KASAN_GENERIC || KASAN_SW_T <<
416 default 0xdfff800000000000 if (ARM64_V <<
417 default 0xdfffc00000000000 if (ARM64_V <<
418 default 0xdffffe0000000000 if ARM64_VA <<
419 default 0xdfffffc000000000 if ARM64_VA <<
420 default 0xdffffff800000000 if ARM64_VA <<
421 default 0xefff800000000000 if (ARM64_V <<
422 default 0xefffc00000000000 if (ARM64_V <<
423 default 0xeffffe0000000000 if ARM64_VA <<
424 default 0xefffffc000000000 if ARM64_VA <<
425 default 0xeffffff800000000 if ARM64_VA <<
426 default 0xffffffffffffffff <<
427 <<
428 config UNWIND_TABLES <<
429 bool <<
430 <<
431 source "arch/arm64/Kconfig.platforms" <<
432 <<
433 menu "Kernel Features" <<
434 <<
435 menu "ARM errata workarounds via the alternati <<
436 <<
437 config AMPERE_ERRATUM_AC03_CPU_38 <<
438 bool "AmpereOne: AC03_CPU_38: Certain <<
439 default y <<
440 help <<
441 This option adds an alternative code <<
442 errata AC03_CPU_38 and AC04_CPU_10 o <<
443 <<
444 The affected design reports FEAT_HAF <<
445 ID_AA64MMFR1_EL1.HAFDBS, but (V)TCR_ <<
446 as required by the architecture. The <<
447 implementation suffers from an addit <<
448 A/D updates can occur after a PTE ha <<
449 <<
450 The workaround forces KVM to explici <<
451 which avoids enabling unadvertised h <<
452 at stage-2. <<
453 <<
454 If unsure, say Y. <<
455 <<
456 config ARM64_WORKAROUND_CLEAN_CACHE <<
457 bool 1043 bool
>> 1044 default n
458 1045
459 config ARM64_ERRATUM_826319 !! 1046 config GENERIC_HWEIGHT
460 bool "Cortex-A53: 826319: System might !! 1047 bool
461 default y 1048 default y
462 select ARM64_WORKAROUND_CLEAN_CACHE <<
463 help <<
464 This option adds an alternative code <<
465 erratum 826319 on Cortex-A53 parts u <<
466 AXI master interface and an L2 cache <<
467 <<
468 If a Cortex-A53 uses an AMBA AXI4 AC <<
469 and is unable to accept a certain wr <<
470 not progress on read data presented <<
471 system can deadlock. <<
472 1049
473 The workaround promotes data cache c !! 1050 config GENERIC_CALIBRATE_DELAY
474 data cache clean-and-invalidate. !! 1051 bool
475 Please note that this does not neces <<
476 as it depends on the alternative fra <<
477 the kernel if an affected CPU is det <<
478 <<
479 If unsure, say Y. <<
480 <<
481 config ARM64_ERRATUM_827319 <<
482 bool "Cortex-A53: 827319: Data cache c <<
483 default y 1052 default y
484 select ARM64_WORKAROUND_CLEAN_CACHE <<
485 help <<
486 This option adds an alternative code <<
487 erratum 827319 on Cortex-A53 parts u <<
488 master interface and an L2 cache. <<
489 <<
490 Under certain conditions this erratu <<
491 to occur at the same time as another <<
492 on the AMBA 5 CHI interface, which c <<
493 interconnect reorders the two transa <<
494 <<
495 The workaround promotes data cache c <<
496 data cache clean-and-invalidate. <<
497 Please note that this does not neces <<
498 as it depends on the alternative fra <<
499 the kernel if an affected CPU is det <<
500 <<
501 If unsure, say Y. <<
502 1053
503 config ARM64_ERRATUM_824069 !! 1054 config SCHED_OMIT_FRAME_POINTER
504 bool "Cortex-A53: 824069: Cache line m !! 1055 bool
505 default y 1056 default y
506 select ARM64_WORKAROUND_CLEAN_CACHE <<
507 help <<
508 This option adds an alternative code <<
509 erratum 824069 on Cortex-A53 parts u <<
510 to a coherent interconnect. <<
511 <<
512 If a Cortex-A53 processor is executi <<
513 write instruction at the same time a <<
514 cluster is executing a cache mainten <<
515 address, then this erratum might cau <<
516 incorrectly marked as dirty. <<
517 <<
518 The workaround promotes data cache c <<
519 data cache clean-and-invalidate. <<
520 Please note that this option does no <<
521 workaround, as it depends on the alt <<
522 only patch the kernel if an affected <<
523 <<
524 If unsure, say Y. <<
525 1057
526 config ARM64_ERRATUM_819472 !! 1058 #
527 bool "Cortex-A53: 819472: Store exclus !! 1059 # Select some configuration options automatically based on user selections.
528 default y !! 1060 #
529 select ARM64_WORKAROUND_CLEAN_CACHE !! 1061 config FW_ARC
530 help !! 1062 bool
531 This option adds an alternative code <<
532 erratum 819472 on Cortex-A53 parts u <<
533 present when it is connected to a co <<
534 <<
535 If the processor is executing a load <<
536 the same time as a processor in anot <<
537 maintenance operation to the same ad <<
538 cause data corruption. <<
539 <<
540 The workaround promotes data cache c <<
541 data cache clean-and-invalidate. <<
542 Please note that this does not neces <<
543 as it depends on the alternative fra <<
544 the kernel if an affected CPU is det <<
545 1063
546 If unsure, say Y. !! 1064 config ARCH_MAY_HAVE_PC_FDC
>> 1065 bool
547 1066
548 config ARM64_ERRATUM_832075 !! 1067 config BOOT_RAW
549 bool "Cortex-A57: 832075: possible dea !! 1068 bool
550 default y <<
551 help <<
552 This option adds an alternative code <<
553 erratum 832075 on Cortex-A57 parts u <<
554 1069
555 Affected Cortex-A57 parts might dead !! 1070 config CEVT_BCM1480
556 instructions to Write-Back memory ar !! 1071 bool
557 1072
558 The workaround is to promote device !! 1073 config CEVT_DS1287
559 semantics. !! 1074 bool
560 Please note that this does not neces <<
561 as it depends on the alternative fra <<
562 the kernel if an affected CPU is det <<
563 1075
564 If unsure, say Y. !! 1076 config CEVT_GT641XX
>> 1077 bool
565 1078
566 config ARM64_ERRATUM_834220 !! 1079 config CEVT_R4K
567 bool "Cortex-A57: 834220: Stage 2 tran !! 1080 bool
568 depends on KVM <<
569 help <<
570 This option adds an alternative code <<
571 erratum 834220 on Cortex-A57 parts u <<
572 <<
573 Affected Cortex-A57 parts might repo <<
574 fault as the result of a Stage 1 fau <<
575 page boundary when there is a permis <<
576 alignment fault at Stage 1 and a tra <<
577 <<
578 The workaround is to verify that the <<
579 doesn't generate a fault before hand <<
580 Please note that this does not neces <<
581 as it depends on the alternative fra <<
582 the kernel if an affected CPU is det <<
583 1081
584 If unsure, say N. !! 1082 config CEVT_SB1250
>> 1083 bool
585 1084
586 config ARM64_ERRATUM_1742098 !! 1085 config CEVT_TXX9
587 bool "Cortex-A57/A72: 1742098: ELR rec !! 1086 bool
588 depends on COMPAT <<
589 default y <<
590 help <<
591 This option removes the AES hwcap fo <<
592 workaround erratum 1742098 on Cortex <<
593 <<
594 Affected parts may corrupt the AES s <<
595 taken between a pair of AES instruct <<
596 are only present if the cryptography <<
597 All software should have a fallback <<
598 that don't implement the cryptograph <<
599 1087
600 If unsure, say Y. !! 1088 config CSRC_BCM1480
>> 1089 bool
601 1090
602 config ARM64_ERRATUM_845719 !! 1091 config CSRC_IOASIC
603 bool "Cortex-A53: 845719: a load might !! 1092 bool
604 depends on COMPAT <<
605 default y <<
606 help <<
607 This option adds an alternative code <<
608 erratum 845719 on Cortex-A53 parts u <<
609 <<
610 When running a compat (AArch32) user <<
611 part, a load at EL0 from a virtual a <<
612 bits of the virtual address used by <<
613 might return incorrect data. <<
614 <<
615 The workaround is to write the conte <<
616 return to a 32-bit task. <<
617 Please note that this does not neces <<
618 as it depends on the alternative fra <<
619 the kernel if an affected CPU is det <<
620 1093
621 If unsure, say Y. !! 1094 config CSRC_R4K
>> 1095 bool
622 1096
623 config ARM64_ERRATUM_843419 !! 1097 config CSRC_SB1250
624 bool "Cortex-A53: 843419: A load or st !! 1098 bool
625 default y <<
626 help <<
627 This option links the kernel with '- <<
628 enables PLT support to replace certa <<
629 cause subsequent memory accesses to <<
630 Cortex-A53 parts up to r0p4. <<
631 1099
632 If unsure, say Y. !! 1100 config MIPS_CLOCK_VSYSCALL
>> 1101 def_bool CSRC_R4K || CLKSRC_MIPS_GIC
633 1102
634 config ARM64_LD_HAS_FIX_ERRATUM_843419 !! 1103 config GPIO_TXX9
635 def_bool $(ld-option,--fix-cortex-a53- !! 1104 select GPIOLIB
>> 1105 bool
636 1106
637 config ARM64_ERRATUM_1024718 !! 1107 config FW_CFE
638 bool "Cortex-A55: 1024718: Update of D !! 1108 bool
639 default y <<
640 help <<
641 This option adds a workaround for AR <<
642 1109
643 Affected Cortex-A55 cores (all revis !! 1110 config ARCH_DMA_ADDR_T_64BIT
644 update of the hardware dirty bit whe !! 1111 def_bool (HIGHMEM && ARCH_PHYS_ADDR_T_64BIT) || 64BIT
645 without a break-before-make. The wor <<
646 of hardware DBM locally on the affec <<
647 this erratum will continue to use th <<
648 1112
649 If unsure, say Y. !! 1113 config ARCH_SUPPORTS_UPROBES
>> 1114 bool
650 1115
651 config ARM64_ERRATUM_1418040 !! 1116 config DMA_MAYBE_COHERENT
652 bool "Cortex-A76/Neoverse-N1: MRC read !! 1117 select DMA_NONCOHERENT
653 default y !! 1118 bool
654 depends on COMPAT <<
655 help <<
656 This option adds a workaround for AR <<
657 errata 1188873 and 1418040. <<
658 1119
659 Affected Cortex-A76/Neoverse-N1 core !! 1120 config DMA_PERDEV_COHERENT
660 cause register corruption when acces !! 1121 bool
661 from AArch32 userspace. !! 1122 select DMA_MAYBE_COHERENT
662 1123
663 If unsure, say Y. !! 1124 config DMA_COHERENT
>> 1125 bool
664 1126
665 config ARM64_WORKAROUND_SPECULATIVE_AT !! 1127 config DMA_NONCOHERENT
666 bool 1128 bool
>> 1129 select NEED_DMA_MAP_STATE
667 1130
668 config ARM64_ERRATUM_1165522 !! 1131 config NEED_DMA_MAP_STATE
669 bool "Cortex-A76: 1165522: Speculative !! 1132 bool
670 default y <<
671 select ARM64_WORKAROUND_SPECULATIVE_AT <<
672 help <<
673 This option adds a workaround for AR <<
674 1133
675 Affected Cortex-A76 cores (r0p0, r1p !! 1134 config SYS_HAS_EARLY_PRINTK
676 corrupted TLBs by speculating an AT !! 1135 bool
677 context switch. <<
678 1136
679 If unsure, say Y. !! 1137 config SYS_SUPPORTS_HOTPLUG_CPU
>> 1138 bool
680 1139
681 config ARM64_ERRATUM_1319367 !! 1140 config MIPS_BONITO64
682 bool "Cortex-A57/A72: 1319537: Specula !! 1141 bool
683 default y <<
684 select ARM64_WORKAROUND_SPECULATIVE_AT <<
685 help <<
686 This option adds work arounds for AR <<
687 and A72 erratum 1319367 <<
688 1142
689 Cortex-A57 and A72 cores could end-u !! 1143 config MIPS_MSC
690 speculating an AT instruction during !! 1144 bool
691 1145
692 If unsure, say Y. !! 1146 config MIPS_NILE4
>> 1147 bool
693 1148
694 config ARM64_ERRATUM_1530923 !! 1149 config SYNC_R4K
695 bool "Cortex-A55: 1530923: Speculative !! 1150 bool
696 default y <<
697 select ARM64_WORKAROUND_SPECULATIVE_AT <<
698 help <<
699 This option adds a workaround for AR <<
700 1151
701 Affected Cortex-A55 cores (r0p0, r0p !! 1152 config MIPS_MACHINE
702 corrupted TLBs by speculating an AT !! 1153 def_bool n
703 context switch. <<
704 1154
705 If unsure, say Y. !! 1155 config NO_IOPORT_MAP
>> 1156 def_bool n
706 1157
707 config ARM64_WORKAROUND_REPEAT_TLBI !! 1158 config GENERIC_CSUM
708 bool 1159 bool
709 1160
710 config ARM64_ERRATUM_2441007 !! 1161 config GENERIC_ISA_DMA
711 bool "Cortex-A55: Completion of affect !! 1162 bool
712 select ARM64_WORKAROUND_REPEAT_TLBI !! 1163 select ZONE_DMA if GENERIC_ISA_DMA_SUPPORT_BROKEN=n
713 help !! 1164 select ISA_DMA_API
714 This option adds a workaround for AR <<
715 <<
716 Under very rare circumstances, affec <<
717 may not handle a race between a brea <<
718 CPU, and another CPU accessing the s <<
719 store to a page that has been unmapp <<
720 1165
721 Work around this by adding the affec !! 1166 config GENERIC_ISA_DMA_SUPPORT_BROKEN
722 TLB sequences to be done twice. !! 1167 bool
>> 1168 select GENERIC_ISA_DMA
723 1169
724 If unsure, say N. !! 1170 config ISA_DMA_API
>> 1171 bool
725 1172
726 config ARM64_ERRATUM_1286807 !! 1173 config HOLES_IN_ZONE
727 bool "Cortex-A76: Modification of the !! 1174 bool
728 select ARM64_WORKAROUND_REPEAT_TLBI <<
729 help <<
730 This option adds a workaround for AR <<
731 <<
732 On the affected Cortex-A76 cores (r0 <<
733 address for a cacheable mapping of a <<
734 accessed by a core while another cor <<
735 address to a new physical page using <<
736 break-before-make sequence, then und <<
737 TLBI+DSB completes before a read usi <<
738 invalidated has been observed by oth <<
739 workaround repeats the TLBI+DSB oper <<
740 1175
741 If unsure, say N. !! 1176 config SYS_SUPPORTS_RELOCATABLE
>> 1177 bool
>> 1178 help
>> 1179 Selected if the platform supports relocating the kernel.
>> 1180 The platform must provide plat_get_fdt() if it selects CONFIG_USE_OF
>> 1181 to allow access to command line and entropy sources.
742 1182
743 config ARM64_ERRATUM_1463225 !! 1183 #
744 bool "Cortex-A76: Software Step might !! 1184 # Endianness selection. Sufficiently obscure so many users don't know what to
745 default y !! 1185 # answer,so we try hard to limit the available choices. Also the use of a
>> 1186 # choice statement should be more obvious to the user.
>> 1187 #
>> 1188 choice
>> 1189 prompt "Endianness selection"
746 help 1190 help
747 This option adds a workaround for Ar !! 1191 Some MIPS machines can be configured for either little or big endian
>> 1192 byte order. These modes require different kernels and a different
>> 1193 Linux distribution. In general there is one preferred byteorder for a
>> 1194 particular system but some systems are just as commonly used in the
>> 1195 one or the other endianness.
748 1196
749 On the affected Cortex-A76 cores (r0 !! 1197 config CPU_BIG_ENDIAN
750 of a system call instruction (SVC) c !! 1198 bool "Big endian"
751 subsequent interrupts when software !! 1199 depends on SYS_SUPPORTS_BIG_ENDIAN
752 exception handler of the system call <<
753 is enabled or VHE is in use. <<
754 1200
755 Work around the erratum by triggerin !! 1201 config CPU_LITTLE_ENDIAN
756 when handling a system call from a t !! 1202 bool "Little endian"
757 in a VHE configuration of the kernel !! 1203 depends on SYS_SUPPORTS_LITTLE_ENDIAN
758 1204
759 If unsure, say Y. !! 1205 endchoice
760 1206
761 config ARM64_ERRATUM_1542419 !! 1207 config EXPORT_UASM
762 bool "Neoverse-N1: workaround mis-orde !! 1208 bool
763 help <<
764 This option adds a workaround for AR <<
765 1542419. <<
766 1209
767 Affected Neoverse-N1 cores could exe !! 1210 config SYS_SUPPORTS_APM_EMULATION
768 modified by another CPU. The workaro !! 1211 bool
769 counterpart. <<
770 1212
771 Workaround the issue by hiding the D !! 1213 config SYS_SUPPORTS_BIG_ENDIAN
772 forces user-space to perform cache m !! 1214 bool
773 1215
774 If unsure, say N. !! 1216 config SYS_SUPPORTS_LITTLE_ENDIAN
>> 1217 bool
775 1218
776 config ARM64_ERRATUM_1508412 !! 1219 config SYS_SUPPORTS_HUGETLBFS
777 bool "Cortex-A77: 1508412: workaround !! 1220 bool
>> 1221 depends on CPU_SUPPORTS_HUGEPAGES && 64BIT
778 default y 1222 default y
779 help <<
780 This option adds a workaround for Ar <<
781 1223
782 Affected Cortex-A77 cores (r0p0, r1p !! 1224 config MIPS_HUGE_TLB_SUPPORT
783 of a store-exclusive or read of PAR_ !! 1225 def_bool HUGETLB_PAGE || TRANSPARENT_HUGEPAGE
784 non-cacheable memory attributes. The <<
785 counterpart. <<
786 1226
787 KVM guests must also have the workar !! 1227 config IRQ_CPU_RM7K
788 deadlock the system. !! 1228 bool
789 1229
790 Work around the issue by inserting D !! 1230 config IRQ_MSP_SLP
791 register reads and warning KVM users !! 1231 bool
792 to prevent a speculative PAR_EL1 rea <<
793 1232
794 If unsure, say Y. !! 1233 config IRQ_MSP_CIC
>> 1234 bool
795 1235
796 config ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MO !! 1236 config IRQ_TXX9
797 bool 1237 bool
798 1238
799 config ARM64_ERRATUM_2051678 !! 1239 config IRQ_GT641XX
800 bool "Cortex-A510: 2051678: disable Ha !! 1240 bool
801 default y <<
802 help <<
803 This options adds the workaround for <<
804 Affected Cortex-A510 might not respe <<
805 hardware update of the page table's <<
806 is to not enable the feature on affe <<
807 1241
808 If unsure, say Y. !! 1242 config PCI_GT64XXX_PCI0
>> 1243 bool
809 1244
810 config ARM64_ERRATUM_2077057 !! 1245 config NO_EXCEPT_FILL
811 bool "Cortex-A510: 2077057: workaround !! 1246 bool
812 default y <<
813 help <<
814 This option adds the workaround for <<
815 Affected Cortex-A510 may corrupt SPS <<
816 expected, but a Pointer Authenticati <<
817 erratum causes SPSR_EL1 to be copied <<
818 EL1 to cause a return to EL2 with a <<
819 1247
820 This can only happen when EL2 is ste !! 1248 config SOC_EMMA2RH
>> 1249 bool
>> 1250 select CEVT_R4K
>> 1251 select CSRC_R4K
>> 1252 select DMA_NONCOHERENT
>> 1253 select IRQ_MIPS_CPU
>> 1254 select SWAP_IO_SPACE
>> 1255 select SYS_HAS_CPU_R5500
>> 1256 select SYS_SUPPORTS_32BIT_KERNEL
>> 1257 select SYS_SUPPORTS_64BIT_KERNEL
>> 1258 select SYS_SUPPORTS_BIG_ENDIAN
821 1259
822 When these conditions occur, the SPS !! 1260 config SOC_PNX833X
823 previous guest entry, and can be res !! 1261 bool
>> 1262 select CEVT_R4K
>> 1263 select CSRC_R4K
>> 1264 select IRQ_MIPS_CPU
>> 1265 select DMA_NONCOHERENT
>> 1266 select SYS_HAS_CPU_MIPS32_R2
>> 1267 select SYS_SUPPORTS_32BIT_KERNEL
>> 1268 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 1269 select SYS_SUPPORTS_BIG_ENDIAN
>> 1270 select SYS_SUPPORTS_MIPS16
>> 1271 select CPU_MIPSR2_IRQ_VI
824 1272
825 If unsure, say Y. !! 1273 config SOC_PNX8335
>> 1274 bool
>> 1275 select SOC_PNX833X
826 1276
827 config ARM64_ERRATUM_2658417 !! 1277 config MIPS_SPRAM
828 bool "Cortex-A510: 2658417: remove BF1 !! 1278 bool
829 default y <<
830 help <<
831 This option adds the workaround for <<
832 Affected Cortex-A510 (r0p0 to r1p1) <<
833 BFMMLA or VMMLA instructions in rare <<
834 A510 CPUs are using shared neon hard <<
835 discoverable by the kernel, hide the <<
836 user-space should not be using these <<
837 1279
838 If unsure, say Y. !! 1280 config SWAP_IO_SPACE
>> 1281 bool
839 1282
840 config ARM64_ERRATUM_2119858 !! 1283 config SGI_HAS_INDYDOG
841 bool "Cortex-A710/X2: 2119858: workaro !! 1284 bool
842 default y <<
843 depends on CORESIGHT_TRBE <<
844 select ARM64_WORKAROUND_TRBE_OVERWRITE <<
845 help <<
846 This option adds the workaround for <<
847 1285
848 Affected Cortex-A710/X2 cores could !! 1286 config SGI_HAS_HAL2
849 data at the base of the buffer (poin !! 1287 bool
850 the event of a WRAP event. <<
851 1288
852 Work around the issue by always maki !! 1289 config SGI_HAS_SEEQ
853 256 bytes before enabling the buffer !! 1290 bool
854 the buffer with ETM ignore packets u <<
855 1291
856 If unsure, say Y. !! 1292 config SGI_HAS_WD93
>> 1293 bool
857 1294
858 config ARM64_ERRATUM_2139208 !! 1295 config SGI_HAS_ZILOG
859 bool "Neoverse-N2: 2139208: workaround !! 1296 bool
860 default y <<
861 depends on CORESIGHT_TRBE <<
862 select ARM64_WORKAROUND_TRBE_OVERWRITE <<
863 help <<
864 This option adds the workaround for <<
865 1297
866 Affected Neoverse-N2 cores could ove !! 1298 config SGI_HAS_I8042
867 data at the base of the buffer (poin !! 1299 bool
868 the event of a WRAP event. <<
869 1300
870 Work around the issue by always maki !! 1301 config DEFAULT_SGI_PARTITION
871 256 bytes before enabling the buffer !! 1302 bool
872 the buffer with ETM ignore packets u <<
873 1303
874 If unsure, say Y. !! 1304 config FW_ARC32
>> 1305 bool
875 1306
876 config ARM64_WORKAROUND_TSB_FLUSH_FAILURE !! 1307 config FW_SNIPROM
877 bool 1308 bool
878 1309
879 config ARM64_ERRATUM_2054223 !! 1310 config BOOT_ELF32
880 bool "Cortex-A710: 2054223: workaround !! 1311 bool
881 default y <<
882 select ARM64_WORKAROUND_TSB_FLUSH_FAIL <<
883 help <<
884 Enable workaround for ARM Cortex-A71 <<
885 1312
886 Affected cores may fail to flush the !! 1313 config MIPS_L1_CACHE_SHIFT_4
887 the PE is in trace prohibited state. !! 1314 bool
888 of the trace cached. <<
889 1315
890 Workaround is to issue two TSB conse !! 1316 config MIPS_L1_CACHE_SHIFT_5
>> 1317 bool
891 1318
892 If unsure, say Y. !! 1319 config MIPS_L1_CACHE_SHIFT_6
>> 1320 bool
893 1321
894 config ARM64_ERRATUM_2067961 !! 1322 config MIPS_L1_CACHE_SHIFT_7
895 bool "Neoverse-N2: 2067961: workaround !! 1323 bool
896 default y <<
897 select ARM64_WORKAROUND_TSB_FLUSH_FAIL <<
898 help <<
899 Enable workaround for ARM Neoverse-N <<
900 1324
901 Affected cores may fail to flush the !! 1325 config MIPS_L1_CACHE_SHIFT
902 the PE is in trace prohibited state. !! 1326 int
903 of the trace cached. !! 1327 default "7" if MIPS_L1_CACHE_SHIFT_7
>> 1328 default "6" if MIPS_L1_CACHE_SHIFT_6
>> 1329 default "5" if MIPS_L1_CACHE_SHIFT_5
>> 1330 default "4" if MIPS_L1_CACHE_SHIFT_4
>> 1331 default "5"
904 1332
905 Workaround is to issue two TSB conse !! 1333 config HAVE_STD_PC_SERIAL_PORT
>> 1334 bool
906 1335
907 If unsure, say Y. !! 1336 config ARC_CONSOLE
>> 1337 bool "ARC console support"
>> 1338 depends on SGI_IP22 || SGI_IP28 || (SNI_RM && CPU_LITTLE_ENDIAN)
908 1339
909 config ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANG !! 1340 config ARC_MEMORY
910 bool 1341 bool
911 !! 1342 depends on MACH_JAZZ || SNI_RM || SGI_IP32
912 config ARM64_ERRATUM_2253138 <<
913 bool "Neoverse-N2: 2253138: workaround <<
914 depends on CORESIGHT_TRBE <<
915 default y 1343 default y
916 select ARM64_WORKAROUND_TRBE_WRITE_OUT <<
917 help <<
918 This option adds the workaround for <<
919 <<
920 Affected Neoverse-N2 cores might wri <<
921 for TRBE. Under some conditions, the <<
922 virtually addressed page following t <<
923 (i.e., the TRBLIMITR_EL1.LIMIT), ins <<
924 <<
925 Work around this in the driver by al <<
926 page beyond the TRBLIMITR_EL1.LIMIT, <<
927 <<
928 If unsure, say Y. <<
929 1344
930 config ARM64_ERRATUM_2224489 !! 1345 config ARC_PROMLIB
931 bool "Cortex-A710/X2: 2224489: workaro !! 1346 bool
932 depends on CORESIGHT_TRBE !! 1347 depends on MACH_JAZZ || SNI_RM || SGI_IP22 || SGI_IP28 || SGI_IP32
933 default y 1348 default y
934 select ARM64_WORKAROUND_TRBE_WRITE_OUT <<
935 help <<
936 This option adds the workaround for <<
937 <<
938 Affected Cortex-A710/X2 cores might <<
939 for TRBE. Under some conditions, the <<
940 virtually addressed page following t <<
941 (i.e., the TRBLIMITR_EL1.LIMIT), ins <<
942 1349
943 Work around this in the driver by al !! 1350 config FW_ARC64
944 page beyond the TRBLIMITR_EL1.LIMIT, !! 1351 bool
945 <<
946 If unsure, say Y. <<
947 1352
948 config ARM64_ERRATUM_2441009 !! 1353 config BOOT_ELF64
949 bool "Cortex-A510: Completion of affec !! 1354 bool
950 select ARM64_WORKAROUND_REPEAT_TLBI <<
951 help <<
952 This option adds a workaround for AR <<
953 <<
954 Under very rare circumstances, affec <<
955 may not handle a race between a brea <<
956 CPU, and another CPU accessing the s <<
957 store to a page that has been unmapp <<
958 1355
959 Work around this by adding the affec !! 1356 menu "CPU selection"
960 TLB sequences to be done twice. <<
961 1357
962 If unsure, say N. !! 1358 choice
>> 1359 prompt "CPU type"
>> 1360 default CPU_R4X00
963 1361
964 config ARM64_ERRATUM_2064142 !! 1362 config CPU_LOONGSON3
965 bool "Cortex-A510: 2064142: workaround !! 1363 bool "Loongson 3 CPU"
966 depends on CORESIGHT_TRBE !! 1364 depends on SYS_HAS_CPU_LOONGSON3
967 default y !! 1365 select CPU_SUPPORTS_64BIT_KERNEL
>> 1366 select CPU_SUPPORTS_HIGHMEM
>> 1367 select CPU_SUPPORTS_HUGEPAGES
>> 1368 select WEAK_ORDERING
>> 1369 select WEAK_REORDERING_BEYOND_LLSC
>> 1370 select MIPS_PGD_C0_CONTEXT
>> 1371 select GPIOLIB
968 help 1372 help
969 This option adds the workaround for !! 1373 The Loongson 3 processor implements the MIPS64R2 instruction
970 !! 1374 set with many extensions.
971 Affected Cortex-A510 core might fail <<
972 TRBE has been disabled. Under some c <<
973 writes into TRBE registers TRBLIMITR <<
974 and TRBTRG_EL1 will be ignored and w <<
975 1375
976 Work around this in the driver by ex !! 1376 config LOONGSON3_ENHANCEMENT
977 is stopped and before performing a s !! 1377 bool "New Loongson 3 CPU Enhancements"
978 registers. !! 1378 default n
>> 1379 select CPU_MIPSR2
>> 1380 select CPU_HAS_PREFETCH
>> 1381 depends on CPU_LOONGSON3
>> 1382 help
>> 1383 New Loongson 3 CPU (since Loongson-3A R2, as opposed to Loongson-3A
>> 1384 R1, Loongson-3B R1 and Loongson-3B R2) has many enhancements, such as
>> 1385 FTLB, L1-VCache, EI/DI/Wait/Prefetch instruction, DSP/DSPv2 ASE, User
>> 1386 Local register, Read-Inhibit/Execute-Inhibit, SFB (Store Fill Buffer),
>> 1387 Fast TLB refill support, etc.
>> 1388
>> 1389 This option enable those enhancements which are not probed at run
>> 1390 time. If you want a generic kernel to run on all Loongson 3 machines,
>> 1391 please say 'N' here. If you want a high-performance kernel to run on
>> 1392 new Loongson 3 machines only, please say 'Y' here.
>> 1393
>> 1394 config CPU_LOONGSON2E
>> 1395 bool "Loongson 2E"
>> 1396 depends on SYS_HAS_CPU_LOONGSON2E
>> 1397 select CPU_LOONGSON2
>> 1398 help
>> 1399 The Loongson 2E processor implements the MIPS III instruction set
>> 1400 with many extensions.
>> 1401
>> 1402 It has an internal FPGA northbridge, which is compatible to
>> 1403 bonito64.
>> 1404
>> 1405 config CPU_LOONGSON2F
>> 1406 bool "Loongson 2F"
>> 1407 depends on SYS_HAS_CPU_LOONGSON2F
>> 1408 select CPU_LOONGSON2
>> 1409 select GPIOLIB
>> 1410 help
>> 1411 The Loongson 2F processor implements the MIPS III instruction set
>> 1412 with many extensions.
>> 1413
>> 1414 Loongson2F have built-in DDR2 and PCIX controller. The PCIX controller
>> 1415 have a similar programming interface with FPGA northbridge used in
>> 1416 Loongson2E.
>> 1417
>> 1418 config CPU_LOONGSON1B
>> 1419 bool "Loongson 1B"
>> 1420 depends on SYS_HAS_CPU_LOONGSON1B
>> 1421 select CPU_LOONGSON1
>> 1422 select LEDS_GPIO_REGISTER
>> 1423 help
>> 1424 The Loongson 1B is a 32-bit SoC, which implements the MIPS32
>> 1425 release 2 instruction set.
>> 1426
>> 1427 config CPU_LOONGSON1C
>> 1428 bool "Loongson 1C"
>> 1429 depends on SYS_HAS_CPU_LOONGSON1C
>> 1430 select CPU_LOONGSON1
>> 1431 select ARCH_WANT_OPTIONAL_GPIOLIB
>> 1432 select LEDS_GPIO_REGISTER
>> 1433 help
>> 1434 The Loongson 1C is a 32-bit SoC, which implements the MIPS32
>> 1435 release 2 instruction set.
>> 1436
>> 1437 config CPU_MIPS32_R1
>> 1438 bool "MIPS32 Release 1"
>> 1439 depends on SYS_HAS_CPU_MIPS32_R1
>> 1440 select CPU_HAS_PREFETCH
>> 1441 select CPU_SUPPORTS_32BIT_KERNEL
>> 1442 select CPU_SUPPORTS_HIGHMEM
>> 1443 help
>> 1444 Choose this option to build a kernel for release 1 or later of the
>> 1445 MIPS32 architecture. Most modern embedded systems with a 32-bit
>> 1446 MIPS processor are based on a MIPS32 processor. If you know the
>> 1447 specific type of processor in your system, choose those that one
>> 1448 otherwise CPU_MIPS32_R1 is a safe bet for any MIPS32 system.
>> 1449 Release 2 of the MIPS32 architecture is available since several
>> 1450 years so chances are you even have a MIPS32 Release 2 processor
>> 1451 in which case you should choose CPU_MIPS32_R2 instead for better
>> 1452 performance.
>> 1453
>> 1454 config CPU_MIPS32_R2
>> 1455 bool "MIPS32 Release 2"
>> 1456 depends on SYS_HAS_CPU_MIPS32_R2
>> 1457 select CPU_HAS_PREFETCH
>> 1458 select CPU_SUPPORTS_32BIT_KERNEL
>> 1459 select CPU_SUPPORTS_HIGHMEM
>> 1460 select CPU_SUPPORTS_MSA
>> 1461 select HAVE_KVM
>> 1462 help
>> 1463 Choose this option to build a kernel for release 2 or later of the
>> 1464 MIPS32 architecture. Most modern embedded systems with a 32-bit
>> 1465 MIPS processor are based on a MIPS32 processor. If you know the
>> 1466 specific type of processor in your system, choose those that one
>> 1467 otherwise CPU_MIPS32_R1 is a safe bet for any MIPS32 system.
>> 1468
>> 1469 config CPU_MIPS32_R6
>> 1470 bool "MIPS32 Release 6"
>> 1471 depends on SYS_HAS_CPU_MIPS32_R6
>> 1472 select CPU_HAS_PREFETCH
>> 1473 select CPU_SUPPORTS_32BIT_KERNEL
>> 1474 select CPU_SUPPORTS_HIGHMEM
>> 1475 select CPU_SUPPORTS_MSA
>> 1476 select GENERIC_CSUM
>> 1477 select HAVE_KVM
>> 1478 select MIPS_O32_FP64_SUPPORT
>> 1479 help
>> 1480 Choose this option to build a kernel for release 6 or later of the
>> 1481 MIPS32 architecture. New MIPS processors, starting with the Warrior
>> 1482 family, are based on a MIPS32r6 processor. If you own an older
>> 1483 processor, you probably need to select MIPS32r1 or MIPS32r2 instead.
>> 1484
>> 1485 config CPU_MIPS64_R1
>> 1486 bool "MIPS64 Release 1"
>> 1487 depends on SYS_HAS_CPU_MIPS64_R1
>> 1488 select CPU_HAS_PREFETCH
>> 1489 select CPU_SUPPORTS_32BIT_KERNEL
>> 1490 select CPU_SUPPORTS_64BIT_KERNEL
>> 1491 select CPU_SUPPORTS_HIGHMEM
>> 1492 select CPU_SUPPORTS_HUGEPAGES
>> 1493 help
>> 1494 Choose this option to build a kernel for release 1 or later of the
>> 1495 MIPS64 architecture. Many modern embedded systems with a 64-bit
>> 1496 MIPS processor are based on a MIPS64 processor. If you know the
>> 1497 specific type of processor in your system, choose those that one
>> 1498 otherwise CPU_MIPS64_R1 is a safe bet for any MIPS64 system.
>> 1499 Release 2 of the MIPS64 architecture is available since several
>> 1500 years so chances are you even have a MIPS64 Release 2 processor
>> 1501 in which case you should choose CPU_MIPS64_R2 instead for better
>> 1502 performance.
>> 1503
>> 1504 config CPU_MIPS64_R2
>> 1505 bool "MIPS64 Release 2"
>> 1506 depends on SYS_HAS_CPU_MIPS64_R2
>> 1507 select CPU_HAS_PREFETCH
>> 1508 select CPU_SUPPORTS_32BIT_KERNEL
>> 1509 select CPU_SUPPORTS_64BIT_KERNEL
>> 1510 select CPU_SUPPORTS_HIGHMEM
>> 1511 select CPU_SUPPORTS_HUGEPAGES
>> 1512 select CPU_SUPPORTS_MSA
>> 1513 select HAVE_KVM
>> 1514 help
>> 1515 Choose this option to build a kernel for release 2 or later of the
>> 1516 MIPS64 architecture. Many modern embedded systems with a 64-bit
>> 1517 MIPS processor are based on a MIPS64 processor. If you know the
>> 1518 specific type of processor in your system, choose those that one
>> 1519 otherwise CPU_MIPS64_R1 is a safe bet for any MIPS64 system.
>> 1520
>> 1521 config CPU_MIPS64_R6
>> 1522 bool "MIPS64 Release 6"
>> 1523 depends on SYS_HAS_CPU_MIPS64_R6
>> 1524 select CPU_HAS_PREFETCH
>> 1525 select CPU_SUPPORTS_32BIT_KERNEL
>> 1526 select CPU_SUPPORTS_64BIT_KERNEL
>> 1527 select CPU_SUPPORTS_HIGHMEM
>> 1528 select CPU_SUPPORTS_MSA
>> 1529 select GENERIC_CSUM
>> 1530 select MIPS_O32_FP64_SUPPORT if 32BIT || MIPS32_O32
>> 1531 select HAVE_KVM
>> 1532 help
>> 1533 Choose this option to build a kernel for release 6 or later of the
>> 1534 MIPS64 architecture. New MIPS processors, starting with the Warrior
>> 1535 family, are based on a MIPS64r6 processor. If you own an older
>> 1536 processor, you probably need to select MIPS64r1 or MIPS64r2 instead.
>> 1537
>> 1538 config CPU_R3000
>> 1539 bool "R3000"
>> 1540 depends on SYS_HAS_CPU_R3000
>> 1541 select CPU_HAS_WB
>> 1542 select CPU_SUPPORTS_32BIT_KERNEL
>> 1543 select CPU_SUPPORTS_HIGHMEM
>> 1544 help
>> 1545 Please make sure to pick the right CPU type. Linux/MIPS is not
>> 1546 designed to be generic, i.e. Kernels compiled for R3000 CPUs will
>> 1547 *not* work on R4000 machines and vice versa. However, since most
>> 1548 of the supported machines have an R4000 (or similar) CPU, R4x00
>> 1549 might be a safe bet. If the resulting kernel does not work,
>> 1550 try to recompile with R3000.
>> 1551
>> 1552 config CPU_TX39XX
>> 1553 bool "R39XX"
>> 1554 depends on SYS_HAS_CPU_TX39XX
>> 1555 select CPU_SUPPORTS_32BIT_KERNEL
>> 1556
>> 1557 config CPU_VR41XX
>> 1558 bool "R41xx"
>> 1559 depends on SYS_HAS_CPU_VR41XX
>> 1560 select CPU_SUPPORTS_32BIT_KERNEL
>> 1561 select CPU_SUPPORTS_64BIT_KERNEL
>> 1562 help
>> 1563 The options selects support for the NEC VR4100 series of processors.
>> 1564 Only choose this option if you have one of these processors as a
>> 1565 kernel built with this option will not run on any other type of
>> 1566 processor or vice versa.
>> 1567
>> 1568 config CPU_R4300
>> 1569 bool "R4300"
>> 1570 depends on SYS_HAS_CPU_R4300
>> 1571 select CPU_SUPPORTS_32BIT_KERNEL
>> 1572 select CPU_SUPPORTS_64BIT_KERNEL
>> 1573 help
>> 1574 MIPS Technologies R4300-series processors.
>> 1575
>> 1576 config CPU_R4X00
>> 1577 bool "R4x00"
>> 1578 depends on SYS_HAS_CPU_R4X00
>> 1579 select CPU_SUPPORTS_32BIT_KERNEL
>> 1580 select CPU_SUPPORTS_64BIT_KERNEL
>> 1581 select CPU_SUPPORTS_HUGEPAGES
>> 1582 help
>> 1583 MIPS Technologies R4000-series processors other than 4300, including
>> 1584 the R4000, R4400, R4600, and 4700.
>> 1585
>> 1586 config CPU_TX49XX
>> 1587 bool "R49XX"
>> 1588 depends on SYS_HAS_CPU_TX49XX
>> 1589 select CPU_HAS_PREFETCH
>> 1590 select CPU_SUPPORTS_32BIT_KERNEL
>> 1591 select CPU_SUPPORTS_64BIT_KERNEL
>> 1592 select CPU_SUPPORTS_HUGEPAGES
>> 1593
>> 1594 config CPU_R5000
>> 1595 bool "R5000"
>> 1596 depends on SYS_HAS_CPU_R5000
>> 1597 select CPU_SUPPORTS_32BIT_KERNEL
>> 1598 select CPU_SUPPORTS_64BIT_KERNEL
>> 1599 select CPU_SUPPORTS_HUGEPAGES
>> 1600 help
>> 1601 MIPS Technologies R5000-series processors other than the Nevada.
>> 1602
>> 1603 config CPU_R5432
>> 1604 bool "R5432"
>> 1605 depends on SYS_HAS_CPU_R5432
>> 1606 select CPU_SUPPORTS_32BIT_KERNEL
>> 1607 select CPU_SUPPORTS_64BIT_KERNEL
>> 1608 select CPU_SUPPORTS_HUGEPAGES
>> 1609
>> 1610 config CPU_R5500
>> 1611 bool "R5500"
>> 1612 depends on SYS_HAS_CPU_R5500
>> 1613 select CPU_SUPPORTS_32BIT_KERNEL
>> 1614 select CPU_SUPPORTS_64BIT_KERNEL
>> 1615 select CPU_SUPPORTS_HUGEPAGES
>> 1616 help
>> 1617 NEC VR5500 and VR5500A series processors implement 64-bit MIPS IV
>> 1618 instruction set.
>> 1619
>> 1620 config CPU_R6000
>> 1621 bool "R6000"
>> 1622 depends on SYS_HAS_CPU_R6000
>> 1623 select CPU_SUPPORTS_32BIT_KERNEL
>> 1624 help
>> 1625 MIPS Technologies R6000 and R6000A series processors. Note these
>> 1626 processors are extremely rare and the support for them is incomplete.
>> 1627
>> 1628 config CPU_NEVADA
>> 1629 bool "RM52xx"
>> 1630 depends on SYS_HAS_CPU_NEVADA
>> 1631 select CPU_SUPPORTS_32BIT_KERNEL
>> 1632 select CPU_SUPPORTS_64BIT_KERNEL
>> 1633 select CPU_SUPPORTS_HUGEPAGES
>> 1634 help
>> 1635 QED / PMC-Sierra RM52xx-series ("Nevada") processors.
>> 1636
>> 1637 config CPU_R8000
>> 1638 bool "R8000"
>> 1639 depends on SYS_HAS_CPU_R8000
>> 1640 select CPU_HAS_PREFETCH
>> 1641 select CPU_SUPPORTS_64BIT_KERNEL
>> 1642 help
>> 1643 MIPS Technologies R8000 processors. Note these processors are
>> 1644 uncommon and the support for them is incomplete.
>> 1645
>> 1646 config CPU_R10000
>> 1647 bool "R10000"
>> 1648 depends on SYS_HAS_CPU_R10000
>> 1649 select CPU_HAS_PREFETCH
>> 1650 select CPU_SUPPORTS_32BIT_KERNEL
>> 1651 select CPU_SUPPORTS_64BIT_KERNEL
>> 1652 select CPU_SUPPORTS_HIGHMEM
>> 1653 select CPU_SUPPORTS_HUGEPAGES
>> 1654 help
>> 1655 MIPS Technologies R10000-series processors.
>> 1656
>> 1657 config CPU_RM7000
>> 1658 bool "RM7000"
>> 1659 depends on SYS_HAS_CPU_RM7000
>> 1660 select CPU_HAS_PREFETCH
>> 1661 select CPU_SUPPORTS_32BIT_KERNEL
>> 1662 select CPU_SUPPORTS_64BIT_KERNEL
>> 1663 select CPU_SUPPORTS_HIGHMEM
>> 1664 select CPU_SUPPORTS_HUGEPAGES
>> 1665
>> 1666 config CPU_SB1
>> 1667 bool "SB1"
>> 1668 depends on SYS_HAS_CPU_SB1
>> 1669 select CPU_SUPPORTS_32BIT_KERNEL
>> 1670 select CPU_SUPPORTS_64BIT_KERNEL
>> 1671 select CPU_SUPPORTS_HIGHMEM
>> 1672 select CPU_SUPPORTS_HUGEPAGES
>> 1673 select WEAK_ORDERING
>> 1674
>> 1675 config CPU_CAVIUM_OCTEON
>> 1676 bool "Cavium Octeon processor"
>> 1677 depends on SYS_HAS_CPU_CAVIUM_OCTEON
>> 1678 select CPU_HAS_PREFETCH
>> 1679 select CPU_SUPPORTS_64BIT_KERNEL
>> 1680 select WEAK_ORDERING
>> 1681 select CPU_SUPPORTS_HIGHMEM
>> 1682 select CPU_SUPPORTS_HUGEPAGES
>> 1683 select USB_EHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 1684 select USB_OHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 1685 select MIPS_L1_CACHE_SHIFT_7
>> 1686 help
>> 1687 The Cavium Octeon processor is a highly integrated chip containing
>> 1688 many ethernet hardware widgets for networking tasks. The processor
>> 1689 can have up to 16 Mips64v2 cores and 8 integrated gigabit ethernets.
>> 1690 Full details can be found at http://www.caviumnetworks.com.
>> 1691
>> 1692 config CPU_BMIPS
>> 1693 bool "Broadcom BMIPS"
>> 1694 depends on SYS_HAS_CPU_BMIPS
>> 1695 select CPU_MIPS32
>> 1696 select CPU_BMIPS32_3300 if SYS_HAS_CPU_BMIPS32_3300
>> 1697 select CPU_BMIPS4350 if SYS_HAS_CPU_BMIPS4350
>> 1698 select CPU_BMIPS4380 if SYS_HAS_CPU_BMIPS4380
>> 1699 select CPU_BMIPS5000 if SYS_HAS_CPU_BMIPS5000
>> 1700 select CPU_SUPPORTS_32BIT_KERNEL
>> 1701 select DMA_NONCOHERENT
>> 1702 select IRQ_MIPS_CPU
>> 1703 select SWAP_IO_SPACE
>> 1704 select WEAK_ORDERING
>> 1705 select CPU_SUPPORTS_HIGHMEM
>> 1706 select CPU_HAS_PREFETCH
>> 1707 help
>> 1708 Support for BMIPS32/3300/4350/4380 and BMIPS5000 processors.
>> 1709
>> 1710 config CPU_XLR
>> 1711 bool "Netlogic XLR SoC"
>> 1712 depends on SYS_HAS_CPU_XLR
>> 1713 select CPU_SUPPORTS_32BIT_KERNEL
>> 1714 select CPU_SUPPORTS_64BIT_KERNEL
>> 1715 select CPU_SUPPORTS_HIGHMEM
>> 1716 select CPU_SUPPORTS_HUGEPAGES
>> 1717 select WEAK_ORDERING
>> 1718 select WEAK_REORDERING_BEYOND_LLSC
>> 1719 help
>> 1720 Netlogic Microsystems XLR/XLS processors.
>> 1721
>> 1722 config CPU_XLP
>> 1723 bool "Netlogic XLP SoC"
>> 1724 depends on SYS_HAS_CPU_XLP
>> 1725 select CPU_SUPPORTS_32BIT_KERNEL
>> 1726 select CPU_SUPPORTS_64BIT_KERNEL
>> 1727 select CPU_SUPPORTS_HIGHMEM
>> 1728 select WEAK_ORDERING
>> 1729 select WEAK_REORDERING_BEYOND_LLSC
>> 1730 select CPU_HAS_PREFETCH
>> 1731 select CPU_MIPSR2
>> 1732 select CPU_SUPPORTS_HUGEPAGES
>> 1733 select MIPS_ASID_BITS_VARIABLE
>> 1734 help
>> 1735 Netlogic Microsystems XLP processors.
>> 1736 endchoice
979 1737
980 If unsure, say Y. !! 1738 config CPU_MIPS32_3_5_FEATURES
>> 1739 bool "MIPS32 Release 3.5 Features"
>> 1740 depends on SYS_HAS_CPU_MIPS32_R3_5
>> 1741 depends on CPU_MIPS32_R2 || CPU_MIPS32_R6
>> 1742 help
>> 1743 Choose this option to build a kernel for release 2 or later of the
>> 1744 MIPS32 architecture including features from the 3.5 release such as
>> 1745 support for Enhanced Virtual Addressing (EVA).
>> 1746
>> 1747 config CPU_MIPS32_3_5_EVA
>> 1748 bool "Enhanced Virtual Addressing (EVA)"
>> 1749 depends on CPU_MIPS32_3_5_FEATURES
>> 1750 select EVA
>> 1751 default y
>> 1752 help
>> 1753 Choose this option if you want to enable the Enhanced Virtual
>> 1754 Addressing (EVA) on your MIPS32 core (such as proAptiv).
>> 1755 One of its primary benefits is an increase in the maximum size
>> 1756 of lowmem (up to 3GB). If unsure, say 'N' here.
>> 1757
>> 1758 config CPU_MIPS32_R5_FEATURES
>> 1759 bool "MIPS32 Release 5 Features"
>> 1760 depends on SYS_HAS_CPU_MIPS32_R5
>> 1761 depends on CPU_MIPS32_R2
>> 1762 help
>> 1763 Choose this option to build a kernel for release 2 or later of the
>> 1764 MIPS32 architecture including features from release 5 such as
>> 1765 support for Extended Physical Addressing (XPA).
>> 1766
>> 1767 config CPU_MIPS32_R5_XPA
>> 1768 bool "Extended Physical Addressing (XPA)"
>> 1769 depends on CPU_MIPS32_R5_FEATURES
>> 1770 depends on !EVA
>> 1771 depends on !PAGE_SIZE_4KB
>> 1772 depends on SYS_SUPPORTS_HIGHMEM
>> 1773 select XPA
>> 1774 select HIGHMEM
>> 1775 select ARCH_PHYS_ADDR_T_64BIT
>> 1776 default n
>> 1777 help
>> 1778 Choose this option if you want to enable the Extended Physical
>> 1779 Addressing (XPA) on your MIPS32 core (such as P5600 series). The
>> 1780 benefit is to increase physical addressing equal to or greater
>> 1781 than 40 bits. Note that this has the side effect of turning on
>> 1782 64-bit addressing which in turn makes the PTEs 64-bit in size.
>> 1783 If unsure, say 'N' here.
981 1784
982 config ARM64_ERRATUM_2038923 !! 1785 if CPU_LOONGSON2F
983 bool "Cortex-A510: 2038923: workaround !! 1786 config CPU_NOP_WORKAROUNDS
984 depends on CORESIGHT_TRBE !! 1787 bool
985 default y <<
986 help <<
987 This option adds the workaround for <<
988 <<
989 Affected Cortex-A510 core might caus <<
990 prohibited within the CPU. As a resu <<
991 might be corrupted. This happens aft <<
992 TRBLIMITR_EL1.E, followed by just a <<
993 execution changes from a context, in <<
994 isn't, or vice versa. In these menti <<
995 is prohibited is inconsistent betwee <<
996 the trace buffer state might be corr <<
997 <<
998 Work around this in the driver by pr <<
999 trace is prohibited or not based on <<
1000 change to TRBLIMITR_EL1.E with at l <<
1001 two ISB instructions if no ERET is <<
1002 1788
1003 If unsure, say Y. !! 1789 config CPU_JUMP_WORKAROUNDS
>> 1790 bool
1004 1791
1005 config ARM64_ERRATUM_1902691 !! 1792 config CPU_LOONGSON2F_WORKAROUNDS
1006 bool "Cortex-A510: 1902691: workaroun !! 1793 bool "Loongson 2F Workarounds"
1007 depends on CORESIGHT_TRBE <<
1008 default y 1794 default y
>> 1795 select CPU_NOP_WORKAROUNDS
>> 1796 select CPU_JUMP_WORKAROUNDS
1009 help 1797 help
1010 This option adds the workaround for !! 1798 Loongson 2F01 / 2F02 processors have the NOP & JUMP issues which
>> 1799 require workarounds. Without workarounds the system may hang
>> 1800 unexpectedly. For more information please refer to the gas
>> 1801 -mfix-loongson2f-nop and -mfix-loongson2f-jump options.
>> 1802
>> 1803 Loongson 2F03 and later have fixed these issues and no workarounds
>> 1804 are needed. The workarounds have no significant side effect on them
>> 1805 but may decrease the performance of the system so this option should
>> 1806 be disabled unless the kernel is intended to be run on 2F01 or 2F02
>> 1807 systems.
1011 1808
1012 Affected Cortex-A510 core might cau !! 1809 If unsure, please say Y.
1013 into the memory. Effectively TRBE i !! 1810 endif # CPU_LOONGSON2F
1014 trace data. <<
1015 1811
1016 Work around this problem in the dri !! 1812 config SYS_SUPPORTS_ZBOOT
1017 affected cpus. The firmware must ha !! 1813 bool
1018 on such implementations. This will !! 1814 select HAVE_KERNEL_GZIP
1019 do this already. !! 1815 select HAVE_KERNEL_BZIP2
>> 1816 select HAVE_KERNEL_LZ4
>> 1817 select HAVE_KERNEL_LZMA
>> 1818 select HAVE_KERNEL_LZO
>> 1819 select HAVE_KERNEL_XZ
1020 1820
1021 If unsure, say Y. !! 1821 config SYS_SUPPORTS_ZBOOT_UART16550
>> 1822 bool
>> 1823 select SYS_SUPPORTS_ZBOOT
1022 1824
1023 config ARM64_ERRATUM_2457168 !! 1825 config SYS_SUPPORTS_ZBOOT_UART_PROM
1024 bool "Cortex-A510: 2457168: workaroun !! 1826 bool
1025 depends on ARM64_AMU_EXTN !! 1827 select SYS_SUPPORTS_ZBOOT
1026 default y <<
1027 help <<
1028 This option adds the workaround for <<
1029 1828
1030 The AMU counter AMEVCNTR01 (constan !! 1829 config CPU_LOONGSON2
1031 as the system counter. On affected !! 1830 bool
1032 incorrectly giving a significantly !! 1831 select CPU_SUPPORTS_32BIT_KERNEL
>> 1832 select CPU_SUPPORTS_64BIT_KERNEL
>> 1833 select CPU_SUPPORTS_HIGHMEM
>> 1834 select CPU_SUPPORTS_HUGEPAGES
1033 1835
1034 Work around this problem by returni !! 1836 config CPU_LOONGSON1
1035 key locations that results in disab !! 1837 bool
1036 is the same to firmware disabling a !! 1838 select CPU_MIPS32
>> 1839 select CPU_MIPSR2
>> 1840 select CPU_HAS_PREFETCH
>> 1841 select CPU_SUPPORTS_32BIT_KERNEL
>> 1842 select CPU_SUPPORTS_HIGHMEM
>> 1843 select CPU_SUPPORTS_CPUFREQ
1037 1844
1038 If unsure, say Y. !! 1845 config CPU_BMIPS32_3300
>> 1846 select SMP_UP if SMP
>> 1847 bool
1039 1848
1040 config ARM64_ERRATUM_2645198 !! 1849 config CPU_BMIPS4350
1041 bool "Cortex-A715: 2645198: Workaroun !! 1850 bool
1042 default y !! 1851 select SYS_SUPPORTS_SMP
1043 help !! 1852 select SYS_SUPPORTS_HOTPLUG_CPU
1044 This option adds the workaround for <<
1045 1853
1046 If a Cortex-A715 cpu sees a page ma !! 1854 config CPU_BMIPS4380
1047 to non-executable, it may corrupt t !! 1855 bool
1048 next instruction abort caused by pe !! 1856 select MIPS_L1_CACHE_SHIFT_6
>> 1857 select SYS_SUPPORTS_SMP
>> 1858 select SYS_SUPPORTS_HOTPLUG_CPU
>> 1859 select CPU_HAS_RIXI
1049 1860
1050 Only user-space does executable to !! 1861 config CPU_BMIPS5000
1051 mprotect() system call. Workaround !! 1862 bool
1052 TLB invalidation, for all changes t !! 1863 select MIPS_CPU_SCACHE
>> 1864 select MIPS_L1_CACHE_SHIFT_7
>> 1865 select SYS_SUPPORTS_SMP
>> 1866 select SYS_SUPPORTS_HOTPLUG_CPU
>> 1867 select CPU_HAS_RIXI
1053 1868
1054 If unsure, say Y. !! 1869 config SYS_HAS_CPU_LOONGSON3
>> 1870 bool
>> 1871 select CPU_SUPPORTS_CPUFREQ
>> 1872 select CPU_HAS_RIXI
1055 1873
1056 config ARM64_WORKAROUND_SPECULATIVE_UNPRIV_LO !! 1874 config SYS_HAS_CPU_LOONGSON2E
1057 bool 1875 bool
1058 1876
1059 config ARM64_ERRATUM_2966298 !! 1877 config SYS_HAS_CPU_LOONGSON2F
1060 bool "Cortex-A520: 2966298: workaroun !! 1878 bool
1061 select ARM64_WORKAROUND_SPECULATIVE_U !! 1879 select CPU_SUPPORTS_CPUFREQ
1062 default y !! 1880 select CPU_SUPPORTS_ADDRWINCFG if 64BIT
1063 help !! 1881 select CPU_SUPPORTS_UNCACHED_ACCELERATED
1064 This option adds the workaround for <<
1065 1882
1066 On an affected Cortex-A520 core, a !! 1883 config SYS_HAS_CPU_LOONGSON1B
1067 load might leak data from a privile !! 1884 bool
1068 1885
1069 Work around this problem by executi !! 1886 config SYS_HAS_CPU_LOONGSON1C
>> 1887 bool
1070 1888
1071 If unsure, say Y. !! 1889 config SYS_HAS_CPU_MIPS32_R1
>> 1890 bool
1072 1891
1073 config ARM64_ERRATUM_3117295 !! 1892 config SYS_HAS_CPU_MIPS32_R2
1074 bool "Cortex-A510: 3117295: workaroun !! 1893 bool
1075 select ARM64_WORKAROUND_SPECULATIVE_U <<
1076 default y <<
1077 help <<
1078 This option adds the workaround for <<
1079 1894
1080 On an affected Cortex-A510 core, a !! 1895 config SYS_HAS_CPU_MIPS32_R3_5
1081 load might leak data from a privile !! 1896 bool
1082 1897
1083 Work around this problem by executi !! 1898 config SYS_HAS_CPU_MIPS32_R5
>> 1899 bool
1084 1900
1085 If unsure, say Y. !! 1901 config SYS_HAS_CPU_MIPS32_R6
>> 1902 bool
1086 1903
1087 config ARM64_ERRATUM_3194386 !! 1904 config SYS_HAS_CPU_MIPS64_R1
1088 bool "Cortex-*/Neoverse-*: workaround !! 1905 bool
1089 default y <<
1090 help <<
1091 This option adds the workaround for <<
1092 1906
1093 * ARM Cortex-A76 erratum 3324349 !! 1907 config SYS_HAS_CPU_MIPS64_R2
1094 * ARM Cortex-A77 erratum 3324348 !! 1908 bool
1095 * ARM Cortex-A78 erratum 3324344 <<
1096 * ARM Cortex-A78C erratum 3324346 <<
1097 * ARM Cortex-A78C erratum 3324347 <<
1098 * ARM Cortex-A710 erratam 3324338 <<
1099 * ARM Cortex-A715 errartum 3456084 <<
1100 * ARM Cortex-A720 erratum 3456091 <<
1101 * ARM Cortex-A725 erratum 3456106 <<
1102 * ARM Cortex-X1 erratum 3324344 <<
1103 * ARM Cortex-X1C erratum 3324346 <<
1104 * ARM Cortex-X2 erratum 3324338 <<
1105 * ARM Cortex-X3 erratum 3324335 <<
1106 * ARM Cortex-X4 erratum 3194386 <<
1107 * ARM Cortex-X925 erratum 3324334 <<
1108 * ARM Neoverse-N1 erratum 3324349 <<
1109 * ARM Neoverse N2 erratum 3324339 <<
1110 * ARM Neoverse-N3 erratum 3456111 <<
1111 * ARM Neoverse-V1 erratum 3324341 <<
1112 * ARM Neoverse V2 erratum 3324336 <<
1113 * ARM Neoverse-V3 erratum 3312417 <<
1114 <<
1115 On affected cores "MSR SSBS, #0" in <<
1116 subsequent speculative instructions <<
1117 speculative store bypassing. <<
1118 <<
1119 Work around this problem by placing <<
1120 Instruction Synchronization Barrier <<
1121 SSBS. The presence of the SSBS spec <<
1122 from hwcaps and EL0 reads of ID_AA6 <<
1123 will use the PR_SPEC_STORE_BYPASS p <<
1124 1909
1125 If unsure, say Y. !! 1910 config SYS_HAS_CPU_MIPS64_R6
>> 1911 bool
1126 1912
1127 config CAVIUM_ERRATUM_22375 !! 1913 config SYS_HAS_CPU_R3000
1128 bool "Cavium erratum 22375, 24313" !! 1914 bool
1129 default y <<
1130 help <<
1131 Enable workaround for errata 22375 <<
1132 1915
1133 This implements two gicv3-its errat !! 1916 config SYS_HAS_CPU_TX39XX
1134 with a small impact affecting only !! 1917 bool
1135 1918
1136 erratum 22375: only alloc 8MB tab !! 1919 config SYS_HAS_CPU_VR41XX
1137 erratum 24313: ignore memory acce !! 1920 bool
1138 1921
1139 The fixes are in ITS initialization !! 1922 config SYS_HAS_CPU_R4300
1140 type and table size provided by the !! 1923 bool
1141 1924
1142 If unsure, say Y. !! 1925 config SYS_HAS_CPU_R4X00
>> 1926 bool
1143 1927
1144 config CAVIUM_ERRATUM_23144 !! 1928 config SYS_HAS_CPU_TX49XX
1145 bool "Cavium erratum 23144: ITS SYNC !! 1929 bool
1146 depends on NUMA <<
1147 default y <<
1148 help <<
1149 ITS SYNC command hang for cross nod <<
1150 1930
1151 If unsure, say Y. !! 1931 config SYS_HAS_CPU_R5000
>> 1932 bool
1152 1933
1153 config CAVIUM_ERRATUM_23154 !! 1934 config SYS_HAS_CPU_R5432
1154 bool "Cavium errata 23154 and 38545: !! 1935 bool
1155 default y <<
1156 help <<
1157 The ThunderX GICv3 implementation r <<
1158 reading the IAR status to ensure da <<
1159 (access to icc_iar1_el1 is not sync <<
1160 1936
1161 It also suffers from erratum 38545 !! 1937 config SYS_HAS_CPU_R5500
1162 OcteonTX and OcteonTX2), resulting !! 1938 bool
1163 spuriously presented to the CPU int <<
1164 1939
1165 If unsure, say Y. !! 1940 config SYS_HAS_CPU_R6000
>> 1941 bool
1166 1942
1167 config CAVIUM_ERRATUM_27456 !! 1943 config SYS_HAS_CPU_NEVADA
1168 bool "Cavium erratum 27456: Broadcast !! 1944 bool
1169 default y <<
1170 help <<
1171 On ThunderX T88 pass 1.x through 2. <<
1172 instructions may cause the icache t <<
1173 contains data for a non-current ASI <<
1174 invalidate the icache when changing <<
1175 1945
1176 If unsure, say Y. !! 1946 config SYS_HAS_CPU_R8000
>> 1947 bool
1177 1948
1178 config CAVIUM_ERRATUM_30115 !! 1949 config SYS_HAS_CPU_R10000
1179 bool "Cavium erratum 30115: Guest may !! 1950 bool
1180 default y <<
1181 help <<
1182 On ThunderX T88 pass 1.x through 2. <<
1183 1.2, and T83 Pass 1.0, KVM guest ex <<
1184 interrupts in host. Trapping both G <<
1185 accesses sidesteps the issue. <<
1186 1951
1187 If unsure, say Y. !! 1952 config SYS_HAS_CPU_RM7000
>> 1953 bool
1188 1954
1189 config CAVIUM_TX2_ERRATUM_219 !! 1955 config SYS_HAS_CPU_SB1
1190 bool "Cavium ThunderX2 erratum 219: P !! 1956 bool
1191 default y <<
1192 help <<
1193 On Cavium ThunderX2, a load, store <<
1194 TTBR update and the corresponding c <<
1195 cause a spurious Data Abort to be d <<
1196 the CPU core. <<
1197 <<
1198 Work around the issue by avoiding t <<
1199 trapping KVM guest TTBRx_EL1 writes <<
1200 trap handler performs the correspon <<
1201 instruction and ensures context syn <<
1202 exception return. <<
1203 1957
1204 If unsure, say Y. !! 1958 config SYS_HAS_CPU_CAVIUM_OCTEON
>> 1959 bool
1205 1960
1206 config FUJITSU_ERRATUM_010001 !! 1961 config SYS_HAS_CPU_BMIPS
1207 bool "Fujitsu-A64FX erratum E#010001: !! 1962 bool
1208 default y <<
1209 help <<
1210 This option adds a workaround for F <<
1211 On some variants of the Fujitsu-A64 <<
1212 accesses may cause undefined fault <<
1213 This fault occurs under a specific <<
1214 load/store instruction performs an <<
1215 case-1 TTBR0_EL1 with TCR_EL1.NFD0 <<
1216 case-2 TTBR0_EL2 with TCR_EL2.NFD0 <<
1217 case-3 TTBR1_EL1 with TCR_EL1.NFD1 <<
1218 case-4 TTBR1_EL2 with TCR_EL2.NFD1 <<
1219 1963
1220 The workaround is to ensure these b !! 1964 config SYS_HAS_CPU_BMIPS32_3300
1221 The workaround only affects the Fuj !! 1965 bool
>> 1966 select SYS_HAS_CPU_BMIPS
1222 1967
1223 If unsure, say Y. !! 1968 config SYS_HAS_CPU_BMIPS4350
>> 1969 bool
>> 1970 select SYS_HAS_CPU_BMIPS
1224 1971
1225 config HISILICON_ERRATUM_161600802 !! 1972 config SYS_HAS_CPU_BMIPS4380
1226 bool "Hip07 161600802: Erroneous redi !! 1973 bool
1227 default y !! 1974 select SYS_HAS_CPU_BMIPS
1228 help <<
1229 The HiSilicon Hip07 SoC uses the wr <<
1230 when issued ITS commands such as VM <<
1231 a 128kB offset to be applied to the <<
1232 1975
1233 If unsure, say Y. !! 1976 config SYS_HAS_CPU_BMIPS5000
>> 1977 bool
>> 1978 select SYS_HAS_CPU_BMIPS
1234 1979
1235 config QCOM_FALKOR_ERRATUM_1003 !! 1980 config SYS_HAS_CPU_XLR
1236 bool "Falkor E1003: Incorrect transla !! 1981 bool
1237 default y <<
1238 help <<
1239 On Falkor v1, an incorrect ASID may <<
1240 and BADDR are changed together in T <<
1241 in TTBR1_EL1, this situation only o <<
1242 then only for entries in the walk c <<
1243 is unchanged. Work around the errat <<
1244 entries for the trampoline before e <<
1245 1982
1246 config QCOM_FALKOR_ERRATUM_1009 !! 1983 config SYS_HAS_CPU_XLP
1247 bool "Falkor E1009: Prematurely compl !! 1984 bool
>> 1985
>> 1986 config MIPS_MALTA_PM
>> 1987 depends on MIPS_MALTA
>> 1988 depends on PCI
>> 1989 bool
1248 default y 1990 default y
1249 select ARM64_WORKAROUND_REPEAT_TLBI <<
1250 help <<
1251 On Falkor v1, the CPU may premature <<
1252 TLBI xxIS invalidate maintenance op <<
1253 one more time to fix the issue. <<
1254 1991
1255 If unsure, say Y. !! 1992 #
>> 1993 # CPU may reorder R->R, R->W, W->R, W->W
>> 1994 # Reordering beyond LL and SC is handled in WEAK_REORDERING_BEYOND_LLSC
>> 1995 #
>> 1996 config WEAK_ORDERING
>> 1997 bool
1256 1998
1257 config QCOM_QDF2400_ERRATUM_0065 !! 1999 #
1258 bool "QDF2400 E0065: Incorrect GITS_T !! 2000 # CPU may reorder reads and writes beyond LL/SC
1259 default y !! 2001 # CPU may reorder R->LL, R->LL, W->LL, W->LL, R->SC, R->SC, W->SC, W->SC
1260 help !! 2002 #
1261 On Qualcomm Datacenter Technologies !! 2003 config WEAK_REORDERING_BEYOND_LLSC
1262 ITE size incorrectly. The GITS_TYPE !! 2004 bool
1263 been indicated as 16Bytes (0xf), no !! 2005 endmenu
1264 2006
1265 If unsure, say Y. !! 2007 #
>> 2008 # These two indicate any level of the MIPS32 and MIPS64 architecture
>> 2009 #
>> 2010 config CPU_MIPS32
>> 2011 bool
>> 2012 default y if CPU_MIPS32_R1 || CPU_MIPS32_R2 || CPU_MIPS32_R6
1266 2013
1267 config QCOM_FALKOR_ERRATUM_E1041 !! 2014 config CPU_MIPS64
1268 bool "Falkor E1041: Speculative instr !! 2015 bool
1269 default y !! 2016 default y if CPU_MIPS64_R1 || CPU_MIPS64_R2 || CPU_MIPS64_R6
1270 help <<
1271 Falkor CPU may speculatively fetch <<
1272 memory location when MMU translatio <<
1273 to SCTLR_ELn[M]=0. Prefix an ISB in <<
1274 2017
1275 If unsure, say Y. !! 2018 #
>> 2019 # These two indicate the revision of the architecture, either Release 1 or Release 2
>> 2020 #
>> 2021 config CPU_MIPSR1
>> 2022 bool
>> 2023 default y if CPU_MIPS32_R1 || CPU_MIPS64_R1
1276 2024
1277 config NVIDIA_CARMEL_CNP_ERRATUM !! 2025 config CPU_MIPSR2
1278 bool "NVIDIA Carmel CNP: CNP on Carme !! 2026 bool
1279 default y !! 2027 default y if CPU_MIPS32_R2 || CPU_MIPS64_R2 || CPU_CAVIUM_OCTEON
1280 help !! 2028 select CPU_HAS_RIXI
1281 If CNP is enabled on Carmel cores, !! 2029 select MIPS_SPRAM
1282 invalidate shared TLB entries insta <<
1283 on standard ARM cores. <<
1284 2030
1285 If unsure, say Y. !! 2031 config CPU_MIPSR6
>> 2032 bool
>> 2033 default y if CPU_MIPS32_R6 || CPU_MIPS64_R6
>> 2034 select CPU_HAS_RIXI
>> 2035 select HAVE_ARCH_BITREVERSE
>> 2036 select MIPS_ASID_BITS_VARIABLE
>> 2037 select MIPS_SPRAM
1286 2038
1287 config ROCKCHIP_ERRATUM_3588001 !! 2039 config EVA
1288 bool "Rockchip 3588001: GIC600 can no !! 2040 bool
1289 default y <<
1290 help <<
1291 The Rockchip RK3588 GIC600 SoC inte <<
1292 This means, that its sharability fe <<
1293 is supported by the IP itself. <<
1294 2041
1295 If unsure, say Y. !! 2042 config XPA
>> 2043 bool
1296 2044
1297 config SOCIONEXT_SYNQUACER_PREITS !! 2045 config SYS_SUPPORTS_32BIT_KERNEL
1298 bool "Socionext Synquacer: Workaround !! 2046 bool
1299 default y !! 2047 config SYS_SUPPORTS_64BIT_KERNEL
1300 help !! 2048 bool
1301 Socionext Synquacer SoCs implement !! 2049 config CPU_SUPPORTS_32BIT_KERNEL
1302 MSI doorbell writes with non-zero v !! 2050 bool
>> 2051 config CPU_SUPPORTS_64BIT_KERNEL
>> 2052 bool
>> 2053 config CPU_SUPPORTS_CPUFREQ
>> 2054 bool
>> 2055 config CPU_SUPPORTS_ADDRWINCFG
>> 2056 bool
>> 2057 config CPU_SUPPORTS_HUGEPAGES
>> 2058 bool
>> 2059 config CPU_SUPPORTS_UNCACHED_ACCELERATED
>> 2060 bool
>> 2061 config MIPS_PGD_C0_CONTEXT
>> 2062 bool
>> 2063 default y if 64BIT && CPU_MIPSR2 && !CPU_XLP
1303 2064
1304 If unsure, say Y. !! 2065 #
>> 2066 # Set to y for ptrace access to watch registers.
>> 2067 #
>> 2068 config HARDWARE_WATCHPOINTS
>> 2069 bool
>> 2070 default y if CPU_MIPSR1 || CPU_MIPSR2 || CPU_MIPSR6
1305 2071
1306 endmenu # "ARM errata workarounds via the alt !! 2072 menu "Kernel type"
1307 2073
1308 choice 2074 choice
1309 prompt "Page size" !! 2075 prompt "Kernel code model"
1310 default ARM64_4K_PAGES <<
1311 help 2076 help
1312 Page size (translation granule) con !! 2077 You should only select this option if you have a workload that
1313 !! 2078 actually benefits from 64-bit processing or if your machine has
1314 config ARM64_4K_PAGES !! 2079 large memory. You will only be presented a single option in this
1315 bool "4KB" !! 2080 menu if your system does not support both 32-bit and 64-bit kernels.
1316 select HAVE_PAGE_SIZE_4KB !! 2081
1317 help !! 2082 config 32BIT
1318 This feature enables 4KB pages supp !! 2083 bool "32-bit kernel"
1319 !! 2084 depends on CPU_SUPPORTS_32BIT_KERNEL && SYS_SUPPORTS_32BIT_KERNEL
1320 config ARM64_16K_PAGES !! 2085 select TRAD_SIGNALS
1321 bool "16KB" <<
1322 select HAVE_PAGE_SIZE_16KB <<
1323 help 2086 help
1324 The system will use 16KB pages supp !! 2087 Select this option if you want to build a 32-bit kernel.
1325 requires applications compiled with <<
1326 aligned segments. <<
1327 2088
1328 config ARM64_64K_PAGES !! 2089 config 64BIT
1329 bool "64KB" !! 2090 bool "64-bit kernel"
1330 select HAVE_PAGE_SIZE_64KB !! 2091 depends on CPU_SUPPORTS_64BIT_KERNEL && SYS_SUPPORTS_64BIT_KERNEL
1331 help 2092 help
1332 This feature enables 64KB pages sup !! 2093 Select this option if you want to build a 64-bit kernel.
1333 allowing only two levels of page ta <<
1334 look-up. AArch32 emulation requires <<
1335 with 64K aligned segments. <<
1336 2094
1337 endchoice 2095 endchoice
1338 2096
>> 2097 config KVM_GUEST
>> 2098 bool "KVM Guest Kernel"
>> 2099 depends on BROKEN_ON_SMP
>> 2100 help
>> 2101 Select this option if building a guest kernel for KVM (Trap & Emulate)
>> 2102 mode.
>> 2103
>> 2104 config KVM_GUEST_TIMER_FREQ
>> 2105 int "Count/Compare Timer Frequency (MHz)"
>> 2106 depends on KVM_GUEST
>> 2107 default 100
>> 2108 help
>> 2109 Set this to non-zero if building a guest kernel for KVM to skip RTC
>> 2110 emulation when determining guest CPU Frequency. Instead, the guest's
>> 2111 timer frequency is specified directly.
>> 2112
>> 2113 config MIPS_VA_BITS_48
>> 2114 bool "48 bits virtual memory"
>> 2115 depends on 64BIT
>> 2116 help
>> 2117 Support a maximum at least 48 bits of application virtual memory.
>> 2118 Default is 40 bits or less, depending on the CPU.
>> 2119 This option result in a small memory overhead for page tables.
>> 2120 This option is only supported with 16k and 64k page sizes.
>> 2121 If unsure, say N.
>> 2122
1339 choice 2123 choice
1340 prompt "Virtual address space size" !! 2124 prompt "Kernel page size"
1341 default ARM64_VA_BITS_52 !! 2125 default PAGE_SIZE_4KB
1342 help <<
1343 Allows choosing one of multiple pos <<
1344 space sizes. The level of translati <<
1345 a combination of page size and virt <<
1346 <<
1347 config ARM64_VA_BITS_36 <<
1348 bool "36-bit" if EXPERT <<
1349 depends on PAGE_SIZE_16KB <<
1350 <<
1351 config ARM64_VA_BITS_39 <<
1352 bool "39-bit" <<
1353 depends on PAGE_SIZE_4KB <<
1354 <<
1355 config ARM64_VA_BITS_42 <<
1356 bool "42-bit" <<
1357 depends on PAGE_SIZE_64KB <<
1358 <<
1359 config ARM64_VA_BITS_47 <<
1360 bool "47-bit" <<
1361 depends on PAGE_SIZE_16KB <<
1362 <<
1363 config ARM64_VA_BITS_48 <<
1364 bool "48-bit" <<
1365 <<
1366 config ARM64_VA_BITS_52 <<
1367 bool "52-bit" <<
1368 depends on ARM64_PAN || !ARM64_SW_TTB <<
1369 help <<
1370 Enable 52-bit virtual addressing fo <<
1371 requested via a hint to mmap(). The <<
1372 virtual addresses for its own mappi <<
1373 this feature is available, otherwis <<
1374 <<
1375 NOTE: Enabling 52-bit virtual addre <<
1376 ARMv8.3 Pointer Authentication will <<
1377 reduced from 7 bits to 3 bits, whic <<
1378 impact on its susceptibility to bru <<
1379 2126
1380 If unsure, select 48-bit virtual ad !! 2127 config PAGE_SIZE_4KB
>> 2128 bool "4kB"
>> 2129 depends on !CPU_LOONGSON2 && !CPU_LOONGSON3
>> 2130 depends on !MIPS_VA_BITS_48
>> 2131 help
>> 2132 This option select the standard 4kB Linux page size. On some
>> 2133 R3000-family processors this is the only available page size. Using
>> 2134 4kB page size will minimize memory consumption and is therefore
>> 2135 recommended for low memory systems.
>> 2136
>> 2137 config PAGE_SIZE_8KB
>> 2138 bool "8kB"
>> 2139 depends on CPU_R8000 || CPU_CAVIUM_OCTEON
>> 2140 depends on !MIPS_VA_BITS_48
>> 2141 help
>> 2142 Using 8kB page size will result in higher performance kernel at
>> 2143 the price of higher memory consumption. This option is available
>> 2144 only on R8000 and cnMIPS processors. Note that you will need a
>> 2145 suitable Linux distribution to support this.
>> 2146
>> 2147 config PAGE_SIZE_16KB
>> 2148 bool "16kB"
>> 2149 depends on !CPU_R3000 && !CPU_TX39XX
>> 2150 help
>> 2151 Using 16kB page size will result in higher performance kernel at
>> 2152 the price of higher memory consumption. This option is available on
>> 2153 all non-R3000 family processors. Note that you will need a suitable
>> 2154 Linux distribution to support this.
>> 2155
>> 2156 config PAGE_SIZE_32KB
>> 2157 bool "32kB"
>> 2158 depends on CPU_CAVIUM_OCTEON
>> 2159 depends on !MIPS_VA_BITS_48
>> 2160 help
>> 2161 Using 32kB page size will result in higher performance kernel at
>> 2162 the price of higher memory consumption. This option is available
>> 2163 only on cnMIPS cores. Note that you will need a suitable Linux
>> 2164 distribution to support this.
>> 2165
>> 2166 config PAGE_SIZE_64KB
>> 2167 bool "64kB"
>> 2168 depends on !CPU_R3000 && !CPU_TX39XX && !CPU_R6000
>> 2169 help
>> 2170 Using 64kB page size will result in higher performance kernel at
>> 2171 the price of higher memory consumption. This option is available on
>> 2172 all non-R3000 family processor. Not that at the time of this
>> 2173 writing this option is still high experimental.
1381 2174
1382 endchoice 2175 endchoice
1383 2176
1384 config ARM64_FORCE_52BIT !! 2177 config FORCE_MAX_ZONEORDER
1385 bool "Force 52-bit virtual addresses !! 2178 int "Maximum zone order"
1386 depends on ARM64_VA_BITS_52 && EXPERT !! 2179 range 14 64 if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_64KB
1387 help !! 2180 default "14" if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_64KB
1388 For systems with 52-bit userspace V !! 2181 range 13 64 if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_32KB
1389 to maintain compatibility with olde !! 2182 default "13" if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_32KB
1390 unless a hint is supplied to mmap. !! 2183 range 12 64 if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_16KB
1391 !! 2184 default "12" if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_16KB
1392 This configuration option disables !! 2185 range 11 64
1393 forces all userspace addresses to b !! 2186 default "11"
1394 should only enable this configurati !! 2187 help
1395 memory management code. If unsure s !! 2188 The kernel memory allocator divides physically contiguous memory
>> 2189 blocks into "zones", where each zone is a power of two number of
>> 2190 pages. This option selects the largest power of two that the kernel
>> 2191 keeps in the memory allocator. If you need to allocate very large
>> 2192 blocks of physically contiguous memory, then you may need to
>> 2193 increase this value.
1396 2194
1397 config ARM64_VA_BITS !! 2195 This config option is actually maximum order plus one. For example,
1398 int !! 2196 a value of 11 means that the largest free memory block is 2^10 pages.
1399 default 36 if ARM64_VA_BITS_36 <<
1400 default 39 if ARM64_VA_BITS_39 <<
1401 default 42 if ARM64_VA_BITS_42 <<
1402 default 47 if ARM64_VA_BITS_47 <<
1403 default 48 if ARM64_VA_BITS_48 <<
1404 default 52 if ARM64_VA_BITS_52 <<
1405 2197
1406 choice !! 2198 The page size is not necessarily 4KB. Keep this in mind
1407 prompt "Physical address space size" !! 2199 when choosing a value for this option.
1408 default ARM64_PA_BITS_48 <<
1409 help <<
1410 Choose the maximum physical address <<
1411 support. <<
1412 2200
1413 config ARM64_PA_BITS_48 !! 2201 config BOARD_SCACHE
1414 bool "48-bit" !! 2202 bool
1415 depends on ARM64_64K_PAGES || !ARM64_ <<
1416 <<
1417 config ARM64_PA_BITS_52 <<
1418 bool "52-bit" <<
1419 depends on ARM64_64K_PAGES || ARM64_V <<
1420 depends on ARM64_PAN || !ARM64_SW_TTB <<
1421 help <<
1422 Enable support for a 52-bit physica <<
1423 part of the ARMv8.2-LPA extension. <<
1424 <<
1425 With this enabled, the kernel will <<
1426 do not support ARMv8.2-LPA, but wit <<
1427 minor performance overhead). <<
1428 2203
1429 endchoice !! 2204 config IP22_CPU_SCACHE
>> 2205 bool
>> 2206 select BOARD_SCACHE
1430 2207
1431 config ARM64_PA_BITS !! 2208 #
1432 int !! 2209 # Support for a MIPS32 / MIPS64 style S-caches
1433 default 48 if ARM64_PA_BITS_48 !! 2210 #
1434 default 52 if ARM64_PA_BITS_52 !! 2211 config MIPS_CPU_SCACHE
>> 2212 bool
>> 2213 select BOARD_SCACHE
1435 2214
1436 config ARM64_LPA2 !! 2215 config R5000_CPU_SCACHE
1437 def_bool y !! 2216 bool
1438 depends on ARM64_PA_BITS_52 && !ARM64 !! 2217 select BOARD_SCACHE
1439 2218
1440 choice !! 2219 config RM7000_CPU_SCACHE
1441 prompt "Endianness" !! 2220 bool
1442 default CPU_LITTLE_ENDIAN !! 2221 select BOARD_SCACHE
1443 help <<
1444 Select the endianness of data acces <<
1445 applications will need to be compil <<
1446 that is selected here. <<
1447 2222
1448 config CPU_BIG_ENDIAN !! 2223 config SIBYTE_DMA_PAGEOPS
1449 bool "Build big-endian kernel" !! 2224 bool "Use DMA to clear/copy pages"
1450 # https://github.com/llvm/llvm-projec !! 2225 depends on CPU_SB1
1451 depends on AS_IS_GNU || AS_VERSION >= <<
1452 help 2226 help
1453 Say Y if you plan on running a kern !! 2227 Instead of using the CPU to zero and copy pages, use a Data Mover
>> 2228 channel. These DMA channels are otherwise unused by the standard
>> 2229 SiByte Linux port. Seems to give a small performance benefit.
1454 2230
1455 config CPU_LITTLE_ENDIAN !! 2231 config CPU_HAS_PREFETCH
1456 bool "Build little-endian kernel" !! 2232 bool
1457 help <<
1458 Say Y if you plan on running a kern <<
1459 This is usually the case for distri <<
1460 2233
1461 endchoice !! 2234 config CPU_GENERIC_DUMP_TLB
>> 2235 bool
>> 2236 default y if !(CPU_R3000 || CPU_R6000 || CPU_R8000 || CPU_TX39XX)
1462 2237
1463 config SCHED_MC !! 2238 config CPU_R4K_FPU
1464 bool "Multi-core scheduler support" !! 2239 bool
1465 help !! 2240 default y if !(CPU_R3000 || CPU_R6000 || CPU_TX39XX || CPU_CAVIUM_OCTEON)
1466 Multi-core scheduler support improv <<
1467 making when dealing with multi-core <<
1468 increased overhead in some places. <<
1469 2241
1470 config SCHED_CLUSTER !! 2242 config CPU_R4K_CACHE_TLB
1471 bool "Cluster scheduler support" !! 2243 bool
1472 help !! 2244 default y if !(CPU_R3000 || CPU_R8000 || CPU_SB1 || CPU_TX39XX || CPU_CAVIUM_OCTEON)
1473 Cluster scheduler support improves <<
1474 making when dealing with machines t <<
1475 Cluster usually means a couple of C <<
1476 by sharing mid-level caches, last-l <<
1477 busses. <<
1478 2245
1479 config SCHED_SMT !! 2246 config MIPS_MT_SMP
1480 bool "SMT scheduler support" !! 2247 bool "MIPS MT SMP support (1 TC on each available VPE)"
1481 help !! 2248 depends on SYS_SUPPORTS_MULTITHREADING && !CPU_MIPSR6
1482 Improves the CPU scheduler's decisi !! 2249 select CPU_MIPSR2_IRQ_VI
1483 MultiThreading at a cost of slightl !! 2250 select CPU_MIPSR2_IRQ_EI
1484 places. If unsure say N here. !! 2251 select SYNC_R4K
>> 2252 select MIPS_MT
>> 2253 select SMP
>> 2254 select SMP_UP
>> 2255 select SYS_SUPPORTS_SMP
>> 2256 select SYS_SUPPORTS_SCHED_SMT
>> 2257 select MIPS_PERF_SHARED_TC_COUNTERS
>> 2258 help
>> 2259 This is a kernel model which is known as SMVP. This is supported
>> 2260 on cores with the MT ASE and uses the available VPEs to implement
>> 2261 virtual processors which supports SMP. This is equivalent to the
>> 2262 Intel Hyperthreading feature. For further information go to
>> 2263 <http://www.imgtec.com/mips/mips-multithreading.asp>.
1485 2264
1486 config NR_CPUS !! 2265 config MIPS_MT
1487 int "Maximum number of CPUs (2-4096)" !! 2266 bool
1488 range 2 4096 <<
1489 default "512" <<
1490 2267
1491 config HOTPLUG_CPU !! 2268 config SCHED_SMT
1492 bool "Support for hot-pluggable CPUs" !! 2269 bool "SMT (multithreading) scheduler support"
1493 select GENERIC_IRQ_MIGRATION !! 2270 depends on SYS_SUPPORTS_SCHED_SMT
>> 2271 default n
1494 help 2272 help
1495 Say Y here to experiment with turni !! 2273 SMT scheduler support improves the CPU scheduler's decision making
1496 can be controlled through /sys/devi !! 2274 when dealing with MIPS MT enabled cores at a cost of slightly
>> 2275 increased overhead in some places. If unsure say N here.
1497 2276
1498 # Common NUMA Features !! 2277 config SYS_SUPPORTS_SCHED_SMT
1499 config NUMA !! 2278 bool
1500 bool "NUMA Memory Allocation and Sche <<
1501 select GENERIC_ARCH_NUMA <<
1502 select OF_NUMA <<
1503 select HAVE_SETUP_PER_CPU_AREA <<
1504 select NEED_PER_CPU_EMBED_FIRST_CHUNK <<
1505 select NEED_PER_CPU_PAGE_FIRST_CHUNK <<
1506 select USE_PERCPU_NUMA_NODE_ID <<
1507 help <<
1508 Enable NUMA (Non-Uniform Memory Acc <<
1509 <<
1510 The kernel will try to allocate mem <<
1511 local memory of the CPU and add som <<
1512 NUMA awareness to the kernel. <<
1513 2279
1514 config NODES_SHIFT !! 2280 config SYS_SUPPORTS_MULTITHREADING
1515 int "Maximum NUMA Nodes (as a power o !! 2281 bool
1516 range 1 10 <<
1517 default "4" <<
1518 depends on NUMA <<
1519 help <<
1520 Specify the maximum number of NUMA <<
1521 system. Increases memory reserved <<
1522 2282
1523 source "kernel/Kconfig.hz" !! 2283 config MIPS_MT_FPAFF
>> 2284 bool "Dynamic FPU affinity for FP-intensive threads"
>> 2285 default y
>> 2286 depends on MIPS_MT_SMP
1524 2287
1525 config ARCH_SPARSEMEM_ENABLE !! 2288 config MIPSR2_TO_R6_EMULATOR
1526 def_bool y !! 2289 bool "MIPS R2-to-R6 emulator"
1527 select SPARSEMEM_VMEMMAP_ENABLE !! 2290 depends on CPU_MIPSR6 && !SMP
1528 select SPARSEMEM_VMEMMAP !! 2291 default y
>> 2292 help
>> 2293 Choose this option if you want to run non-R6 MIPS userland code.
>> 2294 Even if you say 'Y' here, the emulator will still be disabled by
>> 2295 default. You can enable it using the 'mipsr2emu' kernel option.
>> 2296 The only reason this is a build-time option is to save ~14K from the
>> 2297 final kernel image.
>> 2298 comment "MIPS R2-to-R6 emulator is only available for UP kernels"
>> 2299 depends on SMP && CPU_MIPSR6
>> 2300
>> 2301 config MIPS_VPE_LOADER
>> 2302 bool "VPE loader support."
>> 2303 depends on SYS_SUPPORTS_MULTITHREADING && MODULES
>> 2304 select CPU_MIPSR2_IRQ_VI
>> 2305 select CPU_MIPSR2_IRQ_EI
>> 2306 select MIPS_MT
>> 2307 help
>> 2308 Includes a loader for loading an elf relocatable object
>> 2309 onto another VPE and running it.
1529 2310
1530 config HW_PERF_EVENTS !! 2311 config MIPS_VPE_LOADER_CMP
1531 def_bool y !! 2312 bool
1532 depends on ARM_PMU !! 2313 default "y"
>> 2314 depends on MIPS_VPE_LOADER && MIPS_CMP
1533 2315
1534 # Supported by clang >= 7.0 or GCC >= 12.0.0 !! 2316 config MIPS_VPE_LOADER_MT
1535 config CC_HAVE_SHADOW_CALL_STACK !! 2317 bool
1536 def_bool $(cc-option, -fsanitize=shad !! 2318 default "y"
>> 2319 depends on MIPS_VPE_LOADER && !MIPS_CMP
1537 2320
1538 config PARAVIRT !! 2321 config MIPS_VPE_LOADER_TOM
1539 bool "Enable paravirtualization code" !! 2322 bool "Load VPE program into memory hidden from linux"
>> 2323 depends on MIPS_VPE_LOADER
>> 2324 default y
1540 help 2325 help
1541 This changes the kernel so it can m !! 2326 The loader can use memory that is present but has been hidden from
1542 under a hypervisor, potentially imp !! 2327 Linux using the kernel command line option "mem=xxMB". It's up to
1543 over full virtualization. !! 2328 you to ensure the amount you put in the option and the space your
>> 2329 program requires is less or equal to the amount physically present.
1544 2330
1545 config PARAVIRT_TIME_ACCOUNTING !! 2331 config MIPS_VPE_APSP_API
1546 bool "Paravirtual steal time accounti !! 2332 bool "Enable support for AP/SP API (RTLX)"
1547 select PARAVIRT !! 2333 depends on MIPS_VPE_LOADER
1548 help 2334 help
1549 Select this option to enable fine g <<
1550 accounting. Time spent executing ot <<
1551 the current vCPU is discounted from <<
1552 that, there can be a small performa <<
1553 <<
1554 If in doubt, say N here. <<
1555 <<
1556 config ARCH_SUPPORTS_KEXEC <<
1557 def_bool PM_SLEEP_SMP <<
1558 <<
1559 config ARCH_SUPPORTS_KEXEC_FILE <<
1560 def_bool y <<
1561 <<
1562 config ARCH_SELECTS_KEXEC_FILE <<
1563 def_bool y <<
1564 depends on KEXEC_FILE <<
1565 select HAVE_IMA_KEXEC if IMA <<
1566 2335
1567 config ARCH_SUPPORTS_KEXEC_SIG !! 2336 config MIPS_VPE_APSP_API_CMP
1568 def_bool y !! 2337 bool
1569 !! 2338 default "y"
1570 config ARCH_SUPPORTS_KEXEC_IMAGE_VERIFY_SIG !! 2339 depends on MIPS_VPE_APSP_API && MIPS_CMP
1571 def_bool y <<
1572 <<
1573 config ARCH_DEFAULT_KEXEC_IMAGE_VERIFY_SIG <<
1574 def_bool y <<
1575 <<
1576 config ARCH_SUPPORTS_CRASH_DUMP <<
1577 def_bool y <<
1578 <<
1579 config ARCH_HAS_GENERIC_CRASHKERNEL_RESERVATI <<
1580 def_bool CRASH_RESERVE <<
1581 <<
1582 config TRANS_TABLE <<
1583 def_bool y <<
1584 depends on HIBERNATION || KEXEC_CORE <<
1585 <<
1586 config XEN_DOM0 <<
1587 def_bool y <<
1588 depends on XEN <<
1589 2340
1590 config XEN !! 2341 config MIPS_VPE_APSP_API_MT
1591 bool "Xen guest support on ARM64" !! 2342 bool
1592 depends on ARM64 && OF !! 2343 default "y"
1593 select SWIOTLB_XEN !! 2344 depends on MIPS_VPE_APSP_API && !MIPS_CMP
1594 select PARAVIRT <<
1595 help <<
1596 Say Y if you want to run Linux in a <<
1597 2345
1598 # include/linux/mmzone.h requires the followi !! 2346 config MIPS_CMP
1599 # !! 2347 bool "MIPS CMP framework support (DEPRECATED)"
1600 # MAX_PAGE_ORDER + PAGE_SHIFT <= SECTION_SI !! 2348 depends on SYS_SUPPORTS_MIPS_CMP && !CPU_MIPSR6
1601 # !! 2349 select SMP
1602 # so the maximum value of MAX_PAGE_ORDER is S !! 2350 select SYNC_R4K
1603 # !! 2351 select SYS_SUPPORTS_SMP
1604 # | SECTION_SIZE_BITS | PAGE_SHIFT | m !! 2352 select WEAK_ORDERING
1605 # ----+-------------------+--------------+--- !! 2353 default n
1606 # 4K | 27 | 12 | <<
1607 # 16K | 27 | 14 | <<
1608 # 64K | 29 | 16 | <<
1609 config ARCH_FORCE_MAX_ORDER <<
1610 int <<
1611 default "13" if ARM64_64K_PAGES <<
1612 default "11" if ARM64_16K_PAGES <<
1613 default "10" <<
1614 help 2354 help
1615 The kernel page allocator limits th !! 2355 Select this if you are using a bootloader which implements the "CMP
1616 contiguous allocations. The limit i !! 2356 framework" protocol (ie. YAMON) and want your kernel to make use of
1617 defines the maximal power of two of !! 2357 its ability to start secondary CPUs.
1618 allocated as a single contiguous bl !! 2358
1619 overriding the default setting when !! 2359 Unless you have a specific need, you should use CONFIG_MIPS_CPS
1620 large blocks of physically contiguo !! 2360 instead of this.
1621 !! 2361
1622 The maximal size of allocation cann !! 2362 config MIPS_CPS
1623 section, so the value of MAX_PAGE_O !! 2363 bool "MIPS Coherent Processing System support"
>> 2364 depends on SYS_SUPPORTS_MIPS_CPS
>> 2365 select MIPS_CM
>> 2366 select MIPS_CPC
>> 2367 select MIPS_CPS_PM if HOTPLUG_CPU
>> 2368 select SMP
>> 2369 select SYNC_R4K if (CEVT_R4K || CSRC_R4K)
>> 2370 select SYS_SUPPORTS_HOTPLUG_CPU
>> 2371 select SYS_SUPPORTS_SMP
>> 2372 select WEAK_ORDERING
>> 2373 help
>> 2374 Select this if you wish to run an SMP kernel across multiple cores
>> 2375 within a MIPS Coherent Processing System. When this option is
>> 2376 enabled the kernel will probe for other cores and boot them with
>> 2377 no external assistance. It is safe to enable this when hardware
>> 2378 support is unavailable.
>> 2379
>> 2380 config MIPS_CPS_PM
>> 2381 depends on MIPS_CPS
>> 2382 select MIPS_CPC
>> 2383 bool
1624 2384
1625 MAX_PAGE_ORDER + PAGE_SHIFT <= SE !! 2385 config MIPS_CM
>> 2386 bool
1626 2387
1627 Don't change if unsure. !! 2388 config MIPS_CPC
>> 2389 bool
1628 2390
1629 config UNMAP_KERNEL_AT_EL0 !! 2391 config SB1_PASS_2_WORKAROUNDS
1630 bool "Unmap kernel when running in us !! 2392 bool
>> 2393 depends on CPU_SB1 && (CPU_SB1_PASS_2_2 || CPU_SB1_PASS_2)
1631 default y 2394 default y
1632 help <<
1633 Speculation attacks against some hi <<
1634 be used to bypass MMU permission ch <<
1635 userspace. This can be defended aga <<
1636 when running in userspace, mapping <<
1637 via a trampoline page in the vector <<
1638 2395
1639 If unsure, say Y. !! 2396 config SB1_PASS_2_1_WORKAROUNDS
1640 !! 2397 bool
1641 config MITIGATE_SPECTRE_BRANCH_HISTORY !! 2398 depends on CPU_SB1 && CPU_SB1_PASS_2
1642 bool "Mitigate Spectre style attacks <<
1643 default y 2399 default y
1644 help <<
1645 Speculation attacks against some hi <<
1646 make use of branch history to influ <<
1647 When taking an exception from user- <<
1648 or a firmware call overwrites the b <<
1649 2400
1650 config RODATA_FULL_DEFAULT_ENABLED <<
1651 bool "Apply r/o permissions of VM are <<
1652 default y <<
1653 help <<
1654 Apply read-only attributes of VM ar <<
1655 the backing pages as well. This pre <<
1656 from being modified (inadvertently <<
1657 mapping of the same memory page. Th <<
1658 be turned off at runtime by passing <<
1659 with rodata=full if this option is <<
1660 2401
1661 This requires the linear region to !! 2402 config ARCH_PHYS_ADDR_T_64BIT
1662 which may adversely affect performa !! 2403 bool
1663 2404
1664 config ARM64_SW_TTBR0_PAN !! 2405 choice
1665 bool "Emulate Privileged Access Never !! 2406 prompt "SmartMIPS or microMIPS ASE support"
1666 depends on !KCSAN <<
1667 help <<
1668 Enabling this option prevents the k <<
1669 user-space memory directly by point <<
1670 zeroed area and reserved ASID. The <<
1671 restore the valid TTBR0_EL1 tempora <<
1672 2407
1673 config ARM64_TAGGED_ADDR_ABI !! 2408 config CPU_NEEDS_NO_SMARTMIPS_OR_MICROMIPS
1674 bool "Enable the tagged user addresse !! 2409 bool "None"
1675 default y <<
1676 help 2410 help
1677 When this option is enabled, user a !! 2411 Select this if you want neither microMIPS nor SmartMIPS support
1678 relaxed ABI via prctl() allowing ta <<
1679 to system calls as pointer argument <<
1680 Documentation/arch/arm64/tagged-add <<
1681 2412
1682 menuconfig COMPAT !! 2413 config CPU_HAS_SMARTMIPS
1683 bool "Kernel support for 32-bit EL0" !! 2414 depends on SYS_SUPPORTS_SMARTMIPS
1684 depends on ARM64_4K_PAGES || EXPERT !! 2415 bool "SmartMIPS"
1685 select HAVE_UID16 !! 2416 help
1686 select OLD_SIGSUSPEND3 !! 2417 SmartMIPS is a extension of the MIPS32 architecture aimed at
1687 select COMPAT_OLD_SIGACTION !! 2418 increased security at both hardware and software level for
>> 2419 smartcards. Enabling this option will allow proper use of the
>> 2420 SmartMIPS instructions by Linux applications. However a kernel with
>> 2421 this option will not work on a MIPS core without SmartMIPS core. If
>> 2422 you don't know you probably don't have SmartMIPS and should say N
>> 2423 here.
>> 2424
>> 2425 config CPU_MICROMIPS
>> 2426 depends on 32BIT && SYS_SUPPORTS_MICROMIPS && !CPU_MIPSR6
>> 2427 bool "microMIPS"
1688 help 2428 help
1689 This option enables support for a 3 !! 2429 When this option is enabled the kernel will be built using the
1690 kernel at EL1. AArch32-specific com !! 2430 microMIPS ISA
1691 the user helper functions, VFP supp <<
1692 handled appropriately by the kernel <<
1693 <<
1694 If you use a page size other than 4 <<
1695 that you will only be able to execu <<
1696 with page size aligned segments. <<
1697 2431
1698 If you want to execute 32-bit users !! 2432 endchoice
1699 2433
1700 if COMPAT !! 2434 config CPU_HAS_MSA
>> 2435 bool "Support for the MIPS SIMD Architecture"
>> 2436 depends on CPU_SUPPORTS_MSA
>> 2437 depends on 64BIT || MIPS_O32_FP64_SUPPORT
>> 2438 help
>> 2439 MIPS SIMD Architecture (MSA) introduces 128 bit wide vector registers
>> 2440 and a set of SIMD instructions to operate on them. When this option
>> 2441 is enabled the kernel will support allocating & switching MSA
>> 2442 vector register contexts. If you know that your kernel will only be
>> 2443 running on CPUs which do not support MSA or that your userland will
>> 2444 not be making use of it then you may wish to say N here to reduce
>> 2445 the size & complexity of your kernel.
1701 2446
1702 config KUSER_HELPERS !! 2447 If unsure, say Y.
1703 bool "Enable kuser helpers page for 3 <<
1704 default y <<
1705 help <<
1706 Warning: disabling this option may <<
1707 2448
1708 Provide kuser helpers to compat tas !! 2449 config CPU_HAS_WB
1709 helper code to userspace in read on !! 2450 bool
1710 to allow userspace to be independen <<
1711 the system. This permits binaries t <<
1712 to ARMv8 without modification. <<
1713 2451
1714 See Documentation/arch/arm/kernel_u !! 2452 config XKS01
>> 2453 bool
1715 2454
1716 However, the fixed address nature o !! 2455 config CPU_HAS_RIXI
1717 by ROP (return orientated programmi !! 2456 bool
1718 exploits. <<
1719 2457
1720 If all of the binaries and librarie !! 2458 #
1721 are built specifically for your pla !! 2459 # Vectored interrupt mode is an R2 feature
1722 these helpers, then you can turn th !! 2460 #
1723 such exploits. However, in that cas !! 2461 config CPU_MIPSR2_IRQ_VI
1724 relying on those helpers is run, it !! 2462 bool
1725 2463
1726 Say N here only if you are absolute !! 2464 #
1727 need these helpers; otherwise, the !! 2465 # Extended interrupt mode is an R2 feature
>> 2466 #
>> 2467 config CPU_MIPSR2_IRQ_EI
>> 2468 bool
1728 2469
1729 config COMPAT_VDSO !! 2470 config CPU_HAS_SYNC
1730 bool "Enable vDSO for 32-bit applicat !! 2471 bool
1731 depends on !CPU_BIG_ENDIAN !! 2472 depends on !CPU_R3000
1732 depends on (CC_IS_CLANG && LD_IS_LLD) <<
1733 select GENERIC_COMPAT_VDSO <<
1734 default y 2473 default y
1735 help <<
1736 Place in the process address space <<
1737 ELF shared object providing fast im <<
1738 and clock_gettime. <<
1739 2474
1740 You must have a 32-bit build of gli !! 2475 #
1741 to seamlessly take advantage of thi !! 2476 # CPU non-features
>> 2477 #
>> 2478 config CPU_DADDI_WORKAROUNDS
>> 2479 bool
1742 2480
1743 config THUMB2_COMPAT_VDSO !! 2481 config CPU_R4000_WORKAROUNDS
1744 bool "Compile the 32-bit vDSO for Thu !! 2482 bool
1745 depends on COMPAT_VDSO !! 2483 select CPU_R4400_WORKAROUNDS
1746 default y <<
1747 help <<
1748 Compile the compat vDSO with '-mthu <<
1749 otherwise with '-marm'. <<
1750 2484
1751 config COMPAT_ALIGNMENT_FIXUPS !! 2485 config CPU_R4400_WORKAROUNDS
1752 bool "Fix up misaligned multi-word lo !! 2486 bool
1753 2487
1754 menuconfig ARMV8_DEPRECATED !! 2488 config MIPS_ASID_SHIFT
1755 bool "Emulate deprecated/obsolete ARM !! 2489 int
1756 depends on SYSCTL !! 2490 default 6 if CPU_R3000 || CPU_TX39XX
1757 help !! 2491 default 4 if CPU_R8000
1758 Legacy software support may require !! 2492 default 0
1759 that have been deprecated or obsole <<
1760 2493
1761 Enable this config to enable select !! 2494 config MIPS_ASID_BITS
1762 features. !! 2495 int
>> 2496 default 0 if MIPS_ASID_BITS_VARIABLE
>> 2497 default 6 if CPU_R3000 || CPU_TX39XX
>> 2498 default 8
1763 2499
1764 If unsure, say Y !! 2500 config MIPS_ASID_BITS_VARIABLE
>> 2501 bool
1765 2502
1766 if ARMV8_DEPRECATED !! 2503 #
>> 2504 # - Highmem only makes sense for the 32-bit kernel.
>> 2505 # - The current highmem code will only work properly on physically indexed
>> 2506 # caches such as R3000, SB1, R7000 or those that look like they're virtually
>> 2507 # indexed such as R4000/R4400 SC and MC versions or R10000. So for the
>> 2508 # moment we protect the user and offer the highmem option only on machines
>> 2509 # where it's known to be safe. This will not offer highmem on a few systems
>> 2510 # such as MIPS32 and MIPS64 CPUs which may have virtual and physically
>> 2511 # indexed CPUs but we're playing safe.
>> 2512 # - We use SYS_SUPPORTS_HIGHMEM to offer highmem only for systems where we
>> 2513 # know they might have memory configurations that could make use of highmem
>> 2514 # support.
>> 2515 #
>> 2516 config HIGHMEM
>> 2517 bool "High Memory Support"
>> 2518 depends on 32BIT && CPU_SUPPORTS_HIGHMEM && SYS_SUPPORTS_HIGHMEM && !CPU_MIPS32_3_5_EVA
1767 2519
1768 config SWP_EMULATION !! 2520 config CPU_SUPPORTS_HIGHMEM
1769 bool "Emulate SWP/SWPB instructions" !! 2521 bool
1770 help <<
1771 ARMv8 obsoletes the use of A32 SWP/ <<
1772 they are always undefined. Say Y he <<
1773 emulation of these instructions for <<
1774 This feature can be controlled at r <<
1775 sysctl which is disabled by default <<
1776 2522
1777 In some older versions of glibc [<= !! 2523 config SYS_SUPPORTS_HIGHMEM
1778 trylock() operations with the assum !! 2524 bool
1779 be preempted. This invalid assumpti <<
1780 with SWP emulation enabled, leading <<
1781 application. <<
1782 2525
1783 NOTE: when accessing uncached share !! 2526 config SYS_SUPPORTS_SMARTMIPS
1784 on an external transaction monitori !! 2527 bool
1785 monitor to maintain update atomicit <<
1786 implement a global monitor, this op <<
1787 perform SWP operations to uncached <<
1788 2528
1789 If unsure, say Y !! 2529 config SYS_SUPPORTS_MICROMIPS
>> 2530 bool
1790 2531
1791 config CP15_BARRIER_EMULATION !! 2532 config SYS_SUPPORTS_MIPS16
1792 bool "Emulate CP15 Barrier instructio !! 2533 bool
1793 help 2534 help
1794 The CP15 barrier instructions - CP1 !! 2535 This option must be set if a kernel might be executed on a MIPS16-
1795 CP15DMB - are deprecated in ARMv8 ( !! 2536 enabled CPU even if MIPS16 is not actually being used. In other
1796 strongly recommended to use the ISB !! 2537 words, it makes the kernel MIPS16-tolerant.
1797 instructions instead. <<
1798 2538
1799 Say Y here to enable software emula !! 2539 config CPU_SUPPORTS_MSA
1800 instructions for AArch32 userspace !! 2540 bool
1801 enabled, CP15 barrier usage is trac <<
1802 identify software that needs updati <<
1803 controlled at runtime with the abi. <<
1804 2541
1805 If unsure, say Y !! 2542 config ARCH_FLATMEM_ENABLE
>> 2543 def_bool y
>> 2544 depends on !NUMA && !CPU_LOONGSON2
1806 2545
1807 config SETEND_EMULATION !! 2546 config ARCH_DISCONTIGMEM_ENABLE
1808 bool "Emulate SETEND instruction" !! 2547 bool
>> 2548 default y if SGI_IP27
1809 help 2549 help
1810 The SETEND instruction alters the d !! 2550 Say Y to support efficient handling of discontiguous physical memory,
1811 AArch32 EL0, and is deprecated in A !! 2551 for architectures which are either NUMA (Non-Uniform Memory Access)
1812 !! 2552 or have huge holes in the physical address space for other reasons.
1813 Say Y here to enable software emula !! 2553 See <file:Documentation/vm/numa> for more.
1814 for AArch32 userspace code. This fe <<
1815 at runtime with the abi.setend sysc <<
1816 2554
1817 Note: All the cpus on the system mu !! 2555 config ARCH_SPARSEMEM_ENABLE
1818 for this feature to be enabled. If !! 2556 bool
1819 endian - is hotplugged in after thi !! 2557 select SPARSEMEM_STATIC
1820 be unexpected results in the applic <<
1821 <<
1822 If unsure, say Y <<
1823 endif # ARMV8_DEPRECATED <<
1824 <<
1825 endif # COMPAT <<
1826 <<
1827 menu "ARMv8.1 architectural features" <<
1828 2558
1829 config ARM64_HW_AFDBM !! 2559 config NUMA
1830 bool "Support for hardware updates of !! 2560 bool "NUMA Support"
1831 default y !! 2561 depends on SYS_SUPPORTS_NUMA
1832 help 2562 help
1833 The ARMv8.1 architecture extensions !! 2563 Say Y to compile the kernel to support NUMA (Non-Uniform Memory
1834 hardware updates of the access and !! 2564 Access). This option improves performance on systems with more
1835 table entries. When enabled in TCR_ !! 2565 than two nodes; on two node systems it is generally better to
1836 capable processors, accesses to pag !! 2566 leave it disabled; on single node systems disable this option
1837 set this bit instead of raising an !! 2567 disabled.
1838 Similarly, writes to read-only page <<
1839 clear the read-only bit (AP[2]) ins <<
1840 permission fault. <<
1841 2568
1842 Kernels built with this configurati !! 2569 config SYS_SUPPORTS_NUMA
1843 to work on pre-ARMv8.1 hardware and !! 2570 bool
1844 minimal. If unsure, say Y. <<
1845 2571
1846 config ARM64_PAN !! 2572 config RELOCATABLE
1847 bool "Enable support for Privileged A !! 2573 bool "Relocatable kernel"
1848 default y !! 2574 depends on SYS_SUPPORTS_RELOCATABLE && (CPU_MIPS32_R2 || CPU_MIPS64_R2 || CPU_MIPS32_R6 || CPU_MIPS64_R6)
1849 help 2575 help
1850 Privileged Access Never (PAN; part !! 2576 This builds a kernel image that retains relocation information
1851 prevents the kernel or hypervisor f !! 2577 so it can be loaded someplace besides the default 1MB.
1852 memory directly. !! 2578 The relocations make the kernel binary about 15% larger,
1853 !! 2579 but are discarded at runtime
1854 Choosing this option will cause any !! 2580
1855 copy_to_user et al) memory access t !! 2581 config RELOCATION_TABLE_SIZE
>> 2582 hex "Relocation table size"
>> 2583 depends on RELOCATABLE
>> 2584 range 0x0 0x01000000
>> 2585 default "0x00100000"
>> 2586 ---help---
>> 2587 A table of relocation data will be appended to the kernel binary
>> 2588 and parsed at boot to fix up the relocated kernel.
1856 2589
1857 The feature is detected at runtime, !! 2590 This option allows the amount of space reserved for the table to be
1858 instruction if the cpu does not imp !! 2591 adjusted, although the default of 1Mb should be ok in most cases.
1859 2592
1860 config AS_HAS_LSE_ATOMICS !! 2593 The build will fail and a valid size suggested if this is too small.
1861 def_bool $(as-instr,.arch_extension l <<
1862 2594
1863 config ARM64_LSE_ATOMICS !! 2595 If unsure, leave at the default value.
1864 bool <<
1865 default ARM64_USE_LSE_ATOMICS <<
1866 depends on AS_HAS_LSE_ATOMICS <<
1867 2596
1868 config ARM64_USE_LSE_ATOMICS !! 2597 config RANDOMIZE_BASE
1869 bool "Atomic instructions" !! 2598 bool "Randomize the address of the kernel image"
1870 default y !! 2599 depends on RELOCATABLE
1871 help !! 2600 ---help---
1872 As part of the Large System Extensi !! 2601 Randomizes the physical and virtual address at which the
1873 atomic instructions that are design !! 2602 kernel image is loaded, as a security feature that
1874 very large systems. !! 2603 deters exploit attempts relying on knowledge of the location
1875 !! 2604 of kernel internals.
1876 Say Y here to make use of these ins <<
1877 atomic routines. This incurs a smal <<
1878 not support these instructions and <<
1879 built with binutils >= 2.25 in orde <<
1880 to be used. <<
1881 2605
1882 endmenu # "ARMv8.1 architectural features" !! 2606 Entropy is generated using any coprocessor 0 registers available.
1883 2607
1884 menu "ARMv8.2 architectural features" !! 2608 The kernel will be offset by up to RANDOMIZE_BASE_MAX_OFFSET.
1885 2609
1886 config AS_HAS_ARMV8_2 !! 2610 If unsure, say N.
1887 def_bool $(cc-option,-Wa$(comma)-marc <<
1888 2611
1889 config AS_HAS_SHA3 !! 2612 config RANDOMIZE_BASE_MAX_OFFSET
1890 def_bool $(as-instr,.arch armv8.2-a+s !! 2613 hex "Maximum kASLR offset" if EXPERT
>> 2614 depends on RANDOMIZE_BASE
>> 2615 range 0x0 0x40000000 if EVA || 64BIT
>> 2616 range 0x0 0x08000000
>> 2617 default "0x01000000"
>> 2618 ---help---
>> 2619 When kASLR is active, this provides the maximum offset that will
>> 2620 be applied to the kernel image. It should be set according to the
>> 2621 amount of physical RAM available in the target system minus
>> 2622 PHYSICAL_START and must be a power of 2.
1891 2623
1892 config ARM64_PMEM !! 2624 This is limited by the size of KSEG0, 256Mb on 32-bit or 1Gb with
1893 bool "Enable support for persistent m !! 2625 EVA or 64-bit. The default is 16Mb.
1894 select ARCH_HAS_PMEM_API <<
1895 select ARCH_HAS_UACCESS_FLUSHCACHE <<
1896 help <<
1897 Say Y to enable support for the per <<
1898 ARMv8.2 DCPoP feature. <<
1899 2626
1900 The feature is detected at runtime, !! 2627 config NODES_SHIFT
1901 operations if DC CVAP is not suppor !! 2628 int
1902 DC CVAP itself if the system does n !! 2629 default "6"
>> 2630 depends on NEED_MULTIPLE_NODES
1903 2631
1904 config ARM64_RAS_EXTN !! 2632 config HW_PERF_EVENTS
1905 bool "Enable support for RAS CPU Exte !! 2633 bool "Enable hardware performance counter support for perf events"
>> 2634 depends on PERF_EVENTS && !OPROFILE && (CPU_MIPS32 || CPU_MIPS64 || CPU_R10000 || CPU_SB1 || CPU_CAVIUM_OCTEON || CPU_XLP || CPU_LOONGSON3)
1906 default y 2635 default y
1907 help 2636 help
1908 CPUs that support the Reliability, !! 2637 Enable hardware performance counter support for perf events. If
1909 (RAS) Extensions, part of ARMv8.2 a !! 2638 disabled, perf events will use software events only.
1910 errors, classify them and report th <<
1911 <<
1912 On CPUs with these extensions syste <<
1913 barriers to determine if faults are <<
1914 classification from a new set of re <<
1915 2639
1916 Selecting this feature will allow t !! 2640 source "mm/Kconfig"
1917 and access the new registers if the <<
1918 Platform RAS features may additiona <<
1919 2641
1920 config ARM64_CNP !! 2642 config SMP
1921 bool "Enable support for Common Not P !! 2643 bool "Multi-Processing support"
1922 default y !! 2644 depends on SYS_SUPPORTS_SMP
1923 depends on ARM64_PAN || !ARM64_SW_TTB <<
1924 help 2645 help
1925 Common Not Private (CNP) allows tra !! 2646 This enables support for systems with more than one CPU. If you have
1926 be shared between different PEs in !! 2647 a system with only one CPU, say N. If you have a system with more
1927 domain, so the hardware can use thi !! 2648 than one CPU, say Y.
1928 caching of such entries in the TLB. !! 2649
>> 2650 If you say N here, the kernel will run on uni- and multiprocessor
>> 2651 machines, but will use only one CPU of a multiprocessor machine. If
>> 2652 you say Y here, the kernel will run on many, but not all,
>> 2653 uniprocessor machines. On a uniprocessor machine, the kernel
>> 2654 will run faster if you say N here.
1929 2655
1930 Selecting this option allows the CN !! 2656 People using multiprocessor machines who say Y here should also say
1931 at runtime, and does not affect PEs !! 2657 Y to "Enhanced Real Time Clock Support", below.
1932 this feature. <<
1933 2658
1934 endmenu # "ARMv8.2 architectural features" !! 2659 See also the SMP-HOWTO available at
>> 2660 <http://www.tldp.org/docs.html#howto>.
1935 2661
1936 menu "ARMv8.3 architectural features" !! 2662 If you don't know what to do here, say N.
1937 2663
1938 config ARM64_PTR_AUTH !! 2664 config HOTPLUG_CPU
1939 bool "Enable support for pointer auth !! 2665 bool "Support for hot-pluggable CPUs"
1940 default y !! 2666 depends on SMP && SYS_SUPPORTS_HOTPLUG_CPU
1941 help 2667 help
1942 Pointer authentication (part of the !! 2668 Say Y here to allow turning CPUs off and on. CPUs can be
1943 instructions for signing and authen !! 2669 controlled through /sys/devices/system/cpu.
1944 keys, which can be used to mitigate !! 2670 (Note: power management support will enable this option
1945 and other attacks. !! 2671 automatically on SMP systems. )
>> 2672 Say N if you want to disable CPU hotplug.
1946 2673
1947 This option enables these instructi !! 2674 config SMP_UP
1948 Choosing this option will cause the !! 2675 bool
1949 for each process at exec() time, wi <<
1950 context-switched along with the pro <<
1951 2676
1952 The feature is detected at runtime. !! 2677 config SYS_SUPPORTS_MIPS_CMP
1953 hardware it will not be advertised !! 2678 bool
1954 be enabled. <<
1955 2679
1956 If the feature is present on the bo !! 2680 config SYS_SUPPORTS_MIPS_CPS
1957 the late CPU will be parked. Also, !! 2681 bool
1958 address auth and the late CPU has t <<
1959 but with the feature disabled. On s <<
1960 not be selected. <<
1961 2682
1962 config ARM64_PTR_AUTH_KERNEL !! 2683 config SYS_SUPPORTS_SMP
1963 bool "Use pointer authentication for !! 2684 bool
1964 default y <<
1965 depends on ARM64_PTR_AUTH <<
1966 depends on (CC_HAS_SIGN_RETURN_ADDRES <<
1967 # Modern compilers insert a .note.gnu <<
1968 # which is only understood by binutil <<
1969 depends on LD_IS_LLD || LD_VERSION >= <<
1970 depends on !CC_IS_CLANG || AS_HAS_CFI <<
1971 depends on (!FUNCTION_GRAPH_TRACER || <<
1972 help <<
1973 If the compiler supports the -mbran <<
1974 -msign-return-address flag (e.g. GC <<
1975 will cause the kernel itself to be <<
1976 protection. In this case, and if th <<
1977 support pointer authentication, the <<
1978 disabled with minimal loss of prote <<
1979 2685
1980 This feature works with FUNCTION_GR !! 2686 config NR_CPUS_DEFAULT_4
1981 DYNAMIC_FTRACE_WITH_ARGS is enabled !! 2687 bool
1982 2688
1983 config CC_HAS_BRANCH_PROT_PAC_RET !! 2689 config NR_CPUS_DEFAULT_8
1984 # GCC 9 or later, clang 8 or later !! 2690 bool
1985 def_bool $(cc-option,-mbranch-protect <<
1986 2691
1987 config CC_HAS_SIGN_RETURN_ADDRESS !! 2692 config NR_CPUS_DEFAULT_16
1988 # GCC 7, 8 !! 2693 bool
1989 def_bool $(cc-option,-msign-return-ad <<
1990 2694
1991 config AS_HAS_ARMV8_3 !! 2695 config NR_CPUS_DEFAULT_32
1992 def_bool $(cc-option,-Wa$(comma)-marc !! 2696 bool
1993 2697
1994 config AS_HAS_CFI_NEGATE_RA_STATE !! 2698 config NR_CPUS_DEFAULT_64
1995 def_bool $(as-instr,.cfi_startproc\n. !! 2699 bool
1996 2700
1997 config AS_HAS_LDAPR !! 2701 config NR_CPUS
1998 def_bool $(as-instr,.arch_extension r !! 2702 int "Maximum number of CPUs (2-256)"
>> 2703 range 2 256
>> 2704 depends on SMP
>> 2705 default "4" if NR_CPUS_DEFAULT_4
>> 2706 default "8" if NR_CPUS_DEFAULT_8
>> 2707 default "16" if NR_CPUS_DEFAULT_16
>> 2708 default "32" if NR_CPUS_DEFAULT_32
>> 2709 default "64" if NR_CPUS_DEFAULT_64
>> 2710 help
>> 2711 This allows you to specify the maximum number of CPUs which this
>> 2712 kernel will support. The maximum supported value is 32 for 32-bit
>> 2713 kernel and 64 for 64-bit kernels; the minimum value which makes
>> 2714 sense is 1 for Qemu (useful only for kernel debugging purposes)
>> 2715 and 2 for all others.
>> 2716
>> 2717 This is purely to save memory - each supported CPU adds
>> 2718 approximately eight kilobytes to the kernel image. For best
>> 2719 performance should round up your number of processors to the next
>> 2720 power of two.
1999 2721
2000 endmenu # "ARMv8.3 architectural features" !! 2722 config MIPS_PERF_SHARED_TC_COUNTERS
>> 2723 bool
2001 2724
2002 menu "ARMv8.4 architectural features" !! 2725 #
>> 2726 # Timer Interrupt Frequency Configuration
>> 2727 #
2003 2728
2004 config ARM64_AMU_EXTN !! 2729 choice
2005 bool "Enable support for the Activity !! 2730 prompt "Timer frequency"
2006 default y !! 2731 default HZ_250
2007 help 2732 help
2008 The activity monitors extension is !! 2733 Allows the configuration of the timer frequency.
2009 by the ARMv8.4 CPU architecture. Th <<
2010 of the activity monitors architectu <<
2011 2734
2012 To enable the use of this extension !! 2735 config HZ_24
>> 2736 bool "24 HZ" if SYS_SUPPORTS_24HZ || SYS_SUPPORTS_ARBIT_HZ
2013 2737
2014 Note that for architectural reasons !! 2738 config HZ_48
2015 support when running on CPUs that p !! 2739 bool "48 HZ" if SYS_SUPPORTS_48HZ || SYS_SUPPORTS_ARBIT_HZ
2016 extension. The required support is <<
2017 * Version 1.5 and later of the AR <<
2018 2740
2019 For kernels that have this configur !! 2741 config HZ_100
2020 firmware, you may need to say N her !! 2742 bool "100 HZ" if SYS_SUPPORTS_100HZ || SYS_SUPPORTS_ARBIT_HZ
2021 Otherwise you may experience firmwa <<
2022 accessing the counter registers. Ev <<
2023 symptoms, the values returned by th <<
2024 correctly reflect reality. Most com <<
2025 indicating that the counter is not <<
2026 2743
2027 config AS_HAS_ARMV8_4 !! 2744 config HZ_128
2028 def_bool $(cc-option,-Wa$(comma)-marc !! 2745 bool "128 HZ" if SYS_SUPPORTS_128HZ || SYS_SUPPORTS_ARBIT_HZ
2029 2746
2030 config ARM64_TLB_RANGE !! 2747 config HZ_250
2031 bool "Enable support for tlbi range f !! 2748 bool "250 HZ" if SYS_SUPPORTS_250HZ || SYS_SUPPORTS_ARBIT_HZ
2032 default y <<
2033 depends on AS_HAS_ARMV8_4 <<
2034 help <<
2035 ARMv8.4-TLBI provides TLBI invalida <<
2036 range of input addresses. <<
2037 2749
2038 The feature introduces new assembly !! 2750 config HZ_256
2039 support when binutils >= 2.30. !! 2751 bool "256 HZ" if SYS_SUPPORTS_256HZ || SYS_SUPPORTS_ARBIT_HZ
2040 2752
2041 endmenu # "ARMv8.4 architectural features" !! 2753 config HZ_1000
>> 2754 bool "1000 HZ" if SYS_SUPPORTS_1000HZ || SYS_SUPPORTS_ARBIT_HZ
2042 2755
2043 menu "ARMv8.5 architectural features" !! 2756 config HZ_1024
>> 2757 bool "1024 HZ" if SYS_SUPPORTS_1024HZ || SYS_SUPPORTS_ARBIT_HZ
2044 2758
2045 config AS_HAS_ARMV8_5 !! 2759 endchoice
2046 def_bool $(cc-option,-Wa$(comma)-marc <<
2047 2760
2048 config ARM64_BTI !! 2761 config SYS_SUPPORTS_24HZ
2049 bool "Branch Target Identification su !! 2762 bool
2050 default y <<
2051 help <<
2052 Branch Target Identification (part <<
2053 provides a mechanism to limit the s <<
2054 branch instructions such as BR or B <<
2055 2763
2056 To make use of BTI on CPUs that sup !! 2764 config SYS_SUPPORTS_48HZ
>> 2765 bool
2057 2766
2058 BTI is intended to provide compleme !! 2767 config SYS_SUPPORTS_100HZ
2059 flow integrity protection mechanism !! 2768 bool
2060 authentication mechanism provided a <<
2061 For this reason, it does not make s <<
2062 also enabling support for pointer a <<
2063 enabling this option you should als <<
2064 2769
2065 Userspace binaries must also be spe !! 2770 config SYS_SUPPORTS_128HZ
2066 this mechanism. If you say N here !! 2771 bool
2067 BTI, such binaries can still run, b <<
2068 enforcement of branch destinations. <<
2069 2772
2070 config ARM64_BTI_KERNEL !! 2773 config SYS_SUPPORTS_250HZ
2071 bool "Use Branch Target Identificatio !! 2774 bool
2072 default y <<
2073 depends on ARM64_BTI <<
2074 depends on ARM64_PTR_AUTH_KERNEL <<
2075 depends on CC_HAS_BRANCH_PROT_PAC_RET <<
2076 # https://gcc.gnu.org/bugzilla/show_b <<
2077 depends on !CC_IS_GCC || GCC_VERSION <<
2078 # https://gcc.gnu.org/bugzilla/show_b <<
2079 depends on !CC_IS_GCC <<
2080 depends on (!FUNCTION_GRAPH_TRACER || <<
2081 help <<
2082 Build the kernel with Branch Target <<
2083 and enable enforcement of this for <<
2084 is enabled and the system supports <<
2085 modular code must have BTI enabled. <<
2086 2775
2087 config CC_HAS_BRANCH_PROT_PAC_RET_BTI !! 2776 config SYS_SUPPORTS_256HZ
2088 # GCC 9 or later, clang 8 or later !! 2777 bool
2089 def_bool $(cc-option,-mbranch-protect <<
2090 2778
2091 config ARM64_E0PD !! 2779 config SYS_SUPPORTS_1000HZ
2092 bool "Enable support for E0PD" !! 2780 bool
2093 default y <<
2094 help <<
2095 E0PD (part of the ARMv8.5 extension <<
2096 that EL0 accesses made via TTBR1 al <<
2097 providing similar benefits to KASLR <<
2098 with lower overhead and without dis <<
2099 kernel memory such as SPE. <<
2100 2781
2101 This option enables E0PD for TTBR1 !! 2782 config SYS_SUPPORTS_1024HZ
>> 2783 bool
2102 2784
2103 config ARM64_AS_HAS_MTE !! 2785 config SYS_SUPPORTS_ARBIT_HZ
2104 # Initial support for MTE went in bin !! 2786 bool
2105 # ".arch armv8.5-a+memtag" below. How !! 2787 default y if !SYS_SUPPORTS_24HZ && \
2106 # as a late addition to the final arc !! 2788 !SYS_SUPPORTS_48HZ && \
2107 # is only supported in the newer 2.32 !! 2789 !SYS_SUPPORTS_100HZ && \
2108 # versions, hence the extra "stgm" in !! 2790 !SYS_SUPPORTS_128HZ && \
2109 def_bool $(as-instr,.arch armv8.5-a+m !! 2791 !SYS_SUPPORTS_250HZ && \
>> 2792 !SYS_SUPPORTS_256HZ && \
>> 2793 !SYS_SUPPORTS_1000HZ && \
>> 2794 !SYS_SUPPORTS_1024HZ
2110 2795
2111 config ARM64_MTE !! 2796 config HZ
2112 bool "Memory Tagging Extension suppor !! 2797 int
2113 default y !! 2798 default 24 if HZ_24
2114 depends on ARM64_AS_HAS_MTE && ARM64_ !! 2799 default 48 if HZ_48
2115 depends on AS_HAS_ARMV8_5 !! 2800 default 100 if HZ_100
2116 depends on AS_HAS_LSE_ATOMICS !! 2801 default 128 if HZ_128
2117 # Required for tag checking in the ua !! 2802 default 250 if HZ_250
2118 depends on ARM64_PAN !! 2803 default 256 if HZ_256
2119 select ARCH_HAS_SUBPAGE_FAULTS !! 2804 default 1000 if HZ_1000
2120 select ARCH_USES_HIGH_VMA_FLAGS !! 2805 default 1024 if HZ_1024
2121 select ARCH_USES_PG_ARCH_2 !! 2806
2122 select ARCH_USES_PG_ARCH_3 !! 2807 config SCHED_HRTICK
2123 help !! 2808 def_bool HIGH_RES_TIMERS
2124 Memory Tagging (part of the ARMv8.5 !! 2809
2125 architectural support for run-time, !! 2810 source "kernel/Kconfig.preempt"
2126 various classes of memory error to !! 2811
2127 to eliminate vulnerabilities arisin !! 2812 config KEXEC
2128 languages. !! 2813 bool "Kexec system call"
>> 2814 select KEXEC_CORE
>> 2815 help
>> 2816 kexec is a system call that implements the ability to shutdown your
>> 2817 current kernel, and to start another kernel. It is like a reboot
>> 2818 but it is independent of the system firmware. And like a reboot
>> 2819 you can start any kernel with it, not just Linux.
>> 2820
>> 2821 The name comes from the similarity to the exec system call.
>> 2822
>> 2823 It is an ongoing process to be certain the hardware in a machine
>> 2824 is properly shutdown, so do not be surprised if this code does not
>> 2825 initially work for you. As of this writing the exact hardware
>> 2826 interface is strongly in flux, so no good recommendation can be
>> 2827 made.
>> 2828
>> 2829 config CRASH_DUMP
>> 2830 bool "Kernel crash dumps"
>> 2831 help
>> 2832 Generate crash dump after being started by kexec.
>> 2833 This should be normally only set in special crash dump kernels
>> 2834 which are loaded in the main kernel with kexec-tools into
>> 2835 a specially reserved region and then later executed after
>> 2836 a crash by kdump/kexec. The crash dump kernel must be compiled
>> 2837 to a memory address not used by the main kernel or firmware using
>> 2838 PHYSICAL_START.
>> 2839
>> 2840 config PHYSICAL_START
>> 2841 hex "Physical address where the kernel is loaded"
>> 2842 default "0xffffffff84000000" if 64BIT
>> 2843 default "0x84000000" if 32BIT
>> 2844 depends on CRASH_DUMP
>> 2845 help
>> 2846 This gives the CKSEG0 or KSEG0 address where the kernel is loaded.
>> 2847 If you plan to use kernel for capturing the crash dump change
>> 2848 this value to start of the reserved region (the "X" value as
>> 2849 specified in the "crashkernel=YM@XM" command line boot parameter
>> 2850 passed to the panic-ed kernel).
>> 2851
>> 2852 config SECCOMP
>> 2853 bool "Enable seccomp to safely compute untrusted bytecode"
>> 2854 depends on PROC_FS
>> 2855 default y
>> 2856 help
>> 2857 This kernel feature is useful for number crunching applications
>> 2858 that may need to compute untrusted bytecode during their
>> 2859 execution. By using pipes or other transports made available to
>> 2860 the process as file descriptors supporting the read/write
>> 2861 syscalls, it's possible to isolate those applications in
>> 2862 their own address space using seccomp. Once seccomp is
>> 2863 enabled via /proc/<pid>/seccomp, it cannot be disabled
>> 2864 and the task is only allowed to execute a few safe syscalls
>> 2865 defined by each seccomp mode.
>> 2866
>> 2867 If unsure, say Y. Only embedded should say N here.
>> 2868
>> 2869 config MIPS_O32_FP64_SUPPORT
>> 2870 bool "Support for O32 binaries using 64-bit FP"
>> 2871 depends on 32BIT || MIPS32_O32
>> 2872 help
>> 2873 When this is enabled, the kernel will support use of 64-bit floating
>> 2874 point registers with binaries using the O32 ABI along with the
>> 2875 EF_MIPS_FP64 ELF header flag (typically built with -mfp64). On
>> 2876 32-bit MIPS systems this support is at the cost of increasing the
>> 2877 size and complexity of the compiled FPU emulator. Thus if you are
>> 2878 running a MIPS32 system and know that none of your userland binaries
>> 2879 will require 64-bit floating point, you may wish to reduce the size
>> 2880 of your kernel & potentially improve FP emulation performance by
>> 2881 saying N here.
>> 2882
>> 2883 Although binutils currently supports use of this flag the details
>> 2884 concerning its effect upon the O32 ABI in userland are still being
>> 2885 worked on. In order to avoid userland becoming dependant upon current
>> 2886 behaviour before the details have been finalised, this option should
>> 2887 be considered experimental and only enabled by those working upon
>> 2888 said details.
2129 2889
2130 This option enables the support for !! 2890 If unsure, say N.
2131 Extension at EL0 (i.e. for userspac <<
2132 2891
2133 Selecting this option allows the fe !! 2892 config USE_OF
2134 runtime. Any secondary CPU not impl !! 2893 bool
2135 not be allowed a late bring-up. !! 2894 select OF
>> 2895 select OF_EARLY_FLATTREE
>> 2896 select IRQ_DOMAIN
2136 2897
2137 Userspace binaries that want to use !! 2898 config BUILTIN_DTB
2138 explicitly opt in. The mechanism fo !! 2899 bool
2139 described in: <<
2140 2900
2141 Documentation/arch/arm64/memory-tag !! 2901 choice
>> 2902 prompt "Kernel appended dtb support" if USE_OF
>> 2903 default MIPS_NO_APPENDED_DTB
2142 2904
2143 endmenu # "ARMv8.5 architectural features" !! 2905 config MIPS_NO_APPENDED_DTB
>> 2906 bool "None"
>> 2907 help
>> 2908 Do not enable appended dtb support.
>> 2909
>> 2910 config MIPS_ELF_APPENDED_DTB
>> 2911 bool "vmlinux"
>> 2912 help
>> 2913 With this option, the boot code will look for a device tree binary
>> 2914 DTB) included in the vmlinux ELF section .appended_dtb. By default
>> 2915 it is empty and the DTB can be appended using binutils command
>> 2916 objcopy:
>> 2917
>> 2918 objcopy --update-section .appended_dtb=<filename>.dtb vmlinux
>> 2919
>> 2920 This is meant as a backward compatiblity convenience for those
>> 2921 systems with a bootloader that can't be upgraded to accommodate
>> 2922 the documented boot protocol using a device tree.
>> 2923
>> 2924 config MIPS_RAW_APPENDED_DTB
>> 2925 bool "vmlinux.bin or vmlinuz.bin"
>> 2926 help
>> 2927 With this option, the boot code will look for a device tree binary
>> 2928 DTB) appended to raw vmlinux.bin or vmlinuz.bin.
>> 2929 (e.g. cat vmlinux.bin <filename>.dtb > vmlinux_w_dtb).
>> 2930
>> 2931 This is meant as a backward compatibility convenience for those
>> 2932 systems with a bootloader that can't be upgraded to accommodate
>> 2933 the documented boot protocol using a device tree.
>> 2934
>> 2935 Beware that there is very little in terms of protection against
>> 2936 this option being confused by leftover garbage in memory that might
>> 2937 look like a DTB header after a reboot if no actual DTB is appended
>> 2938 to vmlinux.bin. Do not leave this option active in a production kernel
>> 2939 if you don't intend to always append a DTB.
>> 2940 endchoice
2144 2941
2145 menu "ARMv8.7 architectural features" !! 2942 choice
>> 2943 prompt "Kernel command line type" if !CMDLINE_OVERRIDE
>> 2944 default MIPS_CMDLINE_FROM_DTB if USE_OF && !ATH79 && !MACH_INGENIC && \
>> 2945 !MIPS_MALTA && \
>> 2946 !CAVIUM_OCTEON_SOC
>> 2947 default MIPS_CMDLINE_FROM_BOOTLOADER
>> 2948
>> 2949 config MIPS_CMDLINE_FROM_DTB
>> 2950 depends on USE_OF
>> 2951 bool "Dtb kernel arguments if available"
>> 2952
>> 2953 config MIPS_CMDLINE_DTB_EXTEND
>> 2954 depends on USE_OF
>> 2955 bool "Extend dtb kernel arguments with bootloader arguments"
>> 2956
>> 2957 config MIPS_CMDLINE_FROM_BOOTLOADER
>> 2958 bool "Bootloader kernel arguments if available"
>> 2959
>> 2960 config MIPS_CMDLINE_BUILTIN_EXTEND
>> 2961 depends on CMDLINE_BOOL
>> 2962 bool "Extend builtin kernel arguments with bootloader arguments"
>> 2963 endchoice
2146 2964
2147 config ARM64_EPAN !! 2965 endmenu
2148 bool "Enable support for Enhanced Pri <<
2149 default y <<
2150 depends on ARM64_PAN <<
2151 help <<
2152 Enhanced Privileged Access Never (E <<
2153 Access Never to be used with Execut <<
2154 2966
2155 The feature is detected at runtime, !! 2967 config LOCKDEP_SUPPORT
2156 if the cpu does not implement the f !! 2968 bool
2157 endmenu # "ARMv8.7 architectural features" !! 2969 default y
2158 2970
2159 menu "ARMv8.9 architectural features" !! 2971 config STACKTRACE_SUPPORT
>> 2972 bool
>> 2973 default y
2160 2974
2161 config ARM64_POE !! 2975 config HAVE_LATENCYTOP_SUPPORT
2162 prompt "Permission Overlay Extension" !! 2976 bool
2163 def_bool y !! 2977 default y
2164 select ARCH_USES_HIGH_VMA_FLAGS <<
2165 select ARCH_HAS_PKEYS <<
2166 help <<
2167 The Permission Overlay Extension is <<
2168 Protection Keys. Memory Protection <<
2169 enforcing page-based protections, b <<
2170 of the page tables when an applicat <<
2171 2978
2172 For details, see Documentation/core !! 2979 config PGTABLE_LEVELS
>> 2980 int
>> 2981 default 3 if 64BIT && !PAGE_SIZE_64KB
>> 2982 default 2
2173 2983
2174 If unsure, say y. !! 2984 source "init/Kconfig"
2175 2985
2176 config ARCH_PKEY_BITS !! 2986 source "kernel/Kconfig.freezer"
2177 int <<
2178 default 3 <<
2179 2987
2180 endmenu # "ARMv8.9 architectural features" !! 2988 menu "Bus options (PCI, PCMCIA, EISA, ISA, TC)"
2181 2989
2182 config ARM64_SVE !! 2990 config HW_HAS_EISA
2183 bool "ARM Scalable Vector Extension s !! 2991 bool
2184 default y !! 2992 config HW_HAS_PCI
2185 help !! 2993 bool
2186 The Scalable Vector Extension (SVE) <<
2187 execution state which complements a <<
2188 of the base architecture to support <<
2189 additional vectorisation opportunit <<
2190 2994
2191 To enable use of this extension on !! 2995 config PCI
>> 2996 bool "Support for PCI controller"
>> 2997 depends on HW_HAS_PCI
>> 2998 select PCI_DOMAINS
>> 2999 help
>> 3000 Find out whether you have a PCI motherboard. PCI is the name of a
>> 3001 bus system, i.e. the way the CPU talks to the other stuff inside
>> 3002 your box. Other bus systems are ISA, EISA, or VESA. If you have PCI,
>> 3003 say Y, otherwise N.
>> 3004
>> 3005 config HT_PCI
>> 3006 bool "Support for HT-linked PCI"
>> 3007 default y
>> 3008 depends on CPU_LOONGSON3
>> 3009 select PCI
>> 3010 select PCI_DOMAINS
>> 3011 help
>> 3012 Loongson family machines use Hyper-Transport bus for inter-core
>> 3013 connection and device connection. The PCI bus is a subordinate
>> 3014 linked at HT. Choose Y for Loongson-3 based machines.
2192 3015
2193 On CPUs that support the SVE2 exten !! 3016 config PCI_DOMAINS
2194 those too. !! 3017 bool
2195 3018
2196 Note that for architectural reasons !! 3019 config PCI_DOMAINS_GENERIC
2197 support when running on SVE capable !! 3020 bool
2198 is present in: <<
2199 3021
2200 * version 1.5 and later of the AR !! 3022 config PCI_DRIVERS_GENERIC
2201 * the AArch64 boot wrapper since !! 3023 select PCI_DOMAINS_GENERIC if PCI_DOMAINS
2202 ("bootwrapper: SVE: Enable SVE !! 3024 bool
2203 3025
2204 For other firmware implementations, !! 3026 config PCI_DRIVERS_LEGACY
2205 or vendor. !! 3027 def_bool !PCI_DRIVERS_GENERIC
>> 3028 select NO_GENERIC_PCI_IOPORT_MAP
2206 3029
2207 If you need the kernel to boot on S !! 3030 source "drivers/pci/Kconfig"
2208 firmware, you may need to say N her <<
2209 fixed. Otherwise, you may experien <<
2210 booting the kernel. If unsure and <<
2211 symptoms, you should assume that it <<
2212 3031
2213 config ARM64_SME !! 3032 #
2214 bool "ARM Scalable Matrix Extension s !! 3033 # ISA support is now enabled via select. Too many systems still have the one
2215 default y !! 3034 # or other ISA chip on the board that users don't know about so don't expect
2216 depends on ARM64_SVE !! 3035 # users to choose the right thing ...
2217 depends on BROKEN !! 3036 #
2218 help !! 3037 config ISA
2219 The Scalable Matrix Extension (SME) !! 3038 bool
2220 execution state which utilises a su <<
2221 instruction set, together with the <<
2222 register state capable of holding t <<
2223 enable various matrix operations. <<
2224 3039
2225 config ARM64_PSEUDO_NMI !! 3040 config EISA
2226 bool "Support for NMI-like interrupts !! 3041 bool "EISA support"
2227 select ARM_GIC_V3 !! 3042 depends on HW_HAS_EISA
2228 help !! 3043 select ISA
2229 Adds support for mimicking Non-Mask !! 3044 select GENERIC_ISA_DMA
2230 GIC interrupt priority. This suppor !! 3045 ---help---
2231 ARM GIC. !! 3046 The Extended Industry Standard Architecture (EISA) bus was
>> 3047 developed as an open alternative to the IBM MicroChannel bus.
>> 3048
>> 3049 The EISA bus provided some of the features of the IBM MicroChannel
>> 3050 bus while maintaining backward compatibility with cards made for
>> 3051 the older ISA bus. The EISA bus saw limited use between 1988 and
>> 3052 1995 when it was made obsolete by the PCI bus.
>> 3053
>> 3054 Say Y here if you are building a kernel for an EISA-based machine.
>> 3055
>> 3056 Otherwise, say N.
>> 3057
>> 3058 source "drivers/eisa/Kconfig"
>> 3059
>> 3060 config TC
>> 3061 bool "TURBOchannel support"
>> 3062 depends on MACH_DECSTATION
>> 3063 help
>> 3064 TURBOchannel is a DEC (now Compaq (now HP)) bus for Alpha and MIPS
>> 3065 processors. TURBOchannel programming specifications are available
>> 3066 at:
>> 3067 <ftp://ftp.hp.com/pub/alphaserver/archive/triadd/>
>> 3068 and:
>> 3069 <http://www.computer-refuge.org/classiccmp/ftp.digital.com/pub/DEC/TriAdd/>
>> 3070 Linux driver support status is documented at:
>> 3071 <http://www.linux-mips.org/wiki/DECstation>
2232 3072
2233 This high priority configuration fo !! 3073 config MMU
2234 explicitly enabled by setting the k !! 3074 bool
2235 "irqchip.gicv3_pseudo_nmi" to 1. !! 3075 default y
2236 3076
2237 If unsure, say N !! 3077 config I8253
>> 3078 bool
>> 3079 select CLKSRC_I8253
>> 3080 select CLKEVT_I8253
>> 3081 select MIPS_EXTERNAL_TIMER
2238 3082
2239 if ARM64_PSEUDO_NMI !! 3083 config ZONE_DMA
2240 config ARM64_DEBUG_PRIORITY_MASKING !! 3084 bool
2241 bool "Debug interrupt priority maskin <<
2242 help <<
2243 This adds runtime checks to functio <<
2244 interrupts when using priority mask <<
2245 the validity of ICC_PMR_EL1 when ca <<
2246 3085
2247 If unsure, say N !! 3086 config ZONE_DMA32
2248 endif # ARM64_PSEUDO_NMI !! 3087 bool
2249 3088
2250 config RELOCATABLE !! 3089 source "drivers/pcmcia/Kconfig"
2251 bool "Build a relocatable kernel imag <<
2252 select ARCH_HAS_RELR <<
2253 default y <<
2254 help <<
2255 This builds the kernel as a Positio <<
2256 which retains all relocation metada <<
2257 kernel binary at runtime to a diffe <<
2258 address it was linked at. <<
2259 Since AArch64 uses the RELA relocat <<
2260 relocation pass at runtime even if <<
2261 same address it was linked at. <<
2262 3090
2263 config RANDOMIZE_BASE !! 3091 config RAPIDIO
2264 bool "Randomize the address of the ke !! 3092 tristate "RapidIO support"
2265 select RELOCATABLE !! 3093 depends on PCI
>> 3094 default n
2266 help 3095 help
2267 Randomizes the virtual address at w !! 3096 If you say Y here, the kernel will include drivers and
2268 loaded, as a security feature that !! 3097 infrastructure code to support RapidIO interconnect devices.
2269 relying on knowledge of the locatio <<
2270 <<
2271 It is the bootloader's job to provi <<
2272 random u64 value in /chosen/kaslr-s <<
2273 <<
2274 When booting via the UEFI stub, it <<
2275 EFI_RNG_PROTOCOL implementation (if <<
2276 to the kernel proper. In addition, <<
2277 location of the kernel Image as wel <<
2278 3098
2279 If unsure, say N. !! 3099 source "drivers/rapidio/Kconfig"
2280 3100
2281 config RANDOMIZE_MODULE_REGION_FULL !! 3101 endmenu
2282 bool "Randomize the module region ove <<
2283 depends on RANDOMIZE_BASE <<
2284 default y <<
2285 help <<
2286 Randomizes the location of the modu <<
2287 covering the core kernel. This way, <<
2288 to leak information about the locat <<
2289 but it does imply that function cal <<
2290 kernel will need to be resolved via <<
2291 <<
2292 When this option is not set, the mo <<
2293 a limited range that contains the [ <<
2294 core kernel, so branch relocations <<
2295 the region is exhausted. In this pa <<
2296 exhaustion, modules might be able t <<
2297 3102
2298 config CC_HAVE_STACKPROTECTOR_SYSREG !! 3103 menu "Executable file formats"
2299 def_bool $(cc-option,-mstack-protecto <<
2300 3104
2301 config STACKPROTECTOR_PER_TASK !! 3105 source "fs/Kconfig.binfmt"
2302 def_bool y <<
2303 depends on STACKPROTECTOR && CC_HAVE_ <<
2304 3106
2305 config UNWIND_PATCH_PAC_INTO_SCS !! 3107 config TRAD_SIGNALS
2306 bool "Enable shadow call stack dynami !! 3108 bool
2307 # needs Clang with https://github.com <<
2308 depends on CC_IS_CLANG && CLANG_VERSI <<
2309 depends on ARM64_PTR_AUTH_KERNEL && C <<
2310 depends on SHADOW_CALL_STACK <<
2311 select UNWIND_TABLES <<
2312 select DYNAMIC_SCS <<
2313 <<
2314 config ARM64_CONTPTE <<
2315 bool "Contiguous PTE mappings for use <<
2316 depends on TRANSPARENT_HUGEPAGE <<
2317 default y <<
2318 help <<
2319 When enabled, user mappings are con <<
2320 bit, for any mappings that meet the <<
2321 This reduces TLB pressure and impro <<
2322 <<
2323 endmenu # "Kernel Features" <<
2324 <<
2325 menu "Boot options" <<
2326 <<
2327 config ARM64_ACPI_PARKING_PROTOCOL <<
2328 bool "Enable support for the ARM64 AC <<
2329 depends on ACPI <<
2330 help <<
2331 Enable support for the ARM64 ACPI p <<
2332 the kernel will not allow booting t <<
2333 protocol even if the corresponding <<
2334 MADT table. <<
2335 <<
2336 config CMDLINE <<
2337 string "Default kernel command string <<
2338 default "" <<
2339 help <<
2340 Provide a set of default command-li <<
2341 entering them here. As a minimum, y <<
2342 root device (e.g. root=/dev/nfs). <<
2343 3109
2344 choice !! 3110 config MIPS32_COMPAT
2345 prompt "Kernel command line type" !! 3111 bool
2346 depends on CMDLINE != "" <<
2347 default CMDLINE_FROM_BOOTLOADER <<
2348 help <<
2349 Choose how the kernel will handle t <<
2350 command line string. <<
2351 <<
2352 config CMDLINE_FROM_BOOTLOADER <<
2353 bool "Use bootloader kernel arguments <<
2354 help <<
2355 Uses the command-line options passe <<
2356 the boot loader doesn't provide any <<
2357 string provided in CMDLINE will be <<
2358 <<
2359 config CMDLINE_FORCE <<
2360 bool "Always use the default kernel c <<
2361 help <<
2362 Always use the default kernel comma <<
2363 loader passes other arguments to th <<
2364 This is useful if you cannot or don <<
2365 command-line options your boot load <<
2366 3112
2367 endchoice !! 3113 config COMPAT
>> 3114 bool
2368 3115
2369 config EFI_STUB !! 3116 config SYSVIPC_COMPAT
2370 bool 3117 bool
2371 3118
2372 config EFI !! 3119 config MIPS32_O32
2373 bool "UEFI runtime support" !! 3120 bool "Kernel support for o32 binaries"
2374 depends on OF && !CPU_BIG_ENDIAN !! 3121 depends on 64BIT
2375 depends on KERNEL_MODE_NEON !! 3122 select ARCH_WANT_OLD_COMPAT_IPC
2376 select ARCH_SUPPORTS_ACPI !! 3123 select COMPAT
2377 select LIBFDT !! 3124 select MIPS32_COMPAT
2378 select UCS2_STRING !! 3125 select SYSVIPC_COMPAT if SYSVIPC
2379 select EFI_PARAMS_FROM_FDT !! 3126 help
2380 select EFI_RUNTIME_WRAPPERS !! 3127 Select this option if you want to run o32 binaries. These are pure
2381 select EFI_STUB !! 3128 32-bit binaries as used by the 32-bit Linux/MIPS port. Most of
2382 select EFI_GENERIC_STUB !! 3129 existing binaries are in this format.
2383 imply IMA_SECURE_AND_OR_TRUSTED_BOOT <<
2384 default y <<
2385 help <<
2386 This option provides support for ru <<
2387 by UEFI firmware (such as non-volat <<
2388 clock, and platform reset). A UEFI <<
2389 allow the kernel to be booted as an <<
2390 is only useful on systems that have <<
2391 3130
2392 config COMPRESSED_INSTALL !! 3131 If unsure, say Y.
2393 bool "Install compressed image by def <<
2394 help <<
2395 This makes the regular "make instal <<
2396 image we built, not the legacy unco <<
2397 3132
2398 You can check that a compressed ima !! 3133 config MIPS32_N32
2399 "make zinstall" first, and verifyin !! 3134 bool "Kernel support for n32 binaries"
2400 in your environment before making " !! 3135 depends on 64BIT
2401 you. !! 3136 select COMPAT
>> 3137 select MIPS32_COMPAT
>> 3138 select SYSVIPC_COMPAT if SYSVIPC
>> 3139 help
>> 3140 Select this option if you want to run n32 binaries. These are
>> 3141 64-bit binaries using 32-bit quantities for addressing and certain
>> 3142 data that would normally be 64-bit. They are used in special
>> 3143 cases.
2402 3144
2403 config DMI !! 3145 If unsure, say N.
2404 bool "Enable support for SMBIOS (DMI) <<
2405 depends on EFI <<
2406 default y <<
2407 help <<
2408 This enables SMBIOS/DMI feature for <<
2409 3146
2410 This option is only useful on syste !! 3147 config BINFMT_ELF32
2411 However, even with this option, the !! 3148 bool
2412 continue to boot on existing non-UE !! 3149 default y if MIPS32_O32 || MIPS32_N32
>> 3150 select ELFCORE
2413 3151
2414 endmenu # "Boot options" !! 3152 endmenu
2415 3153
2416 menu "Power management options" 3154 menu "Power management options"
2417 3155
2418 source "kernel/power/Kconfig" <<
2419 <<
2420 config ARCH_HIBERNATION_POSSIBLE 3156 config ARCH_HIBERNATION_POSSIBLE
2421 def_bool y 3157 def_bool y
2422 depends on CPU_PM !! 3158 depends on SYS_SUPPORTS_HOTPLUG_CPU || !SMP
2423 <<
2424 config ARCH_HIBERNATION_HEADER <<
2425 def_bool y <<
2426 depends on HIBERNATION <<
2427 3159
2428 config ARCH_SUSPEND_POSSIBLE 3160 config ARCH_SUSPEND_POSSIBLE
2429 def_bool y 3161 def_bool y
>> 3162 depends on SYS_SUPPORTS_HOTPLUG_CPU || !SMP
>> 3163
>> 3164 source "kernel/power/Kconfig"
>> 3165
>> 3166 endmenu
2430 3167
2431 endmenu # "Power management options" !! 3168 config MIPS_EXTERNAL_TIMER
>> 3169 bool
2432 3170
2433 menu "CPU Power Management" 3171 menu "CPU Power Management"
2434 3172
>> 3173 if CPU_SUPPORTS_CPUFREQ && MIPS_EXTERNAL_TIMER
>> 3174 source "drivers/cpufreq/Kconfig"
>> 3175 endif
>> 3176
2435 source "drivers/cpuidle/Kconfig" 3177 source "drivers/cpuidle/Kconfig"
2436 3178
2437 source "drivers/cpufreq/Kconfig" !! 3179 endmenu
>> 3180
>> 3181 source "net/Kconfig"
>> 3182
>> 3183 source "drivers/Kconfig"
>> 3184
>> 3185 source "drivers/firmware/Kconfig"
>> 3186
>> 3187 source "fs/Kconfig"
>> 3188
>> 3189 source "arch/mips/Kconfig.debug"
2438 3190
2439 endmenu # "CPU Power Management" !! 3191 source "security/Kconfig"
2440 3192
2441 source "drivers/acpi/Kconfig" !! 3193 source "crypto/Kconfig"
2442 3194
2443 source "arch/arm64/kvm/Kconfig" !! 3195 source "lib/Kconfig"
2444 3196
>> 3197 source "arch/mips/kvm/Kconfig"
Linux® is a registered trademark of Linus Torvalds in the United States and other countries.
TOMOYO® is a registered trademark of NTT DATA CORPORATION.