1 # SPDX-License-Identifier: GPL-2.0-only !! 1 config MIPS
2 config ARM64 !! 2 bool
3 def_bool y !! 3 default y
4 select ACPI_APMT if ACPI !! 4 select ARCH_SUPPORTS_UPROBES
5 select ACPI_CCA_REQUIRED if ACPI !! 5 select ARCH_MIGHT_HAVE_PC_PARPORT
6 select ACPI_GENERIC_GSI if ACPI !! 6 select ARCH_MIGHT_HAVE_PC_SERIO
7 select ACPI_GTDT if ACPI !! 7 select ARCH_USE_CMPXCHG_LOCKREF if 64BIT
8 select ACPI_HOTPLUG_CPU if ACPI_PROCES !! 8 select ARCH_USE_BUILTIN_BSWAP
9 select ACPI_IORT if ACPI !! 9 select HAVE_CONTEXT_TRACKING
10 select ACPI_REDUCED_HARDWARE_ONLY if A !! 10 select HAVE_GENERIC_DMA_COHERENT
11 select ACPI_MCFG if (ACPI && PCI) !! 11 select HAVE_IDE
12 select ACPI_SPCR_TABLE if ACPI !! 12 select HAVE_IRQ_EXIT_ON_IRQ_STACK
13 select ACPI_PPTT if ACPI !! 13 select HAVE_OPROFILE
14 select ARCH_HAS_DEBUG_WX !! 14 select HAVE_PERF_EVENTS
15 select ARCH_BINFMT_ELF_EXTRA_PHDRS !! 15 select PERF_USE_VMALLOC
16 select ARCH_BINFMT_ELF_STATE <<
17 select ARCH_CORRECT_STACKTRACE_ON_KRET <<
18 select ARCH_ENABLE_HUGEPAGE_MIGRATION <<
19 select ARCH_ENABLE_MEMORY_HOTPLUG <<
20 select ARCH_ENABLE_MEMORY_HOTREMOVE <<
21 select ARCH_ENABLE_SPLIT_PMD_PTLOCK if <<
22 select ARCH_ENABLE_THP_MIGRATION if TR <<
23 select ARCH_HAS_CACHE_LINE_SIZE <<
24 select ARCH_HAS_CURRENT_STACK_POINTER <<
25 select ARCH_HAS_DEBUG_VIRTUAL <<
26 select ARCH_HAS_DEBUG_VM_PGTABLE <<
27 select ARCH_HAS_DMA_OPS if XEN <<
28 select ARCH_HAS_DMA_PREP_COHERENT <<
29 select ARCH_HAS_ACPI_TABLE_UPGRADE if <<
30 select ARCH_HAS_FAST_MULTIPLIER <<
31 select ARCH_HAS_FORTIFY_SOURCE <<
32 select ARCH_HAS_GCOV_PROFILE_ALL <<
33 select ARCH_HAS_GIGANTIC_PAGE <<
34 select ARCH_HAS_KCOV <<
35 select ARCH_HAS_KERNEL_FPU_SUPPORT if <<
36 select ARCH_HAS_KEEPINITRD <<
37 select ARCH_HAS_MEMBARRIER_SYNC_CORE <<
38 select ARCH_HAS_MEM_ENCRYPT <<
39 select ARCH_HAS_NMI_SAFE_THIS_CPU_OPS <<
40 select ARCH_HAS_NON_OVERLAPPING_ADDRES <<
41 select ARCH_HAS_PTE_DEVMAP <<
42 select ARCH_HAS_PTE_SPECIAL <<
43 select ARCH_HAS_HW_PTE_YOUNG <<
44 select ARCH_HAS_SETUP_DMA_OPS <<
45 select ARCH_HAS_SET_DIRECT_MAP <<
46 select ARCH_HAS_SET_MEMORY <<
47 select ARCH_STACKWALK <<
48 select ARCH_HAS_STRICT_KERNEL_RWX <<
49 select ARCH_HAS_STRICT_MODULE_RWX <<
50 select ARCH_HAS_SYNC_DMA_FOR_DEVICE <<
51 select ARCH_HAS_SYNC_DMA_FOR_CPU <<
52 select ARCH_HAS_SYSCALL_WRAPPER <<
53 select ARCH_HAS_TICK_BROADCAST if GENE <<
54 select ARCH_HAS_ZONE_DMA_SET if EXPERT <<
55 select ARCH_HAVE_ELF_PROT <<
56 select ARCH_HAVE_NMI_SAFE_CMPXCHG <<
57 select ARCH_HAVE_TRACE_MMIO_ACCESS <<
58 select ARCH_INLINE_READ_LOCK if !PREEM <<
59 select ARCH_INLINE_READ_LOCK_BH if !PR <<
60 select ARCH_INLINE_READ_LOCK_IRQ if !P <<
61 select ARCH_INLINE_READ_LOCK_IRQSAVE i <<
62 select ARCH_INLINE_READ_UNLOCK if !PRE <<
63 select ARCH_INLINE_READ_UNLOCK_BH if ! <<
64 select ARCH_INLINE_READ_UNLOCK_IRQ if <<
65 select ARCH_INLINE_READ_UNLOCK_IRQREST <<
66 select ARCH_INLINE_WRITE_LOCK if !PREE <<
67 select ARCH_INLINE_WRITE_LOCK_BH if !P <<
68 select ARCH_INLINE_WRITE_LOCK_IRQ if ! <<
69 select ARCH_INLINE_WRITE_LOCK_IRQSAVE <<
70 select ARCH_INLINE_WRITE_UNLOCK if !PR <<
71 select ARCH_INLINE_WRITE_UNLOCK_BH if <<
72 select ARCH_INLINE_WRITE_UNLOCK_IRQ if <<
73 select ARCH_INLINE_WRITE_UNLOCK_IRQRES <<
74 select ARCH_INLINE_SPIN_TRYLOCK if !PR <<
75 select ARCH_INLINE_SPIN_TRYLOCK_BH if <<
76 select ARCH_INLINE_SPIN_LOCK if !PREEM <<
77 select ARCH_INLINE_SPIN_LOCK_BH if !PR <<
78 select ARCH_INLINE_SPIN_LOCK_IRQ if !P <<
79 select ARCH_INLINE_SPIN_LOCK_IRQSAVE i <<
80 select ARCH_INLINE_SPIN_UNLOCK if !PRE <<
81 select ARCH_INLINE_SPIN_UNLOCK_BH if ! <<
82 select ARCH_INLINE_SPIN_UNLOCK_IRQ if <<
83 select ARCH_INLINE_SPIN_UNLOCK_IRQREST <<
84 select ARCH_KEEP_MEMBLOCK <<
85 select ARCH_MHP_MEMMAP_ON_MEMORY_ENABL <<
86 select ARCH_USE_CMPXCHG_LOCKREF <<
87 select ARCH_USE_GNU_PROPERTY <<
88 select ARCH_USE_MEMTEST <<
89 select ARCH_USE_QUEUED_RWLOCKS <<
90 select ARCH_USE_QUEUED_SPINLOCKS <<
91 select ARCH_USE_SYM_ANNOTATIONS <<
92 select ARCH_SUPPORTS_DEBUG_PAGEALLOC <<
93 select ARCH_SUPPORTS_HUGETLBFS <<
94 select ARCH_SUPPORTS_MEMORY_FAILURE <<
95 select ARCH_SUPPORTS_SHADOW_CALL_STACK <<
96 select ARCH_SUPPORTS_LTO_CLANG if CPU_ <<
97 select ARCH_SUPPORTS_LTO_CLANG_THIN <<
98 select ARCH_SUPPORTS_CFI_CLANG <<
99 select ARCH_SUPPORTS_ATOMIC_RMW <<
100 select ARCH_SUPPORTS_INT128 if CC_HAS_ <<
101 select ARCH_SUPPORTS_NUMA_BALANCING <<
102 select ARCH_SUPPORTS_PAGE_TABLE_CHECK <<
103 select ARCH_SUPPORTS_PER_VMA_LOCK <<
104 select ARCH_SUPPORTS_HUGE_PFNMAP if TR <<
105 select ARCH_SUPPORTS_RT <<
106 select ARCH_WANT_BATCHED_UNMAP_TLB_FLU <<
107 select ARCH_WANT_COMPAT_IPC_PARSE_VERS <<
108 select ARCH_WANT_DEFAULT_BPF_JIT <<
109 select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_ <<
110 select ARCH_WANT_FRAME_POINTERS <<
111 select ARCH_WANT_HUGE_PMD_SHARE if ARM <<
112 select ARCH_WANT_LD_ORPHAN_WARN <<
113 select ARCH_WANTS_EXECMEM_LATE if EXEC <<
114 select ARCH_WANTS_NO_INSTR <<
115 select ARCH_WANTS_THP_SWAP if ARM64_4K <<
116 select ARCH_HAS_UBSAN <<
117 select ARM_AMBA <<
118 select ARM_ARCH_TIMER <<
119 select ARM_GIC <<
120 select AUDIT_ARCH_COMPAT_GENERIC <<
121 select ARM_GIC_V2M if PCI <<
122 select ARM_GIC_V3 <<
123 select ARM_GIC_V3_ITS if PCI <<
124 select ARM_PSCI_FW <<
125 select BUILDTIME_TABLE_SORT <<
126 select CLONE_BACKWARDS <<
127 select COMMON_CLK <<
128 select CPU_PM if (SUSPEND || CPU_IDLE) <<
129 select CPUMASK_OFFSTACK if NR_CPUS > 2 <<
130 select CRC32 <<
131 select DCACHE_WORD_ACCESS <<
132 select DYNAMIC_FTRACE if FUNCTION_TRAC <<
133 select DMA_BOUNCE_UNALIGNED_KMALLOC <<
134 select DMA_DIRECT_REMAP <<
135 select EDAC_SUPPORT <<
136 select FRAME_POINTER <<
137 select FUNCTION_ALIGNMENT_4B <<
138 select FUNCTION_ALIGNMENT_8B if DYNAMI <<
139 select GENERIC_ALLOCATOR <<
140 select GENERIC_ARCH_TOPOLOGY <<
141 select GENERIC_CLOCKEVENTS_BROADCAST <<
142 select GENERIC_CPU_AUTOPROBE <<
143 select GENERIC_CPU_DEVICES <<
144 select GENERIC_CPU_VULNERABILITIES <<
145 select GENERIC_EARLY_IOREMAP <<
146 select GENERIC_IDLE_POLL_SETUP <<
147 select GENERIC_IOREMAP <<
148 select GENERIC_IRQ_IPI <<
149 select GENERIC_IRQ_PROBE <<
150 select GENERIC_IRQ_SHOW <<
151 select GENERIC_IRQ_SHOW_LEVEL <<
152 select GENERIC_LIB_DEVMEM_IS_ALLOWED <<
153 select GENERIC_PCI_IOMAP <<
154 select GENERIC_PTDUMP <<
155 select GENERIC_SCHED_CLOCK <<
156 select GENERIC_SMP_IDLE_THREAD <<
157 select GENERIC_TIME_VSYSCALL <<
158 select GENERIC_GETTIMEOFDAY <<
159 select GENERIC_VDSO_TIME_NS <<
160 select HARDIRQS_SW_RESEND <<
161 select HAS_IOPORT <<
162 select HAVE_MOVE_PMD <<
163 select HAVE_MOVE_PUD <<
164 select HAVE_PCI <<
165 select HAVE_ACPI_APEI if (ACPI && EFI) <<
166 select HAVE_ALIGNED_STRUCT_PAGE <<
167 select HAVE_ARCH_AUDITSYSCALL <<
168 select HAVE_ARCH_BITREVERSE <<
169 select HAVE_ARCH_COMPILER_H <<
170 select HAVE_ARCH_HUGE_VMALLOC <<
171 select HAVE_ARCH_HUGE_VMAP <<
172 select HAVE_ARCH_JUMP_LABEL <<
173 select HAVE_ARCH_JUMP_LABEL_RELATIVE <<
174 select HAVE_ARCH_KASAN <<
175 select HAVE_ARCH_KASAN_VMALLOC <<
176 select HAVE_ARCH_KASAN_SW_TAGS <<
177 select HAVE_ARCH_KASAN_HW_TAGS if ARM6 <<
178 # Some instrumentation may be unsound, <<
179 select HAVE_ARCH_KCSAN if EXPERT <<
180 select HAVE_ARCH_KFENCE <<
181 select HAVE_ARCH_KGDB 16 select HAVE_ARCH_KGDB
182 select HAVE_ARCH_MMAP_RND_BITS !! 17 select HAVE_ARCH_MMAP_RND_BITS if MMU
183 select HAVE_ARCH_MMAP_RND_COMPAT_BITS !! 18 select HAVE_ARCH_MMAP_RND_COMPAT_BITS if MMU && COMPAT
184 select HAVE_ARCH_PREL32_RELOCATIONS <<
185 select HAVE_ARCH_RANDOMIZE_KSTACK_OFFS <<
186 select HAVE_ARCH_SECCOMP_FILTER 19 select HAVE_ARCH_SECCOMP_FILTER
187 select HAVE_ARCH_STACKLEAK <<
188 select HAVE_ARCH_THREAD_STRUCT_WHITELI <<
189 select HAVE_ARCH_TRACEHOOK 20 select HAVE_ARCH_TRACEHOOK
190 select HAVE_ARCH_TRANSPARENT_HUGEPAGE !! 21 select HAVE_CBPF_JIT if !CPU_MICROMIPS
191 select HAVE_ARCH_VMAP_STACK !! 22 select HAVE_FUNCTION_TRACER
192 select HAVE_ARM_SMCCC <<
193 select HAVE_ASM_MODVERSIONS <<
194 select HAVE_EBPF_JIT <<
195 select HAVE_C_RECORDMCOUNT <<
196 select HAVE_CMPXCHG_DOUBLE <<
197 select HAVE_CMPXCHG_LOCAL <<
198 select HAVE_CONTEXT_TRACKING_USER <<
199 select HAVE_DEBUG_KMEMLEAK <<
200 select HAVE_DMA_CONTIGUOUS <<
201 select HAVE_DYNAMIC_FTRACE 23 select HAVE_DYNAMIC_FTRACE
202 select HAVE_DYNAMIC_FTRACE_WITH_ARGS \ <<
203 if (GCC_SUPPORTS_DYNAMIC_FTRAC <<
204 CLANG_SUPPORTS_DYNAMIC_FTR <<
205 select HAVE_DYNAMIC_FTRACE_WITH_DIRECT <<
206 if DYNAMIC_FTRACE_WITH_ARGS && <<
207 select HAVE_DYNAMIC_FTRACE_WITH_CALL_O <<
208 if (DYNAMIC_FTRACE_WITH_ARGS & <<
209 (CC_IS_CLANG || !CC_OPTIMI <<
210 select FTRACE_MCOUNT_USE_PATCHABLE_FUN <<
211 if DYNAMIC_FTRACE_WITH_ARGS <<
212 select HAVE_SAMPLE_FTRACE_DIRECT <<
213 select HAVE_SAMPLE_FTRACE_DIRECT_MULTI <<
214 select HAVE_EFFICIENT_UNALIGNED_ACCESS <<
215 select HAVE_GUP_FAST <<
216 select HAVE_FTRACE_MCOUNT_RECORD 24 select HAVE_FTRACE_MCOUNT_RECORD
217 select HAVE_FUNCTION_TRACER !! 25 select HAVE_C_RECORDMCOUNT
218 select HAVE_FUNCTION_ERROR_INJECTION <<
219 select HAVE_FUNCTION_GRAPH_TRACER 26 select HAVE_FUNCTION_GRAPH_TRACER
220 select HAVE_FUNCTION_GRAPH_RETVAL <<
221 select HAVE_GCC_PLUGINS <<
222 select HAVE_HARDLOCKUP_DETECTOR_PERF i <<
223 HW_PERF_EVENTS && HAVE_PERF_EV <<
224 select HAVE_HW_BREAKPOINT if PERF_EVEN <<
225 select HAVE_IOREMAP_PROT <<
226 select HAVE_IRQ_TIME_ACCOUNTING <<
227 select HAVE_MOD_ARCH_SPECIFIC <<
228 select HAVE_NMI <<
229 select HAVE_PERF_EVENTS <<
230 select HAVE_PERF_EVENTS_NMI if ARM64_P <<
231 select HAVE_PERF_REGS <<
232 select HAVE_PERF_USER_STACK_DUMP <<
233 select HAVE_PREEMPT_DYNAMIC_KEY <<
234 select HAVE_REGS_AND_STACK_ACCESS_API <<
235 select HAVE_POSIX_CPU_TIMERS_TASK_WORK <<
236 select HAVE_FUNCTION_ARG_ACCESS_API <<
237 select MMU_GATHER_RCU_TABLE_FREE <<
238 select HAVE_RSEQ <<
239 select HAVE_RUST if RUSTC_SUPPORTS_ARM <<
240 select HAVE_STACKPROTECTOR <<
241 select HAVE_SYSCALL_TRACEPOINTS <<
242 select HAVE_KPROBES 27 select HAVE_KPROBES
243 select HAVE_KRETPROBES 28 select HAVE_KRETPROBES
244 select HAVE_GENERIC_VDSO !! 29 select HAVE_SYSCALL_TRACEPOINTS
245 select HOTPLUG_CORE_SYNC_DEAD if HOTPL !! 30 select HAVE_DEBUG_KMEMLEAK
246 select IRQ_DOMAIN !! 31 select HAVE_SYSCALL_TRACEPOINTS
>> 32 select ARCH_HAS_ELF_RANDOMIZE
>> 33 select HAVE_ARCH_TRANSPARENT_HUGEPAGE if CPU_SUPPORTS_HUGEPAGES && 64BIT
>> 34 select RTC_LIB if !MACH_LOONGSON64
>> 35 select GENERIC_ATOMIC64 if !64BIT
>> 36 select HAVE_DMA_CONTIGUOUS
>> 37 select HAVE_DMA_API_DEBUG
>> 38 select GENERIC_IRQ_PROBE
>> 39 select GENERIC_IRQ_SHOW
>> 40 select GENERIC_PCI_IOMAP
>> 41 select HAVE_ARCH_JUMP_LABEL
>> 42 select ARCH_WANT_IPC_PARSE_VERSION
247 select IRQ_FORCED_THREADING 43 select IRQ_FORCED_THREADING
248 select KASAN_VMALLOC if KASAN !! 44 select HAVE_MEMBLOCK
249 select LOCK_MM_AND_FIND_VMA !! 45 select HAVE_MEMBLOCK_NODE_MAP
250 select MODULES_USE_ELF_RELA !! 46 select ARCH_DISCARD_MEMBLOCK
251 select NEED_DMA_MAP_STATE !! 47 select GENERIC_SMP_IDLE_THREAD
252 select NEED_SG_DMA_LENGTH !! 48 select BUILDTIME_EXTABLE_SORT
253 select OF !! 49 select GENERIC_CPU_AUTOPROBE
254 select OF_EARLY_FLATTREE !! 50 select GENERIC_CLOCKEVENTS
255 select PCI_DOMAINS_GENERIC if PCI !! 51 select GENERIC_SCHED_CLOCK if !CAVIUM_OCTEON_SOC
256 select PCI_ECAM if (ACPI && PCI) !! 52 select GENERIC_CMOS_UPDATE
257 select PCI_SYSCALL if PCI !! 53 select HAVE_MOD_ARCH_SPECIFIC
258 select POWER_RESET !! 54 select HAVE_NMI
259 select POWER_SUPPLY !! 55 select VIRT_TO_BUS
260 select SPARSE_IRQ !! 56 select MODULES_USE_ELF_REL if MODULES
261 select SWIOTLB !! 57 select MODULES_USE_ELF_RELA if MODULES && 64BIT
>> 58 select CLONE_BACKWARDS
>> 59 select HAVE_DEBUG_STACKOVERFLOW
>> 60 select HAVE_CC_STACKPROTECTOR
>> 61 select CPU_PM if CPU_IDLE
>> 62 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
>> 63 select ARCH_BINFMT_ELF_STATE
262 select SYSCTL_EXCEPTION_TRACE 64 select SYSCTL_EXCEPTION_TRACE
263 select THREAD_INFO_IN_TASK !! 65 select HAVE_VIRT_CPU_ACCOUNTING_GEN
264 select HAVE_ARCH_USERFAULTFD_MINOR if !! 66 select HAVE_IRQ_TIME_ACCOUNTING
265 select HAVE_ARCH_USERFAULTFD_WP if USE !! 67 select GENERIC_TIME_VSYSCALL
266 select TRACE_IRQFLAGS_SUPPORT !! 68 select ARCH_CLOCKSOURCE_DATA
267 select TRACE_IRQFLAGS_NMI_SUPPORT !! 69 select HANDLE_DOMAIN_IRQ
268 select HAVE_SOFTIRQ_ON_OWN_STACK !! 70 select HAVE_EXIT_THREAD
269 select USER_STACKTRACE_SUPPORT !! 71 select HAVE_REGS_AND_STACK_ACCESS_API
270 select VDSO_GETRANDOM !! 72 select HAVE_COPY_THREAD_TLS
271 help <<
272 ARM 64-bit (AArch64) Linux support. <<
273 <<
274 config RUSTC_SUPPORTS_ARM64 <<
275 def_bool y <<
276 depends on CPU_LITTLE_ENDIAN <<
277 # Shadow call stack is only supported <<
278 # <<
279 # When using the UNWIND_PATCH_PAC_INTO <<
280 # required due to use of the -Zfixed-x <<
281 # <<
282 # Otherwise, rustc version 1.82+ is re <<
283 # -Zsanitizer=shadow-call-stack flag. <<
284 depends on !SHADOW_CALL_STACK || RUSTC <<
285 <<
286 config CLANG_SUPPORTS_DYNAMIC_FTRACE_WITH_ARGS <<
287 def_bool CC_IS_CLANG <<
288 # https://github.com/ClangBuiltLinux/l <<
289 depends on AS_IS_GNU || (AS_IS_LLVM && <<
290 <<
291 config GCC_SUPPORTS_DYNAMIC_FTRACE_WITH_ARGS <<
292 def_bool CC_IS_GCC <<
293 depends on $(cc-option,-fpatchable-fun <<
294 <<
295 config 64BIT <<
296 def_bool y <<
297 <<
298 config MMU <<
299 def_bool y <<
300 73
301 config ARM64_CONT_PTE_SHIFT !! 74 menu "Machine selection"
302 int <<
303 default 5 if PAGE_SIZE_64KB <<
304 default 7 if PAGE_SIZE_16KB <<
305 default 4 <<
306 75
307 config ARM64_CONT_PMD_SHIFT !! 76 choice
308 int !! 77 prompt "System type"
309 default 5 if PAGE_SIZE_64KB !! 78 default SGI_IP22
310 default 5 if PAGE_SIZE_16KB <<
311 default 4 <<
312 79
313 config ARCH_MMAP_RND_BITS_MIN !! 80 config MIPS_GENERIC
314 default 14 if PAGE_SIZE_64KB !! 81 bool "Generic board-agnostic MIPS kernel"
315 default 16 if PAGE_SIZE_16KB !! 82 select BOOT_RAW
316 default 18 !! 83 select BUILTIN_DTB
>> 84 select CEVT_R4K
>> 85 select CLKSRC_MIPS_GIC
>> 86 select COMMON_CLK
>> 87 select CPU_MIPSR2_IRQ_VI
>> 88 select CPU_MIPSR2_IRQ_EI
>> 89 select CSRC_R4K
>> 90 select DMA_PERDEV_COHERENT
>> 91 select HW_HAS_PCI
>> 92 select IRQ_MIPS_CPU
>> 93 select LIBFDT
>> 94 select MIPS_CPU_SCACHE
>> 95 select MIPS_GIC
>> 96 select MIPS_L1_CACHE_SHIFT_7
>> 97 select NO_EXCEPT_FILL
>> 98 select PCI_DRIVERS_GENERIC
>> 99 select PINCTRL
>> 100 select SMP_UP if SMP
>> 101 select SWAP_IO_SPACE
>> 102 select SYS_HAS_CPU_MIPS32_R1
>> 103 select SYS_HAS_CPU_MIPS32_R2
>> 104 select SYS_HAS_CPU_MIPS32_R6
>> 105 select SYS_HAS_CPU_MIPS64_R1
>> 106 select SYS_HAS_CPU_MIPS64_R2
>> 107 select SYS_HAS_CPU_MIPS64_R6
>> 108 select SYS_SUPPORTS_32BIT_KERNEL
>> 109 select SYS_SUPPORTS_64BIT_KERNEL
>> 110 select SYS_SUPPORTS_BIG_ENDIAN
>> 111 select SYS_SUPPORTS_HIGHMEM
>> 112 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 113 select SYS_SUPPORTS_MICROMIPS
>> 114 select SYS_SUPPORTS_MIPS_CPS
>> 115 select SYS_SUPPORTS_MIPS16
>> 116 select SYS_SUPPORTS_MULTITHREADING
>> 117 select SYS_SUPPORTS_RELOCATABLE
>> 118 select SYS_SUPPORTS_SMARTMIPS
>> 119 select USB_EHCI_BIG_ENDIAN_DESC if BIG_ENDIAN
>> 120 select USB_EHCI_BIG_ENDIAN_MMIO if BIG_ENDIAN
>> 121 select USB_OHCI_BIG_ENDIAN_DESC if BIG_ENDIAN
>> 122 select USB_OHCI_BIG_ENDIAN_MMIO if BIG_ENDIAN
>> 123 select USB_UHCI_BIG_ENDIAN_DESC if BIG_ENDIAN
>> 124 select USB_UHCI_BIG_ENDIAN_MMIO if BIG_ENDIAN
>> 125 select USE_OF
>> 126 help
>> 127 Select this to build a kernel which aims to support multiple boards,
>> 128 generally using a flattened device tree passed from the bootloader
>> 129 using the boot protocol defined in the UHI (Unified Hosting
>> 130 Interface) specification.
>> 131
>> 132 config MIPS_ALCHEMY
>> 133 bool "Alchemy processor based machines"
>> 134 select ARCH_PHYS_ADDR_T_64BIT
>> 135 select CEVT_R4K
>> 136 select CSRC_R4K
>> 137 select IRQ_MIPS_CPU
>> 138 select DMA_MAYBE_COHERENT # Au1000,1500,1100 aren't, rest is
>> 139 select SYS_HAS_CPU_MIPS32_R1
>> 140 select SYS_SUPPORTS_32BIT_KERNEL
>> 141 select SYS_SUPPORTS_APM_EMULATION
>> 142 select GPIOLIB
>> 143 select SYS_SUPPORTS_ZBOOT
>> 144 select COMMON_CLK
317 145
318 # max bits determined by the following formula !! 146 config AR7
319 # VA_BITS - PAGE_SHIFT - 3 !! 147 bool "Texas Instruments AR7"
320 config ARCH_MMAP_RND_BITS_MAX !! 148 select BOOT_ELF32
321 default 19 if ARM64_VA_BITS=36 !! 149 select DMA_NONCOHERENT
322 default 24 if ARM64_VA_BITS=39 !! 150 select CEVT_R4K
323 default 27 if ARM64_VA_BITS=42 !! 151 select CSRC_R4K
324 default 30 if ARM64_VA_BITS=47 !! 152 select IRQ_MIPS_CPU
325 default 29 if ARM64_VA_BITS=48 && ARM6 !! 153 select NO_EXCEPT_FILL
326 default 31 if ARM64_VA_BITS=48 && ARM6 !! 154 select SWAP_IO_SPACE
327 default 33 if ARM64_VA_BITS=48 !! 155 select SYS_HAS_CPU_MIPS32_R1
328 default 14 if ARM64_64K_PAGES !! 156 select SYS_HAS_EARLY_PRINTK
329 default 16 if ARM64_16K_PAGES !! 157 select SYS_SUPPORTS_32BIT_KERNEL
330 default 18 !! 158 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 159 select SYS_SUPPORTS_MIPS16
>> 160 select SYS_SUPPORTS_ZBOOT_UART16550
>> 161 select GPIOLIB
>> 162 select VLYNQ
>> 163 select HAVE_CLK
>> 164 help
>> 165 Support for the Texas Instruments AR7 System-on-a-Chip
>> 166 family: TNETD7100, 7200 and 7300.
>> 167
>> 168 config ATH25
>> 169 bool "Atheros AR231x/AR531x SoC support"
>> 170 select CEVT_R4K
>> 171 select CSRC_R4K
>> 172 select DMA_NONCOHERENT
>> 173 select IRQ_MIPS_CPU
>> 174 select IRQ_DOMAIN
>> 175 select SYS_HAS_CPU_MIPS32_R1
>> 176 select SYS_SUPPORTS_BIG_ENDIAN
>> 177 select SYS_SUPPORTS_32BIT_KERNEL
>> 178 select SYS_HAS_EARLY_PRINTK
>> 179 help
>> 180 Support for Atheros AR231x and Atheros AR531x based boards
>> 181
>> 182 config ATH79
>> 183 bool "Atheros AR71XX/AR724X/AR913X based boards"
>> 184 select ARCH_HAS_RESET_CONTROLLER
>> 185 select BOOT_RAW
>> 186 select CEVT_R4K
>> 187 select CSRC_R4K
>> 188 select DMA_NONCOHERENT
>> 189 select GPIOLIB
>> 190 select HAVE_CLK
>> 191 select COMMON_CLK
>> 192 select CLKDEV_LOOKUP
>> 193 select IRQ_MIPS_CPU
>> 194 select MIPS_MACHINE
>> 195 select SYS_HAS_CPU_MIPS32_R2
>> 196 select SYS_HAS_EARLY_PRINTK
>> 197 select SYS_SUPPORTS_32BIT_KERNEL
>> 198 select SYS_SUPPORTS_BIG_ENDIAN
>> 199 select SYS_SUPPORTS_MIPS16
>> 200 select SYS_SUPPORTS_ZBOOT_UART_PROM
>> 201 select USE_OF
>> 202 help
>> 203 Support for the Atheros AR71XX/AR724X/AR913X SoCs.
>> 204
>> 205 config BMIPS_GENERIC
>> 206 bool "Broadcom Generic BMIPS kernel"
>> 207 select BOOT_RAW
>> 208 select NO_EXCEPT_FILL
>> 209 select USE_OF
>> 210 select CEVT_R4K
>> 211 select CSRC_R4K
>> 212 select SYNC_R4K
>> 213 select COMMON_CLK
>> 214 select BCM6345_L1_IRQ
>> 215 select BCM7038_L1_IRQ
>> 216 select BCM7120_L2_IRQ
>> 217 select BRCMSTB_L2_IRQ
>> 218 select IRQ_MIPS_CPU
>> 219 select DMA_NONCOHERENT
>> 220 select SYS_SUPPORTS_32BIT_KERNEL
>> 221 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 222 select SYS_SUPPORTS_BIG_ENDIAN
>> 223 select SYS_SUPPORTS_HIGHMEM
>> 224 select SYS_HAS_CPU_BMIPS32_3300
>> 225 select SYS_HAS_CPU_BMIPS4350
>> 226 select SYS_HAS_CPU_BMIPS4380
>> 227 select SYS_HAS_CPU_BMIPS5000
>> 228 select SWAP_IO_SPACE
>> 229 select USB_EHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
>> 230 select USB_EHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 231 select USB_OHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
>> 232 select USB_OHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 233 help
>> 234 Build a generic DT-based kernel image that boots on select
>> 235 BCM33xx cable modem chips, BCM63xx DSL chips, and BCM7xxx set-top
>> 236 box chips. Note that CONFIG_CPU_BIG_ENDIAN/CONFIG_CPU_LITTLE_ENDIAN
>> 237 must be set appropriately for your board.
>> 238
>> 239 config BCM47XX
>> 240 bool "Broadcom BCM47XX based boards"
>> 241 select BOOT_RAW
>> 242 select CEVT_R4K
>> 243 select CSRC_R4K
>> 244 select DMA_NONCOHERENT
>> 245 select HW_HAS_PCI
>> 246 select IRQ_MIPS_CPU
>> 247 select SYS_HAS_CPU_MIPS32_R1
>> 248 select NO_EXCEPT_FILL
>> 249 select SYS_SUPPORTS_32BIT_KERNEL
>> 250 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 251 select SYS_SUPPORTS_MIPS16
>> 252 select SYS_HAS_EARLY_PRINTK
>> 253 select USE_GENERIC_EARLY_PRINTK_8250
>> 254 select GPIOLIB
>> 255 select LEDS_GPIO_REGISTER
>> 256 select BCM47XX_NVRAM
>> 257 select BCM47XX_SPROM
>> 258 help
>> 259 Support for BCM47XX based boards
>> 260
>> 261 config BCM63XX
>> 262 bool "Broadcom BCM63XX based boards"
>> 263 select BOOT_RAW
>> 264 select CEVT_R4K
>> 265 select CSRC_R4K
>> 266 select SYNC_R4K
>> 267 select DMA_NONCOHERENT
>> 268 select IRQ_MIPS_CPU
>> 269 select SYS_SUPPORTS_32BIT_KERNEL
>> 270 select SYS_SUPPORTS_BIG_ENDIAN
>> 271 select SYS_HAS_EARLY_PRINTK
>> 272 select SWAP_IO_SPACE
>> 273 select GPIOLIB
>> 274 select HAVE_CLK
>> 275 select MIPS_L1_CACHE_SHIFT_4
>> 276 help
>> 277 Support for BCM63XX based boards
>> 278
>> 279 config MIPS_COBALT
>> 280 bool "Cobalt Server"
>> 281 select CEVT_R4K
>> 282 select CSRC_R4K
>> 283 select CEVT_GT641XX
>> 284 select DMA_NONCOHERENT
>> 285 select HW_HAS_PCI
>> 286 select I8253
>> 287 select I8259
>> 288 select IRQ_MIPS_CPU
>> 289 select IRQ_GT641XX
>> 290 select PCI_GT64XXX_PCI0
>> 291 select PCI
>> 292 select SYS_HAS_CPU_NEVADA
>> 293 select SYS_HAS_EARLY_PRINTK
>> 294 select SYS_SUPPORTS_32BIT_KERNEL
>> 295 select SYS_SUPPORTS_64BIT_KERNEL
>> 296 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 297 select USE_GENERIC_EARLY_PRINTK_8250
>> 298
>> 299 config MACH_DECSTATION
>> 300 bool "DECstations"
>> 301 select BOOT_ELF32
>> 302 select CEVT_DS1287
>> 303 select CEVT_R4K if CPU_R4X00
>> 304 select CSRC_IOASIC
>> 305 select CSRC_R4K if CPU_R4X00
>> 306 select CPU_DADDI_WORKAROUNDS if 64BIT
>> 307 select CPU_R4000_WORKAROUNDS if 64BIT
>> 308 select CPU_R4400_WORKAROUNDS if 64BIT
>> 309 select DMA_NONCOHERENT
>> 310 select NO_IOPORT_MAP
>> 311 select IRQ_MIPS_CPU
>> 312 select SYS_HAS_CPU_R3000
>> 313 select SYS_HAS_CPU_R4X00
>> 314 select SYS_SUPPORTS_32BIT_KERNEL
>> 315 select SYS_SUPPORTS_64BIT_KERNEL
>> 316 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 317 select SYS_SUPPORTS_128HZ
>> 318 select SYS_SUPPORTS_256HZ
>> 319 select SYS_SUPPORTS_1024HZ
>> 320 select MIPS_L1_CACHE_SHIFT_4
>> 321 help
>> 322 This enables support for DEC's MIPS based workstations. For details
>> 323 see the Linux/MIPS FAQ on <http://www.linux-mips.org/> and the
>> 324 DECstation porting pages on <http://decstation.unix-ag.org/>.
>> 325
>> 326 If you have one of the following DECstation Models you definitely
>> 327 want to choose R4xx0 for the CPU Type:
>> 328
>> 329 DECstation 5000/50
>> 330 DECstation 5000/150
>> 331 DECstation 5000/260
>> 332 DECsystem 5900/260
>> 333
>> 334 otherwise choose R3000.
>> 335
>> 336 config MACH_JAZZ
>> 337 bool "Jazz family of machines"
>> 338 select FW_ARC
>> 339 select FW_ARC32
>> 340 select ARCH_MAY_HAVE_PC_FDC
>> 341 select CEVT_R4K
>> 342 select CSRC_R4K
>> 343 select DEFAULT_SGI_PARTITION if CPU_BIG_ENDIAN
>> 344 select GENERIC_ISA_DMA
>> 345 select HAVE_PCSPKR_PLATFORM
>> 346 select IRQ_MIPS_CPU
>> 347 select I8253
>> 348 select I8259
>> 349 select ISA
>> 350 select SYS_HAS_CPU_R4X00
>> 351 select SYS_SUPPORTS_32BIT_KERNEL
>> 352 select SYS_SUPPORTS_64BIT_KERNEL
>> 353 select SYS_SUPPORTS_100HZ
>> 354 help
>> 355 This a family of machines based on the MIPS R4030 chipset which was
>> 356 used by several vendors to build RISC/os and Windows NT workstations.
>> 357 Members include the Acer PICA, MIPS Magnum 4000, MIPS Millennium and
>> 358 Olivetti M700-10 workstations.
>> 359
>> 360 config MACH_INGENIC
>> 361 bool "Ingenic SoC based machines"
>> 362 select SYS_SUPPORTS_32BIT_KERNEL
>> 363 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 364 select SYS_SUPPORTS_ZBOOT_UART16550
>> 365 select DMA_NONCOHERENT
>> 366 select IRQ_MIPS_CPU
>> 367 select GPIOLIB
>> 368 select COMMON_CLK
>> 369 select GENERIC_IRQ_CHIP
>> 370 select BUILTIN_DTB
>> 371 select USE_OF
>> 372 select LIBFDT
331 373
332 config ARCH_MMAP_RND_COMPAT_BITS_MIN !! 374 config LANTIQ
333 default 7 if ARM64_64K_PAGES !! 375 bool "Lantiq based platforms"
334 default 9 if ARM64_16K_PAGES !! 376 select DMA_NONCOHERENT
335 default 11 !! 377 select IRQ_MIPS_CPU
>> 378 select CEVT_R4K
>> 379 select CSRC_R4K
>> 380 select SYS_HAS_CPU_MIPS32_R1
>> 381 select SYS_HAS_CPU_MIPS32_R2
>> 382 select SYS_SUPPORTS_BIG_ENDIAN
>> 383 select SYS_SUPPORTS_32BIT_KERNEL
>> 384 select SYS_SUPPORTS_MIPS16
>> 385 select SYS_SUPPORTS_MULTITHREADING
>> 386 select SYS_HAS_EARLY_PRINTK
>> 387 select GPIOLIB
>> 388 select SWAP_IO_SPACE
>> 389 select BOOT_RAW
>> 390 select CLKDEV_LOOKUP
>> 391 select USE_OF
>> 392 select PINCTRL
>> 393 select PINCTRL_LANTIQ
>> 394 select ARCH_HAS_RESET_CONTROLLER
>> 395 select RESET_CONTROLLER
>> 396
>> 397 config LASAT
>> 398 bool "LASAT Networks platforms"
>> 399 select CEVT_R4K
>> 400 select CRC32
>> 401 select CSRC_R4K
>> 402 select DMA_NONCOHERENT
>> 403 select SYS_HAS_EARLY_PRINTK
>> 404 select HW_HAS_PCI
>> 405 select IRQ_MIPS_CPU
>> 406 select PCI_GT64XXX_PCI0
>> 407 select MIPS_NILE4
>> 408 select R5000_CPU_SCACHE
>> 409 select SYS_HAS_CPU_R5000
>> 410 select SYS_SUPPORTS_32BIT_KERNEL
>> 411 select SYS_SUPPORTS_64BIT_KERNEL if BROKEN
>> 412 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 413
>> 414 config MACH_LOONGSON32
>> 415 bool "Loongson-1 family of machines"
>> 416 select SYS_SUPPORTS_ZBOOT
>> 417 help
>> 418 This enables support for the Loongson-1 family of machines.
>> 419
>> 420 Loongson-1 is a family of 32-bit MIPS-compatible SoCs developed by
>> 421 the Institute of Computing Technology (ICT), Chinese Academy of
>> 422 Sciences (CAS).
>> 423
>> 424 config MACH_LOONGSON64
>> 425 bool "Loongson-2/3 family of machines"
>> 426 select SYS_SUPPORTS_ZBOOT
>> 427 help
>> 428 This enables the support of Loongson-2/3 family of machines.
>> 429
>> 430 Loongson-2 is a family of single-core CPUs and Loongson-3 is a
>> 431 family of multi-core CPUs. They are both 64-bit general-purpose
>> 432 MIPS-compatible CPUs. Loongson-2/3 are developed by the Institute
>> 433 of Computing Technology (ICT), Chinese Academy of Sciences (CAS)
>> 434 in the People's Republic of China. The chief architect is Professor
>> 435 Weiwu Hu.
>> 436
>> 437 config MACH_PISTACHIO
>> 438 bool "IMG Pistachio SoC based boards"
>> 439 select BOOT_ELF32
>> 440 select BOOT_RAW
>> 441 select CEVT_R4K
>> 442 select CLKSRC_MIPS_GIC
>> 443 select COMMON_CLK
>> 444 select CSRC_R4K
>> 445 select DMA_NONCOHERENT
>> 446 select GPIOLIB
>> 447 select IRQ_MIPS_CPU
>> 448 select LIBFDT
>> 449 select MFD_SYSCON
>> 450 select MIPS_CPU_SCACHE
>> 451 select MIPS_GIC
>> 452 select PINCTRL
>> 453 select REGULATOR
>> 454 select SYS_HAS_CPU_MIPS32_R2
>> 455 select SYS_SUPPORTS_32BIT_KERNEL
>> 456 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 457 select SYS_SUPPORTS_MIPS_CPS
>> 458 select SYS_SUPPORTS_MULTITHREADING
>> 459 select SYS_SUPPORTS_RELOCATABLE
>> 460 select SYS_SUPPORTS_ZBOOT
>> 461 select SYS_HAS_EARLY_PRINTK
>> 462 select USE_GENERIC_EARLY_PRINTK_8250
>> 463 select USE_OF
>> 464 help
>> 465 This enables support for the IMG Pistachio SoC platform.
>> 466
>> 467 config MACH_XILFPGA
>> 468 bool "MIPSfpga Xilinx based boards"
>> 469 select BOOT_ELF32
>> 470 select BOOT_RAW
>> 471 select BUILTIN_DTB
>> 472 select CEVT_R4K
>> 473 select COMMON_CLK
>> 474 select CSRC_R4K
>> 475 select GPIOLIB
>> 476 select IRQ_MIPS_CPU
>> 477 select LIBFDT
>> 478 select MIPS_CPU_SCACHE
>> 479 select SYS_HAS_EARLY_PRINTK
>> 480 select SYS_HAS_CPU_MIPS32_R2
>> 481 select SYS_SUPPORTS_32BIT_KERNEL
>> 482 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 483 select SYS_SUPPORTS_ZBOOT_UART16550
>> 484 select USE_OF
>> 485 select USE_GENERIC_EARLY_PRINTK_8250
>> 486 select XILINX_INTC
>> 487 help
>> 488 This enables support for the IMG University Program MIPSfpga platform.
>> 489
>> 490 config MIPS_MALTA
>> 491 bool "MIPS Malta board"
>> 492 select ARCH_MAY_HAVE_PC_FDC
>> 493 select BOOT_ELF32
>> 494 select BOOT_RAW
>> 495 select BUILTIN_DTB
>> 496 select CEVT_R4K
>> 497 select CSRC_R4K
>> 498 select CLKSRC_MIPS_GIC
>> 499 select COMMON_CLK
>> 500 select DMA_MAYBE_COHERENT
>> 501 select GENERIC_ISA_DMA
>> 502 select HAVE_PCSPKR_PLATFORM
>> 503 select IRQ_MIPS_CPU
>> 504 select MIPS_GIC
>> 505 select HW_HAS_PCI
>> 506 select I8253
>> 507 select I8259
>> 508 select MIPS_BONITO64
>> 509 select MIPS_CPU_SCACHE
>> 510 select MIPS_L1_CACHE_SHIFT_6
>> 511 select PCI_GT64XXX_PCI0
>> 512 select MIPS_MSC
>> 513 select SMP_UP if SMP
>> 514 select SWAP_IO_SPACE
>> 515 select SYS_HAS_CPU_MIPS32_R1
>> 516 select SYS_HAS_CPU_MIPS32_R2
>> 517 select SYS_HAS_CPU_MIPS32_R3_5
>> 518 select SYS_HAS_CPU_MIPS32_R5
>> 519 select SYS_HAS_CPU_MIPS32_R6
>> 520 select SYS_HAS_CPU_MIPS64_R1
>> 521 select SYS_HAS_CPU_MIPS64_R2
>> 522 select SYS_HAS_CPU_MIPS64_R6
>> 523 select SYS_HAS_CPU_NEVADA
>> 524 select SYS_HAS_CPU_RM7000
>> 525 select SYS_SUPPORTS_32BIT_KERNEL
>> 526 select SYS_SUPPORTS_64BIT_KERNEL
>> 527 select SYS_SUPPORTS_BIG_ENDIAN
>> 528 select SYS_SUPPORTS_HIGHMEM
>> 529 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 530 select SYS_SUPPORTS_MICROMIPS
>> 531 select SYS_SUPPORTS_MIPS_CMP
>> 532 select SYS_SUPPORTS_MIPS_CPS
>> 533 select SYS_SUPPORTS_MIPS16
>> 534 select SYS_SUPPORTS_MULTITHREADING
>> 535 select SYS_SUPPORTS_SMARTMIPS
>> 536 select SYS_SUPPORTS_ZBOOT
>> 537 select SYS_SUPPORTS_RELOCATABLE
>> 538 select USE_OF
>> 539 select LIBFDT
>> 540 select ZONE_DMA32 if 64BIT
>> 541 select BUILTIN_DTB
>> 542 select LIBFDT
>> 543 help
>> 544 This enables support for the MIPS Technologies Malta evaluation
>> 545 board.
336 546
337 config ARCH_MMAP_RND_COMPAT_BITS_MAX !! 547 config MACH_PIC32
338 default 16 !! 548 bool "Microchip PIC32 Family"
>> 549 help
>> 550 This enables support for the Microchip PIC32 family of platforms.
339 551
340 config NO_IOPORT_MAP !! 552 Microchip PIC32 is a family of general-purpose 32 bit MIPS core
341 def_bool y if !PCI !! 553 microcontrollers.
>> 554
>> 555 config NEC_MARKEINS
>> 556 bool "NEC EMMA2RH Mark-eins board"
>> 557 select SOC_EMMA2RH
>> 558 select HW_HAS_PCI
>> 559 help
>> 560 This enables support for the NEC Electronics Mark-eins boards.
>> 561
>> 562 config MACH_VR41XX
>> 563 bool "NEC VR4100 series based machines"
>> 564 select CEVT_R4K
>> 565 select CSRC_R4K
>> 566 select SYS_HAS_CPU_VR41XX
>> 567 select SYS_SUPPORTS_MIPS16
>> 568 select GPIOLIB
>> 569
>> 570 config NXP_STB220
>> 571 bool "NXP STB220 board"
>> 572 select SOC_PNX833X
>> 573 help
>> 574 Support for NXP Semiconductors STB220 Development Board.
>> 575
>> 576 config NXP_STB225
>> 577 bool "NXP 225 board"
>> 578 select SOC_PNX833X
>> 579 select SOC_PNX8335
>> 580 help
>> 581 Support for NXP Semiconductors STB225 Development Board.
>> 582
>> 583 config PMC_MSP
>> 584 bool "PMC-Sierra MSP chipsets"
>> 585 select CEVT_R4K
>> 586 select CSRC_R4K
>> 587 select DMA_NONCOHERENT
>> 588 select SWAP_IO_SPACE
>> 589 select NO_EXCEPT_FILL
>> 590 select BOOT_RAW
>> 591 select SYS_HAS_CPU_MIPS32_R1
>> 592 select SYS_HAS_CPU_MIPS32_R2
>> 593 select SYS_SUPPORTS_32BIT_KERNEL
>> 594 select SYS_SUPPORTS_BIG_ENDIAN
>> 595 select SYS_SUPPORTS_MIPS16
>> 596 select IRQ_MIPS_CPU
>> 597 select SERIAL_8250
>> 598 select SERIAL_8250_CONSOLE
>> 599 select USB_EHCI_BIG_ENDIAN_MMIO
>> 600 select USB_EHCI_BIG_ENDIAN_DESC
>> 601 help
>> 602 This adds support for the PMC-Sierra family of Multi-Service
>> 603 Processor System-On-A-Chips. These parts include a number
>> 604 of integrated peripherals, interfaces and DSPs in addition to
>> 605 a variety of MIPS cores.
>> 606
>> 607 config RALINK
>> 608 bool "Ralink based machines"
>> 609 select CEVT_R4K
>> 610 select CSRC_R4K
>> 611 select BOOT_RAW
>> 612 select DMA_NONCOHERENT
>> 613 select IRQ_MIPS_CPU
>> 614 select USE_OF
>> 615 select SYS_HAS_CPU_MIPS32_R1
>> 616 select SYS_HAS_CPU_MIPS32_R2
>> 617 select SYS_SUPPORTS_32BIT_KERNEL
>> 618 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 619 select SYS_SUPPORTS_MIPS16
>> 620 select SYS_HAS_EARLY_PRINTK
>> 621 select CLKDEV_LOOKUP
>> 622 select ARCH_HAS_RESET_CONTROLLER
>> 623 select RESET_CONTROLLER
>> 624
>> 625 config SGI_IP22
>> 626 bool "SGI IP22 (Indy/Indigo2)"
>> 627 select FW_ARC
>> 628 select FW_ARC32
>> 629 select BOOT_ELF32
>> 630 select CEVT_R4K
>> 631 select CSRC_R4K
>> 632 select DEFAULT_SGI_PARTITION
>> 633 select DMA_NONCOHERENT
>> 634 select HW_HAS_EISA
>> 635 select I8253
>> 636 select I8259
>> 637 select IP22_CPU_SCACHE
>> 638 select IRQ_MIPS_CPU
>> 639 select GENERIC_ISA_DMA_SUPPORT_BROKEN
>> 640 select SGI_HAS_I8042
>> 641 select SGI_HAS_INDYDOG
>> 642 select SGI_HAS_HAL2
>> 643 select SGI_HAS_SEEQ
>> 644 select SGI_HAS_WD93
>> 645 select SGI_HAS_ZILOG
>> 646 select SWAP_IO_SPACE
>> 647 select SYS_HAS_CPU_R4X00
>> 648 select SYS_HAS_CPU_R5000
>> 649 #
>> 650 # Disable EARLY_PRINTK for now since it leads to overwritten prom
>> 651 # memory during early boot on some machines.
>> 652 #
>> 653 # See http://www.linux-mips.org/cgi-bin/mesg.cgi?a=linux-mips&i=20091119164009.GA15038%40deprecation.cyrius.com
>> 654 # for a more details discussion
>> 655 #
>> 656 # select SYS_HAS_EARLY_PRINTK
>> 657 select SYS_SUPPORTS_32BIT_KERNEL
>> 658 select SYS_SUPPORTS_64BIT_KERNEL
>> 659 select SYS_SUPPORTS_BIG_ENDIAN
>> 660 select MIPS_L1_CACHE_SHIFT_7
>> 661 help
>> 662 This are the SGI Indy, Challenge S and Indigo2, as well as certain
>> 663 OEM variants like the Tandem CMN B006S. To compile a Linux kernel
>> 664 that runs on these, say Y here.
>> 665
>> 666 config SGI_IP27
>> 667 bool "SGI IP27 (Origin200/2000)"
>> 668 select FW_ARC
>> 669 select FW_ARC64
>> 670 select BOOT_ELF64
>> 671 select DEFAULT_SGI_PARTITION
>> 672 select DMA_COHERENT
>> 673 select SYS_HAS_EARLY_PRINTK
>> 674 select HW_HAS_PCI
>> 675 select NR_CPUS_DEFAULT_64
>> 676 select SYS_HAS_CPU_R10000
>> 677 select SYS_SUPPORTS_64BIT_KERNEL
>> 678 select SYS_SUPPORTS_BIG_ENDIAN
>> 679 select SYS_SUPPORTS_NUMA
>> 680 select SYS_SUPPORTS_SMP
>> 681 select MIPS_L1_CACHE_SHIFT_7
>> 682 help
>> 683 This are the SGI Origin 200, Origin 2000 and Onyx 2 Graphics
>> 684 workstations. To compile a Linux kernel that runs on these, say Y
>> 685 here.
>> 686
>> 687 config SGI_IP28
>> 688 bool "SGI IP28 (Indigo2 R10k)"
>> 689 select FW_ARC
>> 690 select FW_ARC64
>> 691 select BOOT_ELF64
>> 692 select CEVT_R4K
>> 693 select CSRC_R4K
>> 694 select DEFAULT_SGI_PARTITION
>> 695 select DMA_NONCOHERENT
>> 696 select GENERIC_ISA_DMA_SUPPORT_BROKEN
>> 697 select IRQ_MIPS_CPU
>> 698 select HW_HAS_EISA
>> 699 select I8253
>> 700 select I8259
>> 701 select SGI_HAS_I8042
>> 702 select SGI_HAS_INDYDOG
>> 703 select SGI_HAS_HAL2
>> 704 select SGI_HAS_SEEQ
>> 705 select SGI_HAS_WD93
>> 706 select SGI_HAS_ZILOG
>> 707 select SWAP_IO_SPACE
>> 708 select SYS_HAS_CPU_R10000
>> 709 #
>> 710 # Disable EARLY_PRINTK for now since it leads to overwritten prom
>> 711 # memory during early boot on some machines.
>> 712 #
>> 713 # See http://www.linux-mips.org/cgi-bin/mesg.cgi?a=linux-mips&i=20091119164009.GA15038%40deprecation.cyrius.com
>> 714 # for a more details discussion
>> 715 #
>> 716 # select SYS_HAS_EARLY_PRINTK
>> 717 select SYS_SUPPORTS_64BIT_KERNEL
>> 718 select SYS_SUPPORTS_BIG_ENDIAN
>> 719 select MIPS_L1_CACHE_SHIFT_7
>> 720 help
>> 721 This is the SGI Indigo2 with R10000 processor. To compile a Linux
>> 722 kernel that runs on these, say Y here.
>> 723
>> 724 config SGI_IP32
>> 725 bool "SGI IP32 (O2)"
>> 726 select FW_ARC
>> 727 select FW_ARC32
>> 728 select BOOT_ELF32
>> 729 select CEVT_R4K
>> 730 select CSRC_R4K
>> 731 select DMA_NONCOHERENT
>> 732 select HW_HAS_PCI
>> 733 select IRQ_MIPS_CPU
>> 734 select R5000_CPU_SCACHE
>> 735 select RM7000_CPU_SCACHE
>> 736 select SYS_HAS_CPU_R5000
>> 737 select SYS_HAS_CPU_R10000 if BROKEN
>> 738 select SYS_HAS_CPU_RM7000
>> 739 select SYS_HAS_CPU_NEVADA
>> 740 select SYS_SUPPORTS_64BIT_KERNEL
>> 741 select SYS_SUPPORTS_BIG_ENDIAN
>> 742 help
>> 743 If you want this kernel to run on SGI O2 workstation, say Y here.
>> 744
>> 745 config SIBYTE_CRHINE
>> 746 bool "Sibyte BCM91120C-CRhine"
>> 747 select BOOT_ELF32
>> 748 select DMA_COHERENT
>> 749 select SIBYTE_BCM1120
>> 750 select SWAP_IO_SPACE
>> 751 select SYS_HAS_CPU_SB1
>> 752 select SYS_SUPPORTS_BIG_ENDIAN
>> 753 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 754
>> 755 config SIBYTE_CARMEL
>> 756 bool "Sibyte BCM91120x-Carmel"
>> 757 select BOOT_ELF32
>> 758 select DMA_COHERENT
>> 759 select SIBYTE_BCM1120
>> 760 select SWAP_IO_SPACE
>> 761 select SYS_HAS_CPU_SB1
>> 762 select SYS_SUPPORTS_BIG_ENDIAN
>> 763 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 764
>> 765 config SIBYTE_CRHONE
>> 766 bool "Sibyte BCM91125C-CRhone"
>> 767 select BOOT_ELF32
>> 768 select DMA_COHERENT
>> 769 select SIBYTE_BCM1125
>> 770 select SWAP_IO_SPACE
>> 771 select SYS_HAS_CPU_SB1
>> 772 select SYS_SUPPORTS_BIG_ENDIAN
>> 773 select SYS_SUPPORTS_HIGHMEM
>> 774 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 775
>> 776 config SIBYTE_RHONE
>> 777 bool "Sibyte BCM91125E-Rhone"
>> 778 select BOOT_ELF32
>> 779 select DMA_COHERENT
>> 780 select SIBYTE_BCM1125H
>> 781 select SWAP_IO_SPACE
>> 782 select SYS_HAS_CPU_SB1
>> 783 select SYS_SUPPORTS_BIG_ENDIAN
>> 784 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 785
>> 786 config SIBYTE_SWARM
>> 787 bool "Sibyte BCM91250A-SWARM"
>> 788 select BOOT_ELF32
>> 789 select DMA_COHERENT
>> 790 select HAVE_PATA_PLATFORM
>> 791 select SIBYTE_SB1250
>> 792 select SWAP_IO_SPACE
>> 793 select SYS_HAS_CPU_SB1
>> 794 select SYS_SUPPORTS_BIG_ENDIAN
>> 795 select SYS_SUPPORTS_HIGHMEM
>> 796 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 797 select ZONE_DMA32 if 64BIT
>> 798
>> 799 config SIBYTE_LITTLESUR
>> 800 bool "Sibyte BCM91250C2-LittleSur"
>> 801 select BOOT_ELF32
>> 802 select DMA_COHERENT
>> 803 select HAVE_PATA_PLATFORM
>> 804 select SIBYTE_SB1250
>> 805 select SWAP_IO_SPACE
>> 806 select SYS_HAS_CPU_SB1
>> 807 select SYS_SUPPORTS_BIG_ENDIAN
>> 808 select SYS_SUPPORTS_HIGHMEM
>> 809 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 810
>> 811 config SIBYTE_SENTOSA
>> 812 bool "Sibyte BCM91250E-Sentosa"
>> 813 select BOOT_ELF32
>> 814 select DMA_COHERENT
>> 815 select SIBYTE_SB1250
>> 816 select SWAP_IO_SPACE
>> 817 select SYS_HAS_CPU_SB1
>> 818 select SYS_SUPPORTS_BIG_ENDIAN
>> 819 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 820
>> 821 config SIBYTE_BIGSUR
>> 822 bool "Sibyte BCM91480B-BigSur"
>> 823 select BOOT_ELF32
>> 824 select DMA_COHERENT
>> 825 select NR_CPUS_DEFAULT_4
>> 826 select SIBYTE_BCM1x80
>> 827 select SWAP_IO_SPACE
>> 828 select SYS_HAS_CPU_SB1
>> 829 select SYS_SUPPORTS_BIG_ENDIAN
>> 830 select SYS_SUPPORTS_HIGHMEM
>> 831 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 832 select ZONE_DMA32 if 64BIT
>> 833
>> 834 config SNI_RM
>> 835 bool "SNI RM200/300/400"
>> 836 select FW_ARC if CPU_LITTLE_ENDIAN
>> 837 select FW_ARC32 if CPU_LITTLE_ENDIAN
>> 838 select FW_SNIPROM if CPU_BIG_ENDIAN
>> 839 select ARCH_MAY_HAVE_PC_FDC
>> 840 select BOOT_ELF32
>> 841 select CEVT_R4K
>> 842 select CSRC_R4K
>> 843 select DEFAULT_SGI_PARTITION if CPU_BIG_ENDIAN
>> 844 select DMA_NONCOHERENT
>> 845 select GENERIC_ISA_DMA
>> 846 select HAVE_PCSPKR_PLATFORM
>> 847 select HW_HAS_EISA
>> 848 select HW_HAS_PCI
>> 849 select IRQ_MIPS_CPU
>> 850 select I8253
>> 851 select I8259
>> 852 select ISA
>> 853 select SWAP_IO_SPACE if CPU_BIG_ENDIAN
>> 854 select SYS_HAS_CPU_R4X00
>> 855 select SYS_HAS_CPU_R5000
>> 856 select SYS_HAS_CPU_R10000
>> 857 select R5000_CPU_SCACHE
>> 858 select SYS_HAS_EARLY_PRINTK
>> 859 select SYS_SUPPORTS_32BIT_KERNEL
>> 860 select SYS_SUPPORTS_64BIT_KERNEL
>> 861 select SYS_SUPPORTS_BIG_ENDIAN
>> 862 select SYS_SUPPORTS_HIGHMEM
>> 863 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 864 help
>> 865 The SNI RM200/300/400 are MIPS-based machines manufactured by
>> 866 Siemens Nixdorf Informationssysteme (SNI), parent company of Pyramid
>> 867 Technology and now in turn merged with Fujitsu. Say Y here to
>> 868 support this machine type.
>> 869
>> 870 config MACH_TX39XX
>> 871 bool "Toshiba TX39 series based machines"
>> 872
>> 873 config MACH_TX49XX
>> 874 bool "Toshiba TX49 series based machines"
>> 875
>> 876 config MIKROTIK_RB532
>> 877 bool "Mikrotik RB532 boards"
>> 878 select CEVT_R4K
>> 879 select CSRC_R4K
>> 880 select DMA_NONCOHERENT
>> 881 select HW_HAS_PCI
>> 882 select IRQ_MIPS_CPU
>> 883 select SYS_HAS_CPU_MIPS32_R1
>> 884 select SYS_SUPPORTS_32BIT_KERNEL
>> 885 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 886 select SWAP_IO_SPACE
>> 887 select BOOT_RAW
>> 888 select GPIOLIB
>> 889 select MIPS_L1_CACHE_SHIFT_4
>> 890 help
>> 891 Support the Mikrotik(tm) RouterBoard 532 series,
>> 892 based on the IDT RC32434 SoC.
>> 893
>> 894 config CAVIUM_OCTEON_SOC
>> 895 bool "Cavium Networks Octeon SoC based boards"
>> 896 select CEVT_R4K
>> 897 select ARCH_PHYS_ADDR_T_64BIT
>> 898 select DMA_COHERENT
>> 899 select SYS_SUPPORTS_64BIT_KERNEL
>> 900 select SYS_SUPPORTS_BIG_ENDIAN
>> 901 select EDAC_SUPPORT
>> 902 select EDAC_ATOMIC_SCRUB
>> 903 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 904 select SYS_SUPPORTS_HOTPLUG_CPU if CPU_BIG_ENDIAN
>> 905 select SYS_HAS_EARLY_PRINTK
>> 906 select SYS_HAS_CPU_CAVIUM_OCTEON
>> 907 select HW_HAS_PCI
>> 908 select ZONE_DMA32
>> 909 select HOLES_IN_ZONE
>> 910 select GPIOLIB
>> 911 select LIBFDT
>> 912 select USE_OF
>> 913 select ARCH_SPARSEMEM_ENABLE
>> 914 select SYS_SUPPORTS_SMP
>> 915 select NR_CPUS_DEFAULT_16
>> 916 select BUILTIN_DTB
>> 917 select MTD_COMPLEX_MAPPINGS
>> 918 select SYS_SUPPORTS_RELOCATABLE
>> 919 help
>> 920 This option supports all of the Octeon reference boards from Cavium
>> 921 Networks. It builds a kernel that dynamically determines the Octeon
>> 922 CPU type and supports all known board reference implementations.
>> 923 Some of the supported boards are:
>> 924 EBT3000
>> 925 EBH3000
>> 926 EBH3100
>> 927 Thunder
>> 928 Kodama
>> 929 Hikari
>> 930 Say Y here for most Octeon reference boards.
>> 931
>> 932 config NLM_XLR_BOARD
>> 933 bool "Netlogic XLR/XLS based systems"
>> 934 select BOOT_ELF32
>> 935 select NLM_COMMON
>> 936 select SYS_HAS_CPU_XLR
>> 937 select SYS_SUPPORTS_SMP
>> 938 select HW_HAS_PCI
>> 939 select SWAP_IO_SPACE
>> 940 select SYS_SUPPORTS_32BIT_KERNEL
>> 941 select SYS_SUPPORTS_64BIT_KERNEL
>> 942 select ARCH_PHYS_ADDR_T_64BIT
>> 943 select SYS_SUPPORTS_BIG_ENDIAN
>> 944 select SYS_SUPPORTS_HIGHMEM
>> 945 select DMA_COHERENT
>> 946 select NR_CPUS_DEFAULT_32
>> 947 select CEVT_R4K
>> 948 select CSRC_R4K
>> 949 select IRQ_MIPS_CPU
>> 950 select ZONE_DMA32 if 64BIT
>> 951 select SYNC_R4K
>> 952 select SYS_HAS_EARLY_PRINTK
>> 953 select SYS_SUPPORTS_ZBOOT
>> 954 select SYS_SUPPORTS_ZBOOT_UART16550
>> 955 help
>> 956 Support for systems based on Netlogic XLR and XLS processors.
>> 957 Say Y here if you have a XLR or XLS based board.
>> 958
>> 959 config NLM_XLP_BOARD
>> 960 bool "Netlogic XLP based systems"
>> 961 select BOOT_ELF32
>> 962 select NLM_COMMON
>> 963 select SYS_HAS_CPU_XLP
>> 964 select SYS_SUPPORTS_SMP
>> 965 select HW_HAS_PCI
>> 966 select SYS_SUPPORTS_32BIT_KERNEL
>> 967 select SYS_SUPPORTS_64BIT_KERNEL
>> 968 select ARCH_PHYS_ADDR_T_64BIT
>> 969 select GPIOLIB
>> 970 select SYS_SUPPORTS_BIG_ENDIAN
>> 971 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 972 select SYS_SUPPORTS_HIGHMEM
>> 973 select DMA_COHERENT
>> 974 select NR_CPUS_DEFAULT_32
>> 975 select CEVT_R4K
>> 976 select CSRC_R4K
>> 977 select IRQ_MIPS_CPU
>> 978 select ZONE_DMA32 if 64BIT
>> 979 select SYNC_R4K
>> 980 select SYS_HAS_EARLY_PRINTK
>> 981 select USE_OF
>> 982 select SYS_SUPPORTS_ZBOOT
>> 983 select SYS_SUPPORTS_ZBOOT_UART16550
>> 984 help
>> 985 This board is based on Netlogic XLP Processor.
>> 986 Say Y here if you have a XLP based board.
>> 987
>> 988 config MIPS_PARAVIRT
>> 989 bool "Para-Virtualized guest system"
>> 990 select CEVT_R4K
>> 991 select CSRC_R4K
>> 992 select DMA_COHERENT
>> 993 select SYS_SUPPORTS_64BIT_KERNEL
>> 994 select SYS_SUPPORTS_32BIT_KERNEL
>> 995 select SYS_SUPPORTS_BIG_ENDIAN
>> 996 select SYS_SUPPORTS_SMP
>> 997 select NR_CPUS_DEFAULT_4
>> 998 select SYS_HAS_EARLY_PRINTK
>> 999 select SYS_HAS_CPU_MIPS32_R2
>> 1000 select SYS_HAS_CPU_MIPS64_R2
>> 1001 select SYS_HAS_CPU_CAVIUM_OCTEON
>> 1002 select HW_HAS_PCI
>> 1003 select SWAP_IO_SPACE
>> 1004 help
>> 1005 This option supports guest running under ????
342 1006
343 config STACKTRACE_SUPPORT !! 1007 endchoice
344 def_bool y <<
345 1008
346 config ILLEGAL_POINTER_VALUE !! 1009 source "arch/mips/alchemy/Kconfig"
347 hex !! 1010 source "arch/mips/ath25/Kconfig"
348 default 0xdead000000000000 !! 1011 source "arch/mips/ath79/Kconfig"
>> 1012 source "arch/mips/bcm47xx/Kconfig"
>> 1013 source "arch/mips/bcm63xx/Kconfig"
>> 1014 source "arch/mips/bmips/Kconfig"
>> 1015 source "arch/mips/generic/Kconfig"
>> 1016 source "arch/mips/jazz/Kconfig"
>> 1017 source "arch/mips/jz4740/Kconfig"
>> 1018 source "arch/mips/lantiq/Kconfig"
>> 1019 source "arch/mips/lasat/Kconfig"
>> 1020 source "arch/mips/pic32/Kconfig"
>> 1021 source "arch/mips/pistachio/Kconfig"
>> 1022 source "arch/mips/pmcs-msp71xx/Kconfig"
>> 1023 source "arch/mips/ralink/Kconfig"
>> 1024 source "arch/mips/sgi-ip27/Kconfig"
>> 1025 source "arch/mips/sibyte/Kconfig"
>> 1026 source "arch/mips/txx9/Kconfig"
>> 1027 source "arch/mips/vr41xx/Kconfig"
>> 1028 source "arch/mips/cavium-octeon/Kconfig"
>> 1029 source "arch/mips/loongson32/Kconfig"
>> 1030 source "arch/mips/loongson64/Kconfig"
>> 1031 source "arch/mips/netlogic/Kconfig"
>> 1032 source "arch/mips/paravirt/Kconfig"
>> 1033 source "arch/mips/xilfpga/Kconfig"
349 1034
350 config LOCKDEP_SUPPORT !! 1035 endmenu
351 def_bool y <<
352 1036
353 config GENERIC_BUG !! 1037 config RWSEM_GENERIC_SPINLOCK
354 def_bool y !! 1038 bool
355 depends on BUG !! 1039 default y
356 1040
357 config GENERIC_BUG_RELATIVE_POINTERS !! 1041 config RWSEM_XCHGADD_ALGORITHM
358 def_bool y !! 1042 bool
359 depends on GENERIC_BUG <<
360 1043
361 config GENERIC_HWEIGHT 1044 config GENERIC_HWEIGHT
362 def_bool y !! 1045 bool
363 !! 1046 default y
364 config GENERIC_CSUM <<
365 def_bool y <<
366 1047
367 config GENERIC_CALIBRATE_DELAY 1048 config GENERIC_CALIBRATE_DELAY
368 def_bool y <<
369 <<
370 config SMP <<
371 def_bool y <<
372 <<
373 config KERNEL_MODE_NEON <<
374 def_bool y <<
375 <<
376 config FIX_EARLYCON_MEM <<
377 def_bool y <<
378 <<
379 config PGTABLE_LEVELS <<
380 int <<
381 default 2 if ARM64_16K_PAGES && ARM64_ <<
382 default 2 if ARM64_64K_PAGES && ARM64_ <<
383 default 3 if ARM64_64K_PAGES && (ARM64 <<
384 default 3 if ARM64_4K_PAGES && ARM64_V <<
385 default 3 if ARM64_16K_PAGES && ARM64_ <<
386 default 4 if ARM64_16K_PAGES && (ARM64 <<
387 default 4 if !ARM64_64K_PAGES && ARM64 <<
388 default 5 if ARM64_4K_PAGES && ARM64_V <<
389 <<
390 config ARCH_SUPPORTS_UPROBES <<
391 def_bool y <<
392 <<
393 config ARCH_PROC_KCORE_TEXT <<
394 def_bool y <<
395 <<
396 config BROKEN_GAS_INST <<
397 def_bool !$(as-instr,1:\n.inst 0\n.rep <<
398 <<
399 config BUILTIN_RETURN_ADDRESS_STRIPS_PAC <<
400 bool 1049 bool
401 # Clang's __builtin_return_address() s !! 1050 default y
402 # https://github.com/llvm/llvm-project <<
403 default y if CC_IS_CLANG <<
404 # GCC's __builtin_return_address() str <<
405 # and this was backported to 10.2.0, 9 <<
406 # https://gcc.gnu.org/bugzilla/show_bu <<
407 default y if CC_IS_GCC && (GCC_VERSION <<
408 default y if CC_IS_GCC && (GCC_VERSION <<
409 default y if CC_IS_GCC && (GCC_VERSION <<
410 default y if CC_IS_GCC && (GCC_VERSION <<
411 default n <<
412 <<
413 config KASAN_SHADOW_OFFSET <<
414 hex <<
415 depends on KASAN_GENERIC || KASAN_SW_T <<
416 default 0xdfff800000000000 if (ARM64_V <<
417 default 0xdfffc00000000000 if (ARM64_V <<
418 default 0xdffffe0000000000 if ARM64_VA <<
419 default 0xdfffffc000000000 if ARM64_VA <<
420 default 0xdffffff800000000 if ARM64_VA <<
421 default 0xefff800000000000 if (ARM64_V <<
422 default 0xefffc00000000000 if (ARM64_V <<
423 default 0xeffffe0000000000 if ARM64_VA <<
424 default 0xefffffc000000000 if ARM64_VA <<
425 default 0xeffffff800000000 if ARM64_VA <<
426 default 0xffffffffffffffff <<
427 <<
428 config UNWIND_TABLES <<
429 bool <<
430 <<
431 source "arch/arm64/Kconfig.platforms" <<
432 <<
433 menu "Kernel Features" <<
434 <<
435 menu "ARM errata workarounds via the alternati <<
436 <<
437 config AMPERE_ERRATUM_AC03_CPU_38 <<
438 bool "AmpereOne: AC03_CPU_38: Certain <<
439 default y <<
440 help <<
441 This option adds an alternative code <<
442 errata AC03_CPU_38 and AC04_CPU_10 o <<
443 <<
444 The affected design reports FEAT_HAF <<
445 ID_AA64MMFR1_EL1.HAFDBS, but (V)TCR_ <<
446 as required by the architecture. The <<
447 implementation suffers from an addit <<
448 A/D updates can occur after a PTE ha <<
449 <<
450 The workaround forces KVM to explici <<
451 which avoids enabling unadvertised h <<
452 at stage-2. <<
453 <<
454 If unsure, say Y. <<
455 1051
456 config ARM64_WORKAROUND_CLEAN_CACHE !! 1052 config SCHED_OMIT_FRAME_POINTER
457 bool 1053 bool
458 <<
459 config ARM64_ERRATUM_826319 <<
460 bool "Cortex-A53: 826319: System might <<
461 default y 1054 default y
462 select ARM64_WORKAROUND_CLEAN_CACHE <<
463 help <<
464 This option adds an alternative code <<
465 erratum 826319 on Cortex-A53 parts u <<
466 AXI master interface and an L2 cache <<
467 1055
468 If a Cortex-A53 uses an AMBA AXI4 AC !! 1056 #
469 and is unable to accept a certain wr !! 1057 # Select some configuration options automatically based on user selections.
470 not progress on read data presented !! 1058 #
471 system can deadlock. !! 1059 config FW_ARC
472 !! 1060 bool
473 The workaround promotes data cache c <<
474 data cache clean-and-invalidate. <<
475 Please note that this does not neces <<
476 as it depends on the alternative fra <<
477 the kernel if an affected CPU is det <<
478 <<
479 If unsure, say Y. <<
480 <<
481 config ARM64_ERRATUM_827319 <<
482 bool "Cortex-A53: 827319: Data cache c <<
483 default y <<
484 select ARM64_WORKAROUND_CLEAN_CACHE <<
485 help <<
486 This option adds an alternative code <<
487 erratum 827319 on Cortex-A53 parts u <<
488 master interface and an L2 cache. <<
489 <<
490 Under certain conditions this erratu <<
491 to occur at the same time as another <<
492 on the AMBA 5 CHI interface, which c <<
493 interconnect reorders the two transa <<
494 <<
495 The workaround promotes data cache c <<
496 data cache clean-and-invalidate. <<
497 Please note that this does not neces <<
498 as it depends on the alternative fra <<
499 the kernel if an affected CPU is det <<
500 1061
501 If unsure, say Y. !! 1062 config ARCH_MAY_HAVE_PC_FDC
>> 1063 bool
502 1064
503 config ARM64_ERRATUM_824069 !! 1065 config BOOT_RAW
504 bool "Cortex-A53: 824069: Cache line m !! 1066 bool
505 default y <<
506 select ARM64_WORKAROUND_CLEAN_CACHE <<
507 help <<
508 This option adds an alternative code <<
509 erratum 824069 on Cortex-A53 parts u <<
510 to a coherent interconnect. <<
511 <<
512 If a Cortex-A53 processor is executi <<
513 write instruction at the same time a <<
514 cluster is executing a cache mainten <<
515 address, then this erratum might cau <<
516 incorrectly marked as dirty. <<
517 <<
518 The workaround promotes data cache c <<
519 data cache clean-and-invalidate. <<
520 Please note that this option does no <<
521 workaround, as it depends on the alt <<
522 only patch the kernel if an affected <<
523 1067
524 If unsure, say Y. !! 1068 config CEVT_BCM1480
>> 1069 bool
525 1070
526 config ARM64_ERRATUM_819472 !! 1071 config CEVT_DS1287
527 bool "Cortex-A53: 819472: Store exclus !! 1072 bool
528 default y <<
529 select ARM64_WORKAROUND_CLEAN_CACHE <<
530 help <<
531 This option adds an alternative code <<
532 erratum 819472 on Cortex-A53 parts u <<
533 present when it is connected to a co <<
534 <<
535 If the processor is executing a load <<
536 the same time as a processor in anot <<
537 maintenance operation to the same ad <<
538 cause data corruption. <<
539 <<
540 The workaround promotes data cache c <<
541 data cache clean-and-invalidate. <<
542 Please note that this does not neces <<
543 as it depends on the alternative fra <<
544 the kernel if an affected CPU is det <<
545 1073
546 If unsure, say Y. !! 1074 config CEVT_GT641XX
>> 1075 bool
547 1076
548 config ARM64_ERRATUM_832075 !! 1077 config CEVT_R4K
549 bool "Cortex-A57: 832075: possible dea !! 1078 bool
550 default y <<
551 help <<
552 This option adds an alternative code <<
553 erratum 832075 on Cortex-A57 parts u <<
554 1079
555 Affected Cortex-A57 parts might dead !! 1080 config CEVT_SB1250
556 instructions to Write-Back memory ar !! 1081 bool
557 1082
558 The workaround is to promote device !! 1083 config CEVT_TXX9
559 semantics. !! 1084 bool
560 Please note that this does not neces <<
561 as it depends on the alternative fra <<
562 the kernel if an affected CPU is det <<
563 1085
564 If unsure, say Y. !! 1086 config CSRC_BCM1480
>> 1087 bool
565 1088
566 config ARM64_ERRATUM_834220 !! 1089 config CSRC_IOASIC
567 bool "Cortex-A57: 834220: Stage 2 tran !! 1090 bool
568 depends on KVM <<
569 help <<
570 This option adds an alternative code <<
571 erratum 834220 on Cortex-A57 parts u <<
572 <<
573 Affected Cortex-A57 parts might repo <<
574 fault as the result of a Stage 1 fau <<
575 page boundary when there is a permis <<
576 alignment fault at Stage 1 and a tra <<
577 <<
578 The workaround is to verify that the <<
579 doesn't generate a fault before hand <<
580 Please note that this does not neces <<
581 as it depends on the alternative fra <<
582 the kernel if an affected CPU is det <<
583 1091
584 If unsure, say N. !! 1092 config CSRC_R4K
>> 1093 bool
585 1094
586 config ARM64_ERRATUM_1742098 !! 1095 config CSRC_SB1250
587 bool "Cortex-A57/A72: 1742098: ELR rec !! 1096 bool
588 depends on COMPAT <<
589 default y <<
590 help <<
591 This option removes the AES hwcap fo <<
592 workaround erratum 1742098 on Cortex <<
593 <<
594 Affected parts may corrupt the AES s <<
595 taken between a pair of AES instruct <<
596 are only present if the cryptography <<
597 All software should have a fallback <<
598 that don't implement the cryptograph <<
599 1097
600 If unsure, say Y. !! 1098 config MIPS_CLOCK_VSYSCALL
>> 1099 def_bool CSRC_R4K || CLKSRC_MIPS_GIC
601 1100
602 config ARM64_ERRATUM_845719 !! 1101 config GPIO_TXX9
603 bool "Cortex-A53: 845719: a load might !! 1102 select GPIOLIB
604 depends on COMPAT !! 1103 bool
605 default y <<
606 help <<
607 This option adds an alternative code <<
608 erratum 845719 on Cortex-A53 parts u <<
609 <<
610 When running a compat (AArch32) user <<
611 part, a load at EL0 from a virtual a <<
612 bits of the virtual address used by <<
613 might return incorrect data. <<
614 <<
615 The workaround is to write the conte <<
616 return to a 32-bit task. <<
617 Please note that this does not neces <<
618 as it depends on the alternative fra <<
619 the kernel if an affected CPU is det <<
620 1104
621 If unsure, say Y. !! 1105 config FW_CFE
>> 1106 bool
622 1107
623 config ARM64_ERRATUM_843419 !! 1108 config ARCH_DMA_ADDR_T_64BIT
624 bool "Cortex-A53: 843419: A load or st !! 1109 def_bool (HIGHMEM && ARCH_PHYS_ADDR_T_64BIT) || 64BIT
625 default y <<
626 help <<
627 This option links the kernel with '- <<
628 enables PLT support to replace certa <<
629 cause subsequent memory accesses to <<
630 Cortex-A53 parts up to r0p4. <<
631 1110
632 If unsure, say Y. !! 1111 config ARCH_SUPPORTS_UPROBES
>> 1112 bool
633 1113
634 config ARM64_LD_HAS_FIX_ERRATUM_843419 !! 1114 config DMA_MAYBE_COHERENT
635 def_bool $(ld-option,--fix-cortex-a53- !! 1115 select DMA_NONCOHERENT
>> 1116 bool
636 1117
637 config ARM64_ERRATUM_1024718 !! 1118 config DMA_PERDEV_COHERENT
638 bool "Cortex-A55: 1024718: Update of D !! 1119 bool
639 default y !! 1120 select DMA_MAYBE_COHERENT
640 help <<
641 This option adds a workaround for AR <<
642 1121
643 Affected Cortex-A55 cores (all revis !! 1122 config DMA_COHERENT
644 update of the hardware dirty bit whe !! 1123 bool
645 without a break-before-make. The wor <<
646 of hardware DBM locally on the affec <<
647 this erratum will continue to use th <<
648 1124
649 If unsure, say Y. !! 1125 config DMA_NONCOHERENT
>> 1126 bool
>> 1127 select NEED_DMA_MAP_STATE
650 1128
651 config ARM64_ERRATUM_1418040 !! 1129 config NEED_DMA_MAP_STATE
652 bool "Cortex-A76/Neoverse-N1: MRC read !! 1130 bool
653 default y <<
654 depends on COMPAT <<
655 help <<
656 This option adds a workaround for AR <<
657 errata 1188873 and 1418040. <<
658 1131
659 Affected Cortex-A76/Neoverse-N1 core !! 1132 config SYS_HAS_EARLY_PRINTK
660 cause register corruption when acces !! 1133 bool
661 from AArch32 userspace. <<
662 1134
663 If unsure, say Y. !! 1135 config SYS_SUPPORTS_HOTPLUG_CPU
>> 1136 bool
664 1137
665 config ARM64_WORKAROUND_SPECULATIVE_AT !! 1138 config MIPS_BONITO64
666 bool 1139 bool
667 1140
668 config ARM64_ERRATUM_1165522 !! 1141 config MIPS_MSC
669 bool "Cortex-A76: 1165522: Speculative !! 1142 bool
670 default y <<
671 select ARM64_WORKAROUND_SPECULATIVE_AT <<
672 help <<
673 This option adds a workaround for AR <<
674 1143
675 Affected Cortex-A76 cores (r0p0, r1p !! 1144 config MIPS_NILE4
676 corrupted TLBs by speculating an AT !! 1145 bool
677 context switch. <<
678 1146
679 If unsure, say Y. !! 1147 config SYNC_R4K
>> 1148 bool
680 1149
681 config ARM64_ERRATUM_1319367 !! 1150 config MIPS_MACHINE
682 bool "Cortex-A57/A72: 1319537: Specula !! 1151 def_bool n
683 default y <<
684 select ARM64_WORKAROUND_SPECULATIVE_AT <<
685 help <<
686 This option adds work arounds for AR <<
687 and A72 erratum 1319367 <<
688 1152
689 Cortex-A57 and A72 cores could end-u !! 1153 config NO_IOPORT_MAP
690 speculating an AT instruction during !! 1154 def_bool n
691 1155
692 If unsure, say Y. !! 1156 config GENERIC_CSUM
>> 1157 bool
693 1158
694 config ARM64_ERRATUM_1530923 !! 1159 config GENERIC_ISA_DMA
695 bool "Cortex-A55: 1530923: Speculative !! 1160 bool
696 default y !! 1161 select ZONE_DMA if GENERIC_ISA_DMA_SUPPORT_BROKEN=n
697 select ARM64_WORKAROUND_SPECULATIVE_AT !! 1162 select ISA_DMA_API
698 help <<
699 This option adds a workaround for AR <<
700 1163
701 Affected Cortex-A55 cores (r0p0, r0p !! 1164 config GENERIC_ISA_DMA_SUPPORT_BROKEN
702 corrupted TLBs by speculating an AT !! 1165 bool
703 context switch. !! 1166 select GENERIC_ISA_DMA
704 1167
705 If unsure, say Y. !! 1168 config ISA_DMA_API
>> 1169 bool
706 1170
707 config ARM64_WORKAROUND_REPEAT_TLBI !! 1171 config HOLES_IN_ZONE
708 bool 1172 bool
709 1173
710 config ARM64_ERRATUM_2441007 !! 1174 config SYS_SUPPORTS_RELOCATABLE
711 bool "Cortex-A55: Completion of affect !! 1175 bool
712 select ARM64_WORKAROUND_REPEAT_TLBI <<
713 help 1176 help
714 This option adds a workaround for AR !! 1177 Selected if the platform supports relocating the kernel.
715 !! 1178 The platform must provide plat_get_fdt() if it selects CONFIG_USE_OF
716 Under very rare circumstances, affec !! 1179 to allow access to command line and entropy sources.
717 may not handle a race between a brea <<
718 CPU, and another CPU accessing the s <<
719 store to a page that has been unmapp <<
720 <<
721 Work around this by adding the affec <<
722 TLB sequences to be done twice. <<
723 <<
724 If unsure, say N. <<
725 <<
726 config ARM64_ERRATUM_1286807 <<
727 bool "Cortex-A76: Modification of the <<
728 select ARM64_WORKAROUND_REPEAT_TLBI <<
729 help <<
730 This option adds a workaround for AR <<
731 <<
732 On the affected Cortex-A76 cores (r0 <<
733 address for a cacheable mapping of a <<
734 accessed by a core while another cor <<
735 address to a new physical page using <<
736 break-before-make sequence, then und <<
737 TLBI+DSB completes before a read usi <<
738 invalidated has been observed by oth <<
739 workaround repeats the TLBI+DSB oper <<
740 1180
741 If unsure, say N. !! 1181 #
742 !! 1182 # Endianness selection. Sufficiently obscure so many users don't know what to
743 config ARM64_ERRATUM_1463225 !! 1183 # answer,so we try hard to limit the available choices. Also the use of a
744 bool "Cortex-A76: Software Step might !! 1184 # choice statement should be more obvious to the user.
745 default y !! 1185 #
>> 1186 choice
>> 1187 prompt "Endianness selection"
746 help 1188 help
747 This option adds a workaround for Ar !! 1189 Some MIPS machines can be configured for either little or big endian
>> 1190 byte order. These modes require different kernels and a different
>> 1191 Linux distribution. In general there is one preferred byteorder for a
>> 1192 particular system but some systems are just as commonly used in the
>> 1193 one or the other endianness.
748 1194
749 On the affected Cortex-A76 cores (r0 !! 1195 config CPU_BIG_ENDIAN
750 of a system call instruction (SVC) c !! 1196 bool "Big endian"
751 subsequent interrupts when software !! 1197 depends on SYS_SUPPORTS_BIG_ENDIAN
752 exception handler of the system call <<
753 is enabled or VHE is in use. <<
754 1198
755 Work around the erratum by triggerin !! 1199 config CPU_LITTLE_ENDIAN
756 when handling a system call from a t !! 1200 bool "Little endian"
757 in a VHE configuration of the kernel !! 1201 depends on SYS_SUPPORTS_LITTLE_ENDIAN
758 1202
759 If unsure, say Y. !! 1203 endchoice
760 1204
761 config ARM64_ERRATUM_1542419 !! 1205 config EXPORT_UASM
762 bool "Neoverse-N1: workaround mis-orde !! 1206 bool
763 help <<
764 This option adds a workaround for AR <<
765 1542419. <<
766 1207
767 Affected Neoverse-N1 cores could exe !! 1208 config SYS_SUPPORTS_APM_EMULATION
768 modified by another CPU. The workaro !! 1209 bool
769 counterpart. <<
770 1210
771 Workaround the issue by hiding the D !! 1211 config SYS_SUPPORTS_BIG_ENDIAN
772 forces user-space to perform cache m !! 1212 bool
773 1213
774 If unsure, say N. !! 1214 config SYS_SUPPORTS_LITTLE_ENDIAN
>> 1215 bool
775 1216
776 config ARM64_ERRATUM_1508412 !! 1217 config SYS_SUPPORTS_HUGETLBFS
777 bool "Cortex-A77: 1508412: workaround !! 1218 bool
>> 1219 depends on CPU_SUPPORTS_HUGEPAGES && 64BIT
778 default y 1220 default y
779 help <<
780 This option adds a workaround for Ar <<
781 1221
782 Affected Cortex-A77 cores (r0p0, r1p !! 1222 config MIPS_HUGE_TLB_SUPPORT
783 of a store-exclusive or read of PAR_ !! 1223 def_bool HUGETLB_PAGE || TRANSPARENT_HUGEPAGE
784 non-cacheable memory attributes. The <<
785 counterpart. <<
786 1224
787 KVM guests must also have the workar !! 1225 config IRQ_CPU_RM7K
788 deadlock the system. !! 1226 bool
789 1227
790 Work around the issue by inserting D !! 1228 config IRQ_MSP_SLP
791 register reads and warning KVM users !! 1229 bool
792 to prevent a speculative PAR_EL1 rea <<
793 1230
794 If unsure, say Y. !! 1231 config IRQ_MSP_CIC
>> 1232 bool
795 1233
796 config ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MO !! 1234 config IRQ_TXX9
797 bool 1235 bool
798 1236
799 config ARM64_ERRATUM_2051678 !! 1237 config IRQ_GT641XX
800 bool "Cortex-A510: 2051678: disable Ha !! 1238 bool
801 default y <<
802 help <<
803 This options adds the workaround for <<
804 Affected Cortex-A510 might not respe <<
805 hardware update of the page table's <<
806 is to not enable the feature on affe <<
807 1239
808 If unsure, say Y. !! 1240 config PCI_GT64XXX_PCI0
>> 1241 bool
809 1242
810 config ARM64_ERRATUM_2077057 !! 1243 config NO_EXCEPT_FILL
811 bool "Cortex-A510: 2077057: workaround !! 1244 bool
812 default y <<
813 help <<
814 This option adds the workaround for <<
815 Affected Cortex-A510 may corrupt SPS <<
816 expected, but a Pointer Authenticati <<
817 erratum causes SPSR_EL1 to be copied <<
818 EL1 to cause a return to EL2 with a <<
819 1245
820 This can only happen when EL2 is ste !! 1246 config SOC_EMMA2RH
>> 1247 bool
>> 1248 select CEVT_R4K
>> 1249 select CSRC_R4K
>> 1250 select DMA_NONCOHERENT
>> 1251 select IRQ_MIPS_CPU
>> 1252 select SWAP_IO_SPACE
>> 1253 select SYS_HAS_CPU_R5500
>> 1254 select SYS_SUPPORTS_32BIT_KERNEL
>> 1255 select SYS_SUPPORTS_64BIT_KERNEL
>> 1256 select SYS_SUPPORTS_BIG_ENDIAN
821 1257
822 When these conditions occur, the SPS !! 1258 config SOC_PNX833X
823 previous guest entry, and can be res !! 1259 bool
>> 1260 select CEVT_R4K
>> 1261 select CSRC_R4K
>> 1262 select IRQ_MIPS_CPU
>> 1263 select DMA_NONCOHERENT
>> 1264 select SYS_HAS_CPU_MIPS32_R2
>> 1265 select SYS_SUPPORTS_32BIT_KERNEL
>> 1266 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 1267 select SYS_SUPPORTS_BIG_ENDIAN
>> 1268 select SYS_SUPPORTS_MIPS16
>> 1269 select CPU_MIPSR2_IRQ_VI
824 1270
825 If unsure, say Y. !! 1271 config SOC_PNX8335
>> 1272 bool
>> 1273 select SOC_PNX833X
826 1274
827 config ARM64_ERRATUM_2658417 !! 1275 config MIPS_SPRAM
828 bool "Cortex-A510: 2658417: remove BF1 !! 1276 bool
829 default y <<
830 help <<
831 This option adds the workaround for <<
832 Affected Cortex-A510 (r0p0 to r1p1) <<
833 BFMMLA or VMMLA instructions in rare <<
834 A510 CPUs are using shared neon hard <<
835 discoverable by the kernel, hide the <<
836 user-space should not be using these <<
837 1277
838 If unsure, say Y. !! 1278 config SWAP_IO_SPACE
>> 1279 bool
839 1280
840 config ARM64_ERRATUM_2119858 !! 1281 config SGI_HAS_INDYDOG
841 bool "Cortex-A710/X2: 2119858: workaro !! 1282 bool
842 default y <<
843 depends on CORESIGHT_TRBE <<
844 select ARM64_WORKAROUND_TRBE_OVERWRITE <<
845 help <<
846 This option adds the workaround for <<
847 1283
848 Affected Cortex-A710/X2 cores could !! 1284 config SGI_HAS_HAL2
849 data at the base of the buffer (poin !! 1285 bool
850 the event of a WRAP event. <<
851 1286
852 Work around the issue by always maki !! 1287 config SGI_HAS_SEEQ
853 256 bytes before enabling the buffer !! 1288 bool
854 the buffer with ETM ignore packets u <<
855 1289
856 If unsure, say Y. !! 1290 config SGI_HAS_WD93
>> 1291 bool
857 1292
858 config ARM64_ERRATUM_2139208 !! 1293 config SGI_HAS_ZILOG
859 bool "Neoverse-N2: 2139208: workaround !! 1294 bool
860 default y <<
861 depends on CORESIGHT_TRBE <<
862 select ARM64_WORKAROUND_TRBE_OVERWRITE <<
863 help <<
864 This option adds the workaround for <<
865 1295
866 Affected Neoverse-N2 cores could ove !! 1296 config SGI_HAS_I8042
867 data at the base of the buffer (poin !! 1297 bool
868 the event of a WRAP event. <<
869 1298
870 Work around the issue by always maki !! 1299 config DEFAULT_SGI_PARTITION
871 256 bytes before enabling the buffer !! 1300 bool
872 the buffer with ETM ignore packets u <<
873 1301
874 If unsure, say Y. !! 1302 config FW_ARC32
>> 1303 bool
875 1304
876 config ARM64_WORKAROUND_TSB_FLUSH_FAILURE !! 1305 config FW_SNIPROM
877 bool 1306 bool
878 1307
879 config ARM64_ERRATUM_2054223 !! 1308 config BOOT_ELF32
880 bool "Cortex-A710: 2054223: workaround !! 1309 bool
881 default y <<
882 select ARM64_WORKAROUND_TSB_FLUSH_FAIL <<
883 help <<
884 Enable workaround for ARM Cortex-A71 <<
885 1310
886 Affected cores may fail to flush the !! 1311 config MIPS_L1_CACHE_SHIFT_4
887 the PE is in trace prohibited state. !! 1312 bool
888 of the trace cached. <<
889 1313
890 Workaround is to issue two TSB conse !! 1314 config MIPS_L1_CACHE_SHIFT_5
>> 1315 bool
891 1316
892 If unsure, say Y. !! 1317 config MIPS_L1_CACHE_SHIFT_6
>> 1318 bool
893 1319
894 config ARM64_ERRATUM_2067961 !! 1320 config MIPS_L1_CACHE_SHIFT_7
895 bool "Neoverse-N2: 2067961: workaround !! 1321 bool
896 default y <<
897 select ARM64_WORKAROUND_TSB_FLUSH_FAIL <<
898 help <<
899 Enable workaround for ARM Neoverse-N <<
900 1322
901 Affected cores may fail to flush the !! 1323 config MIPS_L1_CACHE_SHIFT
902 the PE is in trace prohibited state. !! 1324 int
903 of the trace cached. !! 1325 default "7" if MIPS_L1_CACHE_SHIFT_7
>> 1326 default "6" if MIPS_L1_CACHE_SHIFT_6
>> 1327 default "5" if MIPS_L1_CACHE_SHIFT_5
>> 1328 default "4" if MIPS_L1_CACHE_SHIFT_4
>> 1329 default "5"
904 1330
905 Workaround is to issue two TSB conse !! 1331 config HAVE_STD_PC_SERIAL_PORT
>> 1332 bool
906 1333
907 If unsure, say Y. !! 1334 config ARC_CONSOLE
>> 1335 bool "ARC console support"
>> 1336 depends on SGI_IP22 || SGI_IP28 || (SNI_RM && CPU_LITTLE_ENDIAN)
908 1337
909 config ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANG !! 1338 config ARC_MEMORY
910 bool 1339 bool
911 !! 1340 depends on MACH_JAZZ || SNI_RM || SGI_IP32
912 config ARM64_ERRATUM_2253138 <<
913 bool "Neoverse-N2: 2253138: workaround <<
914 depends on CORESIGHT_TRBE <<
915 default y 1341 default y
916 select ARM64_WORKAROUND_TRBE_WRITE_OUT <<
917 help <<
918 This option adds the workaround for <<
919 <<
920 Affected Neoverse-N2 cores might wri <<
921 for TRBE. Under some conditions, the <<
922 virtually addressed page following t <<
923 (i.e., the TRBLIMITR_EL1.LIMIT), ins <<
924 1342
925 Work around this in the driver by al !! 1343 config ARC_PROMLIB
926 page beyond the TRBLIMITR_EL1.LIMIT, !! 1344 bool
927 !! 1345 depends on MACH_JAZZ || SNI_RM || SGI_IP22 || SGI_IP28 || SGI_IP32
928 If unsure, say Y. <<
929 <<
930 config ARM64_ERRATUM_2224489 <<
931 bool "Cortex-A710/X2: 2224489: workaro <<
932 depends on CORESIGHT_TRBE <<
933 default y 1346 default y
934 select ARM64_WORKAROUND_TRBE_WRITE_OUT <<
935 help <<
936 This option adds the workaround for <<
937 <<
938 Affected Cortex-A710/X2 cores might <<
939 for TRBE. Under some conditions, the <<
940 virtually addressed page following t <<
941 (i.e., the TRBLIMITR_EL1.LIMIT), ins <<
942 1347
943 Work around this in the driver by al !! 1348 config FW_ARC64
944 page beyond the TRBLIMITR_EL1.LIMIT, !! 1349 bool
945 <<
946 If unsure, say Y. <<
947 1350
948 config ARM64_ERRATUM_2441009 !! 1351 config BOOT_ELF64
949 bool "Cortex-A510: Completion of affec !! 1352 bool
950 select ARM64_WORKAROUND_REPEAT_TLBI <<
951 help <<
952 This option adds a workaround for AR <<
953 <<
954 Under very rare circumstances, affec <<
955 may not handle a race between a brea <<
956 CPU, and another CPU accessing the s <<
957 store to a page that has been unmapp <<
958 1353
959 Work around this by adding the affec !! 1354 menu "CPU selection"
960 TLB sequences to be done twice. <<
961 1355
962 If unsure, say N. !! 1356 choice
>> 1357 prompt "CPU type"
>> 1358 default CPU_R4X00
963 1359
964 config ARM64_ERRATUM_2064142 !! 1360 config CPU_LOONGSON3
965 bool "Cortex-A510: 2064142: workaround !! 1361 bool "Loongson 3 CPU"
966 depends on CORESIGHT_TRBE !! 1362 depends on SYS_HAS_CPU_LOONGSON3
967 default y !! 1363 select CPU_SUPPORTS_64BIT_KERNEL
>> 1364 select CPU_SUPPORTS_HIGHMEM
>> 1365 select CPU_SUPPORTS_HUGEPAGES
>> 1366 select WEAK_ORDERING
>> 1367 select WEAK_REORDERING_BEYOND_LLSC
>> 1368 select MIPS_PGD_C0_CONTEXT
>> 1369 select MIPS_L1_CACHE_SHIFT_6
>> 1370 select GPIOLIB
968 help 1371 help
969 This option adds the workaround for !! 1372 The Loongson 3 processor implements the MIPS64R2 instruction
970 !! 1373 set with many extensions.
971 Affected Cortex-A510 core might fail <<
972 TRBE has been disabled. Under some c <<
973 writes into TRBE registers TRBLIMITR <<
974 and TRBTRG_EL1 will be ignored and w <<
975 1374
976 Work around this in the driver by ex !! 1375 config LOONGSON3_ENHANCEMENT
977 is stopped and before performing a s !! 1376 bool "New Loongson 3 CPU Enhancements"
978 registers. !! 1377 default n
>> 1378 select CPU_MIPSR2
>> 1379 select CPU_HAS_PREFETCH
>> 1380 depends on CPU_LOONGSON3
>> 1381 help
>> 1382 New Loongson 3 CPU (since Loongson-3A R2, as opposed to Loongson-3A
>> 1383 R1, Loongson-3B R1 and Loongson-3B R2) has many enhancements, such as
>> 1384 FTLB, L1-VCache, EI/DI/Wait/Prefetch instruction, DSP/DSPv2 ASE, User
>> 1385 Local register, Read-Inhibit/Execute-Inhibit, SFB (Store Fill Buffer),
>> 1386 Fast TLB refill support, etc.
>> 1387
>> 1388 This option enable those enhancements which are not probed at run
>> 1389 time. If you want a generic kernel to run on all Loongson 3 machines,
>> 1390 please say 'N' here. If you want a high-performance kernel to run on
>> 1391 new Loongson 3 machines only, please say 'Y' here.
>> 1392
>> 1393 config CPU_LOONGSON2E
>> 1394 bool "Loongson 2E"
>> 1395 depends on SYS_HAS_CPU_LOONGSON2E
>> 1396 select CPU_LOONGSON2
>> 1397 help
>> 1398 The Loongson 2E processor implements the MIPS III instruction set
>> 1399 with many extensions.
>> 1400
>> 1401 It has an internal FPGA northbridge, which is compatible to
>> 1402 bonito64.
>> 1403
>> 1404 config CPU_LOONGSON2F
>> 1405 bool "Loongson 2F"
>> 1406 depends on SYS_HAS_CPU_LOONGSON2F
>> 1407 select CPU_LOONGSON2
>> 1408 select GPIOLIB
>> 1409 help
>> 1410 The Loongson 2F processor implements the MIPS III instruction set
>> 1411 with many extensions.
>> 1412
>> 1413 Loongson2F have built-in DDR2 and PCIX controller. The PCIX controller
>> 1414 have a similar programming interface with FPGA northbridge used in
>> 1415 Loongson2E.
>> 1416
>> 1417 config CPU_LOONGSON1B
>> 1418 bool "Loongson 1B"
>> 1419 depends on SYS_HAS_CPU_LOONGSON1B
>> 1420 select CPU_LOONGSON1
>> 1421 select LEDS_GPIO_REGISTER
>> 1422 help
>> 1423 The Loongson 1B is a 32-bit SoC, which implements the MIPS32
>> 1424 release 2 instruction set.
>> 1425
>> 1426 config CPU_LOONGSON1C
>> 1427 bool "Loongson 1C"
>> 1428 depends on SYS_HAS_CPU_LOONGSON1C
>> 1429 select CPU_LOONGSON1
>> 1430 select LEDS_GPIO_REGISTER
>> 1431 help
>> 1432 The Loongson 1C is a 32-bit SoC, which implements the MIPS32
>> 1433 release 2 instruction set.
>> 1434
>> 1435 config CPU_MIPS32_R1
>> 1436 bool "MIPS32 Release 1"
>> 1437 depends on SYS_HAS_CPU_MIPS32_R1
>> 1438 select CPU_HAS_PREFETCH
>> 1439 select CPU_SUPPORTS_32BIT_KERNEL
>> 1440 select CPU_SUPPORTS_HIGHMEM
>> 1441 help
>> 1442 Choose this option to build a kernel for release 1 or later of the
>> 1443 MIPS32 architecture. Most modern embedded systems with a 32-bit
>> 1444 MIPS processor are based on a MIPS32 processor. If you know the
>> 1445 specific type of processor in your system, choose those that one
>> 1446 otherwise CPU_MIPS32_R1 is a safe bet for any MIPS32 system.
>> 1447 Release 2 of the MIPS32 architecture is available since several
>> 1448 years so chances are you even have a MIPS32 Release 2 processor
>> 1449 in which case you should choose CPU_MIPS32_R2 instead for better
>> 1450 performance.
>> 1451
>> 1452 config CPU_MIPS32_R2
>> 1453 bool "MIPS32 Release 2"
>> 1454 depends on SYS_HAS_CPU_MIPS32_R2
>> 1455 select CPU_HAS_PREFETCH
>> 1456 select CPU_SUPPORTS_32BIT_KERNEL
>> 1457 select CPU_SUPPORTS_HIGHMEM
>> 1458 select CPU_SUPPORTS_MSA
>> 1459 select HAVE_KVM
>> 1460 help
>> 1461 Choose this option to build a kernel for release 2 or later of the
>> 1462 MIPS32 architecture. Most modern embedded systems with a 32-bit
>> 1463 MIPS processor are based on a MIPS32 processor. If you know the
>> 1464 specific type of processor in your system, choose those that one
>> 1465 otherwise CPU_MIPS32_R1 is a safe bet for any MIPS32 system.
>> 1466
>> 1467 config CPU_MIPS32_R6
>> 1468 bool "MIPS32 Release 6"
>> 1469 depends on SYS_HAS_CPU_MIPS32_R6
>> 1470 select CPU_HAS_PREFETCH
>> 1471 select CPU_SUPPORTS_32BIT_KERNEL
>> 1472 select CPU_SUPPORTS_HIGHMEM
>> 1473 select CPU_SUPPORTS_MSA
>> 1474 select GENERIC_CSUM
>> 1475 select HAVE_KVM
>> 1476 select MIPS_O32_FP64_SUPPORT
>> 1477 help
>> 1478 Choose this option to build a kernel for release 6 or later of the
>> 1479 MIPS32 architecture. New MIPS processors, starting with the Warrior
>> 1480 family, are based on a MIPS32r6 processor. If you own an older
>> 1481 processor, you probably need to select MIPS32r1 or MIPS32r2 instead.
>> 1482
>> 1483 config CPU_MIPS64_R1
>> 1484 bool "MIPS64 Release 1"
>> 1485 depends on SYS_HAS_CPU_MIPS64_R1
>> 1486 select CPU_HAS_PREFETCH
>> 1487 select CPU_SUPPORTS_32BIT_KERNEL
>> 1488 select CPU_SUPPORTS_64BIT_KERNEL
>> 1489 select CPU_SUPPORTS_HIGHMEM
>> 1490 select CPU_SUPPORTS_HUGEPAGES
>> 1491 help
>> 1492 Choose this option to build a kernel for release 1 or later of the
>> 1493 MIPS64 architecture. Many modern embedded systems with a 64-bit
>> 1494 MIPS processor are based on a MIPS64 processor. If you know the
>> 1495 specific type of processor in your system, choose those that one
>> 1496 otherwise CPU_MIPS64_R1 is a safe bet for any MIPS64 system.
>> 1497 Release 2 of the MIPS64 architecture is available since several
>> 1498 years so chances are you even have a MIPS64 Release 2 processor
>> 1499 in which case you should choose CPU_MIPS64_R2 instead for better
>> 1500 performance.
>> 1501
>> 1502 config CPU_MIPS64_R2
>> 1503 bool "MIPS64 Release 2"
>> 1504 depends on SYS_HAS_CPU_MIPS64_R2
>> 1505 select CPU_HAS_PREFETCH
>> 1506 select CPU_SUPPORTS_32BIT_KERNEL
>> 1507 select CPU_SUPPORTS_64BIT_KERNEL
>> 1508 select CPU_SUPPORTS_HIGHMEM
>> 1509 select CPU_SUPPORTS_HUGEPAGES
>> 1510 select CPU_SUPPORTS_MSA
>> 1511 select HAVE_KVM
>> 1512 help
>> 1513 Choose this option to build a kernel for release 2 or later of the
>> 1514 MIPS64 architecture. Many modern embedded systems with a 64-bit
>> 1515 MIPS processor are based on a MIPS64 processor. If you know the
>> 1516 specific type of processor in your system, choose those that one
>> 1517 otherwise CPU_MIPS64_R1 is a safe bet for any MIPS64 system.
>> 1518
>> 1519 config CPU_MIPS64_R6
>> 1520 bool "MIPS64 Release 6"
>> 1521 depends on SYS_HAS_CPU_MIPS64_R6
>> 1522 select CPU_HAS_PREFETCH
>> 1523 select CPU_SUPPORTS_32BIT_KERNEL
>> 1524 select CPU_SUPPORTS_64BIT_KERNEL
>> 1525 select CPU_SUPPORTS_HIGHMEM
>> 1526 select CPU_SUPPORTS_MSA
>> 1527 select GENERIC_CSUM
>> 1528 select MIPS_O32_FP64_SUPPORT if 32BIT || MIPS32_O32
>> 1529 select HAVE_KVM
>> 1530 help
>> 1531 Choose this option to build a kernel for release 6 or later of the
>> 1532 MIPS64 architecture. New MIPS processors, starting with the Warrior
>> 1533 family, are based on a MIPS64r6 processor. If you own an older
>> 1534 processor, you probably need to select MIPS64r1 or MIPS64r2 instead.
>> 1535
>> 1536 config CPU_R3000
>> 1537 bool "R3000"
>> 1538 depends on SYS_HAS_CPU_R3000
>> 1539 select CPU_HAS_WB
>> 1540 select CPU_SUPPORTS_32BIT_KERNEL
>> 1541 select CPU_SUPPORTS_HIGHMEM
>> 1542 help
>> 1543 Please make sure to pick the right CPU type. Linux/MIPS is not
>> 1544 designed to be generic, i.e. Kernels compiled for R3000 CPUs will
>> 1545 *not* work on R4000 machines and vice versa. However, since most
>> 1546 of the supported machines have an R4000 (or similar) CPU, R4x00
>> 1547 might be a safe bet. If the resulting kernel does not work,
>> 1548 try to recompile with R3000.
>> 1549
>> 1550 config CPU_TX39XX
>> 1551 bool "R39XX"
>> 1552 depends on SYS_HAS_CPU_TX39XX
>> 1553 select CPU_SUPPORTS_32BIT_KERNEL
>> 1554
>> 1555 config CPU_VR41XX
>> 1556 bool "R41xx"
>> 1557 depends on SYS_HAS_CPU_VR41XX
>> 1558 select CPU_SUPPORTS_32BIT_KERNEL
>> 1559 select CPU_SUPPORTS_64BIT_KERNEL
>> 1560 help
>> 1561 The options selects support for the NEC VR4100 series of processors.
>> 1562 Only choose this option if you have one of these processors as a
>> 1563 kernel built with this option will not run on any other type of
>> 1564 processor or vice versa.
>> 1565
>> 1566 config CPU_R4300
>> 1567 bool "R4300"
>> 1568 depends on SYS_HAS_CPU_R4300
>> 1569 select CPU_SUPPORTS_32BIT_KERNEL
>> 1570 select CPU_SUPPORTS_64BIT_KERNEL
>> 1571 help
>> 1572 MIPS Technologies R4300-series processors.
>> 1573
>> 1574 config CPU_R4X00
>> 1575 bool "R4x00"
>> 1576 depends on SYS_HAS_CPU_R4X00
>> 1577 select CPU_SUPPORTS_32BIT_KERNEL
>> 1578 select CPU_SUPPORTS_64BIT_KERNEL
>> 1579 select CPU_SUPPORTS_HUGEPAGES
>> 1580 help
>> 1581 MIPS Technologies R4000-series processors other than 4300, including
>> 1582 the R4000, R4400, R4600, and 4700.
>> 1583
>> 1584 config CPU_TX49XX
>> 1585 bool "R49XX"
>> 1586 depends on SYS_HAS_CPU_TX49XX
>> 1587 select CPU_HAS_PREFETCH
>> 1588 select CPU_SUPPORTS_32BIT_KERNEL
>> 1589 select CPU_SUPPORTS_64BIT_KERNEL
>> 1590 select CPU_SUPPORTS_HUGEPAGES
>> 1591
>> 1592 config CPU_R5000
>> 1593 bool "R5000"
>> 1594 depends on SYS_HAS_CPU_R5000
>> 1595 select CPU_SUPPORTS_32BIT_KERNEL
>> 1596 select CPU_SUPPORTS_64BIT_KERNEL
>> 1597 select CPU_SUPPORTS_HUGEPAGES
>> 1598 help
>> 1599 MIPS Technologies R5000-series processors other than the Nevada.
>> 1600
>> 1601 config CPU_R5432
>> 1602 bool "R5432"
>> 1603 depends on SYS_HAS_CPU_R5432
>> 1604 select CPU_SUPPORTS_32BIT_KERNEL
>> 1605 select CPU_SUPPORTS_64BIT_KERNEL
>> 1606 select CPU_SUPPORTS_HUGEPAGES
>> 1607
>> 1608 config CPU_R5500
>> 1609 bool "R5500"
>> 1610 depends on SYS_HAS_CPU_R5500
>> 1611 select CPU_SUPPORTS_32BIT_KERNEL
>> 1612 select CPU_SUPPORTS_64BIT_KERNEL
>> 1613 select CPU_SUPPORTS_HUGEPAGES
>> 1614 help
>> 1615 NEC VR5500 and VR5500A series processors implement 64-bit MIPS IV
>> 1616 instruction set.
>> 1617
>> 1618 config CPU_R6000
>> 1619 bool "R6000"
>> 1620 depends on SYS_HAS_CPU_R6000
>> 1621 select CPU_SUPPORTS_32BIT_KERNEL
>> 1622 help
>> 1623 MIPS Technologies R6000 and R6000A series processors. Note these
>> 1624 processors are extremely rare and the support for them is incomplete.
>> 1625
>> 1626 config CPU_NEVADA
>> 1627 bool "RM52xx"
>> 1628 depends on SYS_HAS_CPU_NEVADA
>> 1629 select CPU_SUPPORTS_32BIT_KERNEL
>> 1630 select CPU_SUPPORTS_64BIT_KERNEL
>> 1631 select CPU_SUPPORTS_HUGEPAGES
>> 1632 help
>> 1633 QED / PMC-Sierra RM52xx-series ("Nevada") processors.
>> 1634
>> 1635 config CPU_R8000
>> 1636 bool "R8000"
>> 1637 depends on SYS_HAS_CPU_R8000
>> 1638 select CPU_HAS_PREFETCH
>> 1639 select CPU_SUPPORTS_64BIT_KERNEL
>> 1640 help
>> 1641 MIPS Technologies R8000 processors. Note these processors are
>> 1642 uncommon and the support for them is incomplete.
>> 1643
>> 1644 config CPU_R10000
>> 1645 bool "R10000"
>> 1646 depends on SYS_HAS_CPU_R10000
>> 1647 select CPU_HAS_PREFETCH
>> 1648 select CPU_SUPPORTS_32BIT_KERNEL
>> 1649 select CPU_SUPPORTS_64BIT_KERNEL
>> 1650 select CPU_SUPPORTS_HIGHMEM
>> 1651 select CPU_SUPPORTS_HUGEPAGES
>> 1652 help
>> 1653 MIPS Technologies R10000-series processors.
>> 1654
>> 1655 config CPU_RM7000
>> 1656 bool "RM7000"
>> 1657 depends on SYS_HAS_CPU_RM7000
>> 1658 select CPU_HAS_PREFETCH
>> 1659 select CPU_SUPPORTS_32BIT_KERNEL
>> 1660 select CPU_SUPPORTS_64BIT_KERNEL
>> 1661 select CPU_SUPPORTS_HIGHMEM
>> 1662 select CPU_SUPPORTS_HUGEPAGES
>> 1663
>> 1664 config CPU_SB1
>> 1665 bool "SB1"
>> 1666 depends on SYS_HAS_CPU_SB1
>> 1667 select CPU_SUPPORTS_32BIT_KERNEL
>> 1668 select CPU_SUPPORTS_64BIT_KERNEL
>> 1669 select CPU_SUPPORTS_HIGHMEM
>> 1670 select CPU_SUPPORTS_HUGEPAGES
>> 1671 select WEAK_ORDERING
>> 1672
>> 1673 config CPU_CAVIUM_OCTEON
>> 1674 bool "Cavium Octeon processor"
>> 1675 depends on SYS_HAS_CPU_CAVIUM_OCTEON
>> 1676 select CPU_HAS_PREFETCH
>> 1677 select CPU_SUPPORTS_64BIT_KERNEL
>> 1678 select WEAK_ORDERING
>> 1679 select CPU_SUPPORTS_HIGHMEM
>> 1680 select CPU_SUPPORTS_HUGEPAGES
>> 1681 select USB_EHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 1682 select USB_OHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 1683 select MIPS_L1_CACHE_SHIFT_7
>> 1684 select HAVE_KVM
>> 1685 help
>> 1686 The Cavium Octeon processor is a highly integrated chip containing
>> 1687 many ethernet hardware widgets for networking tasks. The processor
>> 1688 can have up to 16 Mips64v2 cores and 8 integrated gigabit ethernets.
>> 1689 Full details can be found at http://www.caviumnetworks.com.
>> 1690
>> 1691 config CPU_BMIPS
>> 1692 bool "Broadcom BMIPS"
>> 1693 depends on SYS_HAS_CPU_BMIPS
>> 1694 select CPU_MIPS32
>> 1695 select CPU_BMIPS32_3300 if SYS_HAS_CPU_BMIPS32_3300
>> 1696 select CPU_BMIPS4350 if SYS_HAS_CPU_BMIPS4350
>> 1697 select CPU_BMIPS4380 if SYS_HAS_CPU_BMIPS4380
>> 1698 select CPU_BMIPS5000 if SYS_HAS_CPU_BMIPS5000
>> 1699 select CPU_SUPPORTS_32BIT_KERNEL
>> 1700 select DMA_NONCOHERENT
>> 1701 select IRQ_MIPS_CPU
>> 1702 select SWAP_IO_SPACE
>> 1703 select WEAK_ORDERING
>> 1704 select CPU_SUPPORTS_HIGHMEM
>> 1705 select CPU_HAS_PREFETCH
>> 1706 select CPU_SUPPORTS_CPUFREQ
>> 1707 select MIPS_EXTERNAL_TIMER
>> 1708 help
>> 1709 Support for BMIPS32/3300/4350/4380 and BMIPS5000 processors.
>> 1710
>> 1711 config CPU_XLR
>> 1712 bool "Netlogic XLR SoC"
>> 1713 depends on SYS_HAS_CPU_XLR
>> 1714 select CPU_SUPPORTS_32BIT_KERNEL
>> 1715 select CPU_SUPPORTS_64BIT_KERNEL
>> 1716 select CPU_SUPPORTS_HIGHMEM
>> 1717 select CPU_SUPPORTS_HUGEPAGES
>> 1718 select WEAK_ORDERING
>> 1719 select WEAK_REORDERING_BEYOND_LLSC
>> 1720 help
>> 1721 Netlogic Microsystems XLR/XLS processors.
>> 1722
>> 1723 config CPU_XLP
>> 1724 bool "Netlogic XLP SoC"
>> 1725 depends on SYS_HAS_CPU_XLP
>> 1726 select CPU_SUPPORTS_32BIT_KERNEL
>> 1727 select CPU_SUPPORTS_64BIT_KERNEL
>> 1728 select CPU_SUPPORTS_HIGHMEM
>> 1729 select WEAK_ORDERING
>> 1730 select WEAK_REORDERING_BEYOND_LLSC
>> 1731 select CPU_HAS_PREFETCH
>> 1732 select CPU_MIPSR2
>> 1733 select CPU_SUPPORTS_HUGEPAGES
>> 1734 select MIPS_ASID_BITS_VARIABLE
>> 1735 help
>> 1736 Netlogic Microsystems XLP processors.
>> 1737 endchoice
979 1738
980 If unsure, say Y. !! 1739 config CPU_MIPS32_3_5_FEATURES
>> 1740 bool "MIPS32 Release 3.5 Features"
>> 1741 depends on SYS_HAS_CPU_MIPS32_R3_5
>> 1742 depends on CPU_MIPS32_R2 || CPU_MIPS32_R6
>> 1743 help
>> 1744 Choose this option to build a kernel for release 2 or later of the
>> 1745 MIPS32 architecture including features from the 3.5 release such as
>> 1746 support for Enhanced Virtual Addressing (EVA).
>> 1747
>> 1748 config CPU_MIPS32_3_5_EVA
>> 1749 bool "Enhanced Virtual Addressing (EVA)"
>> 1750 depends on CPU_MIPS32_3_5_FEATURES
>> 1751 select EVA
>> 1752 default y
>> 1753 help
>> 1754 Choose this option if you want to enable the Enhanced Virtual
>> 1755 Addressing (EVA) on your MIPS32 core (such as proAptiv).
>> 1756 One of its primary benefits is an increase in the maximum size
>> 1757 of lowmem (up to 3GB). If unsure, say 'N' here.
>> 1758
>> 1759 config CPU_MIPS32_R5_FEATURES
>> 1760 bool "MIPS32 Release 5 Features"
>> 1761 depends on SYS_HAS_CPU_MIPS32_R5
>> 1762 depends on CPU_MIPS32_R2
>> 1763 help
>> 1764 Choose this option to build a kernel for release 2 or later of the
>> 1765 MIPS32 architecture including features from release 5 such as
>> 1766 support for Extended Physical Addressing (XPA).
>> 1767
>> 1768 config CPU_MIPS32_R5_XPA
>> 1769 bool "Extended Physical Addressing (XPA)"
>> 1770 depends on CPU_MIPS32_R5_FEATURES
>> 1771 depends on !EVA
>> 1772 depends on !PAGE_SIZE_4KB
>> 1773 depends on SYS_SUPPORTS_HIGHMEM
>> 1774 select XPA
>> 1775 select HIGHMEM
>> 1776 select ARCH_PHYS_ADDR_T_64BIT
>> 1777 default n
>> 1778 help
>> 1779 Choose this option if you want to enable the Extended Physical
>> 1780 Addressing (XPA) on your MIPS32 core (such as P5600 series). The
>> 1781 benefit is to increase physical addressing equal to or greater
>> 1782 than 40 bits. Note that this has the side effect of turning on
>> 1783 64-bit addressing which in turn makes the PTEs 64-bit in size.
>> 1784 If unsure, say 'N' here.
981 1785
982 config ARM64_ERRATUM_2038923 !! 1786 if CPU_LOONGSON2F
983 bool "Cortex-A510: 2038923: workaround !! 1787 config CPU_NOP_WORKAROUNDS
984 depends on CORESIGHT_TRBE !! 1788 bool
985 default y <<
986 help <<
987 This option adds the workaround for <<
988 <<
989 Affected Cortex-A510 core might caus <<
990 prohibited within the CPU. As a resu <<
991 might be corrupted. This happens aft <<
992 TRBLIMITR_EL1.E, followed by just a <<
993 execution changes from a context, in <<
994 isn't, or vice versa. In these menti <<
995 is prohibited is inconsistent betwee <<
996 the trace buffer state might be corr <<
997 <<
998 Work around this in the driver by pr <<
999 trace is prohibited or not based on <<
1000 change to TRBLIMITR_EL1.E with at l <<
1001 two ISB instructions if no ERET is <<
1002 1789
1003 If unsure, say Y. !! 1790 config CPU_JUMP_WORKAROUNDS
>> 1791 bool
1004 1792
1005 config ARM64_ERRATUM_1902691 !! 1793 config CPU_LOONGSON2F_WORKAROUNDS
1006 bool "Cortex-A510: 1902691: workaroun !! 1794 bool "Loongson 2F Workarounds"
1007 depends on CORESIGHT_TRBE <<
1008 default y 1795 default y
>> 1796 select CPU_NOP_WORKAROUNDS
>> 1797 select CPU_JUMP_WORKAROUNDS
1009 help 1798 help
1010 This option adds the workaround for !! 1799 Loongson 2F01 / 2F02 processors have the NOP & JUMP issues which
>> 1800 require workarounds. Without workarounds the system may hang
>> 1801 unexpectedly. For more information please refer to the gas
>> 1802 -mfix-loongson2f-nop and -mfix-loongson2f-jump options.
>> 1803
>> 1804 Loongson 2F03 and later have fixed these issues and no workarounds
>> 1805 are needed. The workarounds have no significant side effect on them
>> 1806 but may decrease the performance of the system so this option should
>> 1807 be disabled unless the kernel is intended to be run on 2F01 or 2F02
>> 1808 systems.
1011 1809
1012 Affected Cortex-A510 core might cau !! 1810 If unsure, please say Y.
1013 into the memory. Effectively TRBE i !! 1811 endif # CPU_LOONGSON2F
1014 trace data. <<
1015 1812
1016 Work around this problem in the dri !! 1813 config SYS_SUPPORTS_ZBOOT
1017 affected cpus. The firmware must ha !! 1814 bool
1018 on such implementations. This will !! 1815 select HAVE_KERNEL_GZIP
1019 do this already. !! 1816 select HAVE_KERNEL_BZIP2
>> 1817 select HAVE_KERNEL_LZ4
>> 1818 select HAVE_KERNEL_LZMA
>> 1819 select HAVE_KERNEL_LZO
>> 1820 select HAVE_KERNEL_XZ
1020 1821
1021 If unsure, say Y. !! 1822 config SYS_SUPPORTS_ZBOOT_UART16550
>> 1823 bool
>> 1824 select SYS_SUPPORTS_ZBOOT
1022 1825
1023 config ARM64_ERRATUM_2457168 !! 1826 config SYS_SUPPORTS_ZBOOT_UART_PROM
1024 bool "Cortex-A510: 2457168: workaroun !! 1827 bool
1025 depends on ARM64_AMU_EXTN !! 1828 select SYS_SUPPORTS_ZBOOT
1026 default y <<
1027 help <<
1028 This option adds the workaround for <<
1029 1829
1030 The AMU counter AMEVCNTR01 (constan !! 1830 config CPU_LOONGSON2
1031 as the system counter. On affected !! 1831 bool
1032 incorrectly giving a significantly !! 1832 select CPU_SUPPORTS_32BIT_KERNEL
>> 1833 select CPU_SUPPORTS_64BIT_KERNEL
>> 1834 select CPU_SUPPORTS_HIGHMEM
>> 1835 select CPU_SUPPORTS_HUGEPAGES
1033 1836
1034 Work around this problem by returni !! 1837 config CPU_LOONGSON1
1035 key locations that results in disab !! 1838 bool
1036 is the same to firmware disabling a !! 1839 select CPU_MIPS32
>> 1840 select CPU_MIPSR2
>> 1841 select CPU_HAS_PREFETCH
>> 1842 select CPU_SUPPORTS_32BIT_KERNEL
>> 1843 select CPU_SUPPORTS_HIGHMEM
>> 1844 select CPU_SUPPORTS_CPUFREQ
1037 1845
1038 If unsure, say Y. !! 1846 config CPU_BMIPS32_3300
>> 1847 select SMP_UP if SMP
>> 1848 bool
1039 1849
1040 config ARM64_ERRATUM_2645198 !! 1850 config CPU_BMIPS4350
1041 bool "Cortex-A715: 2645198: Workaroun !! 1851 bool
1042 default y !! 1852 select SYS_SUPPORTS_SMP
1043 help !! 1853 select SYS_SUPPORTS_HOTPLUG_CPU
1044 This option adds the workaround for <<
1045 1854
1046 If a Cortex-A715 cpu sees a page ma !! 1855 config CPU_BMIPS4380
1047 to non-executable, it may corrupt t !! 1856 bool
1048 next instruction abort caused by pe !! 1857 select MIPS_L1_CACHE_SHIFT_6
>> 1858 select SYS_SUPPORTS_SMP
>> 1859 select SYS_SUPPORTS_HOTPLUG_CPU
>> 1860 select CPU_HAS_RIXI
1049 1861
1050 Only user-space does executable to !! 1862 config CPU_BMIPS5000
1051 mprotect() system call. Workaround !! 1863 bool
1052 TLB invalidation, for all changes t !! 1864 select MIPS_CPU_SCACHE
>> 1865 select MIPS_L1_CACHE_SHIFT_7
>> 1866 select SYS_SUPPORTS_SMP
>> 1867 select SYS_SUPPORTS_HOTPLUG_CPU
>> 1868 select CPU_HAS_RIXI
1053 1869
1054 If unsure, say Y. !! 1870 config SYS_HAS_CPU_LOONGSON3
>> 1871 bool
>> 1872 select CPU_SUPPORTS_CPUFREQ
>> 1873 select CPU_HAS_RIXI
1055 1874
1056 config ARM64_WORKAROUND_SPECULATIVE_UNPRIV_LO !! 1875 config SYS_HAS_CPU_LOONGSON2E
1057 bool 1876 bool
1058 1877
1059 config ARM64_ERRATUM_2966298 !! 1878 config SYS_HAS_CPU_LOONGSON2F
1060 bool "Cortex-A520: 2966298: workaroun !! 1879 bool
1061 select ARM64_WORKAROUND_SPECULATIVE_U !! 1880 select CPU_SUPPORTS_CPUFREQ
1062 default y !! 1881 select CPU_SUPPORTS_ADDRWINCFG if 64BIT
1063 help !! 1882 select CPU_SUPPORTS_UNCACHED_ACCELERATED
1064 This option adds the workaround for <<
1065 1883
1066 On an affected Cortex-A520 core, a !! 1884 config SYS_HAS_CPU_LOONGSON1B
1067 load might leak data from a privile !! 1885 bool
1068 1886
1069 Work around this problem by executi !! 1887 config SYS_HAS_CPU_LOONGSON1C
>> 1888 bool
1070 1889
1071 If unsure, say Y. !! 1890 config SYS_HAS_CPU_MIPS32_R1
>> 1891 bool
1072 1892
1073 config ARM64_ERRATUM_3117295 !! 1893 config SYS_HAS_CPU_MIPS32_R2
1074 bool "Cortex-A510: 3117295: workaroun !! 1894 bool
1075 select ARM64_WORKAROUND_SPECULATIVE_U <<
1076 default y <<
1077 help <<
1078 This option adds the workaround for <<
1079 1895
1080 On an affected Cortex-A510 core, a !! 1896 config SYS_HAS_CPU_MIPS32_R3_5
1081 load might leak data from a privile !! 1897 bool
1082 1898
1083 Work around this problem by executi !! 1899 config SYS_HAS_CPU_MIPS32_R5
>> 1900 bool
1084 1901
1085 If unsure, say Y. !! 1902 config SYS_HAS_CPU_MIPS32_R6
>> 1903 bool
1086 1904
1087 config ARM64_ERRATUM_3194386 !! 1905 config SYS_HAS_CPU_MIPS64_R1
1088 bool "Cortex-*/Neoverse-*: workaround !! 1906 bool
1089 default y <<
1090 help <<
1091 This option adds the workaround for <<
1092 1907
1093 * ARM Cortex-A76 erratum 3324349 !! 1908 config SYS_HAS_CPU_MIPS64_R2
1094 * ARM Cortex-A77 erratum 3324348 !! 1909 bool
1095 * ARM Cortex-A78 erratum 3324344 <<
1096 * ARM Cortex-A78C erratum 3324346 <<
1097 * ARM Cortex-A78C erratum 3324347 <<
1098 * ARM Cortex-A710 erratam 3324338 <<
1099 * ARM Cortex-A715 errartum 3456084 <<
1100 * ARM Cortex-A720 erratum 3456091 <<
1101 * ARM Cortex-A725 erratum 3456106 <<
1102 * ARM Cortex-X1 erratum 3324344 <<
1103 * ARM Cortex-X1C erratum 3324346 <<
1104 * ARM Cortex-X2 erratum 3324338 <<
1105 * ARM Cortex-X3 erratum 3324335 <<
1106 * ARM Cortex-X4 erratum 3194386 <<
1107 * ARM Cortex-X925 erratum 3324334 <<
1108 * ARM Neoverse-N1 erratum 3324349 <<
1109 * ARM Neoverse N2 erratum 3324339 <<
1110 * ARM Neoverse-N3 erratum 3456111 <<
1111 * ARM Neoverse-V1 erratum 3324341 <<
1112 * ARM Neoverse V2 erratum 3324336 <<
1113 * ARM Neoverse-V3 erratum 3312417 <<
1114 <<
1115 On affected cores "MSR SSBS, #0" in <<
1116 subsequent speculative instructions <<
1117 speculative store bypassing. <<
1118 <<
1119 Work around this problem by placing <<
1120 Instruction Synchronization Barrier <<
1121 SSBS. The presence of the SSBS spec <<
1122 from hwcaps and EL0 reads of ID_AA6 <<
1123 will use the PR_SPEC_STORE_BYPASS p <<
1124 1910
1125 If unsure, say Y. !! 1911 config SYS_HAS_CPU_MIPS64_R6
>> 1912 bool
1126 1913
1127 config CAVIUM_ERRATUM_22375 !! 1914 config SYS_HAS_CPU_R3000
1128 bool "Cavium erratum 22375, 24313" !! 1915 bool
1129 default y <<
1130 help <<
1131 Enable workaround for errata 22375 <<
1132 1916
1133 This implements two gicv3-its errat !! 1917 config SYS_HAS_CPU_TX39XX
1134 with a small impact affecting only !! 1918 bool
1135 1919
1136 erratum 22375: only alloc 8MB tab !! 1920 config SYS_HAS_CPU_VR41XX
1137 erratum 24313: ignore memory acce !! 1921 bool
1138 1922
1139 The fixes are in ITS initialization !! 1923 config SYS_HAS_CPU_R4300
1140 type and table size provided by the !! 1924 bool
1141 1925
1142 If unsure, say Y. !! 1926 config SYS_HAS_CPU_R4X00
>> 1927 bool
1143 1928
1144 config CAVIUM_ERRATUM_23144 !! 1929 config SYS_HAS_CPU_TX49XX
1145 bool "Cavium erratum 23144: ITS SYNC !! 1930 bool
1146 depends on NUMA <<
1147 default y <<
1148 help <<
1149 ITS SYNC command hang for cross nod <<
1150 1931
1151 If unsure, say Y. !! 1932 config SYS_HAS_CPU_R5000
>> 1933 bool
1152 1934
1153 config CAVIUM_ERRATUM_23154 !! 1935 config SYS_HAS_CPU_R5432
1154 bool "Cavium errata 23154 and 38545: !! 1936 bool
1155 default y <<
1156 help <<
1157 The ThunderX GICv3 implementation r <<
1158 reading the IAR status to ensure da <<
1159 (access to icc_iar1_el1 is not sync <<
1160 1937
1161 It also suffers from erratum 38545 !! 1938 config SYS_HAS_CPU_R5500
1162 OcteonTX and OcteonTX2), resulting !! 1939 bool
1163 spuriously presented to the CPU int <<
1164 1940
1165 If unsure, say Y. !! 1941 config SYS_HAS_CPU_R6000
>> 1942 bool
1166 1943
1167 config CAVIUM_ERRATUM_27456 !! 1944 config SYS_HAS_CPU_NEVADA
1168 bool "Cavium erratum 27456: Broadcast !! 1945 bool
1169 default y <<
1170 help <<
1171 On ThunderX T88 pass 1.x through 2. <<
1172 instructions may cause the icache t <<
1173 contains data for a non-current ASI <<
1174 invalidate the icache when changing <<
1175 1946
1176 If unsure, say Y. !! 1947 config SYS_HAS_CPU_R8000
>> 1948 bool
1177 1949
1178 config CAVIUM_ERRATUM_30115 !! 1950 config SYS_HAS_CPU_R10000
1179 bool "Cavium erratum 30115: Guest may !! 1951 bool
1180 default y <<
1181 help <<
1182 On ThunderX T88 pass 1.x through 2. <<
1183 1.2, and T83 Pass 1.0, KVM guest ex <<
1184 interrupts in host. Trapping both G <<
1185 accesses sidesteps the issue. <<
1186 1952
1187 If unsure, say Y. !! 1953 config SYS_HAS_CPU_RM7000
>> 1954 bool
1188 1955
1189 config CAVIUM_TX2_ERRATUM_219 !! 1956 config SYS_HAS_CPU_SB1
1190 bool "Cavium ThunderX2 erratum 219: P !! 1957 bool
1191 default y <<
1192 help <<
1193 On Cavium ThunderX2, a load, store <<
1194 TTBR update and the corresponding c <<
1195 cause a spurious Data Abort to be d <<
1196 the CPU core. <<
1197 <<
1198 Work around the issue by avoiding t <<
1199 trapping KVM guest TTBRx_EL1 writes <<
1200 trap handler performs the correspon <<
1201 instruction and ensures context syn <<
1202 exception return. <<
1203 1958
1204 If unsure, say Y. !! 1959 config SYS_HAS_CPU_CAVIUM_OCTEON
>> 1960 bool
1205 1961
1206 config FUJITSU_ERRATUM_010001 !! 1962 config SYS_HAS_CPU_BMIPS
1207 bool "Fujitsu-A64FX erratum E#010001: !! 1963 bool
1208 default y <<
1209 help <<
1210 This option adds a workaround for F <<
1211 On some variants of the Fujitsu-A64 <<
1212 accesses may cause undefined fault <<
1213 This fault occurs under a specific <<
1214 load/store instruction performs an <<
1215 case-1 TTBR0_EL1 with TCR_EL1.NFD0 <<
1216 case-2 TTBR0_EL2 with TCR_EL2.NFD0 <<
1217 case-3 TTBR1_EL1 with TCR_EL1.NFD1 <<
1218 case-4 TTBR1_EL2 with TCR_EL2.NFD1 <<
1219 1964
1220 The workaround is to ensure these b !! 1965 config SYS_HAS_CPU_BMIPS32_3300
1221 The workaround only affects the Fuj !! 1966 bool
>> 1967 select SYS_HAS_CPU_BMIPS
1222 1968
1223 If unsure, say Y. !! 1969 config SYS_HAS_CPU_BMIPS4350
>> 1970 bool
>> 1971 select SYS_HAS_CPU_BMIPS
1224 1972
1225 config HISILICON_ERRATUM_161600802 !! 1973 config SYS_HAS_CPU_BMIPS4380
1226 bool "Hip07 161600802: Erroneous redi !! 1974 bool
1227 default y !! 1975 select SYS_HAS_CPU_BMIPS
1228 help <<
1229 The HiSilicon Hip07 SoC uses the wr <<
1230 when issued ITS commands such as VM <<
1231 a 128kB offset to be applied to the <<
1232 1976
1233 If unsure, say Y. !! 1977 config SYS_HAS_CPU_BMIPS5000
>> 1978 bool
>> 1979 select SYS_HAS_CPU_BMIPS
1234 1980
1235 config QCOM_FALKOR_ERRATUM_1003 !! 1981 config SYS_HAS_CPU_XLR
1236 bool "Falkor E1003: Incorrect transla !! 1982 bool
1237 default y !! 1983
1238 help !! 1984 config SYS_HAS_CPU_XLP
1239 On Falkor v1, an incorrect ASID may !! 1985 bool
1240 and BADDR are changed together in T <<
1241 in TTBR1_EL1, this situation only o <<
1242 then only for entries in the walk c <<
1243 is unchanged. Work around the errat <<
1244 entries for the trampoline before e <<
1245 1986
1246 config QCOM_FALKOR_ERRATUM_1009 !! 1987 config MIPS_MALTA_PM
1247 bool "Falkor E1009: Prematurely compl !! 1988 depends on MIPS_MALTA
>> 1989 depends on PCI
>> 1990 bool
1248 default y 1991 default y
1249 select ARM64_WORKAROUND_REPEAT_TLBI <<
1250 help <<
1251 On Falkor v1, the CPU may premature <<
1252 TLBI xxIS invalidate maintenance op <<
1253 one more time to fix the issue. <<
1254 1992
1255 If unsure, say Y. !! 1993 #
>> 1994 # CPU may reorder R->R, R->W, W->R, W->W
>> 1995 # Reordering beyond LL and SC is handled in WEAK_REORDERING_BEYOND_LLSC
>> 1996 #
>> 1997 config WEAK_ORDERING
>> 1998 bool
1256 1999
1257 config QCOM_QDF2400_ERRATUM_0065 !! 2000 #
1258 bool "QDF2400 E0065: Incorrect GITS_T !! 2001 # CPU may reorder reads and writes beyond LL/SC
1259 default y !! 2002 # CPU may reorder R->LL, R->LL, W->LL, W->LL, R->SC, R->SC, W->SC, W->SC
1260 help !! 2003 #
1261 On Qualcomm Datacenter Technologies !! 2004 config WEAK_REORDERING_BEYOND_LLSC
1262 ITE size incorrectly. The GITS_TYPE !! 2005 bool
1263 been indicated as 16Bytes (0xf), no !! 2006 endmenu
1264 2007
1265 If unsure, say Y. !! 2008 #
>> 2009 # These two indicate any level of the MIPS32 and MIPS64 architecture
>> 2010 #
>> 2011 config CPU_MIPS32
>> 2012 bool
>> 2013 default y if CPU_MIPS32_R1 || CPU_MIPS32_R2 || CPU_MIPS32_R6
1266 2014
1267 config QCOM_FALKOR_ERRATUM_E1041 !! 2015 config CPU_MIPS64
1268 bool "Falkor E1041: Speculative instr !! 2016 bool
1269 default y !! 2017 default y if CPU_MIPS64_R1 || CPU_MIPS64_R2 || CPU_MIPS64_R6
1270 help <<
1271 Falkor CPU may speculatively fetch <<
1272 memory location when MMU translatio <<
1273 to SCTLR_ELn[M]=0. Prefix an ISB in <<
1274 2018
1275 If unsure, say Y. !! 2019 #
>> 2020 # These two indicate the revision of the architecture, either Release 1 or Release 2
>> 2021 #
>> 2022 config CPU_MIPSR1
>> 2023 bool
>> 2024 default y if CPU_MIPS32_R1 || CPU_MIPS64_R1
1276 2025
1277 config NVIDIA_CARMEL_CNP_ERRATUM !! 2026 config CPU_MIPSR2
1278 bool "NVIDIA Carmel CNP: CNP on Carme !! 2027 bool
1279 default y !! 2028 default y if CPU_MIPS32_R2 || CPU_MIPS64_R2 || CPU_CAVIUM_OCTEON
1280 help !! 2029 select CPU_HAS_RIXI
1281 If CNP is enabled on Carmel cores, !! 2030 select MIPS_SPRAM
1282 invalidate shared TLB entries insta <<
1283 on standard ARM cores. <<
1284 2031
1285 If unsure, say Y. !! 2032 config CPU_MIPSR6
>> 2033 bool
>> 2034 default y if CPU_MIPS32_R6 || CPU_MIPS64_R6
>> 2035 select CPU_HAS_RIXI
>> 2036 select HAVE_ARCH_BITREVERSE
>> 2037 select MIPS_ASID_BITS_VARIABLE
>> 2038 select MIPS_SPRAM
1286 2039
1287 config ROCKCHIP_ERRATUM_3588001 !! 2040 config EVA
1288 bool "Rockchip 3588001: GIC600 can no !! 2041 bool
1289 default y <<
1290 help <<
1291 The Rockchip RK3588 GIC600 SoC inte <<
1292 This means, that its sharability fe <<
1293 is supported by the IP itself. <<
1294 2042
1295 If unsure, say Y. !! 2043 config XPA
>> 2044 bool
1296 2045
1297 config SOCIONEXT_SYNQUACER_PREITS !! 2046 config SYS_SUPPORTS_32BIT_KERNEL
1298 bool "Socionext Synquacer: Workaround !! 2047 bool
1299 default y !! 2048 config SYS_SUPPORTS_64BIT_KERNEL
1300 help !! 2049 bool
1301 Socionext Synquacer SoCs implement !! 2050 config CPU_SUPPORTS_32BIT_KERNEL
1302 MSI doorbell writes with non-zero v !! 2051 bool
>> 2052 config CPU_SUPPORTS_64BIT_KERNEL
>> 2053 bool
>> 2054 config CPU_SUPPORTS_CPUFREQ
>> 2055 bool
>> 2056 config CPU_SUPPORTS_ADDRWINCFG
>> 2057 bool
>> 2058 config CPU_SUPPORTS_HUGEPAGES
>> 2059 bool
>> 2060 config CPU_SUPPORTS_UNCACHED_ACCELERATED
>> 2061 bool
>> 2062 config MIPS_PGD_C0_CONTEXT
>> 2063 bool
>> 2064 default y if 64BIT && CPU_MIPSR2 && !CPU_XLP
1303 2065
1304 If unsure, say Y. !! 2066 #
>> 2067 # Set to y for ptrace access to watch registers.
>> 2068 #
>> 2069 config HARDWARE_WATCHPOINTS
>> 2070 bool
>> 2071 default y if CPU_MIPSR1 || CPU_MIPSR2 || CPU_MIPSR6
1305 2072
1306 endmenu # "ARM errata workarounds via the alt !! 2073 menu "Kernel type"
1307 2074
1308 choice 2075 choice
1309 prompt "Page size" !! 2076 prompt "Kernel code model"
1310 default ARM64_4K_PAGES <<
1311 help <<
1312 Page size (translation granule) con <<
1313 <<
1314 config ARM64_4K_PAGES <<
1315 bool "4KB" <<
1316 select HAVE_PAGE_SIZE_4KB <<
1317 help 2077 help
1318 This feature enables 4KB pages supp !! 2078 You should only select this option if you have a workload that
1319 !! 2079 actually benefits from 64-bit processing or if your machine has
1320 config ARM64_16K_PAGES !! 2080 large memory. You will only be presented a single option in this
1321 bool "16KB" !! 2081 menu if your system does not support both 32-bit and 64-bit kernels.
1322 select HAVE_PAGE_SIZE_16KB !! 2082
>> 2083 config 32BIT
>> 2084 bool "32-bit kernel"
>> 2085 depends on CPU_SUPPORTS_32BIT_KERNEL && SYS_SUPPORTS_32BIT_KERNEL
>> 2086 select TRAD_SIGNALS
1323 help 2087 help
1324 The system will use 16KB pages supp !! 2088 Select this option if you want to build a 32-bit kernel.
1325 requires applications compiled with <<
1326 aligned segments. <<
1327 2089
1328 config ARM64_64K_PAGES !! 2090 config 64BIT
1329 bool "64KB" !! 2091 bool "64-bit kernel"
1330 select HAVE_PAGE_SIZE_64KB !! 2092 depends on CPU_SUPPORTS_64BIT_KERNEL && SYS_SUPPORTS_64BIT_KERNEL
1331 help 2093 help
1332 This feature enables 64KB pages sup !! 2094 Select this option if you want to build a 64-bit kernel.
1333 allowing only two levels of page ta <<
1334 look-up. AArch32 emulation requires <<
1335 with 64K aligned segments. <<
1336 2095
1337 endchoice 2096 endchoice
1338 2097
>> 2098 config KVM_GUEST
>> 2099 bool "KVM Guest Kernel"
>> 2100 depends on BROKEN_ON_SMP
>> 2101 help
>> 2102 Select this option if building a guest kernel for KVM (Trap & Emulate)
>> 2103 mode.
>> 2104
>> 2105 config KVM_GUEST_TIMER_FREQ
>> 2106 int "Count/Compare Timer Frequency (MHz)"
>> 2107 depends on KVM_GUEST
>> 2108 default 100
>> 2109 help
>> 2110 Set this to non-zero if building a guest kernel for KVM to skip RTC
>> 2111 emulation when determining guest CPU Frequency. Instead, the guest's
>> 2112 timer frequency is specified directly.
>> 2113
>> 2114 config MIPS_VA_BITS_48
>> 2115 bool "48 bits virtual memory"
>> 2116 depends on 64BIT
>> 2117 help
>> 2118 Support a maximum at least 48 bits of application virtual
>> 2119 memory. Default is 40 bits or less, depending on the CPU.
>> 2120 For page sizes 16k and above, this option results in a small
>> 2121 memory overhead for page tables. For 4k page size, a fourth
>> 2122 level of page tables is added which imposes both a memory
>> 2123 overhead as well as slower TLB fault handling.
>> 2124
>> 2125 If unsure, say N.
>> 2126
1339 choice 2127 choice
1340 prompt "Virtual address space size" !! 2128 prompt "Kernel page size"
1341 default ARM64_VA_BITS_52 !! 2129 default PAGE_SIZE_4KB
1342 help <<
1343 Allows choosing one of multiple pos <<
1344 space sizes. The level of translati <<
1345 a combination of page size and virt <<
1346 <<
1347 config ARM64_VA_BITS_36 <<
1348 bool "36-bit" if EXPERT <<
1349 depends on PAGE_SIZE_16KB <<
1350 <<
1351 config ARM64_VA_BITS_39 <<
1352 bool "39-bit" <<
1353 depends on PAGE_SIZE_4KB <<
1354 <<
1355 config ARM64_VA_BITS_42 <<
1356 bool "42-bit" <<
1357 depends on PAGE_SIZE_64KB <<
1358 <<
1359 config ARM64_VA_BITS_47 <<
1360 bool "47-bit" <<
1361 depends on PAGE_SIZE_16KB <<
1362 <<
1363 config ARM64_VA_BITS_48 <<
1364 bool "48-bit" <<
1365 <<
1366 config ARM64_VA_BITS_52 <<
1367 bool "52-bit" <<
1368 depends on ARM64_PAN || !ARM64_SW_TTB <<
1369 help <<
1370 Enable 52-bit virtual addressing fo <<
1371 requested via a hint to mmap(). The <<
1372 virtual addresses for its own mappi <<
1373 this feature is available, otherwis <<
1374 <<
1375 NOTE: Enabling 52-bit virtual addre <<
1376 ARMv8.3 Pointer Authentication will <<
1377 reduced from 7 bits to 3 bits, whic <<
1378 impact on its susceptibility to bru <<
1379 2130
1380 If unsure, select 48-bit virtual ad !! 2131 config PAGE_SIZE_4KB
>> 2132 bool "4kB"
>> 2133 depends on !CPU_LOONGSON2 && !CPU_LOONGSON3
>> 2134 help
>> 2135 This option select the standard 4kB Linux page size. On some
>> 2136 R3000-family processors this is the only available page size. Using
>> 2137 4kB page size will minimize memory consumption and is therefore
>> 2138 recommended for low memory systems.
>> 2139
>> 2140 config PAGE_SIZE_8KB
>> 2141 bool "8kB"
>> 2142 depends on CPU_R8000 || CPU_CAVIUM_OCTEON
>> 2143 depends on !MIPS_VA_BITS_48
>> 2144 help
>> 2145 Using 8kB page size will result in higher performance kernel at
>> 2146 the price of higher memory consumption. This option is available
>> 2147 only on R8000 and cnMIPS processors. Note that you will need a
>> 2148 suitable Linux distribution to support this.
>> 2149
>> 2150 config PAGE_SIZE_16KB
>> 2151 bool "16kB"
>> 2152 depends on !CPU_R3000 && !CPU_TX39XX
>> 2153 help
>> 2154 Using 16kB page size will result in higher performance kernel at
>> 2155 the price of higher memory consumption. This option is available on
>> 2156 all non-R3000 family processors. Note that you will need a suitable
>> 2157 Linux distribution to support this.
>> 2158
>> 2159 config PAGE_SIZE_32KB
>> 2160 bool "32kB"
>> 2161 depends on CPU_CAVIUM_OCTEON
>> 2162 depends on !MIPS_VA_BITS_48
>> 2163 help
>> 2164 Using 32kB page size will result in higher performance kernel at
>> 2165 the price of higher memory consumption. This option is available
>> 2166 only on cnMIPS cores. Note that you will need a suitable Linux
>> 2167 distribution to support this.
>> 2168
>> 2169 config PAGE_SIZE_64KB
>> 2170 bool "64kB"
>> 2171 depends on !CPU_R3000 && !CPU_TX39XX && !CPU_R6000
>> 2172 help
>> 2173 Using 64kB page size will result in higher performance kernel at
>> 2174 the price of higher memory consumption. This option is available on
>> 2175 all non-R3000 family processor. Not that at the time of this
>> 2176 writing this option is still high experimental.
1381 2177
1382 endchoice 2178 endchoice
1383 2179
1384 config ARM64_FORCE_52BIT !! 2180 config FORCE_MAX_ZONEORDER
1385 bool "Force 52-bit virtual addresses !! 2181 int "Maximum zone order"
1386 depends on ARM64_VA_BITS_52 && EXPERT !! 2182 range 14 64 if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_64KB
1387 help !! 2183 default "14" if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_64KB
1388 For systems with 52-bit userspace V !! 2184 range 13 64 if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_32KB
1389 to maintain compatibility with olde !! 2185 default "13" if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_32KB
1390 unless a hint is supplied to mmap. !! 2186 range 12 64 if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_16KB
1391 !! 2187 default "12" if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_16KB
1392 This configuration option disables !! 2188 range 11 64
1393 forces all userspace addresses to b !! 2189 default "11"
1394 should only enable this configurati !! 2190 help
1395 memory management code. If unsure s !! 2191 The kernel memory allocator divides physically contiguous memory
>> 2192 blocks into "zones", where each zone is a power of two number of
>> 2193 pages. This option selects the largest power of two that the kernel
>> 2194 keeps in the memory allocator. If you need to allocate very large
>> 2195 blocks of physically contiguous memory, then you may need to
>> 2196 increase this value.
1396 2197
1397 config ARM64_VA_BITS !! 2198 This config option is actually maximum order plus one. For example,
1398 int !! 2199 a value of 11 means that the largest free memory block is 2^10 pages.
1399 default 36 if ARM64_VA_BITS_36 <<
1400 default 39 if ARM64_VA_BITS_39 <<
1401 default 42 if ARM64_VA_BITS_42 <<
1402 default 47 if ARM64_VA_BITS_47 <<
1403 default 48 if ARM64_VA_BITS_48 <<
1404 default 52 if ARM64_VA_BITS_52 <<
1405 2200
1406 choice !! 2201 The page size is not necessarily 4KB. Keep this in mind
1407 prompt "Physical address space size" !! 2202 when choosing a value for this option.
1408 default ARM64_PA_BITS_48 <<
1409 help <<
1410 Choose the maximum physical address <<
1411 support. <<
1412 2203
1413 config ARM64_PA_BITS_48 !! 2204 config BOARD_SCACHE
1414 bool "48-bit" !! 2205 bool
1415 depends on ARM64_64K_PAGES || !ARM64_ <<
1416 <<
1417 config ARM64_PA_BITS_52 <<
1418 bool "52-bit" <<
1419 depends on ARM64_64K_PAGES || ARM64_V <<
1420 depends on ARM64_PAN || !ARM64_SW_TTB <<
1421 help <<
1422 Enable support for a 52-bit physica <<
1423 part of the ARMv8.2-LPA extension. <<
1424 <<
1425 With this enabled, the kernel will <<
1426 do not support ARMv8.2-LPA, but wit <<
1427 minor performance overhead). <<
1428 2206
1429 endchoice !! 2207 config IP22_CPU_SCACHE
>> 2208 bool
>> 2209 select BOARD_SCACHE
1430 2210
1431 config ARM64_PA_BITS !! 2211 #
1432 int !! 2212 # Support for a MIPS32 / MIPS64 style S-caches
1433 default 48 if ARM64_PA_BITS_48 !! 2213 #
1434 default 52 if ARM64_PA_BITS_52 !! 2214 config MIPS_CPU_SCACHE
>> 2215 bool
>> 2216 select BOARD_SCACHE
1435 2217
1436 config ARM64_LPA2 !! 2218 config R5000_CPU_SCACHE
1437 def_bool y !! 2219 bool
1438 depends on ARM64_PA_BITS_52 && !ARM64 !! 2220 select BOARD_SCACHE
1439 2221
1440 choice !! 2222 config RM7000_CPU_SCACHE
1441 prompt "Endianness" !! 2223 bool
1442 default CPU_LITTLE_ENDIAN !! 2224 select BOARD_SCACHE
1443 help <<
1444 Select the endianness of data acces <<
1445 applications will need to be compil <<
1446 that is selected here. <<
1447 2225
1448 config CPU_BIG_ENDIAN !! 2226 config SIBYTE_DMA_PAGEOPS
1449 bool "Build big-endian kernel" !! 2227 bool "Use DMA to clear/copy pages"
1450 # https://github.com/llvm/llvm-projec !! 2228 depends on CPU_SB1
1451 depends on AS_IS_GNU || AS_VERSION >= <<
1452 help 2229 help
1453 Say Y if you plan on running a kern !! 2230 Instead of using the CPU to zero and copy pages, use a Data Mover
>> 2231 channel. These DMA channels are otherwise unused by the standard
>> 2232 SiByte Linux port. Seems to give a small performance benefit.
1454 2233
1455 config CPU_LITTLE_ENDIAN !! 2234 config CPU_HAS_PREFETCH
1456 bool "Build little-endian kernel" !! 2235 bool
1457 help <<
1458 Say Y if you plan on running a kern <<
1459 This is usually the case for distri <<
1460 2236
1461 endchoice !! 2237 config CPU_GENERIC_DUMP_TLB
>> 2238 bool
>> 2239 default y if !(CPU_R3000 || CPU_R6000 || CPU_R8000 || CPU_TX39XX)
1462 2240
1463 config SCHED_MC !! 2241 config CPU_R4K_FPU
1464 bool "Multi-core scheduler support" !! 2242 bool
1465 help !! 2243 default y if !(CPU_R3000 || CPU_R6000 || CPU_TX39XX || CPU_CAVIUM_OCTEON)
1466 Multi-core scheduler support improv <<
1467 making when dealing with multi-core <<
1468 increased overhead in some places. <<
1469 2244
1470 config SCHED_CLUSTER !! 2245 config CPU_R4K_CACHE_TLB
1471 bool "Cluster scheduler support" !! 2246 bool
1472 help !! 2247 default y if !(CPU_R3000 || CPU_R8000 || CPU_SB1 || CPU_TX39XX || CPU_CAVIUM_OCTEON)
1473 Cluster scheduler support improves !! 2248
1474 making when dealing with machines t !! 2249 config MIPS_MT_SMP
1475 Cluster usually means a couple of C !! 2250 bool "MIPS MT SMP support (1 TC on each available VPE)"
1476 by sharing mid-level caches, last-l !! 2251 depends on SYS_SUPPORTS_MULTITHREADING && !CPU_MIPSR6
1477 busses. !! 2252 select CPU_MIPSR2_IRQ_VI
>> 2253 select CPU_MIPSR2_IRQ_EI
>> 2254 select SYNC_R4K
>> 2255 select MIPS_MT
>> 2256 select SMP
>> 2257 select SMP_UP
>> 2258 select SYS_SUPPORTS_SMP
>> 2259 select SYS_SUPPORTS_SCHED_SMT
>> 2260 select MIPS_PERF_SHARED_TC_COUNTERS
>> 2261 help
>> 2262 This is a kernel model which is known as SMVP. This is supported
>> 2263 on cores with the MT ASE and uses the available VPEs to implement
>> 2264 virtual processors which supports SMP. This is equivalent to the
>> 2265 Intel Hyperthreading feature. For further information go to
>> 2266 <http://www.imgtec.com/mips/mips-multithreading.asp>.
>> 2267
>> 2268 config MIPS_MT
>> 2269 bool
1478 2270
1479 config SCHED_SMT 2271 config SCHED_SMT
1480 bool "SMT scheduler support" !! 2272 bool "SMT (multithreading) scheduler support"
>> 2273 depends on SYS_SUPPORTS_SCHED_SMT
>> 2274 default n
1481 help 2275 help
1482 Improves the CPU scheduler's decisi !! 2276 SMT scheduler support improves the CPU scheduler's decision making
1483 MultiThreading at a cost of slightl !! 2277 when dealing with MIPS MT enabled cores at a cost of slightly
1484 places. If unsure say N here. !! 2278 increased overhead in some places. If unsure say N here.
1485 2279
1486 config NR_CPUS !! 2280 config SYS_SUPPORTS_SCHED_SMT
1487 int "Maximum number of CPUs (2-4096)" !! 2281 bool
1488 range 2 4096 <<
1489 default "512" <<
1490 2282
1491 config HOTPLUG_CPU !! 2283 config SYS_SUPPORTS_MULTITHREADING
1492 bool "Support for hot-pluggable CPUs" !! 2284 bool
1493 select GENERIC_IRQ_MIGRATION <<
1494 help <<
1495 Say Y here to experiment with turni <<
1496 can be controlled through /sys/devi <<
1497 2285
1498 # Common NUMA Features !! 2286 config MIPS_MT_FPAFF
1499 config NUMA !! 2287 bool "Dynamic FPU affinity for FP-intensive threads"
1500 bool "NUMA Memory Allocation and Sche !! 2288 default y
1501 select GENERIC_ARCH_NUMA !! 2289 depends on MIPS_MT_SMP
1502 select OF_NUMA <<
1503 select HAVE_SETUP_PER_CPU_AREA <<
1504 select NEED_PER_CPU_EMBED_FIRST_CHUNK <<
1505 select NEED_PER_CPU_PAGE_FIRST_CHUNK <<
1506 select USE_PERCPU_NUMA_NODE_ID <<
1507 help <<
1508 Enable NUMA (Non-Uniform Memory Acc <<
1509 <<
1510 The kernel will try to allocate mem <<
1511 local memory of the CPU and add som <<
1512 NUMA awareness to the kernel. <<
1513 2290
1514 config NODES_SHIFT !! 2291 config MIPSR2_TO_R6_EMULATOR
1515 int "Maximum NUMA Nodes (as a power o !! 2292 bool "MIPS R2-to-R6 emulator"
1516 range 1 10 !! 2293 depends on CPU_MIPSR6
1517 default "4" !! 2294 default y
1518 depends on NUMA <<
1519 help 2295 help
1520 Specify the maximum number of NUMA !! 2296 Choose this option if you want to run non-R6 MIPS userland code.
1521 system. Increases memory reserved !! 2297 Even if you say 'Y' here, the emulator will still be disabled by
1522 !! 2298 default. You can enable it using the 'mipsr2emu' kernel option.
1523 source "kernel/Kconfig.hz" !! 2299 The only reason this is a build-time option is to save ~14K from the
>> 2300 final kernel image.
1524 2301
1525 config ARCH_SPARSEMEM_ENABLE !! 2302 config MIPS_VPE_LOADER
1526 def_bool y !! 2303 bool "VPE loader support."
1527 select SPARSEMEM_VMEMMAP_ENABLE !! 2304 depends on SYS_SUPPORTS_MULTITHREADING && MODULES
1528 select SPARSEMEM_VMEMMAP !! 2305 select CPU_MIPSR2_IRQ_VI
>> 2306 select CPU_MIPSR2_IRQ_EI
>> 2307 select MIPS_MT
>> 2308 help
>> 2309 Includes a loader for loading an elf relocatable object
>> 2310 onto another VPE and running it.
1529 2311
1530 config HW_PERF_EVENTS !! 2312 config MIPS_VPE_LOADER_CMP
1531 def_bool y !! 2313 bool
1532 depends on ARM_PMU !! 2314 default "y"
>> 2315 depends on MIPS_VPE_LOADER && MIPS_CMP
1533 2316
1534 # Supported by clang >= 7.0 or GCC >= 12.0.0 !! 2317 config MIPS_VPE_LOADER_MT
1535 config CC_HAVE_SHADOW_CALL_STACK !! 2318 bool
1536 def_bool $(cc-option, -fsanitize=shad !! 2319 default "y"
>> 2320 depends on MIPS_VPE_LOADER && !MIPS_CMP
1537 2321
1538 config PARAVIRT !! 2322 config MIPS_VPE_LOADER_TOM
1539 bool "Enable paravirtualization code" !! 2323 bool "Load VPE program into memory hidden from linux"
>> 2324 depends on MIPS_VPE_LOADER
>> 2325 default y
1540 help 2326 help
1541 This changes the kernel so it can m !! 2327 The loader can use memory that is present but has been hidden from
1542 under a hypervisor, potentially imp !! 2328 Linux using the kernel command line option "mem=xxMB". It's up to
1543 over full virtualization. !! 2329 you to ensure the amount you put in the option and the space your
>> 2330 program requires is less or equal to the amount physically present.
1544 2331
1545 config PARAVIRT_TIME_ACCOUNTING !! 2332 config MIPS_VPE_APSP_API
1546 bool "Paravirtual steal time accounti !! 2333 bool "Enable support for AP/SP API (RTLX)"
1547 select PARAVIRT !! 2334 depends on MIPS_VPE_LOADER
1548 help 2335 help
1549 Select this option to enable fine g <<
1550 accounting. Time spent executing ot <<
1551 the current vCPU is discounted from <<
1552 that, there can be a small performa <<
1553 <<
1554 If in doubt, say N here. <<
1555 2336
1556 config ARCH_SUPPORTS_KEXEC !! 2337 config MIPS_VPE_APSP_API_CMP
1557 def_bool PM_SLEEP_SMP !! 2338 bool
>> 2339 default "y"
>> 2340 depends on MIPS_VPE_APSP_API && MIPS_CMP
1558 2341
1559 config ARCH_SUPPORTS_KEXEC_FILE !! 2342 config MIPS_VPE_APSP_API_MT
1560 def_bool y !! 2343 bool
>> 2344 default "y"
>> 2345 depends on MIPS_VPE_APSP_API && !MIPS_CMP
1561 2346
1562 config ARCH_SELECTS_KEXEC_FILE !! 2347 config MIPS_CMP
1563 def_bool y !! 2348 bool "MIPS CMP framework support (DEPRECATED)"
1564 depends on KEXEC_FILE !! 2349 depends on SYS_SUPPORTS_MIPS_CMP && !CPU_MIPSR6
1565 select HAVE_IMA_KEXEC if IMA !! 2350 select SMP
>> 2351 select SYNC_R4K
>> 2352 select SYS_SUPPORTS_SMP
>> 2353 select WEAK_ORDERING
>> 2354 default n
>> 2355 help
>> 2356 Select this if you are using a bootloader which implements the "CMP
>> 2357 framework" protocol (ie. YAMON) and want your kernel to make use of
>> 2358 its ability to start secondary CPUs.
>> 2359
>> 2360 Unless you have a specific need, you should use CONFIG_MIPS_CPS
>> 2361 instead of this.
>> 2362
>> 2363 config MIPS_CPS
>> 2364 bool "MIPS Coherent Processing System support"
>> 2365 depends on SYS_SUPPORTS_MIPS_CPS
>> 2366 select MIPS_CM
>> 2367 select MIPS_CPC
>> 2368 select MIPS_CPS_PM if HOTPLUG_CPU
>> 2369 select SMP
>> 2370 select SYNC_R4K if (CEVT_R4K || CSRC_R4K)
>> 2371 select SYS_SUPPORTS_HOTPLUG_CPU
>> 2372 select SYS_SUPPORTS_SMP
>> 2373 select WEAK_ORDERING
>> 2374 help
>> 2375 Select this if you wish to run an SMP kernel across multiple cores
>> 2376 within a MIPS Coherent Processing System. When this option is
>> 2377 enabled the kernel will probe for other cores and boot them with
>> 2378 no external assistance. It is safe to enable this when hardware
>> 2379 support is unavailable.
>> 2380
>> 2381 config MIPS_CPS_PM
>> 2382 depends on MIPS_CPS
>> 2383 select MIPS_CPC
>> 2384 bool
1566 2385
1567 config ARCH_SUPPORTS_KEXEC_SIG !! 2386 config MIPS_CM
1568 def_bool y !! 2387 bool
1569 2388
1570 config ARCH_SUPPORTS_KEXEC_IMAGE_VERIFY_SIG !! 2389 config MIPS_CPC
1571 def_bool y !! 2390 bool
1572 2391
1573 config ARCH_DEFAULT_KEXEC_IMAGE_VERIFY_SIG !! 2392 config SB1_PASS_2_WORKAROUNDS
1574 def_bool y !! 2393 bool
>> 2394 depends on CPU_SB1 && (CPU_SB1_PASS_2_2 || CPU_SB1_PASS_2)
>> 2395 default y
1575 2396
1576 config ARCH_SUPPORTS_CRASH_DUMP !! 2397 config SB1_PASS_2_1_WORKAROUNDS
1577 def_bool y !! 2398 bool
>> 2399 depends on CPU_SB1 && CPU_SB1_PASS_2
>> 2400 default y
1578 2401
1579 config ARCH_HAS_GENERIC_CRASHKERNEL_RESERVATI <<
1580 def_bool CRASH_RESERVE <<
1581 2402
1582 config TRANS_TABLE !! 2403 config ARCH_PHYS_ADDR_T_64BIT
1583 def_bool y !! 2404 bool
1584 depends on HIBERNATION || KEXEC_CORE <<
1585 2405
1586 config XEN_DOM0 !! 2406 choice
1587 def_bool y !! 2407 prompt "SmartMIPS or microMIPS ASE support"
1588 depends on XEN <<
1589 2408
1590 config XEN !! 2409 config CPU_NEEDS_NO_SMARTMIPS_OR_MICROMIPS
1591 bool "Xen guest support on ARM64" !! 2410 bool "None"
1592 depends on ARM64 && OF <<
1593 select SWIOTLB_XEN <<
1594 select PARAVIRT <<
1595 help 2411 help
1596 Say Y if you want to run Linux in a !! 2412 Select this if you want neither microMIPS nor SmartMIPS support
1597 2413
1598 # include/linux/mmzone.h requires the followi !! 2414 config CPU_HAS_SMARTMIPS
1599 # !! 2415 depends on SYS_SUPPORTS_SMARTMIPS
1600 # MAX_PAGE_ORDER + PAGE_SHIFT <= SECTION_SI !! 2416 bool "SmartMIPS"
1601 # !! 2417 help
1602 # so the maximum value of MAX_PAGE_ORDER is S !! 2418 SmartMIPS is a extension of the MIPS32 architecture aimed at
1603 # !! 2419 increased security at both hardware and software level for
1604 # | SECTION_SIZE_BITS | PAGE_SHIFT | m !! 2420 smartcards. Enabling this option will allow proper use of the
1605 # ----+-------------------+--------------+--- !! 2421 SmartMIPS instructions by Linux applications. However a kernel with
1606 # 4K | 27 | 12 | !! 2422 this option will not work on a MIPS core without SmartMIPS core. If
1607 # 16K | 27 | 14 | !! 2423 you don't know you probably don't have SmartMIPS and should say N
1608 # 64K | 29 | 16 | !! 2424 here.
1609 config ARCH_FORCE_MAX_ORDER !! 2425
1610 int !! 2426 config CPU_MICROMIPS
1611 default "13" if ARM64_64K_PAGES !! 2427 depends on 32BIT && SYS_SUPPORTS_MICROMIPS && !CPU_MIPSR6
1612 default "11" if ARM64_16K_PAGES !! 2428 bool "microMIPS"
1613 default "10" <<
1614 help 2429 help
1615 The kernel page allocator limits th !! 2430 When this option is enabled the kernel will be built using the
1616 contiguous allocations. The limit i !! 2431 microMIPS ISA
1617 defines the maximal power of two of <<
1618 allocated as a single contiguous bl <<
1619 overriding the default setting when <<
1620 large blocks of physically contiguo <<
1621 <<
1622 The maximal size of allocation cann <<
1623 section, so the value of MAX_PAGE_O <<
1624 <<
1625 MAX_PAGE_ORDER + PAGE_SHIFT <= SE <<
1626 2432
1627 Don't change if unsure. !! 2433 endchoice
1628 2434
1629 config UNMAP_KERNEL_AT_EL0 !! 2435 config CPU_HAS_MSA
1630 bool "Unmap kernel when running in us !! 2436 bool "Support for the MIPS SIMD Architecture"
1631 default y !! 2437 depends on CPU_SUPPORTS_MSA
1632 help !! 2438 depends on 64BIT || MIPS_O32_FP64_SUPPORT
1633 Speculation attacks against some hi !! 2439 help
1634 be used to bypass MMU permission ch !! 2440 MIPS SIMD Architecture (MSA) introduces 128 bit wide vector registers
1635 userspace. This can be defended aga !! 2441 and a set of SIMD instructions to operate on them. When this option
1636 when running in userspace, mapping !! 2442 is enabled the kernel will support allocating & switching MSA
1637 via a trampoline page in the vector !! 2443 vector register contexts. If you know that your kernel will only be
>> 2444 running on CPUs which do not support MSA or that your userland will
>> 2445 not be making use of it then you may wish to say N here to reduce
>> 2446 the size & complexity of your kernel.
1638 2447
1639 If unsure, say Y. 2448 If unsure, say Y.
1640 2449
1641 config MITIGATE_SPECTRE_BRANCH_HISTORY !! 2450 config CPU_HAS_WB
1642 bool "Mitigate Spectre style attacks !! 2451 bool
1643 default y <<
1644 help <<
1645 Speculation attacks against some hi <<
1646 make use of branch history to influ <<
1647 When taking an exception from user- <<
1648 or a firmware call overwrites the b <<
1649 2452
1650 config RODATA_FULL_DEFAULT_ENABLED !! 2453 config XKS01
1651 bool "Apply r/o permissions of VM are !! 2454 bool
1652 default y <<
1653 help <<
1654 Apply read-only attributes of VM ar <<
1655 the backing pages as well. This pre <<
1656 from being modified (inadvertently <<
1657 mapping of the same memory page. Th <<
1658 be turned off at runtime by passing <<
1659 with rodata=full if this option is <<
1660 2455
1661 This requires the linear region to !! 2456 config CPU_HAS_RIXI
1662 which may adversely affect performa !! 2457 bool
1663 2458
1664 config ARM64_SW_TTBR0_PAN !! 2459 #
1665 bool "Emulate Privileged Access Never !! 2460 # Vectored interrupt mode is an R2 feature
1666 depends on !KCSAN !! 2461 #
1667 help !! 2462 config CPU_MIPSR2_IRQ_VI
1668 Enabling this option prevents the k !! 2463 bool
1669 user-space memory directly by point <<
1670 zeroed area and reserved ASID. The <<
1671 restore the valid TTBR0_EL1 tempora <<
1672 2464
1673 config ARM64_TAGGED_ADDR_ABI !! 2465 #
1674 bool "Enable the tagged user addresse !! 2466 # Extended interrupt mode is an R2 feature
1675 default y !! 2467 #
1676 help !! 2468 config CPU_MIPSR2_IRQ_EI
1677 When this option is enabled, user a !! 2469 bool
1678 relaxed ABI via prctl() allowing ta <<
1679 to system calls as pointer argument <<
1680 Documentation/arch/arm64/tagged-add <<
1681 2470
1682 menuconfig COMPAT !! 2471 config CPU_HAS_SYNC
1683 bool "Kernel support for 32-bit EL0" !! 2472 bool
1684 depends on ARM64_4K_PAGES || EXPERT !! 2473 depends on !CPU_R3000
1685 select HAVE_UID16 !! 2474 default y
1686 select OLD_SIGSUSPEND3 <<
1687 select COMPAT_OLD_SIGACTION <<
1688 help <<
1689 This option enables support for a 3 <<
1690 kernel at EL1. AArch32-specific com <<
1691 the user helper functions, VFP supp <<
1692 handled appropriately by the kernel <<
1693 2475
1694 If you use a page size other than 4 !! 2476 #
1695 that you will only be able to execu !! 2477 # CPU non-features
1696 with page size aligned segments. !! 2478 #
>> 2479 config CPU_DADDI_WORKAROUNDS
>> 2480 bool
1697 2481
1698 If you want to execute 32-bit users !! 2482 config CPU_R4000_WORKAROUNDS
>> 2483 bool
>> 2484 select CPU_R4400_WORKAROUNDS
1699 2485
1700 if COMPAT !! 2486 config CPU_R4400_WORKAROUNDS
>> 2487 bool
1701 2488
1702 config KUSER_HELPERS !! 2489 config MIPS_ASID_SHIFT
1703 bool "Enable kuser helpers page for 3 !! 2490 int
1704 default y !! 2491 default 6 if CPU_R3000 || CPU_TX39XX
1705 help !! 2492 default 4 if CPU_R8000
1706 Warning: disabling this option may !! 2493 default 0
1707 2494
1708 Provide kuser helpers to compat tas !! 2495 config MIPS_ASID_BITS
1709 helper code to userspace in read on !! 2496 int
1710 to allow userspace to be independen !! 2497 default 0 if MIPS_ASID_BITS_VARIABLE
1711 the system. This permits binaries t !! 2498 default 6 if CPU_R3000 || CPU_TX39XX
1712 to ARMv8 without modification. !! 2499 default 8
1713 2500
1714 See Documentation/arch/arm/kernel_u !! 2501 config MIPS_ASID_BITS_VARIABLE
>> 2502 bool
1715 2503
1716 However, the fixed address nature o !! 2504 #
1717 by ROP (return orientated programmi !! 2505 # - Highmem only makes sense for the 32-bit kernel.
1718 exploits. !! 2506 # - The current highmem code will only work properly on physically indexed
>> 2507 # caches such as R3000, SB1, R7000 or those that look like they're virtually
>> 2508 # indexed such as R4000/R4400 SC and MC versions or R10000. So for the
>> 2509 # moment we protect the user and offer the highmem option only on machines
>> 2510 # where it's known to be safe. This will not offer highmem on a few systems
>> 2511 # such as MIPS32 and MIPS64 CPUs which may have virtual and physically
>> 2512 # indexed CPUs but we're playing safe.
>> 2513 # - We use SYS_SUPPORTS_HIGHMEM to offer highmem only for systems where we
>> 2514 # know they might have memory configurations that could make use of highmem
>> 2515 # support.
>> 2516 #
>> 2517 config HIGHMEM
>> 2518 bool "High Memory Support"
>> 2519 depends on 32BIT && CPU_SUPPORTS_HIGHMEM && SYS_SUPPORTS_HIGHMEM && !CPU_MIPS32_3_5_EVA
1719 2520
1720 If all of the binaries and librarie !! 2521 config CPU_SUPPORTS_HIGHMEM
1721 are built specifically for your pla !! 2522 bool
1722 these helpers, then you can turn th <<
1723 such exploits. However, in that cas <<
1724 relying on those helpers is run, it <<
1725 2523
1726 Say N here only if you are absolute !! 2524 config SYS_SUPPORTS_HIGHMEM
1727 need these helpers; otherwise, the !! 2525 bool
1728 2526
1729 config COMPAT_VDSO !! 2527 config SYS_SUPPORTS_SMARTMIPS
1730 bool "Enable vDSO for 32-bit applicat !! 2528 bool
1731 depends on !CPU_BIG_ENDIAN <<
1732 depends on (CC_IS_CLANG && LD_IS_LLD) <<
1733 select GENERIC_COMPAT_VDSO <<
1734 default y <<
1735 help <<
1736 Place in the process address space <<
1737 ELF shared object providing fast im <<
1738 and clock_gettime. <<
1739 2529
1740 You must have a 32-bit build of gli !! 2530 config SYS_SUPPORTS_MICROMIPS
1741 to seamlessly take advantage of thi !! 2531 bool
1742 2532
1743 config THUMB2_COMPAT_VDSO !! 2533 config SYS_SUPPORTS_MIPS16
1744 bool "Compile the 32-bit vDSO for Thu !! 2534 bool
1745 depends on COMPAT_VDSO <<
1746 default y <<
1747 help 2535 help
1748 Compile the compat vDSO with '-mthu !! 2536 This option must be set if a kernel might be executed on a MIPS16-
1749 otherwise with '-marm'. !! 2537 enabled CPU even if MIPS16 is not actually being used. In other
1750 !! 2538 words, it makes the kernel MIPS16-tolerant.
1751 config COMPAT_ALIGNMENT_FIXUPS <<
1752 bool "Fix up misaligned multi-word lo <<
1753 2539
1754 menuconfig ARMV8_DEPRECATED !! 2540 config CPU_SUPPORTS_MSA
1755 bool "Emulate deprecated/obsolete ARM !! 2541 bool
1756 depends on SYSCTL <<
1757 help <<
1758 Legacy software support may require <<
1759 that have been deprecated or obsole <<
1760 2542
1761 Enable this config to enable select !! 2543 config ARCH_FLATMEM_ENABLE
1762 features. !! 2544 def_bool y
>> 2545 depends on !NUMA && !CPU_LOONGSON2
1763 2546
1764 If unsure, say Y !! 2547 config ARCH_DISCONTIGMEM_ENABLE
>> 2548 bool
>> 2549 default y if SGI_IP27
>> 2550 help
>> 2551 Say Y to support efficient handling of discontiguous physical memory,
>> 2552 for architectures which are either NUMA (Non-Uniform Memory Access)
>> 2553 or have huge holes in the physical address space for other reasons.
>> 2554 See <file:Documentation/vm/numa> for more.
1765 2555
1766 if ARMV8_DEPRECATED !! 2556 config ARCH_SPARSEMEM_ENABLE
>> 2557 bool
>> 2558 select SPARSEMEM_STATIC
1767 2559
1768 config SWP_EMULATION !! 2560 config NUMA
1769 bool "Emulate SWP/SWPB instructions" !! 2561 bool "NUMA Support"
>> 2562 depends on SYS_SUPPORTS_NUMA
1770 help 2563 help
1771 ARMv8 obsoletes the use of A32 SWP/ !! 2564 Say Y to compile the kernel to support NUMA (Non-Uniform Memory
1772 they are always undefined. Say Y he !! 2565 Access). This option improves performance on systems with more
1773 emulation of these instructions for !! 2566 than two nodes; on two node systems it is generally better to
1774 This feature can be controlled at r !! 2567 leave it disabled; on single node systems disable this option
1775 sysctl which is disabled by default !! 2568 disabled.
1776 2569
1777 In some older versions of glibc [<= !! 2570 config SYS_SUPPORTS_NUMA
1778 trylock() operations with the assum !! 2571 bool
1779 be preempted. This invalid assumpti <<
1780 with SWP emulation enabled, leading <<
1781 application. <<
1782 2572
1783 NOTE: when accessing uncached share !! 2573 config RELOCATABLE
1784 on an external transaction monitori !! 2574 bool "Relocatable kernel"
1785 monitor to maintain update atomicit !! 2575 depends on SYS_SUPPORTS_RELOCATABLE && (CPU_MIPS32_R2 || CPU_MIPS64_R2 || CPU_MIPS32_R6 || CPU_MIPS64_R6 || CAVIUM_OCTEON_SOC)
1786 implement a global monitor, this op !! 2576 help
1787 perform SWP operations to uncached !! 2577 This builds a kernel image that retains relocation information
>> 2578 so it can be loaded someplace besides the default 1MB.
>> 2579 The relocations make the kernel binary about 15% larger,
>> 2580 but are discarded at runtime
>> 2581
>> 2582 config RELOCATION_TABLE_SIZE
>> 2583 hex "Relocation table size"
>> 2584 depends on RELOCATABLE
>> 2585 range 0x0 0x01000000
>> 2586 default "0x00100000"
>> 2587 ---help---
>> 2588 A table of relocation data will be appended to the kernel binary
>> 2589 and parsed at boot to fix up the relocated kernel.
1788 2590
1789 If unsure, say Y !! 2591 This option allows the amount of space reserved for the table to be
>> 2592 adjusted, although the default of 1Mb should be ok in most cases.
1790 2593
1791 config CP15_BARRIER_EMULATION !! 2594 The build will fail and a valid size suggested if this is too small.
1792 bool "Emulate CP15 Barrier instructio <<
1793 help <<
1794 The CP15 barrier instructions - CP1 <<
1795 CP15DMB - are deprecated in ARMv8 ( <<
1796 strongly recommended to use the ISB <<
1797 instructions instead. <<
1798 2595
1799 Say Y here to enable software emula !! 2596 If unsure, leave at the default value.
1800 instructions for AArch32 userspace <<
1801 enabled, CP15 barrier usage is trac <<
1802 identify software that needs updati <<
1803 controlled at runtime with the abi. <<
1804 2597
1805 If unsure, say Y !! 2598 config RANDOMIZE_BASE
>> 2599 bool "Randomize the address of the kernel image"
>> 2600 depends on RELOCATABLE
>> 2601 ---help---
>> 2602 Randomizes the physical and virtual address at which the
>> 2603 kernel image is loaded, as a security feature that
>> 2604 deters exploit attempts relying on knowledge of the location
>> 2605 of kernel internals.
1806 2606
1807 config SETEND_EMULATION !! 2607 Entropy is generated using any coprocessor 0 registers available.
1808 bool "Emulate SETEND instruction" <<
1809 help <<
1810 The SETEND instruction alters the d <<
1811 AArch32 EL0, and is deprecated in A <<
1812 2608
1813 Say Y here to enable software emula !! 2609 The kernel will be offset by up to RANDOMIZE_BASE_MAX_OFFSET.
1814 for AArch32 userspace code. This fe <<
1815 at runtime with the abi.setend sysc <<
1816 2610
1817 Note: All the cpus on the system mu !! 2611 If unsure, say N.
1818 for this feature to be enabled. If <<
1819 endian - is hotplugged in after thi <<
1820 be unexpected results in the applic <<
1821 2612
1822 If unsure, say Y !! 2613 config RANDOMIZE_BASE_MAX_OFFSET
1823 endif # ARMV8_DEPRECATED !! 2614 hex "Maximum kASLR offset" if EXPERT
>> 2615 depends on RANDOMIZE_BASE
>> 2616 range 0x0 0x40000000 if EVA || 64BIT
>> 2617 range 0x0 0x08000000
>> 2618 default "0x01000000"
>> 2619 ---help---
>> 2620 When kASLR is active, this provides the maximum offset that will
>> 2621 be applied to the kernel image. It should be set according to the
>> 2622 amount of physical RAM available in the target system minus
>> 2623 PHYSICAL_START and must be a power of 2.
1824 2624
1825 endif # COMPAT !! 2625 This is limited by the size of KSEG0, 256Mb on 32-bit or 1Gb with
>> 2626 EVA or 64-bit. The default is 16Mb.
1826 2627
1827 menu "ARMv8.1 architectural features" !! 2628 config NODES_SHIFT
>> 2629 int
>> 2630 default "6"
>> 2631 depends on NEED_MULTIPLE_NODES
1828 2632
1829 config ARM64_HW_AFDBM !! 2633 config HW_PERF_EVENTS
1830 bool "Support for hardware updates of !! 2634 bool "Enable hardware performance counter support for perf events"
>> 2635 depends on PERF_EVENTS && !OPROFILE && (CPU_MIPS32 || CPU_MIPS64 || CPU_R10000 || CPU_SB1 || CPU_CAVIUM_OCTEON || CPU_XLP || CPU_LOONGSON3)
1831 default y 2636 default y
1832 help 2637 help
1833 The ARMv8.1 architecture extensions !! 2638 Enable hardware performance counter support for perf events. If
1834 hardware updates of the access and !! 2639 disabled, perf events will use software events only.
1835 table entries. When enabled in TCR_ <<
1836 capable processors, accesses to pag <<
1837 set this bit instead of raising an <<
1838 Similarly, writes to read-only page <<
1839 clear the read-only bit (AP[2]) ins <<
1840 permission fault. <<
1841 2640
1842 Kernels built with this configurati !! 2641 source "mm/Kconfig"
1843 to work on pre-ARMv8.1 hardware and <<
1844 minimal. If unsure, say Y. <<
1845 2642
1846 config ARM64_PAN !! 2643 config SMP
1847 bool "Enable support for Privileged A !! 2644 bool "Multi-Processing support"
1848 default y !! 2645 depends on SYS_SUPPORTS_SMP
1849 help 2646 help
1850 Privileged Access Never (PAN; part !! 2647 This enables support for systems with more than one CPU. If you have
1851 prevents the kernel or hypervisor f !! 2648 a system with only one CPU, say N. If you have a system with more
1852 memory directly. !! 2649 than one CPU, say Y.
>> 2650
>> 2651 If you say N here, the kernel will run on uni- and multiprocessor
>> 2652 machines, but will use only one CPU of a multiprocessor machine. If
>> 2653 you say Y here, the kernel will run on many, but not all,
>> 2654 uniprocessor machines. On a uniprocessor machine, the kernel
>> 2655 will run faster if you say N here.
1853 2656
1854 Choosing this option will cause any !! 2657 People using multiprocessor machines who say Y here should also say
1855 copy_to_user et al) memory access t !! 2658 Y to "Enhanced Real Time Clock Support", below.
1856 2659
1857 The feature is detected at runtime, !! 2660 See also the SMP-HOWTO available at
1858 instruction if the cpu does not imp !! 2661 <http://www.tldp.org/docs.html#howto>.
1859 2662
1860 config AS_HAS_LSE_ATOMICS !! 2663 If you don't know what to do here, say N.
1861 def_bool $(as-instr,.arch_extension l <<
1862 2664
1863 config ARM64_LSE_ATOMICS !! 2665 config HOTPLUG_CPU
1864 bool !! 2666 bool "Support for hot-pluggable CPUs"
1865 default ARM64_USE_LSE_ATOMICS !! 2667 depends on SMP && SYS_SUPPORTS_HOTPLUG_CPU
1866 depends on AS_HAS_LSE_ATOMICS <<
1867 <<
1868 config ARM64_USE_LSE_ATOMICS <<
1869 bool "Atomic instructions" <<
1870 default y <<
1871 help 2668 help
1872 As part of the Large System Extensi !! 2669 Say Y here to allow turning CPUs off and on. CPUs can be
1873 atomic instructions that are design !! 2670 controlled through /sys/devices/system/cpu.
1874 very large systems. !! 2671 (Note: power management support will enable this option
>> 2672 automatically on SMP systems. )
>> 2673 Say N if you want to disable CPU hotplug.
1875 2674
1876 Say Y here to make use of these ins !! 2675 config SMP_UP
1877 atomic routines. This incurs a smal !! 2676 bool
1878 not support these instructions and <<
1879 built with binutils >= 2.25 in orde <<
1880 to be used. <<
1881 <<
1882 endmenu # "ARMv8.1 architectural features" <<
1883 <<
1884 menu "ARMv8.2 architectural features" <<
1885 2677
1886 config AS_HAS_ARMV8_2 !! 2678 config SYS_SUPPORTS_MIPS_CMP
1887 def_bool $(cc-option,-Wa$(comma)-marc !! 2679 bool
1888 2680
1889 config AS_HAS_SHA3 !! 2681 config SYS_SUPPORTS_MIPS_CPS
1890 def_bool $(as-instr,.arch armv8.2-a+s !! 2682 bool
1891 2683
1892 config ARM64_PMEM !! 2684 config SYS_SUPPORTS_SMP
1893 bool "Enable support for persistent m !! 2685 bool
1894 select ARCH_HAS_PMEM_API <<
1895 select ARCH_HAS_UACCESS_FLUSHCACHE <<
1896 help <<
1897 Say Y to enable support for the per <<
1898 ARMv8.2 DCPoP feature. <<
1899 2686
1900 The feature is detected at runtime, !! 2687 config NR_CPUS_DEFAULT_4
1901 operations if DC CVAP is not suppor !! 2688 bool
1902 DC CVAP itself if the system does n <<
1903 2689
1904 config ARM64_RAS_EXTN !! 2690 config NR_CPUS_DEFAULT_8
1905 bool "Enable support for RAS CPU Exte !! 2691 bool
1906 default y <<
1907 help <<
1908 CPUs that support the Reliability, <<
1909 (RAS) Extensions, part of ARMv8.2 a <<
1910 errors, classify them and report th <<
1911 2692
1912 On CPUs with these extensions syste !! 2693 config NR_CPUS_DEFAULT_16
1913 barriers to determine if faults are !! 2694 bool
1914 classification from a new set of re <<
1915 2695
1916 Selecting this feature will allow t !! 2696 config NR_CPUS_DEFAULT_32
1917 and access the new registers if the !! 2697 bool
1918 Platform RAS features may additiona <<
1919 2698
1920 config ARM64_CNP !! 2699 config NR_CPUS_DEFAULT_64
1921 bool "Enable support for Common Not P !! 2700 bool
1922 default y <<
1923 depends on ARM64_PAN || !ARM64_SW_TTB <<
1924 help <<
1925 Common Not Private (CNP) allows tra <<
1926 be shared between different PEs in <<
1927 domain, so the hardware can use thi <<
1928 caching of such entries in the TLB. <<
1929 2701
1930 Selecting this option allows the CN !! 2702 config NR_CPUS
1931 at runtime, and does not affect PEs !! 2703 int "Maximum number of CPUs (2-256)"
1932 this feature. !! 2704 range 2 256
>> 2705 depends on SMP
>> 2706 default "4" if NR_CPUS_DEFAULT_4
>> 2707 default "8" if NR_CPUS_DEFAULT_8
>> 2708 default "16" if NR_CPUS_DEFAULT_16
>> 2709 default "32" if NR_CPUS_DEFAULT_32
>> 2710 default "64" if NR_CPUS_DEFAULT_64
>> 2711 help
>> 2712 This allows you to specify the maximum number of CPUs which this
>> 2713 kernel will support. The maximum supported value is 32 for 32-bit
>> 2714 kernel and 64 for 64-bit kernels; the minimum value which makes
>> 2715 sense is 1 for Qemu (useful only for kernel debugging purposes)
>> 2716 and 2 for all others.
>> 2717
>> 2718 This is purely to save memory - each supported CPU adds
>> 2719 approximately eight kilobytes to the kernel image. For best
>> 2720 performance should round up your number of processors to the next
>> 2721 power of two.
1933 2722
1934 endmenu # "ARMv8.2 architectural features" !! 2723 config MIPS_PERF_SHARED_TC_COUNTERS
>> 2724 bool
1935 2725
1936 menu "ARMv8.3 architectural features" !! 2726 #
>> 2727 # Timer Interrupt Frequency Configuration
>> 2728 #
1937 2729
1938 config ARM64_PTR_AUTH !! 2730 choice
1939 bool "Enable support for pointer auth !! 2731 prompt "Timer frequency"
1940 default y !! 2732 default HZ_250
1941 help 2733 help
1942 Pointer authentication (part of the !! 2734 Allows the configuration of the timer frequency.
1943 instructions for signing and authen <<
1944 keys, which can be used to mitigate <<
1945 and other attacks. <<
1946 2735
1947 This option enables these instructi !! 2736 config HZ_24
1948 Choosing this option will cause the !! 2737 bool "24 HZ" if SYS_SUPPORTS_24HZ || SYS_SUPPORTS_ARBIT_HZ
1949 for each process at exec() time, wi <<
1950 context-switched along with the pro <<
1951 2738
1952 The feature is detected at runtime. !! 2739 config HZ_48
1953 hardware it will not be advertised !! 2740 bool "48 HZ" if SYS_SUPPORTS_48HZ || SYS_SUPPORTS_ARBIT_HZ
1954 be enabled. <<
1955 2741
1956 If the feature is present on the bo !! 2742 config HZ_100
1957 the late CPU will be parked. Also, !! 2743 bool "100 HZ" if SYS_SUPPORTS_100HZ || SYS_SUPPORTS_ARBIT_HZ
1958 address auth and the late CPU has t <<
1959 but with the feature disabled. On s <<
1960 not be selected. <<
1961 2744
1962 config ARM64_PTR_AUTH_KERNEL !! 2745 config HZ_128
1963 bool "Use pointer authentication for !! 2746 bool "128 HZ" if SYS_SUPPORTS_128HZ || SYS_SUPPORTS_ARBIT_HZ
1964 default y <<
1965 depends on ARM64_PTR_AUTH <<
1966 depends on (CC_HAS_SIGN_RETURN_ADDRES <<
1967 # Modern compilers insert a .note.gnu <<
1968 # which is only understood by binutil <<
1969 depends on LD_IS_LLD || LD_VERSION >= <<
1970 depends on !CC_IS_CLANG || AS_HAS_CFI <<
1971 depends on (!FUNCTION_GRAPH_TRACER || <<
1972 help <<
1973 If the compiler supports the -mbran <<
1974 -msign-return-address flag (e.g. GC <<
1975 will cause the kernel itself to be <<
1976 protection. In this case, and if th <<
1977 support pointer authentication, the <<
1978 disabled with minimal loss of prote <<
1979 2747
1980 This feature works with FUNCTION_GR !! 2748 config HZ_250
1981 DYNAMIC_FTRACE_WITH_ARGS is enabled !! 2749 bool "250 HZ" if SYS_SUPPORTS_250HZ || SYS_SUPPORTS_ARBIT_HZ
1982 2750
1983 config CC_HAS_BRANCH_PROT_PAC_RET !! 2751 config HZ_256
1984 # GCC 9 or later, clang 8 or later !! 2752 bool "256 HZ" if SYS_SUPPORTS_256HZ || SYS_SUPPORTS_ARBIT_HZ
1985 def_bool $(cc-option,-mbranch-protect <<
1986 2753
1987 config CC_HAS_SIGN_RETURN_ADDRESS !! 2754 config HZ_1000
1988 # GCC 7, 8 !! 2755 bool "1000 HZ" if SYS_SUPPORTS_1000HZ || SYS_SUPPORTS_ARBIT_HZ
1989 def_bool $(cc-option,-msign-return-ad <<
1990 2756
1991 config AS_HAS_ARMV8_3 !! 2757 config HZ_1024
1992 def_bool $(cc-option,-Wa$(comma)-marc !! 2758 bool "1024 HZ" if SYS_SUPPORTS_1024HZ || SYS_SUPPORTS_ARBIT_HZ
1993 2759
1994 config AS_HAS_CFI_NEGATE_RA_STATE !! 2760 endchoice
1995 def_bool $(as-instr,.cfi_startproc\n. <<
1996 2761
1997 config AS_HAS_LDAPR !! 2762 config SYS_SUPPORTS_24HZ
1998 def_bool $(as-instr,.arch_extension r !! 2763 bool
1999 2764
2000 endmenu # "ARMv8.3 architectural features" !! 2765 config SYS_SUPPORTS_48HZ
>> 2766 bool
2001 2767
2002 menu "ARMv8.4 architectural features" !! 2768 config SYS_SUPPORTS_100HZ
>> 2769 bool
2003 2770
2004 config ARM64_AMU_EXTN !! 2771 config SYS_SUPPORTS_128HZ
2005 bool "Enable support for the Activity !! 2772 bool
2006 default y <<
2007 help <<
2008 The activity monitors extension is <<
2009 by the ARMv8.4 CPU architecture. Th <<
2010 of the activity monitors architectu <<
2011 2773
2012 To enable the use of this extension !! 2774 config SYS_SUPPORTS_250HZ
>> 2775 bool
2013 2776
2014 Note that for architectural reasons !! 2777 config SYS_SUPPORTS_256HZ
2015 support when running on CPUs that p !! 2778 bool
2016 extension. The required support is <<
2017 * Version 1.5 and later of the AR <<
2018 2779
2019 For kernels that have this configur !! 2780 config SYS_SUPPORTS_1000HZ
2020 firmware, you may need to say N her !! 2781 bool
2021 Otherwise you may experience firmwa <<
2022 accessing the counter registers. Ev <<
2023 symptoms, the values returned by th <<
2024 correctly reflect reality. Most com <<
2025 indicating that the counter is not <<
2026 2782
2027 config AS_HAS_ARMV8_4 !! 2783 config SYS_SUPPORTS_1024HZ
2028 def_bool $(cc-option,-Wa$(comma)-marc !! 2784 bool
2029 2785
2030 config ARM64_TLB_RANGE !! 2786 config SYS_SUPPORTS_ARBIT_HZ
2031 bool "Enable support for tlbi range f !! 2787 bool
2032 default y !! 2788 default y if !SYS_SUPPORTS_24HZ && \
2033 depends on AS_HAS_ARMV8_4 !! 2789 !SYS_SUPPORTS_48HZ && \
2034 help !! 2790 !SYS_SUPPORTS_100HZ && \
2035 ARMv8.4-TLBI provides TLBI invalida !! 2791 !SYS_SUPPORTS_128HZ && \
2036 range of input addresses. !! 2792 !SYS_SUPPORTS_250HZ && \
>> 2793 !SYS_SUPPORTS_256HZ && \
>> 2794 !SYS_SUPPORTS_1000HZ && \
>> 2795 !SYS_SUPPORTS_1024HZ
2037 2796
2038 The feature introduces new assembly !! 2797 config HZ
2039 support when binutils >= 2.30. !! 2798 int
>> 2799 default 24 if HZ_24
>> 2800 default 48 if HZ_48
>> 2801 default 100 if HZ_100
>> 2802 default 128 if HZ_128
>> 2803 default 250 if HZ_250
>> 2804 default 256 if HZ_256
>> 2805 default 1000 if HZ_1000
>> 2806 default 1024 if HZ_1024
>> 2807
>> 2808 config SCHED_HRTICK
>> 2809 def_bool HIGH_RES_TIMERS
>> 2810
>> 2811 source "kernel/Kconfig.preempt"
>> 2812
>> 2813 config KEXEC
>> 2814 bool "Kexec system call"
>> 2815 select KEXEC_CORE
>> 2816 help
>> 2817 kexec is a system call that implements the ability to shutdown your
>> 2818 current kernel, and to start another kernel. It is like a reboot
>> 2819 but it is independent of the system firmware. And like a reboot
>> 2820 you can start any kernel with it, not just Linux.
>> 2821
>> 2822 The name comes from the similarity to the exec system call.
>> 2823
>> 2824 It is an ongoing process to be certain the hardware in a machine
>> 2825 is properly shutdown, so do not be surprised if this code does not
>> 2826 initially work for you. As of this writing the exact hardware
>> 2827 interface is strongly in flux, so no good recommendation can be
>> 2828 made.
>> 2829
>> 2830 config CRASH_DUMP
>> 2831 bool "Kernel crash dumps"
>> 2832 help
>> 2833 Generate crash dump after being started by kexec.
>> 2834 This should be normally only set in special crash dump kernels
>> 2835 which are loaded in the main kernel with kexec-tools into
>> 2836 a specially reserved region and then later executed after
>> 2837 a crash by kdump/kexec. The crash dump kernel must be compiled
>> 2838 to a memory address not used by the main kernel or firmware using
>> 2839 PHYSICAL_START.
>> 2840
>> 2841 config PHYSICAL_START
>> 2842 hex "Physical address where the kernel is loaded"
>> 2843 default "0xffffffff84000000" if 64BIT
>> 2844 default "0x84000000" if 32BIT
>> 2845 depends on CRASH_DUMP
>> 2846 help
>> 2847 This gives the CKSEG0 or KSEG0 address where the kernel is loaded.
>> 2848 If you plan to use kernel for capturing the crash dump change
>> 2849 this value to start of the reserved region (the "X" value as
>> 2850 specified in the "crashkernel=YM@XM" command line boot parameter
>> 2851 passed to the panic-ed kernel).
>> 2852
>> 2853 config SECCOMP
>> 2854 bool "Enable seccomp to safely compute untrusted bytecode"
>> 2855 depends on PROC_FS
>> 2856 default y
>> 2857 help
>> 2858 This kernel feature is useful for number crunching applications
>> 2859 that may need to compute untrusted bytecode during their
>> 2860 execution. By using pipes or other transports made available to
>> 2861 the process as file descriptors supporting the read/write
>> 2862 syscalls, it's possible to isolate those applications in
>> 2863 their own address space using seccomp. Once seccomp is
>> 2864 enabled via /proc/<pid>/seccomp, it cannot be disabled
>> 2865 and the task is only allowed to execute a few safe syscalls
>> 2866 defined by each seccomp mode.
>> 2867
>> 2868 If unsure, say Y. Only embedded should say N here.
>> 2869
>> 2870 config MIPS_O32_FP64_SUPPORT
>> 2871 bool "Support for O32 binaries using 64-bit FP"
>> 2872 depends on 32BIT || MIPS32_O32
>> 2873 help
>> 2874 When this is enabled, the kernel will support use of 64-bit floating
>> 2875 point registers with binaries using the O32 ABI along with the
>> 2876 EF_MIPS_FP64 ELF header flag (typically built with -mfp64). On
>> 2877 32-bit MIPS systems this support is at the cost of increasing the
>> 2878 size and complexity of the compiled FPU emulator. Thus if you are
>> 2879 running a MIPS32 system and know that none of your userland binaries
>> 2880 will require 64-bit floating point, you may wish to reduce the size
>> 2881 of your kernel & potentially improve FP emulation performance by
>> 2882 saying N here.
>> 2883
>> 2884 Although binutils currently supports use of this flag the details
>> 2885 concerning its effect upon the O32 ABI in userland are still being
>> 2886 worked on. In order to avoid userland becoming dependant upon current
>> 2887 behaviour before the details have been finalised, this option should
>> 2888 be considered experimental and only enabled by those working upon
>> 2889 said details.
2040 2890
2041 endmenu # "ARMv8.4 architectural features" !! 2891 If unsure, say N.
2042 2892
2043 menu "ARMv8.5 architectural features" !! 2893 config USE_OF
>> 2894 bool
>> 2895 select OF
>> 2896 select OF_EARLY_FLATTREE
>> 2897 select IRQ_DOMAIN
2044 2898
2045 config AS_HAS_ARMV8_5 !! 2899 config BUILTIN_DTB
2046 def_bool $(cc-option,-Wa$(comma)-marc !! 2900 bool
2047 2901
2048 config ARM64_BTI !! 2902 choice
2049 bool "Branch Target Identification su !! 2903 prompt "Kernel appended dtb support" if USE_OF
2050 default y !! 2904 default MIPS_NO_APPENDED_DTB
2051 help <<
2052 Branch Target Identification (part <<
2053 provides a mechanism to limit the s <<
2054 branch instructions such as BR or B <<
2055 2905
2056 To make use of BTI on CPUs that sup !! 2906 config MIPS_NO_APPENDED_DTB
>> 2907 bool "None"
>> 2908 help
>> 2909 Do not enable appended dtb support.
>> 2910
>> 2911 config MIPS_ELF_APPENDED_DTB
>> 2912 bool "vmlinux"
>> 2913 help
>> 2914 With this option, the boot code will look for a device tree binary
>> 2915 DTB) included in the vmlinux ELF section .appended_dtb. By default
>> 2916 it is empty and the DTB can be appended using binutils command
>> 2917 objcopy:
>> 2918
>> 2919 objcopy --update-section .appended_dtb=<filename>.dtb vmlinux
>> 2920
>> 2921 This is meant as a backward compatiblity convenience for those
>> 2922 systems with a bootloader that can't be upgraded to accommodate
>> 2923 the documented boot protocol using a device tree.
>> 2924
>> 2925 config MIPS_RAW_APPENDED_DTB
>> 2926 bool "vmlinux.bin or vmlinuz.bin"
>> 2927 help
>> 2928 With this option, the boot code will look for a device tree binary
>> 2929 DTB) appended to raw vmlinux.bin or vmlinuz.bin.
>> 2930 (e.g. cat vmlinux.bin <filename>.dtb > vmlinux_w_dtb).
>> 2931
>> 2932 This is meant as a backward compatibility convenience for those
>> 2933 systems with a bootloader that can't be upgraded to accommodate
>> 2934 the documented boot protocol using a device tree.
>> 2935
>> 2936 Beware that there is very little in terms of protection against
>> 2937 this option being confused by leftover garbage in memory that might
>> 2938 look like a DTB header after a reboot if no actual DTB is appended
>> 2939 to vmlinux.bin. Do not leave this option active in a production kernel
>> 2940 if you don't intend to always append a DTB.
>> 2941 endchoice
2057 2942
2058 BTI is intended to provide compleme !! 2943 choice
2059 flow integrity protection mechanism !! 2944 prompt "Kernel command line type" if !CMDLINE_OVERRIDE
2060 authentication mechanism provided a !! 2945 default MIPS_CMDLINE_FROM_DTB if USE_OF && !ATH79 && !MACH_INGENIC && \
2061 For this reason, it does not make s !! 2946 !MIPS_MALTA && \
2062 also enabling support for pointer a !! 2947 !CAVIUM_OCTEON_SOC
2063 enabling this option you should als !! 2948 default MIPS_CMDLINE_FROM_BOOTLOADER
>> 2949
>> 2950 config MIPS_CMDLINE_FROM_DTB
>> 2951 depends on USE_OF
>> 2952 bool "Dtb kernel arguments if available"
>> 2953
>> 2954 config MIPS_CMDLINE_DTB_EXTEND
>> 2955 depends on USE_OF
>> 2956 bool "Extend dtb kernel arguments with bootloader arguments"
>> 2957
>> 2958 config MIPS_CMDLINE_FROM_BOOTLOADER
>> 2959 bool "Bootloader kernel arguments if available"
>> 2960
>> 2961 config MIPS_CMDLINE_BUILTIN_EXTEND
>> 2962 depends on CMDLINE_BOOL
>> 2963 bool "Extend builtin kernel arguments with bootloader arguments"
>> 2964 endchoice
2064 2965
2065 Userspace binaries must also be spe !! 2966 endmenu
2066 this mechanism. If you say N here <<
2067 BTI, such binaries can still run, b <<
2068 enforcement of branch destinations. <<
2069 2967
2070 config ARM64_BTI_KERNEL !! 2968 config LOCKDEP_SUPPORT
2071 bool "Use Branch Target Identificatio !! 2969 bool
2072 default y 2970 default y
2073 depends on ARM64_BTI <<
2074 depends on ARM64_PTR_AUTH_KERNEL <<
2075 depends on CC_HAS_BRANCH_PROT_PAC_RET <<
2076 # https://gcc.gnu.org/bugzilla/show_b <<
2077 depends on !CC_IS_GCC || GCC_VERSION <<
2078 # https://gcc.gnu.org/bugzilla/show_b <<
2079 depends on !CC_IS_GCC <<
2080 depends on (!FUNCTION_GRAPH_TRACER || <<
2081 help <<
2082 Build the kernel with Branch Target <<
2083 and enable enforcement of this for <<
2084 is enabled and the system supports <<
2085 modular code must have BTI enabled. <<
2086 <<
2087 config CC_HAS_BRANCH_PROT_PAC_RET_BTI <<
2088 # GCC 9 or later, clang 8 or later <<
2089 def_bool $(cc-option,-mbranch-protect <<
2090 2971
2091 config ARM64_E0PD !! 2972 config STACKTRACE_SUPPORT
2092 bool "Enable support for E0PD" !! 2973 bool
2093 default y 2974 default y
2094 help <<
2095 E0PD (part of the ARMv8.5 extension <<
2096 that EL0 accesses made via TTBR1 al <<
2097 providing similar benefits to KASLR <<
2098 with lower overhead and without dis <<
2099 kernel memory such as SPE. <<
2100 2975
2101 This option enables E0PD for TTBR1 !! 2976 config HAVE_LATENCYTOP_SUPPORT
2102 !! 2977 bool
2103 config ARM64_AS_HAS_MTE <<
2104 # Initial support for MTE went in bin <<
2105 # ".arch armv8.5-a+memtag" below. How <<
2106 # as a late addition to the final arc <<
2107 # is only supported in the newer 2.32 <<
2108 # versions, hence the extra "stgm" in <<
2109 def_bool $(as-instr,.arch armv8.5-a+m <<
2110 <<
2111 config ARM64_MTE <<
2112 bool "Memory Tagging Extension suppor <<
2113 default y 2978 default y
2114 depends on ARM64_AS_HAS_MTE && ARM64_ <<
2115 depends on AS_HAS_ARMV8_5 <<
2116 depends on AS_HAS_LSE_ATOMICS <<
2117 # Required for tag checking in the ua <<
2118 depends on ARM64_PAN <<
2119 select ARCH_HAS_SUBPAGE_FAULTS <<
2120 select ARCH_USES_HIGH_VMA_FLAGS <<
2121 select ARCH_USES_PG_ARCH_2 <<
2122 select ARCH_USES_PG_ARCH_3 <<
2123 help <<
2124 Memory Tagging (part of the ARMv8.5 <<
2125 architectural support for run-time, <<
2126 various classes of memory error to <<
2127 to eliminate vulnerabilities arisin <<
2128 languages. <<
2129 <<
2130 This option enables the support for <<
2131 Extension at EL0 (i.e. for userspac <<
2132 2979
2133 Selecting this option allows the fe !! 2980 config PGTABLE_LEVELS
2134 runtime. Any secondary CPU not impl !! 2981 int
2135 not be allowed a late bring-up. !! 2982 default 4 if PAGE_SIZE_4KB && MIPS_VA_BITS_48
>> 2983 default 3 if 64BIT && !PAGE_SIZE_64KB
>> 2984 default 2
2136 2985
2137 Userspace binaries that want to use !! 2986 source "init/Kconfig"
2138 explicitly opt in. The mechanism fo <<
2139 described in: <<
2140 2987
2141 Documentation/arch/arm64/memory-tag !! 2988 source "kernel/Kconfig.freezer"
2142 2989
2143 endmenu # "ARMv8.5 architectural features" !! 2990 menu "Bus options (PCI, PCMCIA, EISA, ISA, TC)"
2144 2991
2145 menu "ARMv8.7 architectural features" !! 2992 config HW_HAS_EISA
>> 2993 bool
>> 2994 config HW_HAS_PCI
>> 2995 bool
2146 2996
2147 config ARM64_EPAN !! 2997 config PCI
2148 bool "Enable support for Enhanced Pri !! 2998 bool "Support for PCI controller"
2149 default y !! 2999 depends on HW_HAS_PCI
2150 depends on ARM64_PAN !! 3000 select PCI_DOMAINS
2151 help !! 3001 help
2152 Enhanced Privileged Access Never (E !! 3002 Find out whether you have a PCI motherboard. PCI is the name of a
2153 Access Never to be used with Execut !! 3003 bus system, i.e. the way the CPU talks to the other stuff inside
>> 3004 your box. Other bus systems are ISA, EISA, or VESA. If you have PCI,
>> 3005 say Y, otherwise N.
>> 3006
>> 3007 config HT_PCI
>> 3008 bool "Support for HT-linked PCI"
>> 3009 default y
>> 3010 depends on CPU_LOONGSON3
>> 3011 select PCI
>> 3012 select PCI_DOMAINS
>> 3013 help
>> 3014 Loongson family machines use Hyper-Transport bus for inter-core
>> 3015 connection and device connection. The PCI bus is a subordinate
>> 3016 linked at HT. Choose Y for Loongson-3 based machines.
2154 3017
2155 The feature is detected at runtime, !! 3018 config PCI_DOMAINS
2156 if the cpu does not implement the f !! 3019 bool
2157 endmenu # "ARMv8.7 architectural features" <<
2158 3020
2159 menu "ARMv8.9 architectural features" !! 3021 config PCI_DOMAINS_GENERIC
>> 3022 bool
2160 3023
2161 config ARM64_POE !! 3024 config PCI_DRIVERS_GENERIC
2162 prompt "Permission Overlay Extension" !! 3025 select PCI_DOMAINS_GENERIC if PCI_DOMAINS
2163 def_bool y !! 3026 bool
2164 select ARCH_USES_HIGH_VMA_FLAGS <<
2165 select ARCH_HAS_PKEYS <<
2166 help <<
2167 The Permission Overlay Extension is <<
2168 Protection Keys. Memory Protection <<
2169 enforcing page-based protections, b <<
2170 of the page tables when an applicat <<
2171 3027
2172 For details, see Documentation/core !! 3028 config PCI_DRIVERS_LEGACY
>> 3029 def_bool !PCI_DRIVERS_GENERIC
>> 3030 select NO_GENERIC_PCI_IOPORT_MAP
2173 3031
2174 If unsure, say y. !! 3032 source "drivers/pci/Kconfig"
2175 3033
2176 config ARCH_PKEY_BITS !! 3034 #
2177 int !! 3035 # ISA support is now enabled via select. Too many systems still have the one
2178 default 3 !! 3036 # or other ISA chip on the board that users don't know about so don't expect
>> 3037 # users to choose the right thing ...
>> 3038 #
>> 3039 config ISA
>> 3040 bool
2179 3041
2180 endmenu # "ARMv8.9 architectural features" !! 3042 config EISA
>> 3043 bool "EISA support"
>> 3044 depends on HW_HAS_EISA
>> 3045 select ISA
>> 3046 select GENERIC_ISA_DMA
>> 3047 ---help---
>> 3048 The Extended Industry Standard Architecture (EISA) bus was
>> 3049 developed as an open alternative to the IBM MicroChannel bus.
>> 3050
>> 3051 The EISA bus provided some of the features of the IBM MicroChannel
>> 3052 bus while maintaining backward compatibility with cards made for
>> 3053 the older ISA bus. The EISA bus saw limited use between 1988 and
>> 3054 1995 when it was made obsolete by the PCI bus.
>> 3055
>> 3056 Say Y here if you are building a kernel for an EISA-based machine.
>> 3057
>> 3058 Otherwise, say N.
>> 3059
>> 3060 source "drivers/eisa/Kconfig"
>> 3061
>> 3062 config TC
>> 3063 bool "TURBOchannel support"
>> 3064 depends on MACH_DECSTATION
>> 3065 help
>> 3066 TURBOchannel is a DEC (now Compaq (now HP)) bus for Alpha and MIPS
>> 3067 processors. TURBOchannel programming specifications are available
>> 3068 at:
>> 3069 <ftp://ftp.hp.com/pub/alphaserver/archive/triadd/>
>> 3070 and:
>> 3071 <http://www.computer-refuge.org/classiccmp/ftp.digital.com/pub/DEC/TriAdd/>
>> 3072 Linux driver support status is documented at:
>> 3073 <http://www.linux-mips.org/wiki/DECstation>
2181 3074
2182 config ARM64_SVE !! 3075 config MMU
2183 bool "ARM Scalable Vector Extension s !! 3076 bool
2184 default y 3077 default y
2185 help <<
2186 The Scalable Vector Extension (SVE) <<
2187 execution state which complements a <<
2188 of the base architecture to support <<
2189 additional vectorisation opportunit <<
2190 3078
2191 To enable use of this extension on !! 3079 config ARCH_MMAP_RND_BITS_MIN
2192 !! 3080 default 12 if 64BIT
2193 On CPUs that support the SVE2 exten !! 3081 default 8
2194 those too. <<
2195 <<
2196 Note that for architectural reasons <<
2197 support when running on SVE capable <<
2198 is present in: <<
2199 <<
2200 * version 1.5 and later of the AR <<
2201 * the AArch64 boot wrapper since <<
2202 ("bootwrapper: SVE: Enable SVE <<
2203 <<
2204 For other firmware implementations, <<
2205 or vendor. <<
2206 <<
2207 If you need the kernel to boot on S <<
2208 firmware, you may need to say N her <<
2209 fixed. Otherwise, you may experien <<
2210 booting the kernel. If unsure and <<
2211 symptoms, you should assume that it <<
2212 3082
2213 config ARM64_SME !! 3083 config ARCH_MMAP_RND_BITS_MAX
2214 bool "ARM Scalable Matrix Extension s !! 3084 default 18 if 64BIT
2215 default y !! 3085 default 15
2216 depends on ARM64_SVE <<
2217 depends on BROKEN <<
2218 help <<
2219 The Scalable Matrix Extension (SME) <<
2220 execution state which utilises a su <<
2221 instruction set, together with the <<
2222 register state capable of holding t <<
2223 enable various matrix operations. <<
2224 3086
2225 config ARM64_PSEUDO_NMI !! 3087 config ARCH_MMAP_RND_COMPAT_BITS_MIN
2226 bool "Support for NMI-like interrupts !! 3088 default 8
2227 select ARM_GIC_V3 <<
2228 help <<
2229 Adds support for mimicking Non-Mask <<
2230 GIC interrupt priority. This suppor <<
2231 ARM GIC. <<
2232 3089
2233 This high priority configuration fo !! 3090 config ARCH_MMAP_RND_COMPAT_BITS_MAX
2234 explicitly enabled by setting the k !! 3091 default 15
2235 "irqchip.gicv3_pseudo_nmi" to 1. <<
2236 3092
2237 If unsure, say N !! 3093 config I8253
>> 3094 bool
>> 3095 select CLKSRC_I8253
>> 3096 select CLKEVT_I8253
>> 3097 select MIPS_EXTERNAL_TIMER
2238 3098
2239 if ARM64_PSEUDO_NMI !! 3099 config ZONE_DMA
2240 config ARM64_DEBUG_PRIORITY_MASKING !! 3100 bool
2241 bool "Debug interrupt priority maskin <<
2242 help <<
2243 This adds runtime checks to functio <<
2244 interrupts when using priority mask <<
2245 the validity of ICC_PMR_EL1 when ca <<
2246 3101
2247 If unsure, say N !! 3102 config ZONE_DMA32
2248 endif # ARM64_PSEUDO_NMI !! 3103 bool
2249 3104
2250 config RELOCATABLE !! 3105 source "drivers/pcmcia/Kconfig"
2251 bool "Build a relocatable kernel imag <<
2252 select ARCH_HAS_RELR <<
2253 default y <<
2254 help <<
2255 This builds the kernel as a Positio <<
2256 which retains all relocation metada <<
2257 kernel binary at runtime to a diffe <<
2258 address it was linked at. <<
2259 Since AArch64 uses the RELA relocat <<
2260 relocation pass at runtime even if <<
2261 same address it was linked at. <<
2262 3106
2263 config RANDOMIZE_BASE !! 3107 config RAPIDIO
2264 bool "Randomize the address of the ke !! 3108 tristate "RapidIO support"
2265 select RELOCATABLE !! 3109 depends on PCI
>> 3110 default n
2266 help 3111 help
2267 Randomizes the virtual address at w !! 3112 If you say Y here, the kernel will include drivers and
2268 loaded, as a security feature that !! 3113 infrastructure code to support RapidIO interconnect devices.
2269 relying on knowledge of the locatio <<
2270 <<
2271 It is the bootloader's job to provi <<
2272 random u64 value in /chosen/kaslr-s <<
2273 <<
2274 When booting via the UEFI stub, it <<
2275 EFI_RNG_PROTOCOL implementation (if <<
2276 to the kernel proper. In addition, <<
2277 location of the kernel Image as wel <<
2278 3114
2279 If unsure, say N. !! 3115 source "drivers/rapidio/Kconfig"
2280 3116
2281 config RANDOMIZE_MODULE_REGION_FULL !! 3117 endmenu
2282 bool "Randomize the module region ove <<
2283 depends on RANDOMIZE_BASE <<
2284 default y <<
2285 help <<
2286 Randomizes the location of the modu <<
2287 covering the core kernel. This way, <<
2288 to leak information about the locat <<
2289 but it does imply that function cal <<
2290 kernel will need to be resolved via <<
2291 <<
2292 When this option is not set, the mo <<
2293 a limited range that contains the [ <<
2294 core kernel, so branch relocations <<
2295 the region is exhausted. In this pa <<
2296 exhaustion, modules might be able t <<
2297 3118
2298 config CC_HAVE_STACKPROTECTOR_SYSREG !! 3119 menu "Executable file formats"
2299 def_bool $(cc-option,-mstack-protecto <<
2300 3120
2301 config STACKPROTECTOR_PER_TASK !! 3121 source "fs/Kconfig.binfmt"
2302 def_bool y <<
2303 depends on STACKPROTECTOR && CC_HAVE_ <<
2304 3122
2305 config UNWIND_PATCH_PAC_INTO_SCS !! 3123 config TRAD_SIGNALS
2306 bool "Enable shadow call stack dynami !! 3124 bool
2307 # needs Clang with https://github.com <<
2308 depends on CC_IS_CLANG && CLANG_VERSI <<
2309 depends on ARM64_PTR_AUTH_KERNEL && C <<
2310 depends on SHADOW_CALL_STACK <<
2311 select UNWIND_TABLES <<
2312 select DYNAMIC_SCS <<
2313 <<
2314 config ARM64_CONTPTE <<
2315 bool "Contiguous PTE mappings for use <<
2316 depends on TRANSPARENT_HUGEPAGE <<
2317 default y <<
2318 help <<
2319 When enabled, user mappings are con <<
2320 bit, for any mappings that meet the <<
2321 This reduces TLB pressure and impro <<
2322 <<
2323 endmenu # "Kernel Features" <<
2324 <<
2325 menu "Boot options" <<
2326 <<
2327 config ARM64_ACPI_PARKING_PROTOCOL <<
2328 bool "Enable support for the ARM64 AC <<
2329 depends on ACPI <<
2330 help <<
2331 Enable support for the ARM64 ACPI p <<
2332 the kernel will not allow booting t <<
2333 protocol even if the corresponding <<
2334 MADT table. <<
2335 <<
2336 config CMDLINE <<
2337 string "Default kernel command string <<
2338 default "" <<
2339 help <<
2340 Provide a set of default command-li <<
2341 entering them here. As a minimum, y <<
2342 root device (e.g. root=/dev/nfs). <<
2343 3125
2344 choice !! 3126 config MIPS32_COMPAT
2345 prompt "Kernel command line type" !! 3127 bool
2346 depends on CMDLINE != "" <<
2347 default CMDLINE_FROM_BOOTLOADER <<
2348 help <<
2349 Choose how the kernel will handle t <<
2350 command line string. <<
2351 <<
2352 config CMDLINE_FROM_BOOTLOADER <<
2353 bool "Use bootloader kernel arguments <<
2354 help <<
2355 Uses the command-line options passe <<
2356 the boot loader doesn't provide any <<
2357 string provided in CMDLINE will be <<
2358 <<
2359 config CMDLINE_FORCE <<
2360 bool "Always use the default kernel c <<
2361 help <<
2362 Always use the default kernel comma <<
2363 loader passes other arguments to th <<
2364 This is useful if you cannot or don <<
2365 command-line options your boot load <<
2366 3128
2367 endchoice !! 3129 config COMPAT
>> 3130 bool
2368 3131
2369 config EFI_STUB !! 3132 config SYSVIPC_COMPAT
2370 bool 3133 bool
2371 3134
2372 config EFI !! 3135 config MIPS32_O32
2373 bool "UEFI runtime support" !! 3136 bool "Kernel support for o32 binaries"
2374 depends on OF && !CPU_BIG_ENDIAN !! 3137 depends on 64BIT
2375 depends on KERNEL_MODE_NEON !! 3138 select ARCH_WANT_OLD_COMPAT_IPC
2376 select ARCH_SUPPORTS_ACPI !! 3139 select COMPAT
2377 select LIBFDT !! 3140 select MIPS32_COMPAT
2378 select UCS2_STRING !! 3141 select SYSVIPC_COMPAT if SYSVIPC
2379 select EFI_PARAMS_FROM_FDT !! 3142 help
2380 select EFI_RUNTIME_WRAPPERS !! 3143 Select this option if you want to run o32 binaries. These are pure
2381 select EFI_STUB !! 3144 32-bit binaries as used by the 32-bit Linux/MIPS port. Most of
2382 select EFI_GENERIC_STUB !! 3145 existing binaries are in this format.
2383 imply IMA_SECURE_AND_OR_TRUSTED_BOOT <<
2384 default y <<
2385 help <<
2386 This option provides support for ru <<
2387 by UEFI firmware (such as non-volat <<
2388 clock, and platform reset). A UEFI <<
2389 allow the kernel to be booted as an <<
2390 is only useful on systems that have <<
2391 3146
2392 config COMPRESSED_INSTALL !! 3147 If unsure, say Y.
2393 bool "Install compressed image by def <<
2394 help <<
2395 This makes the regular "make instal <<
2396 image we built, not the legacy unco <<
2397 3148
2398 You can check that a compressed ima !! 3149 config MIPS32_N32
2399 "make zinstall" first, and verifyin !! 3150 bool "Kernel support for n32 binaries"
2400 in your environment before making " !! 3151 depends on 64BIT
2401 you. !! 3152 select COMPAT
>> 3153 select MIPS32_COMPAT
>> 3154 select SYSVIPC_COMPAT if SYSVIPC
>> 3155 help
>> 3156 Select this option if you want to run n32 binaries. These are
>> 3157 64-bit binaries using 32-bit quantities for addressing and certain
>> 3158 data that would normally be 64-bit. They are used in special
>> 3159 cases.
2402 3160
2403 config DMI !! 3161 If unsure, say N.
2404 bool "Enable support for SMBIOS (DMI) <<
2405 depends on EFI <<
2406 default y <<
2407 help <<
2408 This enables SMBIOS/DMI feature for <<
2409 3162
2410 This option is only useful on syste !! 3163 config BINFMT_ELF32
2411 However, even with this option, the !! 3164 bool
2412 continue to boot on existing non-UE !! 3165 default y if MIPS32_O32 || MIPS32_N32
>> 3166 select ELFCORE
2413 3167
2414 endmenu # "Boot options" !! 3168 endmenu
2415 3169
2416 menu "Power management options" 3170 menu "Power management options"
2417 3171
2418 source "kernel/power/Kconfig" <<
2419 <<
2420 config ARCH_HIBERNATION_POSSIBLE 3172 config ARCH_HIBERNATION_POSSIBLE
2421 def_bool y 3173 def_bool y
2422 depends on CPU_PM !! 3174 depends on SYS_SUPPORTS_HOTPLUG_CPU || !SMP
2423 <<
2424 config ARCH_HIBERNATION_HEADER <<
2425 def_bool y <<
2426 depends on HIBERNATION <<
2427 3175
2428 config ARCH_SUSPEND_POSSIBLE 3176 config ARCH_SUSPEND_POSSIBLE
2429 def_bool y 3177 def_bool y
>> 3178 depends on SYS_SUPPORTS_HOTPLUG_CPU || !SMP
2430 3179
2431 endmenu # "Power management options" !! 3180 source "kernel/power/Kconfig"
>> 3181
>> 3182 endmenu
>> 3183
>> 3184 config MIPS_EXTERNAL_TIMER
>> 3185 bool
2432 3186
2433 menu "CPU Power Management" 3187 menu "CPU Power Management"
2434 3188
>> 3189 if CPU_SUPPORTS_CPUFREQ && MIPS_EXTERNAL_TIMER
>> 3190 source "drivers/cpufreq/Kconfig"
>> 3191 endif
>> 3192
2435 source "drivers/cpuidle/Kconfig" 3193 source "drivers/cpuidle/Kconfig"
2436 3194
2437 source "drivers/cpufreq/Kconfig" !! 3195 endmenu
>> 3196
>> 3197 source "net/Kconfig"
>> 3198
>> 3199 source "drivers/Kconfig"
>> 3200
>> 3201 source "drivers/firmware/Kconfig"
>> 3202
>> 3203 source "fs/Kconfig"
>> 3204
>> 3205 source "arch/mips/Kconfig.debug"
2438 3206
2439 endmenu # "CPU Power Management" !! 3207 source "security/Kconfig"
2440 3208
2441 source "drivers/acpi/Kconfig" !! 3209 source "crypto/Kconfig"
2442 3210
2443 source "arch/arm64/kvm/Kconfig" !! 3211 source "lib/Kconfig"
2444 3212
>> 3213 source "arch/mips/kvm/Kconfig"
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