1 # SPDX-License-Identifier: GPL-2.0-only !! 1 config MIPS
2 config ARM64 !! 2 bool
3 def_bool y !! 3 default y
4 select ACPI_APMT if ACPI <<
5 select ACPI_CCA_REQUIRED if ACPI <<
6 select ACPI_GENERIC_GSI if ACPI <<
7 select ACPI_GTDT if ACPI <<
8 select ACPI_HOTPLUG_CPU if ACPI_PROCES <<
9 select ACPI_IORT if ACPI <<
10 select ACPI_REDUCED_HARDWARE_ONLY if A <<
11 select ACPI_MCFG if (ACPI && PCI) <<
12 select ACPI_SPCR_TABLE if ACPI <<
13 select ACPI_PPTT if ACPI <<
14 select ARCH_HAS_DEBUG_WX <<
15 select ARCH_BINFMT_ELF_EXTRA_PHDRS <<
16 select ARCH_BINFMT_ELF_STATE 4 select ARCH_BINFMT_ELF_STATE
17 select ARCH_CORRECT_STACKTRACE_ON_KRET !! 5 select ARCH_CLOCKSOURCE_DATA
18 select ARCH_ENABLE_HUGEPAGE_MIGRATION !! 6 select ARCH_DISCARD_MEMBLOCK
19 select ARCH_ENABLE_MEMORY_HOTPLUG !! 7 select ARCH_HAS_ELF_RANDOMIZE
20 select ARCH_ENABLE_MEMORY_HOTREMOVE <<
21 select ARCH_ENABLE_SPLIT_PMD_PTLOCK if <<
22 select ARCH_ENABLE_THP_MIGRATION if TR <<
23 select ARCH_HAS_CACHE_LINE_SIZE <<
24 select ARCH_HAS_CURRENT_STACK_POINTER <<
25 select ARCH_HAS_DEBUG_VIRTUAL <<
26 select ARCH_HAS_DEBUG_VM_PGTABLE <<
27 select ARCH_HAS_DMA_OPS if XEN <<
28 select ARCH_HAS_DMA_PREP_COHERENT <<
29 select ARCH_HAS_ACPI_TABLE_UPGRADE if <<
30 select ARCH_HAS_FAST_MULTIPLIER <<
31 select ARCH_HAS_FORTIFY_SOURCE <<
32 select ARCH_HAS_GCOV_PROFILE_ALL <<
33 select ARCH_HAS_GIGANTIC_PAGE <<
34 select ARCH_HAS_KCOV <<
35 select ARCH_HAS_KERNEL_FPU_SUPPORT if <<
36 select ARCH_HAS_KEEPINITRD <<
37 select ARCH_HAS_MEMBARRIER_SYNC_CORE <<
38 select ARCH_HAS_MEM_ENCRYPT <<
39 select ARCH_HAS_NMI_SAFE_THIS_CPU_OPS <<
40 select ARCH_HAS_NON_OVERLAPPING_ADDRES <<
41 select ARCH_HAS_PTE_DEVMAP <<
42 select ARCH_HAS_PTE_SPECIAL <<
43 select ARCH_HAS_HW_PTE_YOUNG <<
44 select ARCH_HAS_SETUP_DMA_OPS <<
45 select ARCH_HAS_SET_DIRECT_MAP <<
46 select ARCH_HAS_SET_MEMORY <<
47 select ARCH_STACKWALK <<
48 select ARCH_HAS_STRICT_KERNEL_RWX <<
49 select ARCH_HAS_STRICT_MODULE_RWX <<
50 select ARCH_HAS_SYNC_DMA_FOR_DEVICE <<
51 select ARCH_HAS_SYNC_DMA_FOR_CPU <<
52 select ARCH_HAS_SYSCALL_WRAPPER <<
53 select ARCH_HAS_TICK_BROADCAST if GENE 8 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
54 select ARCH_HAS_ZONE_DMA_SET if EXPERT !! 9 select ARCH_MIGHT_HAVE_PC_PARPORT
55 select ARCH_HAVE_ELF_PROT !! 10 select ARCH_MIGHT_HAVE_PC_SERIO
56 select ARCH_HAVE_NMI_SAFE_CMPXCHG !! 11 select ARCH_SUPPORTS_UPROBES
57 select ARCH_HAVE_TRACE_MMIO_ACCESS !! 12 select ARCH_USE_BUILTIN_BSWAP
58 select ARCH_INLINE_READ_LOCK if !PREEM !! 13 select ARCH_USE_CMPXCHG_LOCKREF if 64BIT
59 select ARCH_INLINE_READ_LOCK_BH if !PR <<
60 select ARCH_INLINE_READ_LOCK_IRQ if !P <<
61 select ARCH_INLINE_READ_LOCK_IRQSAVE i <<
62 select ARCH_INLINE_READ_UNLOCK if !PRE <<
63 select ARCH_INLINE_READ_UNLOCK_BH if ! <<
64 select ARCH_INLINE_READ_UNLOCK_IRQ if <<
65 select ARCH_INLINE_READ_UNLOCK_IRQREST <<
66 select ARCH_INLINE_WRITE_LOCK if !PREE <<
67 select ARCH_INLINE_WRITE_LOCK_BH if !P <<
68 select ARCH_INLINE_WRITE_LOCK_IRQ if ! <<
69 select ARCH_INLINE_WRITE_LOCK_IRQSAVE <<
70 select ARCH_INLINE_WRITE_UNLOCK if !PR <<
71 select ARCH_INLINE_WRITE_UNLOCK_BH if <<
72 select ARCH_INLINE_WRITE_UNLOCK_IRQ if <<
73 select ARCH_INLINE_WRITE_UNLOCK_IRQRES <<
74 select ARCH_INLINE_SPIN_TRYLOCK if !PR <<
75 select ARCH_INLINE_SPIN_TRYLOCK_BH if <<
76 select ARCH_INLINE_SPIN_LOCK if !PREEM <<
77 select ARCH_INLINE_SPIN_LOCK_BH if !PR <<
78 select ARCH_INLINE_SPIN_LOCK_IRQ if !P <<
79 select ARCH_INLINE_SPIN_LOCK_IRQSAVE i <<
80 select ARCH_INLINE_SPIN_UNLOCK if !PRE <<
81 select ARCH_INLINE_SPIN_UNLOCK_BH if ! <<
82 select ARCH_INLINE_SPIN_UNLOCK_IRQ if <<
83 select ARCH_INLINE_SPIN_UNLOCK_IRQREST <<
84 select ARCH_KEEP_MEMBLOCK <<
85 select ARCH_MHP_MEMMAP_ON_MEMORY_ENABL <<
86 select ARCH_USE_CMPXCHG_LOCKREF <<
87 select ARCH_USE_GNU_PROPERTY <<
88 select ARCH_USE_MEMTEST <<
89 select ARCH_USE_QUEUED_RWLOCKS 14 select ARCH_USE_QUEUED_RWLOCKS
90 select ARCH_USE_QUEUED_SPINLOCKS 15 select ARCH_USE_QUEUED_SPINLOCKS
91 select ARCH_USE_SYM_ANNOTATIONS !! 16 select ARCH_WANT_IPC_PARSE_VERSION
92 select ARCH_SUPPORTS_DEBUG_PAGEALLOC !! 17 select BUILDTIME_EXTABLE_SORT
93 select ARCH_SUPPORTS_HUGETLBFS <<
94 select ARCH_SUPPORTS_MEMORY_FAILURE <<
95 select ARCH_SUPPORTS_SHADOW_CALL_STACK <<
96 select ARCH_SUPPORTS_LTO_CLANG if CPU_ <<
97 select ARCH_SUPPORTS_LTO_CLANG_THIN <<
98 select ARCH_SUPPORTS_CFI_CLANG <<
99 select ARCH_SUPPORTS_ATOMIC_RMW <<
100 select ARCH_SUPPORTS_INT128 if CC_HAS_ <<
101 select ARCH_SUPPORTS_NUMA_BALANCING <<
102 select ARCH_SUPPORTS_PAGE_TABLE_CHECK <<
103 select ARCH_SUPPORTS_PER_VMA_LOCK <<
104 select ARCH_SUPPORTS_HUGE_PFNMAP if TR <<
105 select ARCH_SUPPORTS_RT <<
106 select ARCH_WANT_BATCHED_UNMAP_TLB_FLU <<
107 select ARCH_WANT_COMPAT_IPC_PARSE_VERS <<
108 select ARCH_WANT_DEFAULT_BPF_JIT <<
109 select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_ <<
110 select ARCH_WANT_FRAME_POINTERS <<
111 select ARCH_WANT_HUGE_PMD_SHARE if ARM <<
112 select ARCH_WANT_LD_ORPHAN_WARN <<
113 select ARCH_WANTS_EXECMEM_LATE if EXEC <<
114 select ARCH_WANTS_NO_INSTR <<
115 select ARCH_WANTS_THP_SWAP if ARM64_4K <<
116 select ARCH_HAS_UBSAN <<
117 select ARM_AMBA <<
118 select ARM_ARCH_TIMER <<
119 select ARM_GIC <<
120 select AUDIT_ARCH_COMPAT_GENERIC <<
121 select ARM_GIC_V2M if PCI <<
122 select ARM_GIC_V3 <<
123 select ARM_GIC_V3_ITS if PCI <<
124 select ARM_PSCI_FW <<
125 select BUILDTIME_TABLE_SORT <<
126 select CLONE_BACKWARDS 18 select CLONE_BACKWARDS
127 select COMMON_CLK !! 19 select CPU_PM if CPU_IDLE
128 select CPU_PM if (SUSPEND || CPU_IDLE) !! 20 select GENERIC_ATOMIC64 if !64BIT
129 select CPUMASK_OFFSTACK if NR_CPUS > 2 !! 21 select GENERIC_CLOCKEVENTS
130 select CRC32 !! 22 select GENERIC_CMOS_UPDATE
131 select DCACHE_WORD_ACCESS <<
132 select DYNAMIC_FTRACE if FUNCTION_TRAC <<
133 select DMA_BOUNCE_UNALIGNED_KMALLOC <<
134 select DMA_DIRECT_REMAP <<
135 select EDAC_SUPPORT <<
136 select FRAME_POINTER <<
137 select FUNCTION_ALIGNMENT_4B <<
138 select FUNCTION_ALIGNMENT_8B if DYNAMI <<
139 select GENERIC_ALLOCATOR <<
140 select GENERIC_ARCH_TOPOLOGY <<
141 select GENERIC_CLOCKEVENTS_BROADCAST <<
142 select GENERIC_CPU_AUTOPROBE 23 select GENERIC_CPU_AUTOPROBE
143 select GENERIC_CPU_DEVICES <<
144 select GENERIC_CPU_VULNERABILITIES <<
145 select GENERIC_EARLY_IOREMAP <<
146 select GENERIC_IDLE_POLL_SETUP <<
147 select GENERIC_IOREMAP <<
148 select GENERIC_IRQ_IPI <<
149 select GENERIC_IRQ_PROBE 24 select GENERIC_IRQ_PROBE
150 select GENERIC_IRQ_SHOW 25 select GENERIC_IRQ_SHOW
151 select GENERIC_IRQ_SHOW_LEVEL <<
152 select GENERIC_LIB_DEVMEM_IS_ALLOWED <<
153 select GENERIC_PCI_IOMAP 26 select GENERIC_PCI_IOMAP
154 select GENERIC_PTDUMP !! 27 select GENERIC_SCHED_CLOCK if !CAVIUM_OCTEON_SOC
155 select GENERIC_SCHED_CLOCK <<
156 select GENERIC_SMP_IDLE_THREAD 28 select GENERIC_SMP_IDLE_THREAD
157 select GENERIC_TIME_VSYSCALL 29 select GENERIC_TIME_VSYSCALL
158 select GENERIC_GETTIMEOFDAY !! 30 select HANDLE_DOMAIN_IRQ
159 select GENERIC_VDSO_TIME_NS <<
160 select HARDIRQS_SW_RESEND <<
161 select HAS_IOPORT <<
162 select HAVE_MOVE_PMD <<
163 select HAVE_MOVE_PUD <<
164 select HAVE_PCI <<
165 select HAVE_ACPI_APEI if (ACPI && EFI) <<
166 select HAVE_ALIGNED_STRUCT_PAGE <<
167 select HAVE_ARCH_AUDITSYSCALL <<
168 select HAVE_ARCH_BITREVERSE <<
169 select HAVE_ARCH_COMPILER_H <<
170 select HAVE_ARCH_HUGE_VMALLOC <<
171 select HAVE_ARCH_HUGE_VMAP <<
172 select HAVE_ARCH_JUMP_LABEL 31 select HAVE_ARCH_JUMP_LABEL
173 select HAVE_ARCH_JUMP_LABEL_RELATIVE <<
174 select HAVE_ARCH_KASAN <<
175 select HAVE_ARCH_KASAN_VMALLOC <<
176 select HAVE_ARCH_KASAN_SW_TAGS <<
177 select HAVE_ARCH_KASAN_HW_TAGS if ARM6 <<
178 # Some instrumentation may be unsound, <<
179 select HAVE_ARCH_KCSAN if EXPERT <<
180 select HAVE_ARCH_KFENCE <<
181 select HAVE_ARCH_KGDB 32 select HAVE_ARCH_KGDB
182 select HAVE_ARCH_MMAP_RND_BITS !! 33 select HAVE_ARCH_MMAP_RND_BITS if MMU
183 select HAVE_ARCH_MMAP_RND_COMPAT_BITS !! 34 select HAVE_ARCH_MMAP_RND_COMPAT_BITS if MMU && COMPAT
184 select HAVE_ARCH_PREL32_RELOCATIONS <<
185 select HAVE_ARCH_RANDOMIZE_KSTACK_OFFS <<
186 select HAVE_ARCH_SECCOMP_FILTER 35 select HAVE_ARCH_SECCOMP_FILTER
187 select HAVE_ARCH_STACKLEAK <<
188 select HAVE_ARCH_THREAD_STRUCT_WHITELI <<
189 select HAVE_ARCH_TRACEHOOK 36 select HAVE_ARCH_TRACEHOOK
190 select HAVE_ARCH_TRANSPARENT_HUGEPAGE !! 37 select HAVE_ARCH_TRANSPARENT_HUGEPAGE if CPU_SUPPORTS_HUGEPAGES && 64BIT
191 select HAVE_ARCH_VMAP_STACK !! 38 select HAVE_CBPF_JIT if (!64BIT && !CPU_MICROMIPS)
192 select HAVE_ARM_SMCCC !! 39 select HAVE_EBPF_JIT if (64BIT && !CPU_MICROMIPS)
193 select HAVE_ASM_MODVERSIONS !! 40 select HAVE_CC_STACKPROTECTOR
194 select HAVE_EBPF_JIT !! 41 select HAVE_CONTEXT_TRACKING
>> 42 select HAVE_COPY_THREAD_TLS
195 select HAVE_C_RECORDMCOUNT 43 select HAVE_C_RECORDMCOUNT
196 select HAVE_CMPXCHG_DOUBLE <<
197 select HAVE_CMPXCHG_LOCAL <<
198 select HAVE_CONTEXT_TRACKING_USER <<
199 select HAVE_DEBUG_KMEMLEAK 44 select HAVE_DEBUG_KMEMLEAK
>> 45 select HAVE_DEBUG_STACKOVERFLOW
>> 46 select HAVE_DMA_API_DEBUG
200 select HAVE_DMA_CONTIGUOUS 47 select HAVE_DMA_CONTIGUOUS
201 select HAVE_DYNAMIC_FTRACE 48 select HAVE_DYNAMIC_FTRACE
202 select HAVE_DYNAMIC_FTRACE_WITH_ARGS \ !! 49 select HAVE_EXIT_THREAD
203 if (GCC_SUPPORTS_DYNAMIC_FTRAC <<
204 CLANG_SUPPORTS_DYNAMIC_FTR <<
205 select HAVE_DYNAMIC_FTRACE_WITH_DIRECT <<
206 if DYNAMIC_FTRACE_WITH_ARGS && <<
207 select HAVE_DYNAMIC_FTRACE_WITH_CALL_O <<
208 if (DYNAMIC_FTRACE_WITH_ARGS & <<
209 (CC_IS_CLANG || !CC_OPTIMI <<
210 select FTRACE_MCOUNT_USE_PATCHABLE_FUN <<
211 if DYNAMIC_FTRACE_WITH_ARGS <<
212 select HAVE_SAMPLE_FTRACE_DIRECT <<
213 select HAVE_SAMPLE_FTRACE_DIRECT_MULTI <<
214 select HAVE_EFFICIENT_UNALIGNED_ACCESS <<
215 select HAVE_GUP_FAST <<
216 select HAVE_FTRACE_MCOUNT_RECORD 50 select HAVE_FTRACE_MCOUNT_RECORD
217 select HAVE_FUNCTION_TRACER <<
218 select HAVE_FUNCTION_ERROR_INJECTION <<
219 select HAVE_FUNCTION_GRAPH_TRACER 51 select HAVE_FUNCTION_GRAPH_TRACER
220 select HAVE_FUNCTION_GRAPH_RETVAL !! 52 select HAVE_FUNCTION_TRACER
221 select HAVE_GCC_PLUGINS !! 53 select HAVE_GENERIC_DMA_COHERENT
222 select HAVE_HARDLOCKUP_DETECTOR_PERF i !! 54 select HAVE_IDE
223 HW_PERF_EVENTS && HAVE_PERF_EV !! 55 select HAVE_IRQ_EXIT_ON_IRQ_STACK
224 select HAVE_HW_BREAKPOINT if PERF_EVEN <<
225 select HAVE_IOREMAP_PROT <<
226 select HAVE_IRQ_TIME_ACCOUNTING 56 select HAVE_IRQ_TIME_ACCOUNTING
>> 57 select HAVE_KPROBES
>> 58 select HAVE_KRETPROBES
>> 59 select HAVE_MEMBLOCK
>> 60 select HAVE_MEMBLOCK_NODE_MAP
227 select HAVE_MOD_ARCH_SPECIFIC 61 select HAVE_MOD_ARCH_SPECIFIC
228 select HAVE_NMI 62 select HAVE_NMI
>> 63 select HAVE_OPROFILE
229 select HAVE_PERF_EVENTS 64 select HAVE_PERF_EVENTS
230 select HAVE_PERF_EVENTS_NMI if ARM64_P <<
231 select HAVE_PERF_REGS <<
232 select HAVE_PERF_USER_STACK_DUMP <<
233 select HAVE_PREEMPT_DYNAMIC_KEY <<
234 select HAVE_REGS_AND_STACK_ACCESS_API 65 select HAVE_REGS_AND_STACK_ACCESS_API
235 select HAVE_POSIX_CPU_TIMERS_TASK_WORK <<
236 select HAVE_FUNCTION_ARG_ACCESS_API <<
237 select MMU_GATHER_RCU_TABLE_FREE <<
238 select HAVE_RSEQ <<
239 select HAVE_RUST if RUSTC_SUPPORTS_ARM <<
240 select HAVE_STACKPROTECTOR <<
241 select HAVE_SYSCALL_TRACEPOINTS 66 select HAVE_SYSCALL_TRACEPOINTS
242 select HAVE_KPROBES !! 67 select HAVE_VIRT_CPU_ACCOUNTING_GEN
243 select HAVE_KRETPROBES <<
244 select HAVE_GENERIC_VDSO <<
245 select HOTPLUG_CORE_SYNC_DEAD if HOTPL <<
246 select IRQ_DOMAIN <<
247 select IRQ_FORCED_THREADING 68 select IRQ_FORCED_THREADING
248 select KASAN_VMALLOC if KASAN !! 69 select MODULES_USE_ELF_RELA if MODULES && 64BIT
249 select LOCK_MM_AND_FIND_VMA !! 70 select MODULES_USE_ELF_REL if MODULES
250 select MODULES_USE_ELF_RELA !! 71 select PERF_USE_VMALLOC
251 select NEED_DMA_MAP_STATE !! 72 select RTC_LIB if !MACH_LOONGSON64
252 select NEED_SG_DMA_LENGTH <<
253 select OF <<
254 select OF_EARLY_FLATTREE <<
255 select PCI_DOMAINS_GENERIC if PCI <<
256 select PCI_ECAM if (ACPI && PCI) <<
257 select PCI_SYSCALL if PCI <<
258 select POWER_RESET <<
259 select POWER_SUPPLY <<
260 select SPARSE_IRQ <<
261 select SWIOTLB <<
262 select SYSCTL_EXCEPTION_TRACE 73 select SYSCTL_EXCEPTION_TRACE
263 select THREAD_INFO_IN_TASK !! 74 select VIRT_TO_BUS
264 select HAVE_ARCH_USERFAULTFD_MINOR if <<
265 select HAVE_ARCH_USERFAULTFD_WP if USE <<
266 select TRACE_IRQFLAGS_SUPPORT <<
267 select TRACE_IRQFLAGS_NMI_SUPPORT <<
268 select HAVE_SOFTIRQ_ON_OWN_STACK <<
269 select USER_STACKTRACE_SUPPORT <<
270 select VDSO_GETRANDOM <<
271 help <<
272 ARM 64-bit (AArch64) Linux support. <<
273 <<
274 config RUSTC_SUPPORTS_ARM64 <<
275 def_bool y <<
276 depends on CPU_LITTLE_ENDIAN <<
277 # Shadow call stack is only supported <<
278 # <<
279 # When using the UNWIND_PATCH_PAC_INTO <<
280 # required due to use of the -Zfixed-x <<
281 # <<
282 # Otherwise, rustc version 1.82+ is re <<
283 # -Zsanitizer=shadow-call-stack flag. <<
284 depends on !SHADOW_CALL_STACK || RUSTC <<
285 <<
286 config CLANG_SUPPORTS_DYNAMIC_FTRACE_WITH_ARGS <<
287 def_bool CC_IS_CLANG <<
288 # https://github.com/ClangBuiltLinux/l <<
289 depends on AS_IS_GNU || (AS_IS_LLVM && <<
290 <<
291 config GCC_SUPPORTS_DYNAMIC_FTRACE_WITH_ARGS <<
292 def_bool CC_IS_GCC <<
293 depends on $(cc-option,-fpatchable-fun <<
294 75
295 config 64BIT !! 76 menu "Machine selection"
296 def_bool y <<
297 <<
298 config MMU <<
299 def_bool y <<
300 77
301 config ARM64_CONT_PTE_SHIFT !! 78 choice
302 int !! 79 prompt "System type"
303 default 5 if PAGE_SIZE_64KB !! 80 default SGI_IP22
304 default 7 if PAGE_SIZE_16KB <<
305 default 4 <<
306 <<
307 config ARM64_CONT_PMD_SHIFT <<
308 int <<
309 default 5 if PAGE_SIZE_64KB <<
310 default 5 if PAGE_SIZE_16KB <<
311 default 4 <<
312 81
313 config ARCH_MMAP_RND_BITS_MIN !! 82 config MIPS_GENERIC
314 default 14 if PAGE_SIZE_64KB !! 83 bool "Generic board-agnostic MIPS kernel"
315 default 16 if PAGE_SIZE_16KB !! 84 select BOOT_RAW
316 default 18 !! 85 select BUILTIN_DTB
>> 86 select CEVT_R4K
>> 87 select CLKSRC_MIPS_GIC
>> 88 select COMMON_CLK
>> 89 select CPU_MIPSR2_IRQ_VI
>> 90 select CPU_MIPSR2_IRQ_EI
>> 91 select CSRC_R4K
>> 92 select DMA_PERDEV_COHERENT
>> 93 select HW_HAS_PCI
>> 94 select IRQ_MIPS_CPU
>> 95 select LIBFDT
>> 96 select MIPS_CPU_SCACHE
>> 97 select MIPS_GIC
>> 98 select MIPS_L1_CACHE_SHIFT_7
>> 99 select NO_EXCEPT_FILL
>> 100 select PCI_DRIVERS_GENERIC
>> 101 select PINCTRL
>> 102 select SMP_UP if SMP
>> 103 select SWAP_IO_SPACE
>> 104 select SYS_HAS_CPU_MIPS32_R1
>> 105 select SYS_HAS_CPU_MIPS32_R2
>> 106 select SYS_HAS_CPU_MIPS32_R6
>> 107 select SYS_HAS_CPU_MIPS64_R1
>> 108 select SYS_HAS_CPU_MIPS64_R2
>> 109 select SYS_HAS_CPU_MIPS64_R6
>> 110 select SYS_SUPPORTS_32BIT_KERNEL
>> 111 select SYS_SUPPORTS_64BIT_KERNEL
>> 112 select SYS_SUPPORTS_BIG_ENDIAN
>> 113 select SYS_SUPPORTS_HIGHMEM
>> 114 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 115 select SYS_SUPPORTS_MICROMIPS
>> 116 select SYS_SUPPORTS_MIPS_CPS
>> 117 select SYS_SUPPORTS_MIPS16
>> 118 select SYS_SUPPORTS_MULTITHREADING
>> 119 select SYS_SUPPORTS_RELOCATABLE
>> 120 select SYS_SUPPORTS_SMARTMIPS
>> 121 select USB_EHCI_BIG_ENDIAN_DESC if BIG_ENDIAN
>> 122 select USB_EHCI_BIG_ENDIAN_MMIO if BIG_ENDIAN
>> 123 select USB_OHCI_BIG_ENDIAN_DESC if BIG_ENDIAN
>> 124 select USB_OHCI_BIG_ENDIAN_MMIO if BIG_ENDIAN
>> 125 select USB_UHCI_BIG_ENDIAN_DESC if BIG_ENDIAN
>> 126 select USB_UHCI_BIG_ENDIAN_MMIO if BIG_ENDIAN
>> 127 select USE_OF
>> 128 help
>> 129 Select this to build a kernel which aims to support multiple boards,
>> 130 generally using a flattened device tree passed from the bootloader
>> 131 using the boot protocol defined in the UHI (Unified Hosting
>> 132 Interface) specification.
>> 133
>> 134 config MIPS_ALCHEMY
>> 135 bool "Alchemy processor based machines"
>> 136 select ARCH_PHYS_ADDR_T_64BIT
>> 137 select CEVT_R4K
>> 138 select CSRC_R4K
>> 139 select IRQ_MIPS_CPU
>> 140 select DMA_MAYBE_COHERENT # Au1000,1500,1100 aren't, rest is
>> 141 select SYS_HAS_CPU_MIPS32_R1
>> 142 select SYS_SUPPORTS_32BIT_KERNEL
>> 143 select SYS_SUPPORTS_APM_EMULATION
>> 144 select GPIOLIB
>> 145 select SYS_SUPPORTS_ZBOOT
>> 146 select COMMON_CLK
317 147
318 # max bits determined by the following formula !! 148 config AR7
319 # VA_BITS - PAGE_SHIFT - 3 !! 149 bool "Texas Instruments AR7"
320 config ARCH_MMAP_RND_BITS_MAX !! 150 select BOOT_ELF32
321 default 19 if ARM64_VA_BITS=36 !! 151 select DMA_NONCOHERENT
322 default 24 if ARM64_VA_BITS=39 !! 152 select CEVT_R4K
323 default 27 if ARM64_VA_BITS=42 !! 153 select CSRC_R4K
324 default 30 if ARM64_VA_BITS=47 !! 154 select IRQ_MIPS_CPU
325 default 29 if ARM64_VA_BITS=48 && ARM6 !! 155 select NO_EXCEPT_FILL
326 default 31 if ARM64_VA_BITS=48 && ARM6 !! 156 select SWAP_IO_SPACE
327 default 33 if ARM64_VA_BITS=48 !! 157 select SYS_HAS_CPU_MIPS32_R1
328 default 14 if ARM64_64K_PAGES !! 158 select SYS_HAS_EARLY_PRINTK
329 default 16 if ARM64_16K_PAGES !! 159 select SYS_SUPPORTS_32BIT_KERNEL
330 default 18 !! 160 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 161 select SYS_SUPPORTS_MIPS16
>> 162 select SYS_SUPPORTS_ZBOOT_UART16550
>> 163 select GPIOLIB
>> 164 select VLYNQ
>> 165 select HAVE_CLK
>> 166 help
>> 167 Support for the Texas Instruments AR7 System-on-a-Chip
>> 168 family: TNETD7100, 7200 and 7300.
>> 169
>> 170 config ATH25
>> 171 bool "Atheros AR231x/AR531x SoC support"
>> 172 select CEVT_R4K
>> 173 select CSRC_R4K
>> 174 select DMA_NONCOHERENT
>> 175 select IRQ_MIPS_CPU
>> 176 select IRQ_DOMAIN
>> 177 select SYS_HAS_CPU_MIPS32_R1
>> 178 select SYS_SUPPORTS_BIG_ENDIAN
>> 179 select SYS_SUPPORTS_32BIT_KERNEL
>> 180 select SYS_HAS_EARLY_PRINTK
>> 181 help
>> 182 Support for Atheros AR231x and Atheros AR531x based boards
>> 183
>> 184 config ATH79
>> 185 bool "Atheros AR71XX/AR724X/AR913X based boards"
>> 186 select ARCH_HAS_RESET_CONTROLLER
>> 187 select BOOT_RAW
>> 188 select CEVT_R4K
>> 189 select CSRC_R4K
>> 190 select DMA_NONCOHERENT
>> 191 select GPIOLIB
>> 192 select HAVE_CLK
>> 193 select COMMON_CLK
>> 194 select CLKDEV_LOOKUP
>> 195 select IRQ_MIPS_CPU
>> 196 select MIPS_MACHINE
>> 197 select SYS_HAS_CPU_MIPS32_R2
>> 198 select SYS_HAS_EARLY_PRINTK
>> 199 select SYS_SUPPORTS_32BIT_KERNEL
>> 200 select SYS_SUPPORTS_BIG_ENDIAN
>> 201 select SYS_SUPPORTS_MIPS16
>> 202 select SYS_SUPPORTS_ZBOOT_UART_PROM
>> 203 select USE_OF
>> 204 help
>> 205 Support for the Atheros AR71XX/AR724X/AR913X SoCs.
>> 206
>> 207 config BMIPS_GENERIC
>> 208 bool "Broadcom Generic BMIPS kernel"
>> 209 select BOOT_RAW
>> 210 select NO_EXCEPT_FILL
>> 211 select USE_OF
>> 212 select CEVT_R4K
>> 213 select CSRC_R4K
>> 214 select SYNC_R4K
>> 215 select COMMON_CLK
>> 216 select BCM6345_L1_IRQ
>> 217 select BCM7038_L1_IRQ
>> 218 select BCM7120_L2_IRQ
>> 219 select BRCMSTB_L2_IRQ
>> 220 select IRQ_MIPS_CPU
>> 221 select DMA_NONCOHERENT
>> 222 select SYS_SUPPORTS_32BIT_KERNEL
>> 223 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 224 select SYS_SUPPORTS_BIG_ENDIAN
>> 225 select SYS_SUPPORTS_HIGHMEM
>> 226 select SYS_HAS_CPU_BMIPS32_3300
>> 227 select SYS_HAS_CPU_BMIPS4350
>> 228 select SYS_HAS_CPU_BMIPS4380
>> 229 select SYS_HAS_CPU_BMIPS5000
>> 230 select SWAP_IO_SPACE
>> 231 select USB_EHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
>> 232 select USB_EHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 233 select USB_OHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
>> 234 select USB_OHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 235 help
>> 236 Build a generic DT-based kernel image that boots on select
>> 237 BCM33xx cable modem chips, BCM63xx DSL chips, and BCM7xxx set-top
>> 238 box chips. Note that CONFIG_CPU_BIG_ENDIAN/CONFIG_CPU_LITTLE_ENDIAN
>> 239 must be set appropriately for your board.
>> 240
>> 241 config BCM47XX
>> 242 bool "Broadcom BCM47XX based boards"
>> 243 select BOOT_RAW
>> 244 select CEVT_R4K
>> 245 select CSRC_R4K
>> 246 select DMA_NONCOHERENT
>> 247 select HW_HAS_PCI
>> 248 select IRQ_MIPS_CPU
>> 249 select SYS_HAS_CPU_MIPS32_R1
>> 250 select NO_EXCEPT_FILL
>> 251 select SYS_SUPPORTS_32BIT_KERNEL
>> 252 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 253 select SYS_SUPPORTS_MIPS16
>> 254 select SYS_HAS_EARLY_PRINTK
>> 255 select USE_GENERIC_EARLY_PRINTK_8250
>> 256 select GPIOLIB
>> 257 select LEDS_GPIO_REGISTER
>> 258 select BCM47XX_NVRAM
>> 259 select BCM47XX_SPROM
>> 260 help
>> 261 Support for BCM47XX based boards
>> 262
>> 263 config BCM63XX
>> 264 bool "Broadcom BCM63XX based boards"
>> 265 select BOOT_RAW
>> 266 select CEVT_R4K
>> 267 select CSRC_R4K
>> 268 select SYNC_R4K
>> 269 select DMA_NONCOHERENT
>> 270 select IRQ_MIPS_CPU
>> 271 select SYS_SUPPORTS_32BIT_KERNEL
>> 272 select SYS_SUPPORTS_BIG_ENDIAN
>> 273 select SYS_HAS_EARLY_PRINTK
>> 274 select SWAP_IO_SPACE
>> 275 select GPIOLIB
>> 276 select HAVE_CLK
>> 277 select MIPS_L1_CACHE_SHIFT_4
>> 278 help
>> 279 Support for BCM63XX based boards
>> 280
>> 281 config MIPS_COBALT
>> 282 bool "Cobalt Server"
>> 283 select CEVT_R4K
>> 284 select CSRC_R4K
>> 285 select CEVT_GT641XX
>> 286 select DMA_NONCOHERENT
>> 287 select HW_HAS_PCI
>> 288 select I8253
>> 289 select I8259
>> 290 select IRQ_MIPS_CPU
>> 291 select IRQ_GT641XX
>> 292 select PCI_GT64XXX_PCI0
>> 293 select PCI
>> 294 select SYS_HAS_CPU_NEVADA
>> 295 select SYS_HAS_EARLY_PRINTK
>> 296 select SYS_SUPPORTS_32BIT_KERNEL
>> 297 select SYS_SUPPORTS_64BIT_KERNEL
>> 298 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 299 select USE_GENERIC_EARLY_PRINTK_8250
>> 300
>> 301 config MACH_DECSTATION
>> 302 bool "DECstations"
>> 303 select BOOT_ELF32
>> 304 select CEVT_DS1287
>> 305 select CEVT_R4K if CPU_R4X00
>> 306 select CSRC_IOASIC
>> 307 select CSRC_R4K if CPU_R4X00
>> 308 select CPU_DADDI_WORKAROUNDS if 64BIT
>> 309 select CPU_R4000_WORKAROUNDS if 64BIT
>> 310 select CPU_R4400_WORKAROUNDS if 64BIT
>> 311 select DMA_NONCOHERENT
>> 312 select NO_IOPORT_MAP
>> 313 select IRQ_MIPS_CPU
>> 314 select SYS_HAS_CPU_R3000
>> 315 select SYS_HAS_CPU_R4X00
>> 316 select SYS_SUPPORTS_32BIT_KERNEL
>> 317 select SYS_SUPPORTS_64BIT_KERNEL
>> 318 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 319 select SYS_SUPPORTS_128HZ
>> 320 select SYS_SUPPORTS_256HZ
>> 321 select SYS_SUPPORTS_1024HZ
>> 322 select MIPS_L1_CACHE_SHIFT_4
>> 323 help
>> 324 This enables support for DEC's MIPS based workstations. For details
>> 325 see the Linux/MIPS FAQ on <http://www.linux-mips.org/> and the
>> 326 DECstation porting pages on <http://decstation.unix-ag.org/>.
>> 327
>> 328 If you have one of the following DECstation Models you definitely
>> 329 want to choose R4xx0 for the CPU Type:
>> 330
>> 331 DECstation 5000/50
>> 332 DECstation 5000/150
>> 333 DECstation 5000/260
>> 334 DECsystem 5900/260
>> 335
>> 336 otherwise choose R3000.
>> 337
>> 338 config MACH_JAZZ
>> 339 bool "Jazz family of machines"
>> 340 select FW_ARC
>> 341 select FW_ARC32
>> 342 select ARCH_MAY_HAVE_PC_FDC
>> 343 select CEVT_R4K
>> 344 select CSRC_R4K
>> 345 select DEFAULT_SGI_PARTITION if CPU_BIG_ENDIAN
>> 346 select GENERIC_ISA_DMA
>> 347 select HAVE_PCSPKR_PLATFORM
>> 348 select IRQ_MIPS_CPU
>> 349 select I8253
>> 350 select I8259
>> 351 select ISA
>> 352 select SYS_HAS_CPU_R4X00
>> 353 select SYS_SUPPORTS_32BIT_KERNEL
>> 354 select SYS_SUPPORTS_64BIT_KERNEL
>> 355 select SYS_SUPPORTS_100HZ
>> 356 help
>> 357 This a family of machines based on the MIPS R4030 chipset which was
>> 358 used by several vendors to build RISC/os and Windows NT workstations.
>> 359 Members include the Acer PICA, MIPS Magnum 4000, MIPS Millennium and
>> 360 Olivetti M700-10 workstations.
>> 361
>> 362 config MACH_INGENIC
>> 363 bool "Ingenic SoC based machines"
>> 364 select SYS_SUPPORTS_32BIT_KERNEL
>> 365 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 366 select SYS_SUPPORTS_ZBOOT_UART16550
>> 367 select DMA_NONCOHERENT
>> 368 select IRQ_MIPS_CPU
>> 369 select PINCTRL
>> 370 select GPIOLIB
>> 371 select COMMON_CLK
>> 372 select GENERIC_IRQ_CHIP
>> 373 select BUILTIN_DTB
>> 374 select USE_OF
>> 375 select LIBFDT
331 376
332 config ARCH_MMAP_RND_COMPAT_BITS_MIN !! 377 config LANTIQ
333 default 7 if ARM64_64K_PAGES !! 378 bool "Lantiq based platforms"
334 default 9 if ARM64_16K_PAGES !! 379 select DMA_NONCOHERENT
335 default 11 !! 380 select IRQ_MIPS_CPU
>> 381 select CEVT_R4K
>> 382 select CSRC_R4K
>> 383 select SYS_HAS_CPU_MIPS32_R1
>> 384 select SYS_HAS_CPU_MIPS32_R2
>> 385 select SYS_SUPPORTS_BIG_ENDIAN
>> 386 select SYS_SUPPORTS_32BIT_KERNEL
>> 387 select SYS_SUPPORTS_MIPS16
>> 388 select SYS_SUPPORTS_MULTITHREADING
>> 389 select SYS_HAS_EARLY_PRINTK
>> 390 select GPIOLIB
>> 391 select SWAP_IO_SPACE
>> 392 select BOOT_RAW
>> 393 select CLKDEV_LOOKUP
>> 394 select USE_OF
>> 395 select PINCTRL
>> 396 select PINCTRL_LANTIQ
>> 397 select ARCH_HAS_RESET_CONTROLLER
>> 398 select RESET_CONTROLLER
>> 399
>> 400 config LASAT
>> 401 bool "LASAT Networks platforms"
>> 402 select CEVT_R4K
>> 403 select CRC32
>> 404 select CSRC_R4K
>> 405 select DMA_NONCOHERENT
>> 406 select SYS_HAS_EARLY_PRINTK
>> 407 select HW_HAS_PCI
>> 408 select IRQ_MIPS_CPU
>> 409 select PCI_GT64XXX_PCI0
>> 410 select MIPS_NILE4
>> 411 select R5000_CPU_SCACHE
>> 412 select SYS_HAS_CPU_R5000
>> 413 select SYS_SUPPORTS_32BIT_KERNEL
>> 414 select SYS_SUPPORTS_64BIT_KERNEL if BROKEN
>> 415 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 416
>> 417 config MACH_LOONGSON32
>> 418 bool "Loongson-1 family of machines"
>> 419 select SYS_SUPPORTS_ZBOOT
>> 420 help
>> 421 This enables support for the Loongson-1 family of machines.
>> 422
>> 423 Loongson-1 is a family of 32-bit MIPS-compatible SoCs developed by
>> 424 the Institute of Computing Technology (ICT), Chinese Academy of
>> 425 Sciences (CAS).
>> 426
>> 427 config MACH_LOONGSON64
>> 428 bool "Loongson-2/3 family of machines"
>> 429 select SYS_SUPPORTS_ZBOOT
>> 430 help
>> 431 This enables the support of Loongson-2/3 family of machines.
>> 432
>> 433 Loongson-2 is a family of single-core CPUs and Loongson-3 is a
>> 434 family of multi-core CPUs. They are both 64-bit general-purpose
>> 435 MIPS-compatible CPUs. Loongson-2/3 are developed by the Institute
>> 436 of Computing Technology (ICT), Chinese Academy of Sciences (CAS)
>> 437 in the People's Republic of China. The chief architect is Professor
>> 438 Weiwu Hu.
>> 439
>> 440 config MACH_PISTACHIO
>> 441 bool "IMG Pistachio SoC based boards"
>> 442 select BOOT_ELF32
>> 443 select BOOT_RAW
>> 444 select CEVT_R4K
>> 445 select CLKSRC_MIPS_GIC
>> 446 select COMMON_CLK
>> 447 select CSRC_R4K
>> 448 select DMA_NONCOHERENT
>> 449 select GPIOLIB
>> 450 select IRQ_MIPS_CPU
>> 451 select LIBFDT
>> 452 select MFD_SYSCON
>> 453 select MIPS_CPU_SCACHE
>> 454 select MIPS_GIC
>> 455 select PINCTRL
>> 456 select REGULATOR
>> 457 select SYS_HAS_CPU_MIPS32_R2
>> 458 select SYS_SUPPORTS_32BIT_KERNEL
>> 459 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 460 select SYS_SUPPORTS_MIPS_CPS
>> 461 select SYS_SUPPORTS_MULTITHREADING
>> 462 select SYS_SUPPORTS_RELOCATABLE
>> 463 select SYS_SUPPORTS_ZBOOT
>> 464 select SYS_HAS_EARLY_PRINTK
>> 465 select USE_GENERIC_EARLY_PRINTK_8250
>> 466 select USE_OF
>> 467 help
>> 468 This enables support for the IMG Pistachio SoC platform.
>> 469
>> 470 config MACH_XILFPGA
>> 471 bool "MIPSfpga Xilinx based boards"
>> 472 select BOOT_ELF32
>> 473 select BOOT_RAW
>> 474 select BUILTIN_DTB
>> 475 select CEVT_R4K
>> 476 select COMMON_CLK
>> 477 select CSRC_R4K
>> 478 select GPIOLIB
>> 479 select IRQ_MIPS_CPU
>> 480 select LIBFDT
>> 481 select MIPS_CPU_SCACHE
>> 482 select SYS_HAS_EARLY_PRINTK
>> 483 select SYS_HAS_CPU_MIPS32_R2
>> 484 select SYS_SUPPORTS_32BIT_KERNEL
>> 485 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 486 select SYS_SUPPORTS_ZBOOT_UART16550
>> 487 select USE_OF
>> 488 select USE_GENERIC_EARLY_PRINTK_8250
>> 489 select XILINX_INTC
>> 490 help
>> 491 This enables support for the IMG University Program MIPSfpga platform.
>> 492
>> 493 config MIPS_MALTA
>> 494 bool "MIPS Malta board"
>> 495 select ARCH_MAY_HAVE_PC_FDC
>> 496 select BOOT_ELF32
>> 497 select BOOT_RAW
>> 498 select BUILTIN_DTB
>> 499 select CEVT_R4K
>> 500 select CSRC_R4K
>> 501 select CLKSRC_MIPS_GIC
>> 502 select COMMON_CLK
>> 503 select DMA_MAYBE_COHERENT
>> 504 select GENERIC_ISA_DMA
>> 505 select HAVE_PCSPKR_PLATFORM
>> 506 select IRQ_MIPS_CPU
>> 507 select MIPS_GIC
>> 508 select HW_HAS_PCI
>> 509 select I8253
>> 510 select I8259
>> 511 select MIPS_BONITO64
>> 512 select MIPS_CPU_SCACHE
>> 513 select MIPS_L1_CACHE_SHIFT_6
>> 514 select PCI_GT64XXX_PCI0
>> 515 select MIPS_MSC
>> 516 select SMP_UP if SMP
>> 517 select SWAP_IO_SPACE
>> 518 select SYS_HAS_CPU_MIPS32_R1
>> 519 select SYS_HAS_CPU_MIPS32_R2
>> 520 select SYS_HAS_CPU_MIPS32_R3_5
>> 521 select SYS_HAS_CPU_MIPS32_R5
>> 522 select SYS_HAS_CPU_MIPS32_R6
>> 523 select SYS_HAS_CPU_MIPS64_R1
>> 524 select SYS_HAS_CPU_MIPS64_R2
>> 525 select SYS_HAS_CPU_MIPS64_R6
>> 526 select SYS_HAS_CPU_NEVADA
>> 527 select SYS_HAS_CPU_RM7000
>> 528 select SYS_SUPPORTS_32BIT_KERNEL
>> 529 select SYS_SUPPORTS_64BIT_KERNEL
>> 530 select SYS_SUPPORTS_BIG_ENDIAN
>> 531 select SYS_SUPPORTS_HIGHMEM
>> 532 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 533 select SYS_SUPPORTS_MICROMIPS
>> 534 select SYS_SUPPORTS_MIPS_CMP
>> 535 select SYS_SUPPORTS_MIPS_CPS
>> 536 select SYS_SUPPORTS_MIPS16
>> 537 select SYS_SUPPORTS_MULTITHREADING
>> 538 select SYS_SUPPORTS_SMARTMIPS
>> 539 select SYS_SUPPORTS_ZBOOT
>> 540 select SYS_SUPPORTS_RELOCATABLE
>> 541 select USE_OF
>> 542 select LIBFDT
>> 543 select ZONE_DMA32 if 64BIT
>> 544 select BUILTIN_DTB
>> 545 select LIBFDT
>> 546 help
>> 547 This enables support for the MIPS Technologies Malta evaluation
>> 548 board.
336 549
337 config ARCH_MMAP_RND_COMPAT_BITS_MAX !! 550 config MACH_PIC32
338 default 16 !! 551 bool "Microchip PIC32 Family"
>> 552 help
>> 553 This enables support for the Microchip PIC32 family of platforms.
339 554
340 config NO_IOPORT_MAP !! 555 Microchip PIC32 is a family of general-purpose 32 bit MIPS core
341 def_bool y if !PCI !! 556 microcontrollers.
>> 557
>> 558 config NEC_MARKEINS
>> 559 bool "NEC EMMA2RH Mark-eins board"
>> 560 select SOC_EMMA2RH
>> 561 select HW_HAS_PCI
>> 562 help
>> 563 This enables support for the NEC Electronics Mark-eins boards.
>> 564
>> 565 config MACH_VR41XX
>> 566 bool "NEC VR4100 series based machines"
>> 567 select CEVT_R4K
>> 568 select CSRC_R4K
>> 569 select SYS_HAS_CPU_VR41XX
>> 570 select SYS_SUPPORTS_MIPS16
>> 571 select GPIOLIB
>> 572
>> 573 config NXP_STB220
>> 574 bool "NXP STB220 board"
>> 575 select SOC_PNX833X
>> 576 help
>> 577 Support for NXP Semiconductors STB220 Development Board.
>> 578
>> 579 config NXP_STB225
>> 580 bool "NXP 225 board"
>> 581 select SOC_PNX833X
>> 582 select SOC_PNX8335
>> 583 help
>> 584 Support for NXP Semiconductors STB225 Development Board.
>> 585
>> 586 config PMC_MSP
>> 587 bool "PMC-Sierra MSP chipsets"
>> 588 select CEVT_R4K
>> 589 select CSRC_R4K
>> 590 select DMA_NONCOHERENT
>> 591 select SWAP_IO_SPACE
>> 592 select NO_EXCEPT_FILL
>> 593 select BOOT_RAW
>> 594 select SYS_HAS_CPU_MIPS32_R1
>> 595 select SYS_HAS_CPU_MIPS32_R2
>> 596 select SYS_SUPPORTS_32BIT_KERNEL
>> 597 select SYS_SUPPORTS_BIG_ENDIAN
>> 598 select SYS_SUPPORTS_MIPS16
>> 599 select IRQ_MIPS_CPU
>> 600 select SERIAL_8250
>> 601 select SERIAL_8250_CONSOLE
>> 602 select USB_EHCI_BIG_ENDIAN_MMIO
>> 603 select USB_EHCI_BIG_ENDIAN_DESC
>> 604 help
>> 605 This adds support for the PMC-Sierra family of Multi-Service
>> 606 Processor System-On-A-Chips. These parts include a number
>> 607 of integrated peripherals, interfaces and DSPs in addition to
>> 608 a variety of MIPS cores.
>> 609
>> 610 config RALINK
>> 611 bool "Ralink based machines"
>> 612 select CEVT_R4K
>> 613 select CSRC_R4K
>> 614 select BOOT_RAW
>> 615 select DMA_NONCOHERENT
>> 616 select IRQ_MIPS_CPU
>> 617 select USE_OF
>> 618 select SYS_HAS_CPU_MIPS32_R1
>> 619 select SYS_HAS_CPU_MIPS32_R2
>> 620 select SYS_SUPPORTS_32BIT_KERNEL
>> 621 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 622 select SYS_SUPPORTS_MIPS16
>> 623 select SYS_HAS_EARLY_PRINTK
>> 624 select CLKDEV_LOOKUP
>> 625 select ARCH_HAS_RESET_CONTROLLER
>> 626 select RESET_CONTROLLER
>> 627
>> 628 config SGI_IP22
>> 629 bool "SGI IP22 (Indy/Indigo2)"
>> 630 select FW_ARC
>> 631 select FW_ARC32
>> 632 select BOOT_ELF32
>> 633 select CEVT_R4K
>> 634 select CSRC_R4K
>> 635 select DEFAULT_SGI_PARTITION
>> 636 select DMA_NONCOHERENT
>> 637 select HW_HAS_EISA
>> 638 select I8253
>> 639 select I8259
>> 640 select IP22_CPU_SCACHE
>> 641 select IRQ_MIPS_CPU
>> 642 select GENERIC_ISA_DMA_SUPPORT_BROKEN
>> 643 select SGI_HAS_I8042
>> 644 select SGI_HAS_INDYDOG
>> 645 select SGI_HAS_HAL2
>> 646 select SGI_HAS_SEEQ
>> 647 select SGI_HAS_WD93
>> 648 select SGI_HAS_ZILOG
>> 649 select SWAP_IO_SPACE
>> 650 select SYS_HAS_CPU_R4X00
>> 651 select SYS_HAS_CPU_R5000
>> 652 #
>> 653 # Disable EARLY_PRINTK for now since it leads to overwritten prom
>> 654 # memory during early boot on some machines.
>> 655 #
>> 656 # See http://www.linux-mips.org/cgi-bin/mesg.cgi?a=linux-mips&i=20091119164009.GA15038%40deprecation.cyrius.com
>> 657 # for a more details discussion
>> 658 #
>> 659 # select SYS_HAS_EARLY_PRINTK
>> 660 select SYS_SUPPORTS_32BIT_KERNEL
>> 661 select SYS_SUPPORTS_64BIT_KERNEL
>> 662 select SYS_SUPPORTS_BIG_ENDIAN
>> 663 select MIPS_L1_CACHE_SHIFT_7
>> 664 help
>> 665 This are the SGI Indy, Challenge S and Indigo2, as well as certain
>> 666 OEM variants like the Tandem CMN B006S. To compile a Linux kernel
>> 667 that runs on these, say Y here.
>> 668
>> 669 config SGI_IP27
>> 670 bool "SGI IP27 (Origin200/2000)"
>> 671 select FW_ARC
>> 672 select FW_ARC64
>> 673 select BOOT_ELF64
>> 674 select DEFAULT_SGI_PARTITION
>> 675 select DMA_COHERENT
>> 676 select SYS_HAS_EARLY_PRINTK
>> 677 select HW_HAS_PCI
>> 678 select NR_CPUS_DEFAULT_64
>> 679 select SYS_HAS_CPU_R10000
>> 680 select SYS_SUPPORTS_64BIT_KERNEL
>> 681 select SYS_SUPPORTS_BIG_ENDIAN
>> 682 select SYS_SUPPORTS_NUMA
>> 683 select SYS_SUPPORTS_SMP
>> 684 select MIPS_L1_CACHE_SHIFT_7
>> 685 help
>> 686 This are the SGI Origin 200, Origin 2000 and Onyx 2 Graphics
>> 687 workstations. To compile a Linux kernel that runs on these, say Y
>> 688 here.
>> 689
>> 690 config SGI_IP28
>> 691 bool "SGI IP28 (Indigo2 R10k)"
>> 692 select FW_ARC
>> 693 select FW_ARC64
>> 694 select BOOT_ELF64
>> 695 select CEVT_R4K
>> 696 select CSRC_R4K
>> 697 select DEFAULT_SGI_PARTITION
>> 698 select DMA_NONCOHERENT
>> 699 select GENERIC_ISA_DMA_SUPPORT_BROKEN
>> 700 select IRQ_MIPS_CPU
>> 701 select HW_HAS_EISA
>> 702 select I8253
>> 703 select I8259
>> 704 select SGI_HAS_I8042
>> 705 select SGI_HAS_INDYDOG
>> 706 select SGI_HAS_HAL2
>> 707 select SGI_HAS_SEEQ
>> 708 select SGI_HAS_WD93
>> 709 select SGI_HAS_ZILOG
>> 710 select SWAP_IO_SPACE
>> 711 select SYS_HAS_CPU_R10000
>> 712 #
>> 713 # Disable EARLY_PRINTK for now since it leads to overwritten prom
>> 714 # memory during early boot on some machines.
>> 715 #
>> 716 # See http://www.linux-mips.org/cgi-bin/mesg.cgi?a=linux-mips&i=20091119164009.GA15038%40deprecation.cyrius.com
>> 717 # for a more details discussion
>> 718 #
>> 719 # select SYS_HAS_EARLY_PRINTK
>> 720 select SYS_SUPPORTS_64BIT_KERNEL
>> 721 select SYS_SUPPORTS_BIG_ENDIAN
>> 722 select MIPS_L1_CACHE_SHIFT_7
>> 723 help
>> 724 This is the SGI Indigo2 with R10000 processor. To compile a Linux
>> 725 kernel that runs on these, say Y here.
>> 726
>> 727 config SGI_IP32
>> 728 bool "SGI IP32 (O2)"
>> 729 select FW_ARC
>> 730 select FW_ARC32
>> 731 select BOOT_ELF32
>> 732 select CEVT_R4K
>> 733 select CSRC_R4K
>> 734 select DMA_NONCOHERENT
>> 735 select HW_HAS_PCI
>> 736 select IRQ_MIPS_CPU
>> 737 select R5000_CPU_SCACHE
>> 738 select RM7000_CPU_SCACHE
>> 739 select SYS_HAS_CPU_R5000
>> 740 select SYS_HAS_CPU_R10000 if BROKEN
>> 741 select SYS_HAS_CPU_RM7000
>> 742 select SYS_HAS_CPU_NEVADA
>> 743 select SYS_SUPPORTS_64BIT_KERNEL
>> 744 select SYS_SUPPORTS_BIG_ENDIAN
>> 745 help
>> 746 If you want this kernel to run on SGI O2 workstation, say Y here.
>> 747
>> 748 config SIBYTE_CRHINE
>> 749 bool "Sibyte BCM91120C-CRhine"
>> 750 select BOOT_ELF32
>> 751 select DMA_COHERENT
>> 752 select SIBYTE_BCM1120
>> 753 select SWAP_IO_SPACE
>> 754 select SYS_HAS_CPU_SB1
>> 755 select SYS_SUPPORTS_BIG_ENDIAN
>> 756 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 757
>> 758 config SIBYTE_CARMEL
>> 759 bool "Sibyte BCM91120x-Carmel"
>> 760 select BOOT_ELF32
>> 761 select DMA_COHERENT
>> 762 select SIBYTE_BCM1120
>> 763 select SWAP_IO_SPACE
>> 764 select SYS_HAS_CPU_SB1
>> 765 select SYS_SUPPORTS_BIG_ENDIAN
>> 766 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 767
>> 768 config SIBYTE_CRHONE
>> 769 bool "Sibyte BCM91125C-CRhone"
>> 770 select BOOT_ELF32
>> 771 select DMA_COHERENT
>> 772 select SIBYTE_BCM1125
>> 773 select SWAP_IO_SPACE
>> 774 select SYS_HAS_CPU_SB1
>> 775 select SYS_SUPPORTS_BIG_ENDIAN
>> 776 select SYS_SUPPORTS_HIGHMEM
>> 777 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 778
>> 779 config SIBYTE_RHONE
>> 780 bool "Sibyte BCM91125E-Rhone"
>> 781 select BOOT_ELF32
>> 782 select DMA_COHERENT
>> 783 select SIBYTE_BCM1125H
>> 784 select SWAP_IO_SPACE
>> 785 select SYS_HAS_CPU_SB1
>> 786 select SYS_SUPPORTS_BIG_ENDIAN
>> 787 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 788
>> 789 config SIBYTE_SWARM
>> 790 bool "Sibyte BCM91250A-SWARM"
>> 791 select BOOT_ELF32
>> 792 select DMA_COHERENT
>> 793 select HAVE_PATA_PLATFORM
>> 794 select SIBYTE_SB1250
>> 795 select SWAP_IO_SPACE
>> 796 select SYS_HAS_CPU_SB1
>> 797 select SYS_SUPPORTS_BIG_ENDIAN
>> 798 select SYS_SUPPORTS_HIGHMEM
>> 799 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 800 select ZONE_DMA32 if 64BIT
>> 801
>> 802 config SIBYTE_LITTLESUR
>> 803 bool "Sibyte BCM91250C2-LittleSur"
>> 804 select BOOT_ELF32
>> 805 select DMA_COHERENT
>> 806 select HAVE_PATA_PLATFORM
>> 807 select SIBYTE_SB1250
>> 808 select SWAP_IO_SPACE
>> 809 select SYS_HAS_CPU_SB1
>> 810 select SYS_SUPPORTS_BIG_ENDIAN
>> 811 select SYS_SUPPORTS_HIGHMEM
>> 812 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 813
>> 814 config SIBYTE_SENTOSA
>> 815 bool "Sibyte BCM91250E-Sentosa"
>> 816 select BOOT_ELF32
>> 817 select DMA_COHERENT
>> 818 select SIBYTE_SB1250
>> 819 select SWAP_IO_SPACE
>> 820 select SYS_HAS_CPU_SB1
>> 821 select SYS_SUPPORTS_BIG_ENDIAN
>> 822 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 823
>> 824 config SIBYTE_BIGSUR
>> 825 bool "Sibyte BCM91480B-BigSur"
>> 826 select BOOT_ELF32
>> 827 select DMA_COHERENT
>> 828 select NR_CPUS_DEFAULT_4
>> 829 select SIBYTE_BCM1x80
>> 830 select SWAP_IO_SPACE
>> 831 select SYS_HAS_CPU_SB1
>> 832 select SYS_SUPPORTS_BIG_ENDIAN
>> 833 select SYS_SUPPORTS_HIGHMEM
>> 834 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 835 select ZONE_DMA32 if 64BIT
>> 836
>> 837 config SNI_RM
>> 838 bool "SNI RM200/300/400"
>> 839 select FW_ARC if CPU_LITTLE_ENDIAN
>> 840 select FW_ARC32 if CPU_LITTLE_ENDIAN
>> 841 select FW_SNIPROM if CPU_BIG_ENDIAN
>> 842 select ARCH_MAY_HAVE_PC_FDC
>> 843 select BOOT_ELF32
>> 844 select CEVT_R4K
>> 845 select CSRC_R4K
>> 846 select DEFAULT_SGI_PARTITION if CPU_BIG_ENDIAN
>> 847 select DMA_NONCOHERENT
>> 848 select GENERIC_ISA_DMA
>> 849 select HAVE_PCSPKR_PLATFORM
>> 850 select HW_HAS_EISA
>> 851 select HW_HAS_PCI
>> 852 select IRQ_MIPS_CPU
>> 853 select I8253
>> 854 select I8259
>> 855 select ISA
>> 856 select SWAP_IO_SPACE if CPU_BIG_ENDIAN
>> 857 select SYS_HAS_CPU_R4X00
>> 858 select SYS_HAS_CPU_R5000
>> 859 select SYS_HAS_CPU_R10000
>> 860 select R5000_CPU_SCACHE
>> 861 select SYS_HAS_EARLY_PRINTK
>> 862 select SYS_SUPPORTS_32BIT_KERNEL
>> 863 select SYS_SUPPORTS_64BIT_KERNEL
>> 864 select SYS_SUPPORTS_BIG_ENDIAN
>> 865 select SYS_SUPPORTS_HIGHMEM
>> 866 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 867 help
>> 868 The SNI RM200/300/400 are MIPS-based machines manufactured by
>> 869 Siemens Nixdorf Informationssysteme (SNI), parent company of Pyramid
>> 870 Technology and now in turn merged with Fujitsu. Say Y here to
>> 871 support this machine type.
>> 872
>> 873 config MACH_TX39XX
>> 874 bool "Toshiba TX39 series based machines"
>> 875
>> 876 config MACH_TX49XX
>> 877 bool "Toshiba TX49 series based machines"
>> 878
>> 879 config MIKROTIK_RB532
>> 880 bool "Mikrotik RB532 boards"
>> 881 select CEVT_R4K
>> 882 select CSRC_R4K
>> 883 select DMA_NONCOHERENT
>> 884 select HW_HAS_PCI
>> 885 select IRQ_MIPS_CPU
>> 886 select SYS_HAS_CPU_MIPS32_R1
>> 887 select SYS_SUPPORTS_32BIT_KERNEL
>> 888 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 889 select SWAP_IO_SPACE
>> 890 select BOOT_RAW
>> 891 select GPIOLIB
>> 892 select MIPS_L1_CACHE_SHIFT_4
>> 893 help
>> 894 Support the Mikrotik(tm) RouterBoard 532 series,
>> 895 based on the IDT RC32434 SoC.
>> 896
>> 897 config CAVIUM_OCTEON_SOC
>> 898 bool "Cavium Networks Octeon SoC based boards"
>> 899 select CEVT_R4K
>> 900 select ARCH_PHYS_ADDR_T_64BIT
>> 901 select DMA_COHERENT
>> 902 select SYS_SUPPORTS_64BIT_KERNEL
>> 903 select SYS_SUPPORTS_BIG_ENDIAN
>> 904 select EDAC_SUPPORT
>> 905 select EDAC_ATOMIC_SCRUB
>> 906 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 907 select SYS_SUPPORTS_HOTPLUG_CPU if CPU_BIG_ENDIAN
>> 908 select SYS_HAS_EARLY_PRINTK
>> 909 select SYS_HAS_CPU_CAVIUM_OCTEON
>> 910 select HW_HAS_PCI
>> 911 select ZONE_DMA32
>> 912 select HOLES_IN_ZONE
>> 913 select GPIOLIB
>> 914 select LIBFDT
>> 915 select USE_OF
>> 916 select ARCH_SPARSEMEM_ENABLE
>> 917 select SYS_SUPPORTS_SMP
>> 918 select NR_CPUS_DEFAULT_16
>> 919 select BUILTIN_DTB
>> 920 select MTD_COMPLEX_MAPPINGS
>> 921 select SYS_SUPPORTS_RELOCATABLE
>> 922 help
>> 923 This option supports all of the Octeon reference boards from Cavium
>> 924 Networks. It builds a kernel that dynamically determines the Octeon
>> 925 CPU type and supports all known board reference implementations.
>> 926 Some of the supported boards are:
>> 927 EBT3000
>> 928 EBH3000
>> 929 EBH3100
>> 930 Thunder
>> 931 Kodama
>> 932 Hikari
>> 933 Say Y here for most Octeon reference boards.
>> 934
>> 935 config NLM_XLR_BOARD
>> 936 bool "Netlogic XLR/XLS based systems"
>> 937 select BOOT_ELF32
>> 938 select NLM_COMMON
>> 939 select SYS_HAS_CPU_XLR
>> 940 select SYS_SUPPORTS_SMP
>> 941 select HW_HAS_PCI
>> 942 select SWAP_IO_SPACE
>> 943 select SYS_SUPPORTS_32BIT_KERNEL
>> 944 select SYS_SUPPORTS_64BIT_KERNEL
>> 945 select ARCH_PHYS_ADDR_T_64BIT
>> 946 select SYS_SUPPORTS_BIG_ENDIAN
>> 947 select SYS_SUPPORTS_HIGHMEM
>> 948 select DMA_COHERENT
>> 949 select NR_CPUS_DEFAULT_32
>> 950 select CEVT_R4K
>> 951 select CSRC_R4K
>> 952 select IRQ_MIPS_CPU
>> 953 select ZONE_DMA32 if 64BIT
>> 954 select SYNC_R4K
>> 955 select SYS_HAS_EARLY_PRINTK
>> 956 select SYS_SUPPORTS_ZBOOT
>> 957 select SYS_SUPPORTS_ZBOOT_UART16550
>> 958 help
>> 959 Support for systems based on Netlogic XLR and XLS processors.
>> 960 Say Y here if you have a XLR or XLS based board.
>> 961
>> 962 config NLM_XLP_BOARD
>> 963 bool "Netlogic XLP based systems"
>> 964 select BOOT_ELF32
>> 965 select NLM_COMMON
>> 966 select SYS_HAS_CPU_XLP
>> 967 select SYS_SUPPORTS_SMP
>> 968 select HW_HAS_PCI
>> 969 select SYS_SUPPORTS_32BIT_KERNEL
>> 970 select SYS_SUPPORTS_64BIT_KERNEL
>> 971 select ARCH_PHYS_ADDR_T_64BIT
>> 972 select GPIOLIB
>> 973 select SYS_SUPPORTS_BIG_ENDIAN
>> 974 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 975 select SYS_SUPPORTS_HIGHMEM
>> 976 select DMA_COHERENT
>> 977 select NR_CPUS_DEFAULT_32
>> 978 select CEVT_R4K
>> 979 select CSRC_R4K
>> 980 select IRQ_MIPS_CPU
>> 981 select ZONE_DMA32 if 64BIT
>> 982 select SYNC_R4K
>> 983 select SYS_HAS_EARLY_PRINTK
>> 984 select USE_OF
>> 985 select SYS_SUPPORTS_ZBOOT
>> 986 select SYS_SUPPORTS_ZBOOT_UART16550
>> 987 help
>> 988 This board is based on Netlogic XLP Processor.
>> 989 Say Y here if you have a XLP based board.
>> 990
>> 991 config MIPS_PARAVIRT
>> 992 bool "Para-Virtualized guest system"
>> 993 select CEVT_R4K
>> 994 select CSRC_R4K
>> 995 select DMA_COHERENT
>> 996 select SYS_SUPPORTS_64BIT_KERNEL
>> 997 select SYS_SUPPORTS_32BIT_KERNEL
>> 998 select SYS_SUPPORTS_BIG_ENDIAN
>> 999 select SYS_SUPPORTS_SMP
>> 1000 select NR_CPUS_DEFAULT_4
>> 1001 select SYS_HAS_EARLY_PRINTK
>> 1002 select SYS_HAS_CPU_MIPS32_R2
>> 1003 select SYS_HAS_CPU_MIPS64_R2
>> 1004 select SYS_HAS_CPU_CAVIUM_OCTEON
>> 1005 select HW_HAS_PCI
>> 1006 select SWAP_IO_SPACE
>> 1007 help
>> 1008 This option supports guest running under ????
342 1009
343 config STACKTRACE_SUPPORT !! 1010 endchoice
344 def_bool y <<
345 1011
346 config ILLEGAL_POINTER_VALUE !! 1012 source "arch/mips/alchemy/Kconfig"
347 hex !! 1013 source "arch/mips/ath25/Kconfig"
348 default 0xdead000000000000 !! 1014 source "arch/mips/ath79/Kconfig"
>> 1015 source "arch/mips/bcm47xx/Kconfig"
>> 1016 source "arch/mips/bcm63xx/Kconfig"
>> 1017 source "arch/mips/bmips/Kconfig"
>> 1018 source "arch/mips/generic/Kconfig"
>> 1019 source "arch/mips/jazz/Kconfig"
>> 1020 source "arch/mips/jz4740/Kconfig"
>> 1021 source "arch/mips/lantiq/Kconfig"
>> 1022 source "arch/mips/lasat/Kconfig"
>> 1023 source "arch/mips/pic32/Kconfig"
>> 1024 source "arch/mips/pistachio/Kconfig"
>> 1025 source "arch/mips/pmcs-msp71xx/Kconfig"
>> 1026 source "arch/mips/ralink/Kconfig"
>> 1027 source "arch/mips/sgi-ip27/Kconfig"
>> 1028 source "arch/mips/sibyte/Kconfig"
>> 1029 source "arch/mips/txx9/Kconfig"
>> 1030 source "arch/mips/vr41xx/Kconfig"
>> 1031 source "arch/mips/cavium-octeon/Kconfig"
>> 1032 source "arch/mips/loongson32/Kconfig"
>> 1033 source "arch/mips/loongson64/Kconfig"
>> 1034 source "arch/mips/netlogic/Kconfig"
>> 1035 source "arch/mips/paravirt/Kconfig"
>> 1036 source "arch/mips/xilfpga/Kconfig"
349 1037
350 config LOCKDEP_SUPPORT !! 1038 endmenu
351 def_bool y <<
352 1039
353 config GENERIC_BUG !! 1040 config RWSEM_GENERIC_SPINLOCK
354 def_bool y !! 1041 bool
355 depends on BUG !! 1042 default y
356 1043
357 config GENERIC_BUG_RELATIVE_POINTERS !! 1044 config RWSEM_XCHGADD_ALGORITHM
358 def_bool y !! 1045 bool
359 depends on GENERIC_BUG <<
360 1046
361 config GENERIC_HWEIGHT 1047 config GENERIC_HWEIGHT
362 def_bool y !! 1048 bool
363 !! 1049 default y
364 config GENERIC_CSUM <<
365 def_bool y <<
366 1050
367 config GENERIC_CALIBRATE_DELAY 1051 config GENERIC_CALIBRATE_DELAY
368 def_bool y <<
369 <<
370 config SMP <<
371 def_bool y <<
372 <<
373 config KERNEL_MODE_NEON <<
374 def_bool y <<
375 <<
376 config FIX_EARLYCON_MEM <<
377 def_bool y <<
378 <<
379 config PGTABLE_LEVELS <<
380 int <<
381 default 2 if ARM64_16K_PAGES && ARM64_ <<
382 default 2 if ARM64_64K_PAGES && ARM64_ <<
383 default 3 if ARM64_64K_PAGES && (ARM64 <<
384 default 3 if ARM64_4K_PAGES && ARM64_V <<
385 default 3 if ARM64_16K_PAGES && ARM64_ <<
386 default 4 if ARM64_16K_PAGES && (ARM64 <<
387 default 4 if !ARM64_64K_PAGES && ARM64 <<
388 default 5 if ARM64_4K_PAGES && ARM64_V <<
389 <<
390 config ARCH_SUPPORTS_UPROBES <<
391 def_bool y <<
392 <<
393 config ARCH_PROC_KCORE_TEXT <<
394 def_bool y <<
395 <<
396 config BROKEN_GAS_INST <<
397 def_bool !$(as-instr,1:\n.inst 0\n.rep <<
398 <<
399 config BUILTIN_RETURN_ADDRESS_STRIPS_PAC <<
400 bool 1052 bool
401 # Clang's __builtin_return_address() s !! 1053 default y
402 # https://github.com/llvm/llvm-project <<
403 default y if CC_IS_CLANG <<
404 # GCC's __builtin_return_address() str <<
405 # and this was backported to 10.2.0, 9 <<
406 # https://gcc.gnu.org/bugzilla/show_bu <<
407 default y if CC_IS_GCC && (GCC_VERSION <<
408 default y if CC_IS_GCC && (GCC_VERSION <<
409 default y if CC_IS_GCC && (GCC_VERSION <<
410 default y if CC_IS_GCC && (GCC_VERSION <<
411 default n <<
412 <<
413 config KASAN_SHADOW_OFFSET <<
414 hex <<
415 depends on KASAN_GENERIC || KASAN_SW_T <<
416 default 0xdfff800000000000 if (ARM64_V <<
417 default 0xdfffc00000000000 if (ARM64_V <<
418 default 0xdffffe0000000000 if ARM64_VA <<
419 default 0xdfffffc000000000 if ARM64_VA <<
420 default 0xdffffff800000000 if ARM64_VA <<
421 default 0xefff800000000000 if (ARM64_V <<
422 default 0xefffc00000000000 if (ARM64_V <<
423 default 0xeffffe0000000000 if ARM64_VA <<
424 default 0xefffffc000000000 if ARM64_VA <<
425 default 0xeffffff800000000 if ARM64_VA <<
426 default 0xffffffffffffffff <<
427 <<
428 config UNWIND_TABLES <<
429 bool <<
430 <<
431 source "arch/arm64/Kconfig.platforms" <<
432 <<
433 menu "Kernel Features" <<
434 <<
435 menu "ARM errata workarounds via the alternati <<
436 <<
437 config AMPERE_ERRATUM_AC03_CPU_38 <<
438 bool "AmpereOne: AC03_CPU_38: Certain <<
439 default y <<
440 help <<
441 This option adds an alternative code <<
442 errata AC03_CPU_38 and AC04_CPU_10 o <<
443 <<
444 The affected design reports FEAT_HAF <<
445 ID_AA64MMFR1_EL1.HAFDBS, but (V)TCR_ <<
446 as required by the architecture. The <<
447 implementation suffers from an addit <<
448 A/D updates can occur after a PTE ha <<
449 <<
450 The workaround forces KVM to explici <<
451 which avoids enabling unadvertised h <<
452 at stage-2. <<
453 <<
454 If unsure, say Y. <<
455 1054
456 config ARM64_WORKAROUND_CLEAN_CACHE !! 1055 config SCHED_OMIT_FRAME_POINTER
457 bool 1056 bool
458 <<
459 config ARM64_ERRATUM_826319 <<
460 bool "Cortex-A53: 826319: System might <<
461 default y 1057 default y
462 select ARM64_WORKAROUND_CLEAN_CACHE <<
463 help <<
464 This option adds an alternative code <<
465 erratum 826319 on Cortex-A53 parts u <<
466 AXI master interface and an L2 cache <<
467 <<
468 If a Cortex-A53 uses an AMBA AXI4 AC <<
469 and is unable to accept a certain wr <<
470 not progress on read data presented <<
471 system can deadlock. <<
472 1058
473 The workaround promotes data cache c !! 1059 #
474 data cache clean-and-invalidate. !! 1060 # Select some configuration options automatically based on user selections.
475 Please note that this does not neces !! 1061 #
476 as it depends on the alternative fra !! 1062 config FW_ARC
477 the kernel if an affected CPU is det !! 1063 bool
478 <<
479 If unsure, say Y. <<
480 <<
481 config ARM64_ERRATUM_827319 <<
482 bool "Cortex-A53: 827319: Data cache c <<
483 default y <<
484 select ARM64_WORKAROUND_CLEAN_CACHE <<
485 help <<
486 This option adds an alternative code <<
487 erratum 827319 on Cortex-A53 parts u <<
488 master interface and an L2 cache. <<
489 <<
490 Under certain conditions this erratu <<
491 to occur at the same time as another <<
492 on the AMBA 5 CHI interface, which c <<
493 interconnect reorders the two transa <<
494 <<
495 The workaround promotes data cache c <<
496 data cache clean-and-invalidate. <<
497 Please note that this does not neces <<
498 as it depends on the alternative fra <<
499 the kernel if an affected CPU is det <<
500 1064
501 If unsure, say Y. !! 1065 config ARCH_MAY_HAVE_PC_FDC
>> 1066 bool
502 1067
503 config ARM64_ERRATUM_824069 !! 1068 config BOOT_RAW
504 bool "Cortex-A53: 824069: Cache line m !! 1069 bool
505 default y <<
506 select ARM64_WORKAROUND_CLEAN_CACHE <<
507 help <<
508 This option adds an alternative code <<
509 erratum 824069 on Cortex-A53 parts u <<
510 to a coherent interconnect. <<
511 <<
512 If a Cortex-A53 processor is executi <<
513 write instruction at the same time a <<
514 cluster is executing a cache mainten <<
515 address, then this erratum might cau <<
516 incorrectly marked as dirty. <<
517 <<
518 The workaround promotes data cache c <<
519 data cache clean-and-invalidate. <<
520 Please note that this option does no <<
521 workaround, as it depends on the alt <<
522 only patch the kernel if an affected <<
523 1070
524 If unsure, say Y. !! 1071 config CEVT_BCM1480
>> 1072 bool
525 1073
526 config ARM64_ERRATUM_819472 !! 1074 config CEVT_DS1287
527 bool "Cortex-A53: 819472: Store exclus !! 1075 bool
528 default y <<
529 select ARM64_WORKAROUND_CLEAN_CACHE <<
530 help <<
531 This option adds an alternative code <<
532 erratum 819472 on Cortex-A53 parts u <<
533 present when it is connected to a co <<
534 <<
535 If the processor is executing a load <<
536 the same time as a processor in anot <<
537 maintenance operation to the same ad <<
538 cause data corruption. <<
539 <<
540 The workaround promotes data cache c <<
541 data cache clean-and-invalidate. <<
542 Please note that this does not neces <<
543 as it depends on the alternative fra <<
544 the kernel if an affected CPU is det <<
545 1076
546 If unsure, say Y. !! 1077 config CEVT_GT641XX
>> 1078 bool
547 1079
548 config ARM64_ERRATUM_832075 !! 1080 config CEVT_R4K
549 bool "Cortex-A57: 832075: possible dea !! 1081 bool
550 default y <<
551 help <<
552 This option adds an alternative code <<
553 erratum 832075 on Cortex-A57 parts u <<
554 1082
555 Affected Cortex-A57 parts might dead !! 1083 config CEVT_SB1250
556 instructions to Write-Back memory ar !! 1084 bool
557 1085
558 The workaround is to promote device !! 1086 config CEVT_TXX9
559 semantics. !! 1087 bool
560 Please note that this does not neces <<
561 as it depends on the alternative fra <<
562 the kernel if an affected CPU is det <<
563 1088
564 If unsure, say Y. !! 1089 config CSRC_BCM1480
>> 1090 bool
565 1091
566 config ARM64_ERRATUM_834220 !! 1092 config CSRC_IOASIC
567 bool "Cortex-A57: 834220: Stage 2 tran !! 1093 bool
568 depends on KVM <<
569 help <<
570 This option adds an alternative code <<
571 erratum 834220 on Cortex-A57 parts u <<
572 <<
573 Affected Cortex-A57 parts might repo <<
574 fault as the result of a Stage 1 fau <<
575 page boundary when there is a permis <<
576 alignment fault at Stage 1 and a tra <<
577 <<
578 The workaround is to verify that the <<
579 doesn't generate a fault before hand <<
580 Please note that this does not neces <<
581 as it depends on the alternative fra <<
582 the kernel if an affected CPU is det <<
583 1094
584 If unsure, say N. !! 1095 config CSRC_R4K
>> 1096 bool
585 1097
586 config ARM64_ERRATUM_1742098 !! 1098 config CSRC_SB1250
587 bool "Cortex-A57/A72: 1742098: ELR rec !! 1099 bool
588 depends on COMPAT <<
589 default y <<
590 help <<
591 This option removes the AES hwcap fo <<
592 workaround erratum 1742098 on Cortex <<
593 <<
594 Affected parts may corrupt the AES s <<
595 taken between a pair of AES instruct <<
596 are only present if the cryptography <<
597 All software should have a fallback <<
598 that don't implement the cryptograph <<
599 1100
600 If unsure, say Y. !! 1101 config MIPS_CLOCK_VSYSCALL
>> 1102 def_bool CSRC_R4K || CLKSRC_MIPS_GIC
601 1103
602 config ARM64_ERRATUM_845719 !! 1104 config GPIO_TXX9
603 bool "Cortex-A53: 845719: a load might !! 1105 select GPIOLIB
604 depends on COMPAT !! 1106 bool
605 default y <<
606 help <<
607 This option adds an alternative code <<
608 erratum 845719 on Cortex-A53 parts u <<
609 <<
610 When running a compat (AArch32) user <<
611 part, a load at EL0 from a virtual a <<
612 bits of the virtual address used by <<
613 might return incorrect data. <<
614 <<
615 The workaround is to write the conte <<
616 return to a 32-bit task. <<
617 Please note that this does not neces <<
618 as it depends on the alternative fra <<
619 the kernel if an affected CPU is det <<
620 1107
621 If unsure, say Y. !! 1108 config FW_CFE
>> 1109 bool
622 1110
623 config ARM64_ERRATUM_843419 !! 1111 config ARCH_DMA_ADDR_T_64BIT
624 bool "Cortex-A53: 843419: A load or st !! 1112 def_bool (HIGHMEM && ARCH_PHYS_ADDR_T_64BIT) || 64BIT
625 default y <<
626 help <<
627 This option links the kernel with '- <<
628 enables PLT support to replace certa <<
629 cause subsequent memory accesses to <<
630 Cortex-A53 parts up to r0p4. <<
631 1113
632 If unsure, say Y. !! 1114 config ARCH_SUPPORTS_UPROBES
>> 1115 bool
633 1116
634 config ARM64_LD_HAS_FIX_ERRATUM_843419 !! 1117 config DMA_MAYBE_COHERENT
635 def_bool $(ld-option,--fix-cortex-a53- !! 1118 select DMA_NONCOHERENT
>> 1119 bool
636 1120
637 config ARM64_ERRATUM_1024718 !! 1121 config DMA_PERDEV_COHERENT
638 bool "Cortex-A55: 1024718: Update of D !! 1122 bool
639 default y !! 1123 select DMA_MAYBE_COHERENT
640 help <<
641 This option adds a workaround for AR <<
642 1124
643 Affected Cortex-A55 cores (all revis !! 1125 config DMA_COHERENT
644 update of the hardware dirty bit whe !! 1126 bool
645 without a break-before-make. The wor <<
646 of hardware DBM locally on the affec <<
647 this erratum will continue to use th <<
648 1127
649 If unsure, say Y. !! 1128 config DMA_NONCOHERENT
>> 1129 bool
>> 1130 select NEED_DMA_MAP_STATE
650 1131
651 config ARM64_ERRATUM_1418040 !! 1132 config NEED_DMA_MAP_STATE
652 bool "Cortex-A76/Neoverse-N1: MRC read !! 1133 bool
653 default y <<
654 depends on COMPAT <<
655 help <<
656 This option adds a workaround for AR <<
657 errata 1188873 and 1418040. <<
658 1134
659 Affected Cortex-A76/Neoverse-N1 core !! 1135 config SYS_HAS_EARLY_PRINTK
660 cause register corruption when acces !! 1136 bool
661 from AArch32 userspace. <<
662 1137
663 If unsure, say Y. !! 1138 config SYS_SUPPORTS_HOTPLUG_CPU
>> 1139 bool
664 1140
665 config ARM64_WORKAROUND_SPECULATIVE_AT !! 1141 config MIPS_BONITO64
666 bool 1142 bool
667 1143
668 config ARM64_ERRATUM_1165522 !! 1144 config MIPS_MSC
669 bool "Cortex-A76: 1165522: Speculative !! 1145 bool
670 default y <<
671 select ARM64_WORKAROUND_SPECULATIVE_AT <<
672 help <<
673 This option adds a workaround for AR <<
674 1146
675 Affected Cortex-A76 cores (r0p0, r1p !! 1147 config MIPS_NILE4
676 corrupted TLBs by speculating an AT !! 1148 bool
677 context switch. <<
678 1149
679 If unsure, say Y. !! 1150 config SYNC_R4K
>> 1151 bool
680 1152
681 config ARM64_ERRATUM_1319367 !! 1153 config MIPS_MACHINE
682 bool "Cortex-A57/A72: 1319537: Specula !! 1154 def_bool n
683 default y <<
684 select ARM64_WORKAROUND_SPECULATIVE_AT <<
685 help <<
686 This option adds work arounds for AR <<
687 and A72 erratum 1319367 <<
688 1155
689 Cortex-A57 and A72 cores could end-u !! 1156 config NO_IOPORT_MAP
690 speculating an AT instruction during !! 1157 def_bool n
691 1158
692 If unsure, say Y. !! 1159 config GENERIC_CSUM
>> 1160 bool
693 1161
694 config ARM64_ERRATUM_1530923 !! 1162 config GENERIC_ISA_DMA
695 bool "Cortex-A55: 1530923: Speculative !! 1163 bool
696 default y !! 1164 select ZONE_DMA if GENERIC_ISA_DMA_SUPPORT_BROKEN=n
697 select ARM64_WORKAROUND_SPECULATIVE_AT !! 1165 select ISA_DMA_API
698 help <<
699 This option adds a workaround for AR <<
700 1166
701 Affected Cortex-A55 cores (r0p0, r0p !! 1167 config GENERIC_ISA_DMA_SUPPORT_BROKEN
702 corrupted TLBs by speculating an AT !! 1168 bool
703 context switch. !! 1169 select GENERIC_ISA_DMA
704 1170
705 If unsure, say Y. !! 1171 config ISA_DMA_API
>> 1172 bool
706 1173
707 config ARM64_WORKAROUND_REPEAT_TLBI !! 1174 config HOLES_IN_ZONE
708 bool 1175 bool
709 1176
710 config ARM64_ERRATUM_2441007 !! 1177 config SYS_SUPPORTS_RELOCATABLE
711 bool "Cortex-A55: Completion of affect !! 1178 bool
712 select ARM64_WORKAROUND_REPEAT_TLBI <<
713 help 1179 help
714 This option adds a workaround for AR !! 1180 Selected if the platform supports relocating the kernel.
715 !! 1181 The platform must provide plat_get_fdt() if it selects CONFIG_USE_OF
716 Under very rare circumstances, affec !! 1182 to allow access to command line and entropy sources.
717 may not handle a race between a brea <<
718 CPU, and another CPU accessing the s <<
719 store to a page that has been unmapp <<
720 <<
721 Work around this by adding the affec <<
722 TLB sequences to be done twice. <<
723 1183
724 If unsure, say N. !! 1184 config MIPS_CBPF_JIT
>> 1185 def_bool y
>> 1186 depends on BPF_JIT && HAVE_CBPF_JIT
725 1187
726 config ARM64_ERRATUM_1286807 !! 1188 config MIPS_EBPF_JIT
727 bool "Cortex-A76: Modification of the !! 1189 def_bool y
728 select ARM64_WORKAROUND_REPEAT_TLBI !! 1190 depends on BPF_JIT && HAVE_EBPF_JIT
729 help <<
730 This option adds a workaround for AR <<
731 <<
732 On the affected Cortex-A76 cores (r0 <<
733 address for a cacheable mapping of a <<
734 accessed by a core while another cor <<
735 address to a new physical page using <<
736 break-before-make sequence, then und <<
737 TLBI+DSB completes before a read usi <<
738 invalidated has been observed by oth <<
739 workaround repeats the TLBI+DSB oper <<
740 1191
741 If unsure, say N. <<
742 1192
743 config ARM64_ERRATUM_1463225 !! 1193 #
744 bool "Cortex-A76: Software Step might !! 1194 # Endianness selection. Sufficiently obscure so many users don't know what to
745 default y !! 1195 # answer,so we try hard to limit the available choices. Also the use of a
>> 1196 # choice statement should be more obvious to the user.
>> 1197 #
>> 1198 choice
>> 1199 prompt "Endianness selection"
746 help 1200 help
747 This option adds a workaround for Ar !! 1201 Some MIPS machines can be configured for either little or big endian
>> 1202 byte order. These modes require different kernels and a different
>> 1203 Linux distribution. In general there is one preferred byteorder for a
>> 1204 particular system but some systems are just as commonly used in the
>> 1205 one or the other endianness.
748 1206
749 On the affected Cortex-A76 cores (r0 !! 1207 config CPU_BIG_ENDIAN
750 of a system call instruction (SVC) c !! 1208 bool "Big endian"
751 subsequent interrupts when software !! 1209 depends on SYS_SUPPORTS_BIG_ENDIAN
752 exception handler of the system call <<
753 is enabled or VHE is in use. <<
754 1210
755 Work around the erratum by triggerin !! 1211 config CPU_LITTLE_ENDIAN
756 when handling a system call from a t !! 1212 bool "Little endian"
757 in a VHE configuration of the kernel !! 1213 depends on SYS_SUPPORTS_LITTLE_ENDIAN
758 1214
759 If unsure, say Y. !! 1215 endchoice
760 1216
761 config ARM64_ERRATUM_1542419 !! 1217 config EXPORT_UASM
762 bool "Neoverse-N1: workaround mis-orde !! 1218 bool
763 help <<
764 This option adds a workaround for AR <<
765 1542419. <<
766 1219
767 Affected Neoverse-N1 cores could exe !! 1220 config SYS_SUPPORTS_APM_EMULATION
768 modified by another CPU. The workaro !! 1221 bool
769 counterpart. <<
770 1222
771 Workaround the issue by hiding the D !! 1223 config SYS_SUPPORTS_BIG_ENDIAN
772 forces user-space to perform cache m !! 1224 bool
773 1225
774 If unsure, say N. !! 1226 config SYS_SUPPORTS_LITTLE_ENDIAN
>> 1227 bool
775 1228
776 config ARM64_ERRATUM_1508412 !! 1229 config SYS_SUPPORTS_HUGETLBFS
777 bool "Cortex-A77: 1508412: workaround !! 1230 bool
>> 1231 depends on CPU_SUPPORTS_HUGEPAGES && 64BIT
778 default y 1232 default y
779 help <<
780 This option adds a workaround for Ar <<
781 1233
782 Affected Cortex-A77 cores (r0p0, r1p !! 1234 config MIPS_HUGE_TLB_SUPPORT
783 of a store-exclusive or read of PAR_ !! 1235 def_bool HUGETLB_PAGE || TRANSPARENT_HUGEPAGE
784 non-cacheable memory attributes. The <<
785 counterpart. <<
786 1236
787 KVM guests must also have the workar !! 1237 config IRQ_CPU_RM7K
788 deadlock the system. !! 1238 bool
789 1239
790 Work around the issue by inserting D !! 1240 config IRQ_MSP_SLP
791 register reads and warning KVM users !! 1241 bool
792 to prevent a speculative PAR_EL1 rea <<
793 1242
794 If unsure, say Y. !! 1243 config IRQ_MSP_CIC
>> 1244 bool
795 1245
796 config ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MO !! 1246 config IRQ_TXX9
797 bool 1247 bool
798 1248
799 config ARM64_ERRATUM_2051678 !! 1249 config IRQ_GT641XX
800 bool "Cortex-A510: 2051678: disable Ha !! 1250 bool
801 default y <<
802 help <<
803 This options adds the workaround for <<
804 Affected Cortex-A510 might not respe <<
805 hardware update of the page table's <<
806 is to not enable the feature on affe <<
807 1251
808 If unsure, say Y. !! 1252 config PCI_GT64XXX_PCI0
>> 1253 bool
809 1254
810 config ARM64_ERRATUM_2077057 !! 1255 config NO_EXCEPT_FILL
811 bool "Cortex-A510: 2077057: workaround !! 1256 bool
812 default y <<
813 help <<
814 This option adds the workaround for <<
815 Affected Cortex-A510 may corrupt SPS <<
816 expected, but a Pointer Authenticati <<
817 erratum causes SPSR_EL1 to be copied <<
818 EL1 to cause a return to EL2 with a <<
819 1257
820 This can only happen when EL2 is ste !! 1258 config SOC_EMMA2RH
>> 1259 bool
>> 1260 select CEVT_R4K
>> 1261 select CSRC_R4K
>> 1262 select DMA_NONCOHERENT
>> 1263 select IRQ_MIPS_CPU
>> 1264 select SWAP_IO_SPACE
>> 1265 select SYS_HAS_CPU_R5500
>> 1266 select SYS_SUPPORTS_32BIT_KERNEL
>> 1267 select SYS_SUPPORTS_64BIT_KERNEL
>> 1268 select SYS_SUPPORTS_BIG_ENDIAN
821 1269
822 When these conditions occur, the SPS !! 1270 config SOC_PNX833X
823 previous guest entry, and can be res !! 1271 bool
>> 1272 select CEVT_R4K
>> 1273 select CSRC_R4K
>> 1274 select IRQ_MIPS_CPU
>> 1275 select DMA_NONCOHERENT
>> 1276 select SYS_HAS_CPU_MIPS32_R2
>> 1277 select SYS_SUPPORTS_32BIT_KERNEL
>> 1278 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 1279 select SYS_SUPPORTS_BIG_ENDIAN
>> 1280 select SYS_SUPPORTS_MIPS16
>> 1281 select CPU_MIPSR2_IRQ_VI
824 1282
825 If unsure, say Y. !! 1283 config SOC_PNX8335
>> 1284 bool
>> 1285 select SOC_PNX833X
826 1286
827 config ARM64_ERRATUM_2658417 !! 1287 config MIPS_SPRAM
828 bool "Cortex-A510: 2658417: remove BF1 !! 1288 bool
829 default y <<
830 help <<
831 This option adds the workaround for <<
832 Affected Cortex-A510 (r0p0 to r1p1) <<
833 BFMMLA or VMMLA instructions in rare <<
834 A510 CPUs are using shared neon hard <<
835 discoverable by the kernel, hide the <<
836 user-space should not be using these <<
837 1289
838 If unsure, say Y. !! 1290 config SWAP_IO_SPACE
>> 1291 bool
839 1292
840 config ARM64_ERRATUM_2119858 !! 1293 config SGI_HAS_INDYDOG
841 bool "Cortex-A710/X2: 2119858: workaro !! 1294 bool
842 default y <<
843 depends on CORESIGHT_TRBE <<
844 select ARM64_WORKAROUND_TRBE_OVERWRITE <<
845 help <<
846 This option adds the workaround for <<
847 1295
848 Affected Cortex-A710/X2 cores could !! 1296 config SGI_HAS_HAL2
849 data at the base of the buffer (poin !! 1297 bool
850 the event of a WRAP event. <<
851 1298
852 Work around the issue by always maki !! 1299 config SGI_HAS_SEEQ
853 256 bytes before enabling the buffer !! 1300 bool
854 the buffer with ETM ignore packets u <<
855 1301
856 If unsure, say Y. !! 1302 config SGI_HAS_WD93
>> 1303 bool
857 1304
858 config ARM64_ERRATUM_2139208 !! 1305 config SGI_HAS_ZILOG
859 bool "Neoverse-N2: 2139208: workaround !! 1306 bool
860 default y <<
861 depends on CORESIGHT_TRBE <<
862 select ARM64_WORKAROUND_TRBE_OVERWRITE <<
863 help <<
864 This option adds the workaround for <<
865 1307
866 Affected Neoverse-N2 cores could ove !! 1308 config SGI_HAS_I8042
867 data at the base of the buffer (poin !! 1309 bool
868 the event of a WRAP event. <<
869 1310
870 Work around the issue by always maki !! 1311 config DEFAULT_SGI_PARTITION
871 256 bytes before enabling the buffer !! 1312 bool
872 the buffer with ETM ignore packets u <<
873 1313
874 If unsure, say Y. !! 1314 config FW_ARC32
>> 1315 bool
875 1316
876 config ARM64_WORKAROUND_TSB_FLUSH_FAILURE !! 1317 config FW_SNIPROM
877 bool 1318 bool
878 1319
879 config ARM64_ERRATUM_2054223 !! 1320 config BOOT_ELF32
880 bool "Cortex-A710: 2054223: workaround !! 1321 bool
881 default y <<
882 select ARM64_WORKAROUND_TSB_FLUSH_FAIL <<
883 help <<
884 Enable workaround for ARM Cortex-A71 <<
885 1322
886 Affected cores may fail to flush the !! 1323 config MIPS_L1_CACHE_SHIFT_4
887 the PE is in trace prohibited state. !! 1324 bool
888 of the trace cached. <<
889 1325
890 Workaround is to issue two TSB conse !! 1326 config MIPS_L1_CACHE_SHIFT_5
>> 1327 bool
891 1328
892 If unsure, say Y. !! 1329 config MIPS_L1_CACHE_SHIFT_6
>> 1330 bool
893 1331
894 config ARM64_ERRATUM_2067961 !! 1332 config MIPS_L1_CACHE_SHIFT_7
895 bool "Neoverse-N2: 2067961: workaround !! 1333 bool
896 default y <<
897 select ARM64_WORKAROUND_TSB_FLUSH_FAIL <<
898 help <<
899 Enable workaround for ARM Neoverse-N <<
900 1334
901 Affected cores may fail to flush the !! 1335 config MIPS_L1_CACHE_SHIFT
902 the PE is in trace prohibited state. !! 1336 int
903 of the trace cached. !! 1337 default "7" if MIPS_L1_CACHE_SHIFT_7
>> 1338 default "6" if MIPS_L1_CACHE_SHIFT_6
>> 1339 default "5" if MIPS_L1_CACHE_SHIFT_5
>> 1340 default "4" if MIPS_L1_CACHE_SHIFT_4
>> 1341 default "5"
904 1342
905 Workaround is to issue two TSB conse !! 1343 config HAVE_STD_PC_SERIAL_PORT
>> 1344 bool
906 1345
907 If unsure, say Y. !! 1346 config ARC_CONSOLE
>> 1347 bool "ARC console support"
>> 1348 depends on SGI_IP22 || SGI_IP28 || (SNI_RM && CPU_LITTLE_ENDIAN)
908 1349
909 config ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANG !! 1350 config ARC_MEMORY
910 bool 1351 bool
911 !! 1352 depends on MACH_JAZZ || SNI_RM || SGI_IP32
912 config ARM64_ERRATUM_2253138 <<
913 bool "Neoverse-N2: 2253138: workaround <<
914 depends on CORESIGHT_TRBE <<
915 default y 1353 default y
916 select ARM64_WORKAROUND_TRBE_WRITE_OUT <<
917 help <<
918 This option adds the workaround for <<
919 <<
920 Affected Neoverse-N2 cores might wri <<
921 for TRBE. Under some conditions, the <<
922 virtually addressed page following t <<
923 (i.e., the TRBLIMITR_EL1.LIMIT), ins <<
924 1354
925 Work around this in the driver by al !! 1355 config ARC_PROMLIB
926 page beyond the TRBLIMITR_EL1.LIMIT, !! 1356 bool
927 !! 1357 depends on MACH_JAZZ || SNI_RM || SGI_IP22 || SGI_IP28 || SGI_IP32
928 If unsure, say Y. <<
929 <<
930 config ARM64_ERRATUM_2224489 <<
931 bool "Cortex-A710/X2: 2224489: workaro <<
932 depends on CORESIGHT_TRBE <<
933 default y 1358 default y
934 select ARM64_WORKAROUND_TRBE_WRITE_OUT <<
935 help <<
936 This option adds the workaround for <<
937 <<
938 Affected Cortex-A710/X2 cores might <<
939 for TRBE. Under some conditions, the <<
940 virtually addressed page following t <<
941 (i.e., the TRBLIMITR_EL1.LIMIT), ins <<
942 1359
943 Work around this in the driver by al !! 1360 config FW_ARC64
944 page beyond the TRBLIMITR_EL1.LIMIT, !! 1361 bool
945 <<
946 If unsure, say Y. <<
947 1362
948 config ARM64_ERRATUM_2441009 !! 1363 config BOOT_ELF64
949 bool "Cortex-A510: Completion of affec !! 1364 bool
950 select ARM64_WORKAROUND_REPEAT_TLBI <<
951 help <<
952 This option adds a workaround for AR <<
953 <<
954 Under very rare circumstances, affec <<
955 may not handle a race between a brea <<
956 CPU, and another CPU accessing the s <<
957 store to a page that has been unmapp <<
958 1365
959 Work around this by adding the affec !! 1366 menu "CPU selection"
960 TLB sequences to be done twice. <<
961 1367
962 If unsure, say N. !! 1368 choice
>> 1369 prompt "CPU type"
>> 1370 default CPU_R4X00
963 1371
964 config ARM64_ERRATUM_2064142 !! 1372 config CPU_LOONGSON3
965 bool "Cortex-A510: 2064142: workaround !! 1373 bool "Loongson 3 CPU"
966 depends on CORESIGHT_TRBE !! 1374 depends on SYS_HAS_CPU_LOONGSON3
967 default y !! 1375 select CPU_SUPPORTS_64BIT_KERNEL
>> 1376 select CPU_SUPPORTS_HIGHMEM
>> 1377 select CPU_SUPPORTS_HUGEPAGES
>> 1378 select WEAK_ORDERING
>> 1379 select WEAK_REORDERING_BEYOND_LLSC
>> 1380 select MIPS_PGD_C0_CONTEXT
>> 1381 select MIPS_L1_CACHE_SHIFT_6
>> 1382 select GPIOLIB
968 help 1383 help
969 This option adds the workaround for !! 1384 The Loongson 3 processor implements the MIPS64R2 instruction
970 !! 1385 set with many extensions.
971 Affected Cortex-A510 core might fail <<
972 TRBE has been disabled. Under some c <<
973 writes into TRBE registers TRBLIMITR <<
974 and TRBTRG_EL1 will be ignored and w <<
975 1386
976 Work around this in the driver by ex !! 1387 config LOONGSON3_ENHANCEMENT
977 is stopped and before performing a s !! 1388 bool "New Loongson 3 CPU Enhancements"
978 registers. !! 1389 default n
>> 1390 select CPU_MIPSR2
>> 1391 select CPU_HAS_PREFETCH
>> 1392 depends on CPU_LOONGSON3
>> 1393 help
>> 1394 New Loongson 3 CPU (since Loongson-3A R2, as opposed to Loongson-3A
>> 1395 R1, Loongson-3B R1 and Loongson-3B R2) has many enhancements, such as
>> 1396 FTLB, L1-VCache, EI/DI/Wait/Prefetch instruction, DSP/DSPv2 ASE, User
>> 1397 Local register, Read-Inhibit/Execute-Inhibit, SFB (Store Fill Buffer),
>> 1398 Fast TLB refill support, etc.
>> 1399
>> 1400 This option enable those enhancements which are not probed at run
>> 1401 time. If you want a generic kernel to run on all Loongson 3 machines,
>> 1402 please say 'N' here. If you want a high-performance kernel to run on
>> 1403 new Loongson 3 machines only, please say 'Y' here.
>> 1404
>> 1405 config CPU_LOONGSON2E
>> 1406 bool "Loongson 2E"
>> 1407 depends on SYS_HAS_CPU_LOONGSON2E
>> 1408 select CPU_LOONGSON2
>> 1409 help
>> 1410 The Loongson 2E processor implements the MIPS III instruction set
>> 1411 with many extensions.
>> 1412
>> 1413 It has an internal FPGA northbridge, which is compatible to
>> 1414 bonito64.
>> 1415
>> 1416 config CPU_LOONGSON2F
>> 1417 bool "Loongson 2F"
>> 1418 depends on SYS_HAS_CPU_LOONGSON2F
>> 1419 select CPU_LOONGSON2
>> 1420 select GPIOLIB
>> 1421 help
>> 1422 The Loongson 2F processor implements the MIPS III instruction set
>> 1423 with many extensions.
>> 1424
>> 1425 Loongson2F have built-in DDR2 and PCIX controller. The PCIX controller
>> 1426 have a similar programming interface with FPGA northbridge used in
>> 1427 Loongson2E.
>> 1428
>> 1429 config CPU_LOONGSON1B
>> 1430 bool "Loongson 1B"
>> 1431 depends on SYS_HAS_CPU_LOONGSON1B
>> 1432 select CPU_LOONGSON1
>> 1433 select LEDS_GPIO_REGISTER
>> 1434 help
>> 1435 The Loongson 1B is a 32-bit SoC, which implements the MIPS32
>> 1436 release 2 instruction set.
>> 1437
>> 1438 config CPU_LOONGSON1C
>> 1439 bool "Loongson 1C"
>> 1440 depends on SYS_HAS_CPU_LOONGSON1C
>> 1441 select CPU_LOONGSON1
>> 1442 select LEDS_GPIO_REGISTER
>> 1443 help
>> 1444 The Loongson 1C is a 32-bit SoC, which implements the MIPS32
>> 1445 release 2 instruction set.
>> 1446
>> 1447 config CPU_MIPS32_R1
>> 1448 bool "MIPS32 Release 1"
>> 1449 depends on SYS_HAS_CPU_MIPS32_R1
>> 1450 select CPU_HAS_PREFETCH
>> 1451 select CPU_SUPPORTS_32BIT_KERNEL
>> 1452 select CPU_SUPPORTS_HIGHMEM
>> 1453 help
>> 1454 Choose this option to build a kernel for release 1 or later of the
>> 1455 MIPS32 architecture. Most modern embedded systems with a 32-bit
>> 1456 MIPS processor are based on a MIPS32 processor. If you know the
>> 1457 specific type of processor in your system, choose those that one
>> 1458 otherwise CPU_MIPS32_R1 is a safe bet for any MIPS32 system.
>> 1459 Release 2 of the MIPS32 architecture is available since several
>> 1460 years so chances are you even have a MIPS32 Release 2 processor
>> 1461 in which case you should choose CPU_MIPS32_R2 instead for better
>> 1462 performance.
>> 1463
>> 1464 config CPU_MIPS32_R2
>> 1465 bool "MIPS32 Release 2"
>> 1466 depends on SYS_HAS_CPU_MIPS32_R2
>> 1467 select CPU_HAS_PREFETCH
>> 1468 select CPU_SUPPORTS_32BIT_KERNEL
>> 1469 select CPU_SUPPORTS_HIGHMEM
>> 1470 select CPU_SUPPORTS_MSA
>> 1471 select HAVE_KVM
>> 1472 help
>> 1473 Choose this option to build a kernel for release 2 or later of the
>> 1474 MIPS32 architecture. Most modern embedded systems with a 32-bit
>> 1475 MIPS processor are based on a MIPS32 processor. If you know the
>> 1476 specific type of processor in your system, choose those that one
>> 1477 otherwise CPU_MIPS32_R1 is a safe bet for any MIPS32 system.
>> 1478
>> 1479 config CPU_MIPS32_R6
>> 1480 bool "MIPS32 Release 6"
>> 1481 depends on SYS_HAS_CPU_MIPS32_R6
>> 1482 select CPU_HAS_PREFETCH
>> 1483 select CPU_SUPPORTS_32BIT_KERNEL
>> 1484 select CPU_SUPPORTS_HIGHMEM
>> 1485 select CPU_SUPPORTS_MSA
>> 1486 select GENERIC_CSUM
>> 1487 select HAVE_KVM
>> 1488 select MIPS_O32_FP64_SUPPORT
>> 1489 help
>> 1490 Choose this option to build a kernel for release 6 or later of the
>> 1491 MIPS32 architecture. New MIPS processors, starting with the Warrior
>> 1492 family, are based on a MIPS32r6 processor. If you own an older
>> 1493 processor, you probably need to select MIPS32r1 or MIPS32r2 instead.
>> 1494
>> 1495 config CPU_MIPS64_R1
>> 1496 bool "MIPS64 Release 1"
>> 1497 depends on SYS_HAS_CPU_MIPS64_R1
>> 1498 select CPU_HAS_PREFETCH
>> 1499 select CPU_SUPPORTS_32BIT_KERNEL
>> 1500 select CPU_SUPPORTS_64BIT_KERNEL
>> 1501 select CPU_SUPPORTS_HIGHMEM
>> 1502 select CPU_SUPPORTS_HUGEPAGES
>> 1503 help
>> 1504 Choose this option to build a kernel for release 1 or later of the
>> 1505 MIPS64 architecture. Many modern embedded systems with a 64-bit
>> 1506 MIPS processor are based on a MIPS64 processor. If you know the
>> 1507 specific type of processor in your system, choose those that one
>> 1508 otherwise CPU_MIPS64_R1 is a safe bet for any MIPS64 system.
>> 1509 Release 2 of the MIPS64 architecture is available since several
>> 1510 years so chances are you even have a MIPS64 Release 2 processor
>> 1511 in which case you should choose CPU_MIPS64_R2 instead for better
>> 1512 performance.
>> 1513
>> 1514 config CPU_MIPS64_R2
>> 1515 bool "MIPS64 Release 2"
>> 1516 depends on SYS_HAS_CPU_MIPS64_R2
>> 1517 select CPU_HAS_PREFETCH
>> 1518 select CPU_SUPPORTS_32BIT_KERNEL
>> 1519 select CPU_SUPPORTS_64BIT_KERNEL
>> 1520 select CPU_SUPPORTS_HIGHMEM
>> 1521 select CPU_SUPPORTS_HUGEPAGES
>> 1522 select CPU_SUPPORTS_MSA
>> 1523 select HAVE_KVM
>> 1524 help
>> 1525 Choose this option to build a kernel for release 2 or later of the
>> 1526 MIPS64 architecture. Many modern embedded systems with a 64-bit
>> 1527 MIPS processor are based on a MIPS64 processor. If you know the
>> 1528 specific type of processor in your system, choose those that one
>> 1529 otherwise CPU_MIPS64_R1 is a safe bet for any MIPS64 system.
>> 1530
>> 1531 config CPU_MIPS64_R6
>> 1532 bool "MIPS64 Release 6"
>> 1533 depends on SYS_HAS_CPU_MIPS64_R6
>> 1534 select CPU_HAS_PREFETCH
>> 1535 select CPU_SUPPORTS_32BIT_KERNEL
>> 1536 select CPU_SUPPORTS_64BIT_KERNEL
>> 1537 select CPU_SUPPORTS_HIGHMEM
>> 1538 select CPU_SUPPORTS_MSA
>> 1539 select GENERIC_CSUM
>> 1540 select MIPS_O32_FP64_SUPPORT if 32BIT || MIPS32_O32
>> 1541 select HAVE_KVM
>> 1542 help
>> 1543 Choose this option to build a kernel for release 6 or later of the
>> 1544 MIPS64 architecture. New MIPS processors, starting with the Warrior
>> 1545 family, are based on a MIPS64r6 processor. If you own an older
>> 1546 processor, you probably need to select MIPS64r1 or MIPS64r2 instead.
>> 1547
>> 1548 config CPU_R3000
>> 1549 bool "R3000"
>> 1550 depends on SYS_HAS_CPU_R3000
>> 1551 select CPU_HAS_WB
>> 1552 select CPU_SUPPORTS_32BIT_KERNEL
>> 1553 select CPU_SUPPORTS_HIGHMEM
>> 1554 help
>> 1555 Please make sure to pick the right CPU type. Linux/MIPS is not
>> 1556 designed to be generic, i.e. Kernels compiled for R3000 CPUs will
>> 1557 *not* work on R4000 machines and vice versa. However, since most
>> 1558 of the supported machines have an R4000 (or similar) CPU, R4x00
>> 1559 might be a safe bet. If the resulting kernel does not work,
>> 1560 try to recompile with R3000.
>> 1561
>> 1562 config CPU_TX39XX
>> 1563 bool "R39XX"
>> 1564 depends on SYS_HAS_CPU_TX39XX
>> 1565 select CPU_SUPPORTS_32BIT_KERNEL
>> 1566
>> 1567 config CPU_VR41XX
>> 1568 bool "R41xx"
>> 1569 depends on SYS_HAS_CPU_VR41XX
>> 1570 select CPU_SUPPORTS_32BIT_KERNEL
>> 1571 select CPU_SUPPORTS_64BIT_KERNEL
>> 1572 help
>> 1573 The options selects support for the NEC VR4100 series of processors.
>> 1574 Only choose this option if you have one of these processors as a
>> 1575 kernel built with this option will not run on any other type of
>> 1576 processor or vice versa.
>> 1577
>> 1578 config CPU_R4300
>> 1579 bool "R4300"
>> 1580 depends on SYS_HAS_CPU_R4300
>> 1581 select CPU_SUPPORTS_32BIT_KERNEL
>> 1582 select CPU_SUPPORTS_64BIT_KERNEL
>> 1583 help
>> 1584 MIPS Technologies R4300-series processors.
>> 1585
>> 1586 config CPU_R4X00
>> 1587 bool "R4x00"
>> 1588 depends on SYS_HAS_CPU_R4X00
>> 1589 select CPU_SUPPORTS_32BIT_KERNEL
>> 1590 select CPU_SUPPORTS_64BIT_KERNEL
>> 1591 select CPU_SUPPORTS_HUGEPAGES
>> 1592 help
>> 1593 MIPS Technologies R4000-series processors other than 4300, including
>> 1594 the R4000, R4400, R4600, and 4700.
>> 1595
>> 1596 config CPU_TX49XX
>> 1597 bool "R49XX"
>> 1598 depends on SYS_HAS_CPU_TX49XX
>> 1599 select CPU_HAS_PREFETCH
>> 1600 select CPU_SUPPORTS_32BIT_KERNEL
>> 1601 select CPU_SUPPORTS_64BIT_KERNEL
>> 1602 select CPU_SUPPORTS_HUGEPAGES
>> 1603
>> 1604 config CPU_R5000
>> 1605 bool "R5000"
>> 1606 depends on SYS_HAS_CPU_R5000
>> 1607 select CPU_SUPPORTS_32BIT_KERNEL
>> 1608 select CPU_SUPPORTS_64BIT_KERNEL
>> 1609 select CPU_SUPPORTS_HUGEPAGES
>> 1610 help
>> 1611 MIPS Technologies R5000-series processors other than the Nevada.
>> 1612
>> 1613 config CPU_R5432
>> 1614 bool "R5432"
>> 1615 depends on SYS_HAS_CPU_R5432
>> 1616 select CPU_SUPPORTS_32BIT_KERNEL
>> 1617 select CPU_SUPPORTS_64BIT_KERNEL
>> 1618 select CPU_SUPPORTS_HUGEPAGES
>> 1619
>> 1620 config CPU_R5500
>> 1621 bool "R5500"
>> 1622 depends on SYS_HAS_CPU_R5500
>> 1623 select CPU_SUPPORTS_32BIT_KERNEL
>> 1624 select CPU_SUPPORTS_64BIT_KERNEL
>> 1625 select CPU_SUPPORTS_HUGEPAGES
>> 1626 help
>> 1627 NEC VR5500 and VR5500A series processors implement 64-bit MIPS IV
>> 1628 instruction set.
>> 1629
>> 1630 config CPU_R6000
>> 1631 bool "R6000"
>> 1632 depends on SYS_HAS_CPU_R6000
>> 1633 select CPU_SUPPORTS_32BIT_KERNEL
>> 1634 help
>> 1635 MIPS Technologies R6000 and R6000A series processors. Note these
>> 1636 processors are extremely rare and the support for them is incomplete.
>> 1637
>> 1638 config CPU_NEVADA
>> 1639 bool "RM52xx"
>> 1640 depends on SYS_HAS_CPU_NEVADA
>> 1641 select CPU_SUPPORTS_32BIT_KERNEL
>> 1642 select CPU_SUPPORTS_64BIT_KERNEL
>> 1643 select CPU_SUPPORTS_HUGEPAGES
>> 1644 help
>> 1645 QED / PMC-Sierra RM52xx-series ("Nevada") processors.
>> 1646
>> 1647 config CPU_R8000
>> 1648 bool "R8000"
>> 1649 depends on SYS_HAS_CPU_R8000
>> 1650 select CPU_HAS_PREFETCH
>> 1651 select CPU_SUPPORTS_64BIT_KERNEL
>> 1652 help
>> 1653 MIPS Technologies R8000 processors. Note these processors are
>> 1654 uncommon and the support for them is incomplete.
>> 1655
>> 1656 config CPU_R10000
>> 1657 bool "R10000"
>> 1658 depends on SYS_HAS_CPU_R10000
>> 1659 select CPU_HAS_PREFETCH
>> 1660 select CPU_SUPPORTS_32BIT_KERNEL
>> 1661 select CPU_SUPPORTS_64BIT_KERNEL
>> 1662 select CPU_SUPPORTS_HIGHMEM
>> 1663 select CPU_SUPPORTS_HUGEPAGES
>> 1664 help
>> 1665 MIPS Technologies R10000-series processors.
>> 1666
>> 1667 config CPU_RM7000
>> 1668 bool "RM7000"
>> 1669 depends on SYS_HAS_CPU_RM7000
>> 1670 select CPU_HAS_PREFETCH
>> 1671 select CPU_SUPPORTS_32BIT_KERNEL
>> 1672 select CPU_SUPPORTS_64BIT_KERNEL
>> 1673 select CPU_SUPPORTS_HIGHMEM
>> 1674 select CPU_SUPPORTS_HUGEPAGES
>> 1675
>> 1676 config CPU_SB1
>> 1677 bool "SB1"
>> 1678 depends on SYS_HAS_CPU_SB1
>> 1679 select CPU_SUPPORTS_32BIT_KERNEL
>> 1680 select CPU_SUPPORTS_64BIT_KERNEL
>> 1681 select CPU_SUPPORTS_HIGHMEM
>> 1682 select CPU_SUPPORTS_HUGEPAGES
>> 1683 select WEAK_ORDERING
>> 1684
>> 1685 config CPU_CAVIUM_OCTEON
>> 1686 bool "Cavium Octeon processor"
>> 1687 depends on SYS_HAS_CPU_CAVIUM_OCTEON
>> 1688 select CPU_HAS_PREFETCH
>> 1689 select CPU_SUPPORTS_64BIT_KERNEL
>> 1690 select WEAK_ORDERING
>> 1691 select CPU_SUPPORTS_HIGHMEM
>> 1692 select CPU_SUPPORTS_HUGEPAGES
>> 1693 select USB_EHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 1694 select USB_OHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 1695 select MIPS_L1_CACHE_SHIFT_7
>> 1696 select HAVE_KVM
>> 1697 help
>> 1698 The Cavium Octeon processor is a highly integrated chip containing
>> 1699 many ethernet hardware widgets for networking tasks. The processor
>> 1700 can have up to 16 Mips64v2 cores and 8 integrated gigabit ethernets.
>> 1701 Full details can be found at http://www.caviumnetworks.com.
>> 1702
>> 1703 config CPU_BMIPS
>> 1704 bool "Broadcom BMIPS"
>> 1705 depends on SYS_HAS_CPU_BMIPS
>> 1706 select CPU_MIPS32
>> 1707 select CPU_BMIPS32_3300 if SYS_HAS_CPU_BMIPS32_3300
>> 1708 select CPU_BMIPS4350 if SYS_HAS_CPU_BMIPS4350
>> 1709 select CPU_BMIPS4380 if SYS_HAS_CPU_BMIPS4380
>> 1710 select CPU_BMIPS5000 if SYS_HAS_CPU_BMIPS5000
>> 1711 select CPU_SUPPORTS_32BIT_KERNEL
>> 1712 select DMA_NONCOHERENT
>> 1713 select IRQ_MIPS_CPU
>> 1714 select SWAP_IO_SPACE
>> 1715 select WEAK_ORDERING
>> 1716 select CPU_SUPPORTS_HIGHMEM
>> 1717 select CPU_HAS_PREFETCH
>> 1718 select CPU_SUPPORTS_CPUFREQ
>> 1719 select MIPS_EXTERNAL_TIMER
>> 1720 help
>> 1721 Support for BMIPS32/3300/4350/4380 and BMIPS5000 processors.
>> 1722
>> 1723 config CPU_XLR
>> 1724 bool "Netlogic XLR SoC"
>> 1725 depends on SYS_HAS_CPU_XLR
>> 1726 select CPU_SUPPORTS_32BIT_KERNEL
>> 1727 select CPU_SUPPORTS_64BIT_KERNEL
>> 1728 select CPU_SUPPORTS_HIGHMEM
>> 1729 select CPU_SUPPORTS_HUGEPAGES
>> 1730 select WEAK_ORDERING
>> 1731 select WEAK_REORDERING_BEYOND_LLSC
>> 1732 help
>> 1733 Netlogic Microsystems XLR/XLS processors.
>> 1734
>> 1735 config CPU_XLP
>> 1736 bool "Netlogic XLP SoC"
>> 1737 depends on SYS_HAS_CPU_XLP
>> 1738 select CPU_SUPPORTS_32BIT_KERNEL
>> 1739 select CPU_SUPPORTS_64BIT_KERNEL
>> 1740 select CPU_SUPPORTS_HIGHMEM
>> 1741 select WEAK_ORDERING
>> 1742 select WEAK_REORDERING_BEYOND_LLSC
>> 1743 select CPU_HAS_PREFETCH
>> 1744 select CPU_MIPSR2
>> 1745 select CPU_SUPPORTS_HUGEPAGES
>> 1746 select MIPS_ASID_BITS_VARIABLE
>> 1747 help
>> 1748 Netlogic Microsystems XLP processors.
>> 1749 endchoice
979 1750
980 If unsure, say Y. !! 1751 config CPU_MIPS32_3_5_FEATURES
>> 1752 bool "MIPS32 Release 3.5 Features"
>> 1753 depends on SYS_HAS_CPU_MIPS32_R3_5
>> 1754 depends on CPU_MIPS32_R2 || CPU_MIPS32_R6
>> 1755 help
>> 1756 Choose this option to build a kernel for release 2 or later of the
>> 1757 MIPS32 architecture including features from the 3.5 release such as
>> 1758 support for Enhanced Virtual Addressing (EVA).
>> 1759
>> 1760 config CPU_MIPS32_3_5_EVA
>> 1761 bool "Enhanced Virtual Addressing (EVA)"
>> 1762 depends on CPU_MIPS32_3_5_FEATURES
>> 1763 select EVA
>> 1764 default y
>> 1765 help
>> 1766 Choose this option if you want to enable the Enhanced Virtual
>> 1767 Addressing (EVA) on your MIPS32 core (such as proAptiv).
>> 1768 One of its primary benefits is an increase in the maximum size
>> 1769 of lowmem (up to 3GB). If unsure, say 'N' here.
>> 1770
>> 1771 config CPU_MIPS32_R5_FEATURES
>> 1772 bool "MIPS32 Release 5 Features"
>> 1773 depends on SYS_HAS_CPU_MIPS32_R5
>> 1774 depends on CPU_MIPS32_R2
>> 1775 help
>> 1776 Choose this option to build a kernel for release 2 or later of the
>> 1777 MIPS32 architecture including features from release 5 such as
>> 1778 support for Extended Physical Addressing (XPA).
>> 1779
>> 1780 config CPU_MIPS32_R5_XPA
>> 1781 bool "Extended Physical Addressing (XPA)"
>> 1782 depends on CPU_MIPS32_R5_FEATURES
>> 1783 depends on !EVA
>> 1784 depends on !PAGE_SIZE_4KB
>> 1785 depends on SYS_SUPPORTS_HIGHMEM
>> 1786 select XPA
>> 1787 select HIGHMEM
>> 1788 select ARCH_PHYS_ADDR_T_64BIT
>> 1789 default n
>> 1790 help
>> 1791 Choose this option if you want to enable the Extended Physical
>> 1792 Addressing (XPA) on your MIPS32 core (such as P5600 series). The
>> 1793 benefit is to increase physical addressing equal to or greater
>> 1794 than 40 bits. Note that this has the side effect of turning on
>> 1795 64-bit addressing which in turn makes the PTEs 64-bit in size.
>> 1796 If unsure, say 'N' here.
981 1797
982 config ARM64_ERRATUM_2038923 !! 1798 if CPU_LOONGSON2F
983 bool "Cortex-A510: 2038923: workaround !! 1799 config CPU_NOP_WORKAROUNDS
984 depends on CORESIGHT_TRBE !! 1800 bool
985 default y <<
986 help <<
987 This option adds the workaround for <<
988 <<
989 Affected Cortex-A510 core might caus <<
990 prohibited within the CPU. As a resu <<
991 might be corrupted. This happens aft <<
992 TRBLIMITR_EL1.E, followed by just a <<
993 execution changes from a context, in <<
994 isn't, or vice versa. In these menti <<
995 is prohibited is inconsistent betwee <<
996 the trace buffer state might be corr <<
997 <<
998 Work around this in the driver by pr <<
999 trace is prohibited or not based on <<
1000 change to TRBLIMITR_EL1.E with at l <<
1001 two ISB instructions if no ERET is <<
1002 1801
1003 If unsure, say Y. !! 1802 config CPU_JUMP_WORKAROUNDS
>> 1803 bool
1004 1804
1005 config ARM64_ERRATUM_1902691 !! 1805 config CPU_LOONGSON2F_WORKAROUNDS
1006 bool "Cortex-A510: 1902691: workaroun !! 1806 bool "Loongson 2F Workarounds"
1007 depends on CORESIGHT_TRBE <<
1008 default y 1807 default y
>> 1808 select CPU_NOP_WORKAROUNDS
>> 1809 select CPU_JUMP_WORKAROUNDS
1009 help 1810 help
1010 This option adds the workaround for !! 1811 Loongson 2F01 / 2F02 processors have the NOP & JUMP issues which
>> 1812 require workarounds. Without workarounds the system may hang
>> 1813 unexpectedly. For more information please refer to the gas
>> 1814 -mfix-loongson2f-nop and -mfix-loongson2f-jump options.
>> 1815
>> 1816 Loongson 2F03 and later have fixed these issues and no workarounds
>> 1817 are needed. The workarounds have no significant side effect on them
>> 1818 but may decrease the performance of the system so this option should
>> 1819 be disabled unless the kernel is intended to be run on 2F01 or 2F02
>> 1820 systems.
1011 1821
1012 Affected Cortex-A510 core might cau !! 1822 If unsure, please say Y.
1013 into the memory. Effectively TRBE i !! 1823 endif # CPU_LOONGSON2F
1014 trace data. <<
1015 1824
1016 Work around this problem in the dri !! 1825 config SYS_SUPPORTS_ZBOOT
1017 affected cpus. The firmware must ha !! 1826 bool
1018 on such implementations. This will !! 1827 select HAVE_KERNEL_GZIP
1019 do this already. !! 1828 select HAVE_KERNEL_BZIP2
>> 1829 select HAVE_KERNEL_LZ4
>> 1830 select HAVE_KERNEL_LZMA
>> 1831 select HAVE_KERNEL_LZO
>> 1832 select HAVE_KERNEL_XZ
1020 1833
1021 If unsure, say Y. !! 1834 config SYS_SUPPORTS_ZBOOT_UART16550
>> 1835 bool
>> 1836 select SYS_SUPPORTS_ZBOOT
1022 1837
1023 config ARM64_ERRATUM_2457168 !! 1838 config SYS_SUPPORTS_ZBOOT_UART_PROM
1024 bool "Cortex-A510: 2457168: workaroun !! 1839 bool
1025 depends on ARM64_AMU_EXTN !! 1840 select SYS_SUPPORTS_ZBOOT
1026 default y <<
1027 help <<
1028 This option adds the workaround for <<
1029 1841
1030 The AMU counter AMEVCNTR01 (constan !! 1842 config CPU_LOONGSON2
1031 as the system counter. On affected !! 1843 bool
1032 incorrectly giving a significantly !! 1844 select CPU_SUPPORTS_32BIT_KERNEL
>> 1845 select CPU_SUPPORTS_64BIT_KERNEL
>> 1846 select CPU_SUPPORTS_HIGHMEM
>> 1847 select CPU_SUPPORTS_HUGEPAGES
1033 1848
1034 Work around this problem by returni !! 1849 config CPU_LOONGSON1
1035 key locations that results in disab !! 1850 bool
1036 is the same to firmware disabling a !! 1851 select CPU_MIPS32
>> 1852 select CPU_MIPSR2
>> 1853 select CPU_HAS_PREFETCH
>> 1854 select CPU_SUPPORTS_32BIT_KERNEL
>> 1855 select CPU_SUPPORTS_HIGHMEM
>> 1856 select CPU_SUPPORTS_CPUFREQ
1037 1857
1038 If unsure, say Y. !! 1858 config CPU_BMIPS32_3300
>> 1859 select SMP_UP if SMP
>> 1860 bool
1039 1861
1040 config ARM64_ERRATUM_2645198 !! 1862 config CPU_BMIPS4350
1041 bool "Cortex-A715: 2645198: Workaroun !! 1863 bool
1042 default y !! 1864 select SYS_SUPPORTS_SMP
1043 help !! 1865 select SYS_SUPPORTS_HOTPLUG_CPU
1044 This option adds the workaround for <<
1045 1866
1046 If a Cortex-A715 cpu sees a page ma !! 1867 config CPU_BMIPS4380
1047 to non-executable, it may corrupt t !! 1868 bool
1048 next instruction abort caused by pe !! 1869 select MIPS_L1_CACHE_SHIFT_6
>> 1870 select SYS_SUPPORTS_SMP
>> 1871 select SYS_SUPPORTS_HOTPLUG_CPU
>> 1872 select CPU_HAS_RIXI
1049 1873
1050 Only user-space does executable to !! 1874 config CPU_BMIPS5000
1051 mprotect() system call. Workaround !! 1875 bool
1052 TLB invalidation, for all changes t !! 1876 select MIPS_CPU_SCACHE
>> 1877 select MIPS_L1_CACHE_SHIFT_7
>> 1878 select SYS_SUPPORTS_SMP
>> 1879 select SYS_SUPPORTS_HOTPLUG_CPU
>> 1880 select CPU_HAS_RIXI
1053 1881
1054 If unsure, say Y. !! 1882 config SYS_HAS_CPU_LOONGSON3
>> 1883 bool
>> 1884 select CPU_SUPPORTS_CPUFREQ
>> 1885 select CPU_HAS_RIXI
1055 1886
1056 config ARM64_WORKAROUND_SPECULATIVE_UNPRIV_LO !! 1887 config SYS_HAS_CPU_LOONGSON2E
1057 bool 1888 bool
1058 1889
1059 config ARM64_ERRATUM_2966298 !! 1890 config SYS_HAS_CPU_LOONGSON2F
1060 bool "Cortex-A520: 2966298: workaroun !! 1891 bool
1061 select ARM64_WORKAROUND_SPECULATIVE_U !! 1892 select CPU_SUPPORTS_CPUFREQ
1062 default y !! 1893 select CPU_SUPPORTS_ADDRWINCFG if 64BIT
1063 help !! 1894 select CPU_SUPPORTS_UNCACHED_ACCELERATED
1064 This option adds the workaround for <<
1065 1895
1066 On an affected Cortex-A520 core, a !! 1896 config SYS_HAS_CPU_LOONGSON1B
1067 load might leak data from a privile !! 1897 bool
1068 1898
1069 Work around this problem by executi !! 1899 config SYS_HAS_CPU_LOONGSON1C
>> 1900 bool
1070 1901
1071 If unsure, say Y. !! 1902 config SYS_HAS_CPU_MIPS32_R1
>> 1903 bool
1072 1904
1073 config ARM64_ERRATUM_3117295 !! 1905 config SYS_HAS_CPU_MIPS32_R2
1074 bool "Cortex-A510: 3117295: workaroun !! 1906 bool
1075 select ARM64_WORKAROUND_SPECULATIVE_U <<
1076 default y <<
1077 help <<
1078 This option adds the workaround for <<
1079 1907
1080 On an affected Cortex-A510 core, a !! 1908 config SYS_HAS_CPU_MIPS32_R3_5
1081 load might leak data from a privile !! 1909 bool
1082 1910
1083 Work around this problem by executi !! 1911 config SYS_HAS_CPU_MIPS32_R5
>> 1912 bool
1084 1913
1085 If unsure, say Y. !! 1914 config SYS_HAS_CPU_MIPS32_R6
>> 1915 bool
1086 1916
1087 config ARM64_ERRATUM_3194386 !! 1917 config SYS_HAS_CPU_MIPS64_R1
1088 bool "Cortex-*/Neoverse-*: workaround !! 1918 bool
1089 default y <<
1090 help <<
1091 This option adds the workaround for <<
1092 1919
1093 * ARM Cortex-A76 erratum 3324349 !! 1920 config SYS_HAS_CPU_MIPS64_R2
1094 * ARM Cortex-A77 erratum 3324348 !! 1921 bool
1095 * ARM Cortex-A78 erratum 3324344 <<
1096 * ARM Cortex-A78C erratum 3324346 <<
1097 * ARM Cortex-A78C erratum 3324347 <<
1098 * ARM Cortex-A710 erratam 3324338 <<
1099 * ARM Cortex-A715 errartum 3456084 <<
1100 * ARM Cortex-A720 erratum 3456091 <<
1101 * ARM Cortex-A725 erratum 3456106 <<
1102 * ARM Cortex-X1 erratum 3324344 <<
1103 * ARM Cortex-X1C erratum 3324346 <<
1104 * ARM Cortex-X2 erratum 3324338 <<
1105 * ARM Cortex-X3 erratum 3324335 <<
1106 * ARM Cortex-X4 erratum 3194386 <<
1107 * ARM Cortex-X925 erratum 3324334 <<
1108 * ARM Neoverse-N1 erratum 3324349 <<
1109 * ARM Neoverse N2 erratum 3324339 <<
1110 * ARM Neoverse-N3 erratum 3456111 <<
1111 * ARM Neoverse-V1 erratum 3324341 <<
1112 * ARM Neoverse V2 erratum 3324336 <<
1113 * ARM Neoverse-V3 erratum 3312417 <<
1114 <<
1115 On affected cores "MSR SSBS, #0" in <<
1116 subsequent speculative instructions <<
1117 speculative store bypassing. <<
1118 <<
1119 Work around this problem by placing <<
1120 Instruction Synchronization Barrier <<
1121 SSBS. The presence of the SSBS spec <<
1122 from hwcaps and EL0 reads of ID_AA6 <<
1123 will use the PR_SPEC_STORE_BYPASS p <<
1124 1922
1125 If unsure, say Y. !! 1923 config SYS_HAS_CPU_MIPS64_R6
>> 1924 bool
1126 1925
1127 config CAVIUM_ERRATUM_22375 !! 1926 config SYS_HAS_CPU_R3000
1128 bool "Cavium erratum 22375, 24313" !! 1927 bool
1129 default y <<
1130 help <<
1131 Enable workaround for errata 22375 <<
1132 1928
1133 This implements two gicv3-its errat !! 1929 config SYS_HAS_CPU_TX39XX
1134 with a small impact affecting only !! 1930 bool
1135 1931
1136 erratum 22375: only alloc 8MB tab !! 1932 config SYS_HAS_CPU_VR41XX
1137 erratum 24313: ignore memory acce !! 1933 bool
1138 1934
1139 The fixes are in ITS initialization !! 1935 config SYS_HAS_CPU_R4300
1140 type and table size provided by the !! 1936 bool
1141 1937
1142 If unsure, say Y. !! 1938 config SYS_HAS_CPU_R4X00
>> 1939 bool
1143 1940
1144 config CAVIUM_ERRATUM_23144 !! 1941 config SYS_HAS_CPU_TX49XX
1145 bool "Cavium erratum 23144: ITS SYNC !! 1942 bool
1146 depends on NUMA <<
1147 default y <<
1148 help <<
1149 ITS SYNC command hang for cross nod <<
1150 1943
1151 If unsure, say Y. !! 1944 config SYS_HAS_CPU_R5000
>> 1945 bool
1152 1946
1153 config CAVIUM_ERRATUM_23154 !! 1947 config SYS_HAS_CPU_R5432
1154 bool "Cavium errata 23154 and 38545: !! 1948 bool
1155 default y <<
1156 help <<
1157 The ThunderX GICv3 implementation r <<
1158 reading the IAR status to ensure da <<
1159 (access to icc_iar1_el1 is not sync <<
1160 1949
1161 It also suffers from erratum 38545 !! 1950 config SYS_HAS_CPU_R5500
1162 OcteonTX and OcteonTX2), resulting !! 1951 bool
1163 spuriously presented to the CPU int <<
1164 1952
1165 If unsure, say Y. !! 1953 config SYS_HAS_CPU_R6000
>> 1954 bool
1166 1955
1167 config CAVIUM_ERRATUM_27456 !! 1956 config SYS_HAS_CPU_NEVADA
1168 bool "Cavium erratum 27456: Broadcast !! 1957 bool
1169 default y <<
1170 help <<
1171 On ThunderX T88 pass 1.x through 2. <<
1172 instructions may cause the icache t <<
1173 contains data for a non-current ASI <<
1174 invalidate the icache when changing <<
1175 1958
1176 If unsure, say Y. !! 1959 config SYS_HAS_CPU_R8000
>> 1960 bool
1177 1961
1178 config CAVIUM_ERRATUM_30115 !! 1962 config SYS_HAS_CPU_R10000
1179 bool "Cavium erratum 30115: Guest may !! 1963 bool
1180 default y <<
1181 help <<
1182 On ThunderX T88 pass 1.x through 2. <<
1183 1.2, and T83 Pass 1.0, KVM guest ex <<
1184 interrupts in host. Trapping both G <<
1185 accesses sidesteps the issue. <<
1186 1964
1187 If unsure, say Y. !! 1965 config SYS_HAS_CPU_RM7000
>> 1966 bool
1188 1967
1189 config CAVIUM_TX2_ERRATUM_219 !! 1968 config SYS_HAS_CPU_SB1
1190 bool "Cavium ThunderX2 erratum 219: P !! 1969 bool
1191 default y <<
1192 help <<
1193 On Cavium ThunderX2, a load, store <<
1194 TTBR update and the corresponding c <<
1195 cause a spurious Data Abort to be d <<
1196 the CPU core. <<
1197 <<
1198 Work around the issue by avoiding t <<
1199 trapping KVM guest TTBRx_EL1 writes <<
1200 trap handler performs the correspon <<
1201 instruction and ensures context syn <<
1202 exception return. <<
1203 1970
1204 If unsure, say Y. !! 1971 config SYS_HAS_CPU_CAVIUM_OCTEON
>> 1972 bool
1205 1973
1206 config FUJITSU_ERRATUM_010001 !! 1974 config SYS_HAS_CPU_BMIPS
1207 bool "Fujitsu-A64FX erratum E#010001: !! 1975 bool
1208 default y !! 1976
1209 help !! 1977 config SYS_HAS_CPU_BMIPS32_3300
1210 This option adds a workaround for F !! 1978 bool
1211 On some variants of the Fujitsu-A64 !! 1979 select SYS_HAS_CPU_BMIPS
1212 accesses may cause undefined fault <<
1213 This fault occurs under a specific <<
1214 load/store instruction performs an <<
1215 case-1 TTBR0_EL1 with TCR_EL1.NFD0 <<
1216 case-2 TTBR0_EL2 with TCR_EL2.NFD0 <<
1217 case-3 TTBR1_EL1 with TCR_EL1.NFD1 <<
1218 case-4 TTBR1_EL2 with TCR_EL2.NFD1 <<
1219 1980
1220 The workaround is to ensure these b !! 1981 config SYS_HAS_CPU_BMIPS4350
1221 The workaround only affects the Fuj !! 1982 bool
>> 1983 select SYS_HAS_CPU_BMIPS
1222 1984
1223 If unsure, say Y. !! 1985 config SYS_HAS_CPU_BMIPS4380
>> 1986 bool
>> 1987 select SYS_HAS_CPU_BMIPS
1224 1988
1225 config HISILICON_ERRATUM_161600802 !! 1989 config SYS_HAS_CPU_BMIPS5000
1226 bool "Hip07 161600802: Erroneous redi !! 1990 bool
1227 default y !! 1991 select SYS_HAS_CPU_BMIPS
1228 help <<
1229 The HiSilicon Hip07 SoC uses the wr <<
1230 when issued ITS commands such as VM <<
1231 a 128kB offset to be applied to the <<
1232 1992
1233 If unsure, say Y. !! 1993 config SYS_HAS_CPU_XLR
>> 1994 bool
1234 1995
1235 config QCOM_FALKOR_ERRATUM_1003 !! 1996 config SYS_HAS_CPU_XLP
1236 bool "Falkor E1003: Incorrect transla !! 1997 bool
1237 default y <<
1238 help <<
1239 On Falkor v1, an incorrect ASID may <<
1240 and BADDR are changed together in T <<
1241 in TTBR1_EL1, this situation only o <<
1242 then only for entries in the walk c <<
1243 is unchanged. Work around the errat <<
1244 entries for the trampoline before e <<
1245 1998
1246 config QCOM_FALKOR_ERRATUM_1009 !! 1999 config MIPS_MALTA_PM
1247 bool "Falkor E1009: Prematurely compl !! 2000 depends on MIPS_MALTA
>> 2001 depends on PCI
>> 2002 bool
1248 default y 2003 default y
1249 select ARM64_WORKAROUND_REPEAT_TLBI <<
1250 help <<
1251 On Falkor v1, the CPU may premature <<
1252 TLBI xxIS invalidate maintenance op <<
1253 one more time to fix the issue. <<
1254 2004
1255 If unsure, say Y. !! 2005 #
>> 2006 # CPU may reorder R->R, R->W, W->R, W->W
>> 2007 # Reordering beyond LL and SC is handled in WEAK_REORDERING_BEYOND_LLSC
>> 2008 #
>> 2009 config WEAK_ORDERING
>> 2010 bool
1256 2011
1257 config QCOM_QDF2400_ERRATUM_0065 !! 2012 #
1258 bool "QDF2400 E0065: Incorrect GITS_T !! 2013 # CPU may reorder reads and writes beyond LL/SC
1259 default y !! 2014 # CPU may reorder R->LL, R->LL, W->LL, W->LL, R->SC, R->SC, W->SC, W->SC
1260 help !! 2015 #
1261 On Qualcomm Datacenter Technologies !! 2016 config WEAK_REORDERING_BEYOND_LLSC
1262 ITE size incorrectly. The GITS_TYPE !! 2017 bool
1263 been indicated as 16Bytes (0xf), no !! 2018 endmenu
1264 2019
1265 If unsure, say Y. !! 2020 #
>> 2021 # These two indicate any level of the MIPS32 and MIPS64 architecture
>> 2022 #
>> 2023 config CPU_MIPS32
>> 2024 bool
>> 2025 default y if CPU_MIPS32_R1 || CPU_MIPS32_R2 || CPU_MIPS32_R6
1266 2026
1267 config QCOM_FALKOR_ERRATUM_E1041 !! 2027 config CPU_MIPS64
1268 bool "Falkor E1041: Speculative instr !! 2028 bool
1269 default y !! 2029 default y if CPU_MIPS64_R1 || CPU_MIPS64_R2 || CPU_MIPS64_R6
1270 help <<
1271 Falkor CPU may speculatively fetch <<
1272 memory location when MMU translatio <<
1273 to SCTLR_ELn[M]=0. Prefix an ISB in <<
1274 2030
1275 If unsure, say Y. !! 2031 #
>> 2032 # These two indicate the revision of the architecture, either Release 1 or Release 2
>> 2033 #
>> 2034 config CPU_MIPSR1
>> 2035 bool
>> 2036 default y if CPU_MIPS32_R1 || CPU_MIPS64_R1
1276 2037
1277 config NVIDIA_CARMEL_CNP_ERRATUM !! 2038 config CPU_MIPSR2
1278 bool "NVIDIA Carmel CNP: CNP on Carme !! 2039 bool
1279 default y !! 2040 default y if CPU_MIPS32_R2 || CPU_MIPS64_R2 || CPU_CAVIUM_OCTEON
1280 help !! 2041 select CPU_HAS_RIXI
1281 If CNP is enabled on Carmel cores, !! 2042 select MIPS_SPRAM
1282 invalidate shared TLB entries insta <<
1283 on standard ARM cores. <<
1284 2043
1285 If unsure, say Y. !! 2044 config CPU_MIPSR6
>> 2045 bool
>> 2046 default y if CPU_MIPS32_R6 || CPU_MIPS64_R6
>> 2047 select CPU_HAS_RIXI
>> 2048 select HAVE_ARCH_BITREVERSE
>> 2049 select MIPS_ASID_BITS_VARIABLE
>> 2050 select MIPS_SPRAM
1286 2051
1287 config ROCKCHIP_ERRATUM_3588001 !! 2052 config EVA
1288 bool "Rockchip 3588001: GIC600 can no !! 2053 bool
1289 default y <<
1290 help <<
1291 The Rockchip RK3588 GIC600 SoC inte <<
1292 This means, that its sharability fe <<
1293 is supported by the IP itself. <<
1294 2054
1295 If unsure, say Y. !! 2055 config XPA
>> 2056 bool
1296 2057
1297 config SOCIONEXT_SYNQUACER_PREITS !! 2058 config SYS_SUPPORTS_32BIT_KERNEL
1298 bool "Socionext Synquacer: Workaround !! 2059 bool
1299 default y !! 2060 config SYS_SUPPORTS_64BIT_KERNEL
1300 help !! 2061 bool
1301 Socionext Synquacer SoCs implement !! 2062 config CPU_SUPPORTS_32BIT_KERNEL
1302 MSI doorbell writes with non-zero v !! 2063 bool
>> 2064 config CPU_SUPPORTS_64BIT_KERNEL
>> 2065 bool
>> 2066 config CPU_SUPPORTS_CPUFREQ
>> 2067 bool
>> 2068 config CPU_SUPPORTS_ADDRWINCFG
>> 2069 bool
>> 2070 config CPU_SUPPORTS_HUGEPAGES
>> 2071 bool
>> 2072 config CPU_SUPPORTS_UNCACHED_ACCELERATED
>> 2073 bool
>> 2074 config MIPS_PGD_C0_CONTEXT
>> 2075 bool
>> 2076 default y if 64BIT && (CPU_MIPSR2 || CPU_MIPSR6) && !CPU_XLP
1303 2077
1304 If unsure, say Y. !! 2078 #
>> 2079 # Set to y for ptrace access to watch registers.
>> 2080 #
>> 2081 config HARDWARE_WATCHPOINTS
>> 2082 bool
>> 2083 default y if CPU_MIPSR1 || CPU_MIPSR2 || CPU_MIPSR6
1305 2084
1306 endmenu # "ARM errata workarounds via the alt !! 2085 menu "Kernel type"
1307 2086
1308 choice 2087 choice
1309 prompt "Page size" !! 2088 prompt "Kernel code model"
1310 default ARM64_4K_PAGES <<
1311 help 2089 help
1312 Page size (translation granule) con !! 2090 You should only select this option if you have a workload that
1313 !! 2091 actually benefits from 64-bit processing or if your machine has
1314 config ARM64_4K_PAGES !! 2092 large memory. You will only be presented a single option in this
1315 bool "4KB" !! 2093 menu if your system does not support both 32-bit and 64-bit kernels.
1316 select HAVE_PAGE_SIZE_4KB !! 2094
>> 2095 config 32BIT
>> 2096 bool "32-bit kernel"
>> 2097 depends on CPU_SUPPORTS_32BIT_KERNEL && SYS_SUPPORTS_32BIT_KERNEL
>> 2098 select TRAD_SIGNALS
1317 help 2099 help
1318 This feature enables 4KB pages supp !! 2100 Select this option if you want to build a 32-bit kernel.
1319 2101
1320 config ARM64_16K_PAGES !! 2102 config 64BIT
1321 bool "16KB" !! 2103 bool "64-bit kernel"
1322 select HAVE_PAGE_SIZE_16KB !! 2104 depends on CPU_SUPPORTS_64BIT_KERNEL && SYS_SUPPORTS_64BIT_KERNEL
1323 help <<
1324 The system will use 16KB pages supp <<
1325 requires applications compiled with <<
1326 aligned segments. <<
1327 <<
1328 config ARM64_64K_PAGES <<
1329 bool "64KB" <<
1330 select HAVE_PAGE_SIZE_64KB <<
1331 help 2105 help
1332 This feature enables 64KB pages sup !! 2106 Select this option if you want to build a 64-bit kernel.
1333 allowing only two levels of page ta <<
1334 look-up. AArch32 emulation requires <<
1335 with 64K aligned segments. <<
1336 2107
1337 endchoice 2108 endchoice
1338 2109
>> 2110 config KVM_GUEST
>> 2111 bool "KVM Guest Kernel"
>> 2112 depends on BROKEN_ON_SMP
>> 2113 help
>> 2114 Select this option if building a guest kernel for KVM (Trap & Emulate)
>> 2115 mode.
>> 2116
>> 2117 config KVM_GUEST_TIMER_FREQ
>> 2118 int "Count/Compare Timer Frequency (MHz)"
>> 2119 depends on KVM_GUEST
>> 2120 default 100
>> 2121 help
>> 2122 Set this to non-zero if building a guest kernel for KVM to skip RTC
>> 2123 emulation when determining guest CPU Frequency. Instead, the guest's
>> 2124 timer frequency is specified directly.
>> 2125
>> 2126 config MIPS_VA_BITS_48
>> 2127 bool "48 bits virtual memory"
>> 2128 depends on 64BIT
>> 2129 help
>> 2130 Support a maximum at least 48 bits of application virtual
>> 2131 memory. Default is 40 bits or less, depending on the CPU.
>> 2132 For page sizes 16k and above, this option results in a small
>> 2133 memory overhead for page tables. For 4k page size, a fourth
>> 2134 level of page tables is added which imposes both a memory
>> 2135 overhead as well as slower TLB fault handling.
>> 2136
>> 2137 If unsure, say N.
>> 2138
1339 choice 2139 choice
1340 prompt "Virtual address space size" !! 2140 prompt "Kernel page size"
1341 default ARM64_VA_BITS_52 !! 2141 default PAGE_SIZE_4KB
1342 help <<
1343 Allows choosing one of multiple pos <<
1344 space sizes. The level of translati <<
1345 a combination of page size and virt <<
1346 <<
1347 config ARM64_VA_BITS_36 <<
1348 bool "36-bit" if EXPERT <<
1349 depends on PAGE_SIZE_16KB <<
1350 <<
1351 config ARM64_VA_BITS_39 <<
1352 bool "39-bit" <<
1353 depends on PAGE_SIZE_4KB <<
1354 <<
1355 config ARM64_VA_BITS_42 <<
1356 bool "42-bit" <<
1357 depends on PAGE_SIZE_64KB <<
1358 <<
1359 config ARM64_VA_BITS_47 <<
1360 bool "47-bit" <<
1361 depends on PAGE_SIZE_16KB <<
1362 <<
1363 config ARM64_VA_BITS_48 <<
1364 bool "48-bit" <<
1365 <<
1366 config ARM64_VA_BITS_52 <<
1367 bool "52-bit" <<
1368 depends on ARM64_PAN || !ARM64_SW_TTB <<
1369 help <<
1370 Enable 52-bit virtual addressing fo <<
1371 requested via a hint to mmap(). The <<
1372 virtual addresses for its own mappi <<
1373 this feature is available, otherwis <<
1374 <<
1375 NOTE: Enabling 52-bit virtual addre <<
1376 ARMv8.3 Pointer Authentication will <<
1377 reduced from 7 bits to 3 bits, whic <<
1378 impact on its susceptibility to bru <<
1379 2142
1380 If unsure, select 48-bit virtual ad !! 2143 config PAGE_SIZE_4KB
>> 2144 bool "4kB"
>> 2145 depends on !CPU_LOONGSON2 && !CPU_LOONGSON3
>> 2146 help
>> 2147 This option select the standard 4kB Linux page size. On some
>> 2148 R3000-family processors this is the only available page size. Using
>> 2149 4kB page size will minimize memory consumption and is therefore
>> 2150 recommended for low memory systems.
>> 2151
>> 2152 config PAGE_SIZE_8KB
>> 2153 bool "8kB"
>> 2154 depends on CPU_R8000 || CPU_CAVIUM_OCTEON
>> 2155 depends on !MIPS_VA_BITS_48
>> 2156 help
>> 2157 Using 8kB page size will result in higher performance kernel at
>> 2158 the price of higher memory consumption. This option is available
>> 2159 only on R8000 and cnMIPS processors. Note that you will need a
>> 2160 suitable Linux distribution to support this.
>> 2161
>> 2162 config PAGE_SIZE_16KB
>> 2163 bool "16kB"
>> 2164 depends on !CPU_R3000 && !CPU_TX39XX
>> 2165 help
>> 2166 Using 16kB page size will result in higher performance kernel at
>> 2167 the price of higher memory consumption. This option is available on
>> 2168 all non-R3000 family processors. Note that you will need a suitable
>> 2169 Linux distribution to support this.
>> 2170
>> 2171 config PAGE_SIZE_32KB
>> 2172 bool "32kB"
>> 2173 depends on CPU_CAVIUM_OCTEON
>> 2174 depends on !MIPS_VA_BITS_48
>> 2175 help
>> 2176 Using 32kB page size will result in higher performance kernel at
>> 2177 the price of higher memory consumption. This option is available
>> 2178 only on cnMIPS cores. Note that you will need a suitable Linux
>> 2179 distribution to support this.
>> 2180
>> 2181 config PAGE_SIZE_64KB
>> 2182 bool "64kB"
>> 2183 depends on !CPU_R3000 && !CPU_TX39XX && !CPU_R6000
>> 2184 help
>> 2185 Using 64kB page size will result in higher performance kernel at
>> 2186 the price of higher memory consumption. This option is available on
>> 2187 all non-R3000 family processor. Not that at the time of this
>> 2188 writing this option is still high experimental.
1381 2189
1382 endchoice 2190 endchoice
1383 2191
1384 config ARM64_FORCE_52BIT !! 2192 config FORCE_MAX_ZONEORDER
1385 bool "Force 52-bit virtual addresses !! 2193 int "Maximum zone order"
1386 depends on ARM64_VA_BITS_52 && EXPERT !! 2194 range 14 64 if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_64KB
1387 help !! 2195 default "14" if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_64KB
1388 For systems with 52-bit userspace V !! 2196 range 13 64 if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_32KB
1389 to maintain compatibility with olde !! 2197 default "13" if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_32KB
1390 unless a hint is supplied to mmap. !! 2198 range 12 64 if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_16KB
1391 !! 2199 default "12" if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_16KB
1392 This configuration option disables !! 2200 range 11 64
1393 forces all userspace addresses to b !! 2201 default "11"
1394 should only enable this configurati !! 2202 help
1395 memory management code. If unsure s !! 2203 The kernel memory allocator divides physically contiguous memory
>> 2204 blocks into "zones", where each zone is a power of two number of
>> 2205 pages. This option selects the largest power of two that the kernel
>> 2206 keeps in the memory allocator. If you need to allocate very large
>> 2207 blocks of physically contiguous memory, then you may need to
>> 2208 increase this value.
1396 2209
1397 config ARM64_VA_BITS !! 2210 This config option is actually maximum order plus one. For example,
1398 int !! 2211 a value of 11 means that the largest free memory block is 2^10 pages.
1399 default 36 if ARM64_VA_BITS_36 <<
1400 default 39 if ARM64_VA_BITS_39 <<
1401 default 42 if ARM64_VA_BITS_42 <<
1402 default 47 if ARM64_VA_BITS_47 <<
1403 default 48 if ARM64_VA_BITS_48 <<
1404 default 52 if ARM64_VA_BITS_52 <<
1405 2212
1406 choice !! 2213 The page size is not necessarily 4KB. Keep this in mind
1407 prompt "Physical address space size" !! 2214 when choosing a value for this option.
1408 default ARM64_PA_BITS_48 <<
1409 help <<
1410 Choose the maximum physical address <<
1411 support. <<
1412 2215
1413 config ARM64_PA_BITS_48 !! 2216 config BOARD_SCACHE
1414 bool "48-bit" !! 2217 bool
1415 depends on ARM64_64K_PAGES || !ARM64_ <<
1416 <<
1417 config ARM64_PA_BITS_52 <<
1418 bool "52-bit" <<
1419 depends on ARM64_64K_PAGES || ARM64_V <<
1420 depends on ARM64_PAN || !ARM64_SW_TTB <<
1421 help <<
1422 Enable support for a 52-bit physica <<
1423 part of the ARMv8.2-LPA extension. <<
1424 <<
1425 With this enabled, the kernel will <<
1426 do not support ARMv8.2-LPA, but wit <<
1427 minor performance overhead). <<
1428 2218
1429 endchoice !! 2219 config IP22_CPU_SCACHE
>> 2220 bool
>> 2221 select BOARD_SCACHE
1430 2222
1431 config ARM64_PA_BITS !! 2223 #
1432 int !! 2224 # Support for a MIPS32 / MIPS64 style S-caches
1433 default 48 if ARM64_PA_BITS_48 !! 2225 #
1434 default 52 if ARM64_PA_BITS_52 !! 2226 config MIPS_CPU_SCACHE
>> 2227 bool
>> 2228 select BOARD_SCACHE
1435 2229
1436 config ARM64_LPA2 !! 2230 config R5000_CPU_SCACHE
1437 def_bool y !! 2231 bool
1438 depends on ARM64_PA_BITS_52 && !ARM64 !! 2232 select BOARD_SCACHE
1439 2233
1440 choice !! 2234 config RM7000_CPU_SCACHE
1441 prompt "Endianness" !! 2235 bool
1442 default CPU_LITTLE_ENDIAN !! 2236 select BOARD_SCACHE
1443 help <<
1444 Select the endianness of data acces <<
1445 applications will need to be compil <<
1446 that is selected here. <<
1447 2237
1448 config CPU_BIG_ENDIAN !! 2238 config SIBYTE_DMA_PAGEOPS
1449 bool "Build big-endian kernel" !! 2239 bool "Use DMA to clear/copy pages"
1450 # https://github.com/llvm/llvm-projec !! 2240 depends on CPU_SB1
1451 depends on AS_IS_GNU || AS_VERSION >= <<
1452 help 2241 help
1453 Say Y if you plan on running a kern !! 2242 Instead of using the CPU to zero and copy pages, use a Data Mover
>> 2243 channel. These DMA channels are otherwise unused by the standard
>> 2244 SiByte Linux port. Seems to give a small performance benefit.
1454 2245
1455 config CPU_LITTLE_ENDIAN !! 2246 config CPU_HAS_PREFETCH
1456 bool "Build little-endian kernel" !! 2247 bool
1457 help <<
1458 Say Y if you plan on running a kern <<
1459 This is usually the case for distri <<
1460 2248
1461 endchoice !! 2249 config CPU_GENERIC_DUMP_TLB
>> 2250 bool
>> 2251 default y if !(CPU_R3000 || CPU_R6000 || CPU_R8000 || CPU_TX39XX)
1462 2252
1463 config SCHED_MC !! 2253 config CPU_R4K_FPU
1464 bool "Multi-core scheduler support" !! 2254 bool
1465 help !! 2255 default y if !(CPU_R3000 || CPU_R6000 || CPU_TX39XX || CPU_CAVIUM_OCTEON)
1466 Multi-core scheduler support improv <<
1467 making when dealing with multi-core <<
1468 increased overhead in some places. <<
1469 2256
1470 config SCHED_CLUSTER !! 2257 config CPU_R4K_CACHE_TLB
1471 bool "Cluster scheduler support" !! 2258 bool
1472 help !! 2259 default y if !(CPU_R3000 || CPU_R8000 || CPU_SB1 || CPU_TX39XX || CPU_CAVIUM_OCTEON)
1473 Cluster scheduler support improves !! 2260
1474 making when dealing with machines t !! 2261 config MIPS_MT_SMP
1475 Cluster usually means a couple of C !! 2262 bool "MIPS MT SMP support (1 TC on each available VPE)"
1476 by sharing mid-level caches, last-l !! 2263 depends on SYS_SUPPORTS_MULTITHREADING && !CPU_MIPSR6 && !CPU_MICROMIPS
1477 busses. !! 2264 select CPU_MIPSR2_IRQ_VI
>> 2265 select CPU_MIPSR2_IRQ_EI
>> 2266 select SYNC_R4K
>> 2267 select MIPS_MT
>> 2268 select SMP
>> 2269 select SMP_UP
>> 2270 select SYS_SUPPORTS_SMP
>> 2271 select SYS_SUPPORTS_SCHED_SMT
>> 2272 select MIPS_PERF_SHARED_TC_COUNTERS
>> 2273 help
>> 2274 This is a kernel model which is known as SMVP. This is supported
>> 2275 on cores with the MT ASE and uses the available VPEs to implement
>> 2276 virtual processors which supports SMP. This is equivalent to the
>> 2277 Intel Hyperthreading feature. For further information go to
>> 2278 <http://www.imgtec.com/mips/mips-multithreading.asp>.
>> 2279
>> 2280 config MIPS_MT
>> 2281 bool
1478 2282
1479 config SCHED_SMT 2283 config SCHED_SMT
1480 bool "SMT scheduler support" !! 2284 bool "SMT (multithreading) scheduler support"
>> 2285 depends on SYS_SUPPORTS_SCHED_SMT
>> 2286 default n
1481 help 2287 help
1482 Improves the CPU scheduler's decisi !! 2288 SMT scheduler support improves the CPU scheduler's decision making
1483 MultiThreading at a cost of slightl !! 2289 when dealing with MIPS MT enabled cores at a cost of slightly
1484 places. If unsure say N here. !! 2290 increased overhead in some places. If unsure say N here.
1485 2291
1486 config NR_CPUS !! 2292 config SYS_SUPPORTS_SCHED_SMT
1487 int "Maximum number of CPUs (2-4096)" !! 2293 bool
1488 range 2 4096 <<
1489 default "512" <<
1490 2294
1491 config HOTPLUG_CPU !! 2295 config SYS_SUPPORTS_MULTITHREADING
1492 bool "Support for hot-pluggable CPUs" !! 2296 bool
1493 select GENERIC_IRQ_MIGRATION <<
1494 help <<
1495 Say Y here to experiment with turni <<
1496 can be controlled through /sys/devi <<
1497 2297
1498 # Common NUMA Features !! 2298 config MIPS_MT_FPAFF
1499 config NUMA !! 2299 bool "Dynamic FPU affinity for FP-intensive threads"
1500 bool "NUMA Memory Allocation and Sche !! 2300 default y
1501 select GENERIC_ARCH_NUMA !! 2301 depends on MIPS_MT_SMP
1502 select OF_NUMA <<
1503 select HAVE_SETUP_PER_CPU_AREA <<
1504 select NEED_PER_CPU_EMBED_FIRST_CHUNK <<
1505 select NEED_PER_CPU_PAGE_FIRST_CHUNK <<
1506 select USE_PERCPU_NUMA_NODE_ID <<
1507 help <<
1508 Enable NUMA (Non-Uniform Memory Acc <<
1509 <<
1510 The kernel will try to allocate mem <<
1511 local memory of the CPU and add som <<
1512 NUMA awareness to the kernel. <<
1513 2302
1514 config NODES_SHIFT !! 2303 config MIPSR2_TO_R6_EMULATOR
1515 int "Maximum NUMA Nodes (as a power o !! 2304 bool "MIPS R2-to-R6 emulator"
1516 range 1 10 !! 2305 depends on CPU_MIPSR6
1517 default "4" !! 2306 default y
1518 depends on NUMA <<
1519 help 2307 help
1520 Specify the maximum number of NUMA !! 2308 Choose this option if you want to run non-R6 MIPS userland code.
1521 system. Increases memory reserved !! 2309 Even if you say 'Y' here, the emulator will still be disabled by
>> 2310 default. You can enable it using the 'mipsr2emu' kernel option.
>> 2311 The only reason this is a build-time option is to save ~14K from the
>> 2312 final kernel image.
1522 2313
1523 source "kernel/Kconfig.hz" !! 2314 config MIPS_VPE_LOADER
1524 !! 2315 bool "VPE loader support."
1525 config ARCH_SPARSEMEM_ENABLE !! 2316 depends on SYS_SUPPORTS_MULTITHREADING && MODULES
1526 def_bool y !! 2317 select CPU_MIPSR2_IRQ_VI
1527 select SPARSEMEM_VMEMMAP_ENABLE !! 2318 select CPU_MIPSR2_IRQ_EI
1528 select SPARSEMEM_VMEMMAP !! 2319 select MIPS_MT
>> 2320 help
>> 2321 Includes a loader for loading an elf relocatable object
>> 2322 onto another VPE and running it.
1529 2323
1530 config HW_PERF_EVENTS !! 2324 config MIPS_VPE_LOADER_CMP
1531 def_bool y !! 2325 bool
1532 depends on ARM_PMU !! 2326 default "y"
>> 2327 depends on MIPS_VPE_LOADER && MIPS_CMP
1533 2328
1534 # Supported by clang >= 7.0 or GCC >= 12.0.0 !! 2329 config MIPS_VPE_LOADER_MT
1535 config CC_HAVE_SHADOW_CALL_STACK !! 2330 bool
1536 def_bool $(cc-option, -fsanitize=shad !! 2331 default "y"
>> 2332 depends on MIPS_VPE_LOADER && !MIPS_CMP
1537 2333
1538 config PARAVIRT !! 2334 config MIPS_VPE_LOADER_TOM
1539 bool "Enable paravirtualization code" !! 2335 bool "Load VPE program into memory hidden from linux"
>> 2336 depends on MIPS_VPE_LOADER
>> 2337 default y
1540 help 2338 help
1541 This changes the kernel so it can m !! 2339 The loader can use memory that is present but has been hidden from
1542 under a hypervisor, potentially imp !! 2340 Linux using the kernel command line option "mem=xxMB". It's up to
1543 over full virtualization. !! 2341 you to ensure the amount you put in the option and the space your
>> 2342 program requires is less or equal to the amount physically present.
1544 2343
1545 config PARAVIRT_TIME_ACCOUNTING !! 2344 config MIPS_VPE_APSP_API
1546 bool "Paravirtual steal time accounti !! 2345 bool "Enable support for AP/SP API (RTLX)"
1547 select PARAVIRT !! 2346 depends on MIPS_VPE_LOADER
1548 help 2347 help
1549 Select this option to enable fine g <<
1550 accounting. Time spent executing ot <<
1551 the current vCPU is discounted from <<
1552 that, there can be a small performa <<
1553 <<
1554 If in doubt, say N here. <<
1555 2348
1556 config ARCH_SUPPORTS_KEXEC !! 2349 config MIPS_VPE_APSP_API_CMP
1557 def_bool PM_SLEEP_SMP !! 2350 bool
>> 2351 default "y"
>> 2352 depends on MIPS_VPE_APSP_API && MIPS_CMP
1558 2353
1559 config ARCH_SUPPORTS_KEXEC_FILE !! 2354 config MIPS_VPE_APSP_API_MT
1560 def_bool y !! 2355 bool
>> 2356 default "y"
>> 2357 depends on MIPS_VPE_APSP_API && !MIPS_CMP
1561 2358
1562 config ARCH_SELECTS_KEXEC_FILE !! 2359 config MIPS_CMP
1563 def_bool y !! 2360 bool "MIPS CMP framework support (DEPRECATED)"
1564 depends on KEXEC_FILE !! 2361 depends on SYS_SUPPORTS_MIPS_CMP && !CPU_MIPSR6
1565 select HAVE_IMA_KEXEC if IMA !! 2362 select SMP
>> 2363 select SYNC_R4K
>> 2364 select SYS_SUPPORTS_SMP
>> 2365 select WEAK_ORDERING
>> 2366 default n
>> 2367 help
>> 2368 Select this if you are using a bootloader which implements the "CMP
>> 2369 framework" protocol (ie. YAMON) and want your kernel to make use of
>> 2370 its ability to start secondary CPUs.
>> 2371
>> 2372 Unless you have a specific need, you should use CONFIG_MIPS_CPS
>> 2373 instead of this.
>> 2374
>> 2375 config MIPS_CPS
>> 2376 bool "MIPS Coherent Processing System support"
>> 2377 depends on SYS_SUPPORTS_MIPS_CPS
>> 2378 select MIPS_CM
>> 2379 select MIPS_CPC
>> 2380 select MIPS_CPS_PM if HOTPLUG_CPU
>> 2381 select SMP
>> 2382 select SYNC_R4K if (CEVT_R4K || CSRC_R4K)
>> 2383 select SYS_SUPPORTS_HOTPLUG_CPU
>> 2384 select SYS_SUPPORTS_SCHED_SMT if CPU_MIPSR6
>> 2385 select SYS_SUPPORTS_SMP
>> 2386 select WEAK_ORDERING
>> 2387 help
>> 2388 Select this if you wish to run an SMP kernel across multiple cores
>> 2389 within a MIPS Coherent Processing System. When this option is
>> 2390 enabled the kernel will probe for other cores and boot them with
>> 2391 no external assistance. It is safe to enable this when hardware
>> 2392 support is unavailable.
>> 2393
>> 2394 config MIPS_CPS_PM
>> 2395 depends on MIPS_CPS
>> 2396 select MIPS_CPC
>> 2397 bool
1566 2398
1567 config ARCH_SUPPORTS_KEXEC_SIG !! 2399 config MIPS_CM
1568 def_bool y !! 2400 bool
1569 2401
1570 config ARCH_SUPPORTS_KEXEC_IMAGE_VERIFY_SIG !! 2402 config MIPS_CPC
1571 def_bool y !! 2403 bool
1572 2404
1573 config ARCH_DEFAULT_KEXEC_IMAGE_VERIFY_SIG !! 2405 config SB1_PASS_2_WORKAROUNDS
1574 def_bool y !! 2406 bool
>> 2407 depends on CPU_SB1 && (CPU_SB1_PASS_2_2 || CPU_SB1_PASS_2)
>> 2408 default y
1575 2409
1576 config ARCH_SUPPORTS_CRASH_DUMP !! 2410 config SB1_PASS_2_1_WORKAROUNDS
1577 def_bool y !! 2411 bool
>> 2412 depends on CPU_SB1 && CPU_SB1_PASS_2
>> 2413 default y
1578 2414
1579 config ARCH_HAS_GENERIC_CRASHKERNEL_RESERVATI <<
1580 def_bool CRASH_RESERVE <<
1581 2415
1582 config TRANS_TABLE !! 2416 config ARCH_PHYS_ADDR_T_64BIT
1583 def_bool y !! 2417 bool
1584 depends on HIBERNATION || KEXEC_CORE <<
1585 2418
1586 config XEN_DOM0 !! 2419 choice
1587 def_bool y !! 2420 prompt "SmartMIPS or microMIPS ASE support"
1588 depends on XEN <<
1589 2421
1590 config XEN !! 2422 config CPU_NEEDS_NO_SMARTMIPS_OR_MICROMIPS
1591 bool "Xen guest support on ARM64" !! 2423 bool "None"
1592 depends on ARM64 && OF <<
1593 select SWIOTLB_XEN <<
1594 select PARAVIRT <<
1595 help 2424 help
1596 Say Y if you want to run Linux in a !! 2425 Select this if you want neither microMIPS nor SmartMIPS support
1597 2426
1598 # include/linux/mmzone.h requires the followi !! 2427 config CPU_HAS_SMARTMIPS
1599 # !! 2428 depends on SYS_SUPPORTS_SMARTMIPS
1600 # MAX_PAGE_ORDER + PAGE_SHIFT <= SECTION_SI !! 2429 bool "SmartMIPS"
1601 # !! 2430 help
1602 # so the maximum value of MAX_PAGE_ORDER is S !! 2431 SmartMIPS is a extension of the MIPS32 architecture aimed at
1603 # !! 2432 increased security at both hardware and software level for
1604 # | SECTION_SIZE_BITS | PAGE_SHIFT | m !! 2433 smartcards. Enabling this option will allow proper use of the
1605 # ----+-------------------+--------------+--- !! 2434 SmartMIPS instructions by Linux applications. However a kernel with
1606 # 4K | 27 | 12 | !! 2435 this option will not work on a MIPS core without SmartMIPS core. If
1607 # 16K | 27 | 14 | !! 2436 you don't know you probably don't have SmartMIPS and should say N
1608 # 64K | 29 | 16 | !! 2437 here.
1609 config ARCH_FORCE_MAX_ORDER !! 2438
1610 int !! 2439 config CPU_MICROMIPS
1611 default "13" if ARM64_64K_PAGES !! 2440 depends on 32BIT && SYS_SUPPORTS_MICROMIPS && !CPU_MIPSR6
1612 default "11" if ARM64_16K_PAGES !! 2441 bool "microMIPS"
1613 default "10" <<
1614 help 2442 help
1615 The kernel page allocator limits th !! 2443 When this option is enabled the kernel will be built using the
1616 contiguous allocations. The limit i !! 2444 microMIPS ISA
1617 defines the maximal power of two of <<
1618 allocated as a single contiguous bl <<
1619 overriding the default setting when <<
1620 large blocks of physically contiguo <<
1621 <<
1622 The maximal size of allocation cann <<
1623 section, so the value of MAX_PAGE_O <<
1624 2445
1625 MAX_PAGE_ORDER + PAGE_SHIFT <= SE !! 2446 endchoice
1626 <<
1627 Don't change if unsure. <<
1628 2447
1629 config UNMAP_KERNEL_AT_EL0 !! 2448 config CPU_HAS_MSA
1630 bool "Unmap kernel when running in us !! 2449 bool "Support for the MIPS SIMD Architecture"
1631 default y !! 2450 depends on CPU_SUPPORTS_MSA
1632 help !! 2451 depends on 64BIT || MIPS_O32_FP64_SUPPORT
1633 Speculation attacks against some hi !! 2452 help
1634 be used to bypass MMU permission ch !! 2453 MIPS SIMD Architecture (MSA) introduces 128 bit wide vector registers
1635 userspace. This can be defended aga !! 2454 and a set of SIMD instructions to operate on them. When this option
1636 when running in userspace, mapping !! 2455 is enabled the kernel will support allocating & switching MSA
1637 via a trampoline page in the vector !! 2456 vector register contexts. If you know that your kernel will only be
>> 2457 running on CPUs which do not support MSA or that your userland will
>> 2458 not be making use of it then you may wish to say N here to reduce
>> 2459 the size & complexity of your kernel.
1638 2460
1639 If unsure, say Y. 2461 If unsure, say Y.
1640 2462
1641 config MITIGATE_SPECTRE_BRANCH_HISTORY !! 2463 config CPU_HAS_WB
1642 bool "Mitigate Spectre style attacks !! 2464 bool
1643 default y <<
1644 help <<
1645 Speculation attacks against some hi <<
1646 make use of branch history to influ <<
1647 When taking an exception from user- <<
1648 or a firmware call overwrites the b <<
1649 2465
1650 config RODATA_FULL_DEFAULT_ENABLED !! 2466 config XKS01
1651 bool "Apply r/o permissions of VM are !! 2467 bool
1652 default y !! 2468
1653 help !! 2469 config CPU_HAS_RIXI
1654 Apply read-only attributes of VM ar !! 2470 bool
1655 the backing pages as well. This pre <<
1656 from being modified (inadvertently <<
1657 mapping of the same memory page. Th <<
1658 be turned off at runtime by passing <<
1659 with rodata=full if this option is <<
1660 2471
1661 This requires the linear region to !! 2472 #
1662 which may adversely affect performa !! 2473 # Vectored interrupt mode is an R2 feature
>> 2474 #
>> 2475 config CPU_MIPSR2_IRQ_VI
>> 2476 bool
1663 2477
1664 config ARM64_SW_TTBR0_PAN !! 2478 #
1665 bool "Emulate Privileged Access Never !! 2479 # Extended interrupt mode is an R2 feature
1666 depends on !KCSAN !! 2480 #
1667 help !! 2481 config CPU_MIPSR2_IRQ_EI
1668 Enabling this option prevents the k !! 2482 bool
1669 user-space memory directly by point <<
1670 zeroed area and reserved ASID. The <<
1671 restore the valid TTBR0_EL1 tempora <<
1672 2483
1673 config ARM64_TAGGED_ADDR_ABI !! 2484 config CPU_HAS_SYNC
1674 bool "Enable the tagged user addresse !! 2485 bool
>> 2486 depends on !CPU_R3000
1675 default y 2487 default y
1676 help <<
1677 When this option is enabled, user a <<
1678 relaxed ABI via prctl() allowing ta <<
1679 to system calls as pointer argument <<
1680 Documentation/arch/arm64/tagged-add <<
1681 <<
1682 menuconfig COMPAT <<
1683 bool "Kernel support for 32-bit EL0" <<
1684 depends on ARM64_4K_PAGES || EXPERT <<
1685 select HAVE_UID16 <<
1686 select OLD_SIGSUSPEND3 <<
1687 select COMPAT_OLD_SIGACTION <<
1688 help <<
1689 This option enables support for a 3 <<
1690 kernel at EL1. AArch32-specific com <<
1691 the user helper functions, VFP supp <<
1692 handled appropriately by the kernel <<
1693 2488
1694 If you use a page size other than 4 !! 2489 #
1695 that you will only be able to execu !! 2490 # CPU non-features
1696 with page size aligned segments. !! 2491 #
>> 2492 config CPU_DADDI_WORKAROUNDS
>> 2493 bool
1697 2494
1698 If you want to execute 32-bit users !! 2495 config CPU_R4000_WORKAROUNDS
>> 2496 bool
>> 2497 select CPU_R4400_WORKAROUNDS
1699 2498
1700 if COMPAT !! 2499 config CPU_R4400_WORKAROUNDS
>> 2500 bool
1701 2501
1702 config KUSER_HELPERS !! 2502 config MIPS_ASID_SHIFT
1703 bool "Enable kuser helpers page for 3 !! 2503 int
1704 default y !! 2504 default 6 if CPU_R3000 || CPU_TX39XX
1705 help !! 2505 default 4 if CPU_R8000
1706 Warning: disabling this option may !! 2506 default 0
1707 2507
1708 Provide kuser helpers to compat tas !! 2508 config MIPS_ASID_BITS
1709 helper code to userspace in read on !! 2509 int
1710 to allow userspace to be independen !! 2510 default 0 if MIPS_ASID_BITS_VARIABLE
1711 the system. This permits binaries t !! 2511 default 6 if CPU_R3000 || CPU_TX39XX
1712 to ARMv8 without modification. !! 2512 default 8
1713 2513
1714 See Documentation/arch/arm/kernel_u !! 2514 config MIPS_ASID_BITS_VARIABLE
>> 2515 bool
1715 2516
1716 However, the fixed address nature o !! 2517 #
1717 by ROP (return orientated programmi !! 2518 # - Highmem only makes sense for the 32-bit kernel.
1718 exploits. !! 2519 # - The current highmem code will only work properly on physically indexed
>> 2520 # caches such as R3000, SB1, R7000 or those that look like they're virtually
>> 2521 # indexed such as R4000/R4400 SC and MC versions or R10000. So for the
>> 2522 # moment we protect the user and offer the highmem option only on machines
>> 2523 # where it's known to be safe. This will not offer highmem on a few systems
>> 2524 # such as MIPS32 and MIPS64 CPUs which may have virtual and physically
>> 2525 # indexed CPUs but we're playing safe.
>> 2526 # - We use SYS_SUPPORTS_HIGHMEM to offer highmem only for systems where we
>> 2527 # know they might have memory configurations that could make use of highmem
>> 2528 # support.
>> 2529 #
>> 2530 config HIGHMEM
>> 2531 bool "High Memory Support"
>> 2532 depends on 32BIT && CPU_SUPPORTS_HIGHMEM && SYS_SUPPORTS_HIGHMEM && !CPU_MIPS32_3_5_EVA
1719 2533
1720 If all of the binaries and librarie !! 2534 config CPU_SUPPORTS_HIGHMEM
1721 are built specifically for your pla !! 2535 bool
1722 these helpers, then you can turn th <<
1723 such exploits. However, in that cas <<
1724 relying on those helpers is run, it <<
1725 2536
1726 Say N here only if you are absolute !! 2537 config SYS_SUPPORTS_HIGHMEM
1727 need these helpers; otherwise, the !! 2538 bool
1728 2539
1729 config COMPAT_VDSO !! 2540 config SYS_SUPPORTS_SMARTMIPS
1730 bool "Enable vDSO for 32-bit applicat !! 2541 bool
1731 depends on !CPU_BIG_ENDIAN <<
1732 depends on (CC_IS_CLANG && LD_IS_LLD) <<
1733 select GENERIC_COMPAT_VDSO <<
1734 default y <<
1735 help <<
1736 Place in the process address space <<
1737 ELF shared object providing fast im <<
1738 and clock_gettime. <<
1739 2542
1740 You must have a 32-bit build of gli !! 2543 config SYS_SUPPORTS_MICROMIPS
1741 to seamlessly take advantage of thi !! 2544 bool
1742 2545
1743 config THUMB2_COMPAT_VDSO !! 2546 config SYS_SUPPORTS_MIPS16
1744 bool "Compile the 32-bit vDSO for Thu !! 2547 bool
1745 depends on COMPAT_VDSO <<
1746 default y <<
1747 help 2548 help
1748 Compile the compat vDSO with '-mthu !! 2549 This option must be set if a kernel might be executed on a MIPS16-
1749 otherwise with '-marm'. !! 2550 enabled CPU even if MIPS16 is not actually being used. In other
1750 !! 2551 words, it makes the kernel MIPS16-tolerant.
1751 config COMPAT_ALIGNMENT_FIXUPS <<
1752 bool "Fix up misaligned multi-word lo <<
1753 2552
1754 menuconfig ARMV8_DEPRECATED !! 2553 config CPU_SUPPORTS_MSA
1755 bool "Emulate deprecated/obsolete ARM !! 2554 bool
1756 depends on SYSCTL <<
1757 help <<
1758 Legacy software support may require <<
1759 that have been deprecated or obsole <<
1760 2555
1761 Enable this config to enable select !! 2556 config ARCH_FLATMEM_ENABLE
1762 features. !! 2557 def_bool y
>> 2558 depends on !NUMA && !CPU_LOONGSON2
1763 2559
1764 If unsure, say Y !! 2560 config ARCH_DISCONTIGMEM_ENABLE
>> 2561 bool
>> 2562 default y if SGI_IP27
>> 2563 help
>> 2564 Say Y to support efficient handling of discontiguous physical memory,
>> 2565 for architectures which are either NUMA (Non-Uniform Memory Access)
>> 2566 or have huge holes in the physical address space for other reasons.
>> 2567 See <file:Documentation/vm/numa> for more.
1765 2568
1766 if ARMV8_DEPRECATED !! 2569 config ARCH_SPARSEMEM_ENABLE
>> 2570 bool
>> 2571 select SPARSEMEM_STATIC
1767 2572
1768 config SWP_EMULATION !! 2573 config NUMA
1769 bool "Emulate SWP/SWPB instructions" !! 2574 bool "NUMA Support"
>> 2575 depends on SYS_SUPPORTS_NUMA
1770 help 2576 help
1771 ARMv8 obsoletes the use of A32 SWP/ !! 2577 Say Y to compile the kernel to support NUMA (Non-Uniform Memory
1772 they are always undefined. Say Y he !! 2578 Access). This option improves performance on systems with more
1773 emulation of these instructions for !! 2579 than two nodes; on two node systems it is generally better to
1774 This feature can be controlled at r !! 2580 leave it disabled; on single node systems disable this option
1775 sysctl which is disabled by default !! 2581 disabled.
1776 2582
1777 In some older versions of glibc [<= !! 2583 config SYS_SUPPORTS_NUMA
1778 trylock() operations with the assum !! 2584 bool
1779 be preempted. This invalid assumpti <<
1780 with SWP emulation enabled, leading <<
1781 application. <<
1782 2585
1783 NOTE: when accessing uncached share !! 2586 config RELOCATABLE
1784 on an external transaction monitori !! 2587 bool "Relocatable kernel"
1785 monitor to maintain update atomicit !! 2588 depends on SYS_SUPPORTS_RELOCATABLE && (CPU_MIPS32_R2 || CPU_MIPS64_R2 || CPU_MIPS32_R6 || CPU_MIPS64_R6 || CAVIUM_OCTEON_SOC)
1786 implement a global monitor, this op !! 2589 help
1787 perform SWP operations to uncached !! 2590 This builds a kernel image that retains relocation information
>> 2591 so it can be loaded someplace besides the default 1MB.
>> 2592 The relocations make the kernel binary about 15% larger,
>> 2593 but are discarded at runtime
>> 2594
>> 2595 config RELOCATION_TABLE_SIZE
>> 2596 hex "Relocation table size"
>> 2597 depends on RELOCATABLE
>> 2598 range 0x0 0x01000000
>> 2599 default "0x00100000"
>> 2600 ---help---
>> 2601 A table of relocation data will be appended to the kernel binary
>> 2602 and parsed at boot to fix up the relocated kernel.
1788 2603
1789 If unsure, say Y !! 2604 This option allows the amount of space reserved for the table to be
>> 2605 adjusted, although the default of 1Mb should be ok in most cases.
1790 2606
1791 config CP15_BARRIER_EMULATION !! 2607 The build will fail and a valid size suggested if this is too small.
1792 bool "Emulate CP15 Barrier instructio <<
1793 help <<
1794 The CP15 barrier instructions - CP1 <<
1795 CP15DMB - are deprecated in ARMv8 ( <<
1796 strongly recommended to use the ISB <<
1797 instructions instead. <<
1798 2608
1799 Say Y here to enable software emula !! 2609 If unsure, leave at the default value.
1800 instructions for AArch32 userspace <<
1801 enabled, CP15 barrier usage is trac <<
1802 identify software that needs updati <<
1803 controlled at runtime with the abi. <<
1804 2610
1805 If unsure, say Y !! 2611 config RANDOMIZE_BASE
>> 2612 bool "Randomize the address of the kernel image"
>> 2613 depends on RELOCATABLE
>> 2614 ---help---
>> 2615 Randomizes the physical and virtual address at which the
>> 2616 kernel image is loaded, as a security feature that
>> 2617 deters exploit attempts relying on knowledge of the location
>> 2618 of kernel internals.
1806 2619
1807 config SETEND_EMULATION !! 2620 Entropy is generated using any coprocessor 0 registers available.
1808 bool "Emulate SETEND instruction" <<
1809 help <<
1810 The SETEND instruction alters the d <<
1811 AArch32 EL0, and is deprecated in A <<
1812 2621
1813 Say Y here to enable software emula !! 2622 The kernel will be offset by up to RANDOMIZE_BASE_MAX_OFFSET.
1814 for AArch32 userspace code. This fe <<
1815 at runtime with the abi.setend sysc <<
1816 2623
1817 Note: All the cpus on the system mu !! 2624 If unsure, say N.
1818 for this feature to be enabled. If <<
1819 endian - is hotplugged in after thi <<
1820 be unexpected results in the applic <<
1821 2625
1822 If unsure, say Y !! 2626 config RANDOMIZE_BASE_MAX_OFFSET
1823 endif # ARMV8_DEPRECATED !! 2627 hex "Maximum kASLR offset" if EXPERT
>> 2628 depends on RANDOMIZE_BASE
>> 2629 range 0x0 0x40000000 if EVA || 64BIT
>> 2630 range 0x0 0x08000000
>> 2631 default "0x01000000"
>> 2632 ---help---
>> 2633 When kASLR is active, this provides the maximum offset that will
>> 2634 be applied to the kernel image. It should be set according to the
>> 2635 amount of physical RAM available in the target system minus
>> 2636 PHYSICAL_START and must be a power of 2.
1824 2637
1825 endif # COMPAT !! 2638 This is limited by the size of KSEG0, 256Mb on 32-bit or 1Gb with
>> 2639 EVA or 64-bit. The default is 16Mb.
1826 2640
1827 menu "ARMv8.1 architectural features" !! 2641 config NODES_SHIFT
>> 2642 int
>> 2643 default "6"
>> 2644 depends on NEED_MULTIPLE_NODES
1828 2645
1829 config ARM64_HW_AFDBM !! 2646 config HW_PERF_EVENTS
1830 bool "Support for hardware updates of !! 2647 bool "Enable hardware performance counter support for perf events"
>> 2648 depends on PERF_EVENTS && !OPROFILE && (CPU_MIPS32 || CPU_MIPS64 || CPU_R10000 || CPU_SB1 || CPU_CAVIUM_OCTEON || CPU_XLP || CPU_LOONGSON3)
1831 default y 2649 default y
1832 help 2650 help
1833 The ARMv8.1 architecture extensions !! 2651 Enable hardware performance counter support for perf events. If
1834 hardware updates of the access and !! 2652 disabled, perf events will use software events only.
1835 table entries. When enabled in TCR_ <<
1836 capable processors, accesses to pag <<
1837 set this bit instead of raising an <<
1838 Similarly, writes to read-only page <<
1839 clear the read-only bit (AP[2]) ins <<
1840 permission fault. <<
1841 2653
1842 Kernels built with this configurati !! 2654 source "mm/Kconfig"
1843 to work on pre-ARMv8.1 hardware and <<
1844 minimal. If unsure, say Y. <<
1845 2655
1846 config ARM64_PAN !! 2656 config SMP
1847 bool "Enable support for Privileged A !! 2657 bool "Multi-Processing support"
1848 default y !! 2658 depends on SYS_SUPPORTS_SMP
1849 help 2659 help
1850 Privileged Access Never (PAN; part !! 2660 This enables support for systems with more than one CPU. If you have
1851 prevents the kernel or hypervisor f !! 2661 a system with only one CPU, say N. If you have a system with more
1852 memory directly. !! 2662 than one CPU, say Y.
1853 !! 2663
1854 Choosing this option will cause any !! 2664 If you say N here, the kernel will run on uni- and multiprocessor
1855 copy_to_user et al) memory access t !! 2665 machines, but will use only one CPU of a multiprocessor machine. If
>> 2666 you say Y here, the kernel will run on many, but not all,
>> 2667 uniprocessor machines. On a uniprocessor machine, the kernel
>> 2668 will run faster if you say N here.
1856 2669
1857 The feature is detected at runtime, !! 2670 People using multiprocessor machines who say Y here should also say
1858 instruction if the cpu does not imp !! 2671 Y to "Enhanced Real Time Clock Support", below.
1859 2672
1860 config AS_HAS_LSE_ATOMICS !! 2673 See also the SMP-HOWTO available at
1861 def_bool $(as-instr,.arch_extension l !! 2674 <http://www.tldp.org/docs.html#howto>.
1862 2675
1863 config ARM64_LSE_ATOMICS !! 2676 If you don't know what to do here, say N.
1864 bool <<
1865 default ARM64_USE_LSE_ATOMICS <<
1866 depends on AS_HAS_LSE_ATOMICS <<
1867 2677
1868 config ARM64_USE_LSE_ATOMICS !! 2678 config HOTPLUG_CPU
1869 bool "Atomic instructions" !! 2679 bool "Support for hot-pluggable CPUs"
1870 default y !! 2680 depends on SMP && SYS_SUPPORTS_HOTPLUG_CPU
1871 help 2681 help
1872 As part of the Large System Extensi !! 2682 Say Y here to allow turning CPUs off and on. CPUs can be
1873 atomic instructions that are design !! 2683 controlled through /sys/devices/system/cpu.
1874 very large systems. !! 2684 (Note: power management support will enable this option
1875 !! 2685 automatically on SMP systems. )
1876 Say Y here to make use of these ins !! 2686 Say N if you want to disable CPU hotplug.
1877 atomic routines. This incurs a smal <<
1878 not support these instructions and <<
1879 built with binutils >= 2.25 in orde <<
1880 to be used. <<
1881 <<
1882 endmenu # "ARMv8.1 architectural features" <<
1883 2687
1884 menu "ARMv8.2 architectural features" !! 2688 config SMP_UP
>> 2689 bool
1885 2690
1886 config AS_HAS_ARMV8_2 !! 2691 config SYS_SUPPORTS_MIPS_CMP
1887 def_bool $(cc-option,-Wa$(comma)-marc !! 2692 bool
1888 2693
1889 config AS_HAS_SHA3 !! 2694 config SYS_SUPPORTS_MIPS_CPS
1890 def_bool $(as-instr,.arch armv8.2-a+s !! 2695 bool
1891 2696
1892 config ARM64_PMEM !! 2697 config SYS_SUPPORTS_SMP
1893 bool "Enable support for persistent m !! 2698 bool
1894 select ARCH_HAS_PMEM_API <<
1895 select ARCH_HAS_UACCESS_FLUSHCACHE <<
1896 help <<
1897 Say Y to enable support for the per <<
1898 ARMv8.2 DCPoP feature. <<
1899 2699
1900 The feature is detected at runtime, !! 2700 config NR_CPUS_DEFAULT_4
1901 operations if DC CVAP is not suppor !! 2701 bool
1902 DC CVAP itself if the system does n <<
1903 2702
1904 config ARM64_RAS_EXTN !! 2703 config NR_CPUS_DEFAULT_8
1905 bool "Enable support for RAS CPU Exte !! 2704 bool
1906 default y <<
1907 help <<
1908 CPUs that support the Reliability, <<
1909 (RAS) Extensions, part of ARMv8.2 a <<
1910 errors, classify them and report th <<
1911 2705
1912 On CPUs with these extensions syste !! 2706 config NR_CPUS_DEFAULT_16
1913 barriers to determine if faults are !! 2707 bool
1914 classification from a new set of re <<
1915 2708
1916 Selecting this feature will allow t !! 2709 config NR_CPUS_DEFAULT_32
1917 and access the new registers if the !! 2710 bool
1918 Platform RAS features may additiona <<
1919 2711
1920 config ARM64_CNP !! 2712 config NR_CPUS_DEFAULT_64
1921 bool "Enable support for Common Not P !! 2713 bool
1922 default y <<
1923 depends on ARM64_PAN || !ARM64_SW_TTB <<
1924 help <<
1925 Common Not Private (CNP) allows tra <<
1926 be shared between different PEs in <<
1927 domain, so the hardware can use thi <<
1928 caching of such entries in the TLB. <<
1929 2714
1930 Selecting this option allows the CN !! 2715 config NR_CPUS
1931 at runtime, and does not affect PEs !! 2716 int "Maximum number of CPUs (2-256)"
1932 this feature. !! 2717 range 2 256
>> 2718 depends on SMP
>> 2719 default "4" if NR_CPUS_DEFAULT_4
>> 2720 default "8" if NR_CPUS_DEFAULT_8
>> 2721 default "16" if NR_CPUS_DEFAULT_16
>> 2722 default "32" if NR_CPUS_DEFAULT_32
>> 2723 default "64" if NR_CPUS_DEFAULT_64
>> 2724 help
>> 2725 This allows you to specify the maximum number of CPUs which this
>> 2726 kernel will support. The maximum supported value is 32 for 32-bit
>> 2727 kernel and 64 for 64-bit kernels; the minimum value which makes
>> 2728 sense is 1 for Qemu (useful only for kernel debugging purposes)
>> 2729 and 2 for all others.
>> 2730
>> 2731 This is purely to save memory - each supported CPU adds
>> 2732 approximately eight kilobytes to the kernel image. For best
>> 2733 performance should round up your number of processors to the next
>> 2734 power of two.
1933 2735
1934 endmenu # "ARMv8.2 architectural features" !! 2736 config MIPS_PERF_SHARED_TC_COUNTERS
>> 2737 bool
1935 2738
1936 menu "ARMv8.3 architectural features" !! 2739 #
>> 2740 # Timer Interrupt Frequency Configuration
>> 2741 #
1937 2742
1938 config ARM64_PTR_AUTH !! 2743 choice
1939 bool "Enable support for pointer auth !! 2744 prompt "Timer frequency"
1940 default y !! 2745 default HZ_250
1941 help 2746 help
1942 Pointer authentication (part of the !! 2747 Allows the configuration of the timer frequency.
1943 instructions for signing and authen <<
1944 keys, which can be used to mitigate <<
1945 and other attacks. <<
1946 2748
1947 This option enables these instructi !! 2749 config HZ_24
1948 Choosing this option will cause the !! 2750 bool "24 HZ" if SYS_SUPPORTS_24HZ || SYS_SUPPORTS_ARBIT_HZ
1949 for each process at exec() time, wi <<
1950 context-switched along with the pro <<
1951 2751
1952 The feature is detected at runtime. !! 2752 config HZ_48
1953 hardware it will not be advertised !! 2753 bool "48 HZ" if SYS_SUPPORTS_48HZ || SYS_SUPPORTS_ARBIT_HZ
1954 be enabled. <<
1955 2754
1956 If the feature is present on the bo !! 2755 config HZ_100
1957 the late CPU will be parked. Also, !! 2756 bool "100 HZ" if SYS_SUPPORTS_100HZ || SYS_SUPPORTS_ARBIT_HZ
1958 address auth and the late CPU has t <<
1959 but with the feature disabled. On s <<
1960 not be selected. <<
1961 2757
1962 config ARM64_PTR_AUTH_KERNEL !! 2758 config HZ_128
1963 bool "Use pointer authentication for !! 2759 bool "128 HZ" if SYS_SUPPORTS_128HZ || SYS_SUPPORTS_ARBIT_HZ
1964 default y <<
1965 depends on ARM64_PTR_AUTH <<
1966 depends on (CC_HAS_SIGN_RETURN_ADDRES <<
1967 # Modern compilers insert a .note.gnu <<
1968 # which is only understood by binutil <<
1969 depends on LD_IS_LLD || LD_VERSION >= <<
1970 depends on !CC_IS_CLANG || AS_HAS_CFI <<
1971 depends on (!FUNCTION_GRAPH_TRACER || <<
1972 help <<
1973 If the compiler supports the -mbran <<
1974 -msign-return-address flag (e.g. GC <<
1975 will cause the kernel itself to be <<
1976 protection. In this case, and if th <<
1977 support pointer authentication, the <<
1978 disabled with minimal loss of prote <<
1979 2760
1980 This feature works with FUNCTION_GR !! 2761 config HZ_250
1981 DYNAMIC_FTRACE_WITH_ARGS is enabled !! 2762 bool "250 HZ" if SYS_SUPPORTS_250HZ || SYS_SUPPORTS_ARBIT_HZ
1982 2763
1983 config CC_HAS_BRANCH_PROT_PAC_RET !! 2764 config HZ_256
1984 # GCC 9 or later, clang 8 or later !! 2765 bool "256 HZ" if SYS_SUPPORTS_256HZ || SYS_SUPPORTS_ARBIT_HZ
1985 def_bool $(cc-option,-mbranch-protect <<
1986 2766
1987 config CC_HAS_SIGN_RETURN_ADDRESS !! 2767 config HZ_1000
1988 # GCC 7, 8 !! 2768 bool "1000 HZ" if SYS_SUPPORTS_1000HZ || SYS_SUPPORTS_ARBIT_HZ
1989 def_bool $(cc-option,-msign-return-ad <<
1990 2769
1991 config AS_HAS_ARMV8_3 !! 2770 config HZ_1024
1992 def_bool $(cc-option,-Wa$(comma)-marc !! 2771 bool "1024 HZ" if SYS_SUPPORTS_1024HZ || SYS_SUPPORTS_ARBIT_HZ
1993 2772
1994 config AS_HAS_CFI_NEGATE_RA_STATE !! 2773 endchoice
1995 def_bool $(as-instr,.cfi_startproc\n. <<
1996 2774
1997 config AS_HAS_LDAPR !! 2775 config SYS_SUPPORTS_24HZ
1998 def_bool $(as-instr,.arch_extension r !! 2776 bool
1999 2777
2000 endmenu # "ARMv8.3 architectural features" !! 2778 config SYS_SUPPORTS_48HZ
>> 2779 bool
2001 2780
2002 menu "ARMv8.4 architectural features" !! 2781 config SYS_SUPPORTS_100HZ
>> 2782 bool
2003 2783
2004 config ARM64_AMU_EXTN !! 2784 config SYS_SUPPORTS_128HZ
2005 bool "Enable support for the Activity !! 2785 bool
2006 default y <<
2007 help <<
2008 The activity monitors extension is <<
2009 by the ARMv8.4 CPU architecture. Th <<
2010 of the activity monitors architectu <<
2011 2786
2012 To enable the use of this extension !! 2787 config SYS_SUPPORTS_250HZ
>> 2788 bool
2013 2789
2014 Note that for architectural reasons !! 2790 config SYS_SUPPORTS_256HZ
2015 support when running on CPUs that p !! 2791 bool
2016 extension. The required support is <<
2017 * Version 1.5 and later of the AR <<
2018 2792
2019 For kernels that have this configur !! 2793 config SYS_SUPPORTS_1000HZ
2020 firmware, you may need to say N her !! 2794 bool
2021 Otherwise you may experience firmwa <<
2022 accessing the counter registers. Ev <<
2023 symptoms, the values returned by th <<
2024 correctly reflect reality. Most com <<
2025 indicating that the counter is not <<
2026 2795
2027 config AS_HAS_ARMV8_4 !! 2796 config SYS_SUPPORTS_1024HZ
2028 def_bool $(cc-option,-Wa$(comma)-marc !! 2797 bool
2029 2798
2030 config ARM64_TLB_RANGE !! 2799 config SYS_SUPPORTS_ARBIT_HZ
2031 bool "Enable support for tlbi range f !! 2800 bool
2032 default y !! 2801 default y if !SYS_SUPPORTS_24HZ && \
2033 depends on AS_HAS_ARMV8_4 !! 2802 !SYS_SUPPORTS_48HZ && \
2034 help !! 2803 !SYS_SUPPORTS_100HZ && \
2035 ARMv8.4-TLBI provides TLBI invalida !! 2804 !SYS_SUPPORTS_128HZ && \
2036 range of input addresses. !! 2805 !SYS_SUPPORTS_250HZ && \
>> 2806 !SYS_SUPPORTS_256HZ && \
>> 2807 !SYS_SUPPORTS_1000HZ && \
>> 2808 !SYS_SUPPORTS_1024HZ
2037 2809
2038 The feature introduces new assembly !! 2810 config HZ
2039 support when binutils >= 2.30. !! 2811 int
>> 2812 default 24 if HZ_24
>> 2813 default 48 if HZ_48
>> 2814 default 100 if HZ_100
>> 2815 default 128 if HZ_128
>> 2816 default 250 if HZ_250
>> 2817 default 256 if HZ_256
>> 2818 default 1000 if HZ_1000
>> 2819 default 1024 if HZ_1024
>> 2820
>> 2821 config SCHED_HRTICK
>> 2822 def_bool HIGH_RES_TIMERS
>> 2823
>> 2824 source "kernel/Kconfig.preempt"
>> 2825
>> 2826 config KEXEC
>> 2827 bool "Kexec system call"
>> 2828 select KEXEC_CORE
>> 2829 help
>> 2830 kexec is a system call that implements the ability to shutdown your
>> 2831 current kernel, and to start another kernel. It is like a reboot
>> 2832 but it is independent of the system firmware. And like a reboot
>> 2833 you can start any kernel with it, not just Linux.
>> 2834
>> 2835 The name comes from the similarity to the exec system call.
>> 2836
>> 2837 It is an ongoing process to be certain the hardware in a machine
>> 2838 is properly shutdown, so do not be surprised if this code does not
>> 2839 initially work for you. As of this writing the exact hardware
>> 2840 interface is strongly in flux, so no good recommendation can be
>> 2841 made.
>> 2842
>> 2843 config CRASH_DUMP
>> 2844 bool "Kernel crash dumps"
>> 2845 help
>> 2846 Generate crash dump after being started by kexec.
>> 2847 This should be normally only set in special crash dump kernels
>> 2848 which are loaded in the main kernel with kexec-tools into
>> 2849 a specially reserved region and then later executed after
>> 2850 a crash by kdump/kexec. The crash dump kernel must be compiled
>> 2851 to a memory address not used by the main kernel or firmware using
>> 2852 PHYSICAL_START.
>> 2853
>> 2854 config PHYSICAL_START
>> 2855 hex "Physical address where the kernel is loaded"
>> 2856 default "0xffffffff84000000" if 64BIT
>> 2857 default "0x84000000" if 32BIT
>> 2858 depends on CRASH_DUMP
>> 2859 help
>> 2860 This gives the CKSEG0 or KSEG0 address where the kernel is loaded.
>> 2861 If you plan to use kernel for capturing the crash dump change
>> 2862 this value to start of the reserved region (the "X" value as
>> 2863 specified in the "crashkernel=YM@XM" command line boot parameter
>> 2864 passed to the panic-ed kernel).
>> 2865
>> 2866 config SECCOMP
>> 2867 bool "Enable seccomp to safely compute untrusted bytecode"
>> 2868 depends on PROC_FS
>> 2869 default y
>> 2870 help
>> 2871 This kernel feature is useful for number crunching applications
>> 2872 that may need to compute untrusted bytecode during their
>> 2873 execution. By using pipes or other transports made available to
>> 2874 the process as file descriptors supporting the read/write
>> 2875 syscalls, it's possible to isolate those applications in
>> 2876 their own address space using seccomp. Once seccomp is
>> 2877 enabled via /proc/<pid>/seccomp, it cannot be disabled
>> 2878 and the task is only allowed to execute a few safe syscalls
>> 2879 defined by each seccomp mode.
>> 2880
>> 2881 If unsure, say Y. Only embedded should say N here.
>> 2882
>> 2883 config MIPS_O32_FP64_SUPPORT
>> 2884 bool "Support for O32 binaries using 64-bit FP"
>> 2885 depends on 32BIT || MIPS32_O32
>> 2886 help
>> 2887 When this is enabled, the kernel will support use of 64-bit floating
>> 2888 point registers with binaries using the O32 ABI along with the
>> 2889 EF_MIPS_FP64 ELF header flag (typically built with -mfp64). On
>> 2890 32-bit MIPS systems this support is at the cost of increasing the
>> 2891 size and complexity of the compiled FPU emulator. Thus if you are
>> 2892 running a MIPS32 system and know that none of your userland binaries
>> 2893 will require 64-bit floating point, you may wish to reduce the size
>> 2894 of your kernel & potentially improve FP emulation performance by
>> 2895 saying N here.
>> 2896
>> 2897 Although binutils currently supports use of this flag the details
>> 2898 concerning its effect upon the O32 ABI in userland are still being
>> 2899 worked on. In order to avoid userland becoming dependant upon current
>> 2900 behaviour before the details have been finalised, this option should
>> 2901 be considered experimental and only enabled by those working upon
>> 2902 said details.
2040 2903
2041 endmenu # "ARMv8.4 architectural features" !! 2904 If unsure, say N.
2042 2905
2043 menu "ARMv8.5 architectural features" !! 2906 config USE_OF
>> 2907 bool
>> 2908 select OF
>> 2909 select OF_EARLY_FLATTREE
>> 2910 select IRQ_DOMAIN
2044 2911
2045 config AS_HAS_ARMV8_5 !! 2912 config BUILTIN_DTB
2046 def_bool $(cc-option,-Wa$(comma)-marc !! 2913 bool
2047 2914
2048 config ARM64_BTI !! 2915 choice
2049 bool "Branch Target Identification su !! 2916 prompt "Kernel appended dtb support" if USE_OF
2050 default y !! 2917 default MIPS_NO_APPENDED_DTB
2051 help <<
2052 Branch Target Identification (part <<
2053 provides a mechanism to limit the s <<
2054 branch instructions such as BR or B <<
2055 2918
2056 To make use of BTI on CPUs that sup !! 2919 config MIPS_NO_APPENDED_DTB
>> 2920 bool "None"
>> 2921 help
>> 2922 Do not enable appended dtb support.
>> 2923
>> 2924 config MIPS_ELF_APPENDED_DTB
>> 2925 bool "vmlinux"
>> 2926 help
>> 2927 With this option, the boot code will look for a device tree binary
>> 2928 DTB) included in the vmlinux ELF section .appended_dtb. By default
>> 2929 it is empty and the DTB can be appended using binutils command
>> 2930 objcopy:
>> 2931
>> 2932 objcopy --update-section .appended_dtb=<filename>.dtb vmlinux
>> 2933
>> 2934 This is meant as a backward compatiblity convenience for those
>> 2935 systems with a bootloader that can't be upgraded to accommodate
>> 2936 the documented boot protocol using a device tree.
>> 2937
>> 2938 config MIPS_RAW_APPENDED_DTB
>> 2939 bool "vmlinux.bin or vmlinuz.bin"
>> 2940 help
>> 2941 With this option, the boot code will look for a device tree binary
>> 2942 DTB) appended to raw vmlinux.bin or vmlinuz.bin.
>> 2943 (e.g. cat vmlinux.bin <filename>.dtb > vmlinux_w_dtb).
>> 2944
>> 2945 This is meant as a backward compatibility convenience for those
>> 2946 systems with a bootloader that can't be upgraded to accommodate
>> 2947 the documented boot protocol using a device tree.
>> 2948
>> 2949 Beware that there is very little in terms of protection against
>> 2950 this option being confused by leftover garbage in memory that might
>> 2951 look like a DTB header after a reboot if no actual DTB is appended
>> 2952 to vmlinux.bin. Do not leave this option active in a production kernel
>> 2953 if you don't intend to always append a DTB.
>> 2954 endchoice
2057 2955
2058 BTI is intended to provide compleme !! 2956 choice
2059 flow integrity protection mechanism !! 2957 prompt "Kernel command line type" if !CMDLINE_OVERRIDE
2060 authentication mechanism provided a !! 2958 default MIPS_CMDLINE_FROM_DTB if USE_OF && !ATH79 && !MACH_INGENIC && \
2061 For this reason, it does not make s !! 2959 !MIPS_MALTA && \
2062 also enabling support for pointer a !! 2960 !CAVIUM_OCTEON_SOC
2063 enabling this option you should als !! 2961 default MIPS_CMDLINE_FROM_BOOTLOADER
>> 2962
>> 2963 config MIPS_CMDLINE_FROM_DTB
>> 2964 depends on USE_OF
>> 2965 bool "Dtb kernel arguments if available"
>> 2966
>> 2967 config MIPS_CMDLINE_DTB_EXTEND
>> 2968 depends on USE_OF
>> 2969 bool "Extend dtb kernel arguments with bootloader arguments"
>> 2970
>> 2971 config MIPS_CMDLINE_FROM_BOOTLOADER
>> 2972 bool "Bootloader kernel arguments if available"
>> 2973
>> 2974 config MIPS_CMDLINE_BUILTIN_EXTEND
>> 2975 depends on CMDLINE_BOOL
>> 2976 bool "Extend builtin kernel arguments with bootloader arguments"
>> 2977 endchoice
2064 2978
2065 Userspace binaries must also be spe !! 2979 endmenu
2066 this mechanism. If you say N here <<
2067 BTI, such binaries can still run, b <<
2068 enforcement of branch destinations. <<
2069 2980
2070 config ARM64_BTI_KERNEL !! 2981 config LOCKDEP_SUPPORT
2071 bool "Use Branch Target Identificatio !! 2982 bool
2072 default y 2983 default y
2073 depends on ARM64_BTI <<
2074 depends on ARM64_PTR_AUTH_KERNEL <<
2075 depends on CC_HAS_BRANCH_PROT_PAC_RET <<
2076 # https://gcc.gnu.org/bugzilla/show_b <<
2077 depends on !CC_IS_GCC || GCC_VERSION <<
2078 # https://gcc.gnu.org/bugzilla/show_b <<
2079 depends on !CC_IS_GCC <<
2080 depends on (!FUNCTION_GRAPH_TRACER || <<
2081 help <<
2082 Build the kernel with Branch Target <<
2083 and enable enforcement of this for <<
2084 is enabled and the system supports <<
2085 modular code must have BTI enabled. <<
2086 2984
2087 config CC_HAS_BRANCH_PROT_PAC_RET_BTI !! 2985 config STACKTRACE_SUPPORT
2088 # GCC 9 or later, clang 8 or later !! 2986 bool
2089 def_bool $(cc-option,-mbranch-protect <<
2090 <<
2091 config ARM64_E0PD <<
2092 bool "Enable support for E0PD" <<
2093 default y 2987 default y
2094 help <<
2095 E0PD (part of the ARMv8.5 extension <<
2096 that EL0 accesses made via TTBR1 al <<
2097 providing similar benefits to KASLR <<
2098 with lower overhead and without dis <<
2099 kernel memory such as SPE. <<
2100 <<
2101 This option enables E0PD for TTBR1 <<
2102 <<
2103 config ARM64_AS_HAS_MTE <<
2104 # Initial support for MTE went in bin <<
2105 # ".arch armv8.5-a+memtag" below. How <<
2106 # as a late addition to the final arc <<
2107 # is only supported in the newer 2.32 <<
2108 # versions, hence the extra "stgm" in <<
2109 def_bool $(as-instr,.arch armv8.5-a+m <<
2110 2988
2111 config ARM64_MTE !! 2989 config HAVE_LATENCYTOP_SUPPORT
2112 bool "Memory Tagging Extension suppor !! 2990 bool
2113 default y 2991 default y
2114 depends on ARM64_AS_HAS_MTE && ARM64_ <<
2115 depends on AS_HAS_ARMV8_5 <<
2116 depends on AS_HAS_LSE_ATOMICS <<
2117 # Required for tag checking in the ua <<
2118 depends on ARM64_PAN <<
2119 select ARCH_HAS_SUBPAGE_FAULTS <<
2120 select ARCH_USES_HIGH_VMA_FLAGS <<
2121 select ARCH_USES_PG_ARCH_2 <<
2122 select ARCH_USES_PG_ARCH_3 <<
2123 help <<
2124 Memory Tagging (part of the ARMv8.5 <<
2125 architectural support for run-time, <<
2126 various classes of memory error to <<
2127 to eliminate vulnerabilities arisin <<
2128 languages. <<
2129 2992
2130 This option enables the support for !! 2993 config PGTABLE_LEVELS
2131 Extension at EL0 (i.e. for userspac !! 2994 int
>> 2995 default 4 if PAGE_SIZE_4KB && MIPS_VA_BITS_48
>> 2996 default 3 if 64BIT && !PAGE_SIZE_64KB
>> 2997 default 2
2132 2998
2133 Selecting this option allows the fe !! 2999 source "init/Kconfig"
2134 runtime. Any secondary CPU not impl <<
2135 not be allowed a late bring-up. <<
2136 3000
2137 Userspace binaries that want to use !! 3001 source "kernel/Kconfig.freezer"
2138 explicitly opt in. The mechanism fo <<
2139 described in: <<
2140 3002
2141 Documentation/arch/arm64/memory-tag !! 3003 menu "Bus options (PCI, PCMCIA, EISA, ISA, TC)"
2142 3004
2143 endmenu # "ARMv8.5 architectural features" !! 3005 config HW_HAS_EISA
>> 3006 bool
>> 3007 config HW_HAS_PCI
>> 3008 bool
2144 3009
2145 menu "ARMv8.7 architectural features" !! 3010 config PCI
>> 3011 bool "Support for PCI controller"
>> 3012 depends on HW_HAS_PCI
>> 3013 select PCI_DOMAINS
>> 3014 help
>> 3015 Find out whether you have a PCI motherboard. PCI is the name of a
>> 3016 bus system, i.e. the way the CPU talks to the other stuff inside
>> 3017 your box. Other bus systems are ISA, EISA, or VESA. If you have PCI,
>> 3018 say Y, otherwise N.
>> 3019
>> 3020 config HT_PCI
>> 3021 bool "Support for HT-linked PCI"
>> 3022 default y
>> 3023 depends on CPU_LOONGSON3
>> 3024 select PCI
>> 3025 select PCI_DOMAINS
>> 3026 help
>> 3027 Loongson family machines use Hyper-Transport bus for inter-core
>> 3028 connection and device connection. The PCI bus is a subordinate
>> 3029 linked at HT. Choose Y for Loongson-3 based machines.
2146 3030
2147 config ARM64_EPAN !! 3031 config PCI_DOMAINS
2148 bool "Enable support for Enhanced Pri !! 3032 bool
2149 default y <<
2150 depends on ARM64_PAN <<
2151 help <<
2152 Enhanced Privileged Access Never (E <<
2153 Access Never to be used with Execut <<
2154 <<
2155 The feature is detected at runtime, <<
2156 if the cpu does not implement the f <<
2157 endmenu # "ARMv8.7 architectural features" <<
2158 3033
2159 menu "ARMv8.9 architectural features" !! 3034 config PCI_DOMAINS_GENERIC
>> 3035 bool
2160 3036
2161 config ARM64_POE !! 3037 config PCI_DRIVERS_GENERIC
2162 prompt "Permission Overlay Extension" !! 3038 select PCI_DOMAINS_GENERIC if PCI_DOMAINS
2163 def_bool y !! 3039 bool
2164 select ARCH_USES_HIGH_VMA_FLAGS <<
2165 select ARCH_HAS_PKEYS <<
2166 help <<
2167 The Permission Overlay Extension is <<
2168 Protection Keys. Memory Protection <<
2169 enforcing page-based protections, b <<
2170 of the page tables when an applicat <<
2171 3040
2172 For details, see Documentation/core !! 3041 config PCI_DRIVERS_LEGACY
>> 3042 def_bool !PCI_DRIVERS_GENERIC
>> 3043 select NO_GENERIC_PCI_IOPORT_MAP
2173 3044
2174 If unsure, say y. !! 3045 source "drivers/pci/Kconfig"
2175 3046
2176 config ARCH_PKEY_BITS !! 3047 #
2177 int !! 3048 # ISA support is now enabled via select. Too many systems still have the one
2178 default 3 !! 3049 # or other ISA chip on the board that users don't know about so don't expect
>> 3050 # users to choose the right thing ...
>> 3051 #
>> 3052 config ISA
>> 3053 bool
2179 3054
2180 endmenu # "ARMv8.9 architectural features" !! 3055 config EISA
>> 3056 bool "EISA support"
>> 3057 depends on HW_HAS_EISA
>> 3058 select ISA
>> 3059 select GENERIC_ISA_DMA
>> 3060 ---help---
>> 3061 The Extended Industry Standard Architecture (EISA) bus was
>> 3062 developed as an open alternative to the IBM MicroChannel bus.
>> 3063
>> 3064 The EISA bus provided some of the features of the IBM MicroChannel
>> 3065 bus while maintaining backward compatibility with cards made for
>> 3066 the older ISA bus. The EISA bus saw limited use between 1988 and
>> 3067 1995 when it was made obsolete by the PCI bus.
>> 3068
>> 3069 Say Y here if you are building a kernel for an EISA-based machine.
>> 3070
>> 3071 Otherwise, say N.
>> 3072
>> 3073 source "drivers/eisa/Kconfig"
>> 3074
>> 3075 config TC
>> 3076 bool "TURBOchannel support"
>> 3077 depends on MACH_DECSTATION
>> 3078 help
>> 3079 TURBOchannel is a DEC (now Compaq (now HP)) bus for Alpha and MIPS
>> 3080 processors. TURBOchannel programming specifications are available
>> 3081 at:
>> 3082 <ftp://ftp.hp.com/pub/alphaserver/archive/triadd/>
>> 3083 and:
>> 3084 <http://www.computer-refuge.org/classiccmp/ftp.digital.com/pub/DEC/TriAdd/>
>> 3085 Linux driver support status is documented at:
>> 3086 <http://www.linux-mips.org/wiki/DECstation>
2181 3087
2182 config ARM64_SVE !! 3088 config MMU
2183 bool "ARM Scalable Vector Extension s !! 3089 bool
2184 default y 3090 default y
2185 help <<
2186 The Scalable Vector Extension (SVE) <<
2187 execution state which complements a <<
2188 of the base architecture to support <<
2189 additional vectorisation opportunit <<
2190 <<
2191 To enable use of this extension on <<
2192 <<
2193 On CPUs that support the SVE2 exten <<
2194 those too. <<
2195 <<
2196 Note that for architectural reasons <<
2197 support when running on SVE capable <<
2198 is present in: <<
2199 3091
2200 * version 1.5 and later of the AR !! 3092 config ARCH_MMAP_RND_BITS_MIN
2201 * the AArch64 boot wrapper since !! 3093 default 12 if 64BIT
2202 ("bootwrapper: SVE: Enable SVE !! 3094 default 8
2203 <<
2204 For other firmware implementations, <<
2205 or vendor. <<
2206 <<
2207 If you need the kernel to boot on S <<
2208 firmware, you may need to say N her <<
2209 fixed. Otherwise, you may experien <<
2210 booting the kernel. If unsure and <<
2211 symptoms, you should assume that it <<
2212 3095
2213 config ARM64_SME !! 3096 config ARCH_MMAP_RND_BITS_MAX
2214 bool "ARM Scalable Matrix Extension s !! 3097 default 18 if 64BIT
2215 default y !! 3098 default 15
2216 depends on ARM64_SVE <<
2217 depends on BROKEN <<
2218 help <<
2219 The Scalable Matrix Extension (SME) <<
2220 execution state which utilises a su <<
2221 instruction set, together with the <<
2222 register state capable of holding t <<
2223 enable various matrix operations. <<
2224 3099
2225 config ARM64_PSEUDO_NMI !! 3100 config ARCH_MMAP_RND_COMPAT_BITS_MIN
2226 bool "Support for NMI-like interrupts !! 3101 default 8
2227 select ARM_GIC_V3 <<
2228 help <<
2229 Adds support for mimicking Non-Mask <<
2230 GIC interrupt priority. This suppor <<
2231 ARM GIC. <<
2232 3102
2233 This high priority configuration fo !! 3103 config ARCH_MMAP_RND_COMPAT_BITS_MAX
2234 explicitly enabled by setting the k !! 3104 default 15
2235 "irqchip.gicv3_pseudo_nmi" to 1. <<
2236 3105
2237 If unsure, say N !! 3106 config I8253
>> 3107 bool
>> 3108 select CLKSRC_I8253
>> 3109 select CLKEVT_I8253
>> 3110 select MIPS_EXTERNAL_TIMER
2238 3111
2239 if ARM64_PSEUDO_NMI !! 3112 config ZONE_DMA
2240 config ARM64_DEBUG_PRIORITY_MASKING !! 3113 bool
2241 bool "Debug interrupt priority maskin <<
2242 help <<
2243 This adds runtime checks to functio <<
2244 interrupts when using priority mask <<
2245 the validity of ICC_PMR_EL1 when ca <<
2246 3114
2247 If unsure, say N !! 3115 config ZONE_DMA32
2248 endif # ARM64_PSEUDO_NMI !! 3116 bool
2249 3117
2250 config RELOCATABLE !! 3118 source "drivers/pcmcia/Kconfig"
2251 bool "Build a relocatable kernel imag <<
2252 select ARCH_HAS_RELR <<
2253 default y <<
2254 help <<
2255 This builds the kernel as a Positio <<
2256 which retains all relocation metada <<
2257 kernel binary at runtime to a diffe <<
2258 address it was linked at. <<
2259 Since AArch64 uses the RELA relocat <<
2260 relocation pass at runtime even if <<
2261 same address it was linked at. <<
2262 3119
2263 config RANDOMIZE_BASE !! 3120 config RAPIDIO
2264 bool "Randomize the address of the ke !! 3121 tristate "RapidIO support"
2265 select RELOCATABLE !! 3122 depends on PCI
>> 3123 default n
2266 help 3124 help
2267 Randomizes the virtual address at w !! 3125 If you say Y here, the kernel will include drivers and
2268 loaded, as a security feature that !! 3126 infrastructure code to support RapidIO interconnect devices.
2269 relying on knowledge of the locatio <<
2270 <<
2271 It is the bootloader's job to provi <<
2272 random u64 value in /chosen/kaslr-s <<
2273 <<
2274 When booting via the UEFI stub, it <<
2275 EFI_RNG_PROTOCOL implementation (if <<
2276 to the kernel proper. In addition, <<
2277 location of the kernel Image as wel <<
2278 3127
2279 If unsure, say N. !! 3128 source "drivers/rapidio/Kconfig"
2280 3129
2281 config RANDOMIZE_MODULE_REGION_FULL !! 3130 endmenu
2282 bool "Randomize the module region ove <<
2283 depends on RANDOMIZE_BASE <<
2284 default y <<
2285 help <<
2286 Randomizes the location of the modu <<
2287 covering the core kernel. This way, <<
2288 to leak information about the locat <<
2289 but it does imply that function cal <<
2290 kernel will need to be resolved via <<
2291 <<
2292 When this option is not set, the mo <<
2293 a limited range that contains the [ <<
2294 core kernel, so branch relocations <<
2295 the region is exhausted. In this pa <<
2296 exhaustion, modules might be able t <<
2297 3131
2298 config CC_HAVE_STACKPROTECTOR_SYSREG !! 3132 menu "Executable file formats"
2299 def_bool $(cc-option,-mstack-protecto <<
2300 3133
2301 config STACKPROTECTOR_PER_TASK !! 3134 source "fs/Kconfig.binfmt"
2302 def_bool y <<
2303 depends on STACKPROTECTOR && CC_HAVE_ <<
2304 3135
2305 config UNWIND_PATCH_PAC_INTO_SCS !! 3136 config TRAD_SIGNALS
2306 bool "Enable shadow call stack dynami !! 3137 bool
2307 # needs Clang with https://github.com <<
2308 depends on CC_IS_CLANG && CLANG_VERSI <<
2309 depends on ARM64_PTR_AUTH_KERNEL && C <<
2310 depends on SHADOW_CALL_STACK <<
2311 select UNWIND_TABLES <<
2312 select DYNAMIC_SCS <<
2313 <<
2314 config ARM64_CONTPTE <<
2315 bool "Contiguous PTE mappings for use <<
2316 depends on TRANSPARENT_HUGEPAGE <<
2317 default y <<
2318 help <<
2319 When enabled, user mappings are con <<
2320 bit, for any mappings that meet the <<
2321 This reduces TLB pressure and impro <<
2322 <<
2323 endmenu # "Kernel Features" <<
2324 <<
2325 menu "Boot options" <<
2326 <<
2327 config ARM64_ACPI_PARKING_PROTOCOL <<
2328 bool "Enable support for the ARM64 AC <<
2329 depends on ACPI <<
2330 help <<
2331 Enable support for the ARM64 ACPI p <<
2332 the kernel will not allow booting t <<
2333 protocol even if the corresponding <<
2334 MADT table. <<
2335 <<
2336 config CMDLINE <<
2337 string "Default kernel command string <<
2338 default "" <<
2339 help <<
2340 Provide a set of default command-li <<
2341 entering them here. As a minimum, y <<
2342 root device (e.g. root=/dev/nfs). <<
2343 3138
2344 choice !! 3139 config MIPS32_COMPAT
2345 prompt "Kernel command line type" !! 3140 bool
2346 depends on CMDLINE != "" <<
2347 default CMDLINE_FROM_BOOTLOADER <<
2348 help <<
2349 Choose how the kernel will handle t <<
2350 command line string. <<
2351 <<
2352 config CMDLINE_FROM_BOOTLOADER <<
2353 bool "Use bootloader kernel arguments <<
2354 help <<
2355 Uses the command-line options passe <<
2356 the boot loader doesn't provide any <<
2357 string provided in CMDLINE will be <<
2358 <<
2359 config CMDLINE_FORCE <<
2360 bool "Always use the default kernel c <<
2361 help <<
2362 Always use the default kernel comma <<
2363 loader passes other arguments to th <<
2364 This is useful if you cannot or don <<
2365 command-line options your boot load <<
2366 3141
2367 endchoice !! 3142 config COMPAT
>> 3143 bool
2368 3144
2369 config EFI_STUB !! 3145 config SYSVIPC_COMPAT
2370 bool 3146 bool
2371 3147
2372 config EFI !! 3148 config MIPS32_O32
2373 bool "UEFI runtime support" !! 3149 bool "Kernel support for o32 binaries"
2374 depends on OF && !CPU_BIG_ENDIAN !! 3150 depends on 64BIT
2375 depends on KERNEL_MODE_NEON !! 3151 select ARCH_WANT_OLD_COMPAT_IPC
2376 select ARCH_SUPPORTS_ACPI !! 3152 select COMPAT
2377 select LIBFDT !! 3153 select MIPS32_COMPAT
2378 select UCS2_STRING !! 3154 select SYSVIPC_COMPAT if SYSVIPC
2379 select EFI_PARAMS_FROM_FDT !! 3155 help
2380 select EFI_RUNTIME_WRAPPERS !! 3156 Select this option if you want to run o32 binaries. These are pure
2381 select EFI_STUB !! 3157 32-bit binaries as used by the 32-bit Linux/MIPS port. Most of
2382 select EFI_GENERIC_STUB !! 3158 existing binaries are in this format.
2383 imply IMA_SECURE_AND_OR_TRUSTED_BOOT <<
2384 default y <<
2385 help <<
2386 This option provides support for ru <<
2387 by UEFI firmware (such as non-volat <<
2388 clock, and platform reset). A UEFI <<
2389 allow the kernel to be booted as an <<
2390 is only useful on systems that have <<
2391 3159
2392 config COMPRESSED_INSTALL !! 3160 If unsure, say Y.
2393 bool "Install compressed image by def <<
2394 help <<
2395 This makes the regular "make instal <<
2396 image we built, not the legacy unco <<
2397 3161
2398 You can check that a compressed ima !! 3162 config MIPS32_N32
2399 "make zinstall" first, and verifyin !! 3163 bool "Kernel support for n32 binaries"
2400 in your environment before making " !! 3164 depends on 64BIT
2401 you. !! 3165 select COMPAT
>> 3166 select MIPS32_COMPAT
>> 3167 select SYSVIPC_COMPAT if SYSVIPC
>> 3168 help
>> 3169 Select this option if you want to run n32 binaries. These are
>> 3170 64-bit binaries using 32-bit quantities for addressing and certain
>> 3171 data that would normally be 64-bit. They are used in special
>> 3172 cases.
2402 3173
2403 config DMI !! 3174 If unsure, say N.
2404 bool "Enable support for SMBIOS (DMI) <<
2405 depends on EFI <<
2406 default y <<
2407 help <<
2408 This enables SMBIOS/DMI feature for <<
2409 3175
2410 This option is only useful on syste !! 3176 config BINFMT_ELF32
2411 However, even with this option, the !! 3177 bool
2412 continue to boot on existing non-UE !! 3178 default y if MIPS32_O32 || MIPS32_N32
>> 3179 select ELFCORE
2413 3180
2414 endmenu # "Boot options" !! 3181 endmenu
2415 3182
2416 menu "Power management options" 3183 menu "Power management options"
2417 3184
2418 source "kernel/power/Kconfig" <<
2419 <<
2420 config ARCH_HIBERNATION_POSSIBLE 3185 config ARCH_HIBERNATION_POSSIBLE
2421 def_bool y 3186 def_bool y
2422 depends on CPU_PM !! 3187 depends on SYS_SUPPORTS_HOTPLUG_CPU || !SMP
2423 <<
2424 config ARCH_HIBERNATION_HEADER <<
2425 def_bool y <<
2426 depends on HIBERNATION <<
2427 3188
2428 config ARCH_SUSPEND_POSSIBLE 3189 config ARCH_SUSPEND_POSSIBLE
2429 def_bool y 3190 def_bool y
>> 3191 depends on SYS_SUPPORTS_HOTPLUG_CPU || !SMP
>> 3192
>> 3193 source "kernel/power/Kconfig"
2430 3194
2431 endmenu # "Power management options" !! 3195 endmenu
>> 3196
>> 3197 config MIPS_EXTERNAL_TIMER
>> 3198 bool
2432 3199
2433 menu "CPU Power Management" 3200 menu "CPU Power Management"
2434 3201
>> 3202 if CPU_SUPPORTS_CPUFREQ && MIPS_EXTERNAL_TIMER
>> 3203 source "drivers/cpufreq/Kconfig"
>> 3204 endif
>> 3205
2435 source "drivers/cpuidle/Kconfig" 3206 source "drivers/cpuidle/Kconfig"
2436 3207
2437 source "drivers/cpufreq/Kconfig" !! 3208 endmenu
>> 3209
>> 3210 source "net/Kconfig"
>> 3211
>> 3212 source "drivers/Kconfig"
>> 3213
>> 3214 source "drivers/firmware/Kconfig"
>> 3215
>> 3216 source "fs/Kconfig"
>> 3217
>> 3218 source "arch/mips/Kconfig.debug"
2438 3219
2439 endmenu # "CPU Power Management" !! 3220 source "security/Kconfig"
2440 3221
2441 source "drivers/acpi/Kconfig" !! 3222 source "crypto/Kconfig"
2442 3223
2443 source "arch/arm64/kvm/Kconfig" !! 3224 source "lib/Kconfig"
2444 3225
>> 3226 source "arch/mips/kvm/Kconfig"
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