1 # SPDX-License-Identifier: GPL-2.0-only !! 1 # SPDX-License-Identifier: GPL-2.0
2 config ARM64 !! 2 config MIPS
3 def_bool y !! 3 bool
4 select ACPI_APMT if ACPI !! 4 default y
5 select ACPI_CCA_REQUIRED if ACPI <<
6 select ACPI_GENERIC_GSI if ACPI <<
7 select ACPI_GTDT if ACPI <<
8 select ACPI_HOTPLUG_CPU if ACPI_PROCES <<
9 select ACPI_IORT if ACPI <<
10 select ACPI_REDUCED_HARDWARE_ONLY if A <<
11 select ACPI_MCFG if (ACPI && PCI) <<
12 select ACPI_SPCR_TABLE if ACPI <<
13 select ACPI_PPTT if ACPI <<
14 select ARCH_HAS_DEBUG_WX <<
15 select ARCH_BINFMT_ELF_EXTRA_PHDRS <<
16 select ARCH_BINFMT_ELF_STATE 5 select ARCH_BINFMT_ELF_STATE
17 select ARCH_CORRECT_STACKTRACE_ON_KRET !! 6 select ARCH_CLOCKSOURCE_DATA
18 select ARCH_ENABLE_HUGEPAGE_MIGRATION !! 7 select ARCH_HAS_CPU_FINALIZE_INIT
19 select ARCH_ENABLE_MEMORY_HOTPLUG !! 8 select ARCH_DISCARD_MEMBLOCK
20 select ARCH_ENABLE_MEMORY_HOTREMOVE !! 9 select ARCH_HAS_ELF_RANDOMIZE
21 select ARCH_ENABLE_SPLIT_PMD_PTLOCK if <<
22 select ARCH_ENABLE_THP_MIGRATION if TR <<
23 select ARCH_HAS_CACHE_LINE_SIZE <<
24 select ARCH_HAS_CURRENT_STACK_POINTER <<
25 select ARCH_HAS_DEBUG_VIRTUAL <<
26 select ARCH_HAS_DEBUG_VM_PGTABLE <<
27 select ARCH_HAS_DMA_OPS if XEN <<
28 select ARCH_HAS_DMA_PREP_COHERENT <<
29 select ARCH_HAS_ACPI_TABLE_UPGRADE if <<
30 select ARCH_HAS_FAST_MULTIPLIER <<
31 select ARCH_HAS_FORTIFY_SOURCE <<
32 select ARCH_HAS_GCOV_PROFILE_ALL <<
33 select ARCH_HAS_GIGANTIC_PAGE <<
34 select ARCH_HAS_KCOV <<
35 select ARCH_HAS_KERNEL_FPU_SUPPORT if <<
36 select ARCH_HAS_KEEPINITRD <<
37 select ARCH_HAS_MEMBARRIER_SYNC_CORE <<
38 select ARCH_HAS_MEM_ENCRYPT <<
39 select ARCH_HAS_NMI_SAFE_THIS_CPU_OPS <<
40 select ARCH_HAS_NON_OVERLAPPING_ADDRES <<
41 select ARCH_HAS_PTE_DEVMAP <<
42 select ARCH_HAS_PTE_SPECIAL <<
43 select ARCH_HAS_HW_PTE_YOUNG <<
44 select ARCH_HAS_SETUP_DMA_OPS <<
45 select ARCH_HAS_SET_DIRECT_MAP <<
46 select ARCH_HAS_SET_MEMORY <<
47 select ARCH_STACKWALK <<
48 select ARCH_HAS_STRICT_KERNEL_RWX <<
49 select ARCH_HAS_STRICT_MODULE_RWX <<
50 select ARCH_HAS_SYNC_DMA_FOR_DEVICE <<
51 select ARCH_HAS_SYNC_DMA_FOR_CPU <<
52 select ARCH_HAS_SYSCALL_WRAPPER <<
53 select ARCH_HAS_TICK_BROADCAST if GENE 10 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
54 select ARCH_HAS_ZONE_DMA_SET if EXPERT !! 11 select ARCH_MIGHT_HAVE_PC_PARPORT
55 select ARCH_HAVE_ELF_PROT !! 12 select ARCH_MIGHT_HAVE_PC_SERIO
56 select ARCH_HAVE_NMI_SAFE_CMPXCHG !! 13 select ARCH_SUPPORTS_UPROBES
57 select ARCH_HAVE_TRACE_MMIO_ACCESS !! 14 select ARCH_USE_BUILTIN_BSWAP
58 select ARCH_INLINE_READ_LOCK if !PREEM !! 15 select ARCH_USE_CMPXCHG_LOCKREF if 64BIT
59 select ARCH_INLINE_READ_LOCK_BH if !PR <<
60 select ARCH_INLINE_READ_LOCK_IRQ if !P <<
61 select ARCH_INLINE_READ_LOCK_IRQSAVE i <<
62 select ARCH_INLINE_READ_UNLOCK if !PRE <<
63 select ARCH_INLINE_READ_UNLOCK_BH if ! <<
64 select ARCH_INLINE_READ_UNLOCK_IRQ if <<
65 select ARCH_INLINE_READ_UNLOCK_IRQREST <<
66 select ARCH_INLINE_WRITE_LOCK if !PREE <<
67 select ARCH_INLINE_WRITE_LOCK_BH if !P <<
68 select ARCH_INLINE_WRITE_LOCK_IRQ if ! <<
69 select ARCH_INLINE_WRITE_LOCK_IRQSAVE <<
70 select ARCH_INLINE_WRITE_UNLOCK if !PR <<
71 select ARCH_INLINE_WRITE_UNLOCK_BH if <<
72 select ARCH_INLINE_WRITE_UNLOCK_IRQ if <<
73 select ARCH_INLINE_WRITE_UNLOCK_IRQRES <<
74 select ARCH_INLINE_SPIN_TRYLOCK if !PR <<
75 select ARCH_INLINE_SPIN_TRYLOCK_BH if <<
76 select ARCH_INLINE_SPIN_LOCK if !PREEM <<
77 select ARCH_INLINE_SPIN_LOCK_BH if !PR <<
78 select ARCH_INLINE_SPIN_LOCK_IRQ if !P <<
79 select ARCH_INLINE_SPIN_LOCK_IRQSAVE i <<
80 select ARCH_INLINE_SPIN_UNLOCK if !PRE <<
81 select ARCH_INLINE_SPIN_UNLOCK_BH if ! <<
82 select ARCH_INLINE_SPIN_UNLOCK_IRQ if <<
83 select ARCH_INLINE_SPIN_UNLOCK_IRQREST <<
84 select ARCH_KEEP_MEMBLOCK <<
85 select ARCH_MHP_MEMMAP_ON_MEMORY_ENABL <<
86 select ARCH_USE_CMPXCHG_LOCKREF <<
87 select ARCH_USE_GNU_PROPERTY <<
88 select ARCH_USE_MEMTEST <<
89 select ARCH_USE_QUEUED_RWLOCKS 16 select ARCH_USE_QUEUED_RWLOCKS
90 select ARCH_USE_QUEUED_SPINLOCKS 17 select ARCH_USE_QUEUED_SPINLOCKS
91 select ARCH_USE_SYM_ANNOTATIONS !! 18 select ARCH_WANT_IPC_PARSE_VERSION
92 select ARCH_SUPPORTS_DEBUG_PAGEALLOC !! 19 select BUILDTIME_EXTABLE_SORT
93 select ARCH_SUPPORTS_HUGETLBFS <<
94 select ARCH_SUPPORTS_MEMORY_FAILURE <<
95 select ARCH_SUPPORTS_SHADOW_CALL_STACK <<
96 select ARCH_SUPPORTS_LTO_CLANG if CPU_ <<
97 select ARCH_SUPPORTS_LTO_CLANG_THIN <<
98 select ARCH_SUPPORTS_CFI_CLANG <<
99 select ARCH_SUPPORTS_ATOMIC_RMW <<
100 select ARCH_SUPPORTS_INT128 if CC_HAS_ <<
101 select ARCH_SUPPORTS_NUMA_BALANCING <<
102 select ARCH_SUPPORTS_PAGE_TABLE_CHECK <<
103 select ARCH_SUPPORTS_PER_VMA_LOCK <<
104 select ARCH_SUPPORTS_HUGE_PFNMAP if TR <<
105 select ARCH_SUPPORTS_RT <<
106 select ARCH_WANT_BATCHED_UNMAP_TLB_FLU <<
107 select ARCH_WANT_COMPAT_IPC_PARSE_VERS <<
108 select ARCH_WANT_DEFAULT_BPF_JIT <<
109 select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_ <<
110 select ARCH_WANT_FRAME_POINTERS <<
111 select ARCH_WANT_HUGE_PMD_SHARE if ARM <<
112 select ARCH_WANT_LD_ORPHAN_WARN <<
113 select ARCH_WANTS_EXECMEM_LATE if EXEC <<
114 select ARCH_WANTS_NO_INSTR <<
115 select ARCH_WANTS_THP_SWAP if ARM64_4K <<
116 select ARCH_HAS_UBSAN <<
117 select ARM_AMBA <<
118 select ARM_ARCH_TIMER <<
119 select ARM_GIC <<
120 select AUDIT_ARCH_COMPAT_GENERIC <<
121 select ARM_GIC_V2M if PCI <<
122 select ARM_GIC_V3 <<
123 select ARM_GIC_V3_ITS if PCI <<
124 select ARM_PSCI_FW <<
125 select BUILDTIME_TABLE_SORT <<
126 select CLONE_BACKWARDS 20 select CLONE_BACKWARDS
127 select COMMON_CLK !! 21 select CPU_PM if CPU_IDLE
128 select CPU_PM if (SUSPEND || CPU_IDLE) !! 22 select GENERIC_ATOMIC64 if !64BIT
129 select CPUMASK_OFFSTACK if NR_CPUS > 2 !! 23 select GENERIC_CLOCKEVENTS
130 select CRC32 !! 24 select GENERIC_CMOS_UPDATE
131 select DCACHE_WORD_ACCESS <<
132 select DYNAMIC_FTRACE if FUNCTION_TRAC <<
133 select DMA_BOUNCE_UNALIGNED_KMALLOC <<
134 select DMA_DIRECT_REMAP <<
135 select EDAC_SUPPORT <<
136 select FRAME_POINTER <<
137 select FUNCTION_ALIGNMENT_4B <<
138 select FUNCTION_ALIGNMENT_8B if DYNAMI <<
139 select GENERIC_ALLOCATOR <<
140 select GENERIC_ARCH_TOPOLOGY <<
141 select GENERIC_CLOCKEVENTS_BROADCAST <<
142 select GENERIC_CPU_AUTOPROBE 25 select GENERIC_CPU_AUTOPROBE
143 select GENERIC_CPU_DEVICES <<
144 select GENERIC_CPU_VULNERABILITIES <<
145 select GENERIC_EARLY_IOREMAP <<
146 select GENERIC_IDLE_POLL_SETUP <<
147 select GENERIC_IOREMAP <<
148 select GENERIC_IRQ_IPI <<
149 select GENERIC_IRQ_PROBE 26 select GENERIC_IRQ_PROBE
150 select GENERIC_IRQ_SHOW 27 select GENERIC_IRQ_SHOW
151 select GENERIC_IRQ_SHOW_LEVEL <<
152 select GENERIC_LIB_DEVMEM_IS_ALLOWED <<
153 select GENERIC_PCI_IOMAP 28 select GENERIC_PCI_IOMAP
154 select GENERIC_PTDUMP !! 29 select GENERIC_SCHED_CLOCK if !CAVIUM_OCTEON_SOC
155 select GENERIC_SCHED_CLOCK <<
156 select GENERIC_SMP_IDLE_THREAD 30 select GENERIC_SMP_IDLE_THREAD
157 select GENERIC_TIME_VSYSCALL 31 select GENERIC_TIME_VSYSCALL
158 select GENERIC_GETTIMEOFDAY !! 32 select HANDLE_DOMAIN_IRQ
159 select GENERIC_VDSO_TIME_NS <<
160 select HARDIRQS_SW_RESEND <<
161 select HAS_IOPORT <<
162 select HAVE_MOVE_PMD <<
163 select HAVE_MOVE_PUD <<
164 select HAVE_PCI <<
165 select HAVE_ACPI_APEI if (ACPI && EFI) <<
166 select HAVE_ALIGNED_STRUCT_PAGE <<
167 select HAVE_ARCH_AUDITSYSCALL <<
168 select HAVE_ARCH_BITREVERSE <<
169 select HAVE_ARCH_COMPILER_H 33 select HAVE_ARCH_COMPILER_H
170 select HAVE_ARCH_HUGE_VMALLOC <<
171 select HAVE_ARCH_HUGE_VMAP <<
172 select HAVE_ARCH_JUMP_LABEL 34 select HAVE_ARCH_JUMP_LABEL
173 select HAVE_ARCH_JUMP_LABEL_RELATIVE <<
174 select HAVE_ARCH_KASAN <<
175 select HAVE_ARCH_KASAN_VMALLOC <<
176 select HAVE_ARCH_KASAN_SW_TAGS <<
177 select HAVE_ARCH_KASAN_HW_TAGS if ARM6 <<
178 # Some instrumentation may be unsound, <<
179 select HAVE_ARCH_KCSAN if EXPERT <<
180 select HAVE_ARCH_KFENCE <<
181 select HAVE_ARCH_KGDB 35 select HAVE_ARCH_KGDB
182 select HAVE_ARCH_MMAP_RND_BITS !! 36 select HAVE_ARCH_MMAP_RND_BITS if MMU
183 select HAVE_ARCH_MMAP_RND_COMPAT_BITS !! 37 select HAVE_ARCH_MMAP_RND_COMPAT_BITS if MMU && COMPAT
184 select HAVE_ARCH_PREL32_RELOCATIONS <<
185 select HAVE_ARCH_RANDOMIZE_KSTACK_OFFS <<
186 select HAVE_ARCH_SECCOMP_FILTER 38 select HAVE_ARCH_SECCOMP_FILTER
187 select HAVE_ARCH_STACKLEAK <<
188 select HAVE_ARCH_THREAD_STRUCT_WHITELI <<
189 select HAVE_ARCH_TRACEHOOK 39 select HAVE_ARCH_TRACEHOOK
190 select HAVE_ARCH_TRANSPARENT_HUGEPAGE !! 40 select HAVE_ARCH_TRANSPARENT_HUGEPAGE if CPU_SUPPORTS_HUGEPAGES && 64BIT
191 select HAVE_ARCH_VMAP_STACK !! 41 select HAVE_CBPF_JIT if (!64BIT && !CPU_MICROMIPS)
192 select HAVE_ARM_SMCCC !! 42 select HAVE_EBPF_JIT if (64BIT && !CPU_MICROMIPS)
193 select HAVE_ASM_MODVERSIONS !! 43 select HAVE_CC_STACKPROTECTOR
194 select HAVE_EBPF_JIT !! 44 select HAVE_CONTEXT_TRACKING
>> 45 select HAVE_COPY_THREAD_TLS
195 select HAVE_C_RECORDMCOUNT 46 select HAVE_C_RECORDMCOUNT
196 select HAVE_CMPXCHG_DOUBLE <<
197 select HAVE_CMPXCHG_LOCAL <<
198 select HAVE_CONTEXT_TRACKING_USER <<
199 select HAVE_DEBUG_KMEMLEAK 47 select HAVE_DEBUG_KMEMLEAK
>> 48 select HAVE_DEBUG_STACKOVERFLOW
>> 49 select HAVE_DMA_API_DEBUG
200 select HAVE_DMA_CONTIGUOUS 50 select HAVE_DMA_CONTIGUOUS
201 select HAVE_DYNAMIC_FTRACE 51 select HAVE_DYNAMIC_FTRACE
202 select HAVE_DYNAMIC_FTRACE_WITH_ARGS \ !! 52 select HAVE_EXIT_THREAD
203 if (GCC_SUPPORTS_DYNAMIC_FTRAC <<
204 CLANG_SUPPORTS_DYNAMIC_FTR <<
205 select HAVE_DYNAMIC_FTRACE_WITH_DIRECT <<
206 if DYNAMIC_FTRACE_WITH_ARGS && <<
207 select HAVE_DYNAMIC_FTRACE_WITH_CALL_O <<
208 if (DYNAMIC_FTRACE_WITH_ARGS & <<
209 (CC_IS_CLANG || !CC_OPTIMI <<
210 select FTRACE_MCOUNT_USE_PATCHABLE_FUN <<
211 if DYNAMIC_FTRACE_WITH_ARGS <<
212 select HAVE_SAMPLE_FTRACE_DIRECT <<
213 select HAVE_SAMPLE_FTRACE_DIRECT_MULTI <<
214 select HAVE_EFFICIENT_UNALIGNED_ACCESS <<
215 select HAVE_GUP_FAST <<
216 select HAVE_FTRACE_MCOUNT_RECORD 53 select HAVE_FTRACE_MCOUNT_RECORD
217 select HAVE_FUNCTION_TRACER <<
218 select HAVE_FUNCTION_ERROR_INJECTION <<
219 select HAVE_FUNCTION_GRAPH_TRACER 54 select HAVE_FUNCTION_GRAPH_TRACER
220 select HAVE_FUNCTION_GRAPH_RETVAL !! 55 select HAVE_FUNCTION_TRACER
221 select HAVE_GCC_PLUGINS !! 56 select HAVE_GENERIC_DMA_COHERENT
222 select HAVE_HARDLOCKUP_DETECTOR_PERF i !! 57 select HAVE_IDE
223 HW_PERF_EVENTS && HAVE_PERF_EV !! 58 select HAVE_IRQ_EXIT_ON_IRQ_STACK
224 select HAVE_HW_BREAKPOINT if PERF_EVEN <<
225 select HAVE_IOREMAP_PROT <<
226 select HAVE_IRQ_TIME_ACCOUNTING 59 select HAVE_IRQ_TIME_ACCOUNTING
>> 60 select HAVE_KPROBES
>> 61 select HAVE_KRETPROBES
>> 62 select HAVE_MEMBLOCK
>> 63 select HAVE_MEMBLOCK_NODE_MAP
227 select HAVE_MOD_ARCH_SPECIFIC 64 select HAVE_MOD_ARCH_SPECIFIC
228 select HAVE_NMI 65 select HAVE_NMI
>> 66 select HAVE_OPROFILE
229 select HAVE_PERF_EVENTS 67 select HAVE_PERF_EVENTS
230 select HAVE_PERF_EVENTS_NMI if ARM64_P <<
231 select HAVE_PERF_REGS <<
232 select HAVE_PERF_USER_STACK_DUMP <<
233 select HAVE_PREEMPT_DYNAMIC_KEY <<
234 select HAVE_REGS_AND_STACK_ACCESS_API 68 select HAVE_REGS_AND_STACK_ACCESS_API
235 select HAVE_POSIX_CPU_TIMERS_TASK_WORK <<
236 select HAVE_FUNCTION_ARG_ACCESS_API <<
237 select MMU_GATHER_RCU_TABLE_FREE <<
238 select HAVE_RSEQ <<
239 select HAVE_RUST if RUSTC_SUPPORTS_ARM <<
240 select HAVE_STACKPROTECTOR <<
241 select HAVE_SYSCALL_TRACEPOINTS 69 select HAVE_SYSCALL_TRACEPOINTS
242 select HAVE_KPROBES !! 70 select HAVE_VIRT_CPU_ACCOUNTING_GEN if 64BIT || !SMP
243 select HAVE_KRETPROBES <<
244 select HAVE_GENERIC_VDSO <<
245 select HOTPLUG_CORE_SYNC_DEAD if HOTPL <<
246 select IRQ_DOMAIN <<
247 select IRQ_FORCED_THREADING 71 select IRQ_FORCED_THREADING
248 select KASAN_VMALLOC if KASAN !! 72 select MODULES_USE_ELF_RELA if MODULES && 64BIT
249 select LOCK_MM_AND_FIND_VMA !! 73 select MODULES_USE_ELF_REL if MODULES
250 select MODULES_USE_ELF_RELA !! 74 select PERF_USE_VMALLOC
251 select NEED_DMA_MAP_STATE !! 75 select RTC_LIB if !MACH_LOONGSON64
252 select NEED_SG_DMA_LENGTH <<
253 select OF <<
254 select OF_EARLY_FLATTREE <<
255 select PCI_DOMAINS_GENERIC if PCI <<
256 select PCI_ECAM if (ACPI && PCI) <<
257 select PCI_SYSCALL if PCI <<
258 select POWER_RESET <<
259 select POWER_SUPPLY <<
260 select SPARSE_IRQ <<
261 select SWIOTLB <<
262 select SYSCTL_EXCEPTION_TRACE 76 select SYSCTL_EXCEPTION_TRACE
263 select THREAD_INFO_IN_TASK !! 77 select VIRT_TO_BUS
264 select HAVE_ARCH_USERFAULTFD_MINOR if <<
265 select HAVE_ARCH_USERFAULTFD_WP if USE <<
266 select TRACE_IRQFLAGS_SUPPORT <<
267 select TRACE_IRQFLAGS_NMI_SUPPORT <<
268 select HAVE_SOFTIRQ_ON_OWN_STACK <<
269 select USER_STACKTRACE_SUPPORT <<
270 select VDSO_GETRANDOM <<
271 help <<
272 ARM 64-bit (AArch64) Linux support. <<
273 <<
274 config RUSTC_SUPPORTS_ARM64 <<
275 def_bool y <<
276 depends on CPU_LITTLE_ENDIAN <<
277 # Shadow call stack is only supported <<
278 # <<
279 # When using the UNWIND_PATCH_PAC_INTO <<
280 # required due to use of the -Zfixed-x <<
281 # <<
282 # Otherwise, rustc version 1.82+ is re <<
283 # -Zsanitizer=shadow-call-stack flag. <<
284 depends on !SHADOW_CALL_STACK || RUSTC <<
285 <<
286 config CLANG_SUPPORTS_DYNAMIC_FTRACE_WITH_ARGS <<
287 def_bool CC_IS_CLANG <<
288 # https://github.com/ClangBuiltLinux/l <<
289 depends on AS_IS_GNU || (AS_IS_LLVM && <<
290 <<
291 config GCC_SUPPORTS_DYNAMIC_FTRACE_WITH_ARGS <<
292 def_bool CC_IS_GCC <<
293 depends on $(cc-option,-fpatchable-fun <<
294 78
295 config 64BIT !! 79 menu "Machine selection"
296 def_bool y <<
297 <<
298 config MMU <<
299 def_bool y <<
300 80
301 config ARM64_CONT_PTE_SHIFT !! 81 choice
302 int !! 82 prompt "System type"
303 default 5 if PAGE_SIZE_64KB !! 83 default SGI_IP22
304 default 7 if PAGE_SIZE_16KB <<
305 default 4 <<
306 <<
307 config ARM64_CONT_PMD_SHIFT <<
308 int <<
309 default 5 if PAGE_SIZE_64KB <<
310 default 5 if PAGE_SIZE_16KB <<
311 default 4 <<
312 84
313 config ARCH_MMAP_RND_BITS_MIN !! 85 config MIPS_GENERIC
314 default 14 if PAGE_SIZE_64KB !! 86 bool "Generic board-agnostic MIPS kernel"
315 default 16 if PAGE_SIZE_16KB !! 87 select BOOT_RAW
316 default 18 !! 88 select BUILTIN_DTB
>> 89 select CEVT_R4K
>> 90 select CLKSRC_MIPS_GIC
>> 91 select COMMON_CLK
>> 92 select CPU_MIPSR2_IRQ_VI
>> 93 select CPU_MIPSR2_IRQ_EI
>> 94 select CSRC_R4K
>> 95 select DMA_PERDEV_COHERENT
>> 96 select HW_HAS_PCI
>> 97 select IRQ_MIPS_CPU
>> 98 select LIBFDT
>> 99 select MIPS_CPU_SCACHE
>> 100 select MIPS_GIC
>> 101 select MIPS_L1_CACHE_SHIFT_7
>> 102 select NO_EXCEPT_FILL
>> 103 select PCI_DRIVERS_GENERIC
>> 104 select PINCTRL
>> 105 select SMP_UP if SMP
>> 106 select SWAP_IO_SPACE
>> 107 select SYS_HAS_CPU_MIPS32_R1
>> 108 select SYS_HAS_CPU_MIPS32_R2
>> 109 select SYS_HAS_CPU_MIPS32_R6
>> 110 select SYS_HAS_CPU_MIPS64_R1
>> 111 select SYS_HAS_CPU_MIPS64_R2
>> 112 select SYS_HAS_CPU_MIPS64_R6
>> 113 select SYS_SUPPORTS_32BIT_KERNEL
>> 114 select SYS_SUPPORTS_64BIT_KERNEL
>> 115 select SYS_SUPPORTS_BIG_ENDIAN
>> 116 select SYS_SUPPORTS_HIGHMEM
>> 117 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 118 select SYS_SUPPORTS_MICROMIPS
>> 119 select SYS_SUPPORTS_MIPS_CPS
>> 120 select SYS_SUPPORTS_MIPS16
>> 121 select SYS_SUPPORTS_MULTITHREADING
>> 122 select SYS_SUPPORTS_RELOCATABLE
>> 123 select SYS_SUPPORTS_SMARTMIPS
>> 124 select USB_EHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
>> 125 select USB_EHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 126 select USB_OHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
>> 127 select USB_OHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 128 select USB_UHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
>> 129 select USB_UHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 130 select USE_OF
>> 131 help
>> 132 Select this to build a kernel which aims to support multiple boards,
>> 133 generally using a flattened device tree passed from the bootloader
>> 134 using the boot protocol defined in the UHI (Unified Hosting
>> 135 Interface) specification.
>> 136
>> 137 config MIPS_ALCHEMY
>> 138 bool "Alchemy processor based machines"
>> 139 select ARCH_PHYS_ADDR_T_64BIT
>> 140 select CEVT_R4K
>> 141 select CSRC_R4K
>> 142 select IRQ_MIPS_CPU
>> 143 select DMA_MAYBE_COHERENT # Au1000,1500,1100 aren't, rest is
>> 144 select SYS_HAS_CPU_MIPS32_R1
>> 145 select SYS_SUPPORTS_32BIT_KERNEL
>> 146 select SYS_SUPPORTS_APM_EMULATION
>> 147 select GPIOLIB
>> 148 select SYS_SUPPORTS_ZBOOT
>> 149 select COMMON_CLK
317 150
318 # max bits determined by the following formula !! 151 config AR7
319 # VA_BITS - PAGE_SHIFT - 3 !! 152 bool "Texas Instruments AR7"
320 config ARCH_MMAP_RND_BITS_MAX !! 153 select BOOT_ELF32
321 default 19 if ARM64_VA_BITS=36 !! 154 select DMA_NONCOHERENT
322 default 24 if ARM64_VA_BITS=39 !! 155 select CEVT_R4K
323 default 27 if ARM64_VA_BITS=42 !! 156 select CSRC_R4K
324 default 30 if ARM64_VA_BITS=47 !! 157 select IRQ_MIPS_CPU
325 default 29 if ARM64_VA_BITS=48 && ARM6 !! 158 select NO_EXCEPT_FILL
326 default 31 if ARM64_VA_BITS=48 && ARM6 !! 159 select SWAP_IO_SPACE
327 default 33 if ARM64_VA_BITS=48 !! 160 select SYS_HAS_CPU_MIPS32_R1
328 default 14 if ARM64_64K_PAGES !! 161 select SYS_HAS_EARLY_PRINTK
329 default 16 if ARM64_16K_PAGES !! 162 select SYS_SUPPORTS_32BIT_KERNEL
330 default 18 !! 163 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 164 select SYS_SUPPORTS_MIPS16
>> 165 select SYS_SUPPORTS_ZBOOT_UART16550
>> 166 select GPIOLIB
>> 167 select VLYNQ
>> 168 select HAVE_CLK
>> 169 help
>> 170 Support for the Texas Instruments AR7 System-on-a-Chip
>> 171 family: TNETD7100, 7200 and 7300.
>> 172
>> 173 config ATH25
>> 174 bool "Atheros AR231x/AR531x SoC support"
>> 175 select CEVT_R4K
>> 176 select CSRC_R4K
>> 177 select DMA_NONCOHERENT
>> 178 select IRQ_MIPS_CPU
>> 179 select IRQ_DOMAIN
>> 180 select SYS_HAS_CPU_MIPS32_R1
>> 181 select SYS_SUPPORTS_BIG_ENDIAN
>> 182 select SYS_SUPPORTS_32BIT_KERNEL
>> 183 select SYS_HAS_EARLY_PRINTK
>> 184 help
>> 185 Support for Atheros AR231x and Atheros AR531x based boards
>> 186
>> 187 config ATH79
>> 188 bool "Atheros AR71XX/AR724X/AR913X based boards"
>> 189 select ARCH_HAS_RESET_CONTROLLER
>> 190 select BOOT_RAW
>> 191 select CEVT_R4K
>> 192 select CSRC_R4K
>> 193 select DMA_NONCOHERENT
>> 194 select GPIOLIB
>> 195 select HAVE_CLK
>> 196 select COMMON_CLK
>> 197 select CLKDEV_LOOKUP
>> 198 select IRQ_MIPS_CPU
>> 199 select MIPS_MACHINE
>> 200 select SYS_HAS_CPU_MIPS32_R2
>> 201 select SYS_HAS_EARLY_PRINTK
>> 202 select SYS_SUPPORTS_32BIT_KERNEL
>> 203 select SYS_SUPPORTS_BIG_ENDIAN
>> 204 select SYS_SUPPORTS_MIPS16
>> 205 select SYS_SUPPORTS_ZBOOT_UART_PROM
>> 206 select USE_OF
>> 207 help
>> 208 Support for the Atheros AR71XX/AR724X/AR913X SoCs.
>> 209
>> 210 config BMIPS_GENERIC
>> 211 bool "Broadcom Generic BMIPS kernel"
>> 212 select BOOT_RAW
>> 213 select NO_EXCEPT_FILL
>> 214 select USE_OF
>> 215 select CEVT_R4K
>> 216 select CSRC_R4K
>> 217 select SYNC_R4K
>> 218 select COMMON_CLK
>> 219 select BCM6345_L1_IRQ
>> 220 select BCM7038_L1_IRQ
>> 221 select BCM7120_L2_IRQ
>> 222 select BRCMSTB_L2_IRQ
>> 223 select IRQ_MIPS_CPU
>> 224 select DMA_NONCOHERENT
>> 225 select SYS_SUPPORTS_32BIT_KERNEL
>> 226 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 227 select SYS_SUPPORTS_BIG_ENDIAN
>> 228 select SYS_SUPPORTS_HIGHMEM
>> 229 select SYS_HAS_CPU_BMIPS32_3300
>> 230 select SYS_HAS_CPU_BMIPS4350
>> 231 select SYS_HAS_CPU_BMIPS4380
>> 232 select SYS_HAS_CPU_BMIPS5000
>> 233 select SWAP_IO_SPACE
>> 234 select USB_EHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
>> 235 select USB_EHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 236 select USB_OHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
>> 237 select USB_OHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 238 help
>> 239 Build a generic DT-based kernel image that boots on select
>> 240 BCM33xx cable modem chips, BCM63xx DSL chips, and BCM7xxx set-top
>> 241 box chips. Note that CONFIG_CPU_BIG_ENDIAN/CONFIG_CPU_LITTLE_ENDIAN
>> 242 must be set appropriately for your board.
>> 243
>> 244 config BCM47XX
>> 245 bool "Broadcom BCM47XX based boards"
>> 246 select BOOT_RAW
>> 247 select CEVT_R4K
>> 248 select CSRC_R4K
>> 249 select DMA_NONCOHERENT
>> 250 select HW_HAS_PCI
>> 251 select IRQ_MIPS_CPU
>> 252 select SYS_HAS_CPU_MIPS32_R1
>> 253 select NO_EXCEPT_FILL
>> 254 select SYS_SUPPORTS_32BIT_KERNEL
>> 255 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 256 select SYS_SUPPORTS_MIPS16
>> 257 select SYS_HAS_EARLY_PRINTK
>> 258 select USE_GENERIC_EARLY_PRINTK_8250
>> 259 select GPIOLIB
>> 260 select LEDS_GPIO_REGISTER
>> 261 select BCM47XX_NVRAM
>> 262 select BCM47XX_SPROM
>> 263 help
>> 264 Support for BCM47XX based boards
>> 265
>> 266 config BCM63XX
>> 267 bool "Broadcom BCM63XX based boards"
>> 268 select BOOT_RAW
>> 269 select CEVT_R4K
>> 270 select CSRC_R4K
>> 271 select SYNC_R4K
>> 272 select DMA_NONCOHERENT
>> 273 select IRQ_MIPS_CPU
>> 274 select SYS_SUPPORTS_32BIT_KERNEL
>> 275 select SYS_SUPPORTS_BIG_ENDIAN
>> 276 select SYS_HAS_EARLY_PRINTK
>> 277 select SYS_HAS_CPU_BMIPS32_3300
>> 278 select SYS_HAS_CPU_BMIPS4350
>> 279 select SYS_HAS_CPU_BMIPS4380
>> 280 select SWAP_IO_SPACE
>> 281 select GPIOLIB
>> 282 select HAVE_CLK
>> 283 select MIPS_L1_CACHE_SHIFT_4
>> 284 help
>> 285 Support for BCM63XX based boards
>> 286
>> 287 config MIPS_COBALT
>> 288 bool "Cobalt Server"
>> 289 select CEVT_R4K
>> 290 select CSRC_R4K
>> 291 select CEVT_GT641XX
>> 292 select DMA_NONCOHERENT
>> 293 select HW_HAS_PCI
>> 294 select I8253
>> 295 select I8259
>> 296 select IRQ_MIPS_CPU
>> 297 select IRQ_GT641XX
>> 298 select PCI_GT64XXX_PCI0
>> 299 select PCI
>> 300 select SYS_HAS_CPU_NEVADA
>> 301 select SYS_HAS_EARLY_PRINTK
>> 302 select SYS_SUPPORTS_32BIT_KERNEL
>> 303 select SYS_SUPPORTS_64BIT_KERNEL
>> 304 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 305 select USE_GENERIC_EARLY_PRINTK_8250
>> 306
>> 307 config MACH_DECSTATION
>> 308 bool "DECstations"
>> 309 select BOOT_ELF32
>> 310 select CEVT_DS1287
>> 311 select CEVT_R4K if CPU_R4X00
>> 312 select CSRC_IOASIC
>> 313 select CSRC_R4K if CPU_R4X00
>> 314 select CPU_DADDI_WORKAROUNDS if 64BIT
>> 315 select CPU_R4000_WORKAROUNDS if 64BIT
>> 316 select CPU_R4400_WORKAROUNDS if 64BIT
>> 317 select DMA_NONCOHERENT
>> 318 select NO_IOPORT_MAP
>> 319 select IRQ_MIPS_CPU
>> 320 select SYS_HAS_CPU_R3000
>> 321 select SYS_HAS_CPU_R4X00
>> 322 select SYS_SUPPORTS_32BIT_KERNEL
>> 323 select SYS_SUPPORTS_64BIT_KERNEL
>> 324 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 325 select SYS_SUPPORTS_128HZ
>> 326 select SYS_SUPPORTS_256HZ
>> 327 select SYS_SUPPORTS_1024HZ
>> 328 select MIPS_L1_CACHE_SHIFT_4
>> 329 help
>> 330 This enables support for DEC's MIPS based workstations. For details
>> 331 see the Linux/MIPS FAQ on <http://www.linux-mips.org/> and the
>> 332 DECstation porting pages on <http://decstation.unix-ag.org/>.
>> 333
>> 334 If you have one of the following DECstation Models you definitely
>> 335 want to choose R4xx0 for the CPU Type:
>> 336
>> 337 DECstation 5000/50
>> 338 DECstation 5000/150
>> 339 DECstation 5000/260
>> 340 DECsystem 5900/260
>> 341
>> 342 otherwise choose R3000.
>> 343
>> 344 config MACH_JAZZ
>> 345 bool "Jazz family of machines"
>> 346 select FW_ARC
>> 347 select FW_ARC32
>> 348 select ARCH_MAY_HAVE_PC_FDC
>> 349 select CEVT_R4K
>> 350 select CSRC_R4K
>> 351 select DEFAULT_SGI_PARTITION if CPU_BIG_ENDIAN
>> 352 select GENERIC_ISA_DMA
>> 353 select HAVE_PCSPKR_PLATFORM
>> 354 select IRQ_MIPS_CPU
>> 355 select I8253
>> 356 select I8259
>> 357 select ISA
>> 358 select SYS_HAS_CPU_R4X00
>> 359 select SYS_SUPPORTS_32BIT_KERNEL
>> 360 select SYS_SUPPORTS_64BIT_KERNEL
>> 361 select SYS_SUPPORTS_100HZ
>> 362 help
>> 363 This a family of machines based on the MIPS R4030 chipset which was
>> 364 used by several vendors to build RISC/os and Windows NT workstations.
>> 365 Members include the Acer PICA, MIPS Magnum 4000, MIPS Millennium and
>> 366 Olivetti M700-10 workstations.
>> 367
>> 368 config MACH_INGENIC
>> 369 bool "Ingenic SoC based machines"
>> 370 select SYS_SUPPORTS_32BIT_KERNEL
>> 371 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 372 select SYS_SUPPORTS_ZBOOT_UART16550
>> 373 select DMA_NONCOHERENT
>> 374 select IRQ_MIPS_CPU
>> 375 select PINCTRL
>> 376 select GPIOLIB
>> 377 select COMMON_CLK
>> 378 select GENERIC_IRQ_CHIP
>> 379 select BUILTIN_DTB
>> 380 select USE_OF
>> 381 select LIBFDT
331 382
332 config ARCH_MMAP_RND_COMPAT_BITS_MIN !! 383 config LANTIQ
333 default 7 if ARM64_64K_PAGES !! 384 bool "Lantiq based platforms"
334 default 9 if ARM64_16K_PAGES !! 385 select DMA_NONCOHERENT
335 default 11 !! 386 select IRQ_MIPS_CPU
>> 387 select CEVT_R4K
>> 388 select CSRC_R4K
>> 389 select SYS_HAS_CPU_MIPS32_R1
>> 390 select SYS_HAS_CPU_MIPS32_R2
>> 391 select SYS_SUPPORTS_BIG_ENDIAN
>> 392 select SYS_SUPPORTS_32BIT_KERNEL
>> 393 select SYS_SUPPORTS_MIPS16
>> 394 select SYS_SUPPORTS_MULTITHREADING
>> 395 select SYS_HAS_EARLY_PRINTK
>> 396 select GPIOLIB
>> 397 select SWAP_IO_SPACE
>> 398 select BOOT_RAW
>> 399 select CLKDEV_LOOKUP
>> 400 select USE_OF
>> 401 select PINCTRL
>> 402 select PINCTRL_LANTIQ
>> 403 select ARCH_HAS_RESET_CONTROLLER
>> 404 select RESET_CONTROLLER
>> 405
>> 406 config LASAT
>> 407 bool "LASAT Networks platforms"
>> 408 select CEVT_R4K
>> 409 select CRC32
>> 410 select CSRC_R4K
>> 411 select DMA_NONCOHERENT
>> 412 select SYS_HAS_EARLY_PRINTK
>> 413 select HW_HAS_PCI
>> 414 select IRQ_MIPS_CPU
>> 415 select PCI_GT64XXX_PCI0
>> 416 select MIPS_NILE4
>> 417 select R5000_CPU_SCACHE
>> 418 select SYS_HAS_CPU_R5000
>> 419 select SYS_SUPPORTS_32BIT_KERNEL
>> 420 select SYS_SUPPORTS_64BIT_KERNEL if BROKEN
>> 421 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 422
>> 423 config MACH_LOONGSON32
>> 424 bool "Loongson-1 family of machines"
>> 425 select SYS_SUPPORTS_ZBOOT
>> 426 help
>> 427 This enables support for the Loongson-1 family of machines.
>> 428
>> 429 Loongson-1 is a family of 32-bit MIPS-compatible SoCs developed by
>> 430 the Institute of Computing Technology (ICT), Chinese Academy of
>> 431 Sciences (CAS).
>> 432
>> 433 config MACH_LOONGSON64
>> 434 bool "Loongson-2/3 family of machines"
>> 435 select SYS_SUPPORTS_ZBOOT
>> 436 help
>> 437 This enables the support of Loongson-2/3 family of machines.
>> 438
>> 439 Loongson-2 is a family of single-core CPUs and Loongson-3 is a
>> 440 family of multi-core CPUs. They are both 64-bit general-purpose
>> 441 MIPS-compatible CPUs. Loongson-2/3 are developed by the Institute
>> 442 of Computing Technology (ICT), Chinese Academy of Sciences (CAS)
>> 443 in the People's Republic of China. The chief architect is Professor
>> 444 Weiwu Hu.
>> 445
>> 446 config MACH_PISTACHIO
>> 447 bool "IMG Pistachio SoC based boards"
>> 448 select BOOT_ELF32
>> 449 select BOOT_RAW
>> 450 select CEVT_R4K
>> 451 select CLKSRC_MIPS_GIC
>> 452 select COMMON_CLK
>> 453 select CSRC_R4K
>> 454 select DMA_NONCOHERENT
>> 455 select GPIOLIB
>> 456 select IRQ_MIPS_CPU
>> 457 select LIBFDT
>> 458 select MFD_SYSCON
>> 459 select MIPS_CPU_SCACHE
>> 460 select MIPS_GIC
>> 461 select PINCTRL
>> 462 select REGULATOR
>> 463 select SYS_HAS_CPU_MIPS32_R2
>> 464 select SYS_SUPPORTS_32BIT_KERNEL
>> 465 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 466 select SYS_SUPPORTS_MIPS_CPS
>> 467 select SYS_SUPPORTS_MULTITHREADING
>> 468 select SYS_SUPPORTS_RELOCATABLE
>> 469 select SYS_SUPPORTS_ZBOOT
>> 470 select SYS_HAS_EARLY_PRINTK
>> 471 select USE_GENERIC_EARLY_PRINTK_8250
>> 472 select USE_OF
>> 473 help
>> 474 This enables support for the IMG Pistachio SoC platform.
>> 475
>> 476 config MACH_XILFPGA
>> 477 bool "MIPSfpga Xilinx based boards"
>> 478 select BOOT_ELF32
>> 479 select BOOT_RAW
>> 480 select BUILTIN_DTB
>> 481 select CEVT_R4K
>> 482 select COMMON_CLK
>> 483 select CSRC_R4K
>> 484 select GPIOLIB
>> 485 select IRQ_MIPS_CPU
>> 486 select LIBFDT
>> 487 select MIPS_CPU_SCACHE
>> 488 select SYS_HAS_EARLY_PRINTK
>> 489 select SYS_HAS_CPU_MIPS32_R2
>> 490 select SYS_SUPPORTS_32BIT_KERNEL
>> 491 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 492 select SYS_SUPPORTS_ZBOOT_UART16550
>> 493 select USE_OF
>> 494 select USE_GENERIC_EARLY_PRINTK_8250
>> 495 select XILINX_INTC
>> 496 help
>> 497 This enables support for the IMG University Program MIPSfpga platform.
>> 498
>> 499 config MIPS_MALTA
>> 500 bool "MIPS Malta board"
>> 501 select ARCH_MAY_HAVE_PC_FDC
>> 502 select BOOT_ELF32
>> 503 select BOOT_RAW
>> 504 select BUILTIN_DTB
>> 505 select CEVT_R4K
>> 506 select CSRC_R4K
>> 507 select CLKSRC_MIPS_GIC
>> 508 select COMMON_CLK
>> 509 select DMA_MAYBE_COHERENT
>> 510 select GENERIC_ISA_DMA
>> 511 select HAVE_PCSPKR_PLATFORM
>> 512 select IRQ_MIPS_CPU
>> 513 select MIPS_GIC
>> 514 select HW_HAS_PCI
>> 515 select I8253
>> 516 select I8259
>> 517 select MIPS_BONITO64
>> 518 select MIPS_CPU_SCACHE
>> 519 select MIPS_L1_CACHE_SHIFT_6
>> 520 select PCI_GT64XXX_PCI0
>> 521 select MIPS_MSC
>> 522 select SMP_UP if SMP
>> 523 select SWAP_IO_SPACE
>> 524 select SYS_HAS_CPU_MIPS32_R1
>> 525 select SYS_HAS_CPU_MIPS32_R2
>> 526 select SYS_HAS_CPU_MIPS32_R3_5
>> 527 select SYS_HAS_CPU_MIPS32_R5
>> 528 select SYS_HAS_CPU_MIPS32_R6
>> 529 select SYS_HAS_CPU_MIPS64_R1
>> 530 select SYS_HAS_CPU_MIPS64_R2
>> 531 select SYS_HAS_CPU_MIPS64_R6
>> 532 select SYS_HAS_CPU_NEVADA
>> 533 select SYS_HAS_CPU_RM7000
>> 534 select SYS_SUPPORTS_32BIT_KERNEL
>> 535 select SYS_SUPPORTS_64BIT_KERNEL
>> 536 select SYS_SUPPORTS_BIG_ENDIAN
>> 537 select SYS_SUPPORTS_HIGHMEM
>> 538 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 539 select SYS_SUPPORTS_MICROMIPS
>> 540 select SYS_SUPPORTS_MIPS_CMP
>> 541 select SYS_SUPPORTS_MIPS_CPS
>> 542 select SYS_SUPPORTS_MIPS16
>> 543 select SYS_SUPPORTS_MULTITHREADING
>> 544 select SYS_SUPPORTS_SMARTMIPS
>> 545 select SYS_SUPPORTS_ZBOOT
>> 546 select SYS_SUPPORTS_RELOCATABLE
>> 547 select USE_OF
>> 548 select LIBFDT
>> 549 select ZONE_DMA32 if 64BIT
>> 550 select BUILTIN_DTB
>> 551 select LIBFDT
>> 552 help
>> 553 This enables support for the MIPS Technologies Malta evaluation
>> 554 board.
336 555
337 config ARCH_MMAP_RND_COMPAT_BITS_MAX !! 556 config MACH_PIC32
338 default 16 !! 557 bool "Microchip PIC32 Family"
>> 558 help
>> 559 This enables support for the Microchip PIC32 family of platforms.
339 560
340 config NO_IOPORT_MAP !! 561 Microchip PIC32 is a family of general-purpose 32 bit MIPS core
341 def_bool y if !PCI !! 562 microcontrollers.
>> 563
>> 564 config NEC_MARKEINS
>> 565 bool "NEC EMMA2RH Mark-eins board"
>> 566 select SOC_EMMA2RH
>> 567 select HW_HAS_PCI
>> 568 help
>> 569 This enables support for the NEC Electronics Mark-eins boards.
>> 570
>> 571 config MACH_VR41XX
>> 572 bool "NEC VR4100 series based machines"
>> 573 select CEVT_R4K
>> 574 select CSRC_R4K
>> 575 select SYS_HAS_CPU_VR41XX
>> 576 select SYS_SUPPORTS_MIPS16
>> 577 select GPIOLIB
>> 578
>> 579 config NXP_STB220
>> 580 bool "NXP STB220 board"
>> 581 select SOC_PNX833X
>> 582 help
>> 583 Support for NXP Semiconductors STB220 Development Board.
>> 584
>> 585 config NXP_STB225
>> 586 bool "NXP 225 board"
>> 587 select SOC_PNX833X
>> 588 select SOC_PNX8335
>> 589 help
>> 590 Support for NXP Semiconductors STB225 Development Board.
>> 591
>> 592 config PMC_MSP
>> 593 bool "PMC-Sierra MSP chipsets"
>> 594 select CEVT_R4K
>> 595 select CSRC_R4K
>> 596 select DMA_NONCOHERENT
>> 597 select SWAP_IO_SPACE
>> 598 select NO_EXCEPT_FILL
>> 599 select BOOT_RAW
>> 600 select SYS_HAS_CPU_MIPS32_R1
>> 601 select SYS_HAS_CPU_MIPS32_R2
>> 602 select SYS_SUPPORTS_32BIT_KERNEL
>> 603 select SYS_SUPPORTS_BIG_ENDIAN
>> 604 select SYS_SUPPORTS_MIPS16
>> 605 select IRQ_MIPS_CPU
>> 606 select SERIAL_8250
>> 607 select SERIAL_8250_CONSOLE
>> 608 select USB_EHCI_BIG_ENDIAN_MMIO
>> 609 select USB_EHCI_BIG_ENDIAN_DESC
>> 610 help
>> 611 This adds support for the PMC-Sierra family of Multi-Service
>> 612 Processor System-On-A-Chips. These parts include a number
>> 613 of integrated peripherals, interfaces and DSPs in addition to
>> 614 a variety of MIPS cores.
>> 615
>> 616 config RALINK
>> 617 bool "Ralink based machines"
>> 618 select CEVT_R4K
>> 619 select CSRC_R4K
>> 620 select BOOT_RAW
>> 621 select DMA_NONCOHERENT
>> 622 select IRQ_MIPS_CPU
>> 623 select USE_OF
>> 624 select SYS_HAS_CPU_MIPS32_R1
>> 625 select SYS_HAS_CPU_MIPS32_R2
>> 626 select SYS_SUPPORTS_32BIT_KERNEL
>> 627 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 628 select SYS_SUPPORTS_MIPS16
>> 629 select SYS_HAS_EARLY_PRINTK
>> 630 select CLKDEV_LOOKUP
>> 631 select ARCH_HAS_RESET_CONTROLLER
>> 632 select RESET_CONTROLLER
>> 633
>> 634 config SGI_IP22
>> 635 bool "SGI IP22 (Indy/Indigo2)"
>> 636 select FW_ARC
>> 637 select FW_ARC32
>> 638 select BOOT_ELF32
>> 639 select CEVT_R4K
>> 640 select CSRC_R4K
>> 641 select DEFAULT_SGI_PARTITION
>> 642 select DMA_NONCOHERENT
>> 643 select HW_HAS_EISA
>> 644 select I8253
>> 645 select I8259
>> 646 select IP22_CPU_SCACHE
>> 647 select IRQ_MIPS_CPU
>> 648 select GENERIC_ISA_DMA_SUPPORT_BROKEN
>> 649 select SGI_HAS_I8042
>> 650 select SGI_HAS_INDYDOG
>> 651 select SGI_HAS_HAL2
>> 652 select SGI_HAS_SEEQ
>> 653 select SGI_HAS_WD93
>> 654 select SGI_HAS_ZILOG
>> 655 select SWAP_IO_SPACE
>> 656 select SYS_HAS_CPU_R4X00
>> 657 select SYS_HAS_CPU_R5000
>> 658 #
>> 659 # Disable EARLY_PRINTK for now since it leads to overwritten prom
>> 660 # memory during early boot on some machines.
>> 661 #
>> 662 # See http://www.linux-mips.org/cgi-bin/mesg.cgi?a=linux-mips&i=20091119164009.GA15038%40deprecation.cyrius.com
>> 663 # for a more details discussion
>> 664 #
>> 665 # select SYS_HAS_EARLY_PRINTK
>> 666 select SYS_SUPPORTS_32BIT_KERNEL
>> 667 select SYS_SUPPORTS_64BIT_KERNEL
>> 668 select SYS_SUPPORTS_BIG_ENDIAN
>> 669 select MIPS_L1_CACHE_SHIFT_7
>> 670 help
>> 671 This are the SGI Indy, Challenge S and Indigo2, as well as certain
>> 672 OEM variants like the Tandem CMN B006S. To compile a Linux kernel
>> 673 that runs on these, say Y here.
>> 674
>> 675 config SGI_IP27
>> 676 bool "SGI IP27 (Origin200/2000)"
>> 677 select FW_ARC
>> 678 select FW_ARC64
>> 679 select BOOT_ELF64
>> 680 select DEFAULT_SGI_PARTITION
>> 681 select DMA_COHERENT
>> 682 select SYS_HAS_EARLY_PRINTK
>> 683 select HW_HAS_PCI
>> 684 select NR_CPUS_DEFAULT_64
>> 685 select SYS_HAS_CPU_R10000
>> 686 select SYS_SUPPORTS_64BIT_KERNEL
>> 687 select SYS_SUPPORTS_BIG_ENDIAN
>> 688 select SYS_SUPPORTS_NUMA
>> 689 select SYS_SUPPORTS_SMP
>> 690 select MIPS_L1_CACHE_SHIFT_7
>> 691 help
>> 692 This are the SGI Origin 200, Origin 2000 and Onyx 2 Graphics
>> 693 workstations. To compile a Linux kernel that runs on these, say Y
>> 694 here.
>> 695
>> 696 config SGI_IP28
>> 697 bool "SGI IP28 (Indigo2 R10k)"
>> 698 select FW_ARC
>> 699 select FW_ARC64
>> 700 select BOOT_ELF64
>> 701 select CEVT_R4K
>> 702 select CSRC_R4K
>> 703 select DEFAULT_SGI_PARTITION
>> 704 select DMA_NONCOHERENT
>> 705 select GENERIC_ISA_DMA_SUPPORT_BROKEN
>> 706 select IRQ_MIPS_CPU
>> 707 select HW_HAS_EISA
>> 708 select I8253
>> 709 select I8259
>> 710 select SGI_HAS_I8042
>> 711 select SGI_HAS_INDYDOG
>> 712 select SGI_HAS_HAL2
>> 713 select SGI_HAS_SEEQ
>> 714 select SGI_HAS_WD93
>> 715 select SGI_HAS_ZILOG
>> 716 select SWAP_IO_SPACE
>> 717 select SYS_HAS_CPU_R10000
>> 718 #
>> 719 # Disable EARLY_PRINTK for now since it leads to overwritten prom
>> 720 # memory during early boot on some machines.
>> 721 #
>> 722 # See http://www.linux-mips.org/cgi-bin/mesg.cgi?a=linux-mips&i=20091119164009.GA15038%40deprecation.cyrius.com
>> 723 # for a more details discussion
>> 724 #
>> 725 # select SYS_HAS_EARLY_PRINTK
>> 726 select SYS_SUPPORTS_64BIT_KERNEL
>> 727 select SYS_SUPPORTS_BIG_ENDIAN
>> 728 select MIPS_L1_CACHE_SHIFT_7
>> 729 help
>> 730 This is the SGI Indigo2 with R10000 processor. To compile a Linux
>> 731 kernel that runs on these, say Y here.
>> 732
>> 733 config SGI_IP32
>> 734 bool "SGI IP32 (O2)"
>> 735 select FW_ARC
>> 736 select FW_ARC32
>> 737 select BOOT_ELF32
>> 738 select CEVT_R4K
>> 739 select CSRC_R4K
>> 740 select DMA_NONCOHERENT
>> 741 select HW_HAS_PCI
>> 742 select IRQ_MIPS_CPU
>> 743 select R5000_CPU_SCACHE
>> 744 select RM7000_CPU_SCACHE
>> 745 select SYS_HAS_CPU_R5000
>> 746 select SYS_HAS_CPU_R10000 if BROKEN
>> 747 select SYS_HAS_CPU_RM7000
>> 748 select SYS_HAS_CPU_NEVADA
>> 749 select SYS_SUPPORTS_64BIT_KERNEL
>> 750 select SYS_SUPPORTS_BIG_ENDIAN
>> 751 help
>> 752 If you want this kernel to run on SGI O2 workstation, say Y here.
>> 753
>> 754 config SIBYTE_CRHINE
>> 755 bool "Sibyte BCM91120C-CRhine"
>> 756 select BOOT_ELF32
>> 757 select DMA_COHERENT
>> 758 select SIBYTE_BCM1120
>> 759 select SWAP_IO_SPACE
>> 760 select SYS_HAS_CPU_SB1
>> 761 select SYS_SUPPORTS_BIG_ENDIAN
>> 762 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 763
>> 764 config SIBYTE_CARMEL
>> 765 bool "Sibyte BCM91120x-Carmel"
>> 766 select BOOT_ELF32
>> 767 select DMA_COHERENT
>> 768 select SIBYTE_BCM1120
>> 769 select SWAP_IO_SPACE
>> 770 select SYS_HAS_CPU_SB1
>> 771 select SYS_SUPPORTS_BIG_ENDIAN
>> 772 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 773
>> 774 config SIBYTE_CRHONE
>> 775 bool "Sibyte BCM91125C-CRhone"
>> 776 select BOOT_ELF32
>> 777 select DMA_COHERENT
>> 778 select SIBYTE_BCM1125
>> 779 select SWAP_IO_SPACE
>> 780 select SYS_HAS_CPU_SB1
>> 781 select SYS_SUPPORTS_BIG_ENDIAN
>> 782 select SYS_SUPPORTS_HIGHMEM
>> 783 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 784
>> 785 config SIBYTE_RHONE
>> 786 bool "Sibyte BCM91125E-Rhone"
>> 787 select BOOT_ELF32
>> 788 select DMA_COHERENT
>> 789 select SIBYTE_BCM1125H
>> 790 select SWAP_IO_SPACE
>> 791 select SYS_HAS_CPU_SB1
>> 792 select SYS_SUPPORTS_BIG_ENDIAN
>> 793 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 794
>> 795 config SIBYTE_SWARM
>> 796 bool "Sibyte BCM91250A-SWARM"
>> 797 select BOOT_ELF32
>> 798 select DMA_COHERENT
>> 799 select HAVE_PATA_PLATFORM
>> 800 select SIBYTE_SB1250
>> 801 select SWAP_IO_SPACE
>> 802 select SYS_HAS_CPU_SB1
>> 803 select SYS_SUPPORTS_BIG_ENDIAN
>> 804 select SYS_SUPPORTS_HIGHMEM
>> 805 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 806 select ZONE_DMA32 if 64BIT
>> 807
>> 808 config SIBYTE_LITTLESUR
>> 809 bool "Sibyte BCM91250C2-LittleSur"
>> 810 select BOOT_ELF32
>> 811 select DMA_COHERENT
>> 812 select HAVE_PATA_PLATFORM
>> 813 select SIBYTE_SB1250
>> 814 select SWAP_IO_SPACE
>> 815 select SYS_HAS_CPU_SB1
>> 816 select SYS_SUPPORTS_BIG_ENDIAN
>> 817 select SYS_SUPPORTS_HIGHMEM
>> 818 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 819 select ZONE_DMA32 if 64BIT
>> 820
>> 821 config SIBYTE_SENTOSA
>> 822 bool "Sibyte BCM91250E-Sentosa"
>> 823 select BOOT_ELF32
>> 824 select DMA_COHERENT
>> 825 select SIBYTE_SB1250
>> 826 select SWAP_IO_SPACE
>> 827 select SYS_HAS_CPU_SB1
>> 828 select SYS_SUPPORTS_BIG_ENDIAN
>> 829 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 830
>> 831 config SIBYTE_BIGSUR
>> 832 bool "Sibyte BCM91480B-BigSur"
>> 833 select BOOT_ELF32
>> 834 select DMA_COHERENT
>> 835 select NR_CPUS_DEFAULT_4
>> 836 select SIBYTE_BCM1x80
>> 837 select SWAP_IO_SPACE
>> 838 select SYS_HAS_CPU_SB1
>> 839 select SYS_SUPPORTS_BIG_ENDIAN
>> 840 select SYS_SUPPORTS_HIGHMEM
>> 841 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 842 select ZONE_DMA32 if 64BIT
>> 843
>> 844 config SNI_RM
>> 845 bool "SNI RM200/300/400"
>> 846 select FW_ARC if CPU_LITTLE_ENDIAN
>> 847 select FW_ARC32 if CPU_LITTLE_ENDIAN
>> 848 select FW_SNIPROM if CPU_BIG_ENDIAN
>> 849 select ARCH_MAY_HAVE_PC_FDC
>> 850 select BOOT_ELF32
>> 851 select CEVT_R4K
>> 852 select CSRC_R4K
>> 853 select DEFAULT_SGI_PARTITION if CPU_BIG_ENDIAN
>> 854 select DMA_NONCOHERENT
>> 855 select GENERIC_ISA_DMA
>> 856 select HAVE_PCSPKR_PLATFORM
>> 857 select HW_HAS_EISA
>> 858 select HW_HAS_PCI
>> 859 select IRQ_MIPS_CPU
>> 860 select I8253
>> 861 select I8259
>> 862 select ISA
>> 863 select MIPS_L1_CACHE_SHIFT_6
>> 864 select SWAP_IO_SPACE if CPU_BIG_ENDIAN
>> 865 select SYS_HAS_CPU_R4X00
>> 866 select SYS_HAS_CPU_R5000
>> 867 select SYS_HAS_CPU_R10000
>> 868 select R5000_CPU_SCACHE
>> 869 select SYS_HAS_EARLY_PRINTK
>> 870 select SYS_SUPPORTS_32BIT_KERNEL
>> 871 select SYS_SUPPORTS_64BIT_KERNEL
>> 872 select SYS_SUPPORTS_BIG_ENDIAN
>> 873 select SYS_SUPPORTS_HIGHMEM
>> 874 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 875 help
>> 876 The SNI RM200/300/400 are MIPS-based machines manufactured by
>> 877 Siemens Nixdorf Informationssysteme (SNI), parent company of Pyramid
>> 878 Technology and now in turn merged with Fujitsu. Say Y here to
>> 879 support this machine type.
>> 880
>> 881 config MACH_TX39XX
>> 882 bool "Toshiba TX39 series based machines"
>> 883
>> 884 config MACH_TX49XX
>> 885 bool "Toshiba TX49 series based machines"
>> 886
>> 887 config MIKROTIK_RB532
>> 888 bool "Mikrotik RB532 boards"
>> 889 select CEVT_R4K
>> 890 select CSRC_R4K
>> 891 select DMA_NONCOHERENT
>> 892 select HW_HAS_PCI
>> 893 select IRQ_MIPS_CPU
>> 894 select SYS_HAS_CPU_MIPS32_R1
>> 895 select SYS_SUPPORTS_32BIT_KERNEL
>> 896 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 897 select SWAP_IO_SPACE
>> 898 select BOOT_RAW
>> 899 select GPIOLIB
>> 900 select MIPS_L1_CACHE_SHIFT_4
>> 901 help
>> 902 Support the Mikrotik(tm) RouterBoard 532 series,
>> 903 based on the IDT RC32434 SoC.
>> 904
>> 905 config CAVIUM_OCTEON_SOC
>> 906 bool "Cavium Networks Octeon SoC based boards"
>> 907 select CEVT_R4K
>> 908 select ARCH_PHYS_ADDR_T_64BIT
>> 909 select DMA_COHERENT
>> 910 select SYS_SUPPORTS_64BIT_KERNEL
>> 911 select SYS_SUPPORTS_BIG_ENDIAN
>> 912 select EDAC_SUPPORT
>> 913 select EDAC_ATOMIC_SCRUB
>> 914 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 915 select SYS_SUPPORTS_HOTPLUG_CPU if CPU_BIG_ENDIAN
>> 916 select SYS_HAS_EARLY_PRINTK
>> 917 select SYS_HAS_CPU_CAVIUM_OCTEON
>> 918 select HW_HAS_PCI
>> 919 select ZONE_DMA32
>> 920 select HOLES_IN_ZONE
>> 921 select GPIOLIB
>> 922 select LIBFDT
>> 923 select USE_OF
>> 924 select ARCH_SPARSEMEM_ENABLE
>> 925 select SYS_SUPPORTS_SMP
>> 926 select NR_CPUS_DEFAULT_16
>> 927 select BUILTIN_DTB
>> 928 select MTD_COMPLEX_MAPPINGS
>> 929 select SYS_SUPPORTS_RELOCATABLE
>> 930 help
>> 931 This option supports all of the Octeon reference boards from Cavium
>> 932 Networks. It builds a kernel that dynamically determines the Octeon
>> 933 CPU type and supports all known board reference implementations.
>> 934 Some of the supported boards are:
>> 935 EBT3000
>> 936 EBH3000
>> 937 EBH3100
>> 938 Thunder
>> 939 Kodama
>> 940 Hikari
>> 941 Say Y here for most Octeon reference boards.
>> 942
>> 943 config NLM_XLR_BOARD
>> 944 bool "Netlogic XLR/XLS based systems"
>> 945 select BOOT_ELF32
>> 946 select NLM_COMMON
>> 947 select SYS_HAS_CPU_XLR
>> 948 select SYS_SUPPORTS_SMP
>> 949 select HW_HAS_PCI
>> 950 select SWAP_IO_SPACE
>> 951 select SYS_SUPPORTS_32BIT_KERNEL
>> 952 select SYS_SUPPORTS_64BIT_KERNEL
>> 953 select ARCH_PHYS_ADDR_T_64BIT
>> 954 select SYS_SUPPORTS_BIG_ENDIAN
>> 955 select SYS_SUPPORTS_HIGHMEM
>> 956 select DMA_COHERENT
>> 957 select NR_CPUS_DEFAULT_32
>> 958 select CEVT_R4K
>> 959 select CSRC_R4K
>> 960 select IRQ_MIPS_CPU
>> 961 select ZONE_DMA32 if 64BIT
>> 962 select SYNC_R4K
>> 963 select SYS_HAS_EARLY_PRINTK
>> 964 select SYS_SUPPORTS_ZBOOT
>> 965 select SYS_SUPPORTS_ZBOOT_UART16550
>> 966 help
>> 967 Support for systems based on Netlogic XLR and XLS processors.
>> 968 Say Y here if you have a XLR or XLS based board.
>> 969
>> 970 config NLM_XLP_BOARD
>> 971 bool "Netlogic XLP based systems"
>> 972 select BOOT_ELF32
>> 973 select NLM_COMMON
>> 974 select SYS_HAS_CPU_XLP
>> 975 select SYS_SUPPORTS_SMP
>> 976 select HW_HAS_PCI
>> 977 select SYS_SUPPORTS_32BIT_KERNEL
>> 978 select SYS_SUPPORTS_64BIT_KERNEL
>> 979 select ARCH_PHYS_ADDR_T_64BIT
>> 980 select GPIOLIB
>> 981 select SYS_SUPPORTS_BIG_ENDIAN
>> 982 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 983 select SYS_SUPPORTS_HIGHMEM
>> 984 select DMA_COHERENT
>> 985 select NR_CPUS_DEFAULT_32
>> 986 select CEVT_R4K
>> 987 select CSRC_R4K
>> 988 select IRQ_MIPS_CPU
>> 989 select ZONE_DMA32 if 64BIT
>> 990 select SYNC_R4K
>> 991 select SYS_HAS_EARLY_PRINTK
>> 992 select USE_OF
>> 993 select SYS_SUPPORTS_ZBOOT
>> 994 select SYS_SUPPORTS_ZBOOT_UART16550
>> 995 help
>> 996 This board is based on Netlogic XLP Processor.
>> 997 Say Y here if you have a XLP based board.
>> 998
>> 999 config MIPS_PARAVIRT
>> 1000 bool "Para-Virtualized guest system"
>> 1001 select CEVT_R4K
>> 1002 select CSRC_R4K
>> 1003 select DMA_COHERENT
>> 1004 select SYS_SUPPORTS_64BIT_KERNEL
>> 1005 select SYS_SUPPORTS_32BIT_KERNEL
>> 1006 select SYS_SUPPORTS_BIG_ENDIAN
>> 1007 select SYS_SUPPORTS_SMP
>> 1008 select NR_CPUS_DEFAULT_4
>> 1009 select SYS_HAS_EARLY_PRINTK
>> 1010 select SYS_HAS_CPU_MIPS32_R2
>> 1011 select SYS_HAS_CPU_MIPS64_R2
>> 1012 select SYS_HAS_CPU_CAVIUM_OCTEON
>> 1013 select HW_HAS_PCI
>> 1014 select SWAP_IO_SPACE
>> 1015 help
>> 1016 This option supports guest running under ????
342 1017
343 config STACKTRACE_SUPPORT !! 1018 endchoice
344 def_bool y <<
345 1019
346 config ILLEGAL_POINTER_VALUE !! 1020 source "arch/mips/alchemy/Kconfig"
347 hex !! 1021 source "arch/mips/ath25/Kconfig"
348 default 0xdead000000000000 !! 1022 source "arch/mips/ath79/Kconfig"
>> 1023 source "arch/mips/bcm47xx/Kconfig"
>> 1024 source "arch/mips/bcm63xx/Kconfig"
>> 1025 source "arch/mips/bmips/Kconfig"
>> 1026 source "arch/mips/generic/Kconfig"
>> 1027 source "arch/mips/jazz/Kconfig"
>> 1028 source "arch/mips/jz4740/Kconfig"
>> 1029 source "arch/mips/lantiq/Kconfig"
>> 1030 source "arch/mips/lasat/Kconfig"
>> 1031 source "arch/mips/pic32/Kconfig"
>> 1032 source "arch/mips/pistachio/Kconfig"
>> 1033 source "arch/mips/pmcs-msp71xx/Kconfig"
>> 1034 source "arch/mips/ralink/Kconfig"
>> 1035 source "arch/mips/sgi-ip27/Kconfig"
>> 1036 source "arch/mips/sibyte/Kconfig"
>> 1037 source "arch/mips/txx9/Kconfig"
>> 1038 source "arch/mips/vr41xx/Kconfig"
>> 1039 source "arch/mips/cavium-octeon/Kconfig"
>> 1040 source "arch/mips/loongson32/Kconfig"
>> 1041 source "arch/mips/loongson64/Kconfig"
>> 1042 source "arch/mips/netlogic/Kconfig"
>> 1043 source "arch/mips/paravirt/Kconfig"
>> 1044 source "arch/mips/xilfpga/Kconfig"
349 1045
350 config LOCKDEP_SUPPORT !! 1046 endmenu
351 def_bool y <<
352 1047
353 config GENERIC_BUG !! 1048 config RWSEM_GENERIC_SPINLOCK
354 def_bool y !! 1049 bool
355 depends on BUG !! 1050 default y
356 1051
357 config GENERIC_BUG_RELATIVE_POINTERS !! 1052 config RWSEM_XCHGADD_ALGORITHM
358 def_bool y !! 1053 bool
359 depends on GENERIC_BUG <<
360 1054
361 config GENERIC_HWEIGHT 1055 config GENERIC_HWEIGHT
362 def_bool y !! 1056 bool
363 !! 1057 default y
364 config GENERIC_CSUM <<
365 def_bool y <<
366 1058
367 config GENERIC_CALIBRATE_DELAY 1059 config GENERIC_CALIBRATE_DELAY
368 def_bool y <<
369 <<
370 config SMP <<
371 def_bool y <<
372 <<
373 config KERNEL_MODE_NEON <<
374 def_bool y <<
375 <<
376 config FIX_EARLYCON_MEM <<
377 def_bool y <<
378 <<
379 config PGTABLE_LEVELS <<
380 int <<
381 default 2 if ARM64_16K_PAGES && ARM64_ <<
382 default 2 if ARM64_64K_PAGES && ARM64_ <<
383 default 3 if ARM64_64K_PAGES && (ARM64 <<
384 default 3 if ARM64_4K_PAGES && ARM64_V <<
385 default 3 if ARM64_16K_PAGES && ARM64_ <<
386 default 4 if ARM64_16K_PAGES && (ARM64 <<
387 default 4 if !ARM64_64K_PAGES && ARM64 <<
388 default 5 if ARM64_4K_PAGES && ARM64_V <<
389 <<
390 config ARCH_SUPPORTS_UPROBES <<
391 def_bool y <<
392 <<
393 config ARCH_PROC_KCORE_TEXT <<
394 def_bool y <<
395 <<
396 config BROKEN_GAS_INST <<
397 def_bool !$(as-instr,1:\n.inst 0\n.rep <<
398 <<
399 config BUILTIN_RETURN_ADDRESS_STRIPS_PAC <<
400 bool 1060 bool
401 # Clang's __builtin_return_address() s !! 1061 default y
402 # https://github.com/llvm/llvm-project <<
403 default y if CC_IS_CLANG <<
404 # GCC's __builtin_return_address() str <<
405 # and this was backported to 10.2.0, 9 <<
406 # https://gcc.gnu.org/bugzilla/show_bu <<
407 default y if CC_IS_GCC && (GCC_VERSION <<
408 default y if CC_IS_GCC && (GCC_VERSION <<
409 default y if CC_IS_GCC && (GCC_VERSION <<
410 default y if CC_IS_GCC && (GCC_VERSION <<
411 default n <<
412 <<
413 config KASAN_SHADOW_OFFSET <<
414 hex <<
415 depends on KASAN_GENERIC || KASAN_SW_T <<
416 default 0xdfff800000000000 if (ARM64_V <<
417 default 0xdfffc00000000000 if (ARM64_V <<
418 default 0xdffffe0000000000 if ARM64_VA <<
419 default 0xdfffffc000000000 if ARM64_VA <<
420 default 0xdffffff800000000 if ARM64_VA <<
421 default 0xefff800000000000 if (ARM64_V <<
422 default 0xefffc00000000000 if (ARM64_V <<
423 default 0xeffffe0000000000 if ARM64_VA <<
424 default 0xefffffc000000000 if ARM64_VA <<
425 default 0xeffffff800000000 if ARM64_VA <<
426 default 0xffffffffffffffff <<
427 <<
428 config UNWIND_TABLES <<
429 bool <<
430 <<
431 source "arch/arm64/Kconfig.platforms" <<
432 <<
433 menu "Kernel Features" <<
434 <<
435 menu "ARM errata workarounds via the alternati <<
436 <<
437 config AMPERE_ERRATUM_AC03_CPU_38 <<
438 bool "AmpereOne: AC03_CPU_38: Certain <<
439 default y <<
440 help <<
441 This option adds an alternative code <<
442 errata AC03_CPU_38 and AC04_CPU_10 o <<
443 <<
444 The affected design reports FEAT_HAF <<
445 ID_AA64MMFR1_EL1.HAFDBS, but (V)TCR_ <<
446 as required by the architecture. The <<
447 implementation suffers from an addit <<
448 A/D updates can occur after a PTE ha <<
449 <<
450 The workaround forces KVM to explici <<
451 which avoids enabling unadvertised h <<
452 at stage-2. <<
453 <<
454 If unsure, say Y. <<
455 1062
456 config ARM64_WORKAROUND_CLEAN_CACHE !! 1063 config SCHED_OMIT_FRAME_POINTER
457 bool 1064 bool
458 <<
459 config ARM64_ERRATUM_826319 <<
460 bool "Cortex-A53: 826319: System might <<
461 default y 1065 default y
462 select ARM64_WORKAROUND_CLEAN_CACHE <<
463 help <<
464 This option adds an alternative code <<
465 erratum 826319 on Cortex-A53 parts u <<
466 AXI master interface and an L2 cache <<
467 <<
468 If a Cortex-A53 uses an AMBA AXI4 AC <<
469 and is unable to accept a certain wr <<
470 not progress on read data presented <<
471 system can deadlock. <<
472 1066
473 The workaround promotes data cache c !! 1067 #
474 data cache clean-and-invalidate. !! 1068 # Select some configuration options automatically based on user selections.
475 Please note that this does not neces !! 1069 #
476 as it depends on the alternative fra !! 1070 config FW_ARC
477 the kernel if an affected CPU is det !! 1071 bool
478 <<
479 If unsure, say Y. <<
480 <<
481 config ARM64_ERRATUM_827319 <<
482 bool "Cortex-A53: 827319: Data cache c <<
483 default y <<
484 select ARM64_WORKAROUND_CLEAN_CACHE <<
485 help <<
486 This option adds an alternative code <<
487 erratum 827319 on Cortex-A53 parts u <<
488 master interface and an L2 cache. <<
489 <<
490 Under certain conditions this erratu <<
491 to occur at the same time as another <<
492 on the AMBA 5 CHI interface, which c <<
493 interconnect reorders the two transa <<
494 <<
495 The workaround promotes data cache c <<
496 data cache clean-and-invalidate. <<
497 Please note that this does not neces <<
498 as it depends on the alternative fra <<
499 the kernel if an affected CPU is det <<
500 1072
501 If unsure, say Y. !! 1073 config ARCH_MAY_HAVE_PC_FDC
>> 1074 bool
502 1075
503 config ARM64_ERRATUM_824069 !! 1076 config BOOT_RAW
504 bool "Cortex-A53: 824069: Cache line m !! 1077 bool
505 default y <<
506 select ARM64_WORKAROUND_CLEAN_CACHE <<
507 help <<
508 This option adds an alternative code <<
509 erratum 824069 on Cortex-A53 parts u <<
510 to a coherent interconnect. <<
511 <<
512 If a Cortex-A53 processor is executi <<
513 write instruction at the same time a <<
514 cluster is executing a cache mainten <<
515 address, then this erratum might cau <<
516 incorrectly marked as dirty. <<
517 <<
518 The workaround promotes data cache c <<
519 data cache clean-and-invalidate. <<
520 Please note that this option does no <<
521 workaround, as it depends on the alt <<
522 only patch the kernel if an affected <<
523 1078
524 If unsure, say Y. !! 1079 config CEVT_BCM1480
>> 1080 bool
525 1081
526 config ARM64_ERRATUM_819472 !! 1082 config CEVT_DS1287
527 bool "Cortex-A53: 819472: Store exclus !! 1083 bool
528 default y <<
529 select ARM64_WORKAROUND_CLEAN_CACHE <<
530 help <<
531 This option adds an alternative code <<
532 erratum 819472 on Cortex-A53 parts u <<
533 present when it is connected to a co <<
534 <<
535 If the processor is executing a load <<
536 the same time as a processor in anot <<
537 maintenance operation to the same ad <<
538 cause data corruption. <<
539 <<
540 The workaround promotes data cache c <<
541 data cache clean-and-invalidate. <<
542 Please note that this does not neces <<
543 as it depends on the alternative fra <<
544 the kernel if an affected CPU is det <<
545 1084
546 If unsure, say Y. !! 1085 config CEVT_GT641XX
>> 1086 bool
547 1087
548 config ARM64_ERRATUM_832075 !! 1088 config CEVT_R4K
549 bool "Cortex-A57: 832075: possible dea !! 1089 bool
550 default y <<
551 help <<
552 This option adds an alternative code <<
553 erratum 832075 on Cortex-A57 parts u <<
554 1090
555 Affected Cortex-A57 parts might dead !! 1091 config CEVT_SB1250
556 instructions to Write-Back memory ar !! 1092 bool
557 1093
558 The workaround is to promote device !! 1094 config CEVT_TXX9
559 semantics. !! 1095 bool
560 Please note that this does not neces <<
561 as it depends on the alternative fra <<
562 the kernel if an affected CPU is det <<
563 1096
564 If unsure, say Y. !! 1097 config CSRC_BCM1480
>> 1098 bool
565 1099
566 config ARM64_ERRATUM_834220 !! 1100 config CSRC_IOASIC
567 bool "Cortex-A57: 834220: Stage 2 tran !! 1101 bool
568 depends on KVM <<
569 help <<
570 This option adds an alternative code <<
571 erratum 834220 on Cortex-A57 parts u <<
572 <<
573 Affected Cortex-A57 parts might repo <<
574 fault as the result of a Stage 1 fau <<
575 page boundary when there is a permis <<
576 alignment fault at Stage 1 and a tra <<
577 <<
578 The workaround is to verify that the <<
579 doesn't generate a fault before hand <<
580 Please note that this does not neces <<
581 as it depends on the alternative fra <<
582 the kernel if an affected CPU is det <<
583 1102
584 If unsure, say N. !! 1103 config CSRC_R4K
>> 1104 bool
585 1105
586 config ARM64_ERRATUM_1742098 !! 1106 config CSRC_SB1250
587 bool "Cortex-A57/A72: 1742098: ELR rec !! 1107 bool
588 depends on COMPAT <<
589 default y <<
590 help <<
591 This option removes the AES hwcap fo <<
592 workaround erratum 1742098 on Cortex <<
593 <<
594 Affected parts may corrupt the AES s <<
595 taken between a pair of AES instruct <<
596 are only present if the cryptography <<
597 All software should have a fallback <<
598 that don't implement the cryptograph <<
599 1108
600 If unsure, say Y. !! 1109 config MIPS_CLOCK_VSYSCALL
>> 1110 def_bool CSRC_R4K || CLKSRC_MIPS_GIC
601 1111
602 config ARM64_ERRATUM_845719 !! 1112 config GPIO_TXX9
603 bool "Cortex-A53: 845719: a load might !! 1113 select GPIOLIB
604 depends on COMPAT !! 1114 bool
605 default y <<
606 help <<
607 This option adds an alternative code <<
608 erratum 845719 on Cortex-A53 parts u <<
609 <<
610 When running a compat (AArch32) user <<
611 part, a load at EL0 from a virtual a <<
612 bits of the virtual address used by <<
613 might return incorrect data. <<
614 <<
615 The workaround is to write the conte <<
616 return to a 32-bit task. <<
617 Please note that this does not neces <<
618 as it depends on the alternative fra <<
619 the kernel if an affected CPU is det <<
620 1115
621 If unsure, say Y. !! 1116 config FW_CFE
>> 1117 bool
622 1118
623 config ARM64_ERRATUM_843419 !! 1119 config ARCH_DMA_ADDR_T_64BIT
624 bool "Cortex-A53: 843419: A load or st !! 1120 def_bool (HIGHMEM && ARCH_PHYS_ADDR_T_64BIT) || 64BIT
625 default y <<
626 help <<
627 This option links the kernel with '- <<
628 enables PLT support to replace certa <<
629 cause subsequent memory accesses to <<
630 Cortex-A53 parts up to r0p4. <<
631 1121
632 If unsure, say Y. !! 1122 config ARCH_SUPPORTS_UPROBES
>> 1123 bool
633 1124
634 config ARM64_LD_HAS_FIX_ERRATUM_843419 !! 1125 config DMA_MAYBE_COHERENT
635 def_bool $(ld-option,--fix-cortex-a53- !! 1126 select DMA_NONCOHERENT
>> 1127 bool
636 1128
637 config ARM64_ERRATUM_1024718 !! 1129 config DMA_PERDEV_COHERENT
638 bool "Cortex-A55: 1024718: Update of D !! 1130 bool
639 default y !! 1131 select DMA_MAYBE_COHERENT
640 help <<
641 This option adds a workaround for AR <<
642 1132
643 Affected Cortex-A55 cores (all revis !! 1133 config DMA_COHERENT
644 update of the hardware dirty bit whe !! 1134 bool
645 without a break-before-make. The wor <<
646 of hardware DBM locally on the affec <<
647 this erratum will continue to use th <<
648 1135
649 If unsure, say Y. !! 1136 config DMA_NONCOHERENT
>> 1137 bool
>> 1138 select NEED_DMA_MAP_STATE
650 1139
651 config ARM64_ERRATUM_1418040 !! 1140 config NEED_DMA_MAP_STATE
652 bool "Cortex-A76/Neoverse-N1: MRC read !! 1141 bool
653 default y <<
654 depends on COMPAT <<
655 help <<
656 This option adds a workaround for AR <<
657 errata 1188873 and 1418040. <<
658 1142
659 Affected Cortex-A76/Neoverse-N1 core !! 1143 config SYS_HAS_EARLY_PRINTK
660 cause register corruption when acces !! 1144 bool
661 from AArch32 userspace. <<
662 1145
663 If unsure, say Y. !! 1146 config SYS_SUPPORTS_HOTPLUG_CPU
>> 1147 bool
664 1148
665 config ARM64_WORKAROUND_SPECULATIVE_AT !! 1149 config MIPS_BONITO64
666 bool 1150 bool
667 1151
668 config ARM64_ERRATUM_1165522 !! 1152 config MIPS_MSC
669 bool "Cortex-A76: 1165522: Speculative !! 1153 bool
670 default y <<
671 select ARM64_WORKAROUND_SPECULATIVE_AT <<
672 help <<
673 This option adds a workaround for AR <<
674 1154
675 Affected Cortex-A76 cores (r0p0, r1p !! 1155 config MIPS_NILE4
676 corrupted TLBs by speculating an AT !! 1156 bool
677 context switch. <<
678 1157
679 If unsure, say Y. !! 1158 config SYNC_R4K
>> 1159 bool
680 1160
681 config ARM64_ERRATUM_1319367 !! 1161 config MIPS_MACHINE
682 bool "Cortex-A57/A72: 1319537: Specula !! 1162 def_bool n
683 default y <<
684 select ARM64_WORKAROUND_SPECULATIVE_AT <<
685 help <<
686 This option adds work arounds for AR <<
687 and A72 erratum 1319367 <<
688 1163
689 Cortex-A57 and A72 cores could end-u !! 1164 config NO_IOPORT_MAP
690 speculating an AT instruction during !! 1165 def_bool n
691 1166
692 If unsure, say Y. !! 1167 config GENERIC_CSUM
>> 1168 bool
693 1169
694 config ARM64_ERRATUM_1530923 !! 1170 config GENERIC_ISA_DMA
695 bool "Cortex-A55: 1530923: Speculative !! 1171 bool
696 default y !! 1172 select ZONE_DMA if GENERIC_ISA_DMA_SUPPORT_BROKEN=n
697 select ARM64_WORKAROUND_SPECULATIVE_AT !! 1173 select ISA_DMA_API
698 help <<
699 This option adds a workaround for AR <<
700 1174
701 Affected Cortex-A55 cores (r0p0, r0p !! 1175 config GENERIC_ISA_DMA_SUPPORT_BROKEN
702 corrupted TLBs by speculating an AT !! 1176 bool
703 context switch. !! 1177 select GENERIC_ISA_DMA
704 1178
705 If unsure, say Y. !! 1179 config ISA_DMA_API
>> 1180 bool
706 1181
707 config ARM64_WORKAROUND_REPEAT_TLBI !! 1182 config HOLES_IN_ZONE
708 bool 1183 bool
709 1184
710 config ARM64_ERRATUM_2441007 !! 1185 config SYS_SUPPORTS_RELOCATABLE
711 bool "Cortex-A55: Completion of affect !! 1186 bool
712 select ARM64_WORKAROUND_REPEAT_TLBI <<
713 help 1187 help
714 This option adds a workaround for AR !! 1188 Selected if the platform supports relocating the kernel.
715 !! 1189 The platform must provide plat_get_fdt() if it selects CONFIG_USE_OF
716 Under very rare circumstances, affec !! 1190 to allow access to command line and entropy sources.
717 may not handle a race between a brea <<
718 CPU, and another CPU accessing the s <<
719 store to a page that has been unmapp <<
720 1191
721 Work around this by adding the affec !! 1192 config MIPS_CBPF_JIT
722 TLB sequences to be done twice. !! 1193 def_bool y
723 !! 1194 depends on BPF_JIT && HAVE_CBPF_JIT
724 If unsure, say N. <<
725 1195
726 config ARM64_ERRATUM_1286807 !! 1196 config MIPS_EBPF_JIT
727 bool "Cortex-A76: Modification of the !! 1197 def_bool y
728 select ARM64_WORKAROUND_REPEAT_TLBI !! 1198 depends on BPF_JIT && HAVE_EBPF_JIT
729 help <<
730 This option adds a workaround for AR <<
731 <<
732 On the affected Cortex-A76 cores (r0 <<
733 address for a cacheable mapping of a <<
734 accessed by a core while another cor <<
735 address to a new physical page using <<
736 break-before-make sequence, then und <<
737 TLBI+DSB completes before a read usi <<
738 invalidated has been observed by oth <<
739 workaround repeats the TLBI+DSB oper <<
740 1199
741 If unsure, say N. <<
742 1200
743 config ARM64_ERRATUM_1463225 !! 1201 #
744 bool "Cortex-A76: Software Step might !! 1202 # Endianness selection. Sufficiently obscure so many users don't know what to
745 default y !! 1203 # answer,so we try hard to limit the available choices. Also the use of a
>> 1204 # choice statement should be more obvious to the user.
>> 1205 #
>> 1206 choice
>> 1207 prompt "Endianness selection"
746 help 1208 help
747 This option adds a workaround for Ar !! 1209 Some MIPS machines can be configured for either little or big endian
>> 1210 byte order. These modes require different kernels and a different
>> 1211 Linux distribution. In general there is one preferred byteorder for a
>> 1212 particular system but some systems are just as commonly used in the
>> 1213 one or the other endianness.
748 1214
749 On the affected Cortex-A76 cores (r0 !! 1215 config CPU_BIG_ENDIAN
750 of a system call instruction (SVC) c !! 1216 bool "Big endian"
751 subsequent interrupts when software !! 1217 depends on SYS_SUPPORTS_BIG_ENDIAN
752 exception handler of the system call <<
753 is enabled or VHE is in use. <<
754 1218
755 Work around the erratum by triggerin !! 1219 config CPU_LITTLE_ENDIAN
756 when handling a system call from a t !! 1220 bool "Little endian"
757 in a VHE configuration of the kernel !! 1221 depends on SYS_SUPPORTS_LITTLE_ENDIAN
758 1222
759 If unsure, say Y. !! 1223 endchoice
760 1224
761 config ARM64_ERRATUM_1542419 !! 1225 config EXPORT_UASM
762 bool "Neoverse-N1: workaround mis-orde !! 1226 bool
763 help <<
764 This option adds a workaround for AR <<
765 1542419. <<
766 1227
767 Affected Neoverse-N1 cores could exe !! 1228 config SYS_SUPPORTS_APM_EMULATION
768 modified by another CPU. The workaro !! 1229 bool
769 counterpart. <<
770 1230
771 Workaround the issue by hiding the D !! 1231 config SYS_SUPPORTS_BIG_ENDIAN
772 forces user-space to perform cache m !! 1232 bool
773 1233
774 If unsure, say N. !! 1234 config SYS_SUPPORTS_LITTLE_ENDIAN
>> 1235 bool
775 1236
776 config ARM64_ERRATUM_1508412 !! 1237 config SYS_SUPPORTS_HUGETLBFS
777 bool "Cortex-A77: 1508412: workaround !! 1238 bool
>> 1239 depends on CPU_SUPPORTS_HUGEPAGES && 64BIT
778 default y 1240 default y
779 help <<
780 This option adds a workaround for Ar <<
781 1241
782 Affected Cortex-A77 cores (r0p0, r1p !! 1242 config MIPS_HUGE_TLB_SUPPORT
783 of a store-exclusive or read of PAR_ !! 1243 def_bool HUGETLB_PAGE || TRANSPARENT_HUGEPAGE
784 non-cacheable memory attributes. The <<
785 counterpart. <<
786 1244
787 KVM guests must also have the workar !! 1245 config IRQ_CPU_RM7K
788 deadlock the system. !! 1246 bool
789 1247
790 Work around the issue by inserting D !! 1248 config IRQ_MSP_SLP
791 register reads and warning KVM users !! 1249 bool
792 to prevent a speculative PAR_EL1 rea <<
793 1250
794 If unsure, say Y. !! 1251 config IRQ_MSP_CIC
>> 1252 bool
795 1253
796 config ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MO !! 1254 config IRQ_TXX9
797 bool 1255 bool
798 1256
799 config ARM64_ERRATUM_2051678 !! 1257 config IRQ_GT641XX
800 bool "Cortex-A510: 2051678: disable Ha !! 1258 bool
801 default y <<
802 help <<
803 This options adds the workaround for <<
804 Affected Cortex-A510 might not respe <<
805 hardware update of the page table's <<
806 is to not enable the feature on affe <<
807 1259
808 If unsure, say Y. !! 1260 config PCI_GT64XXX_PCI0
>> 1261 bool
809 1262
810 config ARM64_ERRATUM_2077057 !! 1263 config NO_EXCEPT_FILL
811 bool "Cortex-A510: 2077057: workaround !! 1264 bool
812 default y <<
813 help <<
814 This option adds the workaround for <<
815 Affected Cortex-A510 may corrupt SPS <<
816 expected, but a Pointer Authenticati <<
817 erratum causes SPSR_EL1 to be copied <<
818 EL1 to cause a return to EL2 with a <<
819 1265
820 This can only happen when EL2 is ste !! 1266 config SOC_EMMA2RH
>> 1267 bool
>> 1268 select CEVT_R4K
>> 1269 select CSRC_R4K
>> 1270 select DMA_NONCOHERENT
>> 1271 select IRQ_MIPS_CPU
>> 1272 select SWAP_IO_SPACE
>> 1273 select SYS_HAS_CPU_R5500
>> 1274 select SYS_SUPPORTS_32BIT_KERNEL
>> 1275 select SYS_SUPPORTS_64BIT_KERNEL
>> 1276 select SYS_SUPPORTS_BIG_ENDIAN
821 1277
822 When these conditions occur, the SPS !! 1278 config SOC_PNX833X
823 previous guest entry, and can be res !! 1279 bool
>> 1280 select CEVT_R4K
>> 1281 select CSRC_R4K
>> 1282 select IRQ_MIPS_CPU
>> 1283 select DMA_NONCOHERENT
>> 1284 select SYS_HAS_CPU_MIPS32_R2
>> 1285 select SYS_SUPPORTS_32BIT_KERNEL
>> 1286 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 1287 select SYS_SUPPORTS_BIG_ENDIAN
>> 1288 select SYS_SUPPORTS_MIPS16
>> 1289 select CPU_MIPSR2_IRQ_VI
824 1290
825 If unsure, say Y. !! 1291 config SOC_PNX8335
>> 1292 bool
>> 1293 select SOC_PNX833X
826 1294
827 config ARM64_ERRATUM_2658417 !! 1295 config MIPS_SPRAM
828 bool "Cortex-A510: 2658417: remove BF1 !! 1296 bool
829 default y <<
830 help <<
831 This option adds the workaround for <<
832 Affected Cortex-A510 (r0p0 to r1p1) <<
833 BFMMLA or VMMLA instructions in rare <<
834 A510 CPUs are using shared neon hard <<
835 discoverable by the kernel, hide the <<
836 user-space should not be using these <<
837 1297
838 If unsure, say Y. !! 1298 config SWAP_IO_SPACE
>> 1299 bool
839 1300
840 config ARM64_ERRATUM_2119858 !! 1301 config SGI_HAS_INDYDOG
841 bool "Cortex-A710/X2: 2119858: workaro !! 1302 bool
842 default y <<
843 depends on CORESIGHT_TRBE <<
844 select ARM64_WORKAROUND_TRBE_OVERWRITE <<
845 help <<
846 This option adds the workaround for <<
847 1303
848 Affected Cortex-A710/X2 cores could !! 1304 config SGI_HAS_HAL2
849 data at the base of the buffer (poin !! 1305 bool
850 the event of a WRAP event. <<
851 1306
852 Work around the issue by always maki !! 1307 config SGI_HAS_SEEQ
853 256 bytes before enabling the buffer !! 1308 bool
854 the buffer with ETM ignore packets u <<
855 1309
856 If unsure, say Y. !! 1310 config SGI_HAS_WD93
>> 1311 bool
857 1312
858 config ARM64_ERRATUM_2139208 !! 1313 config SGI_HAS_ZILOG
859 bool "Neoverse-N2: 2139208: workaround !! 1314 bool
860 default y <<
861 depends on CORESIGHT_TRBE <<
862 select ARM64_WORKAROUND_TRBE_OVERWRITE <<
863 help <<
864 This option adds the workaround for <<
865 1315
866 Affected Neoverse-N2 cores could ove !! 1316 config SGI_HAS_I8042
867 data at the base of the buffer (poin !! 1317 bool
868 the event of a WRAP event. <<
869 1318
870 Work around the issue by always maki !! 1319 config DEFAULT_SGI_PARTITION
871 256 bytes before enabling the buffer !! 1320 bool
872 the buffer with ETM ignore packets u <<
873 1321
874 If unsure, say Y. !! 1322 config FW_ARC32
>> 1323 bool
875 1324
876 config ARM64_WORKAROUND_TSB_FLUSH_FAILURE !! 1325 config FW_SNIPROM
877 bool 1326 bool
878 1327
879 config ARM64_ERRATUM_2054223 !! 1328 config BOOT_ELF32
880 bool "Cortex-A710: 2054223: workaround !! 1329 bool
881 default y <<
882 select ARM64_WORKAROUND_TSB_FLUSH_FAIL <<
883 help <<
884 Enable workaround for ARM Cortex-A71 <<
885 1330
886 Affected cores may fail to flush the !! 1331 config MIPS_L1_CACHE_SHIFT_4
887 the PE is in trace prohibited state. !! 1332 bool
888 of the trace cached. <<
889 1333
890 Workaround is to issue two TSB conse !! 1334 config MIPS_L1_CACHE_SHIFT_5
>> 1335 bool
891 1336
892 If unsure, say Y. !! 1337 config MIPS_L1_CACHE_SHIFT_6
>> 1338 bool
893 1339
894 config ARM64_ERRATUM_2067961 !! 1340 config MIPS_L1_CACHE_SHIFT_7
895 bool "Neoverse-N2: 2067961: workaround !! 1341 bool
896 default y <<
897 select ARM64_WORKAROUND_TSB_FLUSH_FAIL <<
898 help <<
899 Enable workaround for ARM Neoverse-N <<
900 1342
901 Affected cores may fail to flush the !! 1343 config MIPS_L1_CACHE_SHIFT
902 the PE is in trace prohibited state. !! 1344 int
903 of the trace cached. !! 1345 default "7" if MIPS_L1_CACHE_SHIFT_7
>> 1346 default "6" if MIPS_L1_CACHE_SHIFT_6
>> 1347 default "5" if MIPS_L1_CACHE_SHIFT_5
>> 1348 default "4" if MIPS_L1_CACHE_SHIFT_4
>> 1349 default "5"
904 1350
905 Workaround is to issue two TSB conse !! 1351 config HAVE_STD_PC_SERIAL_PORT
>> 1352 bool
906 1353
907 If unsure, say Y. !! 1354 config ARC_CONSOLE
>> 1355 bool "ARC console support"
>> 1356 depends on SGI_IP22 || SGI_IP28 || (SNI_RM && CPU_LITTLE_ENDIAN)
908 1357
909 config ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANG !! 1358 config ARC_MEMORY
910 bool 1359 bool
911 !! 1360 depends on MACH_JAZZ || SNI_RM || SGI_IP32
912 config ARM64_ERRATUM_2253138 <<
913 bool "Neoverse-N2: 2253138: workaround <<
914 depends on CORESIGHT_TRBE <<
915 default y 1361 default y
916 select ARM64_WORKAROUND_TRBE_WRITE_OUT <<
917 help <<
918 This option adds the workaround for <<
919 1362
920 Affected Neoverse-N2 cores might wri !! 1363 config ARC_PROMLIB
921 for TRBE. Under some conditions, the !! 1364 bool
922 virtually addressed page following t !! 1365 depends on MACH_JAZZ || SNI_RM || SGI_IP22 || SGI_IP28 || SGI_IP32
923 (i.e., the TRBLIMITR_EL1.LIMIT), ins <<
924 <<
925 Work around this in the driver by al <<
926 page beyond the TRBLIMITR_EL1.LIMIT, <<
927 <<
928 If unsure, say Y. <<
929 <<
930 config ARM64_ERRATUM_2224489 <<
931 bool "Cortex-A710/X2: 2224489: workaro <<
932 depends on CORESIGHT_TRBE <<
933 default y 1366 default y
934 select ARM64_WORKAROUND_TRBE_WRITE_OUT <<
935 help <<
936 This option adds the workaround for <<
937 1367
938 Affected Cortex-A710/X2 cores might !! 1368 config FW_ARC64
939 for TRBE. Under some conditions, the !! 1369 bool
940 virtually addressed page following t <<
941 (i.e., the TRBLIMITR_EL1.LIMIT), ins <<
942 <<
943 Work around this in the driver by al <<
944 page beyond the TRBLIMITR_EL1.LIMIT, <<
945 <<
946 If unsure, say Y. <<
947 1370
948 config ARM64_ERRATUM_2441009 !! 1371 config BOOT_ELF64
949 bool "Cortex-A510: Completion of affec !! 1372 bool
950 select ARM64_WORKAROUND_REPEAT_TLBI <<
951 help <<
952 This option adds a workaround for AR <<
953 <<
954 Under very rare circumstances, affec <<
955 may not handle a race between a brea <<
956 CPU, and another CPU accessing the s <<
957 store to a page that has been unmapp <<
958 1373
959 Work around this by adding the affec !! 1374 menu "CPU selection"
960 TLB sequences to be done twice. <<
961 1375
962 If unsure, say N. !! 1376 choice
>> 1377 prompt "CPU type"
>> 1378 default CPU_R4X00
963 1379
964 config ARM64_ERRATUM_2064142 !! 1380 config CPU_LOONGSON3
965 bool "Cortex-A510: 2064142: workaround !! 1381 bool "Loongson 3 CPU"
966 depends on CORESIGHT_TRBE !! 1382 depends on SYS_HAS_CPU_LOONGSON3
967 default y !! 1383 select CPU_SUPPORTS_64BIT_KERNEL
>> 1384 select CPU_SUPPORTS_HIGHMEM
>> 1385 select CPU_SUPPORTS_HUGEPAGES
>> 1386 select WEAK_ORDERING
>> 1387 select WEAK_REORDERING_BEYOND_LLSC
>> 1388 select MIPS_PGD_C0_CONTEXT
>> 1389 select MIPS_L1_CACHE_SHIFT_6
>> 1390 select MIPS_FP_SUPPORT
>> 1391 select GPIOLIB
968 help 1392 help
969 This option adds the workaround for !! 1393 The Loongson 3 processor implements the MIPS64R2 instruction
>> 1394 set with many extensions.
970 1395
971 Affected Cortex-A510 core might fail !! 1396 config LOONGSON3_ENHANCEMENT
972 TRBE has been disabled. Under some c !! 1397 bool "New Loongson 3 CPU Enhancements"
973 writes into TRBE registers TRBLIMITR !! 1398 default n
974 and TRBTRG_EL1 will be ignored and w !! 1399 select CPU_MIPSR2
975 !! 1400 select CPU_HAS_PREFETCH
976 Work around this in the driver by ex !! 1401 depends on CPU_LOONGSON3
977 is stopped and before performing a s !! 1402 help
978 registers. !! 1403 New Loongson 3 CPU (since Loongson-3A R2, as opposed to Loongson-3A
>> 1404 R1, Loongson-3B R1 and Loongson-3B R2) has many enhancements, such as
>> 1405 FTLB, L1-VCache, EI/DI/Wait/Prefetch instruction, DSP/DSPv2 ASE, User
>> 1406 Local register, Read-Inhibit/Execute-Inhibit, SFB (Store Fill Buffer),
>> 1407 Fast TLB refill support, etc.
>> 1408
>> 1409 This option enable those enhancements which are not probed at run
>> 1410 time. If you want a generic kernel to run on all Loongson 3 machines,
>> 1411 please say 'N' here. If you want a high-performance kernel to run on
>> 1412 new Loongson 3 machines only, please say 'Y' here.
>> 1413
>> 1414 config CPU_LOONGSON2E
>> 1415 bool "Loongson 2E"
>> 1416 depends on SYS_HAS_CPU_LOONGSON2E
>> 1417 select CPU_LOONGSON2
>> 1418 help
>> 1419 The Loongson 2E processor implements the MIPS III instruction set
>> 1420 with many extensions.
>> 1421
>> 1422 It has an internal FPGA northbridge, which is compatible to
>> 1423 bonito64.
>> 1424
>> 1425 config CPU_LOONGSON2F
>> 1426 bool "Loongson 2F"
>> 1427 depends on SYS_HAS_CPU_LOONGSON2F
>> 1428 select CPU_LOONGSON2
>> 1429 select GPIOLIB
>> 1430 help
>> 1431 The Loongson 2F processor implements the MIPS III instruction set
>> 1432 with many extensions.
>> 1433
>> 1434 Loongson2F have built-in DDR2 and PCIX controller. The PCIX controller
>> 1435 have a similar programming interface with FPGA northbridge used in
>> 1436 Loongson2E.
>> 1437
>> 1438 config CPU_LOONGSON1B
>> 1439 bool "Loongson 1B"
>> 1440 depends on SYS_HAS_CPU_LOONGSON1B
>> 1441 select CPU_LOONGSON1
>> 1442 select LEDS_GPIO_REGISTER
>> 1443 help
>> 1444 The Loongson 1B is a 32-bit SoC, which implements the MIPS32
>> 1445 release 2 instruction set.
>> 1446
>> 1447 config CPU_LOONGSON1C
>> 1448 bool "Loongson 1C"
>> 1449 depends on SYS_HAS_CPU_LOONGSON1C
>> 1450 select CPU_LOONGSON1
>> 1451 select LEDS_GPIO_REGISTER
>> 1452 help
>> 1453 The Loongson 1C is a 32-bit SoC, which implements the MIPS32
>> 1454 release 2 instruction set.
>> 1455
>> 1456 config CPU_MIPS32_R1
>> 1457 bool "MIPS32 Release 1"
>> 1458 depends on SYS_HAS_CPU_MIPS32_R1
>> 1459 select CPU_HAS_PREFETCH
>> 1460 select CPU_SUPPORTS_32BIT_KERNEL
>> 1461 select CPU_SUPPORTS_HIGHMEM
>> 1462 help
>> 1463 Choose this option to build a kernel for release 1 or later of the
>> 1464 MIPS32 architecture. Most modern embedded systems with a 32-bit
>> 1465 MIPS processor are based on a MIPS32 processor. If you know the
>> 1466 specific type of processor in your system, choose those that one
>> 1467 otherwise CPU_MIPS32_R1 is a safe bet for any MIPS32 system.
>> 1468 Release 2 of the MIPS32 architecture is available since several
>> 1469 years so chances are you even have a MIPS32 Release 2 processor
>> 1470 in which case you should choose CPU_MIPS32_R2 instead for better
>> 1471 performance.
>> 1472
>> 1473 config CPU_MIPS32_R2
>> 1474 bool "MIPS32 Release 2"
>> 1475 depends on SYS_HAS_CPU_MIPS32_R2
>> 1476 select CPU_HAS_PREFETCH
>> 1477 select CPU_SUPPORTS_32BIT_KERNEL
>> 1478 select CPU_SUPPORTS_HIGHMEM
>> 1479 select CPU_SUPPORTS_MSA
>> 1480 select HAVE_KVM
>> 1481 help
>> 1482 Choose this option to build a kernel for release 2 or later of the
>> 1483 MIPS32 architecture. Most modern embedded systems with a 32-bit
>> 1484 MIPS processor are based on a MIPS32 processor. If you know the
>> 1485 specific type of processor in your system, choose those that one
>> 1486 otherwise CPU_MIPS32_R1 is a safe bet for any MIPS32 system.
>> 1487
>> 1488 config CPU_MIPS32_R6
>> 1489 bool "MIPS32 Release 6"
>> 1490 depends on SYS_HAS_CPU_MIPS32_R6
>> 1491 select CPU_HAS_PREFETCH
>> 1492 select CPU_SUPPORTS_32BIT_KERNEL
>> 1493 select CPU_SUPPORTS_HIGHMEM
>> 1494 select CPU_SUPPORTS_MSA
>> 1495 select GENERIC_CSUM
>> 1496 select HAVE_KVM
>> 1497 select MIPS_O32_FP64_SUPPORT
>> 1498 help
>> 1499 Choose this option to build a kernel for release 6 or later of the
>> 1500 MIPS32 architecture. New MIPS processors, starting with the Warrior
>> 1501 family, are based on a MIPS32r6 processor. If you own an older
>> 1502 processor, you probably need to select MIPS32r1 or MIPS32r2 instead.
>> 1503
>> 1504 config CPU_MIPS64_R1
>> 1505 bool "MIPS64 Release 1"
>> 1506 depends on SYS_HAS_CPU_MIPS64_R1
>> 1507 select CPU_HAS_PREFETCH
>> 1508 select CPU_SUPPORTS_32BIT_KERNEL
>> 1509 select CPU_SUPPORTS_64BIT_KERNEL
>> 1510 select CPU_SUPPORTS_HIGHMEM
>> 1511 select CPU_SUPPORTS_HUGEPAGES
>> 1512 help
>> 1513 Choose this option to build a kernel for release 1 or later of the
>> 1514 MIPS64 architecture. Many modern embedded systems with a 64-bit
>> 1515 MIPS processor are based on a MIPS64 processor. If you know the
>> 1516 specific type of processor in your system, choose those that one
>> 1517 otherwise CPU_MIPS64_R1 is a safe bet for any MIPS64 system.
>> 1518 Release 2 of the MIPS64 architecture is available since several
>> 1519 years so chances are you even have a MIPS64 Release 2 processor
>> 1520 in which case you should choose CPU_MIPS64_R2 instead for better
>> 1521 performance.
>> 1522
>> 1523 config CPU_MIPS64_R2
>> 1524 bool "MIPS64 Release 2"
>> 1525 depends on SYS_HAS_CPU_MIPS64_R2
>> 1526 select CPU_HAS_PREFETCH
>> 1527 select CPU_SUPPORTS_32BIT_KERNEL
>> 1528 select CPU_SUPPORTS_64BIT_KERNEL
>> 1529 select CPU_SUPPORTS_HIGHMEM
>> 1530 select CPU_SUPPORTS_HUGEPAGES
>> 1531 select CPU_SUPPORTS_MSA
>> 1532 select HAVE_KVM
>> 1533 help
>> 1534 Choose this option to build a kernel for release 2 or later of the
>> 1535 MIPS64 architecture. Many modern embedded systems with a 64-bit
>> 1536 MIPS processor are based on a MIPS64 processor. If you know the
>> 1537 specific type of processor in your system, choose those that one
>> 1538 otherwise CPU_MIPS64_R1 is a safe bet for any MIPS64 system.
>> 1539
>> 1540 config CPU_MIPS64_R6
>> 1541 bool "MIPS64 Release 6"
>> 1542 depends on SYS_HAS_CPU_MIPS64_R6
>> 1543 select CPU_HAS_PREFETCH
>> 1544 select CPU_SUPPORTS_32BIT_KERNEL
>> 1545 select CPU_SUPPORTS_64BIT_KERNEL
>> 1546 select CPU_SUPPORTS_HIGHMEM
>> 1547 select CPU_SUPPORTS_MSA
>> 1548 select GENERIC_CSUM
>> 1549 select MIPS_O32_FP64_SUPPORT if 32BIT || MIPS32_O32
>> 1550 select HAVE_KVM
>> 1551 help
>> 1552 Choose this option to build a kernel for release 6 or later of the
>> 1553 MIPS64 architecture. New MIPS processors, starting with the Warrior
>> 1554 family, are based on a MIPS64r6 processor. If you own an older
>> 1555 processor, you probably need to select MIPS64r1 or MIPS64r2 instead.
>> 1556
>> 1557 config CPU_R3000
>> 1558 bool "R3000"
>> 1559 depends on SYS_HAS_CPU_R3000
>> 1560 select CPU_HAS_WB
>> 1561 select CPU_SUPPORTS_32BIT_KERNEL
>> 1562 select CPU_SUPPORTS_HIGHMEM
>> 1563 help
>> 1564 Please make sure to pick the right CPU type. Linux/MIPS is not
>> 1565 designed to be generic, i.e. Kernels compiled for R3000 CPUs will
>> 1566 *not* work on R4000 machines and vice versa. However, since most
>> 1567 of the supported machines have an R4000 (or similar) CPU, R4x00
>> 1568 might be a safe bet. If the resulting kernel does not work,
>> 1569 try to recompile with R3000.
>> 1570
>> 1571 config CPU_TX39XX
>> 1572 bool "R39XX"
>> 1573 depends on SYS_HAS_CPU_TX39XX
>> 1574 select CPU_SUPPORTS_32BIT_KERNEL
>> 1575
>> 1576 config CPU_VR41XX
>> 1577 bool "R41xx"
>> 1578 depends on SYS_HAS_CPU_VR41XX
>> 1579 select CPU_SUPPORTS_32BIT_KERNEL
>> 1580 select CPU_SUPPORTS_64BIT_KERNEL
>> 1581 help
>> 1582 The options selects support for the NEC VR4100 series of processors.
>> 1583 Only choose this option if you have one of these processors as a
>> 1584 kernel built with this option will not run on any other type of
>> 1585 processor or vice versa.
>> 1586
>> 1587 config CPU_R4300
>> 1588 bool "R4300"
>> 1589 depends on SYS_HAS_CPU_R4300
>> 1590 select CPU_SUPPORTS_32BIT_KERNEL
>> 1591 select CPU_SUPPORTS_64BIT_KERNEL
>> 1592 help
>> 1593 MIPS Technologies R4300-series processors.
>> 1594
>> 1595 config CPU_R4X00
>> 1596 bool "R4x00"
>> 1597 depends on SYS_HAS_CPU_R4X00
>> 1598 select CPU_SUPPORTS_32BIT_KERNEL
>> 1599 select CPU_SUPPORTS_64BIT_KERNEL
>> 1600 select CPU_SUPPORTS_HUGEPAGES
>> 1601 help
>> 1602 MIPS Technologies R4000-series processors other than 4300, including
>> 1603 the R4000, R4400, R4600, and 4700.
>> 1604
>> 1605 config CPU_TX49XX
>> 1606 bool "R49XX"
>> 1607 depends on SYS_HAS_CPU_TX49XX
>> 1608 select CPU_HAS_PREFETCH
>> 1609 select CPU_SUPPORTS_32BIT_KERNEL
>> 1610 select CPU_SUPPORTS_64BIT_KERNEL
>> 1611 select CPU_SUPPORTS_HUGEPAGES
>> 1612
>> 1613 config CPU_R5000
>> 1614 bool "R5000"
>> 1615 depends on SYS_HAS_CPU_R5000
>> 1616 select CPU_SUPPORTS_32BIT_KERNEL
>> 1617 select CPU_SUPPORTS_64BIT_KERNEL
>> 1618 select CPU_SUPPORTS_HUGEPAGES
>> 1619 help
>> 1620 MIPS Technologies R5000-series processors other than the Nevada.
>> 1621
>> 1622 config CPU_R5432
>> 1623 bool "R5432"
>> 1624 depends on SYS_HAS_CPU_R5432
>> 1625 select CPU_SUPPORTS_32BIT_KERNEL
>> 1626 select CPU_SUPPORTS_64BIT_KERNEL
>> 1627 select CPU_SUPPORTS_HUGEPAGES
>> 1628
>> 1629 config CPU_R5500
>> 1630 bool "R5500"
>> 1631 depends on SYS_HAS_CPU_R5500
>> 1632 select CPU_SUPPORTS_32BIT_KERNEL
>> 1633 select CPU_SUPPORTS_64BIT_KERNEL
>> 1634 select CPU_SUPPORTS_HUGEPAGES
>> 1635 help
>> 1636 NEC VR5500 and VR5500A series processors implement 64-bit MIPS IV
>> 1637 instruction set.
>> 1638
>> 1639 config CPU_NEVADA
>> 1640 bool "RM52xx"
>> 1641 depends on SYS_HAS_CPU_NEVADA
>> 1642 select CPU_SUPPORTS_32BIT_KERNEL
>> 1643 select CPU_SUPPORTS_64BIT_KERNEL
>> 1644 select CPU_SUPPORTS_HUGEPAGES
>> 1645 help
>> 1646 QED / PMC-Sierra RM52xx-series ("Nevada") processors.
>> 1647
>> 1648 config CPU_R8000
>> 1649 bool "R8000"
>> 1650 depends on SYS_HAS_CPU_R8000
>> 1651 select CPU_HAS_PREFETCH
>> 1652 select CPU_SUPPORTS_64BIT_KERNEL
>> 1653 help
>> 1654 MIPS Technologies R8000 processors. Note these processors are
>> 1655 uncommon and the support for them is incomplete.
>> 1656
>> 1657 config CPU_R10000
>> 1658 bool "R10000"
>> 1659 depends on SYS_HAS_CPU_R10000
>> 1660 select CPU_HAS_PREFETCH
>> 1661 select CPU_SUPPORTS_32BIT_KERNEL
>> 1662 select CPU_SUPPORTS_64BIT_KERNEL
>> 1663 select CPU_SUPPORTS_HIGHMEM
>> 1664 select CPU_SUPPORTS_HUGEPAGES
>> 1665 help
>> 1666 MIPS Technologies R10000-series processors.
>> 1667
>> 1668 config CPU_RM7000
>> 1669 bool "RM7000"
>> 1670 depends on SYS_HAS_CPU_RM7000
>> 1671 select CPU_HAS_PREFETCH
>> 1672 select CPU_SUPPORTS_32BIT_KERNEL
>> 1673 select CPU_SUPPORTS_64BIT_KERNEL
>> 1674 select CPU_SUPPORTS_HIGHMEM
>> 1675 select CPU_SUPPORTS_HUGEPAGES
>> 1676
>> 1677 config CPU_SB1
>> 1678 bool "SB1"
>> 1679 depends on SYS_HAS_CPU_SB1
>> 1680 select CPU_SUPPORTS_32BIT_KERNEL
>> 1681 select CPU_SUPPORTS_64BIT_KERNEL
>> 1682 select CPU_SUPPORTS_HIGHMEM
>> 1683 select CPU_SUPPORTS_HUGEPAGES
>> 1684 select WEAK_ORDERING
>> 1685
>> 1686 config CPU_CAVIUM_OCTEON
>> 1687 bool "Cavium Octeon processor"
>> 1688 depends on SYS_HAS_CPU_CAVIUM_OCTEON
>> 1689 select CPU_HAS_PREFETCH
>> 1690 select CPU_SUPPORTS_64BIT_KERNEL
>> 1691 select WEAK_ORDERING
>> 1692 select CPU_SUPPORTS_HIGHMEM
>> 1693 select CPU_SUPPORTS_HUGEPAGES
>> 1694 select USB_EHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 1695 select USB_OHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 1696 select MIPS_L1_CACHE_SHIFT_7
>> 1697 select HAVE_KVM
>> 1698 help
>> 1699 The Cavium Octeon processor is a highly integrated chip containing
>> 1700 many ethernet hardware widgets for networking tasks. The processor
>> 1701 can have up to 16 Mips64v2 cores and 8 integrated gigabit ethernets.
>> 1702 Full details can be found at http://www.caviumnetworks.com.
>> 1703
>> 1704 config CPU_BMIPS
>> 1705 bool "Broadcom BMIPS"
>> 1706 depends on SYS_HAS_CPU_BMIPS
>> 1707 select CPU_MIPS32
>> 1708 select CPU_BMIPS32_3300 if SYS_HAS_CPU_BMIPS32_3300
>> 1709 select CPU_BMIPS4350 if SYS_HAS_CPU_BMIPS4350
>> 1710 select CPU_BMIPS4380 if SYS_HAS_CPU_BMIPS4380
>> 1711 select CPU_BMIPS5000 if SYS_HAS_CPU_BMIPS5000
>> 1712 select CPU_SUPPORTS_32BIT_KERNEL
>> 1713 select DMA_NONCOHERENT
>> 1714 select IRQ_MIPS_CPU
>> 1715 select SWAP_IO_SPACE
>> 1716 select WEAK_ORDERING
>> 1717 select CPU_SUPPORTS_HIGHMEM
>> 1718 select CPU_HAS_PREFETCH
>> 1719 select CPU_SUPPORTS_CPUFREQ
>> 1720 select MIPS_EXTERNAL_TIMER
>> 1721 help
>> 1722 Support for BMIPS32/3300/4350/4380 and BMIPS5000 processors.
>> 1723
>> 1724 config CPU_XLR
>> 1725 bool "Netlogic XLR SoC"
>> 1726 depends on SYS_HAS_CPU_XLR
>> 1727 select CPU_SUPPORTS_32BIT_KERNEL
>> 1728 select CPU_SUPPORTS_64BIT_KERNEL
>> 1729 select CPU_SUPPORTS_HIGHMEM
>> 1730 select CPU_SUPPORTS_HUGEPAGES
>> 1731 select WEAK_ORDERING
>> 1732 select WEAK_REORDERING_BEYOND_LLSC
>> 1733 help
>> 1734 Netlogic Microsystems XLR/XLS processors.
>> 1735
>> 1736 config CPU_XLP
>> 1737 bool "Netlogic XLP SoC"
>> 1738 depends on SYS_HAS_CPU_XLP
>> 1739 select CPU_SUPPORTS_32BIT_KERNEL
>> 1740 select CPU_SUPPORTS_64BIT_KERNEL
>> 1741 select CPU_SUPPORTS_HIGHMEM
>> 1742 select WEAK_ORDERING
>> 1743 select WEAK_REORDERING_BEYOND_LLSC
>> 1744 select CPU_HAS_PREFETCH
>> 1745 select CPU_MIPSR2
>> 1746 select CPU_SUPPORTS_HUGEPAGES
>> 1747 select MIPS_ASID_BITS_VARIABLE
>> 1748 help
>> 1749 Netlogic Microsystems XLP processors.
>> 1750 endchoice
979 1751
980 If unsure, say Y. !! 1752 config CPU_MIPS32_3_5_FEATURES
>> 1753 bool "MIPS32 Release 3.5 Features"
>> 1754 depends on SYS_HAS_CPU_MIPS32_R3_5
>> 1755 depends on CPU_MIPS32_R2 || CPU_MIPS32_R6
>> 1756 help
>> 1757 Choose this option to build a kernel for release 2 or later of the
>> 1758 MIPS32 architecture including features from the 3.5 release such as
>> 1759 support for Enhanced Virtual Addressing (EVA).
>> 1760
>> 1761 config CPU_MIPS32_3_5_EVA
>> 1762 bool "Enhanced Virtual Addressing (EVA)"
>> 1763 depends on CPU_MIPS32_3_5_FEATURES
>> 1764 select EVA
>> 1765 default y
>> 1766 help
>> 1767 Choose this option if you want to enable the Enhanced Virtual
>> 1768 Addressing (EVA) on your MIPS32 core (such as proAptiv).
>> 1769 One of its primary benefits is an increase in the maximum size
>> 1770 of lowmem (up to 3GB). If unsure, say 'N' here.
>> 1771
>> 1772 config CPU_MIPS32_R5_FEATURES
>> 1773 bool "MIPS32 Release 5 Features"
>> 1774 depends on SYS_HAS_CPU_MIPS32_R5
>> 1775 depends on CPU_MIPS32_R2
>> 1776 help
>> 1777 Choose this option to build a kernel for release 2 or later of the
>> 1778 MIPS32 architecture including features from release 5 such as
>> 1779 support for Extended Physical Addressing (XPA).
>> 1780
>> 1781 config CPU_MIPS32_R5_XPA
>> 1782 bool "Extended Physical Addressing (XPA)"
>> 1783 depends on CPU_MIPS32_R5_FEATURES
>> 1784 depends on !EVA
>> 1785 depends on !PAGE_SIZE_4KB
>> 1786 depends on SYS_SUPPORTS_HIGHMEM
>> 1787 select XPA
>> 1788 select HIGHMEM
>> 1789 select ARCH_PHYS_ADDR_T_64BIT
>> 1790 default n
>> 1791 help
>> 1792 Choose this option if you want to enable the Extended Physical
>> 1793 Addressing (XPA) on your MIPS32 core (such as P5600 series). The
>> 1794 benefit is to increase physical addressing equal to or greater
>> 1795 than 40 bits. Note that this has the side effect of turning on
>> 1796 64-bit addressing which in turn makes the PTEs 64-bit in size.
>> 1797 If unsure, say 'N' here.
981 1798
982 config ARM64_ERRATUM_2038923 !! 1799 if CPU_LOONGSON2F
983 bool "Cortex-A510: 2038923: workaround !! 1800 config CPU_NOP_WORKAROUNDS
984 depends on CORESIGHT_TRBE !! 1801 bool
985 default y <<
986 help <<
987 This option adds the workaround for <<
988 <<
989 Affected Cortex-A510 core might caus <<
990 prohibited within the CPU. As a resu <<
991 might be corrupted. This happens aft <<
992 TRBLIMITR_EL1.E, followed by just a <<
993 execution changes from a context, in <<
994 isn't, or vice versa. In these menti <<
995 is prohibited is inconsistent betwee <<
996 the trace buffer state might be corr <<
997 <<
998 Work around this in the driver by pr <<
999 trace is prohibited or not based on <<
1000 change to TRBLIMITR_EL1.E with at l <<
1001 two ISB instructions if no ERET is <<
1002 1802
1003 If unsure, say Y. !! 1803 config CPU_JUMP_WORKAROUNDS
>> 1804 bool
1004 1805
1005 config ARM64_ERRATUM_1902691 !! 1806 config CPU_LOONGSON2F_WORKAROUNDS
1006 bool "Cortex-A510: 1902691: workaroun !! 1807 bool "Loongson 2F Workarounds"
1007 depends on CORESIGHT_TRBE <<
1008 default y 1808 default y
>> 1809 select CPU_NOP_WORKAROUNDS
>> 1810 select CPU_JUMP_WORKAROUNDS
1009 help 1811 help
1010 This option adds the workaround for !! 1812 Loongson 2F01 / 2F02 processors have the NOP & JUMP issues which
>> 1813 require workarounds. Without workarounds the system may hang
>> 1814 unexpectedly. For more information please refer to the gas
>> 1815 -mfix-loongson2f-nop and -mfix-loongson2f-jump options.
>> 1816
>> 1817 Loongson 2F03 and later have fixed these issues and no workarounds
>> 1818 are needed. The workarounds have no significant side effect on them
>> 1819 but may decrease the performance of the system so this option should
>> 1820 be disabled unless the kernel is intended to be run on 2F01 or 2F02
>> 1821 systems.
1011 1822
1012 Affected Cortex-A510 core might cau !! 1823 If unsure, please say Y.
1013 into the memory. Effectively TRBE i !! 1824 endif # CPU_LOONGSON2F
1014 trace data. <<
1015 1825
1016 Work around this problem in the dri !! 1826 config SYS_SUPPORTS_ZBOOT
1017 affected cpus. The firmware must ha !! 1827 bool
1018 on such implementations. This will !! 1828 select HAVE_KERNEL_GZIP
1019 do this already. !! 1829 select HAVE_KERNEL_BZIP2
>> 1830 select HAVE_KERNEL_LZ4
>> 1831 select HAVE_KERNEL_LZMA
>> 1832 select HAVE_KERNEL_LZO
>> 1833 select HAVE_KERNEL_XZ
1020 1834
1021 If unsure, say Y. !! 1835 config SYS_SUPPORTS_ZBOOT_UART16550
>> 1836 bool
>> 1837 select SYS_SUPPORTS_ZBOOT
1022 1838
1023 config ARM64_ERRATUM_2457168 !! 1839 config SYS_SUPPORTS_ZBOOT_UART_PROM
1024 bool "Cortex-A510: 2457168: workaroun !! 1840 bool
1025 depends on ARM64_AMU_EXTN !! 1841 select SYS_SUPPORTS_ZBOOT
1026 default y <<
1027 help <<
1028 This option adds the workaround for <<
1029 1842
1030 The AMU counter AMEVCNTR01 (constan !! 1843 config CPU_LOONGSON2
1031 as the system counter. On affected !! 1844 bool
1032 incorrectly giving a significantly !! 1845 select CPU_SUPPORTS_32BIT_KERNEL
>> 1846 select CPU_SUPPORTS_64BIT_KERNEL
>> 1847 select CPU_SUPPORTS_HIGHMEM
>> 1848 select CPU_SUPPORTS_HUGEPAGES
1033 1849
1034 Work around this problem by returni !! 1850 config CPU_LOONGSON1
1035 key locations that results in disab !! 1851 bool
1036 is the same to firmware disabling a !! 1852 select CPU_MIPS32
>> 1853 select CPU_MIPSR2
>> 1854 select CPU_HAS_PREFETCH
>> 1855 select CPU_SUPPORTS_32BIT_KERNEL
>> 1856 select CPU_SUPPORTS_HIGHMEM
>> 1857 select CPU_SUPPORTS_CPUFREQ
1037 1858
1038 If unsure, say Y. !! 1859 config CPU_BMIPS32_3300
>> 1860 select SMP_UP if SMP
>> 1861 bool
1039 1862
1040 config ARM64_ERRATUM_2645198 !! 1863 config CPU_BMIPS4350
1041 bool "Cortex-A715: 2645198: Workaroun !! 1864 bool
1042 default y !! 1865 select SYS_SUPPORTS_SMP
1043 help !! 1866 select SYS_SUPPORTS_HOTPLUG_CPU
1044 This option adds the workaround for <<
1045 1867
1046 If a Cortex-A715 cpu sees a page ma !! 1868 config CPU_BMIPS4380
1047 to non-executable, it may corrupt t !! 1869 bool
1048 next instruction abort caused by pe !! 1870 select MIPS_L1_CACHE_SHIFT_6
>> 1871 select SYS_SUPPORTS_SMP
>> 1872 select SYS_SUPPORTS_HOTPLUG_CPU
>> 1873 select CPU_HAS_RIXI
1049 1874
1050 Only user-space does executable to !! 1875 config CPU_BMIPS5000
1051 mprotect() system call. Workaround !! 1876 bool
1052 TLB invalidation, for all changes t !! 1877 select MIPS_CPU_SCACHE
>> 1878 select MIPS_L1_CACHE_SHIFT_7
>> 1879 select SYS_SUPPORTS_SMP
>> 1880 select SYS_SUPPORTS_HOTPLUG_CPU
>> 1881 select CPU_HAS_RIXI
1053 1882
1054 If unsure, say Y. !! 1883 config SYS_HAS_CPU_LOONGSON3
>> 1884 bool
>> 1885 select CPU_SUPPORTS_CPUFREQ
>> 1886 select CPU_HAS_RIXI
1055 1887
1056 config ARM64_WORKAROUND_SPECULATIVE_UNPRIV_LO !! 1888 config SYS_HAS_CPU_LOONGSON2E
1057 bool 1889 bool
1058 1890
1059 config ARM64_ERRATUM_2966298 !! 1891 config SYS_HAS_CPU_LOONGSON2F
1060 bool "Cortex-A520: 2966298: workaroun !! 1892 bool
1061 select ARM64_WORKAROUND_SPECULATIVE_U !! 1893 select CPU_SUPPORTS_CPUFREQ
1062 default y !! 1894 select CPU_SUPPORTS_ADDRWINCFG if 64BIT
1063 help !! 1895 select CPU_SUPPORTS_UNCACHED_ACCELERATED
1064 This option adds the workaround for <<
1065 1896
1066 On an affected Cortex-A520 core, a !! 1897 config SYS_HAS_CPU_LOONGSON1B
1067 load might leak data from a privile !! 1898 bool
1068 1899
1069 Work around this problem by executi !! 1900 config SYS_HAS_CPU_LOONGSON1C
>> 1901 bool
1070 1902
1071 If unsure, say Y. !! 1903 config SYS_HAS_CPU_MIPS32_R1
>> 1904 bool
1072 1905
1073 config ARM64_ERRATUM_3117295 !! 1906 config SYS_HAS_CPU_MIPS32_R2
1074 bool "Cortex-A510: 3117295: workaroun !! 1907 bool
1075 select ARM64_WORKAROUND_SPECULATIVE_U <<
1076 default y <<
1077 help <<
1078 This option adds the workaround for <<
1079 1908
1080 On an affected Cortex-A510 core, a !! 1909 config SYS_HAS_CPU_MIPS32_R3_5
1081 load might leak data from a privile !! 1910 bool
1082 1911
1083 Work around this problem by executi !! 1912 config SYS_HAS_CPU_MIPS32_R5
>> 1913 bool
1084 1914
1085 If unsure, say Y. !! 1915 config SYS_HAS_CPU_MIPS32_R6
>> 1916 bool
1086 1917
1087 config ARM64_ERRATUM_3194386 !! 1918 config SYS_HAS_CPU_MIPS64_R1
1088 bool "Cortex-*/Neoverse-*: workaround !! 1919 bool
1089 default y <<
1090 help <<
1091 This option adds the workaround for <<
1092 1920
1093 * ARM Cortex-A76 erratum 3324349 !! 1921 config SYS_HAS_CPU_MIPS64_R2
1094 * ARM Cortex-A77 erratum 3324348 !! 1922 bool
1095 * ARM Cortex-A78 erratum 3324344 <<
1096 * ARM Cortex-A78C erratum 3324346 <<
1097 * ARM Cortex-A78C erratum 3324347 <<
1098 * ARM Cortex-A710 erratam 3324338 <<
1099 * ARM Cortex-A715 errartum 3456084 <<
1100 * ARM Cortex-A720 erratum 3456091 <<
1101 * ARM Cortex-A725 erratum 3456106 <<
1102 * ARM Cortex-X1 erratum 3324344 <<
1103 * ARM Cortex-X1C erratum 3324346 <<
1104 * ARM Cortex-X2 erratum 3324338 <<
1105 * ARM Cortex-X3 erratum 3324335 <<
1106 * ARM Cortex-X4 erratum 3194386 <<
1107 * ARM Cortex-X925 erratum 3324334 <<
1108 * ARM Neoverse-N1 erratum 3324349 <<
1109 * ARM Neoverse N2 erratum 3324339 <<
1110 * ARM Neoverse-N3 erratum 3456111 <<
1111 * ARM Neoverse-V1 erratum 3324341 <<
1112 * ARM Neoverse V2 erratum 3324336 <<
1113 * ARM Neoverse-V3 erratum 3312417 <<
1114 <<
1115 On affected cores "MSR SSBS, #0" in <<
1116 subsequent speculative instructions <<
1117 speculative store bypassing. <<
1118 <<
1119 Work around this problem by placing <<
1120 Instruction Synchronization Barrier <<
1121 SSBS. The presence of the SSBS spec <<
1122 from hwcaps and EL0 reads of ID_AA6 <<
1123 will use the PR_SPEC_STORE_BYPASS p <<
1124 1923
1125 If unsure, say Y. !! 1924 config SYS_HAS_CPU_MIPS64_R6
>> 1925 bool
1126 1926
1127 config CAVIUM_ERRATUM_22375 !! 1927 config SYS_HAS_CPU_R3000
1128 bool "Cavium erratum 22375, 24313" !! 1928 bool
1129 default y <<
1130 help <<
1131 Enable workaround for errata 22375 <<
1132 1929
1133 This implements two gicv3-its errat !! 1930 config SYS_HAS_CPU_TX39XX
1134 with a small impact affecting only !! 1931 bool
1135 1932
1136 erratum 22375: only alloc 8MB tab !! 1933 config SYS_HAS_CPU_VR41XX
1137 erratum 24313: ignore memory acce !! 1934 bool
1138 1935
1139 The fixes are in ITS initialization !! 1936 config SYS_HAS_CPU_R4300
1140 type and table size provided by the !! 1937 bool
1141 1938
1142 If unsure, say Y. !! 1939 config SYS_HAS_CPU_R4X00
>> 1940 bool
1143 1941
1144 config CAVIUM_ERRATUM_23144 !! 1942 config SYS_HAS_CPU_TX49XX
1145 bool "Cavium erratum 23144: ITS SYNC !! 1943 bool
1146 depends on NUMA <<
1147 default y <<
1148 help <<
1149 ITS SYNC command hang for cross nod <<
1150 1944
1151 If unsure, say Y. !! 1945 config SYS_HAS_CPU_R5000
>> 1946 bool
1152 1947
1153 config CAVIUM_ERRATUM_23154 !! 1948 config SYS_HAS_CPU_R5432
1154 bool "Cavium errata 23154 and 38545: !! 1949 bool
1155 default y <<
1156 help <<
1157 The ThunderX GICv3 implementation r <<
1158 reading the IAR status to ensure da <<
1159 (access to icc_iar1_el1 is not sync <<
1160 1950
1161 It also suffers from erratum 38545 !! 1951 config SYS_HAS_CPU_R5500
1162 OcteonTX and OcteonTX2), resulting !! 1952 bool
1163 spuriously presented to the CPU int <<
1164 1953
1165 If unsure, say Y. !! 1954 config SYS_HAS_CPU_NEVADA
>> 1955 bool
1166 1956
1167 config CAVIUM_ERRATUM_27456 !! 1957 config SYS_HAS_CPU_R8000
1168 bool "Cavium erratum 27456: Broadcast !! 1958 bool
1169 default y <<
1170 help <<
1171 On ThunderX T88 pass 1.x through 2. <<
1172 instructions may cause the icache t <<
1173 contains data for a non-current ASI <<
1174 invalidate the icache when changing <<
1175 1959
1176 If unsure, say Y. !! 1960 config SYS_HAS_CPU_R10000
>> 1961 bool
1177 1962
1178 config CAVIUM_ERRATUM_30115 !! 1963 config SYS_HAS_CPU_RM7000
1179 bool "Cavium erratum 30115: Guest may !! 1964 bool
1180 default y <<
1181 help <<
1182 On ThunderX T88 pass 1.x through 2. <<
1183 1.2, and T83 Pass 1.0, KVM guest ex <<
1184 interrupts in host. Trapping both G <<
1185 accesses sidesteps the issue. <<
1186 1965
1187 If unsure, say Y. !! 1966 config SYS_HAS_CPU_SB1
>> 1967 bool
1188 1968
1189 config CAVIUM_TX2_ERRATUM_219 !! 1969 config SYS_HAS_CPU_CAVIUM_OCTEON
1190 bool "Cavium ThunderX2 erratum 219: P !! 1970 bool
1191 default y <<
1192 help <<
1193 On Cavium ThunderX2, a load, store <<
1194 TTBR update and the corresponding c <<
1195 cause a spurious Data Abort to be d <<
1196 the CPU core. <<
1197 <<
1198 Work around the issue by avoiding t <<
1199 trapping KVM guest TTBRx_EL1 writes <<
1200 trap handler performs the correspon <<
1201 instruction and ensures context syn <<
1202 exception return. <<
1203 1971
1204 If unsure, say Y. !! 1972 config SYS_HAS_CPU_BMIPS
>> 1973 bool
1205 1974
1206 config FUJITSU_ERRATUM_010001 !! 1975 config SYS_HAS_CPU_BMIPS32_3300
1207 bool "Fujitsu-A64FX erratum E#010001: !! 1976 bool
1208 default y !! 1977 select SYS_HAS_CPU_BMIPS
1209 help <<
1210 This option adds a workaround for F <<
1211 On some variants of the Fujitsu-A64 <<
1212 accesses may cause undefined fault <<
1213 This fault occurs under a specific <<
1214 load/store instruction performs an <<
1215 case-1 TTBR0_EL1 with TCR_EL1.NFD0 <<
1216 case-2 TTBR0_EL2 with TCR_EL2.NFD0 <<
1217 case-3 TTBR1_EL1 with TCR_EL1.NFD1 <<
1218 case-4 TTBR1_EL2 with TCR_EL2.NFD1 <<
1219 1978
1220 The workaround is to ensure these b !! 1979 config SYS_HAS_CPU_BMIPS4350
1221 The workaround only affects the Fuj !! 1980 bool
>> 1981 select SYS_HAS_CPU_BMIPS
1222 1982
1223 If unsure, say Y. !! 1983 config SYS_HAS_CPU_BMIPS4380
>> 1984 bool
>> 1985 select SYS_HAS_CPU_BMIPS
1224 1986
1225 config HISILICON_ERRATUM_161600802 !! 1987 config SYS_HAS_CPU_BMIPS5000
1226 bool "Hip07 161600802: Erroneous redi !! 1988 bool
1227 default y !! 1989 select SYS_HAS_CPU_BMIPS
1228 help <<
1229 The HiSilicon Hip07 SoC uses the wr <<
1230 when issued ITS commands such as VM <<
1231 a 128kB offset to be applied to the <<
1232 1990
1233 If unsure, say Y. !! 1991 config SYS_HAS_CPU_XLR
>> 1992 bool
1234 1993
1235 config QCOM_FALKOR_ERRATUM_1003 !! 1994 config SYS_HAS_CPU_XLP
1236 bool "Falkor E1003: Incorrect transla !! 1995 bool
1237 default y <<
1238 help <<
1239 On Falkor v1, an incorrect ASID may <<
1240 and BADDR are changed together in T <<
1241 in TTBR1_EL1, this situation only o <<
1242 then only for entries in the walk c <<
1243 is unchanged. Work around the errat <<
1244 entries for the trampoline before e <<
1245 1996
1246 config QCOM_FALKOR_ERRATUM_1009 !! 1997 config MIPS_MALTA_PM
1247 bool "Falkor E1009: Prematurely compl !! 1998 depends on MIPS_MALTA
>> 1999 depends on PCI
>> 2000 bool
1248 default y 2001 default y
1249 select ARM64_WORKAROUND_REPEAT_TLBI <<
1250 help <<
1251 On Falkor v1, the CPU may premature <<
1252 TLBI xxIS invalidate maintenance op <<
1253 one more time to fix the issue. <<
1254 2002
1255 If unsure, say Y. !! 2003 #
>> 2004 # CPU may reorder R->R, R->W, W->R, W->W
>> 2005 # Reordering beyond LL and SC is handled in WEAK_REORDERING_BEYOND_LLSC
>> 2006 #
>> 2007 config WEAK_ORDERING
>> 2008 bool
1256 2009
1257 config QCOM_QDF2400_ERRATUM_0065 !! 2010 #
1258 bool "QDF2400 E0065: Incorrect GITS_T !! 2011 # CPU may reorder reads and writes beyond LL/SC
1259 default y !! 2012 # CPU may reorder R->LL, R->LL, W->LL, W->LL, R->SC, R->SC, W->SC, W->SC
1260 help !! 2013 #
1261 On Qualcomm Datacenter Technologies !! 2014 config WEAK_REORDERING_BEYOND_LLSC
1262 ITE size incorrectly. The GITS_TYPE !! 2015 bool
1263 been indicated as 16Bytes (0xf), no !! 2016 endmenu
1264 2017
1265 If unsure, say Y. !! 2018 #
>> 2019 # These two indicate any level of the MIPS32 and MIPS64 architecture
>> 2020 #
>> 2021 config CPU_MIPS32
>> 2022 bool
>> 2023 default y if CPU_MIPS32_R1 || CPU_MIPS32_R2 || CPU_MIPS32_R6
1266 2024
1267 config QCOM_FALKOR_ERRATUM_E1041 !! 2025 config CPU_MIPS64
1268 bool "Falkor E1041: Speculative instr !! 2026 bool
1269 default y !! 2027 default y if CPU_MIPS64_R1 || CPU_MIPS64_R2 || CPU_MIPS64_R6
1270 help <<
1271 Falkor CPU may speculatively fetch <<
1272 memory location when MMU translatio <<
1273 to SCTLR_ELn[M]=0. Prefix an ISB in <<
1274 2028
1275 If unsure, say Y. !! 2029 #
>> 2030 # These two indicate the revision of the architecture, either Release 1 or Release 2
>> 2031 #
>> 2032 config CPU_MIPSR1
>> 2033 bool
>> 2034 default y if CPU_MIPS32_R1 || CPU_MIPS64_R1
1276 2035
1277 config NVIDIA_CARMEL_CNP_ERRATUM !! 2036 config CPU_MIPSR2
1278 bool "NVIDIA Carmel CNP: CNP on Carme !! 2037 bool
1279 default y !! 2038 default y if CPU_MIPS32_R2 || CPU_MIPS64_R2 || CPU_CAVIUM_OCTEON
1280 help !! 2039 select CPU_HAS_RIXI
1281 If CNP is enabled on Carmel cores, !! 2040 select MIPS_SPRAM
1282 invalidate shared TLB entries insta <<
1283 on standard ARM cores. <<
1284 2041
1285 If unsure, say Y. !! 2042 config CPU_MIPSR6
>> 2043 bool
>> 2044 default y if CPU_MIPS32_R6 || CPU_MIPS64_R6
>> 2045 select CPU_HAS_RIXI
>> 2046 select HAVE_ARCH_BITREVERSE
>> 2047 select MIPS_ASID_BITS_VARIABLE
>> 2048 select MIPS_SPRAM
1286 2049
1287 config ROCKCHIP_ERRATUM_3588001 !! 2050 config EVA
1288 bool "Rockchip 3588001: GIC600 can no !! 2051 bool
1289 default y <<
1290 help <<
1291 The Rockchip RK3588 GIC600 SoC inte <<
1292 This means, that its sharability fe <<
1293 is supported by the IP itself. <<
1294 2052
1295 If unsure, say Y. !! 2053 config XPA
>> 2054 bool
1296 2055
1297 config SOCIONEXT_SYNQUACER_PREITS !! 2056 config SYS_SUPPORTS_32BIT_KERNEL
1298 bool "Socionext Synquacer: Workaround !! 2057 bool
1299 default y !! 2058 config SYS_SUPPORTS_64BIT_KERNEL
1300 help !! 2059 bool
1301 Socionext Synquacer SoCs implement !! 2060 config CPU_SUPPORTS_32BIT_KERNEL
1302 MSI doorbell writes with non-zero v !! 2061 bool
>> 2062 config CPU_SUPPORTS_64BIT_KERNEL
>> 2063 bool
>> 2064 config CPU_SUPPORTS_CPUFREQ
>> 2065 bool
>> 2066 config CPU_SUPPORTS_ADDRWINCFG
>> 2067 bool
>> 2068 config CPU_SUPPORTS_HUGEPAGES
>> 2069 bool
>> 2070 config CPU_SUPPORTS_UNCACHED_ACCELERATED
>> 2071 bool
>> 2072 config MIPS_PGD_C0_CONTEXT
>> 2073 bool
>> 2074 default y if 64BIT && (CPU_MIPSR2 || CPU_MIPSR6) && !CPU_XLP
1303 2075
1304 If unsure, say Y. !! 2076 #
>> 2077 # Set to y for ptrace access to watch registers.
>> 2078 #
>> 2079 config HARDWARE_WATCHPOINTS
>> 2080 bool
>> 2081 default y if CPU_MIPSR1 || CPU_MIPSR2 || CPU_MIPSR6
1305 2082
1306 endmenu # "ARM errata workarounds via the alt !! 2083 menu "Kernel type"
1307 2084
1308 choice 2085 choice
1309 prompt "Page size" !! 2086 prompt "Kernel code model"
1310 default ARM64_4K_PAGES <<
1311 help 2087 help
1312 Page size (translation granule) con !! 2088 You should only select this option if you have a workload that
1313 !! 2089 actually benefits from 64-bit processing or if your machine has
1314 config ARM64_4K_PAGES !! 2090 large memory. You will only be presented a single option in this
1315 bool "4KB" !! 2091 menu if your system does not support both 32-bit and 64-bit kernels.
1316 select HAVE_PAGE_SIZE_4KB !! 2092
1317 help !! 2093 config 32BIT
1318 This feature enables 4KB pages supp !! 2094 bool "32-bit kernel"
1319 !! 2095 depends on CPU_SUPPORTS_32BIT_KERNEL && SYS_SUPPORTS_32BIT_KERNEL
1320 config ARM64_16K_PAGES !! 2096 select TRAD_SIGNALS
1321 bool "16KB" <<
1322 select HAVE_PAGE_SIZE_16KB <<
1323 help 2097 help
1324 The system will use 16KB pages supp !! 2098 Select this option if you want to build a 32-bit kernel.
1325 requires applications compiled with <<
1326 aligned segments. <<
1327 2099
1328 config ARM64_64K_PAGES !! 2100 config 64BIT
1329 bool "64KB" !! 2101 bool "64-bit kernel"
1330 select HAVE_PAGE_SIZE_64KB !! 2102 depends on CPU_SUPPORTS_64BIT_KERNEL && SYS_SUPPORTS_64BIT_KERNEL
1331 help 2103 help
1332 This feature enables 64KB pages sup !! 2104 Select this option if you want to build a 64-bit kernel.
1333 allowing only two levels of page ta <<
1334 look-up. AArch32 emulation requires <<
1335 with 64K aligned segments. <<
1336 2105
1337 endchoice 2106 endchoice
1338 2107
>> 2108 config KVM_GUEST
>> 2109 bool "KVM Guest Kernel"
>> 2110 depends on BROKEN_ON_SMP
>> 2111 help
>> 2112 Select this option if building a guest kernel for KVM (Trap & Emulate)
>> 2113 mode.
>> 2114
>> 2115 config KVM_GUEST_TIMER_FREQ
>> 2116 int "Count/Compare Timer Frequency (MHz)"
>> 2117 depends on KVM_GUEST
>> 2118 default 100
>> 2119 help
>> 2120 Set this to non-zero if building a guest kernel for KVM to skip RTC
>> 2121 emulation when determining guest CPU Frequency. Instead, the guest's
>> 2122 timer frequency is specified directly.
>> 2123
>> 2124 config MIPS_VA_BITS_48
>> 2125 bool "48 bits virtual memory"
>> 2126 depends on 64BIT
>> 2127 help
>> 2128 Support a maximum at least 48 bits of application virtual
>> 2129 memory. Default is 40 bits or less, depending on the CPU.
>> 2130 For page sizes 16k and above, this option results in a small
>> 2131 memory overhead for page tables. For 4k page size, a fourth
>> 2132 level of page tables is added which imposes both a memory
>> 2133 overhead as well as slower TLB fault handling.
>> 2134
>> 2135 If unsure, say N.
>> 2136
1339 choice 2137 choice
1340 prompt "Virtual address space size" !! 2138 prompt "Kernel page size"
1341 default ARM64_VA_BITS_52 !! 2139 default PAGE_SIZE_4KB
1342 help <<
1343 Allows choosing one of multiple pos <<
1344 space sizes. The level of translati <<
1345 a combination of page size and virt <<
1346 <<
1347 config ARM64_VA_BITS_36 <<
1348 bool "36-bit" if EXPERT <<
1349 depends on PAGE_SIZE_16KB <<
1350 <<
1351 config ARM64_VA_BITS_39 <<
1352 bool "39-bit" <<
1353 depends on PAGE_SIZE_4KB <<
1354 <<
1355 config ARM64_VA_BITS_42 <<
1356 bool "42-bit" <<
1357 depends on PAGE_SIZE_64KB <<
1358 <<
1359 config ARM64_VA_BITS_47 <<
1360 bool "47-bit" <<
1361 depends on PAGE_SIZE_16KB <<
1362 <<
1363 config ARM64_VA_BITS_48 <<
1364 bool "48-bit" <<
1365 <<
1366 config ARM64_VA_BITS_52 <<
1367 bool "52-bit" <<
1368 depends on ARM64_PAN || !ARM64_SW_TTB <<
1369 help <<
1370 Enable 52-bit virtual addressing fo <<
1371 requested via a hint to mmap(). The <<
1372 virtual addresses for its own mappi <<
1373 this feature is available, otherwis <<
1374 <<
1375 NOTE: Enabling 52-bit virtual addre <<
1376 ARMv8.3 Pointer Authentication will <<
1377 reduced from 7 bits to 3 bits, whic <<
1378 impact on its susceptibility to bru <<
1379 2140
1380 If unsure, select 48-bit virtual ad !! 2141 config PAGE_SIZE_4KB
>> 2142 bool "4kB"
>> 2143 depends on !CPU_LOONGSON2 && !CPU_LOONGSON3
>> 2144 help
>> 2145 This option select the standard 4kB Linux page size. On some
>> 2146 R3000-family processors this is the only available page size. Using
>> 2147 4kB page size will minimize memory consumption and is therefore
>> 2148 recommended for low memory systems.
>> 2149
>> 2150 config PAGE_SIZE_8KB
>> 2151 bool "8kB"
>> 2152 depends on CPU_R8000 || CPU_CAVIUM_OCTEON
>> 2153 depends on !MIPS_VA_BITS_48
>> 2154 help
>> 2155 Using 8kB page size will result in higher performance kernel at
>> 2156 the price of higher memory consumption. This option is available
>> 2157 only on R8000 and cnMIPS processors. Note that you will need a
>> 2158 suitable Linux distribution to support this.
>> 2159
>> 2160 config PAGE_SIZE_16KB
>> 2161 bool "16kB"
>> 2162 depends on !CPU_R3000 && !CPU_TX39XX
>> 2163 help
>> 2164 Using 16kB page size will result in higher performance kernel at
>> 2165 the price of higher memory consumption. This option is available on
>> 2166 all non-R3000 family processors. Note that you will need a suitable
>> 2167 Linux distribution to support this.
>> 2168
>> 2169 config PAGE_SIZE_32KB
>> 2170 bool "32kB"
>> 2171 depends on CPU_CAVIUM_OCTEON
>> 2172 depends on !MIPS_VA_BITS_48
>> 2173 help
>> 2174 Using 32kB page size will result in higher performance kernel at
>> 2175 the price of higher memory consumption. This option is available
>> 2176 only on cnMIPS cores. Note that you will need a suitable Linux
>> 2177 distribution to support this.
>> 2178
>> 2179 config PAGE_SIZE_64KB
>> 2180 bool "64kB"
>> 2181 depends on !CPU_R3000 && !CPU_TX39XX
>> 2182 help
>> 2183 Using 64kB page size will result in higher performance kernel at
>> 2184 the price of higher memory consumption. This option is available on
>> 2185 all non-R3000 family processor. Not that at the time of this
>> 2186 writing this option is still high experimental.
1381 2187
1382 endchoice 2188 endchoice
1383 2189
1384 config ARM64_FORCE_52BIT !! 2190 config FORCE_MAX_ZONEORDER
1385 bool "Force 52-bit virtual addresses !! 2191 int "Maximum zone order"
1386 depends on ARM64_VA_BITS_52 && EXPERT !! 2192 range 14 64 if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_64KB
1387 help !! 2193 default "14" if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_64KB
1388 For systems with 52-bit userspace V !! 2194 range 13 64 if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_32KB
1389 to maintain compatibility with olde !! 2195 default "13" if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_32KB
1390 unless a hint is supplied to mmap. !! 2196 range 12 64 if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_16KB
1391 !! 2197 default "12" if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_16KB
1392 This configuration option disables !! 2198 range 11 64
1393 forces all userspace addresses to b !! 2199 default "11"
1394 should only enable this configurati !! 2200 help
1395 memory management code. If unsure s !! 2201 The kernel memory allocator divides physically contiguous memory
>> 2202 blocks into "zones", where each zone is a power of two number of
>> 2203 pages. This option selects the largest power of two that the kernel
>> 2204 keeps in the memory allocator. If you need to allocate very large
>> 2205 blocks of physically contiguous memory, then you may need to
>> 2206 increase this value.
1396 2207
1397 config ARM64_VA_BITS !! 2208 This config option is actually maximum order plus one. For example,
1398 int !! 2209 a value of 11 means that the largest free memory block is 2^10 pages.
1399 default 36 if ARM64_VA_BITS_36 <<
1400 default 39 if ARM64_VA_BITS_39 <<
1401 default 42 if ARM64_VA_BITS_42 <<
1402 default 47 if ARM64_VA_BITS_47 <<
1403 default 48 if ARM64_VA_BITS_48 <<
1404 default 52 if ARM64_VA_BITS_52 <<
1405 2210
1406 choice !! 2211 The page size is not necessarily 4KB. Keep this in mind
1407 prompt "Physical address space size" !! 2212 when choosing a value for this option.
1408 default ARM64_PA_BITS_48 <<
1409 help <<
1410 Choose the maximum physical address <<
1411 support. <<
1412 2213
1413 config ARM64_PA_BITS_48 !! 2214 config BOARD_SCACHE
1414 bool "48-bit" !! 2215 bool
1415 depends on ARM64_64K_PAGES || !ARM64_ <<
1416 <<
1417 config ARM64_PA_BITS_52 <<
1418 bool "52-bit" <<
1419 depends on ARM64_64K_PAGES || ARM64_V <<
1420 depends on ARM64_PAN || !ARM64_SW_TTB <<
1421 help <<
1422 Enable support for a 52-bit physica <<
1423 part of the ARMv8.2-LPA extension. <<
1424 <<
1425 With this enabled, the kernel will <<
1426 do not support ARMv8.2-LPA, but wit <<
1427 minor performance overhead). <<
1428 2216
1429 endchoice !! 2217 config IP22_CPU_SCACHE
>> 2218 bool
>> 2219 select BOARD_SCACHE
1430 2220
1431 config ARM64_PA_BITS !! 2221 #
1432 int !! 2222 # Support for a MIPS32 / MIPS64 style S-caches
1433 default 48 if ARM64_PA_BITS_48 !! 2223 #
1434 default 52 if ARM64_PA_BITS_52 !! 2224 config MIPS_CPU_SCACHE
>> 2225 bool
>> 2226 select BOARD_SCACHE
1435 2227
1436 config ARM64_LPA2 !! 2228 config R5000_CPU_SCACHE
1437 def_bool y !! 2229 bool
1438 depends on ARM64_PA_BITS_52 && !ARM64 !! 2230 select BOARD_SCACHE
1439 2231
1440 choice !! 2232 config RM7000_CPU_SCACHE
1441 prompt "Endianness" !! 2233 bool
1442 default CPU_LITTLE_ENDIAN !! 2234 select BOARD_SCACHE
1443 help <<
1444 Select the endianness of data acces <<
1445 applications will need to be compil <<
1446 that is selected here. <<
1447 2235
1448 config CPU_BIG_ENDIAN !! 2236 config SIBYTE_DMA_PAGEOPS
1449 bool "Build big-endian kernel" !! 2237 bool "Use DMA to clear/copy pages"
1450 # https://github.com/llvm/llvm-projec !! 2238 depends on CPU_SB1
1451 depends on AS_IS_GNU || AS_VERSION >= <<
1452 help 2239 help
1453 Say Y if you plan on running a kern !! 2240 Instead of using the CPU to zero and copy pages, use a Data Mover
>> 2241 channel. These DMA channels are otherwise unused by the standard
>> 2242 SiByte Linux port. Seems to give a small performance benefit.
1454 2243
1455 config CPU_LITTLE_ENDIAN !! 2244 config CPU_HAS_PREFETCH
1456 bool "Build little-endian kernel" !! 2245 bool
1457 help <<
1458 Say Y if you plan on running a kern <<
1459 This is usually the case for distri <<
1460 2246
1461 endchoice !! 2247 config CPU_GENERIC_DUMP_TLB
>> 2248 bool
>> 2249 default y if !(CPU_R3000 || CPU_R8000 || CPU_TX39XX)
1462 2250
1463 config SCHED_MC !! 2251 config CPU_R4K_FPU
1464 bool "Multi-core scheduler support" !! 2252 bool
1465 help !! 2253 default y if !(CPU_R3000 || CPU_TX39XX)
1466 Multi-core scheduler support improv <<
1467 making when dealing with multi-core <<
1468 increased overhead in some places. <<
1469 2254
1470 config SCHED_CLUSTER !! 2255 config CPU_R4K_CACHE_TLB
1471 bool "Cluster scheduler support" !! 2256 bool
1472 help !! 2257 default y if !(CPU_R3000 || CPU_R8000 || CPU_SB1 || CPU_TX39XX || CPU_CAVIUM_OCTEON)
1473 Cluster scheduler support improves !! 2258
1474 making when dealing with machines t !! 2259 config MIPS_MT_SMP
1475 Cluster usually means a couple of C !! 2260 bool "MIPS MT SMP support (1 TC on each available VPE)"
1476 by sharing mid-level caches, last-l !! 2261 default y
1477 busses. !! 2262 depends on SYS_SUPPORTS_MULTITHREADING && !CPU_MIPSR6 && !CPU_MICROMIPS
>> 2263 select CPU_MIPSR2_IRQ_VI
>> 2264 select CPU_MIPSR2_IRQ_EI
>> 2265 select SYNC_R4K
>> 2266 select MIPS_MT
>> 2267 select SMP
>> 2268 select SMP_UP
>> 2269 select SYS_SUPPORTS_SMP
>> 2270 select SYS_SUPPORTS_SCHED_SMT
>> 2271 select MIPS_PERF_SHARED_TC_COUNTERS
>> 2272 help
>> 2273 This is a kernel model which is known as SMVP. This is supported
>> 2274 on cores with the MT ASE and uses the available VPEs to implement
>> 2275 virtual processors which supports SMP. This is equivalent to the
>> 2276 Intel Hyperthreading feature. For further information go to
>> 2277 <http://www.imgtec.com/mips/mips-multithreading.asp>.
>> 2278
>> 2279 config MIPS_MT
>> 2280 bool
1478 2281
1479 config SCHED_SMT 2282 config SCHED_SMT
1480 bool "SMT scheduler support" !! 2283 bool "SMT (multithreading) scheduler support"
>> 2284 depends on SYS_SUPPORTS_SCHED_SMT
>> 2285 default n
1481 help 2286 help
1482 Improves the CPU scheduler's decisi !! 2287 SMT scheduler support improves the CPU scheduler's decision making
1483 MultiThreading at a cost of slightl !! 2288 when dealing with MIPS MT enabled cores at a cost of slightly
1484 places. If unsure say N here. !! 2289 increased overhead in some places. If unsure say N here.
1485 2290
1486 config NR_CPUS !! 2291 config SYS_SUPPORTS_SCHED_SMT
1487 int "Maximum number of CPUs (2-4096)" !! 2292 bool
1488 range 2 4096 <<
1489 default "512" <<
1490 2293
1491 config HOTPLUG_CPU !! 2294 config SYS_SUPPORTS_MULTITHREADING
1492 bool "Support for hot-pluggable CPUs" !! 2295 bool
1493 select GENERIC_IRQ_MIGRATION <<
1494 help <<
1495 Say Y here to experiment with turni <<
1496 can be controlled through /sys/devi <<
1497 2296
1498 # Common NUMA Features !! 2297 config MIPS_MT_FPAFF
1499 config NUMA !! 2298 bool "Dynamic FPU affinity for FP-intensive threads"
1500 bool "NUMA Memory Allocation and Sche !! 2299 default y
1501 select GENERIC_ARCH_NUMA !! 2300 depends on MIPS_MT_SMP
1502 select OF_NUMA <<
1503 select HAVE_SETUP_PER_CPU_AREA <<
1504 select NEED_PER_CPU_EMBED_FIRST_CHUNK <<
1505 select NEED_PER_CPU_PAGE_FIRST_CHUNK <<
1506 select USE_PERCPU_NUMA_NODE_ID <<
1507 help <<
1508 Enable NUMA (Non-Uniform Memory Acc <<
1509 <<
1510 The kernel will try to allocate mem <<
1511 local memory of the CPU and add som <<
1512 NUMA awareness to the kernel. <<
1513 2301
1514 config NODES_SHIFT !! 2302 config MIPSR2_TO_R6_EMULATOR
1515 int "Maximum NUMA Nodes (as a power o !! 2303 bool "MIPS R2-to-R6 emulator"
1516 range 1 10 !! 2304 depends on CPU_MIPSR6
1517 default "4" !! 2305 default y
1518 depends on NUMA <<
1519 help 2306 help
1520 Specify the maximum number of NUMA !! 2307 Choose this option if you want to run non-R6 MIPS userland code.
1521 system. Increases memory reserved !! 2308 Even if you say 'Y' here, the emulator will still be disabled by
>> 2309 default. You can enable it using the 'mipsr2emu' kernel option.
>> 2310 The only reason this is a build-time option is to save ~14K from the
>> 2311 final kernel image.
1522 2312
1523 source "kernel/Kconfig.hz" !! 2313 config MIPS_VPE_LOADER
1524 !! 2314 bool "VPE loader support."
1525 config ARCH_SPARSEMEM_ENABLE !! 2315 depends on SYS_SUPPORTS_MULTITHREADING && MODULES
1526 def_bool y !! 2316 select CPU_MIPSR2_IRQ_VI
1527 select SPARSEMEM_VMEMMAP_ENABLE !! 2317 select CPU_MIPSR2_IRQ_EI
1528 select SPARSEMEM_VMEMMAP !! 2318 select MIPS_MT
>> 2319 help
>> 2320 Includes a loader for loading an elf relocatable object
>> 2321 onto another VPE and running it.
1529 2322
1530 config HW_PERF_EVENTS !! 2323 config MIPS_VPE_LOADER_CMP
1531 def_bool y !! 2324 bool
1532 depends on ARM_PMU !! 2325 default "y"
>> 2326 depends on MIPS_VPE_LOADER && MIPS_CMP
1533 2327
1534 # Supported by clang >= 7.0 or GCC >= 12.0.0 !! 2328 config MIPS_VPE_LOADER_MT
1535 config CC_HAVE_SHADOW_CALL_STACK !! 2329 bool
1536 def_bool $(cc-option, -fsanitize=shad !! 2330 default "y"
>> 2331 depends on MIPS_VPE_LOADER && !MIPS_CMP
1537 2332
1538 config PARAVIRT !! 2333 config MIPS_VPE_LOADER_TOM
1539 bool "Enable paravirtualization code" !! 2334 bool "Load VPE program into memory hidden from linux"
>> 2335 depends on MIPS_VPE_LOADER
>> 2336 default y
1540 help 2337 help
1541 This changes the kernel so it can m !! 2338 The loader can use memory that is present but has been hidden from
1542 under a hypervisor, potentially imp !! 2339 Linux using the kernel command line option "mem=xxMB". It's up to
1543 over full virtualization. !! 2340 you to ensure the amount you put in the option and the space your
>> 2341 program requires is less or equal to the amount physically present.
1544 2342
1545 config PARAVIRT_TIME_ACCOUNTING !! 2343 config MIPS_VPE_APSP_API
1546 bool "Paravirtual steal time accounti !! 2344 bool "Enable support for AP/SP API (RTLX)"
1547 select PARAVIRT !! 2345 depends on MIPS_VPE_LOADER
1548 help 2346 help
1549 Select this option to enable fine g <<
1550 accounting. Time spent executing ot <<
1551 the current vCPU is discounted from <<
1552 that, there can be a small performa <<
1553 2347
1554 If in doubt, say N here. !! 2348 config MIPS_VPE_APSP_API_CMP
>> 2349 bool
>> 2350 default "y"
>> 2351 depends on MIPS_VPE_APSP_API && MIPS_CMP
1555 2352
1556 config ARCH_SUPPORTS_KEXEC !! 2353 config MIPS_VPE_APSP_API_MT
1557 def_bool PM_SLEEP_SMP !! 2354 bool
>> 2355 default "y"
>> 2356 depends on MIPS_VPE_APSP_API && !MIPS_CMP
1558 2357
1559 config ARCH_SUPPORTS_KEXEC_FILE !! 2358 config MIPS_CMP
1560 def_bool y !! 2359 bool "MIPS CMP framework support (DEPRECATED)"
>> 2360 depends on SYS_SUPPORTS_MIPS_CMP && !CPU_MIPSR6
>> 2361 select SMP
>> 2362 select SYNC_R4K
>> 2363 select SYS_SUPPORTS_SMP
>> 2364 select WEAK_ORDERING
>> 2365 default n
>> 2366 help
>> 2367 Select this if you are using a bootloader which implements the "CMP
>> 2368 framework" protocol (ie. YAMON) and want your kernel to make use of
>> 2369 its ability to start secondary CPUs.
>> 2370
>> 2371 Unless you have a specific need, you should use CONFIG_MIPS_CPS
>> 2372 instead of this.
>> 2373
>> 2374 config MIPS_CPS
>> 2375 bool "MIPS Coherent Processing System support"
>> 2376 depends on SYS_SUPPORTS_MIPS_CPS
>> 2377 select MIPS_CM
>> 2378 select MIPS_CPS_PM if HOTPLUG_CPU
>> 2379 select SMP
>> 2380 select SYNC_R4K if (CEVT_R4K || CSRC_R4K)
>> 2381 select SYS_SUPPORTS_HOTPLUG_CPU
>> 2382 select SYS_SUPPORTS_SCHED_SMT if CPU_MIPSR6
>> 2383 select SYS_SUPPORTS_SMP
>> 2384 select WEAK_ORDERING
>> 2385 help
>> 2386 Select this if you wish to run an SMP kernel across multiple cores
>> 2387 within a MIPS Coherent Processing System. When this option is
>> 2388 enabled the kernel will probe for other cores and boot them with
>> 2389 no external assistance. It is safe to enable this when hardware
>> 2390 support is unavailable.
1561 2391
1562 config ARCH_SELECTS_KEXEC_FILE !! 2392 config MIPS_CPS_PM
1563 def_bool y !! 2393 depends on MIPS_CPS
1564 depends on KEXEC_FILE !! 2394 bool
1565 select HAVE_IMA_KEXEC if IMA <<
1566 2395
1567 config ARCH_SUPPORTS_KEXEC_SIG !! 2396 config MIPS_CM
1568 def_bool y !! 2397 bool
>> 2398 select MIPS_CPC
1569 2399
1570 config ARCH_SUPPORTS_KEXEC_IMAGE_VERIFY_SIG !! 2400 config MIPS_CPC
1571 def_bool y !! 2401 bool
1572 2402
1573 config ARCH_DEFAULT_KEXEC_IMAGE_VERIFY_SIG !! 2403 config SB1_PASS_2_WORKAROUNDS
1574 def_bool y !! 2404 bool
>> 2405 depends on CPU_SB1 && (CPU_SB1_PASS_2_2 || CPU_SB1_PASS_2)
>> 2406 default y
1575 2407
1576 config ARCH_SUPPORTS_CRASH_DUMP !! 2408 config SB1_PASS_2_1_WORKAROUNDS
1577 def_bool y !! 2409 bool
>> 2410 depends on CPU_SB1 && CPU_SB1_PASS_2
>> 2411 default y
1578 2412
1579 config ARCH_HAS_GENERIC_CRASHKERNEL_RESERVATI <<
1580 def_bool CRASH_RESERVE <<
1581 2413
1582 config TRANS_TABLE !! 2414 config ARCH_PHYS_ADDR_T_64BIT
1583 def_bool y !! 2415 bool
1584 depends on HIBERNATION || KEXEC_CORE <<
1585 2416
1586 config XEN_DOM0 !! 2417 choice
1587 def_bool y !! 2418 prompt "SmartMIPS or microMIPS ASE support"
1588 depends on XEN <<
1589 2419
1590 config XEN !! 2420 config CPU_NEEDS_NO_SMARTMIPS_OR_MICROMIPS
1591 bool "Xen guest support on ARM64" !! 2421 bool "None"
1592 depends on ARM64 && OF <<
1593 select SWIOTLB_XEN <<
1594 select PARAVIRT <<
1595 help 2422 help
1596 Say Y if you want to run Linux in a !! 2423 Select this if you want neither microMIPS nor SmartMIPS support
1597 2424
1598 # include/linux/mmzone.h requires the followi !! 2425 config CPU_HAS_SMARTMIPS
1599 # !! 2426 depends on SYS_SUPPORTS_SMARTMIPS
1600 # MAX_PAGE_ORDER + PAGE_SHIFT <= SECTION_SI !! 2427 bool "SmartMIPS"
1601 # !! 2428 help
1602 # so the maximum value of MAX_PAGE_ORDER is S !! 2429 SmartMIPS is a extension of the MIPS32 architecture aimed at
1603 # !! 2430 increased security at both hardware and software level for
1604 # | SECTION_SIZE_BITS | PAGE_SHIFT | m !! 2431 smartcards. Enabling this option will allow proper use of the
1605 # ----+-------------------+--------------+--- !! 2432 SmartMIPS instructions by Linux applications. However a kernel with
1606 # 4K | 27 | 12 | !! 2433 this option will not work on a MIPS core without SmartMIPS core. If
1607 # 16K | 27 | 14 | !! 2434 you don't know you probably don't have SmartMIPS and should say N
1608 # 64K | 29 | 16 | !! 2435 here.
1609 config ARCH_FORCE_MAX_ORDER !! 2436
1610 int !! 2437 config CPU_MICROMIPS
1611 default "13" if ARM64_64K_PAGES !! 2438 depends on 32BIT && SYS_SUPPORTS_MICROMIPS && !CPU_MIPSR6
1612 default "11" if ARM64_16K_PAGES !! 2439 bool "microMIPS"
1613 default "10" <<
1614 help 2440 help
1615 The kernel page allocator limits th !! 2441 When this option is enabled the kernel will be built using the
1616 contiguous allocations. The limit i !! 2442 microMIPS ISA
1617 defines the maximal power of two of <<
1618 allocated as a single contiguous bl <<
1619 overriding the default setting when <<
1620 large blocks of physically contiguo <<
1621 <<
1622 The maximal size of allocation cann <<
1623 section, so the value of MAX_PAGE_O <<
1624 <<
1625 MAX_PAGE_ORDER + PAGE_SHIFT <= SE <<
1626 2443
1627 Don't change if unsure. !! 2444 endchoice
1628 2445
1629 config UNMAP_KERNEL_AT_EL0 !! 2446 config CPU_HAS_MSA
1630 bool "Unmap kernel when running in us !! 2447 bool "Support for the MIPS SIMD Architecture"
1631 default y !! 2448 depends on CPU_SUPPORTS_MSA
1632 help !! 2449 depends on 64BIT || MIPS_O32_FP64_SUPPORT
1633 Speculation attacks against some hi !! 2450 help
1634 be used to bypass MMU permission ch !! 2451 MIPS SIMD Architecture (MSA) introduces 128 bit wide vector registers
1635 userspace. This can be defended aga !! 2452 and a set of SIMD instructions to operate on them. When this option
1636 when running in userspace, mapping !! 2453 is enabled the kernel will support allocating & switching MSA
1637 via a trampoline page in the vector !! 2454 vector register contexts. If you know that your kernel will only be
>> 2455 running on CPUs which do not support MSA or that your userland will
>> 2456 not be making use of it then you may wish to say N here to reduce
>> 2457 the size & complexity of your kernel.
1638 2458
1639 If unsure, say Y. 2459 If unsure, say Y.
1640 2460
1641 config MITIGATE_SPECTRE_BRANCH_HISTORY !! 2461 config CPU_HAS_WB
1642 bool "Mitigate Spectre style attacks !! 2462 bool
1643 default y <<
1644 help <<
1645 Speculation attacks against some hi <<
1646 make use of branch history to influ <<
1647 When taking an exception from user- <<
1648 or a firmware call overwrites the b <<
1649 2463
1650 config RODATA_FULL_DEFAULT_ENABLED !! 2464 config XKS01
1651 bool "Apply r/o permissions of VM are !! 2465 bool
1652 default y <<
1653 help <<
1654 Apply read-only attributes of VM ar <<
1655 the backing pages as well. This pre <<
1656 from being modified (inadvertently <<
1657 mapping of the same memory page. Th <<
1658 be turned off at runtime by passing <<
1659 with rodata=full if this option is <<
1660 2466
1661 This requires the linear region to !! 2467 config CPU_HAS_RIXI
1662 which may adversely affect performa !! 2468 bool
1663 2469
1664 config ARM64_SW_TTBR0_PAN !! 2470 #
1665 bool "Emulate Privileged Access Never !! 2471 # Vectored interrupt mode is an R2 feature
1666 depends on !KCSAN !! 2472 #
1667 help !! 2473 config CPU_MIPSR2_IRQ_VI
1668 Enabling this option prevents the k !! 2474 bool
1669 user-space memory directly by point <<
1670 zeroed area and reserved ASID. The <<
1671 restore the valid TTBR0_EL1 tempora <<
1672 2475
1673 config ARM64_TAGGED_ADDR_ABI !! 2476 #
1674 bool "Enable the tagged user addresse !! 2477 # Extended interrupt mode is an R2 feature
1675 default y !! 2478 #
1676 help !! 2479 config CPU_MIPSR2_IRQ_EI
1677 When this option is enabled, user a !! 2480 bool
1678 relaxed ABI via prctl() allowing ta <<
1679 to system calls as pointer argument <<
1680 Documentation/arch/arm64/tagged-add <<
1681 2481
1682 menuconfig COMPAT !! 2482 config CPU_HAS_SYNC
1683 bool "Kernel support for 32-bit EL0" !! 2483 bool
1684 depends on ARM64_4K_PAGES || EXPERT !! 2484 depends on !CPU_R3000
1685 select HAVE_UID16 !! 2485 default y
1686 select OLD_SIGSUSPEND3 <<
1687 select COMPAT_OLD_SIGACTION <<
1688 help <<
1689 This option enables support for a 3 <<
1690 kernel at EL1. AArch32-specific com <<
1691 the user helper functions, VFP supp <<
1692 handled appropriately by the kernel <<
1693 2486
1694 If you use a page size other than 4 !! 2487 #
1695 that you will only be able to execu !! 2488 # CPU non-features
1696 with page size aligned segments. !! 2489 #
>> 2490 config CPU_DADDI_WORKAROUNDS
>> 2491 bool
1697 2492
1698 If you want to execute 32-bit users !! 2493 config CPU_R4000_WORKAROUNDS
>> 2494 bool
>> 2495 select CPU_R4400_WORKAROUNDS
1699 2496
1700 if COMPAT !! 2497 config CPU_R4400_WORKAROUNDS
>> 2498 bool
1701 2499
1702 config KUSER_HELPERS !! 2500 config MIPS_ASID_SHIFT
1703 bool "Enable kuser helpers page for 3 !! 2501 int
1704 default y !! 2502 default 6 if CPU_R3000 || CPU_TX39XX
1705 help !! 2503 default 4 if CPU_R8000
1706 Warning: disabling this option may !! 2504 default 0
1707 2505
1708 Provide kuser helpers to compat tas !! 2506 config MIPS_ASID_BITS
1709 helper code to userspace in read on !! 2507 int
1710 to allow userspace to be independen !! 2508 default 0 if MIPS_ASID_BITS_VARIABLE
1711 the system. This permits binaries t !! 2509 default 6 if CPU_R3000 || CPU_TX39XX
1712 to ARMv8 without modification. !! 2510 default 8
1713 2511
1714 See Documentation/arch/arm/kernel_u !! 2512 config MIPS_ASID_BITS_VARIABLE
>> 2513 bool
1715 2514
1716 However, the fixed address nature o !! 2515 #
1717 by ROP (return orientated programmi !! 2516 # - Highmem only makes sense for the 32-bit kernel.
1718 exploits. !! 2517 # - The current highmem code will only work properly on physically indexed
>> 2518 # caches such as R3000, SB1, R7000 or those that look like they're virtually
>> 2519 # indexed such as R4000/R4400 SC and MC versions or R10000. So for the
>> 2520 # moment we protect the user and offer the highmem option only on machines
>> 2521 # where it's known to be safe. This will not offer highmem on a few systems
>> 2522 # such as MIPS32 and MIPS64 CPUs which may have virtual and physically
>> 2523 # indexed CPUs but we're playing safe.
>> 2524 # - We use SYS_SUPPORTS_HIGHMEM to offer highmem only for systems where we
>> 2525 # know they might have memory configurations that could make use of highmem
>> 2526 # support.
>> 2527 #
>> 2528 config HIGHMEM
>> 2529 bool "High Memory Support"
>> 2530 depends on 32BIT && CPU_SUPPORTS_HIGHMEM && SYS_SUPPORTS_HIGHMEM && !CPU_MIPS32_3_5_EVA
1719 2531
1720 If all of the binaries and librarie !! 2532 config CPU_SUPPORTS_HIGHMEM
1721 are built specifically for your pla !! 2533 bool
1722 these helpers, then you can turn th <<
1723 such exploits. However, in that cas <<
1724 relying on those helpers is run, it <<
1725 2534
1726 Say N here only if you are absolute !! 2535 config SYS_SUPPORTS_HIGHMEM
1727 need these helpers; otherwise, the !! 2536 bool
1728 2537
1729 config COMPAT_VDSO !! 2538 config SYS_SUPPORTS_SMARTMIPS
1730 bool "Enable vDSO for 32-bit applicat !! 2539 bool
1731 depends on !CPU_BIG_ENDIAN <<
1732 depends on (CC_IS_CLANG && LD_IS_LLD) <<
1733 select GENERIC_COMPAT_VDSO <<
1734 default y <<
1735 help <<
1736 Place in the process address space <<
1737 ELF shared object providing fast im <<
1738 and clock_gettime. <<
1739 2540
1740 You must have a 32-bit build of gli !! 2541 config SYS_SUPPORTS_MICROMIPS
1741 to seamlessly take advantage of thi !! 2542 bool
1742 2543
1743 config THUMB2_COMPAT_VDSO !! 2544 config SYS_SUPPORTS_MIPS16
1744 bool "Compile the 32-bit vDSO for Thu !! 2545 bool
1745 depends on COMPAT_VDSO <<
1746 default y <<
1747 help 2546 help
1748 Compile the compat vDSO with '-mthu !! 2547 This option must be set if a kernel might be executed on a MIPS16-
1749 otherwise with '-marm'. !! 2548 enabled CPU even if MIPS16 is not actually being used. In other
1750 !! 2549 words, it makes the kernel MIPS16-tolerant.
1751 config COMPAT_ALIGNMENT_FIXUPS <<
1752 bool "Fix up misaligned multi-word lo <<
1753 2550
1754 menuconfig ARMV8_DEPRECATED !! 2551 config CPU_SUPPORTS_MSA
1755 bool "Emulate deprecated/obsolete ARM !! 2552 bool
1756 depends on SYSCTL <<
1757 help <<
1758 Legacy software support may require <<
1759 that have been deprecated or obsole <<
1760 2553
1761 Enable this config to enable select !! 2554 config ARCH_FLATMEM_ENABLE
1762 features. !! 2555 def_bool y
>> 2556 depends on !NUMA && !CPU_LOONGSON2
1763 2557
1764 If unsure, say Y !! 2558 config ARCH_DISCONTIGMEM_ENABLE
>> 2559 bool
>> 2560 default y if SGI_IP27
>> 2561 help
>> 2562 Say Y to support efficient handling of discontiguous physical memory,
>> 2563 for architectures which are either NUMA (Non-Uniform Memory Access)
>> 2564 or have huge holes in the physical address space for other reasons.
>> 2565 See <file:Documentation/vm/numa> for more.
1765 2566
1766 if ARMV8_DEPRECATED !! 2567 config ARCH_SPARSEMEM_ENABLE
>> 2568 bool
>> 2569 select SPARSEMEM_STATIC
1767 2570
1768 config SWP_EMULATION !! 2571 config NUMA
1769 bool "Emulate SWP/SWPB instructions" !! 2572 bool "NUMA Support"
>> 2573 depends on SYS_SUPPORTS_NUMA
1770 help 2574 help
1771 ARMv8 obsoletes the use of A32 SWP/ !! 2575 Say Y to compile the kernel to support NUMA (Non-Uniform Memory
1772 they are always undefined. Say Y he !! 2576 Access). This option improves performance on systems with more
1773 emulation of these instructions for !! 2577 than two nodes; on two node systems it is generally better to
1774 This feature can be controlled at r !! 2578 leave it disabled; on single node systems disable this option
1775 sysctl which is disabled by default !! 2579 disabled.
1776 2580
1777 In some older versions of glibc [<= !! 2581 config SYS_SUPPORTS_NUMA
1778 trylock() operations with the assum !! 2582 bool
1779 be preempted. This invalid assumpti <<
1780 with SWP emulation enabled, leading <<
1781 application. <<
1782 2583
1783 NOTE: when accessing uncached share !! 2584 config RELOCATABLE
1784 on an external transaction monitori !! 2585 bool "Relocatable kernel"
1785 monitor to maintain update atomicit !! 2586 depends on SYS_SUPPORTS_RELOCATABLE && (CPU_MIPS32_R2 || CPU_MIPS64_R2 || CPU_MIPS32_R6 || CPU_MIPS64_R6 || CAVIUM_OCTEON_SOC)
1786 implement a global monitor, this op !! 2587 help
1787 perform SWP operations to uncached !! 2588 This builds a kernel image that retains relocation information
>> 2589 so it can be loaded someplace besides the default 1MB.
>> 2590 The relocations make the kernel binary about 15% larger,
>> 2591 but are discarded at runtime
>> 2592
>> 2593 config RELOCATION_TABLE_SIZE
>> 2594 hex "Relocation table size"
>> 2595 depends on RELOCATABLE
>> 2596 range 0x0 0x01000000
>> 2597 default "0x00100000"
>> 2598 ---help---
>> 2599 A table of relocation data will be appended to the kernel binary
>> 2600 and parsed at boot to fix up the relocated kernel.
1788 2601
1789 If unsure, say Y !! 2602 This option allows the amount of space reserved for the table to be
>> 2603 adjusted, although the default of 1Mb should be ok in most cases.
1790 2604
1791 config CP15_BARRIER_EMULATION !! 2605 The build will fail and a valid size suggested if this is too small.
1792 bool "Emulate CP15 Barrier instructio <<
1793 help <<
1794 The CP15 barrier instructions - CP1 <<
1795 CP15DMB - are deprecated in ARMv8 ( <<
1796 strongly recommended to use the ISB <<
1797 instructions instead. <<
1798 2606
1799 Say Y here to enable software emula !! 2607 If unsure, leave at the default value.
1800 instructions for AArch32 userspace <<
1801 enabled, CP15 barrier usage is trac <<
1802 identify software that needs updati <<
1803 controlled at runtime with the abi. <<
1804 2608
1805 If unsure, say Y !! 2609 config RANDOMIZE_BASE
>> 2610 bool "Randomize the address of the kernel image"
>> 2611 depends on RELOCATABLE
>> 2612 ---help---
>> 2613 Randomizes the physical and virtual address at which the
>> 2614 kernel image is loaded, as a security feature that
>> 2615 deters exploit attempts relying on knowledge of the location
>> 2616 of kernel internals.
1806 2617
1807 config SETEND_EMULATION !! 2618 Entropy is generated using any coprocessor 0 registers available.
1808 bool "Emulate SETEND instruction" <<
1809 help <<
1810 The SETEND instruction alters the d <<
1811 AArch32 EL0, and is deprecated in A <<
1812 2619
1813 Say Y here to enable software emula !! 2620 The kernel will be offset by up to RANDOMIZE_BASE_MAX_OFFSET.
1814 for AArch32 userspace code. This fe <<
1815 at runtime with the abi.setend sysc <<
1816 2621
1817 Note: All the cpus on the system mu !! 2622 If unsure, say N.
1818 for this feature to be enabled. If <<
1819 endian - is hotplugged in after thi <<
1820 be unexpected results in the applic <<
1821 2623
1822 If unsure, say Y !! 2624 config RANDOMIZE_BASE_MAX_OFFSET
1823 endif # ARMV8_DEPRECATED !! 2625 hex "Maximum kASLR offset" if EXPERT
>> 2626 depends on RANDOMIZE_BASE
>> 2627 range 0x0 0x40000000 if EVA || 64BIT
>> 2628 range 0x0 0x08000000
>> 2629 default "0x01000000"
>> 2630 ---help---
>> 2631 When kASLR is active, this provides the maximum offset that will
>> 2632 be applied to the kernel image. It should be set according to the
>> 2633 amount of physical RAM available in the target system minus
>> 2634 PHYSICAL_START and must be a power of 2.
1824 2635
1825 endif # COMPAT !! 2636 This is limited by the size of KSEG0, 256Mb on 32-bit or 1Gb with
>> 2637 EVA or 64-bit. The default is 16Mb.
1826 2638
1827 menu "ARMv8.1 architectural features" !! 2639 config NODES_SHIFT
>> 2640 int
>> 2641 default "6"
>> 2642 depends on NEED_MULTIPLE_NODES
1828 2643
1829 config ARM64_HW_AFDBM !! 2644 config HW_PERF_EVENTS
1830 bool "Support for hardware updates of !! 2645 bool "Enable hardware performance counter support for perf events"
>> 2646 depends on PERF_EVENTS && !OPROFILE && (CPU_MIPS32 || CPU_MIPS64 || CPU_R10000 || CPU_SB1 || CPU_CAVIUM_OCTEON || CPU_XLP || CPU_LOONGSON3)
1831 default y 2647 default y
1832 help 2648 help
1833 The ARMv8.1 architecture extensions !! 2649 Enable hardware performance counter support for perf events. If
1834 hardware updates of the access and !! 2650 disabled, perf events will use software events only.
1835 table entries. When enabled in TCR_ <<
1836 capable processors, accesses to pag <<
1837 set this bit instead of raising an <<
1838 Similarly, writes to read-only page <<
1839 clear the read-only bit (AP[2]) ins <<
1840 permission fault. <<
1841 2651
1842 Kernels built with this configurati !! 2652 source "mm/Kconfig"
1843 to work on pre-ARMv8.1 hardware and <<
1844 minimal. If unsure, say Y. <<
1845 2653
1846 config ARM64_PAN !! 2654 config SMP
1847 bool "Enable support for Privileged A !! 2655 bool "Multi-Processing support"
1848 default y !! 2656 depends on SYS_SUPPORTS_SMP
1849 help 2657 help
1850 Privileged Access Never (PAN; part !! 2658 This enables support for systems with more than one CPU. If you have
1851 prevents the kernel or hypervisor f !! 2659 a system with only one CPU, say N. If you have a system with more
1852 memory directly. !! 2660 than one CPU, say Y.
1853 !! 2661
1854 Choosing this option will cause any !! 2662 If you say N here, the kernel will run on uni- and multiprocessor
1855 copy_to_user et al) memory access t !! 2663 machines, but will use only one CPU of a multiprocessor machine. If
>> 2664 you say Y here, the kernel will run on many, but not all,
>> 2665 uniprocessor machines. On a uniprocessor machine, the kernel
>> 2666 will run faster if you say N here.
1856 2667
1857 The feature is detected at runtime, !! 2668 People using multiprocessor machines who say Y here should also say
1858 instruction if the cpu does not imp !! 2669 Y to "Enhanced Real Time Clock Support", below.
1859 2670
1860 config AS_HAS_LSE_ATOMICS !! 2671 See also the SMP-HOWTO available at
1861 def_bool $(as-instr,.arch_extension l !! 2672 <http://www.tldp.org/docs.html#howto>.
1862 2673
1863 config ARM64_LSE_ATOMICS !! 2674 If you don't know what to do here, say N.
1864 bool <<
1865 default ARM64_USE_LSE_ATOMICS <<
1866 depends on AS_HAS_LSE_ATOMICS <<
1867 2675
1868 config ARM64_USE_LSE_ATOMICS !! 2676 config HOTPLUG_CPU
1869 bool "Atomic instructions" !! 2677 bool "Support for hot-pluggable CPUs"
1870 default y !! 2678 depends on SMP && SYS_SUPPORTS_HOTPLUG_CPU
1871 help 2679 help
1872 As part of the Large System Extensi !! 2680 Say Y here to allow turning CPUs off and on. CPUs can be
1873 atomic instructions that are design !! 2681 controlled through /sys/devices/system/cpu.
1874 very large systems. !! 2682 (Note: power management support will enable this option
1875 !! 2683 automatically on SMP systems. )
1876 Say Y here to make use of these ins !! 2684 Say N if you want to disable CPU hotplug.
1877 atomic routines. This incurs a smal <<
1878 not support these instructions and <<
1879 built with binutils >= 2.25 in orde <<
1880 to be used. <<
1881 <<
1882 endmenu # "ARMv8.1 architectural features" <<
1883 2685
1884 menu "ARMv8.2 architectural features" !! 2686 config SMP_UP
>> 2687 bool
1885 2688
1886 config AS_HAS_ARMV8_2 !! 2689 config SYS_SUPPORTS_MIPS_CMP
1887 def_bool $(cc-option,-Wa$(comma)-marc !! 2690 bool
1888 2691
1889 config AS_HAS_SHA3 !! 2692 config SYS_SUPPORTS_MIPS_CPS
1890 def_bool $(as-instr,.arch armv8.2-a+s !! 2693 bool
1891 2694
1892 config ARM64_PMEM !! 2695 config SYS_SUPPORTS_SMP
1893 bool "Enable support for persistent m !! 2696 bool
1894 select ARCH_HAS_PMEM_API <<
1895 select ARCH_HAS_UACCESS_FLUSHCACHE <<
1896 help <<
1897 Say Y to enable support for the per <<
1898 ARMv8.2 DCPoP feature. <<
1899 2697
1900 The feature is detected at runtime, !! 2698 config NR_CPUS_DEFAULT_4
1901 operations if DC CVAP is not suppor !! 2699 bool
1902 DC CVAP itself if the system does n <<
1903 2700
1904 config ARM64_RAS_EXTN !! 2701 config NR_CPUS_DEFAULT_8
1905 bool "Enable support for RAS CPU Exte !! 2702 bool
1906 default y <<
1907 help <<
1908 CPUs that support the Reliability, <<
1909 (RAS) Extensions, part of ARMv8.2 a <<
1910 errors, classify them and report th <<
1911 2703
1912 On CPUs with these extensions syste !! 2704 config NR_CPUS_DEFAULT_16
1913 barriers to determine if faults are !! 2705 bool
1914 classification from a new set of re <<
1915 2706
1916 Selecting this feature will allow t !! 2707 config NR_CPUS_DEFAULT_32
1917 and access the new registers if the !! 2708 bool
1918 Platform RAS features may additiona <<
1919 2709
1920 config ARM64_CNP !! 2710 config NR_CPUS_DEFAULT_64
1921 bool "Enable support for Common Not P !! 2711 bool
1922 default y <<
1923 depends on ARM64_PAN || !ARM64_SW_TTB <<
1924 help <<
1925 Common Not Private (CNP) allows tra <<
1926 be shared between different PEs in <<
1927 domain, so the hardware can use thi <<
1928 caching of such entries in the TLB. <<
1929 2712
1930 Selecting this option allows the CN !! 2713 config NR_CPUS
1931 at runtime, and does not affect PEs !! 2714 int "Maximum number of CPUs (2-256)"
1932 this feature. !! 2715 range 2 256
>> 2716 depends on SMP
>> 2717 default "4" if NR_CPUS_DEFAULT_4
>> 2718 default "8" if NR_CPUS_DEFAULT_8
>> 2719 default "16" if NR_CPUS_DEFAULT_16
>> 2720 default "32" if NR_CPUS_DEFAULT_32
>> 2721 default "64" if NR_CPUS_DEFAULT_64
>> 2722 help
>> 2723 This allows you to specify the maximum number of CPUs which this
>> 2724 kernel will support. The maximum supported value is 32 for 32-bit
>> 2725 kernel and 64 for 64-bit kernels; the minimum value which makes
>> 2726 sense is 1 for Qemu (useful only for kernel debugging purposes)
>> 2727 and 2 for all others.
>> 2728
>> 2729 This is purely to save memory - each supported CPU adds
>> 2730 approximately eight kilobytes to the kernel image. For best
>> 2731 performance should round up your number of processors to the next
>> 2732 power of two.
1933 2733
1934 endmenu # "ARMv8.2 architectural features" !! 2734 config MIPS_PERF_SHARED_TC_COUNTERS
>> 2735 bool
1935 2736
1936 menu "ARMv8.3 architectural features" !! 2737 #
>> 2738 # Timer Interrupt Frequency Configuration
>> 2739 #
1937 2740
1938 config ARM64_PTR_AUTH !! 2741 choice
1939 bool "Enable support for pointer auth !! 2742 prompt "Timer frequency"
1940 default y !! 2743 default HZ_250
1941 help 2744 help
1942 Pointer authentication (part of the !! 2745 Allows the configuration of the timer frequency.
1943 instructions for signing and authen <<
1944 keys, which can be used to mitigate <<
1945 and other attacks. <<
1946 2746
1947 This option enables these instructi !! 2747 config HZ_24
1948 Choosing this option will cause the !! 2748 bool "24 HZ" if SYS_SUPPORTS_24HZ || SYS_SUPPORTS_ARBIT_HZ
1949 for each process at exec() time, wi <<
1950 context-switched along with the pro <<
1951 2749
1952 The feature is detected at runtime. !! 2750 config HZ_48
1953 hardware it will not be advertised !! 2751 bool "48 HZ" if SYS_SUPPORTS_48HZ || SYS_SUPPORTS_ARBIT_HZ
1954 be enabled. <<
1955 2752
1956 If the feature is present on the bo !! 2753 config HZ_100
1957 the late CPU will be parked. Also, !! 2754 bool "100 HZ" if SYS_SUPPORTS_100HZ || SYS_SUPPORTS_ARBIT_HZ
1958 address auth and the late CPU has t <<
1959 but with the feature disabled. On s <<
1960 not be selected. <<
1961 2755
1962 config ARM64_PTR_AUTH_KERNEL !! 2756 config HZ_128
1963 bool "Use pointer authentication for !! 2757 bool "128 HZ" if SYS_SUPPORTS_128HZ || SYS_SUPPORTS_ARBIT_HZ
1964 default y <<
1965 depends on ARM64_PTR_AUTH <<
1966 depends on (CC_HAS_SIGN_RETURN_ADDRES <<
1967 # Modern compilers insert a .note.gnu <<
1968 # which is only understood by binutil <<
1969 depends on LD_IS_LLD || LD_VERSION >= <<
1970 depends on !CC_IS_CLANG || AS_HAS_CFI <<
1971 depends on (!FUNCTION_GRAPH_TRACER || <<
1972 help <<
1973 If the compiler supports the -mbran <<
1974 -msign-return-address flag (e.g. GC <<
1975 will cause the kernel itself to be <<
1976 protection. In this case, and if th <<
1977 support pointer authentication, the <<
1978 disabled with minimal loss of prote <<
1979 2758
1980 This feature works with FUNCTION_GR !! 2759 config HZ_250
1981 DYNAMIC_FTRACE_WITH_ARGS is enabled !! 2760 bool "250 HZ" if SYS_SUPPORTS_250HZ || SYS_SUPPORTS_ARBIT_HZ
1982 2761
1983 config CC_HAS_BRANCH_PROT_PAC_RET !! 2762 config HZ_256
1984 # GCC 9 or later, clang 8 or later !! 2763 bool "256 HZ" if SYS_SUPPORTS_256HZ || SYS_SUPPORTS_ARBIT_HZ
1985 def_bool $(cc-option,-mbranch-protect <<
1986 2764
1987 config CC_HAS_SIGN_RETURN_ADDRESS !! 2765 config HZ_1000
1988 # GCC 7, 8 !! 2766 bool "1000 HZ" if SYS_SUPPORTS_1000HZ || SYS_SUPPORTS_ARBIT_HZ
1989 def_bool $(cc-option,-msign-return-ad <<
1990 2767
1991 config AS_HAS_ARMV8_3 !! 2768 config HZ_1024
1992 def_bool $(cc-option,-Wa$(comma)-marc !! 2769 bool "1024 HZ" if SYS_SUPPORTS_1024HZ || SYS_SUPPORTS_ARBIT_HZ
1993 2770
1994 config AS_HAS_CFI_NEGATE_RA_STATE !! 2771 endchoice
1995 def_bool $(as-instr,.cfi_startproc\n. <<
1996 2772
1997 config AS_HAS_LDAPR !! 2773 config SYS_SUPPORTS_24HZ
1998 def_bool $(as-instr,.arch_extension r !! 2774 bool
1999 2775
2000 endmenu # "ARMv8.3 architectural features" !! 2776 config SYS_SUPPORTS_48HZ
>> 2777 bool
2001 2778
2002 menu "ARMv8.4 architectural features" !! 2779 config SYS_SUPPORTS_100HZ
>> 2780 bool
2003 2781
2004 config ARM64_AMU_EXTN !! 2782 config SYS_SUPPORTS_128HZ
2005 bool "Enable support for the Activity !! 2783 bool
2006 default y <<
2007 help <<
2008 The activity monitors extension is <<
2009 by the ARMv8.4 CPU architecture. Th <<
2010 of the activity monitors architectu <<
2011 2784
2012 To enable the use of this extension !! 2785 config SYS_SUPPORTS_250HZ
>> 2786 bool
2013 2787
2014 Note that for architectural reasons !! 2788 config SYS_SUPPORTS_256HZ
2015 support when running on CPUs that p !! 2789 bool
2016 extension. The required support is <<
2017 * Version 1.5 and later of the AR <<
2018 2790
2019 For kernels that have this configur !! 2791 config SYS_SUPPORTS_1000HZ
2020 firmware, you may need to say N her !! 2792 bool
2021 Otherwise you may experience firmwa <<
2022 accessing the counter registers. Ev <<
2023 symptoms, the values returned by th <<
2024 correctly reflect reality. Most com <<
2025 indicating that the counter is not <<
2026 2793
2027 config AS_HAS_ARMV8_4 !! 2794 config SYS_SUPPORTS_1024HZ
2028 def_bool $(cc-option,-Wa$(comma)-marc !! 2795 bool
2029 2796
2030 config ARM64_TLB_RANGE !! 2797 config SYS_SUPPORTS_ARBIT_HZ
2031 bool "Enable support for tlbi range f !! 2798 bool
2032 default y !! 2799 default y if !SYS_SUPPORTS_24HZ && \
2033 depends on AS_HAS_ARMV8_4 !! 2800 !SYS_SUPPORTS_48HZ && \
2034 help !! 2801 !SYS_SUPPORTS_100HZ && \
2035 ARMv8.4-TLBI provides TLBI invalida !! 2802 !SYS_SUPPORTS_128HZ && \
2036 range of input addresses. !! 2803 !SYS_SUPPORTS_250HZ && \
>> 2804 !SYS_SUPPORTS_256HZ && \
>> 2805 !SYS_SUPPORTS_1000HZ && \
>> 2806 !SYS_SUPPORTS_1024HZ
2037 2807
2038 The feature introduces new assembly !! 2808 config HZ
2039 support when binutils >= 2.30. !! 2809 int
>> 2810 default 24 if HZ_24
>> 2811 default 48 if HZ_48
>> 2812 default 100 if HZ_100
>> 2813 default 128 if HZ_128
>> 2814 default 250 if HZ_250
>> 2815 default 256 if HZ_256
>> 2816 default 1000 if HZ_1000
>> 2817 default 1024 if HZ_1024
>> 2818
>> 2819 config SCHED_HRTICK
>> 2820 def_bool HIGH_RES_TIMERS
>> 2821
>> 2822 source "kernel/Kconfig.preempt"
>> 2823
>> 2824 config KEXEC
>> 2825 bool "Kexec system call"
>> 2826 select KEXEC_CORE
>> 2827 help
>> 2828 kexec is a system call that implements the ability to shutdown your
>> 2829 current kernel, and to start another kernel. It is like a reboot
>> 2830 but it is independent of the system firmware. And like a reboot
>> 2831 you can start any kernel with it, not just Linux.
>> 2832
>> 2833 The name comes from the similarity to the exec system call.
>> 2834
>> 2835 It is an ongoing process to be certain the hardware in a machine
>> 2836 is properly shutdown, so do not be surprised if this code does not
>> 2837 initially work for you. As of this writing the exact hardware
>> 2838 interface is strongly in flux, so no good recommendation can be
>> 2839 made.
>> 2840
>> 2841 config CRASH_DUMP
>> 2842 bool "Kernel crash dumps"
>> 2843 help
>> 2844 Generate crash dump after being started by kexec.
>> 2845 This should be normally only set in special crash dump kernels
>> 2846 which are loaded in the main kernel with kexec-tools into
>> 2847 a specially reserved region and then later executed after
>> 2848 a crash by kdump/kexec. The crash dump kernel must be compiled
>> 2849 to a memory address not used by the main kernel or firmware using
>> 2850 PHYSICAL_START.
>> 2851
>> 2852 config PHYSICAL_START
>> 2853 hex "Physical address where the kernel is loaded"
>> 2854 default "0xffffffff84000000" if 64BIT
>> 2855 default "0x84000000" if 32BIT
>> 2856 depends on CRASH_DUMP
>> 2857 help
>> 2858 This gives the CKSEG0 or KSEG0 address where the kernel is loaded.
>> 2859 If you plan to use kernel for capturing the crash dump change
>> 2860 this value to start of the reserved region (the "X" value as
>> 2861 specified in the "crashkernel=YM@XM" command line boot parameter
>> 2862 passed to the panic-ed kernel).
>> 2863
>> 2864 config SECCOMP
>> 2865 bool "Enable seccomp to safely compute untrusted bytecode"
>> 2866 depends on PROC_FS
>> 2867 default y
>> 2868 help
>> 2869 This kernel feature is useful for number crunching applications
>> 2870 that may need to compute untrusted bytecode during their
>> 2871 execution. By using pipes or other transports made available to
>> 2872 the process as file descriptors supporting the read/write
>> 2873 syscalls, it's possible to isolate those applications in
>> 2874 their own address space using seccomp. Once seccomp is
>> 2875 enabled via /proc/<pid>/seccomp, it cannot be disabled
>> 2876 and the task is only allowed to execute a few safe syscalls
>> 2877 defined by each seccomp mode.
>> 2878
>> 2879 If unsure, say Y. Only embedded should say N here.
>> 2880
>> 2881 config MIPS_O32_FP64_SUPPORT
>> 2882 bool "Support for O32 binaries using 64-bit FP"
>> 2883 depends on 32BIT || MIPS32_O32
>> 2884 help
>> 2885 When this is enabled, the kernel will support use of 64-bit floating
>> 2886 point registers with binaries using the O32 ABI along with the
>> 2887 EF_MIPS_FP64 ELF header flag (typically built with -mfp64). On
>> 2888 32-bit MIPS systems this support is at the cost of increasing the
>> 2889 size and complexity of the compiled FPU emulator. Thus if you are
>> 2890 running a MIPS32 system and know that none of your userland binaries
>> 2891 will require 64-bit floating point, you may wish to reduce the size
>> 2892 of your kernel & potentially improve FP emulation performance by
>> 2893 saying N here.
>> 2894
>> 2895 Although binutils currently supports use of this flag the details
>> 2896 concerning its effect upon the O32 ABI in userland are still being
>> 2897 worked on. In order to avoid userland becoming dependant upon current
>> 2898 behaviour before the details have been finalised, this option should
>> 2899 be considered experimental and only enabled by those working upon
>> 2900 said details.
2040 2901
2041 endmenu # "ARMv8.4 architectural features" !! 2902 If unsure, say N.
2042 2903
2043 menu "ARMv8.5 architectural features" !! 2904 config USE_OF
>> 2905 bool
>> 2906 select OF
>> 2907 select OF_EARLY_FLATTREE
>> 2908 select IRQ_DOMAIN
2044 2909
2045 config AS_HAS_ARMV8_5 !! 2910 config BUILTIN_DTB
2046 def_bool $(cc-option,-Wa$(comma)-marc !! 2911 bool
2047 2912
2048 config ARM64_BTI !! 2913 choice
2049 bool "Branch Target Identification su !! 2914 prompt "Kernel appended dtb support" if USE_OF
2050 default y !! 2915 default MIPS_NO_APPENDED_DTB
2051 help <<
2052 Branch Target Identification (part <<
2053 provides a mechanism to limit the s <<
2054 branch instructions such as BR or B <<
2055 2916
2056 To make use of BTI on CPUs that sup !! 2917 config MIPS_NO_APPENDED_DTB
>> 2918 bool "None"
>> 2919 help
>> 2920 Do not enable appended dtb support.
>> 2921
>> 2922 config MIPS_ELF_APPENDED_DTB
>> 2923 bool "vmlinux"
>> 2924 help
>> 2925 With this option, the boot code will look for a device tree binary
>> 2926 DTB) included in the vmlinux ELF section .appended_dtb. By default
>> 2927 it is empty and the DTB can be appended using binutils command
>> 2928 objcopy:
>> 2929
>> 2930 objcopy --update-section .appended_dtb=<filename>.dtb vmlinux
>> 2931
>> 2932 This is meant as a backward compatiblity convenience for those
>> 2933 systems with a bootloader that can't be upgraded to accommodate
>> 2934 the documented boot protocol using a device tree.
>> 2935
>> 2936 config MIPS_RAW_APPENDED_DTB
>> 2937 bool "vmlinux.bin or vmlinuz.bin"
>> 2938 help
>> 2939 With this option, the boot code will look for a device tree binary
>> 2940 DTB) appended to raw vmlinux.bin or vmlinuz.bin.
>> 2941 (e.g. cat vmlinux.bin <filename>.dtb > vmlinux_w_dtb).
>> 2942
>> 2943 This is meant as a backward compatibility convenience for those
>> 2944 systems with a bootloader that can't be upgraded to accommodate
>> 2945 the documented boot protocol using a device tree.
>> 2946
>> 2947 Beware that there is very little in terms of protection against
>> 2948 this option being confused by leftover garbage in memory that might
>> 2949 look like a DTB header after a reboot if no actual DTB is appended
>> 2950 to vmlinux.bin. Do not leave this option active in a production kernel
>> 2951 if you don't intend to always append a DTB.
>> 2952 endchoice
2057 2953
2058 BTI is intended to provide compleme !! 2954 choice
2059 flow integrity protection mechanism !! 2955 prompt "Kernel command line type" if !CMDLINE_OVERRIDE
2060 authentication mechanism provided a !! 2956 default MIPS_CMDLINE_FROM_DTB if USE_OF && !ATH79 && !MACH_INGENIC && \
2061 For this reason, it does not make s !! 2957 !MIPS_MALTA && \
2062 also enabling support for pointer a !! 2958 !CAVIUM_OCTEON_SOC
2063 enabling this option you should als !! 2959 default MIPS_CMDLINE_FROM_BOOTLOADER
>> 2960
>> 2961 config MIPS_CMDLINE_FROM_DTB
>> 2962 depends on USE_OF
>> 2963 bool "Dtb kernel arguments if available"
>> 2964
>> 2965 config MIPS_CMDLINE_DTB_EXTEND
>> 2966 depends on USE_OF
>> 2967 bool "Extend dtb kernel arguments with bootloader arguments"
>> 2968
>> 2969 config MIPS_CMDLINE_FROM_BOOTLOADER
>> 2970 bool "Bootloader kernel arguments if available"
>> 2971
>> 2972 config MIPS_CMDLINE_BUILTIN_EXTEND
>> 2973 depends on CMDLINE_BOOL
>> 2974 bool "Extend builtin kernel arguments with bootloader arguments"
>> 2975 endchoice
2064 2976
2065 Userspace binaries must also be spe !! 2977 endmenu
2066 this mechanism. If you say N here <<
2067 BTI, such binaries can still run, b <<
2068 enforcement of branch destinations. <<
2069 2978
2070 config ARM64_BTI_KERNEL !! 2979 config LOCKDEP_SUPPORT
2071 bool "Use Branch Target Identificatio !! 2980 bool
2072 default y 2981 default y
2073 depends on ARM64_BTI <<
2074 depends on ARM64_PTR_AUTH_KERNEL <<
2075 depends on CC_HAS_BRANCH_PROT_PAC_RET <<
2076 # https://gcc.gnu.org/bugzilla/show_b <<
2077 depends on !CC_IS_GCC || GCC_VERSION <<
2078 # https://gcc.gnu.org/bugzilla/show_b <<
2079 depends on !CC_IS_GCC <<
2080 depends on (!FUNCTION_GRAPH_TRACER || <<
2081 help <<
2082 Build the kernel with Branch Target <<
2083 and enable enforcement of this for <<
2084 is enabled and the system supports <<
2085 modular code must have BTI enabled. <<
2086 2982
2087 config CC_HAS_BRANCH_PROT_PAC_RET_BTI !! 2983 config STACKTRACE_SUPPORT
2088 # GCC 9 or later, clang 8 or later !! 2984 bool
2089 def_bool $(cc-option,-mbranch-protect <<
2090 <<
2091 config ARM64_E0PD <<
2092 bool "Enable support for E0PD" <<
2093 default y 2985 default y
2094 help <<
2095 E0PD (part of the ARMv8.5 extension <<
2096 that EL0 accesses made via TTBR1 al <<
2097 providing similar benefits to KASLR <<
2098 with lower overhead and without dis <<
2099 kernel memory such as SPE. <<
2100 <<
2101 This option enables E0PD for TTBR1 <<
2102 <<
2103 config ARM64_AS_HAS_MTE <<
2104 # Initial support for MTE went in bin <<
2105 # ".arch armv8.5-a+memtag" below. How <<
2106 # as a late addition to the final arc <<
2107 # is only supported in the newer 2.32 <<
2108 # versions, hence the extra "stgm" in <<
2109 def_bool $(as-instr,.arch armv8.5-a+m <<
2110 2986
2111 config ARM64_MTE !! 2987 config HAVE_LATENCYTOP_SUPPORT
2112 bool "Memory Tagging Extension suppor !! 2988 bool
2113 default y 2989 default y
2114 depends on ARM64_AS_HAS_MTE && ARM64_ <<
2115 depends on AS_HAS_ARMV8_5 <<
2116 depends on AS_HAS_LSE_ATOMICS <<
2117 # Required for tag checking in the ua <<
2118 depends on ARM64_PAN <<
2119 select ARCH_HAS_SUBPAGE_FAULTS <<
2120 select ARCH_USES_HIGH_VMA_FLAGS <<
2121 select ARCH_USES_PG_ARCH_2 <<
2122 select ARCH_USES_PG_ARCH_3 <<
2123 help <<
2124 Memory Tagging (part of the ARMv8.5 <<
2125 architectural support for run-time, <<
2126 various classes of memory error to <<
2127 to eliminate vulnerabilities arisin <<
2128 languages. <<
2129 2990
2130 This option enables the support for !! 2991 config PGTABLE_LEVELS
2131 Extension at EL0 (i.e. for userspac !! 2992 int
>> 2993 default 4 if PAGE_SIZE_4KB && MIPS_VA_BITS_48
>> 2994 default 3 if 64BIT && (!PAGE_SIZE_64KB || MIPS_VA_BITS_48)
>> 2995 default 2
2132 2996
2133 Selecting this option allows the fe !! 2997 source "init/Kconfig"
2134 runtime. Any secondary CPU not impl <<
2135 not be allowed a late bring-up. <<
2136 2998
2137 Userspace binaries that want to use !! 2999 source "kernel/Kconfig.freezer"
2138 explicitly opt in. The mechanism fo <<
2139 described in: <<
2140 3000
2141 Documentation/arch/arm64/memory-tag !! 3001 menu "Bus options (PCI, PCMCIA, EISA, ISA, TC)"
2142 3002
2143 endmenu # "ARMv8.5 architectural features" !! 3003 config HW_HAS_EISA
>> 3004 bool
>> 3005 config HW_HAS_PCI
>> 3006 bool
2144 3007
2145 menu "ARMv8.7 architectural features" !! 3008 config PCI
>> 3009 bool "Support for PCI controller"
>> 3010 depends on HW_HAS_PCI
>> 3011 select PCI_DOMAINS
>> 3012 help
>> 3013 Find out whether you have a PCI motherboard. PCI is the name of a
>> 3014 bus system, i.e. the way the CPU talks to the other stuff inside
>> 3015 your box. Other bus systems are ISA, EISA, or VESA. If you have PCI,
>> 3016 say Y, otherwise N.
>> 3017
>> 3018 config HT_PCI
>> 3019 bool "Support for HT-linked PCI"
>> 3020 default y
>> 3021 depends on CPU_LOONGSON3
>> 3022 select PCI
>> 3023 select PCI_DOMAINS
>> 3024 help
>> 3025 Loongson family machines use Hyper-Transport bus for inter-core
>> 3026 connection and device connection. The PCI bus is a subordinate
>> 3027 linked at HT. Choose Y for Loongson-3 based machines.
2146 3028
2147 config ARM64_EPAN !! 3029 config PCI_DOMAINS
2148 bool "Enable support for Enhanced Pri !! 3030 bool
2149 default y <<
2150 depends on ARM64_PAN <<
2151 help <<
2152 Enhanced Privileged Access Never (E <<
2153 Access Never to be used with Execut <<
2154 <<
2155 The feature is detected at runtime, <<
2156 if the cpu does not implement the f <<
2157 endmenu # "ARMv8.7 architectural features" <<
2158 3031
2159 menu "ARMv8.9 architectural features" !! 3032 config PCI_DOMAINS_GENERIC
>> 3033 bool
2160 3034
2161 config ARM64_POE !! 3035 config PCI_DRIVERS_GENERIC
2162 prompt "Permission Overlay Extension" !! 3036 select PCI_DOMAINS_GENERIC if PCI_DOMAINS
2163 def_bool y !! 3037 bool
2164 select ARCH_USES_HIGH_VMA_FLAGS <<
2165 select ARCH_HAS_PKEYS <<
2166 help <<
2167 The Permission Overlay Extension is <<
2168 Protection Keys. Memory Protection <<
2169 enforcing page-based protections, b <<
2170 of the page tables when an applicat <<
2171 3038
2172 For details, see Documentation/core !! 3039 config PCI_DRIVERS_LEGACY
>> 3040 def_bool !PCI_DRIVERS_GENERIC
>> 3041 select NO_GENERIC_PCI_IOPORT_MAP
2173 3042
2174 If unsure, say y. !! 3043 source "drivers/pci/Kconfig"
2175 3044
2176 config ARCH_PKEY_BITS !! 3045 #
2177 int !! 3046 # ISA support is now enabled via select. Too many systems still have the one
2178 default 3 !! 3047 # or other ISA chip on the board that users don't know about so don't expect
>> 3048 # users to choose the right thing ...
>> 3049 #
>> 3050 config ISA
>> 3051 bool
2179 3052
2180 endmenu # "ARMv8.9 architectural features" !! 3053 config EISA
>> 3054 bool "EISA support"
>> 3055 depends on HW_HAS_EISA
>> 3056 select ISA
>> 3057 select GENERIC_ISA_DMA
>> 3058 ---help---
>> 3059 The Extended Industry Standard Architecture (EISA) bus was
>> 3060 developed as an open alternative to the IBM MicroChannel bus.
>> 3061
>> 3062 The EISA bus provided some of the features of the IBM MicroChannel
>> 3063 bus while maintaining backward compatibility with cards made for
>> 3064 the older ISA bus. The EISA bus saw limited use between 1988 and
>> 3065 1995 when it was made obsolete by the PCI bus.
>> 3066
>> 3067 Say Y here if you are building a kernel for an EISA-based machine.
>> 3068
>> 3069 Otherwise, say N.
>> 3070
>> 3071 source "drivers/eisa/Kconfig"
>> 3072
>> 3073 config TC
>> 3074 bool "TURBOchannel support"
>> 3075 depends on MACH_DECSTATION
>> 3076 help
>> 3077 TURBOchannel is a DEC (now Compaq (now HP)) bus for Alpha and MIPS
>> 3078 processors. TURBOchannel programming specifications are available
>> 3079 at:
>> 3080 <ftp://ftp.hp.com/pub/alphaserver/archive/triadd/>
>> 3081 and:
>> 3082 <http://www.computer-refuge.org/classiccmp/ftp.digital.com/pub/DEC/TriAdd/>
>> 3083 Linux driver support status is documented at:
>> 3084 <http://www.linux-mips.org/wiki/DECstation>
2181 3085
2182 config ARM64_SVE !! 3086 config MMU
2183 bool "ARM Scalable Vector Extension s !! 3087 bool
2184 default y 3088 default y
2185 help <<
2186 The Scalable Vector Extension (SVE) <<
2187 execution state which complements a <<
2188 of the base architecture to support <<
2189 additional vectorisation opportunit <<
2190 <<
2191 To enable use of this extension on <<
2192 <<
2193 On CPUs that support the SVE2 exten <<
2194 those too. <<
2195 <<
2196 Note that for architectural reasons <<
2197 support when running on SVE capable <<
2198 is present in: <<
2199 3089
2200 * version 1.5 and later of the AR !! 3090 config ARCH_MMAP_RND_BITS_MIN
2201 * the AArch64 boot wrapper since !! 3091 default 12 if 64BIT
2202 ("bootwrapper: SVE: Enable SVE !! 3092 default 8
2203 <<
2204 For other firmware implementations, <<
2205 or vendor. <<
2206 <<
2207 If you need the kernel to boot on S <<
2208 firmware, you may need to say N her <<
2209 fixed. Otherwise, you may experien <<
2210 booting the kernel. If unsure and <<
2211 symptoms, you should assume that it <<
2212 3093
2213 config ARM64_SME !! 3094 config ARCH_MMAP_RND_BITS_MAX
2214 bool "ARM Scalable Matrix Extension s !! 3095 default 18 if 64BIT
2215 default y !! 3096 default 15
2216 depends on ARM64_SVE <<
2217 depends on BROKEN <<
2218 help <<
2219 The Scalable Matrix Extension (SME) <<
2220 execution state which utilises a su <<
2221 instruction set, together with the <<
2222 register state capable of holding t <<
2223 enable various matrix operations. <<
2224 3097
2225 config ARM64_PSEUDO_NMI !! 3098 config ARCH_MMAP_RND_COMPAT_BITS_MIN
2226 bool "Support for NMI-like interrupts !! 3099 default 8
2227 select ARM_GIC_V3 <<
2228 help <<
2229 Adds support for mimicking Non-Mask <<
2230 GIC interrupt priority. This suppor <<
2231 ARM GIC. <<
2232 3100
2233 This high priority configuration fo !! 3101 config ARCH_MMAP_RND_COMPAT_BITS_MAX
2234 explicitly enabled by setting the k !! 3102 default 15
2235 "irqchip.gicv3_pseudo_nmi" to 1. <<
2236 3103
2237 If unsure, say N !! 3104 config I8253
>> 3105 bool
>> 3106 select CLKSRC_I8253
>> 3107 select CLKEVT_I8253
>> 3108 select MIPS_EXTERNAL_TIMER
2238 3109
2239 if ARM64_PSEUDO_NMI !! 3110 config ZONE_DMA
2240 config ARM64_DEBUG_PRIORITY_MASKING !! 3111 bool
2241 bool "Debug interrupt priority maskin <<
2242 help <<
2243 This adds runtime checks to functio <<
2244 interrupts when using priority mask <<
2245 the validity of ICC_PMR_EL1 when ca <<
2246 3112
2247 If unsure, say N !! 3113 config ZONE_DMA32
2248 endif # ARM64_PSEUDO_NMI !! 3114 bool
2249 3115
2250 config RELOCATABLE !! 3116 source "drivers/pcmcia/Kconfig"
2251 bool "Build a relocatable kernel imag <<
2252 select ARCH_HAS_RELR <<
2253 default y <<
2254 help <<
2255 This builds the kernel as a Positio <<
2256 which retains all relocation metada <<
2257 kernel binary at runtime to a diffe <<
2258 address it was linked at. <<
2259 Since AArch64 uses the RELA relocat <<
2260 relocation pass at runtime even if <<
2261 same address it was linked at. <<
2262 3117
2263 config RANDOMIZE_BASE !! 3118 config RAPIDIO
2264 bool "Randomize the address of the ke !! 3119 tristate "RapidIO support"
2265 select RELOCATABLE !! 3120 depends on PCI
>> 3121 default n
2266 help 3122 help
2267 Randomizes the virtual address at w !! 3123 If you say Y here, the kernel will include drivers and
2268 loaded, as a security feature that !! 3124 infrastructure code to support RapidIO interconnect devices.
2269 relying on knowledge of the locatio <<
2270 <<
2271 It is the bootloader's job to provi <<
2272 random u64 value in /chosen/kaslr-s <<
2273 <<
2274 When booting via the UEFI stub, it <<
2275 EFI_RNG_PROTOCOL implementation (if <<
2276 to the kernel proper. In addition, <<
2277 location of the kernel Image as wel <<
2278 3125
2279 If unsure, say N. !! 3126 source "drivers/rapidio/Kconfig"
2280 3127
2281 config RANDOMIZE_MODULE_REGION_FULL !! 3128 endmenu
2282 bool "Randomize the module region ove <<
2283 depends on RANDOMIZE_BASE <<
2284 default y <<
2285 help <<
2286 Randomizes the location of the modu <<
2287 covering the core kernel. This way, <<
2288 to leak information about the locat <<
2289 but it does imply that function cal <<
2290 kernel will need to be resolved via <<
2291 <<
2292 When this option is not set, the mo <<
2293 a limited range that contains the [ <<
2294 core kernel, so branch relocations <<
2295 the region is exhausted. In this pa <<
2296 exhaustion, modules might be able t <<
2297 3129
2298 config CC_HAVE_STACKPROTECTOR_SYSREG !! 3130 menu "Executable file formats"
2299 def_bool $(cc-option,-mstack-protecto <<
2300 3131
2301 config STACKPROTECTOR_PER_TASK !! 3132 source "fs/Kconfig.binfmt"
2302 def_bool y <<
2303 depends on STACKPROTECTOR && CC_HAVE_ <<
2304 3133
2305 config UNWIND_PATCH_PAC_INTO_SCS !! 3134 config TRAD_SIGNALS
2306 bool "Enable shadow call stack dynami !! 3135 bool
2307 # needs Clang with https://github.com <<
2308 depends on CC_IS_CLANG && CLANG_VERSI <<
2309 depends on ARM64_PTR_AUTH_KERNEL && C <<
2310 depends on SHADOW_CALL_STACK <<
2311 select UNWIND_TABLES <<
2312 select DYNAMIC_SCS <<
2313 <<
2314 config ARM64_CONTPTE <<
2315 bool "Contiguous PTE mappings for use <<
2316 depends on TRANSPARENT_HUGEPAGE <<
2317 default y <<
2318 help <<
2319 When enabled, user mappings are con <<
2320 bit, for any mappings that meet the <<
2321 This reduces TLB pressure and impro <<
2322 <<
2323 endmenu # "Kernel Features" <<
2324 <<
2325 menu "Boot options" <<
2326 <<
2327 config ARM64_ACPI_PARKING_PROTOCOL <<
2328 bool "Enable support for the ARM64 AC <<
2329 depends on ACPI <<
2330 help <<
2331 Enable support for the ARM64 ACPI p <<
2332 the kernel will not allow booting t <<
2333 protocol even if the corresponding <<
2334 MADT table. <<
2335 <<
2336 config CMDLINE <<
2337 string "Default kernel command string <<
2338 default "" <<
2339 help <<
2340 Provide a set of default command-li <<
2341 entering them here. As a minimum, y <<
2342 root device (e.g. root=/dev/nfs). <<
2343 3136
2344 choice !! 3137 config MIPS32_COMPAT
2345 prompt "Kernel command line type" !! 3138 bool
2346 depends on CMDLINE != "" <<
2347 default CMDLINE_FROM_BOOTLOADER <<
2348 help <<
2349 Choose how the kernel will handle t <<
2350 command line string. <<
2351 <<
2352 config CMDLINE_FROM_BOOTLOADER <<
2353 bool "Use bootloader kernel arguments <<
2354 help <<
2355 Uses the command-line options passe <<
2356 the boot loader doesn't provide any <<
2357 string provided in CMDLINE will be <<
2358 <<
2359 config CMDLINE_FORCE <<
2360 bool "Always use the default kernel c <<
2361 help <<
2362 Always use the default kernel comma <<
2363 loader passes other arguments to th <<
2364 This is useful if you cannot or don <<
2365 command-line options your boot load <<
2366 3139
2367 endchoice !! 3140 config COMPAT
>> 3141 bool
2368 3142
2369 config EFI_STUB !! 3143 config SYSVIPC_COMPAT
2370 bool 3144 bool
2371 3145
2372 config EFI !! 3146 config MIPS32_O32
2373 bool "UEFI runtime support" !! 3147 bool "Kernel support for o32 binaries"
2374 depends on OF && !CPU_BIG_ENDIAN !! 3148 depends on 64BIT
2375 depends on KERNEL_MODE_NEON !! 3149 select ARCH_WANT_OLD_COMPAT_IPC
2376 select ARCH_SUPPORTS_ACPI !! 3150 select COMPAT
2377 select LIBFDT !! 3151 select MIPS32_COMPAT
2378 select UCS2_STRING !! 3152 select SYSVIPC_COMPAT if SYSVIPC
2379 select EFI_PARAMS_FROM_FDT !! 3153 help
2380 select EFI_RUNTIME_WRAPPERS !! 3154 Select this option if you want to run o32 binaries. These are pure
2381 select EFI_STUB !! 3155 32-bit binaries as used by the 32-bit Linux/MIPS port. Most of
2382 select EFI_GENERIC_STUB !! 3156 existing binaries are in this format.
2383 imply IMA_SECURE_AND_OR_TRUSTED_BOOT <<
2384 default y <<
2385 help <<
2386 This option provides support for ru <<
2387 by UEFI firmware (such as non-volat <<
2388 clock, and platform reset). A UEFI <<
2389 allow the kernel to be booted as an <<
2390 is only useful on systems that have <<
2391 3157
2392 config COMPRESSED_INSTALL !! 3158 If unsure, say Y.
2393 bool "Install compressed image by def <<
2394 help <<
2395 This makes the regular "make instal <<
2396 image we built, not the legacy unco <<
2397 3159
2398 You can check that a compressed ima !! 3160 config MIPS32_N32
2399 "make zinstall" first, and verifyin !! 3161 bool "Kernel support for n32 binaries"
2400 in your environment before making " !! 3162 depends on 64BIT
2401 you. !! 3163 select ARCH_WANT_COMPAT_IPC_PARSE_VERSION
>> 3164 select COMPAT
>> 3165 select MIPS32_COMPAT
>> 3166 select SYSVIPC_COMPAT if SYSVIPC
>> 3167 help
>> 3168 Select this option if you want to run n32 binaries. These are
>> 3169 64-bit binaries using 32-bit quantities for addressing and certain
>> 3170 data that would normally be 64-bit. They are used in special
>> 3171 cases.
2402 3172
2403 config DMI !! 3173 If unsure, say N.
2404 bool "Enable support for SMBIOS (DMI) <<
2405 depends on EFI <<
2406 default y <<
2407 help <<
2408 This enables SMBIOS/DMI feature for <<
2409 3174
2410 This option is only useful on syste !! 3175 config BINFMT_ELF32
2411 However, even with this option, the !! 3176 bool
2412 continue to boot on existing non-UE !! 3177 default y if MIPS32_O32 || MIPS32_N32
>> 3178 select ELFCORE
2413 3179
2414 endmenu # "Boot options" !! 3180 endmenu
2415 3181
2416 menu "Power management options" 3182 menu "Power management options"
2417 3183
2418 source "kernel/power/Kconfig" <<
2419 <<
2420 config ARCH_HIBERNATION_POSSIBLE 3184 config ARCH_HIBERNATION_POSSIBLE
2421 def_bool y 3185 def_bool y
2422 depends on CPU_PM !! 3186 depends on SYS_SUPPORTS_HOTPLUG_CPU || !SMP
2423 <<
2424 config ARCH_HIBERNATION_HEADER <<
2425 def_bool y <<
2426 depends on HIBERNATION <<
2427 3187
2428 config ARCH_SUSPEND_POSSIBLE 3188 config ARCH_SUSPEND_POSSIBLE
2429 def_bool y 3189 def_bool y
>> 3190 depends on SYS_SUPPORTS_HOTPLUG_CPU || !SMP
>> 3191
>> 3192 source "kernel/power/Kconfig"
2430 3193
2431 endmenu # "Power management options" !! 3194 endmenu
>> 3195
>> 3196 config MIPS_EXTERNAL_TIMER
>> 3197 bool
2432 3198
2433 menu "CPU Power Management" 3199 menu "CPU Power Management"
2434 3200
>> 3201 if CPU_SUPPORTS_CPUFREQ && MIPS_EXTERNAL_TIMER
>> 3202 source "drivers/cpufreq/Kconfig"
>> 3203 endif
>> 3204
2435 source "drivers/cpuidle/Kconfig" 3205 source "drivers/cpuidle/Kconfig"
2436 3206
2437 source "drivers/cpufreq/Kconfig" !! 3207 endmenu
>> 3208
>> 3209 source "net/Kconfig"
>> 3210
>> 3211 source "drivers/Kconfig"
>> 3212
>> 3213 source "drivers/firmware/Kconfig"
>> 3214
>> 3215 source "fs/Kconfig"
>> 3216
>> 3217 source "arch/mips/Kconfig.debug"
2438 3218
2439 endmenu # "CPU Power Management" !! 3219 source "security/Kconfig"
2440 3220
2441 source "drivers/acpi/Kconfig" !! 3221 source "crypto/Kconfig"
2442 3222
2443 source "arch/arm64/kvm/Kconfig" !! 3223 source "lib/Kconfig"
2444 3224
>> 3225 source "arch/mips/kvm/Kconfig"
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