1 # SPDX-License-Identifier: GPL-2.0-only !! 1 # SPDX-License-Identifier: GPL-2.0
2 config ARM64 !! 2 config MIPS
3 def_bool y !! 3 bool
4 select ACPI_APMT if ACPI !! 4 default y
5 select ACPI_CCA_REQUIRED if ACPI <<
6 select ACPI_GENERIC_GSI if ACPI <<
7 select ACPI_GTDT if ACPI <<
8 select ACPI_HOTPLUG_CPU if ACPI_PROCES <<
9 select ACPI_IORT if ACPI <<
10 select ACPI_REDUCED_HARDWARE_ONLY if A <<
11 select ACPI_MCFG if (ACPI && PCI) <<
12 select ACPI_SPCR_TABLE if ACPI <<
13 select ACPI_PPTT if ACPI <<
14 select ARCH_HAS_DEBUG_WX <<
15 select ARCH_BINFMT_ELF_EXTRA_PHDRS <<
16 select ARCH_BINFMT_ELF_STATE 5 select ARCH_BINFMT_ELF_STATE
17 select ARCH_CORRECT_STACKTRACE_ON_KRET !! 6 select ARCH_CLOCKSOURCE_DATA
18 select ARCH_ENABLE_HUGEPAGE_MIGRATION !! 7 select ARCH_DISCARD_MEMBLOCK
19 select ARCH_ENABLE_MEMORY_HOTPLUG !! 8 select ARCH_HAS_ELF_RANDOMIZE
20 select ARCH_ENABLE_MEMORY_HOTREMOVE <<
21 select ARCH_ENABLE_SPLIT_PMD_PTLOCK if <<
22 select ARCH_ENABLE_THP_MIGRATION if TR <<
23 select ARCH_HAS_CACHE_LINE_SIZE <<
24 select ARCH_HAS_CURRENT_STACK_POINTER <<
25 select ARCH_HAS_DEBUG_VIRTUAL <<
26 select ARCH_HAS_DEBUG_VM_PGTABLE <<
27 select ARCH_HAS_DMA_OPS if XEN <<
28 select ARCH_HAS_DMA_PREP_COHERENT <<
29 select ARCH_HAS_ACPI_TABLE_UPGRADE if <<
30 select ARCH_HAS_FAST_MULTIPLIER <<
31 select ARCH_HAS_FORTIFY_SOURCE <<
32 select ARCH_HAS_GCOV_PROFILE_ALL <<
33 select ARCH_HAS_GIGANTIC_PAGE <<
34 select ARCH_HAS_KCOV <<
35 select ARCH_HAS_KERNEL_FPU_SUPPORT if <<
36 select ARCH_HAS_KEEPINITRD <<
37 select ARCH_HAS_MEMBARRIER_SYNC_CORE <<
38 select ARCH_HAS_MEM_ENCRYPT <<
39 select ARCH_HAS_NMI_SAFE_THIS_CPU_OPS <<
40 select ARCH_HAS_NON_OVERLAPPING_ADDRES <<
41 select ARCH_HAS_PTE_DEVMAP <<
42 select ARCH_HAS_PTE_SPECIAL <<
43 select ARCH_HAS_HW_PTE_YOUNG <<
44 select ARCH_HAS_SETUP_DMA_OPS <<
45 select ARCH_HAS_SET_DIRECT_MAP <<
46 select ARCH_HAS_SET_MEMORY <<
47 select ARCH_STACKWALK <<
48 select ARCH_HAS_STRICT_KERNEL_RWX <<
49 select ARCH_HAS_STRICT_MODULE_RWX <<
50 select ARCH_HAS_SYNC_DMA_FOR_DEVICE <<
51 select ARCH_HAS_SYNC_DMA_FOR_CPU <<
52 select ARCH_HAS_SYSCALL_WRAPPER <<
53 select ARCH_HAS_TICK_BROADCAST if GENE 9 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
54 select ARCH_HAS_ZONE_DMA_SET if EXPERT !! 10 select ARCH_MIGHT_HAVE_PC_PARPORT
55 select ARCH_HAVE_ELF_PROT !! 11 select ARCH_MIGHT_HAVE_PC_SERIO
56 select ARCH_HAVE_NMI_SAFE_CMPXCHG !! 12 select ARCH_SUPPORTS_UPROBES
57 select ARCH_HAVE_TRACE_MMIO_ACCESS !! 13 select ARCH_USE_BUILTIN_BSWAP
58 select ARCH_INLINE_READ_LOCK if !PREEM !! 14 select ARCH_USE_CMPXCHG_LOCKREF if 64BIT
59 select ARCH_INLINE_READ_LOCK_BH if !PR <<
60 select ARCH_INLINE_READ_LOCK_IRQ if !P <<
61 select ARCH_INLINE_READ_LOCK_IRQSAVE i <<
62 select ARCH_INLINE_READ_UNLOCK if !PRE <<
63 select ARCH_INLINE_READ_UNLOCK_BH if ! <<
64 select ARCH_INLINE_READ_UNLOCK_IRQ if <<
65 select ARCH_INLINE_READ_UNLOCK_IRQREST <<
66 select ARCH_INLINE_WRITE_LOCK if !PREE <<
67 select ARCH_INLINE_WRITE_LOCK_BH if !P <<
68 select ARCH_INLINE_WRITE_LOCK_IRQ if ! <<
69 select ARCH_INLINE_WRITE_LOCK_IRQSAVE <<
70 select ARCH_INLINE_WRITE_UNLOCK if !PR <<
71 select ARCH_INLINE_WRITE_UNLOCK_BH if <<
72 select ARCH_INLINE_WRITE_UNLOCK_IRQ if <<
73 select ARCH_INLINE_WRITE_UNLOCK_IRQRES <<
74 select ARCH_INLINE_SPIN_TRYLOCK if !PR <<
75 select ARCH_INLINE_SPIN_TRYLOCK_BH if <<
76 select ARCH_INLINE_SPIN_LOCK if !PREEM <<
77 select ARCH_INLINE_SPIN_LOCK_BH if !PR <<
78 select ARCH_INLINE_SPIN_LOCK_IRQ if !P <<
79 select ARCH_INLINE_SPIN_LOCK_IRQSAVE i <<
80 select ARCH_INLINE_SPIN_UNLOCK if !PRE <<
81 select ARCH_INLINE_SPIN_UNLOCK_BH if ! <<
82 select ARCH_INLINE_SPIN_UNLOCK_IRQ if <<
83 select ARCH_INLINE_SPIN_UNLOCK_IRQREST <<
84 select ARCH_KEEP_MEMBLOCK <<
85 select ARCH_MHP_MEMMAP_ON_MEMORY_ENABL <<
86 select ARCH_USE_CMPXCHG_LOCKREF <<
87 select ARCH_USE_GNU_PROPERTY <<
88 select ARCH_USE_MEMTEST <<
89 select ARCH_USE_QUEUED_RWLOCKS 15 select ARCH_USE_QUEUED_RWLOCKS
90 select ARCH_USE_QUEUED_SPINLOCKS 16 select ARCH_USE_QUEUED_SPINLOCKS
91 select ARCH_USE_SYM_ANNOTATIONS !! 17 select ARCH_WANT_IPC_PARSE_VERSION
92 select ARCH_SUPPORTS_DEBUG_PAGEALLOC !! 18 select BUILDTIME_EXTABLE_SORT
93 select ARCH_SUPPORTS_HUGETLBFS <<
94 select ARCH_SUPPORTS_MEMORY_FAILURE <<
95 select ARCH_SUPPORTS_SHADOW_CALL_STACK <<
96 select ARCH_SUPPORTS_LTO_CLANG if CPU_ <<
97 select ARCH_SUPPORTS_LTO_CLANG_THIN <<
98 select ARCH_SUPPORTS_CFI_CLANG <<
99 select ARCH_SUPPORTS_ATOMIC_RMW <<
100 select ARCH_SUPPORTS_INT128 if CC_HAS_ <<
101 select ARCH_SUPPORTS_NUMA_BALANCING <<
102 select ARCH_SUPPORTS_PAGE_TABLE_CHECK <<
103 select ARCH_SUPPORTS_PER_VMA_LOCK <<
104 select ARCH_SUPPORTS_HUGE_PFNMAP if TR <<
105 select ARCH_SUPPORTS_RT <<
106 select ARCH_WANT_BATCHED_UNMAP_TLB_FLU <<
107 select ARCH_WANT_COMPAT_IPC_PARSE_VERS <<
108 select ARCH_WANT_DEFAULT_BPF_JIT <<
109 select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_ <<
110 select ARCH_WANT_FRAME_POINTERS <<
111 select ARCH_WANT_HUGE_PMD_SHARE if ARM <<
112 select ARCH_WANT_LD_ORPHAN_WARN <<
113 select ARCH_WANTS_EXECMEM_LATE if EXEC <<
114 select ARCH_WANTS_NO_INSTR <<
115 select ARCH_WANTS_THP_SWAP if ARM64_4K <<
116 select ARCH_HAS_UBSAN <<
117 select ARM_AMBA <<
118 select ARM_ARCH_TIMER <<
119 select ARM_GIC <<
120 select AUDIT_ARCH_COMPAT_GENERIC <<
121 select ARM_GIC_V2M if PCI <<
122 select ARM_GIC_V3 <<
123 select ARM_GIC_V3_ITS if PCI <<
124 select ARM_PSCI_FW <<
125 select BUILDTIME_TABLE_SORT <<
126 select CLONE_BACKWARDS 19 select CLONE_BACKWARDS
127 select COMMON_CLK !! 20 select CPU_PM if CPU_IDLE
128 select CPU_PM if (SUSPEND || CPU_IDLE) !! 21 select GENERIC_ATOMIC64 if !64BIT
129 select CPUMASK_OFFSTACK if NR_CPUS > 2 !! 22 select GENERIC_CLOCKEVENTS
130 select CRC32 !! 23 select GENERIC_CMOS_UPDATE
131 select DCACHE_WORD_ACCESS <<
132 select DYNAMIC_FTRACE if FUNCTION_TRAC <<
133 select DMA_BOUNCE_UNALIGNED_KMALLOC <<
134 select DMA_DIRECT_REMAP <<
135 select EDAC_SUPPORT <<
136 select FRAME_POINTER <<
137 select FUNCTION_ALIGNMENT_4B <<
138 select FUNCTION_ALIGNMENT_8B if DYNAMI <<
139 select GENERIC_ALLOCATOR <<
140 select GENERIC_ARCH_TOPOLOGY <<
141 select GENERIC_CLOCKEVENTS_BROADCAST <<
142 select GENERIC_CPU_AUTOPROBE 24 select GENERIC_CPU_AUTOPROBE
143 select GENERIC_CPU_DEVICES <<
144 select GENERIC_CPU_VULNERABILITIES <<
145 select GENERIC_EARLY_IOREMAP <<
146 select GENERIC_IDLE_POLL_SETUP <<
147 select GENERIC_IOREMAP <<
148 select GENERIC_IRQ_IPI <<
149 select GENERIC_IRQ_PROBE 25 select GENERIC_IRQ_PROBE
150 select GENERIC_IRQ_SHOW 26 select GENERIC_IRQ_SHOW
151 select GENERIC_IRQ_SHOW_LEVEL <<
152 select GENERIC_LIB_DEVMEM_IS_ALLOWED <<
153 select GENERIC_PCI_IOMAP 27 select GENERIC_PCI_IOMAP
154 select GENERIC_PTDUMP !! 28 select GENERIC_SCHED_CLOCK if !CAVIUM_OCTEON_SOC
155 select GENERIC_SCHED_CLOCK <<
156 select GENERIC_SMP_IDLE_THREAD 29 select GENERIC_SMP_IDLE_THREAD
157 select GENERIC_TIME_VSYSCALL 30 select GENERIC_TIME_VSYSCALL
158 select GENERIC_GETTIMEOFDAY !! 31 select HANDLE_DOMAIN_IRQ
159 select GENERIC_VDSO_TIME_NS <<
160 select HARDIRQS_SW_RESEND <<
161 select HAS_IOPORT <<
162 select HAVE_MOVE_PMD <<
163 select HAVE_MOVE_PUD <<
164 select HAVE_PCI <<
165 select HAVE_ACPI_APEI if (ACPI && EFI) <<
166 select HAVE_ALIGNED_STRUCT_PAGE <<
167 select HAVE_ARCH_AUDITSYSCALL <<
168 select HAVE_ARCH_BITREVERSE <<
169 select HAVE_ARCH_COMPILER_H <<
170 select HAVE_ARCH_HUGE_VMALLOC <<
171 select HAVE_ARCH_HUGE_VMAP <<
172 select HAVE_ARCH_JUMP_LABEL 32 select HAVE_ARCH_JUMP_LABEL
173 select HAVE_ARCH_JUMP_LABEL_RELATIVE <<
174 select HAVE_ARCH_KASAN <<
175 select HAVE_ARCH_KASAN_VMALLOC <<
176 select HAVE_ARCH_KASAN_SW_TAGS <<
177 select HAVE_ARCH_KASAN_HW_TAGS if ARM6 <<
178 # Some instrumentation may be unsound, <<
179 select HAVE_ARCH_KCSAN if EXPERT <<
180 select HAVE_ARCH_KFENCE <<
181 select HAVE_ARCH_KGDB 33 select HAVE_ARCH_KGDB
182 select HAVE_ARCH_MMAP_RND_BITS !! 34 select HAVE_ARCH_MMAP_RND_BITS if MMU
183 select HAVE_ARCH_MMAP_RND_COMPAT_BITS !! 35 select HAVE_ARCH_MMAP_RND_COMPAT_BITS if MMU && COMPAT
184 select HAVE_ARCH_PREL32_RELOCATIONS <<
185 select HAVE_ARCH_RANDOMIZE_KSTACK_OFFS <<
186 select HAVE_ARCH_SECCOMP_FILTER 36 select HAVE_ARCH_SECCOMP_FILTER
187 select HAVE_ARCH_STACKLEAK <<
188 select HAVE_ARCH_THREAD_STRUCT_WHITELI <<
189 select HAVE_ARCH_TRACEHOOK 37 select HAVE_ARCH_TRACEHOOK
190 select HAVE_ARCH_TRANSPARENT_HUGEPAGE !! 38 select HAVE_ARCH_TRANSPARENT_HUGEPAGE if CPU_SUPPORTS_HUGEPAGES && 64BIT
191 select HAVE_ARCH_VMAP_STACK !! 39 select HAVE_CBPF_JIT if (!64BIT && !CPU_MICROMIPS)
192 select HAVE_ARM_SMCCC !! 40 select HAVE_EBPF_JIT if (64BIT && !CPU_MICROMIPS)
193 select HAVE_ASM_MODVERSIONS !! 41 select HAVE_CC_STACKPROTECTOR
194 select HAVE_EBPF_JIT !! 42 select HAVE_CONTEXT_TRACKING
>> 43 select HAVE_COPY_THREAD_TLS
195 select HAVE_C_RECORDMCOUNT 44 select HAVE_C_RECORDMCOUNT
196 select HAVE_CMPXCHG_DOUBLE <<
197 select HAVE_CMPXCHG_LOCAL <<
198 select HAVE_CONTEXT_TRACKING_USER <<
199 select HAVE_DEBUG_KMEMLEAK 45 select HAVE_DEBUG_KMEMLEAK
>> 46 select HAVE_DEBUG_STACKOVERFLOW
>> 47 select HAVE_DMA_API_DEBUG
200 select HAVE_DMA_CONTIGUOUS 48 select HAVE_DMA_CONTIGUOUS
201 select HAVE_DYNAMIC_FTRACE 49 select HAVE_DYNAMIC_FTRACE
202 select HAVE_DYNAMIC_FTRACE_WITH_ARGS \ !! 50 select HAVE_EXIT_THREAD
203 if (GCC_SUPPORTS_DYNAMIC_FTRAC <<
204 CLANG_SUPPORTS_DYNAMIC_FTR <<
205 select HAVE_DYNAMIC_FTRACE_WITH_DIRECT <<
206 if DYNAMIC_FTRACE_WITH_ARGS && <<
207 select HAVE_DYNAMIC_FTRACE_WITH_CALL_O <<
208 if (DYNAMIC_FTRACE_WITH_ARGS & <<
209 (CC_IS_CLANG || !CC_OPTIMI <<
210 select FTRACE_MCOUNT_USE_PATCHABLE_FUN <<
211 if DYNAMIC_FTRACE_WITH_ARGS <<
212 select HAVE_SAMPLE_FTRACE_DIRECT <<
213 select HAVE_SAMPLE_FTRACE_DIRECT_MULTI <<
214 select HAVE_EFFICIENT_UNALIGNED_ACCESS <<
215 select HAVE_GUP_FAST <<
216 select HAVE_FTRACE_MCOUNT_RECORD 51 select HAVE_FTRACE_MCOUNT_RECORD
217 select HAVE_FUNCTION_TRACER <<
218 select HAVE_FUNCTION_ERROR_INJECTION <<
219 select HAVE_FUNCTION_GRAPH_TRACER 52 select HAVE_FUNCTION_GRAPH_TRACER
220 select HAVE_FUNCTION_GRAPH_RETVAL !! 53 select HAVE_FUNCTION_TRACER
221 select HAVE_GCC_PLUGINS !! 54 select HAVE_GENERIC_DMA_COHERENT
222 select HAVE_HARDLOCKUP_DETECTOR_PERF i !! 55 select HAVE_IDE
223 HW_PERF_EVENTS && HAVE_PERF_EV !! 56 select HAVE_IRQ_EXIT_ON_IRQ_STACK
224 select HAVE_HW_BREAKPOINT if PERF_EVEN <<
225 select HAVE_IOREMAP_PROT <<
226 select HAVE_IRQ_TIME_ACCOUNTING 57 select HAVE_IRQ_TIME_ACCOUNTING
>> 58 select HAVE_KPROBES
>> 59 select HAVE_KRETPROBES
>> 60 select HAVE_MEMBLOCK
>> 61 select HAVE_MEMBLOCK_NODE_MAP
227 select HAVE_MOD_ARCH_SPECIFIC 62 select HAVE_MOD_ARCH_SPECIFIC
228 select HAVE_NMI 63 select HAVE_NMI
>> 64 select HAVE_OPROFILE
229 select HAVE_PERF_EVENTS 65 select HAVE_PERF_EVENTS
230 select HAVE_PERF_EVENTS_NMI if ARM64_P <<
231 select HAVE_PERF_REGS <<
232 select HAVE_PERF_USER_STACK_DUMP <<
233 select HAVE_PREEMPT_DYNAMIC_KEY <<
234 select HAVE_REGS_AND_STACK_ACCESS_API 66 select HAVE_REGS_AND_STACK_ACCESS_API
235 select HAVE_POSIX_CPU_TIMERS_TASK_WORK <<
236 select HAVE_FUNCTION_ARG_ACCESS_API <<
237 select MMU_GATHER_RCU_TABLE_FREE <<
238 select HAVE_RSEQ <<
239 select HAVE_RUST if RUSTC_SUPPORTS_ARM <<
240 select HAVE_STACKPROTECTOR <<
241 select HAVE_SYSCALL_TRACEPOINTS 67 select HAVE_SYSCALL_TRACEPOINTS
242 select HAVE_KPROBES !! 68 select HAVE_VIRT_CPU_ACCOUNTING_GEN if 64BIT || !SMP
243 select HAVE_KRETPROBES <<
244 select HAVE_GENERIC_VDSO <<
245 select HOTPLUG_CORE_SYNC_DEAD if HOTPL <<
246 select IRQ_DOMAIN <<
247 select IRQ_FORCED_THREADING 69 select IRQ_FORCED_THREADING
248 select KASAN_VMALLOC if KASAN !! 70 select MODULES_USE_ELF_RELA if MODULES && 64BIT
249 select LOCK_MM_AND_FIND_VMA !! 71 select MODULES_USE_ELF_REL if MODULES
250 select MODULES_USE_ELF_RELA !! 72 select PERF_USE_VMALLOC
251 select NEED_DMA_MAP_STATE !! 73 select RTC_LIB if !MACH_LOONGSON64
252 select NEED_SG_DMA_LENGTH <<
253 select OF <<
254 select OF_EARLY_FLATTREE <<
255 select PCI_DOMAINS_GENERIC if PCI <<
256 select PCI_ECAM if (ACPI && PCI) <<
257 select PCI_SYSCALL if PCI <<
258 select POWER_RESET <<
259 select POWER_SUPPLY <<
260 select SPARSE_IRQ <<
261 select SWIOTLB <<
262 select SYSCTL_EXCEPTION_TRACE 74 select SYSCTL_EXCEPTION_TRACE
263 select THREAD_INFO_IN_TASK !! 75 select VIRT_TO_BUS
264 select HAVE_ARCH_USERFAULTFD_MINOR if <<
265 select HAVE_ARCH_USERFAULTFD_WP if USE <<
266 select TRACE_IRQFLAGS_SUPPORT <<
267 select TRACE_IRQFLAGS_NMI_SUPPORT <<
268 select HAVE_SOFTIRQ_ON_OWN_STACK <<
269 select USER_STACKTRACE_SUPPORT <<
270 select VDSO_GETRANDOM <<
271 help <<
272 ARM 64-bit (AArch64) Linux support. <<
273 <<
274 config RUSTC_SUPPORTS_ARM64 <<
275 def_bool y <<
276 depends on CPU_LITTLE_ENDIAN <<
277 # Shadow call stack is only supported <<
278 # <<
279 # When using the UNWIND_PATCH_PAC_INTO <<
280 # required due to use of the -Zfixed-x <<
281 # <<
282 # Otherwise, rustc version 1.82+ is re <<
283 # -Zsanitizer=shadow-call-stack flag. <<
284 depends on !SHADOW_CALL_STACK || RUSTC <<
285 <<
286 config CLANG_SUPPORTS_DYNAMIC_FTRACE_WITH_ARGS <<
287 def_bool CC_IS_CLANG <<
288 # https://github.com/ClangBuiltLinux/l <<
289 depends on AS_IS_GNU || (AS_IS_LLVM && <<
290 <<
291 config GCC_SUPPORTS_DYNAMIC_FTRACE_WITH_ARGS <<
292 def_bool CC_IS_GCC <<
293 depends on $(cc-option,-fpatchable-fun <<
294 <<
295 config 64BIT <<
296 def_bool y <<
297 76
298 config MMU !! 77 menu "Machine selection"
299 def_bool y <<
300 78
301 config ARM64_CONT_PTE_SHIFT !! 79 choice
302 int !! 80 prompt "System type"
303 default 5 if PAGE_SIZE_64KB !! 81 default MIPS_GENERIC
304 default 7 if PAGE_SIZE_16KB <<
305 default 4 <<
306 <<
307 config ARM64_CONT_PMD_SHIFT <<
308 int <<
309 default 5 if PAGE_SIZE_64KB <<
310 default 5 if PAGE_SIZE_16KB <<
311 default 4 <<
312 82
313 config ARCH_MMAP_RND_BITS_MIN !! 83 config MIPS_GENERIC
314 default 14 if PAGE_SIZE_64KB !! 84 bool "Generic board-agnostic MIPS kernel"
315 default 16 if PAGE_SIZE_16KB !! 85 select BOOT_RAW
316 default 18 !! 86 select BUILTIN_DTB
>> 87 select CEVT_R4K
>> 88 select CLKSRC_MIPS_GIC
>> 89 select COMMON_CLK
>> 90 select CPU_MIPSR2_IRQ_VI
>> 91 select CPU_MIPSR2_IRQ_EI
>> 92 select CSRC_R4K
>> 93 select DMA_PERDEV_COHERENT
>> 94 select HW_HAS_PCI
>> 95 select IRQ_MIPS_CPU
>> 96 select LIBFDT
>> 97 select MIPS_CPU_SCACHE
>> 98 select MIPS_GIC
>> 99 select MIPS_L1_CACHE_SHIFT_7
>> 100 select NO_EXCEPT_FILL
>> 101 select PCI_DRIVERS_GENERIC
>> 102 select PINCTRL
>> 103 select SMP_UP if SMP
>> 104 select SWAP_IO_SPACE
>> 105 select SYS_HAS_CPU_MIPS32_R1
>> 106 select SYS_HAS_CPU_MIPS32_R2
>> 107 select SYS_HAS_CPU_MIPS32_R6
>> 108 select SYS_HAS_CPU_MIPS64_R1
>> 109 select SYS_HAS_CPU_MIPS64_R2
>> 110 select SYS_HAS_CPU_MIPS64_R6
>> 111 select SYS_SUPPORTS_32BIT_KERNEL
>> 112 select SYS_SUPPORTS_64BIT_KERNEL
>> 113 select SYS_SUPPORTS_BIG_ENDIAN
>> 114 select SYS_SUPPORTS_HIGHMEM
>> 115 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 116 select SYS_SUPPORTS_MICROMIPS
>> 117 select SYS_SUPPORTS_MIPS_CPS
>> 118 select SYS_SUPPORTS_MIPS16
>> 119 select SYS_SUPPORTS_MULTITHREADING
>> 120 select SYS_SUPPORTS_RELOCATABLE
>> 121 select SYS_SUPPORTS_SMARTMIPS
>> 122 select USB_EHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
>> 123 select USB_EHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 124 select USB_OHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
>> 125 select USB_OHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 126 select USB_UHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
>> 127 select USB_UHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 128 select USE_OF
>> 129 help
>> 130 Select this to build a kernel which aims to support multiple boards,
>> 131 generally using a flattened device tree passed from the bootloader
>> 132 using the boot protocol defined in the UHI (Unified Hosting
>> 133 Interface) specification.
>> 134
>> 135 config MIPS_ALCHEMY
>> 136 bool "Alchemy processor based machines"
>> 137 select ARCH_PHYS_ADDR_T_64BIT
>> 138 select CEVT_R4K
>> 139 select CSRC_R4K
>> 140 select IRQ_MIPS_CPU
>> 141 select DMA_MAYBE_COHERENT # Au1000,1500,1100 aren't, rest is
>> 142 select SYS_HAS_CPU_MIPS32_R1
>> 143 select SYS_SUPPORTS_32BIT_KERNEL
>> 144 select SYS_SUPPORTS_APM_EMULATION
>> 145 select GPIOLIB
>> 146 select SYS_SUPPORTS_ZBOOT
>> 147 select COMMON_CLK
317 148
318 # max bits determined by the following formula !! 149 config AR7
319 # VA_BITS - PAGE_SHIFT - 3 !! 150 bool "Texas Instruments AR7"
320 config ARCH_MMAP_RND_BITS_MAX !! 151 select BOOT_ELF32
321 default 19 if ARM64_VA_BITS=36 !! 152 select DMA_NONCOHERENT
322 default 24 if ARM64_VA_BITS=39 !! 153 select CEVT_R4K
323 default 27 if ARM64_VA_BITS=42 !! 154 select CSRC_R4K
324 default 30 if ARM64_VA_BITS=47 !! 155 select IRQ_MIPS_CPU
325 default 29 if ARM64_VA_BITS=48 && ARM6 !! 156 select NO_EXCEPT_FILL
326 default 31 if ARM64_VA_BITS=48 && ARM6 !! 157 select SWAP_IO_SPACE
327 default 33 if ARM64_VA_BITS=48 !! 158 select SYS_HAS_CPU_MIPS32_R1
328 default 14 if ARM64_64K_PAGES !! 159 select SYS_HAS_EARLY_PRINTK
329 default 16 if ARM64_16K_PAGES !! 160 select SYS_SUPPORTS_32BIT_KERNEL
330 default 18 !! 161 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 162 select SYS_SUPPORTS_MIPS16
>> 163 select SYS_SUPPORTS_ZBOOT_UART16550
>> 164 select GPIOLIB
>> 165 select VLYNQ
>> 166 select HAVE_CLK
>> 167 help
>> 168 Support for the Texas Instruments AR7 System-on-a-Chip
>> 169 family: TNETD7100, 7200 and 7300.
>> 170
>> 171 config ATH25
>> 172 bool "Atheros AR231x/AR531x SoC support"
>> 173 select CEVT_R4K
>> 174 select CSRC_R4K
>> 175 select DMA_NONCOHERENT
>> 176 select IRQ_MIPS_CPU
>> 177 select IRQ_DOMAIN
>> 178 select SYS_HAS_CPU_MIPS32_R1
>> 179 select SYS_SUPPORTS_BIG_ENDIAN
>> 180 select SYS_SUPPORTS_32BIT_KERNEL
>> 181 select SYS_HAS_EARLY_PRINTK
>> 182 help
>> 183 Support for Atheros AR231x and Atheros AR531x based boards
>> 184
>> 185 config ATH79
>> 186 bool "Atheros AR71XX/AR724X/AR913X based boards"
>> 187 select ARCH_HAS_RESET_CONTROLLER
>> 188 select BOOT_RAW
>> 189 select CEVT_R4K
>> 190 select CSRC_R4K
>> 191 select DMA_NONCOHERENT
>> 192 select GPIOLIB
>> 193 select HAVE_CLK
>> 194 select COMMON_CLK
>> 195 select CLKDEV_LOOKUP
>> 196 select IRQ_MIPS_CPU
>> 197 select MIPS_MACHINE
>> 198 select SYS_HAS_CPU_MIPS32_R2
>> 199 select SYS_HAS_EARLY_PRINTK
>> 200 select SYS_SUPPORTS_32BIT_KERNEL
>> 201 select SYS_SUPPORTS_BIG_ENDIAN
>> 202 select SYS_SUPPORTS_MIPS16
>> 203 select SYS_SUPPORTS_ZBOOT_UART_PROM
>> 204 select USE_OF
>> 205 help
>> 206 Support for the Atheros AR71XX/AR724X/AR913X SoCs.
>> 207
>> 208 config BMIPS_GENERIC
>> 209 bool "Broadcom Generic BMIPS kernel"
>> 210 select BOOT_RAW
>> 211 select NO_EXCEPT_FILL
>> 212 select USE_OF
>> 213 select CEVT_R4K
>> 214 select CSRC_R4K
>> 215 select SYNC_R4K
>> 216 select COMMON_CLK
>> 217 select BCM6345_L1_IRQ
>> 218 select BCM7038_L1_IRQ
>> 219 select BCM7120_L2_IRQ
>> 220 select BRCMSTB_L2_IRQ
>> 221 select IRQ_MIPS_CPU
>> 222 select DMA_NONCOHERENT
>> 223 select SYS_SUPPORTS_32BIT_KERNEL
>> 224 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 225 select SYS_SUPPORTS_BIG_ENDIAN
>> 226 select SYS_SUPPORTS_HIGHMEM
>> 227 select SYS_HAS_CPU_BMIPS32_3300
>> 228 select SYS_HAS_CPU_BMIPS4350
>> 229 select SYS_HAS_CPU_BMIPS4380
>> 230 select SYS_HAS_CPU_BMIPS5000
>> 231 select SWAP_IO_SPACE
>> 232 select USB_EHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
>> 233 select USB_EHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 234 select USB_OHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
>> 235 select USB_OHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 236 select HARDIRQS_SW_RESEND
>> 237 help
>> 238 Build a generic DT-based kernel image that boots on select
>> 239 BCM33xx cable modem chips, BCM63xx DSL chips, and BCM7xxx set-top
>> 240 box chips. Note that CONFIG_CPU_BIG_ENDIAN/CONFIG_CPU_LITTLE_ENDIAN
>> 241 must be set appropriately for your board.
>> 242
>> 243 config BCM47XX
>> 244 bool "Broadcom BCM47XX based boards"
>> 245 select BOOT_RAW
>> 246 select CEVT_R4K
>> 247 select CSRC_R4K
>> 248 select DMA_NONCOHERENT
>> 249 select HW_HAS_PCI
>> 250 select IRQ_MIPS_CPU
>> 251 select SYS_HAS_CPU_MIPS32_R1
>> 252 select NO_EXCEPT_FILL
>> 253 select SYS_SUPPORTS_32BIT_KERNEL
>> 254 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 255 select SYS_SUPPORTS_MIPS16
>> 256 select SYS_HAS_EARLY_PRINTK
>> 257 select USE_GENERIC_EARLY_PRINTK_8250
>> 258 select GPIOLIB
>> 259 select LEDS_GPIO_REGISTER
>> 260 select BCM47XX_NVRAM
>> 261 select BCM47XX_SPROM
>> 262 select BCM47XX_SSB if !BCM47XX_BCMA
>> 263 help
>> 264 Support for BCM47XX based boards
>> 265
>> 266 config BCM63XX
>> 267 bool "Broadcom BCM63XX based boards"
>> 268 select BOOT_RAW
>> 269 select CEVT_R4K
>> 270 select CSRC_R4K
>> 271 select SYNC_R4K
>> 272 select DMA_NONCOHERENT
>> 273 select IRQ_MIPS_CPU
>> 274 select SYS_SUPPORTS_32BIT_KERNEL
>> 275 select SYS_SUPPORTS_BIG_ENDIAN
>> 276 select SYS_HAS_EARLY_PRINTK
>> 277 select SWAP_IO_SPACE
>> 278 select GPIOLIB
>> 279 select HAVE_CLK
>> 280 select MIPS_L1_CACHE_SHIFT_4
>> 281 select CLKDEV_LOOKUP
>> 282 help
>> 283 Support for BCM63XX based boards
>> 284
>> 285 config MIPS_COBALT
>> 286 bool "Cobalt Server"
>> 287 select CEVT_R4K
>> 288 select CSRC_R4K
>> 289 select CEVT_GT641XX
>> 290 select DMA_NONCOHERENT
>> 291 select HW_HAS_PCI
>> 292 select I8253
>> 293 select I8259
>> 294 select IRQ_MIPS_CPU
>> 295 select IRQ_GT641XX
>> 296 select PCI_GT64XXX_PCI0
>> 297 select PCI
>> 298 select SYS_HAS_CPU_NEVADA
>> 299 select SYS_HAS_EARLY_PRINTK
>> 300 select SYS_SUPPORTS_32BIT_KERNEL
>> 301 select SYS_SUPPORTS_64BIT_KERNEL
>> 302 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 303 select USE_GENERIC_EARLY_PRINTK_8250
>> 304
>> 305 config MACH_DECSTATION
>> 306 bool "DECstations"
>> 307 select BOOT_ELF32
>> 308 select CEVT_DS1287
>> 309 select CEVT_R4K if CPU_R4X00
>> 310 select CSRC_IOASIC
>> 311 select CSRC_R4K if CPU_R4X00
>> 312 select CPU_DADDI_WORKAROUNDS if 64BIT
>> 313 select CPU_R4000_WORKAROUNDS if 64BIT
>> 314 select CPU_R4400_WORKAROUNDS if 64BIT
>> 315 select DMA_NONCOHERENT
>> 316 select NO_IOPORT_MAP
>> 317 select IRQ_MIPS_CPU
>> 318 select SYS_HAS_CPU_R3000
>> 319 select SYS_HAS_CPU_R4X00
>> 320 select SYS_SUPPORTS_32BIT_KERNEL
>> 321 select SYS_SUPPORTS_64BIT_KERNEL
>> 322 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 323 select SYS_SUPPORTS_128HZ
>> 324 select SYS_SUPPORTS_256HZ
>> 325 select SYS_SUPPORTS_1024HZ
>> 326 select MIPS_L1_CACHE_SHIFT_4
>> 327 help
>> 328 This enables support for DEC's MIPS based workstations. For details
>> 329 see the Linux/MIPS FAQ on <http://www.linux-mips.org/> and the
>> 330 DECstation porting pages on <http://decstation.unix-ag.org/>.
>> 331
>> 332 If you have one of the following DECstation Models you definitely
>> 333 want to choose R4xx0 for the CPU Type:
>> 334
>> 335 DECstation 5000/50
>> 336 DECstation 5000/150
>> 337 DECstation 5000/260
>> 338 DECsystem 5900/260
>> 339
>> 340 otherwise choose R3000.
>> 341
>> 342 config MACH_JAZZ
>> 343 bool "Jazz family of machines"
>> 344 select FW_ARC
>> 345 select FW_ARC32
>> 346 select ARCH_MAY_HAVE_PC_FDC
>> 347 select CEVT_R4K
>> 348 select CSRC_R4K
>> 349 select DEFAULT_SGI_PARTITION if CPU_BIG_ENDIAN
>> 350 select GENERIC_ISA_DMA
>> 351 select HAVE_PCSPKR_PLATFORM
>> 352 select IRQ_MIPS_CPU
>> 353 select I8253
>> 354 select I8259
>> 355 select ISA
>> 356 select SYS_HAS_CPU_R4X00
>> 357 select SYS_SUPPORTS_32BIT_KERNEL
>> 358 select SYS_SUPPORTS_64BIT_KERNEL
>> 359 select SYS_SUPPORTS_100HZ
>> 360 help
>> 361 This a family of machines based on the MIPS R4030 chipset which was
>> 362 used by several vendors to build RISC/os and Windows NT workstations.
>> 363 Members include the Acer PICA, MIPS Magnum 4000, MIPS Millennium and
>> 364 Olivetti M700-10 workstations.
>> 365
>> 366 config MACH_INGENIC
>> 367 bool "Ingenic SoC based machines"
>> 368 select SYS_SUPPORTS_32BIT_KERNEL
>> 369 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 370 select SYS_SUPPORTS_ZBOOT_UART16550
>> 371 select DMA_NONCOHERENT
>> 372 select IRQ_MIPS_CPU
>> 373 select PINCTRL
>> 374 select GPIOLIB
>> 375 select COMMON_CLK
>> 376 select GENERIC_IRQ_CHIP
>> 377 select BUILTIN_DTB
>> 378 select USE_OF
>> 379 select LIBFDT
331 380
332 config ARCH_MMAP_RND_COMPAT_BITS_MIN !! 381 config LANTIQ
333 default 7 if ARM64_64K_PAGES !! 382 bool "Lantiq based platforms"
334 default 9 if ARM64_16K_PAGES !! 383 select DMA_NONCOHERENT
335 default 11 !! 384 select IRQ_MIPS_CPU
>> 385 select CEVT_R4K
>> 386 select CSRC_R4K
>> 387 select SYS_HAS_CPU_MIPS32_R1
>> 388 select SYS_HAS_CPU_MIPS32_R2
>> 389 select SYS_SUPPORTS_BIG_ENDIAN
>> 390 select SYS_SUPPORTS_32BIT_KERNEL
>> 391 select SYS_SUPPORTS_MIPS16
>> 392 select SYS_SUPPORTS_MULTITHREADING
>> 393 select SYS_SUPPORTS_VPE_LOADER
>> 394 select SYS_HAS_EARLY_PRINTK
>> 395 select GPIOLIB
>> 396 select SWAP_IO_SPACE
>> 397 select BOOT_RAW
>> 398 select CLKDEV_LOOKUP
>> 399 select USE_OF
>> 400 select PINCTRL
>> 401 select PINCTRL_LANTIQ
>> 402 select ARCH_HAS_RESET_CONTROLLER
>> 403 select RESET_CONTROLLER
>> 404
>> 405 config LASAT
>> 406 bool "LASAT Networks platforms"
>> 407 select CEVT_R4K
>> 408 select CRC32
>> 409 select CSRC_R4K
>> 410 select DMA_NONCOHERENT
>> 411 select SYS_HAS_EARLY_PRINTK
>> 412 select HW_HAS_PCI
>> 413 select IRQ_MIPS_CPU
>> 414 select PCI_GT64XXX_PCI0
>> 415 select MIPS_NILE4
>> 416 select R5000_CPU_SCACHE
>> 417 select SYS_HAS_CPU_R5000
>> 418 select SYS_SUPPORTS_32BIT_KERNEL
>> 419 select SYS_SUPPORTS_64BIT_KERNEL if BROKEN
>> 420 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 421
>> 422 config MACH_LOONGSON32
>> 423 bool "Loongson-1 family of machines"
>> 424 select SYS_SUPPORTS_ZBOOT
>> 425 help
>> 426 This enables support for the Loongson-1 family of machines.
>> 427
>> 428 Loongson-1 is a family of 32-bit MIPS-compatible SoCs developed by
>> 429 the Institute of Computing Technology (ICT), Chinese Academy of
>> 430 Sciences (CAS).
>> 431
>> 432 config MACH_LOONGSON64
>> 433 bool "Loongson-2/3 family of machines"
>> 434 select SYS_SUPPORTS_ZBOOT
>> 435 help
>> 436 This enables the support of Loongson-2/3 family of machines.
>> 437
>> 438 Loongson-2 is a family of single-core CPUs and Loongson-3 is a
>> 439 family of multi-core CPUs. They are both 64-bit general-purpose
>> 440 MIPS-compatible CPUs. Loongson-2/3 are developed by the Institute
>> 441 of Computing Technology (ICT), Chinese Academy of Sciences (CAS)
>> 442 in the People's Republic of China. The chief architect is Professor
>> 443 Weiwu Hu.
>> 444
>> 445 config MACH_PISTACHIO
>> 446 bool "IMG Pistachio SoC based boards"
>> 447 select BOOT_ELF32
>> 448 select BOOT_RAW
>> 449 select CEVT_R4K
>> 450 select CLKSRC_MIPS_GIC
>> 451 select COMMON_CLK
>> 452 select CSRC_R4K
>> 453 select DMA_NONCOHERENT
>> 454 select GPIOLIB
>> 455 select IRQ_MIPS_CPU
>> 456 select LIBFDT
>> 457 select MFD_SYSCON
>> 458 select MIPS_CPU_SCACHE
>> 459 select MIPS_GIC
>> 460 select PINCTRL
>> 461 select REGULATOR
>> 462 select SYS_HAS_CPU_MIPS32_R2
>> 463 select SYS_SUPPORTS_32BIT_KERNEL
>> 464 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 465 select SYS_SUPPORTS_MIPS_CPS
>> 466 select SYS_SUPPORTS_MULTITHREADING
>> 467 select SYS_SUPPORTS_RELOCATABLE
>> 468 select SYS_SUPPORTS_ZBOOT
>> 469 select SYS_HAS_EARLY_PRINTK
>> 470 select USE_GENERIC_EARLY_PRINTK_8250
>> 471 select USE_OF
>> 472 help
>> 473 This enables support for the IMG Pistachio SoC platform.
>> 474
>> 475 config MIPS_MALTA
>> 476 bool "MIPS Malta board"
>> 477 select ARCH_MAY_HAVE_PC_FDC
>> 478 select BOOT_ELF32
>> 479 select BOOT_RAW
>> 480 select BUILTIN_DTB
>> 481 select CEVT_R4K
>> 482 select CSRC_R4K
>> 483 select CLKSRC_MIPS_GIC
>> 484 select COMMON_CLK
>> 485 select DMA_MAYBE_COHERENT
>> 486 select GENERIC_ISA_DMA
>> 487 select HAVE_PCSPKR_PLATFORM
>> 488 select IRQ_MIPS_CPU
>> 489 select MIPS_GIC
>> 490 select HW_HAS_PCI
>> 491 select I8253
>> 492 select I8259
>> 493 select MIPS_BONITO64
>> 494 select MIPS_CPU_SCACHE
>> 495 select MIPS_L1_CACHE_SHIFT_6
>> 496 select PCI_GT64XXX_PCI0
>> 497 select MIPS_MSC
>> 498 select SMP_UP if SMP
>> 499 select SWAP_IO_SPACE
>> 500 select SYS_HAS_CPU_MIPS32_R1
>> 501 select SYS_HAS_CPU_MIPS32_R2
>> 502 select SYS_HAS_CPU_MIPS32_R3_5
>> 503 select SYS_HAS_CPU_MIPS32_R5
>> 504 select SYS_HAS_CPU_MIPS32_R6
>> 505 select SYS_HAS_CPU_MIPS64_R1
>> 506 select SYS_HAS_CPU_MIPS64_R2
>> 507 select SYS_HAS_CPU_MIPS64_R6
>> 508 select SYS_HAS_CPU_NEVADA
>> 509 select SYS_HAS_CPU_RM7000
>> 510 select SYS_SUPPORTS_32BIT_KERNEL
>> 511 select SYS_SUPPORTS_64BIT_KERNEL
>> 512 select SYS_SUPPORTS_BIG_ENDIAN
>> 513 select SYS_SUPPORTS_HIGHMEM
>> 514 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 515 select SYS_SUPPORTS_MICROMIPS
>> 516 select SYS_SUPPORTS_MIPS_CMP
>> 517 select SYS_SUPPORTS_MIPS_CPS
>> 518 select SYS_SUPPORTS_MIPS16
>> 519 select SYS_SUPPORTS_MULTITHREADING
>> 520 select SYS_SUPPORTS_SMARTMIPS
>> 521 select SYS_SUPPORTS_VPE_LOADER
>> 522 select SYS_SUPPORTS_ZBOOT
>> 523 select SYS_SUPPORTS_RELOCATABLE
>> 524 select USE_OF
>> 525 select LIBFDT
>> 526 select ZONE_DMA32 if 64BIT
>> 527 select BUILTIN_DTB
>> 528 select LIBFDT
>> 529 help
>> 530 This enables support for the MIPS Technologies Malta evaluation
>> 531 board.
336 532
337 config ARCH_MMAP_RND_COMPAT_BITS_MAX !! 533 config MACH_PIC32
338 default 16 !! 534 bool "Microchip PIC32 Family"
>> 535 help
>> 536 This enables support for the Microchip PIC32 family of platforms.
339 537
340 config NO_IOPORT_MAP !! 538 Microchip PIC32 is a family of general-purpose 32 bit MIPS core
341 def_bool y if !PCI !! 539 microcontrollers.
>> 540
>> 541 config NEC_MARKEINS
>> 542 bool "NEC EMMA2RH Mark-eins board"
>> 543 select SOC_EMMA2RH
>> 544 select HW_HAS_PCI
>> 545 help
>> 546 This enables support for the NEC Electronics Mark-eins boards.
>> 547
>> 548 config MACH_VR41XX
>> 549 bool "NEC VR4100 series based machines"
>> 550 select CEVT_R4K
>> 551 select CSRC_R4K
>> 552 select SYS_HAS_CPU_VR41XX
>> 553 select SYS_SUPPORTS_MIPS16
>> 554 select GPIOLIB
>> 555
>> 556 config NXP_STB220
>> 557 bool "NXP STB220 board"
>> 558 select SOC_PNX833X
>> 559 help
>> 560 Support for NXP Semiconductors STB220 Development Board.
>> 561
>> 562 config NXP_STB225
>> 563 bool "NXP 225 board"
>> 564 select SOC_PNX833X
>> 565 select SOC_PNX8335
>> 566 help
>> 567 Support for NXP Semiconductors STB225 Development Board.
>> 568
>> 569 config PMC_MSP
>> 570 bool "PMC-Sierra MSP chipsets"
>> 571 select CEVT_R4K
>> 572 select CSRC_R4K
>> 573 select DMA_NONCOHERENT
>> 574 select SWAP_IO_SPACE
>> 575 select NO_EXCEPT_FILL
>> 576 select BOOT_RAW
>> 577 select SYS_HAS_CPU_MIPS32_R1
>> 578 select SYS_HAS_CPU_MIPS32_R2
>> 579 select SYS_SUPPORTS_32BIT_KERNEL
>> 580 select SYS_SUPPORTS_BIG_ENDIAN
>> 581 select SYS_SUPPORTS_MIPS16
>> 582 select IRQ_MIPS_CPU
>> 583 select SERIAL_8250
>> 584 select SERIAL_8250_CONSOLE
>> 585 select USB_EHCI_BIG_ENDIAN_MMIO
>> 586 select USB_EHCI_BIG_ENDIAN_DESC
>> 587 help
>> 588 This adds support for the PMC-Sierra family of Multi-Service
>> 589 Processor System-On-A-Chips. These parts include a number
>> 590 of integrated peripherals, interfaces and DSPs in addition to
>> 591 a variety of MIPS cores.
>> 592
>> 593 config RALINK
>> 594 bool "Ralink based machines"
>> 595 select CEVT_R4K
>> 596 select CSRC_R4K
>> 597 select BOOT_RAW
>> 598 select DMA_NONCOHERENT
>> 599 select IRQ_MIPS_CPU
>> 600 select USE_OF
>> 601 select SYS_HAS_CPU_MIPS32_R1
>> 602 select SYS_HAS_CPU_MIPS32_R2
>> 603 select SYS_SUPPORTS_32BIT_KERNEL
>> 604 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 605 select SYS_SUPPORTS_MIPS16
>> 606 select SYS_HAS_EARLY_PRINTK
>> 607 select CLKDEV_LOOKUP
>> 608 select ARCH_HAS_RESET_CONTROLLER
>> 609 select RESET_CONTROLLER
>> 610
>> 611 config SGI_IP22
>> 612 bool "SGI IP22 (Indy/Indigo2)"
>> 613 select FW_ARC
>> 614 select FW_ARC32
>> 615 select BOOT_ELF32
>> 616 select CEVT_R4K
>> 617 select CSRC_R4K
>> 618 select DEFAULT_SGI_PARTITION
>> 619 select DMA_NONCOHERENT
>> 620 select HW_HAS_EISA
>> 621 select I8253
>> 622 select I8259
>> 623 select IP22_CPU_SCACHE
>> 624 select IRQ_MIPS_CPU
>> 625 select GENERIC_ISA_DMA_SUPPORT_BROKEN
>> 626 select SGI_HAS_I8042
>> 627 select SGI_HAS_INDYDOG
>> 628 select SGI_HAS_HAL2
>> 629 select SGI_HAS_SEEQ
>> 630 select SGI_HAS_WD93
>> 631 select SGI_HAS_ZILOG
>> 632 select SWAP_IO_SPACE
>> 633 select SYS_HAS_CPU_R4X00
>> 634 select SYS_HAS_CPU_R5000
>> 635 #
>> 636 # Disable EARLY_PRINTK for now since it leads to overwritten prom
>> 637 # memory during early boot on some machines.
>> 638 #
>> 639 # See http://www.linux-mips.org/cgi-bin/mesg.cgi?a=linux-mips&i=20091119164009.GA15038%40deprecation.cyrius.com
>> 640 # for a more details discussion
>> 641 #
>> 642 # select SYS_HAS_EARLY_PRINTK
>> 643 select SYS_SUPPORTS_32BIT_KERNEL
>> 644 select SYS_SUPPORTS_64BIT_KERNEL
>> 645 select SYS_SUPPORTS_BIG_ENDIAN
>> 646 select MIPS_L1_CACHE_SHIFT_7
>> 647 help
>> 648 This are the SGI Indy, Challenge S and Indigo2, as well as certain
>> 649 OEM variants like the Tandem CMN B006S. To compile a Linux kernel
>> 650 that runs on these, say Y here.
>> 651
>> 652 config SGI_IP27
>> 653 bool "SGI IP27 (Origin200/2000)"
>> 654 select FW_ARC
>> 655 select FW_ARC64
>> 656 select BOOT_ELF64
>> 657 select DEFAULT_SGI_PARTITION
>> 658 select DMA_COHERENT
>> 659 select SYS_HAS_EARLY_PRINTK
>> 660 select HW_HAS_PCI
>> 661 select NR_CPUS_DEFAULT_64
>> 662 select SYS_HAS_CPU_R10000
>> 663 select SYS_SUPPORTS_64BIT_KERNEL
>> 664 select SYS_SUPPORTS_BIG_ENDIAN
>> 665 select SYS_SUPPORTS_NUMA
>> 666 select SYS_SUPPORTS_SMP
>> 667 select MIPS_L1_CACHE_SHIFT_7
>> 668 help
>> 669 This are the SGI Origin 200, Origin 2000 and Onyx 2 Graphics
>> 670 workstations. To compile a Linux kernel that runs on these, say Y
>> 671 here.
>> 672
>> 673 config SGI_IP28
>> 674 bool "SGI IP28 (Indigo2 R10k)"
>> 675 select FW_ARC
>> 676 select FW_ARC64
>> 677 select BOOT_ELF64
>> 678 select CEVT_R4K
>> 679 select CSRC_R4K
>> 680 select DEFAULT_SGI_PARTITION
>> 681 select DMA_NONCOHERENT
>> 682 select GENERIC_ISA_DMA_SUPPORT_BROKEN
>> 683 select IRQ_MIPS_CPU
>> 684 select HW_HAS_EISA
>> 685 select I8253
>> 686 select I8259
>> 687 select SGI_HAS_I8042
>> 688 select SGI_HAS_INDYDOG
>> 689 select SGI_HAS_HAL2
>> 690 select SGI_HAS_SEEQ
>> 691 select SGI_HAS_WD93
>> 692 select SGI_HAS_ZILOG
>> 693 select SWAP_IO_SPACE
>> 694 select SYS_HAS_CPU_R10000
>> 695 #
>> 696 # Disable EARLY_PRINTK for now since it leads to overwritten prom
>> 697 # memory during early boot on some machines.
>> 698 #
>> 699 # See http://www.linux-mips.org/cgi-bin/mesg.cgi?a=linux-mips&i=20091119164009.GA15038%40deprecation.cyrius.com
>> 700 # for a more details discussion
>> 701 #
>> 702 # select SYS_HAS_EARLY_PRINTK
>> 703 select SYS_SUPPORTS_64BIT_KERNEL
>> 704 select SYS_SUPPORTS_BIG_ENDIAN
>> 705 select MIPS_L1_CACHE_SHIFT_7
>> 706 help
>> 707 This is the SGI Indigo2 with R10000 processor. To compile a Linux
>> 708 kernel that runs on these, say Y here.
>> 709
>> 710 config SGI_IP32
>> 711 bool "SGI IP32 (O2)"
>> 712 select FW_ARC
>> 713 select FW_ARC32
>> 714 select BOOT_ELF32
>> 715 select CEVT_R4K
>> 716 select CSRC_R4K
>> 717 select DMA_NONCOHERENT
>> 718 select HW_HAS_PCI
>> 719 select IRQ_MIPS_CPU
>> 720 select R5000_CPU_SCACHE
>> 721 select RM7000_CPU_SCACHE
>> 722 select SYS_HAS_CPU_R5000
>> 723 select SYS_HAS_CPU_R10000 if BROKEN
>> 724 select SYS_HAS_CPU_RM7000
>> 725 select SYS_HAS_CPU_NEVADA
>> 726 select SYS_SUPPORTS_64BIT_KERNEL
>> 727 select SYS_SUPPORTS_BIG_ENDIAN
>> 728 help
>> 729 If you want this kernel to run on SGI O2 workstation, say Y here.
>> 730
>> 731 config SIBYTE_CRHINE
>> 732 bool "Sibyte BCM91120C-CRhine"
>> 733 select BOOT_ELF32
>> 734 select DMA_COHERENT
>> 735 select SIBYTE_BCM1120
>> 736 select SWAP_IO_SPACE
>> 737 select SYS_HAS_CPU_SB1
>> 738 select SYS_SUPPORTS_BIG_ENDIAN
>> 739 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 740
>> 741 config SIBYTE_CARMEL
>> 742 bool "Sibyte BCM91120x-Carmel"
>> 743 select BOOT_ELF32
>> 744 select DMA_COHERENT
>> 745 select SIBYTE_BCM1120
>> 746 select SWAP_IO_SPACE
>> 747 select SYS_HAS_CPU_SB1
>> 748 select SYS_SUPPORTS_BIG_ENDIAN
>> 749 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 750
>> 751 config SIBYTE_CRHONE
>> 752 bool "Sibyte BCM91125C-CRhone"
>> 753 select BOOT_ELF32
>> 754 select DMA_COHERENT
>> 755 select SIBYTE_BCM1125
>> 756 select SWAP_IO_SPACE
>> 757 select SYS_HAS_CPU_SB1
>> 758 select SYS_SUPPORTS_BIG_ENDIAN
>> 759 select SYS_SUPPORTS_HIGHMEM
>> 760 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 761
>> 762 config SIBYTE_RHONE
>> 763 bool "Sibyte BCM91125E-Rhone"
>> 764 select BOOT_ELF32
>> 765 select DMA_COHERENT
>> 766 select SIBYTE_BCM1125H
>> 767 select SWAP_IO_SPACE
>> 768 select SYS_HAS_CPU_SB1
>> 769 select SYS_SUPPORTS_BIG_ENDIAN
>> 770 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 771
>> 772 config SIBYTE_SWARM
>> 773 bool "Sibyte BCM91250A-SWARM"
>> 774 select BOOT_ELF32
>> 775 select DMA_COHERENT
>> 776 select HAVE_PATA_PLATFORM
>> 777 select SIBYTE_SB1250
>> 778 select SWAP_IO_SPACE
>> 779 select SYS_HAS_CPU_SB1
>> 780 select SYS_SUPPORTS_BIG_ENDIAN
>> 781 select SYS_SUPPORTS_HIGHMEM
>> 782 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 783 select ZONE_DMA32 if 64BIT
>> 784
>> 785 config SIBYTE_LITTLESUR
>> 786 bool "Sibyte BCM91250C2-LittleSur"
>> 787 select BOOT_ELF32
>> 788 select DMA_COHERENT
>> 789 select HAVE_PATA_PLATFORM
>> 790 select SIBYTE_SB1250
>> 791 select SWAP_IO_SPACE
>> 792 select SYS_HAS_CPU_SB1
>> 793 select SYS_SUPPORTS_BIG_ENDIAN
>> 794 select SYS_SUPPORTS_HIGHMEM
>> 795 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 796
>> 797 config SIBYTE_SENTOSA
>> 798 bool "Sibyte BCM91250E-Sentosa"
>> 799 select BOOT_ELF32
>> 800 select DMA_COHERENT
>> 801 select SIBYTE_SB1250
>> 802 select SWAP_IO_SPACE
>> 803 select SYS_HAS_CPU_SB1
>> 804 select SYS_SUPPORTS_BIG_ENDIAN
>> 805 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 806
>> 807 config SIBYTE_BIGSUR
>> 808 bool "Sibyte BCM91480B-BigSur"
>> 809 select BOOT_ELF32
>> 810 select DMA_COHERENT
>> 811 select NR_CPUS_DEFAULT_4
>> 812 select SIBYTE_BCM1x80
>> 813 select SWAP_IO_SPACE
>> 814 select SYS_HAS_CPU_SB1
>> 815 select SYS_SUPPORTS_BIG_ENDIAN
>> 816 select SYS_SUPPORTS_HIGHMEM
>> 817 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 818 select ZONE_DMA32 if 64BIT
>> 819
>> 820 config SNI_RM
>> 821 bool "SNI RM200/300/400"
>> 822 select FW_ARC if CPU_LITTLE_ENDIAN
>> 823 select FW_ARC32 if CPU_LITTLE_ENDIAN
>> 824 select FW_SNIPROM if CPU_BIG_ENDIAN
>> 825 select ARCH_MAY_HAVE_PC_FDC
>> 826 select BOOT_ELF32
>> 827 select CEVT_R4K
>> 828 select CSRC_R4K
>> 829 select DEFAULT_SGI_PARTITION if CPU_BIG_ENDIAN
>> 830 select DMA_NONCOHERENT
>> 831 select GENERIC_ISA_DMA
>> 832 select HAVE_PCSPKR_PLATFORM
>> 833 select HW_HAS_EISA
>> 834 select HW_HAS_PCI
>> 835 select IRQ_MIPS_CPU
>> 836 select I8253
>> 837 select I8259
>> 838 select ISA
>> 839 select SWAP_IO_SPACE if CPU_BIG_ENDIAN
>> 840 select SYS_HAS_CPU_R4X00
>> 841 select SYS_HAS_CPU_R5000
>> 842 select SYS_HAS_CPU_R10000
>> 843 select R5000_CPU_SCACHE
>> 844 select SYS_HAS_EARLY_PRINTK
>> 845 select SYS_SUPPORTS_32BIT_KERNEL
>> 846 select SYS_SUPPORTS_64BIT_KERNEL
>> 847 select SYS_SUPPORTS_BIG_ENDIAN
>> 848 select SYS_SUPPORTS_HIGHMEM
>> 849 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 850 help
>> 851 The SNI RM200/300/400 are MIPS-based machines manufactured by
>> 852 Siemens Nixdorf Informationssysteme (SNI), parent company of Pyramid
>> 853 Technology and now in turn merged with Fujitsu. Say Y here to
>> 854 support this machine type.
>> 855
>> 856 config MACH_TX39XX
>> 857 bool "Toshiba TX39 series based machines"
>> 858
>> 859 config MACH_TX49XX
>> 860 bool "Toshiba TX49 series based machines"
>> 861
>> 862 config MIKROTIK_RB532
>> 863 bool "Mikrotik RB532 boards"
>> 864 select CEVT_R4K
>> 865 select CSRC_R4K
>> 866 select DMA_NONCOHERENT
>> 867 select HW_HAS_PCI
>> 868 select IRQ_MIPS_CPU
>> 869 select SYS_HAS_CPU_MIPS32_R1
>> 870 select SYS_SUPPORTS_32BIT_KERNEL
>> 871 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 872 select SWAP_IO_SPACE
>> 873 select BOOT_RAW
>> 874 select GPIOLIB
>> 875 select MIPS_L1_CACHE_SHIFT_4
>> 876 help
>> 877 Support the Mikrotik(tm) RouterBoard 532 series,
>> 878 based on the IDT RC32434 SoC.
>> 879
>> 880 config CAVIUM_OCTEON_SOC
>> 881 bool "Cavium Networks Octeon SoC based boards"
>> 882 select CEVT_R4K
>> 883 select ARCH_PHYS_ADDR_T_64BIT
>> 884 select DMA_COHERENT
>> 885 select SYS_SUPPORTS_64BIT_KERNEL
>> 886 select SYS_SUPPORTS_BIG_ENDIAN
>> 887 select EDAC_SUPPORT
>> 888 select EDAC_ATOMIC_SCRUB
>> 889 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 890 select SYS_SUPPORTS_HOTPLUG_CPU if CPU_BIG_ENDIAN
>> 891 select SYS_HAS_EARLY_PRINTK
>> 892 select SYS_HAS_CPU_CAVIUM_OCTEON
>> 893 select HW_HAS_PCI
>> 894 select ZONE_DMA32
>> 895 select HOLES_IN_ZONE
>> 896 select GPIOLIB
>> 897 select LIBFDT
>> 898 select USE_OF
>> 899 select ARCH_SPARSEMEM_ENABLE
>> 900 select SYS_SUPPORTS_SMP
>> 901 select NR_CPUS_DEFAULT_64
>> 902 select MIPS_NR_CPU_NR_MAP_1024
>> 903 select BUILTIN_DTB
>> 904 select MTD_COMPLEX_MAPPINGS
>> 905 select SYS_SUPPORTS_RELOCATABLE
>> 906 help
>> 907 This option supports all of the Octeon reference boards from Cavium
>> 908 Networks. It builds a kernel that dynamically determines the Octeon
>> 909 CPU type and supports all known board reference implementations.
>> 910 Some of the supported boards are:
>> 911 EBT3000
>> 912 EBH3000
>> 913 EBH3100
>> 914 Thunder
>> 915 Kodama
>> 916 Hikari
>> 917 Say Y here for most Octeon reference boards.
>> 918
>> 919 config NLM_XLR_BOARD
>> 920 bool "Netlogic XLR/XLS based systems"
>> 921 select BOOT_ELF32
>> 922 select NLM_COMMON
>> 923 select SYS_HAS_CPU_XLR
>> 924 select SYS_SUPPORTS_SMP
>> 925 select HW_HAS_PCI
>> 926 select SWAP_IO_SPACE
>> 927 select SYS_SUPPORTS_32BIT_KERNEL
>> 928 select SYS_SUPPORTS_64BIT_KERNEL
>> 929 select ARCH_PHYS_ADDR_T_64BIT
>> 930 select SYS_SUPPORTS_BIG_ENDIAN
>> 931 select SYS_SUPPORTS_HIGHMEM
>> 932 select DMA_COHERENT
>> 933 select NR_CPUS_DEFAULT_32
>> 934 select CEVT_R4K
>> 935 select CSRC_R4K
>> 936 select IRQ_MIPS_CPU
>> 937 select ZONE_DMA32 if 64BIT
>> 938 select SYNC_R4K
>> 939 select SYS_HAS_EARLY_PRINTK
>> 940 select SYS_SUPPORTS_ZBOOT
>> 941 select SYS_SUPPORTS_ZBOOT_UART16550
>> 942 help
>> 943 Support for systems based on Netlogic XLR and XLS processors.
>> 944 Say Y here if you have a XLR or XLS based board.
>> 945
>> 946 config NLM_XLP_BOARD
>> 947 bool "Netlogic XLP based systems"
>> 948 select BOOT_ELF32
>> 949 select NLM_COMMON
>> 950 select SYS_HAS_CPU_XLP
>> 951 select SYS_SUPPORTS_SMP
>> 952 select HW_HAS_PCI
>> 953 select SYS_SUPPORTS_32BIT_KERNEL
>> 954 select SYS_SUPPORTS_64BIT_KERNEL
>> 955 select ARCH_PHYS_ADDR_T_64BIT
>> 956 select GPIOLIB
>> 957 select SYS_SUPPORTS_BIG_ENDIAN
>> 958 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 959 select SYS_SUPPORTS_HIGHMEM
>> 960 select DMA_COHERENT
>> 961 select NR_CPUS_DEFAULT_32
>> 962 select CEVT_R4K
>> 963 select CSRC_R4K
>> 964 select IRQ_MIPS_CPU
>> 965 select ZONE_DMA32 if 64BIT
>> 966 select SYNC_R4K
>> 967 select SYS_HAS_EARLY_PRINTK
>> 968 select USE_OF
>> 969 select SYS_SUPPORTS_ZBOOT
>> 970 select SYS_SUPPORTS_ZBOOT_UART16550
>> 971 help
>> 972 This board is based on Netlogic XLP Processor.
>> 973 Say Y here if you have a XLP based board.
>> 974
>> 975 config MIPS_PARAVIRT
>> 976 bool "Para-Virtualized guest system"
>> 977 select CEVT_R4K
>> 978 select CSRC_R4K
>> 979 select DMA_COHERENT
>> 980 select SYS_SUPPORTS_64BIT_KERNEL
>> 981 select SYS_SUPPORTS_32BIT_KERNEL
>> 982 select SYS_SUPPORTS_BIG_ENDIAN
>> 983 select SYS_SUPPORTS_SMP
>> 984 select NR_CPUS_DEFAULT_4
>> 985 select SYS_HAS_EARLY_PRINTK
>> 986 select SYS_HAS_CPU_MIPS32_R2
>> 987 select SYS_HAS_CPU_MIPS64_R2
>> 988 select SYS_HAS_CPU_CAVIUM_OCTEON
>> 989 select HW_HAS_PCI
>> 990 select SWAP_IO_SPACE
>> 991 help
>> 992 This option supports guest running under ????
342 993
343 config STACKTRACE_SUPPORT !! 994 endchoice
344 def_bool y <<
345 995
346 config ILLEGAL_POINTER_VALUE !! 996 source "arch/mips/alchemy/Kconfig"
347 hex !! 997 source "arch/mips/ath25/Kconfig"
348 default 0xdead000000000000 !! 998 source "arch/mips/ath79/Kconfig"
>> 999 source "arch/mips/bcm47xx/Kconfig"
>> 1000 source "arch/mips/bcm63xx/Kconfig"
>> 1001 source "arch/mips/bmips/Kconfig"
>> 1002 source "arch/mips/generic/Kconfig"
>> 1003 source "arch/mips/jazz/Kconfig"
>> 1004 source "arch/mips/jz4740/Kconfig"
>> 1005 source "arch/mips/lantiq/Kconfig"
>> 1006 source "arch/mips/lasat/Kconfig"
>> 1007 source "arch/mips/pic32/Kconfig"
>> 1008 source "arch/mips/pistachio/Kconfig"
>> 1009 source "arch/mips/pmcs-msp71xx/Kconfig"
>> 1010 source "arch/mips/ralink/Kconfig"
>> 1011 source "arch/mips/sgi-ip27/Kconfig"
>> 1012 source "arch/mips/sibyte/Kconfig"
>> 1013 source "arch/mips/txx9/Kconfig"
>> 1014 source "arch/mips/vr41xx/Kconfig"
>> 1015 source "arch/mips/cavium-octeon/Kconfig"
>> 1016 source "arch/mips/loongson32/Kconfig"
>> 1017 source "arch/mips/loongson64/Kconfig"
>> 1018 source "arch/mips/netlogic/Kconfig"
>> 1019 source "arch/mips/paravirt/Kconfig"
349 1020
350 config LOCKDEP_SUPPORT !! 1021 endmenu
351 def_bool y <<
352 1022
353 config GENERIC_BUG !! 1023 config RWSEM_GENERIC_SPINLOCK
354 def_bool y !! 1024 bool
355 depends on BUG !! 1025 default y
356 1026
357 config GENERIC_BUG_RELATIVE_POINTERS !! 1027 config RWSEM_XCHGADD_ALGORITHM
358 def_bool y !! 1028 bool
359 depends on GENERIC_BUG <<
360 1029
361 config GENERIC_HWEIGHT 1030 config GENERIC_HWEIGHT
362 def_bool y !! 1031 bool
363 !! 1032 default y
364 config GENERIC_CSUM <<
365 def_bool y <<
366 1033
367 config GENERIC_CALIBRATE_DELAY 1034 config GENERIC_CALIBRATE_DELAY
368 def_bool y <<
369 <<
370 config SMP <<
371 def_bool y <<
372 <<
373 config KERNEL_MODE_NEON <<
374 def_bool y <<
375 <<
376 config FIX_EARLYCON_MEM <<
377 def_bool y <<
378 <<
379 config PGTABLE_LEVELS <<
380 int <<
381 default 2 if ARM64_16K_PAGES && ARM64_ <<
382 default 2 if ARM64_64K_PAGES && ARM64_ <<
383 default 3 if ARM64_64K_PAGES && (ARM64 <<
384 default 3 if ARM64_4K_PAGES && ARM64_V <<
385 default 3 if ARM64_16K_PAGES && ARM64_ <<
386 default 4 if ARM64_16K_PAGES && (ARM64 <<
387 default 4 if !ARM64_64K_PAGES && ARM64 <<
388 default 5 if ARM64_4K_PAGES && ARM64_V <<
389 <<
390 config ARCH_SUPPORTS_UPROBES <<
391 def_bool y <<
392 <<
393 config ARCH_PROC_KCORE_TEXT <<
394 def_bool y <<
395 <<
396 config BROKEN_GAS_INST <<
397 def_bool !$(as-instr,1:\n.inst 0\n.rep <<
398 <<
399 config BUILTIN_RETURN_ADDRESS_STRIPS_PAC <<
400 bool 1035 bool
401 # Clang's __builtin_return_address() s !! 1036 default y
402 # https://github.com/llvm/llvm-project <<
403 default y if CC_IS_CLANG <<
404 # GCC's __builtin_return_address() str <<
405 # and this was backported to 10.2.0, 9 <<
406 # https://gcc.gnu.org/bugzilla/show_bu <<
407 default y if CC_IS_GCC && (GCC_VERSION <<
408 default y if CC_IS_GCC && (GCC_VERSION <<
409 default y if CC_IS_GCC && (GCC_VERSION <<
410 default y if CC_IS_GCC && (GCC_VERSION <<
411 default n <<
412 <<
413 config KASAN_SHADOW_OFFSET <<
414 hex <<
415 depends on KASAN_GENERIC || KASAN_SW_T <<
416 default 0xdfff800000000000 if (ARM64_V <<
417 default 0xdfffc00000000000 if (ARM64_V <<
418 default 0xdffffe0000000000 if ARM64_VA <<
419 default 0xdfffffc000000000 if ARM64_VA <<
420 default 0xdffffff800000000 if ARM64_VA <<
421 default 0xefff800000000000 if (ARM64_V <<
422 default 0xefffc00000000000 if (ARM64_V <<
423 default 0xeffffe0000000000 if ARM64_VA <<
424 default 0xefffffc000000000 if ARM64_VA <<
425 default 0xeffffff800000000 if ARM64_VA <<
426 default 0xffffffffffffffff <<
427 <<
428 config UNWIND_TABLES <<
429 bool <<
430 <<
431 source "arch/arm64/Kconfig.platforms" <<
432 <<
433 menu "Kernel Features" <<
434 <<
435 menu "ARM errata workarounds via the alternati <<
436 <<
437 config AMPERE_ERRATUM_AC03_CPU_38 <<
438 bool "AmpereOne: AC03_CPU_38: Certain <<
439 default y <<
440 help <<
441 This option adds an alternative code <<
442 errata AC03_CPU_38 and AC04_CPU_10 o <<
443 <<
444 The affected design reports FEAT_HAF <<
445 ID_AA64MMFR1_EL1.HAFDBS, but (V)TCR_ <<
446 as required by the architecture. The <<
447 implementation suffers from an addit <<
448 A/D updates can occur after a PTE ha <<
449 <<
450 The workaround forces KVM to explici <<
451 which avoids enabling unadvertised h <<
452 at stage-2. <<
453 <<
454 If unsure, say Y. <<
455 1037
456 config ARM64_WORKAROUND_CLEAN_CACHE !! 1038 config SCHED_OMIT_FRAME_POINTER
457 bool 1039 bool
458 <<
459 config ARM64_ERRATUM_826319 <<
460 bool "Cortex-A53: 826319: System might <<
461 default y 1040 default y
462 select ARM64_WORKAROUND_CLEAN_CACHE <<
463 help <<
464 This option adds an alternative code <<
465 erratum 826319 on Cortex-A53 parts u <<
466 AXI master interface and an L2 cache <<
467 1041
468 If a Cortex-A53 uses an AMBA AXI4 AC !! 1042 #
469 and is unable to accept a certain wr !! 1043 # Select some configuration options automatically based on user selections.
470 not progress on read data presented !! 1044 #
471 system can deadlock. !! 1045 config FW_ARC
472 !! 1046 bool
473 The workaround promotes data cache c <<
474 data cache clean-and-invalidate. <<
475 Please note that this does not neces <<
476 as it depends on the alternative fra <<
477 the kernel if an affected CPU is det <<
478 <<
479 If unsure, say Y. <<
480 <<
481 config ARM64_ERRATUM_827319 <<
482 bool "Cortex-A53: 827319: Data cache c <<
483 default y <<
484 select ARM64_WORKAROUND_CLEAN_CACHE <<
485 help <<
486 This option adds an alternative code <<
487 erratum 827319 on Cortex-A53 parts u <<
488 master interface and an L2 cache. <<
489 <<
490 Under certain conditions this erratu <<
491 to occur at the same time as another <<
492 on the AMBA 5 CHI interface, which c <<
493 interconnect reorders the two transa <<
494 <<
495 The workaround promotes data cache c <<
496 data cache clean-and-invalidate. <<
497 Please note that this does not neces <<
498 as it depends on the alternative fra <<
499 the kernel if an affected CPU is det <<
500 1047
501 If unsure, say Y. !! 1048 config ARCH_MAY_HAVE_PC_FDC
>> 1049 bool
502 1050
503 config ARM64_ERRATUM_824069 !! 1051 config BOOT_RAW
504 bool "Cortex-A53: 824069: Cache line m !! 1052 bool
505 default y <<
506 select ARM64_WORKAROUND_CLEAN_CACHE <<
507 help <<
508 This option adds an alternative code <<
509 erratum 824069 on Cortex-A53 parts u <<
510 to a coherent interconnect. <<
511 <<
512 If a Cortex-A53 processor is executi <<
513 write instruction at the same time a <<
514 cluster is executing a cache mainten <<
515 address, then this erratum might cau <<
516 incorrectly marked as dirty. <<
517 <<
518 The workaround promotes data cache c <<
519 data cache clean-and-invalidate. <<
520 Please note that this option does no <<
521 workaround, as it depends on the alt <<
522 only patch the kernel if an affected <<
523 1053
524 If unsure, say Y. !! 1054 config CEVT_BCM1480
>> 1055 bool
525 1056
526 config ARM64_ERRATUM_819472 !! 1057 config CEVT_DS1287
527 bool "Cortex-A53: 819472: Store exclus !! 1058 bool
528 default y <<
529 select ARM64_WORKAROUND_CLEAN_CACHE <<
530 help <<
531 This option adds an alternative code <<
532 erratum 819472 on Cortex-A53 parts u <<
533 present when it is connected to a co <<
534 <<
535 If the processor is executing a load <<
536 the same time as a processor in anot <<
537 maintenance operation to the same ad <<
538 cause data corruption. <<
539 <<
540 The workaround promotes data cache c <<
541 data cache clean-and-invalidate. <<
542 Please note that this does not neces <<
543 as it depends on the alternative fra <<
544 the kernel if an affected CPU is det <<
545 1059
546 If unsure, say Y. !! 1060 config CEVT_GT641XX
>> 1061 bool
547 1062
548 config ARM64_ERRATUM_832075 !! 1063 config CEVT_R4K
549 bool "Cortex-A57: 832075: possible dea !! 1064 bool
550 default y <<
551 help <<
552 This option adds an alternative code <<
553 erratum 832075 on Cortex-A57 parts u <<
554 1065
555 Affected Cortex-A57 parts might dead !! 1066 config CEVT_SB1250
556 instructions to Write-Back memory ar !! 1067 bool
557 1068
558 The workaround is to promote device !! 1069 config CEVT_TXX9
559 semantics. !! 1070 bool
560 Please note that this does not neces <<
561 as it depends on the alternative fra <<
562 the kernel if an affected CPU is det <<
563 1071
564 If unsure, say Y. !! 1072 config CSRC_BCM1480
>> 1073 bool
565 1074
566 config ARM64_ERRATUM_834220 !! 1075 config CSRC_IOASIC
567 bool "Cortex-A57: 834220: Stage 2 tran !! 1076 bool
568 depends on KVM <<
569 help <<
570 This option adds an alternative code <<
571 erratum 834220 on Cortex-A57 parts u <<
572 <<
573 Affected Cortex-A57 parts might repo <<
574 fault as the result of a Stage 1 fau <<
575 page boundary when there is a permis <<
576 alignment fault at Stage 1 and a tra <<
577 <<
578 The workaround is to verify that the <<
579 doesn't generate a fault before hand <<
580 Please note that this does not neces <<
581 as it depends on the alternative fra <<
582 the kernel if an affected CPU is det <<
583 1077
584 If unsure, say N. !! 1078 config CSRC_R4K
>> 1079 bool
585 1080
586 config ARM64_ERRATUM_1742098 !! 1081 config CSRC_SB1250
587 bool "Cortex-A57/A72: 1742098: ELR rec !! 1082 bool
588 depends on COMPAT <<
589 default y <<
590 help <<
591 This option removes the AES hwcap fo <<
592 workaround erratum 1742098 on Cortex <<
593 <<
594 Affected parts may corrupt the AES s <<
595 taken between a pair of AES instruct <<
596 are only present if the cryptography <<
597 All software should have a fallback <<
598 that don't implement the cryptograph <<
599 1083
600 If unsure, say Y. !! 1084 config MIPS_CLOCK_VSYSCALL
>> 1085 def_bool CSRC_R4K || CLKSRC_MIPS_GIC
601 1086
602 config ARM64_ERRATUM_845719 !! 1087 config GPIO_TXX9
603 bool "Cortex-A53: 845719: a load might !! 1088 select GPIOLIB
604 depends on COMPAT !! 1089 bool
605 default y <<
606 help <<
607 This option adds an alternative code <<
608 erratum 845719 on Cortex-A53 parts u <<
609 <<
610 When running a compat (AArch32) user <<
611 part, a load at EL0 from a virtual a <<
612 bits of the virtual address used by <<
613 might return incorrect data. <<
614 <<
615 The workaround is to write the conte <<
616 return to a 32-bit task. <<
617 Please note that this does not neces <<
618 as it depends on the alternative fra <<
619 the kernel if an affected CPU is det <<
620 1090
621 If unsure, say Y. !! 1091 config FW_CFE
>> 1092 bool
622 1093
623 config ARM64_ERRATUM_843419 !! 1094 config ARCH_DMA_ADDR_T_64BIT
624 bool "Cortex-A53: 843419: A load or st !! 1095 def_bool (HIGHMEM && ARCH_PHYS_ADDR_T_64BIT) || 64BIT
625 default y <<
626 help <<
627 This option links the kernel with '- <<
628 enables PLT support to replace certa <<
629 cause subsequent memory accesses to <<
630 Cortex-A53 parts up to r0p4. <<
631 1096
632 If unsure, say Y. !! 1097 config ARCH_SUPPORTS_UPROBES
>> 1098 bool
633 1099
634 config ARM64_LD_HAS_FIX_ERRATUM_843419 !! 1100 config DMA_MAYBE_COHERENT
635 def_bool $(ld-option,--fix-cortex-a53- !! 1101 select DMA_NONCOHERENT
>> 1102 bool
636 1103
637 config ARM64_ERRATUM_1024718 !! 1104 config DMA_PERDEV_COHERENT
638 bool "Cortex-A55: 1024718: Update of D !! 1105 bool
639 default y !! 1106 select DMA_MAYBE_COHERENT
640 help <<
641 This option adds a workaround for AR <<
642 1107
643 Affected Cortex-A55 cores (all revis !! 1108 config DMA_COHERENT
644 update of the hardware dirty bit whe !! 1109 bool
645 without a break-before-make. The wor <<
646 of hardware DBM locally on the affec <<
647 this erratum will continue to use th <<
648 1110
649 If unsure, say Y. !! 1111 config DMA_NONCOHERENT
>> 1112 bool
>> 1113 select NEED_DMA_MAP_STATE
650 1114
651 config ARM64_ERRATUM_1418040 !! 1115 config NEED_DMA_MAP_STATE
652 bool "Cortex-A76/Neoverse-N1: MRC read !! 1116 bool
653 default y <<
654 depends on COMPAT <<
655 help <<
656 This option adds a workaround for AR <<
657 errata 1188873 and 1418040. <<
658 1117
659 Affected Cortex-A76/Neoverse-N1 core !! 1118 config SYS_HAS_EARLY_PRINTK
660 cause register corruption when acces !! 1119 bool
661 from AArch32 userspace. <<
662 1120
663 If unsure, say Y. !! 1121 config SYS_SUPPORTS_HOTPLUG_CPU
>> 1122 bool
664 1123
665 config ARM64_WORKAROUND_SPECULATIVE_AT !! 1124 config MIPS_BONITO64
666 bool 1125 bool
667 1126
668 config ARM64_ERRATUM_1165522 !! 1127 config MIPS_MSC
669 bool "Cortex-A76: 1165522: Speculative !! 1128 bool
670 default y <<
671 select ARM64_WORKAROUND_SPECULATIVE_AT <<
672 help <<
673 This option adds a workaround for AR <<
674 1129
675 Affected Cortex-A76 cores (r0p0, r1p !! 1130 config MIPS_NILE4
676 corrupted TLBs by speculating an AT !! 1131 bool
677 context switch. <<
678 1132
679 If unsure, say Y. !! 1133 config SYNC_R4K
>> 1134 bool
680 1135
681 config ARM64_ERRATUM_1319367 !! 1136 config MIPS_MACHINE
682 bool "Cortex-A57/A72: 1319537: Specula !! 1137 def_bool n
683 default y <<
684 select ARM64_WORKAROUND_SPECULATIVE_AT <<
685 help <<
686 This option adds work arounds for AR <<
687 and A72 erratum 1319367 <<
688 1138
689 Cortex-A57 and A72 cores could end-u !! 1139 config NO_IOPORT_MAP
690 speculating an AT instruction during !! 1140 def_bool n
691 1141
692 If unsure, say Y. !! 1142 config GENERIC_CSUM
>> 1143 bool
693 1144
694 config ARM64_ERRATUM_1530923 !! 1145 config GENERIC_ISA_DMA
695 bool "Cortex-A55: 1530923: Speculative !! 1146 bool
696 default y !! 1147 select ZONE_DMA if GENERIC_ISA_DMA_SUPPORT_BROKEN=n
697 select ARM64_WORKAROUND_SPECULATIVE_AT !! 1148 select ISA_DMA_API
698 help <<
699 This option adds a workaround for AR <<
700 1149
701 Affected Cortex-A55 cores (r0p0, r0p !! 1150 config GENERIC_ISA_DMA_SUPPORT_BROKEN
702 corrupted TLBs by speculating an AT !! 1151 bool
703 context switch. !! 1152 select GENERIC_ISA_DMA
704 1153
705 If unsure, say Y. !! 1154 config ISA_DMA_API
>> 1155 bool
706 1156
707 config ARM64_WORKAROUND_REPEAT_TLBI !! 1157 config HOLES_IN_ZONE
708 bool 1158 bool
709 1159
710 config ARM64_ERRATUM_2441007 !! 1160 config SYS_SUPPORTS_RELOCATABLE
711 bool "Cortex-A55: Completion of affect !! 1161 bool
712 select ARM64_WORKAROUND_REPEAT_TLBI <<
713 help 1162 help
714 This option adds a workaround for AR !! 1163 Selected if the platform supports relocating the kernel.
715 !! 1164 The platform must provide plat_get_fdt() if it selects CONFIG_USE_OF
716 Under very rare circumstances, affec !! 1165 to allow access to command line and entropy sources.
717 may not handle a race between a brea <<
718 CPU, and another CPU accessing the s <<
719 store to a page that has been unmapp <<
720 1166
721 Work around this by adding the affec !! 1167 config MIPS_CBPF_JIT
722 TLB sequences to be done twice. !! 1168 def_bool y
723 !! 1169 depends on BPF_JIT && HAVE_CBPF_JIT
724 If unsure, say N. <<
725 1170
726 config ARM64_ERRATUM_1286807 !! 1171 config MIPS_EBPF_JIT
727 bool "Cortex-A76: Modification of the !! 1172 def_bool y
728 select ARM64_WORKAROUND_REPEAT_TLBI !! 1173 depends on BPF_JIT && HAVE_EBPF_JIT
729 help <<
730 This option adds a workaround for AR <<
731 <<
732 On the affected Cortex-A76 cores (r0 <<
733 address for a cacheable mapping of a <<
734 accessed by a core while another cor <<
735 address to a new physical page using <<
736 break-before-make sequence, then und <<
737 TLBI+DSB completes before a read usi <<
738 invalidated has been observed by oth <<
739 workaround repeats the TLBI+DSB oper <<
740 1174
741 If unsure, say N. <<
742 1175
743 config ARM64_ERRATUM_1463225 !! 1176 #
744 bool "Cortex-A76: Software Step might !! 1177 # Endianness selection. Sufficiently obscure so many users don't know what to
745 default y !! 1178 # answer,so we try hard to limit the available choices. Also the use of a
>> 1179 # choice statement should be more obvious to the user.
>> 1180 #
>> 1181 choice
>> 1182 prompt "Endianness selection"
746 help 1183 help
747 This option adds a workaround for Ar !! 1184 Some MIPS machines can be configured for either little or big endian
>> 1185 byte order. These modes require different kernels and a different
>> 1186 Linux distribution. In general there is one preferred byteorder for a
>> 1187 particular system but some systems are just as commonly used in the
>> 1188 one or the other endianness.
748 1189
749 On the affected Cortex-A76 cores (r0 !! 1190 config CPU_BIG_ENDIAN
750 of a system call instruction (SVC) c !! 1191 bool "Big endian"
751 subsequent interrupts when software !! 1192 depends on SYS_SUPPORTS_BIG_ENDIAN
752 exception handler of the system call <<
753 is enabled or VHE is in use. <<
754 1193
755 Work around the erratum by triggerin !! 1194 config CPU_LITTLE_ENDIAN
756 when handling a system call from a t !! 1195 bool "Little endian"
757 in a VHE configuration of the kernel !! 1196 depends on SYS_SUPPORTS_LITTLE_ENDIAN
758 1197
759 If unsure, say Y. !! 1198 endchoice
760 1199
761 config ARM64_ERRATUM_1542419 !! 1200 config EXPORT_UASM
762 bool "Neoverse-N1: workaround mis-orde !! 1201 bool
763 help <<
764 This option adds a workaround for AR <<
765 1542419. <<
766 1202
767 Affected Neoverse-N1 cores could exe !! 1203 config SYS_SUPPORTS_APM_EMULATION
768 modified by another CPU. The workaro !! 1204 bool
769 counterpart. <<
770 1205
771 Workaround the issue by hiding the D !! 1206 config SYS_SUPPORTS_BIG_ENDIAN
772 forces user-space to perform cache m !! 1207 bool
773 1208
774 If unsure, say N. !! 1209 config SYS_SUPPORTS_LITTLE_ENDIAN
>> 1210 bool
775 1211
776 config ARM64_ERRATUM_1508412 !! 1212 config SYS_SUPPORTS_HUGETLBFS
777 bool "Cortex-A77: 1508412: workaround !! 1213 bool
>> 1214 depends on CPU_SUPPORTS_HUGEPAGES && 64BIT
778 default y 1215 default y
779 help <<
780 This option adds a workaround for Ar <<
781 1216
782 Affected Cortex-A77 cores (r0p0, r1p !! 1217 config MIPS_HUGE_TLB_SUPPORT
783 of a store-exclusive or read of PAR_ !! 1218 def_bool HUGETLB_PAGE || TRANSPARENT_HUGEPAGE
784 non-cacheable memory attributes. The <<
785 counterpart. <<
786 1219
787 KVM guests must also have the workar !! 1220 config IRQ_CPU_RM7K
788 deadlock the system. !! 1221 bool
789 1222
790 Work around the issue by inserting D !! 1223 config IRQ_MSP_SLP
791 register reads and warning KVM users !! 1224 bool
792 to prevent a speculative PAR_EL1 rea <<
793 1225
794 If unsure, say Y. !! 1226 config IRQ_MSP_CIC
>> 1227 bool
795 1228
796 config ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MO !! 1229 config IRQ_TXX9
797 bool 1230 bool
798 1231
799 config ARM64_ERRATUM_2051678 !! 1232 config IRQ_GT641XX
800 bool "Cortex-A510: 2051678: disable Ha !! 1233 bool
801 default y <<
802 help <<
803 This options adds the workaround for <<
804 Affected Cortex-A510 might not respe <<
805 hardware update of the page table's <<
806 is to not enable the feature on affe <<
807 1234
808 If unsure, say Y. !! 1235 config PCI_GT64XXX_PCI0
>> 1236 bool
809 1237
810 config ARM64_ERRATUM_2077057 !! 1238 config NO_EXCEPT_FILL
811 bool "Cortex-A510: 2077057: workaround !! 1239 bool
812 default y <<
813 help <<
814 This option adds the workaround for <<
815 Affected Cortex-A510 may corrupt SPS <<
816 expected, but a Pointer Authenticati <<
817 erratum causes SPSR_EL1 to be copied <<
818 EL1 to cause a return to EL2 with a <<
819 1240
820 This can only happen when EL2 is ste !! 1241 config SOC_EMMA2RH
>> 1242 bool
>> 1243 select CEVT_R4K
>> 1244 select CSRC_R4K
>> 1245 select DMA_NONCOHERENT
>> 1246 select IRQ_MIPS_CPU
>> 1247 select SWAP_IO_SPACE
>> 1248 select SYS_HAS_CPU_R5500
>> 1249 select SYS_SUPPORTS_32BIT_KERNEL
>> 1250 select SYS_SUPPORTS_64BIT_KERNEL
>> 1251 select SYS_SUPPORTS_BIG_ENDIAN
821 1252
822 When these conditions occur, the SPS !! 1253 config SOC_PNX833X
823 previous guest entry, and can be res !! 1254 bool
>> 1255 select CEVT_R4K
>> 1256 select CSRC_R4K
>> 1257 select IRQ_MIPS_CPU
>> 1258 select DMA_NONCOHERENT
>> 1259 select SYS_HAS_CPU_MIPS32_R2
>> 1260 select SYS_SUPPORTS_32BIT_KERNEL
>> 1261 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 1262 select SYS_SUPPORTS_BIG_ENDIAN
>> 1263 select SYS_SUPPORTS_MIPS16
>> 1264 select CPU_MIPSR2_IRQ_VI
824 1265
825 If unsure, say Y. !! 1266 config SOC_PNX8335
>> 1267 bool
>> 1268 select SOC_PNX833X
826 1269
827 config ARM64_ERRATUM_2658417 !! 1270 config MIPS_SPRAM
828 bool "Cortex-A510: 2658417: remove BF1 !! 1271 bool
829 default y <<
830 help <<
831 This option adds the workaround for <<
832 Affected Cortex-A510 (r0p0 to r1p1) <<
833 BFMMLA or VMMLA instructions in rare <<
834 A510 CPUs are using shared neon hard <<
835 discoverable by the kernel, hide the <<
836 user-space should not be using these <<
837 1272
838 If unsure, say Y. !! 1273 config SWAP_IO_SPACE
>> 1274 bool
839 1275
840 config ARM64_ERRATUM_2119858 !! 1276 config SGI_HAS_INDYDOG
841 bool "Cortex-A710/X2: 2119858: workaro !! 1277 bool
842 default y <<
843 depends on CORESIGHT_TRBE <<
844 select ARM64_WORKAROUND_TRBE_OVERWRITE <<
845 help <<
846 This option adds the workaround for <<
847 1278
848 Affected Cortex-A710/X2 cores could !! 1279 config SGI_HAS_HAL2
849 data at the base of the buffer (poin !! 1280 bool
850 the event of a WRAP event. <<
851 1281
852 Work around the issue by always maki !! 1282 config SGI_HAS_SEEQ
853 256 bytes before enabling the buffer !! 1283 bool
854 the buffer with ETM ignore packets u <<
855 1284
856 If unsure, say Y. !! 1285 config SGI_HAS_WD93
>> 1286 bool
857 1287
858 config ARM64_ERRATUM_2139208 !! 1288 config SGI_HAS_ZILOG
859 bool "Neoverse-N2: 2139208: workaround !! 1289 bool
860 default y <<
861 depends on CORESIGHT_TRBE <<
862 select ARM64_WORKAROUND_TRBE_OVERWRITE <<
863 help <<
864 This option adds the workaround for <<
865 1290
866 Affected Neoverse-N2 cores could ove !! 1291 config SGI_HAS_I8042
867 data at the base of the buffer (poin !! 1292 bool
868 the event of a WRAP event. <<
869 1293
870 Work around the issue by always maki !! 1294 config DEFAULT_SGI_PARTITION
871 256 bytes before enabling the buffer !! 1295 bool
872 the buffer with ETM ignore packets u <<
873 1296
874 If unsure, say Y. !! 1297 config FW_ARC32
>> 1298 bool
875 1299
876 config ARM64_WORKAROUND_TSB_FLUSH_FAILURE !! 1300 config FW_SNIPROM
877 bool 1301 bool
878 1302
879 config ARM64_ERRATUM_2054223 !! 1303 config BOOT_ELF32
880 bool "Cortex-A710: 2054223: workaround !! 1304 bool
881 default y <<
882 select ARM64_WORKAROUND_TSB_FLUSH_FAIL <<
883 help <<
884 Enable workaround for ARM Cortex-A71 <<
885 1305
886 Affected cores may fail to flush the !! 1306 config MIPS_L1_CACHE_SHIFT_4
887 the PE is in trace prohibited state. !! 1307 bool
888 of the trace cached. <<
889 1308
890 Workaround is to issue two TSB conse !! 1309 config MIPS_L1_CACHE_SHIFT_5
>> 1310 bool
891 1311
892 If unsure, say Y. !! 1312 config MIPS_L1_CACHE_SHIFT_6
>> 1313 bool
893 1314
894 config ARM64_ERRATUM_2067961 !! 1315 config MIPS_L1_CACHE_SHIFT_7
895 bool "Neoverse-N2: 2067961: workaround !! 1316 bool
896 default y <<
897 select ARM64_WORKAROUND_TSB_FLUSH_FAIL <<
898 help <<
899 Enable workaround for ARM Neoverse-N <<
900 1317
901 Affected cores may fail to flush the !! 1318 config MIPS_L1_CACHE_SHIFT
902 the PE is in trace prohibited state. !! 1319 int
903 of the trace cached. !! 1320 default "7" if MIPS_L1_CACHE_SHIFT_7
>> 1321 default "6" if MIPS_L1_CACHE_SHIFT_6
>> 1322 default "5" if MIPS_L1_CACHE_SHIFT_5
>> 1323 default "4" if MIPS_L1_CACHE_SHIFT_4
>> 1324 default "5"
904 1325
905 Workaround is to issue two TSB conse !! 1326 config HAVE_STD_PC_SERIAL_PORT
>> 1327 bool
906 1328
907 If unsure, say Y. !! 1329 config ARC_CONSOLE
>> 1330 bool "ARC console support"
>> 1331 depends on SGI_IP22 || SGI_IP28 || (SNI_RM && CPU_LITTLE_ENDIAN)
908 1332
909 config ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANG !! 1333 config ARC_MEMORY
910 bool 1334 bool
911 !! 1335 depends on MACH_JAZZ || SNI_RM || SGI_IP32
912 config ARM64_ERRATUM_2253138 <<
913 bool "Neoverse-N2: 2253138: workaround <<
914 depends on CORESIGHT_TRBE <<
915 default y 1336 default y
916 select ARM64_WORKAROUND_TRBE_WRITE_OUT <<
917 help <<
918 This option adds the workaround for <<
919 1337
920 Affected Neoverse-N2 cores might wri !! 1338 config ARC_PROMLIB
921 for TRBE. Under some conditions, the !! 1339 bool
922 virtually addressed page following t !! 1340 depends on MACH_JAZZ || SNI_RM || SGI_IP22 || SGI_IP28 || SGI_IP32
923 (i.e., the TRBLIMITR_EL1.LIMIT), ins <<
924 <<
925 Work around this in the driver by al <<
926 page beyond the TRBLIMITR_EL1.LIMIT, <<
927 <<
928 If unsure, say Y. <<
929 <<
930 config ARM64_ERRATUM_2224489 <<
931 bool "Cortex-A710/X2: 2224489: workaro <<
932 depends on CORESIGHT_TRBE <<
933 default y 1341 default y
934 select ARM64_WORKAROUND_TRBE_WRITE_OUT <<
935 help <<
936 This option adds the workaround for <<
937 1342
938 Affected Cortex-A710/X2 cores might !! 1343 config FW_ARC64
939 for TRBE. Under some conditions, the !! 1344 bool
940 virtually addressed page following t <<
941 (i.e., the TRBLIMITR_EL1.LIMIT), ins <<
942 <<
943 Work around this in the driver by al <<
944 page beyond the TRBLIMITR_EL1.LIMIT, <<
945 <<
946 If unsure, say Y. <<
947 1345
948 config ARM64_ERRATUM_2441009 !! 1346 config BOOT_ELF64
949 bool "Cortex-A510: Completion of affec !! 1347 bool
950 select ARM64_WORKAROUND_REPEAT_TLBI <<
951 help <<
952 This option adds a workaround for AR <<
953 <<
954 Under very rare circumstances, affec <<
955 may not handle a race between a brea <<
956 CPU, and another CPU accessing the s <<
957 store to a page that has been unmapp <<
958 1348
959 Work around this by adding the affec !! 1349 menu "CPU selection"
960 TLB sequences to be done twice. <<
961 1350
962 If unsure, say N. !! 1351 choice
>> 1352 prompt "CPU type"
>> 1353 default CPU_R4X00
963 1354
964 config ARM64_ERRATUM_2064142 !! 1355 config CPU_LOONGSON3
965 bool "Cortex-A510: 2064142: workaround !! 1356 bool "Loongson 3 CPU"
966 depends on CORESIGHT_TRBE !! 1357 depends on SYS_HAS_CPU_LOONGSON3
967 default y !! 1358 select CPU_SUPPORTS_64BIT_KERNEL
>> 1359 select CPU_SUPPORTS_HIGHMEM
>> 1360 select CPU_SUPPORTS_HUGEPAGES
>> 1361 select WEAK_ORDERING
>> 1362 select WEAK_REORDERING_BEYOND_LLSC
>> 1363 select MIPS_PGD_C0_CONTEXT
>> 1364 select MIPS_L1_CACHE_SHIFT_6
>> 1365 select GPIOLIB
968 help 1366 help
969 This option adds the workaround for !! 1367 The Loongson 3 processor implements the MIPS64R2 instruction
>> 1368 set with many extensions.
970 1369
971 Affected Cortex-A510 core might fail !! 1370 config LOONGSON3_ENHANCEMENT
972 TRBE has been disabled. Under some c !! 1371 bool "New Loongson 3 CPU Enhancements"
973 writes into TRBE registers TRBLIMITR !! 1372 default n
974 and TRBTRG_EL1 will be ignored and w !! 1373 select CPU_MIPSR2
975 !! 1374 select CPU_HAS_PREFETCH
976 Work around this in the driver by ex !! 1375 depends on CPU_LOONGSON3
977 is stopped and before performing a s !! 1376 help
978 registers. !! 1377 New Loongson 3 CPU (since Loongson-3A R2, as opposed to Loongson-3A
>> 1378 R1, Loongson-3B R1 and Loongson-3B R2) has many enhancements, such as
>> 1379 FTLB, L1-VCache, EI/DI/Wait/Prefetch instruction, DSP/DSPv2 ASE, User
>> 1380 Local register, Read-Inhibit/Execute-Inhibit, SFB (Store Fill Buffer),
>> 1381 Fast TLB refill support, etc.
>> 1382
>> 1383 This option enable those enhancements which are not probed at run
>> 1384 time. If you want a generic kernel to run on all Loongson 3 machines,
>> 1385 please say 'N' here. If you want a high-performance kernel to run on
>> 1386 new Loongson 3 machines only, please say 'Y' here.
>> 1387
>> 1388 config CPU_LOONGSON2E
>> 1389 bool "Loongson 2E"
>> 1390 depends on SYS_HAS_CPU_LOONGSON2E
>> 1391 select CPU_LOONGSON2
>> 1392 help
>> 1393 The Loongson 2E processor implements the MIPS III instruction set
>> 1394 with many extensions.
>> 1395
>> 1396 It has an internal FPGA northbridge, which is compatible to
>> 1397 bonito64.
>> 1398
>> 1399 config CPU_LOONGSON2F
>> 1400 bool "Loongson 2F"
>> 1401 depends on SYS_HAS_CPU_LOONGSON2F
>> 1402 select CPU_LOONGSON2
>> 1403 select GPIOLIB
>> 1404 help
>> 1405 The Loongson 2F processor implements the MIPS III instruction set
>> 1406 with many extensions.
>> 1407
>> 1408 Loongson2F have built-in DDR2 and PCIX controller. The PCIX controller
>> 1409 have a similar programming interface with FPGA northbridge used in
>> 1410 Loongson2E.
>> 1411
>> 1412 config CPU_LOONGSON1B
>> 1413 bool "Loongson 1B"
>> 1414 depends on SYS_HAS_CPU_LOONGSON1B
>> 1415 select CPU_LOONGSON1
>> 1416 select LEDS_GPIO_REGISTER
>> 1417 help
>> 1418 The Loongson 1B is a 32-bit SoC, which implements the MIPS32
>> 1419 release 2 instruction set.
>> 1420
>> 1421 config CPU_LOONGSON1C
>> 1422 bool "Loongson 1C"
>> 1423 depends on SYS_HAS_CPU_LOONGSON1C
>> 1424 select CPU_LOONGSON1
>> 1425 select LEDS_GPIO_REGISTER
>> 1426 help
>> 1427 The Loongson 1C is a 32-bit SoC, which implements the MIPS32
>> 1428 release 2 instruction set.
>> 1429
>> 1430 config CPU_MIPS32_R1
>> 1431 bool "MIPS32 Release 1"
>> 1432 depends on SYS_HAS_CPU_MIPS32_R1
>> 1433 select CPU_HAS_PREFETCH
>> 1434 select CPU_SUPPORTS_32BIT_KERNEL
>> 1435 select CPU_SUPPORTS_HIGHMEM
>> 1436 help
>> 1437 Choose this option to build a kernel for release 1 or later of the
>> 1438 MIPS32 architecture. Most modern embedded systems with a 32-bit
>> 1439 MIPS processor are based on a MIPS32 processor. If you know the
>> 1440 specific type of processor in your system, choose those that one
>> 1441 otherwise CPU_MIPS32_R1 is a safe bet for any MIPS32 system.
>> 1442 Release 2 of the MIPS32 architecture is available since several
>> 1443 years so chances are you even have a MIPS32 Release 2 processor
>> 1444 in which case you should choose CPU_MIPS32_R2 instead for better
>> 1445 performance.
>> 1446
>> 1447 config CPU_MIPS32_R2
>> 1448 bool "MIPS32 Release 2"
>> 1449 depends on SYS_HAS_CPU_MIPS32_R2
>> 1450 select CPU_HAS_PREFETCH
>> 1451 select CPU_SUPPORTS_32BIT_KERNEL
>> 1452 select CPU_SUPPORTS_HIGHMEM
>> 1453 select CPU_SUPPORTS_MSA
>> 1454 select HAVE_KVM
>> 1455 help
>> 1456 Choose this option to build a kernel for release 2 or later of the
>> 1457 MIPS32 architecture. Most modern embedded systems with a 32-bit
>> 1458 MIPS processor are based on a MIPS32 processor. If you know the
>> 1459 specific type of processor in your system, choose those that one
>> 1460 otherwise CPU_MIPS32_R1 is a safe bet for any MIPS32 system.
>> 1461
>> 1462 config CPU_MIPS32_R6
>> 1463 bool "MIPS32 Release 6"
>> 1464 depends on SYS_HAS_CPU_MIPS32_R6
>> 1465 select CPU_HAS_PREFETCH
>> 1466 select CPU_SUPPORTS_32BIT_KERNEL
>> 1467 select CPU_SUPPORTS_HIGHMEM
>> 1468 select CPU_SUPPORTS_MSA
>> 1469 select GENERIC_CSUM
>> 1470 select HAVE_KVM
>> 1471 select MIPS_O32_FP64_SUPPORT
>> 1472 help
>> 1473 Choose this option to build a kernel for release 6 or later of the
>> 1474 MIPS32 architecture. New MIPS processors, starting with the Warrior
>> 1475 family, are based on a MIPS32r6 processor. If you own an older
>> 1476 processor, you probably need to select MIPS32r1 or MIPS32r2 instead.
>> 1477
>> 1478 config CPU_MIPS64_R1
>> 1479 bool "MIPS64 Release 1"
>> 1480 depends on SYS_HAS_CPU_MIPS64_R1
>> 1481 select CPU_HAS_PREFETCH
>> 1482 select CPU_SUPPORTS_32BIT_KERNEL
>> 1483 select CPU_SUPPORTS_64BIT_KERNEL
>> 1484 select CPU_SUPPORTS_HIGHMEM
>> 1485 select CPU_SUPPORTS_HUGEPAGES
>> 1486 help
>> 1487 Choose this option to build a kernel for release 1 or later of the
>> 1488 MIPS64 architecture. Many modern embedded systems with a 64-bit
>> 1489 MIPS processor are based on a MIPS64 processor. If you know the
>> 1490 specific type of processor in your system, choose those that one
>> 1491 otherwise CPU_MIPS64_R1 is a safe bet for any MIPS64 system.
>> 1492 Release 2 of the MIPS64 architecture is available since several
>> 1493 years so chances are you even have a MIPS64 Release 2 processor
>> 1494 in which case you should choose CPU_MIPS64_R2 instead for better
>> 1495 performance.
>> 1496
>> 1497 config CPU_MIPS64_R2
>> 1498 bool "MIPS64 Release 2"
>> 1499 depends on SYS_HAS_CPU_MIPS64_R2
>> 1500 select CPU_HAS_PREFETCH
>> 1501 select CPU_SUPPORTS_32BIT_KERNEL
>> 1502 select CPU_SUPPORTS_64BIT_KERNEL
>> 1503 select CPU_SUPPORTS_HIGHMEM
>> 1504 select CPU_SUPPORTS_HUGEPAGES
>> 1505 select CPU_SUPPORTS_MSA
>> 1506 select HAVE_KVM
>> 1507 help
>> 1508 Choose this option to build a kernel for release 2 or later of the
>> 1509 MIPS64 architecture. Many modern embedded systems with a 64-bit
>> 1510 MIPS processor are based on a MIPS64 processor. If you know the
>> 1511 specific type of processor in your system, choose those that one
>> 1512 otherwise CPU_MIPS64_R1 is a safe bet for any MIPS64 system.
>> 1513
>> 1514 config CPU_MIPS64_R6
>> 1515 bool "MIPS64 Release 6"
>> 1516 depends on SYS_HAS_CPU_MIPS64_R6
>> 1517 select CPU_HAS_PREFETCH
>> 1518 select CPU_SUPPORTS_32BIT_KERNEL
>> 1519 select CPU_SUPPORTS_64BIT_KERNEL
>> 1520 select CPU_SUPPORTS_HIGHMEM
>> 1521 select CPU_SUPPORTS_MSA
>> 1522 select GENERIC_CSUM
>> 1523 select MIPS_O32_FP64_SUPPORT if 32BIT || MIPS32_O32
>> 1524 select HAVE_KVM
>> 1525 help
>> 1526 Choose this option to build a kernel for release 6 or later of the
>> 1527 MIPS64 architecture. New MIPS processors, starting with the Warrior
>> 1528 family, are based on a MIPS64r6 processor. If you own an older
>> 1529 processor, you probably need to select MIPS64r1 or MIPS64r2 instead.
>> 1530
>> 1531 config CPU_R3000
>> 1532 bool "R3000"
>> 1533 depends on SYS_HAS_CPU_R3000
>> 1534 select CPU_HAS_WB
>> 1535 select CPU_SUPPORTS_32BIT_KERNEL
>> 1536 select CPU_SUPPORTS_HIGHMEM
>> 1537 help
>> 1538 Please make sure to pick the right CPU type. Linux/MIPS is not
>> 1539 designed to be generic, i.e. Kernels compiled for R3000 CPUs will
>> 1540 *not* work on R4000 machines and vice versa. However, since most
>> 1541 of the supported machines have an R4000 (or similar) CPU, R4x00
>> 1542 might be a safe bet. If the resulting kernel does not work,
>> 1543 try to recompile with R3000.
>> 1544
>> 1545 config CPU_TX39XX
>> 1546 bool "R39XX"
>> 1547 depends on SYS_HAS_CPU_TX39XX
>> 1548 select CPU_SUPPORTS_32BIT_KERNEL
>> 1549
>> 1550 config CPU_VR41XX
>> 1551 bool "R41xx"
>> 1552 depends on SYS_HAS_CPU_VR41XX
>> 1553 select CPU_SUPPORTS_32BIT_KERNEL
>> 1554 select CPU_SUPPORTS_64BIT_KERNEL
>> 1555 help
>> 1556 The options selects support for the NEC VR4100 series of processors.
>> 1557 Only choose this option if you have one of these processors as a
>> 1558 kernel built with this option will not run on any other type of
>> 1559 processor or vice versa.
>> 1560
>> 1561 config CPU_R4300
>> 1562 bool "R4300"
>> 1563 depends on SYS_HAS_CPU_R4300
>> 1564 select CPU_SUPPORTS_32BIT_KERNEL
>> 1565 select CPU_SUPPORTS_64BIT_KERNEL
>> 1566 help
>> 1567 MIPS Technologies R4300-series processors.
>> 1568
>> 1569 config CPU_R4X00
>> 1570 bool "R4x00"
>> 1571 depends on SYS_HAS_CPU_R4X00
>> 1572 select CPU_SUPPORTS_32BIT_KERNEL
>> 1573 select CPU_SUPPORTS_64BIT_KERNEL
>> 1574 select CPU_SUPPORTS_HUGEPAGES
>> 1575 help
>> 1576 MIPS Technologies R4000-series processors other than 4300, including
>> 1577 the R4000, R4400, R4600, and 4700.
>> 1578
>> 1579 config CPU_TX49XX
>> 1580 bool "R49XX"
>> 1581 depends on SYS_HAS_CPU_TX49XX
>> 1582 select CPU_HAS_PREFETCH
>> 1583 select CPU_SUPPORTS_32BIT_KERNEL
>> 1584 select CPU_SUPPORTS_64BIT_KERNEL
>> 1585 select CPU_SUPPORTS_HUGEPAGES
>> 1586
>> 1587 config CPU_R5000
>> 1588 bool "R5000"
>> 1589 depends on SYS_HAS_CPU_R5000
>> 1590 select CPU_SUPPORTS_32BIT_KERNEL
>> 1591 select CPU_SUPPORTS_64BIT_KERNEL
>> 1592 select CPU_SUPPORTS_HUGEPAGES
>> 1593 help
>> 1594 MIPS Technologies R5000-series processors other than the Nevada.
>> 1595
>> 1596 config CPU_R5432
>> 1597 bool "R5432"
>> 1598 depends on SYS_HAS_CPU_R5432
>> 1599 select CPU_SUPPORTS_32BIT_KERNEL
>> 1600 select CPU_SUPPORTS_64BIT_KERNEL
>> 1601 select CPU_SUPPORTS_HUGEPAGES
>> 1602
>> 1603 config CPU_R5500
>> 1604 bool "R5500"
>> 1605 depends on SYS_HAS_CPU_R5500
>> 1606 select CPU_SUPPORTS_32BIT_KERNEL
>> 1607 select CPU_SUPPORTS_64BIT_KERNEL
>> 1608 select CPU_SUPPORTS_HUGEPAGES
>> 1609 help
>> 1610 NEC VR5500 and VR5500A series processors implement 64-bit MIPS IV
>> 1611 instruction set.
>> 1612
>> 1613 config CPU_NEVADA
>> 1614 bool "RM52xx"
>> 1615 depends on SYS_HAS_CPU_NEVADA
>> 1616 select CPU_SUPPORTS_32BIT_KERNEL
>> 1617 select CPU_SUPPORTS_64BIT_KERNEL
>> 1618 select CPU_SUPPORTS_HUGEPAGES
>> 1619 help
>> 1620 QED / PMC-Sierra RM52xx-series ("Nevada") processors.
>> 1621
>> 1622 config CPU_R8000
>> 1623 bool "R8000"
>> 1624 depends on SYS_HAS_CPU_R8000
>> 1625 select CPU_HAS_PREFETCH
>> 1626 select CPU_SUPPORTS_64BIT_KERNEL
>> 1627 help
>> 1628 MIPS Technologies R8000 processors. Note these processors are
>> 1629 uncommon and the support for them is incomplete.
>> 1630
>> 1631 config CPU_R10000
>> 1632 bool "R10000"
>> 1633 depends on SYS_HAS_CPU_R10000
>> 1634 select CPU_HAS_PREFETCH
>> 1635 select CPU_SUPPORTS_32BIT_KERNEL
>> 1636 select CPU_SUPPORTS_64BIT_KERNEL
>> 1637 select CPU_SUPPORTS_HIGHMEM
>> 1638 select CPU_SUPPORTS_HUGEPAGES
>> 1639 help
>> 1640 MIPS Technologies R10000-series processors.
>> 1641
>> 1642 config CPU_RM7000
>> 1643 bool "RM7000"
>> 1644 depends on SYS_HAS_CPU_RM7000
>> 1645 select CPU_HAS_PREFETCH
>> 1646 select CPU_SUPPORTS_32BIT_KERNEL
>> 1647 select CPU_SUPPORTS_64BIT_KERNEL
>> 1648 select CPU_SUPPORTS_HIGHMEM
>> 1649 select CPU_SUPPORTS_HUGEPAGES
>> 1650
>> 1651 config CPU_SB1
>> 1652 bool "SB1"
>> 1653 depends on SYS_HAS_CPU_SB1
>> 1654 select CPU_SUPPORTS_32BIT_KERNEL
>> 1655 select CPU_SUPPORTS_64BIT_KERNEL
>> 1656 select CPU_SUPPORTS_HIGHMEM
>> 1657 select CPU_SUPPORTS_HUGEPAGES
>> 1658 select WEAK_ORDERING
>> 1659
>> 1660 config CPU_CAVIUM_OCTEON
>> 1661 bool "Cavium Octeon processor"
>> 1662 depends on SYS_HAS_CPU_CAVIUM_OCTEON
>> 1663 select CPU_HAS_PREFETCH
>> 1664 select CPU_SUPPORTS_64BIT_KERNEL
>> 1665 select WEAK_ORDERING
>> 1666 select CPU_SUPPORTS_HIGHMEM
>> 1667 select CPU_SUPPORTS_HUGEPAGES
>> 1668 select USB_EHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 1669 select USB_OHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 1670 select MIPS_L1_CACHE_SHIFT_7
>> 1671 select HAVE_KVM
>> 1672 help
>> 1673 The Cavium Octeon processor is a highly integrated chip containing
>> 1674 many ethernet hardware widgets for networking tasks. The processor
>> 1675 can have up to 16 Mips64v2 cores and 8 integrated gigabit ethernets.
>> 1676 Full details can be found at http://www.caviumnetworks.com.
>> 1677
>> 1678 config CPU_BMIPS
>> 1679 bool "Broadcom BMIPS"
>> 1680 depends on SYS_HAS_CPU_BMIPS
>> 1681 select CPU_MIPS32
>> 1682 select CPU_BMIPS32_3300 if SYS_HAS_CPU_BMIPS32_3300
>> 1683 select CPU_BMIPS4350 if SYS_HAS_CPU_BMIPS4350
>> 1684 select CPU_BMIPS4380 if SYS_HAS_CPU_BMIPS4380
>> 1685 select CPU_BMIPS5000 if SYS_HAS_CPU_BMIPS5000
>> 1686 select CPU_SUPPORTS_32BIT_KERNEL
>> 1687 select DMA_NONCOHERENT
>> 1688 select IRQ_MIPS_CPU
>> 1689 select SWAP_IO_SPACE
>> 1690 select WEAK_ORDERING
>> 1691 select CPU_SUPPORTS_HIGHMEM
>> 1692 select CPU_HAS_PREFETCH
>> 1693 select CPU_SUPPORTS_CPUFREQ
>> 1694 select MIPS_EXTERNAL_TIMER
>> 1695 help
>> 1696 Support for BMIPS32/3300/4350/4380 and BMIPS5000 processors.
>> 1697
>> 1698 config CPU_XLR
>> 1699 bool "Netlogic XLR SoC"
>> 1700 depends on SYS_HAS_CPU_XLR
>> 1701 select CPU_SUPPORTS_32BIT_KERNEL
>> 1702 select CPU_SUPPORTS_64BIT_KERNEL
>> 1703 select CPU_SUPPORTS_HIGHMEM
>> 1704 select CPU_SUPPORTS_HUGEPAGES
>> 1705 select WEAK_ORDERING
>> 1706 select WEAK_REORDERING_BEYOND_LLSC
>> 1707 help
>> 1708 Netlogic Microsystems XLR/XLS processors.
>> 1709
>> 1710 config CPU_XLP
>> 1711 bool "Netlogic XLP SoC"
>> 1712 depends on SYS_HAS_CPU_XLP
>> 1713 select CPU_SUPPORTS_32BIT_KERNEL
>> 1714 select CPU_SUPPORTS_64BIT_KERNEL
>> 1715 select CPU_SUPPORTS_HIGHMEM
>> 1716 select WEAK_ORDERING
>> 1717 select WEAK_REORDERING_BEYOND_LLSC
>> 1718 select CPU_HAS_PREFETCH
>> 1719 select CPU_MIPSR2
>> 1720 select CPU_SUPPORTS_HUGEPAGES
>> 1721 select MIPS_ASID_BITS_VARIABLE
>> 1722 help
>> 1723 Netlogic Microsystems XLP processors.
>> 1724 endchoice
979 1725
980 If unsure, say Y. !! 1726 config CPU_MIPS32_3_5_FEATURES
>> 1727 bool "MIPS32 Release 3.5 Features"
>> 1728 depends on SYS_HAS_CPU_MIPS32_R3_5
>> 1729 depends on CPU_MIPS32_R2 || CPU_MIPS32_R6
>> 1730 help
>> 1731 Choose this option to build a kernel for release 2 or later of the
>> 1732 MIPS32 architecture including features from the 3.5 release such as
>> 1733 support for Enhanced Virtual Addressing (EVA).
>> 1734
>> 1735 config CPU_MIPS32_3_5_EVA
>> 1736 bool "Enhanced Virtual Addressing (EVA)"
>> 1737 depends on CPU_MIPS32_3_5_FEATURES
>> 1738 select EVA
>> 1739 default y
>> 1740 help
>> 1741 Choose this option if you want to enable the Enhanced Virtual
>> 1742 Addressing (EVA) on your MIPS32 core (such as proAptiv).
>> 1743 One of its primary benefits is an increase in the maximum size
>> 1744 of lowmem (up to 3GB). If unsure, say 'N' here.
>> 1745
>> 1746 config CPU_MIPS32_R5_FEATURES
>> 1747 bool "MIPS32 Release 5 Features"
>> 1748 depends on SYS_HAS_CPU_MIPS32_R5
>> 1749 depends on CPU_MIPS32_R2
>> 1750 help
>> 1751 Choose this option to build a kernel for release 2 or later of the
>> 1752 MIPS32 architecture including features from release 5 such as
>> 1753 support for Extended Physical Addressing (XPA).
>> 1754
>> 1755 config CPU_MIPS32_R5_XPA
>> 1756 bool "Extended Physical Addressing (XPA)"
>> 1757 depends on CPU_MIPS32_R5_FEATURES
>> 1758 depends on !EVA
>> 1759 depends on !PAGE_SIZE_4KB
>> 1760 depends on SYS_SUPPORTS_HIGHMEM
>> 1761 select XPA
>> 1762 select HIGHMEM
>> 1763 select ARCH_PHYS_ADDR_T_64BIT
>> 1764 default n
>> 1765 help
>> 1766 Choose this option if you want to enable the Extended Physical
>> 1767 Addressing (XPA) on your MIPS32 core (such as P5600 series). The
>> 1768 benefit is to increase physical addressing equal to or greater
>> 1769 than 40 bits. Note that this has the side effect of turning on
>> 1770 64-bit addressing which in turn makes the PTEs 64-bit in size.
>> 1771 If unsure, say 'N' here.
981 1772
982 config ARM64_ERRATUM_2038923 !! 1773 if CPU_LOONGSON2F
983 bool "Cortex-A510: 2038923: workaround !! 1774 config CPU_NOP_WORKAROUNDS
984 depends on CORESIGHT_TRBE !! 1775 bool
985 default y <<
986 help <<
987 This option adds the workaround for <<
988 <<
989 Affected Cortex-A510 core might caus <<
990 prohibited within the CPU. As a resu <<
991 might be corrupted. This happens aft <<
992 TRBLIMITR_EL1.E, followed by just a <<
993 execution changes from a context, in <<
994 isn't, or vice versa. In these menti <<
995 is prohibited is inconsistent betwee <<
996 the trace buffer state might be corr <<
997 <<
998 Work around this in the driver by pr <<
999 trace is prohibited or not based on <<
1000 change to TRBLIMITR_EL1.E with at l <<
1001 two ISB instructions if no ERET is <<
1002 1776
1003 If unsure, say Y. !! 1777 config CPU_JUMP_WORKAROUNDS
>> 1778 bool
1004 1779
1005 config ARM64_ERRATUM_1902691 !! 1780 config CPU_LOONGSON2F_WORKAROUNDS
1006 bool "Cortex-A510: 1902691: workaroun !! 1781 bool "Loongson 2F Workarounds"
1007 depends on CORESIGHT_TRBE <<
1008 default y 1782 default y
>> 1783 select CPU_NOP_WORKAROUNDS
>> 1784 select CPU_JUMP_WORKAROUNDS
1009 help 1785 help
1010 This option adds the workaround for !! 1786 Loongson 2F01 / 2F02 processors have the NOP & JUMP issues which
>> 1787 require workarounds. Without workarounds the system may hang
>> 1788 unexpectedly. For more information please refer to the gas
>> 1789 -mfix-loongson2f-nop and -mfix-loongson2f-jump options.
>> 1790
>> 1791 Loongson 2F03 and later have fixed these issues and no workarounds
>> 1792 are needed. The workarounds have no significant side effect on them
>> 1793 but may decrease the performance of the system so this option should
>> 1794 be disabled unless the kernel is intended to be run on 2F01 or 2F02
>> 1795 systems.
1011 1796
1012 Affected Cortex-A510 core might cau !! 1797 If unsure, please say Y.
1013 into the memory. Effectively TRBE i !! 1798 endif # CPU_LOONGSON2F
1014 trace data. <<
1015 1799
1016 Work around this problem in the dri !! 1800 config SYS_SUPPORTS_ZBOOT
1017 affected cpus. The firmware must ha !! 1801 bool
1018 on such implementations. This will !! 1802 select HAVE_KERNEL_GZIP
1019 do this already. !! 1803 select HAVE_KERNEL_BZIP2
>> 1804 select HAVE_KERNEL_LZ4
>> 1805 select HAVE_KERNEL_LZMA
>> 1806 select HAVE_KERNEL_LZO
>> 1807 select HAVE_KERNEL_XZ
1020 1808
1021 If unsure, say Y. !! 1809 config SYS_SUPPORTS_ZBOOT_UART16550
>> 1810 bool
>> 1811 select SYS_SUPPORTS_ZBOOT
1022 1812
1023 config ARM64_ERRATUM_2457168 !! 1813 config SYS_SUPPORTS_ZBOOT_UART_PROM
1024 bool "Cortex-A510: 2457168: workaroun !! 1814 bool
1025 depends on ARM64_AMU_EXTN !! 1815 select SYS_SUPPORTS_ZBOOT
1026 default y <<
1027 help <<
1028 This option adds the workaround for <<
1029 1816
1030 The AMU counter AMEVCNTR01 (constan !! 1817 config CPU_LOONGSON2
1031 as the system counter. On affected !! 1818 bool
1032 incorrectly giving a significantly !! 1819 select CPU_SUPPORTS_32BIT_KERNEL
>> 1820 select CPU_SUPPORTS_64BIT_KERNEL
>> 1821 select CPU_SUPPORTS_HIGHMEM
>> 1822 select CPU_SUPPORTS_HUGEPAGES
1033 1823
1034 Work around this problem by returni !! 1824 config CPU_LOONGSON1
1035 key locations that results in disab !! 1825 bool
1036 is the same to firmware disabling a !! 1826 select CPU_MIPS32
>> 1827 select CPU_MIPSR2
>> 1828 select CPU_HAS_PREFETCH
>> 1829 select CPU_SUPPORTS_32BIT_KERNEL
>> 1830 select CPU_SUPPORTS_HIGHMEM
>> 1831 select CPU_SUPPORTS_CPUFREQ
1037 1832
1038 If unsure, say Y. !! 1833 config CPU_BMIPS32_3300
>> 1834 select SMP_UP if SMP
>> 1835 bool
1039 1836
1040 config ARM64_ERRATUM_2645198 !! 1837 config CPU_BMIPS4350
1041 bool "Cortex-A715: 2645198: Workaroun !! 1838 bool
1042 default y !! 1839 select SYS_SUPPORTS_SMP
1043 help !! 1840 select SYS_SUPPORTS_HOTPLUG_CPU
1044 This option adds the workaround for <<
1045 1841
1046 If a Cortex-A715 cpu sees a page ma !! 1842 config CPU_BMIPS4380
1047 to non-executable, it may corrupt t !! 1843 bool
1048 next instruction abort caused by pe !! 1844 select MIPS_L1_CACHE_SHIFT_6
>> 1845 select SYS_SUPPORTS_SMP
>> 1846 select SYS_SUPPORTS_HOTPLUG_CPU
>> 1847 select CPU_HAS_RIXI
1049 1848
1050 Only user-space does executable to !! 1849 config CPU_BMIPS5000
1051 mprotect() system call. Workaround !! 1850 bool
1052 TLB invalidation, for all changes t !! 1851 select MIPS_CPU_SCACHE
>> 1852 select MIPS_L1_CACHE_SHIFT_7
>> 1853 select SYS_SUPPORTS_SMP
>> 1854 select SYS_SUPPORTS_HOTPLUG_CPU
>> 1855 select CPU_HAS_RIXI
1053 1856
1054 If unsure, say Y. !! 1857 config SYS_HAS_CPU_LOONGSON3
>> 1858 bool
>> 1859 select CPU_SUPPORTS_CPUFREQ
>> 1860 select CPU_HAS_RIXI
1055 1861
1056 config ARM64_WORKAROUND_SPECULATIVE_UNPRIV_LO !! 1862 config SYS_HAS_CPU_LOONGSON2E
1057 bool 1863 bool
1058 1864
1059 config ARM64_ERRATUM_2966298 !! 1865 config SYS_HAS_CPU_LOONGSON2F
1060 bool "Cortex-A520: 2966298: workaroun !! 1866 bool
1061 select ARM64_WORKAROUND_SPECULATIVE_U !! 1867 select CPU_SUPPORTS_CPUFREQ
1062 default y !! 1868 select CPU_SUPPORTS_ADDRWINCFG if 64BIT
1063 help !! 1869 select CPU_SUPPORTS_UNCACHED_ACCELERATED
1064 This option adds the workaround for <<
1065 1870
1066 On an affected Cortex-A520 core, a !! 1871 config SYS_HAS_CPU_LOONGSON1B
1067 load might leak data from a privile !! 1872 bool
1068 1873
1069 Work around this problem by executi !! 1874 config SYS_HAS_CPU_LOONGSON1C
>> 1875 bool
1070 1876
1071 If unsure, say Y. !! 1877 config SYS_HAS_CPU_MIPS32_R1
>> 1878 bool
1072 1879
1073 config ARM64_ERRATUM_3117295 !! 1880 config SYS_HAS_CPU_MIPS32_R2
1074 bool "Cortex-A510: 3117295: workaroun !! 1881 bool
1075 select ARM64_WORKAROUND_SPECULATIVE_U <<
1076 default y <<
1077 help <<
1078 This option adds the workaround for <<
1079 1882
1080 On an affected Cortex-A510 core, a !! 1883 config SYS_HAS_CPU_MIPS32_R3_5
1081 load might leak data from a privile !! 1884 bool
1082 1885
1083 Work around this problem by executi !! 1886 config SYS_HAS_CPU_MIPS32_R5
>> 1887 bool
1084 1888
1085 If unsure, say Y. !! 1889 config SYS_HAS_CPU_MIPS32_R6
>> 1890 bool
1086 1891
1087 config ARM64_ERRATUM_3194386 !! 1892 config SYS_HAS_CPU_MIPS64_R1
1088 bool "Cortex-*/Neoverse-*: workaround !! 1893 bool
1089 default y <<
1090 help <<
1091 This option adds the workaround for <<
1092 1894
1093 * ARM Cortex-A76 erratum 3324349 !! 1895 config SYS_HAS_CPU_MIPS64_R2
1094 * ARM Cortex-A77 erratum 3324348 !! 1896 bool
1095 * ARM Cortex-A78 erratum 3324344 <<
1096 * ARM Cortex-A78C erratum 3324346 <<
1097 * ARM Cortex-A78C erratum 3324347 <<
1098 * ARM Cortex-A710 erratam 3324338 <<
1099 * ARM Cortex-A715 errartum 3456084 <<
1100 * ARM Cortex-A720 erratum 3456091 <<
1101 * ARM Cortex-A725 erratum 3456106 <<
1102 * ARM Cortex-X1 erratum 3324344 <<
1103 * ARM Cortex-X1C erratum 3324346 <<
1104 * ARM Cortex-X2 erratum 3324338 <<
1105 * ARM Cortex-X3 erratum 3324335 <<
1106 * ARM Cortex-X4 erratum 3194386 <<
1107 * ARM Cortex-X925 erratum 3324334 <<
1108 * ARM Neoverse-N1 erratum 3324349 <<
1109 * ARM Neoverse N2 erratum 3324339 <<
1110 * ARM Neoverse-N3 erratum 3456111 <<
1111 * ARM Neoverse-V1 erratum 3324341 <<
1112 * ARM Neoverse V2 erratum 3324336 <<
1113 * ARM Neoverse-V3 erratum 3312417 <<
1114 <<
1115 On affected cores "MSR SSBS, #0" in <<
1116 subsequent speculative instructions <<
1117 speculative store bypassing. <<
1118 <<
1119 Work around this problem by placing <<
1120 Instruction Synchronization Barrier <<
1121 SSBS. The presence of the SSBS spec <<
1122 from hwcaps and EL0 reads of ID_AA6 <<
1123 will use the PR_SPEC_STORE_BYPASS p <<
1124 1897
1125 If unsure, say Y. !! 1898 config SYS_HAS_CPU_MIPS64_R6
>> 1899 bool
1126 1900
1127 config CAVIUM_ERRATUM_22375 !! 1901 config SYS_HAS_CPU_R3000
1128 bool "Cavium erratum 22375, 24313" !! 1902 bool
1129 default y <<
1130 help <<
1131 Enable workaround for errata 22375 <<
1132 1903
1133 This implements two gicv3-its errat !! 1904 config SYS_HAS_CPU_TX39XX
1134 with a small impact affecting only !! 1905 bool
1135 1906
1136 erratum 22375: only alloc 8MB tab !! 1907 config SYS_HAS_CPU_VR41XX
1137 erratum 24313: ignore memory acce !! 1908 bool
1138 1909
1139 The fixes are in ITS initialization !! 1910 config SYS_HAS_CPU_R4300
1140 type and table size provided by the !! 1911 bool
1141 1912
1142 If unsure, say Y. !! 1913 config SYS_HAS_CPU_R4X00
>> 1914 bool
1143 1915
1144 config CAVIUM_ERRATUM_23144 !! 1916 config SYS_HAS_CPU_TX49XX
1145 bool "Cavium erratum 23144: ITS SYNC !! 1917 bool
1146 depends on NUMA <<
1147 default y <<
1148 help <<
1149 ITS SYNC command hang for cross nod <<
1150 1918
1151 If unsure, say Y. !! 1919 config SYS_HAS_CPU_R5000
>> 1920 bool
1152 1921
1153 config CAVIUM_ERRATUM_23154 !! 1922 config SYS_HAS_CPU_R5432
1154 bool "Cavium errata 23154 and 38545: !! 1923 bool
1155 default y <<
1156 help <<
1157 The ThunderX GICv3 implementation r <<
1158 reading the IAR status to ensure da <<
1159 (access to icc_iar1_el1 is not sync <<
1160 1924
1161 It also suffers from erratum 38545 !! 1925 config SYS_HAS_CPU_R5500
1162 OcteonTX and OcteonTX2), resulting !! 1926 bool
1163 spuriously presented to the CPU int <<
1164 1927
1165 If unsure, say Y. !! 1928 config SYS_HAS_CPU_NEVADA
>> 1929 bool
1166 1930
1167 config CAVIUM_ERRATUM_27456 !! 1931 config SYS_HAS_CPU_R8000
1168 bool "Cavium erratum 27456: Broadcast !! 1932 bool
1169 default y <<
1170 help <<
1171 On ThunderX T88 pass 1.x through 2. <<
1172 instructions may cause the icache t <<
1173 contains data for a non-current ASI <<
1174 invalidate the icache when changing <<
1175 1933
1176 If unsure, say Y. !! 1934 config SYS_HAS_CPU_R10000
>> 1935 bool
1177 1936
1178 config CAVIUM_ERRATUM_30115 !! 1937 config SYS_HAS_CPU_RM7000
1179 bool "Cavium erratum 30115: Guest may !! 1938 bool
1180 default y <<
1181 help <<
1182 On ThunderX T88 pass 1.x through 2. <<
1183 1.2, and T83 Pass 1.0, KVM guest ex <<
1184 interrupts in host. Trapping both G <<
1185 accesses sidesteps the issue. <<
1186 1939
1187 If unsure, say Y. !! 1940 config SYS_HAS_CPU_SB1
>> 1941 bool
1188 1942
1189 config CAVIUM_TX2_ERRATUM_219 !! 1943 config SYS_HAS_CPU_CAVIUM_OCTEON
1190 bool "Cavium ThunderX2 erratum 219: P !! 1944 bool
1191 default y <<
1192 help <<
1193 On Cavium ThunderX2, a load, store <<
1194 TTBR update and the corresponding c <<
1195 cause a spurious Data Abort to be d <<
1196 the CPU core. <<
1197 <<
1198 Work around the issue by avoiding t <<
1199 trapping KVM guest TTBRx_EL1 writes <<
1200 trap handler performs the correspon <<
1201 instruction and ensures context syn <<
1202 exception return. <<
1203 1945
1204 If unsure, say Y. !! 1946 config SYS_HAS_CPU_BMIPS
>> 1947 bool
1205 1948
1206 config FUJITSU_ERRATUM_010001 !! 1949 config SYS_HAS_CPU_BMIPS32_3300
1207 bool "Fujitsu-A64FX erratum E#010001: !! 1950 bool
1208 default y !! 1951 select SYS_HAS_CPU_BMIPS
1209 help <<
1210 This option adds a workaround for F <<
1211 On some variants of the Fujitsu-A64 <<
1212 accesses may cause undefined fault <<
1213 This fault occurs under a specific <<
1214 load/store instruction performs an <<
1215 case-1 TTBR0_EL1 with TCR_EL1.NFD0 <<
1216 case-2 TTBR0_EL2 with TCR_EL2.NFD0 <<
1217 case-3 TTBR1_EL1 with TCR_EL1.NFD1 <<
1218 case-4 TTBR1_EL2 with TCR_EL2.NFD1 <<
1219 1952
1220 The workaround is to ensure these b !! 1953 config SYS_HAS_CPU_BMIPS4350
1221 The workaround only affects the Fuj !! 1954 bool
>> 1955 select SYS_HAS_CPU_BMIPS
1222 1956
1223 If unsure, say Y. !! 1957 config SYS_HAS_CPU_BMIPS4380
>> 1958 bool
>> 1959 select SYS_HAS_CPU_BMIPS
1224 1960
1225 config HISILICON_ERRATUM_161600802 !! 1961 config SYS_HAS_CPU_BMIPS5000
1226 bool "Hip07 161600802: Erroneous redi !! 1962 bool
1227 default y !! 1963 select SYS_HAS_CPU_BMIPS
1228 help <<
1229 The HiSilicon Hip07 SoC uses the wr <<
1230 when issued ITS commands such as VM <<
1231 a 128kB offset to be applied to the <<
1232 1964
1233 If unsure, say Y. !! 1965 config SYS_HAS_CPU_XLR
>> 1966 bool
1234 1967
1235 config QCOM_FALKOR_ERRATUM_1003 !! 1968 config SYS_HAS_CPU_XLP
1236 bool "Falkor E1003: Incorrect transla !! 1969 bool
1237 default y <<
1238 help <<
1239 On Falkor v1, an incorrect ASID may <<
1240 and BADDR are changed together in T <<
1241 in TTBR1_EL1, this situation only o <<
1242 then only for entries in the walk c <<
1243 is unchanged. Work around the errat <<
1244 entries for the trampoline before e <<
1245 1970
1246 config QCOM_FALKOR_ERRATUM_1009 !! 1971 config MIPS_MALTA_PM
1247 bool "Falkor E1009: Prematurely compl !! 1972 depends on MIPS_MALTA
>> 1973 depends on PCI
>> 1974 bool
1248 default y 1975 default y
1249 select ARM64_WORKAROUND_REPEAT_TLBI <<
1250 help <<
1251 On Falkor v1, the CPU may premature <<
1252 TLBI xxIS invalidate maintenance op <<
1253 one more time to fix the issue. <<
1254 1976
1255 If unsure, say Y. !! 1977 #
>> 1978 # CPU may reorder R->R, R->W, W->R, W->W
>> 1979 # Reordering beyond LL and SC is handled in WEAK_REORDERING_BEYOND_LLSC
>> 1980 #
>> 1981 config WEAK_ORDERING
>> 1982 bool
1256 1983
1257 config QCOM_QDF2400_ERRATUM_0065 !! 1984 #
1258 bool "QDF2400 E0065: Incorrect GITS_T !! 1985 # CPU may reorder reads and writes beyond LL/SC
1259 default y !! 1986 # CPU may reorder R->LL, R->LL, W->LL, W->LL, R->SC, R->SC, W->SC, W->SC
1260 help !! 1987 #
1261 On Qualcomm Datacenter Technologies !! 1988 config WEAK_REORDERING_BEYOND_LLSC
1262 ITE size incorrectly. The GITS_TYPE !! 1989 bool
1263 been indicated as 16Bytes (0xf), no !! 1990 endmenu
1264 1991
1265 If unsure, say Y. !! 1992 #
>> 1993 # These two indicate any level of the MIPS32 and MIPS64 architecture
>> 1994 #
>> 1995 config CPU_MIPS32
>> 1996 bool
>> 1997 default y if CPU_MIPS32_R1 || CPU_MIPS32_R2 || CPU_MIPS32_R6
1266 1998
1267 config QCOM_FALKOR_ERRATUM_E1041 !! 1999 config CPU_MIPS64
1268 bool "Falkor E1041: Speculative instr !! 2000 bool
1269 default y !! 2001 default y if CPU_MIPS64_R1 || CPU_MIPS64_R2 || CPU_MIPS64_R6
1270 help <<
1271 Falkor CPU may speculatively fetch <<
1272 memory location when MMU translatio <<
1273 to SCTLR_ELn[M]=0. Prefix an ISB in <<
1274 2002
1275 If unsure, say Y. !! 2003 #
>> 2004 # These two indicate the revision of the architecture, either Release 1 or Release 2
>> 2005 #
>> 2006 config CPU_MIPSR1
>> 2007 bool
>> 2008 default y if CPU_MIPS32_R1 || CPU_MIPS64_R1
1276 2009
1277 config NVIDIA_CARMEL_CNP_ERRATUM !! 2010 config CPU_MIPSR2
1278 bool "NVIDIA Carmel CNP: CNP on Carme !! 2011 bool
1279 default y !! 2012 default y if CPU_MIPS32_R2 || CPU_MIPS64_R2 || CPU_CAVIUM_OCTEON
1280 help !! 2013 select CPU_HAS_RIXI
1281 If CNP is enabled on Carmel cores, !! 2014 select MIPS_SPRAM
1282 invalidate shared TLB entries insta <<
1283 on standard ARM cores. <<
1284 2015
1285 If unsure, say Y. !! 2016 config CPU_MIPSR6
>> 2017 bool
>> 2018 default y if CPU_MIPS32_R6 || CPU_MIPS64_R6
>> 2019 select CPU_HAS_RIXI
>> 2020 select HAVE_ARCH_BITREVERSE
>> 2021 select MIPS_ASID_BITS_VARIABLE
>> 2022 select MIPS_SPRAM
1286 2023
1287 config ROCKCHIP_ERRATUM_3588001 !! 2024 config EVA
1288 bool "Rockchip 3588001: GIC600 can no !! 2025 bool
1289 default y <<
1290 help <<
1291 The Rockchip RK3588 GIC600 SoC inte <<
1292 This means, that its sharability fe <<
1293 is supported by the IP itself. <<
1294 2026
1295 If unsure, say Y. !! 2027 config XPA
>> 2028 bool
1296 2029
1297 config SOCIONEXT_SYNQUACER_PREITS !! 2030 config SYS_SUPPORTS_32BIT_KERNEL
1298 bool "Socionext Synquacer: Workaround !! 2031 bool
1299 default y !! 2032 config SYS_SUPPORTS_64BIT_KERNEL
1300 help !! 2033 bool
1301 Socionext Synquacer SoCs implement !! 2034 config CPU_SUPPORTS_32BIT_KERNEL
1302 MSI doorbell writes with non-zero v !! 2035 bool
>> 2036 config CPU_SUPPORTS_64BIT_KERNEL
>> 2037 bool
>> 2038 config CPU_SUPPORTS_CPUFREQ
>> 2039 bool
>> 2040 config CPU_SUPPORTS_ADDRWINCFG
>> 2041 bool
>> 2042 config CPU_SUPPORTS_HUGEPAGES
>> 2043 bool
>> 2044 config CPU_SUPPORTS_UNCACHED_ACCELERATED
>> 2045 bool
>> 2046 config MIPS_PGD_C0_CONTEXT
>> 2047 bool
>> 2048 default y if 64BIT && (CPU_MIPSR2 || CPU_MIPSR6) && !CPU_XLP
1303 2049
1304 If unsure, say Y. !! 2050 #
>> 2051 # Set to y for ptrace access to watch registers.
>> 2052 #
>> 2053 config HARDWARE_WATCHPOINTS
>> 2054 bool
>> 2055 default y if CPU_MIPSR1 || CPU_MIPSR2 || CPU_MIPSR6
1305 2056
1306 endmenu # "ARM errata workarounds via the alt !! 2057 menu "Kernel type"
1307 2058
1308 choice 2059 choice
1309 prompt "Page size" !! 2060 prompt "Kernel code model"
1310 default ARM64_4K_PAGES <<
1311 help 2061 help
1312 Page size (translation granule) con !! 2062 You should only select this option if you have a workload that
1313 !! 2063 actually benefits from 64-bit processing or if your machine has
1314 config ARM64_4K_PAGES !! 2064 large memory. You will only be presented a single option in this
1315 bool "4KB" !! 2065 menu if your system does not support both 32-bit and 64-bit kernels.
1316 select HAVE_PAGE_SIZE_4KB !! 2066
1317 help !! 2067 config 32BIT
1318 This feature enables 4KB pages supp !! 2068 bool "32-bit kernel"
1319 !! 2069 depends on CPU_SUPPORTS_32BIT_KERNEL && SYS_SUPPORTS_32BIT_KERNEL
1320 config ARM64_16K_PAGES !! 2070 select TRAD_SIGNALS
1321 bool "16KB" <<
1322 select HAVE_PAGE_SIZE_16KB <<
1323 help 2071 help
1324 The system will use 16KB pages supp !! 2072 Select this option if you want to build a 32-bit kernel.
1325 requires applications compiled with <<
1326 aligned segments. <<
1327 2073
1328 config ARM64_64K_PAGES !! 2074 config 64BIT
1329 bool "64KB" !! 2075 bool "64-bit kernel"
1330 select HAVE_PAGE_SIZE_64KB !! 2076 depends on CPU_SUPPORTS_64BIT_KERNEL && SYS_SUPPORTS_64BIT_KERNEL
1331 help 2077 help
1332 This feature enables 64KB pages sup !! 2078 Select this option if you want to build a 64-bit kernel.
1333 allowing only two levels of page ta <<
1334 look-up. AArch32 emulation requires <<
1335 with 64K aligned segments. <<
1336 2079
1337 endchoice 2080 endchoice
1338 2081
>> 2082 config KVM_GUEST
>> 2083 bool "KVM Guest Kernel"
>> 2084 depends on BROKEN_ON_SMP
>> 2085 help
>> 2086 Select this option if building a guest kernel for KVM (Trap & Emulate)
>> 2087 mode.
>> 2088
>> 2089 config KVM_GUEST_TIMER_FREQ
>> 2090 int "Count/Compare Timer Frequency (MHz)"
>> 2091 depends on KVM_GUEST
>> 2092 default 100
>> 2093 help
>> 2094 Set this to non-zero if building a guest kernel for KVM to skip RTC
>> 2095 emulation when determining guest CPU Frequency. Instead, the guest's
>> 2096 timer frequency is specified directly.
>> 2097
>> 2098 config MIPS_VA_BITS_48
>> 2099 bool "48 bits virtual memory"
>> 2100 depends on 64BIT
>> 2101 help
>> 2102 Support a maximum at least 48 bits of application virtual
>> 2103 memory. Default is 40 bits or less, depending on the CPU.
>> 2104 For page sizes 16k and above, this option results in a small
>> 2105 memory overhead for page tables. For 4k page size, a fourth
>> 2106 level of page tables is added which imposes both a memory
>> 2107 overhead as well as slower TLB fault handling.
>> 2108
>> 2109 If unsure, say N.
>> 2110
1339 choice 2111 choice
1340 prompt "Virtual address space size" !! 2112 prompt "Kernel page size"
1341 default ARM64_VA_BITS_52 !! 2113 default PAGE_SIZE_4KB
1342 help <<
1343 Allows choosing one of multiple pos <<
1344 space sizes. The level of translati <<
1345 a combination of page size and virt <<
1346 <<
1347 config ARM64_VA_BITS_36 <<
1348 bool "36-bit" if EXPERT <<
1349 depends on PAGE_SIZE_16KB <<
1350 <<
1351 config ARM64_VA_BITS_39 <<
1352 bool "39-bit" <<
1353 depends on PAGE_SIZE_4KB <<
1354 <<
1355 config ARM64_VA_BITS_42 <<
1356 bool "42-bit" <<
1357 depends on PAGE_SIZE_64KB <<
1358 <<
1359 config ARM64_VA_BITS_47 <<
1360 bool "47-bit" <<
1361 depends on PAGE_SIZE_16KB <<
1362 <<
1363 config ARM64_VA_BITS_48 <<
1364 bool "48-bit" <<
1365 <<
1366 config ARM64_VA_BITS_52 <<
1367 bool "52-bit" <<
1368 depends on ARM64_PAN || !ARM64_SW_TTB <<
1369 help <<
1370 Enable 52-bit virtual addressing fo <<
1371 requested via a hint to mmap(). The <<
1372 virtual addresses for its own mappi <<
1373 this feature is available, otherwis <<
1374 <<
1375 NOTE: Enabling 52-bit virtual addre <<
1376 ARMv8.3 Pointer Authentication will <<
1377 reduced from 7 bits to 3 bits, whic <<
1378 impact on its susceptibility to bru <<
1379 2114
1380 If unsure, select 48-bit virtual ad !! 2115 config PAGE_SIZE_4KB
>> 2116 bool "4kB"
>> 2117 depends on !CPU_LOONGSON2 && !CPU_LOONGSON3
>> 2118 help
>> 2119 This option select the standard 4kB Linux page size. On some
>> 2120 R3000-family processors this is the only available page size. Using
>> 2121 4kB page size will minimize memory consumption and is therefore
>> 2122 recommended for low memory systems.
>> 2123
>> 2124 config PAGE_SIZE_8KB
>> 2125 bool "8kB"
>> 2126 depends on CPU_R8000 || CPU_CAVIUM_OCTEON
>> 2127 depends on !MIPS_VA_BITS_48
>> 2128 help
>> 2129 Using 8kB page size will result in higher performance kernel at
>> 2130 the price of higher memory consumption. This option is available
>> 2131 only on R8000 and cnMIPS processors. Note that you will need a
>> 2132 suitable Linux distribution to support this.
>> 2133
>> 2134 config PAGE_SIZE_16KB
>> 2135 bool "16kB"
>> 2136 depends on !CPU_R3000 && !CPU_TX39XX
>> 2137 help
>> 2138 Using 16kB page size will result in higher performance kernel at
>> 2139 the price of higher memory consumption. This option is available on
>> 2140 all non-R3000 family processors. Note that you will need a suitable
>> 2141 Linux distribution to support this.
>> 2142
>> 2143 config PAGE_SIZE_32KB
>> 2144 bool "32kB"
>> 2145 depends on CPU_CAVIUM_OCTEON
>> 2146 depends on !MIPS_VA_BITS_48
>> 2147 help
>> 2148 Using 32kB page size will result in higher performance kernel at
>> 2149 the price of higher memory consumption. This option is available
>> 2150 only on cnMIPS cores. Note that you will need a suitable Linux
>> 2151 distribution to support this.
>> 2152
>> 2153 config PAGE_SIZE_64KB
>> 2154 bool "64kB"
>> 2155 depends on !CPU_R3000 && !CPU_TX39XX
>> 2156 help
>> 2157 Using 64kB page size will result in higher performance kernel at
>> 2158 the price of higher memory consumption. This option is available on
>> 2159 all non-R3000 family processor. Not that at the time of this
>> 2160 writing this option is still high experimental.
1381 2161
1382 endchoice 2162 endchoice
1383 2163
1384 config ARM64_FORCE_52BIT !! 2164 config FORCE_MAX_ZONEORDER
1385 bool "Force 52-bit virtual addresses !! 2165 int "Maximum zone order"
1386 depends on ARM64_VA_BITS_52 && EXPERT !! 2166 range 14 64 if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_64KB
1387 help !! 2167 default "14" if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_64KB
1388 For systems with 52-bit userspace V !! 2168 range 13 64 if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_32KB
1389 to maintain compatibility with olde !! 2169 default "13" if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_32KB
1390 unless a hint is supplied to mmap. !! 2170 range 12 64 if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_16KB
1391 !! 2171 default "12" if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_16KB
1392 This configuration option disables !! 2172 range 11 64
1393 forces all userspace addresses to b !! 2173 default "11"
1394 should only enable this configurati !! 2174 help
1395 memory management code. If unsure s !! 2175 The kernel memory allocator divides physically contiguous memory
>> 2176 blocks into "zones", where each zone is a power of two number of
>> 2177 pages. This option selects the largest power of two that the kernel
>> 2178 keeps in the memory allocator. If you need to allocate very large
>> 2179 blocks of physically contiguous memory, then you may need to
>> 2180 increase this value.
1396 2181
1397 config ARM64_VA_BITS !! 2182 This config option is actually maximum order plus one. For example,
1398 int !! 2183 a value of 11 means that the largest free memory block is 2^10 pages.
1399 default 36 if ARM64_VA_BITS_36 <<
1400 default 39 if ARM64_VA_BITS_39 <<
1401 default 42 if ARM64_VA_BITS_42 <<
1402 default 47 if ARM64_VA_BITS_47 <<
1403 default 48 if ARM64_VA_BITS_48 <<
1404 default 52 if ARM64_VA_BITS_52 <<
1405 2184
1406 choice !! 2185 The page size is not necessarily 4KB. Keep this in mind
1407 prompt "Physical address space size" !! 2186 when choosing a value for this option.
1408 default ARM64_PA_BITS_48 <<
1409 help <<
1410 Choose the maximum physical address <<
1411 support. <<
1412 2187
1413 config ARM64_PA_BITS_48 !! 2188 config BOARD_SCACHE
1414 bool "48-bit" !! 2189 bool
1415 depends on ARM64_64K_PAGES || !ARM64_ <<
1416 <<
1417 config ARM64_PA_BITS_52 <<
1418 bool "52-bit" <<
1419 depends on ARM64_64K_PAGES || ARM64_V <<
1420 depends on ARM64_PAN || !ARM64_SW_TTB <<
1421 help <<
1422 Enable support for a 52-bit physica <<
1423 part of the ARMv8.2-LPA extension. <<
1424 <<
1425 With this enabled, the kernel will <<
1426 do not support ARMv8.2-LPA, but wit <<
1427 minor performance overhead). <<
1428 2190
1429 endchoice !! 2191 config IP22_CPU_SCACHE
>> 2192 bool
>> 2193 select BOARD_SCACHE
1430 2194
1431 config ARM64_PA_BITS !! 2195 #
1432 int !! 2196 # Support for a MIPS32 / MIPS64 style S-caches
1433 default 48 if ARM64_PA_BITS_48 !! 2197 #
1434 default 52 if ARM64_PA_BITS_52 !! 2198 config MIPS_CPU_SCACHE
>> 2199 bool
>> 2200 select BOARD_SCACHE
1435 2201
1436 config ARM64_LPA2 !! 2202 config R5000_CPU_SCACHE
1437 def_bool y !! 2203 bool
1438 depends on ARM64_PA_BITS_52 && !ARM64 !! 2204 select BOARD_SCACHE
1439 2205
1440 choice !! 2206 config RM7000_CPU_SCACHE
1441 prompt "Endianness" !! 2207 bool
1442 default CPU_LITTLE_ENDIAN !! 2208 select BOARD_SCACHE
1443 help <<
1444 Select the endianness of data acces <<
1445 applications will need to be compil <<
1446 that is selected here. <<
1447 2209
1448 config CPU_BIG_ENDIAN !! 2210 config SIBYTE_DMA_PAGEOPS
1449 bool "Build big-endian kernel" !! 2211 bool "Use DMA to clear/copy pages"
1450 # https://github.com/llvm/llvm-projec !! 2212 depends on CPU_SB1
1451 depends on AS_IS_GNU || AS_VERSION >= <<
1452 help 2213 help
1453 Say Y if you plan on running a kern !! 2214 Instead of using the CPU to zero and copy pages, use a Data Mover
>> 2215 channel. These DMA channels are otherwise unused by the standard
>> 2216 SiByte Linux port. Seems to give a small performance benefit.
1454 2217
1455 config CPU_LITTLE_ENDIAN !! 2218 config CPU_HAS_PREFETCH
1456 bool "Build little-endian kernel" !! 2219 bool
1457 help <<
1458 Say Y if you plan on running a kern <<
1459 This is usually the case for distri <<
1460 2220
1461 endchoice !! 2221 config CPU_GENERIC_DUMP_TLB
>> 2222 bool
>> 2223 default y if !(CPU_R3000 || CPU_R8000 || CPU_TX39XX)
1462 2224
1463 config SCHED_MC !! 2225 config CPU_R4K_FPU
1464 bool "Multi-core scheduler support" !! 2226 bool
1465 help !! 2227 default y if !(CPU_R3000 || CPU_TX39XX)
1466 Multi-core scheduler support improv <<
1467 making when dealing with multi-core <<
1468 increased overhead in some places. <<
1469 2228
1470 config SCHED_CLUSTER !! 2229 config CPU_R4K_CACHE_TLB
1471 bool "Cluster scheduler support" !! 2230 bool
1472 help !! 2231 default y if !(CPU_R3000 || CPU_R8000 || CPU_SB1 || CPU_TX39XX || CPU_CAVIUM_OCTEON)
1473 Cluster scheduler support improves !! 2232
1474 making when dealing with machines t !! 2233 config MIPS_MT_SMP
1475 Cluster usually means a couple of C !! 2234 bool "MIPS MT SMP support (1 TC on each available VPE)"
1476 by sharing mid-level caches, last-l !! 2235 default y
1477 busses. !! 2236 depends on SYS_SUPPORTS_MULTITHREADING && !CPU_MIPSR6 && !CPU_MICROMIPS
>> 2237 select CPU_MIPSR2_IRQ_VI
>> 2238 select CPU_MIPSR2_IRQ_EI
>> 2239 select SYNC_R4K
>> 2240 select MIPS_MT
>> 2241 select SMP
>> 2242 select SMP_UP
>> 2243 select SYS_SUPPORTS_SMP
>> 2244 select SYS_SUPPORTS_SCHED_SMT
>> 2245 select MIPS_PERF_SHARED_TC_COUNTERS
>> 2246 help
>> 2247 This is a kernel model which is known as SMVP. This is supported
>> 2248 on cores with the MT ASE and uses the available VPEs to implement
>> 2249 virtual processors which supports SMP. This is equivalent to the
>> 2250 Intel Hyperthreading feature. For further information go to
>> 2251 <http://www.imgtec.com/mips/mips-multithreading.asp>.
>> 2252
>> 2253 config MIPS_MT
>> 2254 bool
1478 2255
1479 config SCHED_SMT 2256 config SCHED_SMT
1480 bool "SMT scheduler support" !! 2257 bool "SMT (multithreading) scheduler support"
>> 2258 depends on SYS_SUPPORTS_SCHED_SMT
>> 2259 default n
1481 help 2260 help
1482 Improves the CPU scheduler's decisi !! 2261 SMT scheduler support improves the CPU scheduler's decision making
1483 MultiThreading at a cost of slightl !! 2262 when dealing with MIPS MT enabled cores at a cost of slightly
1484 places. If unsure say N here. !! 2263 increased overhead in some places. If unsure say N here.
1485 2264
1486 config NR_CPUS !! 2265 config SYS_SUPPORTS_SCHED_SMT
1487 int "Maximum number of CPUs (2-4096)" !! 2266 bool
1488 range 2 4096 <<
1489 default "512" <<
1490 2267
1491 config HOTPLUG_CPU !! 2268 config SYS_SUPPORTS_MULTITHREADING
1492 bool "Support for hot-pluggable CPUs" !! 2269 bool
1493 select GENERIC_IRQ_MIGRATION <<
1494 help <<
1495 Say Y here to experiment with turni <<
1496 can be controlled through /sys/devi <<
1497 2270
1498 # Common NUMA Features !! 2271 config MIPS_MT_FPAFF
1499 config NUMA !! 2272 bool "Dynamic FPU affinity for FP-intensive threads"
1500 bool "NUMA Memory Allocation and Sche !! 2273 default y
1501 select GENERIC_ARCH_NUMA !! 2274 depends on MIPS_MT_SMP
1502 select OF_NUMA <<
1503 select HAVE_SETUP_PER_CPU_AREA <<
1504 select NEED_PER_CPU_EMBED_FIRST_CHUNK <<
1505 select NEED_PER_CPU_PAGE_FIRST_CHUNK <<
1506 select USE_PERCPU_NUMA_NODE_ID <<
1507 help <<
1508 Enable NUMA (Non-Uniform Memory Acc <<
1509 <<
1510 The kernel will try to allocate mem <<
1511 local memory of the CPU and add som <<
1512 NUMA awareness to the kernel. <<
1513 2275
1514 config NODES_SHIFT !! 2276 config MIPSR2_TO_R6_EMULATOR
1515 int "Maximum NUMA Nodes (as a power o !! 2277 bool "MIPS R2-to-R6 emulator"
1516 range 1 10 !! 2278 depends on CPU_MIPSR6
1517 default "4" !! 2279 default y
1518 depends on NUMA <<
1519 help 2280 help
1520 Specify the maximum number of NUMA !! 2281 Choose this option if you want to run non-R6 MIPS userland code.
1521 system. Increases memory reserved !! 2282 Even if you say 'Y' here, the emulator will still be disabled by
>> 2283 default. You can enable it using the 'mipsr2emu' kernel option.
>> 2284 The only reason this is a build-time option is to save ~14K from the
>> 2285 final kernel image.
1522 2286
1523 source "kernel/Kconfig.hz" !! 2287 config SYS_SUPPORTS_VPE_LOADER
>> 2288 bool
>> 2289 depends on SYS_SUPPORTS_MULTITHREADING
>> 2290 help
>> 2291 Indicates that the platform supports the VPE loader, and provides
>> 2292 physical_memsize.
1524 2293
1525 config ARCH_SPARSEMEM_ENABLE !! 2294 config MIPS_VPE_LOADER
1526 def_bool y !! 2295 bool "VPE loader support."
1527 select SPARSEMEM_VMEMMAP_ENABLE !! 2296 depends on SYS_SUPPORTS_VPE_LOADER && MODULES
1528 select SPARSEMEM_VMEMMAP !! 2297 select CPU_MIPSR2_IRQ_VI
>> 2298 select CPU_MIPSR2_IRQ_EI
>> 2299 select MIPS_MT
>> 2300 help
>> 2301 Includes a loader for loading an elf relocatable object
>> 2302 onto another VPE and running it.
1529 2303
1530 config HW_PERF_EVENTS !! 2304 config MIPS_VPE_LOADER_CMP
1531 def_bool y !! 2305 bool
1532 depends on ARM_PMU !! 2306 default "y"
>> 2307 depends on MIPS_VPE_LOADER && MIPS_CMP
1533 2308
1534 # Supported by clang >= 7.0 or GCC >= 12.0.0 !! 2309 config MIPS_VPE_LOADER_MT
1535 config CC_HAVE_SHADOW_CALL_STACK !! 2310 bool
1536 def_bool $(cc-option, -fsanitize=shad !! 2311 default "y"
>> 2312 depends on MIPS_VPE_LOADER && !MIPS_CMP
1537 2313
1538 config PARAVIRT !! 2314 config MIPS_VPE_LOADER_TOM
1539 bool "Enable paravirtualization code" !! 2315 bool "Load VPE program into memory hidden from linux"
>> 2316 depends on MIPS_VPE_LOADER
>> 2317 default y
1540 help 2318 help
1541 This changes the kernel so it can m !! 2319 The loader can use memory that is present but has been hidden from
1542 under a hypervisor, potentially imp !! 2320 Linux using the kernel command line option "mem=xxMB". It's up to
1543 over full virtualization. !! 2321 you to ensure the amount you put in the option and the space your
>> 2322 program requires is less or equal to the amount physically present.
1544 2323
1545 config PARAVIRT_TIME_ACCOUNTING !! 2324 config MIPS_VPE_APSP_API
1546 bool "Paravirtual steal time accounti !! 2325 bool "Enable support for AP/SP API (RTLX)"
1547 select PARAVIRT !! 2326 depends on MIPS_VPE_LOADER
1548 help 2327 help
1549 Select this option to enable fine g <<
1550 accounting. Time spent executing ot <<
1551 the current vCPU is discounted from <<
1552 that, there can be a small performa <<
1553 2328
1554 If in doubt, say N here. !! 2329 config MIPS_VPE_APSP_API_CMP
>> 2330 bool
>> 2331 default "y"
>> 2332 depends on MIPS_VPE_APSP_API && MIPS_CMP
1555 2333
1556 config ARCH_SUPPORTS_KEXEC !! 2334 config MIPS_VPE_APSP_API_MT
1557 def_bool PM_SLEEP_SMP !! 2335 bool
>> 2336 default "y"
>> 2337 depends on MIPS_VPE_APSP_API && !MIPS_CMP
1558 2338
1559 config ARCH_SUPPORTS_KEXEC_FILE !! 2339 config MIPS_CMP
1560 def_bool y !! 2340 bool "MIPS CMP framework support (DEPRECATED)"
>> 2341 depends on SYS_SUPPORTS_MIPS_CMP && !CPU_MIPSR6
>> 2342 select SMP
>> 2343 select SYNC_R4K
>> 2344 select SYS_SUPPORTS_SMP
>> 2345 select WEAK_ORDERING
>> 2346 default n
>> 2347 help
>> 2348 Select this if you are using a bootloader which implements the "CMP
>> 2349 framework" protocol (ie. YAMON) and want your kernel to make use of
>> 2350 its ability to start secondary CPUs.
>> 2351
>> 2352 Unless you have a specific need, you should use CONFIG_MIPS_CPS
>> 2353 instead of this.
>> 2354
>> 2355 config MIPS_CPS
>> 2356 bool "MIPS Coherent Processing System support"
>> 2357 depends on SYS_SUPPORTS_MIPS_CPS
>> 2358 select MIPS_CM
>> 2359 select MIPS_CPS_PM if HOTPLUG_CPU
>> 2360 select SMP
>> 2361 select SYNC_R4K if (CEVT_R4K || CSRC_R4K)
>> 2362 select SYS_SUPPORTS_HOTPLUG_CPU
>> 2363 select SYS_SUPPORTS_SCHED_SMT if CPU_MIPSR6
>> 2364 select SYS_SUPPORTS_SMP
>> 2365 select WEAK_ORDERING
>> 2366 help
>> 2367 Select this if you wish to run an SMP kernel across multiple cores
>> 2368 within a MIPS Coherent Processing System. When this option is
>> 2369 enabled the kernel will probe for other cores and boot them with
>> 2370 no external assistance. It is safe to enable this when hardware
>> 2371 support is unavailable.
1561 2372
1562 config ARCH_SELECTS_KEXEC_FILE !! 2373 config MIPS_CPS_PM
1563 def_bool y !! 2374 depends on MIPS_CPS
1564 depends on KEXEC_FILE !! 2375 bool
1565 select HAVE_IMA_KEXEC if IMA <<
1566 2376
1567 config ARCH_SUPPORTS_KEXEC_SIG !! 2377 config MIPS_CM
1568 def_bool y !! 2378 bool
>> 2379 select MIPS_CPC
1569 2380
1570 config ARCH_SUPPORTS_KEXEC_IMAGE_VERIFY_SIG !! 2381 config MIPS_CPC
1571 def_bool y !! 2382 bool
1572 2383
1573 config ARCH_DEFAULT_KEXEC_IMAGE_VERIFY_SIG !! 2384 config SB1_PASS_2_WORKAROUNDS
1574 def_bool y !! 2385 bool
>> 2386 depends on CPU_SB1 && (CPU_SB1_PASS_2_2 || CPU_SB1_PASS_2)
>> 2387 default y
1575 2388
1576 config ARCH_SUPPORTS_CRASH_DUMP !! 2389 config SB1_PASS_2_1_WORKAROUNDS
1577 def_bool y !! 2390 bool
>> 2391 depends on CPU_SB1 && CPU_SB1_PASS_2
>> 2392 default y
1578 2393
1579 config ARCH_HAS_GENERIC_CRASHKERNEL_RESERVATI <<
1580 def_bool CRASH_RESERVE <<
1581 2394
1582 config TRANS_TABLE !! 2395 config ARCH_PHYS_ADDR_T_64BIT
1583 def_bool y !! 2396 bool
1584 depends on HIBERNATION || KEXEC_CORE <<
1585 2397
1586 config XEN_DOM0 !! 2398 choice
1587 def_bool y !! 2399 prompt "SmartMIPS or microMIPS ASE support"
1588 depends on XEN <<
1589 2400
1590 config XEN !! 2401 config CPU_NEEDS_NO_SMARTMIPS_OR_MICROMIPS
1591 bool "Xen guest support on ARM64" !! 2402 bool "None"
1592 depends on ARM64 && OF <<
1593 select SWIOTLB_XEN <<
1594 select PARAVIRT <<
1595 help 2403 help
1596 Say Y if you want to run Linux in a !! 2404 Select this if you want neither microMIPS nor SmartMIPS support
1597 2405
1598 # include/linux/mmzone.h requires the followi !! 2406 config CPU_HAS_SMARTMIPS
1599 # !! 2407 depends on SYS_SUPPORTS_SMARTMIPS
1600 # MAX_PAGE_ORDER + PAGE_SHIFT <= SECTION_SI !! 2408 bool "SmartMIPS"
1601 # !! 2409 help
1602 # so the maximum value of MAX_PAGE_ORDER is S !! 2410 SmartMIPS is a extension of the MIPS32 architecture aimed at
1603 # !! 2411 increased security at both hardware and software level for
1604 # | SECTION_SIZE_BITS | PAGE_SHIFT | m !! 2412 smartcards. Enabling this option will allow proper use of the
1605 # ----+-------------------+--------------+--- !! 2413 SmartMIPS instructions by Linux applications. However a kernel with
1606 # 4K | 27 | 12 | !! 2414 this option will not work on a MIPS core without SmartMIPS core. If
1607 # 16K | 27 | 14 | !! 2415 you don't know you probably don't have SmartMIPS and should say N
1608 # 64K | 29 | 16 | !! 2416 here.
1609 config ARCH_FORCE_MAX_ORDER !! 2417
1610 int !! 2418 config CPU_MICROMIPS
1611 default "13" if ARM64_64K_PAGES !! 2419 depends on 32BIT && SYS_SUPPORTS_MICROMIPS && !CPU_MIPSR6
1612 default "11" if ARM64_16K_PAGES !! 2420 bool "microMIPS"
1613 default "10" <<
1614 help 2421 help
1615 The kernel page allocator limits th !! 2422 When this option is enabled the kernel will be built using the
1616 contiguous allocations. The limit i !! 2423 microMIPS ISA
1617 defines the maximal power of two of <<
1618 allocated as a single contiguous bl <<
1619 overriding the default setting when <<
1620 large blocks of physically contiguo <<
1621 <<
1622 The maximal size of allocation cann <<
1623 section, so the value of MAX_PAGE_O <<
1624 2424
1625 MAX_PAGE_ORDER + PAGE_SHIFT <= SE !! 2425 endchoice
1626 <<
1627 Don't change if unsure. <<
1628 2426
1629 config UNMAP_KERNEL_AT_EL0 !! 2427 config CPU_HAS_MSA
1630 bool "Unmap kernel when running in us !! 2428 bool "Support for the MIPS SIMD Architecture"
1631 default y !! 2429 depends on CPU_SUPPORTS_MSA
1632 help !! 2430 depends on 64BIT || MIPS_O32_FP64_SUPPORT
1633 Speculation attacks against some hi !! 2431 help
1634 be used to bypass MMU permission ch !! 2432 MIPS SIMD Architecture (MSA) introduces 128 bit wide vector registers
1635 userspace. This can be defended aga !! 2433 and a set of SIMD instructions to operate on them. When this option
1636 when running in userspace, mapping !! 2434 is enabled the kernel will support allocating & switching MSA
1637 via a trampoline page in the vector !! 2435 vector register contexts. If you know that your kernel will only be
>> 2436 running on CPUs which do not support MSA or that your userland will
>> 2437 not be making use of it then you may wish to say N here to reduce
>> 2438 the size & complexity of your kernel.
1638 2439
1639 If unsure, say Y. 2440 If unsure, say Y.
1640 2441
1641 config MITIGATE_SPECTRE_BRANCH_HISTORY !! 2442 config CPU_HAS_WB
1642 bool "Mitigate Spectre style attacks !! 2443 bool
1643 default y <<
1644 help <<
1645 Speculation attacks against some hi <<
1646 make use of branch history to influ <<
1647 When taking an exception from user- <<
1648 or a firmware call overwrites the b <<
1649 2444
1650 config RODATA_FULL_DEFAULT_ENABLED !! 2445 config XKS01
1651 bool "Apply r/o permissions of VM are !! 2446 bool
1652 default y !! 2447
1653 help !! 2448 config CPU_HAS_RIXI
1654 Apply read-only attributes of VM ar !! 2449 bool
1655 the backing pages as well. This pre <<
1656 from being modified (inadvertently <<
1657 mapping of the same memory page. Th <<
1658 be turned off at runtime by passing <<
1659 with rodata=full if this option is <<
1660 2450
1661 This requires the linear region to !! 2451 #
1662 which may adversely affect performa !! 2452 # Vectored interrupt mode is an R2 feature
>> 2453 #
>> 2454 config CPU_MIPSR2_IRQ_VI
>> 2455 bool
1663 2456
1664 config ARM64_SW_TTBR0_PAN !! 2457 #
1665 bool "Emulate Privileged Access Never !! 2458 # Extended interrupt mode is an R2 feature
1666 depends on !KCSAN !! 2459 #
1667 help !! 2460 config CPU_MIPSR2_IRQ_EI
1668 Enabling this option prevents the k !! 2461 bool
1669 user-space memory directly by point <<
1670 zeroed area and reserved ASID. The <<
1671 restore the valid TTBR0_EL1 tempora <<
1672 2462
1673 config ARM64_TAGGED_ADDR_ABI !! 2463 config CPU_HAS_SYNC
1674 bool "Enable the tagged user addresse !! 2464 bool
>> 2465 depends on !CPU_R3000
1675 default y 2466 default y
1676 help <<
1677 When this option is enabled, user a <<
1678 relaxed ABI via prctl() allowing ta <<
1679 to system calls as pointer argument <<
1680 Documentation/arch/arm64/tagged-add <<
1681 <<
1682 menuconfig COMPAT <<
1683 bool "Kernel support for 32-bit EL0" <<
1684 depends on ARM64_4K_PAGES || EXPERT <<
1685 select HAVE_UID16 <<
1686 select OLD_SIGSUSPEND3 <<
1687 select COMPAT_OLD_SIGACTION <<
1688 help <<
1689 This option enables support for a 3 <<
1690 kernel at EL1. AArch32-specific com <<
1691 the user helper functions, VFP supp <<
1692 handled appropriately by the kernel <<
1693 2467
1694 If you use a page size other than 4 !! 2468 #
1695 that you will only be able to execu !! 2469 # CPU non-features
1696 with page size aligned segments. !! 2470 #
>> 2471 config CPU_DADDI_WORKAROUNDS
>> 2472 bool
1697 2473
1698 If you want to execute 32-bit users !! 2474 config CPU_R4000_WORKAROUNDS
>> 2475 bool
>> 2476 select CPU_R4400_WORKAROUNDS
1699 2477
1700 if COMPAT !! 2478 config CPU_R4400_WORKAROUNDS
>> 2479 bool
1701 2480
1702 config KUSER_HELPERS !! 2481 config MIPS_ASID_SHIFT
1703 bool "Enable kuser helpers page for 3 !! 2482 int
1704 default y !! 2483 default 6 if CPU_R3000 || CPU_TX39XX
1705 help !! 2484 default 4 if CPU_R8000
1706 Warning: disabling this option may !! 2485 default 0
1707 2486
1708 Provide kuser helpers to compat tas !! 2487 config MIPS_ASID_BITS
1709 helper code to userspace in read on !! 2488 int
1710 to allow userspace to be independen !! 2489 default 0 if MIPS_ASID_BITS_VARIABLE
1711 the system. This permits binaries t !! 2490 default 6 if CPU_R3000 || CPU_TX39XX
1712 to ARMv8 without modification. !! 2491 default 8
1713 2492
1714 See Documentation/arch/arm/kernel_u !! 2493 config MIPS_ASID_BITS_VARIABLE
>> 2494 bool
1715 2495
1716 However, the fixed address nature o !! 2496 #
1717 by ROP (return orientated programmi !! 2497 # - Highmem only makes sense for the 32-bit kernel.
1718 exploits. !! 2498 # - The current highmem code will only work properly on physically indexed
>> 2499 # caches such as R3000, SB1, R7000 or those that look like they're virtually
>> 2500 # indexed such as R4000/R4400 SC and MC versions or R10000. So for the
>> 2501 # moment we protect the user and offer the highmem option only on machines
>> 2502 # where it's known to be safe. This will not offer highmem on a few systems
>> 2503 # such as MIPS32 and MIPS64 CPUs which may have virtual and physically
>> 2504 # indexed CPUs but we're playing safe.
>> 2505 # - We use SYS_SUPPORTS_HIGHMEM to offer highmem only for systems where we
>> 2506 # know they might have memory configurations that could make use of highmem
>> 2507 # support.
>> 2508 #
>> 2509 config HIGHMEM
>> 2510 bool "High Memory Support"
>> 2511 depends on 32BIT && CPU_SUPPORTS_HIGHMEM && SYS_SUPPORTS_HIGHMEM && !CPU_MIPS32_3_5_EVA
1719 2512
1720 If all of the binaries and librarie !! 2513 config CPU_SUPPORTS_HIGHMEM
1721 are built specifically for your pla !! 2514 bool
1722 these helpers, then you can turn th <<
1723 such exploits. However, in that cas <<
1724 relying on those helpers is run, it <<
1725 2515
1726 Say N here only if you are absolute !! 2516 config SYS_SUPPORTS_HIGHMEM
1727 need these helpers; otherwise, the !! 2517 bool
1728 2518
1729 config COMPAT_VDSO !! 2519 config SYS_SUPPORTS_SMARTMIPS
1730 bool "Enable vDSO for 32-bit applicat !! 2520 bool
1731 depends on !CPU_BIG_ENDIAN <<
1732 depends on (CC_IS_CLANG && LD_IS_LLD) <<
1733 select GENERIC_COMPAT_VDSO <<
1734 default y <<
1735 help <<
1736 Place in the process address space <<
1737 ELF shared object providing fast im <<
1738 and clock_gettime. <<
1739 2521
1740 You must have a 32-bit build of gli !! 2522 config SYS_SUPPORTS_MICROMIPS
1741 to seamlessly take advantage of thi !! 2523 bool
1742 2524
1743 config THUMB2_COMPAT_VDSO !! 2525 config SYS_SUPPORTS_MIPS16
1744 bool "Compile the 32-bit vDSO for Thu !! 2526 bool
1745 depends on COMPAT_VDSO <<
1746 default y <<
1747 help 2527 help
1748 Compile the compat vDSO with '-mthu !! 2528 This option must be set if a kernel might be executed on a MIPS16-
1749 otherwise with '-marm'. !! 2529 enabled CPU even if MIPS16 is not actually being used. In other
1750 !! 2530 words, it makes the kernel MIPS16-tolerant.
1751 config COMPAT_ALIGNMENT_FIXUPS <<
1752 bool "Fix up misaligned multi-word lo <<
1753 2531
1754 menuconfig ARMV8_DEPRECATED !! 2532 config CPU_SUPPORTS_MSA
1755 bool "Emulate deprecated/obsolete ARM !! 2533 bool
1756 depends on SYSCTL <<
1757 help <<
1758 Legacy software support may require <<
1759 that have been deprecated or obsole <<
1760 2534
1761 Enable this config to enable select !! 2535 config ARCH_FLATMEM_ENABLE
1762 features. !! 2536 def_bool y
>> 2537 depends on !NUMA && !CPU_LOONGSON2
1763 2538
1764 If unsure, say Y !! 2539 config ARCH_DISCONTIGMEM_ENABLE
>> 2540 bool
>> 2541 default y if SGI_IP27
>> 2542 help
>> 2543 Say Y to support efficient handling of discontiguous physical memory,
>> 2544 for architectures which are either NUMA (Non-Uniform Memory Access)
>> 2545 or have huge holes in the physical address space for other reasons.
>> 2546 See <file:Documentation/vm/numa> for more.
1765 2547
1766 if ARMV8_DEPRECATED !! 2548 config ARCH_SPARSEMEM_ENABLE
>> 2549 bool
>> 2550 select SPARSEMEM_STATIC
1767 2551
1768 config SWP_EMULATION !! 2552 config NUMA
1769 bool "Emulate SWP/SWPB instructions" !! 2553 bool "NUMA Support"
>> 2554 depends on SYS_SUPPORTS_NUMA
1770 help 2555 help
1771 ARMv8 obsoletes the use of A32 SWP/ !! 2556 Say Y to compile the kernel to support NUMA (Non-Uniform Memory
1772 they are always undefined. Say Y he !! 2557 Access). This option improves performance on systems with more
1773 emulation of these instructions for !! 2558 than two nodes; on two node systems it is generally better to
1774 This feature can be controlled at r !! 2559 leave it disabled; on single node systems disable this option
1775 sysctl which is disabled by default !! 2560 disabled.
1776 2561
1777 In some older versions of glibc [<= !! 2562 config SYS_SUPPORTS_NUMA
1778 trylock() operations with the assum !! 2563 bool
1779 be preempted. This invalid assumpti <<
1780 with SWP emulation enabled, leading <<
1781 application. <<
1782 2564
1783 NOTE: when accessing uncached share !! 2565 config RELOCATABLE
1784 on an external transaction monitori !! 2566 bool "Relocatable kernel"
1785 monitor to maintain update atomicit !! 2567 depends on SYS_SUPPORTS_RELOCATABLE && (CPU_MIPS32_R2 || CPU_MIPS64_R2 || CPU_MIPS32_R6 || CPU_MIPS64_R6 || CAVIUM_OCTEON_SOC)
1786 implement a global monitor, this op !! 2568 help
1787 perform SWP operations to uncached !! 2569 This builds a kernel image that retains relocation information
>> 2570 so it can be loaded someplace besides the default 1MB.
>> 2571 The relocations make the kernel binary about 15% larger,
>> 2572 but are discarded at runtime
>> 2573
>> 2574 config RELOCATION_TABLE_SIZE
>> 2575 hex "Relocation table size"
>> 2576 depends on RELOCATABLE
>> 2577 range 0x0 0x01000000
>> 2578 default "0x00100000"
>> 2579 ---help---
>> 2580 A table of relocation data will be appended to the kernel binary
>> 2581 and parsed at boot to fix up the relocated kernel.
1788 2582
1789 If unsure, say Y !! 2583 This option allows the amount of space reserved for the table to be
>> 2584 adjusted, although the default of 1Mb should be ok in most cases.
1790 2585
1791 config CP15_BARRIER_EMULATION !! 2586 The build will fail and a valid size suggested if this is too small.
1792 bool "Emulate CP15 Barrier instructio <<
1793 help <<
1794 The CP15 barrier instructions - CP1 <<
1795 CP15DMB - are deprecated in ARMv8 ( <<
1796 strongly recommended to use the ISB <<
1797 instructions instead. <<
1798 2587
1799 Say Y here to enable software emula !! 2588 If unsure, leave at the default value.
1800 instructions for AArch32 userspace <<
1801 enabled, CP15 barrier usage is trac <<
1802 identify software that needs updati <<
1803 controlled at runtime with the abi. <<
1804 2589
1805 If unsure, say Y !! 2590 config RANDOMIZE_BASE
>> 2591 bool "Randomize the address of the kernel image"
>> 2592 depends on RELOCATABLE
>> 2593 ---help---
>> 2594 Randomizes the physical and virtual address at which the
>> 2595 kernel image is loaded, as a security feature that
>> 2596 deters exploit attempts relying on knowledge of the location
>> 2597 of kernel internals.
1806 2598
1807 config SETEND_EMULATION !! 2599 Entropy is generated using any coprocessor 0 registers available.
1808 bool "Emulate SETEND instruction" <<
1809 help <<
1810 The SETEND instruction alters the d <<
1811 AArch32 EL0, and is deprecated in A <<
1812 2600
1813 Say Y here to enable software emula !! 2601 The kernel will be offset by up to RANDOMIZE_BASE_MAX_OFFSET.
1814 for AArch32 userspace code. This fe <<
1815 at runtime with the abi.setend sysc <<
1816 2602
1817 Note: All the cpus on the system mu !! 2603 If unsure, say N.
1818 for this feature to be enabled. If <<
1819 endian - is hotplugged in after thi <<
1820 be unexpected results in the applic <<
1821 2604
1822 If unsure, say Y !! 2605 config RANDOMIZE_BASE_MAX_OFFSET
1823 endif # ARMV8_DEPRECATED !! 2606 hex "Maximum kASLR offset" if EXPERT
>> 2607 depends on RANDOMIZE_BASE
>> 2608 range 0x0 0x40000000 if EVA || 64BIT
>> 2609 range 0x0 0x08000000
>> 2610 default "0x01000000"
>> 2611 ---help---
>> 2612 When kASLR is active, this provides the maximum offset that will
>> 2613 be applied to the kernel image. It should be set according to the
>> 2614 amount of physical RAM available in the target system minus
>> 2615 PHYSICAL_START and must be a power of 2.
1824 2616
1825 endif # COMPAT !! 2617 This is limited by the size of KSEG0, 256Mb on 32-bit or 1Gb with
>> 2618 EVA or 64-bit. The default is 16Mb.
1826 2619
1827 menu "ARMv8.1 architectural features" !! 2620 config NODES_SHIFT
>> 2621 int
>> 2622 default "6"
>> 2623 depends on NEED_MULTIPLE_NODES
1828 2624
1829 config ARM64_HW_AFDBM !! 2625 config HW_PERF_EVENTS
1830 bool "Support for hardware updates of !! 2626 bool "Enable hardware performance counter support for perf events"
>> 2627 depends on PERF_EVENTS && !OPROFILE && (CPU_MIPS32 || CPU_MIPS64 || CPU_R10000 || CPU_SB1 || CPU_CAVIUM_OCTEON || CPU_XLP || CPU_LOONGSON3)
1831 default y 2628 default y
1832 help 2629 help
1833 The ARMv8.1 architecture extensions !! 2630 Enable hardware performance counter support for perf events. If
1834 hardware updates of the access and !! 2631 disabled, perf events will use software events only.
1835 table entries. When enabled in TCR_ <<
1836 capable processors, accesses to pag <<
1837 set this bit instead of raising an <<
1838 Similarly, writes to read-only page <<
1839 clear the read-only bit (AP[2]) ins <<
1840 permission fault. <<
1841 2632
1842 Kernels built with this configurati !! 2633 source "mm/Kconfig"
1843 to work on pre-ARMv8.1 hardware and <<
1844 minimal. If unsure, say Y. <<
1845 2634
1846 config ARM64_PAN !! 2635 config SMP
1847 bool "Enable support for Privileged A !! 2636 bool "Multi-Processing support"
1848 default y !! 2637 depends on SYS_SUPPORTS_SMP
1849 help 2638 help
1850 Privileged Access Never (PAN; part !! 2639 This enables support for systems with more than one CPU. If you have
1851 prevents the kernel or hypervisor f !! 2640 a system with only one CPU, say N. If you have a system with more
1852 memory directly. !! 2641 than one CPU, say Y.
1853 !! 2642
1854 Choosing this option will cause any !! 2643 If you say N here, the kernel will run on uni- and multiprocessor
1855 copy_to_user et al) memory access t !! 2644 machines, but will use only one CPU of a multiprocessor machine. If
>> 2645 you say Y here, the kernel will run on many, but not all,
>> 2646 uniprocessor machines. On a uniprocessor machine, the kernel
>> 2647 will run faster if you say N here.
1856 2648
1857 The feature is detected at runtime, !! 2649 People using multiprocessor machines who say Y here should also say
1858 instruction if the cpu does not imp !! 2650 Y to "Enhanced Real Time Clock Support", below.
1859 2651
1860 config AS_HAS_LSE_ATOMICS !! 2652 See also the SMP-HOWTO available at
1861 def_bool $(as-instr,.arch_extension l !! 2653 <http://www.tldp.org/docs.html#howto>.
1862 2654
1863 config ARM64_LSE_ATOMICS !! 2655 If you don't know what to do here, say N.
1864 bool <<
1865 default ARM64_USE_LSE_ATOMICS <<
1866 depends on AS_HAS_LSE_ATOMICS <<
1867 2656
1868 config ARM64_USE_LSE_ATOMICS !! 2657 config HOTPLUG_CPU
1869 bool "Atomic instructions" !! 2658 bool "Support for hot-pluggable CPUs"
1870 default y !! 2659 depends on SMP && SYS_SUPPORTS_HOTPLUG_CPU
1871 help 2660 help
1872 As part of the Large System Extensi !! 2661 Say Y here to allow turning CPUs off and on. CPUs can be
1873 atomic instructions that are design !! 2662 controlled through /sys/devices/system/cpu.
1874 very large systems. !! 2663 (Note: power management support will enable this option
>> 2664 automatically on SMP systems. )
>> 2665 Say N if you want to disable CPU hotplug.
1875 2666
1876 Say Y here to make use of these ins !! 2667 config SMP_UP
1877 atomic routines. This incurs a smal !! 2668 bool
1878 not support these instructions and <<
1879 built with binutils >= 2.25 in orde <<
1880 to be used. <<
1881 2669
1882 endmenu # "ARMv8.1 architectural features" !! 2670 config SYS_SUPPORTS_MIPS_CMP
>> 2671 bool
1883 2672
1884 menu "ARMv8.2 architectural features" !! 2673 config SYS_SUPPORTS_MIPS_CPS
>> 2674 bool
1885 2675
1886 config AS_HAS_ARMV8_2 !! 2676 config SYS_SUPPORTS_SMP
1887 def_bool $(cc-option,-Wa$(comma)-marc !! 2677 bool
1888 2678
1889 config AS_HAS_SHA3 !! 2679 config NR_CPUS_DEFAULT_4
1890 def_bool $(as-instr,.arch armv8.2-a+s !! 2680 bool
1891 2681
1892 config ARM64_PMEM !! 2682 config NR_CPUS_DEFAULT_8
1893 bool "Enable support for persistent m !! 2683 bool
1894 select ARCH_HAS_PMEM_API <<
1895 select ARCH_HAS_UACCESS_FLUSHCACHE <<
1896 help <<
1897 Say Y to enable support for the per <<
1898 ARMv8.2 DCPoP feature. <<
1899 2684
1900 The feature is detected at runtime, !! 2685 config NR_CPUS_DEFAULT_16
1901 operations if DC CVAP is not suppor !! 2686 bool
1902 DC CVAP itself if the system does n <<
1903 2687
1904 config ARM64_RAS_EXTN !! 2688 config NR_CPUS_DEFAULT_32
1905 bool "Enable support for RAS CPU Exte !! 2689 bool
1906 default y <<
1907 help <<
1908 CPUs that support the Reliability, <<
1909 (RAS) Extensions, part of ARMv8.2 a <<
1910 errors, classify them and report th <<
1911 2690
1912 On CPUs with these extensions syste !! 2691 config NR_CPUS_DEFAULT_64
1913 barriers to determine if faults are !! 2692 bool
1914 classification from a new set of re <<
1915 2693
1916 Selecting this feature will allow t !! 2694 config NR_CPUS
1917 and access the new registers if the !! 2695 int "Maximum number of CPUs (2-256)"
1918 Platform RAS features may additiona !! 2696 range 2 256
>> 2697 depends on SMP
>> 2698 default "4" if NR_CPUS_DEFAULT_4
>> 2699 default "8" if NR_CPUS_DEFAULT_8
>> 2700 default "16" if NR_CPUS_DEFAULT_16
>> 2701 default "32" if NR_CPUS_DEFAULT_32
>> 2702 default "64" if NR_CPUS_DEFAULT_64
>> 2703 help
>> 2704 This allows you to specify the maximum number of CPUs which this
>> 2705 kernel will support. The maximum supported value is 32 for 32-bit
>> 2706 kernel and 64 for 64-bit kernels; the minimum value which makes
>> 2707 sense is 1 for Qemu (useful only for kernel debugging purposes)
>> 2708 and 2 for all others.
>> 2709
>> 2710 This is purely to save memory - each supported CPU adds
>> 2711 approximately eight kilobytes to the kernel image. For best
>> 2712 performance should round up your number of processors to the next
>> 2713 power of two.
1919 2714
1920 config ARM64_CNP !! 2715 config MIPS_PERF_SHARED_TC_COUNTERS
1921 bool "Enable support for Common Not P !! 2716 bool
1922 default y <<
1923 depends on ARM64_PAN || !ARM64_SW_TTB <<
1924 help <<
1925 Common Not Private (CNP) allows tra <<
1926 be shared between different PEs in <<
1927 domain, so the hardware can use thi <<
1928 caching of such entries in the TLB. <<
1929 2717
1930 Selecting this option allows the CN !! 2718 config MIPS_NR_CPU_NR_MAP_1024
1931 at runtime, and does not affect PEs !! 2719 bool
1932 this feature. <<
1933 2720
1934 endmenu # "ARMv8.2 architectural features" !! 2721 config MIPS_NR_CPU_NR_MAP
>> 2722 int
>> 2723 depends on SMP
>> 2724 default 1024 if MIPS_NR_CPU_NR_MAP_1024
>> 2725 default NR_CPUS if !MIPS_NR_CPU_NR_MAP_1024
1935 2726
1936 menu "ARMv8.3 architectural features" !! 2727 #
>> 2728 # Timer Interrupt Frequency Configuration
>> 2729 #
1937 2730
1938 config ARM64_PTR_AUTH !! 2731 choice
1939 bool "Enable support for pointer auth !! 2732 prompt "Timer frequency"
1940 default y !! 2733 default HZ_250
1941 help 2734 help
1942 Pointer authentication (part of the !! 2735 Allows the configuration of the timer frequency.
1943 instructions for signing and authen <<
1944 keys, which can be used to mitigate <<
1945 and other attacks. <<
1946 2736
1947 This option enables these instructi !! 2737 config HZ_24
1948 Choosing this option will cause the !! 2738 bool "24 HZ" if SYS_SUPPORTS_24HZ || SYS_SUPPORTS_ARBIT_HZ
1949 for each process at exec() time, wi <<
1950 context-switched along with the pro <<
1951 2739
1952 The feature is detected at runtime. !! 2740 config HZ_48
1953 hardware it will not be advertised !! 2741 bool "48 HZ" if SYS_SUPPORTS_48HZ || SYS_SUPPORTS_ARBIT_HZ
1954 be enabled. <<
1955 2742
1956 If the feature is present on the bo !! 2743 config HZ_100
1957 the late CPU will be parked. Also, !! 2744 bool "100 HZ" if SYS_SUPPORTS_100HZ || SYS_SUPPORTS_ARBIT_HZ
1958 address auth and the late CPU has t <<
1959 but with the feature disabled. On s <<
1960 not be selected. <<
1961 2745
1962 config ARM64_PTR_AUTH_KERNEL !! 2746 config HZ_128
1963 bool "Use pointer authentication for !! 2747 bool "128 HZ" if SYS_SUPPORTS_128HZ || SYS_SUPPORTS_ARBIT_HZ
1964 default y <<
1965 depends on ARM64_PTR_AUTH <<
1966 depends on (CC_HAS_SIGN_RETURN_ADDRES <<
1967 # Modern compilers insert a .note.gnu <<
1968 # which is only understood by binutil <<
1969 depends on LD_IS_LLD || LD_VERSION >= <<
1970 depends on !CC_IS_CLANG || AS_HAS_CFI <<
1971 depends on (!FUNCTION_GRAPH_TRACER || <<
1972 help <<
1973 If the compiler supports the -mbran <<
1974 -msign-return-address flag (e.g. GC <<
1975 will cause the kernel itself to be <<
1976 protection. In this case, and if th <<
1977 support pointer authentication, the <<
1978 disabled with minimal loss of prote <<
1979 2748
1980 This feature works with FUNCTION_GR !! 2749 config HZ_250
1981 DYNAMIC_FTRACE_WITH_ARGS is enabled !! 2750 bool "250 HZ" if SYS_SUPPORTS_250HZ || SYS_SUPPORTS_ARBIT_HZ
1982 2751
1983 config CC_HAS_BRANCH_PROT_PAC_RET !! 2752 config HZ_256
1984 # GCC 9 or later, clang 8 or later !! 2753 bool "256 HZ" if SYS_SUPPORTS_256HZ || SYS_SUPPORTS_ARBIT_HZ
1985 def_bool $(cc-option,-mbranch-protect <<
1986 2754
1987 config CC_HAS_SIGN_RETURN_ADDRESS !! 2755 config HZ_1000
1988 # GCC 7, 8 !! 2756 bool "1000 HZ" if SYS_SUPPORTS_1000HZ || SYS_SUPPORTS_ARBIT_HZ
1989 def_bool $(cc-option,-msign-return-ad <<
1990 2757
1991 config AS_HAS_ARMV8_3 !! 2758 config HZ_1024
1992 def_bool $(cc-option,-Wa$(comma)-marc !! 2759 bool "1024 HZ" if SYS_SUPPORTS_1024HZ || SYS_SUPPORTS_ARBIT_HZ
1993 2760
1994 config AS_HAS_CFI_NEGATE_RA_STATE !! 2761 endchoice
1995 def_bool $(as-instr,.cfi_startproc\n. <<
1996 2762
1997 config AS_HAS_LDAPR !! 2763 config SYS_SUPPORTS_24HZ
1998 def_bool $(as-instr,.arch_extension r !! 2764 bool
1999 2765
2000 endmenu # "ARMv8.3 architectural features" !! 2766 config SYS_SUPPORTS_48HZ
>> 2767 bool
2001 2768
2002 menu "ARMv8.4 architectural features" !! 2769 config SYS_SUPPORTS_100HZ
>> 2770 bool
2003 2771
2004 config ARM64_AMU_EXTN !! 2772 config SYS_SUPPORTS_128HZ
2005 bool "Enable support for the Activity !! 2773 bool
2006 default y <<
2007 help <<
2008 The activity monitors extension is <<
2009 by the ARMv8.4 CPU architecture. Th <<
2010 of the activity monitors architectu <<
2011 2774
2012 To enable the use of this extension !! 2775 config SYS_SUPPORTS_250HZ
>> 2776 bool
2013 2777
2014 Note that for architectural reasons !! 2778 config SYS_SUPPORTS_256HZ
2015 support when running on CPUs that p !! 2779 bool
2016 extension. The required support is <<
2017 * Version 1.5 and later of the AR <<
2018 2780
2019 For kernels that have this configur !! 2781 config SYS_SUPPORTS_1000HZ
2020 firmware, you may need to say N her !! 2782 bool
2021 Otherwise you may experience firmwa <<
2022 accessing the counter registers. Ev <<
2023 symptoms, the values returned by th <<
2024 correctly reflect reality. Most com <<
2025 indicating that the counter is not <<
2026 2783
2027 config AS_HAS_ARMV8_4 !! 2784 config SYS_SUPPORTS_1024HZ
2028 def_bool $(cc-option,-Wa$(comma)-marc !! 2785 bool
2029 2786
2030 config ARM64_TLB_RANGE !! 2787 config SYS_SUPPORTS_ARBIT_HZ
2031 bool "Enable support for tlbi range f !! 2788 bool
2032 default y !! 2789 default y if !SYS_SUPPORTS_24HZ && \
2033 depends on AS_HAS_ARMV8_4 !! 2790 !SYS_SUPPORTS_48HZ && \
2034 help !! 2791 !SYS_SUPPORTS_100HZ && \
2035 ARMv8.4-TLBI provides TLBI invalida !! 2792 !SYS_SUPPORTS_128HZ && \
2036 range of input addresses. !! 2793 !SYS_SUPPORTS_250HZ && \
>> 2794 !SYS_SUPPORTS_256HZ && \
>> 2795 !SYS_SUPPORTS_1000HZ && \
>> 2796 !SYS_SUPPORTS_1024HZ
2037 2797
2038 The feature introduces new assembly !! 2798 config HZ
2039 support when binutils >= 2.30. !! 2799 int
>> 2800 default 24 if HZ_24
>> 2801 default 48 if HZ_48
>> 2802 default 100 if HZ_100
>> 2803 default 128 if HZ_128
>> 2804 default 250 if HZ_250
>> 2805 default 256 if HZ_256
>> 2806 default 1000 if HZ_1000
>> 2807 default 1024 if HZ_1024
>> 2808
>> 2809 config SCHED_HRTICK
>> 2810 def_bool HIGH_RES_TIMERS
>> 2811
>> 2812 source "kernel/Kconfig.preempt"
>> 2813
>> 2814 config KEXEC
>> 2815 bool "Kexec system call"
>> 2816 select KEXEC_CORE
>> 2817 help
>> 2818 kexec is a system call that implements the ability to shutdown your
>> 2819 current kernel, and to start another kernel. It is like a reboot
>> 2820 but it is independent of the system firmware. And like a reboot
>> 2821 you can start any kernel with it, not just Linux.
>> 2822
>> 2823 The name comes from the similarity to the exec system call.
>> 2824
>> 2825 It is an ongoing process to be certain the hardware in a machine
>> 2826 is properly shutdown, so do not be surprised if this code does not
>> 2827 initially work for you. As of this writing the exact hardware
>> 2828 interface is strongly in flux, so no good recommendation can be
>> 2829 made.
>> 2830
>> 2831 config CRASH_DUMP
>> 2832 bool "Kernel crash dumps"
>> 2833 help
>> 2834 Generate crash dump after being started by kexec.
>> 2835 This should be normally only set in special crash dump kernels
>> 2836 which are loaded in the main kernel with kexec-tools into
>> 2837 a specially reserved region and then later executed after
>> 2838 a crash by kdump/kexec. The crash dump kernel must be compiled
>> 2839 to a memory address not used by the main kernel or firmware using
>> 2840 PHYSICAL_START.
>> 2841
>> 2842 config PHYSICAL_START
>> 2843 hex "Physical address where the kernel is loaded"
>> 2844 default "0xffffffff84000000" if 64BIT
>> 2845 default "0x84000000" if 32BIT
>> 2846 depends on CRASH_DUMP
>> 2847 help
>> 2848 This gives the CKSEG0 or KSEG0 address where the kernel is loaded.
>> 2849 If you plan to use kernel for capturing the crash dump change
>> 2850 this value to start of the reserved region (the "X" value as
>> 2851 specified in the "crashkernel=YM@XM" command line boot parameter
>> 2852 passed to the panic-ed kernel).
>> 2853
>> 2854 config SECCOMP
>> 2855 bool "Enable seccomp to safely compute untrusted bytecode"
>> 2856 depends on PROC_FS
>> 2857 default y
>> 2858 help
>> 2859 This kernel feature is useful for number crunching applications
>> 2860 that may need to compute untrusted bytecode during their
>> 2861 execution. By using pipes or other transports made available to
>> 2862 the process as file descriptors supporting the read/write
>> 2863 syscalls, it's possible to isolate those applications in
>> 2864 their own address space using seccomp. Once seccomp is
>> 2865 enabled via /proc/<pid>/seccomp, it cannot be disabled
>> 2866 and the task is only allowed to execute a few safe syscalls
>> 2867 defined by each seccomp mode.
>> 2868
>> 2869 If unsure, say Y. Only embedded should say N here.
>> 2870
>> 2871 config MIPS_O32_FP64_SUPPORT
>> 2872 bool "Support for O32 binaries using 64-bit FP"
>> 2873 depends on 32BIT || MIPS32_O32
>> 2874 help
>> 2875 When this is enabled, the kernel will support use of 64-bit floating
>> 2876 point registers with binaries using the O32 ABI along with the
>> 2877 EF_MIPS_FP64 ELF header flag (typically built with -mfp64). On
>> 2878 32-bit MIPS systems this support is at the cost of increasing the
>> 2879 size and complexity of the compiled FPU emulator. Thus if you are
>> 2880 running a MIPS32 system and know that none of your userland binaries
>> 2881 will require 64-bit floating point, you may wish to reduce the size
>> 2882 of your kernel & potentially improve FP emulation performance by
>> 2883 saying N here.
>> 2884
>> 2885 Although binutils currently supports use of this flag the details
>> 2886 concerning its effect upon the O32 ABI in userland are still being
>> 2887 worked on. In order to avoid userland becoming dependant upon current
>> 2888 behaviour before the details have been finalised, this option should
>> 2889 be considered experimental and only enabled by those working upon
>> 2890 said details.
2040 2891
2041 endmenu # "ARMv8.4 architectural features" !! 2892 If unsure, say N.
2042 2893
2043 menu "ARMv8.5 architectural features" !! 2894 config USE_OF
>> 2895 bool
>> 2896 select OF
>> 2897 select OF_EARLY_FLATTREE
>> 2898 select IRQ_DOMAIN
2044 2899
2045 config AS_HAS_ARMV8_5 !! 2900 config BUILTIN_DTB
2046 def_bool $(cc-option,-Wa$(comma)-marc !! 2901 bool
2047 2902
2048 config ARM64_BTI !! 2903 choice
2049 bool "Branch Target Identification su !! 2904 prompt "Kernel appended dtb support" if USE_OF
2050 default y !! 2905 default MIPS_NO_APPENDED_DTB
2051 help <<
2052 Branch Target Identification (part <<
2053 provides a mechanism to limit the s <<
2054 branch instructions such as BR or B <<
2055 2906
2056 To make use of BTI on CPUs that sup !! 2907 config MIPS_NO_APPENDED_DTB
>> 2908 bool "None"
>> 2909 help
>> 2910 Do not enable appended dtb support.
>> 2911
>> 2912 config MIPS_ELF_APPENDED_DTB
>> 2913 bool "vmlinux"
>> 2914 help
>> 2915 With this option, the boot code will look for a device tree binary
>> 2916 DTB) included in the vmlinux ELF section .appended_dtb. By default
>> 2917 it is empty and the DTB can be appended using binutils command
>> 2918 objcopy:
>> 2919
>> 2920 objcopy --update-section .appended_dtb=<filename>.dtb vmlinux
>> 2921
>> 2922 This is meant as a backward compatiblity convenience for those
>> 2923 systems with a bootloader that can't be upgraded to accommodate
>> 2924 the documented boot protocol using a device tree.
>> 2925
>> 2926 config MIPS_RAW_APPENDED_DTB
>> 2927 bool "vmlinux.bin or vmlinuz.bin"
>> 2928 help
>> 2929 With this option, the boot code will look for a device tree binary
>> 2930 DTB) appended to raw vmlinux.bin or vmlinuz.bin.
>> 2931 (e.g. cat vmlinux.bin <filename>.dtb > vmlinux_w_dtb).
>> 2932
>> 2933 This is meant as a backward compatibility convenience for those
>> 2934 systems with a bootloader that can't be upgraded to accommodate
>> 2935 the documented boot protocol using a device tree.
>> 2936
>> 2937 Beware that there is very little in terms of protection against
>> 2938 this option being confused by leftover garbage in memory that might
>> 2939 look like a DTB header after a reboot if no actual DTB is appended
>> 2940 to vmlinux.bin. Do not leave this option active in a production kernel
>> 2941 if you don't intend to always append a DTB.
>> 2942 endchoice
2057 2943
2058 BTI is intended to provide compleme !! 2944 choice
2059 flow integrity protection mechanism !! 2945 prompt "Kernel command line type" if !CMDLINE_OVERRIDE
2060 authentication mechanism provided a !! 2946 default MIPS_CMDLINE_FROM_DTB if USE_OF && !ATH79 && !MACH_INGENIC && \
2061 For this reason, it does not make s !! 2947 !MIPS_MALTA && \
2062 also enabling support for pointer a !! 2948 !CAVIUM_OCTEON_SOC
2063 enabling this option you should als !! 2949 default MIPS_CMDLINE_FROM_BOOTLOADER
>> 2950
>> 2951 config MIPS_CMDLINE_FROM_DTB
>> 2952 depends on USE_OF
>> 2953 bool "Dtb kernel arguments if available"
>> 2954
>> 2955 config MIPS_CMDLINE_DTB_EXTEND
>> 2956 depends on USE_OF
>> 2957 bool "Extend dtb kernel arguments with bootloader arguments"
>> 2958
>> 2959 config MIPS_CMDLINE_FROM_BOOTLOADER
>> 2960 bool "Bootloader kernel arguments if available"
>> 2961
>> 2962 config MIPS_CMDLINE_BUILTIN_EXTEND
>> 2963 depends on CMDLINE_BOOL
>> 2964 bool "Extend builtin kernel arguments with bootloader arguments"
>> 2965 endchoice
2064 2966
2065 Userspace binaries must also be spe !! 2967 endmenu
2066 this mechanism. If you say N here <<
2067 BTI, such binaries can still run, b <<
2068 enforcement of branch destinations. <<
2069 2968
2070 config ARM64_BTI_KERNEL !! 2969 config LOCKDEP_SUPPORT
2071 bool "Use Branch Target Identificatio !! 2970 bool
2072 default y 2971 default y
2073 depends on ARM64_BTI <<
2074 depends on ARM64_PTR_AUTH_KERNEL <<
2075 depends on CC_HAS_BRANCH_PROT_PAC_RET <<
2076 # https://gcc.gnu.org/bugzilla/show_b <<
2077 depends on !CC_IS_GCC || GCC_VERSION <<
2078 # https://gcc.gnu.org/bugzilla/show_b <<
2079 depends on !CC_IS_GCC <<
2080 depends on (!FUNCTION_GRAPH_TRACER || <<
2081 help <<
2082 Build the kernel with Branch Target <<
2083 and enable enforcement of this for <<
2084 is enabled and the system supports <<
2085 modular code must have BTI enabled. <<
2086 2972
2087 config CC_HAS_BRANCH_PROT_PAC_RET_BTI !! 2973 config STACKTRACE_SUPPORT
2088 # GCC 9 or later, clang 8 or later !! 2974 bool
2089 def_bool $(cc-option,-mbranch-protect <<
2090 <<
2091 config ARM64_E0PD <<
2092 bool "Enable support for E0PD" <<
2093 default y 2975 default y
2094 help <<
2095 E0PD (part of the ARMv8.5 extension <<
2096 that EL0 accesses made via TTBR1 al <<
2097 providing similar benefits to KASLR <<
2098 with lower overhead and without dis <<
2099 kernel memory such as SPE. <<
2100 <<
2101 This option enables E0PD for TTBR1 <<
2102 <<
2103 config ARM64_AS_HAS_MTE <<
2104 # Initial support for MTE went in bin <<
2105 # ".arch armv8.5-a+memtag" below. How <<
2106 # as a late addition to the final arc <<
2107 # is only supported in the newer 2.32 <<
2108 # versions, hence the extra "stgm" in <<
2109 def_bool $(as-instr,.arch armv8.5-a+m <<
2110 2976
2111 config ARM64_MTE !! 2977 config HAVE_LATENCYTOP_SUPPORT
2112 bool "Memory Tagging Extension suppor !! 2978 bool
2113 default y 2979 default y
2114 depends on ARM64_AS_HAS_MTE && ARM64_ <<
2115 depends on AS_HAS_ARMV8_5 <<
2116 depends on AS_HAS_LSE_ATOMICS <<
2117 # Required for tag checking in the ua <<
2118 depends on ARM64_PAN <<
2119 select ARCH_HAS_SUBPAGE_FAULTS <<
2120 select ARCH_USES_HIGH_VMA_FLAGS <<
2121 select ARCH_USES_PG_ARCH_2 <<
2122 select ARCH_USES_PG_ARCH_3 <<
2123 help <<
2124 Memory Tagging (part of the ARMv8.5 <<
2125 architectural support for run-time, <<
2126 various classes of memory error to <<
2127 to eliminate vulnerabilities arisin <<
2128 languages. <<
2129 2980
2130 This option enables the support for !! 2981 config PGTABLE_LEVELS
2131 Extension at EL0 (i.e. for userspac !! 2982 int
>> 2983 default 4 if PAGE_SIZE_4KB && MIPS_VA_BITS_48
>> 2984 default 3 if 64BIT && !PAGE_SIZE_64KB
>> 2985 default 2
2132 2986
2133 Selecting this option allows the fe !! 2987 source "init/Kconfig"
2134 runtime. Any secondary CPU not impl <<
2135 not be allowed a late bring-up. <<
2136 2988
2137 Userspace binaries that want to use !! 2989 source "kernel/Kconfig.freezer"
2138 explicitly opt in. The mechanism fo <<
2139 described in: <<
2140 2990
2141 Documentation/arch/arm64/memory-tag !! 2991 menu "Bus options (PCI, PCMCIA, EISA, ISA, TC)"
2142 2992
2143 endmenu # "ARMv8.5 architectural features" !! 2993 config HW_HAS_EISA
>> 2994 bool
>> 2995 config HW_HAS_PCI
>> 2996 bool
2144 2997
2145 menu "ARMv8.7 architectural features" !! 2998 config PCI
>> 2999 bool "Support for PCI controller"
>> 3000 depends on HW_HAS_PCI
>> 3001 select PCI_DOMAINS
>> 3002 help
>> 3003 Find out whether you have a PCI motherboard. PCI is the name of a
>> 3004 bus system, i.e. the way the CPU talks to the other stuff inside
>> 3005 your box. Other bus systems are ISA, EISA, or VESA. If you have PCI,
>> 3006 say Y, otherwise N.
>> 3007
>> 3008 config HT_PCI
>> 3009 bool "Support for HT-linked PCI"
>> 3010 default y
>> 3011 depends on CPU_LOONGSON3
>> 3012 select PCI
>> 3013 select PCI_DOMAINS
>> 3014 help
>> 3015 Loongson family machines use Hyper-Transport bus for inter-core
>> 3016 connection and device connection. The PCI bus is a subordinate
>> 3017 linked at HT. Choose Y for Loongson-3 based machines.
2146 3018
2147 config ARM64_EPAN !! 3019 config PCI_DOMAINS
2148 bool "Enable support for Enhanced Pri !! 3020 bool
2149 default y <<
2150 depends on ARM64_PAN <<
2151 help <<
2152 Enhanced Privileged Access Never (E <<
2153 Access Never to be used with Execut <<
2154 <<
2155 The feature is detected at runtime, <<
2156 if the cpu does not implement the f <<
2157 endmenu # "ARMv8.7 architectural features" <<
2158 3021
2159 menu "ARMv8.9 architectural features" !! 3022 config PCI_DOMAINS_GENERIC
>> 3023 bool
2160 3024
2161 config ARM64_POE !! 3025 config PCI_DRIVERS_GENERIC
2162 prompt "Permission Overlay Extension" !! 3026 select PCI_DOMAINS_GENERIC if PCI_DOMAINS
2163 def_bool y !! 3027 bool
2164 select ARCH_USES_HIGH_VMA_FLAGS <<
2165 select ARCH_HAS_PKEYS <<
2166 help <<
2167 The Permission Overlay Extension is <<
2168 Protection Keys. Memory Protection <<
2169 enforcing page-based protections, b <<
2170 of the page tables when an applicat <<
2171 3028
2172 For details, see Documentation/core !! 3029 config PCI_DRIVERS_LEGACY
>> 3030 def_bool !PCI_DRIVERS_GENERIC
>> 3031 select NO_GENERIC_PCI_IOPORT_MAP
2173 3032
2174 If unsure, say y. !! 3033 source "drivers/pci/Kconfig"
2175 3034
2176 config ARCH_PKEY_BITS !! 3035 #
2177 int !! 3036 # ISA support is now enabled via select. Too many systems still have the one
2178 default 3 !! 3037 # or other ISA chip on the board that users don't know about so don't expect
>> 3038 # users to choose the right thing ...
>> 3039 #
>> 3040 config ISA
>> 3041 bool
2179 3042
2180 endmenu # "ARMv8.9 architectural features" !! 3043 config EISA
>> 3044 bool "EISA support"
>> 3045 depends on HW_HAS_EISA
>> 3046 select ISA
>> 3047 select GENERIC_ISA_DMA
>> 3048 ---help---
>> 3049 The Extended Industry Standard Architecture (EISA) bus was
>> 3050 developed as an open alternative to the IBM MicroChannel bus.
>> 3051
>> 3052 The EISA bus provided some of the features of the IBM MicroChannel
>> 3053 bus while maintaining backward compatibility with cards made for
>> 3054 the older ISA bus. The EISA bus saw limited use between 1988 and
>> 3055 1995 when it was made obsolete by the PCI bus.
>> 3056
>> 3057 Say Y here if you are building a kernel for an EISA-based machine.
>> 3058
>> 3059 Otherwise, say N.
>> 3060
>> 3061 source "drivers/eisa/Kconfig"
>> 3062
>> 3063 config TC
>> 3064 bool "TURBOchannel support"
>> 3065 depends on MACH_DECSTATION
>> 3066 help
>> 3067 TURBOchannel is a DEC (now Compaq (now HP)) bus for Alpha and MIPS
>> 3068 processors. TURBOchannel programming specifications are available
>> 3069 at:
>> 3070 <ftp://ftp.hp.com/pub/alphaserver/archive/triadd/>
>> 3071 and:
>> 3072 <http://www.computer-refuge.org/classiccmp/ftp.digital.com/pub/DEC/TriAdd/>
>> 3073 Linux driver support status is documented at:
>> 3074 <http://www.linux-mips.org/wiki/DECstation>
2181 3075
2182 config ARM64_SVE !! 3076 config MMU
2183 bool "ARM Scalable Vector Extension s !! 3077 bool
2184 default y 3078 default y
2185 help <<
2186 The Scalable Vector Extension (SVE) <<
2187 execution state which complements a <<
2188 of the base architecture to support <<
2189 additional vectorisation opportunit <<
2190 <<
2191 To enable use of this extension on <<
2192 <<
2193 On CPUs that support the SVE2 exten <<
2194 those too. <<
2195 <<
2196 Note that for architectural reasons <<
2197 support when running on SVE capable <<
2198 is present in: <<
2199 3079
2200 * version 1.5 and later of the AR !! 3080 config ARCH_MMAP_RND_BITS_MIN
2201 * the AArch64 boot wrapper since !! 3081 default 12 if 64BIT
2202 ("bootwrapper: SVE: Enable SVE !! 3082 default 8
2203 <<
2204 For other firmware implementations, <<
2205 or vendor. <<
2206 <<
2207 If you need the kernel to boot on S <<
2208 firmware, you may need to say N her <<
2209 fixed. Otherwise, you may experien <<
2210 booting the kernel. If unsure and <<
2211 symptoms, you should assume that it <<
2212 3083
2213 config ARM64_SME !! 3084 config ARCH_MMAP_RND_BITS_MAX
2214 bool "ARM Scalable Matrix Extension s !! 3085 default 18 if 64BIT
2215 default y !! 3086 default 15
2216 depends on ARM64_SVE <<
2217 depends on BROKEN <<
2218 help <<
2219 The Scalable Matrix Extension (SME) <<
2220 execution state which utilises a su <<
2221 instruction set, together with the <<
2222 register state capable of holding t <<
2223 enable various matrix operations. <<
2224 3087
2225 config ARM64_PSEUDO_NMI !! 3088 config ARCH_MMAP_RND_COMPAT_BITS_MIN
2226 bool "Support for NMI-like interrupts !! 3089 default 8
2227 select ARM_GIC_V3 <<
2228 help <<
2229 Adds support for mimicking Non-Mask <<
2230 GIC interrupt priority. This suppor <<
2231 ARM GIC. <<
2232 3090
2233 This high priority configuration fo !! 3091 config ARCH_MMAP_RND_COMPAT_BITS_MAX
2234 explicitly enabled by setting the k !! 3092 default 15
2235 "irqchip.gicv3_pseudo_nmi" to 1. <<
2236 3093
2237 If unsure, say N !! 3094 config I8253
>> 3095 bool
>> 3096 select CLKSRC_I8253
>> 3097 select CLKEVT_I8253
>> 3098 select MIPS_EXTERNAL_TIMER
2238 3099
2239 if ARM64_PSEUDO_NMI !! 3100 config ZONE_DMA
2240 config ARM64_DEBUG_PRIORITY_MASKING !! 3101 bool
2241 bool "Debug interrupt priority maskin <<
2242 help <<
2243 This adds runtime checks to functio <<
2244 interrupts when using priority mask <<
2245 the validity of ICC_PMR_EL1 when ca <<
2246 3102
2247 If unsure, say N !! 3103 config ZONE_DMA32
2248 endif # ARM64_PSEUDO_NMI !! 3104 bool
2249 3105
2250 config RELOCATABLE !! 3106 source "drivers/pcmcia/Kconfig"
2251 bool "Build a relocatable kernel imag <<
2252 select ARCH_HAS_RELR <<
2253 default y <<
2254 help <<
2255 This builds the kernel as a Positio <<
2256 which retains all relocation metada <<
2257 kernel binary at runtime to a diffe <<
2258 address it was linked at. <<
2259 Since AArch64 uses the RELA relocat <<
2260 relocation pass at runtime even if <<
2261 same address it was linked at. <<
2262 3107
2263 config RANDOMIZE_BASE !! 3108 config RAPIDIO
2264 bool "Randomize the address of the ke !! 3109 tristate "RapidIO support"
2265 select RELOCATABLE !! 3110 depends on PCI
>> 3111 default n
2266 help 3112 help
2267 Randomizes the virtual address at w !! 3113 If you say Y here, the kernel will include drivers and
2268 loaded, as a security feature that !! 3114 infrastructure code to support RapidIO interconnect devices.
2269 relying on knowledge of the locatio <<
2270 <<
2271 It is the bootloader's job to provi <<
2272 random u64 value in /chosen/kaslr-s <<
2273 <<
2274 When booting via the UEFI stub, it <<
2275 EFI_RNG_PROTOCOL implementation (if <<
2276 to the kernel proper. In addition, <<
2277 location of the kernel Image as wel <<
2278 3115
2279 If unsure, say N. !! 3116 source "drivers/rapidio/Kconfig"
2280 3117
2281 config RANDOMIZE_MODULE_REGION_FULL !! 3118 endmenu
2282 bool "Randomize the module region ove <<
2283 depends on RANDOMIZE_BASE <<
2284 default y <<
2285 help <<
2286 Randomizes the location of the modu <<
2287 covering the core kernel. This way, <<
2288 to leak information about the locat <<
2289 but it does imply that function cal <<
2290 kernel will need to be resolved via <<
2291 <<
2292 When this option is not set, the mo <<
2293 a limited range that contains the [ <<
2294 core kernel, so branch relocations <<
2295 the region is exhausted. In this pa <<
2296 exhaustion, modules might be able t <<
2297 3119
2298 config CC_HAVE_STACKPROTECTOR_SYSREG !! 3120 menu "Executable file formats"
2299 def_bool $(cc-option,-mstack-protecto <<
2300 3121
2301 config STACKPROTECTOR_PER_TASK !! 3122 source "fs/Kconfig.binfmt"
2302 def_bool y <<
2303 depends on STACKPROTECTOR && CC_HAVE_ <<
2304 3123
2305 config UNWIND_PATCH_PAC_INTO_SCS !! 3124 config TRAD_SIGNALS
2306 bool "Enable shadow call stack dynami !! 3125 bool
2307 # needs Clang with https://github.com <<
2308 depends on CC_IS_CLANG && CLANG_VERSI <<
2309 depends on ARM64_PTR_AUTH_KERNEL && C <<
2310 depends on SHADOW_CALL_STACK <<
2311 select UNWIND_TABLES <<
2312 select DYNAMIC_SCS <<
2313 <<
2314 config ARM64_CONTPTE <<
2315 bool "Contiguous PTE mappings for use <<
2316 depends on TRANSPARENT_HUGEPAGE <<
2317 default y <<
2318 help <<
2319 When enabled, user mappings are con <<
2320 bit, for any mappings that meet the <<
2321 This reduces TLB pressure and impro <<
2322 <<
2323 endmenu # "Kernel Features" <<
2324 <<
2325 menu "Boot options" <<
2326 <<
2327 config ARM64_ACPI_PARKING_PROTOCOL <<
2328 bool "Enable support for the ARM64 AC <<
2329 depends on ACPI <<
2330 help <<
2331 Enable support for the ARM64 ACPI p <<
2332 the kernel will not allow booting t <<
2333 protocol even if the corresponding <<
2334 MADT table. <<
2335 <<
2336 config CMDLINE <<
2337 string "Default kernel command string <<
2338 default "" <<
2339 help <<
2340 Provide a set of default command-li <<
2341 entering them here. As a minimum, y <<
2342 root device (e.g. root=/dev/nfs). <<
2343 3126
2344 choice !! 3127 config MIPS32_COMPAT
2345 prompt "Kernel command line type" !! 3128 bool
2346 depends on CMDLINE != "" <<
2347 default CMDLINE_FROM_BOOTLOADER <<
2348 help <<
2349 Choose how the kernel will handle t <<
2350 command line string. <<
2351 <<
2352 config CMDLINE_FROM_BOOTLOADER <<
2353 bool "Use bootloader kernel arguments <<
2354 help <<
2355 Uses the command-line options passe <<
2356 the boot loader doesn't provide any <<
2357 string provided in CMDLINE will be <<
2358 <<
2359 config CMDLINE_FORCE <<
2360 bool "Always use the default kernel c <<
2361 help <<
2362 Always use the default kernel comma <<
2363 loader passes other arguments to th <<
2364 This is useful if you cannot or don <<
2365 command-line options your boot load <<
2366 3129
2367 endchoice !! 3130 config COMPAT
>> 3131 bool
2368 3132
2369 config EFI_STUB !! 3133 config SYSVIPC_COMPAT
2370 bool 3134 bool
2371 3135
2372 config EFI !! 3136 config MIPS32_O32
2373 bool "UEFI runtime support" !! 3137 bool "Kernel support for o32 binaries"
2374 depends on OF && !CPU_BIG_ENDIAN !! 3138 depends on 64BIT
2375 depends on KERNEL_MODE_NEON !! 3139 select ARCH_WANT_OLD_COMPAT_IPC
2376 select ARCH_SUPPORTS_ACPI !! 3140 select COMPAT
2377 select LIBFDT !! 3141 select MIPS32_COMPAT
2378 select UCS2_STRING !! 3142 select SYSVIPC_COMPAT if SYSVIPC
2379 select EFI_PARAMS_FROM_FDT !! 3143 help
2380 select EFI_RUNTIME_WRAPPERS !! 3144 Select this option if you want to run o32 binaries. These are pure
2381 select EFI_STUB !! 3145 32-bit binaries as used by the 32-bit Linux/MIPS port. Most of
2382 select EFI_GENERIC_STUB !! 3146 existing binaries are in this format.
2383 imply IMA_SECURE_AND_OR_TRUSTED_BOOT <<
2384 default y <<
2385 help <<
2386 This option provides support for ru <<
2387 by UEFI firmware (such as non-volat <<
2388 clock, and platform reset). A UEFI <<
2389 allow the kernel to be booted as an <<
2390 is only useful on systems that have <<
2391 3147
2392 config COMPRESSED_INSTALL !! 3148 If unsure, say Y.
2393 bool "Install compressed image by def <<
2394 help <<
2395 This makes the regular "make instal <<
2396 image we built, not the legacy unco <<
2397 3149
2398 You can check that a compressed ima !! 3150 config MIPS32_N32
2399 "make zinstall" first, and verifyin !! 3151 bool "Kernel support for n32 binaries"
2400 in your environment before making " !! 3152 depends on 64BIT
2401 you. !! 3153 select COMPAT
>> 3154 select MIPS32_COMPAT
>> 3155 select SYSVIPC_COMPAT if SYSVIPC
>> 3156 help
>> 3157 Select this option if you want to run n32 binaries. These are
>> 3158 64-bit binaries using 32-bit quantities for addressing and certain
>> 3159 data that would normally be 64-bit. They are used in special
>> 3160 cases.
2402 3161
2403 config DMI !! 3162 If unsure, say N.
2404 bool "Enable support for SMBIOS (DMI) <<
2405 depends on EFI <<
2406 default y <<
2407 help <<
2408 This enables SMBIOS/DMI feature for <<
2409 3163
2410 This option is only useful on syste !! 3164 config BINFMT_ELF32
2411 However, even with this option, the !! 3165 bool
2412 continue to boot on existing non-UE !! 3166 default y if MIPS32_O32 || MIPS32_N32
>> 3167 select ELFCORE
2413 3168
2414 endmenu # "Boot options" !! 3169 endmenu
2415 3170
2416 menu "Power management options" 3171 menu "Power management options"
2417 3172
2418 source "kernel/power/Kconfig" <<
2419 <<
2420 config ARCH_HIBERNATION_POSSIBLE 3173 config ARCH_HIBERNATION_POSSIBLE
2421 def_bool y 3174 def_bool y
2422 depends on CPU_PM !! 3175 depends on SYS_SUPPORTS_HOTPLUG_CPU || !SMP
2423 <<
2424 config ARCH_HIBERNATION_HEADER <<
2425 def_bool y <<
2426 depends on HIBERNATION <<
2427 3176
2428 config ARCH_SUSPEND_POSSIBLE 3177 config ARCH_SUSPEND_POSSIBLE
2429 def_bool y 3178 def_bool y
>> 3179 depends on SYS_SUPPORTS_HOTPLUG_CPU || !SMP
>> 3180
>> 3181 source "kernel/power/Kconfig"
2430 3182
2431 endmenu # "Power management options" !! 3183 endmenu
>> 3184
>> 3185 config MIPS_EXTERNAL_TIMER
>> 3186 bool
2432 3187
2433 menu "CPU Power Management" 3188 menu "CPU Power Management"
2434 3189
>> 3190 if CPU_SUPPORTS_CPUFREQ && MIPS_EXTERNAL_TIMER
>> 3191 source "drivers/cpufreq/Kconfig"
>> 3192 endif
>> 3193
2435 source "drivers/cpuidle/Kconfig" 3194 source "drivers/cpuidle/Kconfig"
2436 3195
2437 source "drivers/cpufreq/Kconfig" !! 3196 endmenu
>> 3197
>> 3198 source "net/Kconfig"
>> 3199
>> 3200 source "drivers/Kconfig"
>> 3201
>> 3202 source "drivers/firmware/Kconfig"
>> 3203
>> 3204 source "fs/Kconfig"
>> 3205
>> 3206 source "arch/mips/Kconfig.debug"
2438 3207
2439 endmenu # "CPU Power Management" !! 3208 source "security/Kconfig"
2440 3209
2441 source "drivers/acpi/Kconfig" !! 3210 source "crypto/Kconfig"
2442 3211
2443 source "arch/arm64/kvm/Kconfig" !! 3212 source "lib/Kconfig"
2444 3213
>> 3214 source "arch/mips/kvm/Kconfig"
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