1 # SPDX-License-Identifier: GPL-2.0-only !! 1 # SPDX-License-Identifier: GPL-2.0
2 config ARM64 !! 2 config MIPS
3 def_bool y !! 3 bool
4 select ACPI_APMT if ACPI !! 4 default y
5 select ACPI_CCA_REQUIRED if ACPI <<
6 select ACPI_GENERIC_GSI if ACPI <<
7 select ACPI_GTDT if ACPI <<
8 select ACPI_HOTPLUG_CPU if ACPI_PROCES <<
9 select ACPI_IORT if ACPI <<
10 select ACPI_REDUCED_HARDWARE_ONLY if A <<
11 select ACPI_MCFG if (ACPI && PCI) <<
12 select ACPI_SPCR_TABLE if ACPI <<
13 select ACPI_PPTT if ACPI <<
14 select ARCH_HAS_DEBUG_WX <<
15 select ARCH_BINFMT_ELF_EXTRA_PHDRS <<
16 select ARCH_BINFMT_ELF_STATE 5 select ARCH_BINFMT_ELF_STATE
17 select ARCH_CORRECT_STACKTRACE_ON_KRET !! 6 select ARCH_CLOCKSOURCE_DATA
18 select ARCH_ENABLE_HUGEPAGE_MIGRATION !! 7 select ARCH_DISCARD_MEMBLOCK
19 select ARCH_ENABLE_MEMORY_HOTPLUG !! 8 select ARCH_HAS_ELF_RANDOMIZE
20 select ARCH_ENABLE_MEMORY_HOTREMOVE <<
21 select ARCH_ENABLE_SPLIT_PMD_PTLOCK if <<
22 select ARCH_ENABLE_THP_MIGRATION if TR <<
23 select ARCH_HAS_CACHE_LINE_SIZE <<
24 select ARCH_HAS_CURRENT_STACK_POINTER <<
25 select ARCH_HAS_DEBUG_VIRTUAL <<
26 select ARCH_HAS_DEBUG_VM_PGTABLE <<
27 select ARCH_HAS_DMA_OPS if XEN <<
28 select ARCH_HAS_DMA_PREP_COHERENT <<
29 select ARCH_HAS_ACPI_TABLE_UPGRADE if <<
30 select ARCH_HAS_FAST_MULTIPLIER <<
31 select ARCH_HAS_FORTIFY_SOURCE <<
32 select ARCH_HAS_GCOV_PROFILE_ALL <<
33 select ARCH_HAS_GIGANTIC_PAGE <<
34 select ARCH_HAS_KCOV <<
35 select ARCH_HAS_KERNEL_FPU_SUPPORT if <<
36 select ARCH_HAS_KEEPINITRD <<
37 select ARCH_HAS_MEMBARRIER_SYNC_CORE <<
38 select ARCH_HAS_MEM_ENCRYPT <<
39 select ARCH_HAS_NMI_SAFE_THIS_CPU_OPS <<
40 select ARCH_HAS_NON_OVERLAPPING_ADDRES <<
41 select ARCH_HAS_PTE_DEVMAP <<
42 select ARCH_HAS_PTE_SPECIAL <<
43 select ARCH_HAS_HW_PTE_YOUNG <<
44 select ARCH_HAS_SETUP_DMA_OPS <<
45 select ARCH_HAS_SET_DIRECT_MAP <<
46 select ARCH_HAS_SET_MEMORY <<
47 select ARCH_STACKWALK <<
48 select ARCH_HAS_STRICT_KERNEL_RWX <<
49 select ARCH_HAS_STRICT_MODULE_RWX <<
50 select ARCH_HAS_SYNC_DMA_FOR_DEVICE <<
51 select ARCH_HAS_SYNC_DMA_FOR_CPU <<
52 select ARCH_HAS_SYSCALL_WRAPPER <<
53 select ARCH_HAS_TICK_BROADCAST if GENE 9 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
54 select ARCH_HAS_ZONE_DMA_SET if EXPERT !! 10 select ARCH_SUPPORTS_UPROBES
55 select ARCH_HAVE_ELF_PROT !! 11 select ARCH_USE_BUILTIN_BSWAP
56 select ARCH_HAVE_NMI_SAFE_CMPXCHG !! 12 select ARCH_USE_CMPXCHG_LOCKREF if 64BIT
57 select ARCH_HAVE_TRACE_MMIO_ACCESS <<
58 select ARCH_INLINE_READ_LOCK if !PREEM <<
59 select ARCH_INLINE_READ_LOCK_BH if !PR <<
60 select ARCH_INLINE_READ_LOCK_IRQ if !P <<
61 select ARCH_INLINE_READ_LOCK_IRQSAVE i <<
62 select ARCH_INLINE_READ_UNLOCK if !PRE <<
63 select ARCH_INLINE_READ_UNLOCK_BH if ! <<
64 select ARCH_INLINE_READ_UNLOCK_IRQ if <<
65 select ARCH_INLINE_READ_UNLOCK_IRQREST <<
66 select ARCH_INLINE_WRITE_LOCK if !PREE <<
67 select ARCH_INLINE_WRITE_LOCK_BH if !P <<
68 select ARCH_INLINE_WRITE_LOCK_IRQ if ! <<
69 select ARCH_INLINE_WRITE_LOCK_IRQSAVE <<
70 select ARCH_INLINE_WRITE_UNLOCK if !PR <<
71 select ARCH_INLINE_WRITE_UNLOCK_BH if <<
72 select ARCH_INLINE_WRITE_UNLOCK_IRQ if <<
73 select ARCH_INLINE_WRITE_UNLOCK_IRQRES <<
74 select ARCH_INLINE_SPIN_TRYLOCK if !PR <<
75 select ARCH_INLINE_SPIN_TRYLOCK_BH if <<
76 select ARCH_INLINE_SPIN_LOCK if !PREEM <<
77 select ARCH_INLINE_SPIN_LOCK_BH if !PR <<
78 select ARCH_INLINE_SPIN_LOCK_IRQ if !P <<
79 select ARCH_INLINE_SPIN_LOCK_IRQSAVE i <<
80 select ARCH_INLINE_SPIN_UNLOCK if !PRE <<
81 select ARCH_INLINE_SPIN_UNLOCK_BH if ! <<
82 select ARCH_INLINE_SPIN_UNLOCK_IRQ if <<
83 select ARCH_INLINE_SPIN_UNLOCK_IRQREST <<
84 select ARCH_KEEP_MEMBLOCK <<
85 select ARCH_MHP_MEMMAP_ON_MEMORY_ENABL <<
86 select ARCH_USE_CMPXCHG_LOCKREF <<
87 select ARCH_USE_GNU_PROPERTY <<
88 select ARCH_USE_MEMTEST <<
89 select ARCH_USE_QUEUED_RWLOCKS 13 select ARCH_USE_QUEUED_RWLOCKS
90 select ARCH_USE_QUEUED_SPINLOCKS 14 select ARCH_USE_QUEUED_SPINLOCKS
91 select ARCH_USE_SYM_ANNOTATIONS !! 15 select ARCH_WANT_IPC_PARSE_VERSION
92 select ARCH_SUPPORTS_DEBUG_PAGEALLOC !! 16 select BUILDTIME_EXTABLE_SORT
93 select ARCH_SUPPORTS_HUGETLBFS <<
94 select ARCH_SUPPORTS_MEMORY_FAILURE <<
95 select ARCH_SUPPORTS_SHADOW_CALL_STACK <<
96 select ARCH_SUPPORTS_LTO_CLANG if CPU_ <<
97 select ARCH_SUPPORTS_LTO_CLANG_THIN <<
98 select ARCH_SUPPORTS_CFI_CLANG <<
99 select ARCH_SUPPORTS_ATOMIC_RMW <<
100 select ARCH_SUPPORTS_INT128 if CC_HAS_ <<
101 select ARCH_SUPPORTS_NUMA_BALANCING <<
102 select ARCH_SUPPORTS_PAGE_TABLE_CHECK <<
103 select ARCH_SUPPORTS_PER_VMA_LOCK <<
104 select ARCH_SUPPORTS_HUGE_PFNMAP if TR <<
105 select ARCH_SUPPORTS_RT <<
106 select ARCH_WANT_BATCHED_UNMAP_TLB_FLU <<
107 select ARCH_WANT_COMPAT_IPC_PARSE_VERS <<
108 select ARCH_WANT_DEFAULT_BPF_JIT <<
109 select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_ <<
110 select ARCH_WANT_FRAME_POINTERS <<
111 select ARCH_WANT_HUGE_PMD_SHARE if ARM <<
112 select ARCH_WANT_LD_ORPHAN_WARN <<
113 select ARCH_WANTS_EXECMEM_LATE if EXEC <<
114 select ARCH_WANTS_NO_INSTR <<
115 select ARCH_WANTS_THP_SWAP if ARM64_4K <<
116 select ARCH_HAS_UBSAN <<
117 select ARM_AMBA <<
118 select ARM_ARCH_TIMER <<
119 select ARM_GIC <<
120 select AUDIT_ARCH_COMPAT_GENERIC <<
121 select ARM_GIC_V2M if PCI <<
122 select ARM_GIC_V3 <<
123 select ARM_GIC_V3_ITS if PCI <<
124 select ARM_PSCI_FW <<
125 select BUILDTIME_TABLE_SORT <<
126 select CLONE_BACKWARDS 17 select CLONE_BACKWARDS
127 select COMMON_CLK !! 18 select CPU_PM if CPU_IDLE
128 select CPU_PM if (SUSPEND || CPU_IDLE) !! 19 select GENERIC_ATOMIC64 if !64BIT
129 select CPUMASK_OFFSTACK if NR_CPUS > 2 !! 20 select GENERIC_CLOCKEVENTS
130 select CRC32 !! 21 select GENERIC_CMOS_UPDATE
131 select DCACHE_WORD_ACCESS <<
132 select DYNAMIC_FTRACE if FUNCTION_TRAC <<
133 select DMA_BOUNCE_UNALIGNED_KMALLOC <<
134 select DMA_DIRECT_REMAP <<
135 select EDAC_SUPPORT <<
136 select FRAME_POINTER <<
137 select FUNCTION_ALIGNMENT_4B <<
138 select FUNCTION_ALIGNMENT_8B if DYNAMI <<
139 select GENERIC_ALLOCATOR <<
140 select GENERIC_ARCH_TOPOLOGY <<
141 select GENERIC_CLOCKEVENTS_BROADCAST <<
142 select GENERIC_CPU_AUTOPROBE 22 select GENERIC_CPU_AUTOPROBE
143 select GENERIC_CPU_DEVICES <<
144 select GENERIC_CPU_VULNERABILITIES <<
145 select GENERIC_EARLY_IOREMAP <<
146 select GENERIC_IDLE_POLL_SETUP <<
147 select GENERIC_IOREMAP <<
148 select GENERIC_IRQ_IPI <<
149 select GENERIC_IRQ_PROBE 23 select GENERIC_IRQ_PROBE
150 select GENERIC_IRQ_SHOW 24 select GENERIC_IRQ_SHOW
151 select GENERIC_IRQ_SHOW_LEVEL <<
152 select GENERIC_LIB_DEVMEM_IS_ALLOWED <<
153 select GENERIC_PCI_IOMAP 25 select GENERIC_PCI_IOMAP
154 select GENERIC_PTDUMP !! 26 select GENERIC_SCHED_CLOCK if !CAVIUM_OCTEON_SOC
155 select GENERIC_SCHED_CLOCK <<
156 select GENERIC_SMP_IDLE_THREAD 27 select GENERIC_SMP_IDLE_THREAD
157 select GENERIC_TIME_VSYSCALL 28 select GENERIC_TIME_VSYSCALL
158 select GENERIC_GETTIMEOFDAY !! 29 select HANDLE_DOMAIN_IRQ
159 select GENERIC_VDSO_TIME_NS <<
160 select HARDIRQS_SW_RESEND <<
161 select HAS_IOPORT <<
162 select HAVE_MOVE_PMD <<
163 select HAVE_MOVE_PUD <<
164 select HAVE_PCI <<
165 select HAVE_ACPI_APEI if (ACPI && EFI) <<
166 select HAVE_ALIGNED_STRUCT_PAGE <<
167 select HAVE_ARCH_AUDITSYSCALL <<
168 select HAVE_ARCH_BITREVERSE <<
169 select HAVE_ARCH_COMPILER_H <<
170 select HAVE_ARCH_HUGE_VMALLOC <<
171 select HAVE_ARCH_HUGE_VMAP <<
172 select HAVE_ARCH_JUMP_LABEL 30 select HAVE_ARCH_JUMP_LABEL
173 select HAVE_ARCH_JUMP_LABEL_RELATIVE <<
174 select HAVE_ARCH_KASAN <<
175 select HAVE_ARCH_KASAN_VMALLOC <<
176 select HAVE_ARCH_KASAN_SW_TAGS <<
177 select HAVE_ARCH_KASAN_HW_TAGS if ARM6 <<
178 # Some instrumentation may be unsound, <<
179 select HAVE_ARCH_KCSAN if EXPERT <<
180 select HAVE_ARCH_KFENCE <<
181 select HAVE_ARCH_KGDB 31 select HAVE_ARCH_KGDB
182 select HAVE_ARCH_MMAP_RND_BITS !! 32 select HAVE_ARCH_MMAP_RND_BITS if MMU
183 select HAVE_ARCH_MMAP_RND_COMPAT_BITS !! 33 select HAVE_ARCH_MMAP_RND_COMPAT_BITS if MMU && COMPAT
184 select HAVE_ARCH_PREL32_RELOCATIONS <<
185 select HAVE_ARCH_RANDOMIZE_KSTACK_OFFS <<
186 select HAVE_ARCH_SECCOMP_FILTER 34 select HAVE_ARCH_SECCOMP_FILTER
187 select HAVE_ARCH_STACKLEAK <<
188 select HAVE_ARCH_THREAD_STRUCT_WHITELI <<
189 select HAVE_ARCH_TRACEHOOK 35 select HAVE_ARCH_TRACEHOOK
190 select HAVE_ARCH_TRANSPARENT_HUGEPAGE !! 36 select HAVE_ARCH_TRANSPARENT_HUGEPAGE if CPU_SUPPORTS_HUGEPAGES && 64BIT
191 select HAVE_ARCH_VMAP_STACK !! 37 select HAVE_CBPF_JIT if (!64BIT && !CPU_MICROMIPS)
192 select HAVE_ARM_SMCCC !! 38 select HAVE_EBPF_JIT if (64BIT && !CPU_MICROMIPS)
193 select HAVE_ASM_MODVERSIONS !! 39 select HAVE_CC_STACKPROTECTOR
194 select HAVE_EBPF_JIT !! 40 select HAVE_CONTEXT_TRACKING
>> 41 select HAVE_COPY_THREAD_TLS
195 select HAVE_C_RECORDMCOUNT 42 select HAVE_C_RECORDMCOUNT
196 select HAVE_CMPXCHG_DOUBLE <<
197 select HAVE_CMPXCHG_LOCAL <<
198 select HAVE_CONTEXT_TRACKING_USER <<
199 select HAVE_DEBUG_KMEMLEAK 43 select HAVE_DEBUG_KMEMLEAK
>> 44 select HAVE_DEBUG_STACKOVERFLOW
>> 45 select HAVE_DMA_API_DEBUG
200 select HAVE_DMA_CONTIGUOUS 46 select HAVE_DMA_CONTIGUOUS
201 select HAVE_DYNAMIC_FTRACE 47 select HAVE_DYNAMIC_FTRACE
202 select HAVE_DYNAMIC_FTRACE_WITH_ARGS \ !! 48 select HAVE_EXIT_THREAD
203 if (GCC_SUPPORTS_DYNAMIC_FTRAC <<
204 CLANG_SUPPORTS_DYNAMIC_FTR <<
205 select HAVE_DYNAMIC_FTRACE_WITH_DIRECT <<
206 if DYNAMIC_FTRACE_WITH_ARGS && <<
207 select HAVE_DYNAMIC_FTRACE_WITH_CALL_O <<
208 if (DYNAMIC_FTRACE_WITH_ARGS & <<
209 (CC_IS_CLANG || !CC_OPTIMI <<
210 select FTRACE_MCOUNT_USE_PATCHABLE_FUN <<
211 if DYNAMIC_FTRACE_WITH_ARGS <<
212 select HAVE_SAMPLE_FTRACE_DIRECT <<
213 select HAVE_SAMPLE_FTRACE_DIRECT_MULTI <<
214 select HAVE_EFFICIENT_UNALIGNED_ACCESS <<
215 select HAVE_GUP_FAST <<
216 select HAVE_FTRACE_MCOUNT_RECORD 49 select HAVE_FTRACE_MCOUNT_RECORD
217 select HAVE_FUNCTION_TRACER <<
218 select HAVE_FUNCTION_ERROR_INJECTION <<
219 select HAVE_FUNCTION_GRAPH_TRACER 50 select HAVE_FUNCTION_GRAPH_TRACER
220 select HAVE_FUNCTION_GRAPH_RETVAL !! 51 select HAVE_FUNCTION_TRACER
221 select HAVE_GCC_PLUGINS !! 52 select HAVE_GENERIC_DMA_COHERENT
222 select HAVE_HARDLOCKUP_DETECTOR_PERF i !! 53 select HAVE_IDE
223 HW_PERF_EVENTS && HAVE_PERF_EV !! 54 select HAVE_IRQ_EXIT_ON_IRQ_STACK
224 select HAVE_HW_BREAKPOINT if PERF_EVEN <<
225 select HAVE_IOREMAP_PROT <<
226 select HAVE_IRQ_TIME_ACCOUNTING 55 select HAVE_IRQ_TIME_ACCOUNTING
>> 56 select HAVE_KPROBES
>> 57 select HAVE_KRETPROBES
>> 58 select HAVE_MEMBLOCK
>> 59 select HAVE_MEMBLOCK_NODE_MAP
227 select HAVE_MOD_ARCH_SPECIFIC 60 select HAVE_MOD_ARCH_SPECIFIC
228 select HAVE_NMI 61 select HAVE_NMI
>> 62 select HAVE_OPROFILE
229 select HAVE_PERF_EVENTS 63 select HAVE_PERF_EVENTS
230 select HAVE_PERF_EVENTS_NMI if ARM64_P <<
231 select HAVE_PERF_REGS <<
232 select HAVE_PERF_USER_STACK_DUMP <<
233 select HAVE_PREEMPT_DYNAMIC_KEY <<
234 select HAVE_REGS_AND_STACK_ACCESS_API 64 select HAVE_REGS_AND_STACK_ACCESS_API
235 select HAVE_POSIX_CPU_TIMERS_TASK_WORK <<
236 select HAVE_FUNCTION_ARG_ACCESS_API <<
237 select MMU_GATHER_RCU_TABLE_FREE <<
238 select HAVE_RSEQ <<
239 select HAVE_RUST if RUSTC_SUPPORTS_ARM <<
240 select HAVE_STACKPROTECTOR <<
241 select HAVE_SYSCALL_TRACEPOINTS 65 select HAVE_SYSCALL_TRACEPOINTS
242 select HAVE_KPROBES !! 66 select HAVE_VIRT_CPU_ACCOUNTING_GEN if 64BIT || !SMP
243 select HAVE_KRETPROBES <<
244 select HAVE_GENERIC_VDSO <<
245 select HOTPLUG_CORE_SYNC_DEAD if HOTPL <<
246 select IRQ_DOMAIN <<
247 select IRQ_FORCED_THREADING 67 select IRQ_FORCED_THREADING
248 select KASAN_VMALLOC if KASAN !! 68 select MODULES_USE_ELF_RELA if MODULES && 64BIT
249 select LOCK_MM_AND_FIND_VMA !! 69 select MODULES_USE_ELF_REL if MODULES
250 select MODULES_USE_ELF_RELA !! 70 select PERF_USE_VMALLOC
251 select NEED_DMA_MAP_STATE !! 71 select RTC_LIB if !MACH_LOONGSON64
252 select NEED_SG_DMA_LENGTH <<
253 select OF <<
254 select OF_EARLY_FLATTREE <<
255 select PCI_DOMAINS_GENERIC if PCI <<
256 select PCI_ECAM if (ACPI && PCI) <<
257 select PCI_SYSCALL if PCI <<
258 select POWER_RESET <<
259 select POWER_SUPPLY <<
260 select SPARSE_IRQ <<
261 select SWIOTLB <<
262 select SYSCTL_EXCEPTION_TRACE 72 select SYSCTL_EXCEPTION_TRACE
263 select THREAD_INFO_IN_TASK !! 73 select VIRT_TO_BUS
264 select HAVE_ARCH_USERFAULTFD_MINOR if <<
265 select HAVE_ARCH_USERFAULTFD_WP if USE <<
266 select TRACE_IRQFLAGS_SUPPORT <<
267 select TRACE_IRQFLAGS_NMI_SUPPORT <<
268 select HAVE_SOFTIRQ_ON_OWN_STACK <<
269 select USER_STACKTRACE_SUPPORT <<
270 select VDSO_GETRANDOM <<
271 help <<
272 ARM 64-bit (AArch64) Linux support. <<
273 <<
274 config RUSTC_SUPPORTS_ARM64 <<
275 def_bool y <<
276 depends on CPU_LITTLE_ENDIAN <<
277 # Shadow call stack is only supported <<
278 # <<
279 # When using the UNWIND_PATCH_PAC_INTO <<
280 # required due to use of the -Zfixed-x <<
281 # <<
282 # Otherwise, rustc version 1.82+ is re <<
283 # -Zsanitizer=shadow-call-stack flag. <<
284 depends on !SHADOW_CALL_STACK || RUSTC <<
285 <<
286 config CLANG_SUPPORTS_DYNAMIC_FTRACE_WITH_ARGS <<
287 def_bool CC_IS_CLANG <<
288 # https://github.com/ClangBuiltLinux/l <<
289 depends on AS_IS_GNU || (AS_IS_LLVM && <<
290 <<
291 config GCC_SUPPORTS_DYNAMIC_FTRACE_WITH_ARGS <<
292 def_bool CC_IS_GCC <<
293 depends on $(cc-option,-fpatchable-fun <<
294 <<
295 config 64BIT <<
296 def_bool y <<
297 74
298 config MMU !! 75 menu "Machine selection"
299 def_bool y <<
300 76
301 config ARM64_CONT_PTE_SHIFT !! 77 choice
302 int !! 78 prompt "System type"
303 default 5 if PAGE_SIZE_64KB !! 79 default MIPS_GENERIC
304 default 7 if PAGE_SIZE_16KB <<
305 default 4 <<
306 <<
307 config ARM64_CONT_PMD_SHIFT <<
308 int <<
309 default 5 if PAGE_SIZE_64KB <<
310 default 5 if PAGE_SIZE_16KB <<
311 default 4 <<
312 80
313 config ARCH_MMAP_RND_BITS_MIN !! 81 config MIPS_GENERIC
314 default 14 if PAGE_SIZE_64KB !! 82 bool "Generic board-agnostic MIPS kernel"
315 default 16 if PAGE_SIZE_16KB !! 83 select BOOT_RAW
316 default 18 !! 84 select BUILTIN_DTB
>> 85 select CEVT_R4K
>> 86 select CLKSRC_MIPS_GIC
>> 87 select COMMON_CLK
>> 88 select CPU_MIPSR2_IRQ_VI
>> 89 select CPU_MIPSR2_IRQ_EI
>> 90 select CSRC_R4K
>> 91 select DMA_PERDEV_COHERENT
>> 92 select HW_HAS_PCI
>> 93 select IRQ_MIPS_CPU
>> 94 select LIBFDT
>> 95 select MIPS_CPU_SCACHE
>> 96 select MIPS_GIC
>> 97 select MIPS_L1_CACHE_SHIFT_7
>> 98 select NO_EXCEPT_FILL
>> 99 select PCI_DRIVERS_GENERIC
>> 100 select PINCTRL
>> 101 select SMP_UP if SMP
>> 102 select SWAP_IO_SPACE
>> 103 select SYS_HAS_CPU_MIPS32_R1
>> 104 select SYS_HAS_CPU_MIPS32_R2
>> 105 select SYS_HAS_CPU_MIPS32_R6
>> 106 select SYS_HAS_CPU_MIPS64_R1
>> 107 select SYS_HAS_CPU_MIPS64_R2
>> 108 select SYS_HAS_CPU_MIPS64_R6
>> 109 select SYS_SUPPORTS_32BIT_KERNEL
>> 110 select SYS_SUPPORTS_64BIT_KERNEL
>> 111 select SYS_SUPPORTS_BIG_ENDIAN
>> 112 select SYS_SUPPORTS_HIGHMEM
>> 113 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 114 select SYS_SUPPORTS_MICROMIPS
>> 115 select SYS_SUPPORTS_MIPS_CPS
>> 116 select SYS_SUPPORTS_MIPS16
>> 117 select SYS_SUPPORTS_MULTITHREADING
>> 118 select SYS_SUPPORTS_RELOCATABLE
>> 119 select SYS_SUPPORTS_SMARTMIPS
>> 120 select USB_EHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
>> 121 select USB_EHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 122 select USB_OHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
>> 123 select USB_OHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 124 select USB_UHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
>> 125 select USB_UHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 126 select USE_OF
>> 127 help
>> 128 Select this to build a kernel which aims to support multiple boards,
>> 129 generally using a flattened device tree passed from the bootloader
>> 130 using the boot protocol defined in the UHI (Unified Hosting
>> 131 Interface) specification.
>> 132
>> 133 config MIPS_ALCHEMY
>> 134 bool "Alchemy processor based machines"
>> 135 select ARCH_PHYS_ADDR_T_64BIT
>> 136 select CEVT_R4K
>> 137 select CSRC_R4K
>> 138 select IRQ_MIPS_CPU
>> 139 select DMA_MAYBE_COHERENT # Au1000,1500,1100 aren't, rest is
>> 140 select SYS_HAS_CPU_MIPS32_R1
>> 141 select SYS_SUPPORTS_32BIT_KERNEL
>> 142 select SYS_SUPPORTS_APM_EMULATION
>> 143 select GPIOLIB
>> 144 select SYS_SUPPORTS_ZBOOT
>> 145 select COMMON_CLK
317 146
318 # max bits determined by the following formula !! 147 config AR7
319 # VA_BITS - PAGE_SHIFT - 3 !! 148 bool "Texas Instruments AR7"
320 config ARCH_MMAP_RND_BITS_MAX !! 149 select BOOT_ELF32
321 default 19 if ARM64_VA_BITS=36 !! 150 select DMA_NONCOHERENT
322 default 24 if ARM64_VA_BITS=39 !! 151 select CEVT_R4K
323 default 27 if ARM64_VA_BITS=42 !! 152 select CSRC_R4K
324 default 30 if ARM64_VA_BITS=47 !! 153 select IRQ_MIPS_CPU
325 default 29 if ARM64_VA_BITS=48 && ARM6 !! 154 select NO_EXCEPT_FILL
326 default 31 if ARM64_VA_BITS=48 && ARM6 !! 155 select SWAP_IO_SPACE
327 default 33 if ARM64_VA_BITS=48 !! 156 select SYS_HAS_CPU_MIPS32_R1
328 default 14 if ARM64_64K_PAGES !! 157 select SYS_HAS_EARLY_PRINTK
329 default 16 if ARM64_16K_PAGES !! 158 select SYS_SUPPORTS_32BIT_KERNEL
330 default 18 !! 159 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 160 select SYS_SUPPORTS_MIPS16
>> 161 select SYS_SUPPORTS_ZBOOT_UART16550
>> 162 select GPIOLIB
>> 163 select VLYNQ
>> 164 select HAVE_CLK
>> 165 help
>> 166 Support for the Texas Instruments AR7 System-on-a-Chip
>> 167 family: TNETD7100, 7200 and 7300.
>> 168
>> 169 config ATH25
>> 170 bool "Atheros AR231x/AR531x SoC support"
>> 171 select CEVT_R4K
>> 172 select CSRC_R4K
>> 173 select DMA_NONCOHERENT
>> 174 select IRQ_MIPS_CPU
>> 175 select IRQ_DOMAIN
>> 176 select SYS_HAS_CPU_MIPS32_R1
>> 177 select SYS_SUPPORTS_BIG_ENDIAN
>> 178 select SYS_SUPPORTS_32BIT_KERNEL
>> 179 select SYS_HAS_EARLY_PRINTK
>> 180 help
>> 181 Support for Atheros AR231x and Atheros AR531x based boards
>> 182
>> 183 config ATH79
>> 184 bool "Atheros AR71XX/AR724X/AR913X based boards"
>> 185 select ARCH_HAS_RESET_CONTROLLER
>> 186 select BOOT_RAW
>> 187 select CEVT_R4K
>> 188 select CSRC_R4K
>> 189 select DMA_NONCOHERENT
>> 190 select GPIOLIB
>> 191 select HAVE_CLK
>> 192 select COMMON_CLK
>> 193 select CLKDEV_LOOKUP
>> 194 select IRQ_MIPS_CPU
>> 195 select MIPS_MACHINE
>> 196 select SYS_HAS_CPU_MIPS32_R2
>> 197 select SYS_HAS_EARLY_PRINTK
>> 198 select SYS_SUPPORTS_32BIT_KERNEL
>> 199 select SYS_SUPPORTS_BIG_ENDIAN
>> 200 select SYS_SUPPORTS_MIPS16
>> 201 select SYS_SUPPORTS_ZBOOT_UART_PROM
>> 202 select USE_OF
>> 203 help
>> 204 Support for the Atheros AR71XX/AR724X/AR913X SoCs.
>> 205
>> 206 config BMIPS_GENERIC
>> 207 bool "Broadcom Generic BMIPS kernel"
>> 208 select BOOT_RAW
>> 209 select NO_EXCEPT_FILL
>> 210 select USE_OF
>> 211 select CEVT_R4K
>> 212 select CSRC_R4K
>> 213 select SYNC_R4K
>> 214 select COMMON_CLK
>> 215 select BCM6345_L1_IRQ
>> 216 select BCM7038_L1_IRQ
>> 217 select BCM7120_L2_IRQ
>> 218 select BRCMSTB_L2_IRQ
>> 219 select IRQ_MIPS_CPU
>> 220 select DMA_NONCOHERENT
>> 221 select SYS_SUPPORTS_32BIT_KERNEL
>> 222 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 223 select SYS_SUPPORTS_BIG_ENDIAN
>> 224 select SYS_SUPPORTS_HIGHMEM
>> 225 select SYS_HAS_CPU_BMIPS32_3300
>> 226 select SYS_HAS_CPU_BMIPS4350
>> 227 select SYS_HAS_CPU_BMIPS4380
>> 228 select SYS_HAS_CPU_BMIPS5000
>> 229 select SWAP_IO_SPACE
>> 230 select USB_EHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
>> 231 select USB_EHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 232 select USB_OHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
>> 233 select USB_OHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 234 select HARDIRQS_SW_RESEND
>> 235 help
>> 236 Build a generic DT-based kernel image that boots on select
>> 237 BCM33xx cable modem chips, BCM63xx DSL chips, and BCM7xxx set-top
>> 238 box chips. Note that CONFIG_CPU_BIG_ENDIAN/CONFIG_CPU_LITTLE_ENDIAN
>> 239 must be set appropriately for your board.
>> 240
>> 241 config BCM47XX
>> 242 bool "Broadcom BCM47XX based boards"
>> 243 select BOOT_RAW
>> 244 select CEVT_R4K
>> 245 select CSRC_R4K
>> 246 select DMA_NONCOHERENT
>> 247 select HW_HAS_PCI
>> 248 select IRQ_MIPS_CPU
>> 249 select SYS_HAS_CPU_MIPS32_R1
>> 250 select NO_EXCEPT_FILL
>> 251 select SYS_SUPPORTS_32BIT_KERNEL
>> 252 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 253 select SYS_SUPPORTS_MIPS16
>> 254 select SYS_SUPPORTS_ZBOOT
>> 255 select SYS_HAS_EARLY_PRINTK
>> 256 select USE_GENERIC_EARLY_PRINTK_8250
>> 257 select GPIOLIB
>> 258 select LEDS_GPIO_REGISTER
>> 259 select BCM47XX_NVRAM
>> 260 select BCM47XX_SPROM
>> 261 select BCM47XX_SSB if !BCM47XX_BCMA
>> 262 help
>> 263 Support for BCM47XX based boards
>> 264
>> 265 config BCM63XX
>> 266 bool "Broadcom BCM63XX based boards"
>> 267 select BOOT_RAW
>> 268 select CEVT_R4K
>> 269 select CSRC_R4K
>> 270 select SYNC_R4K
>> 271 select DMA_NONCOHERENT
>> 272 select IRQ_MIPS_CPU
>> 273 select SYS_SUPPORTS_32BIT_KERNEL
>> 274 select SYS_SUPPORTS_BIG_ENDIAN
>> 275 select SYS_HAS_EARLY_PRINTK
>> 276 select SWAP_IO_SPACE
>> 277 select GPIOLIB
>> 278 select HAVE_CLK
>> 279 select MIPS_L1_CACHE_SHIFT_4
>> 280 select CLKDEV_LOOKUP
>> 281 help
>> 282 Support for BCM63XX based boards
>> 283
>> 284 config MIPS_COBALT
>> 285 bool "Cobalt Server"
>> 286 select CEVT_R4K
>> 287 select CSRC_R4K
>> 288 select CEVT_GT641XX
>> 289 select DMA_NONCOHERENT
>> 290 select HW_HAS_PCI
>> 291 select I8253
>> 292 select I8259
>> 293 select IRQ_MIPS_CPU
>> 294 select IRQ_GT641XX
>> 295 select PCI_GT64XXX_PCI0
>> 296 select PCI
>> 297 select SYS_HAS_CPU_NEVADA
>> 298 select SYS_HAS_EARLY_PRINTK
>> 299 select SYS_SUPPORTS_32BIT_KERNEL
>> 300 select SYS_SUPPORTS_64BIT_KERNEL
>> 301 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 302 select USE_GENERIC_EARLY_PRINTK_8250
>> 303
>> 304 config MACH_DECSTATION
>> 305 bool "DECstations"
>> 306 select BOOT_ELF32
>> 307 select CEVT_DS1287
>> 308 select CEVT_R4K if CPU_R4X00
>> 309 select CSRC_IOASIC
>> 310 select CSRC_R4K if CPU_R4X00
>> 311 select CPU_DADDI_WORKAROUNDS if 64BIT
>> 312 select CPU_R4000_WORKAROUNDS if 64BIT
>> 313 select CPU_R4400_WORKAROUNDS if 64BIT
>> 314 select DMA_NONCOHERENT
>> 315 select NO_IOPORT_MAP
>> 316 select IRQ_MIPS_CPU
>> 317 select SYS_HAS_CPU_R3000
>> 318 select SYS_HAS_CPU_R4X00
>> 319 select SYS_SUPPORTS_32BIT_KERNEL
>> 320 select SYS_SUPPORTS_64BIT_KERNEL
>> 321 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 322 select SYS_SUPPORTS_128HZ
>> 323 select SYS_SUPPORTS_256HZ
>> 324 select SYS_SUPPORTS_1024HZ
>> 325 select MIPS_L1_CACHE_SHIFT_4
>> 326 help
>> 327 This enables support for DEC's MIPS based workstations. For details
>> 328 see the Linux/MIPS FAQ on <http://www.linux-mips.org/> and the
>> 329 DECstation porting pages on <http://decstation.unix-ag.org/>.
>> 330
>> 331 If you have one of the following DECstation Models you definitely
>> 332 want to choose R4xx0 for the CPU Type:
>> 333
>> 334 DECstation 5000/50
>> 335 DECstation 5000/150
>> 336 DECstation 5000/260
>> 337 DECsystem 5900/260
>> 338
>> 339 otherwise choose R3000.
>> 340
>> 341 config MACH_JAZZ
>> 342 bool "Jazz family of machines"
>> 343 select ARCH_MIGHT_HAVE_PC_PARPORT
>> 344 select ARCH_MIGHT_HAVE_PC_SERIO
>> 345 select FW_ARC
>> 346 select FW_ARC32
>> 347 select ARCH_MAY_HAVE_PC_FDC
>> 348 select CEVT_R4K
>> 349 select CSRC_R4K
>> 350 select DEFAULT_SGI_PARTITION if CPU_BIG_ENDIAN
>> 351 select GENERIC_ISA_DMA
>> 352 select HAVE_PCSPKR_PLATFORM
>> 353 select IRQ_MIPS_CPU
>> 354 select I8253
>> 355 select I8259
>> 356 select ISA
>> 357 select SYS_HAS_CPU_R4X00
>> 358 select SYS_SUPPORTS_32BIT_KERNEL
>> 359 select SYS_SUPPORTS_64BIT_KERNEL
>> 360 select SYS_SUPPORTS_100HZ
>> 361 help
>> 362 This a family of machines based on the MIPS R4030 chipset which was
>> 363 used by several vendors to build RISC/os and Windows NT workstations.
>> 364 Members include the Acer PICA, MIPS Magnum 4000, MIPS Millennium and
>> 365 Olivetti M700-10 workstations.
>> 366
>> 367 config MACH_INGENIC
>> 368 bool "Ingenic SoC based machines"
>> 369 select SYS_SUPPORTS_32BIT_KERNEL
>> 370 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 371 select SYS_SUPPORTS_ZBOOT_UART16550
>> 372 select DMA_NONCOHERENT
>> 373 select IRQ_MIPS_CPU
>> 374 select PINCTRL
>> 375 select GPIOLIB
>> 376 select COMMON_CLK
>> 377 select GENERIC_IRQ_CHIP
>> 378 select BUILTIN_DTB
>> 379 select USE_OF
>> 380 select LIBFDT
331 381
332 config ARCH_MMAP_RND_COMPAT_BITS_MIN !! 382 config LANTIQ
333 default 7 if ARM64_64K_PAGES !! 383 bool "Lantiq based platforms"
334 default 9 if ARM64_16K_PAGES !! 384 select DMA_NONCOHERENT
335 default 11 !! 385 select IRQ_MIPS_CPU
>> 386 select CEVT_R4K
>> 387 select CSRC_R4K
>> 388 select SYS_HAS_CPU_MIPS32_R1
>> 389 select SYS_HAS_CPU_MIPS32_R2
>> 390 select SYS_SUPPORTS_BIG_ENDIAN
>> 391 select SYS_SUPPORTS_32BIT_KERNEL
>> 392 select SYS_SUPPORTS_MIPS16
>> 393 select SYS_SUPPORTS_MULTITHREADING
>> 394 select SYS_SUPPORTS_VPE_LOADER
>> 395 select SYS_HAS_EARLY_PRINTK
>> 396 select GPIOLIB
>> 397 select SWAP_IO_SPACE
>> 398 select BOOT_RAW
>> 399 select CLKDEV_LOOKUP
>> 400 select USE_OF
>> 401 select PINCTRL
>> 402 select PINCTRL_LANTIQ
>> 403 select ARCH_HAS_RESET_CONTROLLER
>> 404 select RESET_CONTROLLER
>> 405
>> 406 config LASAT
>> 407 bool "LASAT Networks platforms"
>> 408 select CEVT_R4K
>> 409 select CRC32
>> 410 select CSRC_R4K
>> 411 select DMA_NONCOHERENT
>> 412 select SYS_HAS_EARLY_PRINTK
>> 413 select HW_HAS_PCI
>> 414 select IRQ_MIPS_CPU
>> 415 select PCI_GT64XXX_PCI0
>> 416 select MIPS_NILE4
>> 417 select R5000_CPU_SCACHE
>> 418 select SYS_HAS_CPU_R5000
>> 419 select SYS_SUPPORTS_32BIT_KERNEL
>> 420 select SYS_SUPPORTS_64BIT_KERNEL if BROKEN
>> 421 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 422
>> 423 config MACH_LOONGSON32
>> 424 bool "Loongson-1 family of machines"
>> 425 select SYS_SUPPORTS_ZBOOT
>> 426 help
>> 427 This enables support for the Loongson-1 family of machines.
>> 428
>> 429 Loongson-1 is a family of 32-bit MIPS-compatible SoCs developed by
>> 430 the Institute of Computing Technology (ICT), Chinese Academy of
>> 431 Sciences (CAS).
>> 432
>> 433 config MACH_LOONGSON64
>> 434 bool "Loongson-2/3 family of machines"
>> 435 select ARCH_HAS_PHYS_TO_DMA
>> 436 select SYS_SUPPORTS_ZBOOT
>> 437 help
>> 438 This enables the support of Loongson-2/3 family of machines.
>> 439
>> 440 Loongson-2 is a family of single-core CPUs and Loongson-3 is a
>> 441 family of multi-core CPUs. They are both 64-bit general-purpose
>> 442 MIPS-compatible CPUs. Loongson-2/3 are developed by the Institute
>> 443 of Computing Technology (ICT), Chinese Academy of Sciences (CAS)
>> 444 in the People's Republic of China. The chief architect is Professor
>> 445 Weiwu Hu.
>> 446
>> 447 config MACH_PISTACHIO
>> 448 bool "IMG Pistachio SoC based boards"
>> 449 select BOOT_ELF32
>> 450 select BOOT_RAW
>> 451 select CEVT_R4K
>> 452 select CLKSRC_MIPS_GIC
>> 453 select COMMON_CLK
>> 454 select CSRC_R4K
>> 455 select DMA_NONCOHERENT
>> 456 select GPIOLIB
>> 457 select IRQ_MIPS_CPU
>> 458 select LIBFDT
>> 459 select MFD_SYSCON
>> 460 select MIPS_CPU_SCACHE
>> 461 select MIPS_GIC
>> 462 select PINCTRL
>> 463 select REGULATOR
>> 464 select SYS_HAS_CPU_MIPS32_R2
>> 465 select SYS_SUPPORTS_32BIT_KERNEL
>> 466 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 467 select SYS_SUPPORTS_MIPS_CPS
>> 468 select SYS_SUPPORTS_MULTITHREADING
>> 469 select SYS_SUPPORTS_RELOCATABLE
>> 470 select SYS_SUPPORTS_ZBOOT
>> 471 select SYS_HAS_EARLY_PRINTK
>> 472 select USE_GENERIC_EARLY_PRINTK_8250
>> 473 select USE_OF
>> 474 help
>> 475 This enables support for the IMG Pistachio SoC platform.
>> 476
>> 477 config MIPS_MALTA
>> 478 bool "MIPS Malta board"
>> 479 select ARCH_MAY_HAVE_PC_FDC
>> 480 select ARCH_MIGHT_HAVE_PC_PARPORT
>> 481 select ARCH_MIGHT_HAVE_PC_SERIO
>> 482 select BOOT_ELF32
>> 483 select BOOT_RAW
>> 484 select BUILTIN_DTB
>> 485 select CEVT_R4K
>> 486 select CSRC_R4K
>> 487 select CLKSRC_MIPS_GIC
>> 488 select COMMON_CLK
>> 489 select DMA_MAYBE_COHERENT
>> 490 select GENERIC_ISA_DMA
>> 491 select HAVE_PCSPKR_PLATFORM
>> 492 select IRQ_MIPS_CPU
>> 493 select MIPS_GIC
>> 494 select HW_HAS_PCI
>> 495 select I8253
>> 496 select I8259
>> 497 select MIPS_BONITO64
>> 498 select MIPS_CPU_SCACHE
>> 499 select MIPS_L1_CACHE_SHIFT_6
>> 500 select PCI_GT64XXX_PCI0
>> 501 select MIPS_MSC
>> 502 select SMP_UP if SMP
>> 503 select SWAP_IO_SPACE
>> 504 select SYS_HAS_CPU_MIPS32_R1
>> 505 select SYS_HAS_CPU_MIPS32_R2
>> 506 select SYS_HAS_CPU_MIPS32_R3_5
>> 507 select SYS_HAS_CPU_MIPS32_R5
>> 508 select SYS_HAS_CPU_MIPS32_R6
>> 509 select SYS_HAS_CPU_MIPS64_R1
>> 510 select SYS_HAS_CPU_MIPS64_R2
>> 511 select SYS_HAS_CPU_MIPS64_R6
>> 512 select SYS_HAS_CPU_NEVADA
>> 513 select SYS_HAS_CPU_RM7000
>> 514 select SYS_SUPPORTS_32BIT_KERNEL
>> 515 select SYS_SUPPORTS_64BIT_KERNEL
>> 516 select SYS_SUPPORTS_BIG_ENDIAN
>> 517 select SYS_SUPPORTS_HIGHMEM
>> 518 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 519 select SYS_SUPPORTS_MICROMIPS
>> 520 select SYS_SUPPORTS_MIPS_CMP
>> 521 select SYS_SUPPORTS_MIPS_CPS
>> 522 select SYS_SUPPORTS_MIPS16
>> 523 select SYS_SUPPORTS_MULTITHREADING
>> 524 select SYS_SUPPORTS_SMARTMIPS
>> 525 select SYS_SUPPORTS_VPE_LOADER
>> 526 select SYS_SUPPORTS_ZBOOT
>> 527 select SYS_SUPPORTS_RELOCATABLE
>> 528 select USE_OF
>> 529 select LIBFDT
>> 530 select ZONE_DMA32 if 64BIT
>> 531 select BUILTIN_DTB
>> 532 select LIBFDT
>> 533 help
>> 534 This enables support for the MIPS Technologies Malta evaluation
>> 535 board.
336 536
337 config ARCH_MMAP_RND_COMPAT_BITS_MAX !! 537 config MACH_PIC32
338 default 16 !! 538 bool "Microchip PIC32 Family"
>> 539 help
>> 540 This enables support for the Microchip PIC32 family of platforms.
339 541
340 config NO_IOPORT_MAP !! 542 Microchip PIC32 is a family of general-purpose 32 bit MIPS core
341 def_bool y if !PCI !! 543 microcontrollers.
>> 544
>> 545 config NEC_MARKEINS
>> 546 bool "NEC EMMA2RH Mark-eins board"
>> 547 select SOC_EMMA2RH
>> 548 select HW_HAS_PCI
>> 549 help
>> 550 This enables support for the NEC Electronics Mark-eins boards.
>> 551
>> 552 config MACH_VR41XX
>> 553 bool "NEC VR4100 series based machines"
>> 554 select CEVT_R4K
>> 555 select CSRC_R4K
>> 556 select SYS_HAS_CPU_VR41XX
>> 557 select SYS_SUPPORTS_MIPS16
>> 558 select GPIOLIB
>> 559
>> 560 config NXP_STB220
>> 561 bool "NXP STB220 board"
>> 562 select SOC_PNX833X
>> 563 help
>> 564 Support for NXP Semiconductors STB220 Development Board.
>> 565
>> 566 config NXP_STB225
>> 567 bool "NXP 225 board"
>> 568 select SOC_PNX833X
>> 569 select SOC_PNX8335
>> 570 help
>> 571 Support for NXP Semiconductors STB225 Development Board.
>> 572
>> 573 config PMC_MSP
>> 574 bool "PMC-Sierra MSP chipsets"
>> 575 select CEVT_R4K
>> 576 select CSRC_R4K
>> 577 select DMA_NONCOHERENT
>> 578 select SWAP_IO_SPACE
>> 579 select NO_EXCEPT_FILL
>> 580 select BOOT_RAW
>> 581 select SYS_HAS_CPU_MIPS32_R1
>> 582 select SYS_HAS_CPU_MIPS32_R2
>> 583 select SYS_SUPPORTS_32BIT_KERNEL
>> 584 select SYS_SUPPORTS_BIG_ENDIAN
>> 585 select SYS_SUPPORTS_MIPS16
>> 586 select IRQ_MIPS_CPU
>> 587 select SERIAL_8250
>> 588 select SERIAL_8250_CONSOLE
>> 589 select USB_EHCI_BIG_ENDIAN_MMIO
>> 590 select USB_EHCI_BIG_ENDIAN_DESC
>> 591 help
>> 592 This adds support for the PMC-Sierra family of Multi-Service
>> 593 Processor System-On-A-Chips. These parts include a number
>> 594 of integrated peripherals, interfaces and DSPs in addition to
>> 595 a variety of MIPS cores.
>> 596
>> 597 config RALINK
>> 598 bool "Ralink based machines"
>> 599 select CEVT_R4K
>> 600 select CSRC_R4K
>> 601 select BOOT_RAW
>> 602 select DMA_NONCOHERENT
>> 603 select IRQ_MIPS_CPU
>> 604 select USE_OF
>> 605 select SYS_HAS_CPU_MIPS32_R1
>> 606 select SYS_HAS_CPU_MIPS32_R2
>> 607 select SYS_SUPPORTS_32BIT_KERNEL
>> 608 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 609 select SYS_SUPPORTS_MIPS16
>> 610 select SYS_HAS_EARLY_PRINTK
>> 611 select CLKDEV_LOOKUP
>> 612 select ARCH_HAS_RESET_CONTROLLER
>> 613 select RESET_CONTROLLER
>> 614
>> 615 config SGI_IP22
>> 616 bool "SGI IP22 (Indy/Indigo2)"
>> 617 select FW_ARC
>> 618 select FW_ARC32
>> 619 select ARCH_MIGHT_HAVE_PC_SERIO
>> 620 select BOOT_ELF32
>> 621 select CEVT_R4K
>> 622 select CSRC_R4K
>> 623 select DEFAULT_SGI_PARTITION
>> 624 select DMA_NONCOHERENT
>> 625 select HW_HAS_EISA
>> 626 select I8253
>> 627 select I8259
>> 628 select IP22_CPU_SCACHE
>> 629 select IRQ_MIPS_CPU
>> 630 select GENERIC_ISA_DMA_SUPPORT_BROKEN
>> 631 select SGI_HAS_I8042
>> 632 select SGI_HAS_INDYDOG
>> 633 select SGI_HAS_HAL2
>> 634 select SGI_HAS_SEEQ
>> 635 select SGI_HAS_WD93
>> 636 select SGI_HAS_ZILOG
>> 637 select SWAP_IO_SPACE
>> 638 select SYS_HAS_CPU_R4X00
>> 639 select SYS_HAS_CPU_R5000
>> 640 #
>> 641 # Disable EARLY_PRINTK for now since it leads to overwritten prom
>> 642 # memory during early boot on some machines.
>> 643 #
>> 644 # See http://www.linux-mips.org/cgi-bin/mesg.cgi?a=linux-mips&i=20091119164009.GA15038%40deprecation.cyrius.com
>> 645 # for a more details discussion
>> 646 #
>> 647 # select SYS_HAS_EARLY_PRINTK
>> 648 select SYS_SUPPORTS_32BIT_KERNEL
>> 649 select SYS_SUPPORTS_64BIT_KERNEL
>> 650 select SYS_SUPPORTS_BIG_ENDIAN
>> 651 select MIPS_L1_CACHE_SHIFT_7
>> 652 help
>> 653 This are the SGI Indy, Challenge S and Indigo2, as well as certain
>> 654 OEM variants like the Tandem CMN B006S. To compile a Linux kernel
>> 655 that runs on these, say Y here.
>> 656
>> 657 config SGI_IP27
>> 658 bool "SGI IP27 (Origin200/2000)"
>> 659 select FW_ARC
>> 660 select FW_ARC64
>> 661 select BOOT_ELF64
>> 662 select DEFAULT_SGI_PARTITION
>> 663 select DMA_COHERENT
>> 664 select SYS_HAS_EARLY_PRINTK
>> 665 select HW_HAS_PCI
>> 666 select NR_CPUS_DEFAULT_64
>> 667 select SYS_HAS_CPU_R10000
>> 668 select SYS_SUPPORTS_64BIT_KERNEL
>> 669 select SYS_SUPPORTS_BIG_ENDIAN
>> 670 select SYS_SUPPORTS_NUMA
>> 671 select SYS_SUPPORTS_SMP
>> 672 select MIPS_L1_CACHE_SHIFT_7
>> 673 help
>> 674 This are the SGI Origin 200, Origin 2000 and Onyx 2 Graphics
>> 675 workstations. To compile a Linux kernel that runs on these, say Y
>> 676 here.
>> 677
>> 678 config SGI_IP28
>> 679 bool "SGI IP28 (Indigo2 R10k)"
>> 680 select FW_ARC
>> 681 select FW_ARC64
>> 682 select ARCH_MIGHT_HAVE_PC_SERIO
>> 683 select BOOT_ELF64
>> 684 select CEVT_R4K
>> 685 select CSRC_R4K
>> 686 select DEFAULT_SGI_PARTITION
>> 687 select DMA_NONCOHERENT
>> 688 select GENERIC_ISA_DMA_SUPPORT_BROKEN
>> 689 select IRQ_MIPS_CPU
>> 690 select HW_HAS_EISA
>> 691 select I8253
>> 692 select I8259
>> 693 select SGI_HAS_I8042
>> 694 select SGI_HAS_INDYDOG
>> 695 select SGI_HAS_HAL2
>> 696 select SGI_HAS_SEEQ
>> 697 select SGI_HAS_WD93
>> 698 select SGI_HAS_ZILOG
>> 699 select SWAP_IO_SPACE
>> 700 select SYS_HAS_CPU_R10000
>> 701 #
>> 702 # Disable EARLY_PRINTK for now since it leads to overwritten prom
>> 703 # memory during early boot on some machines.
>> 704 #
>> 705 # See http://www.linux-mips.org/cgi-bin/mesg.cgi?a=linux-mips&i=20091119164009.GA15038%40deprecation.cyrius.com
>> 706 # for a more details discussion
>> 707 #
>> 708 # select SYS_HAS_EARLY_PRINTK
>> 709 select SYS_SUPPORTS_64BIT_KERNEL
>> 710 select SYS_SUPPORTS_BIG_ENDIAN
>> 711 select MIPS_L1_CACHE_SHIFT_7
>> 712 help
>> 713 This is the SGI Indigo2 with R10000 processor. To compile a Linux
>> 714 kernel that runs on these, say Y here.
>> 715
>> 716 config SGI_IP32
>> 717 bool "SGI IP32 (O2)"
>> 718 select FW_ARC
>> 719 select FW_ARC32
>> 720 select BOOT_ELF32
>> 721 select CEVT_R4K
>> 722 select CSRC_R4K
>> 723 select DMA_NONCOHERENT
>> 724 select HW_HAS_PCI
>> 725 select IRQ_MIPS_CPU
>> 726 select R5000_CPU_SCACHE
>> 727 select RM7000_CPU_SCACHE
>> 728 select SYS_HAS_CPU_R5000
>> 729 select SYS_HAS_CPU_R10000 if BROKEN
>> 730 select SYS_HAS_CPU_RM7000
>> 731 select SYS_HAS_CPU_NEVADA
>> 732 select SYS_SUPPORTS_64BIT_KERNEL
>> 733 select SYS_SUPPORTS_BIG_ENDIAN
>> 734 help
>> 735 If you want this kernel to run on SGI O2 workstation, say Y here.
>> 736
>> 737 config SIBYTE_CRHINE
>> 738 bool "Sibyte BCM91120C-CRhine"
>> 739 select BOOT_ELF32
>> 740 select DMA_COHERENT
>> 741 select SIBYTE_BCM1120
>> 742 select SWAP_IO_SPACE
>> 743 select SYS_HAS_CPU_SB1
>> 744 select SYS_SUPPORTS_BIG_ENDIAN
>> 745 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 746
>> 747 config SIBYTE_CARMEL
>> 748 bool "Sibyte BCM91120x-Carmel"
>> 749 select BOOT_ELF32
>> 750 select DMA_COHERENT
>> 751 select SIBYTE_BCM1120
>> 752 select SWAP_IO_SPACE
>> 753 select SYS_HAS_CPU_SB1
>> 754 select SYS_SUPPORTS_BIG_ENDIAN
>> 755 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 756
>> 757 config SIBYTE_CRHONE
>> 758 bool "Sibyte BCM91125C-CRhone"
>> 759 select BOOT_ELF32
>> 760 select DMA_COHERENT
>> 761 select SIBYTE_BCM1125
>> 762 select SWAP_IO_SPACE
>> 763 select SYS_HAS_CPU_SB1
>> 764 select SYS_SUPPORTS_BIG_ENDIAN
>> 765 select SYS_SUPPORTS_HIGHMEM
>> 766 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 767
>> 768 config SIBYTE_RHONE
>> 769 bool "Sibyte BCM91125E-Rhone"
>> 770 select BOOT_ELF32
>> 771 select DMA_COHERENT
>> 772 select SIBYTE_BCM1125H
>> 773 select SWAP_IO_SPACE
>> 774 select SYS_HAS_CPU_SB1
>> 775 select SYS_SUPPORTS_BIG_ENDIAN
>> 776 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 777
>> 778 config SIBYTE_SWARM
>> 779 bool "Sibyte BCM91250A-SWARM"
>> 780 select BOOT_ELF32
>> 781 select DMA_COHERENT
>> 782 select HAVE_PATA_PLATFORM
>> 783 select SIBYTE_SB1250
>> 784 select SWAP_IO_SPACE
>> 785 select SYS_HAS_CPU_SB1
>> 786 select SYS_SUPPORTS_BIG_ENDIAN
>> 787 select SYS_SUPPORTS_HIGHMEM
>> 788 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 789 select ZONE_DMA32 if 64BIT
>> 790
>> 791 config SIBYTE_LITTLESUR
>> 792 bool "Sibyte BCM91250C2-LittleSur"
>> 793 select BOOT_ELF32
>> 794 select DMA_COHERENT
>> 795 select HAVE_PATA_PLATFORM
>> 796 select SIBYTE_SB1250
>> 797 select SWAP_IO_SPACE
>> 798 select SYS_HAS_CPU_SB1
>> 799 select SYS_SUPPORTS_BIG_ENDIAN
>> 800 select SYS_SUPPORTS_HIGHMEM
>> 801 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 802
>> 803 config SIBYTE_SENTOSA
>> 804 bool "Sibyte BCM91250E-Sentosa"
>> 805 select BOOT_ELF32
>> 806 select DMA_COHERENT
>> 807 select SIBYTE_SB1250
>> 808 select SWAP_IO_SPACE
>> 809 select SYS_HAS_CPU_SB1
>> 810 select SYS_SUPPORTS_BIG_ENDIAN
>> 811 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 812
>> 813 config SIBYTE_BIGSUR
>> 814 bool "Sibyte BCM91480B-BigSur"
>> 815 select BOOT_ELF32
>> 816 select DMA_COHERENT
>> 817 select NR_CPUS_DEFAULT_4
>> 818 select SIBYTE_BCM1x80
>> 819 select SWAP_IO_SPACE
>> 820 select SYS_HAS_CPU_SB1
>> 821 select SYS_SUPPORTS_BIG_ENDIAN
>> 822 select SYS_SUPPORTS_HIGHMEM
>> 823 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 824 select ZONE_DMA32 if 64BIT
>> 825
>> 826 config SNI_RM
>> 827 bool "SNI RM200/300/400"
>> 828 select FW_ARC if CPU_LITTLE_ENDIAN
>> 829 select FW_ARC32 if CPU_LITTLE_ENDIAN
>> 830 select FW_SNIPROM if CPU_BIG_ENDIAN
>> 831 select ARCH_MAY_HAVE_PC_FDC
>> 832 select ARCH_MIGHT_HAVE_PC_PARPORT
>> 833 select ARCH_MIGHT_HAVE_PC_SERIO
>> 834 select BOOT_ELF32
>> 835 select CEVT_R4K
>> 836 select CSRC_R4K
>> 837 select DEFAULT_SGI_PARTITION if CPU_BIG_ENDIAN
>> 838 select DMA_NONCOHERENT
>> 839 select GENERIC_ISA_DMA
>> 840 select HAVE_PCSPKR_PLATFORM
>> 841 select HW_HAS_EISA
>> 842 select HW_HAS_PCI
>> 843 select IRQ_MIPS_CPU
>> 844 select I8253
>> 845 select I8259
>> 846 select ISA
>> 847 select SWAP_IO_SPACE if CPU_BIG_ENDIAN
>> 848 select SYS_HAS_CPU_R4X00
>> 849 select SYS_HAS_CPU_R5000
>> 850 select SYS_HAS_CPU_R10000
>> 851 select R5000_CPU_SCACHE
>> 852 select SYS_HAS_EARLY_PRINTK
>> 853 select SYS_SUPPORTS_32BIT_KERNEL
>> 854 select SYS_SUPPORTS_64BIT_KERNEL
>> 855 select SYS_SUPPORTS_BIG_ENDIAN
>> 856 select SYS_SUPPORTS_HIGHMEM
>> 857 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 858 help
>> 859 The SNI RM200/300/400 are MIPS-based machines manufactured by
>> 860 Siemens Nixdorf Informationssysteme (SNI), parent company of Pyramid
>> 861 Technology and now in turn merged with Fujitsu. Say Y here to
>> 862 support this machine type.
>> 863
>> 864 config MACH_TX39XX
>> 865 bool "Toshiba TX39 series based machines"
>> 866
>> 867 config MACH_TX49XX
>> 868 bool "Toshiba TX49 series based machines"
>> 869
>> 870 config MIKROTIK_RB532
>> 871 bool "Mikrotik RB532 boards"
>> 872 select CEVT_R4K
>> 873 select CSRC_R4K
>> 874 select DMA_NONCOHERENT
>> 875 select HW_HAS_PCI
>> 876 select IRQ_MIPS_CPU
>> 877 select SYS_HAS_CPU_MIPS32_R1
>> 878 select SYS_SUPPORTS_32BIT_KERNEL
>> 879 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 880 select SWAP_IO_SPACE
>> 881 select BOOT_RAW
>> 882 select GPIOLIB
>> 883 select MIPS_L1_CACHE_SHIFT_4
>> 884 help
>> 885 Support the Mikrotik(tm) RouterBoard 532 series,
>> 886 based on the IDT RC32434 SoC.
>> 887
>> 888 config CAVIUM_OCTEON_SOC
>> 889 bool "Cavium Networks Octeon SoC based boards"
>> 890 select CEVT_R4K
>> 891 select ARCH_HAS_PHYS_TO_DMA
>> 892 select ARCH_PHYS_ADDR_T_64BIT
>> 893 select DMA_COHERENT
>> 894 select SYS_SUPPORTS_64BIT_KERNEL
>> 895 select SYS_SUPPORTS_BIG_ENDIAN
>> 896 select EDAC_SUPPORT
>> 897 select EDAC_ATOMIC_SCRUB
>> 898 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 899 select SYS_SUPPORTS_HOTPLUG_CPU if CPU_BIG_ENDIAN
>> 900 select SYS_HAS_EARLY_PRINTK
>> 901 select SYS_HAS_CPU_CAVIUM_OCTEON
>> 902 select HW_HAS_PCI
>> 903 select ZONE_DMA32
>> 904 select HOLES_IN_ZONE
>> 905 select GPIOLIB
>> 906 select LIBFDT
>> 907 select USE_OF
>> 908 select ARCH_SPARSEMEM_ENABLE
>> 909 select SYS_SUPPORTS_SMP
>> 910 select NR_CPUS_DEFAULT_64
>> 911 select MIPS_NR_CPU_NR_MAP_1024
>> 912 select BUILTIN_DTB
>> 913 select MTD_COMPLEX_MAPPINGS
>> 914 select SYS_SUPPORTS_RELOCATABLE
>> 915 help
>> 916 This option supports all of the Octeon reference boards from Cavium
>> 917 Networks. It builds a kernel that dynamically determines the Octeon
>> 918 CPU type and supports all known board reference implementations.
>> 919 Some of the supported boards are:
>> 920 EBT3000
>> 921 EBH3000
>> 922 EBH3100
>> 923 Thunder
>> 924 Kodama
>> 925 Hikari
>> 926 Say Y here for most Octeon reference boards.
>> 927
>> 928 config NLM_XLR_BOARD
>> 929 bool "Netlogic XLR/XLS based systems"
>> 930 select BOOT_ELF32
>> 931 select NLM_COMMON
>> 932 select SYS_HAS_CPU_XLR
>> 933 select SYS_SUPPORTS_SMP
>> 934 select HW_HAS_PCI
>> 935 select SWAP_IO_SPACE
>> 936 select SYS_SUPPORTS_32BIT_KERNEL
>> 937 select SYS_SUPPORTS_64BIT_KERNEL
>> 938 select ARCH_PHYS_ADDR_T_64BIT
>> 939 select SYS_SUPPORTS_BIG_ENDIAN
>> 940 select SYS_SUPPORTS_HIGHMEM
>> 941 select DMA_COHERENT
>> 942 select NR_CPUS_DEFAULT_32
>> 943 select CEVT_R4K
>> 944 select CSRC_R4K
>> 945 select IRQ_MIPS_CPU
>> 946 select ZONE_DMA32 if 64BIT
>> 947 select SYNC_R4K
>> 948 select SYS_HAS_EARLY_PRINTK
>> 949 select SYS_SUPPORTS_ZBOOT
>> 950 select SYS_SUPPORTS_ZBOOT_UART16550
>> 951 help
>> 952 Support for systems based on Netlogic XLR and XLS processors.
>> 953 Say Y here if you have a XLR or XLS based board.
>> 954
>> 955 config NLM_XLP_BOARD
>> 956 bool "Netlogic XLP based systems"
>> 957 select BOOT_ELF32
>> 958 select NLM_COMMON
>> 959 select SYS_HAS_CPU_XLP
>> 960 select SYS_SUPPORTS_SMP
>> 961 select HW_HAS_PCI
>> 962 select SYS_SUPPORTS_32BIT_KERNEL
>> 963 select SYS_SUPPORTS_64BIT_KERNEL
>> 964 select ARCH_PHYS_ADDR_T_64BIT
>> 965 select GPIOLIB
>> 966 select SYS_SUPPORTS_BIG_ENDIAN
>> 967 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 968 select SYS_SUPPORTS_HIGHMEM
>> 969 select DMA_COHERENT
>> 970 select NR_CPUS_DEFAULT_32
>> 971 select CEVT_R4K
>> 972 select CSRC_R4K
>> 973 select IRQ_MIPS_CPU
>> 974 select ZONE_DMA32 if 64BIT
>> 975 select SYNC_R4K
>> 976 select SYS_HAS_EARLY_PRINTK
>> 977 select USE_OF
>> 978 select SYS_SUPPORTS_ZBOOT
>> 979 select SYS_SUPPORTS_ZBOOT_UART16550
>> 980 help
>> 981 This board is based on Netlogic XLP Processor.
>> 982 Say Y here if you have a XLP based board.
>> 983
>> 984 config MIPS_PARAVIRT
>> 985 bool "Para-Virtualized guest system"
>> 986 select CEVT_R4K
>> 987 select CSRC_R4K
>> 988 select DMA_COHERENT
>> 989 select SYS_SUPPORTS_64BIT_KERNEL
>> 990 select SYS_SUPPORTS_32BIT_KERNEL
>> 991 select SYS_SUPPORTS_BIG_ENDIAN
>> 992 select SYS_SUPPORTS_SMP
>> 993 select NR_CPUS_DEFAULT_4
>> 994 select SYS_HAS_EARLY_PRINTK
>> 995 select SYS_HAS_CPU_MIPS32_R2
>> 996 select SYS_HAS_CPU_MIPS64_R2
>> 997 select SYS_HAS_CPU_CAVIUM_OCTEON
>> 998 select HW_HAS_PCI
>> 999 select SWAP_IO_SPACE
>> 1000 help
>> 1001 This option supports guest running under ????
342 1002
343 config STACKTRACE_SUPPORT !! 1003 endchoice
344 def_bool y <<
345 1004
346 config ILLEGAL_POINTER_VALUE !! 1005 source "arch/mips/alchemy/Kconfig"
347 hex !! 1006 source "arch/mips/ath25/Kconfig"
348 default 0xdead000000000000 !! 1007 source "arch/mips/ath79/Kconfig"
>> 1008 source "arch/mips/bcm47xx/Kconfig"
>> 1009 source "arch/mips/bcm63xx/Kconfig"
>> 1010 source "arch/mips/bmips/Kconfig"
>> 1011 source "arch/mips/generic/Kconfig"
>> 1012 source "arch/mips/jazz/Kconfig"
>> 1013 source "arch/mips/jz4740/Kconfig"
>> 1014 source "arch/mips/lantiq/Kconfig"
>> 1015 source "arch/mips/lasat/Kconfig"
>> 1016 source "arch/mips/pic32/Kconfig"
>> 1017 source "arch/mips/pistachio/Kconfig"
>> 1018 source "arch/mips/pmcs-msp71xx/Kconfig"
>> 1019 source "arch/mips/ralink/Kconfig"
>> 1020 source "arch/mips/sgi-ip27/Kconfig"
>> 1021 source "arch/mips/sibyte/Kconfig"
>> 1022 source "arch/mips/txx9/Kconfig"
>> 1023 source "arch/mips/vr41xx/Kconfig"
>> 1024 source "arch/mips/cavium-octeon/Kconfig"
>> 1025 source "arch/mips/loongson32/Kconfig"
>> 1026 source "arch/mips/loongson64/Kconfig"
>> 1027 source "arch/mips/netlogic/Kconfig"
>> 1028 source "arch/mips/paravirt/Kconfig"
349 1029
350 config LOCKDEP_SUPPORT !! 1030 endmenu
351 def_bool y <<
352 1031
353 config GENERIC_BUG !! 1032 config RWSEM_GENERIC_SPINLOCK
354 def_bool y !! 1033 bool
355 depends on BUG !! 1034 default y
356 1035
357 config GENERIC_BUG_RELATIVE_POINTERS !! 1036 config RWSEM_XCHGADD_ALGORITHM
358 def_bool y !! 1037 bool
359 depends on GENERIC_BUG <<
360 1038
361 config GENERIC_HWEIGHT 1039 config GENERIC_HWEIGHT
362 def_bool y !! 1040 bool
363 !! 1041 default y
364 config GENERIC_CSUM <<
365 def_bool y <<
366 1042
367 config GENERIC_CALIBRATE_DELAY 1043 config GENERIC_CALIBRATE_DELAY
368 def_bool y <<
369 <<
370 config SMP <<
371 def_bool y <<
372 <<
373 config KERNEL_MODE_NEON <<
374 def_bool y <<
375 <<
376 config FIX_EARLYCON_MEM <<
377 def_bool y <<
378 <<
379 config PGTABLE_LEVELS <<
380 int <<
381 default 2 if ARM64_16K_PAGES && ARM64_ <<
382 default 2 if ARM64_64K_PAGES && ARM64_ <<
383 default 3 if ARM64_64K_PAGES && (ARM64 <<
384 default 3 if ARM64_4K_PAGES && ARM64_V <<
385 default 3 if ARM64_16K_PAGES && ARM64_ <<
386 default 4 if ARM64_16K_PAGES && (ARM64 <<
387 default 4 if !ARM64_64K_PAGES && ARM64 <<
388 default 5 if ARM64_4K_PAGES && ARM64_V <<
389 <<
390 config ARCH_SUPPORTS_UPROBES <<
391 def_bool y <<
392 <<
393 config ARCH_PROC_KCORE_TEXT <<
394 def_bool y <<
395 <<
396 config BROKEN_GAS_INST <<
397 def_bool !$(as-instr,1:\n.inst 0\n.rep <<
398 <<
399 config BUILTIN_RETURN_ADDRESS_STRIPS_PAC <<
400 bool 1044 bool
401 # Clang's __builtin_return_address() s !! 1045 default y
402 # https://github.com/llvm/llvm-project <<
403 default y if CC_IS_CLANG <<
404 # GCC's __builtin_return_address() str <<
405 # and this was backported to 10.2.0, 9 <<
406 # https://gcc.gnu.org/bugzilla/show_bu <<
407 default y if CC_IS_GCC && (GCC_VERSION <<
408 default y if CC_IS_GCC && (GCC_VERSION <<
409 default y if CC_IS_GCC && (GCC_VERSION <<
410 default y if CC_IS_GCC && (GCC_VERSION <<
411 default n <<
412 <<
413 config KASAN_SHADOW_OFFSET <<
414 hex <<
415 depends on KASAN_GENERIC || KASAN_SW_T <<
416 default 0xdfff800000000000 if (ARM64_V <<
417 default 0xdfffc00000000000 if (ARM64_V <<
418 default 0xdffffe0000000000 if ARM64_VA <<
419 default 0xdfffffc000000000 if ARM64_VA <<
420 default 0xdffffff800000000 if ARM64_VA <<
421 default 0xefff800000000000 if (ARM64_V <<
422 default 0xefffc00000000000 if (ARM64_V <<
423 default 0xeffffe0000000000 if ARM64_VA <<
424 default 0xefffffc000000000 if ARM64_VA <<
425 default 0xeffffff800000000 if ARM64_VA <<
426 default 0xffffffffffffffff <<
427 <<
428 config UNWIND_TABLES <<
429 bool <<
430 <<
431 source "arch/arm64/Kconfig.platforms" <<
432 <<
433 menu "Kernel Features" <<
434 <<
435 menu "ARM errata workarounds via the alternati <<
436 <<
437 config AMPERE_ERRATUM_AC03_CPU_38 <<
438 bool "AmpereOne: AC03_CPU_38: Certain <<
439 default y <<
440 help <<
441 This option adds an alternative code <<
442 errata AC03_CPU_38 and AC04_CPU_10 o <<
443 <<
444 The affected design reports FEAT_HAF <<
445 ID_AA64MMFR1_EL1.HAFDBS, but (V)TCR_ <<
446 as required by the architecture. The <<
447 implementation suffers from an addit <<
448 A/D updates can occur after a PTE ha <<
449 <<
450 The workaround forces KVM to explici <<
451 which avoids enabling unadvertised h <<
452 at stage-2. <<
453 <<
454 If unsure, say Y. <<
455 1046
456 config ARM64_WORKAROUND_CLEAN_CACHE !! 1047 config SCHED_OMIT_FRAME_POINTER
457 bool 1048 bool
458 <<
459 config ARM64_ERRATUM_826319 <<
460 bool "Cortex-A53: 826319: System might <<
461 default y 1049 default y
462 select ARM64_WORKAROUND_CLEAN_CACHE <<
463 help <<
464 This option adds an alternative code <<
465 erratum 826319 on Cortex-A53 parts u <<
466 AXI master interface and an L2 cache <<
467 1050
468 If a Cortex-A53 uses an AMBA AXI4 AC !! 1051 #
469 and is unable to accept a certain wr !! 1052 # Select some configuration options automatically based on user selections.
470 not progress on read data presented !! 1053 #
471 system can deadlock. !! 1054 config FW_ARC
472 !! 1055 bool
473 The workaround promotes data cache c <<
474 data cache clean-and-invalidate. <<
475 Please note that this does not neces <<
476 as it depends on the alternative fra <<
477 the kernel if an affected CPU is det <<
478 <<
479 If unsure, say Y. <<
480 <<
481 config ARM64_ERRATUM_827319 <<
482 bool "Cortex-A53: 827319: Data cache c <<
483 default y <<
484 select ARM64_WORKAROUND_CLEAN_CACHE <<
485 help <<
486 This option adds an alternative code <<
487 erratum 827319 on Cortex-A53 parts u <<
488 master interface and an L2 cache. <<
489 <<
490 Under certain conditions this erratu <<
491 to occur at the same time as another <<
492 on the AMBA 5 CHI interface, which c <<
493 interconnect reorders the two transa <<
494 <<
495 The workaround promotes data cache c <<
496 data cache clean-and-invalidate. <<
497 Please note that this does not neces <<
498 as it depends on the alternative fra <<
499 the kernel if an affected CPU is det <<
500 1056
501 If unsure, say Y. !! 1057 config ARCH_MAY_HAVE_PC_FDC
>> 1058 bool
502 1059
503 config ARM64_ERRATUM_824069 !! 1060 config BOOT_RAW
504 bool "Cortex-A53: 824069: Cache line m !! 1061 bool
505 default y <<
506 select ARM64_WORKAROUND_CLEAN_CACHE <<
507 help <<
508 This option adds an alternative code <<
509 erratum 824069 on Cortex-A53 parts u <<
510 to a coherent interconnect. <<
511 <<
512 If a Cortex-A53 processor is executi <<
513 write instruction at the same time a <<
514 cluster is executing a cache mainten <<
515 address, then this erratum might cau <<
516 incorrectly marked as dirty. <<
517 <<
518 The workaround promotes data cache c <<
519 data cache clean-and-invalidate. <<
520 Please note that this option does no <<
521 workaround, as it depends on the alt <<
522 only patch the kernel if an affected <<
523 1062
524 If unsure, say Y. !! 1063 config CEVT_BCM1480
>> 1064 bool
525 1065
526 config ARM64_ERRATUM_819472 !! 1066 config CEVT_DS1287
527 bool "Cortex-A53: 819472: Store exclus !! 1067 bool
528 default y <<
529 select ARM64_WORKAROUND_CLEAN_CACHE <<
530 help <<
531 This option adds an alternative code <<
532 erratum 819472 on Cortex-A53 parts u <<
533 present when it is connected to a co <<
534 <<
535 If the processor is executing a load <<
536 the same time as a processor in anot <<
537 maintenance operation to the same ad <<
538 cause data corruption. <<
539 <<
540 The workaround promotes data cache c <<
541 data cache clean-and-invalidate. <<
542 Please note that this does not neces <<
543 as it depends on the alternative fra <<
544 the kernel if an affected CPU is det <<
545 1068
546 If unsure, say Y. !! 1069 config CEVT_GT641XX
>> 1070 bool
547 1071
548 config ARM64_ERRATUM_832075 !! 1072 config CEVT_R4K
549 bool "Cortex-A57: 832075: possible dea !! 1073 bool
550 default y <<
551 help <<
552 This option adds an alternative code <<
553 erratum 832075 on Cortex-A57 parts u <<
554 1074
555 Affected Cortex-A57 parts might dead !! 1075 config CEVT_SB1250
556 instructions to Write-Back memory ar !! 1076 bool
557 1077
558 The workaround is to promote device !! 1078 config CEVT_TXX9
559 semantics. !! 1079 bool
560 Please note that this does not neces <<
561 as it depends on the alternative fra <<
562 the kernel if an affected CPU is det <<
563 1080
564 If unsure, say Y. !! 1081 config CSRC_BCM1480
>> 1082 bool
565 1083
566 config ARM64_ERRATUM_834220 !! 1084 config CSRC_IOASIC
567 bool "Cortex-A57: 834220: Stage 2 tran !! 1085 bool
568 depends on KVM <<
569 help <<
570 This option adds an alternative code <<
571 erratum 834220 on Cortex-A57 parts u <<
572 <<
573 Affected Cortex-A57 parts might repo <<
574 fault as the result of a Stage 1 fau <<
575 page boundary when there is a permis <<
576 alignment fault at Stage 1 and a tra <<
577 <<
578 The workaround is to verify that the <<
579 doesn't generate a fault before hand <<
580 Please note that this does not neces <<
581 as it depends on the alternative fra <<
582 the kernel if an affected CPU is det <<
583 1086
584 If unsure, say N. !! 1087 config CSRC_R4K
>> 1088 bool
585 1089
586 config ARM64_ERRATUM_1742098 !! 1090 config CSRC_SB1250
587 bool "Cortex-A57/A72: 1742098: ELR rec !! 1091 bool
588 depends on COMPAT <<
589 default y <<
590 help <<
591 This option removes the AES hwcap fo <<
592 workaround erratum 1742098 on Cortex <<
593 <<
594 Affected parts may corrupt the AES s <<
595 taken between a pair of AES instruct <<
596 are only present if the cryptography <<
597 All software should have a fallback <<
598 that don't implement the cryptograph <<
599 1092
600 If unsure, say Y. !! 1093 config MIPS_CLOCK_VSYSCALL
>> 1094 def_bool CSRC_R4K || CLKSRC_MIPS_GIC
601 1095
602 config ARM64_ERRATUM_845719 !! 1096 config GPIO_TXX9
603 bool "Cortex-A53: 845719: a load might !! 1097 select GPIOLIB
604 depends on COMPAT !! 1098 bool
605 default y <<
606 help <<
607 This option adds an alternative code <<
608 erratum 845719 on Cortex-A53 parts u <<
609 <<
610 When running a compat (AArch32) user <<
611 part, a load at EL0 from a virtual a <<
612 bits of the virtual address used by <<
613 might return incorrect data. <<
614 <<
615 The workaround is to write the conte <<
616 return to a 32-bit task. <<
617 Please note that this does not neces <<
618 as it depends on the alternative fra <<
619 the kernel if an affected CPU is det <<
620 1099
621 If unsure, say Y. !! 1100 config FW_CFE
>> 1101 bool
622 1102
623 config ARM64_ERRATUM_843419 !! 1103 config ARCH_DMA_ADDR_T_64BIT
624 bool "Cortex-A53: 843419: A load or st !! 1104 def_bool (HIGHMEM && ARCH_PHYS_ADDR_T_64BIT) || 64BIT
625 default y <<
626 help <<
627 This option links the kernel with '- <<
628 enables PLT support to replace certa <<
629 cause subsequent memory accesses to <<
630 Cortex-A53 parts up to r0p4. <<
631 1105
632 If unsure, say Y. !! 1106 config ARCH_SUPPORTS_UPROBES
>> 1107 bool
633 1108
634 config ARM64_LD_HAS_FIX_ERRATUM_843419 !! 1109 config DMA_MAYBE_COHERENT
635 def_bool $(ld-option,--fix-cortex-a53- !! 1110 select DMA_NONCOHERENT
>> 1111 bool
636 1112
637 config ARM64_ERRATUM_1024718 !! 1113 config DMA_PERDEV_COHERENT
638 bool "Cortex-A55: 1024718: Update of D !! 1114 bool
639 default y !! 1115 select DMA_MAYBE_COHERENT
640 help <<
641 This option adds a workaround for AR <<
642 1116
643 Affected Cortex-A55 cores (all revis !! 1117 config DMA_COHERENT
644 update of the hardware dirty bit whe !! 1118 bool
645 without a break-before-make. The wor <<
646 of hardware DBM locally on the affec <<
647 this erratum will continue to use th <<
648 1119
649 If unsure, say Y. !! 1120 config DMA_NONCOHERENT
>> 1121 bool
>> 1122 select NEED_DMA_MAP_STATE
650 1123
651 config ARM64_ERRATUM_1418040 !! 1124 config NEED_DMA_MAP_STATE
652 bool "Cortex-A76/Neoverse-N1: MRC read !! 1125 bool
653 default y <<
654 depends on COMPAT <<
655 help <<
656 This option adds a workaround for AR <<
657 errata 1188873 and 1418040. <<
658 1126
659 Affected Cortex-A76/Neoverse-N1 core !! 1127 config SYS_HAS_EARLY_PRINTK
660 cause register corruption when acces !! 1128 bool
661 from AArch32 userspace. <<
662 1129
663 If unsure, say Y. !! 1130 config SYS_SUPPORTS_HOTPLUG_CPU
>> 1131 bool
664 1132
665 config ARM64_WORKAROUND_SPECULATIVE_AT !! 1133 config MIPS_BONITO64
666 bool 1134 bool
667 1135
668 config ARM64_ERRATUM_1165522 !! 1136 config MIPS_MSC
669 bool "Cortex-A76: 1165522: Speculative !! 1137 bool
670 default y <<
671 select ARM64_WORKAROUND_SPECULATIVE_AT <<
672 help <<
673 This option adds a workaround for AR <<
674 1138
675 Affected Cortex-A76 cores (r0p0, r1p !! 1139 config MIPS_NILE4
676 corrupted TLBs by speculating an AT !! 1140 bool
677 context switch. <<
678 1141
679 If unsure, say Y. !! 1142 config SYNC_R4K
>> 1143 bool
680 1144
681 config ARM64_ERRATUM_1319367 !! 1145 config MIPS_MACHINE
682 bool "Cortex-A57/A72: 1319537: Specula !! 1146 def_bool n
683 default y <<
684 select ARM64_WORKAROUND_SPECULATIVE_AT <<
685 help <<
686 This option adds work arounds for AR <<
687 and A72 erratum 1319367 <<
688 1147
689 Cortex-A57 and A72 cores could end-u !! 1148 config NO_IOPORT_MAP
690 speculating an AT instruction during !! 1149 def_bool n
691 1150
692 If unsure, say Y. !! 1151 config GENERIC_CSUM
>> 1152 bool
693 1153
694 config ARM64_ERRATUM_1530923 !! 1154 config GENERIC_ISA_DMA
695 bool "Cortex-A55: 1530923: Speculative !! 1155 bool
696 default y !! 1156 select ZONE_DMA if GENERIC_ISA_DMA_SUPPORT_BROKEN=n
697 select ARM64_WORKAROUND_SPECULATIVE_AT !! 1157 select ISA_DMA_API
698 help <<
699 This option adds a workaround for AR <<
700 1158
701 Affected Cortex-A55 cores (r0p0, r0p !! 1159 config GENERIC_ISA_DMA_SUPPORT_BROKEN
702 corrupted TLBs by speculating an AT !! 1160 bool
703 context switch. !! 1161 select GENERIC_ISA_DMA
704 1162
705 If unsure, say Y. !! 1163 config ISA_DMA_API
>> 1164 bool
706 1165
707 config ARM64_WORKAROUND_REPEAT_TLBI !! 1166 config HOLES_IN_ZONE
708 bool 1167 bool
709 1168
710 config ARM64_ERRATUM_2441007 !! 1169 config SYS_SUPPORTS_RELOCATABLE
711 bool "Cortex-A55: Completion of affect !! 1170 bool
712 select ARM64_WORKAROUND_REPEAT_TLBI <<
713 help 1171 help
714 This option adds a workaround for AR !! 1172 Selected if the platform supports relocating the kernel.
715 !! 1173 The platform must provide plat_get_fdt() if it selects CONFIG_USE_OF
716 Under very rare circumstances, affec !! 1174 to allow access to command line and entropy sources.
717 may not handle a race between a brea <<
718 CPU, and another CPU accessing the s <<
719 store to a page that has been unmapp <<
720 1175
721 Work around this by adding the affec !! 1176 config MIPS_CBPF_JIT
722 TLB sequences to be done twice. !! 1177 def_bool y
723 !! 1178 depends on BPF_JIT && HAVE_CBPF_JIT
724 If unsure, say N. <<
725 1179
726 config ARM64_ERRATUM_1286807 !! 1180 config MIPS_EBPF_JIT
727 bool "Cortex-A76: Modification of the !! 1181 def_bool y
728 select ARM64_WORKAROUND_REPEAT_TLBI !! 1182 depends on BPF_JIT && HAVE_EBPF_JIT
729 help <<
730 This option adds a workaround for AR <<
731 <<
732 On the affected Cortex-A76 cores (r0 <<
733 address for a cacheable mapping of a <<
734 accessed by a core while another cor <<
735 address to a new physical page using <<
736 break-before-make sequence, then und <<
737 TLBI+DSB completes before a read usi <<
738 invalidated has been observed by oth <<
739 workaround repeats the TLBI+DSB oper <<
740 1183
741 If unsure, say N. <<
742 1184
743 config ARM64_ERRATUM_1463225 !! 1185 #
744 bool "Cortex-A76: Software Step might !! 1186 # Endianness selection. Sufficiently obscure so many users don't know what to
745 default y !! 1187 # answer,so we try hard to limit the available choices. Also the use of a
>> 1188 # choice statement should be more obvious to the user.
>> 1189 #
>> 1190 choice
>> 1191 prompt "Endianness selection"
746 help 1192 help
747 This option adds a workaround for Ar !! 1193 Some MIPS machines can be configured for either little or big endian
>> 1194 byte order. These modes require different kernels and a different
>> 1195 Linux distribution. In general there is one preferred byteorder for a
>> 1196 particular system but some systems are just as commonly used in the
>> 1197 one or the other endianness.
748 1198
749 On the affected Cortex-A76 cores (r0 !! 1199 config CPU_BIG_ENDIAN
750 of a system call instruction (SVC) c !! 1200 bool "Big endian"
751 subsequent interrupts when software !! 1201 depends on SYS_SUPPORTS_BIG_ENDIAN
752 exception handler of the system call <<
753 is enabled or VHE is in use. <<
754 1202
755 Work around the erratum by triggerin !! 1203 config CPU_LITTLE_ENDIAN
756 when handling a system call from a t !! 1204 bool "Little endian"
757 in a VHE configuration of the kernel !! 1205 depends on SYS_SUPPORTS_LITTLE_ENDIAN
758 1206
759 If unsure, say Y. !! 1207 endchoice
760 1208
761 config ARM64_ERRATUM_1542419 !! 1209 config EXPORT_UASM
762 bool "Neoverse-N1: workaround mis-orde !! 1210 bool
763 help <<
764 This option adds a workaround for AR <<
765 1542419. <<
766 1211
767 Affected Neoverse-N1 cores could exe !! 1212 config SYS_SUPPORTS_APM_EMULATION
768 modified by another CPU. The workaro !! 1213 bool
769 counterpart. <<
770 1214
771 Workaround the issue by hiding the D !! 1215 config SYS_SUPPORTS_BIG_ENDIAN
772 forces user-space to perform cache m !! 1216 bool
773 1217
774 If unsure, say N. !! 1218 config SYS_SUPPORTS_LITTLE_ENDIAN
>> 1219 bool
775 1220
776 config ARM64_ERRATUM_1508412 !! 1221 config SYS_SUPPORTS_HUGETLBFS
777 bool "Cortex-A77: 1508412: workaround !! 1222 bool
>> 1223 depends on CPU_SUPPORTS_HUGEPAGES && 64BIT
778 default y 1224 default y
779 help <<
780 This option adds a workaround for Ar <<
781 1225
782 Affected Cortex-A77 cores (r0p0, r1p !! 1226 config MIPS_HUGE_TLB_SUPPORT
783 of a store-exclusive or read of PAR_ !! 1227 def_bool HUGETLB_PAGE || TRANSPARENT_HUGEPAGE
784 non-cacheable memory attributes. The <<
785 counterpart. <<
786 1228
787 KVM guests must also have the workar !! 1229 config IRQ_CPU_RM7K
788 deadlock the system. !! 1230 bool
789 1231
790 Work around the issue by inserting D !! 1232 config IRQ_MSP_SLP
791 register reads and warning KVM users !! 1233 bool
792 to prevent a speculative PAR_EL1 rea <<
793 1234
794 If unsure, say Y. !! 1235 config IRQ_MSP_CIC
>> 1236 bool
795 1237
796 config ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MO !! 1238 config IRQ_TXX9
797 bool 1239 bool
798 1240
799 config ARM64_ERRATUM_2051678 !! 1241 config IRQ_GT641XX
800 bool "Cortex-A510: 2051678: disable Ha !! 1242 bool
801 default y <<
802 help <<
803 This options adds the workaround for <<
804 Affected Cortex-A510 might not respe <<
805 hardware update of the page table's <<
806 is to not enable the feature on affe <<
807 1243
808 If unsure, say Y. !! 1244 config PCI_GT64XXX_PCI0
>> 1245 bool
809 1246
810 config ARM64_ERRATUM_2077057 !! 1247 config NO_EXCEPT_FILL
811 bool "Cortex-A510: 2077057: workaround !! 1248 bool
812 default y <<
813 help <<
814 This option adds the workaround for <<
815 Affected Cortex-A510 may corrupt SPS <<
816 expected, but a Pointer Authenticati <<
817 erratum causes SPSR_EL1 to be copied <<
818 EL1 to cause a return to EL2 with a <<
819 1249
820 This can only happen when EL2 is ste !! 1250 config SOC_EMMA2RH
>> 1251 bool
>> 1252 select CEVT_R4K
>> 1253 select CSRC_R4K
>> 1254 select DMA_NONCOHERENT
>> 1255 select IRQ_MIPS_CPU
>> 1256 select SWAP_IO_SPACE
>> 1257 select SYS_HAS_CPU_R5500
>> 1258 select SYS_SUPPORTS_32BIT_KERNEL
>> 1259 select SYS_SUPPORTS_64BIT_KERNEL
>> 1260 select SYS_SUPPORTS_BIG_ENDIAN
821 1261
822 When these conditions occur, the SPS !! 1262 config SOC_PNX833X
823 previous guest entry, and can be res !! 1263 bool
>> 1264 select CEVT_R4K
>> 1265 select CSRC_R4K
>> 1266 select IRQ_MIPS_CPU
>> 1267 select DMA_NONCOHERENT
>> 1268 select SYS_HAS_CPU_MIPS32_R2
>> 1269 select SYS_SUPPORTS_32BIT_KERNEL
>> 1270 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 1271 select SYS_SUPPORTS_BIG_ENDIAN
>> 1272 select SYS_SUPPORTS_MIPS16
>> 1273 select CPU_MIPSR2_IRQ_VI
824 1274
825 If unsure, say Y. !! 1275 config SOC_PNX8335
>> 1276 bool
>> 1277 select SOC_PNX833X
826 1278
827 config ARM64_ERRATUM_2658417 !! 1279 config MIPS_SPRAM
828 bool "Cortex-A510: 2658417: remove BF1 !! 1280 bool
829 default y <<
830 help <<
831 This option adds the workaround for <<
832 Affected Cortex-A510 (r0p0 to r1p1) <<
833 BFMMLA or VMMLA instructions in rare <<
834 A510 CPUs are using shared neon hard <<
835 discoverable by the kernel, hide the <<
836 user-space should not be using these <<
837 1281
838 If unsure, say Y. !! 1282 config SWAP_IO_SPACE
>> 1283 bool
839 1284
840 config ARM64_ERRATUM_2119858 !! 1285 config SGI_HAS_INDYDOG
841 bool "Cortex-A710/X2: 2119858: workaro !! 1286 bool
842 default y <<
843 depends on CORESIGHT_TRBE <<
844 select ARM64_WORKAROUND_TRBE_OVERWRITE <<
845 help <<
846 This option adds the workaround for <<
847 1287
848 Affected Cortex-A710/X2 cores could !! 1288 config SGI_HAS_HAL2
849 data at the base of the buffer (poin !! 1289 bool
850 the event of a WRAP event. <<
851 1290
852 Work around the issue by always maki !! 1291 config SGI_HAS_SEEQ
853 256 bytes before enabling the buffer !! 1292 bool
854 the buffer with ETM ignore packets u <<
855 1293
856 If unsure, say Y. !! 1294 config SGI_HAS_WD93
>> 1295 bool
857 1296
858 config ARM64_ERRATUM_2139208 !! 1297 config SGI_HAS_ZILOG
859 bool "Neoverse-N2: 2139208: workaround !! 1298 bool
860 default y <<
861 depends on CORESIGHT_TRBE <<
862 select ARM64_WORKAROUND_TRBE_OVERWRITE <<
863 help <<
864 This option adds the workaround for <<
865 1299
866 Affected Neoverse-N2 cores could ove !! 1300 config SGI_HAS_I8042
867 data at the base of the buffer (poin !! 1301 bool
868 the event of a WRAP event. <<
869 1302
870 Work around the issue by always maki !! 1303 config DEFAULT_SGI_PARTITION
871 256 bytes before enabling the buffer !! 1304 bool
872 the buffer with ETM ignore packets u <<
873 1305
874 If unsure, say Y. !! 1306 config FW_ARC32
>> 1307 bool
875 1308
876 config ARM64_WORKAROUND_TSB_FLUSH_FAILURE !! 1309 config FW_SNIPROM
877 bool 1310 bool
878 1311
879 config ARM64_ERRATUM_2054223 !! 1312 config BOOT_ELF32
880 bool "Cortex-A710: 2054223: workaround !! 1313 bool
881 default y <<
882 select ARM64_WORKAROUND_TSB_FLUSH_FAIL <<
883 help <<
884 Enable workaround for ARM Cortex-A71 <<
885 1314
886 Affected cores may fail to flush the !! 1315 config MIPS_L1_CACHE_SHIFT_4
887 the PE is in trace prohibited state. !! 1316 bool
888 of the trace cached. <<
889 1317
890 Workaround is to issue two TSB conse !! 1318 config MIPS_L1_CACHE_SHIFT_5
>> 1319 bool
891 1320
892 If unsure, say Y. !! 1321 config MIPS_L1_CACHE_SHIFT_6
>> 1322 bool
893 1323
894 config ARM64_ERRATUM_2067961 !! 1324 config MIPS_L1_CACHE_SHIFT_7
895 bool "Neoverse-N2: 2067961: workaround !! 1325 bool
896 default y <<
897 select ARM64_WORKAROUND_TSB_FLUSH_FAIL <<
898 help <<
899 Enable workaround for ARM Neoverse-N <<
900 1326
901 Affected cores may fail to flush the !! 1327 config MIPS_L1_CACHE_SHIFT
902 the PE is in trace prohibited state. !! 1328 int
903 of the trace cached. !! 1329 default "7" if MIPS_L1_CACHE_SHIFT_7
>> 1330 default "6" if MIPS_L1_CACHE_SHIFT_6
>> 1331 default "5" if MIPS_L1_CACHE_SHIFT_5
>> 1332 default "4" if MIPS_L1_CACHE_SHIFT_4
>> 1333 default "5"
904 1334
905 Workaround is to issue two TSB conse !! 1335 config HAVE_STD_PC_SERIAL_PORT
>> 1336 bool
906 1337
907 If unsure, say Y. !! 1338 config ARC_CONSOLE
>> 1339 bool "ARC console support"
>> 1340 depends on SGI_IP22 || SGI_IP28 || (SNI_RM && CPU_LITTLE_ENDIAN)
908 1341
909 config ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANG !! 1342 config ARC_MEMORY
910 bool 1343 bool
911 !! 1344 depends on MACH_JAZZ || SNI_RM || SGI_IP32
912 config ARM64_ERRATUM_2253138 <<
913 bool "Neoverse-N2: 2253138: workaround <<
914 depends on CORESIGHT_TRBE <<
915 default y 1345 default y
916 select ARM64_WORKAROUND_TRBE_WRITE_OUT <<
917 help <<
918 This option adds the workaround for <<
919 1346
920 Affected Neoverse-N2 cores might wri !! 1347 config ARC_PROMLIB
921 for TRBE. Under some conditions, the !! 1348 bool
922 virtually addressed page following t !! 1349 depends on MACH_JAZZ || SNI_RM || SGI_IP22 || SGI_IP28 || SGI_IP32
923 (i.e., the TRBLIMITR_EL1.LIMIT), ins <<
924 <<
925 Work around this in the driver by al <<
926 page beyond the TRBLIMITR_EL1.LIMIT, <<
927 <<
928 If unsure, say Y. <<
929 <<
930 config ARM64_ERRATUM_2224489 <<
931 bool "Cortex-A710/X2: 2224489: workaro <<
932 depends on CORESIGHT_TRBE <<
933 default y 1350 default y
934 select ARM64_WORKAROUND_TRBE_WRITE_OUT <<
935 help <<
936 This option adds the workaround for <<
937 1351
938 Affected Cortex-A710/X2 cores might !! 1352 config FW_ARC64
939 for TRBE. Under some conditions, the !! 1353 bool
940 virtually addressed page following t <<
941 (i.e., the TRBLIMITR_EL1.LIMIT), ins <<
942 <<
943 Work around this in the driver by al <<
944 page beyond the TRBLIMITR_EL1.LIMIT, <<
945 <<
946 If unsure, say Y. <<
947 1354
948 config ARM64_ERRATUM_2441009 !! 1355 config BOOT_ELF64
949 bool "Cortex-A510: Completion of affec !! 1356 bool
950 select ARM64_WORKAROUND_REPEAT_TLBI <<
951 help <<
952 This option adds a workaround for AR <<
953 <<
954 Under very rare circumstances, affec <<
955 may not handle a race between a brea <<
956 CPU, and another CPU accessing the s <<
957 store to a page that has been unmapp <<
958 1357
959 Work around this by adding the affec !! 1358 menu "CPU selection"
960 TLB sequences to be done twice. <<
961 1359
962 If unsure, say N. !! 1360 choice
>> 1361 prompt "CPU type"
>> 1362 default CPU_R4X00
963 1363
964 config ARM64_ERRATUM_2064142 !! 1364 config CPU_LOONGSON3
965 bool "Cortex-A510: 2064142: workaround !! 1365 bool "Loongson 3 CPU"
966 depends on CORESIGHT_TRBE !! 1366 depends on SYS_HAS_CPU_LOONGSON3
967 default y !! 1367 select CPU_SUPPORTS_64BIT_KERNEL
>> 1368 select CPU_SUPPORTS_HIGHMEM
>> 1369 select CPU_SUPPORTS_HUGEPAGES
>> 1370 select WEAK_ORDERING
>> 1371 select WEAK_REORDERING_BEYOND_LLSC
>> 1372 select MIPS_PGD_C0_CONTEXT
>> 1373 select MIPS_L1_CACHE_SHIFT_6
>> 1374 select GPIOLIB
968 help 1375 help
969 This option adds the workaround for !! 1376 The Loongson 3 processor implements the MIPS64R2 instruction
>> 1377 set with many extensions.
970 1378
971 Affected Cortex-A510 core might fail !! 1379 config LOONGSON3_ENHANCEMENT
972 TRBE has been disabled. Under some c !! 1380 bool "New Loongson 3 CPU Enhancements"
973 writes into TRBE registers TRBLIMITR !! 1381 default n
974 and TRBTRG_EL1 will be ignored and w !! 1382 select CPU_MIPSR2
975 !! 1383 select CPU_HAS_PREFETCH
976 Work around this in the driver by ex !! 1384 depends on CPU_LOONGSON3
977 is stopped and before performing a s !! 1385 help
978 registers. !! 1386 New Loongson 3 CPU (since Loongson-3A R2, as opposed to Loongson-3A
>> 1387 R1, Loongson-3B R1 and Loongson-3B R2) has many enhancements, such as
>> 1388 FTLB, L1-VCache, EI/DI/Wait/Prefetch instruction, DSP/DSPv2 ASE, User
>> 1389 Local register, Read-Inhibit/Execute-Inhibit, SFB (Store Fill Buffer),
>> 1390 Fast TLB refill support, etc.
>> 1391
>> 1392 This option enable those enhancements which are not probed at run
>> 1393 time. If you want a generic kernel to run on all Loongson 3 machines,
>> 1394 please say 'N' here. If you want a high-performance kernel to run on
>> 1395 new Loongson 3 machines only, please say 'Y' here.
>> 1396
>> 1397 config CPU_LOONGSON2E
>> 1398 bool "Loongson 2E"
>> 1399 depends on SYS_HAS_CPU_LOONGSON2E
>> 1400 select CPU_LOONGSON2
>> 1401 help
>> 1402 The Loongson 2E processor implements the MIPS III instruction set
>> 1403 with many extensions.
>> 1404
>> 1405 It has an internal FPGA northbridge, which is compatible to
>> 1406 bonito64.
>> 1407
>> 1408 config CPU_LOONGSON2F
>> 1409 bool "Loongson 2F"
>> 1410 depends on SYS_HAS_CPU_LOONGSON2F
>> 1411 select CPU_LOONGSON2
>> 1412 select GPIOLIB
>> 1413 help
>> 1414 The Loongson 2F processor implements the MIPS III instruction set
>> 1415 with many extensions.
>> 1416
>> 1417 Loongson2F have built-in DDR2 and PCIX controller. The PCIX controller
>> 1418 have a similar programming interface with FPGA northbridge used in
>> 1419 Loongson2E.
>> 1420
>> 1421 config CPU_LOONGSON1B
>> 1422 bool "Loongson 1B"
>> 1423 depends on SYS_HAS_CPU_LOONGSON1B
>> 1424 select CPU_LOONGSON1
>> 1425 select LEDS_GPIO_REGISTER
>> 1426 help
>> 1427 The Loongson 1B is a 32-bit SoC, which implements the MIPS32
>> 1428 release 2 instruction set.
>> 1429
>> 1430 config CPU_LOONGSON1C
>> 1431 bool "Loongson 1C"
>> 1432 depends on SYS_HAS_CPU_LOONGSON1C
>> 1433 select CPU_LOONGSON1
>> 1434 select LEDS_GPIO_REGISTER
>> 1435 help
>> 1436 The Loongson 1C is a 32-bit SoC, which implements the MIPS32
>> 1437 release 2 instruction set.
>> 1438
>> 1439 config CPU_MIPS32_R1
>> 1440 bool "MIPS32 Release 1"
>> 1441 depends on SYS_HAS_CPU_MIPS32_R1
>> 1442 select CPU_HAS_PREFETCH
>> 1443 select CPU_SUPPORTS_32BIT_KERNEL
>> 1444 select CPU_SUPPORTS_HIGHMEM
>> 1445 help
>> 1446 Choose this option to build a kernel for release 1 or later of the
>> 1447 MIPS32 architecture. Most modern embedded systems with a 32-bit
>> 1448 MIPS processor are based on a MIPS32 processor. If you know the
>> 1449 specific type of processor in your system, choose those that one
>> 1450 otherwise CPU_MIPS32_R1 is a safe bet for any MIPS32 system.
>> 1451 Release 2 of the MIPS32 architecture is available since several
>> 1452 years so chances are you even have a MIPS32 Release 2 processor
>> 1453 in which case you should choose CPU_MIPS32_R2 instead for better
>> 1454 performance.
>> 1455
>> 1456 config CPU_MIPS32_R2
>> 1457 bool "MIPS32 Release 2"
>> 1458 depends on SYS_HAS_CPU_MIPS32_R2
>> 1459 select CPU_HAS_PREFETCH
>> 1460 select CPU_SUPPORTS_32BIT_KERNEL
>> 1461 select CPU_SUPPORTS_HIGHMEM
>> 1462 select CPU_SUPPORTS_MSA
>> 1463 select HAVE_KVM
>> 1464 help
>> 1465 Choose this option to build a kernel for release 2 or later of the
>> 1466 MIPS32 architecture. Most modern embedded systems with a 32-bit
>> 1467 MIPS processor are based on a MIPS32 processor. If you know the
>> 1468 specific type of processor in your system, choose those that one
>> 1469 otherwise CPU_MIPS32_R1 is a safe bet for any MIPS32 system.
>> 1470
>> 1471 config CPU_MIPS32_R6
>> 1472 bool "MIPS32 Release 6"
>> 1473 depends on SYS_HAS_CPU_MIPS32_R6
>> 1474 select CPU_HAS_PREFETCH
>> 1475 select CPU_SUPPORTS_32BIT_KERNEL
>> 1476 select CPU_SUPPORTS_HIGHMEM
>> 1477 select CPU_SUPPORTS_MSA
>> 1478 select GENERIC_CSUM
>> 1479 select HAVE_KVM
>> 1480 select MIPS_O32_FP64_SUPPORT
>> 1481 help
>> 1482 Choose this option to build a kernel for release 6 or later of the
>> 1483 MIPS32 architecture. New MIPS processors, starting with the Warrior
>> 1484 family, are based on a MIPS32r6 processor. If you own an older
>> 1485 processor, you probably need to select MIPS32r1 or MIPS32r2 instead.
>> 1486
>> 1487 config CPU_MIPS64_R1
>> 1488 bool "MIPS64 Release 1"
>> 1489 depends on SYS_HAS_CPU_MIPS64_R1
>> 1490 select CPU_HAS_PREFETCH
>> 1491 select CPU_SUPPORTS_32BIT_KERNEL
>> 1492 select CPU_SUPPORTS_64BIT_KERNEL
>> 1493 select CPU_SUPPORTS_HIGHMEM
>> 1494 select CPU_SUPPORTS_HUGEPAGES
>> 1495 help
>> 1496 Choose this option to build a kernel for release 1 or later of the
>> 1497 MIPS64 architecture. Many modern embedded systems with a 64-bit
>> 1498 MIPS processor are based on a MIPS64 processor. If you know the
>> 1499 specific type of processor in your system, choose those that one
>> 1500 otherwise CPU_MIPS64_R1 is a safe bet for any MIPS64 system.
>> 1501 Release 2 of the MIPS64 architecture is available since several
>> 1502 years so chances are you even have a MIPS64 Release 2 processor
>> 1503 in which case you should choose CPU_MIPS64_R2 instead for better
>> 1504 performance.
>> 1505
>> 1506 config CPU_MIPS64_R2
>> 1507 bool "MIPS64 Release 2"
>> 1508 depends on SYS_HAS_CPU_MIPS64_R2
>> 1509 select CPU_HAS_PREFETCH
>> 1510 select CPU_SUPPORTS_32BIT_KERNEL
>> 1511 select CPU_SUPPORTS_64BIT_KERNEL
>> 1512 select CPU_SUPPORTS_HIGHMEM
>> 1513 select CPU_SUPPORTS_HUGEPAGES
>> 1514 select CPU_SUPPORTS_MSA
>> 1515 select HAVE_KVM
>> 1516 help
>> 1517 Choose this option to build a kernel for release 2 or later of the
>> 1518 MIPS64 architecture. Many modern embedded systems with a 64-bit
>> 1519 MIPS processor are based on a MIPS64 processor. If you know the
>> 1520 specific type of processor in your system, choose those that one
>> 1521 otherwise CPU_MIPS64_R1 is a safe bet for any MIPS64 system.
>> 1522
>> 1523 config CPU_MIPS64_R6
>> 1524 bool "MIPS64 Release 6"
>> 1525 depends on SYS_HAS_CPU_MIPS64_R6
>> 1526 select CPU_HAS_PREFETCH
>> 1527 select CPU_SUPPORTS_32BIT_KERNEL
>> 1528 select CPU_SUPPORTS_64BIT_KERNEL
>> 1529 select CPU_SUPPORTS_HIGHMEM
>> 1530 select CPU_SUPPORTS_MSA
>> 1531 select GENERIC_CSUM
>> 1532 select MIPS_O32_FP64_SUPPORT if 32BIT || MIPS32_O32
>> 1533 select HAVE_KVM
>> 1534 help
>> 1535 Choose this option to build a kernel for release 6 or later of the
>> 1536 MIPS64 architecture. New MIPS processors, starting with the Warrior
>> 1537 family, are based on a MIPS64r6 processor. If you own an older
>> 1538 processor, you probably need to select MIPS64r1 or MIPS64r2 instead.
>> 1539
>> 1540 config CPU_R3000
>> 1541 bool "R3000"
>> 1542 depends on SYS_HAS_CPU_R3000
>> 1543 select CPU_HAS_WB
>> 1544 select CPU_SUPPORTS_32BIT_KERNEL
>> 1545 select CPU_SUPPORTS_HIGHMEM
>> 1546 help
>> 1547 Please make sure to pick the right CPU type. Linux/MIPS is not
>> 1548 designed to be generic, i.e. Kernels compiled for R3000 CPUs will
>> 1549 *not* work on R4000 machines and vice versa. However, since most
>> 1550 of the supported machines have an R4000 (or similar) CPU, R4x00
>> 1551 might be a safe bet. If the resulting kernel does not work,
>> 1552 try to recompile with R3000.
>> 1553
>> 1554 config CPU_TX39XX
>> 1555 bool "R39XX"
>> 1556 depends on SYS_HAS_CPU_TX39XX
>> 1557 select CPU_SUPPORTS_32BIT_KERNEL
>> 1558
>> 1559 config CPU_VR41XX
>> 1560 bool "R41xx"
>> 1561 depends on SYS_HAS_CPU_VR41XX
>> 1562 select CPU_SUPPORTS_32BIT_KERNEL
>> 1563 select CPU_SUPPORTS_64BIT_KERNEL
>> 1564 help
>> 1565 The options selects support for the NEC VR4100 series of processors.
>> 1566 Only choose this option if you have one of these processors as a
>> 1567 kernel built with this option will not run on any other type of
>> 1568 processor or vice versa.
>> 1569
>> 1570 config CPU_R4300
>> 1571 bool "R4300"
>> 1572 depends on SYS_HAS_CPU_R4300
>> 1573 select CPU_SUPPORTS_32BIT_KERNEL
>> 1574 select CPU_SUPPORTS_64BIT_KERNEL
>> 1575 help
>> 1576 MIPS Technologies R4300-series processors.
>> 1577
>> 1578 config CPU_R4X00
>> 1579 bool "R4x00"
>> 1580 depends on SYS_HAS_CPU_R4X00
>> 1581 select CPU_SUPPORTS_32BIT_KERNEL
>> 1582 select CPU_SUPPORTS_64BIT_KERNEL
>> 1583 select CPU_SUPPORTS_HUGEPAGES
>> 1584 help
>> 1585 MIPS Technologies R4000-series processors other than 4300, including
>> 1586 the R4000, R4400, R4600, and 4700.
>> 1587
>> 1588 config CPU_TX49XX
>> 1589 bool "R49XX"
>> 1590 depends on SYS_HAS_CPU_TX49XX
>> 1591 select CPU_HAS_PREFETCH
>> 1592 select CPU_SUPPORTS_32BIT_KERNEL
>> 1593 select CPU_SUPPORTS_64BIT_KERNEL
>> 1594 select CPU_SUPPORTS_HUGEPAGES
>> 1595
>> 1596 config CPU_R5000
>> 1597 bool "R5000"
>> 1598 depends on SYS_HAS_CPU_R5000
>> 1599 select CPU_SUPPORTS_32BIT_KERNEL
>> 1600 select CPU_SUPPORTS_64BIT_KERNEL
>> 1601 select CPU_SUPPORTS_HUGEPAGES
>> 1602 help
>> 1603 MIPS Technologies R5000-series processors other than the Nevada.
>> 1604
>> 1605 config CPU_R5432
>> 1606 bool "R5432"
>> 1607 depends on SYS_HAS_CPU_R5432
>> 1608 select CPU_SUPPORTS_32BIT_KERNEL
>> 1609 select CPU_SUPPORTS_64BIT_KERNEL
>> 1610 select CPU_SUPPORTS_HUGEPAGES
>> 1611
>> 1612 config CPU_R5500
>> 1613 bool "R5500"
>> 1614 depends on SYS_HAS_CPU_R5500
>> 1615 select CPU_SUPPORTS_32BIT_KERNEL
>> 1616 select CPU_SUPPORTS_64BIT_KERNEL
>> 1617 select CPU_SUPPORTS_HUGEPAGES
>> 1618 help
>> 1619 NEC VR5500 and VR5500A series processors implement 64-bit MIPS IV
>> 1620 instruction set.
>> 1621
>> 1622 config CPU_NEVADA
>> 1623 bool "RM52xx"
>> 1624 depends on SYS_HAS_CPU_NEVADA
>> 1625 select CPU_SUPPORTS_32BIT_KERNEL
>> 1626 select CPU_SUPPORTS_64BIT_KERNEL
>> 1627 select CPU_SUPPORTS_HUGEPAGES
>> 1628 help
>> 1629 QED / PMC-Sierra RM52xx-series ("Nevada") processors.
>> 1630
>> 1631 config CPU_R8000
>> 1632 bool "R8000"
>> 1633 depends on SYS_HAS_CPU_R8000
>> 1634 select CPU_HAS_PREFETCH
>> 1635 select CPU_SUPPORTS_64BIT_KERNEL
>> 1636 help
>> 1637 MIPS Technologies R8000 processors. Note these processors are
>> 1638 uncommon and the support for them is incomplete.
>> 1639
>> 1640 config CPU_R10000
>> 1641 bool "R10000"
>> 1642 depends on SYS_HAS_CPU_R10000
>> 1643 select CPU_HAS_PREFETCH
>> 1644 select CPU_SUPPORTS_32BIT_KERNEL
>> 1645 select CPU_SUPPORTS_64BIT_KERNEL
>> 1646 select CPU_SUPPORTS_HIGHMEM
>> 1647 select CPU_SUPPORTS_HUGEPAGES
>> 1648 help
>> 1649 MIPS Technologies R10000-series processors.
>> 1650
>> 1651 config CPU_RM7000
>> 1652 bool "RM7000"
>> 1653 depends on SYS_HAS_CPU_RM7000
>> 1654 select CPU_HAS_PREFETCH
>> 1655 select CPU_SUPPORTS_32BIT_KERNEL
>> 1656 select CPU_SUPPORTS_64BIT_KERNEL
>> 1657 select CPU_SUPPORTS_HIGHMEM
>> 1658 select CPU_SUPPORTS_HUGEPAGES
>> 1659
>> 1660 config CPU_SB1
>> 1661 bool "SB1"
>> 1662 depends on SYS_HAS_CPU_SB1
>> 1663 select CPU_SUPPORTS_32BIT_KERNEL
>> 1664 select CPU_SUPPORTS_64BIT_KERNEL
>> 1665 select CPU_SUPPORTS_HIGHMEM
>> 1666 select CPU_SUPPORTS_HUGEPAGES
>> 1667 select WEAK_ORDERING
>> 1668
>> 1669 config CPU_CAVIUM_OCTEON
>> 1670 bool "Cavium Octeon processor"
>> 1671 depends on SYS_HAS_CPU_CAVIUM_OCTEON
>> 1672 select CPU_HAS_PREFETCH
>> 1673 select CPU_SUPPORTS_64BIT_KERNEL
>> 1674 select WEAK_ORDERING
>> 1675 select CPU_SUPPORTS_HIGHMEM
>> 1676 select CPU_SUPPORTS_HUGEPAGES
>> 1677 select USB_EHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 1678 select USB_OHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 1679 select MIPS_L1_CACHE_SHIFT_7
>> 1680 select HAVE_KVM
>> 1681 help
>> 1682 The Cavium Octeon processor is a highly integrated chip containing
>> 1683 many ethernet hardware widgets for networking tasks. The processor
>> 1684 can have up to 16 Mips64v2 cores and 8 integrated gigabit ethernets.
>> 1685 Full details can be found at http://www.caviumnetworks.com.
>> 1686
>> 1687 config CPU_BMIPS
>> 1688 bool "Broadcom BMIPS"
>> 1689 depends on SYS_HAS_CPU_BMIPS
>> 1690 select CPU_MIPS32
>> 1691 select CPU_BMIPS32_3300 if SYS_HAS_CPU_BMIPS32_3300
>> 1692 select CPU_BMIPS4350 if SYS_HAS_CPU_BMIPS4350
>> 1693 select CPU_BMIPS4380 if SYS_HAS_CPU_BMIPS4380
>> 1694 select CPU_BMIPS5000 if SYS_HAS_CPU_BMIPS5000
>> 1695 select CPU_SUPPORTS_32BIT_KERNEL
>> 1696 select DMA_NONCOHERENT
>> 1697 select IRQ_MIPS_CPU
>> 1698 select SWAP_IO_SPACE
>> 1699 select WEAK_ORDERING
>> 1700 select CPU_SUPPORTS_HIGHMEM
>> 1701 select CPU_HAS_PREFETCH
>> 1702 select CPU_SUPPORTS_CPUFREQ
>> 1703 select MIPS_EXTERNAL_TIMER
>> 1704 help
>> 1705 Support for BMIPS32/3300/4350/4380 and BMIPS5000 processors.
>> 1706
>> 1707 config CPU_XLR
>> 1708 bool "Netlogic XLR SoC"
>> 1709 depends on SYS_HAS_CPU_XLR
>> 1710 select CPU_SUPPORTS_32BIT_KERNEL
>> 1711 select CPU_SUPPORTS_64BIT_KERNEL
>> 1712 select CPU_SUPPORTS_HIGHMEM
>> 1713 select CPU_SUPPORTS_HUGEPAGES
>> 1714 select WEAK_ORDERING
>> 1715 select WEAK_REORDERING_BEYOND_LLSC
>> 1716 help
>> 1717 Netlogic Microsystems XLR/XLS processors.
>> 1718
>> 1719 config CPU_XLP
>> 1720 bool "Netlogic XLP SoC"
>> 1721 depends on SYS_HAS_CPU_XLP
>> 1722 select CPU_SUPPORTS_32BIT_KERNEL
>> 1723 select CPU_SUPPORTS_64BIT_KERNEL
>> 1724 select CPU_SUPPORTS_HIGHMEM
>> 1725 select WEAK_ORDERING
>> 1726 select WEAK_REORDERING_BEYOND_LLSC
>> 1727 select CPU_HAS_PREFETCH
>> 1728 select CPU_MIPSR2
>> 1729 select CPU_SUPPORTS_HUGEPAGES
>> 1730 select MIPS_ASID_BITS_VARIABLE
>> 1731 help
>> 1732 Netlogic Microsystems XLP processors.
>> 1733 endchoice
979 1734
980 If unsure, say Y. !! 1735 config CPU_MIPS32_3_5_FEATURES
>> 1736 bool "MIPS32 Release 3.5 Features"
>> 1737 depends on SYS_HAS_CPU_MIPS32_R3_5
>> 1738 depends on CPU_MIPS32_R2 || CPU_MIPS32_R6
>> 1739 help
>> 1740 Choose this option to build a kernel for release 2 or later of the
>> 1741 MIPS32 architecture including features from the 3.5 release such as
>> 1742 support for Enhanced Virtual Addressing (EVA).
>> 1743
>> 1744 config CPU_MIPS32_3_5_EVA
>> 1745 bool "Enhanced Virtual Addressing (EVA)"
>> 1746 depends on CPU_MIPS32_3_5_FEATURES
>> 1747 select EVA
>> 1748 default y
>> 1749 help
>> 1750 Choose this option if you want to enable the Enhanced Virtual
>> 1751 Addressing (EVA) on your MIPS32 core (such as proAptiv).
>> 1752 One of its primary benefits is an increase in the maximum size
>> 1753 of lowmem (up to 3GB). If unsure, say 'N' here.
>> 1754
>> 1755 config CPU_MIPS32_R5_FEATURES
>> 1756 bool "MIPS32 Release 5 Features"
>> 1757 depends on SYS_HAS_CPU_MIPS32_R5
>> 1758 depends on CPU_MIPS32_R2
>> 1759 help
>> 1760 Choose this option to build a kernel for release 2 or later of the
>> 1761 MIPS32 architecture including features from release 5 such as
>> 1762 support for Extended Physical Addressing (XPA).
>> 1763
>> 1764 config CPU_MIPS32_R5_XPA
>> 1765 bool "Extended Physical Addressing (XPA)"
>> 1766 depends on CPU_MIPS32_R5_FEATURES
>> 1767 depends on !EVA
>> 1768 depends on !PAGE_SIZE_4KB
>> 1769 depends on SYS_SUPPORTS_HIGHMEM
>> 1770 select XPA
>> 1771 select HIGHMEM
>> 1772 select ARCH_PHYS_ADDR_T_64BIT
>> 1773 default n
>> 1774 help
>> 1775 Choose this option if you want to enable the Extended Physical
>> 1776 Addressing (XPA) on your MIPS32 core (such as P5600 series). The
>> 1777 benefit is to increase physical addressing equal to or greater
>> 1778 than 40 bits. Note that this has the side effect of turning on
>> 1779 64-bit addressing which in turn makes the PTEs 64-bit in size.
>> 1780 If unsure, say 'N' here.
981 1781
982 config ARM64_ERRATUM_2038923 !! 1782 if CPU_LOONGSON2F
983 bool "Cortex-A510: 2038923: workaround !! 1783 config CPU_NOP_WORKAROUNDS
984 depends on CORESIGHT_TRBE !! 1784 bool
985 default y <<
986 help <<
987 This option adds the workaround for <<
988 <<
989 Affected Cortex-A510 core might caus <<
990 prohibited within the CPU. As a resu <<
991 might be corrupted. This happens aft <<
992 TRBLIMITR_EL1.E, followed by just a <<
993 execution changes from a context, in <<
994 isn't, or vice versa. In these menti <<
995 is prohibited is inconsistent betwee <<
996 the trace buffer state might be corr <<
997 <<
998 Work around this in the driver by pr <<
999 trace is prohibited or not based on <<
1000 change to TRBLIMITR_EL1.E with at l <<
1001 two ISB instructions if no ERET is <<
1002 1785
1003 If unsure, say Y. !! 1786 config CPU_JUMP_WORKAROUNDS
>> 1787 bool
1004 1788
1005 config ARM64_ERRATUM_1902691 !! 1789 config CPU_LOONGSON2F_WORKAROUNDS
1006 bool "Cortex-A510: 1902691: workaroun !! 1790 bool "Loongson 2F Workarounds"
1007 depends on CORESIGHT_TRBE <<
1008 default y 1791 default y
>> 1792 select CPU_NOP_WORKAROUNDS
>> 1793 select CPU_JUMP_WORKAROUNDS
1009 help 1794 help
1010 This option adds the workaround for !! 1795 Loongson 2F01 / 2F02 processors have the NOP & JUMP issues which
>> 1796 require workarounds. Without workarounds the system may hang
>> 1797 unexpectedly. For more information please refer to the gas
>> 1798 -mfix-loongson2f-nop and -mfix-loongson2f-jump options.
>> 1799
>> 1800 Loongson 2F03 and later have fixed these issues and no workarounds
>> 1801 are needed. The workarounds have no significant side effect on them
>> 1802 but may decrease the performance of the system so this option should
>> 1803 be disabled unless the kernel is intended to be run on 2F01 or 2F02
>> 1804 systems.
1011 1805
1012 Affected Cortex-A510 core might cau !! 1806 If unsure, please say Y.
1013 into the memory. Effectively TRBE i !! 1807 endif # CPU_LOONGSON2F
1014 trace data. <<
1015 1808
1016 Work around this problem in the dri !! 1809 config SYS_SUPPORTS_ZBOOT
1017 affected cpus. The firmware must ha !! 1810 bool
1018 on such implementations. This will !! 1811 select HAVE_KERNEL_GZIP
1019 do this already. !! 1812 select HAVE_KERNEL_BZIP2
>> 1813 select HAVE_KERNEL_LZ4
>> 1814 select HAVE_KERNEL_LZMA
>> 1815 select HAVE_KERNEL_LZO
>> 1816 select HAVE_KERNEL_XZ
1020 1817
1021 If unsure, say Y. !! 1818 config SYS_SUPPORTS_ZBOOT_UART16550
>> 1819 bool
>> 1820 select SYS_SUPPORTS_ZBOOT
1022 1821
1023 config ARM64_ERRATUM_2457168 !! 1822 config SYS_SUPPORTS_ZBOOT_UART_PROM
1024 bool "Cortex-A510: 2457168: workaroun !! 1823 bool
1025 depends on ARM64_AMU_EXTN !! 1824 select SYS_SUPPORTS_ZBOOT
1026 default y <<
1027 help <<
1028 This option adds the workaround for <<
1029 1825
1030 The AMU counter AMEVCNTR01 (constan !! 1826 config CPU_LOONGSON2
1031 as the system counter. On affected !! 1827 bool
1032 incorrectly giving a significantly !! 1828 select CPU_SUPPORTS_32BIT_KERNEL
>> 1829 select CPU_SUPPORTS_64BIT_KERNEL
>> 1830 select CPU_SUPPORTS_HIGHMEM
>> 1831 select CPU_SUPPORTS_HUGEPAGES
1033 1832
1034 Work around this problem by returni !! 1833 config CPU_LOONGSON1
1035 key locations that results in disab !! 1834 bool
1036 is the same to firmware disabling a !! 1835 select CPU_MIPS32
>> 1836 select CPU_MIPSR2
>> 1837 select CPU_HAS_PREFETCH
>> 1838 select CPU_SUPPORTS_32BIT_KERNEL
>> 1839 select CPU_SUPPORTS_HIGHMEM
>> 1840 select CPU_SUPPORTS_CPUFREQ
1037 1841
1038 If unsure, say Y. !! 1842 config CPU_BMIPS32_3300
>> 1843 select SMP_UP if SMP
>> 1844 bool
1039 1845
1040 config ARM64_ERRATUM_2645198 !! 1846 config CPU_BMIPS4350
1041 bool "Cortex-A715: 2645198: Workaroun !! 1847 bool
1042 default y !! 1848 select SYS_SUPPORTS_SMP
1043 help !! 1849 select SYS_SUPPORTS_HOTPLUG_CPU
1044 This option adds the workaround for <<
1045 1850
1046 If a Cortex-A715 cpu sees a page ma !! 1851 config CPU_BMIPS4380
1047 to non-executable, it may corrupt t !! 1852 bool
1048 next instruction abort caused by pe !! 1853 select MIPS_L1_CACHE_SHIFT_6
>> 1854 select SYS_SUPPORTS_SMP
>> 1855 select SYS_SUPPORTS_HOTPLUG_CPU
>> 1856 select CPU_HAS_RIXI
1049 1857
1050 Only user-space does executable to !! 1858 config CPU_BMIPS5000
1051 mprotect() system call. Workaround !! 1859 bool
1052 TLB invalidation, for all changes t !! 1860 select MIPS_CPU_SCACHE
>> 1861 select MIPS_L1_CACHE_SHIFT_7
>> 1862 select SYS_SUPPORTS_SMP
>> 1863 select SYS_SUPPORTS_HOTPLUG_CPU
>> 1864 select CPU_HAS_RIXI
1053 1865
1054 If unsure, say Y. !! 1866 config SYS_HAS_CPU_LOONGSON3
>> 1867 bool
>> 1868 select CPU_SUPPORTS_CPUFREQ
>> 1869 select CPU_HAS_RIXI
1055 1870
1056 config ARM64_WORKAROUND_SPECULATIVE_UNPRIV_LO !! 1871 config SYS_HAS_CPU_LOONGSON2E
1057 bool 1872 bool
1058 1873
1059 config ARM64_ERRATUM_2966298 !! 1874 config SYS_HAS_CPU_LOONGSON2F
1060 bool "Cortex-A520: 2966298: workaroun !! 1875 bool
1061 select ARM64_WORKAROUND_SPECULATIVE_U !! 1876 select CPU_SUPPORTS_CPUFREQ
1062 default y !! 1877 select CPU_SUPPORTS_ADDRWINCFG if 64BIT
1063 help !! 1878 select CPU_SUPPORTS_UNCACHED_ACCELERATED
1064 This option adds the workaround for <<
1065 1879
1066 On an affected Cortex-A520 core, a !! 1880 config SYS_HAS_CPU_LOONGSON1B
1067 load might leak data from a privile !! 1881 bool
1068 1882
1069 Work around this problem by executi !! 1883 config SYS_HAS_CPU_LOONGSON1C
>> 1884 bool
1070 1885
1071 If unsure, say Y. !! 1886 config SYS_HAS_CPU_MIPS32_R1
>> 1887 bool
1072 1888
1073 config ARM64_ERRATUM_3117295 !! 1889 config SYS_HAS_CPU_MIPS32_R2
1074 bool "Cortex-A510: 3117295: workaroun !! 1890 bool
1075 select ARM64_WORKAROUND_SPECULATIVE_U <<
1076 default y <<
1077 help <<
1078 This option adds the workaround for <<
1079 1891
1080 On an affected Cortex-A510 core, a !! 1892 config SYS_HAS_CPU_MIPS32_R3_5
1081 load might leak data from a privile !! 1893 bool
1082 1894
1083 Work around this problem by executi !! 1895 config SYS_HAS_CPU_MIPS32_R5
>> 1896 bool
1084 1897
1085 If unsure, say Y. !! 1898 config SYS_HAS_CPU_MIPS32_R6
>> 1899 bool
1086 1900
1087 config ARM64_ERRATUM_3194386 !! 1901 config SYS_HAS_CPU_MIPS64_R1
1088 bool "Cortex-*/Neoverse-*: workaround !! 1902 bool
1089 default y <<
1090 help <<
1091 This option adds the workaround for <<
1092 1903
1093 * ARM Cortex-A76 erratum 3324349 !! 1904 config SYS_HAS_CPU_MIPS64_R2
1094 * ARM Cortex-A77 erratum 3324348 !! 1905 bool
1095 * ARM Cortex-A78 erratum 3324344 <<
1096 * ARM Cortex-A78C erratum 3324346 <<
1097 * ARM Cortex-A78C erratum 3324347 <<
1098 * ARM Cortex-A710 erratam 3324338 <<
1099 * ARM Cortex-A715 errartum 3456084 <<
1100 * ARM Cortex-A720 erratum 3456091 <<
1101 * ARM Cortex-A725 erratum 3456106 <<
1102 * ARM Cortex-X1 erratum 3324344 <<
1103 * ARM Cortex-X1C erratum 3324346 <<
1104 * ARM Cortex-X2 erratum 3324338 <<
1105 * ARM Cortex-X3 erratum 3324335 <<
1106 * ARM Cortex-X4 erratum 3194386 <<
1107 * ARM Cortex-X925 erratum 3324334 <<
1108 * ARM Neoverse-N1 erratum 3324349 <<
1109 * ARM Neoverse N2 erratum 3324339 <<
1110 * ARM Neoverse-N3 erratum 3456111 <<
1111 * ARM Neoverse-V1 erratum 3324341 <<
1112 * ARM Neoverse V2 erratum 3324336 <<
1113 * ARM Neoverse-V3 erratum 3312417 <<
1114 <<
1115 On affected cores "MSR SSBS, #0" in <<
1116 subsequent speculative instructions <<
1117 speculative store bypassing. <<
1118 <<
1119 Work around this problem by placing <<
1120 Instruction Synchronization Barrier <<
1121 SSBS. The presence of the SSBS spec <<
1122 from hwcaps and EL0 reads of ID_AA6 <<
1123 will use the PR_SPEC_STORE_BYPASS p <<
1124 1906
1125 If unsure, say Y. !! 1907 config SYS_HAS_CPU_MIPS64_R6
>> 1908 bool
1126 1909
1127 config CAVIUM_ERRATUM_22375 !! 1910 config SYS_HAS_CPU_R3000
1128 bool "Cavium erratum 22375, 24313" !! 1911 bool
1129 default y <<
1130 help <<
1131 Enable workaround for errata 22375 <<
1132 1912
1133 This implements two gicv3-its errat !! 1913 config SYS_HAS_CPU_TX39XX
1134 with a small impact affecting only !! 1914 bool
1135 1915
1136 erratum 22375: only alloc 8MB tab !! 1916 config SYS_HAS_CPU_VR41XX
1137 erratum 24313: ignore memory acce !! 1917 bool
1138 1918
1139 The fixes are in ITS initialization !! 1919 config SYS_HAS_CPU_R4300
1140 type and table size provided by the !! 1920 bool
1141 1921
1142 If unsure, say Y. !! 1922 config SYS_HAS_CPU_R4X00
>> 1923 bool
1143 1924
1144 config CAVIUM_ERRATUM_23144 !! 1925 config SYS_HAS_CPU_TX49XX
1145 bool "Cavium erratum 23144: ITS SYNC !! 1926 bool
1146 depends on NUMA <<
1147 default y <<
1148 help <<
1149 ITS SYNC command hang for cross nod <<
1150 1927
1151 If unsure, say Y. !! 1928 config SYS_HAS_CPU_R5000
>> 1929 bool
1152 1930
1153 config CAVIUM_ERRATUM_23154 !! 1931 config SYS_HAS_CPU_R5432
1154 bool "Cavium errata 23154 and 38545: !! 1932 bool
1155 default y <<
1156 help <<
1157 The ThunderX GICv3 implementation r <<
1158 reading the IAR status to ensure da <<
1159 (access to icc_iar1_el1 is not sync <<
1160 1933
1161 It also suffers from erratum 38545 !! 1934 config SYS_HAS_CPU_R5500
1162 OcteonTX and OcteonTX2), resulting !! 1935 bool
1163 spuriously presented to the CPU int <<
1164 1936
1165 If unsure, say Y. !! 1937 config SYS_HAS_CPU_NEVADA
>> 1938 bool
1166 1939
1167 config CAVIUM_ERRATUM_27456 !! 1940 config SYS_HAS_CPU_R8000
1168 bool "Cavium erratum 27456: Broadcast !! 1941 bool
1169 default y <<
1170 help <<
1171 On ThunderX T88 pass 1.x through 2. <<
1172 instructions may cause the icache t <<
1173 contains data for a non-current ASI <<
1174 invalidate the icache when changing <<
1175 1942
1176 If unsure, say Y. !! 1943 config SYS_HAS_CPU_R10000
>> 1944 bool
1177 1945
1178 config CAVIUM_ERRATUM_30115 !! 1946 config SYS_HAS_CPU_RM7000
1179 bool "Cavium erratum 30115: Guest may !! 1947 bool
1180 default y <<
1181 help <<
1182 On ThunderX T88 pass 1.x through 2. <<
1183 1.2, and T83 Pass 1.0, KVM guest ex <<
1184 interrupts in host. Trapping both G <<
1185 accesses sidesteps the issue. <<
1186 1948
1187 If unsure, say Y. !! 1949 config SYS_HAS_CPU_SB1
>> 1950 bool
1188 1951
1189 config CAVIUM_TX2_ERRATUM_219 !! 1952 config SYS_HAS_CPU_CAVIUM_OCTEON
1190 bool "Cavium ThunderX2 erratum 219: P !! 1953 bool
1191 default y <<
1192 help <<
1193 On Cavium ThunderX2, a load, store <<
1194 TTBR update and the corresponding c <<
1195 cause a spurious Data Abort to be d <<
1196 the CPU core. <<
1197 <<
1198 Work around the issue by avoiding t <<
1199 trapping KVM guest TTBRx_EL1 writes <<
1200 trap handler performs the correspon <<
1201 instruction and ensures context syn <<
1202 exception return. <<
1203 1954
1204 If unsure, say Y. !! 1955 config SYS_HAS_CPU_BMIPS
>> 1956 bool
1205 1957
1206 config FUJITSU_ERRATUM_010001 !! 1958 config SYS_HAS_CPU_BMIPS32_3300
1207 bool "Fujitsu-A64FX erratum E#010001: !! 1959 bool
1208 default y !! 1960 select SYS_HAS_CPU_BMIPS
1209 help <<
1210 This option adds a workaround for F <<
1211 On some variants of the Fujitsu-A64 <<
1212 accesses may cause undefined fault <<
1213 This fault occurs under a specific <<
1214 load/store instruction performs an <<
1215 case-1 TTBR0_EL1 with TCR_EL1.NFD0 <<
1216 case-2 TTBR0_EL2 with TCR_EL2.NFD0 <<
1217 case-3 TTBR1_EL1 with TCR_EL1.NFD1 <<
1218 case-4 TTBR1_EL2 with TCR_EL2.NFD1 <<
1219 1961
1220 The workaround is to ensure these b !! 1962 config SYS_HAS_CPU_BMIPS4350
1221 The workaround only affects the Fuj !! 1963 bool
>> 1964 select SYS_HAS_CPU_BMIPS
1222 1965
1223 If unsure, say Y. !! 1966 config SYS_HAS_CPU_BMIPS4380
>> 1967 bool
>> 1968 select SYS_HAS_CPU_BMIPS
1224 1969
1225 config HISILICON_ERRATUM_161600802 !! 1970 config SYS_HAS_CPU_BMIPS5000
1226 bool "Hip07 161600802: Erroneous redi !! 1971 bool
1227 default y !! 1972 select SYS_HAS_CPU_BMIPS
1228 help <<
1229 The HiSilicon Hip07 SoC uses the wr <<
1230 when issued ITS commands such as VM <<
1231 a 128kB offset to be applied to the <<
1232 1973
1233 If unsure, say Y. !! 1974 config SYS_HAS_CPU_XLR
>> 1975 bool
1234 1976
1235 config QCOM_FALKOR_ERRATUM_1003 !! 1977 config SYS_HAS_CPU_XLP
1236 bool "Falkor E1003: Incorrect transla !! 1978 bool
1237 default y <<
1238 help <<
1239 On Falkor v1, an incorrect ASID may <<
1240 and BADDR are changed together in T <<
1241 in TTBR1_EL1, this situation only o <<
1242 then only for entries in the walk c <<
1243 is unchanged. Work around the errat <<
1244 entries for the trampoline before e <<
1245 1979
1246 config QCOM_FALKOR_ERRATUM_1009 !! 1980 config MIPS_MALTA_PM
1247 bool "Falkor E1009: Prematurely compl !! 1981 depends on MIPS_MALTA
>> 1982 depends on PCI
>> 1983 bool
1248 default y 1984 default y
1249 select ARM64_WORKAROUND_REPEAT_TLBI <<
1250 help <<
1251 On Falkor v1, the CPU may premature <<
1252 TLBI xxIS invalidate maintenance op <<
1253 one more time to fix the issue. <<
1254 1985
1255 If unsure, say Y. !! 1986 #
>> 1987 # CPU may reorder R->R, R->W, W->R, W->W
>> 1988 # Reordering beyond LL and SC is handled in WEAK_REORDERING_BEYOND_LLSC
>> 1989 #
>> 1990 config WEAK_ORDERING
>> 1991 bool
1256 1992
1257 config QCOM_QDF2400_ERRATUM_0065 !! 1993 #
1258 bool "QDF2400 E0065: Incorrect GITS_T !! 1994 # CPU may reorder reads and writes beyond LL/SC
1259 default y !! 1995 # CPU may reorder R->LL, R->LL, W->LL, W->LL, R->SC, R->SC, W->SC, W->SC
1260 help !! 1996 #
1261 On Qualcomm Datacenter Technologies !! 1997 config WEAK_REORDERING_BEYOND_LLSC
1262 ITE size incorrectly. The GITS_TYPE !! 1998 bool
1263 been indicated as 16Bytes (0xf), no !! 1999 endmenu
1264 2000
1265 If unsure, say Y. !! 2001 #
>> 2002 # These two indicate any level of the MIPS32 and MIPS64 architecture
>> 2003 #
>> 2004 config CPU_MIPS32
>> 2005 bool
>> 2006 default y if CPU_MIPS32_R1 || CPU_MIPS32_R2 || CPU_MIPS32_R6
1266 2007
1267 config QCOM_FALKOR_ERRATUM_E1041 !! 2008 config CPU_MIPS64
1268 bool "Falkor E1041: Speculative instr !! 2009 bool
1269 default y !! 2010 default y if CPU_MIPS64_R1 || CPU_MIPS64_R2 || CPU_MIPS64_R6
1270 help <<
1271 Falkor CPU may speculatively fetch <<
1272 memory location when MMU translatio <<
1273 to SCTLR_ELn[M]=0. Prefix an ISB in <<
1274 2011
1275 If unsure, say Y. !! 2012 #
>> 2013 # These two indicate the revision of the architecture, either Release 1 or Release 2
>> 2014 #
>> 2015 config CPU_MIPSR1
>> 2016 bool
>> 2017 default y if CPU_MIPS32_R1 || CPU_MIPS64_R1
1276 2018
1277 config NVIDIA_CARMEL_CNP_ERRATUM !! 2019 config CPU_MIPSR2
1278 bool "NVIDIA Carmel CNP: CNP on Carme !! 2020 bool
1279 default y !! 2021 default y if CPU_MIPS32_R2 || CPU_MIPS64_R2 || CPU_CAVIUM_OCTEON
1280 help !! 2022 select CPU_HAS_RIXI
1281 If CNP is enabled on Carmel cores, !! 2023 select MIPS_SPRAM
1282 invalidate shared TLB entries insta <<
1283 on standard ARM cores. <<
1284 2024
1285 If unsure, say Y. !! 2025 config CPU_MIPSR6
>> 2026 bool
>> 2027 default y if CPU_MIPS32_R6 || CPU_MIPS64_R6
>> 2028 select CPU_HAS_RIXI
>> 2029 select HAVE_ARCH_BITREVERSE
>> 2030 select MIPS_ASID_BITS_VARIABLE
>> 2031 select MIPS_SPRAM
1286 2032
1287 config ROCKCHIP_ERRATUM_3588001 !! 2033 config EVA
1288 bool "Rockchip 3588001: GIC600 can no !! 2034 bool
1289 default y <<
1290 help <<
1291 The Rockchip RK3588 GIC600 SoC inte <<
1292 This means, that its sharability fe <<
1293 is supported by the IP itself. <<
1294 2035
1295 If unsure, say Y. !! 2036 config XPA
>> 2037 bool
1296 2038
1297 config SOCIONEXT_SYNQUACER_PREITS !! 2039 config SYS_SUPPORTS_32BIT_KERNEL
1298 bool "Socionext Synquacer: Workaround !! 2040 bool
1299 default y !! 2041 config SYS_SUPPORTS_64BIT_KERNEL
1300 help !! 2042 bool
1301 Socionext Synquacer SoCs implement !! 2043 config CPU_SUPPORTS_32BIT_KERNEL
1302 MSI doorbell writes with non-zero v !! 2044 bool
>> 2045 config CPU_SUPPORTS_64BIT_KERNEL
>> 2046 bool
>> 2047 config CPU_SUPPORTS_CPUFREQ
>> 2048 bool
>> 2049 config CPU_SUPPORTS_ADDRWINCFG
>> 2050 bool
>> 2051 config CPU_SUPPORTS_HUGEPAGES
>> 2052 bool
>> 2053 config CPU_SUPPORTS_UNCACHED_ACCELERATED
>> 2054 bool
>> 2055 config MIPS_PGD_C0_CONTEXT
>> 2056 bool
>> 2057 default y if 64BIT && (CPU_MIPSR2 || CPU_MIPSR6) && !CPU_XLP
1303 2058
1304 If unsure, say Y. !! 2059 #
>> 2060 # Set to y for ptrace access to watch registers.
>> 2061 #
>> 2062 config HARDWARE_WATCHPOINTS
>> 2063 bool
>> 2064 default y if CPU_MIPSR1 || CPU_MIPSR2 || CPU_MIPSR6
1305 2065
1306 endmenu # "ARM errata workarounds via the alt !! 2066 menu "Kernel type"
1307 2067
1308 choice 2068 choice
1309 prompt "Page size" !! 2069 prompt "Kernel code model"
1310 default ARM64_4K_PAGES <<
1311 help <<
1312 Page size (translation granule) con <<
1313 <<
1314 config ARM64_4K_PAGES <<
1315 bool "4KB" <<
1316 select HAVE_PAGE_SIZE_4KB <<
1317 help 2070 help
1318 This feature enables 4KB pages supp !! 2071 You should only select this option if you have a workload that
1319 !! 2072 actually benefits from 64-bit processing or if your machine has
1320 config ARM64_16K_PAGES !! 2073 large memory. You will only be presented a single option in this
1321 bool "16KB" !! 2074 menu if your system does not support both 32-bit and 64-bit kernels.
1322 select HAVE_PAGE_SIZE_16KB !! 2075
>> 2076 config 32BIT
>> 2077 bool "32-bit kernel"
>> 2078 depends on CPU_SUPPORTS_32BIT_KERNEL && SYS_SUPPORTS_32BIT_KERNEL
>> 2079 select TRAD_SIGNALS
1323 help 2080 help
1324 The system will use 16KB pages supp !! 2081 Select this option if you want to build a 32-bit kernel.
1325 requires applications compiled with <<
1326 aligned segments. <<
1327 2082
1328 config ARM64_64K_PAGES !! 2083 config 64BIT
1329 bool "64KB" !! 2084 bool "64-bit kernel"
1330 select HAVE_PAGE_SIZE_64KB !! 2085 depends on CPU_SUPPORTS_64BIT_KERNEL && SYS_SUPPORTS_64BIT_KERNEL
1331 help 2086 help
1332 This feature enables 64KB pages sup !! 2087 Select this option if you want to build a 64-bit kernel.
1333 allowing only two levels of page ta <<
1334 look-up. AArch32 emulation requires <<
1335 with 64K aligned segments. <<
1336 2088
1337 endchoice 2089 endchoice
1338 2090
>> 2091 config KVM_GUEST
>> 2092 bool "KVM Guest Kernel"
>> 2093 depends on BROKEN_ON_SMP
>> 2094 help
>> 2095 Select this option if building a guest kernel for KVM (Trap & Emulate)
>> 2096 mode.
>> 2097
>> 2098 config KVM_GUEST_TIMER_FREQ
>> 2099 int "Count/Compare Timer Frequency (MHz)"
>> 2100 depends on KVM_GUEST
>> 2101 default 100
>> 2102 help
>> 2103 Set this to non-zero if building a guest kernel for KVM to skip RTC
>> 2104 emulation when determining guest CPU Frequency. Instead, the guest's
>> 2105 timer frequency is specified directly.
>> 2106
>> 2107 config MIPS_VA_BITS_48
>> 2108 bool "48 bits virtual memory"
>> 2109 depends on 64BIT
>> 2110 help
>> 2111 Support a maximum at least 48 bits of application virtual
>> 2112 memory. Default is 40 bits or less, depending on the CPU.
>> 2113 For page sizes 16k and above, this option results in a small
>> 2114 memory overhead for page tables. For 4k page size, a fourth
>> 2115 level of page tables is added which imposes both a memory
>> 2116 overhead as well as slower TLB fault handling.
>> 2117
>> 2118 If unsure, say N.
>> 2119
1339 choice 2120 choice
1340 prompt "Virtual address space size" !! 2121 prompt "Kernel page size"
1341 default ARM64_VA_BITS_52 !! 2122 default PAGE_SIZE_4KB
1342 help <<
1343 Allows choosing one of multiple pos <<
1344 space sizes. The level of translati <<
1345 a combination of page size and virt <<
1346 <<
1347 config ARM64_VA_BITS_36 <<
1348 bool "36-bit" if EXPERT <<
1349 depends on PAGE_SIZE_16KB <<
1350 <<
1351 config ARM64_VA_BITS_39 <<
1352 bool "39-bit" <<
1353 depends on PAGE_SIZE_4KB <<
1354 <<
1355 config ARM64_VA_BITS_42 <<
1356 bool "42-bit" <<
1357 depends on PAGE_SIZE_64KB <<
1358 <<
1359 config ARM64_VA_BITS_47 <<
1360 bool "47-bit" <<
1361 depends on PAGE_SIZE_16KB <<
1362 <<
1363 config ARM64_VA_BITS_48 <<
1364 bool "48-bit" <<
1365 <<
1366 config ARM64_VA_BITS_52 <<
1367 bool "52-bit" <<
1368 depends on ARM64_PAN || !ARM64_SW_TTB <<
1369 help <<
1370 Enable 52-bit virtual addressing fo <<
1371 requested via a hint to mmap(). The <<
1372 virtual addresses for its own mappi <<
1373 this feature is available, otherwis <<
1374 <<
1375 NOTE: Enabling 52-bit virtual addre <<
1376 ARMv8.3 Pointer Authentication will <<
1377 reduced from 7 bits to 3 bits, whic <<
1378 impact on its susceptibility to bru <<
1379 2123
1380 If unsure, select 48-bit virtual ad !! 2124 config PAGE_SIZE_4KB
>> 2125 bool "4kB"
>> 2126 depends on !CPU_LOONGSON2 && !CPU_LOONGSON3
>> 2127 help
>> 2128 This option select the standard 4kB Linux page size. On some
>> 2129 R3000-family processors this is the only available page size. Using
>> 2130 4kB page size will minimize memory consumption and is therefore
>> 2131 recommended for low memory systems.
>> 2132
>> 2133 config PAGE_SIZE_8KB
>> 2134 bool "8kB"
>> 2135 depends on CPU_R8000 || CPU_CAVIUM_OCTEON
>> 2136 depends on !MIPS_VA_BITS_48
>> 2137 help
>> 2138 Using 8kB page size will result in higher performance kernel at
>> 2139 the price of higher memory consumption. This option is available
>> 2140 only on R8000 and cnMIPS processors. Note that you will need a
>> 2141 suitable Linux distribution to support this.
>> 2142
>> 2143 config PAGE_SIZE_16KB
>> 2144 bool "16kB"
>> 2145 depends on !CPU_R3000 && !CPU_TX39XX
>> 2146 help
>> 2147 Using 16kB page size will result in higher performance kernel at
>> 2148 the price of higher memory consumption. This option is available on
>> 2149 all non-R3000 family processors. Note that you will need a suitable
>> 2150 Linux distribution to support this.
>> 2151
>> 2152 config PAGE_SIZE_32KB
>> 2153 bool "32kB"
>> 2154 depends on CPU_CAVIUM_OCTEON
>> 2155 depends on !MIPS_VA_BITS_48
>> 2156 help
>> 2157 Using 32kB page size will result in higher performance kernel at
>> 2158 the price of higher memory consumption. This option is available
>> 2159 only on cnMIPS cores. Note that you will need a suitable Linux
>> 2160 distribution to support this.
>> 2161
>> 2162 config PAGE_SIZE_64KB
>> 2163 bool "64kB"
>> 2164 depends on !CPU_R3000 && !CPU_TX39XX
>> 2165 help
>> 2166 Using 64kB page size will result in higher performance kernel at
>> 2167 the price of higher memory consumption. This option is available on
>> 2168 all non-R3000 family processor. Not that at the time of this
>> 2169 writing this option is still high experimental.
1381 2170
1382 endchoice 2171 endchoice
1383 2172
1384 config ARM64_FORCE_52BIT !! 2173 config FORCE_MAX_ZONEORDER
1385 bool "Force 52-bit virtual addresses !! 2174 int "Maximum zone order"
1386 depends on ARM64_VA_BITS_52 && EXPERT !! 2175 range 14 64 if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_64KB
1387 help !! 2176 default "14" if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_64KB
1388 For systems with 52-bit userspace V !! 2177 range 13 64 if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_32KB
1389 to maintain compatibility with olde !! 2178 default "13" if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_32KB
1390 unless a hint is supplied to mmap. !! 2179 range 12 64 if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_16KB
1391 !! 2180 default "12" if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_16KB
1392 This configuration option disables !! 2181 range 11 64
1393 forces all userspace addresses to b !! 2182 default "11"
1394 should only enable this configurati !! 2183 help
1395 memory management code. If unsure s !! 2184 The kernel memory allocator divides physically contiguous memory
>> 2185 blocks into "zones", where each zone is a power of two number of
>> 2186 pages. This option selects the largest power of two that the kernel
>> 2187 keeps in the memory allocator. If you need to allocate very large
>> 2188 blocks of physically contiguous memory, then you may need to
>> 2189 increase this value.
1396 2190
1397 config ARM64_VA_BITS !! 2191 This config option is actually maximum order plus one. For example,
1398 int !! 2192 a value of 11 means that the largest free memory block is 2^10 pages.
1399 default 36 if ARM64_VA_BITS_36 <<
1400 default 39 if ARM64_VA_BITS_39 <<
1401 default 42 if ARM64_VA_BITS_42 <<
1402 default 47 if ARM64_VA_BITS_47 <<
1403 default 48 if ARM64_VA_BITS_48 <<
1404 default 52 if ARM64_VA_BITS_52 <<
1405 2193
1406 choice !! 2194 The page size is not necessarily 4KB. Keep this in mind
1407 prompt "Physical address space size" !! 2195 when choosing a value for this option.
1408 default ARM64_PA_BITS_48 <<
1409 help <<
1410 Choose the maximum physical address <<
1411 support. <<
1412 2196
1413 config ARM64_PA_BITS_48 !! 2197 config BOARD_SCACHE
1414 bool "48-bit" !! 2198 bool
1415 depends on ARM64_64K_PAGES || !ARM64_ <<
1416 <<
1417 config ARM64_PA_BITS_52 <<
1418 bool "52-bit" <<
1419 depends on ARM64_64K_PAGES || ARM64_V <<
1420 depends on ARM64_PAN || !ARM64_SW_TTB <<
1421 help <<
1422 Enable support for a 52-bit physica <<
1423 part of the ARMv8.2-LPA extension. <<
1424 <<
1425 With this enabled, the kernel will <<
1426 do not support ARMv8.2-LPA, but wit <<
1427 minor performance overhead). <<
1428 2199
1429 endchoice !! 2200 config IP22_CPU_SCACHE
>> 2201 bool
>> 2202 select BOARD_SCACHE
1430 2203
1431 config ARM64_PA_BITS !! 2204 #
1432 int !! 2205 # Support for a MIPS32 / MIPS64 style S-caches
1433 default 48 if ARM64_PA_BITS_48 !! 2206 #
1434 default 52 if ARM64_PA_BITS_52 !! 2207 config MIPS_CPU_SCACHE
>> 2208 bool
>> 2209 select BOARD_SCACHE
1435 2210
1436 config ARM64_LPA2 !! 2211 config R5000_CPU_SCACHE
1437 def_bool y !! 2212 bool
1438 depends on ARM64_PA_BITS_52 && !ARM64 !! 2213 select BOARD_SCACHE
1439 2214
1440 choice !! 2215 config RM7000_CPU_SCACHE
1441 prompt "Endianness" !! 2216 bool
1442 default CPU_LITTLE_ENDIAN !! 2217 select BOARD_SCACHE
1443 help <<
1444 Select the endianness of data acces <<
1445 applications will need to be compil <<
1446 that is selected here. <<
1447 2218
1448 config CPU_BIG_ENDIAN !! 2219 config SIBYTE_DMA_PAGEOPS
1449 bool "Build big-endian kernel" !! 2220 bool "Use DMA to clear/copy pages"
1450 # https://github.com/llvm/llvm-projec !! 2221 depends on CPU_SB1
1451 depends on AS_IS_GNU || AS_VERSION >= <<
1452 help 2222 help
1453 Say Y if you plan on running a kern !! 2223 Instead of using the CPU to zero and copy pages, use a Data Mover
>> 2224 channel. These DMA channels are otherwise unused by the standard
>> 2225 SiByte Linux port. Seems to give a small performance benefit.
1454 2226
1455 config CPU_LITTLE_ENDIAN !! 2227 config CPU_HAS_PREFETCH
1456 bool "Build little-endian kernel" !! 2228 bool
1457 help <<
1458 Say Y if you plan on running a kern <<
1459 This is usually the case for distri <<
1460 2229
1461 endchoice !! 2230 config CPU_GENERIC_DUMP_TLB
>> 2231 bool
>> 2232 default y if !(CPU_R3000 || CPU_R8000 || CPU_TX39XX)
1462 2233
1463 config SCHED_MC !! 2234 config CPU_R4K_FPU
1464 bool "Multi-core scheduler support" !! 2235 bool
1465 help !! 2236 default y if !(CPU_R3000 || CPU_TX39XX)
1466 Multi-core scheduler support improv <<
1467 making when dealing with multi-core <<
1468 increased overhead in some places. <<
1469 2237
1470 config SCHED_CLUSTER !! 2238 config CPU_R4K_CACHE_TLB
1471 bool "Cluster scheduler support" !! 2239 bool
1472 help !! 2240 default y if !(CPU_R3000 || CPU_R8000 || CPU_SB1 || CPU_TX39XX || CPU_CAVIUM_OCTEON)
1473 Cluster scheduler support improves !! 2241
1474 making when dealing with machines t !! 2242 config MIPS_MT_SMP
1475 Cluster usually means a couple of C !! 2243 bool "MIPS MT SMP support (1 TC on each available VPE)"
1476 by sharing mid-level caches, last-l !! 2244 default y
1477 busses. !! 2245 depends on SYS_SUPPORTS_MULTITHREADING && !CPU_MIPSR6 && !CPU_MICROMIPS
>> 2246 select CPU_MIPSR2_IRQ_VI
>> 2247 select CPU_MIPSR2_IRQ_EI
>> 2248 select SYNC_R4K
>> 2249 select MIPS_MT
>> 2250 select SMP
>> 2251 select SMP_UP
>> 2252 select SYS_SUPPORTS_SMP
>> 2253 select SYS_SUPPORTS_SCHED_SMT
>> 2254 select MIPS_PERF_SHARED_TC_COUNTERS
>> 2255 help
>> 2256 This is a kernel model which is known as SMVP. This is supported
>> 2257 on cores with the MT ASE and uses the available VPEs to implement
>> 2258 virtual processors which supports SMP. This is equivalent to the
>> 2259 Intel Hyperthreading feature. For further information go to
>> 2260 <http://www.imgtec.com/mips/mips-multithreading.asp>.
>> 2261
>> 2262 config MIPS_MT
>> 2263 bool
1478 2264
1479 config SCHED_SMT 2265 config SCHED_SMT
1480 bool "SMT scheduler support" !! 2266 bool "SMT (multithreading) scheduler support"
>> 2267 depends on SYS_SUPPORTS_SCHED_SMT
>> 2268 default n
1481 help 2269 help
1482 Improves the CPU scheduler's decisi !! 2270 SMT scheduler support improves the CPU scheduler's decision making
1483 MultiThreading at a cost of slightl !! 2271 when dealing with MIPS MT enabled cores at a cost of slightly
1484 places. If unsure say N here. !! 2272 increased overhead in some places. If unsure say N here.
1485 2273
1486 config NR_CPUS !! 2274 config SYS_SUPPORTS_SCHED_SMT
1487 int "Maximum number of CPUs (2-4096)" !! 2275 bool
1488 range 2 4096 <<
1489 default "512" <<
1490 2276
1491 config HOTPLUG_CPU !! 2277 config SYS_SUPPORTS_MULTITHREADING
1492 bool "Support for hot-pluggable CPUs" !! 2278 bool
1493 select GENERIC_IRQ_MIGRATION <<
1494 help <<
1495 Say Y here to experiment with turni <<
1496 can be controlled through /sys/devi <<
1497 2279
1498 # Common NUMA Features !! 2280 config MIPS_MT_FPAFF
1499 config NUMA !! 2281 bool "Dynamic FPU affinity for FP-intensive threads"
1500 bool "NUMA Memory Allocation and Sche !! 2282 default y
1501 select GENERIC_ARCH_NUMA !! 2283 depends on MIPS_MT_SMP
1502 select OF_NUMA <<
1503 select HAVE_SETUP_PER_CPU_AREA <<
1504 select NEED_PER_CPU_EMBED_FIRST_CHUNK <<
1505 select NEED_PER_CPU_PAGE_FIRST_CHUNK <<
1506 select USE_PERCPU_NUMA_NODE_ID <<
1507 help <<
1508 Enable NUMA (Non-Uniform Memory Acc <<
1509 <<
1510 The kernel will try to allocate mem <<
1511 local memory of the CPU and add som <<
1512 NUMA awareness to the kernel. <<
1513 2284
1514 config NODES_SHIFT !! 2285 config MIPSR2_TO_R6_EMULATOR
1515 int "Maximum NUMA Nodes (as a power o !! 2286 bool "MIPS R2-to-R6 emulator"
1516 range 1 10 !! 2287 depends on CPU_MIPSR6
1517 default "4" !! 2288 default y
1518 depends on NUMA <<
1519 help 2289 help
1520 Specify the maximum number of NUMA !! 2290 Choose this option if you want to run non-R6 MIPS userland code.
1521 system. Increases memory reserved !! 2291 Even if you say 'Y' here, the emulator will still be disabled by
>> 2292 default. You can enable it using the 'mipsr2emu' kernel option.
>> 2293 The only reason this is a build-time option is to save ~14K from the
>> 2294 final kernel image.
1522 2295
1523 source "kernel/Kconfig.hz" !! 2296 config SYS_SUPPORTS_VPE_LOADER
>> 2297 bool
>> 2298 depends on SYS_SUPPORTS_MULTITHREADING
>> 2299 help
>> 2300 Indicates that the platform supports the VPE loader, and provides
>> 2301 physical_memsize.
1524 2302
1525 config ARCH_SPARSEMEM_ENABLE !! 2303 config MIPS_VPE_LOADER
1526 def_bool y !! 2304 bool "VPE loader support."
1527 select SPARSEMEM_VMEMMAP_ENABLE !! 2305 depends on SYS_SUPPORTS_VPE_LOADER && MODULES
1528 select SPARSEMEM_VMEMMAP !! 2306 select CPU_MIPSR2_IRQ_VI
>> 2307 select CPU_MIPSR2_IRQ_EI
>> 2308 select MIPS_MT
>> 2309 help
>> 2310 Includes a loader for loading an elf relocatable object
>> 2311 onto another VPE and running it.
1529 2312
1530 config HW_PERF_EVENTS !! 2313 config MIPS_VPE_LOADER_CMP
1531 def_bool y !! 2314 bool
1532 depends on ARM_PMU !! 2315 default "y"
>> 2316 depends on MIPS_VPE_LOADER && MIPS_CMP
1533 2317
1534 # Supported by clang >= 7.0 or GCC >= 12.0.0 !! 2318 config MIPS_VPE_LOADER_MT
1535 config CC_HAVE_SHADOW_CALL_STACK !! 2319 bool
1536 def_bool $(cc-option, -fsanitize=shad !! 2320 default "y"
>> 2321 depends on MIPS_VPE_LOADER && !MIPS_CMP
1537 2322
1538 config PARAVIRT !! 2323 config MIPS_VPE_LOADER_TOM
1539 bool "Enable paravirtualization code" !! 2324 bool "Load VPE program into memory hidden from linux"
>> 2325 depends on MIPS_VPE_LOADER
>> 2326 default y
1540 help 2327 help
1541 This changes the kernel so it can m !! 2328 The loader can use memory that is present but has been hidden from
1542 under a hypervisor, potentially imp !! 2329 Linux using the kernel command line option "mem=xxMB". It's up to
1543 over full virtualization. !! 2330 you to ensure the amount you put in the option and the space your
>> 2331 program requires is less or equal to the amount physically present.
1544 2332
1545 config PARAVIRT_TIME_ACCOUNTING !! 2333 config MIPS_VPE_APSP_API
1546 bool "Paravirtual steal time accounti !! 2334 bool "Enable support for AP/SP API (RTLX)"
1547 select PARAVIRT !! 2335 depends on MIPS_VPE_LOADER
1548 help <<
1549 Select this option to enable fine g <<
1550 accounting. Time spent executing ot <<
1551 the current vCPU is discounted from <<
1552 that, there can be a small performa <<
1553 2336
1554 If in doubt, say N here. !! 2337 config MIPS_VPE_APSP_API_CMP
>> 2338 bool
>> 2339 default "y"
>> 2340 depends on MIPS_VPE_APSP_API && MIPS_CMP
1555 2341
1556 config ARCH_SUPPORTS_KEXEC !! 2342 config MIPS_VPE_APSP_API_MT
1557 def_bool PM_SLEEP_SMP !! 2343 bool
>> 2344 default "y"
>> 2345 depends on MIPS_VPE_APSP_API && !MIPS_CMP
1558 2346
1559 config ARCH_SUPPORTS_KEXEC_FILE !! 2347 config MIPS_CMP
1560 def_bool y !! 2348 bool "MIPS CMP framework support (DEPRECATED)"
>> 2349 depends on SYS_SUPPORTS_MIPS_CMP && !CPU_MIPSR6
>> 2350 select SMP
>> 2351 select SYNC_R4K
>> 2352 select SYS_SUPPORTS_SMP
>> 2353 select WEAK_ORDERING
>> 2354 default n
>> 2355 help
>> 2356 Select this if you are using a bootloader which implements the "CMP
>> 2357 framework" protocol (ie. YAMON) and want your kernel to make use of
>> 2358 its ability to start secondary CPUs.
>> 2359
>> 2360 Unless you have a specific need, you should use CONFIG_MIPS_CPS
>> 2361 instead of this.
>> 2362
>> 2363 config MIPS_CPS
>> 2364 bool "MIPS Coherent Processing System support"
>> 2365 depends on SYS_SUPPORTS_MIPS_CPS
>> 2366 select MIPS_CM
>> 2367 select MIPS_CPS_PM if HOTPLUG_CPU
>> 2368 select SMP
>> 2369 select SYNC_R4K if (CEVT_R4K || CSRC_R4K)
>> 2370 select SYS_SUPPORTS_HOTPLUG_CPU
>> 2371 select SYS_SUPPORTS_SCHED_SMT if CPU_MIPSR6
>> 2372 select SYS_SUPPORTS_SMP
>> 2373 select WEAK_ORDERING
>> 2374 help
>> 2375 Select this if you wish to run an SMP kernel across multiple cores
>> 2376 within a MIPS Coherent Processing System. When this option is
>> 2377 enabled the kernel will probe for other cores and boot them with
>> 2378 no external assistance. It is safe to enable this when hardware
>> 2379 support is unavailable.
1561 2380
1562 config ARCH_SELECTS_KEXEC_FILE !! 2381 config MIPS_CPS_PM
1563 def_bool y !! 2382 depends on MIPS_CPS
1564 depends on KEXEC_FILE !! 2383 bool
1565 select HAVE_IMA_KEXEC if IMA <<
1566 2384
1567 config ARCH_SUPPORTS_KEXEC_SIG !! 2385 config MIPS_CM
1568 def_bool y !! 2386 bool
>> 2387 select MIPS_CPC
1569 2388
1570 config ARCH_SUPPORTS_KEXEC_IMAGE_VERIFY_SIG !! 2389 config MIPS_CPC
1571 def_bool y !! 2390 bool
1572 2391
1573 config ARCH_DEFAULT_KEXEC_IMAGE_VERIFY_SIG !! 2392 config SB1_PASS_2_WORKAROUNDS
1574 def_bool y !! 2393 bool
>> 2394 depends on CPU_SB1 && (CPU_SB1_PASS_2_2 || CPU_SB1_PASS_2)
>> 2395 default y
1575 2396
1576 config ARCH_SUPPORTS_CRASH_DUMP !! 2397 config SB1_PASS_2_1_WORKAROUNDS
1577 def_bool y !! 2398 bool
>> 2399 depends on CPU_SB1 && CPU_SB1_PASS_2
>> 2400 default y
1578 2401
1579 config ARCH_HAS_GENERIC_CRASHKERNEL_RESERVATI <<
1580 def_bool CRASH_RESERVE <<
1581 2402
1582 config TRANS_TABLE !! 2403 config ARCH_PHYS_ADDR_T_64BIT
1583 def_bool y !! 2404 bool
1584 depends on HIBERNATION || KEXEC_CORE <<
1585 2405
1586 config XEN_DOM0 !! 2406 choice
1587 def_bool y !! 2407 prompt "SmartMIPS or microMIPS ASE support"
1588 depends on XEN <<
1589 2408
1590 config XEN !! 2409 config CPU_NEEDS_NO_SMARTMIPS_OR_MICROMIPS
1591 bool "Xen guest support on ARM64" !! 2410 bool "None"
1592 depends on ARM64 && OF <<
1593 select SWIOTLB_XEN <<
1594 select PARAVIRT <<
1595 help 2411 help
1596 Say Y if you want to run Linux in a !! 2412 Select this if you want neither microMIPS nor SmartMIPS support
1597 2413
1598 # include/linux/mmzone.h requires the followi !! 2414 config CPU_HAS_SMARTMIPS
1599 # !! 2415 depends on SYS_SUPPORTS_SMARTMIPS
1600 # MAX_PAGE_ORDER + PAGE_SHIFT <= SECTION_SI !! 2416 bool "SmartMIPS"
1601 # !! 2417 help
1602 # so the maximum value of MAX_PAGE_ORDER is S !! 2418 SmartMIPS is a extension of the MIPS32 architecture aimed at
1603 # !! 2419 increased security at both hardware and software level for
1604 # | SECTION_SIZE_BITS | PAGE_SHIFT | m !! 2420 smartcards. Enabling this option will allow proper use of the
1605 # ----+-------------------+--------------+--- !! 2421 SmartMIPS instructions by Linux applications. However a kernel with
1606 # 4K | 27 | 12 | !! 2422 this option will not work on a MIPS core without SmartMIPS core. If
1607 # 16K | 27 | 14 | !! 2423 you don't know you probably don't have SmartMIPS and should say N
1608 # 64K | 29 | 16 | !! 2424 here.
1609 config ARCH_FORCE_MAX_ORDER !! 2425
1610 int !! 2426 config CPU_MICROMIPS
1611 default "13" if ARM64_64K_PAGES !! 2427 depends on 32BIT && SYS_SUPPORTS_MICROMIPS && !CPU_MIPSR6
1612 default "11" if ARM64_16K_PAGES !! 2428 bool "microMIPS"
1613 default "10" <<
1614 help 2429 help
1615 The kernel page allocator limits th !! 2430 When this option is enabled the kernel will be built using the
1616 contiguous allocations. The limit i !! 2431 microMIPS ISA
1617 defines the maximal power of two of <<
1618 allocated as a single contiguous bl <<
1619 overriding the default setting when <<
1620 large blocks of physically contiguo <<
1621 <<
1622 The maximal size of allocation cann <<
1623 section, so the value of MAX_PAGE_O <<
1624 2432
1625 MAX_PAGE_ORDER + PAGE_SHIFT <= SE !! 2433 endchoice
1626 <<
1627 Don't change if unsure. <<
1628 2434
1629 config UNMAP_KERNEL_AT_EL0 !! 2435 config CPU_HAS_MSA
1630 bool "Unmap kernel when running in us !! 2436 bool "Support for the MIPS SIMD Architecture"
1631 default y !! 2437 depends on CPU_SUPPORTS_MSA
1632 help !! 2438 depends on 64BIT || MIPS_O32_FP64_SUPPORT
1633 Speculation attacks against some hi !! 2439 help
1634 be used to bypass MMU permission ch !! 2440 MIPS SIMD Architecture (MSA) introduces 128 bit wide vector registers
1635 userspace. This can be defended aga !! 2441 and a set of SIMD instructions to operate on them. When this option
1636 when running in userspace, mapping !! 2442 is enabled the kernel will support allocating & switching MSA
1637 via a trampoline page in the vector !! 2443 vector register contexts. If you know that your kernel will only be
>> 2444 running on CPUs which do not support MSA or that your userland will
>> 2445 not be making use of it then you may wish to say N here to reduce
>> 2446 the size & complexity of your kernel.
1638 2447
1639 If unsure, say Y. 2448 If unsure, say Y.
1640 2449
1641 config MITIGATE_SPECTRE_BRANCH_HISTORY !! 2450 config CPU_HAS_WB
1642 bool "Mitigate Spectre style attacks !! 2451 bool
1643 default y <<
1644 help <<
1645 Speculation attacks against some hi <<
1646 make use of branch history to influ <<
1647 When taking an exception from user- <<
1648 or a firmware call overwrites the b <<
1649 2452
1650 config RODATA_FULL_DEFAULT_ENABLED !! 2453 config XKS01
1651 bool "Apply r/o permissions of VM are !! 2454 bool
1652 default y !! 2455
1653 help !! 2456 config CPU_HAS_RIXI
1654 Apply read-only attributes of VM ar !! 2457 bool
1655 the backing pages as well. This pre <<
1656 from being modified (inadvertently <<
1657 mapping of the same memory page. Th <<
1658 be turned off at runtime by passing <<
1659 with rodata=full if this option is <<
1660 2458
1661 This requires the linear region to !! 2459 #
1662 which may adversely affect performa !! 2460 # Vectored interrupt mode is an R2 feature
>> 2461 #
>> 2462 config CPU_MIPSR2_IRQ_VI
>> 2463 bool
1663 2464
1664 config ARM64_SW_TTBR0_PAN !! 2465 #
1665 bool "Emulate Privileged Access Never !! 2466 # Extended interrupt mode is an R2 feature
1666 depends on !KCSAN !! 2467 #
1667 help !! 2468 config CPU_MIPSR2_IRQ_EI
1668 Enabling this option prevents the k !! 2469 bool
1669 user-space memory directly by point <<
1670 zeroed area and reserved ASID. The <<
1671 restore the valid TTBR0_EL1 tempora <<
1672 2470
1673 config ARM64_TAGGED_ADDR_ABI !! 2471 config CPU_HAS_SYNC
1674 bool "Enable the tagged user addresse !! 2472 bool
>> 2473 depends on !CPU_R3000
1675 default y 2474 default y
1676 help <<
1677 When this option is enabled, user a <<
1678 relaxed ABI via prctl() allowing ta <<
1679 to system calls as pointer argument <<
1680 Documentation/arch/arm64/tagged-add <<
1681 <<
1682 menuconfig COMPAT <<
1683 bool "Kernel support for 32-bit EL0" <<
1684 depends on ARM64_4K_PAGES || EXPERT <<
1685 select HAVE_UID16 <<
1686 select OLD_SIGSUSPEND3 <<
1687 select COMPAT_OLD_SIGACTION <<
1688 help <<
1689 This option enables support for a 3 <<
1690 kernel at EL1. AArch32-specific com <<
1691 the user helper functions, VFP supp <<
1692 handled appropriately by the kernel <<
1693 2475
1694 If you use a page size other than 4 !! 2476 #
1695 that you will only be able to execu !! 2477 # CPU non-features
1696 with page size aligned segments. !! 2478 #
>> 2479 config CPU_DADDI_WORKAROUNDS
>> 2480 bool
1697 2481
1698 If you want to execute 32-bit users !! 2482 config CPU_R4000_WORKAROUNDS
>> 2483 bool
>> 2484 select CPU_R4400_WORKAROUNDS
1699 2485
1700 if COMPAT !! 2486 config CPU_R4400_WORKAROUNDS
>> 2487 bool
1701 2488
1702 config KUSER_HELPERS !! 2489 config MIPS_ASID_SHIFT
1703 bool "Enable kuser helpers page for 3 !! 2490 int
1704 default y !! 2491 default 6 if CPU_R3000 || CPU_TX39XX
1705 help !! 2492 default 4 if CPU_R8000
1706 Warning: disabling this option may !! 2493 default 0
1707 2494
1708 Provide kuser helpers to compat tas !! 2495 config MIPS_ASID_BITS
1709 helper code to userspace in read on !! 2496 int
1710 to allow userspace to be independen !! 2497 default 0 if MIPS_ASID_BITS_VARIABLE
1711 the system. This permits binaries t !! 2498 default 6 if CPU_R3000 || CPU_TX39XX
1712 to ARMv8 without modification. !! 2499 default 8
1713 2500
1714 See Documentation/arch/arm/kernel_u !! 2501 config MIPS_ASID_BITS_VARIABLE
>> 2502 bool
1715 2503
1716 However, the fixed address nature o !! 2504 #
1717 by ROP (return orientated programmi !! 2505 # - Highmem only makes sense for the 32-bit kernel.
1718 exploits. !! 2506 # - The current highmem code will only work properly on physically indexed
>> 2507 # caches such as R3000, SB1, R7000 or those that look like they're virtually
>> 2508 # indexed such as R4000/R4400 SC and MC versions or R10000. So for the
>> 2509 # moment we protect the user and offer the highmem option only on machines
>> 2510 # where it's known to be safe. This will not offer highmem on a few systems
>> 2511 # such as MIPS32 and MIPS64 CPUs which may have virtual and physically
>> 2512 # indexed CPUs but we're playing safe.
>> 2513 # - We use SYS_SUPPORTS_HIGHMEM to offer highmem only for systems where we
>> 2514 # know they might have memory configurations that could make use of highmem
>> 2515 # support.
>> 2516 #
>> 2517 config HIGHMEM
>> 2518 bool "High Memory Support"
>> 2519 depends on 32BIT && CPU_SUPPORTS_HIGHMEM && SYS_SUPPORTS_HIGHMEM && !CPU_MIPS32_3_5_EVA
1719 2520
1720 If all of the binaries and librarie !! 2521 config CPU_SUPPORTS_HIGHMEM
1721 are built specifically for your pla !! 2522 bool
1722 these helpers, then you can turn th <<
1723 such exploits. However, in that cas <<
1724 relying on those helpers is run, it <<
1725 2523
1726 Say N here only if you are absolute !! 2524 config SYS_SUPPORTS_HIGHMEM
1727 need these helpers; otherwise, the !! 2525 bool
1728 2526
1729 config COMPAT_VDSO !! 2527 config SYS_SUPPORTS_SMARTMIPS
1730 bool "Enable vDSO for 32-bit applicat !! 2528 bool
1731 depends on !CPU_BIG_ENDIAN <<
1732 depends on (CC_IS_CLANG && LD_IS_LLD) <<
1733 select GENERIC_COMPAT_VDSO <<
1734 default y <<
1735 help <<
1736 Place in the process address space <<
1737 ELF shared object providing fast im <<
1738 and clock_gettime. <<
1739 2529
1740 You must have a 32-bit build of gli !! 2530 config SYS_SUPPORTS_MICROMIPS
1741 to seamlessly take advantage of thi !! 2531 bool
1742 2532
1743 config THUMB2_COMPAT_VDSO !! 2533 config SYS_SUPPORTS_MIPS16
1744 bool "Compile the 32-bit vDSO for Thu !! 2534 bool
1745 depends on COMPAT_VDSO <<
1746 default y <<
1747 help 2535 help
1748 Compile the compat vDSO with '-mthu !! 2536 This option must be set if a kernel might be executed on a MIPS16-
1749 otherwise with '-marm'. !! 2537 enabled CPU even if MIPS16 is not actually being used. In other
1750 !! 2538 words, it makes the kernel MIPS16-tolerant.
1751 config COMPAT_ALIGNMENT_FIXUPS <<
1752 bool "Fix up misaligned multi-word lo <<
1753 2539
1754 menuconfig ARMV8_DEPRECATED !! 2540 config CPU_SUPPORTS_MSA
1755 bool "Emulate deprecated/obsolete ARM !! 2541 bool
1756 depends on SYSCTL <<
1757 help <<
1758 Legacy software support may require <<
1759 that have been deprecated or obsole <<
1760 2542
1761 Enable this config to enable select !! 2543 config ARCH_FLATMEM_ENABLE
1762 features. !! 2544 def_bool y
>> 2545 depends on !NUMA && !CPU_LOONGSON2
1763 2546
1764 If unsure, say Y !! 2547 config ARCH_DISCONTIGMEM_ENABLE
>> 2548 bool
>> 2549 default y if SGI_IP27
>> 2550 help
>> 2551 Say Y to support efficient handling of discontiguous physical memory,
>> 2552 for architectures which are either NUMA (Non-Uniform Memory Access)
>> 2553 or have huge holes in the physical address space for other reasons.
>> 2554 See <file:Documentation/vm/numa> for more.
1765 2555
1766 if ARMV8_DEPRECATED !! 2556 config ARCH_SPARSEMEM_ENABLE
>> 2557 bool
>> 2558 select SPARSEMEM_STATIC
1767 2559
1768 config SWP_EMULATION !! 2560 config NUMA
1769 bool "Emulate SWP/SWPB instructions" !! 2561 bool "NUMA Support"
>> 2562 depends on SYS_SUPPORTS_NUMA
1770 help 2563 help
1771 ARMv8 obsoletes the use of A32 SWP/ !! 2564 Say Y to compile the kernel to support NUMA (Non-Uniform Memory
1772 they are always undefined. Say Y he !! 2565 Access). This option improves performance on systems with more
1773 emulation of these instructions for !! 2566 than two nodes; on two node systems it is generally better to
1774 This feature can be controlled at r !! 2567 leave it disabled; on single node systems disable this option
1775 sysctl which is disabled by default !! 2568 disabled.
1776 2569
1777 In some older versions of glibc [<= !! 2570 config SYS_SUPPORTS_NUMA
1778 trylock() operations with the assum !! 2571 bool
1779 be preempted. This invalid assumpti <<
1780 with SWP emulation enabled, leading <<
1781 application. <<
1782 2572
1783 NOTE: when accessing uncached share !! 2573 config RELOCATABLE
1784 on an external transaction monitori !! 2574 bool "Relocatable kernel"
1785 monitor to maintain update atomicit !! 2575 depends on SYS_SUPPORTS_RELOCATABLE && (CPU_MIPS32_R2 || CPU_MIPS64_R2 || CPU_MIPS32_R6 || CPU_MIPS64_R6 || CAVIUM_OCTEON_SOC)
1786 implement a global monitor, this op !! 2576 help
1787 perform SWP operations to uncached !! 2577 This builds a kernel image that retains relocation information
>> 2578 so it can be loaded someplace besides the default 1MB.
>> 2579 The relocations make the kernel binary about 15% larger,
>> 2580 but are discarded at runtime
>> 2581
>> 2582 config RELOCATION_TABLE_SIZE
>> 2583 hex "Relocation table size"
>> 2584 depends on RELOCATABLE
>> 2585 range 0x0 0x01000000
>> 2586 default "0x00100000"
>> 2587 ---help---
>> 2588 A table of relocation data will be appended to the kernel binary
>> 2589 and parsed at boot to fix up the relocated kernel.
1788 2590
1789 If unsure, say Y !! 2591 This option allows the amount of space reserved for the table to be
>> 2592 adjusted, although the default of 1Mb should be ok in most cases.
1790 2593
1791 config CP15_BARRIER_EMULATION !! 2594 The build will fail and a valid size suggested if this is too small.
1792 bool "Emulate CP15 Barrier instructio <<
1793 help <<
1794 The CP15 barrier instructions - CP1 <<
1795 CP15DMB - are deprecated in ARMv8 ( <<
1796 strongly recommended to use the ISB <<
1797 instructions instead. <<
1798 2595
1799 Say Y here to enable software emula !! 2596 If unsure, leave at the default value.
1800 instructions for AArch32 userspace <<
1801 enabled, CP15 barrier usage is trac <<
1802 identify software that needs updati <<
1803 controlled at runtime with the abi. <<
1804 2597
1805 If unsure, say Y !! 2598 config RANDOMIZE_BASE
>> 2599 bool "Randomize the address of the kernel image"
>> 2600 depends on RELOCATABLE
>> 2601 ---help---
>> 2602 Randomizes the physical and virtual address at which the
>> 2603 kernel image is loaded, as a security feature that
>> 2604 deters exploit attempts relying on knowledge of the location
>> 2605 of kernel internals.
1806 2606
1807 config SETEND_EMULATION !! 2607 Entropy is generated using any coprocessor 0 registers available.
1808 bool "Emulate SETEND instruction" <<
1809 help <<
1810 The SETEND instruction alters the d <<
1811 AArch32 EL0, and is deprecated in A <<
1812 2608
1813 Say Y here to enable software emula !! 2609 The kernel will be offset by up to RANDOMIZE_BASE_MAX_OFFSET.
1814 for AArch32 userspace code. This fe <<
1815 at runtime with the abi.setend sysc <<
1816 2610
1817 Note: All the cpus on the system mu !! 2611 If unsure, say N.
1818 for this feature to be enabled. If <<
1819 endian - is hotplugged in after thi <<
1820 be unexpected results in the applic <<
1821 2612
1822 If unsure, say Y !! 2613 config RANDOMIZE_BASE_MAX_OFFSET
1823 endif # ARMV8_DEPRECATED !! 2614 hex "Maximum kASLR offset" if EXPERT
>> 2615 depends on RANDOMIZE_BASE
>> 2616 range 0x0 0x40000000 if EVA || 64BIT
>> 2617 range 0x0 0x08000000
>> 2618 default "0x01000000"
>> 2619 ---help---
>> 2620 When kASLR is active, this provides the maximum offset that will
>> 2621 be applied to the kernel image. It should be set according to the
>> 2622 amount of physical RAM available in the target system minus
>> 2623 PHYSICAL_START and must be a power of 2.
1824 2624
1825 endif # COMPAT !! 2625 This is limited by the size of KSEG0, 256Mb on 32-bit or 1Gb with
>> 2626 EVA or 64-bit. The default is 16Mb.
1826 2627
1827 menu "ARMv8.1 architectural features" !! 2628 config NODES_SHIFT
>> 2629 int
>> 2630 default "6"
>> 2631 depends on NEED_MULTIPLE_NODES
1828 2632
1829 config ARM64_HW_AFDBM !! 2633 config HW_PERF_EVENTS
1830 bool "Support for hardware updates of !! 2634 bool "Enable hardware performance counter support for perf events"
>> 2635 depends on PERF_EVENTS && !OPROFILE && (CPU_MIPS32 || CPU_MIPS64 || CPU_R10000 || CPU_SB1 || CPU_CAVIUM_OCTEON || CPU_XLP || CPU_LOONGSON3)
1831 default y 2636 default y
1832 help 2637 help
1833 The ARMv8.1 architecture extensions !! 2638 Enable hardware performance counter support for perf events. If
1834 hardware updates of the access and !! 2639 disabled, perf events will use software events only.
1835 table entries. When enabled in TCR_ <<
1836 capable processors, accesses to pag <<
1837 set this bit instead of raising an <<
1838 Similarly, writes to read-only page <<
1839 clear the read-only bit (AP[2]) ins <<
1840 permission fault. <<
1841 2640
1842 Kernels built with this configurati !! 2641 source "mm/Kconfig"
1843 to work on pre-ARMv8.1 hardware and <<
1844 minimal. If unsure, say Y. <<
1845 2642
1846 config ARM64_PAN !! 2643 config SMP
1847 bool "Enable support for Privileged A !! 2644 bool "Multi-Processing support"
1848 default y !! 2645 depends on SYS_SUPPORTS_SMP
1849 help 2646 help
1850 Privileged Access Never (PAN; part !! 2647 This enables support for systems with more than one CPU. If you have
1851 prevents the kernel or hypervisor f !! 2648 a system with only one CPU, say N. If you have a system with more
1852 memory directly. !! 2649 than one CPU, say Y.
1853 !! 2650
1854 Choosing this option will cause any !! 2651 If you say N here, the kernel will run on uni- and multiprocessor
1855 copy_to_user et al) memory access t !! 2652 machines, but will use only one CPU of a multiprocessor machine. If
>> 2653 you say Y here, the kernel will run on many, but not all,
>> 2654 uniprocessor machines. On a uniprocessor machine, the kernel
>> 2655 will run faster if you say N here.
1856 2656
1857 The feature is detected at runtime, !! 2657 People using multiprocessor machines who say Y here should also say
1858 instruction if the cpu does not imp !! 2658 Y to "Enhanced Real Time Clock Support", below.
1859 2659
1860 config AS_HAS_LSE_ATOMICS !! 2660 See also the SMP-HOWTO available at
1861 def_bool $(as-instr,.arch_extension l !! 2661 <http://www.tldp.org/docs.html#howto>.
1862 2662
1863 config ARM64_LSE_ATOMICS !! 2663 If you don't know what to do here, say N.
1864 bool <<
1865 default ARM64_USE_LSE_ATOMICS <<
1866 depends on AS_HAS_LSE_ATOMICS <<
1867 2664
1868 config ARM64_USE_LSE_ATOMICS !! 2665 config HOTPLUG_CPU
1869 bool "Atomic instructions" !! 2666 bool "Support for hot-pluggable CPUs"
1870 default y !! 2667 depends on SMP && SYS_SUPPORTS_HOTPLUG_CPU
1871 help 2668 help
1872 As part of the Large System Extensi !! 2669 Say Y here to allow turning CPUs off and on. CPUs can be
1873 atomic instructions that are design !! 2670 controlled through /sys/devices/system/cpu.
1874 very large systems. !! 2671 (Note: power management support will enable this option
>> 2672 automatically on SMP systems. )
>> 2673 Say N if you want to disable CPU hotplug.
1875 2674
1876 Say Y here to make use of these ins !! 2675 config SMP_UP
1877 atomic routines. This incurs a smal !! 2676 bool
1878 not support these instructions and <<
1879 built with binutils >= 2.25 in orde <<
1880 to be used. <<
1881 2677
1882 endmenu # "ARMv8.1 architectural features" !! 2678 config SYS_SUPPORTS_MIPS_CMP
>> 2679 bool
1883 2680
1884 menu "ARMv8.2 architectural features" !! 2681 config SYS_SUPPORTS_MIPS_CPS
>> 2682 bool
1885 2683
1886 config AS_HAS_ARMV8_2 !! 2684 config SYS_SUPPORTS_SMP
1887 def_bool $(cc-option,-Wa$(comma)-marc !! 2685 bool
1888 2686
1889 config AS_HAS_SHA3 !! 2687 config NR_CPUS_DEFAULT_4
1890 def_bool $(as-instr,.arch armv8.2-a+s !! 2688 bool
1891 2689
1892 config ARM64_PMEM !! 2690 config NR_CPUS_DEFAULT_8
1893 bool "Enable support for persistent m !! 2691 bool
1894 select ARCH_HAS_PMEM_API <<
1895 select ARCH_HAS_UACCESS_FLUSHCACHE <<
1896 help <<
1897 Say Y to enable support for the per <<
1898 ARMv8.2 DCPoP feature. <<
1899 2692
1900 The feature is detected at runtime, !! 2693 config NR_CPUS_DEFAULT_16
1901 operations if DC CVAP is not suppor !! 2694 bool
1902 DC CVAP itself if the system does n <<
1903 2695
1904 config ARM64_RAS_EXTN !! 2696 config NR_CPUS_DEFAULT_32
1905 bool "Enable support for RAS CPU Exte !! 2697 bool
1906 default y <<
1907 help <<
1908 CPUs that support the Reliability, <<
1909 (RAS) Extensions, part of ARMv8.2 a <<
1910 errors, classify them and report th <<
1911 2698
1912 On CPUs with these extensions syste !! 2699 config NR_CPUS_DEFAULT_64
1913 barriers to determine if faults are !! 2700 bool
1914 classification from a new set of re <<
1915 2701
1916 Selecting this feature will allow t !! 2702 config NR_CPUS
1917 and access the new registers if the !! 2703 int "Maximum number of CPUs (2-256)"
1918 Platform RAS features may additiona !! 2704 range 2 256
>> 2705 depends on SMP
>> 2706 default "4" if NR_CPUS_DEFAULT_4
>> 2707 default "8" if NR_CPUS_DEFAULT_8
>> 2708 default "16" if NR_CPUS_DEFAULT_16
>> 2709 default "32" if NR_CPUS_DEFAULT_32
>> 2710 default "64" if NR_CPUS_DEFAULT_64
>> 2711 help
>> 2712 This allows you to specify the maximum number of CPUs which this
>> 2713 kernel will support. The maximum supported value is 32 for 32-bit
>> 2714 kernel and 64 for 64-bit kernels; the minimum value which makes
>> 2715 sense is 1 for Qemu (useful only for kernel debugging purposes)
>> 2716 and 2 for all others.
>> 2717
>> 2718 This is purely to save memory - each supported CPU adds
>> 2719 approximately eight kilobytes to the kernel image. For best
>> 2720 performance should round up your number of processors to the next
>> 2721 power of two.
1919 2722
1920 config ARM64_CNP !! 2723 config MIPS_PERF_SHARED_TC_COUNTERS
1921 bool "Enable support for Common Not P !! 2724 bool
1922 default y <<
1923 depends on ARM64_PAN || !ARM64_SW_TTB <<
1924 help <<
1925 Common Not Private (CNP) allows tra <<
1926 be shared between different PEs in <<
1927 domain, so the hardware can use thi <<
1928 caching of such entries in the TLB. <<
1929 2725
1930 Selecting this option allows the CN !! 2726 config MIPS_NR_CPU_NR_MAP_1024
1931 at runtime, and does not affect PEs !! 2727 bool
1932 this feature. <<
1933 2728
1934 endmenu # "ARMv8.2 architectural features" !! 2729 config MIPS_NR_CPU_NR_MAP
>> 2730 int
>> 2731 depends on SMP
>> 2732 default 1024 if MIPS_NR_CPU_NR_MAP_1024
>> 2733 default NR_CPUS if !MIPS_NR_CPU_NR_MAP_1024
1935 2734
1936 menu "ARMv8.3 architectural features" !! 2735 #
>> 2736 # Timer Interrupt Frequency Configuration
>> 2737 #
1937 2738
1938 config ARM64_PTR_AUTH !! 2739 choice
1939 bool "Enable support for pointer auth !! 2740 prompt "Timer frequency"
1940 default y !! 2741 default HZ_250
1941 help 2742 help
1942 Pointer authentication (part of the !! 2743 Allows the configuration of the timer frequency.
1943 instructions for signing and authen <<
1944 keys, which can be used to mitigate <<
1945 and other attacks. <<
1946 2744
1947 This option enables these instructi !! 2745 config HZ_24
1948 Choosing this option will cause the !! 2746 bool "24 HZ" if SYS_SUPPORTS_24HZ || SYS_SUPPORTS_ARBIT_HZ
1949 for each process at exec() time, wi <<
1950 context-switched along with the pro <<
1951 2747
1952 The feature is detected at runtime. !! 2748 config HZ_48
1953 hardware it will not be advertised !! 2749 bool "48 HZ" if SYS_SUPPORTS_48HZ || SYS_SUPPORTS_ARBIT_HZ
1954 be enabled. <<
1955 2750
1956 If the feature is present on the bo !! 2751 config HZ_100
1957 the late CPU will be parked. Also, !! 2752 bool "100 HZ" if SYS_SUPPORTS_100HZ || SYS_SUPPORTS_ARBIT_HZ
1958 address auth and the late CPU has t <<
1959 but with the feature disabled. On s <<
1960 not be selected. <<
1961 2753
1962 config ARM64_PTR_AUTH_KERNEL !! 2754 config HZ_128
1963 bool "Use pointer authentication for !! 2755 bool "128 HZ" if SYS_SUPPORTS_128HZ || SYS_SUPPORTS_ARBIT_HZ
1964 default y <<
1965 depends on ARM64_PTR_AUTH <<
1966 depends on (CC_HAS_SIGN_RETURN_ADDRES <<
1967 # Modern compilers insert a .note.gnu <<
1968 # which is only understood by binutil <<
1969 depends on LD_IS_LLD || LD_VERSION >= <<
1970 depends on !CC_IS_CLANG || AS_HAS_CFI <<
1971 depends on (!FUNCTION_GRAPH_TRACER || <<
1972 help <<
1973 If the compiler supports the -mbran <<
1974 -msign-return-address flag (e.g. GC <<
1975 will cause the kernel itself to be <<
1976 protection. In this case, and if th <<
1977 support pointer authentication, the <<
1978 disabled with minimal loss of prote <<
1979 2756
1980 This feature works with FUNCTION_GR !! 2757 config HZ_250
1981 DYNAMIC_FTRACE_WITH_ARGS is enabled !! 2758 bool "250 HZ" if SYS_SUPPORTS_250HZ || SYS_SUPPORTS_ARBIT_HZ
1982 2759
1983 config CC_HAS_BRANCH_PROT_PAC_RET !! 2760 config HZ_256
1984 # GCC 9 or later, clang 8 or later !! 2761 bool "256 HZ" if SYS_SUPPORTS_256HZ || SYS_SUPPORTS_ARBIT_HZ
1985 def_bool $(cc-option,-mbranch-protect <<
1986 2762
1987 config CC_HAS_SIGN_RETURN_ADDRESS !! 2763 config HZ_1000
1988 # GCC 7, 8 !! 2764 bool "1000 HZ" if SYS_SUPPORTS_1000HZ || SYS_SUPPORTS_ARBIT_HZ
1989 def_bool $(cc-option,-msign-return-ad <<
1990 2765
1991 config AS_HAS_ARMV8_3 !! 2766 config HZ_1024
1992 def_bool $(cc-option,-Wa$(comma)-marc !! 2767 bool "1024 HZ" if SYS_SUPPORTS_1024HZ || SYS_SUPPORTS_ARBIT_HZ
1993 2768
1994 config AS_HAS_CFI_NEGATE_RA_STATE !! 2769 endchoice
1995 def_bool $(as-instr,.cfi_startproc\n. <<
1996 2770
1997 config AS_HAS_LDAPR !! 2771 config SYS_SUPPORTS_24HZ
1998 def_bool $(as-instr,.arch_extension r !! 2772 bool
1999 2773
2000 endmenu # "ARMv8.3 architectural features" !! 2774 config SYS_SUPPORTS_48HZ
>> 2775 bool
2001 2776
2002 menu "ARMv8.4 architectural features" !! 2777 config SYS_SUPPORTS_100HZ
>> 2778 bool
2003 2779
2004 config ARM64_AMU_EXTN !! 2780 config SYS_SUPPORTS_128HZ
2005 bool "Enable support for the Activity !! 2781 bool
2006 default y <<
2007 help <<
2008 The activity monitors extension is <<
2009 by the ARMv8.4 CPU architecture. Th <<
2010 of the activity monitors architectu <<
2011 2782
2012 To enable the use of this extension !! 2783 config SYS_SUPPORTS_250HZ
>> 2784 bool
2013 2785
2014 Note that for architectural reasons !! 2786 config SYS_SUPPORTS_256HZ
2015 support when running on CPUs that p !! 2787 bool
2016 extension. The required support is <<
2017 * Version 1.5 and later of the AR <<
2018 2788
2019 For kernels that have this configur !! 2789 config SYS_SUPPORTS_1000HZ
2020 firmware, you may need to say N her !! 2790 bool
2021 Otherwise you may experience firmwa <<
2022 accessing the counter registers. Ev <<
2023 symptoms, the values returned by th <<
2024 correctly reflect reality. Most com <<
2025 indicating that the counter is not <<
2026 2791
2027 config AS_HAS_ARMV8_4 !! 2792 config SYS_SUPPORTS_1024HZ
2028 def_bool $(cc-option,-Wa$(comma)-marc !! 2793 bool
2029 2794
2030 config ARM64_TLB_RANGE !! 2795 config SYS_SUPPORTS_ARBIT_HZ
2031 bool "Enable support for tlbi range f !! 2796 bool
2032 default y !! 2797 default y if !SYS_SUPPORTS_24HZ && \
2033 depends on AS_HAS_ARMV8_4 !! 2798 !SYS_SUPPORTS_48HZ && \
2034 help !! 2799 !SYS_SUPPORTS_100HZ && \
2035 ARMv8.4-TLBI provides TLBI invalida !! 2800 !SYS_SUPPORTS_128HZ && \
2036 range of input addresses. !! 2801 !SYS_SUPPORTS_250HZ && \
>> 2802 !SYS_SUPPORTS_256HZ && \
>> 2803 !SYS_SUPPORTS_1000HZ && \
>> 2804 !SYS_SUPPORTS_1024HZ
2037 2805
2038 The feature introduces new assembly !! 2806 config HZ
2039 support when binutils >= 2.30. !! 2807 int
>> 2808 default 24 if HZ_24
>> 2809 default 48 if HZ_48
>> 2810 default 100 if HZ_100
>> 2811 default 128 if HZ_128
>> 2812 default 250 if HZ_250
>> 2813 default 256 if HZ_256
>> 2814 default 1000 if HZ_1000
>> 2815 default 1024 if HZ_1024
>> 2816
>> 2817 config SCHED_HRTICK
>> 2818 def_bool HIGH_RES_TIMERS
>> 2819
>> 2820 source "kernel/Kconfig.preempt"
>> 2821
>> 2822 config KEXEC
>> 2823 bool "Kexec system call"
>> 2824 select KEXEC_CORE
>> 2825 help
>> 2826 kexec is a system call that implements the ability to shutdown your
>> 2827 current kernel, and to start another kernel. It is like a reboot
>> 2828 but it is independent of the system firmware. And like a reboot
>> 2829 you can start any kernel with it, not just Linux.
>> 2830
>> 2831 The name comes from the similarity to the exec system call.
>> 2832
>> 2833 It is an ongoing process to be certain the hardware in a machine
>> 2834 is properly shutdown, so do not be surprised if this code does not
>> 2835 initially work for you. As of this writing the exact hardware
>> 2836 interface is strongly in flux, so no good recommendation can be
>> 2837 made.
>> 2838
>> 2839 config CRASH_DUMP
>> 2840 bool "Kernel crash dumps"
>> 2841 help
>> 2842 Generate crash dump after being started by kexec.
>> 2843 This should be normally only set in special crash dump kernels
>> 2844 which are loaded in the main kernel with kexec-tools into
>> 2845 a specially reserved region and then later executed after
>> 2846 a crash by kdump/kexec. The crash dump kernel must be compiled
>> 2847 to a memory address not used by the main kernel or firmware using
>> 2848 PHYSICAL_START.
>> 2849
>> 2850 config PHYSICAL_START
>> 2851 hex "Physical address where the kernel is loaded"
>> 2852 default "0xffffffff84000000" if 64BIT
>> 2853 default "0x84000000" if 32BIT
>> 2854 depends on CRASH_DUMP
>> 2855 help
>> 2856 This gives the CKSEG0 or KSEG0 address where the kernel is loaded.
>> 2857 If you plan to use kernel for capturing the crash dump change
>> 2858 this value to start of the reserved region (the "X" value as
>> 2859 specified in the "crashkernel=YM@XM" command line boot parameter
>> 2860 passed to the panic-ed kernel).
>> 2861
>> 2862 config SECCOMP
>> 2863 bool "Enable seccomp to safely compute untrusted bytecode"
>> 2864 depends on PROC_FS
>> 2865 default y
>> 2866 help
>> 2867 This kernel feature is useful for number crunching applications
>> 2868 that may need to compute untrusted bytecode during their
>> 2869 execution. By using pipes or other transports made available to
>> 2870 the process as file descriptors supporting the read/write
>> 2871 syscalls, it's possible to isolate those applications in
>> 2872 their own address space using seccomp. Once seccomp is
>> 2873 enabled via /proc/<pid>/seccomp, it cannot be disabled
>> 2874 and the task is only allowed to execute a few safe syscalls
>> 2875 defined by each seccomp mode.
>> 2876
>> 2877 If unsure, say Y. Only embedded should say N here.
>> 2878
>> 2879 config MIPS_O32_FP64_SUPPORT
>> 2880 bool "Support for O32 binaries using 64-bit FP"
>> 2881 depends on 32BIT || MIPS32_O32
>> 2882 help
>> 2883 When this is enabled, the kernel will support use of 64-bit floating
>> 2884 point registers with binaries using the O32 ABI along with the
>> 2885 EF_MIPS_FP64 ELF header flag (typically built with -mfp64). On
>> 2886 32-bit MIPS systems this support is at the cost of increasing the
>> 2887 size and complexity of the compiled FPU emulator. Thus if you are
>> 2888 running a MIPS32 system and know that none of your userland binaries
>> 2889 will require 64-bit floating point, you may wish to reduce the size
>> 2890 of your kernel & potentially improve FP emulation performance by
>> 2891 saying N here.
>> 2892
>> 2893 Although binutils currently supports use of this flag the details
>> 2894 concerning its effect upon the O32 ABI in userland are still being
>> 2895 worked on. In order to avoid userland becoming dependant upon current
>> 2896 behaviour before the details have been finalised, this option should
>> 2897 be considered experimental and only enabled by those working upon
>> 2898 said details.
2040 2899
2041 endmenu # "ARMv8.4 architectural features" !! 2900 If unsure, say N.
2042 2901
2043 menu "ARMv8.5 architectural features" !! 2902 config USE_OF
>> 2903 bool
>> 2904 select OF
>> 2905 select OF_EARLY_FLATTREE
>> 2906 select IRQ_DOMAIN
2044 2907
2045 config AS_HAS_ARMV8_5 !! 2908 config BUILTIN_DTB
2046 def_bool $(cc-option,-Wa$(comma)-marc !! 2909 bool
2047 2910
2048 config ARM64_BTI !! 2911 choice
2049 bool "Branch Target Identification su !! 2912 prompt "Kernel appended dtb support" if USE_OF
2050 default y !! 2913 default MIPS_NO_APPENDED_DTB
2051 help <<
2052 Branch Target Identification (part <<
2053 provides a mechanism to limit the s <<
2054 branch instructions such as BR or B <<
2055 2914
2056 To make use of BTI on CPUs that sup !! 2915 config MIPS_NO_APPENDED_DTB
>> 2916 bool "None"
>> 2917 help
>> 2918 Do not enable appended dtb support.
>> 2919
>> 2920 config MIPS_ELF_APPENDED_DTB
>> 2921 bool "vmlinux"
>> 2922 help
>> 2923 With this option, the boot code will look for a device tree binary
>> 2924 DTB) included in the vmlinux ELF section .appended_dtb. By default
>> 2925 it is empty and the DTB can be appended using binutils command
>> 2926 objcopy:
>> 2927
>> 2928 objcopy --update-section .appended_dtb=<filename>.dtb vmlinux
>> 2929
>> 2930 This is meant as a backward compatiblity convenience for those
>> 2931 systems with a bootloader that can't be upgraded to accommodate
>> 2932 the documented boot protocol using a device tree.
>> 2933
>> 2934 config MIPS_RAW_APPENDED_DTB
>> 2935 bool "vmlinux.bin or vmlinuz.bin"
>> 2936 help
>> 2937 With this option, the boot code will look for a device tree binary
>> 2938 DTB) appended to raw vmlinux.bin or vmlinuz.bin.
>> 2939 (e.g. cat vmlinux.bin <filename>.dtb > vmlinux_w_dtb).
>> 2940
>> 2941 This is meant as a backward compatibility convenience for those
>> 2942 systems with a bootloader that can't be upgraded to accommodate
>> 2943 the documented boot protocol using a device tree.
>> 2944
>> 2945 Beware that there is very little in terms of protection against
>> 2946 this option being confused by leftover garbage in memory that might
>> 2947 look like a DTB header after a reboot if no actual DTB is appended
>> 2948 to vmlinux.bin. Do not leave this option active in a production kernel
>> 2949 if you don't intend to always append a DTB.
>> 2950 endchoice
2057 2951
2058 BTI is intended to provide compleme !! 2952 choice
2059 flow integrity protection mechanism !! 2953 prompt "Kernel command line type" if !CMDLINE_OVERRIDE
2060 authentication mechanism provided a !! 2954 default MIPS_CMDLINE_FROM_DTB if USE_OF && !ATH79 && !MACH_INGENIC && \
2061 For this reason, it does not make s !! 2955 !MIPS_MALTA && \
2062 also enabling support for pointer a !! 2956 !CAVIUM_OCTEON_SOC
2063 enabling this option you should als !! 2957 default MIPS_CMDLINE_FROM_BOOTLOADER
>> 2958
>> 2959 config MIPS_CMDLINE_FROM_DTB
>> 2960 depends on USE_OF
>> 2961 bool "Dtb kernel arguments if available"
>> 2962
>> 2963 config MIPS_CMDLINE_DTB_EXTEND
>> 2964 depends on USE_OF
>> 2965 bool "Extend dtb kernel arguments with bootloader arguments"
>> 2966
>> 2967 config MIPS_CMDLINE_FROM_BOOTLOADER
>> 2968 bool "Bootloader kernel arguments if available"
>> 2969
>> 2970 config MIPS_CMDLINE_BUILTIN_EXTEND
>> 2971 depends on CMDLINE_BOOL
>> 2972 bool "Extend builtin kernel arguments with bootloader arguments"
>> 2973 endchoice
2064 2974
2065 Userspace binaries must also be spe !! 2975 endmenu
2066 this mechanism. If you say N here <<
2067 BTI, such binaries can still run, b <<
2068 enforcement of branch destinations. <<
2069 2976
2070 config ARM64_BTI_KERNEL !! 2977 config LOCKDEP_SUPPORT
2071 bool "Use Branch Target Identificatio !! 2978 bool
2072 default y 2979 default y
2073 depends on ARM64_BTI <<
2074 depends on ARM64_PTR_AUTH_KERNEL <<
2075 depends on CC_HAS_BRANCH_PROT_PAC_RET <<
2076 # https://gcc.gnu.org/bugzilla/show_b <<
2077 depends on !CC_IS_GCC || GCC_VERSION <<
2078 # https://gcc.gnu.org/bugzilla/show_b <<
2079 depends on !CC_IS_GCC <<
2080 depends on (!FUNCTION_GRAPH_TRACER || <<
2081 help <<
2082 Build the kernel with Branch Target <<
2083 and enable enforcement of this for <<
2084 is enabled and the system supports <<
2085 modular code must have BTI enabled. <<
2086 2980
2087 config CC_HAS_BRANCH_PROT_PAC_RET_BTI !! 2981 config STACKTRACE_SUPPORT
2088 # GCC 9 or later, clang 8 or later !! 2982 bool
2089 def_bool $(cc-option,-mbranch-protect <<
2090 <<
2091 config ARM64_E0PD <<
2092 bool "Enable support for E0PD" <<
2093 default y 2983 default y
2094 help <<
2095 E0PD (part of the ARMv8.5 extension <<
2096 that EL0 accesses made via TTBR1 al <<
2097 providing similar benefits to KASLR <<
2098 with lower overhead and without dis <<
2099 kernel memory such as SPE. <<
2100 <<
2101 This option enables E0PD for TTBR1 <<
2102 <<
2103 config ARM64_AS_HAS_MTE <<
2104 # Initial support for MTE went in bin <<
2105 # ".arch armv8.5-a+memtag" below. How <<
2106 # as a late addition to the final arc <<
2107 # is only supported in the newer 2.32 <<
2108 # versions, hence the extra "stgm" in <<
2109 def_bool $(as-instr,.arch armv8.5-a+m <<
2110 2984
2111 config ARM64_MTE !! 2985 config HAVE_LATENCYTOP_SUPPORT
2112 bool "Memory Tagging Extension suppor !! 2986 bool
2113 default y 2987 default y
2114 depends on ARM64_AS_HAS_MTE && ARM64_ <<
2115 depends on AS_HAS_ARMV8_5 <<
2116 depends on AS_HAS_LSE_ATOMICS <<
2117 # Required for tag checking in the ua <<
2118 depends on ARM64_PAN <<
2119 select ARCH_HAS_SUBPAGE_FAULTS <<
2120 select ARCH_USES_HIGH_VMA_FLAGS <<
2121 select ARCH_USES_PG_ARCH_2 <<
2122 select ARCH_USES_PG_ARCH_3 <<
2123 help <<
2124 Memory Tagging (part of the ARMv8.5 <<
2125 architectural support for run-time, <<
2126 various classes of memory error to <<
2127 to eliminate vulnerabilities arisin <<
2128 languages. <<
2129 2988
2130 This option enables the support for !! 2989 config PGTABLE_LEVELS
2131 Extension at EL0 (i.e. for userspac !! 2990 int
>> 2991 default 4 if PAGE_SIZE_4KB && MIPS_VA_BITS_48
>> 2992 default 3 if 64BIT && !PAGE_SIZE_64KB
>> 2993 default 2
2132 2994
2133 Selecting this option allows the fe !! 2995 source "init/Kconfig"
2134 runtime. Any secondary CPU not impl <<
2135 not be allowed a late bring-up. <<
2136 2996
2137 Userspace binaries that want to use !! 2997 source "kernel/Kconfig.freezer"
2138 explicitly opt in. The mechanism fo <<
2139 described in: <<
2140 2998
2141 Documentation/arch/arm64/memory-tag !! 2999 menu "Bus options (PCI, PCMCIA, EISA, ISA, TC)"
2142 3000
2143 endmenu # "ARMv8.5 architectural features" !! 3001 config HW_HAS_EISA
>> 3002 bool
>> 3003 config HW_HAS_PCI
>> 3004 bool
2144 3005
2145 menu "ARMv8.7 architectural features" !! 3006 config PCI
>> 3007 bool "Support for PCI controller"
>> 3008 depends on HW_HAS_PCI
>> 3009 select PCI_DOMAINS
>> 3010 help
>> 3011 Find out whether you have a PCI motherboard. PCI is the name of a
>> 3012 bus system, i.e. the way the CPU talks to the other stuff inside
>> 3013 your box. Other bus systems are ISA, EISA, or VESA. If you have PCI,
>> 3014 say Y, otherwise N.
>> 3015
>> 3016 config HT_PCI
>> 3017 bool "Support for HT-linked PCI"
>> 3018 default y
>> 3019 depends on CPU_LOONGSON3
>> 3020 select PCI
>> 3021 select PCI_DOMAINS
>> 3022 help
>> 3023 Loongson family machines use Hyper-Transport bus for inter-core
>> 3024 connection and device connection. The PCI bus is a subordinate
>> 3025 linked at HT. Choose Y for Loongson-3 based machines.
2146 3026
2147 config ARM64_EPAN !! 3027 config PCI_DOMAINS
2148 bool "Enable support for Enhanced Pri !! 3028 bool
2149 default y <<
2150 depends on ARM64_PAN <<
2151 help <<
2152 Enhanced Privileged Access Never (E <<
2153 Access Never to be used with Execut <<
2154 <<
2155 The feature is detected at runtime, <<
2156 if the cpu does not implement the f <<
2157 endmenu # "ARMv8.7 architectural features" <<
2158 3029
2159 menu "ARMv8.9 architectural features" !! 3030 config PCI_DOMAINS_GENERIC
>> 3031 bool
2160 3032
2161 config ARM64_POE !! 3033 config PCI_DRIVERS_GENERIC
2162 prompt "Permission Overlay Extension" !! 3034 select PCI_DOMAINS_GENERIC if PCI_DOMAINS
2163 def_bool y !! 3035 bool
2164 select ARCH_USES_HIGH_VMA_FLAGS <<
2165 select ARCH_HAS_PKEYS <<
2166 help <<
2167 The Permission Overlay Extension is <<
2168 Protection Keys. Memory Protection <<
2169 enforcing page-based protections, b <<
2170 of the page tables when an applicat <<
2171 3036
2172 For details, see Documentation/core !! 3037 config PCI_DRIVERS_LEGACY
>> 3038 def_bool !PCI_DRIVERS_GENERIC
>> 3039 select NO_GENERIC_PCI_IOPORT_MAP
2173 3040
2174 If unsure, say y. !! 3041 source "drivers/pci/Kconfig"
2175 3042
2176 config ARCH_PKEY_BITS !! 3043 #
2177 int !! 3044 # ISA support is now enabled via select. Too many systems still have the one
2178 default 3 !! 3045 # or other ISA chip on the board that users don't know about so don't expect
>> 3046 # users to choose the right thing ...
>> 3047 #
>> 3048 config ISA
>> 3049 bool
2179 3050
2180 endmenu # "ARMv8.9 architectural features" !! 3051 config EISA
>> 3052 bool "EISA support"
>> 3053 depends on HW_HAS_EISA
>> 3054 select ISA
>> 3055 select GENERIC_ISA_DMA
>> 3056 ---help---
>> 3057 The Extended Industry Standard Architecture (EISA) bus was
>> 3058 developed as an open alternative to the IBM MicroChannel bus.
>> 3059
>> 3060 The EISA bus provided some of the features of the IBM MicroChannel
>> 3061 bus while maintaining backward compatibility with cards made for
>> 3062 the older ISA bus. The EISA bus saw limited use between 1988 and
>> 3063 1995 when it was made obsolete by the PCI bus.
>> 3064
>> 3065 Say Y here if you are building a kernel for an EISA-based machine.
>> 3066
>> 3067 Otherwise, say N.
>> 3068
>> 3069 source "drivers/eisa/Kconfig"
>> 3070
>> 3071 config TC
>> 3072 bool "TURBOchannel support"
>> 3073 depends on MACH_DECSTATION
>> 3074 help
>> 3075 TURBOchannel is a DEC (now Compaq (now HP)) bus for Alpha and MIPS
>> 3076 processors. TURBOchannel programming specifications are available
>> 3077 at:
>> 3078 <ftp://ftp.hp.com/pub/alphaserver/archive/triadd/>
>> 3079 and:
>> 3080 <http://www.computer-refuge.org/classiccmp/ftp.digital.com/pub/DEC/TriAdd/>
>> 3081 Linux driver support status is documented at:
>> 3082 <http://www.linux-mips.org/wiki/DECstation>
2181 3083
2182 config ARM64_SVE !! 3084 config MMU
2183 bool "ARM Scalable Vector Extension s !! 3085 bool
2184 default y 3086 default y
2185 help <<
2186 The Scalable Vector Extension (SVE) <<
2187 execution state which complements a <<
2188 of the base architecture to support <<
2189 additional vectorisation opportunit <<
2190 <<
2191 To enable use of this extension on <<
2192 <<
2193 On CPUs that support the SVE2 exten <<
2194 those too. <<
2195 <<
2196 Note that for architectural reasons <<
2197 support when running on SVE capable <<
2198 is present in: <<
2199 3087
2200 * version 1.5 and later of the AR !! 3088 config ARCH_MMAP_RND_BITS_MIN
2201 * the AArch64 boot wrapper since !! 3089 default 12 if 64BIT
2202 ("bootwrapper: SVE: Enable SVE !! 3090 default 8
2203 <<
2204 For other firmware implementations, <<
2205 or vendor. <<
2206 <<
2207 If you need the kernel to boot on S <<
2208 firmware, you may need to say N her <<
2209 fixed. Otherwise, you may experien <<
2210 booting the kernel. If unsure and <<
2211 symptoms, you should assume that it <<
2212 3091
2213 config ARM64_SME !! 3092 config ARCH_MMAP_RND_BITS_MAX
2214 bool "ARM Scalable Matrix Extension s !! 3093 default 18 if 64BIT
2215 default y !! 3094 default 15
2216 depends on ARM64_SVE <<
2217 depends on BROKEN <<
2218 help <<
2219 The Scalable Matrix Extension (SME) <<
2220 execution state which utilises a su <<
2221 instruction set, together with the <<
2222 register state capable of holding t <<
2223 enable various matrix operations. <<
2224 3095
2225 config ARM64_PSEUDO_NMI !! 3096 config ARCH_MMAP_RND_COMPAT_BITS_MIN
2226 bool "Support for NMI-like interrupts !! 3097 default 8
2227 select ARM_GIC_V3 <<
2228 help <<
2229 Adds support for mimicking Non-Mask <<
2230 GIC interrupt priority. This suppor <<
2231 ARM GIC. <<
2232 3098
2233 This high priority configuration fo !! 3099 config ARCH_MMAP_RND_COMPAT_BITS_MAX
2234 explicitly enabled by setting the k !! 3100 default 15
2235 "irqchip.gicv3_pseudo_nmi" to 1. <<
2236 3101
2237 If unsure, say N !! 3102 config I8253
>> 3103 bool
>> 3104 select CLKSRC_I8253
>> 3105 select CLKEVT_I8253
>> 3106 select MIPS_EXTERNAL_TIMER
2238 3107
2239 if ARM64_PSEUDO_NMI !! 3108 config ZONE_DMA
2240 config ARM64_DEBUG_PRIORITY_MASKING !! 3109 bool
2241 bool "Debug interrupt priority maskin <<
2242 help <<
2243 This adds runtime checks to functio <<
2244 interrupts when using priority mask <<
2245 the validity of ICC_PMR_EL1 when ca <<
2246 3110
2247 If unsure, say N !! 3111 config ZONE_DMA32
2248 endif # ARM64_PSEUDO_NMI !! 3112 bool
2249 3113
2250 config RELOCATABLE !! 3114 source "drivers/pcmcia/Kconfig"
2251 bool "Build a relocatable kernel imag <<
2252 select ARCH_HAS_RELR <<
2253 default y <<
2254 help <<
2255 This builds the kernel as a Positio <<
2256 which retains all relocation metada <<
2257 kernel binary at runtime to a diffe <<
2258 address it was linked at. <<
2259 Since AArch64 uses the RELA relocat <<
2260 relocation pass at runtime even if <<
2261 same address it was linked at. <<
2262 3115
2263 config RANDOMIZE_BASE !! 3116 config RAPIDIO
2264 bool "Randomize the address of the ke !! 3117 tristate "RapidIO support"
2265 select RELOCATABLE !! 3118 depends on PCI
>> 3119 default n
2266 help 3120 help
2267 Randomizes the virtual address at w !! 3121 If you say Y here, the kernel will include drivers and
2268 loaded, as a security feature that !! 3122 infrastructure code to support RapidIO interconnect devices.
2269 relying on knowledge of the locatio <<
2270 <<
2271 It is the bootloader's job to provi <<
2272 random u64 value in /chosen/kaslr-s <<
2273 <<
2274 When booting via the UEFI stub, it <<
2275 EFI_RNG_PROTOCOL implementation (if <<
2276 to the kernel proper. In addition, <<
2277 location of the kernel Image as wel <<
2278 3123
2279 If unsure, say N. !! 3124 source "drivers/rapidio/Kconfig"
2280 3125
2281 config RANDOMIZE_MODULE_REGION_FULL !! 3126 endmenu
2282 bool "Randomize the module region ove <<
2283 depends on RANDOMIZE_BASE <<
2284 default y <<
2285 help <<
2286 Randomizes the location of the modu <<
2287 covering the core kernel. This way, <<
2288 to leak information about the locat <<
2289 but it does imply that function cal <<
2290 kernel will need to be resolved via <<
2291 <<
2292 When this option is not set, the mo <<
2293 a limited range that contains the [ <<
2294 core kernel, so branch relocations <<
2295 the region is exhausted. In this pa <<
2296 exhaustion, modules might be able t <<
2297 3127
2298 config CC_HAVE_STACKPROTECTOR_SYSREG !! 3128 menu "Executable file formats"
2299 def_bool $(cc-option,-mstack-protecto <<
2300 3129
2301 config STACKPROTECTOR_PER_TASK !! 3130 source "fs/Kconfig.binfmt"
2302 def_bool y <<
2303 depends on STACKPROTECTOR && CC_HAVE_ <<
2304 3131
2305 config UNWIND_PATCH_PAC_INTO_SCS !! 3132 config TRAD_SIGNALS
2306 bool "Enable shadow call stack dynami !! 3133 bool
2307 # needs Clang with https://github.com <<
2308 depends on CC_IS_CLANG && CLANG_VERSI <<
2309 depends on ARM64_PTR_AUTH_KERNEL && C <<
2310 depends on SHADOW_CALL_STACK <<
2311 select UNWIND_TABLES <<
2312 select DYNAMIC_SCS <<
2313 <<
2314 config ARM64_CONTPTE <<
2315 bool "Contiguous PTE mappings for use <<
2316 depends on TRANSPARENT_HUGEPAGE <<
2317 default y <<
2318 help <<
2319 When enabled, user mappings are con <<
2320 bit, for any mappings that meet the <<
2321 This reduces TLB pressure and impro <<
2322 <<
2323 endmenu # "Kernel Features" <<
2324 <<
2325 menu "Boot options" <<
2326 <<
2327 config ARM64_ACPI_PARKING_PROTOCOL <<
2328 bool "Enable support for the ARM64 AC <<
2329 depends on ACPI <<
2330 help <<
2331 Enable support for the ARM64 ACPI p <<
2332 the kernel will not allow booting t <<
2333 protocol even if the corresponding <<
2334 MADT table. <<
2335 <<
2336 config CMDLINE <<
2337 string "Default kernel command string <<
2338 default "" <<
2339 help <<
2340 Provide a set of default command-li <<
2341 entering them here. As a minimum, y <<
2342 root device (e.g. root=/dev/nfs). <<
2343 3134
2344 choice !! 3135 config MIPS32_COMPAT
2345 prompt "Kernel command line type" !! 3136 bool
2346 depends on CMDLINE != "" <<
2347 default CMDLINE_FROM_BOOTLOADER <<
2348 help <<
2349 Choose how the kernel will handle t <<
2350 command line string. <<
2351 <<
2352 config CMDLINE_FROM_BOOTLOADER <<
2353 bool "Use bootloader kernel arguments <<
2354 help <<
2355 Uses the command-line options passe <<
2356 the boot loader doesn't provide any <<
2357 string provided in CMDLINE will be <<
2358 <<
2359 config CMDLINE_FORCE <<
2360 bool "Always use the default kernel c <<
2361 help <<
2362 Always use the default kernel comma <<
2363 loader passes other arguments to th <<
2364 This is useful if you cannot or don <<
2365 command-line options your boot load <<
2366 3137
2367 endchoice !! 3138 config COMPAT
>> 3139 bool
2368 3140
2369 config EFI_STUB !! 3141 config SYSVIPC_COMPAT
2370 bool 3142 bool
2371 3143
2372 config EFI !! 3144 config MIPS32_O32
2373 bool "UEFI runtime support" !! 3145 bool "Kernel support for o32 binaries"
2374 depends on OF && !CPU_BIG_ENDIAN !! 3146 depends on 64BIT
2375 depends on KERNEL_MODE_NEON !! 3147 select ARCH_WANT_OLD_COMPAT_IPC
2376 select ARCH_SUPPORTS_ACPI !! 3148 select COMPAT
2377 select LIBFDT !! 3149 select MIPS32_COMPAT
2378 select UCS2_STRING !! 3150 select SYSVIPC_COMPAT if SYSVIPC
2379 select EFI_PARAMS_FROM_FDT !! 3151 help
2380 select EFI_RUNTIME_WRAPPERS !! 3152 Select this option if you want to run o32 binaries. These are pure
2381 select EFI_STUB !! 3153 32-bit binaries as used by the 32-bit Linux/MIPS port. Most of
2382 select EFI_GENERIC_STUB !! 3154 existing binaries are in this format.
2383 imply IMA_SECURE_AND_OR_TRUSTED_BOOT <<
2384 default y <<
2385 help <<
2386 This option provides support for ru <<
2387 by UEFI firmware (such as non-volat <<
2388 clock, and platform reset). A UEFI <<
2389 allow the kernel to be booted as an <<
2390 is only useful on systems that have <<
2391 3155
2392 config COMPRESSED_INSTALL !! 3156 If unsure, say Y.
2393 bool "Install compressed image by def <<
2394 help <<
2395 This makes the regular "make instal <<
2396 image we built, not the legacy unco <<
2397 3157
2398 You can check that a compressed ima !! 3158 config MIPS32_N32
2399 "make zinstall" first, and verifyin !! 3159 bool "Kernel support for n32 binaries"
2400 in your environment before making " !! 3160 depends on 64BIT
2401 you. !! 3161 select COMPAT
>> 3162 select MIPS32_COMPAT
>> 3163 select SYSVIPC_COMPAT if SYSVIPC
>> 3164 help
>> 3165 Select this option if you want to run n32 binaries. These are
>> 3166 64-bit binaries using 32-bit quantities for addressing and certain
>> 3167 data that would normally be 64-bit. They are used in special
>> 3168 cases.
2402 3169
2403 config DMI !! 3170 If unsure, say N.
2404 bool "Enable support for SMBIOS (DMI) <<
2405 depends on EFI <<
2406 default y <<
2407 help <<
2408 This enables SMBIOS/DMI feature for <<
2409 3171
2410 This option is only useful on syste !! 3172 config BINFMT_ELF32
2411 However, even with this option, the !! 3173 bool
2412 continue to boot on existing non-UE !! 3174 default y if MIPS32_O32 || MIPS32_N32
>> 3175 select ELFCORE
2413 3176
2414 endmenu # "Boot options" !! 3177 endmenu
2415 3178
2416 menu "Power management options" 3179 menu "Power management options"
2417 3180
2418 source "kernel/power/Kconfig" <<
2419 <<
2420 config ARCH_HIBERNATION_POSSIBLE 3181 config ARCH_HIBERNATION_POSSIBLE
2421 def_bool y 3182 def_bool y
2422 depends on CPU_PM !! 3183 depends on SYS_SUPPORTS_HOTPLUG_CPU || !SMP
2423 <<
2424 config ARCH_HIBERNATION_HEADER <<
2425 def_bool y <<
2426 depends on HIBERNATION <<
2427 3184
2428 config ARCH_SUSPEND_POSSIBLE 3185 config ARCH_SUSPEND_POSSIBLE
2429 def_bool y 3186 def_bool y
>> 3187 depends on SYS_SUPPORTS_HOTPLUG_CPU || !SMP
>> 3188
>> 3189 source "kernel/power/Kconfig"
2430 3190
2431 endmenu # "Power management options" !! 3191 endmenu
>> 3192
>> 3193 config MIPS_EXTERNAL_TIMER
>> 3194 bool
2432 3195
2433 menu "CPU Power Management" 3196 menu "CPU Power Management"
2434 3197
>> 3198 if CPU_SUPPORTS_CPUFREQ && MIPS_EXTERNAL_TIMER
>> 3199 source "drivers/cpufreq/Kconfig"
>> 3200 endif
>> 3201
2435 source "drivers/cpuidle/Kconfig" 3202 source "drivers/cpuidle/Kconfig"
2436 3203
2437 source "drivers/cpufreq/Kconfig" !! 3204 endmenu
>> 3205
>> 3206 source "net/Kconfig"
>> 3207
>> 3208 source "drivers/Kconfig"
>> 3209
>> 3210 source "drivers/firmware/Kconfig"
>> 3211
>> 3212 source "fs/Kconfig"
>> 3213
>> 3214 source "arch/mips/Kconfig.debug"
2438 3215
2439 endmenu # "CPU Power Management" !! 3216 source "security/Kconfig"
2440 3217
2441 source "drivers/acpi/Kconfig" !! 3218 source "crypto/Kconfig"
2442 3219
2443 source "arch/arm64/kvm/Kconfig" !! 3220 source "lib/Kconfig"
2444 3221
>> 3222 source "arch/mips/kvm/Kconfig"
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