1 # SPDX-License-Identifier: GPL-2.0-only !! 1 # SPDX-License-Identifier: GPL-2.0
2 config ARM64 !! 2 config MIPS
3 def_bool y !! 3 bool
4 select ACPI_APMT if ACPI !! 4 default y
5 select ACPI_CCA_REQUIRED if ACPI <<
6 select ACPI_GENERIC_GSI if ACPI <<
7 select ACPI_GTDT if ACPI <<
8 select ACPI_HOTPLUG_CPU if ACPI_PROCES <<
9 select ACPI_IORT if ACPI <<
10 select ACPI_REDUCED_HARDWARE_ONLY if A <<
11 select ACPI_MCFG if (ACPI && PCI) <<
12 select ACPI_SPCR_TABLE if ACPI <<
13 select ACPI_PPTT if ACPI <<
14 select ARCH_HAS_DEBUG_WX <<
15 select ARCH_BINFMT_ELF_EXTRA_PHDRS <<
16 select ARCH_BINFMT_ELF_STATE 5 select ARCH_BINFMT_ELF_STATE
17 select ARCH_CORRECT_STACKTRACE_ON_KRET !! 6 select ARCH_CLOCKSOURCE_DATA
18 select ARCH_ENABLE_HUGEPAGE_MIGRATION !! 7 select ARCH_DISCARD_MEMBLOCK
19 select ARCH_ENABLE_MEMORY_HOTPLUG !! 8 select ARCH_HAS_ELF_RANDOMIZE
20 select ARCH_ENABLE_MEMORY_HOTREMOVE <<
21 select ARCH_ENABLE_SPLIT_PMD_PTLOCK if <<
22 select ARCH_ENABLE_THP_MIGRATION if TR <<
23 select ARCH_HAS_CACHE_LINE_SIZE <<
24 select ARCH_HAS_CURRENT_STACK_POINTER <<
25 select ARCH_HAS_DEBUG_VIRTUAL <<
26 select ARCH_HAS_DEBUG_VM_PGTABLE <<
27 select ARCH_HAS_DMA_OPS if XEN <<
28 select ARCH_HAS_DMA_PREP_COHERENT <<
29 select ARCH_HAS_ACPI_TABLE_UPGRADE if <<
30 select ARCH_HAS_FAST_MULTIPLIER <<
31 select ARCH_HAS_FORTIFY_SOURCE <<
32 select ARCH_HAS_GCOV_PROFILE_ALL <<
33 select ARCH_HAS_GIGANTIC_PAGE <<
34 select ARCH_HAS_KCOV <<
35 select ARCH_HAS_KERNEL_FPU_SUPPORT if <<
36 select ARCH_HAS_KEEPINITRD <<
37 select ARCH_HAS_MEMBARRIER_SYNC_CORE <<
38 select ARCH_HAS_MEM_ENCRYPT <<
39 select ARCH_HAS_NMI_SAFE_THIS_CPU_OPS <<
40 select ARCH_HAS_NON_OVERLAPPING_ADDRES <<
41 select ARCH_HAS_PTE_DEVMAP <<
42 select ARCH_HAS_PTE_SPECIAL <<
43 select ARCH_HAS_HW_PTE_YOUNG <<
44 select ARCH_HAS_SETUP_DMA_OPS <<
45 select ARCH_HAS_SET_DIRECT_MAP <<
46 select ARCH_HAS_SET_MEMORY <<
47 select ARCH_STACKWALK <<
48 select ARCH_HAS_STRICT_KERNEL_RWX <<
49 select ARCH_HAS_STRICT_MODULE_RWX <<
50 select ARCH_HAS_SYNC_DMA_FOR_DEVICE <<
51 select ARCH_HAS_SYNC_DMA_FOR_CPU <<
52 select ARCH_HAS_SYSCALL_WRAPPER <<
53 select ARCH_HAS_TICK_BROADCAST if GENE 9 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
54 select ARCH_HAS_ZONE_DMA_SET if EXPERT !! 10 select ARCH_SUPPORTS_UPROBES
55 select ARCH_HAVE_ELF_PROT !! 11 select ARCH_USE_BUILTIN_BSWAP
56 select ARCH_HAVE_NMI_SAFE_CMPXCHG !! 12 select ARCH_USE_CMPXCHG_LOCKREF if 64BIT
57 select ARCH_HAVE_TRACE_MMIO_ACCESS <<
58 select ARCH_INLINE_READ_LOCK if !PREEM <<
59 select ARCH_INLINE_READ_LOCK_BH if !PR <<
60 select ARCH_INLINE_READ_LOCK_IRQ if !P <<
61 select ARCH_INLINE_READ_LOCK_IRQSAVE i <<
62 select ARCH_INLINE_READ_UNLOCK if !PRE <<
63 select ARCH_INLINE_READ_UNLOCK_BH if ! <<
64 select ARCH_INLINE_READ_UNLOCK_IRQ if <<
65 select ARCH_INLINE_READ_UNLOCK_IRQREST <<
66 select ARCH_INLINE_WRITE_LOCK if !PREE <<
67 select ARCH_INLINE_WRITE_LOCK_BH if !P <<
68 select ARCH_INLINE_WRITE_LOCK_IRQ if ! <<
69 select ARCH_INLINE_WRITE_LOCK_IRQSAVE <<
70 select ARCH_INLINE_WRITE_UNLOCK if !PR <<
71 select ARCH_INLINE_WRITE_UNLOCK_BH if <<
72 select ARCH_INLINE_WRITE_UNLOCK_IRQ if <<
73 select ARCH_INLINE_WRITE_UNLOCK_IRQRES <<
74 select ARCH_INLINE_SPIN_TRYLOCK if !PR <<
75 select ARCH_INLINE_SPIN_TRYLOCK_BH if <<
76 select ARCH_INLINE_SPIN_LOCK if !PREEM <<
77 select ARCH_INLINE_SPIN_LOCK_BH if !PR <<
78 select ARCH_INLINE_SPIN_LOCK_IRQ if !P <<
79 select ARCH_INLINE_SPIN_LOCK_IRQSAVE i <<
80 select ARCH_INLINE_SPIN_UNLOCK if !PRE <<
81 select ARCH_INLINE_SPIN_UNLOCK_BH if ! <<
82 select ARCH_INLINE_SPIN_UNLOCK_IRQ if <<
83 select ARCH_INLINE_SPIN_UNLOCK_IRQREST <<
84 select ARCH_KEEP_MEMBLOCK <<
85 select ARCH_MHP_MEMMAP_ON_MEMORY_ENABL <<
86 select ARCH_USE_CMPXCHG_LOCKREF <<
87 select ARCH_USE_GNU_PROPERTY <<
88 select ARCH_USE_MEMTEST <<
89 select ARCH_USE_QUEUED_RWLOCKS 13 select ARCH_USE_QUEUED_RWLOCKS
90 select ARCH_USE_QUEUED_SPINLOCKS 14 select ARCH_USE_QUEUED_SPINLOCKS
91 select ARCH_USE_SYM_ANNOTATIONS !! 15 select ARCH_WANT_IPC_PARSE_VERSION
92 select ARCH_SUPPORTS_DEBUG_PAGEALLOC !! 16 select BUILDTIME_EXTABLE_SORT
93 select ARCH_SUPPORTS_HUGETLBFS <<
94 select ARCH_SUPPORTS_MEMORY_FAILURE <<
95 select ARCH_SUPPORTS_SHADOW_CALL_STACK <<
96 select ARCH_SUPPORTS_LTO_CLANG if CPU_ <<
97 select ARCH_SUPPORTS_LTO_CLANG_THIN <<
98 select ARCH_SUPPORTS_CFI_CLANG <<
99 select ARCH_SUPPORTS_ATOMIC_RMW <<
100 select ARCH_SUPPORTS_INT128 if CC_HAS_ <<
101 select ARCH_SUPPORTS_NUMA_BALANCING <<
102 select ARCH_SUPPORTS_PAGE_TABLE_CHECK <<
103 select ARCH_SUPPORTS_PER_VMA_LOCK <<
104 select ARCH_SUPPORTS_HUGE_PFNMAP if TR <<
105 select ARCH_SUPPORTS_RT <<
106 select ARCH_WANT_BATCHED_UNMAP_TLB_FLU <<
107 select ARCH_WANT_COMPAT_IPC_PARSE_VERS <<
108 select ARCH_WANT_DEFAULT_BPF_JIT <<
109 select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_ <<
110 select ARCH_WANT_FRAME_POINTERS <<
111 select ARCH_WANT_HUGE_PMD_SHARE if ARM <<
112 select ARCH_WANT_LD_ORPHAN_WARN <<
113 select ARCH_WANTS_EXECMEM_LATE if EXEC <<
114 select ARCH_WANTS_NO_INSTR <<
115 select ARCH_WANTS_THP_SWAP if ARM64_4K <<
116 select ARCH_HAS_UBSAN <<
117 select ARM_AMBA <<
118 select ARM_ARCH_TIMER <<
119 select ARM_GIC <<
120 select AUDIT_ARCH_COMPAT_GENERIC <<
121 select ARM_GIC_V2M if PCI <<
122 select ARM_GIC_V3 <<
123 select ARM_GIC_V3_ITS if PCI <<
124 select ARM_PSCI_FW <<
125 select BUILDTIME_TABLE_SORT <<
126 select CLONE_BACKWARDS 17 select CLONE_BACKWARDS
127 select COMMON_CLK !! 18 select CPU_PM if CPU_IDLE
128 select CPU_PM if (SUSPEND || CPU_IDLE) !! 19 select GENERIC_ATOMIC64 if !64BIT
129 select CPUMASK_OFFSTACK if NR_CPUS > 2 !! 20 select GENERIC_CLOCKEVENTS
130 select CRC32 !! 21 select GENERIC_CMOS_UPDATE
131 select DCACHE_WORD_ACCESS <<
132 select DYNAMIC_FTRACE if FUNCTION_TRAC <<
133 select DMA_BOUNCE_UNALIGNED_KMALLOC <<
134 select DMA_DIRECT_REMAP <<
135 select EDAC_SUPPORT <<
136 select FRAME_POINTER <<
137 select FUNCTION_ALIGNMENT_4B <<
138 select FUNCTION_ALIGNMENT_8B if DYNAMI <<
139 select GENERIC_ALLOCATOR <<
140 select GENERIC_ARCH_TOPOLOGY <<
141 select GENERIC_CLOCKEVENTS_BROADCAST <<
142 select GENERIC_CPU_AUTOPROBE 22 select GENERIC_CPU_AUTOPROBE
143 select GENERIC_CPU_DEVICES <<
144 select GENERIC_CPU_VULNERABILITIES <<
145 select GENERIC_EARLY_IOREMAP <<
146 select GENERIC_IDLE_POLL_SETUP <<
147 select GENERIC_IOREMAP <<
148 select GENERIC_IRQ_IPI <<
149 select GENERIC_IRQ_PROBE 23 select GENERIC_IRQ_PROBE
150 select GENERIC_IRQ_SHOW 24 select GENERIC_IRQ_SHOW
151 select GENERIC_IRQ_SHOW_LEVEL <<
152 select GENERIC_LIB_DEVMEM_IS_ALLOWED <<
153 select GENERIC_PCI_IOMAP 25 select GENERIC_PCI_IOMAP
154 select GENERIC_PTDUMP !! 26 select GENERIC_SCHED_CLOCK if !CAVIUM_OCTEON_SOC
155 select GENERIC_SCHED_CLOCK <<
156 select GENERIC_SMP_IDLE_THREAD 27 select GENERIC_SMP_IDLE_THREAD
157 select GENERIC_TIME_VSYSCALL 28 select GENERIC_TIME_VSYSCALL
158 select GENERIC_GETTIMEOFDAY !! 29 select HANDLE_DOMAIN_IRQ
159 select GENERIC_VDSO_TIME_NS <<
160 select HARDIRQS_SW_RESEND <<
161 select HAS_IOPORT <<
162 select HAVE_MOVE_PMD <<
163 select HAVE_MOVE_PUD <<
164 select HAVE_PCI <<
165 select HAVE_ACPI_APEI if (ACPI && EFI) <<
166 select HAVE_ALIGNED_STRUCT_PAGE <<
167 select HAVE_ARCH_AUDITSYSCALL <<
168 select HAVE_ARCH_BITREVERSE <<
169 select HAVE_ARCH_COMPILER_H <<
170 select HAVE_ARCH_HUGE_VMALLOC <<
171 select HAVE_ARCH_HUGE_VMAP <<
172 select HAVE_ARCH_JUMP_LABEL 30 select HAVE_ARCH_JUMP_LABEL
173 select HAVE_ARCH_JUMP_LABEL_RELATIVE <<
174 select HAVE_ARCH_KASAN <<
175 select HAVE_ARCH_KASAN_VMALLOC <<
176 select HAVE_ARCH_KASAN_SW_TAGS <<
177 select HAVE_ARCH_KASAN_HW_TAGS if ARM6 <<
178 # Some instrumentation may be unsound, <<
179 select HAVE_ARCH_KCSAN if EXPERT <<
180 select HAVE_ARCH_KFENCE <<
181 select HAVE_ARCH_KGDB 31 select HAVE_ARCH_KGDB
182 select HAVE_ARCH_MMAP_RND_BITS !! 32 select HAVE_ARCH_MMAP_RND_BITS if MMU
183 select HAVE_ARCH_MMAP_RND_COMPAT_BITS !! 33 select HAVE_ARCH_MMAP_RND_COMPAT_BITS if MMU && COMPAT
184 select HAVE_ARCH_PREL32_RELOCATIONS <<
185 select HAVE_ARCH_RANDOMIZE_KSTACK_OFFS <<
186 select HAVE_ARCH_SECCOMP_FILTER 34 select HAVE_ARCH_SECCOMP_FILTER
187 select HAVE_ARCH_STACKLEAK <<
188 select HAVE_ARCH_THREAD_STRUCT_WHITELI <<
189 select HAVE_ARCH_TRACEHOOK 35 select HAVE_ARCH_TRACEHOOK
190 select HAVE_ARCH_TRANSPARENT_HUGEPAGE !! 36 select HAVE_ARCH_TRANSPARENT_HUGEPAGE if CPU_SUPPORTS_HUGEPAGES && 64BIT
191 select HAVE_ARCH_VMAP_STACK !! 37 select HAVE_CBPF_JIT if (!64BIT && !CPU_MICROMIPS)
192 select HAVE_ARM_SMCCC !! 38 select HAVE_EBPF_JIT if (64BIT && !CPU_MICROMIPS)
193 select HAVE_ASM_MODVERSIONS !! 39 select HAVE_CC_STACKPROTECTOR
194 select HAVE_EBPF_JIT !! 40 select HAVE_CONTEXT_TRACKING
>> 41 select HAVE_COPY_THREAD_TLS
195 select HAVE_C_RECORDMCOUNT 42 select HAVE_C_RECORDMCOUNT
196 select HAVE_CMPXCHG_DOUBLE <<
197 select HAVE_CMPXCHG_LOCAL <<
198 select HAVE_CONTEXT_TRACKING_USER <<
199 select HAVE_DEBUG_KMEMLEAK 43 select HAVE_DEBUG_KMEMLEAK
>> 44 select HAVE_DEBUG_STACKOVERFLOW
>> 45 select HAVE_DMA_API_DEBUG
200 select HAVE_DMA_CONTIGUOUS 46 select HAVE_DMA_CONTIGUOUS
201 select HAVE_DYNAMIC_FTRACE 47 select HAVE_DYNAMIC_FTRACE
202 select HAVE_DYNAMIC_FTRACE_WITH_ARGS \ !! 48 select HAVE_EXIT_THREAD
203 if (GCC_SUPPORTS_DYNAMIC_FTRAC <<
204 CLANG_SUPPORTS_DYNAMIC_FTR <<
205 select HAVE_DYNAMIC_FTRACE_WITH_DIRECT <<
206 if DYNAMIC_FTRACE_WITH_ARGS && <<
207 select HAVE_DYNAMIC_FTRACE_WITH_CALL_O <<
208 if (DYNAMIC_FTRACE_WITH_ARGS & <<
209 (CC_IS_CLANG || !CC_OPTIMI <<
210 select FTRACE_MCOUNT_USE_PATCHABLE_FUN <<
211 if DYNAMIC_FTRACE_WITH_ARGS <<
212 select HAVE_SAMPLE_FTRACE_DIRECT <<
213 select HAVE_SAMPLE_FTRACE_DIRECT_MULTI <<
214 select HAVE_EFFICIENT_UNALIGNED_ACCESS <<
215 select HAVE_GUP_FAST <<
216 select HAVE_FTRACE_MCOUNT_RECORD 49 select HAVE_FTRACE_MCOUNT_RECORD
217 select HAVE_FUNCTION_TRACER <<
218 select HAVE_FUNCTION_ERROR_INJECTION <<
219 select HAVE_FUNCTION_GRAPH_TRACER 50 select HAVE_FUNCTION_GRAPH_TRACER
220 select HAVE_FUNCTION_GRAPH_RETVAL !! 51 select HAVE_FUNCTION_TRACER
221 select HAVE_GCC_PLUGINS !! 52 select HAVE_GENERIC_DMA_COHERENT
222 select HAVE_HARDLOCKUP_DETECTOR_PERF i !! 53 select HAVE_IDE
223 HW_PERF_EVENTS && HAVE_PERF_EV !! 54 select HAVE_IRQ_EXIT_ON_IRQ_STACK
224 select HAVE_HW_BREAKPOINT if PERF_EVEN <<
225 select HAVE_IOREMAP_PROT <<
226 select HAVE_IRQ_TIME_ACCOUNTING 55 select HAVE_IRQ_TIME_ACCOUNTING
>> 56 select HAVE_KPROBES
>> 57 select HAVE_KRETPROBES
>> 58 select HAVE_MEMBLOCK
>> 59 select HAVE_MEMBLOCK_NODE_MAP
227 select HAVE_MOD_ARCH_SPECIFIC 60 select HAVE_MOD_ARCH_SPECIFIC
228 select HAVE_NMI 61 select HAVE_NMI
>> 62 select HAVE_OPROFILE
229 select HAVE_PERF_EVENTS 63 select HAVE_PERF_EVENTS
230 select HAVE_PERF_EVENTS_NMI if ARM64_P <<
231 select HAVE_PERF_REGS <<
232 select HAVE_PERF_USER_STACK_DUMP <<
233 select HAVE_PREEMPT_DYNAMIC_KEY <<
234 select HAVE_REGS_AND_STACK_ACCESS_API 64 select HAVE_REGS_AND_STACK_ACCESS_API
235 select HAVE_POSIX_CPU_TIMERS_TASK_WORK <<
236 select HAVE_FUNCTION_ARG_ACCESS_API <<
237 select MMU_GATHER_RCU_TABLE_FREE <<
238 select HAVE_RSEQ <<
239 select HAVE_RUST if RUSTC_SUPPORTS_ARM <<
240 select HAVE_STACKPROTECTOR <<
241 select HAVE_SYSCALL_TRACEPOINTS 65 select HAVE_SYSCALL_TRACEPOINTS
242 select HAVE_KPROBES !! 66 select HAVE_VIRT_CPU_ACCOUNTING_GEN if 64BIT || !SMP
243 select HAVE_KRETPROBES <<
244 select HAVE_GENERIC_VDSO <<
245 select HOTPLUG_CORE_SYNC_DEAD if HOTPL <<
246 select IRQ_DOMAIN <<
247 select IRQ_FORCED_THREADING 67 select IRQ_FORCED_THREADING
248 select KASAN_VMALLOC if KASAN !! 68 select MODULES_USE_ELF_RELA if MODULES && 64BIT
249 select LOCK_MM_AND_FIND_VMA !! 69 select MODULES_USE_ELF_REL if MODULES
250 select MODULES_USE_ELF_RELA !! 70 select PERF_USE_VMALLOC
251 select NEED_DMA_MAP_STATE !! 71 select RTC_LIB if !MACH_LOONGSON64
252 select NEED_SG_DMA_LENGTH <<
253 select OF <<
254 select OF_EARLY_FLATTREE <<
255 select PCI_DOMAINS_GENERIC if PCI <<
256 select PCI_ECAM if (ACPI && PCI) <<
257 select PCI_SYSCALL if PCI <<
258 select POWER_RESET <<
259 select POWER_SUPPLY <<
260 select SPARSE_IRQ <<
261 select SWIOTLB <<
262 select SYSCTL_EXCEPTION_TRACE 72 select SYSCTL_EXCEPTION_TRACE
263 select THREAD_INFO_IN_TASK !! 73 select VIRT_TO_BUS
264 select HAVE_ARCH_USERFAULTFD_MINOR if <<
265 select HAVE_ARCH_USERFAULTFD_WP if USE <<
266 select TRACE_IRQFLAGS_SUPPORT <<
267 select TRACE_IRQFLAGS_NMI_SUPPORT <<
268 select HAVE_SOFTIRQ_ON_OWN_STACK <<
269 select USER_STACKTRACE_SUPPORT <<
270 select VDSO_GETRANDOM <<
271 help <<
272 ARM 64-bit (AArch64) Linux support. <<
273 <<
274 config RUSTC_SUPPORTS_ARM64 <<
275 def_bool y <<
276 depends on CPU_LITTLE_ENDIAN <<
277 # Shadow call stack is only supported <<
278 # <<
279 # When using the UNWIND_PATCH_PAC_INTO <<
280 # required due to use of the -Zfixed-x <<
281 # <<
282 # Otherwise, rustc version 1.82+ is re <<
283 # -Zsanitizer=shadow-call-stack flag. <<
284 depends on !SHADOW_CALL_STACK || RUSTC <<
285 <<
286 config CLANG_SUPPORTS_DYNAMIC_FTRACE_WITH_ARGS <<
287 def_bool CC_IS_CLANG <<
288 # https://github.com/ClangBuiltLinux/l <<
289 depends on AS_IS_GNU || (AS_IS_LLVM && <<
290 <<
291 config GCC_SUPPORTS_DYNAMIC_FTRACE_WITH_ARGS <<
292 def_bool CC_IS_GCC <<
293 depends on $(cc-option,-fpatchable-fun <<
294 <<
295 config 64BIT <<
296 def_bool y <<
297 74
298 config MMU !! 75 menu "Machine selection"
299 def_bool y <<
300 76
301 config ARM64_CONT_PTE_SHIFT !! 77 choice
302 int !! 78 prompt "System type"
303 default 5 if PAGE_SIZE_64KB !! 79 default MIPS_GENERIC
304 default 7 if PAGE_SIZE_16KB <<
305 default 4 <<
306 <<
307 config ARM64_CONT_PMD_SHIFT <<
308 int <<
309 default 5 if PAGE_SIZE_64KB <<
310 default 5 if PAGE_SIZE_16KB <<
311 default 4 <<
312 80
313 config ARCH_MMAP_RND_BITS_MIN !! 81 config MIPS_GENERIC
314 default 14 if PAGE_SIZE_64KB !! 82 bool "Generic board-agnostic MIPS kernel"
315 default 16 if PAGE_SIZE_16KB !! 83 select BOOT_RAW
316 default 18 !! 84 select BUILTIN_DTB
>> 85 select CEVT_R4K
>> 86 select CLKSRC_MIPS_GIC
>> 87 select COMMON_CLK
>> 88 select CPU_MIPSR2_IRQ_VI
>> 89 select CPU_MIPSR2_IRQ_EI
>> 90 select CSRC_R4K
>> 91 select DMA_PERDEV_COHERENT
>> 92 select HW_HAS_PCI
>> 93 select IRQ_MIPS_CPU
>> 94 select LIBFDT
>> 95 select MIPS_CPU_SCACHE
>> 96 select MIPS_GIC
>> 97 select MIPS_L1_CACHE_SHIFT_7
>> 98 select NO_EXCEPT_FILL
>> 99 select PCI_DRIVERS_GENERIC
>> 100 select PINCTRL
>> 101 select SMP_UP if SMP
>> 102 select SWAP_IO_SPACE
>> 103 select SYS_HAS_CPU_MIPS32_R1
>> 104 select SYS_HAS_CPU_MIPS32_R2
>> 105 select SYS_HAS_CPU_MIPS32_R6
>> 106 select SYS_HAS_CPU_MIPS64_R1
>> 107 select SYS_HAS_CPU_MIPS64_R2
>> 108 select SYS_HAS_CPU_MIPS64_R6
>> 109 select SYS_SUPPORTS_32BIT_KERNEL
>> 110 select SYS_SUPPORTS_64BIT_KERNEL
>> 111 select SYS_SUPPORTS_BIG_ENDIAN
>> 112 select SYS_SUPPORTS_HIGHMEM
>> 113 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 114 select SYS_SUPPORTS_MICROMIPS
>> 115 select SYS_SUPPORTS_MIPS_CPS
>> 116 select SYS_SUPPORTS_MIPS16
>> 117 select SYS_SUPPORTS_MULTITHREADING
>> 118 select SYS_SUPPORTS_RELOCATABLE
>> 119 select SYS_SUPPORTS_SMARTMIPS
>> 120 select USB_EHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
>> 121 select USB_EHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 122 select USB_OHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
>> 123 select USB_OHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 124 select USB_UHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
>> 125 select USB_UHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 126 select USE_OF
>> 127 help
>> 128 Select this to build a kernel which aims to support multiple boards,
>> 129 generally using a flattened device tree passed from the bootloader
>> 130 using the boot protocol defined in the UHI (Unified Hosting
>> 131 Interface) specification.
>> 132
>> 133 config MIPS_ALCHEMY
>> 134 bool "Alchemy processor based machines"
>> 135 select ARCH_PHYS_ADDR_T_64BIT
>> 136 select CEVT_R4K
>> 137 select CSRC_R4K
>> 138 select IRQ_MIPS_CPU
>> 139 select DMA_MAYBE_COHERENT # Au1000,1500,1100 aren't, rest is
>> 140 select SYS_HAS_CPU_MIPS32_R1
>> 141 select SYS_SUPPORTS_32BIT_KERNEL
>> 142 select SYS_SUPPORTS_APM_EMULATION
>> 143 select GPIOLIB
>> 144 select SYS_SUPPORTS_ZBOOT
>> 145 select COMMON_CLK
317 146
318 # max bits determined by the following formula !! 147 config AR7
319 # VA_BITS - PAGE_SHIFT - 3 !! 148 bool "Texas Instruments AR7"
320 config ARCH_MMAP_RND_BITS_MAX !! 149 select BOOT_ELF32
321 default 19 if ARM64_VA_BITS=36 !! 150 select DMA_NONCOHERENT
322 default 24 if ARM64_VA_BITS=39 !! 151 select CEVT_R4K
323 default 27 if ARM64_VA_BITS=42 !! 152 select CSRC_R4K
324 default 30 if ARM64_VA_BITS=47 !! 153 select IRQ_MIPS_CPU
325 default 29 if ARM64_VA_BITS=48 && ARM6 !! 154 select NO_EXCEPT_FILL
326 default 31 if ARM64_VA_BITS=48 && ARM6 !! 155 select SWAP_IO_SPACE
327 default 33 if ARM64_VA_BITS=48 !! 156 select SYS_HAS_CPU_MIPS32_R1
328 default 14 if ARM64_64K_PAGES !! 157 select SYS_HAS_EARLY_PRINTK
329 default 16 if ARM64_16K_PAGES !! 158 select SYS_SUPPORTS_32BIT_KERNEL
330 default 18 !! 159 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 160 select SYS_SUPPORTS_MIPS16
>> 161 select SYS_SUPPORTS_ZBOOT_UART16550
>> 162 select GPIOLIB
>> 163 select VLYNQ
>> 164 select HAVE_CLK
>> 165 help
>> 166 Support for the Texas Instruments AR7 System-on-a-Chip
>> 167 family: TNETD7100, 7200 and 7300.
>> 168
>> 169 config ATH25
>> 170 bool "Atheros AR231x/AR531x SoC support"
>> 171 select CEVT_R4K
>> 172 select CSRC_R4K
>> 173 select DMA_NONCOHERENT
>> 174 select IRQ_MIPS_CPU
>> 175 select IRQ_DOMAIN
>> 176 select SYS_HAS_CPU_MIPS32_R1
>> 177 select SYS_SUPPORTS_BIG_ENDIAN
>> 178 select SYS_SUPPORTS_32BIT_KERNEL
>> 179 select SYS_HAS_EARLY_PRINTK
>> 180 help
>> 181 Support for Atheros AR231x and Atheros AR531x based boards
>> 182
>> 183 config ATH79
>> 184 bool "Atheros AR71XX/AR724X/AR913X based boards"
>> 185 select ARCH_HAS_RESET_CONTROLLER
>> 186 select BOOT_RAW
>> 187 select CEVT_R4K
>> 188 select CSRC_R4K
>> 189 select DMA_NONCOHERENT
>> 190 select GPIOLIB
>> 191 select HAVE_CLK
>> 192 select COMMON_CLK
>> 193 select CLKDEV_LOOKUP
>> 194 select IRQ_MIPS_CPU
>> 195 select MIPS_MACHINE
>> 196 select SYS_HAS_CPU_MIPS32_R2
>> 197 select SYS_HAS_EARLY_PRINTK
>> 198 select SYS_SUPPORTS_32BIT_KERNEL
>> 199 select SYS_SUPPORTS_BIG_ENDIAN
>> 200 select SYS_SUPPORTS_MIPS16
>> 201 select SYS_SUPPORTS_ZBOOT_UART_PROM
>> 202 select USE_OF
>> 203 select USB_EHCI_ROOT_HUB_TT if USB_EHCI_HCD_PLATFORM
>> 204 help
>> 205 Support for the Atheros AR71XX/AR724X/AR913X SoCs.
>> 206
>> 207 config BMIPS_GENERIC
>> 208 bool "Broadcom Generic BMIPS kernel"
>> 209 select BOOT_RAW
>> 210 select NO_EXCEPT_FILL
>> 211 select USE_OF
>> 212 select CEVT_R4K
>> 213 select CSRC_R4K
>> 214 select SYNC_R4K
>> 215 select COMMON_CLK
>> 216 select BCM6345_L1_IRQ
>> 217 select BCM7038_L1_IRQ
>> 218 select BCM7120_L2_IRQ
>> 219 select BRCMSTB_L2_IRQ
>> 220 select IRQ_MIPS_CPU
>> 221 select DMA_NONCOHERENT
>> 222 select SYS_SUPPORTS_32BIT_KERNEL
>> 223 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 224 select SYS_SUPPORTS_BIG_ENDIAN
>> 225 select SYS_SUPPORTS_HIGHMEM
>> 226 select SYS_HAS_CPU_BMIPS32_3300
>> 227 select SYS_HAS_CPU_BMIPS4350
>> 228 select SYS_HAS_CPU_BMIPS4380
>> 229 select SYS_HAS_CPU_BMIPS5000
>> 230 select SWAP_IO_SPACE
>> 231 select USB_EHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
>> 232 select USB_EHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 233 select USB_OHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
>> 234 select USB_OHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 235 select HARDIRQS_SW_RESEND
>> 236 help
>> 237 Build a generic DT-based kernel image that boots on select
>> 238 BCM33xx cable modem chips, BCM63xx DSL chips, and BCM7xxx set-top
>> 239 box chips. Note that CONFIG_CPU_BIG_ENDIAN/CONFIG_CPU_LITTLE_ENDIAN
>> 240 must be set appropriately for your board.
>> 241
>> 242 config BCM47XX
>> 243 bool "Broadcom BCM47XX based boards"
>> 244 select BOOT_RAW
>> 245 select CEVT_R4K
>> 246 select CSRC_R4K
>> 247 select DMA_NONCOHERENT
>> 248 select HW_HAS_PCI
>> 249 select IRQ_MIPS_CPU
>> 250 select SYS_HAS_CPU_MIPS32_R1
>> 251 select NO_EXCEPT_FILL
>> 252 select SYS_SUPPORTS_32BIT_KERNEL
>> 253 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 254 select SYS_SUPPORTS_MIPS16
>> 255 select SYS_SUPPORTS_ZBOOT
>> 256 select SYS_HAS_EARLY_PRINTK
>> 257 select USE_GENERIC_EARLY_PRINTK_8250
>> 258 select GPIOLIB
>> 259 select LEDS_GPIO_REGISTER
>> 260 select BCM47XX_NVRAM
>> 261 select BCM47XX_SPROM
>> 262 select BCM47XX_SSB if !BCM47XX_BCMA
>> 263 help
>> 264 Support for BCM47XX based boards
>> 265
>> 266 config BCM63XX
>> 267 bool "Broadcom BCM63XX based boards"
>> 268 select BOOT_RAW
>> 269 select CEVT_R4K
>> 270 select CSRC_R4K
>> 271 select SYNC_R4K
>> 272 select DMA_NONCOHERENT
>> 273 select IRQ_MIPS_CPU
>> 274 select SYS_SUPPORTS_32BIT_KERNEL
>> 275 select SYS_SUPPORTS_BIG_ENDIAN
>> 276 select SYS_HAS_EARLY_PRINTK
>> 277 select SWAP_IO_SPACE
>> 278 select GPIOLIB
>> 279 select HAVE_CLK
>> 280 select MIPS_L1_CACHE_SHIFT_4
>> 281 select CLKDEV_LOOKUP
>> 282 help
>> 283 Support for BCM63XX based boards
>> 284
>> 285 config MIPS_COBALT
>> 286 bool "Cobalt Server"
>> 287 select CEVT_R4K
>> 288 select CSRC_R4K
>> 289 select CEVT_GT641XX
>> 290 select DMA_NONCOHERENT
>> 291 select HW_HAS_PCI
>> 292 select I8253
>> 293 select I8259
>> 294 select IRQ_MIPS_CPU
>> 295 select IRQ_GT641XX
>> 296 select PCI_GT64XXX_PCI0
>> 297 select PCI
>> 298 select SYS_HAS_CPU_NEVADA
>> 299 select SYS_HAS_EARLY_PRINTK
>> 300 select SYS_SUPPORTS_32BIT_KERNEL
>> 301 select SYS_SUPPORTS_64BIT_KERNEL
>> 302 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 303 select USE_GENERIC_EARLY_PRINTK_8250
>> 304
>> 305 config MACH_DECSTATION
>> 306 bool "DECstations"
>> 307 select BOOT_ELF32
>> 308 select CEVT_DS1287
>> 309 select CEVT_R4K if CPU_R4X00
>> 310 select CSRC_IOASIC
>> 311 select CSRC_R4K if CPU_R4X00
>> 312 select CPU_DADDI_WORKAROUNDS if 64BIT
>> 313 select CPU_R4000_WORKAROUNDS if 64BIT
>> 314 select CPU_R4400_WORKAROUNDS if 64BIT
>> 315 select DMA_NONCOHERENT
>> 316 select NO_IOPORT_MAP
>> 317 select IRQ_MIPS_CPU
>> 318 select SYS_HAS_CPU_R3000
>> 319 select SYS_HAS_CPU_R4X00
>> 320 select SYS_SUPPORTS_32BIT_KERNEL
>> 321 select SYS_SUPPORTS_64BIT_KERNEL
>> 322 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 323 select SYS_SUPPORTS_128HZ
>> 324 select SYS_SUPPORTS_256HZ
>> 325 select SYS_SUPPORTS_1024HZ
>> 326 select MIPS_L1_CACHE_SHIFT_4
>> 327 help
>> 328 This enables support for DEC's MIPS based workstations. For details
>> 329 see the Linux/MIPS FAQ on <http://www.linux-mips.org/> and the
>> 330 DECstation porting pages on <http://decstation.unix-ag.org/>.
>> 331
>> 332 If you have one of the following DECstation Models you definitely
>> 333 want to choose R4xx0 for the CPU Type:
>> 334
>> 335 DECstation 5000/50
>> 336 DECstation 5000/150
>> 337 DECstation 5000/260
>> 338 DECsystem 5900/260
>> 339
>> 340 otherwise choose R3000.
>> 341
>> 342 config MACH_JAZZ
>> 343 bool "Jazz family of machines"
>> 344 select ARCH_MIGHT_HAVE_PC_PARPORT
>> 345 select ARCH_MIGHT_HAVE_PC_SERIO
>> 346 select FW_ARC
>> 347 select FW_ARC32
>> 348 select ARCH_MAY_HAVE_PC_FDC
>> 349 select CEVT_R4K
>> 350 select CSRC_R4K
>> 351 select DEFAULT_SGI_PARTITION if CPU_BIG_ENDIAN
>> 352 select GENERIC_ISA_DMA
>> 353 select HAVE_PCSPKR_PLATFORM
>> 354 select IRQ_MIPS_CPU
>> 355 select I8253
>> 356 select I8259
>> 357 select ISA
>> 358 select SYS_HAS_CPU_R4X00
>> 359 select SYS_SUPPORTS_32BIT_KERNEL
>> 360 select SYS_SUPPORTS_64BIT_KERNEL
>> 361 select SYS_SUPPORTS_100HZ
>> 362 help
>> 363 This a family of machines based on the MIPS R4030 chipset which was
>> 364 used by several vendors to build RISC/os and Windows NT workstations.
>> 365 Members include the Acer PICA, MIPS Magnum 4000, MIPS Millennium and
>> 366 Olivetti M700-10 workstations.
>> 367
>> 368 config MACH_INGENIC
>> 369 bool "Ingenic SoC based machines"
>> 370 select SYS_SUPPORTS_32BIT_KERNEL
>> 371 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 372 select SYS_SUPPORTS_ZBOOT_UART16550
>> 373 select DMA_NONCOHERENT
>> 374 select IRQ_MIPS_CPU
>> 375 select PINCTRL
>> 376 select GPIOLIB
>> 377 select COMMON_CLK
>> 378 select GENERIC_IRQ_CHIP
>> 379 select BUILTIN_DTB
>> 380 select USE_OF
>> 381 select LIBFDT
331 382
332 config ARCH_MMAP_RND_COMPAT_BITS_MIN !! 383 config LANTIQ
333 default 7 if ARM64_64K_PAGES !! 384 bool "Lantiq based platforms"
334 default 9 if ARM64_16K_PAGES !! 385 select DMA_NONCOHERENT
335 default 11 !! 386 select IRQ_MIPS_CPU
>> 387 select CEVT_R4K
>> 388 select CSRC_R4K
>> 389 select SYS_HAS_CPU_MIPS32_R1
>> 390 select SYS_HAS_CPU_MIPS32_R2
>> 391 select SYS_SUPPORTS_BIG_ENDIAN
>> 392 select SYS_SUPPORTS_32BIT_KERNEL
>> 393 select SYS_SUPPORTS_MIPS16
>> 394 select SYS_SUPPORTS_MULTITHREADING
>> 395 select SYS_SUPPORTS_VPE_LOADER
>> 396 select SYS_HAS_EARLY_PRINTK
>> 397 select GPIOLIB
>> 398 select SWAP_IO_SPACE
>> 399 select BOOT_RAW
>> 400 select CLKDEV_LOOKUP
>> 401 select USE_OF
>> 402 select PINCTRL
>> 403 select PINCTRL_LANTIQ
>> 404 select ARCH_HAS_RESET_CONTROLLER
>> 405 select RESET_CONTROLLER
>> 406
>> 407 config LASAT
>> 408 bool "LASAT Networks platforms"
>> 409 select CEVT_R4K
>> 410 select CRC32
>> 411 select CSRC_R4K
>> 412 select DMA_NONCOHERENT
>> 413 select SYS_HAS_EARLY_PRINTK
>> 414 select HW_HAS_PCI
>> 415 select IRQ_MIPS_CPU
>> 416 select PCI_GT64XXX_PCI0
>> 417 select MIPS_NILE4
>> 418 select R5000_CPU_SCACHE
>> 419 select SYS_HAS_CPU_R5000
>> 420 select SYS_SUPPORTS_32BIT_KERNEL
>> 421 select SYS_SUPPORTS_64BIT_KERNEL if BROKEN
>> 422 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 423
>> 424 config MACH_LOONGSON32
>> 425 bool "Loongson-1 family of machines"
>> 426 select SYS_SUPPORTS_ZBOOT
>> 427 help
>> 428 This enables support for the Loongson-1 family of machines.
>> 429
>> 430 Loongson-1 is a family of 32-bit MIPS-compatible SoCs developed by
>> 431 the Institute of Computing Technology (ICT), Chinese Academy of
>> 432 Sciences (CAS).
>> 433
>> 434 config MACH_LOONGSON64
>> 435 bool "Loongson-2/3 family of machines"
>> 436 select ARCH_HAS_PHYS_TO_DMA
>> 437 select SYS_SUPPORTS_ZBOOT
>> 438 help
>> 439 This enables the support of Loongson-2/3 family of machines.
>> 440
>> 441 Loongson-2 is a family of single-core CPUs and Loongson-3 is a
>> 442 family of multi-core CPUs. They are both 64-bit general-purpose
>> 443 MIPS-compatible CPUs. Loongson-2/3 are developed by the Institute
>> 444 of Computing Technology (ICT), Chinese Academy of Sciences (CAS)
>> 445 in the People's Republic of China. The chief architect is Professor
>> 446 Weiwu Hu.
>> 447
>> 448 config MACH_PISTACHIO
>> 449 bool "IMG Pistachio SoC based boards"
>> 450 select BOOT_ELF32
>> 451 select BOOT_RAW
>> 452 select CEVT_R4K
>> 453 select CLKSRC_MIPS_GIC
>> 454 select COMMON_CLK
>> 455 select CSRC_R4K
>> 456 select DMA_NONCOHERENT
>> 457 select GPIOLIB
>> 458 select IRQ_MIPS_CPU
>> 459 select LIBFDT
>> 460 select MFD_SYSCON
>> 461 select MIPS_CPU_SCACHE
>> 462 select MIPS_GIC
>> 463 select PINCTRL
>> 464 select REGULATOR
>> 465 select SYS_HAS_CPU_MIPS32_R2
>> 466 select SYS_SUPPORTS_32BIT_KERNEL
>> 467 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 468 select SYS_SUPPORTS_MIPS_CPS
>> 469 select SYS_SUPPORTS_MULTITHREADING
>> 470 select SYS_SUPPORTS_RELOCATABLE
>> 471 select SYS_SUPPORTS_ZBOOT
>> 472 select SYS_HAS_EARLY_PRINTK
>> 473 select USE_GENERIC_EARLY_PRINTK_8250
>> 474 select USE_OF
>> 475 help
>> 476 This enables support for the IMG Pistachio SoC platform.
>> 477
>> 478 config MIPS_MALTA
>> 479 bool "MIPS Malta board"
>> 480 select ARCH_MAY_HAVE_PC_FDC
>> 481 select ARCH_MIGHT_HAVE_PC_PARPORT
>> 482 select ARCH_MIGHT_HAVE_PC_SERIO
>> 483 select BOOT_ELF32
>> 484 select BOOT_RAW
>> 485 select BUILTIN_DTB
>> 486 select CEVT_R4K
>> 487 select CSRC_R4K
>> 488 select CLKSRC_MIPS_GIC
>> 489 select COMMON_CLK
>> 490 select DMA_MAYBE_COHERENT
>> 491 select GENERIC_ISA_DMA
>> 492 select HAVE_PCSPKR_PLATFORM
>> 493 select IRQ_MIPS_CPU
>> 494 select MIPS_GIC
>> 495 select HW_HAS_PCI
>> 496 select I8253
>> 497 select I8259
>> 498 select MIPS_BONITO64
>> 499 select MIPS_CPU_SCACHE
>> 500 select MIPS_L1_CACHE_SHIFT_6
>> 501 select PCI_GT64XXX_PCI0
>> 502 select MIPS_MSC
>> 503 select SMP_UP if SMP
>> 504 select SWAP_IO_SPACE
>> 505 select SYS_HAS_CPU_MIPS32_R1
>> 506 select SYS_HAS_CPU_MIPS32_R2
>> 507 select SYS_HAS_CPU_MIPS32_R3_5
>> 508 select SYS_HAS_CPU_MIPS32_R5
>> 509 select SYS_HAS_CPU_MIPS32_R6
>> 510 select SYS_HAS_CPU_MIPS64_R1
>> 511 select SYS_HAS_CPU_MIPS64_R2
>> 512 select SYS_HAS_CPU_MIPS64_R6
>> 513 select SYS_HAS_CPU_NEVADA
>> 514 select SYS_HAS_CPU_RM7000
>> 515 select SYS_SUPPORTS_32BIT_KERNEL
>> 516 select SYS_SUPPORTS_64BIT_KERNEL
>> 517 select SYS_SUPPORTS_BIG_ENDIAN
>> 518 select SYS_SUPPORTS_HIGHMEM
>> 519 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 520 select SYS_SUPPORTS_MICROMIPS
>> 521 select SYS_SUPPORTS_MIPS_CMP
>> 522 select SYS_SUPPORTS_MIPS_CPS
>> 523 select SYS_SUPPORTS_MIPS16
>> 524 select SYS_SUPPORTS_MULTITHREADING
>> 525 select SYS_SUPPORTS_SMARTMIPS
>> 526 select SYS_SUPPORTS_VPE_LOADER
>> 527 select SYS_SUPPORTS_ZBOOT
>> 528 select SYS_SUPPORTS_RELOCATABLE
>> 529 select USE_OF
>> 530 select LIBFDT
>> 531 select ZONE_DMA32 if 64BIT
>> 532 select BUILTIN_DTB
>> 533 select LIBFDT
>> 534 help
>> 535 This enables support for the MIPS Technologies Malta evaluation
>> 536 board.
336 537
337 config ARCH_MMAP_RND_COMPAT_BITS_MAX !! 538 config MACH_PIC32
338 default 16 !! 539 bool "Microchip PIC32 Family"
>> 540 help
>> 541 This enables support for the Microchip PIC32 family of platforms.
339 542
340 config NO_IOPORT_MAP !! 543 Microchip PIC32 is a family of general-purpose 32 bit MIPS core
341 def_bool y if !PCI !! 544 microcontrollers.
>> 545
>> 546 config NEC_MARKEINS
>> 547 bool "NEC EMMA2RH Mark-eins board"
>> 548 select SOC_EMMA2RH
>> 549 select HW_HAS_PCI
>> 550 help
>> 551 This enables support for the NEC Electronics Mark-eins boards.
>> 552
>> 553 config MACH_VR41XX
>> 554 bool "NEC VR4100 series based machines"
>> 555 select CEVT_R4K
>> 556 select CSRC_R4K
>> 557 select SYS_HAS_CPU_VR41XX
>> 558 select SYS_SUPPORTS_MIPS16
>> 559 select GPIOLIB
>> 560
>> 561 config NXP_STB220
>> 562 bool "NXP STB220 board"
>> 563 select SOC_PNX833X
>> 564 help
>> 565 Support for NXP Semiconductors STB220 Development Board.
>> 566
>> 567 config NXP_STB225
>> 568 bool "NXP 225 board"
>> 569 select SOC_PNX833X
>> 570 select SOC_PNX8335
>> 571 help
>> 572 Support for NXP Semiconductors STB225 Development Board.
>> 573
>> 574 config PMC_MSP
>> 575 bool "PMC-Sierra MSP chipsets"
>> 576 select CEVT_R4K
>> 577 select CSRC_R4K
>> 578 select DMA_NONCOHERENT
>> 579 select SWAP_IO_SPACE
>> 580 select NO_EXCEPT_FILL
>> 581 select BOOT_RAW
>> 582 select SYS_HAS_CPU_MIPS32_R1
>> 583 select SYS_HAS_CPU_MIPS32_R2
>> 584 select SYS_SUPPORTS_32BIT_KERNEL
>> 585 select SYS_SUPPORTS_BIG_ENDIAN
>> 586 select SYS_SUPPORTS_MIPS16
>> 587 select IRQ_MIPS_CPU
>> 588 select SERIAL_8250
>> 589 select SERIAL_8250_CONSOLE
>> 590 select USB_EHCI_BIG_ENDIAN_MMIO
>> 591 select USB_EHCI_BIG_ENDIAN_DESC
>> 592 help
>> 593 This adds support for the PMC-Sierra family of Multi-Service
>> 594 Processor System-On-A-Chips. These parts include a number
>> 595 of integrated peripherals, interfaces and DSPs in addition to
>> 596 a variety of MIPS cores.
>> 597
>> 598 config RALINK
>> 599 bool "Ralink based machines"
>> 600 select CEVT_R4K
>> 601 select CSRC_R4K
>> 602 select BOOT_RAW
>> 603 select DMA_NONCOHERENT
>> 604 select IRQ_MIPS_CPU
>> 605 select USE_OF
>> 606 select SYS_HAS_CPU_MIPS32_R1
>> 607 select SYS_HAS_CPU_MIPS32_R2
>> 608 select SYS_SUPPORTS_32BIT_KERNEL
>> 609 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 610 select SYS_SUPPORTS_MIPS16
>> 611 select SYS_HAS_EARLY_PRINTK
>> 612 select CLKDEV_LOOKUP
>> 613 select ARCH_HAS_RESET_CONTROLLER
>> 614 select RESET_CONTROLLER
>> 615
>> 616 config SGI_IP22
>> 617 bool "SGI IP22 (Indy/Indigo2)"
>> 618 select FW_ARC
>> 619 select FW_ARC32
>> 620 select ARCH_MIGHT_HAVE_PC_SERIO
>> 621 select BOOT_ELF32
>> 622 select CEVT_R4K
>> 623 select CSRC_R4K
>> 624 select DEFAULT_SGI_PARTITION
>> 625 select DMA_NONCOHERENT
>> 626 select HW_HAS_EISA
>> 627 select I8253
>> 628 select I8259
>> 629 select IP22_CPU_SCACHE
>> 630 select IRQ_MIPS_CPU
>> 631 select GENERIC_ISA_DMA_SUPPORT_BROKEN
>> 632 select SGI_HAS_I8042
>> 633 select SGI_HAS_INDYDOG
>> 634 select SGI_HAS_HAL2
>> 635 select SGI_HAS_SEEQ
>> 636 select SGI_HAS_WD93
>> 637 select SGI_HAS_ZILOG
>> 638 select SWAP_IO_SPACE
>> 639 select SYS_HAS_CPU_R4X00
>> 640 select SYS_HAS_CPU_R5000
>> 641 #
>> 642 # Disable EARLY_PRINTK for now since it leads to overwritten prom
>> 643 # memory during early boot on some machines.
>> 644 #
>> 645 # See http://www.linux-mips.org/cgi-bin/mesg.cgi?a=linux-mips&i=20091119164009.GA15038%40deprecation.cyrius.com
>> 646 # for a more details discussion
>> 647 #
>> 648 # select SYS_HAS_EARLY_PRINTK
>> 649 select SYS_SUPPORTS_32BIT_KERNEL
>> 650 select SYS_SUPPORTS_64BIT_KERNEL
>> 651 select SYS_SUPPORTS_BIG_ENDIAN
>> 652 select MIPS_L1_CACHE_SHIFT_7
>> 653 help
>> 654 This are the SGI Indy, Challenge S and Indigo2, as well as certain
>> 655 OEM variants like the Tandem CMN B006S. To compile a Linux kernel
>> 656 that runs on these, say Y here.
>> 657
>> 658 config SGI_IP27
>> 659 bool "SGI IP27 (Origin200/2000)"
>> 660 select FW_ARC
>> 661 select FW_ARC64
>> 662 select BOOT_ELF64
>> 663 select DEFAULT_SGI_PARTITION
>> 664 select DMA_COHERENT
>> 665 select SYS_HAS_EARLY_PRINTK
>> 666 select HW_HAS_PCI
>> 667 select NR_CPUS_DEFAULT_64
>> 668 select SYS_HAS_CPU_R10000
>> 669 select SYS_SUPPORTS_64BIT_KERNEL
>> 670 select SYS_SUPPORTS_BIG_ENDIAN
>> 671 select SYS_SUPPORTS_NUMA
>> 672 select SYS_SUPPORTS_SMP
>> 673 select MIPS_L1_CACHE_SHIFT_7
>> 674 help
>> 675 This are the SGI Origin 200, Origin 2000 and Onyx 2 Graphics
>> 676 workstations. To compile a Linux kernel that runs on these, say Y
>> 677 here.
>> 678
>> 679 config SGI_IP28
>> 680 bool "SGI IP28 (Indigo2 R10k)"
>> 681 select FW_ARC
>> 682 select FW_ARC64
>> 683 select ARCH_MIGHT_HAVE_PC_SERIO
>> 684 select BOOT_ELF64
>> 685 select CEVT_R4K
>> 686 select CSRC_R4K
>> 687 select DEFAULT_SGI_PARTITION
>> 688 select DMA_NONCOHERENT
>> 689 select GENERIC_ISA_DMA_SUPPORT_BROKEN
>> 690 select IRQ_MIPS_CPU
>> 691 select HW_HAS_EISA
>> 692 select I8253
>> 693 select I8259
>> 694 select SGI_HAS_I8042
>> 695 select SGI_HAS_INDYDOG
>> 696 select SGI_HAS_HAL2
>> 697 select SGI_HAS_SEEQ
>> 698 select SGI_HAS_WD93
>> 699 select SGI_HAS_ZILOG
>> 700 select SWAP_IO_SPACE
>> 701 select SYS_HAS_CPU_R10000
>> 702 #
>> 703 # Disable EARLY_PRINTK for now since it leads to overwritten prom
>> 704 # memory during early boot on some machines.
>> 705 #
>> 706 # See http://www.linux-mips.org/cgi-bin/mesg.cgi?a=linux-mips&i=20091119164009.GA15038%40deprecation.cyrius.com
>> 707 # for a more details discussion
>> 708 #
>> 709 # select SYS_HAS_EARLY_PRINTK
>> 710 select SYS_SUPPORTS_64BIT_KERNEL
>> 711 select SYS_SUPPORTS_BIG_ENDIAN
>> 712 select MIPS_L1_CACHE_SHIFT_7
>> 713 help
>> 714 This is the SGI Indigo2 with R10000 processor. To compile a Linux
>> 715 kernel that runs on these, say Y here.
>> 716
>> 717 config SGI_IP32
>> 718 bool "SGI IP32 (O2)"
>> 719 select FW_ARC
>> 720 select FW_ARC32
>> 721 select BOOT_ELF32
>> 722 select CEVT_R4K
>> 723 select CSRC_R4K
>> 724 select DMA_NONCOHERENT
>> 725 select HW_HAS_PCI
>> 726 select IRQ_MIPS_CPU
>> 727 select R5000_CPU_SCACHE
>> 728 select RM7000_CPU_SCACHE
>> 729 select SYS_HAS_CPU_R5000
>> 730 select SYS_HAS_CPU_R10000 if BROKEN
>> 731 select SYS_HAS_CPU_RM7000
>> 732 select SYS_HAS_CPU_NEVADA
>> 733 select SYS_SUPPORTS_64BIT_KERNEL
>> 734 select SYS_SUPPORTS_BIG_ENDIAN
>> 735 help
>> 736 If you want this kernel to run on SGI O2 workstation, say Y here.
>> 737
>> 738 config SIBYTE_CRHINE
>> 739 bool "Sibyte BCM91120C-CRhine"
>> 740 select BOOT_ELF32
>> 741 select DMA_COHERENT
>> 742 select SIBYTE_BCM1120
>> 743 select SWAP_IO_SPACE
>> 744 select SYS_HAS_CPU_SB1
>> 745 select SYS_SUPPORTS_BIG_ENDIAN
>> 746 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 747
>> 748 config SIBYTE_CARMEL
>> 749 bool "Sibyte BCM91120x-Carmel"
>> 750 select BOOT_ELF32
>> 751 select DMA_COHERENT
>> 752 select SIBYTE_BCM1120
>> 753 select SWAP_IO_SPACE
>> 754 select SYS_HAS_CPU_SB1
>> 755 select SYS_SUPPORTS_BIG_ENDIAN
>> 756 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 757
>> 758 config SIBYTE_CRHONE
>> 759 bool "Sibyte BCM91125C-CRhone"
>> 760 select BOOT_ELF32
>> 761 select DMA_COHERENT
>> 762 select SIBYTE_BCM1125
>> 763 select SWAP_IO_SPACE
>> 764 select SYS_HAS_CPU_SB1
>> 765 select SYS_SUPPORTS_BIG_ENDIAN
>> 766 select SYS_SUPPORTS_HIGHMEM
>> 767 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 768
>> 769 config SIBYTE_RHONE
>> 770 bool "Sibyte BCM91125E-Rhone"
>> 771 select BOOT_ELF32
>> 772 select DMA_COHERENT
>> 773 select SIBYTE_BCM1125H
>> 774 select SWAP_IO_SPACE
>> 775 select SYS_HAS_CPU_SB1
>> 776 select SYS_SUPPORTS_BIG_ENDIAN
>> 777 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 778
>> 779 config SIBYTE_SWARM
>> 780 bool "Sibyte BCM91250A-SWARM"
>> 781 select BOOT_ELF32
>> 782 select DMA_COHERENT
>> 783 select HAVE_PATA_PLATFORM
>> 784 select SIBYTE_SB1250
>> 785 select SWAP_IO_SPACE
>> 786 select SYS_HAS_CPU_SB1
>> 787 select SYS_SUPPORTS_BIG_ENDIAN
>> 788 select SYS_SUPPORTS_HIGHMEM
>> 789 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 790 select ZONE_DMA32 if 64BIT
>> 791
>> 792 config SIBYTE_LITTLESUR
>> 793 bool "Sibyte BCM91250C2-LittleSur"
>> 794 select BOOT_ELF32
>> 795 select DMA_COHERENT
>> 796 select HAVE_PATA_PLATFORM
>> 797 select SIBYTE_SB1250
>> 798 select SWAP_IO_SPACE
>> 799 select SYS_HAS_CPU_SB1
>> 800 select SYS_SUPPORTS_BIG_ENDIAN
>> 801 select SYS_SUPPORTS_HIGHMEM
>> 802 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 803
>> 804 config SIBYTE_SENTOSA
>> 805 bool "Sibyte BCM91250E-Sentosa"
>> 806 select BOOT_ELF32
>> 807 select DMA_COHERENT
>> 808 select SIBYTE_SB1250
>> 809 select SWAP_IO_SPACE
>> 810 select SYS_HAS_CPU_SB1
>> 811 select SYS_SUPPORTS_BIG_ENDIAN
>> 812 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 813
>> 814 config SIBYTE_BIGSUR
>> 815 bool "Sibyte BCM91480B-BigSur"
>> 816 select BOOT_ELF32
>> 817 select DMA_COHERENT
>> 818 select NR_CPUS_DEFAULT_4
>> 819 select SIBYTE_BCM1x80
>> 820 select SWAP_IO_SPACE
>> 821 select SYS_HAS_CPU_SB1
>> 822 select SYS_SUPPORTS_BIG_ENDIAN
>> 823 select SYS_SUPPORTS_HIGHMEM
>> 824 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 825 select ZONE_DMA32 if 64BIT
>> 826
>> 827 config SNI_RM
>> 828 bool "SNI RM200/300/400"
>> 829 select FW_ARC if CPU_LITTLE_ENDIAN
>> 830 select FW_ARC32 if CPU_LITTLE_ENDIAN
>> 831 select FW_SNIPROM if CPU_BIG_ENDIAN
>> 832 select ARCH_MAY_HAVE_PC_FDC
>> 833 select ARCH_MIGHT_HAVE_PC_PARPORT
>> 834 select ARCH_MIGHT_HAVE_PC_SERIO
>> 835 select BOOT_ELF32
>> 836 select CEVT_R4K
>> 837 select CSRC_R4K
>> 838 select DEFAULT_SGI_PARTITION if CPU_BIG_ENDIAN
>> 839 select DMA_NONCOHERENT
>> 840 select GENERIC_ISA_DMA
>> 841 select HAVE_PCSPKR_PLATFORM
>> 842 select HW_HAS_EISA
>> 843 select HW_HAS_PCI
>> 844 select IRQ_MIPS_CPU
>> 845 select I8253
>> 846 select I8259
>> 847 select ISA
>> 848 select SWAP_IO_SPACE if CPU_BIG_ENDIAN
>> 849 select SYS_HAS_CPU_R4X00
>> 850 select SYS_HAS_CPU_R5000
>> 851 select SYS_HAS_CPU_R10000
>> 852 select R5000_CPU_SCACHE
>> 853 select SYS_HAS_EARLY_PRINTK
>> 854 select SYS_SUPPORTS_32BIT_KERNEL
>> 855 select SYS_SUPPORTS_64BIT_KERNEL
>> 856 select SYS_SUPPORTS_BIG_ENDIAN
>> 857 select SYS_SUPPORTS_HIGHMEM
>> 858 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 859 help
>> 860 The SNI RM200/300/400 are MIPS-based machines manufactured by
>> 861 Siemens Nixdorf Informationssysteme (SNI), parent company of Pyramid
>> 862 Technology and now in turn merged with Fujitsu. Say Y here to
>> 863 support this machine type.
>> 864
>> 865 config MACH_TX39XX
>> 866 bool "Toshiba TX39 series based machines"
>> 867
>> 868 config MACH_TX49XX
>> 869 bool "Toshiba TX49 series based machines"
>> 870
>> 871 config MIKROTIK_RB532
>> 872 bool "Mikrotik RB532 boards"
>> 873 select CEVT_R4K
>> 874 select CSRC_R4K
>> 875 select DMA_NONCOHERENT
>> 876 select HW_HAS_PCI
>> 877 select IRQ_MIPS_CPU
>> 878 select SYS_HAS_CPU_MIPS32_R1
>> 879 select SYS_SUPPORTS_32BIT_KERNEL
>> 880 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 881 select SWAP_IO_SPACE
>> 882 select BOOT_RAW
>> 883 select GPIOLIB
>> 884 select MIPS_L1_CACHE_SHIFT_4
>> 885 help
>> 886 Support the Mikrotik(tm) RouterBoard 532 series,
>> 887 based on the IDT RC32434 SoC.
>> 888
>> 889 config CAVIUM_OCTEON_SOC
>> 890 bool "Cavium Networks Octeon SoC based boards"
>> 891 select CEVT_R4K
>> 892 select ARCH_HAS_PHYS_TO_DMA
>> 893 select ARCH_PHYS_ADDR_T_64BIT
>> 894 select DMA_COHERENT
>> 895 select SYS_SUPPORTS_64BIT_KERNEL
>> 896 select SYS_SUPPORTS_BIG_ENDIAN
>> 897 select EDAC_SUPPORT
>> 898 select EDAC_ATOMIC_SCRUB
>> 899 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 900 select SYS_SUPPORTS_HOTPLUG_CPU if CPU_BIG_ENDIAN
>> 901 select SYS_HAS_EARLY_PRINTK
>> 902 select SYS_HAS_CPU_CAVIUM_OCTEON
>> 903 select HW_HAS_PCI
>> 904 select ZONE_DMA32
>> 905 select HOLES_IN_ZONE
>> 906 select GPIOLIB
>> 907 select LIBFDT
>> 908 select USE_OF
>> 909 select ARCH_SPARSEMEM_ENABLE
>> 910 select SYS_SUPPORTS_SMP
>> 911 select NR_CPUS_DEFAULT_64
>> 912 select MIPS_NR_CPU_NR_MAP_1024
>> 913 select BUILTIN_DTB
>> 914 select MTD_COMPLEX_MAPPINGS
>> 915 select SYS_SUPPORTS_RELOCATABLE
>> 916 help
>> 917 This option supports all of the Octeon reference boards from Cavium
>> 918 Networks. It builds a kernel that dynamically determines the Octeon
>> 919 CPU type and supports all known board reference implementations.
>> 920 Some of the supported boards are:
>> 921 EBT3000
>> 922 EBH3000
>> 923 EBH3100
>> 924 Thunder
>> 925 Kodama
>> 926 Hikari
>> 927 Say Y here for most Octeon reference boards.
>> 928
>> 929 config NLM_XLR_BOARD
>> 930 bool "Netlogic XLR/XLS based systems"
>> 931 select BOOT_ELF32
>> 932 select NLM_COMMON
>> 933 select SYS_HAS_CPU_XLR
>> 934 select SYS_SUPPORTS_SMP
>> 935 select HW_HAS_PCI
>> 936 select SWAP_IO_SPACE
>> 937 select SYS_SUPPORTS_32BIT_KERNEL
>> 938 select SYS_SUPPORTS_64BIT_KERNEL
>> 939 select ARCH_PHYS_ADDR_T_64BIT
>> 940 select SYS_SUPPORTS_BIG_ENDIAN
>> 941 select SYS_SUPPORTS_HIGHMEM
>> 942 select DMA_COHERENT
>> 943 select NR_CPUS_DEFAULT_32
>> 944 select CEVT_R4K
>> 945 select CSRC_R4K
>> 946 select IRQ_MIPS_CPU
>> 947 select ZONE_DMA32 if 64BIT
>> 948 select SYNC_R4K
>> 949 select SYS_HAS_EARLY_PRINTK
>> 950 select SYS_SUPPORTS_ZBOOT
>> 951 select SYS_SUPPORTS_ZBOOT_UART16550
>> 952 help
>> 953 Support for systems based on Netlogic XLR and XLS processors.
>> 954 Say Y here if you have a XLR or XLS based board.
>> 955
>> 956 config NLM_XLP_BOARD
>> 957 bool "Netlogic XLP based systems"
>> 958 select BOOT_ELF32
>> 959 select NLM_COMMON
>> 960 select SYS_HAS_CPU_XLP
>> 961 select SYS_SUPPORTS_SMP
>> 962 select HW_HAS_PCI
>> 963 select SYS_SUPPORTS_32BIT_KERNEL
>> 964 select SYS_SUPPORTS_64BIT_KERNEL
>> 965 select ARCH_PHYS_ADDR_T_64BIT
>> 966 select GPIOLIB
>> 967 select SYS_SUPPORTS_BIG_ENDIAN
>> 968 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 969 select SYS_SUPPORTS_HIGHMEM
>> 970 select DMA_COHERENT
>> 971 select NR_CPUS_DEFAULT_32
>> 972 select CEVT_R4K
>> 973 select CSRC_R4K
>> 974 select IRQ_MIPS_CPU
>> 975 select ZONE_DMA32 if 64BIT
>> 976 select SYNC_R4K
>> 977 select SYS_HAS_EARLY_PRINTK
>> 978 select USE_OF
>> 979 select SYS_SUPPORTS_ZBOOT
>> 980 select SYS_SUPPORTS_ZBOOT_UART16550
>> 981 help
>> 982 This board is based on Netlogic XLP Processor.
>> 983 Say Y here if you have a XLP based board.
>> 984
>> 985 config MIPS_PARAVIRT
>> 986 bool "Para-Virtualized guest system"
>> 987 select CEVT_R4K
>> 988 select CSRC_R4K
>> 989 select DMA_COHERENT
>> 990 select SYS_SUPPORTS_64BIT_KERNEL
>> 991 select SYS_SUPPORTS_32BIT_KERNEL
>> 992 select SYS_SUPPORTS_BIG_ENDIAN
>> 993 select SYS_SUPPORTS_SMP
>> 994 select NR_CPUS_DEFAULT_4
>> 995 select SYS_HAS_EARLY_PRINTK
>> 996 select SYS_HAS_CPU_MIPS32_R2
>> 997 select SYS_HAS_CPU_MIPS64_R2
>> 998 select SYS_HAS_CPU_CAVIUM_OCTEON
>> 999 select HW_HAS_PCI
>> 1000 select SWAP_IO_SPACE
>> 1001 help
>> 1002 This option supports guest running under ????
342 1003
343 config STACKTRACE_SUPPORT !! 1004 endchoice
344 def_bool y <<
345 1005
346 config ILLEGAL_POINTER_VALUE !! 1006 source "arch/mips/alchemy/Kconfig"
347 hex !! 1007 source "arch/mips/ath25/Kconfig"
348 default 0xdead000000000000 !! 1008 source "arch/mips/ath79/Kconfig"
>> 1009 source "arch/mips/bcm47xx/Kconfig"
>> 1010 source "arch/mips/bcm63xx/Kconfig"
>> 1011 source "arch/mips/bmips/Kconfig"
>> 1012 source "arch/mips/generic/Kconfig"
>> 1013 source "arch/mips/jazz/Kconfig"
>> 1014 source "arch/mips/jz4740/Kconfig"
>> 1015 source "arch/mips/lantiq/Kconfig"
>> 1016 source "arch/mips/lasat/Kconfig"
>> 1017 source "arch/mips/pic32/Kconfig"
>> 1018 source "arch/mips/pistachio/Kconfig"
>> 1019 source "arch/mips/pmcs-msp71xx/Kconfig"
>> 1020 source "arch/mips/ralink/Kconfig"
>> 1021 source "arch/mips/sgi-ip27/Kconfig"
>> 1022 source "arch/mips/sibyte/Kconfig"
>> 1023 source "arch/mips/txx9/Kconfig"
>> 1024 source "arch/mips/vr41xx/Kconfig"
>> 1025 source "arch/mips/cavium-octeon/Kconfig"
>> 1026 source "arch/mips/loongson32/Kconfig"
>> 1027 source "arch/mips/loongson64/Kconfig"
>> 1028 source "arch/mips/netlogic/Kconfig"
>> 1029 source "arch/mips/paravirt/Kconfig"
349 1030
350 config LOCKDEP_SUPPORT !! 1031 endmenu
351 def_bool y <<
352 1032
353 config GENERIC_BUG !! 1033 config RWSEM_GENERIC_SPINLOCK
354 def_bool y !! 1034 bool
355 depends on BUG !! 1035 default y
356 1036
357 config GENERIC_BUG_RELATIVE_POINTERS !! 1037 config RWSEM_XCHGADD_ALGORITHM
358 def_bool y !! 1038 bool
359 depends on GENERIC_BUG <<
360 1039
361 config GENERIC_HWEIGHT 1040 config GENERIC_HWEIGHT
362 def_bool y !! 1041 bool
363 !! 1042 default y
364 config GENERIC_CSUM <<
365 def_bool y <<
366 1043
367 config GENERIC_CALIBRATE_DELAY 1044 config GENERIC_CALIBRATE_DELAY
368 def_bool y <<
369 <<
370 config SMP <<
371 def_bool y <<
372 <<
373 config KERNEL_MODE_NEON <<
374 def_bool y <<
375 <<
376 config FIX_EARLYCON_MEM <<
377 def_bool y <<
378 <<
379 config PGTABLE_LEVELS <<
380 int <<
381 default 2 if ARM64_16K_PAGES && ARM64_ <<
382 default 2 if ARM64_64K_PAGES && ARM64_ <<
383 default 3 if ARM64_64K_PAGES && (ARM64 <<
384 default 3 if ARM64_4K_PAGES && ARM64_V <<
385 default 3 if ARM64_16K_PAGES && ARM64_ <<
386 default 4 if ARM64_16K_PAGES && (ARM64 <<
387 default 4 if !ARM64_64K_PAGES && ARM64 <<
388 default 5 if ARM64_4K_PAGES && ARM64_V <<
389 <<
390 config ARCH_SUPPORTS_UPROBES <<
391 def_bool y <<
392 <<
393 config ARCH_PROC_KCORE_TEXT <<
394 def_bool y <<
395 <<
396 config BROKEN_GAS_INST <<
397 def_bool !$(as-instr,1:\n.inst 0\n.rep <<
398 <<
399 config BUILTIN_RETURN_ADDRESS_STRIPS_PAC <<
400 bool 1045 bool
401 # Clang's __builtin_return_address() s !! 1046 default y
402 # https://github.com/llvm/llvm-project <<
403 default y if CC_IS_CLANG <<
404 # GCC's __builtin_return_address() str <<
405 # and this was backported to 10.2.0, 9 <<
406 # https://gcc.gnu.org/bugzilla/show_bu <<
407 default y if CC_IS_GCC && (GCC_VERSION <<
408 default y if CC_IS_GCC && (GCC_VERSION <<
409 default y if CC_IS_GCC && (GCC_VERSION <<
410 default y if CC_IS_GCC && (GCC_VERSION <<
411 default n <<
412 <<
413 config KASAN_SHADOW_OFFSET <<
414 hex <<
415 depends on KASAN_GENERIC || KASAN_SW_T <<
416 default 0xdfff800000000000 if (ARM64_V <<
417 default 0xdfffc00000000000 if (ARM64_V <<
418 default 0xdffffe0000000000 if ARM64_VA <<
419 default 0xdfffffc000000000 if ARM64_VA <<
420 default 0xdffffff800000000 if ARM64_VA <<
421 default 0xefff800000000000 if (ARM64_V <<
422 default 0xefffc00000000000 if (ARM64_V <<
423 default 0xeffffe0000000000 if ARM64_VA <<
424 default 0xefffffc000000000 if ARM64_VA <<
425 default 0xeffffff800000000 if ARM64_VA <<
426 default 0xffffffffffffffff <<
427 <<
428 config UNWIND_TABLES <<
429 bool <<
430 <<
431 source "arch/arm64/Kconfig.platforms" <<
432 <<
433 menu "Kernel Features" <<
434 <<
435 menu "ARM errata workarounds via the alternati <<
436 <<
437 config AMPERE_ERRATUM_AC03_CPU_38 <<
438 bool "AmpereOne: AC03_CPU_38: Certain <<
439 default y <<
440 help <<
441 This option adds an alternative code <<
442 errata AC03_CPU_38 and AC04_CPU_10 o <<
443 <<
444 The affected design reports FEAT_HAF <<
445 ID_AA64MMFR1_EL1.HAFDBS, but (V)TCR_ <<
446 as required by the architecture. The <<
447 implementation suffers from an addit <<
448 A/D updates can occur after a PTE ha <<
449 <<
450 The workaround forces KVM to explici <<
451 which avoids enabling unadvertised h <<
452 at stage-2. <<
453 <<
454 If unsure, say Y. <<
455 1047
456 config ARM64_WORKAROUND_CLEAN_CACHE !! 1048 config SCHED_OMIT_FRAME_POINTER
457 bool 1049 bool
458 <<
459 config ARM64_ERRATUM_826319 <<
460 bool "Cortex-A53: 826319: System might <<
461 default y 1050 default y
462 select ARM64_WORKAROUND_CLEAN_CACHE <<
463 help <<
464 This option adds an alternative code <<
465 erratum 826319 on Cortex-A53 parts u <<
466 AXI master interface and an L2 cache <<
467 1051
468 If a Cortex-A53 uses an AMBA AXI4 AC !! 1052 #
469 and is unable to accept a certain wr !! 1053 # Select some configuration options automatically based on user selections.
470 not progress on read data presented !! 1054 #
471 system can deadlock. !! 1055 config FW_ARC
472 !! 1056 bool
473 The workaround promotes data cache c <<
474 data cache clean-and-invalidate. <<
475 Please note that this does not neces <<
476 as it depends on the alternative fra <<
477 the kernel if an affected CPU is det <<
478 <<
479 If unsure, say Y. <<
480 <<
481 config ARM64_ERRATUM_827319 <<
482 bool "Cortex-A53: 827319: Data cache c <<
483 default y <<
484 select ARM64_WORKAROUND_CLEAN_CACHE <<
485 help <<
486 This option adds an alternative code <<
487 erratum 827319 on Cortex-A53 parts u <<
488 master interface and an L2 cache. <<
489 <<
490 Under certain conditions this erratu <<
491 to occur at the same time as another <<
492 on the AMBA 5 CHI interface, which c <<
493 interconnect reorders the two transa <<
494 <<
495 The workaround promotes data cache c <<
496 data cache clean-and-invalidate. <<
497 Please note that this does not neces <<
498 as it depends on the alternative fra <<
499 the kernel if an affected CPU is det <<
500 1057
501 If unsure, say Y. !! 1058 config ARCH_MAY_HAVE_PC_FDC
>> 1059 bool
502 1060
503 config ARM64_ERRATUM_824069 !! 1061 config BOOT_RAW
504 bool "Cortex-A53: 824069: Cache line m !! 1062 bool
505 default y <<
506 select ARM64_WORKAROUND_CLEAN_CACHE <<
507 help <<
508 This option adds an alternative code <<
509 erratum 824069 on Cortex-A53 parts u <<
510 to a coherent interconnect. <<
511 <<
512 If a Cortex-A53 processor is executi <<
513 write instruction at the same time a <<
514 cluster is executing a cache mainten <<
515 address, then this erratum might cau <<
516 incorrectly marked as dirty. <<
517 <<
518 The workaround promotes data cache c <<
519 data cache clean-and-invalidate. <<
520 Please note that this option does no <<
521 workaround, as it depends on the alt <<
522 only patch the kernel if an affected <<
523 1063
524 If unsure, say Y. !! 1064 config CEVT_BCM1480
>> 1065 bool
525 1066
526 config ARM64_ERRATUM_819472 !! 1067 config CEVT_DS1287
527 bool "Cortex-A53: 819472: Store exclus !! 1068 bool
528 default y <<
529 select ARM64_WORKAROUND_CLEAN_CACHE <<
530 help <<
531 This option adds an alternative code <<
532 erratum 819472 on Cortex-A53 parts u <<
533 present when it is connected to a co <<
534 <<
535 If the processor is executing a load <<
536 the same time as a processor in anot <<
537 maintenance operation to the same ad <<
538 cause data corruption. <<
539 <<
540 The workaround promotes data cache c <<
541 data cache clean-and-invalidate. <<
542 Please note that this does not neces <<
543 as it depends on the alternative fra <<
544 the kernel if an affected CPU is det <<
545 1069
546 If unsure, say Y. !! 1070 config CEVT_GT641XX
>> 1071 bool
547 1072
548 config ARM64_ERRATUM_832075 !! 1073 config CEVT_R4K
549 bool "Cortex-A57: 832075: possible dea !! 1074 bool
550 default y <<
551 help <<
552 This option adds an alternative code <<
553 erratum 832075 on Cortex-A57 parts u <<
554 1075
555 Affected Cortex-A57 parts might dead !! 1076 config CEVT_SB1250
556 instructions to Write-Back memory ar !! 1077 bool
557 1078
558 The workaround is to promote device !! 1079 config CEVT_TXX9
559 semantics. !! 1080 bool
560 Please note that this does not neces <<
561 as it depends on the alternative fra <<
562 the kernel if an affected CPU is det <<
563 1081
564 If unsure, say Y. !! 1082 config CSRC_BCM1480
>> 1083 bool
565 1084
566 config ARM64_ERRATUM_834220 !! 1085 config CSRC_IOASIC
567 bool "Cortex-A57: 834220: Stage 2 tran !! 1086 bool
568 depends on KVM <<
569 help <<
570 This option adds an alternative code <<
571 erratum 834220 on Cortex-A57 parts u <<
572 <<
573 Affected Cortex-A57 parts might repo <<
574 fault as the result of a Stage 1 fau <<
575 page boundary when there is a permis <<
576 alignment fault at Stage 1 and a tra <<
577 <<
578 The workaround is to verify that the <<
579 doesn't generate a fault before hand <<
580 Please note that this does not neces <<
581 as it depends on the alternative fra <<
582 the kernel if an affected CPU is det <<
583 1087
584 If unsure, say N. !! 1088 config CSRC_R4K
>> 1089 bool
585 1090
586 config ARM64_ERRATUM_1742098 !! 1091 config CSRC_SB1250
587 bool "Cortex-A57/A72: 1742098: ELR rec !! 1092 bool
588 depends on COMPAT <<
589 default y <<
590 help <<
591 This option removes the AES hwcap fo <<
592 workaround erratum 1742098 on Cortex <<
593 <<
594 Affected parts may corrupt the AES s <<
595 taken between a pair of AES instruct <<
596 are only present if the cryptography <<
597 All software should have a fallback <<
598 that don't implement the cryptograph <<
599 1093
600 If unsure, say Y. !! 1094 config MIPS_CLOCK_VSYSCALL
>> 1095 def_bool CSRC_R4K || CLKSRC_MIPS_GIC
601 1096
602 config ARM64_ERRATUM_845719 !! 1097 config GPIO_TXX9
603 bool "Cortex-A53: 845719: a load might !! 1098 select GPIOLIB
604 depends on COMPAT !! 1099 bool
605 default y <<
606 help <<
607 This option adds an alternative code <<
608 erratum 845719 on Cortex-A53 parts u <<
609 <<
610 When running a compat (AArch32) user <<
611 part, a load at EL0 from a virtual a <<
612 bits of the virtual address used by <<
613 might return incorrect data. <<
614 <<
615 The workaround is to write the conte <<
616 return to a 32-bit task. <<
617 Please note that this does not neces <<
618 as it depends on the alternative fra <<
619 the kernel if an affected CPU is det <<
620 1100
621 If unsure, say Y. !! 1101 config FW_CFE
>> 1102 bool
622 1103
623 config ARM64_ERRATUM_843419 !! 1104 config ARCH_DMA_ADDR_T_64BIT
624 bool "Cortex-A53: 843419: A load or st !! 1105 def_bool (HIGHMEM && ARCH_PHYS_ADDR_T_64BIT) || 64BIT
625 default y <<
626 help <<
627 This option links the kernel with '- <<
628 enables PLT support to replace certa <<
629 cause subsequent memory accesses to <<
630 Cortex-A53 parts up to r0p4. <<
631 1106
632 If unsure, say Y. !! 1107 config ARCH_SUPPORTS_UPROBES
>> 1108 bool
633 1109
634 config ARM64_LD_HAS_FIX_ERRATUM_843419 !! 1110 config DMA_MAYBE_COHERENT
635 def_bool $(ld-option,--fix-cortex-a53- !! 1111 select DMA_NONCOHERENT
>> 1112 bool
636 1113
637 config ARM64_ERRATUM_1024718 !! 1114 config DMA_PERDEV_COHERENT
638 bool "Cortex-A55: 1024718: Update of D !! 1115 bool
639 default y !! 1116 select DMA_MAYBE_COHERENT
640 help <<
641 This option adds a workaround for AR <<
642 1117
643 Affected Cortex-A55 cores (all revis !! 1118 config DMA_COHERENT
644 update of the hardware dirty bit whe !! 1119 bool
645 without a break-before-make. The wor <<
646 of hardware DBM locally on the affec <<
647 this erratum will continue to use th <<
648 1120
649 If unsure, say Y. !! 1121 config DMA_NONCOHERENT
>> 1122 bool
>> 1123 select NEED_DMA_MAP_STATE
650 1124
651 config ARM64_ERRATUM_1418040 !! 1125 config NEED_DMA_MAP_STATE
652 bool "Cortex-A76/Neoverse-N1: MRC read !! 1126 bool
653 default y <<
654 depends on COMPAT <<
655 help <<
656 This option adds a workaround for AR <<
657 errata 1188873 and 1418040. <<
658 1127
659 Affected Cortex-A76/Neoverse-N1 core !! 1128 config SYS_HAS_EARLY_PRINTK
660 cause register corruption when acces !! 1129 bool
661 from AArch32 userspace. <<
662 1130
663 If unsure, say Y. !! 1131 config SYS_SUPPORTS_HOTPLUG_CPU
>> 1132 bool
664 1133
665 config ARM64_WORKAROUND_SPECULATIVE_AT !! 1134 config MIPS_BONITO64
666 bool 1135 bool
667 1136
668 config ARM64_ERRATUM_1165522 !! 1137 config MIPS_MSC
669 bool "Cortex-A76: 1165522: Speculative !! 1138 bool
670 default y <<
671 select ARM64_WORKAROUND_SPECULATIVE_AT <<
672 help <<
673 This option adds a workaround for AR <<
674 1139
675 Affected Cortex-A76 cores (r0p0, r1p !! 1140 config MIPS_NILE4
676 corrupted TLBs by speculating an AT !! 1141 bool
677 context switch. <<
678 1142
679 If unsure, say Y. !! 1143 config SYNC_R4K
>> 1144 bool
680 1145
681 config ARM64_ERRATUM_1319367 !! 1146 config MIPS_MACHINE
682 bool "Cortex-A57/A72: 1319537: Specula !! 1147 def_bool n
683 default y <<
684 select ARM64_WORKAROUND_SPECULATIVE_AT <<
685 help <<
686 This option adds work arounds for AR <<
687 and A72 erratum 1319367 <<
688 1148
689 Cortex-A57 and A72 cores could end-u !! 1149 config NO_IOPORT_MAP
690 speculating an AT instruction during !! 1150 def_bool n
691 1151
692 If unsure, say Y. !! 1152 config GENERIC_CSUM
>> 1153 bool
693 1154
694 config ARM64_ERRATUM_1530923 !! 1155 config GENERIC_ISA_DMA
695 bool "Cortex-A55: 1530923: Speculative !! 1156 bool
696 default y !! 1157 select ZONE_DMA if GENERIC_ISA_DMA_SUPPORT_BROKEN=n
697 select ARM64_WORKAROUND_SPECULATIVE_AT !! 1158 select ISA_DMA_API
698 help <<
699 This option adds a workaround for AR <<
700 1159
701 Affected Cortex-A55 cores (r0p0, r0p !! 1160 config GENERIC_ISA_DMA_SUPPORT_BROKEN
702 corrupted TLBs by speculating an AT !! 1161 bool
703 context switch. !! 1162 select GENERIC_ISA_DMA
704 1163
705 If unsure, say Y. !! 1164 config ISA_DMA_API
>> 1165 bool
706 1166
707 config ARM64_WORKAROUND_REPEAT_TLBI !! 1167 config HOLES_IN_ZONE
708 bool 1168 bool
709 1169
710 config ARM64_ERRATUM_2441007 !! 1170 config SYS_SUPPORTS_RELOCATABLE
711 bool "Cortex-A55: Completion of affect !! 1171 bool
712 select ARM64_WORKAROUND_REPEAT_TLBI <<
713 help 1172 help
714 This option adds a workaround for AR !! 1173 Selected if the platform supports relocating the kernel.
715 !! 1174 The platform must provide plat_get_fdt() if it selects CONFIG_USE_OF
716 Under very rare circumstances, affec !! 1175 to allow access to command line and entropy sources.
717 may not handle a race between a brea <<
718 CPU, and another CPU accessing the s <<
719 store to a page that has been unmapp <<
720 1176
721 Work around this by adding the affec !! 1177 config MIPS_CBPF_JIT
722 TLB sequences to be done twice. !! 1178 def_bool y
723 !! 1179 depends on BPF_JIT && HAVE_CBPF_JIT
724 If unsure, say N. <<
725 1180
726 config ARM64_ERRATUM_1286807 !! 1181 config MIPS_EBPF_JIT
727 bool "Cortex-A76: Modification of the !! 1182 def_bool y
728 select ARM64_WORKAROUND_REPEAT_TLBI !! 1183 depends on BPF_JIT && HAVE_EBPF_JIT
729 help <<
730 This option adds a workaround for AR <<
731 <<
732 On the affected Cortex-A76 cores (r0 <<
733 address for a cacheable mapping of a <<
734 accessed by a core while another cor <<
735 address to a new physical page using <<
736 break-before-make sequence, then und <<
737 TLBI+DSB completes before a read usi <<
738 invalidated has been observed by oth <<
739 workaround repeats the TLBI+DSB oper <<
740 1184
741 If unsure, say N. <<
742 1185
743 config ARM64_ERRATUM_1463225 !! 1186 #
744 bool "Cortex-A76: Software Step might !! 1187 # Endianness selection. Sufficiently obscure so many users don't know what to
745 default y !! 1188 # answer,so we try hard to limit the available choices. Also the use of a
>> 1189 # choice statement should be more obvious to the user.
>> 1190 #
>> 1191 choice
>> 1192 prompt "Endianness selection"
746 help 1193 help
747 This option adds a workaround for Ar !! 1194 Some MIPS machines can be configured for either little or big endian
>> 1195 byte order. These modes require different kernels and a different
>> 1196 Linux distribution. In general there is one preferred byteorder for a
>> 1197 particular system but some systems are just as commonly used in the
>> 1198 one or the other endianness.
748 1199
749 On the affected Cortex-A76 cores (r0 !! 1200 config CPU_BIG_ENDIAN
750 of a system call instruction (SVC) c !! 1201 bool "Big endian"
751 subsequent interrupts when software !! 1202 depends on SYS_SUPPORTS_BIG_ENDIAN
752 exception handler of the system call <<
753 is enabled or VHE is in use. <<
754 1203
755 Work around the erratum by triggerin !! 1204 config CPU_LITTLE_ENDIAN
756 when handling a system call from a t !! 1205 bool "Little endian"
757 in a VHE configuration of the kernel !! 1206 depends on SYS_SUPPORTS_LITTLE_ENDIAN
758 1207
759 If unsure, say Y. !! 1208 endchoice
760 1209
761 config ARM64_ERRATUM_1542419 !! 1210 config EXPORT_UASM
762 bool "Neoverse-N1: workaround mis-orde !! 1211 bool
763 help <<
764 This option adds a workaround for AR <<
765 1542419. <<
766 1212
767 Affected Neoverse-N1 cores could exe !! 1213 config SYS_SUPPORTS_APM_EMULATION
768 modified by another CPU. The workaro !! 1214 bool
769 counterpart. <<
770 1215
771 Workaround the issue by hiding the D !! 1216 config SYS_SUPPORTS_BIG_ENDIAN
772 forces user-space to perform cache m !! 1217 bool
773 1218
774 If unsure, say N. !! 1219 config SYS_SUPPORTS_LITTLE_ENDIAN
>> 1220 bool
775 1221
776 config ARM64_ERRATUM_1508412 !! 1222 config SYS_SUPPORTS_HUGETLBFS
777 bool "Cortex-A77: 1508412: workaround !! 1223 bool
>> 1224 depends on CPU_SUPPORTS_HUGEPAGES && 64BIT
778 default y 1225 default y
779 help <<
780 This option adds a workaround for Ar <<
781 1226
782 Affected Cortex-A77 cores (r0p0, r1p !! 1227 config MIPS_HUGE_TLB_SUPPORT
783 of a store-exclusive or read of PAR_ !! 1228 def_bool HUGETLB_PAGE || TRANSPARENT_HUGEPAGE
784 non-cacheable memory attributes. The <<
785 counterpart. <<
786 1229
787 KVM guests must also have the workar !! 1230 config IRQ_CPU_RM7K
788 deadlock the system. !! 1231 bool
789 1232
790 Work around the issue by inserting D !! 1233 config IRQ_MSP_SLP
791 register reads and warning KVM users !! 1234 bool
792 to prevent a speculative PAR_EL1 rea <<
793 1235
794 If unsure, say Y. !! 1236 config IRQ_MSP_CIC
>> 1237 bool
795 1238
796 config ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MO !! 1239 config IRQ_TXX9
797 bool 1240 bool
798 1241
799 config ARM64_ERRATUM_2051678 !! 1242 config IRQ_GT641XX
800 bool "Cortex-A510: 2051678: disable Ha !! 1243 bool
801 default y <<
802 help <<
803 This options adds the workaround for <<
804 Affected Cortex-A510 might not respe <<
805 hardware update of the page table's <<
806 is to not enable the feature on affe <<
807 1244
808 If unsure, say Y. !! 1245 config PCI_GT64XXX_PCI0
>> 1246 bool
809 1247
810 config ARM64_ERRATUM_2077057 !! 1248 config NO_EXCEPT_FILL
811 bool "Cortex-A510: 2077057: workaround !! 1249 bool
812 default y <<
813 help <<
814 This option adds the workaround for <<
815 Affected Cortex-A510 may corrupt SPS <<
816 expected, but a Pointer Authenticati <<
817 erratum causes SPSR_EL1 to be copied <<
818 EL1 to cause a return to EL2 with a <<
819 1250
820 This can only happen when EL2 is ste !! 1251 config SOC_EMMA2RH
>> 1252 bool
>> 1253 select CEVT_R4K
>> 1254 select CSRC_R4K
>> 1255 select DMA_NONCOHERENT
>> 1256 select IRQ_MIPS_CPU
>> 1257 select SWAP_IO_SPACE
>> 1258 select SYS_HAS_CPU_R5500
>> 1259 select SYS_SUPPORTS_32BIT_KERNEL
>> 1260 select SYS_SUPPORTS_64BIT_KERNEL
>> 1261 select SYS_SUPPORTS_BIG_ENDIAN
821 1262
822 When these conditions occur, the SPS !! 1263 config SOC_PNX833X
823 previous guest entry, and can be res !! 1264 bool
>> 1265 select CEVT_R4K
>> 1266 select CSRC_R4K
>> 1267 select IRQ_MIPS_CPU
>> 1268 select DMA_NONCOHERENT
>> 1269 select SYS_HAS_CPU_MIPS32_R2
>> 1270 select SYS_SUPPORTS_32BIT_KERNEL
>> 1271 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 1272 select SYS_SUPPORTS_BIG_ENDIAN
>> 1273 select SYS_SUPPORTS_MIPS16
>> 1274 select CPU_MIPSR2_IRQ_VI
824 1275
825 If unsure, say Y. !! 1276 config SOC_PNX8335
>> 1277 bool
>> 1278 select SOC_PNX833X
826 1279
827 config ARM64_ERRATUM_2658417 !! 1280 config MIPS_SPRAM
828 bool "Cortex-A510: 2658417: remove BF1 !! 1281 bool
829 default y <<
830 help <<
831 This option adds the workaround for <<
832 Affected Cortex-A510 (r0p0 to r1p1) <<
833 BFMMLA or VMMLA instructions in rare <<
834 A510 CPUs are using shared neon hard <<
835 discoverable by the kernel, hide the <<
836 user-space should not be using these <<
837 1282
838 If unsure, say Y. !! 1283 config SWAP_IO_SPACE
>> 1284 bool
839 1285
840 config ARM64_ERRATUM_2119858 !! 1286 config SGI_HAS_INDYDOG
841 bool "Cortex-A710/X2: 2119858: workaro !! 1287 bool
842 default y <<
843 depends on CORESIGHT_TRBE <<
844 select ARM64_WORKAROUND_TRBE_OVERWRITE <<
845 help <<
846 This option adds the workaround for <<
847 1288
848 Affected Cortex-A710/X2 cores could !! 1289 config SGI_HAS_HAL2
849 data at the base of the buffer (poin !! 1290 bool
850 the event of a WRAP event. <<
851 1291
852 Work around the issue by always maki !! 1292 config SGI_HAS_SEEQ
853 256 bytes before enabling the buffer !! 1293 bool
854 the buffer with ETM ignore packets u <<
855 1294
856 If unsure, say Y. !! 1295 config SGI_HAS_WD93
>> 1296 bool
857 1297
858 config ARM64_ERRATUM_2139208 !! 1298 config SGI_HAS_ZILOG
859 bool "Neoverse-N2: 2139208: workaround !! 1299 bool
860 default y <<
861 depends on CORESIGHT_TRBE <<
862 select ARM64_WORKAROUND_TRBE_OVERWRITE <<
863 help <<
864 This option adds the workaround for <<
865 1300
866 Affected Neoverse-N2 cores could ove !! 1301 config SGI_HAS_I8042
867 data at the base of the buffer (poin !! 1302 bool
868 the event of a WRAP event. <<
869 1303
870 Work around the issue by always maki !! 1304 config DEFAULT_SGI_PARTITION
871 256 bytes before enabling the buffer !! 1305 bool
872 the buffer with ETM ignore packets u <<
873 1306
874 If unsure, say Y. !! 1307 config FW_ARC32
>> 1308 bool
875 1309
876 config ARM64_WORKAROUND_TSB_FLUSH_FAILURE !! 1310 config FW_SNIPROM
877 bool 1311 bool
878 1312
879 config ARM64_ERRATUM_2054223 !! 1313 config BOOT_ELF32
880 bool "Cortex-A710: 2054223: workaround !! 1314 bool
881 default y <<
882 select ARM64_WORKAROUND_TSB_FLUSH_FAIL <<
883 help <<
884 Enable workaround for ARM Cortex-A71 <<
885 1315
886 Affected cores may fail to flush the !! 1316 config MIPS_L1_CACHE_SHIFT_4
887 the PE is in trace prohibited state. !! 1317 bool
888 of the trace cached. <<
889 1318
890 Workaround is to issue two TSB conse !! 1319 config MIPS_L1_CACHE_SHIFT_5
>> 1320 bool
891 1321
892 If unsure, say Y. !! 1322 config MIPS_L1_CACHE_SHIFT_6
>> 1323 bool
893 1324
894 config ARM64_ERRATUM_2067961 !! 1325 config MIPS_L1_CACHE_SHIFT_7
895 bool "Neoverse-N2: 2067961: workaround !! 1326 bool
896 default y <<
897 select ARM64_WORKAROUND_TSB_FLUSH_FAIL <<
898 help <<
899 Enable workaround for ARM Neoverse-N <<
900 1327
901 Affected cores may fail to flush the !! 1328 config MIPS_L1_CACHE_SHIFT
902 the PE is in trace prohibited state. !! 1329 int
903 of the trace cached. !! 1330 default "7" if MIPS_L1_CACHE_SHIFT_7
>> 1331 default "6" if MIPS_L1_CACHE_SHIFT_6
>> 1332 default "5" if MIPS_L1_CACHE_SHIFT_5
>> 1333 default "4" if MIPS_L1_CACHE_SHIFT_4
>> 1334 default "5"
904 1335
905 Workaround is to issue two TSB conse !! 1336 config HAVE_STD_PC_SERIAL_PORT
>> 1337 bool
906 1338
907 If unsure, say Y. !! 1339 config ARC_CONSOLE
>> 1340 bool "ARC console support"
>> 1341 depends on SGI_IP22 || SGI_IP28 || (SNI_RM && CPU_LITTLE_ENDIAN)
908 1342
909 config ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANG !! 1343 config ARC_MEMORY
910 bool 1344 bool
911 !! 1345 depends on MACH_JAZZ || SNI_RM || SGI_IP32
912 config ARM64_ERRATUM_2253138 <<
913 bool "Neoverse-N2: 2253138: workaround <<
914 depends on CORESIGHT_TRBE <<
915 default y 1346 default y
916 select ARM64_WORKAROUND_TRBE_WRITE_OUT <<
917 help <<
918 This option adds the workaround for <<
919 1347
920 Affected Neoverse-N2 cores might wri !! 1348 config ARC_PROMLIB
921 for TRBE. Under some conditions, the !! 1349 bool
922 virtually addressed page following t !! 1350 depends on MACH_JAZZ || SNI_RM || SGI_IP22 || SGI_IP28 || SGI_IP32
923 (i.e., the TRBLIMITR_EL1.LIMIT), ins <<
924 <<
925 Work around this in the driver by al <<
926 page beyond the TRBLIMITR_EL1.LIMIT, <<
927 <<
928 If unsure, say Y. <<
929 <<
930 config ARM64_ERRATUM_2224489 <<
931 bool "Cortex-A710/X2: 2224489: workaro <<
932 depends on CORESIGHT_TRBE <<
933 default y 1351 default y
934 select ARM64_WORKAROUND_TRBE_WRITE_OUT <<
935 help <<
936 This option adds the workaround for <<
937 1352
938 Affected Cortex-A710/X2 cores might !! 1353 config FW_ARC64
939 for TRBE. Under some conditions, the !! 1354 bool
940 virtually addressed page following t <<
941 (i.e., the TRBLIMITR_EL1.LIMIT), ins <<
942 <<
943 Work around this in the driver by al <<
944 page beyond the TRBLIMITR_EL1.LIMIT, <<
945 <<
946 If unsure, say Y. <<
947 1355
948 config ARM64_ERRATUM_2441009 !! 1356 config BOOT_ELF64
949 bool "Cortex-A510: Completion of affec !! 1357 bool
950 select ARM64_WORKAROUND_REPEAT_TLBI <<
951 help <<
952 This option adds a workaround for AR <<
953 <<
954 Under very rare circumstances, affec <<
955 may not handle a race between a brea <<
956 CPU, and another CPU accessing the s <<
957 store to a page that has been unmapp <<
958 1358
959 Work around this by adding the affec !! 1359 menu "CPU selection"
960 TLB sequences to be done twice. <<
961 1360
962 If unsure, say N. !! 1361 choice
>> 1362 prompt "CPU type"
>> 1363 default CPU_R4X00
963 1364
964 config ARM64_ERRATUM_2064142 !! 1365 config CPU_LOONGSON3
965 bool "Cortex-A510: 2064142: workaround !! 1366 bool "Loongson 3 CPU"
966 depends on CORESIGHT_TRBE !! 1367 depends on SYS_HAS_CPU_LOONGSON3
967 default y !! 1368 select CPU_SUPPORTS_64BIT_KERNEL
>> 1369 select CPU_SUPPORTS_HIGHMEM
>> 1370 select CPU_SUPPORTS_HUGEPAGES
>> 1371 select WEAK_ORDERING
>> 1372 select WEAK_REORDERING_BEYOND_LLSC
>> 1373 select MIPS_PGD_C0_CONTEXT
>> 1374 select MIPS_L1_CACHE_SHIFT_6
>> 1375 select GPIOLIB
968 help 1376 help
969 This option adds the workaround for !! 1377 The Loongson 3 processor implements the MIPS64R2 instruction
>> 1378 set with many extensions.
970 1379
971 Affected Cortex-A510 core might fail !! 1380 config LOONGSON3_ENHANCEMENT
972 TRBE has been disabled. Under some c !! 1381 bool "New Loongson 3 CPU Enhancements"
973 writes into TRBE registers TRBLIMITR !! 1382 default n
974 and TRBTRG_EL1 will be ignored and w !! 1383 select CPU_MIPSR2
975 !! 1384 select CPU_HAS_PREFETCH
976 Work around this in the driver by ex !! 1385 depends on CPU_LOONGSON3
977 is stopped and before performing a s !! 1386 help
978 registers. !! 1387 New Loongson 3 CPU (since Loongson-3A R2, as opposed to Loongson-3A
>> 1388 R1, Loongson-3B R1 and Loongson-3B R2) has many enhancements, such as
>> 1389 FTLB, L1-VCache, EI/DI/Wait/Prefetch instruction, DSP/DSPv2 ASE, User
>> 1390 Local register, Read-Inhibit/Execute-Inhibit, SFB (Store Fill Buffer),
>> 1391 Fast TLB refill support, etc.
>> 1392
>> 1393 This option enable those enhancements which are not probed at run
>> 1394 time. If you want a generic kernel to run on all Loongson 3 machines,
>> 1395 please say 'N' here. If you want a high-performance kernel to run on
>> 1396 new Loongson 3 machines only, please say 'Y' here.
>> 1397
>> 1398 config CPU_LOONGSON2E
>> 1399 bool "Loongson 2E"
>> 1400 depends on SYS_HAS_CPU_LOONGSON2E
>> 1401 select CPU_LOONGSON2
>> 1402 help
>> 1403 The Loongson 2E processor implements the MIPS III instruction set
>> 1404 with many extensions.
>> 1405
>> 1406 It has an internal FPGA northbridge, which is compatible to
>> 1407 bonito64.
>> 1408
>> 1409 config CPU_LOONGSON2F
>> 1410 bool "Loongson 2F"
>> 1411 depends on SYS_HAS_CPU_LOONGSON2F
>> 1412 select CPU_LOONGSON2
>> 1413 select GPIOLIB
>> 1414 help
>> 1415 The Loongson 2F processor implements the MIPS III instruction set
>> 1416 with many extensions.
>> 1417
>> 1418 Loongson2F have built-in DDR2 and PCIX controller. The PCIX controller
>> 1419 have a similar programming interface with FPGA northbridge used in
>> 1420 Loongson2E.
>> 1421
>> 1422 config CPU_LOONGSON1B
>> 1423 bool "Loongson 1B"
>> 1424 depends on SYS_HAS_CPU_LOONGSON1B
>> 1425 select CPU_LOONGSON1
>> 1426 select LEDS_GPIO_REGISTER
>> 1427 help
>> 1428 The Loongson 1B is a 32-bit SoC, which implements the MIPS32
>> 1429 release 2 instruction set.
>> 1430
>> 1431 config CPU_LOONGSON1C
>> 1432 bool "Loongson 1C"
>> 1433 depends on SYS_HAS_CPU_LOONGSON1C
>> 1434 select CPU_LOONGSON1
>> 1435 select LEDS_GPIO_REGISTER
>> 1436 help
>> 1437 The Loongson 1C is a 32-bit SoC, which implements the MIPS32
>> 1438 release 2 instruction set.
>> 1439
>> 1440 config CPU_MIPS32_R1
>> 1441 bool "MIPS32 Release 1"
>> 1442 depends on SYS_HAS_CPU_MIPS32_R1
>> 1443 select CPU_HAS_PREFETCH
>> 1444 select CPU_SUPPORTS_32BIT_KERNEL
>> 1445 select CPU_SUPPORTS_HIGHMEM
>> 1446 help
>> 1447 Choose this option to build a kernel for release 1 or later of the
>> 1448 MIPS32 architecture. Most modern embedded systems with a 32-bit
>> 1449 MIPS processor are based on a MIPS32 processor. If you know the
>> 1450 specific type of processor in your system, choose those that one
>> 1451 otherwise CPU_MIPS32_R1 is a safe bet for any MIPS32 system.
>> 1452 Release 2 of the MIPS32 architecture is available since several
>> 1453 years so chances are you even have a MIPS32 Release 2 processor
>> 1454 in which case you should choose CPU_MIPS32_R2 instead for better
>> 1455 performance.
>> 1456
>> 1457 config CPU_MIPS32_R2
>> 1458 bool "MIPS32 Release 2"
>> 1459 depends on SYS_HAS_CPU_MIPS32_R2
>> 1460 select CPU_HAS_PREFETCH
>> 1461 select CPU_SUPPORTS_32BIT_KERNEL
>> 1462 select CPU_SUPPORTS_HIGHMEM
>> 1463 select CPU_SUPPORTS_MSA
>> 1464 select HAVE_KVM
>> 1465 help
>> 1466 Choose this option to build a kernel for release 2 or later of the
>> 1467 MIPS32 architecture. Most modern embedded systems with a 32-bit
>> 1468 MIPS processor are based on a MIPS32 processor. If you know the
>> 1469 specific type of processor in your system, choose those that one
>> 1470 otherwise CPU_MIPS32_R1 is a safe bet for any MIPS32 system.
>> 1471
>> 1472 config CPU_MIPS32_R6
>> 1473 bool "MIPS32 Release 6"
>> 1474 depends on SYS_HAS_CPU_MIPS32_R6
>> 1475 select CPU_HAS_PREFETCH
>> 1476 select CPU_SUPPORTS_32BIT_KERNEL
>> 1477 select CPU_SUPPORTS_HIGHMEM
>> 1478 select CPU_SUPPORTS_MSA
>> 1479 select GENERIC_CSUM
>> 1480 select HAVE_KVM
>> 1481 select MIPS_O32_FP64_SUPPORT
>> 1482 help
>> 1483 Choose this option to build a kernel for release 6 or later of the
>> 1484 MIPS32 architecture. New MIPS processors, starting with the Warrior
>> 1485 family, are based on a MIPS32r6 processor. If you own an older
>> 1486 processor, you probably need to select MIPS32r1 or MIPS32r2 instead.
>> 1487
>> 1488 config CPU_MIPS64_R1
>> 1489 bool "MIPS64 Release 1"
>> 1490 depends on SYS_HAS_CPU_MIPS64_R1
>> 1491 select CPU_HAS_PREFETCH
>> 1492 select CPU_SUPPORTS_32BIT_KERNEL
>> 1493 select CPU_SUPPORTS_64BIT_KERNEL
>> 1494 select CPU_SUPPORTS_HIGHMEM
>> 1495 select CPU_SUPPORTS_HUGEPAGES
>> 1496 help
>> 1497 Choose this option to build a kernel for release 1 or later of the
>> 1498 MIPS64 architecture. Many modern embedded systems with a 64-bit
>> 1499 MIPS processor are based on a MIPS64 processor. If you know the
>> 1500 specific type of processor in your system, choose those that one
>> 1501 otherwise CPU_MIPS64_R1 is a safe bet for any MIPS64 system.
>> 1502 Release 2 of the MIPS64 architecture is available since several
>> 1503 years so chances are you even have a MIPS64 Release 2 processor
>> 1504 in which case you should choose CPU_MIPS64_R2 instead for better
>> 1505 performance.
>> 1506
>> 1507 config CPU_MIPS64_R2
>> 1508 bool "MIPS64 Release 2"
>> 1509 depends on SYS_HAS_CPU_MIPS64_R2
>> 1510 select CPU_HAS_PREFETCH
>> 1511 select CPU_SUPPORTS_32BIT_KERNEL
>> 1512 select CPU_SUPPORTS_64BIT_KERNEL
>> 1513 select CPU_SUPPORTS_HIGHMEM
>> 1514 select CPU_SUPPORTS_HUGEPAGES
>> 1515 select CPU_SUPPORTS_MSA
>> 1516 select HAVE_KVM
>> 1517 help
>> 1518 Choose this option to build a kernel for release 2 or later of the
>> 1519 MIPS64 architecture. Many modern embedded systems with a 64-bit
>> 1520 MIPS processor are based on a MIPS64 processor. If you know the
>> 1521 specific type of processor in your system, choose those that one
>> 1522 otherwise CPU_MIPS64_R1 is a safe bet for any MIPS64 system.
>> 1523
>> 1524 config CPU_MIPS64_R6
>> 1525 bool "MIPS64 Release 6"
>> 1526 depends on SYS_HAS_CPU_MIPS64_R6
>> 1527 select CPU_HAS_PREFETCH
>> 1528 select CPU_SUPPORTS_32BIT_KERNEL
>> 1529 select CPU_SUPPORTS_64BIT_KERNEL
>> 1530 select CPU_SUPPORTS_HIGHMEM
>> 1531 select CPU_SUPPORTS_MSA
>> 1532 select GENERIC_CSUM
>> 1533 select MIPS_O32_FP64_SUPPORT if 32BIT || MIPS32_O32
>> 1534 select HAVE_KVM
>> 1535 help
>> 1536 Choose this option to build a kernel for release 6 or later of the
>> 1537 MIPS64 architecture. New MIPS processors, starting with the Warrior
>> 1538 family, are based on a MIPS64r6 processor. If you own an older
>> 1539 processor, you probably need to select MIPS64r1 or MIPS64r2 instead.
>> 1540
>> 1541 config CPU_R3000
>> 1542 bool "R3000"
>> 1543 depends on SYS_HAS_CPU_R3000
>> 1544 select CPU_HAS_WB
>> 1545 select CPU_SUPPORTS_32BIT_KERNEL
>> 1546 select CPU_SUPPORTS_HIGHMEM
>> 1547 help
>> 1548 Please make sure to pick the right CPU type. Linux/MIPS is not
>> 1549 designed to be generic, i.e. Kernels compiled for R3000 CPUs will
>> 1550 *not* work on R4000 machines and vice versa. However, since most
>> 1551 of the supported machines have an R4000 (or similar) CPU, R4x00
>> 1552 might be a safe bet. If the resulting kernel does not work,
>> 1553 try to recompile with R3000.
>> 1554
>> 1555 config CPU_TX39XX
>> 1556 bool "R39XX"
>> 1557 depends on SYS_HAS_CPU_TX39XX
>> 1558 select CPU_SUPPORTS_32BIT_KERNEL
>> 1559
>> 1560 config CPU_VR41XX
>> 1561 bool "R41xx"
>> 1562 depends on SYS_HAS_CPU_VR41XX
>> 1563 select CPU_SUPPORTS_32BIT_KERNEL
>> 1564 select CPU_SUPPORTS_64BIT_KERNEL
>> 1565 help
>> 1566 The options selects support for the NEC VR4100 series of processors.
>> 1567 Only choose this option if you have one of these processors as a
>> 1568 kernel built with this option will not run on any other type of
>> 1569 processor or vice versa.
>> 1570
>> 1571 config CPU_R4300
>> 1572 bool "R4300"
>> 1573 depends on SYS_HAS_CPU_R4300
>> 1574 select CPU_SUPPORTS_32BIT_KERNEL
>> 1575 select CPU_SUPPORTS_64BIT_KERNEL
>> 1576 help
>> 1577 MIPS Technologies R4300-series processors.
>> 1578
>> 1579 config CPU_R4X00
>> 1580 bool "R4x00"
>> 1581 depends on SYS_HAS_CPU_R4X00
>> 1582 select CPU_SUPPORTS_32BIT_KERNEL
>> 1583 select CPU_SUPPORTS_64BIT_KERNEL
>> 1584 select CPU_SUPPORTS_HUGEPAGES
>> 1585 help
>> 1586 MIPS Technologies R4000-series processors other than 4300, including
>> 1587 the R4000, R4400, R4600, and 4700.
>> 1588
>> 1589 config CPU_TX49XX
>> 1590 bool "R49XX"
>> 1591 depends on SYS_HAS_CPU_TX49XX
>> 1592 select CPU_HAS_PREFETCH
>> 1593 select CPU_SUPPORTS_32BIT_KERNEL
>> 1594 select CPU_SUPPORTS_64BIT_KERNEL
>> 1595 select CPU_SUPPORTS_HUGEPAGES
>> 1596
>> 1597 config CPU_R5000
>> 1598 bool "R5000"
>> 1599 depends on SYS_HAS_CPU_R5000
>> 1600 select CPU_SUPPORTS_32BIT_KERNEL
>> 1601 select CPU_SUPPORTS_64BIT_KERNEL
>> 1602 select CPU_SUPPORTS_HUGEPAGES
>> 1603 help
>> 1604 MIPS Technologies R5000-series processors other than the Nevada.
>> 1605
>> 1606 config CPU_R5432
>> 1607 bool "R5432"
>> 1608 depends on SYS_HAS_CPU_R5432
>> 1609 select CPU_SUPPORTS_32BIT_KERNEL
>> 1610 select CPU_SUPPORTS_64BIT_KERNEL
>> 1611 select CPU_SUPPORTS_HUGEPAGES
>> 1612
>> 1613 config CPU_R5500
>> 1614 bool "R5500"
>> 1615 depends on SYS_HAS_CPU_R5500
>> 1616 select CPU_SUPPORTS_32BIT_KERNEL
>> 1617 select CPU_SUPPORTS_64BIT_KERNEL
>> 1618 select CPU_SUPPORTS_HUGEPAGES
>> 1619 help
>> 1620 NEC VR5500 and VR5500A series processors implement 64-bit MIPS IV
>> 1621 instruction set.
>> 1622
>> 1623 config CPU_NEVADA
>> 1624 bool "RM52xx"
>> 1625 depends on SYS_HAS_CPU_NEVADA
>> 1626 select CPU_SUPPORTS_32BIT_KERNEL
>> 1627 select CPU_SUPPORTS_64BIT_KERNEL
>> 1628 select CPU_SUPPORTS_HUGEPAGES
>> 1629 help
>> 1630 QED / PMC-Sierra RM52xx-series ("Nevada") processors.
>> 1631
>> 1632 config CPU_R8000
>> 1633 bool "R8000"
>> 1634 depends on SYS_HAS_CPU_R8000
>> 1635 select CPU_HAS_PREFETCH
>> 1636 select CPU_SUPPORTS_64BIT_KERNEL
>> 1637 help
>> 1638 MIPS Technologies R8000 processors. Note these processors are
>> 1639 uncommon and the support for them is incomplete.
>> 1640
>> 1641 config CPU_R10000
>> 1642 bool "R10000"
>> 1643 depends on SYS_HAS_CPU_R10000
>> 1644 select CPU_HAS_PREFETCH
>> 1645 select CPU_SUPPORTS_32BIT_KERNEL
>> 1646 select CPU_SUPPORTS_64BIT_KERNEL
>> 1647 select CPU_SUPPORTS_HIGHMEM
>> 1648 select CPU_SUPPORTS_HUGEPAGES
>> 1649 help
>> 1650 MIPS Technologies R10000-series processors.
>> 1651
>> 1652 config CPU_RM7000
>> 1653 bool "RM7000"
>> 1654 depends on SYS_HAS_CPU_RM7000
>> 1655 select CPU_HAS_PREFETCH
>> 1656 select CPU_SUPPORTS_32BIT_KERNEL
>> 1657 select CPU_SUPPORTS_64BIT_KERNEL
>> 1658 select CPU_SUPPORTS_HIGHMEM
>> 1659 select CPU_SUPPORTS_HUGEPAGES
>> 1660
>> 1661 config CPU_SB1
>> 1662 bool "SB1"
>> 1663 depends on SYS_HAS_CPU_SB1
>> 1664 select CPU_SUPPORTS_32BIT_KERNEL
>> 1665 select CPU_SUPPORTS_64BIT_KERNEL
>> 1666 select CPU_SUPPORTS_HIGHMEM
>> 1667 select CPU_SUPPORTS_HUGEPAGES
>> 1668 select WEAK_ORDERING
>> 1669
>> 1670 config CPU_CAVIUM_OCTEON
>> 1671 bool "Cavium Octeon processor"
>> 1672 depends on SYS_HAS_CPU_CAVIUM_OCTEON
>> 1673 select CPU_HAS_PREFETCH
>> 1674 select CPU_SUPPORTS_64BIT_KERNEL
>> 1675 select WEAK_ORDERING
>> 1676 select CPU_SUPPORTS_HIGHMEM
>> 1677 select CPU_SUPPORTS_HUGEPAGES
>> 1678 select USB_EHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 1679 select USB_OHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 1680 select MIPS_L1_CACHE_SHIFT_7
>> 1681 select HAVE_KVM
>> 1682 help
>> 1683 The Cavium Octeon processor is a highly integrated chip containing
>> 1684 many ethernet hardware widgets for networking tasks. The processor
>> 1685 can have up to 16 Mips64v2 cores and 8 integrated gigabit ethernets.
>> 1686 Full details can be found at http://www.caviumnetworks.com.
>> 1687
>> 1688 config CPU_BMIPS
>> 1689 bool "Broadcom BMIPS"
>> 1690 depends on SYS_HAS_CPU_BMIPS
>> 1691 select CPU_MIPS32
>> 1692 select CPU_BMIPS32_3300 if SYS_HAS_CPU_BMIPS32_3300
>> 1693 select CPU_BMIPS4350 if SYS_HAS_CPU_BMIPS4350
>> 1694 select CPU_BMIPS4380 if SYS_HAS_CPU_BMIPS4380
>> 1695 select CPU_BMIPS5000 if SYS_HAS_CPU_BMIPS5000
>> 1696 select CPU_SUPPORTS_32BIT_KERNEL
>> 1697 select DMA_NONCOHERENT
>> 1698 select IRQ_MIPS_CPU
>> 1699 select SWAP_IO_SPACE
>> 1700 select WEAK_ORDERING
>> 1701 select CPU_SUPPORTS_HIGHMEM
>> 1702 select CPU_HAS_PREFETCH
>> 1703 select CPU_SUPPORTS_CPUFREQ
>> 1704 select MIPS_EXTERNAL_TIMER
>> 1705 help
>> 1706 Support for BMIPS32/3300/4350/4380 and BMIPS5000 processors.
>> 1707
>> 1708 config CPU_XLR
>> 1709 bool "Netlogic XLR SoC"
>> 1710 depends on SYS_HAS_CPU_XLR
>> 1711 select CPU_SUPPORTS_32BIT_KERNEL
>> 1712 select CPU_SUPPORTS_64BIT_KERNEL
>> 1713 select CPU_SUPPORTS_HIGHMEM
>> 1714 select CPU_SUPPORTS_HUGEPAGES
>> 1715 select WEAK_ORDERING
>> 1716 select WEAK_REORDERING_BEYOND_LLSC
>> 1717 help
>> 1718 Netlogic Microsystems XLR/XLS processors.
>> 1719
>> 1720 config CPU_XLP
>> 1721 bool "Netlogic XLP SoC"
>> 1722 depends on SYS_HAS_CPU_XLP
>> 1723 select CPU_SUPPORTS_32BIT_KERNEL
>> 1724 select CPU_SUPPORTS_64BIT_KERNEL
>> 1725 select CPU_SUPPORTS_HIGHMEM
>> 1726 select WEAK_ORDERING
>> 1727 select WEAK_REORDERING_BEYOND_LLSC
>> 1728 select CPU_HAS_PREFETCH
>> 1729 select CPU_MIPSR2
>> 1730 select CPU_SUPPORTS_HUGEPAGES
>> 1731 select MIPS_ASID_BITS_VARIABLE
>> 1732 help
>> 1733 Netlogic Microsystems XLP processors.
>> 1734 endchoice
979 1735
980 If unsure, say Y. !! 1736 config CPU_MIPS32_3_5_FEATURES
>> 1737 bool "MIPS32 Release 3.5 Features"
>> 1738 depends on SYS_HAS_CPU_MIPS32_R3_5
>> 1739 depends on CPU_MIPS32_R2 || CPU_MIPS32_R6
>> 1740 help
>> 1741 Choose this option to build a kernel for release 2 or later of the
>> 1742 MIPS32 architecture including features from the 3.5 release such as
>> 1743 support for Enhanced Virtual Addressing (EVA).
>> 1744
>> 1745 config CPU_MIPS32_3_5_EVA
>> 1746 bool "Enhanced Virtual Addressing (EVA)"
>> 1747 depends on CPU_MIPS32_3_5_FEATURES
>> 1748 select EVA
>> 1749 default y
>> 1750 help
>> 1751 Choose this option if you want to enable the Enhanced Virtual
>> 1752 Addressing (EVA) on your MIPS32 core (such as proAptiv).
>> 1753 One of its primary benefits is an increase in the maximum size
>> 1754 of lowmem (up to 3GB). If unsure, say 'N' here.
>> 1755
>> 1756 config CPU_MIPS32_R5_FEATURES
>> 1757 bool "MIPS32 Release 5 Features"
>> 1758 depends on SYS_HAS_CPU_MIPS32_R5
>> 1759 depends on CPU_MIPS32_R2
>> 1760 help
>> 1761 Choose this option to build a kernel for release 2 or later of the
>> 1762 MIPS32 architecture including features from release 5 such as
>> 1763 support for Extended Physical Addressing (XPA).
>> 1764
>> 1765 config CPU_MIPS32_R5_XPA
>> 1766 bool "Extended Physical Addressing (XPA)"
>> 1767 depends on CPU_MIPS32_R5_FEATURES
>> 1768 depends on !EVA
>> 1769 depends on !PAGE_SIZE_4KB
>> 1770 depends on SYS_SUPPORTS_HIGHMEM
>> 1771 select XPA
>> 1772 select HIGHMEM
>> 1773 select ARCH_PHYS_ADDR_T_64BIT
>> 1774 default n
>> 1775 help
>> 1776 Choose this option if you want to enable the Extended Physical
>> 1777 Addressing (XPA) on your MIPS32 core (such as P5600 series). The
>> 1778 benefit is to increase physical addressing equal to or greater
>> 1779 than 40 bits. Note that this has the side effect of turning on
>> 1780 64-bit addressing which in turn makes the PTEs 64-bit in size.
>> 1781 If unsure, say 'N' here.
981 1782
982 config ARM64_ERRATUM_2038923 !! 1783 if CPU_LOONGSON2F
983 bool "Cortex-A510: 2038923: workaround !! 1784 config CPU_NOP_WORKAROUNDS
984 depends on CORESIGHT_TRBE !! 1785 bool
985 default y <<
986 help <<
987 This option adds the workaround for <<
988 <<
989 Affected Cortex-A510 core might caus <<
990 prohibited within the CPU. As a resu <<
991 might be corrupted. This happens aft <<
992 TRBLIMITR_EL1.E, followed by just a <<
993 execution changes from a context, in <<
994 isn't, or vice versa. In these menti <<
995 is prohibited is inconsistent betwee <<
996 the trace buffer state might be corr <<
997 <<
998 Work around this in the driver by pr <<
999 trace is prohibited or not based on <<
1000 change to TRBLIMITR_EL1.E with at l <<
1001 two ISB instructions if no ERET is <<
1002 1786
1003 If unsure, say Y. !! 1787 config CPU_JUMP_WORKAROUNDS
>> 1788 bool
1004 1789
1005 config ARM64_ERRATUM_1902691 !! 1790 config CPU_LOONGSON2F_WORKAROUNDS
1006 bool "Cortex-A510: 1902691: workaroun !! 1791 bool "Loongson 2F Workarounds"
1007 depends on CORESIGHT_TRBE <<
1008 default y 1792 default y
>> 1793 select CPU_NOP_WORKAROUNDS
>> 1794 select CPU_JUMP_WORKAROUNDS
1009 help 1795 help
1010 This option adds the workaround for !! 1796 Loongson 2F01 / 2F02 processors have the NOP & JUMP issues which
>> 1797 require workarounds. Without workarounds the system may hang
>> 1798 unexpectedly. For more information please refer to the gas
>> 1799 -mfix-loongson2f-nop and -mfix-loongson2f-jump options.
>> 1800
>> 1801 Loongson 2F03 and later have fixed these issues and no workarounds
>> 1802 are needed. The workarounds have no significant side effect on them
>> 1803 but may decrease the performance of the system so this option should
>> 1804 be disabled unless the kernel is intended to be run on 2F01 or 2F02
>> 1805 systems.
1011 1806
1012 Affected Cortex-A510 core might cau !! 1807 If unsure, please say Y.
1013 into the memory. Effectively TRBE i !! 1808 endif # CPU_LOONGSON2F
1014 trace data. <<
1015 1809
1016 Work around this problem in the dri !! 1810 config SYS_SUPPORTS_ZBOOT
1017 affected cpus. The firmware must ha !! 1811 bool
1018 on such implementations. This will !! 1812 select HAVE_KERNEL_GZIP
1019 do this already. !! 1813 select HAVE_KERNEL_BZIP2
>> 1814 select HAVE_KERNEL_LZ4
>> 1815 select HAVE_KERNEL_LZMA
>> 1816 select HAVE_KERNEL_LZO
>> 1817 select HAVE_KERNEL_XZ
1020 1818
1021 If unsure, say Y. !! 1819 config SYS_SUPPORTS_ZBOOT_UART16550
>> 1820 bool
>> 1821 select SYS_SUPPORTS_ZBOOT
1022 1822
1023 config ARM64_ERRATUM_2457168 !! 1823 config SYS_SUPPORTS_ZBOOT_UART_PROM
1024 bool "Cortex-A510: 2457168: workaroun !! 1824 bool
1025 depends on ARM64_AMU_EXTN !! 1825 select SYS_SUPPORTS_ZBOOT
1026 default y <<
1027 help <<
1028 This option adds the workaround for <<
1029 1826
1030 The AMU counter AMEVCNTR01 (constan !! 1827 config CPU_LOONGSON2
1031 as the system counter. On affected !! 1828 bool
1032 incorrectly giving a significantly !! 1829 select CPU_SUPPORTS_32BIT_KERNEL
>> 1830 select CPU_SUPPORTS_64BIT_KERNEL
>> 1831 select CPU_SUPPORTS_HIGHMEM
>> 1832 select CPU_SUPPORTS_HUGEPAGES
1033 1833
1034 Work around this problem by returni !! 1834 config CPU_LOONGSON1
1035 key locations that results in disab !! 1835 bool
1036 is the same to firmware disabling a !! 1836 select CPU_MIPS32
>> 1837 select CPU_MIPSR2
>> 1838 select CPU_HAS_PREFETCH
>> 1839 select CPU_SUPPORTS_32BIT_KERNEL
>> 1840 select CPU_SUPPORTS_HIGHMEM
>> 1841 select CPU_SUPPORTS_CPUFREQ
1037 1842
1038 If unsure, say Y. !! 1843 config CPU_BMIPS32_3300
>> 1844 select SMP_UP if SMP
>> 1845 bool
1039 1846
1040 config ARM64_ERRATUM_2645198 !! 1847 config CPU_BMIPS4350
1041 bool "Cortex-A715: 2645198: Workaroun !! 1848 bool
1042 default y !! 1849 select SYS_SUPPORTS_SMP
1043 help !! 1850 select SYS_SUPPORTS_HOTPLUG_CPU
1044 This option adds the workaround for <<
1045 1851
1046 If a Cortex-A715 cpu sees a page ma !! 1852 config CPU_BMIPS4380
1047 to non-executable, it may corrupt t !! 1853 bool
1048 next instruction abort caused by pe !! 1854 select MIPS_L1_CACHE_SHIFT_6
>> 1855 select SYS_SUPPORTS_SMP
>> 1856 select SYS_SUPPORTS_HOTPLUG_CPU
>> 1857 select CPU_HAS_RIXI
1049 1858
1050 Only user-space does executable to !! 1859 config CPU_BMIPS5000
1051 mprotect() system call. Workaround !! 1860 bool
1052 TLB invalidation, for all changes t !! 1861 select MIPS_CPU_SCACHE
>> 1862 select MIPS_L1_CACHE_SHIFT_7
>> 1863 select SYS_SUPPORTS_SMP
>> 1864 select SYS_SUPPORTS_HOTPLUG_CPU
>> 1865 select CPU_HAS_RIXI
1053 1866
1054 If unsure, say Y. !! 1867 config SYS_HAS_CPU_LOONGSON3
>> 1868 bool
>> 1869 select CPU_SUPPORTS_CPUFREQ
>> 1870 select CPU_HAS_RIXI
1055 1871
1056 config ARM64_WORKAROUND_SPECULATIVE_UNPRIV_LO !! 1872 config SYS_HAS_CPU_LOONGSON2E
1057 bool 1873 bool
1058 1874
1059 config ARM64_ERRATUM_2966298 !! 1875 config SYS_HAS_CPU_LOONGSON2F
1060 bool "Cortex-A520: 2966298: workaroun !! 1876 bool
1061 select ARM64_WORKAROUND_SPECULATIVE_U !! 1877 select CPU_SUPPORTS_CPUFREQ
1062 default y !! 1878 select CPU_SUPPORTS_ADDRWINCFG if 64BIT
1063 help !! 1879 select CPU_SUPPORTS_UNCACHED_ACCELERATED
1064 This option adds the workaround for <<
1065 1880
1066 On an affected Cortex-A520 core, a !! 1881 config SYS_HAS_CPU_LOONGSON1B
1067 load might leak data from a privile !! 1882 bool
1068 1883
1069 Work around this problem by executi !! 1884 config SYS_HAS_CPU_LOONGSON1C
>> 1885 bool
1070 1886
1071 If unsure, say Y. !! 1887 config SYS_HAS_CPU_MIPS32_R1
>> 1888 bool
1072 1889
1073 config ARM64_ERRATUM_3117295 !! 1890 config SYS_HAS_CPU_MIPS32_R2
1074 bool "Cortex-A510: 3117295: workaroun !! 1891 bool
1075 select ARM64_WORKAROUND_SPECULATIVE_U <<
1076 default y <<
1077 help <<
1078 This option adds the workaround for <<
1079 1892
1080 On an affected Cortex-A510 core, a !! 1893 config SYS_HAS_CPU_MIPS32_R3_5
1081 load might leak data from a privile !! 1894 bool
1082 1895
1083 Work around this problem by executi !! 1896 config SYS_HAS_CPU_MIPS32_R5
>> 1897 bool
1084 1898
1085 If unsure, say Y. !! 1899 config SYS_HAS_CPU_MIPS32_R6
>> 1900 bool
1086 1901
1087 config ARM64_ERRATUM_3194386 !! 1902 config SYS_HAS_CPU_MIPS64_R1
1088 bool "Cortex-*/Neoverse-*: workaround !! 1903 bool
1089 default y <<
1090 help <<
1091 This option adds the workaround for <<
1092 1904
1093 * ARM Cortex-A76 erratum 3324349 !! 1905 config SYS_HAS_CPU_MIPS64_R2
1094 * ARM Cortex-A77 erratum 3324348 !! 1906 bool
1095 * ARM Cortex-A78 erratum 3324344 <<
1096 * ARM Cortex-A78C erratum 3324346 <<
1097 * ARM Cortex-A78C erratum 3324347 <<
1098 * ARM Cortex-A710 erratam 3324338 <<
1099 * ARM Cortex-A715 errartum 3456084 <<
1100 * ARM Cortex-A720 erratum 3456091 <<
1101 * ARM Cortex-A725 erratum 3456106 <<
1102 * ARM Cortex-X1 erratum 3324344 <<
1103 * ARM Cortex-X1C erratum 3324346 <<
1104 * ARM Cortex-X2 erratum 3324338 <<
1105 * ARM Cortex-X3 erratum 3324335 <<
1106 * ARM Cortex-X4 erratum 3194386 <<
1107 * ARM Cortex-X925 erratum 3324334 <<
1108 * ARM Neoverse-N1 erratum 3324349 <<
1109 * ARM Neoverse N2 erratum 3324339 <<
1110 * ARM Neoverse-N3 erratum 3456111 <<
1111 * ARM Neoverse-V1 erratum 3324341 <<
1112 * ARM Neoverse V2 erratum 3324336 <<
1113 * ARM Neoverse-V3 erratum 3312417 <<
1114 <<
1115 On affected cores "MSR SSBS, #0" in <<
1116 subsequent speculative instructions <<
1117 speculative store bypassing. <<
1118 <<
1119 Work around this problem by placing <<
1120 Instruction Synchronization Barrier <<
1121 SSBS. The presence of the SSBS spec <<
1122 from hwcaps and EL0 reads of ID_AA6 <<
1123 will use the PR_SPEC_STORE_BYPASS p <<
1124 1907
1125 If unsure, say Y. !! 1908 config SYS_HAS_CPU_MIPS64_R6
>> 1909 bool
1126 1910
1127 config CAVIUM_ERRATUM_22375 !! 1911 config SYS_HAS_CPU_R3000
1128 bool "Cavium erratum 22375, 24313" !! 1912 bool
1129 default y <<
1130 help <<
1131 Enable workaround for errata 22375 <<
1132 1913
1133 This implements two gicv3-its errat !! 1914 config SYS_HAS_CPU_TX39XX
1134 with a small impact affecting only !! 1915 bool
1135 1916
1136 erratum 22375: only alloc 8MB tab !! 1917 config SYS_HAS_CPU_VR41XX
1137 erratum 24313: ignore memory acce !! 1918 bool
1138 1919
1139 The fixes are in ITS initialization !! 1920 config SYS_HAS_CPU_R4300
1140 type and table size provided by the !! 1921 bool
1141 1922
1142 If unsure, say Y. !! 1923 config SYS_HAS_CPU_R4X00
>> 1924 bool
1143 1925
1144 config CAVIUM_ERRATUM_23144 !! 1926 config SYS_HAS_CPU_TX49XX
1145 bool "Cavium erratum 23144: ITS SYNC !! 1927 bool
1146 depends on NUMA <<
1147 default y <<
1148 help <<
1149 ITS SYNC command hang for cross nod <<
1150 1928
1151 If unsure, say Y. !! 1929 config SYS_HAS_CPU_R5000
>> 1930 bool
1152 1931
1153 config CAVIUM_ERRATUM_23154 !! 1932 config SYS_HAS_CPU_R5432
1154 bool "Cavium errata 23154 and 38545: !! 1933 bool
1155 default y <<
1156 help <<
1157 The ThunderX GICv3 implementation r <<
1158 reading the IAR status to ensure da <<
1159 (access to icc_iar1_el1 is not sync <<
1160 1934
1161 It also suffers from erratum 38545 !! 1935 config SYS_HAS_CPU_R5500
1162 OcteonTX and OcteonTX2), resulting !! 1936 bool
1163 spuriously presented to the CPU int <<
1164 1937
1165 If unsure, say Y. !! 1938 config SYS_HAS_CPU_NEVADA
>> 1939 bool
1166 1940
1167 config CAVIUM_ERRATUM_27456 !! 1941 config SYS_HAS_CPU_R8000
1168 bool "Cavium erratum 27456: Broadcast !! 1942 bool
1169 default y <<
1170 help <<
1171 On ThunderX T88 pass 1.x through 2. <<
1172 instructions may cause the icache t <<
1173 contains data for a non-current ASI <<
1174 invalidate the icache when changing <<
1175 1943
1176 If unsure, say Y. !! 1944 config SYS_HAS_CPU_R10000
>> 1945 bool
1177 1946
1178 config CAVIUM_ERRATUM_30115 !! 1947 config SYS_HAS_CPU_RM7000
1179 bool "Cavium erratum 30115: Guest may !! 1948 bool
1180 default y <<
1181 help <<
1182 On ThunderX T88 pass 1.x through 2. <<
1183 1.2, and T83 Pass 1.0, KVM guest ex <<
1184 interrupts in host. Trapping both G <<
1185 accesses sidesteps the issue. <<
1186 1949
1187 If unsure, say Y. !! 1950 config SYS_HAS_CPU_SB1
>> 1951 bool
1188 1952
1189 config CAVIUM_TX2_ERRATUM_219 !! 1953 config SYS_HAS_CPU_CAVIUM_OCTEON
1190 bool "Cavium ThunderX2 erratum 219: P !! 1954 bool
1191 default y <<
1192 help <<
1193 On Cavium ThunderX2, a load, store <<
1194 TTBR update and the corresponding c <<
1195 cause a spurious Data Abort to be d <<
1196 the CPU core. <<
1197 <<
1198 Work around the issue by avoiding t <<
1199 trapping KVM guest TTBRx_EL1 writes <<
1200 trap handler performs the correspon <<
1201 instruction and ensures context syn <<
1202 exception return. <<
1203 1955
1204 If unsure, say Y. !! 1956 config SYS_HAS_CPU_BMIPS
>> 1957 bool
1205 1958
1206 config FUJITSU_ERRATUM_010001 !! 1959 config SYS_HAS_CPU_BMIPS32_3300
1207 bool "Fujitsu-A64FX erratum E#010001: !! 1960 bool
1208 default y !! 1961 select SYS_HAS_CPU_BMIPS
1209 help <<
1210 This option adds a workaround for F <<
1211 On some variants of the Fujitsu-A64 <<
1212 accesses may cause undefined fault <<
1213 This fault occurs under a specific <<
1214 load/store instruction performs an <<
1215 case-1 TTBR0_EL1 with TCR_EL1.NFD0 <<
1216 case-2 TTBR0_EL2 with TCR_EL2.NFD0 <<
1217 case-3 TTBR1_EL1 with TCR_EL1.NFD1 <<
1218 case-4 TTBR1_EL2 with TCR_EL2.NFD1 <<
1219 1962
1220 The workaround is to ensure these b !! 1963 config SYS_HAS_CPU_BMIPS4350
1221 The workaround only affects the Fuj !! 1964 bool
>> 1965 select SYS_HAS_CPU_BMIPS
1222 1966
1223 If unsure, say Y. !! 1967 config SYS_HAS_CPU_BMIPS4380
>> 1968 bool
>> 1969 select SYS_HAS_CPU_BMIPS
1224 1970
1225 config HISILICON_ERRATUM_161600802 !! 1971 config SYS_HAS_CPU_BMIPS5000
1226 bool "Hip07 161600802: Erroneous redi !! 1972 bool
1227 default y !! 1973 select SYS_HAS_CPU_BMIPS
1228 help <<
1229 The HiSilicon Hip07 SoC uses the wr <<
1230 when issued ITS commands such as VM <<
1231 a 128kB offset to be applied to the <<
1232 1974
1233 If unsure, say Y. !! 1975 config SYS_HAS_CPU_XLR
>> 1976 bool
1234 1977
1235 config QCOM_FALKOR_ERRATUM_1003 !! 1978 config SYS_HAS_CPU_XLP
1236 bool "Falkor E1003: Incorrect transla !! 1979 bool
1237 default y <<
1238 help <<
1239 On Falkor v1, an incorrect ASID may <<
1240 and BADDR are changed together in T <<
1241 in TTBR1_EL1, this situation only o <<
1242 then only for entries in the walk c <<
1243 is unchanged. Work around the errat <<
1244 entries for the trampoline before e <<
1245 1980
1246 config QCOM_FALKOR_ERRATUM_1009 !! 1981 config MIPS_MALTA_PM
1247 bool "Falkor E1009: Prematurely compl !! 1982 depends on MIPS_MALTA
>> 1983 depends on PCI
>> 1984 bool
1248 default y 1985 default y
1249 select ARM64_WORKAROUND_REPEAT_TLBI <<
1250 help <<
1251 On Falkor v1, the CPU may premature <<
1252 TLBI xxIS invalidate maintenance op <<
1253 one more time to fix the issue. <<
1254 1986
1255 If unsure, say Y. !! 1987 #
>> 1988 # CPU may reorder R->R, R->W, W->R, W->W
>> 1989 # Reordering beyond LL and SC is handled in WEAK_REORDERING_BEYOND_LLSC
>> 1990 #
>> 1991 config WEAK_ORDERING
>> 1992 bool
1256 1993
1257 config QCOM_QDF2400_ERRATUM_0065 !! 1994 #
1258 bool "QDF2400 E0065: Incorrect GITS_T !! 1995 # CPU may reorder reads and writes beyond LL/SC
1259 default y !! 1996 # CPU may reorder R->LL, R->LL, W->LL, W->LL, R->SC, R->SC, W->SC, W->SC
1260 help !! 1997 #
1261 On Qualcomm Datacenter Technologies !! 1998 config WEAK_REORDERING_BEYOND_LLSC
1262 ITE size incorrectly. The GITS_TYPE !! 1999 bool
1263 been indicated as 16Bytes (0xf), no !! 2000 endmenu
1264 2001
1265 If unsure, say Y. !! 2002 #
>> 2003 # These two indicate any level of the MIPS32 and MIPS64 architecture
>> 2004 #
>> 2005 config CPU_MIPS32
>> 2006 bool
>> 2007 default y if CPU_MIPS32_R1 || CPU_MIPS32_R2 || CPU_MIPS32_R6
1266 2008
1267 config QCOM_FALKOR_ERRATUM_E1041 !! 2009 config CPU_MIPS64
1268 bool "Falkor E1041: Speculative instr !! 2010 bool
1269 default y !! 2011 default y if CPU_MIPS64_R1 || CPU_MIPS64_R2 || CPU_MIPS64_R6
1270 help <<
1271 Falkor CPU may speculatively fetch <<
1272 memory location when MMU translatio <<
1273 to SCTLR_ELn[M]=0. Prefix an ISB in <<
1274 2012
1275 If unsure, say Y. !! 2013 #
>> 2014 # These two indicate the revision of the architecture, either Release 1 or Release 2
>> 2015 #
>> 2016 config CPU_MIPSR1
>> 2017 bool
>> 2018 default y if CPU_MIPS32_R1 || CPU_MIPS64_R1
1276 2019
1277 config NVIDIA_CARMEL_CNP_ERRATUM !! 2020 config CPU_MIPSR2
1278 bool "NVIDIA Carmel CNP: CNP on Carme !! 2021 bool
1279 default y !! 2022 default y if CPU_MIPS32_R2 || CPU_MIPS64_R2 || CPU_CAVIUM_OCTEON
1280 help !! 2023 select CPU_HAS_RIXI
1281 If CNP is enabled on Carmel cores, !! 2024 select MIPS_SPRAM
1282 invalidate shared TLB entries insta <<
1283 on standard ARM cores. <<
1284 2025
1285 If unsure, say Y. !! 2026 config CPU_MIPSR6
>> 2027 bool
>> 2028 default y if CPU_MIPS32_R6 || CPU_MIPS64_R6
>> 2029 select CPU_HAS_RIXI
>> 2030 select HAVE_ARCH_BITREVERSE
>> 2031 select MIPS_ASID_BITS_VARIABLE
>> 2032 select MIPS_CRC_SUPPORT
>> 2033 select MIPS_SPRAM
1286 2034
1287 config ROCKCHIP_ERRATUM_3588001 !! 2035 config EVA
1288 bool "Rockchip 3588001: GIC600 can no !! 2036 bool
1289 default y <<
1290 help <<
1291 The Rockchip RK3588 GIC600 SoC inte <<
1292 This means, that its sharability fe <<
1293 is supported by the IP itself. <<
1294 2037
1295 If unsure, say Y. !! 2038 config XPA
>> 2039 bool
1296 2040
1297 config SOCIONEXT_SYNQUACER_PREITS !! 2041 config SYS_SUPPORTS_32BIT_KERNEL
1298 bool "Socionext Synquacer: Workaround !! 2042 bool
1299 default y !! 2043 config SYS_SUPPORTS_64BIT_KERNEL
1300 help !! 2044 bool
1301 Socionext Synquacer SoCs implement !! 2045 config CPU_SUPPORTS_32BIT_KERNEL
1302 MSI doorbell writes with non-zero v !! 2046 bool
>> 2047 config CPU_SUPPORTS_64BIT_KERNEL
>> 2048 bool
>> 2049 config CPU_SUPPORTS_CPUFREQ
>> 2050 bool
>> 2051 config CPU_SUPPORTS_ADDRWINCFG
>> 2052 bool
>> 2053 config CPU_SUPPORTS_HUGEPAGES
>> 2054 bool
>> 2055 config CPU_SUPPORTS_UNCACHED_ACCELERATED
>> 2056 bool
>> 2057 config MIPS_PGD_C0_CONTEXT
>> 2058 bool
>> 2059 default y if 64BIT && (CPU_MIPSR2 || CPU_MIPSR6) && !CPU_XLP
1303 2060
1304 If unsure, say Y. !! 2061 #
>> 2062 # Set to y for ptrace access to watch registers.
>> 2063 #
>> 2064 config HARDWARE_WATCHPOINTS
>> 2065 bool
>> 2066 default y if CPU_MIPSR1 || CPU_MIPSR2 || CPU_MIPSR6
1305 2067
1306 endmenu # "ARM errata workarounds via the alt !! 2068 menu "Kernel type"
1307 2069
1308 choice 2070 choice
1309 prompt "Page size" !! 2071 prompt "Kernel code model"
1310 default ARM64_4K_PAGES <<
1311 help <<
1312 Page size (translation granule) con <<
1313 <<
1314 config ARM64_4K_PAGES <<
1315 bool "4KB" <<
1316 select HAVE_PAGE_SIZE_4KB <<
1317 help 2072 help
1318 This feature enables 4KB pages supp !! 2073 You should only select this option if you have a workload that
1319 !! 2074 actually benefits from 64-bit processing or if your machine has
1320 config ARM64_16K_PAGES !! 2075 large memory. You will only be presented a single option in this
1321 bool "16KB" !! 2076 menu if your system does not support both 32-bit and 64-bit kernels.
1322 select HAVE_PAGE_SIZE_16KB !! 2077
>> 2078 config 32BIT
>> 2079 bool "32-bit kernel"
>> 2080 depends on CPU_SUPPORTS_32BIT_KERNEL && SYS_SUPPORTS_32BIT_KERNEL
>> 2081 select TRAD_SIGNALS
1323 help 2082 help
1324 The system will use 16KB pages supp !! 2083 Select this option if you want to build a 32-bit kernel.
1325 requires applications compiled with <<
1326 aligned segments. <<
1327 2084
1328 config ARM64_64K_PAGES !! 2085 config 64BIT
1329 bool "64KB" !! 2086 bool "64-bit kernel"
1330 select HAVE_PAGE_SIZE_64KB !! 2087 depends on CPU_SUPPORTS_64BIT_KERNEL && SYS_SUPPORTS_64BIT_KERNEL
1331 help 2088 help
1332 This feature enables 64KB pages sup !! 2089 Select this option if you want to build a 64-bit kernel.
1333 allowing only two levels of page ta <<
1334 look-up. AArch32 emulation requires <<
1335 with 64K aligned segments. <<
1336 2090
1337 endchoice 2091 endchoice
1338 2092
>> 2093 config KVM_GUEST
>> 2094 bool "KVM Guest Kernel"
>> 2095 depends on BROKEN_ON_SMP
>> 2096 help
>> 2097 Select this option if building a guest kernel for KVM (Trap & Emulate)
>> 2098 mode.
>> 2099
>> 2100 config KVM_GUEST_TIMER_FREQ
>> 2101 int "Count/Compare Timer Frequency (MHz)"
>> 2102 depends on KVM_GUEST
>> 2103 default 100
>> 2104 help
>> 2105 Set this to non-zero if building a guest kernel for KVM to skip RTC
>> 2106 emulation when determining guest CPU Frequency. Instead, the guest's
>> 2107 timer frequency is specified directly.
>> 2108
>> 2109 config MIPS_VA_BITS_48
>> 2110 bool "48 bits virtual memory"
>> 2111 depends on 64BIT
>> 2112 help
>> 2113 Support a maximum at least 48 bits of application virtual
>> 2114 memory. Default is 40 bits or less, depending on the CPU.
>> 2115 For page sizes 16k and above, this option results in a small
>> 2116 memory overhead for page tables. For 4k page size, a fourth
>> 2117 level of page tables is added which imposes both a memory
>> 2118 overhead as well as slower TLB fault handling.
>> 2119
>> 2120 If unsure, say N.
>> 2121
1339 choice 2122 choice
1340 prompt "Virtual address space size" !! 2123 prompt "Kernel page size"
1341 default ARM64_VA_BITS_52 !! 2124 default PAGE_SIZE_4KB
1342 help <<
1343 Allows choosing one of multiple pos <<
1344 space sizes. The level of translati <<
1345 a combination of page size and virt <<
1346 <<
1347 config ARM64_VA_BITS_36 <<
1348 bool "36-bit" if EXPERT <<
1349 depends on PAGE_SIZE_16KB <<
1350 <<
1351 config ARM64_VA_BITS_39 <<
1352 bool "39-bit" <<
1353 depends on PAGE_SIZE_4KB <<
1354 <<
1355 config ARM64_VA_BITS_42 <<
1356 bool "42-bit" <<
1357 depends on PAGE_SIZE_64KB <<
1358 <<
1359 config ARM64_VA_BITS_47 <<
1360 bool "47-bit" <<
1361 depends on PAGE_SIZE_16KB <<
1362 <<
1363 config ARM64_VA_BITS_48 <<
1364 bool "48-bit" <<
1365 <<
1366 config ARM64_VA_BITS_52 <<
1367 bool "52-bit" <<
1368 depends on ARM64_PAN || !ARM64_SW_TTB <<
1369 help <<
1370 Enable 52-bit virtual addressing fo <<
1371 requested via a hint to mmap(). The <<
1372 virtual addresses for its own mappi <<
1373 this feature is available, otherwis <<
1374 <<
1375 NOTE: Enabling 52-bit virtual addre <<
1376 ARMv8.3 Pointer Authentication will <<
1377 reduced from 7 bits to 3 bits, whic <<
1378 impact on its susceptibility to bru <<
1379 2125
1380 If unsure, select 48-bit virtual ad !! 2126 config PAGE_SIZE_4KB
>> 2127 bool "4kB"
>> 2128 depends on !CPU_LOONGSON2 && !CPU_LOONGSON3
>> 2129 help
>> 2130 This option select the standard 4kB Linux page size. On some
>> 2131 R3000-family processors this is the only available page size. Using
>> 2132 4kB page size will minimize memory consumption and is therefore
>> 2133 recommended for low memory systems.
>> 2134
>> 2135 config PAGE_SIZE_8KB
>> 2136 bool "8kB"
>> 2137 depends on CPU_R8000 || CPU_CAVIUM_OCTEON
>> 2138 depends on !MIPS_VA_BITS_48
>> 2139 help
>> 2140 Using 8kB page size will result in higher performance kernel at
>> 2141 the price of higher memory consumption. This option is available
>> 2142 only on R8000 and cnMIPS processors. Note that you will need a
>> 2143 suitable Linux distribution to support this.
>> 2144
>> 2145 config PAGE_SIZE_16KB
>> 2146 bool "16kB"
>> 2147 depends on !CPU_R3000 && !CPU_TX39XX
>> 2148 help
>> 2149 Using 16kB page size will result in higher performance kernel at
>> 2150 the price of higher memory consumption. This option is available on
>> 2151 all non-R3000 family processors. Note that you will need a suitable
>> 2152 Linux distribution to support this.
>> 2153
>> 2154 config PAGE_SIZE_32KB
>> 2155 bool "32kB"
>> 2156 depends on CPU_CAVIUM_OCTEON
>> 2157 depends on !MIPS_VA_BITS_48
>> 2158 help
>> 2159 Using 32kB page size will result in higher performance kernel at
>> 2160 the price of higher memory consumption. This option is available
>> 2161 only on cnMIPS cores. Note that you will need a suitable Linux
>> 2162 distribution to support this.
>> 2163
>> 2164 config PAGE_SIZE_64KB
>> 2165 bool "64kB"
>> 2166 depends on !CPU_R3000 && !CPU_TX39XX
>> 2167 help
>> 2168 Using 64kB page size will result in higher performance kernel at
>> 2169 the price of higher memory consumption. This option is available on
>> 2170 all non-R3000 family processor. Not that at the time of this
>> 2171 writing this option is still high experimental.
1381 2172
1382 endchoice 2173 endchoice
1383 2174
1384 config ARM64_FORCE_52BIT !! 2175 config FORCE_MAX_ZONEORDER
1385 bool "Force 52-bit virtual addresses !! 2176 int "Maximum zone order"
1386 depends on ARM64_VA_BITS_52 && EXPERT !! 2177 range 14 64 if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_64KB
1387 help !! 2178 default "14" if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_64KB
1388 For systems with 52-bit userspace V !! 2179 range 13 64 if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_32KB
1389 to maintain compatibility with olde !! 2180 default "13" if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_32KB
1390 unless a hint is supplied to mmap. !! 2181 range 12 64 if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_16KB
1391 !! 2182 default "12" if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_16KB
1392 This configuration option disables !! 2183 range 11 64
1393 forces all userspace addresses to b !! 2184 default "11"
1394 should only enable this configurati !! 2185 help
1395 memory management code. If unsure s !! 2186 The kernel memory allocator divides physically contiguous memory
>> 2187 blocks into "zones", where each zone is a power of two number of
>> 2188 pages. This option selects the largest power of two that the kernel
>> 2189 keeps in the memory allocator. If you need to allocate very large
>> 2190 blocks of physically contiguous memory, then you may need to
>> 2191 increase this value.
1396 2192
1397 config ARM64_VA_BITS !! 2193 This config option is actually maximum order plus one. For example,
1398 int !! 2194 a value of 11 means that the largest free memory block is 2^10 pages.
1399 default 36 if ARM64_VA_BITS_36 <<
1400 default 39 if ARM64_VA_BITS_39 <<
1401 default 42 if ARM64_VA_BITS_42 <<
1402 default 47 if ARM64_VA_BITS_47 <<
1403 default 48 if ARM64_VA_BITS_48 <<
1404 default 52 if ARM64_VA_BITS_52 <<
1405 2195
1406 choice !! 2196 The page size is not necessarily 4KB. Keep this in mind
1407 prompt "Physical address space size" !! 2197 when choosing a value for this option.
1408 default ARM64_PA_BITS_48 <<
1409 help <<
1410 Choose the maximum physical address <<
1411 support. <<
1412 2198
1413 config ARM64_PA_BITS_48 !! 2199 config BOARD_SCACHE
1414 bool "48-bit" !! 2200 bool
1415 depends on ARM64_64K_PAGES || !ARM64_ <<
1416 <<
1417 config ARM64_PA_BITS_52 <<
1418 bool "52-bit" <<
1419 depends on ARM64_64K_PAGES || ARM64_V <<
1420 depends on ARM64_PAN || !ARM64_SW_TTB <<
1421 help <<
1422 Enable support for a 52-bit physica <<
1423 part of the ARMv8.2-LPA extension. <<
1424 <<
1425 With this enabled, the kernel will <<
1426 do not support ARMv8.2-LPA, but wit <<
1427 minor performance overhead). <<
1428 2201
1429 endchoice !! 2202 config IP22_CPU_SCACHE
>> 2203 bool
>> 2204 select BOARD_SCACHE
1430 2205
1431 config ARM64_PA_BITS !! 2206 #
1432 int !! 2207 # Support for a MIPS32 / MIPS64 style S-caches
1433 default 48 if ARM64_PA_BITS_48 !! 2208 #
1434 default 52 if ARM64_PA_BITS_52 !! 2209 config MIPS_CPU_SCACHE
>> 2210 bool
>> 2211 select BOARD_SCACHE
1435 2212
1436 config ARM64_LPA2 !! 2213 config R5000_CPU_SCACHE
1437 def_bool y !! 2214 bool
1438 depends on ARM64_PA_BITS_52 && !ARM64 !! 2215 select BOARD_SCACHE
1439 2216
1440 choice !! 2217 config RM7000_CPU_SCACHE
1441 prompt "Endianness" !! 2218 bool
1442 default CPU_LITTLE_ENDIAN !! 2219 select BOARD_SCACHE
1443 help <<
1444 Select the endianness of data acces <<
1445 applications will need to be compil <<
1446 that is selected here. <<
1447 2220
1448 config CPU_BIG_ENDIAN !! 2221 config SIBYTE_DMA_PAGEOPS
1449 bool "Build big-endian kernel" !! 2222 bool "Use DMA to clear/copy pages"
1450 # https://github.com/llvm/llvm-projec !! 2223 depends on CPU_SB1
1451 depends on AS_IS_GNU || AS_VERSION >= <<
1452 help 2224 help
1453 Say Y if you plan on running a kern !! 2225 Instead of using the CPU to zero and copy pages, use a Data Mover
>> 2226 channel. These DMA channels are otherwise unused by the standard
>> 2227 SiByte Linux port. Seems to give a small performance benefit.
1454 2228
1455 config CPU_LITTLE_ENDIAN !! 2229 config CPU_HAS_PREFETCH
1456 bool "Build little-endian kernel" !! 2230 bool
1457 help <<
1458 Say Y if you plan on running a kern <<
1459 This is usually the case for distri <<
1460 2231
1461 endchoice !! 2232 config CPU_GENERIC_DUMP_TLB
>> 2233 bool
>> 2234 default y if !(CPU_R3000 || CPU_R8000 || CPU_TX39XX)
1462 2235
1463 config SCHED_MC !! 2236 config CPU_R4K_FPU
1464 bool "Multi-core scheduler support" !! 2237 bool
1465 help !! 2238 default y if !(CPU_R3000 || CPU_TX39XX)
1466 Multi-core scheduler support improv <<
1467 making when dealing with multi-core <<
1468 increased overhead in some places. <<
1469 2239
1470 config SCHED_CLUSTER !! 2240 config CPU_R4K_CACHE_TLB
1471 bool "Cluster scheduler support" !! 2241 bool
1472 help !! 2242 default y if !(CPU_R3000 || CPU_R8000 || CPU_SB1 || CPU_TX39XX || CPU_CAVIUM_OCTEON)
1473 Cluster scheduler support improves !! 2243
1474 making when dealing with machines t !! 2244 config MIPS_MT_SMP
1475 Cluster usually means a couple of C !! 2245 bool "MIPS MT SMP support (1 TC on each available VPE)"
1476 by sharing mid-level caches, last-l !! 2246 default y
1477 busses. !! 2247 depends on SYS_SUPPORTS_MULTITHREADING && !CPU_MIPSR6 && !CPU_MICROMIPS
>> 2248 select CPU_MIPSR2_IRQ_VI
>> 2249 select CPU_MIPSR2_IRQ_EI
>> 2250 select SYNC_R4K
>> 2251 select MIPS_MT
>> 2252 select SMP
>> 2253 select SMP_UP
>> 2254 select SYS_SUPPORTS_SMP
>> 2255 select SYS_SUPPORTS_SCHED_SMT
>> 2256 select MIPS_PERF_SHARED_TC_COUNTERS
>> 2257 help
>> 2258 This is a kernel model which is known as SMVP. This is supported
>> 2259 on cores with the MT ASE and uses the available VPEs to implement
>> 2260 virtual processors which supports SMP. This is equivalent to the
>> 2261 Intel Hyperthreading feature. For further information go to
>> 2262 <http://www.imgtec.com/mips/mips-multithreading.asp>.
>> 2263
>> 2264 config MIPS_MT
>> 2265 bool
1478 2266
1479 config SCHED_SMT 2267 config SCHED_SMT
1480 bool "SMT scheduler support" !! 2268 bool "SMT (multithreading) scheduler support"
>> 2269 depends on SYS_SUPPORTS_SCHED_SMT
>> 2270 default n
1481 help 2271 help
1482 Improves the CPU scheduler's decisi !! 2272 SMT scheduler support improves the CPU scheduler's decision making
1483 MultiThreading at a cost of slightl !! 2273 when dealing with MIPS MT enabled cores at a cost of slightly
1484 places. If unsure say N here. !! 2274 increased overhead in some places. If unsure say N here.
1485 2275
1486 config NR_CPUS !! 2276 config SYS_SUPPORTS_SCHED_SMT
1487 int "Maximum number of CPUs (2-4096)" !! 2277 bool
1488 range 2 4096 <<
1489 default "512" <<
1490 2278
1491 config HOTPLUG_CPU !! 2279 config SYS_SUPPORTS_MULTITHREADING
1492 bool "Support for hot-pluggable CPUs" !! 2280 bool
1493 select GENERIC_IRQ_MIGRATION <<
1494 help <<
1495 Say Y here to experiment with turni <<
1496 can be controlled through /sys/devi <<
1497 2281
1498 # Common NUMA Features !! 2282 config MIPS_MT_FPAFF
1499 config NUMA !! 2283 bool "Dynamic FPU affinity for FP-intensive threads"
1500 bool "NUMA Memory Allocation and Sche !! 2284 default y
1501 select GENERIC_ARCH_NUMA !! 2285 depends on MIPS_MT_SMP
1502 select OF_NUMA <<
1503 select HAVE_SETUP_PER_CPU_AREA <<
1504 select NEED_PER_CPU_EMBED_FIRST_CHUNK <<
1505 select NEED_PER_CPU_PAGE_FIRST_CHUNK <<
1506 select USE_PERCPU_NUMA_NODE_ID <<
1507 help <<
1508 Enable NUMA (Non-Uniform Memory Acc <<
1509 <<
1510 The kernel will try to allocate mem <<
1511 local memory of the CPU and add som <<
1512 NUMA awareness to the kernel. <<
1513 2286
1514 config NODES_SHIFT !! 2287 config MIPSR2_TO_R6_EMULATOR
1515 int "Maximum NUMA Nodes (as a power o !! 2288 bool "MIPS R2-to-R6 emulator"
1516 range 1 10 !! 2289 depends on CPU_MIPSR6
1517 default "4" !! 2290 default y
1518 depends on NUMA <<
1519 help 2291 help
1520 Specify the maximum number of NUMA !! 2292 Choose this option if you want to run non-R6 MIPS userland code.
1521 system. Increases memory reserved !! 2293 Even if you say 'Y' here, the emulator will still be disabled by
>> 2294 default. You can enable it using the 'mipsr2emu' kernel option.
>> 2295 The only reason this is a build-time option is to save ~14K from the
>> 2296 final kernel image.
1522 2297
1523 source "kernel/Kconfig.hz" !! 2298 config SYS_SUPPORTS_VPE_LOADER
>> 2299 bool
>> 2300 depends on SYS_SUPPORTS_MULTITHREADING
>> 2301 help
>> 2302 Indicates that the platform supports the VPE loader, and provides
>> 2303 physical_memsize.
1524 2304
1525 config ARCH_SPARSEMEM_ENABLE !! 2305 config MIPS_VPE_LOADER
1526 def_bool y !! 2306 bool "VPE loader support."
1527 select SPARSEMEM_VMEMMAP_ENABLE !! 2307 depends on SYS_SUPPORTS_VPE_LOADER && MODULES
1528 select SPARSEMEM_VMEMMAP !! 2308 select CPU_MIPSR2_IRQ_VI
>> 2309 select CPU_MIPSR2_IRQ_EI
>> 2310 select MIPS_MT
>> 2311 help
>> 2312 Includes a loader for loading an elf relocatable object
>> 2313 onto another VPE and running it.
1529 2314
1530 config HW_PERF_EVENTS !! 2315 config MIPS_VPE_LOADER_CMP
1531 def_bool y !! 2316 bool
1532 depends on ARM_PMU !! 2317 default "y"
>> 2318 depends on MIPS_VPE_LOADER && MIPS_CMP
1533 2319
1534 # Supported by clang >= 7.0 or GCC >= 12.0.0 !! 2320 config MIPS_VPE_LOADER_MT
1535 config CC_HAVE_SHADOW_CALL_STACK !! 2321 bool
1536 def_bool $(cc-option, -fsanitize=shad !! 2322 default "y"
>> 2323 depends on MIPS_VPE_LOADER && !MIPS_CMP
1537 2324
1538 config PARAVIRT !! 2325 config MIPS_VPE_LOADER_TOM
1539 bool "Enable paravirtualization code" !! 2326 bool "Load VPE program into memory hidden from linux"
>> 2327 depends on MIPS_VPE_LOADER
>> 2328 default y
1540 help 2329 help
1541 This changes the kernel so it can m !! 2330 The loader can use memory that is present but has been hidden from
1542 under a hypervisor, potentially imp !! 2331 Linux using the kernel command line option "mem=xxMB". It's up to
1543 over full virtualization. !! 2332 you to ensure the amount you put in the option and the space your
>> 2333 program requires is less or equal to the amount physically present.
1544 2334
1545 config PARAVIRT_TIME_ACCOUNTING !! 2335 config MIPS_VPE_APSP_API
1546 bool "Paravirtual steal time accounti !! 2336 bool "Enable support for AP/SP API (RTLX)"
1547 select PARAVIRT !! 2337 depends on MIPS_VPE_LOADER
1548 help <<
1549 Select this option to enable fine g <<
1550 accounting. Time spent executing ot <<
1551 the current vCPU is discounted from <<
1552 that, there can be a small performa <<
1553 2338
1554 If in doubt, say N here. !! 2339 config MIPS_VPE_APSP_API_CMP
>> 2340 bool
>> 2341 default "y"
>> 2342 depends on MIPS_VPE_APSP_API && MIPS_CMP
1555 2343
1556 config ARCH_SUPPORTS_KEXEC !! 2344 config MIPS_VPE_APSP_API_MT
1557 def_bool PM_SLEEP_SMP !! 2345 bool
>> 2346 default "y"
>> 2347 depends on MIPS_VPE_APSP_API && !MIPS_CMP
1558 2348
1559 config ARCH_SUPPORTS_KEXEC_FILE !! 2349 config MIPS_CMP
1560 def_bool y !! 2350 bool "MIPS CMP framework support (DEPRECATED)"
>> 2351 depends on SYS_SUPPORTS_MIPS_CMP && !CPU_MIPSR6
>> 2352 select SMP
>> 2353 select SYNC_R4K
>> 2354 select SYS_SUPPORTS_SMP
>> 2355 select WEAK_ORDERING
>> 2356 default n
>> 2357 help
>> 2358 Select this if you are using a bootloader which implements the "CMP
>> 2359 framework" protocol (ie. YAMON) and want your kernel to make use of
>> 2360 its ability to start secondary CPUs.
>> 2361
>> 2362 Unless you have a specific need, you should use CONFIG_MIPS_CPS
>> 2363 instead of this.
>> 2364
>> 2365 config MIPS_CPS
>> 2366 bool "MIPS Coherent Processing System support"
>> 2367 depends on SYS_SUPPORTS_MIPS_CPS
>> 2368 select MIPS_CM
>> 2369 select MIPS_CPS_PM if HOTPLUG_CPU
>> 2370 select SMP
>> 2371 select SYNC_R4K if (CEVT_R4K || CSRC_R4K)
>> 2372 select SYS_SUPPORTS_HOTPLUG_CPU
>> 2373 select SYS_SUPPORTS_SCHED_SMT if CPU_MIPSR6
>> 2374 select SYS_SUPPORTS_SMP
>> 2375 select WEAK_ORDERING
>> 2376 help
>> 2377 Select this if you wish to run an SMP kernel across multiple cores
>> 2378 within a MIPS Coherent Processing System. When this option is
>> 2379 enabled the kernel will probe for other cores and boot them with
>> 2380 no external assistance. It is safe to enable this when hardware
>> 2381 support is unavailable.
1561 2382
1562 config ARCH_SELECTS_KEXEC_FILE !! 2383 config MIPS_CPS_PM
1563 def_bool y !! 2384 depends on MIPS_CPS
1564 depends on KEXEC_FILE !! 2385 bool
1565 select HAVE_IMA_KEXEC if IMA <<
1566 2386
1567 config ARCH_SUPPORTS_KEXEC_SIG !! 2387 config MIPS_CM
1568 def_bool y !! 2388 bool
>> 2389 select MIPS_CPC
1569 2390
1570 config ARCH_SUPPORTS_KEXEC_IMAGE_VERIFY_SIG !! 2391 config MIPS_CPC
1571 def_bool y !! 2392 bool
1572 2393
1573 config ARCH_DEFAULT_KEXEC_IMAGE_VERIFY_SIG !! 2394 config SB1_PASS_2_WORKAROUNDS
1574 def_bool y !! 2395 bool
>> 2396 depends on CPU_SB1 && (CPU_SB1_PASS_2_2 || CPU_SB1_PASS_2)
>> 2397 default y
1575 2398
1576 config ARCH_SUPPORTS_CRASH_DUMP !! 2399 config SB1_PASS_2_1_WORKAROUNDS
1577 def_bool y !! 2400 bool
>> 2401 depends on CPU_SB1 && CPU_SB1_PASS_2
>> 2402 default y
1578 2403
1579 config ARCH_HAS_GENERIC_CRASHKERNEL_RESERVATI <<
1580 def_bool CRASH_RESERVE <<
1581 2404
1582 config TRANS_TABLE !! 2405 config ARCH_PHYS_ADDR_T_64BIT
1583 def_bool y !! 2406 bool
1584 depends on HIBERNATION || KEXEC_CORE <<
1585 2407
1586 config XEN_DOM0 !! 2408 choice
1587 def_bool y !! 2409 prompt "SmartMIPS or microMIPS ASE support"
1588 depends on XEN <<
1589 2410
1590 config XEN !! 2411 config CPU_NEEDS_NO_SMARTMIPS_OR_MICROMIPS
1591 bool "Xen guest support on ARM64" !! 2412 bool "None"
1592 depends on ARM64 && OF <<
1593 select SWIOTLB_XEN <<
1594 select PARAVIRT <<
1595 help 2413 help
1596 Say Y if you want to run Linux in a !! 2414 Select this if you want neither microMIPS nor SmartMIPS support
1597 2415
1598 # include/linux/mmzone.h requires the followi !! 2416 config CPU_HAS_SMARTMIPS
1599 # !! 2417 depends on SYS_SUPPORTS_SMARTMIPS
1600 # MAX_PAGE_ORDER + PAGE_SHIFT <= SECTION_SI !! 2418 bool "SmartMIPS"
1601 # !! 2419 help
1602 # so the maximum value of MAX_PAGE_ORDER is S !! 2420 SmartMIPS is a extension of the MIPS32 architecture aimed at
1603 # !! 2421 increased security at both hardware and software level for
1604 # | SECTION_SIZE_BITS | PAGE_SHIFT | m !! 2422 smartcards. Enabling this option will allow proper use of the
1605 # ----+-------------------+--------------+--- !! 2423 SmartMIPS instructions by Linux applications. However a kernel with
1606 # 4K | 27 | 12 | !! 2424 this option will not work on a MIPS core without SmartMIPS core. If
1607 # 16K | 27 | 14 | !! 2425 you don't know you probably don't have SmartMIPS and should say N
1608 # 64K | 29 | 16 | !! 2426 here.
1609 config ARCH_FORCE_MAX_ORDER !! 2427
1610 int !! 2428 config CPU_MICROMIPS
1611 default "13" if ARM64_64K_PAGES !! 2429 depends on 32BIT && SYS_SUPPORTS_MICROMIPS && !CPU_MIPSR6
1612 default "11" if ARM64_16K_PAGES !! 2430 bool "microMIPS"
1613 default "10" <<
1614 help 2431 help
1615 The kernel page allocator limits th !! 2432 When this option is enabled the kernel will be built using the
1616 contiguous allocations. The limit i !! 2433 microMIPS ISA
1617 defines the maximal power of two of <<
1618 allocated as a single contiguous bl <<
1619 overriding the default setting when <<
1620 large blocks of physically contiguo <<
1621 <<
1622 The maximal size of allocation cann <<
1623 section, so the value of MAX_PAGE_O <<
1624 2434
1625 MAX_PAGE_ORDER + PAGE_SHIFT <= SE !! 2435 endchoice
1626 <<
1627 Don't change if unsure. <<
1628 2436
1629 config UNMAP_KERNEL_AT_EL0 !! 2437 config CPU_HAS_MSA
1630 bool "Unmap kernel when running in us !! 2438 bool "Support for the MIPS SIMD Architecture"
1631 default y !! 2439 depends on CPU_SUPPORTS_MSA
1632 help !! 2440 depends on 64BIT || MIPS_O32_FP64_SUPPORT
1633 Speculation attacks against some hi !! 2441 help
1634 be used to bypass MMU permission ch !! 2442 MIPS SIMD Architecture (MSA) introduces 128 bit wide vector registers
1635 userspace. This can be defended aga !! 2443 and a set of SIMD instructions to operate on them. When this option
1636 when running in userspace, mapping !! 2444 is enabled the kernel will support allocating & switching MSA
1637 via a trampoline page in the vector !! 2445 vector register contexts. If you know that your kernel will only be
>> 2446 running on CPUs which do not support MSA or that your userland will
>> 2447 not be making use of it then you may wish to say N here to reduce
>> 2448 the size & complexity of your kernel.
1638 2449
1639 If unsure, say Y. 2450 If unsure, say Y.
1640 2451
1641 config MITIGATE_SPECTRE_BRANCH_HISTORY !! 2452 config CPU_HAS_WB
1642 bool "Mitigate Spectre style attacks !! 2453 bool
1643 default y <<
1644 help <<
1645 Speculation attacks against some hi <<
1646 make use of branch history to influ <<
1647 When taking an exception from user- <<
1648 or a firmware call overwrites the b <<
1649 2454
1650 config RODATA_FULL_DEFAULT_ENABLED !! 2455 config XKS01
1651 bool "Apply r/o permissions of VM are !! 2456 bool
1652 default y !! 2457
1653 help !! 2458 config CPU_HAS_RIXI
1654 Apply read-only attributes of VM ar !! 2459 bool
1655 the backing pages as well. This pre <<
1656 from being modified (inadvertently <<
1657 mapping of the same memory page. Th <<
1658 be turned off at runtime by passing <<
1659 with rodata=full if this option is <<
1660 2460
1661 This requires the linear region to !! 2461 #
1662 which may adversely affect performa !! 2462 # Vectored interrupt mode is an R2 feature
>> 2463 #
>> 2464 config CPU_MIPSR2_IRQ_VI
>> 2465 bool
1663 2466
1664 config ARM64_SW_TTBR0_PAN !! 2467 #
1665 bool "Emulate Privileged Access Never !! 2468 # Extended interrupt mode is an R2 feature
1666 depends on !KCSAN !! 2469 #
1667 help !! 2470 config CPU_MIPSR2_IRQ_EI
1668 Enabling this option prevents the k !! 2471 bool
1669 user-space memory directly by point <<
1670 zeroed area and reserved ASID. The <<
1671 restore the valid TTBR0_EL1 tempora <<
1672 2472
1673 config ARM64_TAGGED_ADDR_ABI !! 2473 config CPU_HAS_SYNC
1674 bool "Enable the tagged user addresse !! 2474 bool
>> 2475 depends on !CPU_R3000
1675 default y 2476 default y
1676 help <<
1677 When this option is enabled, user a <<
1678 relaxed ABI via prctl() allowing ta <<
1679 to system calls as pointer argument <<
1680 Documentation/arch/arm64/tagged-add <<
1681 2477
1682 menuconfig COMPAT !! 2478 #
1683 bool "Kernel support for 32-bit EL0" !! 2479 # CPU non-features
1684 depends on ARM64_4K_PAGES || EXPERT !! 2480 #
1685 select HAVE_UID16 !! 2481 config CPU_DADDI_WORKAROUNDS
1686 select OLD_SIGSUSPEND3 !! 2482 bool
1687 select COMPAT_OLD_SIGACTION <<
1688 help <<
1689 This option enables support for a 3 <<
1690 kernel at EL1. AArch32-specific com <<
1691 the user helper functions, VFP supp <<
1692 handled appropriately by the kernel <<
1693 2483
1694 If you use a page size other than 4 !! 2484 config CPU_R4000_WORKAROUNDS
1695 that you will only be able to execu !! 2485 bool
1696 with page size aligned segments. !! 2486 select CPU_R4400_WORKAROUNDS
1697 2487
1698 If you want to execute 32-bit users !! 2488 config CPU_R4400_WORKAROUNDS
>> 2489 bool
1699 2490
1700 if COMPAT !! 2491 config MIPS_ASID_SHIFT
>> 2492 int
>> 2493 default 6 if CPU_R3000 || CPU_TX39XX
>> 2494 default 4 if CPU_R8000
>> 2495 default 0
1701 2496
1702 config KUSER_HELPERS !! 2497 config MIPS_ASID_BITS
1703 bool "Enable kuser helpers page for 3 !! 2498 int
1704 default y !! 2499 default 0 if MIPS_ASID_BITS_VARIABLE
1705 help !! 2500 default 6 if CPU_R3000 || CPU_TX39XX
1706 Warning: disabling this option may !! 2501 default 8
1707 2502
1708 Provide kuser helpers to compat tas !! 2503 config MIPS_ASID_BITS_VARIABLE
1709 helper code to userspace in read on !! 2504 bool
1710 to allow userspace to be independen <<
1711 the system. This permits binaries t <<
1712 to ARMv8 without modification. <<
1713 2505
1714 See Documentation/arch/arm/kernel_u !! 2506 config MIPS_CRC_SUPPORT
>> 2507 bool
1715 2508
1716 However, the fixed address nature o !! 2509 #
1717 by ROP (return orientated programmi !! 2510 # - Highmem only makes sense for the 32-bit kernel.
1718 exploits. !! 2511 # - The current highmem code will only work properly on physically indexed
>> 2512 # caches such as R3000, SB1, R7000 or those that look like they're virtually
>> 2513 # indexed such as R4000/R4400 SC and MC versions or R10000. So for the
>> 2514 # moment we protect the user and offer the highmem option only on machines
>> 2515 # where it's known to be safe. This will not offer highmem on a few systems
>> 2516 # such as MIPS32 and MIPS64 CPUs which may have virtual and physically
>> 2517 # indexed CPUs but we're playing safe.
>> 2518 # - We use SYS_SUPPORTS_HIGHMEM to offer highmem only for systems where we
>> 2519 # know they might have memory configurations that could make use of highmem
>> 2520 # support.
>> 2521 #
>> 2522 config HIGHMEM
>> 2523 bool "High Memory Support"
>> 2524 depends on 32BIT && CPU_SUPPORTS_HIGHMEM && SYS_SUPPORTS_HIGHMEM && !CPU_MIPS32_3_5_EVA
1719 2525
1720 If all of the binaries and librarie !! 2526 config CPU_SUPPORTS_HIGHMEM
1721 are built specifically for your pla !! 2527 bool
1722 these helpers, then you can turn th <<
1723 such exploits. However, in that cas <<
1724 relying on those helpers is run, it <<
1725 2528
1726 Say N here only if you are absolute !! 2529 config SYS_SUPPORTS_HIGHMEM
1727 need these helpers; otherwise, the !! 2530 bool
1728 2531
1729 config COMPAT_VDSO !! 2532 config SYS_SUPPORTS_SMARTMIPS
1730 bool "Enable vDSO for 32-bit applicat !! 2533 bool
1731 depends on !CPU_BIG_ENDIAN <<
1732 depends on (CC_IS_CLANG && LD_IS_LLD) <<
1733 select GENERIC_COMPAT_VDSO <<
1734 default y <<
1735 help <<
1736 Place in the process address space <<
1737 ELF shared object providing fast im <<
1738 and clock_gettime. <<
1739 2534
1740 You must have a 32-bit build of gli !! 2535 config SYS_SUPPORTS_MICROMIPS
1741 to seamlessly take advantage of thi !! 2536 bool
1742 2537
1743 config THUMB2_COMPAT_VDSO !! 2538 config SYS_SUPPORTS_MIPS16
1744 bool "Compile the 32-bit vDSO for Thu !! 2539 bool
1745 depends on COMPAT_VDSO <<
1746 default y <<
1747 help 2540 help
1748 Compile the compat vDSO with '-mthu !! 2541 This option must be set if a kernel might be executed on a MIPS16-
1749 otherwise with '-marm'. !! 2542 enabled CPU even if MIPS16 is not actually being used. In other
1750 !! 2543 words, it makes the kernel MIPS16-tolerant.
1751 config COMPAT_ALIGNMENT_FIXUPS <<
1752 bool "Fix up misaligned multi-word lo <<
1753 2544
1754 menuconfig ARMV8_DEPRECATED !! 2545 config CPU_SUPPORTS_MSA
1755 bool "Emulate deprecated/obsolete ARM !! 2546 bool
1756 depends on SYSCTL <<
1757 help <<
1758 Legacy software support may require <<
1759 that have been deprecated or obsole <<
1760 2547
1761 Enable this config to enable select !! 2548 config ARCH_FLATMEM_ENABLE
1762 features. !! 2549 def_bool y
>> 2550 depends on !NUMA && !CPU_LOONGSON2
1763 2551
1764 If unsure, say Y !! 2552 config ARCH_DISCONTIGMEM_ENABLE
>> 2553 bool
>> 2554 default y if SGI_IP27
>> 2555 help
>> 2556 Say Y to support efficient handling of discontiguous physical memory,
>> 2557 for architectures which are either NUMA (Non-Uniform Memory Access)
>> 2558 or have huge holes in the physical address space for other reasons.
>> 2559 See <file:Documentation/vm/numa> for more.
1765 2560
1766 if ARMV8_DEPRECATED !! 2561 config ARCH_SPARSEMEM_ENABLE
>> 2562 bool
>> 2563 select SPARSEMEM_STATIC
1767 2564
1768 config SWP_EMULATION !! 2565 config NUMA
1769 bool "Emulate SWP/SWPB instructions" !! 2566 bool "NUMA Support"
>> 2567 depends on SYS_SUPPORTS_NUMA
1770 help 2568 help
1771 ARMv8 obsoletes the use of A32 SWP/ !! 2569 Say Y to compile the kernel to support NUMA (Non-Uniform Memory
1772 they are always undefined. Say Y he !! 2570 Access). This option improves performance on systems with more
1773 emulation of these instructions for !! 2571 than two nodes; on two node systems it is generally better to
1774 This feature can be controlled at r !! 2572 leave it disabled; on single node systems disable this option
1775 sysctl which is disabled by default !! 2573 disabled.
1776 2574
1777 In some older versions of glibc [<= !! 2575 config SYS_SUPPORTS_NUMA
1778 trylock() operations with the assum !! 2576 bool
1779 be preempted. This invalid assumpti <<
1780 with SWP emulation enabled, leading <<
1781 application. <<
1782 2577
1783 NOTE: when accessing uncached share !! 2578 config RELOCATABLE
1784 on an external transaction monitori !! 2579 bool "Relocatable kernel"
1785 monitor to maintain update atomicit !! 2580 depends on SYS_SUPPORTS_RELOCATABLE && (CPU_MIPS32_R2 || CPU_MIPS64_R2 || CPU_MIPS32_R6 || CPU_MIPS64_R6 || CAVIUM_OCTEON_SOC)
1786 implement a global monitor, this op !! 2581 help
1787 perform SWP operations to uncached !! 2582 This builds a kernel image that retains relocation information
>> 2583 so it can be loaded someplace besides the default 1MB.
>> 2584 The relocations make the kernel binary about 15% larger,
>> 2585 but are discarded at runtime
>> 2586
>> 2587 config RELOCATION_TABLE_SIZE
>> 2588 hex "Relocation table size"
>> 2589 depends on RELOCATABLE
>> 2590 range 0x0 0x01000000
>> 2591 default "0x00100000"
>> 2592 ---help---
>> 2593 A table of relocation data will be appended to the kernel binary
>> 2594 and parsed at boot to fix up the relocated kernel.
1788 2595
1789 If unsure, say Y !! 2596 This option allows the amount of space reserved for the table to be
>> 2597 adjusted, although the default of 1Mb should be ok in most cases.
1790 2598
1791 config CP15_BARRIER_EMULATION !! 2599 The build will fail and a valid size suggested if this is too small.
1792 bool "Emulate CP15 Barrier instructio <<
1793 help <<
1794 The CP15 barrier instructions - CP1 <<
1795 CP15DMB - are deprecated in ARMv8 ( <<
1796 strongly recommended to use the ISB <<
1797 instructions instead. <<
1798 2600
1799 Say Y here to enable software emula !! 2601 If unsure, leave at the default value.
1800 instructions for AArch32 userspace <<
1801 enabled, CP15 barrier usage is trac <<
1802 identify software that needs updati <<
1803 controlled at runtime with the abi. <<
1804 2602
1805 If unsure, say Y !! 2603 config RANDOMIZE_BASE
>> 2604 bool "Randomize the address of the kernel image"
>> 2605 depends on RELOCATABLE
>> 2606 ---help---
>> 2607 Randomizes the physical and virtual address at which the
>> 2608 kernel image is loaded, as a security feature that
>> 2609 deters exploit attempts relying on knowledge of the location
>> 2610 of kernel internals.
1806 2611
1807 config SETEND_EMULATION !! 2612 Entropy is generated using any coprocessor 0 registers available.
1808 bool "Emulate SETEND instruction" <<
1809 help <<
1810 The SETEND instruction alters the d <<
1811 AArch32 EL0, and is deprecated in A <<
1812 2613
1813 Say Y here to enable software emula !! 2614 The kernel will be offset by up to RANDOMIZE_BASE_MAX_OFFSET.
1814 for AArch32 userspace code. This fe <<
1815 at runtime with the abi.setend sysc <<
1816 2615
1817 Note: All the cpus on the system mu !! 2616 If unsure, say N.
1818 for this feature to be enabled. If <<
1819 endian - is hotplugged in after thi <<
1820 be unexpected results in the applic <<
1821 2617
1822 If unsure, say Y !! 2618 config RANDOMIZE_BASE_MAX_OFFSET
1823 endif # ARMV8_DEPRECATED !! 2619 hex "Maximum kASLR offset" if EXPERT
>> 2620 depends on RANDOMIZE_BASE
>> 2621 range 0x0 0x40000000 if EVA || 64BIT
>> 2622 range 0x0 0x08000000
>> 2623 default "0x01000000"
>> 2624 ---help---
>> 2625 When kASLR is active, this provides the maximum offset that will
>> 2626 be applied to the kernel image. It should be set according to the
>> 2627 amount of physical RAM available in the target system minus
>> 2628 PHYSICAL_START and must be a power of 2.
1824 2629
1825 endif # COMPAT !! 2630 This is limited by the size of KSEG0, 256Mb on 32-bit or 1Gb with
>> 2631 EVA or 64-bit. The default is 16Mb.
1826 2632
1827 menu "ARMv8.1 architectural features" !! 2633 config NODES_SHIFT
>> 2634 int
>> 2635 default "6"
>> 2636 depends on NEED_MULTIPLE_NODES
1828 2637
1829 config ARM64_HW_AFDBM !! 2638 config HW_PERF_EVENTS
1830 bool "Support for hardware updates of !! 2639 bool "Enable hardware performance counter support for perf events"
>> 2640 depends on PERF_EVENTS && !OPROFILE && (CPU_MIPS32 || CPU_MIPS64 || CPU_R10000 || CPU_SB1 || CPU_CAVIUM_OCTEON || CPU_XLP || CPU_LOONGSON3)
1831 default y 2641 default y
1832 help 2642 help
1833 The ARMv8.1 architecture extensions !! 2643 Enable hardware performance counter support for perf events. If
1834 hardware updates of the access and !! 2644 disabled, perf events will use software events only.
1835 table entries. When enabled in TCR_ <<
1836 capable processors, accesses to pag <<
1837 set this bit instead of raising an <<
1838 Similarly, writes to read-only page <<
1839 clear the read-only bit (AP[2]) ins <<
1840 permission fault. <<
1841 2645
1842 Kernels built with this configurati !! 2646 source "mm/Kconfig"
1843 to work on pre-ARMv8.1 hardware and <<
1844 minimal. If unsure, say Y. <<
1845 2647
1846 config ARM64_PAN !! 2648 config SMP
1847 bool "Enable support for Privileged A !! 2649 bool "Multi-Processing support"
1848 default y !! 2650 depends on SYS_SUPPORTS_SMP
1849 help 2651 help
1850 Privileged Access Never (PAN; part !! 2652 This enables support for systems with more than one CPU. If you have
1851 prevents the kernel or hypervisor f !! 2653 a system with only one CPU, say N. If you have a system with more
1852 memory directly. !! 2654 than one CPU, say Y.
1853 !! 2655
1854 Choosing this option will cause any !! 2656 If you say N here, the kernel will run on uni- and multiprocessor
1855 copy_to_user et al) memory access t !! 2657 machines, but will use only one CPU of a multiprocessor machine. If
>> 2658 you say Y here, the kernel will run on many, but not all,
>> 2659 uniprocessor machines. On a uniprocessor machine, the kernel
>> 2660 will run faster if you say N here.
1856 2661
1857 The feature is detected at runtime, !! 2662 People using multiprocessor machines who say Y here should also say
1858 instruction if the cpu does not imp !! 2663 Y to "Enhanced Real Time Clock Support", below.
1859 2664
1860 config AS_HAS_LSE_ATOMICS !! 2665 See also the SMP-HOWTO available at
1861 def_bool $(as-instr,.arch_extension l !! 2666 <http://www.tldp.org/docs.html#howto>.
1862 2667
1863 config ARM64_LSE_ATOMICS !! 2668 If you don't know what to do here, say N.
1864 bool <<
1865 default ARM64_USE_LSE_ATOMICS <<
1866 depends on AS_HAS_LSE_ATOMICS <<
1867 2669
1868 config ARM64_USE_LSE_ATOMICS !! 2670 config HOTPLUG_CPU
1869 bool "Atomic instructions" !! 2671 bool "Support for hot-pluggable CPUs"
1870 default y !! 2672 depends on SMP && SYS_SUPPORTS_HOTPLUG_CPU
1871 help 2673 help
1872 As part of the Large System Extensi !! 2674 Say Y here to allow turning CPUs off and on. CPUs can be
1873 atomic instructions that are design !! 2675 controlled through /sys/devices/system/cpu.
1874 very large systems. !! 2676 (Note: power management support will enable this option
>> 2677 automatically on SMP systems. )
>> 2678 Say N if you want to disable CPU hotplug.
1875 2679
1876 Say Y here to make use of these ins !! 2680 config SMP_UP
1877 atomic routines. This incurs a smal !! 2681 bool
1878 not support these instructions and <<
1879 built with binutils >= 2.25 in orde <<
1880 to be used. <<
1881 2682
1882 endmenu # "ARMv8.1 architectural features" !! 2683 config SYS_SUPPORTS_MIPS_CMP
>> 2684 bool
1883 2685
1884 menu "ARMv8.2 architectural features" !! 2686 config SYS_SUPPORTS_MIPS_CPS
>> 2687 bool
1885 2688
1886 config AS_HAS_ARMV8_2 !! 2689 config SYS_SUPPORTS_SMP
1887 def_bool $(cc-option,-Wa$(comma)-marc !! 2690 bool
1888 2691
1889 config AS_HAS_SHA3 !! 2692 config NR_CPUS_DEFAULT_4
1890 def_bool $(as-instr,.arch armv8.2-a+s !! 2693 bool
1891 2694
1892 config ARM64_PMEM !! 2695 config NR_CPUS_DEFAULT_8
1893 bool "Enable support for persistent m !! 2696 bool
1894 select ARCH_HAS_PMEM_API <<
1895 select ARCH_HAS_UACCESS_FLUSHCACHE <<
1896 help <<
1897 Say Y to enable support for the per <<
1898 ARMv8.2 DCPoP feature. <<
1899 2697
1900 The feature is detected at runtime, !! 2698 config NR_CPUS_DEFAULT_16
1901 operations if DC CVAP is not suppor !! 2699 bool
1902 DC CVAP itself if the system does n <<
1903 2700
1904 config ARM64_RAS_EXTN !! 2701 config NR_CPUS_DEFAULT_32
1905 bool "Enable support for RAS CPU Exte !! 2702 bool
1906 default y <<
1907 help <<
1908 CPUs that support the Reliability, <<
1909 (RAS) Extensions, part of ARMv8.2 a <<
1910 errors, classify them and report th <<
1911 2703
1912 On CPUs with these extensions syste !! 2704 config NR_CPUS_DEFAULT_64
1913 barriers to determine if faults are !! 2705 bool
1914 classification from a new set of re <<
1915 2706
1916 Selecting this feature will allow t !! 2707 config NR_CPUS
1917 and access the new registers if the !! 2708 int "Maximum number of CPUs (2-256)"
1918 Platform RAS features may additiona !! 2709 range 2 256
>> 2710 depends on SMP
>> 2711 default "4" if NR_CPUS_DEFAULT_4
>> 2712 default "8" if NR_CPUS_DEFAULT_8
>> 2713 default "16" if NR_CPUS_DEFAULT_16
>> 2714 default "32" if NR_CPUS_DEFAULT_32
>> 2715 default "64" if NR_CPUS_DEFAULT_64
>> 2716 help
>> 2717 This allows you to specify the maximum number of CPUs which this
>> 2718 kernel will support. The maximum supported value is 32 for 32-bit
>> 2719 kernel and 64 for 64-bit kernels; the minimum value which makes
>> 2720 sense is 1 for Qemu (useful only for kernel debugging purposes)
>> 2721 and 2 for all others.
>> 2722
>> 2723 This is purely to save memory - each supported CPU adds
>> 2724 approximately eight kilobytes to the kernel image. For best
>> 2725 performance should round up your number of processors to the next
>> 2726 power of two.
1919 2727
1920 config ARM64_CNP !! 2728 config MIPS_PERF_SHARED_TC_COUNTERS
1921 bool "Enable support for Common Not P !! 2729 bool
1922 default y <<
1923 depends on ARM64_PAN || !ARM64_SW_TTB <<
1924 help <<
1925 Common Not Private (CNP) allows tra <<
1926 be shared between different PEs in <<
1927 domain, so the hardware can use thi <<
1928 caching of such entries in the TLB. <<
1929 2730
1930 Selecting this option allows the CN !! 2731 config MIPS_NR_CPU_NR_MAP_1024
1931 at runtime, and does not affect PEs !! 2732 bool
1932 this feature. <<
1933 2733
1934 endmenu # "ARMv8.2 architectural features" !! 2734 config MIPS_NR_CPU_NR_MAP
>> 2735 int
>> 2736 depends on SMP
>> 2737 default 1024 if MIPS_NR_CPU_NR_MAP_1024
>> 2738 default NR_CPUS if !MIPS_NR_CPU_NR_MAP_1024
1935 2739
1936 menu "ARMv8.3 architectural features" !! 2740 #
>> 2741 # Timer Interrupt Frequency Configuration
>> 2742 #
1937 2743
1938 config ARM64_PTR_AUTH !! 2744 choice
1939 bool "Enable support for pointer auth !! 2745 prompt "Timer frequency"
1940 default y !! 2746 default HZ_250
1941 help 2747 help
1942 Pointer authentication (part of the !! 2748 Allows the configuration of the timer frequency.
1943 instructions for signing and authen <<
1944 keys, which can be used to mitigate <<
1945 and other attacks. <<
1946 2749
1947 This option enables these instructi !! 2750 config HZ_24
1948 Choosing this option will cause the !! 2751 bool "24 HZ" if SYS_SUPPORTS_24HZ || SYS_SUPPORTS_ARBIT_HZ
1949 for each process at exec() time, wi <<
1950 context-switched along with the pro <<
1951 2752
1952 The feature is detected at runtime. !! 2753 config HZ_48
1953 hardware it will not be advertised !! 2754 bool "48 HZ" if SYS_SUPPORTS_48HZ || SYS_SUPPORTS_ARBIT_HZ
1954 be enabled. <<
1955 2755
1956 If the feature is present on the bo !! 2756 config HZ_100
1957 the late CPU will be parked. Also, !! 2757 bool "100 HZ" if SYS_SUPPORTS_100HZ || SYS_SUPPORTS_ARBIT_HZ
1958 address auth and the late CPU has t <<
1959 but with the feature disabled. On s <<
1960 not be selected. <<
1961 2758
1962 config ARM64_PTR_AUTH_KERNEL !! 2759 config HZ_128
1963 bool "Use pointer authentication for !! 2760 bool "128 HZ" if SYS_SUPPORTS_128HZ || SYS_SUPPORTS_ARBIT_HZ
1964 default y <<
1965 depends on ARM64_PTR_AUTH <<
1966 depends on (CC_HAS_SIGN_RETURN_ADDRES <<
1967 # Modern compilers insert a .note.gnu <<
1968 # which is only understood by binutil <<
1969 depends on LD_IS_LLD || LD_VERSION >= <<
1970 depends on !CC_IS_CLANG || AS_HAS_CFI <<
1971 depends on (!FUNCTION_GRAPH_TRACER || <<
1972 help <<
1973 If the compiler supports the -mbran <<
1974 -msign-return-address flag (e.g. GC <<
1975 will cause the kernel itself to be <<
1976 protection. In this case, and if th <<
1977 support pointer authentication, the <<
1978 disabled with minimal loss of prote <<
1979 2761
1980 This feature works with FUNCTION_GR !! 2762 config HZ_250
1981 DYNAMIC_FTRACE_WITH_ARGS is enabled !! 2763 bool "250 HZ" if SYS_SUPPORTS_250HZ || SYS_SUPPORTS_ARBIT_HZ
1982 2764
1983 config CC_HAS_BRANCH_PROT_PAC_RET !! 2765 config HZ_256
1984 # GCC 9 or later, clang 8 or later !! 2766 bool "256 HZ" if SYS_SUPPORTS_256HZ || SYS_SUPPORTS_ARBIT_HZ
1985 def_bool $(cc-option,-mbranch-protect <<
1986 2767
1987 config CC_HAS_SIGN_RETURN_ADDRESS !! 2768 config HZ_1000
1988 # GCC 7, 8 !! 2769 bool "1000 HZ" if SYS_SUPPORTS_1000HZ || SYS_SUPPORTS_ARBIT_HZ
1989 def_bool $(cc-option,-msign-return-ad <<
1990 2770
1991 config AS_HAS_ARMV8_3 !! 2771 config HZ_1024
1992 def_bool $(cc-option,-Wa$(comma)-marc !! 2772 bool "1024 HZ" if SYS_SUPPORTS_1024HZ || SYS_SUPPORTS_ARBIT_HZ
1993 2773
1994 config AS_HAS_CFI_NEGATE_RA_STATE !! 2774 endchoice
1995 def_bool $(as-instr,.cfi_startproc\n. <<
1996 2775
1997 config AS_HAS_LDAPR !! 2776 config SYS_SUPPORTS_24HZ
1998 def_bool $(as-instr,.arch_extension r !! 2777 bool
1999 2778
2000 endmenu # "ARMv8.3 architectural features" !! 2779 config SYS_SUPPORTS_48HZ
>> 2780 bool
2001 2781
2002 menu "ARMv8.4 architectural features" !! 2782 config SYS_SUPPORTS_100HZ
>> 2783 bool
2003 2784
2004 config ARM64_AMU_EXTN !! 2785 config SYS_SUPPORTS_128HZ
2005 bool "Enable support for the Activity !! 2786 bool
2006 default y <<
2007 help <<
2008 The activity monitors extension is <<
2009 by the ARMv8.4 CPU architecture. Th <<
2010 of the activity monitors architectu <<
2011 2787
2012 To enable the use of this extension !! 2788 config SYS_SUPPORTS_250HZ
>> 2789 bool
2013 2790
2014 Note that for architectural reasons !! 2791 config SYS_SUPPORTS_256HZ
2015 support when running on CPUs that p !! 2792 bool
2016 extension. The required support is <<
2017 * Version 1.5 and later of the AR <<
2018 2793
2019 For kernels that have this configur !! 2794 config SYS_SUPPORTS_1000HZ
2020 firmware, you may need to say N her !! 2795 bool
2021 Otherwise you may experience firmwa <<
2022 accessing the counter registers. Ev <<
2023 symptoms, the values returned by th <<
2024 correctly reflect reality. Most com <<
2025 indicating that the counter is not <<
2026 2796
2027 config AS_HAS_ARMV8_4 !! 2797 config SYS_SUPPORTS_1024HZ
2028 def_bool $(cc-option,-Wa$(comma)-marc !! 2798 bool
2029 2799
2030 config ARM64_TLB_RANGE !! 2800 config SYS_SUPPORTS_ARBIT_HZ
2031 bool "Enable support for tlbi range f !! 2801 bool
2032 default y !! 2802 default y if !SYS_SUPPORTS_24HZ && \
2033 depends on AS_HAS_ARMV8_4 !! 2803 !SYS_SUPPORTS_48HZ && \
2034 help !! 2804 !SYS_SUPPORTS_100HZ && \
2035 ARMv8.4-TLBI provides TLBI invalida !! 2805 !SYS_SUPPORTS_128HZ && \
2036 range of input addresses. !! 2806 !SYS_SUPPORTS_250HZ && \
>> 2807 !SYS_SUPPORTS_256HZ && \
>> 2808 !SYS_SUPPORTS_1000HZ && \
>> 2809 !SYS_SUPPORTS_1024HZ
2037 2810
2038 The feature introduces new assembly !! 2811 config HZ
2039 support when binutils >= 2.30. !! 2812 int
>> 2813 default 24 if HZ_24
>> 2814 default 48 if HZ_48
>> 2815 default 100 if HZ_100
>> 2816 default 128 if HZ_128
>> 2817 default 250 if HZ_250
>> 2818 default 256 if HZ_256
>> 2819 default 1000 if HZ_1000
>> 2820 default 1024 if HZ_1024
>> 2821
>> 2822 config SCHED_HRTICK
>> 2823 def_bool HIGH_RES_TIMERS
>> 2824
>> 2825 source "kernel/Kconfig.preempt"
>> 2826
>> 2827 config KEXEC
>> 2828 bool "Kexec system call"
>> 2829 select KEXEC_CORE
>> 2830 help
>> 2831 kexec is a system call that implements the ability to shutdown your
>> 2832 current kernel, and to start another kernel. It is like a reboot
>> 2833 but it is independent of the system firmware. And like a reboot
>> 2834 you can start any kernel with it, not just Linux.
>> 2835
>> 2836 The name comes from the similarity to the exec system call.
>> 2837
>> 2838 It is an ongoing process to be certain the hardware in a machine
>> 2839 is properly shutdown, so do not be surprised if this code does not
>> 2840 initially work for you. As of this writing the exact hardware
>> 2841 interface is strongly in flux, so no good recommendation can be
>> 2842 made.
>> 2843
>> 2844 config CRASH_DUMP
>> 2845 bool "Kernel crash dumps"
>> 2846 help
>> 2847 Generate crash dump after being started by kexec.
>> 2848 This should be normally only set in special crash dump kernels
>> 2849 which are loaded in the main kernel with kexec-tools into
>> 2850 a specially reserved region and then later executed after
>> 2851 a crash by kdump/kexec. The crash dump kernel must be compiled
>> 2852 to a memory address not used by the main kernel or firmware using
>> 2853 PHYSICAL_START.
>> 2854
>> 2855 config PHYSICAL_START
>> 2856 hex "Physical address where the kernel is loaded"
>> 2857 default "0xffffffff84000000"
>> 2858 depends on CRASH_DUMP
>> 2859 help
>> 2860 This gives the CKSEG0 or KSEG0 address where the kernel is loaded.
>> 2861 If you plan to use kernel for capturing the crash dump change
>> 2862 this value to start of the reserved region (the "X" value as
>> 2863 specified in the "crashkernel=YM@XM" command line boot parameter
>> 2864 passed to the panic-ed kernel).
>> 2865
>> 2866 config SECCOMP
>> 2867 bool "Enable seccomp to safely compute untrusted bytecode"
>> 2868 depends on PROC_FS
>> 2869 default y
>> 2870 help
>> 2871 This kernel feature is useful for number crunching applications
>> 2872 that may need to compute untrusted bytecode during their
>> 2873 execution. By using pipes or other transports made available to
>> 2874 the process as file descriptors supporting the read/write
>> 2875 syscalls, it's possible to isolate those applications in
>> 2876 their own address space using seccomp. Once seccomp is
>> 2877 enabled via /proc/<pid>/seccomp, it cannot be disabled
>> 2878 and the task is only allowed to execute a few safe syscalls
>> 2879 defined by each seccomp mode.
>> 2880
>> 2881 If unsure, say Y. Only embedded should say N here.
>> 2882
>> 2883 config MIPS_O32_FP64_SUPPORT
>> 2884 bool "Support for O32 binaries using 64-bit FP"
>> 2885 depends on 32BIT || MIPS32_O32
>> 2886 help
>> 2887 When this is enabled, the kernel will support use of 64-bit floating
>> 2888 point registers with binaries using the O32 ABI along with the
>> 2889 EF_MIPS_FP64 ELF header flag (typically built with -mfp64). On
>> 2890 32-bit MIPS systems this support is at the cost of increasing the
>> 2891 size and complexity of the compiled FPU emulator. Thus if you are
>> 2892 running a MIPS32 system and know that none of your userland binaries
>> 2893 will require 64-bit floating point, you may wish to reduce the size
>> 2894 of your kernel & potentially improve FP emulation performance by
>> 2895 saying N here.
>> 2896
>> 2897 Although binutils currently supports use of this flag the details
>> 2898 concerning its effect upon the O32 ABI in userland are still being
>> 2899 worked on. In order to avoid userland becoming dependant upon current
>> 2900 behaviour before the details have been finalised, this option should
>> 2901 be considered experimental and only enabled by those working upon
>> 2902 said details.
2040 2903
2041 endmenu # "ARMv8.4 architectural features" !! 2904 If unsure, say N.
2042 2905
2043 menu "ARMv8.5 architectural features" !! 2906 config USE_OF
>> 2907 bool
>> 2908 select OF
>> 2909 select OF_EARLY_FLATTREE
>> 2910 select IRQ_DOMAIN
2044 2911
2045 config AS_HAS_ARMV8_5 !! 2912 config BUILTIN_DTB
2046 def_bool $(cc-option,-Wa$(comma)-marc !! 2913 bool
2047 2914
2048 config ARM64_BTI !! 2915 choice
2049 bool "Branch Target Identification su !! 2916 prompt "Kernel appended dtb support" if USE_OF
2050 default y !! 2917 default MIPS_NO_APPENDED_DTB
2051 help <<
2052 Branch Target Identification (part <<
2053 provides a mechanism to limit the s <<
2054 branch instructions such as BR or B <<
2055 2918
2056 To make use of BTI on CPUs that sup !! 2919 config MIPS_NO_APPENDED_DTB
>> 2920 bool "None"
>> 2921 help
>> 2922 Do not enable appended dtb support.
>> 2923
>> 2924 config MIPS_ELF_APPENDED_DTB
>> 2925 bool "vmlinux"
>> 2926 help
>> 2927 With this option, the boot code will look for a device tree binary
>> 2928 DTB) included in the vmlinux ELF section .appended_dtb. By default
>> 2929 it is empty and the DTB can be appended using binutils command
>> 2930 objcopy:
>> 2931
>> 2932 objcopy --update-section .appended_dtb=<filename>.dtb vmlinux
>> 2933
>> 2934 This is meant as a backward compatiblity convenience for those
>> 2935 systems with a bootloader that can't be upgraded to accommodate
>> 2936 the documented boot protocol using a device tree.
>> 2937
>> 2938 config MIPS_RAW_APPENDED_DTB
>> 2939 bool "vmlinux.bin or vmlinuz.bin"
>> 2940 help
>> 2941 With this option, the boot code will look for a device tree binary
>> 2942 DTB) appended to raw vmlinux.bin or vmlinuz.bin.
>> 2943 (e.g. cat vmlinux.bin <filename>.dtb > vmlinux_w_dtb).
>> 2944
>> 2945 This is meant as a backward compatibility convenience for those
>> 2946 systems with a bootloader that can't be upgraded to accommodate
>> 2947 the documented boot protocol using a device tree.
>> 2948
>> 2949 Beware that there is very little in terms of protection against
>> 2950 this option being confused by leftover garbage in memory that might
>> 2951 look like a DTB header after a reboot if no actual DTB is appended
>> 2952 to vmlinux.bin. Do not leave this option active in a production kernel
>> 2953 if you don't intend to always append a DTB.
>> 2954 endchoice
2057 2955
2058 BTI is intended to provide compleme !! 2956 choice
2059 flow integrity protection mechanism !! 2957 prompt "Kernel command line type" if !CMDLINE_OVERRIDE
2060 authentication mechanism provided a !! 2958 default MIPS_CMDLINE_FROM_DTB if USE_OF && !ATH79 && !MACH_INGENIC && \
2061 For this reason, it does not make s !! 2959 !MIPS_MALTA && \
2062 also enabling support for pointer a !! 2960 !CAVIUM_OCTEON_SOC
2063 enabling this option you should als !! 2961 default MIPS_CMDLINE_FROM_BOOTLOADER
>> 2962
>> 2963 config MIPS_CMDLINE_FROM_DTB
>> 2964 depends on USE_OF
>> 2965 bool "Dtb kernel arguments if available"
>> 2966
>> 2967 config MIPS_CMDLINE_DTB_EXTEND
>> 2968 depends on USE_OF
>> 2969 bool "Extend dtb kernel arguments with bootloader arguments"
>> 2970
>> 2971 config MIPS_CMDLINE_FROM_BOOTLOADER
>> 2972 bool "Bootloader kernel arguments if available"
>> 2973
>> 2974 config MIPS_CMDLINE_BUILTIN_EXTEND
>> 2975 depends on CMDLINE_BOOL
>> 2976 bool "Extend builtin kernel arguments with bootloader arguments"
>> 2977 endchoice
2064 2978
2065 Userspace binaries must also be spe !! 2979 endmenu
2066 this mechanism. If you say N here <<
2067 BTI, such binaries can still run, b <<
2068 enforcement of branch destinations. <<
2069 2980
2070 config ARM64_BTI_KERNEL !! 2981 config LOCKDEP_SUPPORT
2071 bool "Use Branch Target Identificatio !! 2982 bool
2072 default y 2983 default y
2073 depends on ARM64_BTI <<
2074 depends on ARM64_PTR_AUTH_KERNEL <<
2075 depends on CC_HAS_BRANCH_PROT_PAC_RET <<
2076 # https://gcc.gnu.org/bugzilla/show_b <<
2077 depends on !CC_IS_GCC || GCC_VERSION <<
2078 # https://gcc.gnu.org/bugzilla/show_b <<
2079 depends on !CC_IS_GCC <<
2080 depends on (!FUNCTION_GRAPH_TRACER || <<
2081 help <<
2082 Build the kernel with Branch Target <<
2083 and enable enforcement of this for <<
2084 is enabled and the system supports <<
2085 modular code must have BTI enabled. <<
2086 2984
2087 config CC_HAS_BRANCH_PROT_PAC_RET_BTI !! 2985 config STACKTRACE_SUPPORT
2088 # GCC 9 or later, clang 8 or later !! 2986 bool
2089 def_bool $(cc-option,-mbranch-protect <<
2090 <<
2091 config ARM64_E0PD <<
2092 bool "Enable support for E0PD" <<
2093 default y 2987 default y
2094 help <<
2095 E0PD (part of the ARMv8.5 extension <<
2096 that EL0 accesses made via TTBR1 al <<
2097 providing similar benefits to KASLR <<
2098 with lower overhead and without dis <<
2099 kernel memory such as SPE. <<
2100 <<
2101 This option enables E0PD for TTBR1 <<
2102 <<
2103 config ARM64_AS_HAS_MTE <<
2104 # Initial support for MTE went in bin <<
2105 # ".arch armv8.5-a+memtag" below. How <<
2106 # as a late addition to the final arc <<
2107 # is only supported in the newer 2.32 <<
2108 # versions, hence the extra "stgm" in <<
2109 def_bool $(as-instr,.arch armv8.5-a+m <<
2110 2988
2111 config ARM64_MTE !! 2989 config HAVE_LATENCYTOP_SUPPORT
2112 bool "Memory Tagging Extension suppor !! 2990 bool
2113 default y 2991 default y
2114 depends on ARM64_AS_HAS_MTE && ARM64_ <<
2115 depends on AS_HAS_ARMV8_5 <<
2116 depends on AS_HAS_LSE_ATOMICS <<
2117 # Required for tag checking in the ua <<
2118 depends on ARM64_PAN <<
2119 select ARCH_HAS_SUBPAGE_FAULTS <<
2120 select ARCH_USES_HIGH_VMA_FLAGS <<
2121 select ARCH_USES_PG_ARCH_2 <<
2122 select ARCH_USES_PG_ARCH_3 <<
2123 help <<
2124 Memory Tagging (part of the ARMv8.5 <<
2125 architectural support for run-time, <<
2126 various classes of memory error to <<
2127 to eliminate vulnerabilities arisin <<
2128 languages. <<
2129 2992
2130 This option enables the support for !! 2993 config PGTABLE_LEVELS
2131 Extension at EL0 (i.e. for userspac !! 2994 int
>> 2995 default 4 if PAGE_SIZE_4KB && MIPS_VA_BITS_48
>> 2996 default 3 if 64BIT && !PAGE_SIZE_64KB
>> 2997 default 2
2132 2998
2133 Selecting this option allows the fe !! 2999 source "init/Kconfig"
2134 runtime. Any secondary CPU not impl <<
2135 not be allowed a late bring-up. <<
2136 3000
2137 Userspace binaries that want to use !! 3001 source "kernel/Kconfig.freezer"
2138 explicitly opt in. The mechanism fo <<
2139 described in: <<
2140 3002
2141 Documentation/arch/arm64/memory-tag !! 3003 menu "Bus options (PCI, PCMCIA, EISA, ISA, TC)"
2142 3004
2143 endmenu # "ARMv8.5 architectural features" !! 3005 config HW_HAS_EISA
>> 3006 bool
>> 3007 config HW_HAS_PCI
>> 3008 bool
2144 3009
2145 menu "ARMv8.7 architectural features" !! 3010 config PCI
>> 3011 bool "Support for PCI controller"
>> 3012 depends on HW_HAS_PCI
>> 3013 select PCI_DOMAINS
>> 3014 help
>> 3015 Find out whether you have a PCI motherboard. PCI is the name of a
>> 3016 bus system, i.e. the way the CPU talks to the other stuff inside
>> 3017 your box. Other bus systems are ISA, EISA, or VESA. If you have PCI,
>> 3018 say Y, otherwise N.
>> 3019
>> 3020 config HT_PCI
>> 3021 bool "Support for HT-linked PCI"
>> 3022 default y
>> 3023 depends on CPU_LOONGSON3
>> 3024 select PCI
>> 3025 select PCI_DOMAINS
>> 3026 help
>> 3027 Loongson family machines use Hyper-Transport bus for inter-core
>> 3028 connection and device connection. The PCI bus is a subordinate
>> 3029 linked at HT. Choose Y for Loongson-3 based machines.
2146 3030
2147 config ARM64_EPAN !! 3031 config PCI_DOMAINS
2148 bool "Enable support for Enhanced Pri !! 3032 bool
2149 default y <<
2150 depends on ARM64_PAN <<
2151 help <<
2152 Enhanced Privileged Access Never (E <<
2153 Access Never to be used with Execut <<
2154 <<
2155 The feature is detected at runtime, <<
2156 if the cpu does not implement the f <<
2157 endmenu # "ARMv8.7 architectural features" <<
2158 3033
2159 menu "ARMv8.9 architectural features" !! 3034 config PCI_DOMAINS_GENERIC
>> 3035 bool
2160 3036
2161 config ARM64_POE !! 3037 config PCI_DRIVERS_GENERIC
2162 prompt "Permission Overlay Extension" !! 3038 select PCI_DOMAINS_GENERIC if PCI_DOMAINS
2163 def_bool y !! 3039 bool
2164 select ARCH_USES_HIGH_VMA_FLAGS <<
2165 select ARCH_HAS_PKEYS <<
2166 help <<
2167 The Permission Overlay Extension is <<
2168 Protection Keys. Memory Protection <<
2169 enforcing page-based protections, b <<
2170 of the page tables when an applicat <<
2171 3040
2172 For details, see Documentation/core !! 3041 config PCI_DRIVERS_LEGACY
>> 3042 def_bool !PCI_DRIVERS_GENERIC
>> 3043 select NO_GENERIC_PCI_IOPORT_MAP
2173 3044
2174 If unsure, say y. !! 3045 source "drivers/pci/Kconfig"
2175 3046
2176 config ARCH_PKEY_BITS !! 3047 #
2177 int !! 3048 # ISA support is now enabled via select. Too many systems still have the one
2178 default 3 !! 3049 # or other ISA chip on the board that users don't know about so don't expect
>> 3050 # users to choose the right thing ...
>> 3051 #
>> 3052 config ISA
>> 3053 bool
2179 3054
2180 endmenu # "ARMv8.9 architectural features" !! 3055 config EISA
>> 3056 bool "EISA support"
>> 3057 depends on HW_HAS_EISA
>> 3058 select ISA
>> 3059 select GENERIC_ISA_DMA
>> 3060 ---help---
>> 3061 The Extended Industry Standard Architecture (EISA) bus was
>> 3062 developed as an open alternative to the IBM MicroChannel bus.
>> 3063
>> 3064 The EISA bus provided some of the features of the IBM MicroChannel
>> 3065 bus while maintaining backward compatibility with cards made for
>> 3066 the older ISA bus. The EISA bus saw limited use between 1988 and
>> 3067 1995 when it was made obsolete by the PCI bus.
>> 3068
>> 3069 Say Y here if you are building a kernel for an EISA-based machine.
>> 3070
>> 3071 Otherwise, say N.
>> 3072
>> 3073 source "drivers/eisa/Kconfig"
>> 3074
>> 3075 config TC
>> 3076 bool "TURBOchannel support"
>> 3077 depends on MACH_DECSTATION
>> 3078 help
>> 3079 TURBOchannel is a DEC (now Compaq (now HP)) bus for Alpha and MIPS
>> 3080 processors. TURBOchannel programming specifications are available
>> 3081 at:
>> 3082 <ftp://ftp.hp.com/pub/alphaserver/archive/triadd/>
>> 3083 and:
>> 3084 <http://www.computer-refuge.org/classiccmp/ftp.digital.com/pub/DEC/TriAdd/>
>> 3085 Linux driver support status is documented at:
>> 3086 <http://www.linux-mips.org/wiki/DECstation>
2181 3087
2182 config ARM64_SVE !! 3088 config MMU
2183 bool "ARM Scalable Vector Extension s !! 3089 bool
2184 default y 3090 default y
2185 help <<
2186 The Scalable Vector Extension (SVE) <<
2187 execution state which complements a <<
2188 of the base architecture to support <<
2189 additional vectorisation opportunit <<
2190 <<
2191 To enable use of this extension on <<
2192 <<
2193 On CPUs that support the SVE2 exten <<
2194 those too. <<
2195 <<
2196 Note that for architectural reasons <<
2197 support when running on SVE capable <<
2198 is present in: <<
2199 3091
2200 * version 1.5 and later of the AR !! 3092 config ARCH_MMAP_RND_BITS_MIN
2201 * the AArch64 boot wrapper since !! 3093 default 12 if 64BIT
2202 ("bootwrapper: SVE: Enable SVE !! 3094 default 8
2203 <<
2204 For other firmware implementations, <<
2205 or vendor. <<
2206 <<
2207 If you need the kernel to boot on S <<
2208 firmware, you may need to say N her <<
2209 fixed. Otherwise, you may experien <<
2210 booting the kernel. If unsure and <<
2211 symptoms, you should assume that it <<
2212 3095
2213 config ARM64_SME !! 3096 config ARCH_MMAP_RND_BITS_MAX
2214 bool "ARM Scalable Matrix Extension s !! 3097 default 18 if 64BIT
2215 default y !! 3098 default 15
2216 depends on ARM64_SVE <<
2217 depends on BROKEN <<
2218 help <<
2219 The Scalable Matrix Extension (SME) <<
2220 execution state which utilises a su <<
2221 instruction set, together with the <<
2222 register state capable of holding t <<
2223 enable various matrix operations. <<
2224 3099
2225 config ARM64_PSEUDO_NMI !! 3100 config ARCH_MMAP_RND_COMPAT_BITS_MIN
2226 bool "Support for NMI-like interrupts !! 3101 default 8
2227 select ARM_GIC_V3 <<
2228 help <<
2229 Adds support for mimicking Non-Mask <<
2230 GIC interrupt priority. This suppor <<
2231 ARM GIC. <<
2232 3102
2233 This high priority configuration fo !! 3103 config ARCH_MMAP_RND_COMPAT_BITS_MAX
2234 explicitly enabled by setting the k !! 3104 default 15
2235 "irqchip.gicv3_pseudo_nmi" to 1. <<
2236 3105
2237 If unsure, say N !! 3106 config I8253
>> 3107 bool
>> 3108 select CLKSRC_I8253
>> 3109 select CLKEVT_I8253
>> 3110 select MIPS_EXTERNAL_TIMER
2238 3111
2239 if ARM64_PSEUDO_NMI !! 3112 config ZONE_DMA
2240 config ARM64_DEBUG_PRIORITY_MASKING !! 3113 bool
2241 bool "Debug interrupt priority maskin <<
2242 help <<
2243 This adds runtime checks to functio <<
2244 interrupts when using priority mask <<
2245 the validity of ICC_PMR_EL1 when ca <<
2246 3114
2247 If unsure, say N !! 3115 config ZONE_DMA32
2248 endif # ARM64_PSEUDO_NMI !! 3116 bool
2249 3117
2250 config RELOCATABLE !! 3118 source "drivers/pcmcia/Kconfig"
2251 bool "Build a relocatable kernel imag <<
2252 select ARCH_HAS_RELR <<
2253 default y <<
2254 help <<
2255 This builds the kernel as a Positio <<
2256 which retains all relocation metada <<
2257 kernel binary at runtime to a diffe <<
2258 address it was linked at. <<
2259 Since AArch64 uses the RELA relocat <<
2260 relocation pass at runtime even if <<
2261 same address it was linked at. <<
2262 3119
2263 config RANDOMIZE_BASE !! 3120 config RAPIDIO
2264 bool "Randomize the address of the ke !! 3121 tristate "RapidIO support"
2265 select RELOCATABLE !! 3122 depends on PCI
>> 3123 default n
2266 help 3124 help
2267 Randomizes the virtual address at w !! 3125 If you say Y here, the kernel will include drivers and
2268 loaded, as a security feature that !! 3126 infrastructure code to support RapidIO interconnect devices.
2269 relying on knowledge of the locatio <<
2270 <<
2271 It is the bootloader's job to provi <<
2272 random u64 value in /chosen/kaslr-s <<
2273 <<
2274 When booting via the UEFI stub, it <<
2275 EFI_RNG_PROTOCOL implementation (if <<
2276 to the kernel proper. In addition, <<
2277 location of the kernel Image as wel <<
2278 3127
2279 If unsure, say N. !! 3128 source "drivers/rapidio/Kconfig"
2280 3129
2281 config RANDOMIZE_MODULE_REGION_FULL !! 3130 endmenu
2282 bool "Randomize the module region ove <<
2283 depends on RANDOMIZE_BASE <<
2284 default y <<
2285 help <<
2286 Randomizes the location of the modu <<
2287 covering the core kernel. This way, <<
2288 to leak information about the locat <<
2289 but it does imply that function cal <<
2290 kernel will need to be resolved via <<
2291 <<
2292 When this option is not set, the mo <<
2293 a limited range that contains the [ <<
2294 core kernel, so branch relocations <<
2295 the region is exhausted. In this pa <<
2296 exhaustion, modules might be able t <<
2297 3131
2298 config CC_HAVE_STACKPROTECTOR_SYSREG !! 3132 menu "Executable file formats"
2299 def_bool $(cc-option,-mstack-protecto <<
2300 3133
2301 config STACKPROTECTOR_PER_TASK !! 3134 source "fs/Kconfig.binfmt"
2302 def_bool y <<
2303 depends on STACKPROTECTOR && CC_HAVE_ <<
2304 3135
2305 config UNWIND_PATCH_PAC_INTO_SCS !! 3136 config TRAD_SIGNALS
2306 bool "Enable shadow call stack dynami !! 3137 bool
2307 # needs Clang with https://github.com <<
2308 depends on CC_IS_CLANG && CLANG_VERSI <<
2309 depends on ARM64_PTR_AUTH_KERNEL && C <<
2310 depends on SHADOW_CALL_STACK <<
2311 select UNWIND_TABLES <<
2312 select DYNAMIC_SCS <<
2313 <<
2314 config ARM64_CONTPTE <<
2315 bool "Contiguous PTE mappings for use <<
2316 depends on TRANSPARENT_HUGEPAGE <<
2317 default y <<
2318 help <<
2319 When enabled, user mappings are con <<
2320 bit, for any mappings that meet the <<
2321 This reduces TLB pressure and impro <<
2322 <<
2323 endmenu # "Kernel Features" <<
2324 <<
2325 menu "Boot options" <<
2326 <<
2327 config ARM64_ACPI_PARKING_PROTOCOL <<
2328 bool "Enable support for the ARM64 AC <<
2329 depends on ACPI <<
2330 help <<
2331 Enable support for the ARM64 ACPI p <<
2332 the kernel will not allow booting t <<
2333 protocol even if the corresponding <<
2334 MADT table. <<
2335 <<
2336 config CMDLINE <<
2337 string "Default kernel command string <<
2338 default "" <<
2339 help <<
2340 Provide a set of default command-li <<
2341 entering them here. As a minimum, y <<
2342 root device (e.g. root=/dev/nfs). <<
2343 3138
2344 choice !! 3139 config MIPS32_COMPAT
2345 prompt "Kernel command line type" !! 3140 bool
2346 depends on CMDLINE != "" <<
2347 default CMDLINE_FROM_BOOTLOADER <<
2348 help <<
2349 Choose how the kernel will handle t <<
2350 command line string. <<
2351 <<
2352 config CMDLINE_FROM_BOOTLOADER <<
2353 bool "Use bootloader kernel arguments <<
2354 help <<
2355 Uses the command-line options passe <<
2356 the boot loader doesn't provide any <<
2357 string provided in CMDLINE will be <<
2358 <<
2359 config CMDLINE_FORCE <<
2360 bool "Always use the default kernel c <<
2361 help <<
2362 Always use the default kernel comma <<
2363 loader passes other arguments to th <<
2364 This is useful if you cannot or don <<
2365 command-line options your boot load <<
2366 3141
2367 endchoice !! 3142 config COMPAT
>> 3143 bool
2368 3144
2369 config EFI_STUB !! 3145 config SYSVIPC_COMPAT
2370 bool 3146 bool
2371 3147
2372 config EFI !! 3148 config MIPS32_O32
2373 bool "UEFI runtime support" !! 3149 bool "Kernel support for o32 binaries"
2374 depends on OF && !CPU_BIG_ENDIAN !! 3150 depends on 64BIT
2375 depends on KERNEL_MODE_NEON !! 3151 select ARCH_WANT_OLD_COMPAT_IPC
2376 select ARCH_SUPPORTS_ACPI !! 3152 select COMPAT
2377 select LIBFDT !! 3153 select MIPS32_COMPAT
2378 select UCS2_STRING !! 3154 select SYSVIPC_COMPAT if SYSVIPC
2379 select EFI_PARAMS_FROM_FDT !! 3155 help
2380 select EFI_RUNTIME_WRAPPERS !! 3156 Select this option if you want to run o32 binaries. These are pure
2381 select EFI_STUB !! 3157 32-bit binaries as used by the 32-bit Linux/MIPS port. Most of
2382 select EFI_GENERIC_STUB !! 3158 existing binaries are in this format.
2383 imply IMA_SECURE_AND_OR_TRUSTED_BOOT <<
2384 default y <<
2385 help <<
2386 This option provides support for ru <<
2387 by UEFI firmware (such as non-volat <<
2388 clock, and platform reset). A UEFI <<
2389 allow the kernel to be booted as an <<
2390 is only useful on systems that have <<
2391 3159
2392 config COMPRESSED_INSTALL !! 3160 If unsure, say Y.
2393 bool "Install compressed image by def <<
2394 help <<
2395 This makes the regular "make instal <<
2396 image we built, not the legacy unco <<
2397 3161
2398 You can check that a compressed ima !! 3162 config MIPS32_N32
2399 "make zinstall" first, and verifyin !! 3163 bool "Kernel support for n32 binaries"
2400 in your environment before making " !! 3164 depends on 64BIT
2401 you. !! 3165 select COMPAT
>> 3166 select MIPS32_COMPAT
>> 3167 select SYSVIPC_COMPAT if SYSVIPC
>> 3168 help
>> 3169 Select this option if you want to run n32 binaries. These are
>> 3170 64-bit binaries using 32-bit quantities for addressing and certain
>> 3171 data that would normally be 64-bit. They are used in special
>> 3172 cases.
2402 3173
2403 config DMI !! 3174 If unsure, say N.
2404 bool "Enable support for SMBIOS (DMI) <<
2405 depends on EFI <<
2406 default y <<
2407 help <<
2408 This enables SMBIOS/DMI feature for <<
2409 3175
2410 This option is only useful on syste !! 3176 config BINFMT_ELF32
2411 However, even with this option, the !! 3177 bool
2412 continue to boot on existing non-UE !! 3178 default y if MIPS32_O32 || MIPS32_N32
>> 3179 select ELFCORE
2413 3180
2414 endmenu # "Boot options" !! 3181 endmenu
2415 3182
2416 menu "Power management options" 3183 menu "Power management options"
2417 3184
2418 source "kernel/power/Kconfig" <<
2419 <<
2420 config ARCH_HIBERNATION_POSSIBLE 3185 config ARCH_HIBERNATION_POSSIBLE
2421 def_bool y 3186 def_bool y
2422 depends on CPU_PM !! 3187 depends on SYS_SUPPORTS_HOTPLUG_CPU || !SMP
2423 <<
2424 config ARCH_HIBERNATION_HEADER <<
2425 def_bool y <<
2426 depends on HIBERNATION <<
2427 3188
2428 config ARCH_SUSPEND_POSSIBLE 3189 config ARCH_SUSPEND_POSSIBLE
2429 def_bool y 3190 def_bool y
>> 3191 depends on SYS_SUPPORTS_HOTPLUG_CPU || !SMP
>> 3192
>> 3193 source "kernel/power/Kconfig"
2430 3194
2431 endmenu # "Power management options" !! 3195 endmenu
>> 3196
>> 3197 config MIPS_EXTERNAL_TIMER
>> 3198 bool
2432 3199
2433 menu "CPU Power Management" 3200 menu "CPU Power Management"
2434 3201
>> 3202 if CPU_SUPPORTS_CPUFREQ && MIPS_EXTERNAL_TIMER
>> 3203 source "drivers/cpufreq/Kconfig"
>> 3204 endif
>> 3205
2435 source "drivers/cpuidle/Kconfig" 3206 source "drivers/cpuidle/Kconfig"
2436 3207
2437 source "drivers/cpufreq/Kconfig" !! 3208 endmenu
>> 3209
>> 3210 source "net/Kconfig"
>> 3211
>> 3212 source "drivers/Kconfig"
>> 3213
>> 3214 source "drivers/firmware/Kconfig"
>> 3215
>> 3216 source "fs/Kconfig"
>> 3217
>> 3218 source "arch/mips/Kconfig.debug"
2438 3219
2439 endmenu # "CPU Power Management" !! 3220 source "security/Kconfig"
2440 3221
2441 source "drivers/acpi/Kconfig" !! 3222 source "crypto/Kconfig"
2442 3223
2443 source "arch/arm64/kvm/Kconfig" !! 3224 source "lib/Kconfig"
2444 3225
>> 3226 source "arch/mips/kvm/Kconfig"
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