1 # SPDX-License-Identifier: GPL-2.0-only !! 1 # SPDX-License-Identifier: GPL-2.0
2 config ARM64 !! 2 config MIPS
3 def_bool y !! 3 bool
4 select ACPI_APMT if ACPI !! 4 default y
5 select ACPI_CCA_REQUIRED if ACPI <<
6 select ACPI_GENERIC_GSI if ACPI <<
7 select ACPI_GTDT if ACPI <<
8 select ACPI_HOTPLUG_CPU if ACPI_PROCES <<
9 select ACPI_IORT if ACPI <<
10 select ACPI_REDUCED_HARDWARE_ONLY if A <<
11 select ACPI_MCFG if (ACPI && PCI) <<
12 select ACPI_SPCR_TABLE if ACPI <<
13 select ACPI_PPTT if ACPI <<
14 select ARCH_HAS_DEBUG_WX <<
15 select ARCH_BINFMT_ELF_EXTRA_PHDRS <<
16 select ARCH_BINFMT_ELF_STATE 5 select ARCH_BINFMT_ELF_STATE
17 select ARCH_CORRECT_STACKTRACE_ON_KRET !! 6 select ARCH_CLOCKSOURCE_DATA
18 select ARCH_ENABLE_HUGEPAGE_MIGRATION !! 7 select ARCH_DISCARD_MEMBLOCK
19 select ARCH_ENABLE_MEMORY_HOTPLUG !! 8 select ARCH_HAS_ELF_RANDOMIZE
20 select ARCH_ENABLE_MEMORY_HOTREMOVE <<
21 select ARCH_ENABLE_SPLIT_PMD_PTLOCK if <<
22 select ARCH_ENABLE_THP_MIGRATION if TR <<
23 select ARCH_HAS_CACHE_LINE_SIZE <<
24 select ARCH_HAS_CURRENT_STACK_POINTER <<
25 select ARCH_HAS_DEBUG_VIRTUAL <<
26 select ARCH_HAS_DEBUG_VM_PGTABLE <<
27 select ARCH_HAS_DMA_OPS if XEN <<
28 select ARCH_HAS_DMA_PREP_COHERENT <<
29 select ARCH_HAS_ACPI_TABLE_UPGRADE if <<
30 select ARCH_HAS_FAST_MULTIPLIER <<
31 select ARCH_HAS_FORTIFY_SOURCE <<
32 select ARCH_HAS_GCOV_PROFILE_ALL <<
33 select ARCH_HAS_GIGANTIC_PAGE <<
34 select ARCH_HAS_KCOV <<
35 select ARCH_HAS_KERNEL_FPU_SUPPORT if <<
36 select ARCH_HAS_KEEPINITRD <<
37 select ARCH_HAS_MEMBARRIER_SYNC_CORE <<
38 select ARCH_HAS_MEM_ENCRYPT <<
39 select ARCH_HAS_NMI_SAFE_THIS_CPU_OPS <<
40 select ARCH_HAS_NON_OVERLAPPING_ADDRES <<
41 select ARCH_HAS_PTE_DEVMAP <<
42 select ARCH_HAS_PTE_SPECIAL <<
43 select ARCH_HAS_HW_PTE_YOUNG <<
44 select ARCH_HAS_SETUP_DMA_OPS <<
45 select ARCH_HAS_SET_DIRECT_MAP <<
46 select ARCH_HAS_SET_MEMORY <<
47 select ARCH_STACKWALK <<
48 select ARCH_HAS_STRICT_KERNEL_RWX <<
49 select ARCH_HAS_STRICT_MODULE_RWX <<
50 select ARCH_HAS_SYNC_DMA_FOR_DEVICE <<
51 select ARCH_HAS_SYNC_DMA_FOR_CPU <<
52 select ARCH_HAS_SYSCALL_WRAPPER <<
53 select ARCH_HAS_TICK_BROADCAST if GENE 9 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
54 select ARCH_HAS_ZONE_DMA_SET if EXPERT !! 10 select ARCH_SUPPORTS_UPROBES
55 select ARCH_HAVE_ELF_PROT !! 11 select ARCH_USE_BUILTIN_BSWAP
56 select ARCH_HAVE_NMI_SAFE_CMPXCHG !! 12 select ARCH_USE_CMPXCHG_LOCKREF if 64BIT
57 select ARCH_HAVE_TRACE_MMIO_ACCESS <<
58 select ARCH_INLINE_READ_LOCK if !PREEM <<
59 select ARCH_INLINE_READ_LOCK_BH if !PR <<
60 select ARCH_INLINE_READ_LOCK_IRQ if !P <<
61 select ARCH_INLINE_READ_LOCK_IRQSAVE i <<
62 select ARCH_INLINE_READ_UNLOCK if !PRE <<
63 select ARCH_INLINE_READ_UNLOCK_BH if ! <<
64 select ARCH_INLINE_READ_UNLOCK_IRQ if <<
65 select ARCH_INLINE_READ_UNLOCK_IRQREST <<
66 select ARCH_INLINE_WRITE_LOCK if !PREE <<
67 select ARCH_INLINE_WRITE_LOCK_BH if !P <<
68 select ARCH_INLINE_WRITE_LOCK_IRQ if ! <<
69 select ARCH_INLINE_WRITE_LOCK_IRQSAVE <<
70 select ARCH_INLINE_WRITE_UNLOCK if !PR <<
71 select ARCH_INLINE_WRITE_UNLOCK_BH if <<
72 select ARCH_INLINE_WRITE_UNLOCK_IRQ if <<
73 select ARCH_INLINE_WRITE_UNLOCK_IRQRES <<
74 select ARCH_INLINE_SPIN_TRYLOCK if !PR <<
75 select ARCH_INLINE_SPIN_TRYLOCK_BH if <<
76 select ARCH_INLINE_SPIN_LOCK if !PREEM <<
77 select ARCH_INLINE_SPIN_LOCK_BH if !PR <<
78 select ARCH_INLINE_SPIN_LOCK_IRQ if !P <<
79 select ARCH_INLINE_SPIN_LOCK_IRQSAVE i <<
80 select ARCH_INLINE_SPIN_UNLOCK if !PRE <<
81 select ARCH_INLINE_SPIN_UNLOCK_BH if ! <<
82 select ARCH_INLINE_SPIN_UNLOCK_IRQ if <<
83 select ARCH_INLINE_SPIN_UNLOCK_IRQREST <<
84 select ARCH_KEEP_MEMBLOCK <<
85 select ARCH_MHP_MEMMAP_ON_MEMORY_ENABL <<
86 select ARCH_USE_CMPXCHG_LOCKREF <<
87 select ARCH_USE_GNU_PROPERTY <<
88 select ARCH_USE_MEMTEST <<
89 select ARCH_USE_QUEUED_RWLOCKS 13 select ARCH_USE_QUEUED_RWLOCKS
90 select ARCH_USE_QUEUED_SPINLOCKS 14 select ARCH_USE_QUEUED_SPINLOCKS
91 select ARCH_USE_SYM_ANNOTATIONS !! 15 select ARCH_WANT_IPC_PARSE_VERSION
92 select ARCH_SUPPORTS_DEBUG_PAGEALLOC !! 16 select BUILDTIME_EXTABLE_SORT
93 select ARCH_SUPPORTS_HUGETLBFS <<
94 select ARCH_SUPPORTS_MEMORY_FAILURE <<
95 select ARCH_SUPPORTS_SHADOW_CALL_STACK <<
96 select ARCH_SUPPORTS_LTO_CLANG if CPU_ <<
97 select ARCH_SUPPORTS_LTO_CLANG_THIN <<
98 select ARCH_SUPPORTS_CFI_CLANG <<
99 select ARCH_SUPPORTS_ATOMIC_RMW <<
100 select ARCH_SUPPORTS_INT128 if CC_HAS_ <<
101 select ARCH_SUPPORTS_NUMA_BALANCING <<
102 select ARCH_SUPPORTS_PAGE_TABLE_CHECK <<
103 select ARCH_SUPPORTS_PER_VMA_LOCK <<
104 select ARCH_SUPPORTS_HUGE_PFNMAP if TR <<
105 select ARCH_SUPPORTS_RT <<
106 select ARCH_WANT_BATCHED_UNMAP_TLB_FLU <<
107 select ARCH_WANT_COMPAT_IPC_PARSE_VERS <<
108 select ARCH_WANT_DEFAULT_BPF_JIT <<
109 select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_ <<
110 select ARCH_WANT_FRAME_POINTERS <<
111 select ARCH_WANT_HUGE_PMD_SHARE if ARM <<
112 select ARCH_WANT_LD_ORPHAN_WARN <<
113 select ARCH_WANTS_EXECMEM_LATE if EXEC <<
114 select ARCH_WANTS_NO_INSTR <<
115 select ARCH_WANTS_THP_SWAP if ARM64_4K <<
116 select ARCH_HAS_UBSAN <<
117 select ARM_AMBA <<
118 select ARM_ARCH_TIMER <<
119 select ARM_GIC <<
120 select AUDIT_ARCH_COMPAT_GENERIC <<
121 select ARM_GIC_V2M if PCI <<
122 select ARM_GIC_V3 <<
123 select ARM_GIC_V3_ITS if PCI <<
124 select ARM_PSCI_FW <<
125 select BUILDTIME_TABLE_SORT <<
126 select CLONE_BACKWARDS 17 select CLONE_BACKWARDS
127 select COMMON_CLK !! 18 select CPU_PM if CPU_IDLE
128 select CPU_PM if (SUSPEND || CPU_IDLE) !! 19 select GENERIC_ATOMIC64 if !64BIT
129 select CPUMASK_OFFSTACK if NR_CPUS > 2 !! 20 select GENERIC_CLOCKEVENTS
130 select CRC32 !! 21 select GENERIC_CMOS_UPDATE
131 select DCACHE_WORD_ACCESS <<
132 select DYNAMIC_FTRACE if FUNCTION_TRAC <<
133 select DMA_BOUNCE_UNALIGNED_KMALLOC <<
134 select DMA_DIRECT_REMAP <<
135 select EDAC_SUPPORT <<
136 select FRAME_POINTER <<
137 select FUNCTION_ALIGNMENT_4B <<
138 select FUNCTION_ALIGNMENT_8B if DYNAMI <<
139 select GENERIC_ALLOCATOR <<
140 select GENERIC_ARCH_TOPOLOGY <<
141 select GENERIC_CLOCKEVENTS_BROADCAST <<
142 select GENERIC_CPU_AUTOPROBE 22 select GENERIC_CPU_AUTOPROBE
143 select GENERIC_CPU_DEVICES <<
144 select GENERIC_CPU_VULNERABILITIES <<
145 select GENERIC_EARLY_IOREMAP <<
146 select GENERIC_IDLE_POLL_SETUP <<
147 select GENERIC_IOREMAP <<
148 select GENERIC_IRQ_IPI <<
149 select GENERIC_IRQ_PROBE 23 select GENERIC_IRQ_PROBE
150 select GENERIC_IRQ_SHOW 24 select GENERIC_IRQ_SHOW
151 select GENERIC_IRQ_SHOW_LEVEL !! 25 select GENERIC_LIB_ASHLDI3
152 select GENERIC_LIB_DEVMEM_IS_ALLOWED !! 26 select GENERIC_LIB_ASHRDI3
>> 27 select GENERIC_LIB_CMPDI2
>> 28 select GENERIC_LIB_LSHRDI3
>> 29 select GENERIC_LIB_UCMPDI2
153 select GENERIC_PCI_IOMAP 30 select GENERIC_PCI_IOMAP
154 select GENERIC_PTDUMP !! 31 select GENERIC_SCHED_CLOCK if !CAVIUM_OCTEON_SOC
155 select GENERIC_SCHED_CLOCK <<
156 select GENERIC_SMP_IDLE_THREAD 32 select GENERIC_SMP_IDLE_THREAD
157 select GENERIC_TIME_VSYSCALL 33 select GENERIC_TIME_VSYSCALL
158 select GENERIC_GETTIMEOFDAY !! 34 select HANDLE_DOMAIN_IRQ
159 select GENERIC_VDSO_TIME_NS <<
160 select HARDIRQS_SW_RESEND <<
161 select HAS_IOPORT <<
162 select HAVE_MOVE_PMD <<
163 select HAVE_MOVE_PUD <<
164 select HAVE_PCI <<
165 select HAVE_ACPI_APEI if (ACPI && EFI) <<
166 select HAVE_ALIGNED_STRUCT_PAGE <<
167 select HAVE_ARCH_AUDITSYSCALL <<
168 select HAVE_ARCH_BITREVERSE <<
169 select HAVE_ARCH_COMPILER_H <<
170 select HAVE_ARCH_HUGE_VMALLOC <<
171 select HAVE_ARCH_HUGE_VMAP <<
172 select HAVE_ARCH_JUMP_LABEL 35 select HAVE_ARCH_JUMP_LABEL
173 select HAVE_ARCH_JUMP_LABEL_RELATIVE <<
174 select HAVE_ARCH_KASAN <<
175 select HAVE_ARCH_KASAN_VMALLOC <<
176 select HAVE_ARCH_KASAN_SW_TAGS <<
177 select HAVE_ARCH_KASAN_HW_TAGS if ARM6 <<
178 # Some instrumentation may be unsound, <<
179 select HAVE_ARCH_KCSAN if EXPERT <<
180 select HAVE_ARCH_KFENCE <<
181 select HAVE_ARCH_KGDB 36 select HAVE_ARCH_KGDB
182 select HAVE_ARCH_MMAP_RND_BITS !! 37 select HAVE_ARCH_MMAP_RND_BITS if MMU
183 select HAVE_ARCH_MMAP_RND_COMPAT_BITS !! 38 select HAVE_ARCH_MMAP_RND_COMPAT_BITS if MMU && COMPAT
184 select HAVE_ARCH_PREL32_RELOCATIONS <<
185 select HAVE_ARCH_RANDOMIZE_KSTACK_OFFS <<
186 select HAVE_ARCH_SECCOMP_FILTER 39 select HAVE_ARCH_SECCOMP_FILTER
187 select HAVE_ARCH_STACKLEAK <<
188 select HAVE_ARCH_THREAD_STRUCT_WHITELI <<
189 select HAVE_ARCH_TRACEHOOK 40 select HAVE_ARCH_TRACEHOOK
190 select HAVE_ARCH_TRANSPARENT_HUGEPAGE !! 41 select HAVE_ARCH_TRANSPARENT_HUGEPAGE if CPU_SUPPORTS_HUGEPAGES && 64BIT
191 select HAVE_ARCH_VMAP_STACK !! 42 select HAVE_CBPF_JIT if (!64BIT && !CPU_MICROMIPS)
192 select HAVE_ARM_SMCCC !! 43 select HAVE_EBPF_JIT if (64BIT && !CPU_MICROMIPS)
193 select HAVE_ASM_MODVERSIONS !! 44 select HAVE_CONTEXT_TRACKING
194 select HAVE_EBPF_JIT !! 45 select HAVE_COPY_THREAD_TLS
195 select HAVE_C_RECORDMCOUNT 46 select HAVE_C_RECORDMCOUNT
196 select HAVE_CMPXCHG_DOUBLE <<
197 select HAVE_CMPXCHG_LOCAL <<
198 select HAVE_CONTEXT_TRACKING_USER <<
199 select HAVE_DEBUG_KMEMLEAK 47 select HAVE_DEBUG_KMEMLEAK
>> 48 select HAVE_DEBUG_STACKOVERFLOW
200 select HAVE_DMA_CONTIGUOUS 49 select HAVE_DMA_CONTIGUOUS
201 select HAVE_DYNAMIC_FTRACE 50 select HAVE_DYNAMIC_FTRACE
202 select HAVE_DYNAMIC_FTRACE_WITH_ARGS \ !! 51 select HAVE_EXIT_THREAD
203 if (GCC_SUPPORTS_DYNAMIC_FTRAC <<
204 CLANG_SUPPORTS_DYNAMIC_FTR <<
205 select HAVE_DYNAMIC_FTRACE_WITH_DIRECT <<
206 if DYNAMIC_FTRACE_WITH_ARGS && <<
207 select HAVE_DYNAMIC_FTRACE_WITH_CALL_O <<
208 if (DYNAMIC_FTRACE_WITH_ARGS & <<
209 (CC_IS_CLANG || !CC_OPTIMI <<
210 select FTRACE_MCOUNT_USE_PATCHABLE_FUN <<
211 if DYNAMIC_FTRACE_WITH_ARGS <<
212 select HAVE_SAMPLE_FTRACE_DIRECT <<
213 select HAVE_SAMPLE_FTRACE_DIRECT_MULTI <<
214 select HAVE_EFFICIENT_UNALIGNED_ACCESS <<
215 select HAVE_GUP_FAST <<
216 select HAVE_FTRACE_MCOUNT_RECORD 52 select HAVE_FTRACE_MCOUNT_RECORD
217 select HAVE_FUNCTION_TRACER <<
218 select HAVE_FUNCTION_ERROR_INJECTION <<
219 select HAVE_FUNCTION_GRAPH_TRACER 53 select HAVE_FUNCTION_GRAPH_TRACER
220 select HAVE_FUNCTION_GRAPH_RETVAL !! 54 select HAVE_FUNCTION_TRACER
221 select HAVE_GCC_PLUGINS !! 55 select HAVE_GENERIC_DMA_COHERENT
222 select HAVE_HARDLOCKUP_DETECTOR_PERF i !! 56 select HAVE_IDE
223 HW_PERF_EVENTS && HAVE_PERF_EV !! 57 select HAVE_IRQ_EXIT_ON_IRQ_STACK
224 select HAVE_HW_BREAKPOINT if PERF_EVEN <<
225 select HAVE_IOREMAP_PROT <<
226 select HAVE_IRQ_TIME_ACCOUNTING 58 select HAVE_IRQ_TIME_ACCOUNTING
>> 59 select HAVE_KPROBES
>> 60 select HAVE_KRETPROBES
>> 61 select HAVE_MEMBLOCK
>> 62 select HAVE_MEMBLOCK_NODE_MAP
227 select HAVE_MOD_ARCH_SPECIFIC 63 select HAVE_MOD_ARCH_SPECIFIC
228 select HAVE_NMI 64 select HAVE_NMI
>> 65 select HAVE_OPROFILE
229 select HAVE_PERF_EVENTS 66 select HAVE_PERF_EVENTS
230 select HAVE_PERF_EVENTS_NMI if ARM64_P <<
231 select HAVE_PERF_REGS <<
232 select HAVE_PERF_USER_STACK_DUMP <<
233 select HAVE_PREEMPT_DYNAMIC_KEY <<
234 select HAVE_REGS_AND_STACK_ACCESS_API 67 select HAVE_REGS_AND_STACK_ACCESS_API
235 select HAVE_POSIX_CPU_TIMERS_TASK_WORK <<
236 select HAVE_FUNCTION_ARG_ACCESS_API <<
237 select MMU_GATHER_RCU_TABLE_FREE <<
238 select HAVE_RSEQ 68 select HAVE_RSEQ
239 select HAVE_RUST if RUSTC_SUPPORTS_ARM <<
240 select HAVE_STACKPROTECTOR 69 select HAVE_STACKPROTECTOR
241 select HAVE_SYSCALL_TRACEPOINTS 70 select HAVE_SYSCALL_TRACEPOINTS
242 select HAVE_KPROBES !! 71 select HAVE_VIRT_CPU_ACCOUNTING_GEN if 64BIT || !SMP
243 select HAVE_KRETPROBES <<
244 select HAVE_GENERIC_VDSO <<
245 select HOTPLUG_CORE_SYNC_DEAD if HOTPL <<
246 select IRQ_DOMAIN <<
247 select IRQ_FORCED_THREADING 72 select IRQ_FORCED_THREADING
248 select KASAN_VMALLOC if KASAN !! 73 select MODULES_USE_ELF_RELA if MODULES && 64BIT
249 select LOCK_MM_AND_FIND_VMA !! 74 select MODULES_USE_ELF_REL if MODULES
250 select MODULES_USE_ELF_RELA !! 75 select PERF_USE_VMALLOC
251 select NEED_DMA_MAP_STATE !! 76 select RTC_LIB if !MACH_LOONGSON64
252 select NEED_SG_DMA_LENGTH <<
253 select OF <<
254 select OF_EARLY_FLATTREE <<
255 select PCI_DOMAINS_GENERIC if PCI <<
256 select PCI_ECAM if (ACPI && PCI) <<
257 select PCI_SYSCALL if PCI <<
258 select POWER_RESET <<
259 select POWER_SUPPLY <<
260 select SPARSE_IRQ <<
261 select SWIOTLB <<
262 select SYSCTL_EXCEPTION_TRACE 77 select SYSCTL_EXCEPTION_TRACE
263 select THREAD_INFO_IN_TASK !! 78 select VIRT_TO_BUS
264 select HAVE_ARCH_USERFAULTFD_MINOR if <<
265 select HAVE_ARCH_USERFAULTFD_WP if USE <<
266 select TRACE_IRQFLAGS_SUPPORT <<
267 select TRACE_IRQFLAGS_NMI_SUPPORT <<
268 select HAVE_SOFTIRQ_ON_OWN_STACK <<
269 select USER_STACKTRACE_SUPPORT <<
270 select VDSO_GETRANDOM <<
271 help <<
272 ARM 64-bit (AArch64) Linux support. <<
273 79
274 config RUSTC_SUPPORTS_ARM64 !! 80 menu "Machine selection"
275 def_bool y <<
276 depends on CPU_LITTLE_ENDIAN <<
277 # Shadow call stack is only supported <<
278 # <<
279 # When using the UNWIND_PATCH_PAC_INTO <<
280 # required due to use of the -Zfixed-x <<
281 # <<
282 # Otherwise, rustc version 1.82+ is re <<
283 # -Zsanitizer=shadow-call-stack flag. <<
284 depends on !SHADOW_CALL_STACK || RUSTC <<
285 <<
286 config CLANG_SUPPORTS_DYNAMIC_FTRACE_WITH_ARGS <<
287 def_bool CC_IS_CLANG <<
288 # https://github.com/ClangBuiltLinux/l <<
289 depends on AS_IS_GNU || (AS_IS_LLVM && <<
290 <<
291 config GCC_SUPPORTS_DYNAMIC_FTRACE_WITH_ARGS <<
292 def_bool CC_IS_GCC <<
293 depends on $(cc-option,-fpatchable-fun <<
294 81
295 config 64BIT !! 82 choice
296 def_bool y !! 83 prompt "System type"
297 !! 84 default MIPS_GENERIC
298 config MMU <<
299 def_bool y <<
300 <<
301 config ARM64_CONT_PTE_SHIFT <<
302 int <<
303 default 5 if PAGE_SIZE_64KB <<
304 default 7 if PAGE_SIZE_16KB <<
305 default 4 <<
306 <<
307 config ARM64_CONT_PMD_SHIFT <<
308 int <<
309 default 5 if PAGE_SIZE_64KB <<
310 default 5 if PAGE_SIZE_16KB <<
311 default 4 <<
312 85
313 config ARCH_MMAP_RND_BITS_MIN !! 86 config MIPS_GENERIC
314 default 14 if PAGE_SIZE_64KB !! 87 bool "Generic board-agnostic MIPS kernel"
315 default 16 if PAGE_SIZE_16KB !! 88 select BOOT_RAW
316 default 18 !! 89 select BUILTIN_DTB
>> 90 select CEVT_R4K
>> 91 select CLKSRC_MIPS_GIC
>> 92 select COMMON_CLK
>> 93 select CPU_MIPSR2_IRQ_VI
>> 94 select CPU_MIPSR2_IRQ_EI
>> 95 select CSRC_R4K
>> 96 select DMA_PERDEV_COHERENT
>> 97 select HW_HAS_PCI
>> 98 select IRQ_MIPS_CPU
>> 99 select LIBFDT
>> 100 select MIPS_CPU_SCACHE
>> 101 select MIPS_GIC
>> 102 select MIPS_L1_CACHE_SHIFT_7
>> 103 select NO_EXCEPT_FILL
>> 104 select PCI_DRIVERS_GENERIC
>> 105 select PINCTRL
>> 106 select SMP_UP if SMP
>> 107 select SWAP_IO_SPACE
>> 108 select SYS_HAS_CPU_MIPS32_R1
>> 109 select SYS_HAS_CPU_MIPS32_R2
>> 110 select SYS_HAS_CPU_MIPS32_R6
>> 111 select SYS_HAS_CPU_MIPS64_R1
>> 112 select SYS_HAS_CPU_MIPS64_R2
>> 113 select SYS_HAS_CPU_MIPS64_R6
>> 114 select SYS_SUPPORTS_32BIT_KERNEL
>> 115 select SYS_SUPPORTS_64BIT_KERNEL
>> 116 select SYS_SUPPORTS_BIG_ENDIAN
>> 117 select SYS_SUPPORTS_HIGHMEM
>> 118 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 119 select SYS_SUPPORTS_MICROMIPS
>> 120 select SYS_SUPPORTS_MIPS_CPS
>> 121 select SYS_SUPPORTS_MIPS16
>> 122 select SYS_SUPPORTS_MULTITHREADING
>> 123 select SYS_SUPPORTS_RELOCATABLE
>> 124 select SYS_SUPPORTS_SMARTMIPS
>> 125 select USB_EHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
>> 126 select USB_EHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 127 select USB_OHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
>> 128 select USB_OHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 129 select USB_UHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
>> 130 select USB_UHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 131 select USE_OF
>> 132 help
>> 133 Select this to build a kernel which aims to support multiple boards,
>> 134 generally using a flattened device tree passed from the bootloader
>> 135 using the boot protocol defined in the UHI (Unified Hosting
>> 136 Interface) specification.
>> 137
>> 138 config MIPS_ALCHEMY
>> 139 bool "Alchemy processor based machines"
>> 140 select PHYS_ADDR_T_64BIT
>> 141 select CEVT_R4K
>> 142 select CSRC_R4K
>> 143 select IRQ_MIPS_CPU
>> 144 select DMA_MAYBE_COHERENT # Au1000,1500,1100 aren't, rest is
>> 145 select SYS_HAS_CPU_MIPS32_R1
>> 146 select SYS_SUPPORTS_32BIT_KERNEL
>> 147 select SYS_SUPPORTS_APM_EMULATION
>> 148 select GPIOLIB
>> 149 select SYS_SUPPORTS_ZBOOT
>> 150 select COMMON_CLK
317 151
318 # max bits determined by the following formula !! 152 config AR7
319 # VA_BITS - PAGE_SHIFT - 3 !! 153 bool "Texas Instruments AR7"
320 config ARCH_MMAP_RND_BITS_MAX !! 154 select BOOT_ELF32
321 default 19 if ARM64_VA_BITS=36 !! 155 select DMA_NONCOHERENT
322 default 24 if ARM64_VA_BITS=39 !! 156 select CEVT_R4K
323 default 27 if ARM64_VA_BITS=42 !! 157 select CSRC_R4K
324 default 30 if ARM64_VA_BITS=47 !! 158 select IRQ_MIPS_CPU
325 default 29 if ARM64_VA_BITS=48 && ARM6 !! 159 select NO_EXCEPT_FILL
326 default 31 if ARM64_VA_BITS=48 && ARM6 !! 160 select SWAP_IO_SPACE
327 default 33 if ARM64_VA_BITS=48 !! 161 select SYS_HAS_CPU_MIPS32_R1
328 default 14 if ARM64_64K_PAGES !! 162 select SYS_HAS_EARLY_PRINTK
329 default 16 if ARM64_16K_PAGES !! 163 select SYS_SUPPORTS_32BIT_KERNEL
330 default 18 !! 164 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 165 select SYS_SUPPORTS_MIPS16
>> 166 select SYS_SUPPORTS_ZBOOT_UART16550
>> 167 select GPIOLIB
>> 168 select VLYNQ
>> 169 select HAVE_CLK
>> 170 help
>> 171 Support for the Texas Instruments AR7 System-on-a-Chip
>> 172 family: TNETD7100, 7200 and 7300.
>> 173
>> 174 config ATH25
>> 175 bool "Atheros AR231x/AR531x SoC support"
>> 176 select CEVT_R4K
>> 177 select CSRC_R4K
>> 178 select DMA_NONCOHERENT
>> 179 select IRQ_MIPS_CPU
>> 180 select IRQ_DOMAIN
>> 181 select SYS_HAS_CPU_MIPS32_R1
>> 182 select SYS_SUPPORTS_BIG_ENDIAN
>> 183 select SYS_SUPPORTS_32BIT_KERNEL
>> 184 select SYS_HAS_EARLY_PRINTK
>> 185 help
>> 186 Support for Atheros AR231x and Atheros AR531x based boards
>> 187
>> 188 config ATH79
>> 189 bool "Atheros AR71XX/AR724X/AR913X based boards"
>> 190 select ARCH_HAS_RESET_CONTROLLER
>> 191 select BOOT_RAW
>> 192 select CEVT_R4K
>> 193 select CSRC_R4K
>> 194 select DMA_NONCOHERENT
>> 195 select GPIOLIB
>> 196 select HAVE_CLK
>> 197 select COMMON_CLK
>> 198 select CLKDEV_LOOKUP
>> 199 select IRQ_MIPS_CPU
>> 200 select MIPS_MACHINE
>> 201 select SYS_HAS_CPU_MIPS32_R2
>> 202 select SYS_HAS_EARLY_PRINTK
>> 203 select SYS_SUPPORTS_32BIT_KERNEL
>> 204 select SYS_SUPPORTS_BIG_ENDIAN
>> 205 select SYS_SUPPORTS_MIPS16
>> 206 select SYS_SUPPORTS_ZBOOT_UART_PROM
>> 207 select USE_OF
>> 208 select USB_EHCI_ROOT_HUB_TT if USB_EHCI_HCD_PLATFORM
>> 209 help
>> 210 Support for the Atheros AR71XX/AR724X/AR913X SoCs.
>> 211
>> 212 config BMIPS_GENERIC
>> 213 bool "Broadcom Generic BMIPS kernel"
>> 214 select BOOT_RAW
>> 215 select NO_EXCEPT_FILL
>> 216 select USE_OF
>> 217 select CEVT_R4K
>> 218 select CSRC_R4K
>> 219 select SYNC_R4K
>> 220 select COMMON_CLK
>> 221 select BCM6345_L1_IRQ
>> 222 select BCM7038_L1_IRQ
>> 223 select BCM7120_L2_IRQ
>> 224 select BRCMSTB_L2_IRQ
>> 225 select IRQ_MIPS_CPU
>> 226 select DMA_NONCOHERENT
>> 227 select SYS_SUPPORTS_32BIT_KERNEL
>> 228 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 229 select SYS_SUPPORTS_BIG_ENDIAN
>> 230 select SYS_SUPPORTS_HIGHMEM
>> 231 select SYS_HAS_CPU_BMIPS32_3300
>> 232 select SYS_HAS_CPU_BMIPS4350
>> 233 select SYS_HAS_CPU_BMIPS4380
>> 234 select SYS_HAS_CPU_BMIPS5000
>> 235 select SWAP_IO_SPACE
>> 236 select USB_EHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
>> 237 select USB_EHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 238 select USB_OHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
>> 239 select USB_OHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 240 select HARDIRQS_SW_RESEND
>> 241 help
>> 242 Build a generic DT-based kernel image that boots on select
>> 243 BCM33xx cable modem chips, BCM63xx DSL chips, and BCM7xxx set-top
>> 244 box chips. Note that CONFIG_CPU_BIG_ENDIAN/CONFIG_CPU_LITTLE_ENDIAN
>> 245 must be set appropriately for your board.
>> 246
>> 247 config BCM47XX
>> 248 bool "Broadcom BCM47XX based boards"
>> 249 select BOOT_RAW
>> 250 select CEVT_R4K
>> 251 select CSRC_R4K
>> 252 select DMA_NONCOHERENT
>> 253 select HW_HAS_PCI
>> 254 select IRQ_MIPS_CPU
>> 255 select SYS_HAS_CPU_MIPS32_R1
>> 256 select NO_EXCEPT_FILL
>> 257 select SYS_SUPPORTS_32BIT_KERNEL
>> 258 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 259 select SYS_SUPPORTS_MIPS16
>> 260 select SYS_SUPPORTS_ZBOOT
>> 261 select SYS_HAS_EARLY_PRINTK
>> 262 select USE_GENERIC_EARLY_PRINTK_8250
>> 263 select GPIOLIB
>> 264 select LEDS_GPIO_REGISTER
>> 265 select BCM47XX_NVRAM
>> 266 select BCM47XX_SPROM
>> 267 select BCM47XX_SSB if !BCM47XX_BCMA
>> 268 help
>> 269 Support for BCM47XX based boards
>> 270
>> 271 config BCM63XX
>> 272 bool "Broadcom BCM63XX based boards"
>> 273 select BOOT_RAW
>> 274 select CEVT_R4K
>> 275 select CSRC_R4K
>> 276 select SYNC_R4K
>> 277 select DMA_NONCOHERENT
>> 278 select IRQ_MIPS_CPU
>> 279 select SYS_SUPPORTS_32BIT_KERNEL
>> 280 select SYS_SUPPORTS_BIG_ENDIAN
>> 281 select SYS_HAS_EARLY_PRINTK
>> 282 select SWAP_IO_SPACE
>> 283 select GPIOLIB
>> 284 select HAVE_CLK
>> 285 select MIPS_L1_CACHE_SHIFT_4
>> 286 select CLKDEV_LOOKUP
>> 287 help
>> 288 Support for BCM63XX based boards
>> 289
>> 290 config MIPS_COBALT
>> 291 bool "Cobalt Server"
>> 292 select CEVT_R4K
>> 293 select CSRC_R4K
>> 294 select CEVT_GT641XX
>> 295 select DMA_NONCOHERENT
>> 296 select HW_HAS_PCI
>> 297 select I8253
>> 298 select I8259
>> 299 select IRQ_MIPS_CPU
>> 300 select IRQ_GT641XX
>> 301 select PCI_GT64XXX_PCI0
>> 302 select PCI
>> 303 select SYS_HAS_CPU_NEVADA
>> 304 select SYS_HAS_EARLY_PRINTK
>> 305 select SYS_SUPPORTS_32BIT_KERNEL
>> 306 select SYS_SUPPORTS_64BIT_KERNEL
>> 307 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 308 select USE_GENERIC_EARLY_PRINTK_8250
>> 309
>> 310 config MACH_DECSTATION
>> 311 bool "DECstations"
>> 312 select BOOT_ELF32
>> 313 select CEVT_DS1287
>> 314 select CEVT_R4K if CPU_R4X00
>> 315 select CSRC_IOASIC
>> 316 select CSRC_R4K if CPU_R4X00
>> 317 select CPU_DADDI_WORKAROUNDS if 64BIT
>> 318 select CPU_R4000_WORKAROUNDS if 64BIT
>> 319 select CPU_R4400_WORKAROUNDS if 64BIT
>> 320 select DMA_NONCOHERENT
>> 321 select NO_IOPORT_MAP
>> 322 select IRQ_MIPS_CPU
>> 323 select SYS_HAS_CPU_R3000
>> 324 select SYS_HAS_CPU_R4X00
>> 325 select SYS_SUPPORTS_32BIT_KERNEL
>> 326 select SYS_SUPPORTS_64BIT_KERNEL
>> 327 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 328 select SYS_SUPPORTS_128HZ
>> 329 select SYS_SUPPORTS_256HZ
>> 330 select SYS_SUPPORTS_1024HZ
>> 331 select MIPS_L1_CACHE_SHIFT_4
>> 332 help
>> 333 This enables support for DEC's MIPS based workstations. For details
>> 334 see the Linux/MIPS FAQ on <http://www.linux-mips.org/> and the
>> 335 DECstation porting pages on <http://decstation.unix-ag.org/>.
>> 336
>> 337 If you have one of the following DECstation Models you definitely
>> 338 want to choose R4xx0 for the CPU Type:
>> 339
>> 340 DECstation 5000/50
>> 341 DECstation 5000/150
>> 342 DECstation 5000/260
>> 343 DECsystem 5900/260
>> 344
>> 345 otherwise choose R3000.
>> 346
>> 347 config MACH_JAZZ
>> 348 bool "Jazz family of machines"
>> 349 select ARCH_MIGHT_HAVE_PC_PARPORT
>> 350 select ARCH_MIGHT_HAVE_PC_SERIO
>> 351 select FW_ARC
>> 352 select FW_ARC32
>> 353 select ARCH_MAY_HAVE_PC_FDC
>> 354 select CEVT_R4K
>> 355 select CSRC_R4K
>> 356 select DEFAULT_SGI_PARTITION if CPU_BIG_ENDIAN
>> 357 select GENERIC_ISA_DMA
>> 358 select HAVE_PCSPKR_PLATFORM
>> 359 select IRQ_MIPS_CPU
>> 360 select I8253
>> 361 select I8259
>> 362 select ISA
>> 363 select SYS_HAS_CPU_R4X00
>> 364 select SYS_SUPPORTS_32BIT_KERNEL
>> 365 select SYS_SUPPORTS_64BIT_KERNEL
>> 366 select SYS_SUPPORTS_100HZ
>> 367 help
>> 368 This a family of machines based on the MIPS R4030 chipset which was
>> 369 used by several vendors to build RISC/os and Windows NT workstations.
>> 370 Members include the Acer PICA, MIPS Magnum 4000, MIPS Millennium and
>> 371 Olivetti M700-10 workstations.
>> 372
>> 373 config MACH_INGENIC
>> 374 bool "Ingenic SoC based machines"
>> 375 select SYS_SUPPORTS_32BIT_KERNEL
>> 376 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 377 select SYS_SUPPORTS_ZBOOT_UART16550
>> 378 select DMA_NONCOHERENT
>> 379 select IRQ_MIPS_CPU
>> 380 select PINCTRL
>> 381 select GPIOLIB
>> 382 select COMMON_CLK
>> 383 select GENERIC_IRQ_CHIP
>> 384 select BUILTIN_DTB
>> 385 select USE_OF
>> 386 select LIBFDT
331 387
332 config ARCH_MMAP_RND_COMPAT_BITS_MIN !! 388 config LANTIQ
333 default 7 if ARM64_64K_PAGES !! 389 bool "Lantiq based platforms"
334 default 9 if ARM64_16K_PAGES !! 390 select DMA_NONCOHERENT
335 default 11 !! 391 select IRQ_MIPS_CPU
>> 392 select CEVT_R4K
>> 393 select CSRC_R4K
>> 394 select SYS_HAS_CPU_MIPS32_R1
>> 395 select SYS_HAS_CPU_MIPS32_R2
>> 396 select SYS_SUPPORTS_BIG_ENDIAN
>> 397 select SYS_SUPPORTS_32BIT_KERNEL
>> 398 select SYS_SUPPORTS_MIPS16
>> 399 select SYS_SUPPORTS_MULTITHREADING
>> 400 select SYS_SUPPORTS_VPE_LOADER
>> 401 select SYS_HAS_EARLY_PRINTK
>> 402 select GPIOLIB
>> 403 select SWAP_IO_SPACE
>> 404 select BOOT_RAW
>> 405 select CLKDEV_LOOKUP
>> 406 select USE_OF
>> 407 select PINCTRL
>> 408 select PINCTRL_LANTIQ
>> 409 select ARCH_HAS_RESET_CONTROLLER
>> 410 select RESET_CONTROLLER
>> 411
>> 412 config LASAT
>> 413 bool "LASAT Networks platforms"
>> 414 select CEVT_R4K
>> 415 select CRC32
>> 416 select CSRC_R4K
>> 417 select DMA_NONCOHERENT
>> 418 select SYS_HAS_EARLY_PRINTK
>> 419 select HW_HAS_PCI
>> 420 select IRQ_MIPS_CPU
>> 421 select PCI_GT64XXX_PCI0
>> 422 select MIPS_NILE4
>> 423 select R5000_CPU_SCACHE
>> 424 select SYS_HAS_CPU_R5000
>> 425 select SYS_SUPPORTS_32BIT_KERNEL
>> 426 select SYS_SUPPORTS_64BIT_KERNEL if BROKEN
>> 427 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 428
>> 429 config MACH_LOONGSON32
>> 430 bool "Loongson-1 family of machines"
>> 431 select SYS_SUPPORTS_ZBOOT
>> 432 help
>> 433 This enables support for the Loongson-1 family of machines.
>> 434
>> 435 Loongson-1 is a family of 32-bit MIPS-compatible SoCs developed by
>> 436 the Institute of Computing Technology (ICT), Chinese Academy of
>> 437 Sciences (CAS).
>> 438
>> 439 config MACH_LOONGSON64
>> 440 bool "Loongson-2/3 family of machines"
>> 441 select ARCH_HAS_PHYS_TO_DMA
>> 442 select SYS_SUPPORTS_ZBOOT
>> 443 help
>> 444 This enables the support of Loongson-2/3 family of machines.
>> 445
>> 446 Loongson-2 is a family of single-core CPUs and Loongson-3 is a
>> 447 family of multi-core CPUs. They are both 64-bit general-purpose
>> 448 MIPS-compatible CPUs. Loongson-2/3 are developed by the Institute
>> 449 of Computing Technology (ICT), Chinese Academy of Sciences (CAS)
>> 450 in the People's Republic of China. The chief architect is Professor
>> 451 Weiwu Hu.
>> 452
>> 453 config MACH_PISTACHIO
>> 454 bool "IMG Pistachio SoC based boards"
>> 455 select BOOT_ELF32
>> 456 select BOOT_RAW
>> 457 select CEVT_R4K
>> 458 select CLKSRC_MIPS_GIC
>> 459 select COMMON_CLK
>> 460 select CSRC_R4K
>> 461 select DMA_NONCOHERENT
>> 462 select GPIOLIB
>> 463 select IRQ_MIPS_CPU
>> 464 select LIBFDT
>> 465 select MFD_SYSCON
>> 466 select MIPS_CPU_SCACHE
>> 467 select MIPS_GIC
>> 468 select PINCTRL
>> 469 select REGULATOR
>> 470 select SYS_HAS_CPU_MIPS32_R2
>> 471 select SYS_SUPPORTS_32BIT_KERNEL
>> 472 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 473 select SYS_SUPPORTS_MIPS_CPS
>> 474 select SYS_SUPPORTS_MULTITHREADING
>> 475 select SYS_SUPPORTS_RELOCATABLE
>> 476 select SYS_SUPPORTS_ZBOOT
>> 477 select SYS_HAS_EARLY_PRINTK
>> 478 select USE_GENERIC_EARLY_PRINTK_8250
>> 479 select USE_OF
>> 480 help
>> 481 This enables support for the IMG Pistachio SoC platform.
>> 482
>> 483 config MIPS_MALTA
>> 484 bool "MIPS Malta board"
>> 485 select ARCH_MAY_HAVE_PC_FDC
>> 486 select ARCH_MIGHT_HAVE_PC_PARPORT
>> 487 select ARCH_MIGHT_HAVE_PC_SERIO
>> 488 select BOOT_ELF32
>> 489 select BOOT_RAW
>> 490 select BUILTIN_DTB
>> 491 select CEVT_R4K
>> 492 select CSRC_R4K
>> 493 select CLKSRC_MIPS_GIC
>> 494 select COMMON_CLK
>> 495 select DMA_MAYBE_COHERENT
>> 496 select GENERIC_ISA_DMA
>> 497 select HAVE_PCSPKR_PLATFORM
>> 498 select IRQ_MIPS_CPU
>> 499 select MIPS_GIC
>> 500 select HW_HAS_PCI
>> 501 select I8253
>> 502 select I8259
>> 503 select MIPS_BONITO64
>> 504 select MIPS_CPU_SCACHE
>> 505 select MIPS_L1_CACHE_SHIFT_6
>> 506 select PCI_GT64XXX_PCI0
>> 507 select MIPS_MSC
>> 508 select SMP_UP if SMP
>> 509 select SWAP_IO_SPACE
>> 510 select SYS_HAS_CPU_MIPS32_R1
>> 511 select SYS_HAS_CPU_MIPS32_R2
>> 512 select SYS_HAS_CPU_MIPS32_R3_5
>> 513 select SYS_HAS_CPU_MIPS32_R5
>> 514 select SYS_HAS_CPU_MIPS32_R6
>> 515 select SYS_HAS_CPU_MIPS64_R1
>> 516 select SYS_HAS_CPU_MIPS64_R2
>> 517 select SYS_HAS_CPU_MIPS64_R6
>> 518 select SYS_HAS_CPU_NEVADA
>> 519 select SYS_HAS_CPU_RM7000
>> 520 select SYS_SUPPORTS_32BIT_KERNEL
>> 521 select SYS_SUPPORTS_64BIT_KERNEL
>> 522 select SYS_SUPPORTS_BIG_ENDIAN
>> 523 select SYS_SUPPORTS_HIGHMEM
>> 524 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 525 select SYS_SUPPORTS_MICROMIPS
>> 526 select SYS_SUPPORTS_MIPS_CMP
>> 527 select SYS_SUPPORTS_MIPS_CPS
>> 528 select SYS_SUPPORTS_MIPS16
>> 529 select SYS_SUPPORTS_MULTITHREADING
>> 530 select SYS_SUPPORTS_SMARTMIPS
>> 531 select SYS_SUPPORTS_VPE_LOADER
>> 532 select SYS_SUPPORTS_ZBOOT
>> 533 select SYS_SUPPORTS_RELOCATABLE
>> 534 select USE_OF
>> 535 select LIBFDT
>> 536 select ZONE_DMA32 if 64BIT
>> 537 select BUILTIN_DTB
>> 538 select LIBFDT
>> 539 help
>> 540 This enables support for the MIPS Technologies Malta evaluation
>> 541 board.
336 542
337 config ARCH_MMAP_RND_COMPAT_BITS_MAX !! 543 config MACH_PIC32
338 default 16 !! 544 bool "Microchip PIC32 Family"
>> 545 help
>> 546 This enables support for the Microchip PIC32 family of platforms.
339 547
340 config NO_IOPORT_MAP !! 548 Microchip PIC32 is a family of general-purpose 32 bit MIPS core
341 def_bool y if !PCI !! 549 microcontrollers.
>> 550
>> 551 config NEC_MARKEINS
>> 552 bool "NEC EMMA2RH Mark-eins board"
>> 553 select SOC_EMMA2RH
>> 554 select HW_HAS_PCI
>> 555 help
>> 556 This enables support for the NEC Electronics Mark-eins boards.
>> 557
>> 558 config MACH_VR41XX
>> 559 bool "NEC VR4100 series based machines"
>> 560 select CEVT_R4K
>> 561 select CSRC_R4K
>> 562 select SYS_HAS_CPU_VR41XX
>> 563 select SYS_SUPPORTS_MIPS16
>> 564 select GPIOLIB
>> 565
>> 566 config NXP_STB220
>> 567 bool "NXP STB220 board"
>> 568 select SOC_PNX833X
>> 569 help
>> 570 Support for NXP Semiconductors STB220 Development Board.
>> 571
>> 572 config NXP_STB225
>> 573 bool "NXP 225 board"
>> 574 select SOC_PNX833X
>> 575 select SOC_PNX8335
>> 576 help
>> 577 Support for NXP Semiconductors STB225 Development Board.
>> 578
>> 579 config PMC_MSP
>> 580 bool "PMC-Sierra MSP chipsets"
>> 581 select CEVT_R4K
>> 582 select CSRC_R4K
>> 583 select DMA_NONCOHERENT
>> 584 select SWAP_IO_SPACE
>> 585 select NO_EXCEPT_FILL
>> 586 select BOOT_RAW
>> 587 select SYS_HAS_CPU_MIPS32_R1
>> 588 select SYS_HAS_CPU_MIPS32_R2
>> 589 select SYS_SUPPORTS_32BIT_KERNEL
>> 590 select SYS_SUPPORTS_BIG_ENDIAN
>> 591 select SYS_SUPPORTS_MIPS16
>> 592 select IRQ_MIPS_CPU
>> 593 select SERIAL_8250
>> 594 select SERIAL_8250_CONSOLE
>> 595 select USB_EHCI_BIG_ENDIAN_MMIO
>> 596 select USB_EHCI_BIG_ENDIAN_DESC
>> 597 help
>> 598 This adds support for the PMC-Sierra family of Multi-Service
>> 599 Processor System-On-A-Chips. These parts include a number
>> 600 of integrated peripherals, interfaces and DSPs in addition to
>> 601 a variety of MIPS cores.
>> 602
>> 603 config RALINK
>> 604 bool "Ralink based machines"
>> 605 select CEVT_R4K
>> 606 select CSRC_R4K
>> 607 select BOOT_RAW
>> 608 select DMA_NONCOHERENT
>> 609 select IRQ_MIPS_CPU
>> 610 select USE_OF
>> 611 select SYS_HAS_CPU_MIPS32_R1
>> 612 select SYS_HAS_CPU_MIPS32_R2
>> 613 select SYS_SUPPORTS_32BIT_KERNEL
>> 614 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 615 select SYS_SUPPORTS_MIPS16
>> 616 select SYS_HAS_EARLY_PRINTK
>> 617 select CLKDEV_LOOKUP
>> 618 select ARCH_HAS_RESET_CONTROLLER
>> 619 select RESET_CONTROLLER
>> 620
>> 621 config SGI_IP22
>> 622 bool "SGI IP22 (Indy/Indigo2)"
>> 623 select FW_ARC
>> 624 select FW_ARC32
>> 625 select ARCH_MIGHT_HAVE_PC_SERIO
>> 626 select BOOT_ELF32
>> 627 select CEVT_R4K
>> 628 select CSRC_R4K
>> 629 select DEFAULT_SGI_PARTITION
>> 630 select DMA_NONCOHERENT
>> 631 select HW_HAS_EISA
>> 632 select I8253
>> 633 select I8259
>> 634 select IP22_CPU_SCACHE
>> 635 select IRQ_MIPS_CPU
>> 636 select GENERIC_ISA_DMA_SUPPORT_BROKEN
>> 637 select SGI_HAS_I8042
>> 638 select SGI_HAS_INDYDOG
>> 639 select SGI_HAS_HAL2
>> 640 select SGI_HAS_SEEQ
>> 641 select SGI_HAS_WD93
>> 642 select SGI_HAS_ZILOG
>> 643 select SWAP_IO_SPACE
>> 644 select SYS_HAS_CPU_R4X00
>> 645 select SYS_HAS_CPU_R5000
>> 646 #
>> 647 # Disable EARLY_PRINTK for now since it leads to overwritten prom
>> 648 # memory during early boot on some machines.
>> 649 #
>> 650 # See http://www.linux-mips.org/cgi-bin/mesg.cgi?a=linux-mips&i=20091119164009.GA15038%40deprecation.cyrius.com
>> 651 # for a more details discussion
>> 652 #
>> 653 # select SYS_HAS_EARLY_PRINTK
>> 654 select SYS_SUPPORTS_32BIT_KERNEL
>> 655 select SYS_SUPPORTS_64BIT_KERNEL
>> 656 select SYS_SUPPORTS_BIG_ENDIAN
>> 657 select MIPS_L1_CACHE_SHIFT_7
>> 658 help
>> 659 This are the SGI Indy, Challenge S and Indigo2, as well as certain
>> 660 OEM variants like the Tandem CMN B006S. To compile a Linux kernel
>> 661 that runs on these, say Y here.
>> 662
>> 663 config SGI_IP27
>> 664 bool "SGI IP27 (Origin200/2000)"
>> 665 select FW_ARC
>> 666 select FW_ARC64
>> 667 select BOOT_ELF64
>> 668 select DEFAULT_SGI_PARTITION
>> 669 select DMA_COHERENT
>> 670 select SYS_HAS_EARLY_PRINTK
>> 671 select HW_HAS_PCI
>> 672 select NR_CPUS_DEFAULT_64
>> 673 select SYS_HAS_CPU_R10000
>> 674 select SYS_SUPPORTS_64BIT_KERNEL
>> 675 select SYS_SUPPORTS_BIG_ENDIAN
>> 676 select SYS_SUPPORTS_NUMA
>> 677 select SYS_SUPPORTS_SMP
>> 678 select MIPS_L1_CACHE_SHIFT_7
>> 679 help
>> 680 This are the SGI Origin 200, Origin 2000 and Onyx 2 Graphics
>> 681 workstations. To compile a Linux kernel that runs on these, say Y
>> 682 here.
>> 683
>> 684 config SGI_IP28
>> 685 bool "SGI IP28 (Indigo2 R10k)"
>> 686 select FW_ARC
>> 687 select FW_ARC64
>> 688 select ARCH_MIGHT_HAVE_PC_SERIO
>> 689 select BOOT_ELF64
>> 690 select CEVT_R4K
>> 691 select CSRC_R4K
>> 692 select DEFAULT_SGI_PARTITION
>> 693 select DMA_NONCOHERENT
>> 694 select GENERIC_ISA_DMA_SUPPORT_BROKEN
>> 695 select IRQ_MIPS_CPU
>> 696 select HW_HAS_EISA
>> 697 select I8253
>> 698 select I8259
>> 699 select SGI_HAS_I8042
>> 700 select SGI_HAS_INDYDOG
>> 701 select SGI_HAS_HAL2
>> 702 select SGI_HAS_SEEQ
>> 703 select SGI_HAS_WD93
>> 704 select SGI_HAS_ZILOG
>> 705 select SWAP_IO_SPACE
>> 706 select SYS_HAS_CPU_R10000
>> 707 #
>> 708 # Disable EARLY_PRINTK for now since it leads to overwritten prom
>> 709 # memory during early boot on some machines.
>> 710 #
>> 711 # See http://www.linux-mips.org/cgi-bin/mesg.cgi?a=linux-mips&i=20091119164009.GA15038%40deprecation.cyrius.com
>> 712 # for a more details discussion
>> 713 #
>> 714 # select SYS_HAS_EARLY_PRINTK
>> 715 select SYS_SUPPORTS_64BIT_KERNEL
>> 716 select SYS_SUPPORTS_BIG_ENDIAN
>> 717 select MIPS_L1_CACHE_SHIFT_7
>> 718 help
>> 719 This is the SGI Indigo2 with R10000 processor. To compile a Linux
>> 720 kernel that runs on these, say Y here.
>> 721
>> 722 config SGI_IP32
>> 723 bool "SGI IP32 (O2)"
>> 724 select FW_ARC
>> 725 select FW_ARC32
>> 726 select BOOT_ELF32
>> 727 select CEVT_R4K
>> 728 select CSRC_R4K
>> 729 select DMA_NONCOHERENT
>> 730 select HW_HAS_PCI
>> 731 select IRQ_MIPS_CPU
>> 732 select R5000_CPU_SCACHE
>> 733 select RM7000_CPU_SCACHE
>> 734 select SYS_HAS_CPU_R5000
>> 735 select SYS_HAS_CPU_R10000 if BROKEN
>> 736 select SYS_HAS_CPU_RM7000
>> 737 select SYS_HAS_CPU_NEVADA
>> 738 select SYS_SUPPORTS_64BIT_KERNEL
>> 739 select SYS_SUPPORTS_BIG_ENDIAN
>> 740 help
>> 741 If you want this kernel to run on SGI O2 workstation, say Y here.
>> 742
>> 743 config SIBYTE_CRHINE
>> 744 bool "Sibyte BCM91120C-CRhine"
>> 745 select BOOT_ELF32
>> 746 select DMA_COHERENT
>> 747 select SIBYTE_BCM1120
>> 748 select SWAP_IO_SPACE
>> 749 select SYS_HAS_CPU_SB1
>> 750 select SYS_SUPPORTS_BIG_ENDIAN
>> 751 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 752
>> 753 config SIBYTE_CARMEL
>> 754 bool "Sibyte BCM91120x-Carmel"
>> 755 select BOOT_ELF32
>> 756 select DMA_COHERENT
>> 757 select SIBYTE_BCM1120
>> 758 select SWAP_IO_SPACE
>> 759 select SYS_HAS_CPU_SB1
>> 760 select SYS_SUPPORTS_BIG_ENDIAN
>> 761 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 762
>> 763 config SIBYTE_CRHONE
>> 764 bool "Sibyte BCM91125C-CRhone"
>> 765 select BOOT_ELF32
>> 766 select DMA_COHERENT
>> 767 select SIBYTE_BCM1125
>> 768 select SWAP_IO_SPACE
>> 769 select SYS_HAS_CPU_SB1
>> 770 select SYS_SUPPORTS_BIG_ENDIAN
>> 771 select SYS_SUPPORTS_HIGHMEM
>> 772 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 773
>> 774 config SIBYTE_RHONE
>> 775 bool "Sibyte BCM91125E-Rhone"
>> 776 select BOOT_ELF32
>> 777 select DMA_COHERENT
>> 778 select SIBYTE_BCM1125H
>> 779 select SWAP_IO_SPACE
>> 780 select SYS_HAS_CPU_SB1
>> 781 select SYS_SUPPORTS_BIG_ENDIAN
>> 782 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 783
>> 784 config SIBYTE_SWARM
>> 785 bool "Sibyte BCM91250A-SWARM"
>> 786 select BOOT_ELF32
>> 787 select DMA_COHERENT
>> 788 select HAVE_PATA_PLATFORM
>> 789 select SIBYTE_SB1250
>> 790 select SWAP_IO_SPACE
>> 791 select SYS_HAS_CPU_SB1
>> 792 select SYS_SUPPORTS_BIG_ENDIAN
>> 793 select SYS_SUPPORTS_HIGHMEM
>> 794 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 795 select ZONE_DMA32 if 64BIT
>> 796
>> 797 config SIBYTE_LITTLESUR
>> 798 bool "Sibyte BCM91250C2-LittleSur"
>> 799 select BOOT_ELF32
>> 800 select DMA_COHERENT
>> 801 select HAVE_PATA_PLATFORM
>> 802 select SIBYTE_SB1250
>> 803 select SWAP_IO_SPACE
>> 804 select SYS_HAS_CPU_SB1
>> 805 select SYS_SUPPORTS_BIG_ENDIAN
>> 806 select SYS_SUPPORTS_HIGHMEM
>> 807 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 808
>> 809 config SIBYTE_SENTOSA
>> 810 bool "Sibyte BCM91250E-Sentosa"
>> 811 select BOOT_ELF32
>> 812 select DMA_COHERENT
>> 813 select SIBYTE_SB1250
>> 814 select SWAP_IO_SPACE
>> 815 select SYS_HAS_CPU_SB1
>> 816 select SYS_SUPPORTS_BIG_ENDIAN
>> 817 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 818
>> 819 config SIBYTE_BIGSUR
>> 820 bool "Sibyte BCM91480B-BigSur"
>> 821 select BOOT_ELF32
>> 822 select DMA_COHERENT
>> 823 select NR_CPUS_DEFAULT_4
>> 824 select SIBYTE_BCM1x80
>> 825 select SWAP_IO_SPACE
>> 826 select SYS_HAS_CPU_SB1
>> 827 select SYS_SUPPORTS_BIG_ENDIAN
>> 828 select SYS_SUPPORTS_HIGHMEM
>> 829 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 830 select ZONE_DMA32 if 64BIT
>> 831
>> 832 config SNI_RM
>> 833 bool "SNI RM200/300/400"
>> 834 select FW_ARC if CPU_LITTLE_ENDIAN
>> 835 select FW_ARC32 if CPU_LITTLE_ENDIAN
>> 836 select FW_SNIPROM if CPU_BIG_ENDIAN
>> 837 select ARCH_MAY_HAVE_PC_FDC
>> 838 select ARCH_MIGHT_HAVE_PC_PARPORT
>> 839 select ARCH_MIGHT_HAVE_PC_SERIO
>> 840 select BOOT_ELF32
>> 841 select CEVT_R4K
>> 842 select CSRC_R4K
>> 843 select DEFAULT_SGI_PARTITION if CPU_BIG_ENDIAN
>> 844 select DMA_NONCOHERENT
>> 845 select GENERIC_ISA_DMA
>> 846 select HAVE_PCSPKR_PLATFORM
>> 847 select HW_HAS_EISA
>> 848 select HW_HAS_PCI
>> 849 select IRQ_MIPS_CPU
>> 850 select I8253
>> 851 select I8259
>> 852 select ISA
>> 853 select SWAP_IO_SPACE if CPU_BIG_ENDIAN
>> 854 select SYS_HAS_CPU_R4X00
>> 855 select SYS_HAS_CPU_R5000
>> 856 select SYS_HAS_CPU_R10000
>> 857 select R5000_CPU_SCACHE
>> 858 select SYS_HAS_EARLY_PRINTK
>> 859 select SYS_SUPPORTS_32BIT_KERNEL
>> 860 select SYS_SUPPORTS_64BIT_KERNEL
>> 861 select SYS_SUPPORTS_BIG_ENDIAN
>> 862 select SYS_SUPPORTS_HIGHMEM
>> 863 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 864 help
>> 865 The SNI RM200/300/400 are MIPS-based machines manufactured by
>> 866 Siemens Nixdorf Informationssysteme (SNI), parent company of Pyramid
>> 867 Technology and now in turn merged with Fujitsu. Say Y here to
>> 868 support this machine type.
>> 869
>> 870 config MACH_TX39XX
>> 871 bool "Toshiba TX39 series based machines"
>> 872
>> 873 config MACH_TX49XX
>> 874 bool "Toshiba TX49 series based machines"
>> 875
>> 876 config MIKROTIK_RB532
>> 877 bool "Mikrotik RB532 boards"
>> 878 select CEVT_R4K
>> 879 select CSRC_R4K
>> 880 select DMA_NONCOHERENT
>> 881 select HW_HAS_PCI
>> 882 select IRQ_MIPS_CPU
>> 883 select SYS_HAS_CPU_MIPS32_R1
>> 884 select SYS_SUPPORTS_32BIT_KERNEL
>> 885 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 886 select SWAP_IO_SPACE
>> 887 select BOOT_RAW
>> 888 select GPIOLIB
>> 889 select MIPS_L1_CACHE_SHIFT_4
>> 890 help
>> 891 Support the Mikrotik(tm) RouterBoard 532 series,
>> 892 based on the IDT RC32434 SoC.
>> 893
>> 894 config CAVIUM_OCTEON_SOC
>> 895 bool "Cavium Networks Octeon SoC based boards"
>> 896 select CEVT_R4K
>> 897 select ARCH_HAS_PHYS_TO_DMA
>> 898 select PHYS_ADDR_T_64BIT
>> 899 select DMA_COHERENT
>> 900 select SYS_SUPPORTS_64BIT_KERNEL
>> 901 select SYS_SUPPORTS_BIG_ENDIAN
>> 902 select EDAC_SUPPORT
>> 903 select EDAC_ATOMIC_SCRUB
>> 904 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 905 select SYS_SUPPORTS_HOTPLUG_CPU if CPU_BIG_ENDIAN
>> 906 select SYS_HAS_EARLY_PRINTK
>> 907 select SYS_HAS_CPU_CAVIUM_OCTEON
>> 908 select HW_HAS_PCI
>> 909 select ZONE_DMA32
>> 910 select HOLES_IN_ZONE
>> 911 select GPIOLIB
>> 912 select LIBFDT
>> 913 select USE_OF
>> 914 select ARCH_SPARSEMEM_ENABLE
>> 915 select SYS_SUPPORTS_SMP
>> 916 select NR_CPUS_DEFAULT_64
>> 917 select MIPS_NR_CPU_NR_MAP_1024
>> 918 select BUILTIN_DTB
>> 919 select MTD_COMPLEX_MAPPINGS
>> 920 select SWIOTLB
>> 921 select SYS_SUPPORTS_RELOCATABLE
>> 922 help
>> 923 This option supports all of the Octeon reference boards from Cavium
>> 924 Networks. It builds a kernel that dynamically determines the Octeon
>> 925 CPU type and supports all known board reference implementations.
>> 926 Some of the supported boards are:
>> 927 EBT3000
>> 928 EBH3000
>> 929 EBH3100
>> 930 Thunder
>> 931 Kodama
>> 932 Hikari
>> 933 Say Y here for most Octeon reference boards.
>> 934
>> 935 config NLM_XLR_BOARD
>> 936 bool "Netlogic XLR/XLS based systems"
>> 937 select BOOT_ELF32
>> 938 select NLM_COMMON
>> 939 select SYS_HAS_CPU_XLR
>> 940 select SYS_SUPPORTS_SMP
>> 941 select HW_HAS_PCI
>> 942 select SWAP_IO_SPACE
>> 943 select SYS_SUPPORTS_32BIT_KERNEL
>> 944 select SYS_SUPPORTS_64BIT_KERNEL
>> 945 select PHYS_ADDR_T_64BIT
>> 946 select SYS_SUPPORTS_BIG_ENDIAN
>> 947 select SYS_SUPPORTS_HIGHMEM
>> 948 select DMA_COHERENT
>> 949 select NR_CPUS_DEFAULT_32
>> 950 select CEVT_R4K
>> 951 select CSRC_R4K
>> 952 select IRQ_MIPS_CPU
>> 953 select ZONE_DMA32 if 64BIT
>> 954 select SYNC_R4K
>> 955 select SYS_HAS_EARLY_PRINTK
>> 956 select SYS_SUPPORTS_ZBOOT
>> 957 select SYS_SUPPORTS_ZBOOT_UART16550
>> 958 help
>> 959 Support for systems based on Netlogic XLR and XLS processors.
>> 960 Say Y here if you have a XLR or XLS based board.
>> 961
>> 962 config NLM_XLP_BOARD
>> 963 bool "Netlogic XLP based systems"
>> 964 select BOOT_ELF32
>> 965 select NLM_COMMON
>> 966 select SYS_HAS_CPU_XLP
>> 967 select SYS_SUPPORTS_SMP
>> 968 select HW_HAS_PCI
>> 969 select SYS_SUPPORTS_32BIT_KERNEL
>> 970 select SYS_SUPPORTS_64BIT_KERNEL
>> 971 select PHYS_ADDR_T_64BIT
>> 972 select GPIOLIB
>> 973 select SYS_SUPPORTS_BIG_ENDIAN
>> 974 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 975 select SYS_SUPPORTS_HIGHMEM
>> 976 select DMA_COHERENT
>> 977 select NR_CPUS_DEFAULT_32
>> 978 select CEVT_R4K
>> 979 select CSRC_R4K
>> 980 select IRQ_MIPS_CPU
>> 981 select ZONE_DMA32 if 64BIT
>> 982 select SYNC_R4K
>> 983 select SYS_HAS_EARLY_PRINTK
>> 984 select USE_OF
>> 985 select SYS_SUPPORTS_ZBOOT
>> 986 select SYS_SUPPORTS_ZBOOT_UART16550
>> 987 help
>> 988 This board is based on Netlogic XLP Processor.
>> 989 Say Y here if you have a XLP based board.
>> 990
>> 991 config MIPS_PARAVIRT
>> 992 bool "Para-Virtualized guest system"
>> 993 select CEVT_R4K
>> 994 select CSRC_R4K
>> 995 select DMA_COHERENT
>> 996 select SYS_SUPPORTS_64BIT_KERNEL
>> 997 select SYS_SUPPORTS_32BIT_KERNEL
>> 998 select SYS_SUPPORTS_BIG_ENDIAN
>> 999 select SYS_SUPPORTS_SMP
>> 1000 select NR_CPUS_DEFAULT_4
>> 1001 select SYS_HAS_EARLY_PRINTK
>> 1002 select SYS_HAS_CPU_MIPS32_R2
>> 1003 select SYS_HAS_CPU_MIPS64_R2
>> 1004 select SYS_HAS_CPU_CAVIUM_OCTEON
>> 1005 select HW_HAS_PCI
>> 1006 select SWAP_IO_SPACE
>> 1007 help
>> 1008 This option supports guest running under ????
342 1009
343 config STACKTRACE_SUPPORT !! 1010 endchoice
344 def_bool y <<
345 1011
346 config ILLEGAL_POINTER_VALUE !! 1012 source "arch/mips/alchemy/Kconfig"
347 hex !! 1013 source "arch/mips/ath25/Kconfig"
348 default 0xdead000000000000 !! 1014 source "arch/mips/ath79/Kconfig"
>> 1015 source "arch/mips/bcm47xx/Kconfig"
>> 1016 source "arch/mips/bcm63xx/Kconfig"
>> 1017 source "arch/mips/bmips/Kconfig"
>> 1018 source "arch/mips/generic/Kconfig"
>> 1019 source "arch/mips/jazz/Kconfig"
>> 1020 source "arch/mips/jz4740/Kconfig"
>> 1021 source "arch/mips/lantiq/Kconfig"
>> 1022 source "arch/mips/lasat/Kconfig"
>> 1023 source "arch/mips/pic32/Kconfig"
>> 1024 source "arch/mips/pistachio/Kconfig"
>> 1025 source "arch/mips/pmcs-msp71xx/Kconfig"
>> 1026 source "arch/mips/ralink/Kconfig"
>> 1027 source "arch/mips/sgi-ip27/Kconfig"
>> 1028 source "arch/mips/sibyte/Kconfig"
>> 1029 source "arch/mips/txx9/Kconfig"
>> 1030 source "arch/mips/vr41xx/Kconfig"
>> 1031 source "arch/mips/cavium-octeon/Kconfig"
>> 1032 source "arch/mips/loongson32/Kconfig"
>> 1033 source "arch/mips/loongson64/Kconfig"
>> 1034 source "arch/mips/netlogic/Kconfig"
>> 1035 source "arch/mips/paravirt/Kconfig"
349 1036
350 config LOCKDEP_SUPPORT !! 1037 endmenu
351 def_bool y <<
352 1038
353 config GENERIC_BUG !! 1039 config RWSEM_GENERIC_SPINLOCK
354 def_bool y !! 1040 bool
355 depends on BUG !! 1041 default y
356 1042
357 config GENERIC_BUG_RELATIVE_POINTERS !! 1043 config RWSEM_XCHGADD_ALGORITHM
358 def_bool y !! 1044 bool
359 depends on GENERIC_BUG <<
360 1045
361 config GENERIC_HWEIGHT 1046 config GENERIC_HWEIGHT
362 def_bool y <<
363 <<
364 config GENERIC_CSUM <<
365 def_bool y <<
366 <<
367 config GENERIC_CALIBRATE_DELAY <<
368 def_bool y <<
369 <<
370 config SMP <<
371 def_bool y <<
372 <<
373 config KERNEL_MODE_NEON <<
374 def_bool y <<
375 <<
376 config FIX_EARLYCON_MEM <<
377 def_bool y <<
378 <<
379 config PGTABLE_LEVELS <<
380 int <<
381 default 2 if ARM64_16K_PAGES && ARM64_ <<
382 default 2 if ARM64_64K_PAGES && ARM64_ <<
383 default 3 if ARM64_64K_PAGES && (ARM64 <<
384 default 3 if ARM64_4K_PAGES && ARM64_V <<
385 default 3 if ARM64_16K_PAGES && ARM64_ <<
386 default 4 if ARM64_16K_PAGES && (ARM64 <<
387 default 4 if !ARM64_64K_PAGES && ARM64 <<
388 default 5 if ARM64_4K_PAGES && ARM64_V <<
389 <<
390 config ARCH_SUPPORTS_UPROBES <<
391 def_bool y <<
392 <<
393 config ARCH_PROC_KCORE_TEXT <<
394 def_bool y <<
395 <<
396 config BROKEN_GAS_INST <<
397 def_bool !$(as-instr,1:\n.inst 0\n.rep <<
398 <<
399 config BUILTIN_RETURN_ADDRESS_STRIPS_PAC <<
400 bool 1047 bool
401 # Clang's __builtin_return_address() s !! 1048 default y
402 # https://github.com/llvm/llvm-project <<
403 default y if CC_IS_CLANG <<
404 # GCC's __builtin_return_address() str <<
405 # and this was backported to 10.2.0, 9 <<
406 # https://gcc.gnu.org/bugzilla/show_bu <<
407 default y if CC_IS_GCC && (GCC_VERSION <<
408 default y if CC_IS_GCC && (GCC_VERSION <<
409 default y if CC_IS_GCC && (GCC_VERSION <<
410 default y if CC_IS_GCC && (GCC_VERSION <<
411 default n <<
412 <<
413 config KASAN_SHADOW_OFFSET <<
414 hex <<
415 depends on KASAN_GENERIC || KASAN_SW_T <<
416 default 0xdfff800000000000 if (ARM64_V <<
417 default 0xdfffc00000000000 if (ARM64_V <<
418 default 0xdffffe0000000000 if ARM64_VA <<
419 default 0xdfffffc000000000 if ARM64_VA <<
420 default 0xdffffff800000000 if ARM64_VA <<
421 default 0xefff800000000000 if (ARM64_V <<
422 default 0xefffc00000000000 if (ARM64_V <<
423 default 0xeffffe0000000000 if ARM64_VA <<
424 default 0xefffffc000000000 if ARM64_VA <<
425 default 0xeffffff800000000 if ARM64_VA <<
426 default 0xffffffffffffffff <<
427 <<
428 config UNWIND_TABLES <<
429 bool <<
430 <<
431 source "arch/arm64/Kconfig.platforms" <<
432 <<
433 menu "Kernel Features" <<
434 <<
435 menu "ARM errata workarounds via the alternati <<
436 <<
437 config AMPERE_ERRATUM_AC03_CPU_38 <<
438 bool "AmpereOne: AC03_CPU_38: Certain <<
439 default y <<
440 help <<
441 This option adds an alternative code <<
442 errata AC03_CPU_38 and AC04_CPU_10 o <<
443 <<
444 The affected design reports FEAT_HAF <<
445 ID_AA64MMFR1_EL1.HAFDBS, but (V)TCR_ <<
446 as required by the architecture. The <<
447 implementation suffers from an addit <<
448 A/D updates can occur after a PTE ha <<
449 <<
450 The workaround forces KVM to explici <<
451 which avoids enabling unadvertised h <<
452 at stage-2. <<
453 <<
454 If unsure, say Y. <<
455 1049
456 config ARM64_WORKAROUND_CLEAN_CACHE !! 1050 config GENERIC_CALIBRATE_DELAY
457 bool 1051 bool
458 <<
459 config ARM64_ERRATUM_826319 <<
460 bool "Cortex-A53: 826319: System might <<
461 default y 1052 default y
462 select ARM64_WORKAROUND_CLEAN_CACHE <<
463 help <<
464 This option adds an alternative code <<
465 erratum 826319 on Cortex-A53 parts u <<
466 AXI master interface and an L2 cache <<
467 <<
468 If a Cortex-A53 uses an AMBA AXI4 AC <<
469 and is unable to accept a certain wr <<
470 not progress on read data presented <<
471 system can deadlock. <<
472 1053
473 The workaround promotes data cache c !! 1054 config SCHED_OMIT_FRAME_POINTER
474 data cache clean-and-invalidate. !! 1055 bool
475 Please note that this does not neces <<
476 as it depends on the alternative fra <<
477 the kernel if an affected CPU is det <<
478 <<
479 If unsure, say Y. <<
480 <<
481 config ARM64_ERRATUM_827319 <<
482 bool "Cortex-A53: 827319: Data cache c <<
483 default y 1056 default y
484 select ARM64_WORKAROUND_CLEAN_CACHE <<
485 help <<
486 This option adds an alternative code <<
487 erratum 827319 on Cortex-A53 parts u <<
488 master interface and an L2 cache. <<
489 <<
490 Under certain conditions this erratu <<
491 to occur at the same time as another <<
492 on the AMBA 5 CHI interface, which c <<
493 interconnect reorders the two transa <<
494 <<
495 The workaround promotes data cache c <<
496 data cache clean-and-invalidate. <<
497 Please note that this does not neces <<
498 as it depends on the alternative fra <<
499 the kernel if an affected CPU is det <<
500 1057
501 If unsure, say Y. !! 1058 #
502 !! 1059 # Select some configuration options automatically based on user selections.
503 config ARM64_ERRATUM_824069 !! 1060 #
504 bool "Cortex-A53: 824069: Cache line m !! 1061 config FW_ARC
505 default y !! 1062 bool
506 select ARM64_WORKAROUND_CLEAN_CACHE <<
507 help <<
508 This option adds an alternative code <<
509 erratum 824069 on Cortex-A53 parts u <<
510 to a coherent interconnect. <<
511 <<
512 If a Cortex-A53 processor is executi <<
513 write instruction at the same time a <<
514 cluster is executing a cache mainten <<
515 address, then this erratum might cau <<
516 incorrectly marked as dirty. <<
517 <<
518 The workaround promotes data cache c <<
519 data cache clean-and-invalidate. <<
520 Please note that this option does no <<
521 workaround, as it depends on the alt <<
522 only patch the kernel if an affected <<
523 1063
524 If unsure, say Y. !! 1064 config ARCH_MAY_HAVE_PC_FDC
>> 1065 bool
525 1066
526 config ARM64_ERRATUM_819472 !! 1067 config BOOT_RAW
527 bool "Cortex-A53: 819472: Store exclus !! 1068 bool
528 default y <<
529 select ARM64_WORKAROUND_CLEAN_CACHE <<
530 help <<
531 This option adds an alternative code <<
532 erratum 819472 on Cortex-A53 parts u <<
533 present when it is connected to a co <<
534 <<
535 If the processor is executing a load <<
536 the same time as a processor in anot <<
537 maintenance operation to the same ad <<
538 cause data corruption. <<
539 <<
540 The workaround promotes data cache c <<
541 data cache clean-and-invalidate. <<
542 Please note that this does not neces <<
543 as it depends on the alternative fra <<
544 the kernel if an affected CPU is det <<
545 1069
546 If unsure, say Y. !! 1070 config CEVT_BCM1480
>> 1071 bool
547 1072
548 config ARM64_ERRATUM_832075 !! 1073 config CEVT_DS1287
549 bool "Cortex-A57: 832075: possible dea !! 1074 bool
550 default y <<
551 help <<
552 This option adds an alternative code <<
553 erratum 832075 on Cortex-A57 parts u <<
554 1075
555 Affected Cortex-A57 parts might dead !! 1076 config CEVT_GT641XX
556 instructions to Write-Back memory ar !! 1077 bool
557 1078
558 The workaround is to promote device !! 1079 config CEVT_R4K
559 semantics. !! 1080 bool
560 Please note that this does not neces <<
561 as it depends on the alternative fra <<
562 the kernel if an affected CPU is det <<
563 1081
564 If unsure, say Y. !! 1082 config CEVT_SB1250
>> 1083 bool
565 1084
566 config ARM64_ERRATUM_834220 !! 1085 config CEVT_TXX9
567 bool "Cortex-A57: 834220: Stage 2 tran !! 1086 bool
568 depends on KVM <<
569 help <<
570 This option adds an alternative code <<
571 erratum 834220 on Cortex-A57 parts u <<
572 <<
573 Affected Cortex-A57 parts might repo <<
574 fault as the result of a Stage 1 fau <<
575 page boundary when there is a permis <<
576 alignment fault at Stage 1 and a tra <<
577 <<
578 The workaround is to verify that the <<
579 doesn't generate a fault before hand <<
580 Please note that this does not neces <<
581 as it depends on the alternative fra <<
582 the kernel if an affected CPU is det <<
583 1087
584 If unsure, say N. !! 1088 config CSRC_BCM1480
>> 1089 bool
585 1090
586 config ARM64_ERRATUM_1742098 !! 1091 config CSRC_IOASIC
587 bool "Cortex-A57/A72: 1742098: ELR rec !! 1092 bool
588 depends on COMPAT <<
589 default y <<
590 help <<
591 This option removes the AES hwcap fo <<
592 workaround erratum 1742098 on Cortex <<
593 <<
594 Affected parts may corrupt the AES s <<
595 taken between a pair of AES instruct <<
596 are only present if the cryptography <<
597 All software should have a fallback <<
598 that don't implement the cryptograph <<
599 1093
600 If unsure, say Y. !! 1094 config CSRC_R4K
>> 1095 bool
601 1096
602 config ARM64_ERRATUM_845719 !! 1097 config CSRC_SB1250
603 bool "Cortex-A53: 845719: a load might !! 1098 bool
604 depends on COMPAT <<
605 default y <<
606 help <<
607 This option adds an alternative code <<
608 erratum 845719 on Cortex-A53 parts u <<
609 <<
610 When running a compat (AArch32) user <<
611 part, a load at EL0 from a virtual a <<
612 bits of the virtual address used by <<
613 might return incorrect data. <<
614 <<
615 The workaround is to write the conte <<
616 return to a 32-bit task. <<
617 Please note that this does not neces <<
618 as it depends on the alternative fra <<
619 the kernel if an affected CPU is det <<
620 1099
621 If unsure, say Y. !! 1100 config MIPS_CLOCK_VSYSCALL
>> 1101 def_bool CSRC_R4K || CLKSRC_MIPS_GIC
622 1102
623 config ARM64_ERRATUM_843419 !! 1103 config GPIO_TXX9
624 bool "Cortex-A53: 843419: A load or st !! 1104 select GPIOLIB
625 default y !! 1105 bool
626 help <<
627 This option links the kernel with '- <<
628 enables PLT support to replace certa <<
629 cause subsequent memory accesses to <<
630 Cortex-A53 parts up to r0p4. <<
631 1106
632 If unsure, say Y. !! 1107 config FW_CFE
>> 1108 bool
633 1109
634 config ARM64_LD_HAS_FIX_ERRATUM_843419 !! 1110 config ARCH_SUPPORTS_UPROBES
635 def_bool $(ld-option,--fix-cortex-a53- !! 1111 bool
636 1112
637 config ARM64_ERRATUM_1024718 !! 1113 config DMA_MAYBE_COHERENT
638 bool "Cortex-A55: 1024718: Update of D !! 1114 select DMA_NONCOHERENT
639 default y !! 1115 bool
640 help <<
641 This option adds a workaround for AR <<
642 1116
643 Affected Cortex-A55 cores (all revis !! 1117 config DMA_PERDEV_COHERENT
644 update of the hardware dirty bit whe !! 1118 bool
645 without a break-before-make. The wor !! 1119 select DMA_MAYBE_COHERENT
646 of hardware DBM locally on the affec <<
647 this erratum will continue to use th <<
648 1120
649 If unsure, say Y. !! 1121 config DMA_COHERENT
>> 1122 bool
650 1123
651 config ARM64_ERRATUM_1418040 !! 1124 config DMA_NONCOHERENT
652 bool "Cortex-A76/Neoverse-N1: MRC read !! 1125 bool
653 default y !! 1126 select NEED_DMA_MAP_STATE
654 depends on COMPAT <<
655 help <<
656 This option adds a workaround for AR <<
657 errata 1188873 and 1418040. <<
658 1127
659 Affected Cortex-A76/Neoverse-N1 core !! 1128 config SYS_HAS_EARLY_PRINTK
660 cause register corruption when acces !! 1129 bool
661 from AArch32 userspace. <<
662 1130
663 If unsure, say Y. !! 1131 config SYS_SUPPORTS_HOTPLUG_CPU
>> 1132 bool
664 1133
665 config ARM64_WORKAROUND_SPECULATIVE_AT !! 1134 config MIPS_BONITO64
666 bool 1135 bool
667 1136
668 config ARM64_ERRATUM_1165522 !! 1137 config MIPS_MSC
669 bool "Cortex-A76: 1165522: Speculative !! 1138 bool
670 default y <<
671 select ARM64_WORKAROUND_SPECULATIVE_AT <<
672 help <<
673 This option adds a workaround for AR <<
674 1139
675 Affected Cortex-A76 cores (r0p0, r1p !! 1140 config MIPS_NILE4
676 corrupted TLBs by speculating an AT !! 1141 bool
677 context switch. <<
678 1142
679 If unsure, say Y. !! 1143 config SYNC_R4K
>> 1144 bool
680 1145
681 config ARM64_ERRATUM_1319367 !! 1146 config MIPS_MACHINE
682 bool "Cortex-A57/A72: 1319537: Specula !! 1147 def_bool n
683 default y <<
684 select ARM64_WORKAROUND_SPECULATIVE_AT <<
685 help <<
686 This option adds work arounds for AR <<
687 and A72 erratum 1319367 <<
688 1148
689 Cortex-A57 and A72 cores could end-u !! 1149 config NO_IOPORT_MAP
690 speculating an AT instruction during !! 1150 def_bool n
691 1151
692 If unsure, say Y. !! 1152 config GENERIC_CSUM
>> 1153 bool
693 1154
694 config ARM64_ERRATUM_1530923 !! 1155 config GENERIC_ISA_DMA
695 bool "Cortex-A55: 1530923: Speculative !! 1156 bool
696 default y !! 1157 select ZONE_DMA if GENERIC_ISA_DMA_SUPPORT_BROKEN=n
697 select ARM64_WORKAROUND_SPECULATIVE_AT !! 1158 select ISA_DMA_API
698 help <<
699 This option adds a workaround for AR <<
700 1159
701 Affected Cortex-A55 cores (r0p0, r0p !! 1160 config GENERIC_ISA_DMA_SUPPORT_BROKEN
702 corrupted TLBs by speculating an AT !! 1161 bool
703 context switch. !! 1162 select GENERIC_ISA_DMA
704 1163
705 If unsure, say Y. !! 1164 config ISA_DMA_API
>> 1165 bool
706 1166
707 config ARM64_WORKAROUND_REPEAT_TLBI !! 1167 config HOLES_IN_ZONE
708 bool 1168 bool
709 1169
710 config ARM64_ERRATUM_2441007 !! 1170 config SYS_SUPPORTS_RELOCATABLE
711 bool "Cortex-A55: Completion of affect !! 1171 bool
712 select ARM64_WORKAROUND_REPEAT_TLBI <<
713 help 1172 help
714 This option adds a workaround for AR !! 1173 Selected if the platform supports relocating the kernel.
715 !! 1174 The platform must provide plat_get_fdt() if it selects CONFIG_USE_OF
716 Under very rare circumstances, affec !! 1175 to allow access to command line and entropy sources.
717 may not handle a race between a brea <<
718 CPU, and another CPU accessing the s <<
719 store to a page that has been unmapp <<
720 1176
721 Work around this by adding the affec !! 1177 config MIPS_CBPF_JIT
722 TLB sequences to be done twice. !! 1178 def_bool y
>> 1179 depends on BPF_JIT && HAVE_CBPF_JIT
723 1180
724 If unsure, say N. !! 1181 config MIPS_EBPF_JIT
>> 1182 def_bool y
>> 1183 depends on BPF_JIT && HAVE_EBPF_JIT
725 1184
726 config ARM64_ERRATUM_1286807 <<
727 bool "Cortex-A76: Modification of the <<
728 select ARM64_WORKAROUND_REPEAT_TLBI <<
729 help <<
730 This option adds a workaround for AR <<
731 <<
732 On the affected Cortex-A76 cores (r0 <<
733 address for a cacheable mapping of a <<
734 accessed by a core while another cor <<
735 address to a new physical page using <<
736 break-before-make sequence, then und <<
737 TLBI+DSB completes before a read usi <<
738 invalidated has been observed by oth <<
739 workaround repeats the TLBI+DSB oper <<
740 1185
741 If unsure, say N. !! 1186 #
742 !! 1187 # Endianness selection. Sufficiently obscure so many users don't know what to
743 config ARM64_ERRATUM_1463225 !! 1188 # answer,so we try hard to limit the available choices. Also the use of a
744 bool "Cortex-A76: Software Step might !! 1189 # choice statement should be more obvious to the user.
745 default y !! 1190 #
>> 1191 choice
>> 1192 prompt "Endianness selection"
746 help 1193 help
747 This option adds a workaround for Ar !! 1194 Some MIPS machines can be configured for either little or big endian
>> 1195 byte order. These modes require different kernels and a different
>> 1196 Linux distribution. In general there is one preferred byteorder for a
>> 1197 particular system but some systems are just as commonly used in the
>> 1198 one or the other endianness.
748 1199
749 On the affected Cortex-A76 cores (r0 !! 1200 config CPU_BIG_ENDIAN
750 of a system call instruction (SVC) c !! 1201 bool "Big endian"
751 subsequent interrupts when software !! 1202 depends on SYS_SUPPORTS_BIG_ENDIAN
752 exception handler of the system call <<
753 is enabled or VHE is in use. <<
754 1203
755 Work around the erratum by triggerin !! 1204 config CPU_LITTLE_ENDIAN
756 when handling a system call from a t !! 1205 bool "Little endian"
757 in a VHE configuration of the kernel !! 1206 depends on SYS_SUPPORTS_LITTLE_ENDIAN
758 1207
759 If unsure, say Y. !! 1208 endchoice
760 1209
761 config ARM64_ERRATUM_1542419 !! 1210 config EXPORT_UASM
762 bool "Neoverse-N1: workaround mis-orde !! 1211 bool
763 help <<
764 This option adds a workaround for AR <<
765 1542419. <<
766 1212
767 Affected Neoverse-N1 cores could exe !! 1213 config SYS_SUPPORTS_APM_EMULATION
768 modified by another CPU. The workaro !! 1214 bool
769 counterpart. <<
770 1215
771 Workaround the issue by hiding the D !! 1216 config SYS_SUPPORTS_BIG_ENDIAN
772 forces user-space to perform cache m !! 1217 bool
773 1218
774 If unsure, say N. !! 1219 config SYS_SUPPORTS_LITTLE_ENDIAN
>> 1220 bool
775 1221
776 config ARM64_ERRATUM_1508412 !! 1222 config SYS_SUPPORTS_HUGETLBFS
777 bool "Cortex-A77: 1508412: workaround !! 1223 bool
>> 1224 depends on CPU_SUPPORTS_HUGEPAGES && 64BIT
778 default y 1225 default y
779 help <<
780 This option adds a workaround for Ar <<
781 1226
782 Affected Cortex-A77 cores (r0p0, r1p !! 1227 config MIPS_HUGE_TLB_SUPPORT
783 of a store-exclusive or read of PAR_ !! 1228 def_bool HUGETLB_PAGE || TRANSPARENT_HUGEPAGE
784 non-cacheable memory attributes. The <<
785 counterpart. <<
786 1229
787 KVM guests must also have the workar !! 1230 config IRQ_CPU_RM7K
788 deadlock the system. !! 1231 bool
789 1232
790 Work around the issue by inserting D !! 1233 config IRQ_MSP_SLP
791 register reads and warning KVM users !! 1234 bool
792 to prevent a speculative PAR_EL1 rea <<
793 1235
794 If unsure, say Y. !! 1236 config IRQ_MSP_CIC
>> 1237 bool
795 1238
796 config ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MO !! 1239 config IRQ_TXX9
797 bool 1240 bool
798 1241
799 config ARM64_ERRATUM_2051678 !! 1242 config IRQ_GT641XX
800 bool "Cortex-A510: 2051678: disable Ha !! 1243 bool
801 default y <<
802 help <<
803 This options adds the workaround for <<
804 Affected Cortex-A510 might not respe <<
805 hardware update of the page table's <<
806 is to not enable the feature on affe <<
807 1244
808 If unsure, say Y. !! 1245 config PCI_GT64XXX_PCI0
>> 1246 bool
809 1247
810 config ARM64_ERRATUM_2077057 !! 1248 config NO_EXCEPT_FILL
811 bool "Cortex-A510: 2077057: workaround !! 1249 bool
812 default y <<
813 help <<
814 This option adds the workaround for <<
815 Affected Cortex-A510 may corrupt SPS <<
816 expected, but a Pointer Authenticati <<
817 erratum causes SPSR_EL1 to be copied <<
818 EL1 to cause a return to EL2 with a <<
819 1250
820 This can only happen when EL2 is ste !! 1251 config SOC_EMMA2RH
>> 1252 bool
>> 1253 select CEVT_R4K
>> 1254 select CSRC_R4K
>> 1255 select DMA_NONCOHERENT
>> 1256 select IRQ_MIPS_CPU
>> 1257 select SWAP_IO_SPACE
>> 1258 select SYS_HAS_CPU_R5500
>> 1259 select SYS_SUPPORTS_32BIT_KERNEL
>> 1260 select SYS_SUPPORTS_64BIT_KERNEL
>> 1261 select SYS_SUPPORTS_BIG_ENDIAN
821 1262
822 When these conditions occur, the SPS !! 1263 config SOC_PNX833X
823 previous guest entry, and can be res !! 1264 bool
>> 1265 select CEVT_R4K
>> 1266 select CSRC_R4K
>> 1267 select IRQ_MIPS_CPU
>> 1268 select DMA_NONCOHERENT
>> 1269 select SYS_HAS_CPU_MIPS32_R2
>> 1270 select SYS_SUPPORTS_32BIT_KERNEL
>> 1271 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 1272 select SYS_SUPPORTS_BIG_ENDIAN
>> 1273 select SYS_SUPPORTS_MIPS16
>> 1274 select CPU_MIPSR2_IRQ_VI
824 1275
825 If unsure, say Y. !! 1276 config SOC_PNX8335
>> 1277 bool
>> 1278 select SOC_PNX833X
826 1279
827 config ARM64_ERRATUM_2658417 !! 1280 config MIPS_SPRAM
828 bool "Cortex-A510: 2658417: remove BF1 !! 1281 bool
829 default y <<
830 help <<
831 This option adds the workaround for <<
832 Affected Cortex-A510 (r0p0 to r1p1) <<
833 BFMMLA or VMMLA instructions in rare <<
834 A510 CPUs are using shared neon hard <<
835 discoverable by the kernel, hide the <<
836 user-space should not be using these <<
837 1282
838 If unsure, say Y. !! 1283 config SWAP_IO_SPACE
>> 1284 bool
839 1285
840 config ARM64_ERRATUM_2119858 !! 1286 config SGI_HAS_INDYDOG
841 bool "Cortex-A710/X2: 2119858: workaro !! 1287 bool
842 default y <<
843 depends on CORESIGHT_TRBE <<
844 select ARM64_WORKAROUND_TRBE_OVERWRITE <<
845 help <<
846 This option adds the workaround for <<
847 1288
848 Affected Cortex-A710/X2 cores could !! 1289 config SGI_HAS_HAL2
849 data at the base of the buffer (poin !! 1290 bool
850 the event of a WRAP event. <<
851 1291
852 Work around the issue by always maki !! 1292 config SGI_HAS_SEEQ
853 256 bytes before enabling the buffer !! 1293 bool
854 the buffer with ETM ignore packets u <<
855 1294
856 If unsure, say Y. !! 1295 config SGI_HAS_WD93
>> 1296 bool
857 1297
858 config ARM64_ERRATUM_2139208 !! 1298 config SGI_HAS_ZILOG
859 bool "Neoverse-N2: 2139208: workaround !! 1299 bool
860 default y <<
861 depends on CORESIGHT_TRBE <<
862 select ARM64_WORKAROUND_TRBE_OVERWRITE <<
863 help <<
864 This option adds the workaround for <<
865 1300
866 Affected Neoverse-N2 cores could ove !! 1301 config SGI_HAS_I8042
867 data at the base of the buffer (poin !! 1302 bool
868 the event of a WRAP event. <<
869 1303
870 Work around the issue by always maki !! 1304 config DEFAULT_SGI_PARTITION
871 256 bytes before enabling the buffer !! 1305 bool
872 the buffer with ETM ignore packets u <<
873 1306
874 If unsure, say Y. !! 1307 config FW_ARC32
>> 1308 bool
875 1309
876 config ARM64_WORKAROUND_TSB_FLUSH_FAILURE !! 1310 config FW_SNIPROM
877 bool 1311 bool
878 1312
879 config ARM64_ERRATUM_2054223 !! 1313 config BOOT_ELF32
880 bool "Cortex-A710: 2054223: workaround !! 1314 bool
881 default y <<
882 select ARM64_WORKAROUND_TSB_FLUSH_FAIL <<
883 help <<
884 Enable workaround for ARM Cortex-A71 <<
885 1315
886 Affected cores may fail to flush the !! 1316 config MIPS_L1_CACHE_SHIFT_4
887 the PE is in trace prohibited state. !! 1317 bool
888 of the trace cached. <<
889 1318
890 Workaround is to issue two TSB conse !! 1319 config MIPS_L1_CACHE_SHIFT_5
>> 1320 bool
891 1321
892 If unsure, say Y. !! 1322 config MIPS_L1_CACHE_SHIFT_6
>> 1323 bool
893 1324
894 config ARM64_ERRATUM_2067961 !! 1325 config MIPS_L1_CACHE_SHIFT_7
895 bool "Neoverse-N2: 2067961: workaround !! 1326 bool
896 default y <<
897 select ARM64_WORKAROUND_TSB_FLUSH_FAIL <<
898 help <<
899 Enable workaround for ARM Neoverse-N <<
900 1327
901 Affected cores may fail to flush the !! 1328 config MIPS_L1_CACHE_SHIFT
902 the PE is in trace prohibited state. !! 1329 int
903 of the trace cached. !! 1330 default "7" if MIPS_L1_CACHE_SHIFT_7
>> 1331 default "6" if MIPS_L1_CACHE_SHIFT_6
>> 1332 default "5" if MIPS_L1_CACHE_SHIFT_5
>> 1333 default "4" if MIPS_L1_CACHE_SHIFT_4
>> 1334 default "5"
904 1335
905 Workaround is to issue two TSB conse !! 1336 config HAVE_STD_PC_SERIAL_PORT
>> 1337 bool
906 1338
907 If unsure, say Y. !! 1339 config ARC_CONSOLE
>> 1340 bool "ARC console support"
>> 1341 depends on SGI_IP22 || SGI_IP28 || (SNI_RM && CPU_LITTLE_ENDIAN)
908 1342
909 config ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANG !! 1343 config ARC_MEMORY
910 bool 1344 bool
911 !! 1345 depends on MACH_JAZZ || SNI_RM || SGI_IP32
912 config ARM64_ERRATUM_2253138 <<
913 bool "Neoverse-N2: 2253138: workaround <<
914 depends on CORESIGHT_TRBE <<
915 default y 1346 default y
916 select ARM64_WORKAROUND_TRBE_WRITE_OUT <<
917 help <<
918 This option adds the workaround for <<
919 <<
920 Affected Neoverse-N2 cores might wri <<
921 for TRBE. Under some conditions, the <<
922 virtually addressed page following t <<
923 (i.e., the TRBLIMITR_EL1.LIMIT), ins <<
924 <<
925 Work around this in the driver by al <<
926 page beyond the TRBLIMITR_EL1.LIMIT, <<
927 1347
928 If unsure, say Y. !! 1348 config ARC_PROMLIB
929 !! 1349 bool
930 config ARM64_ERRATUM_2224489 !! 1350 depends on MACH_JAZZ || SNI_RM || SGI_IP22 || SGI_IP28 || SGI_IP32
931 bool "Cortex-A710/X2: 2224489: workaro <<
932 depends on CORESIGHT_TRBE <<
933 default y 1351 default y
934 select ARM64_WORKAROUND_TRBE_WRITE_OUT <<
935 help <<
936 This option adds the workaround for <<
937 <<
938 Affected Cortex-A710/X2 cores might <<
939 for TRBE. Under some conditions, the <<
940 virtually addressed page following t <<
941 (i.e., the TRBLIMITR_EL1.LIMIT), ins <<
942 <<
943 Work around this in the driver by al <<
944 page beyond the TRBLIMITR_EL1.LIMIT, <<
945 1352
946 If unsure, say Y. !! 1353 config FW_ARC64
>> 1354 bool
947 1355
948 config ARM64_ERRATUM_2441009 !! 1356 config BOOT_ELF64
949 bool "Cortex-A510: Completion of affec !! 1357 bool
950 select ARM64_WORKAROUND_REPEAT_TLBI <<
951 help <<
952 This option adds a workaround for AR <<
953 <<
954 Under very rare circumstances, affec <<
955 may not handle a race between a brea <<
956 CPU, and another CPU accessing the s <<
957 store to a page that has been unmapp <<
958 1358
959 Work around this by adding the affec !! 1359 menu "CPU selection"
960 TLB sequences to be done twice. <<
961 1360
962 If unsure, say N. !! 1361 choice
>> 1362 prompt "CPU type"
>> 1363 default CPU_R4X00
963 1364
964 config ARM64_ERRATUM_2064142 !! 1365 config CPU_LOONGSON3
965 bool "Cortex-A510: 2064142: workaround !! 1366 bool "Loongson 3 CPU"
966 depends on CORESIGHT_TRBE !! 1367 depends on SYS_HAS_CPU_LOONGSON3
967 default y !! 1368 select CPU_SUPPORTS_64BIT_KERNEL
>> 1369 select CPU_SUPPORTS_HIGHMEM
>> 1370 select CPU_SUPPORTS_HUGEPAGES
>> 1371 select WEAK_ORDERING
>> 1372 select WEAK_REORDERING_BEYOND_LLSC
>> 1373 select MIPS_PGD_C0_CONTEXT
>> 1374 select MIPS_L1_CACHE_SHIFT_6
>> 1375 select GPIOLIB
>> 1376 select SWIOTLB
968 help 1377 help
969 This option adds the workaround for !! 1378 The Loongson 3 processor implements the MIPS64R2 instruction
970 !! 1379 set with many extensions.
971 Affected Cortex-A510 core might fail <<
972 TRBE has been disabled. Under some c <<
973 writes into TRBE registers TRBLIMITR <<
974 and TRBTRG_EL1 will be ignored and w <<
975 1380
976 Work around this in the driver by ex !! 1381 config LOONGSON3_ENHANCEMENT
977 is stopped and before performing a s !! 1382 bool "New Loongson 3 CPU Enhancements"
978 registers. !! 1383 default n
>> 1384 select CPU_MIPSR2
>> 1385 select CPU_HAS_PREFETCH
>> 1386 depends on CPU_LOONGSON3
>> 1387 help
>> 1388 New Loongson 3 CPU (since Loongson-3A R2, as opposed to Loongson-3A
>> 1389 R1, Loongson-3B R1 and Loongson-3B R2) has many enhancements, such as
>> 1390 FTLB, L1-VCache, EI/DI/Wait/Prefetch instruction, DSP/DSPv2 ASE, User
>> 1391 Local register, Read-Inhibit/Execute-Inhibit, SFB (Store Fill Buffer),
>> 1392 Fast TLB refill support, etc.
>> 1393
>> 1394 This option enable those enhancements which are not probed at run
>> 1395 time. If you want a generic kernel to run on all Loongson 3 machines,
>> 1396 please say 'N' here. If you want a high-performance kernel to run on
>> 1397 new Loongson 3 machines only, please say 'Y' here.
>> 1398
>> 1399 config CPU_LOONGSON2E
>> 1400 bool "Loongson 2E"
>> 1401 depends on SYS_HAS_CPU_LOONGSON2E
>> 1402 select CPU_LOONGSON2
>> 1403 help
>> 1404 The Loongson 2E processor implements the MIPS III instruction set
>> 1405 with many extensions.
>> 1406
>> 1407 It has an internal FPGA northbridge, which is compatible to
>> 1408 bonito64.
>> 1409
>> 1410 config CPU_LOONGSON2F
>> 1411 bool "Loongson 2F"
>> 1412 depends on SYS_HAS_CPU_LOONGSON2F
>> 1413 select CPU_LOONGSON2
>> 1414 select GPIOLIB
>> 1415 help
>> 1416 The Loongson 2F processor implements the MIPS III instruction set
>> 1417 with many extensions.
>> 1418
>> 1419 Loongson2F have built-in DDR2 and PCIX controller. The PCIX controller
>> 1420 have a similar programming interface with FPGA northbridge used in
>> 1421 Loongson2E.
>> 1422
>> 1423 config CPU_LOONGSON1B
>> 1424 bool "Loongson 1B"
>> 1425 depends on SYS_HAS_CPU_LOONGSON1B
>> 1426 select CPU_LOONGSON1
>> 1427 select LEDS_GPIO_REGISTER
>> 1428 help
>> 1429 The Loongson 1B is a 32-bit SoC, which implements the MIPS32
>> 1430 release 2 instruction set.
>> 1431
>> 1432 config CPU_LOONGSON1C
>> 1433 bool "Loongson 1C"
>> 1434 depends on SYS_HAS_CPU_LOONGSON1C
>> 1435 select CPU_LOONGSON1
>> 1436 select LEDS_GPIO_REGISTER
>> 1437 help
>> 1438 The Loongson 1C is a 32-bit SoC, which implements the MIPS32
>> 1439 release 2 instruction set.
>> 1440
>> 1441 config CPU_MIPS32_R1
>> 1442 bool "MIPS32 Release 1"
>> 1443 depends on SYS_HAS_CPU_MIPS32_R1
>> 1444 select CPU_HAS_PREFETCH
>> 1445 select CPU_SUPPORTS_32BIT_KERNEL
>> 1446 select CPU_SUPPORTS_HIGHMEM
>> 1447 help
>> 1448 Choose this option to build a kernel for release 1 or later of the
>> 1449 MIPS32 architecture. Most modern embedded systems with a 32-bit
>> 1450 MIPS processor are based on a MIPS32 processor. If you know the
>> 1451 specific type of processor in your system, choose those that one
>> 1452 otherwise CPU_MIPS32_R1 is a safe bet for any MIPS32 system.
>> 1453 Release 2 of the MIPS32 architecture is available since several
>> 1454 years so chances are you even have a MIPS32 Release 2 processor
>> 1455 in which case you should choose CPU_MIPS32_R2 instead for better
>> 1456 performance.
>> 1457
>> 1458 config CPU_MIPS32_R2
>> 1459 bool "MIPS32 Release 2"
>> 1460 depends on SYS_HAS_CPU_MIPS32_R2
>> 1461 select CPU_HAS_PREFETCH
>> 1462 select CPU_SUPPORTS_32BIT_KERNEL
>> 1463 select CPU_SUPPORTS_HIGHMEM
>> 1464 select CPU_SUPPORTS_MSA
>> 1465 select HAVE_KVM
>> 1466 help
>> 1467 Choose this option to build a kernel for release 2 or later of the
>> 1468 MIPS32 architecture. Most modern embedded systems with a 32-bit
>> 1469 MIPS processor are based on a MIPS32 processor. If you know the
>> 1470 specific type of processor in your system, choose those that one
>> 1471 otherwise CPU_MIPS32_R1 is a safe bet for any MIPS32 system.
>> 1472
>> 1473 config CPU_MIPS32_R6
>> 1474 bool "MIPS32 Release 6"
>> 1475 depends on SYS_HAS_CPU_MIPS32_R6
>> 1476 select CPU_HAS_PREFETCH
>> 1477 select CPU_SUPPORTS_32BIT_KERNEL
>> 1478 select CPU_SUPPORTS_HIGHMEM
>> 1479 select CPU_SUPPORTS_MSA
>> 1480 select GENERIC_CSUM
>> 1481 select HAVE_KVM
>> 1482 select MIPS_O32_FP64_SUPPORT
>> 1483 help
>> 1484 Choose this option to build a kernel for release 6 or later of the
>> 1485 MIPS32 architecture. New MIPS processors, starting with the Warrior
>> 1486 family, are based on a MIPS32r6 processor. If you own an older
>> 1487 processor, you probably need to select MIPS32r1 or MIPS32r2 instead.
>> 1488
>> 1489 config CPU_MIPS64_R1
>> 1490 bool "MIPS64 Release 1"
>> 1491 depends on SYS_HAS_CPU_MIPS64_R1
>> 1492 select CPU_HAS_PREFETCH
>> 1493 select CPU_SUPPORTS_32BIT_KERNEL
>> 1494 select CPU_SUPPORTS_64BIT_KERNEL
>> 1495 select CPU_SUPPORTS_HIGHMEM
>> 1496 select CPU_SUPPORTS_HUGEPAGES
>> 1497 help
>> 1498 Choose this option to build a kernel for release 1 or later of the
>> 1499 MIPS64 architecture. Many modern embedded systems with a 64-bit
>> 1500 MIPS processor are based on a MIPS64 processor. If you know the
>> 1501 specific type of processor in your system, choose those that one
>> 1502 otherwise CPU_MIPS64_R1 is a safe bet for any MIPS64 system.
>> 1503 Release 2 of the MIPS64 architecture is available since several
>> 1504 years so chances are you even have a MIPS64 Release 2 processor
>> 1505 in which case you should choose CPU_MIPS64_R2 instead for better
>> 1506 performance.
>> 1507
>> 1508 config CPU_MIPS64_R2
>> 1509 bool "MIPS64 Release 2"
>> 1510 depends on SYS_HAS_CPU_MIPS64_R2
>> 1511 select CPU_HAS_PREFETCH
>> 1512 select CPU_SUPPORTS_32BIT_KERNEL
>> 1513 select CPU_SUPPORTS_64BIT_KERNEL
>> 1514 select CPU_SUPPORTS_HIGHMEM
>> 1515 select CPU_SUPPORTS_HUGEPAGES
>> 1516 select CPU_SUPPORTS_MSA
>> 1517 select HAVE_KVM
>> 1518 help
>> 1519 Choose this option to build a kernel for release 2 or later of the
>> 1520 MIPS64 architecture. Many modern embedded systems with a 64-bit
>> 1521 MIPS processor are based on a MIPS64 processor. If you know the
>> 1522 specific type of processor in your system, choose those that one
>> 1523 otherwise CPU_MIPS64_R1 is a safe bet for any MIPS64 system.
>> 1524
>> 1525 config CPU_MIPS64_R6
>> 1526 bool "MIPS64 Release 6"
>> 1527 depends on SYS_HAS_CPU_MIPS64_R6
>> 1528 select CPU_HAS_PREFETCH
>> 1529 select CPU_SUPPORTS_32BIT_KERNEL
>> 1530 select CPU_SUPPORTS_64BIT_KERNEL
>> 1531 select CPU_SUPPORTS_HIGHMEM
>> 1532 select CPU_SUPPORTS_MSA
>> 1533 select GENERIC_CSUM
>> 1534 select MIPS_O32_FP64_SUPPORT if 32BIT || MIPS32_O32
>> 1535 select HAVE_KVM
>> 1536 help
>> 1537 Choose this option to build a kernel for release 6 or later of the
>> 1538 MIPS64 architecture. New MIPS processors, starting with the Warrior
>> 1539 family, are based on a MIPS64r6 processor. If you own an older
>> 1540 processor, you probably need to select MIPS64r1 or MIPS64r2 instead.
>> 1541
>> 1542 config CPU_R3000
>> 1543 bool "R3000"
>> 1544 depends on SYS_HAS_CPU_R3000
>> 1545 select CPU_HAS_WB
>> 1546 select CPU_SUPPORTS_32BIT_KERNEL
>> 1547 select CPU_SUPPORTS_HIGHMEM
>> 1548 help
>> 1549 Please make sure to pick the right CPU type. Linux/MIPS is not
>> 1550 designed to be generic, i.e. Kernels compiled for R3000 CPUs will
>> 1551 *not* work on R4000 machines and vice versa. However, since most
>> 1552 of the supported machines have an R4000 (or similar) CPU, R4x00
>> 1553 might be a safe bet. If the resulting kernel does not work,
>> 1554 try to recompile with R3000.
>> 1555
>> 1556 config CPU_TX39XX
>> 1557 bool "R39XX"
>> 1558 depends on SYS_HAS_CPU_TX39XX
>> 1559 select CPU_SUPPORTS_32BIT_KERNEL
>> 1560
>> 1561 config CPU_VR41XX
>> 1562 bool "R41xx"
>> 1563 depends on SYS_HAS_CPU_VR41XX
>> 1564 select CPU_SUPPORTS_32BIT_KERNEL
>> 1565 select CPU_SUPPORTS_64BIT_KERNEL
>> 1566 help
>> 1567 The options selects support for the NEC VR4100 series of processors.
>> 1568 Only choose this option if you have one of these processors as a
>> 1569 kernel built with this option will not run on any other type of
>> 1570 processor or vice versa.
>> 1571
>> 1572 config CPU_R4300
>> 1573 bool "R4300"
>> 1574 depends on SYS_HAS_CPU_R4300
>> 1575 select CPU_SUPPORTS_32BIT_KERNEL
>> 1576 select CPU_SUPPORTS_64BIT_KERNEL
>> 1577 help
>> 1578 MIPS Technologies R4300-series processors.
>> 1579
>> 1580 config CPU_R4X00
>> 1581 bool "R4x00"
>> 1582 depends on SYS_HAS_CPU_R4X00
>> 1583 select CPU_SUPPORTS_32BIT_KERNEL
>> 1584 select CPU_SUPPORTS_64BIT_KERNEL
>> 1585 select CPU_SUPPORTS_HUGEPAGES
>> 1586 help
>> 1587 MIPS Technologies R4000-series processors other than 4300, including
>> 1588 the R4000, R4400, R4600, and 4700.
>> 1589
>> 1590 config CPU_TX49XX
>> 1591 bool "R49XX"
>> 1592 depends on SYS_HAS_CPU_TX49XX
>> 1593 select CPU_HAS_PREFETCH
>> 1594 select CPU_SUPPORTS_32BIT_KERNEL
>> 1595 select CPU_SUPPORTS_64BIT_KERNEL
>> 1596 select CPU_SUPPORTS_HUGEPAGES
>> 1597
>> 1598 config CPU_R5000
>> 1599 bool "R5000"
>> 1600 depends on SYS_HAS_CPU_R5000
>> 1601 select CPU_SUPPORTS_32BIT_KERNEL
>> 1602 select CPU_SUPPORTS_64BIT_KERNEL
>> 1603 select CPU_SUPPORTS_HUGEPAGES
>> 1604 help
>> 1605 MIPS Technologies R5000-series processors other than the Nevada.
>> 1606
>> 1607 config CPU_R5432
>> 1608 bool "R5432"
>> 1609 depends on SYS_HAS_CPU_R5432
>> 1610 select CPU_SUPPORTS_32BIT_KERNEL
>> 1611 select CPU_SUPPORTS_64BIT_KERNEL
>> 1612 select CPU_SUPPORTS_HUGEPAGES
>> 1613
>> 1614 config CPU_R5500
>> 1615 bool "R5500"
>> 1616 depends on SYS_HAS_CPU_R5500
>> 1617 select CPU_SUPPORTS_32BIT_KERNEL
>> 1618 select CPU_SUPPORTS_64BIT_KERNEL
>> 1619 select CPU_SUPPORTS_HUGEPAGES
>> 1620 help
>> 1621 NEC VR5500 and VR5500A series processors implement 64-bit MIPS IV
>> 1622 instruction set.
>> 1623
>> 1624 config CPU_NEVADA
>> 1625 bool "RM52xx"
>> 1626 depends on SYS_HAS_CPU_NEVADA
>> 1627 select CPU_SUPPORTS_32BIT_KERNEL
>> 1628 select CPU_SUPPORTS_64BIT_KERNEL
>> 1629 select CPU_SUPPORTS_HUGEPAGES
>> 1630 help
>> 1631 QED / PMC-Sierra RM52xx-series ("Nevada") processors.
>> 1632
>> 1633 config CPU_R8000
>> 1634 bool "R8000"
>> 1635 depends on SYS_HAS_CPU_R8000
>> 1636 select CPU_HAS_PREFETCH
>> 1637 select CPU_SUPPORTS_64BIT_KERNEL
>> 1638 help
>> 1639 MIPS Technologies R8000 processors. Note these processors are
>> 1640 uncommon and the support for them is incomplete.
>> 1641
>> 1642 config CPU_R10000
>> 1643 bool "R10000"
>> 1644 depends on SYS_HAS_CPU_R10000
>> 1645 select CPU_HAS_PREFETCH
>> 1646 select CPU_SUPPORTS_32BIT_KERNEL
>> 1647 select CPU_SUPPORTS_64BIT_KERNEL
>> 1648 select CPU_SUPPORTS_HIGHMEM
>> 1649 select CPU_SUPPORTS_HUGEPAGES
>> 1650 help
>> 1651 MIPS Technologies R10000-series processors.
>> 1652
>> 1653 config CPU_RM7000
>> 1654 bool "RM7000"
>> 1655 depends on SYS_HAS_CPU_RM7000
>> 1656 select CPU_HAS_PREFETCH
>> 1657 select CPU_SUPPORTS_32BIT_KERNEL
>> 1658 select CPU_SUPPORTS_64BIT_KERNEL
>> 1659 select CPU_SUPPORTS_HIGHMEM
>> 1660 select CPU_SUPPORTS_HUGEPAGES
>> 1661
>> 1662 config CPU_SB1
>> 1663 bool "SB1"
>> 1664 depends on SYS_HAS_CPU_SB1
>> 1665 select CPU_SUPPORTS_32BIT_KERNEL
>> 1666 select CPU_SUPPORTS_64BIT_KERNEL
>> 1667 select CPU_SUPPORTS_HIGHMEM
>> 1668 select CPU_SUPPORTS_HUGEPAGES
>> 1669 select WEAK_ORDERING
>> 1670
>> 1671 config CPU_CAVIUM_OCTEON
>> 1672 bool "Cavium Octeon processor"
>> 1673 depends on SYS_HAS_CPU_CAVIUM_OCTEON
>> 1674 select CPU_HAS_PREFETCH
>> 1675 select CPU_SUPPORTS_64BIT_KERNEL
>> 1676 select WEAK_ORDERING
>> 1677 select CPU_SUPPORTS_HIGHMEM
>> 1678 select CPU_SUPPORTS_HUGEPAGES
>> 1679 select USB_EHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 1680 select USB_OHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 1681 select MIPS_L1_CACHE_SHIFT_7
>> 1682 select HAVE_KVM
>> 1683 help
>> 1684 The Cavium Octeon processor is a highly integrated chip containing
>> 1685 many ethernet hardware widgets for networking tasks. The processor
>> 1686 can have up to 16 Mips64v2 cores and 8 integrated gigabit ethernets.
>> 1687 Full details can be found at http://www.caviumnetworks.com.
>> 1688
>> 1689 config CPU_BMIPS
>> 1690 bool "Broadcom BMIPS"
>> 1691 depends on SYS_HAS_CPU_BMIPS
>> 1692 select CPU_MIPS32
>> 1693 select CPU_BMIPS32_3300 if SYS_HAS_CPU_BMIPS32_3300
>> 1694 select CPU_BMIPS4350 if SYS_HAS_CPU_BMIPS4350
>> 1695 select CPU_BMIPS4380 if SYS_HAS_CPU_BMIPS4380
>> 1696 select CPU_BMIPS5000 if SYS_HAS_CPU_BMIPS5000
>> 1697 select CPU_SUPPORTS_32BIT_KERNEL
>> 1698 select DMA_NONCOHERENT
>> 1699 select IRQ_MIPS_CPU
>> 1700 select SWAP_IO_SPACE
>> 1701 select WEAK_ORDERING
>> 1702 select CPU_SUPPORTS_HIGHMEM
>> 1703 select CPU_HAS_PREFETCH
>> 1704 select CPU_SUPPORTS_CPUFREQ
>> 1705 select MIPS_EXTERNAL_TIMER
>> 1706 help
>> 1707 Support for BMIPS32/3300/4350/4380 and BMIPS5000 processors.
>> 1708
>> 1709 config CPU_XLR
>> 1710 bool "Netlogic XLR SoC"
>> 1711 depends on SYS_HAS_CPU_XLR
>> 1712 select CPU_SUPPORTS_32BIT_KERNEL
>> 1713 select CPU_SUPPORTS_64BIT_KERNEL
>> 1714 select CPU_SUPPORTS_HIGHMEM
>> 1715 select CPU_SUPPORTS_HUGEPAGES
>> 1716 select WEAK_ORDERING
>> 1717 select WEAK_REORDERING_BEYOND_LLSC
>> 1718 help
>> 1719 Netlogic Microsystems XLR/XLS processors.
>> 1720
>> 1721 config CPU_XLP
>> 1722 bool "Netlogic XLP SoC"
>> 1723 depends on SYS_HAS_CPU_XLP
>> 1724 select CPU_SUPPORTS_32BIT_KERNEL
>> 1725 select CPU_SUPPORTS_64BIT_KERNEL
>> 1726 select CPU_SUPPORTS_HIGHMEM
>> 1727 select WEAK_ORDERING
>> 1728 select WEAK_REORDERING_BEYOND_LLSC
>> 1729 select CPU_HAS_PREFETCH
>> 1730 select CPU_MIPSR2
>> 1731 select CPU_SUPPORTS_HUGEPAGES
>> 1732 select MIPS_ASID_BITS_VARIABLE
>> 1733 help
>> 1734 Netlogic Microsystems XLP processors.
>> 1735 endchoice
979 1736
980 If unsure, say Y. !! 1737 config CPU_MIPS32_3_5_FEATURES
>> 1738 bool "MIPS32 Release 3.5 Features"
>> 1739 depends on SYS_HAS_CPU_MIPS32_R3_5
>> 1740 depends on CPU_MIPS32_R2 || CPU_MIPS32_R6
>> 1741 help
>> 1742 Choose this option to build a kernel for release 2 or later of the
>> 1743 MIPS32 architecture including features from the 3.5 release such as
>> 1744 support for Enhanced Virtual Addressing (EVA).
>> 1745
>> 1746 config CPU_MIPS32_3_5_EVA
>> 1747 bool "Enhanced Virtual Addressing (EVA)"
>> 1748 depends on CPU_MIPS32_3_5_FEATURES
>> 1749 select EVA
>> 1750 default y
>> 1751 help
>> 1752 Choose this option if you want to enable the Enhanced Virtual
>> 1753 Addressing (EVA) on your MIPS32 core (such as proAptiv).
>> 1754 One of its primary benefits is an increase in the maximum size
>> 1755 of lowmem (up to 3GB). If unsure, say 'N' here.
>> 1756
>> 1757 config CPU_MIPS32_R5_FEATURES
>> 1758 bool "MIPS32 Release 5 Features"
>> 1759 depends on SYS_HAS_CPU_MIPS32_R5
>> 1760 depends on CPU_MIPS32_R2
>> 1761 help
>> 1762 Choose this option to build a kernel for release 2 or later of the
>> 1763 MIPS32 architecture including features from release 5 such as
>> 1764 support for Extended Physical Addressing (XPA).
>> 1765
>> 1766 config CPU_MIPS32_R5_XPA
>> 1767 bool "Extended Physical Addressing (XPA)"
>> 1768 depends on CPU_MIPS32_R5_FEATURES
>> 1769 depends on !EVA
>> 1770 depends on !PAGE_SIZE_4KB
>> 1771 depends on SYS_SUPPORTS_HIGHMEM
>> 1772 select XPA
>> 1773 select HIGHMEM
>> 1774 select PHYS_ADDR_T_64BIT
>> 1775 default n
>> 1776 help
>> 1777 Choose this option if you want to enable the Extended Physical
>> 1778 Addressing (XPA) on your MIPS32 core (such as P5600 series). The
>> 1779 benefit is to increase physical addressing equal to or greater
>> 1780 than 40 bits. Note that this has the side effect of turning on
>> 1781 64-bit addressing which in turn makes the PTEs 64-bit in size.
>> 1782 If unsure, say 'N' here.
981 1783
982 config ARM64_ERRATUM_2038923 !! 1784 if CPU_LOONGSON2F
983 bool "Cortex-A510: 2038923: workaround !! 1785 config CPU_NOP_WORKAROUNDS
984 depends on CORESIGHT_TRBE !! 1786 bool
985 default y <<
986 help <<
987 This option adds the workaround for <<
988 <<
989 Affected Cortex-A510 core might caus <<
990 prohibited within the CPU. As a resu <<
991 might be corrupted. This happens aft <<
992 TRBLIMITR_EL1.E, followed by just a <<
993 execution changes from a context, in <<
994 isn't, or vice versa. In these menti <<
995 is prohibited is inconsistent betwee <<
996 the trace buffer state might be corr <<
997 <<
998 Work around this in the driver by pr <<
999 trace is prohibited or not based on <<
1000 change to TRBLIMITR_EL1.E with at l <<
1001 two ISB instructions if no ERET is <<
1002 1787
1003 If unsure, say Y. !! 1788 config CPU_JUMP_WORKAROUNDS
>> 1789 bool
1004 1790
1005 config ARM64_ERRATUM_1902691 !! 1791 config CPU_LOONGSON2F_WORKAROUNDS
1006 bool "Cortex-A510: 1902691: workaroun !! 1792 bool "Loongson 2F Workarounds"
1007 depends on CORESIGHT_TRBE <<
1008 default y 1793 default y
>> 1794 select CPU_NOP_WORKAROUNDS
>> 1795 select CPU_JUMP_WORKAROUNDS
1009 help 1796 help
1010 This option adds the workaround for !! 1797 Loongson 2F01 / 2F02 processors have the NOP & JUMP issues which
>> 1798 require workarounds. Without workarounds the system may hang
>> 1799 unexpectedly. For more information please refer to the gas
>> 1800 -mfix-loongson2f-nop and -mfix-loongson2f-jump options.
>> 1801
>> 1802 Loongson 2F03 and later have fixed these issues and no workarounds
>> 1803 are needed. The workarounds have no significant side effect on them
>> 1804 but may decrease the performance of the system so this option should
>> 1805 be disabled unless the kernel is intended to be run on 2F01 or 2F02
>> 1806 systems.
1011 1807
1012 Affected Cortex-A510 core might cau !! 1808 If unsure, please say Y.
1013 into the memory. Effectively TRBE i !! 1809 endif # CPU_LOONGSON2F
1014 trace data. <<
1015 1810
1016 Work around this problem in the dri !! 1811 config SYS_SUPPORTS_ZBOOT
1017 affected cpus. The firmware must ha !! 1812 bool
1018 on such implementations. This will !! 1813 select HAVE_KERNEL_GZIP
1019 do this already. !! 1814 select HAVE_KERNEL_BZIP2
>> 1815 select HAVE_KERNEL_LZ4
>> 1816 select HAVE_KERNEL_LZMA
>> 1817 select HAVE_KERNEL_LZO
>> 1818 select HAVE_KERNEL_XZ
1020 1819
1021 If unsure, say Y. !! 1820 config SYS_SUPPORTS_ZBOOT_UART16550
>> 1821 bool
>> 1822 select SYS_SUPPORTS_ZBOOT
1022 1823
1023 config ARM64_ERRATUM_2457168 !! 1824 config SYS_SUPPORTS_ZBOOT_UART_PROM
1024 bool "Cortex-A510: 2457168: workaroun !! 1825 bool
1025 depends on ARM64_AMU_EXTN !! 1826 select SYS_SUPPORTS_ZBOOT
1026 default y <<
1027 help <<
1028 This option adds the workaround for <<
1029 1827
1030 The AMU counter AMEVCNTR01 (constan !! 1828 config CPU_LOONGSON2
1031 as the system counter. On affected !! 1829 bool
1032 incorrectly giving a significantly !! 1830 select CPU_SUPPORTS_32BIT_KERNEL
>> 1831 select CPU_SUPPORTS_64BIT_KERNEL
>> 1832 select CPU_SUPPORTS_HIGHMEM
>> 1833 select CPU_SUPPORTS_HUGEPAGES
1033 1834
1034 Work around this problem by returni !! 1835 config CPU_LOONGSON1
1035 key locations that results in disab !! 1836 bool
1036 is the same to firmware disabling a !! 1837 select CPU_MIPS32
>> 1838 select CPU_MIPSR2
>> 1839 select CPU_HAS_PREFETCH
>> 1840 select CPU_SUPPORTS_32BIT_KERNEL
>> 1841 select CPU_SUPPORTS_HIGHMEM
>> 1842 select CPU_SUPPORTS_CPUFREQ
1037 1843
1038 If unsure, say Y. !! 1844 config CPU_BMIPS32_3300
>> 1845 select SMP_UP if SMP
>> 1846 bool
1039 1847
1040 config ARM64_ERRATUM_2645198 !! 1848 config CPU_BMIPS4350
1041 bool "Cortex-A715: 2645198: Workaroun !! 1849 bool
1042 default y !! 1850 select SYS_SUPPORTS_SMP
1043 help !! 1851 select SYS_SUPPORTS_HOTPLUG_CPU
1044 This option adds the workaround for <<
1045 1852
1046 If a Cortex-A715 cpu sees a page ma !! 1853 config CPU_BMIPS4380
1047 to non-executable, it may corrupt t !! 1854 bool
1048 next instruction abort caused by pe !! 1855 select MIPS_L1_CACHE_SHIFT_6
>> 1856 select SYS_SUPPORTS_SMP
>> 1857 select SYS_SUPPORTS_HOTPLUG_CPU
>> 1858 select CPU_HAS_RIXI
1049 1859
1050 Only user-space does executable to !! 1860 config CPU_BMIPS5000
1051 mprotect() system call. Workaround !! 1861 bool
1052 TLB invalidation, for all changes t !! 1862 select MIPS_CPU_SCACHE
>> 1863 select MIPS_L1_CACHE_SHIFT_7
>> 1864 select SYS_SUPPORTS_SMP
>> 1865 select SYS_SUPPORTS_HOTPLUG_CPU
>> 1866 select CPU_HAS_RIXI
1053 1867
1054 If unsure, say Y. !! 1868 config SYS_HAS_CPU_LOONGSON3
>> 1869 bool
>> 1870 select CPU_SUPPORTS_CPUFREQ
>> 1871 select CPU_HAS_RIXI
1055 1872
1056 config ARM64_WORKAROUND_SPECULATIVE_UNPRIV_LO !! 1873 config SYS_HAS_CPU_LOONGSON2E
1057 bool 1874 bool
1058 1875
1059 config ARM64_ERRATUM_2966298 !! 1876 config SYS_HAS_CPU_LOONGSON2F
1060 bool "Cortex-A520: 2966298: workaroun !! 1877 bool
1061 select ARM64_WORKAROUND_SPECULATIVE_U !! 1878 select CPU_SUPPORTS_CPUFREQ
1062 default y !! 1879 select CPU_SUPPORTS_ADDRWINCFG if 64BIT
1063 help !! 1880 select CPU_SUPPORTS_UNCACHED_ACCELERATED
1064 This option adds the workaround for <<
1065 1881
1066 On an affected Cortex-A520 core, a !! 1882 config SYS_HAS_CPU_LOONGSON1B
1067 load might leak data from a privile !! 1883 bool
1068 1884
1069 Work around this problem by executi !! 1885 config SYS_HAS_CPU_LOONGSON1C
>> 1886 bool
1070 1887
1071 If unsure, say Y. !! 1888 config SYS_HAS_CPU_MIPS32_R1
>> 1889 bool
1072 1890
1073 config ARM64_ERRATUM_3117295 !! 1891 config SYS_HAS_CPU_MIPS32_R2
1074 bool "Cortex-A510: 3117295: workaroun !! 1892 bool
1075 select ARM64_WORKAROUND_SPECULATIVE_U <<
1076 default y <<
1077 help <<
1078 This option adds the workaround for <<
1079 1893
1080 On an affected Cortex-A510 core, a !! 1894 config SYS_HAS_CPU_MIPS32_R3_5
1081 load might leak data from a privile !! 1895 bool
1082 1896
1083 Work around this problem by executi !! 1897 config SYS_HAS_CPU_MIPS32_R5
>> 1898 bool
1084 1899
1085 If unsure, say Y. !! 1900 config SYS_HAS_CPU_MIPS32_R6
>> 1901 bool
1086 1902
1087 config ARM64_ERRATUM_3194386 !! 1903 config SYS_HAS_CPU_MIPS64_R1
1088 bool "Cortex-*/Neoverse-*: workaround !! 1904 bool
1089 default y <<
1090 help <<
1091 This option adds the workaround for <<
1092 1905
1093 * ARM Cortex-A76 erratum 3324349 !! 1906 config SYS_HAS_CPU_MIPS64_R2
1094 * ARM Cortex-A77 erratum 3324348 !! 1907 bool
1095 * ARM Cortex-A78 erratum 3324344 <<
1096 * ARM Cortex-A78C erratum 3324346 <<
1097 * ARM Cortex-A78C erratum 3324347 <<
1098 * ARM Cortex-A710 erratam 3324338 <<
1099 * ARM Cortex-A715 errartum 3456084 <<
1100 * ARM Cortex-A720 erratum 3456091 <<
1101 * ARM Cortex-A725 erratum 3456106 <<
1102 * ARM Cortex-X1 erratum 3324344 <<
1103 * ARM Cortex-X1C erratum 3324346 <<
1104 * ARM Cortex-X2 erratum 3324338 <<
1105 * ARM Cortex-X3 erratum 3324335 <<
1106 * ARM Cortex-X4 erratum 3194386 <<
1107 * ARM Cortex-X925 erratum 3324334 <<
1108 * ARM Neoverse-N1 erratum 3324349 <<
1109 * ARM Neoverse N2 erratum 3324339 <<
1110 * ARM Neoverse-N3 erratum 3456111 <<
1111 * ARM Neoverse-V1 erratum 3324341 <<
1112 * ARM Neoverse V2 erratum 3324336 <<
1113 * ARM Neoverse-V3 erratum 3312417 <<
1114 <<
1115 On affected cores "MSR SSBS, #0" in <<
1116 subsequent speculative instructions <<
1117 speculative store bypassing. <<
1118 <<
1119 Work around this problem by placing <<
1120 Instruction Synchronization Barrier <<
1121 SSBS. The presence of the SSBS spec <<
1122 from hwcaps and EL0 reads of ID_AA6 <<
1123 will use the PR_SPEC_STORE_BYPASS p <<
1124 1908
1125 If unsure, say Y. !! 1909 config SYS_HAS_CPU_MIPS64_R6
>> 1910 bool
1126 1911
1127 config CAVIUM_ERRATUM_22375 !! 1912 config SYS_HAS_CPU_R3000
1128 bool "Cavium erratum 22375, 24313" !! 1913 bool
1129 default y <<
1130 help <<
1131 Enable workaround for errata 22375 <<
1132 1914
1133 This implements two gicv3-its errat !! 1915 config SYS_HAS_CPU_TX39XX
1134 with a small impact affecting only !! 1916 bool
1135 1917
1136 erratum 22375: only alloc 8MB tab !! 1918 config SYS_HAS_CPU_VR41XX
1137 erratum 24313: ignore memory acce !! 1919 bool
1138 1920
1139 The fixes are in ITS initialization !! 1921 config SYS_HAS_CPU_R4300
1140 type and table size provided by the !! 1922 bool
1141 1923
1142 If unsure, say Y. !! 1924 config SYS_HAS_CPU_R4X00
>> 1925 bool
1143 1926
1144 config CAVIUM_ERRATUM_23144 !! 1927 config SYS_HAS_CPU_TX49XX
1145 bool "Cavium erratum 23144: ITS SYNC !! 1928 bool
1146 depends on NUMA <<
1147 default y <<
1148 help <<
1149 ITS SYNC command hang for cross nod <<
1150 1929
1151 If unsure, say Y. !! 1930 config SYS_HAS_CPU_R5000
>> 1931 bool
1152 1932
1153 config CAVIUM_ERRATUM_23154 !! 1933 config SYS_HAS_CPU_R5432
1154 bool "Cavium errata 23154 and 38545: !! 1934 bool
1155 default y <<
1156 help <<
1157 The ThunderX GICv3 implementation r <<
1158 reading the IAR status to ensure da <<
1159 (access to icc_iar1_el1 is not sync <<
1160 1935
1161 It also suffers from erratum 38545 !! 1936 config SYS_HAS_CPU_R5500
1162 OcteonTX and OcteonTX2), resulting !! 1937 bool
1163 spuriously presented to the CPU int <<
1164 1938
1165 If unsure, say Y. !! 1939 config SYS_HAS_CPU_NEVADA
>> 1940 bool
1166 1941
1167 config CAVIUM_ERRATUM_27456 !! 1942 config SYS_HAS_CPU_R8000
1168 bool "Cavium erratum 27456: Broadcast !! 1943 bool
1169 default y <<
1170 help <<
1171 On ThunderX T88 pass 1.x through 2. <<
1172 instructions may cause the icache t <<
1173 contains data for a non-current ASI <<
1174 invalidate the icache when changing <<
1175 1944
1176 If unsure, say Y. !! 1945 config SYS_HAS_CPU_R10000
>> 1946 bool
1177 1947
1178 config CAVIUM_ERRATUM_30115 !! 1948 config SYS_HAS_CPU_RM7000
1179 bool "Cavium erratum 30115: Guest may !! 1949 bool
1180 default y <<
1181 help <<
1182 On ThunderX T88 pass 1.x through 2. <<
1183 1.2, and T83 Pass 1.0, KVM guest ex <<
1184 interrupts in host. Trapping both G <<
1185 accesses sidesteps the issue. <<
1186 1950
1187 If unsure, say Y. !! 1951 config SYS_HAS_CPU_SB1
>> 1952 bool
1188 1953
1189 config CAVIUM_TX2_ERRATUM_219 !! 1954 config SYS_HAS_CPU_CAVIUM_OCTEON
1190 bool "Cavium ThunderX2 erratum 219: P !! 1955 bool
1191 default y <<
1192 help <<
1193 On Cavium ThunderX2, a load, store <<
1194 TTBR update and the corresponding c <<
1195 cause a spurious Data Abort to be d <<
1196 the CPU core. <<
1197 <<
1198 Work around the issue by avoiding t <<
1199 trapping KVM guest TTBRx_EL1 writes <<
1200 trap handler performs the correspon <<
1201 instruction and ensures context syn <<
1202 exception return. <<
1203 1956
1204 If unsure, say Y. !! 1957 config SYS_HAS_CPU_BMIPS
>> 1958 bool
1205 1959
1206 config FUJITSU_ERRATUM_010001 !! 1960 config SYS_HAS_CPU_BMIPS32_3300
1207 bool "Fujitsu-A64FX erratum E#010001: !! 1961 bool
1208 default y !! 1962 select SYS_HAS_CPU_BMIPS
1209 help <<
1210 This option adds a workaround for F <<
1211 On some variants of the Fujitsu-A64 <<
1212 accesses may cause undefined fault <<
1213 This fault occurs under a specific <<
1214 load/store instruction performs an <<
1215 case-1 TTBR0_EL1 with TCR_EL1.NFD0 <<
1216 case-2 TTBR0_EL2 with TCR_EL2.NFD0 <<
1217 case-3 TTBR1_EL1 with TCR_EL1.NFD1 <<
1218 case-4 TTBR1_EL2 with TCR_EL2.NFD1 <<
1219 1963
1220 The workaround is to ensure these b !! 1964 config SYS_HAS_CPU_BMIPS4350
1221 The workaround only affects the Fuj !! 1965 bool
>> 1966 select SYS_HAS_CPU_BMIPS
1222 1967
1223 If unsure, say Y. !! 1968 config SYS_HAS_CPU_BMIPS4380
>> 1969 bool
>> 1970 select SYS_HAS_CPU_BMIPS
1224 1971
1225 config HISILICON_ERRATUM_161600802 !! 1972 config SYS_HAS_CPU_BMIPS5000
1226 bool "Hip07 161600802: Erroneous redi !! 1973 bool
1227 default y !! 1974 select SYS_HAS_CPU_BMIPS
1228 help <<
1229 The HiSilicon Hip07 SoC uses the wr <<
1230 when issued ITS commands such as VM <<
1231 a 128kB offset to be applied to the <<
1232 1975
1233 If unsure, say Y. !! 1976 config SYS_HAS_CPU_XLR
>> 1977 bool
1234 1978
1235 config QCOM_FALKOR_ERRATUM_1003 !! 1979 config SYS_HAS_CPU_XLP
1236 bool "Falkor E1003: Incorrect transla !! 1980 bool
1237 default y <<
1238 help <<
1239 On Falkor v1, an incorrect ASID may <<
1240 and BADDR are changed together in T <<
1241 in TTBR1_EL1, this situation only o <<
1242 then only for entries in the walk c <<
1243 is unchanged. Work around the errat <<
1244 entries for the trampoline before e <<
1245 1981
1246 config QCOM_FALKOR_ERRATUM_1009 !! 1982 config MIPS_MALTA_PM
1247 bool "Falkor E1009: Prematurely compl !! 1983 depends on MIPS_MALTA
>> 1984 depends on PCI
>> 1985 bool
1248 default y 1986 default y
1249 select ARM64_WORKAROUND_REPEAT_TLBI <<
1250 help <<
1251 On Falkor v1, the CPU may premature <<
1252 TLBI xxIS invalidate maintenance op <<
1253 one more time to fix the issue. <<
1254 1987
1255 If unsure, say Y. !! 1988 #
>> 1989 # CPU may reorder R->R, R->W, W->R, W->W
>> 1990 # Reordering beyond LL and SC is handled in WEAK_REORDERING_BEYOND_LLSC
>> 1991 #
>> 1992 config WEAK_ORDERING
>> 1993 bool
1256 1994
1257 config QCOM_QDF2400_ERRATUM_0065 !! 1995 #
1258 bool "QDF2400 E0065: Incorrect GITS_T !! 1996 # CPU may reorder reads and writes beyond LL/SC
1259 default y !! 1997 # CPU may reorder R->LL, R->LL, W->LL, W->LL, R->SC, R->SC, W->SC, W->SC
1260 help !! 1998 #
1261 On Qualcomm Datacenter Technologies !! 1999 config WEAK_REORDERING_BEYOND_LLSC
1262 ITE size incorrectly. The GITS_TYPE !! 2000 bool
1263 been indicated as 16Bytes (0xf), no !! 2001 endmenu
1264 2002
1265 If unsure, say Y. !! 2003 #
>> 2004 # These two indicate any level of the MIPS32 and MIPS64 architecture
>> 2005 #
>> 2006 config CPU_MIPS32
>> 2007 bool
>> 2008 default y if CPU_MIPS32_R1 || CPU_MIPS32_R2 || CPU_MIPS32_R6
1266 2009
1267 config QCOM_FALKOR_ERRATUM_E1041 !! 2010 config CPU_MIPS64
1268 bool "Falkor E1041: Speculative instr !! 2011 bool
1269 default y !! 2012 default y if CPU_MIPS64_R1 || CPU_MIPS64_R2 || CPU_MIPS64_R6
1270 help <<
1271 Falkor CPU may speculatively fetch <<
1272 memory location when MMU translatio <<
1273 to SCTLR_ELn[M]=0. Prefix an ISB in <<
1274 2013
1275 If unsure, say Y. !! 2014 #
>> 2015 # These two indicate the revision of the architecture, either Release 1 or Release 2
>> 2016 #
>> 2017 config CPU_MIPSR1
>> 2018 bool
>> 2019 default y if CPU_MIPS32_R1 || CPU_MIPS64_R1
1276 2020
1277 config NVIDIA_CARMEL_CNP_ERRATUM !! 2021 config CPU_MIPSR2
1278 bool "NVIDIA Carmel CNP: CNP on Carme !! 2022 bool
1279 default y !! 2023 default y if CPU_MIPS32_R2 || CPU_MIPS64_R2 || CPU_CAVIUM_OCTEON
1280 help !! 2024 select CPU_HAS_RIXI
1281 If CNP is enabled on Carmel cores, !! 2025 select MIPS_SPRAM
1282 invalidate shared TLB entries insta <<
1283 on standard ARM cores. <<
1284 2026
1285 If unsure, say Y. !! 2027 config CPU_MIPSR6
>> 2028 bool
>> 2029 default y if CPU_MIPS32_R6 || CPU_MIPS64_R6
>> 2030 select CPU_HAS_RIXI
>> 2031 select HAVE_ARCH_BITREVERSE
>> 2032 select MIPS_ASID_BITS_VARIABLE
>> 2033 select MIPS_CRC_SUPPORT
>> 2034 select MIPS_SPRAM
1286 2035
1287 config ROCKCHIP_ERRATUM_3588001 !! 2036 config EVA
1288 bool "Rockchip 3588001: GIC600 can no !! 2037 bool
1289 default y <<
1290 help <<
1291 The Rockchip RK3588 GIC600 SoC inte <<
1292 This means, that its sharability fe <<
1293 is supported by the IP itself. <<
1294 2038
1295 If unsure, say Y. !! 2039 config XPA
>> 2040 bool
1296 2041
1297 config SOCIONEXT_SYNQUACER_PREITS !! 2042 config SYS_SUPPORTS_32BIT_KERNEL
1298 bool "Socionext Synquacer: Workaround !! 2043 bool
1299 default y !! 2044 config SYS_SUPPORTS_64BIT_KERNEL
1300 help !! 2045 bool
1301 Socionext Synquacer SoCs implement !! 2046 config CPU_SUPPORTS_32BIT_KERNEL
1302 MSI doorbell writes with non-zero v !! 2047 bool
>> 2048 config CPU_SUPPORTS_64BIT_KERNEL
>> 2049 bool
>> 2050 config CPU_SUPPORTS_CPUFREQ
>> 2051 bool
>> 2052 config CPU_SUPPORTS_ADDRWINCFG
>> 2053 bool
>> 2054 config CPU_SUPPORTS_HUGEPAGES
>> 2055 bool
>> 2056 config CPU_SUPPORTS_UNCACHED_ACCELERATED
>> 2057 bool
>> 2058 config MIPS_PGD_C0_CONTEXT
>> 2059 bool
>> 2060 default y if 64BIT && (CPU_MIPSR2 || CPU_MIPSR6) && !CPU_XLP
1303 2061
1304 If unsure, say Y. !! 2062 #
>> 2063 # Set to y for ptrace access to watch registers.
>> 2064 #
>> 2065 config HARDWARE_WATCHPOINTS
>> 2066 bool
>> 2067 default y if CPU_MIPSR1 || CPU_MIPSR2 || CPU_MIPSR6
1305 2068
1306 endmenu # "ARM errata workarounds via the alt !! 2069 menu "Kernel type"
1307 2070
1308 choice 2071 choice
1309 prompt "Page size" !! 2072 prompt "Kernel code model"
1310 default ARM64_4K_PAGES <<
1311 help 2073 help
1312 Page size (translation granule) con !! 2074 You should only select this option if you have a workload that
1313 !! 2075 actually benefits from 64-bit processing or if your machine has
1314 config ARM64_4K_PAGES !! 2076 large memory. You will only be presented a single option in this
1315 bool "4KB" !! 2077 menu if your system does not support both 32-bit and 64-bit kernels.
1316 select HAVE_PAGE_SIZE_4KB !! 2078
1317 help !! 2079 config 32BIT
1318 This feature enables 4KB pages supp !! 2080 bool "32-bit kernel"
1319 !! 2081 depends on CPU_SUPPORTS_32BIT_KERNEL && SYS_SUPPORTS_32BIT_KERNEL
1320 config ARM64_16K_PAGES !! 2082 select TRAD_SIGNALS
1321 bool "16KB" <<
1322 select HAVE_PAGE_SIZE_16KB <<
1323 help 2083 help
1324 The system will use 16KB pages supp !! 2084 Select this option if you want to build a 32-bit kernel.
1325 requires applications compiled with <<
1326 aligned segments. <<
1327 2085
1328 config ARM64_64K_PAGES !! 2086 config 64BIT
1329 bool "64KB" !! 2087 bool "64-bit kernel"
1330 select HAVE_PAGE_SIZE_64KB !! 2088 depends on CPU_SUPPORTS_64BIT_KERNEL && SYS_SUPPORTS_64BIT_KERNEL
1331 help 2089 help
1332 This feature enables 64KB pages sup !! 2090 Select this option if you want to build a 64-bit kernel.
1333 allowing only two levels of page ta <<
1334 look-up. AArch32 emulation requires <<
1335 with 64K aligned segments. <<
1336 2091
1337 endchoice 2092 endchoice
1338 2093
>> 2094 config KVM_GUEST
>> 2095 bool "KVM Guest Kernel"
>> 2096 depends on BROKEN_ON_SMP
>> 2097 help
>> 2098 Select this option if building a guest kernel for KVM (Trap & Emulate)
>> 2099 mode.
>> 2100
>> 2101 config KVM_GUEST_TIMER_FREQ
>> 2102 int "Count/Compare Timer Frequency (MHz)"
>> 2103 depends on KVM_GUEST
>> 2104 default 100
>> 2105 help
>> 2106 Set this to non-zero if building a guest kernel for KVM to skip RTC
>> 2107 emulation when determining guest CPU Frequency. Instead, the guest's
>> 2108 timer frequency is specified directly.
>> 2109
>> 2110 config MIPS_VA_BITS_48
>> 2111 bool "48 bits virtual memory"
>> 2112 depends on 64BIT
>> 2113 help
>> 2114 Support a maximum at least 48 bits of application virtual
>> 2115 memory. Default is 40 bits or less, depending on the CPU.
>> 2116 For page sizes 16k and above, this option results in a small
>> 2117 memory overhead for page tables. For 4k page size, a fourth
>> 2118 level of page tables is added which imposes both a memory
>> 2119 overhead as well as slower TLB fault handling.
>> 2120
>> 2121 If unsure, say N.
>> 2122
1339 choice 2123 choice
1340 prompt "Virtual address space size" !! 2124 prompt "Kernel page size"
1341 default ARM64_VA_BITS_52 !! 2125 default PAGE_SIZE_4KB
1342 help <<
1343 Allows choosing one of multiple pos <<
1344 space sizes. The level of translati <<
1345 a combination of page size and virt <<
1346 <<
1347 config ARM64_VA_BITS_36 <<
1348 bool "36-bit" if EXPERT <<
1349 depends on PAGE_SIZE_16KB <<
1350 <<
1351 config ARM64_VA_BITS_39 <<
1352 bool "39-bit" <<
1353 depends on PAGE_SIZE_4KB <<
1354 <<
1355 config ARM64_VA_BITS_42 <<
1356 bool "42-bit" <<
1357 depends on PAGE_SIZE_64KB <<
1358 <<
1359 config ARM64_VA_BITS_47 <<
1360 bool "47-bit" <<
1361 depends on PAGE_SIZE_16KB <<
1362 <<
1363 config ARM64_VA_BITS_48 <<
1364 bool "48-bit" <<
1365 <<
1366 config ARM64_VA_BITS_52 <<
1367 bool "52-bit" <<
1368 depends on ARM64_PAN || !ARM64_SW_TTB <<
1369 help <<
1370 Enable 52-bit virtual addressing fo <<
1371 requested via a hint to mmap(). The <<
1372 virtual addresses for its own mappi <<
1373 this feature is available, otherwis <<
1374 <<
1375 NOTE: Enabling 52-bit virtual addre <<
1376 ARMv8.3 Pointer Authentication will <<
1377 reduced from 7 bits to 3 bits, whic <<
1378 impact on its susceptibility to bru <<
1379 2126
1380 If unsure, select 48-bit virtual ad !! 2127 config PAGE_SIZE_4KB
>> 2128 bool "4kB"
>> 2129 depends on !CPU_LOONGSON2 && !CPU_LOONGSON3
>> 2130 help
>> 2131 This option select the standard 4kB Linux page size. On some
>> 2132 R3000-family processors this is the only available page size. Using
>> 2133 4kB page size will minimize memory consumption and is therefore
>> 2134 recommended for low memory systems.
>> 2135
>> 2136 config PAGE_SIZE_8KB
>> 2137 bool "8kB"
>> 2138 depends on CPU_R8000 || CPU_CAVIUM_OCTEON
>> 2139 depends on !MIPS_VA_BITS_48
>> 2140 help
>> 2141 Using 8kB page size will result in higher performance kernel at
>> 2142 the price of higher memory consumption. This option is available
>> 2143 only on R8000 and cnMIPS processors. Note that you will need a
>> 2144 suitable Linux distribution to support this.
>> 2145
>> 2146 config PAGE_SIZE_16KB
>> 2147 bool "16kB"
>> 2148 depends on !CPU_R3000 && !CPU_TX39XX
>> 2149 help
>> 2150 Using 16kB page size will result in higher performance kernel at
>> 2151 the price of higher memory consumption. This option is available on
>> 2152 all non-R3000 family processors. Note that you will need a suitable
>> 2153 Linux distribution to support this.
>> 2154
>> 2155 config PAGE_SIZE_32KB
>> 2156 bool "32kB"
>> 2157 depends on CPU_CAVIUM_OCTEON
>> 2158 depends on !MIPS_VA_BITS_48
>> 2159 help
>> 2160 Using 32kB page size will result in higher performance kernel at
>> 2161 the price of higher memory consumption. This option is available
>> 2162 only on cnMIPS cores. Note that you will need a suitable Linux
>> 2163 distribution to support this.
>> 2164
>> 2165 config PAGE_SIZE_64KB
>> 2166 bool "64kB"
>> 2167 depends on !CPU_R3000 && !CPU_TX39XX
>> 2168 help
>> 2169 Using 64kB page size will result in higher performance kernel at
>> 2170 the price of higher memory consumption. This option is available on
>> 2171 all non-R3000 family processor. Not that at the time of this
>> 2172 writing this option is still high experimental.
1381 2173
1382 endchoice 2174 endchoice
1383 2175
1384 config ARM64_FORCE_52BIT !! 2176 config FORCE_MAX_ZONEORDER
1385 bool "Force 52-bit virtual addresses !! 2177 int "Maximum zone order"
1386 depends on ARM64_VA_BITS_52 && EXPERT !! 2178 range 14 64 if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_64KB
1387 help !! 2179 default "14" if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_64KB
1388 For systems with 52-bit userspace V !! 2180 range 13 64 if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_32KB
1389 to maintain compatibility with olde !! 2181 default "13" if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_32KB
1390 unless a hint is supplied to mmap. !! 2182 range 12 64 if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_16KB
1391 !! 2183 default "12" if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_16KB
1392 This configuration option disables !! 2184 range 11 64
1393 forces all userspace addresses to b !! 2185 default "11"
1394 should only enable this configurati !! 2186 help
1395 memory management code. If unsure s !! 2187 The kernel memory allocator divides physically contiguous memory
>> 2188 blocks into "zones", where each zone is a power of two number of
>> 2189 pages. This option selects the largest power of two that the kernel
>> 2190 keeps in the memory allocator. If you need to allocate very large
>> 2191 blocks of physically contiguous memory, then you may need to
>> 2192 increase this value.
1396 2193
1397 config ARM64_VA_BITS !! 2194 This config option is actually maximum order plus one. For example,
1398 int !! 2195 a value of 11 means that the largest free memory block is 2^10 pages.
1399 default 36 if ARM64_VA_BITS_36 <<
1400 default 39 if ARM64_VA_BITS_39 <<
1401 default 42 if ARM64_VA_BITS_42 <<
1402 default 47 if ARM64_VA_BITS_47 <<
1403 default 48 if ARM64_VA_BITS_48 <<
1404 default 52 if ARM64_VA_BITS_52 <<
1405 2196
1406 choice !! 2197 The page size is not necessarily 4KB. Keep this in mind
1407 prompt "Physical address space size" !! 2198 when choosing a value for this option.
1408 default ARM64_PA_BITS_48 <<
1409 help <<
1410 Choose the maximum physical address <<
1411 support. <<
1412 2199
1413 config ARM64_PA_BITS_48 !! 2200 config BOARD_SCACHE
1414 bool "48-bit" !! 2201 bool
1415 depends on ARM64_64K_PAGES || !ARM64_ <<
1416 <<
1417 config ARM64_PA_BITS_52 <<
1418 bool "52-bit" <<
1419 depends on ARM64_64K_PAGES || ARM64_V <<
1420 depends on ARM64_PAN || !ARM64_SW_TTB <<
1421 help <<
1422 Enable support for a 52-bit physica <<
1423 part of the ARMv8.2-LPA extension. <<
1424 <<
1425 With this enabled, the kernel will <<
1426 do not support ARMv8.2-LPA, but wit <<
1427 minor performance overhead). <<
1428 2202
1429 endchoice !! 2203 config IP22_CPU_SCACHE
>> 2204 bool
>> 2205 select BOARD_SCACHE
1430 2206
1431 config ARM64_PA_BITS !! 2207 #
1432 int !! 2208 # Support for a MIPS32 / MIPS64 style S-caches
1433 default 48 if ARM64_PA_BITS_48 !! 2209 #
1434 default 52 if ARM64_PA_BITS_52 !! 2210 config MIPS_CPU_SCACHE
>> 2211 bool
>> 2212 select BOARD_SCACHE
1435 2213
1436 config ARM64_LPA2 !! 2214 config R5000_CPU_SCACHE
1437 def_bool y !! 2215 bool
1438 depends on ARM64_PA_BITS_52 && !ARM64 !! 2216 select BOARD_SCACHE
1439 2217
1440 choice !! 2218 config RM7000_CPU_SCACHE
1441 prompt "Endianness" !! 2219 bool
1442 default CPU_LITTLE_ENDIAN !! 2220 select BOARD_SCACHE
1443 help <<
1444 Select the endianness of data acces <<
1445 applications will need to be compil <<
1446 that is selected here. <<
1447 2221
1448 config CPU_BIG_ENDIAN !! 2222 config SIBYTE_DMA_PAGEOPS
1449 bool "Build big-endian kernel" !! 2223 bool "Use DMA to clear/copy pages"
1450 # https://github.com/llvm/llvm-projec !! 2224 depends on CPU_SB1
1451 depends on AS_IS_GNU || AS_VERSION >= <<
1452 help 2225 help
1453 Say Y if you plan on running a kern !! 2226 Instead of using the CPU to zero and copy pages, use a Data Mover
>> 2227 channel. These DMA channels are otherwise unused by the standard
>> 2228 SiByte Linux port. Seems to give a small performance benefit.
1454 2229
1455 config CPU_LITTLE_ENDIAN !! 2230 config CPU_HAS_PREFETCH
1456 bool "Build little-endian kernel" !! 2231 bool
1457 help <<
1458 Say Y if you plan on running a kern <<
1459 This is usually the case for distri <<
1460 2232
1461 endchoice !! 2233 config CPU_GENERIC_DUMP_TLB
>> 2234 bool
>> 2235 default y if !(CPU_R3000 || CPU_R8000 || CPU_TX39XX)
1462 2236
1463 config SCHED_MC !! 2237 config CPU_R4K_FPU
1464 bool "Multi-core scheduler support" !! 2238 bool
1465 help !! 2239 default y if !(CPU_R3000 || CPU_TX39XX)
1466 Multi-core scheduler support improv <<
1467 making when dealing with multi-core <<
1468 increased overhead in some places. <<
1469 2240
1470 config SCHED_CLUSTER !! 2241 config CPU_R4K_CACHE_TLB
1471 bool "Cluster scheduler support" !! 2242 bool
1472 help !! 2243 default y if !(CPU_R3000 || CPU_R8000 || CPU_SB1 || CPU_TX39XX || CPU_CAVIUM_OCTEON)
1473 Cluster scheduler support improves !! 2244
1474 making when dealing with machines t !! 2245 config MIPS_MT_SMP
1475 Cluster usually means a couple of C !! 2246 bool "MIPS MT SMP support (1 TC on each available VPE)"
1476 by sharing mid-level caches, last-l !! 2247 default y
1477 busses. !! 2248 depends on SYS_SUPPORTS_MULTITHREADING && !CPU_MIPSR6 && !CPU_MICROMIPS
>> 2249 select CPU_MIPSR2_IRQ_VI
>> 2250 select CPU_MIPSR2_IRQ_EI
>> 2251 select SYNC_R4K
>> 2252 select MIPS_MT
>> 2253 select SMP
>> 2254 select SMP_UP
>> 2255 select SYS_SUPPORTS_SMP
>> 2256 select SYS_SUPPORTS_SCHED_SMT
>> 2257 select MIPS_PERF_SHARED_TC_COUNTERS
>> 2258 help
>> 2259 This is a kernel model which is known as SMVP. This is supported
>> 2260 on cores with the MT ASE and uses the available VPEs to implement
>> 2261 virtual processors which supports SMP. This is equivalent to the
>> 2262 Intel Hyperthreading feature. For further information go to
>> 2263 <http://www.imgtec.com/mips/mips-multithreading.asp>.
>> 2264
>> 2265 config MIPS_MT
>> 2266 bool
1478 2267
1479 config SCHED_SMT 2268 config SCHED_SMT
1480 bool "SMT scheduler support" !! 2269 bool "SMT (multithreading) scheduler support"
>> 2270 depends on SYS_SUPPORTS_SCHED_SMT
>> 2271 default n
1481 help 2272 help
1482 Improves the CPU scheduler's decisi !! 2273 SMT scheduler support improves the CPU scheduler's decision making
1483 MultiThreading at a cost of slightl !! 2274 when dealing with MIPS MT enabled cores at a cost of slightly
1484 places. If unsure say N here. !! 2275 increased overhead in some places. If unsure say N here.
1485 2276
1486 config NR_CPUS !! 2277 config SYS_SUPPORTS_SCHED_SMT
1487 int "Maximum number of CPUs (2-4096)" !! 2278 bool
1488 range 2 4096 <<
1489 default "512" <<
1490 2279
1491 config HOTPLUG_CPU !! 2280 config SYS_SUPPORTS_MULTITHREADING
1492 bool "Support for hot-pluggable CPUs" !! 2281 bool
1493 select GENERIC_IRQ_MIGRATION <<
1494 help <<
1495 Say Y here to experiment with turni <<
1496 can be controlled through /sys/devi <<
1497 2282
1498 # Common NUMA Features !! 2283 config MIPS_MT_FPAFF
1499 config NUMA !! 2284 bool "Dynamic FPU affinity for FP-intensive threads"
1500 bool "NUMA Memory Allocation and Sche !! 2285 default y
1501 select GENERIC_ARCH_NUMA !! 2286 depends on MIPS_MT_SMP
1502 select OF_NUMA <<
1503 select HAVE_SETUP_PER_CPU_AREA <<
1504 select NEED_PER_CPU_EMBED_FIRST_CHUNK <<
1505 select NEED_PER_CPU_PAGE_FIRST_CHUNK <<
1506 select USE_PERCPU_NUMA_NODE_ID <<
1507 help <<
1508 Enable NUMA (Non-Uniform Memory Acc <<
1509 <<
1510 The kernel will try to allocate mem <<
1511 local memory of the CPU and add som <<
1512 NUMA awareness to the kernel. <<
1513 2287
1514 config NODES_SHIFT !! 2288 config MIPSR2_TO_R6_EMULATOR
1515 int "Maximum NUMA Nodes (as a power o !! 2289 bool "MIPS R2-to-R6 emulator"
1516 range 1 10 !! 2290 depends on CPU_MIPSR6
1517 default "4" !! 2291 default y
1518 depends on NUMA <<
1519 help 2292 help
1520 Specify the maximum number of NUMA !! 2293 Choose this option if you want to run non-R6 MIPS userland code.
1521 system. Increases memory reserved !! 2294 Even if you say 'Y' here, the emulator will still be disabled by
>> 2295 default. You can enable it using the 'mipsr2emu' kernel option.
>> 2296 The only reason this is a build-time option is to save ~14K from the
>> 2297 final kernel image.
1522 2298
1523 source "kernel/Kconfig.hz" !! 2299 config SYS_SUPPORTS_VPE_LOADER
1524 !! 2300 bool
1525 config ARCH_SPARSEMEM_ENABLE !! 2301 depends on SYS_SUPPORTS_MULTITHREADING
1526 def_bool y !! 2302 help
1527 select SPARSEMEM_VMEMMAP_ENABLE !! 2303 Indicates that the platform supports the VPE loader, and provides
1528 select SPARSEMEM_VMEMMAP !! 2304 physical_memsize.
1529 2305
1530 config HW_PERF_EVENTS !! 2306 config MIPS_VPE_LOADER
1531 def_bool y !! 2307 bool "VPE loader support."
1532 depends on ARM_PMU !! 2308 depends on SYS_SUPPORTS_VPE_LOADER && MODULES
>> 2309 select CPU_MIPSR2_IRQ_VI
>> 2310 select CPU_MIPSR2_IRQ_EI
>> 2311 select MIPS_MT
>> 2312 help
>> 2313 Includes a loader for loading an elf relocatable object
>> 2314 onto another VPE and running it.
1533 2315
1534 # Supported by clang >= 7.0 or GCC >= 12.0.0 !! 2316 config MIPS_VPE_LOADER_CMP
1535 config CC_HAVE_SHADOW_CALL_STACK !! 2317 bool
1536 def_bool $(cc-option, -fsanitize=shad !! 2318 default "y"
>> 2319 depends on MIPS_VPE_LOADER && MIPS_CMP
1537 2320
1538 config PARAVIRT !! 2321 config MIPS_VPE_LOADER_MT
1539 bool "Enable paravirtualization code" !! 2322 bool
1540 help !! 2323 default "y"
1541 This changes the kernel so it can m !! 2324 depends on MIPS_VPE_LOADER && !MIPS_CMP
1542 under a hypervisor, potentially imp <<
1543 over full virtualization. <<
1544 2325
1545 config PARAVIRT_TIME_ACCOUNTING !! 2326 config MIPS_VPE_LOADER_TOM
1546 bool "Paravirtual steal time accounti !! 2327 bool "Load VPE program into memory hidden from linux"
1547 select PARAVIRT !! 2328 depends on MIPS_VPE_LOADER
>> 2329 default y
1548 help 2330 help
1549 Select this option to enable fine g !! 2331 The loader can use memory that is present but has been hidden from
1550 accounting. Time spent executing ot !! 2332 Linux using the kernel command line option "mem=xxMB". It's up to
1551 the current vCPU is discounted from !! 2333 you to ensure the amount you put in the option and the space your
1552 that, there can be a small performa !! 2334 program requires is less or equal to the amount physically present.
1553 2335
1554 If in doubt, say N here. !! 2336 config MIPS_VPE_APSP_API
>> 2337 bool "Enable support for AP/SP API (RTLX)"
>> 2338 depends on MIPS_VPE_LOADER
1555 2339
1556 config ARCH_SUPPORTS_KEXEC !! 2340 config MIPS_VPE_APSP_API_CMP
1557 def_bool PM_SLEEP_SMP !! 2341 bool
>> 2342 default "y"
>> 2343 depends on MIPS_VPE_APSP_API && MIPS_CMP
1558 2344
1559 config ARCH_SUPPORTS_KEXEC_FILE !! 2345 config MIPS_VPE_APSP_API_MT
1560 def_bool y !! 2346 bool
>> 2347 default "y"
>> 2348 depends on MIPS_VPE_APSP_API && !MIPS_CMP
1561 2349
1562 config ARCH_SELECTS_KEXEC_FILE !! 2350 config MIPS_CMP
1563 def_bool y !! 2351 bool "MIPS CMP framework support (DEPRECATED)"
1564 depends on KEXEC_FILE !! 2352 depends on SYS_SUPPORTS_MIPS_CMP && !CPU_MIPSR6
1565 select HAVE_IMA_KEXEC if IMA !! 2353 select SMP
>> 2354 select SYNC_R4K
>> 2355 select SYS_SUPPORTS_SMP
>> 2356 select WEAK_ORDERING
>> 2357 default n
>> 2358 help
>> 2359 Select this if you are using a bootloader which implements the "CMP
>> 2360 framework" protocol (ie. YAMON) and want your kernel to make use of
>> 2361 its ability to start secondary CPUs.
>> 2362
>> 2363 Unless you have a specific need, you should use CONFIG_MIPS_CPS
>> 2364 instead of this.
>> 2365
>> 2366 config MIPS_CPS
>> 2367 bool "MIPS Coherent Processing System support"
>> 2368 depends on SYS_SUPPORTS_MIPS_CPS
>> 2369 select MIPS_CM
>> 2370 select MIPS_CPS_PM if HOTPLUG_CPU
>> 2371 select SMP
>> 2372 select SYNC_R4K if (CEVT_R4K || CSRC_R4K)
>> 2373 select SYS_SUPPORTS_HOTPLUG_CPU
>> 2374 select SYS_SUPPORTS_SCHED_SMT if CPU_MIPSR6
>> 2375 select SYS_SUPPORTS_SMP
>> 2376 select WEAK_ORDERING
>> 2377 help
>> 2378 Select this if you wish to run an SMP kernel across multiple cores
>> 2379 within a MIPS Coherent Processing System. When this option is
>> 2380 enabled the kernel will probe for other cores and boot them with
>> 2381 no external assistance. It is safe to enable this when hardware
>> 2382 support is unavailable.
1566 2383
1567 config ARCH_SUPPORTS_KEXEC_SIG !! 2384 config MIPS_CPS_PM
1568 def_bool y !! 2385 depends on MIPS_CPS
>> 2386 bool
1569 2387
1570 config ARCH_SUPPORTS_KEXEC_IMAGE_VERIFY_SIG !! 2388 config MIPS_CM
1571 def_bool y !! 2389 bool
>> 2390 select MIPS_CPC
1572 2391
1573 config ARCH_DEFAULT_KEXEC_IMAGE_VERIFY_SIG !! 2392 config MIPS_CPC
1574 def_bool y !! 2393 bool
1575 2394
1576 config ARCH_SUPPORTS_CRASH_DUMP !! 2395 config SB1_PASS_2_WORKAROUNDS
1577 def_bool y !! 2396 bool
>> 2397 depends on CPU_SB1 && (CPU_SB1_PASS_2_2 || CPU_SB1_PASS_2)
>> 2398 default y
1578 2399
1579 config ARCH_HAS_GENERIC_CRASHKERNEL_RESERVATI !! 2400 config SB1_PASS_2_1_WORKAROUNDS
1580 def_bool CRASH_RESERVE !! 2401 bool
>> 2402 depends on CPU_SB1 && CPU_SB1_PASS_2
>> 2403 default y
1581 2404
1582 config TRANS_TABLE <<
1583 def_bool y <<
1584 depends on HIBERNATION || KEXEC_CORE <<
1585 2405
1586 config XEN_DOM0 !! 2406 choice
1587 def_bool y !! 2407 prompt "SmartMIPS or microMIPS ASE support"
1588 depends on XEN <<
1589 2408
1590 config XEN !! 2409 config CPU_NEEDS_NO_SMARTMIPS_OR_MICROMIPS
1591 bool "Xen guest support on ARM64" !! 2410 bool "None"
1592 depends on ARM64 && OF <<
1593 select SWIOTLB_XEN <<
1594 select PARAVIRT <<
1595 help 2411 help
1596 Say Y if you want to run Linux in a !! 2412 Select this if you want neither microMIPS nor SmartMIPS support
1597 2413
1598 # include/linux/mmzone.h requires the followi !! 2414 config CPU_HAS_SMARTMIPS
1599 # !! 2415 depends on SYS_SUPPORTS_SMARTMIPS
1600 # MAX_PAGE_ORDER + PAGE_SHIFT <= SECTION_SI !! 2416 bool "SmartMIPS"
1601 # !! 2417 help
1602 # so the maximum value of MAX_PAGE_ORDER is S !! 2418 SmartMIPS is a extension of the MIPS32 architecture aimed at
1603 # !! 2419 increased security at both hardware and software level for
1604 # | SECTION_SIZE_BITS | PAGE_SHIFT | m !! 2420 smartcards. Enabling this option will allow proper use of the
1605 # ----+-------------------+--------------+--- !! 2421 SmartMIPS instructions by Linux applications. However a kernel with
1606 # 4K | 27 | 12 | !! 2422 this option will not work on a MIPS core without SmartMIPS core. If
1607 # 16K | 27 | 14 | !! 2423 you don't know you probably don't have SmartMIPS and should say N
1608 # 64K | 29 | 16 | !! 2424 here.
1609 config ARCH_FORCE_MAX_ORDER !! 2425
1610 int !! 2426 config CPU_MICROMIPS
1611 default "13" if ARM64_64K_PAGES !! 2427 depends on 32BIT && SYS_SUPPORTS_MICROMIPS && !CPU_MIPSR6
1612 default "11" if ARM64_16K_PAGES !! 2428 bool "microMIPS"
1613 default "10" <<
1614 help 2429 help
1615 The kernel page allocator limits th !! 2430 When this option is enabled the kernel will be built using the
1616 contiguous allocations. The limit i !! 2431 microMIPS ISA
1617 defines the maximal power of two of <<
1618 allocated as a single contiguous bl <<
1619 overriding the default setting when <<
1620 large blocks of physically contiguo <<
1621 <<
1622 The maximal size of allocation cann <<
1623 section, so the value of MAX_PAGE_O <<
1624 <<
1625 MAX_PAGE_ORDER + PAGE_SHIFT <= SE <<
1626 2432
1627 Don't change if unsure. !! 2433 endchoice
1628 2434
1629 config UNMAP_KERNEL_AT_EL0 !! 2435 config CPU_HAS_MSA
1630 bool "Unmap kernel when running in us !! 2436 bool "Support for the MIPS SIMD Architecture"
1631 default y !! 2437 depends on CPU_SUPPORTS_MSA
1632 help !! 2438 depends on 64BIT || MIPS_O32_FP64_SUPPORT
1633 Speculation attacks against some hi !! 2439 help
1634 be used to bypass MMU permission ch !! 2440 MIPS SIMD Architecture (MSA) introduces 128 bit wide vector registers
1635 userspace. This can be defended aga !! 2441 and a set of SIMD instructions to operate on them. When this option
1636 when running in userspace, mapping !! 2442 is enabled the kernel will support allocating & switching MSA
1637 via a trampoline page in the vector !! 2443 vector register contexts. If you know that your kernel will only be
>> 2444 running on CPUs which do not support MSA or that your userland will
>> 2445 not be making use of it then you may wish to say N here to reduce
>> 2446 the size & complexity of your kernel.
1638 2447
1639 If unsure, say Y. 2448 If unsure, say Y.
1640 2449
1641 config MITIGATE_SPECTRE_BRANCH_HISTORY !! 2450 config CPU_HAS_WB
1642 bool "Mitigate Spectre style attacks !! 2451 bool
1643 default y <<
1644 help <<
1645 Speculation attacks against some hi <<
1646 make use of branch history to influ <<
1647 When taking an exception from user- <<
1648 or a firmware call overwrites the b <<
1649 2452
1650 config RODATA_FULL_DEFAULT_ENABLED !! 2453 config XKS01
1651 bool "Apply r/o permissions of VM are !! 2454 bool
1652 default y <<
1653 help <<
1654 Apply read-only attributes of VM ar <<
1655 the backing pages as well. This pre <<
1656 from being modified (inadvertently <<
1657 mapping of the same memory page. Th <<
1658 be turned off at runtime by passing <<
1659 with rodata=full if this option is <<
1660 2455
1661 This requires the linear region to !! 2456 config CPU_HAS_RIXI
1662 which may adversely affect performa !! 2457 bool
1663 2458
1664 config ARM64_SW_TTBR0_PAN !! 2459 #
1665 bool "Emulate Privileged Access Never !! 2460 # Vectored interrupt mode is an R2 feature
1666 depends on !KCSAN !! 2461 #
1667 help !! 2462 config CPU_MIPSR2_IRQ_VI
1668 Enabling this option prevents the k !! 2463 bool
1669 user-space memory directly by point <<
1670 zeroed area and reserved ASID. The <<
1671 restore the valid TTBR0_EL1 tempora <<
1672 2464
1673 config ARM64_TAGGED_ADDR_ABI !! 2465 #
1674 bool "Enable the tagged user addresse !! 2466 # Extended interrupt mode is an R2 feature
>> 2467 #
>> 2468 config CPU_MIPSR2_IRQ_EI
>> 2469 bool
>> 2470
>> 2471 config CPU_HAS_SYNC
>> 2472 bool
>> 2473 depends on !CPU_R3000
1675 default y 2474 default y
1676 help <<
1677 When this option is enabled, user a <<
1678 relaxed ABI via prctl() allowing ta <<
1679 to system calls as pointer argument <<
1680 Documentation/arch/arm64/tagged-add <<
1681 2475
1682 menuconfig COMPAT !! 2476 #
1683 bool "Kernel support for 32-bit EL0" !! 2477 # CPU non-features
1684 depends on ARM64_4K_PAGES || EXPERT !! 2478 #
1685 select HAVE_UID16 !! 2479 config CPU_DADDI_WORKAROUNDS
1686 select OLD_SIGSUSPEND3 !! 2480 bool
1687 select COMPAT_OLD_SIGACTION <<
1688 help <<
1689 This option enables support for a 3 <<
1690 kernel at EL1. AArch32-specific com <<
1691 the user helper functions, VFP supp <<
1692 handled appropriately by the kernel <<
1693 2481
1694 If you use a page size other than 4 !! 2482 config CPU_R4000_WORKAROUNDS
1695 that you will only be able to execu !! 2483 bool
1696 with page size aligned segments. !! 2484 select CPU_R4400_WORKAROUNDS
1697 2485
1698 If you want to execute 32-bit users !! 2486 config CPU_R4400_WORKAROUNDS
>> 2487 bool
1699 2488
1700 if COMPAT !! 2489 config MIPS_ASID_SHIFT
>> 2490 int
>> 2491 default 6 if CPU_R3000 || CPU_TX39XX
>> 2492 default 4 if CPU_R8000
>> 2493 default 0
1701 2494
1702 config KUSER_HELPERS !! 2495 config MIPS_ASID_BITS
1703 bool "Enable kuser helpers page for 3 !! 2496 int
1704 default y !! 2497 default 0 if MIPS_ASID_BITS_VARIABLE
1705 help !! 2498 default 6 if CPU_R3000 || CPU_TX39XX
1706 Warning: disabling this option may !! 2499 default 8
1707 2500
1708 Provide kuser helpers to compat tas !! 2501 config MIPS_ASID_BITS_VARIABLE
1709 helper code to userspace in read on !! 2502 bool
1710 to allow userspace to be independen <<
1711 the system. This permits binaries t <<
1712 to ARMv8 without modification. <<
1713 2503
1714 See Documentation/arch/arm/kernel_u !! 2504 config MIPS_CRC_SUPPORT
>> 2505 bool
1715 2506
1716 However, the fixed address nature o !! 2507 #
1717 by ROP (return orientated programmi !! 2508 # - Highmem only makes sense for the 32-bit kernel.
1718 exploits. !! 2509 # - The current highmem code will only work properly on physically indexed
>> 2510 # caches such as R3000, SB1, R7000 or those that look like they're virtually
>> 2511 # indexed such as R4000/R4400 SC and MC versions or R10000. So for the
>> 2512 # moment we protect the user and offer the highmem option only on machines
>> 2513 # where it's known to be safe. This will not offer highmem on a few systems
>> 2514 # such as MIPS32 and MIPS64 CPUs which may have virtual and physically
>> 2515 # indexed CPUs but we're playing safe.
>> 2516 # - We use SYS_SUPPORTS_HIGHMEM to offer highmem only for systems where we
>> 2517 # know they might have memory configurations that could make use of highmem
>> 2518 # support.
>> 2519 #
>> 2520 config HIGHMEM
>> 2521 bool "High Memory Support"
>> 2522 depends on 32BIT && CPU_SUPPORTS_HIGHMEM && SYS_SUPPORTS_HIGHMEM && !CPU_MIPS32_3_5_EVA
1719 2523
1720 If all of the binaries and librarie !! 2524 config CPU_SUPPORTS_HIGHMEM
1721 are built specifically for your pla !! 2525 bool
1722 these helpers, then you can turn th <<
1723 such exploits. However, in that cas <<
1724 relying on those helpers is run, it <<
1725 2526
1726 Say N here only if you are absolute !! 2527 config SYS_SUPPORTS_HIGHMEM
1727 need these helpers; otherwise, the !! 2528 bool
1728 2529
1729 config COMPAT_VDSO !! 2530 config SYS_SUPPORTS_SMARTMIPS
1730 bool "Enable vDSO for 32-bit applicat !! 2531 bool
1731 depends on !CPU_BIG_ENDIAN <<
1732 depends on (CC_IS_CLANG && LD_IS_LLD) <<
1733 select GENERIC_COMPAT_VDSO <<
1734 default y <<
1735 help <<
1736 Place in the process address space <<
1737 ELF shared object providing fast im <<
1738 and clock_gettime. <<
1739 2532
1740 You must have a 32-bit build of gli !! 2533 config SYS_SUPPORTS_MICROMIPS
1741 to seamlessly take advantage of thi !! 2534 bool
1742 2535
1743 config THUMB2_COMPAT_VDSO !! 2536 config SYS_SUPPORTS_MIPS16
1744 bool "Compile the 32-bit vDSO for Thu !! 2537 bool
1745 depends on COMPAT_VDSO <<
1746 default y <<
1747 help 2538 help
1748 Compile the compat vDSO with '-mthu !! 2539 This option must be set if a kernel might be executed on a MIPS16-
1749 otherwise with '-marm'. !! 2540 enabled CPU even if MIPS16 is not actually being used. In other
>> 2541 words, it makes the kernel MIPS16-tolerant.
1750 2542
1751 config COMPAT_ALIGNMENT_FIXUPS !! 2543 config CPU_SUPPORTS_MSA
1752 bool "Fix up misaligned multi-word lo !! 2544 bool
1753 <<
1754 menuconfig ARMV8_DEPRECATED <<
1755 bool "Emulate deprecated/obsolete ARM <<
1756 depends on SYSCTL <<
1757 help <<
1758 Legacy software support may require <<
1759 that have been deprecated or obsole <<
1760 2545
1761 Enable this config to enable select !! 2546 config ARCH_FLATMEM_ENABLE
1762 features. !! 2547 def_bool y
>> 2548 depends on !NUMA && !CPU_LOONGSON2
1763 2549
1764 If unsure, say Y !! 2550 config ARCH_DISCONTIGMEM_ENABLE
>> 2551 bool
>> 2552 default y if SGI_IP27
>> 2553 help
>> 2554 Say Y to support efficient handling of discontiguous physical memory,
>> 2555 for architectures which are either NUMA (Non-Uniform Memory Access)
>> 2556 or have huge holes in the physical address space for other reasons.
>> 2557 See <file:Documentation/vm/numa.rst> for more.
1765 2558
1766 if ARMV8_DEPRECATED !! 2559 config ARCH_SPARSEMEM_ENABLE
>> 2560 bool
>> 2561 select SPARSEMEM_STATIC
1767 2562
1768 config SWP_EMULATION !! 2563 config NUMA
1769 bool "Emulate SWP/SWPB instructions" !! 2564 bool "NUMA Support"
>> 2565 depends on SYS_SUPPORTS_NUMA
1770 help 2566 help
1771 ARMv8 obsoletes the use of A32 SWP/ !! 2567 Say Y to compile the kernel to support NUMA (Non-Uniform Memory
1772 they are always undefined. Say Y he !! 2568 Access). This option improves performance on systems with more
1773 emulation of these instructions for !! 2569 than two nodes; on two node systems it is generally better to
1774 This feature can be controlled at r !! 2570 leave it disabled; on single node systems disable this option
1775 sysctl which is disabled by default !! 2571 disabled.
1776 2572
1777 In some older versions of glibc [<= !! 2573 config SYS_SUPPORTS_NUMA
1778 trylock() operations with the assum !! 2574 bool
1779 be preempted. This invalid assumpti <<
1780 with SWP emulation enabled, leading <<
1781 application. <<
1782 2575
1783 NOTE: when accessing uncached share !! 2576 config RELOCATABLE
1784 on an external transaction monitori !! 2577 bool "Relocatable kernel"
1785 monitor to maintain update atomicit !! 2578 depends on SYS_SUPPORTS_RELOCATABLE && (CPU_MIPS32_R2 || CPU_MIPS64_R2 || CPU_MIPS32_R6 || CPU_MIPS64_R6 || CAVIUM_OCTEON_SOC)
1786 implement a global monitor, this op !! 2579 help
1787 perform SWP operations to uncached !! 2580 This builds a kernel image that retains relocation information
>> 2581 so it can be loaded someplace besides the default 1MB.
>> 2582 The relocations make the kernel binary about 15% larger,
>> 2583 but are discarded at runtime
>> 2584
>> 2585 config RELOCATION_TABLE_SIZE
>> 2586 hex "Relocation table size"
>> 2587 depends on RELOCATABLE
>> 2588 range 0x0 0x01000000
>> 2589 default "0x00100000"
>> 2590 ---help---
>> 2591 A table of relocation data will be appended to the kernel binary
>> 2592 and parsed at boot to fix up the relocated kernel.
1788 2593
1789 If unsure, say Y !! 2594 This option allows the amount of space reserved for the table to be
>> 2595 adjusted, although the default of 1Mb should be ok in most cases.
1790 2596
1791 config CP15_BARRIER_EMULATION !! 2597 The build will fail and a valid size suggested if this is too small.
1792 bool "Emulate CP15 Barrier instructio <<
1793 help <<
1794 The CP15 barrier instructions - CP1 <<
1795 CP15DMB - are deprecated in ARMv8 ( <<
1796 strongly recommended to use the ISB <<
1797 instructions instead. <<
1798 2598
1799 Say Y here to enable software emula !! 2599 If unsure, leave at the default value.
1800 instructions for AArch32 userspace <<
1801 enabled, CP15 barrier usage is trac <<
1802 identify software that needs updati <<
1803 controlled at runtime with the abi. <<
1804 2600
1805 If unsure, say Y !! 2601 config RANDOMIZE_BASE
>> 2602 bool "Randomize the address of the kernel image"
>> 2603 depends on RELOCATABLE
>> 2604 ---help---
>> 2605 Randomizes the physical and virtual address at which the
>> 2606 kernel image is loaded, as a security feature that
>> 2607 deters exploit attempts relying on knowledge of the location
>> 2608 of kernel internals.
1806 2609
1807 config SETEND_EMULATION !! 2610 Entropy is generated using any coprocessor 0 registers available.
1808 bool "Emulate SETEND instruction" <<
1809 help <<
1810 The SETEND instruction alters the d <<
1811 AArch32 EL0, and is deprecated in A <<
1812 2611
1813 Say Y here to enable software emula !! 2612 The kernel will be offset by up to RANDOMIZE_BASE_MAX_OFFSET.
1814 for AArch32 userspace code. This fe <<
1815 at runtime with the abi.setend sysc <<
1816 2613
1817 Note: All the cpus on the system mu !! 2614 If unsure, say N.
1818 for this feature to be enabled. If <<
1819 endian - is hotplugged in after thi <<
1820 be unexpected results in the applic <<
1821 2615
1822 If unsure, say Y !! 2616 config RANDOMIZE_BASE_MAX_OFFSET
1823 endif # ARMV8_DEPRECATED !! 2617 hex "Maximum kASLR offset" if EXPERT
>> 2618 depends on RANDOMIZE_BASE
>> 2619 range 0x0 0x40000000 if EVA || 64BIT
>> 2620 range 0x0 0x08000000
>> 2621 default "0x01000000"
>> 2622 ---help---
>> 2623 When kASLR is active, this provides the maximum offset that will
>> 2624 be applied to the kernel image. It should be set according to the
>> 2625 amount of physical RAM available in the target system minus
>> 2626 PHYSICAL_START and must be a power of 2.
1824 2627
1825 endif # COMPAT !! 2628 This is limited by the size of KSEG0, 256Mb on 32-bit or 1Gb with
>> 2629 EVA or 64-bit. The default is 16Mb.
1826 2630
1827 menu "ARMv8.1 architectural features" !! 2631 config NODES_SHIFT
>> 2632 int
>> 2633 default "6"
>> 2634 depends on NEED_MULTIPLE_NODES
1828 2635
1829 config ARM64_HW_AFDBM !! 2636 config HW_PERF_EVENTS
1830 bool "Support for hardware updates of !! 2637 bool "Enable hardware performance counter support for perf events"
>> 2638 depends on PERF_EVENTS && !OPROFILE && (CPU_MIPS32 || CPU_MIPS64 || CPU_R10000 || CPU_SB1 || CPU_CAVIUM_OCTEON || CPU_XLP || CPU_LOONGSON3)
1831 default y 2639 default y
1832 help 2640 help
1833 The ARMv8.1 architecture extensions !! 2641 Enable hardware performance counter support for perf events. If
1834 hardware updates of the access and !! 2642 disabled, perf events will use software events only.
1835 table entries. When enabled in TCR_ <<
1836 capable processors, accesses to pag <<
1837 set this bit instead of raising an <<
1838 Similarly, writes to read-only page <<
1839 clear the read-only bit (AP[2]) ins <<
1840 permission fault. <<
1841 2643
1842 Kernels built with this configurati !! 2644 source "mm/Kconfig"
1843 to work on pre-ARMv8.1 hardware and <<
1844 minimal. If unsure, say Y. <<
1845 2645
1846 config ARM64_PAN !! 2646 config SMP
1847 bool "Enable support for Privileged A !! 2647 bool "Multi-Processing support"
1848 default y !! 2648 depends on SYS_SUPPORTS_SMP
1849 help 2649 help
1850 Privileged Access Never (PAN; part !! 2650 This enables support for systems with more than one CPU. If you have
1851 prevents the kernel or hypervisor f !! 2651 a system with only one CPU, say N. If you have a system with more
1852 memory directly. !! 2652 than one CPU, say Y.
>> 2653
>> 2654 If you say N here, the kernel will run on uni- and multiprocessor
>> 2655 machines, but will use only one CPU of a multiprocessor machine. If
>> 2656 you say Y here, the kernel will run on many, but not all,
>> 2657 uniprocessor machines. On a uniprocessor machine, the kernel
>> 2658 will run faster if you say N here.
1853 2659
1854 Choosing this option will cause any !! 2660 People using multiprocessor machines who say Y here should also say
1855 copy_to_user et al) memory access t !! 2661 Y to "Enhanced Real Time Clock Support", below.
1856 2662
1857 The feature is detected at runtime, !! 2663 See also the SMP-HOWTO available at
1858 instruction if the cpu does not imp !! 2664 <http://www.tldp.org/docs.html#howto>.
1859 2665
1860 config AS_HAS_LSE_ATOMICS !! 2666 If you don't know what to do here, say N.
1861 def_bool $(as-instr,.arch_extension l <<
1862 2667
1863 config ARM64_LSE_ATOMICS !! 2668 config HOTPLUG_CPU
1864 bool !! 2669 bool "Support for hot-pluggable CPUs"
1865 default ARM64_USE_LSE_ATOMICS !! 2670 depends on SMP && SYS_SUPPORTS_HOTPLUG_CPU
1866 depends on AS_HAS_LSE_ATOMICS <<
1867 <<
1868 config ARM64_USE_LSE_ATOMICS <<
1869 bool "Atomic instructions" <<
1870 default y <<
1871 help 2671 help
1872 As part of the Large System Extensi !! 2672 Say Y here to allow turning CPUs off and on. CPUs can be
1873 atomic instructions that are design !! 2673 controlled through /sys/devices/system/cpu.
1874 very large systems. !! 2674 (Note: power management support will enable this option
>> 2675 automatically on SMP systems. )
>> 2676 Say N if you want to disable CPU hotplug.
1875 2677
1876 Say Y here to make use of these ins !! 2678 config SMP_UP
1877 atomic routines. This incurs a smal !! 2679 bool
1878 not support these instructions and <<
1879 built with binutils >= 2.25 in orde <<
1880 to be used. <<
1881 2680
1882 endmenu # "ARMv8.1 architectural features" !! 2681 config SYS_SUPPORTS_MIPS_CMP
>> 2682 bool
1883 2683
1884 menu "ARMv8.2 architectural features" !! 2684 config SYS_SUPPORTS_MIPS_CPS
>> 2685 bool
1885 2686
1886 config AS_HAS_ARMV8_2 !! 2687 config SYS_SUPPORTS_SMP
1887 def_bool $(cc-option,-Wa$(comma)-marc !! 2688 bool
1888 2689
1889 config AS_HAS_SHA3 !! 2690 config NR_CPUS_DEFAULT_4
1890 def_bool $(as-instr,.arch armv8.2-a+s !! 2691 bool
1891 2692
1892 config ARM64_PMEM !! 2693 config NR_CPUS_DEFAULT_8
1893 bool "Enable support for persistent m !! 2694 bool
1894 select ARCH_HAS_PMEM_API <<
1895 select ARCH_HAS_UACCESS_FLUSHCACHE <<
1896 help <<
1897 Say Y to enable support for the per <<
1898 ARMv8.2 DCPoP feature. <<
1899 2695
1900 The feature is detected at runtime, !! 2696 config NR_CPUS_DEFAULT_16
1901 operations if DC CVAP is not suppor !! 2697 bool
1902 DC CVAP itself if the system does n <<
1903 2698
1904 config ARM64_RAS_EXTN !! 2699 config NR_CPUS_DEFAULT_32
1905 bool "Enable support for RAS CPU Exte !! 2700 bool
1906 default y <<
1907 help <<
1908 CPUs that support the Reliability, <<
1909 (RAS) Extensions, part of ARMv8.2 a <<
1910 errors, classify them and report th <<
1911 2701
1912 On CPUs with these extensions syste !! 2702 config NR_CPUS_DEFAULT_64
1913 barriers to determine if faults are !! 2703 bool
1914 classification from a new set of re <<
1915 2704
1916 Selecting this feature will allow t !! 2705 config NR_CPUS
1917 and access the new registers if the !! 2706 int "Maximum number of CPUs (2-256)"
1918 Platform RAS features may additiona !! 2707 range 2 256
>> 2708 depends on SMP
>> 2709 default "4" if NR_CPUS_DEFAULT_4
>> 2710 default "8" if NR_CPUS_DEFAULT_8
>> 2711 default "16" if NR_CPUS_DEFAULT_16
>> 2712 default "32" if NR_CPUS_DEFAULT_32
>> 2713 default "64" if NR_CPUS_DEFAULT_64
>> 2714 help
>> 2715 This allows you to specify the maximum number of CPUs which this
>> 2716 kernel will support. The maximum supported value is 32 for 32-bit
>> 2717 kernel and 64 for 64-bit kernels; the minimum value which makes
>> 2718 sense is 1 for Qemu (useful only for kernel debugging purposes)
>> 2719 and 2 for all others.
>> 2720
>> 2721 This is purely to save memory - each supported CPU adds
>> 2722 approximately eight kilobytes to the kernel image. For best
>> 2723 performance should round up your number of processors to the next
>> 2724 power of two.
1919 2725
1920 config ARM64_CNP !! 2726 config MIPS_PERF_SHARED_TC_COUNTERS
1921 bool "Enable support for Common Not P !! 2727 bool
1922 default y <<
1923 depends on ARM64_PAN || !ARM64_SW_TTB <<
1924 help <<
1925 Common Not Private (CNP) allows tra <<
1926 be shared between different PEs in <<
1927 domain, so the hardware can use thi <<
1928 caching of such entries in the TLB. <<
1929 2728
1930 Selecting this option allows the CN !! 2729 config MIPS_NR_CPU_NR_MAP_1024
1931 at runtime, and does not affect PEs !! 2730 bool
1932 this feature. <<
1933 2731
1934 endmenu # "ARMv8.2 architectural features" !! 2732 config MIPS_NR_CPU_NR_MAP
>> 2733 int
>> 2734 depends on SMP
>> 2735 default 1024 if MIPS_NR_CPU_NR_MAP_1024
>> 2736 default NR_CPUS if !MIPS_NR_CPU_NR_MAP_1024
1935 2737
1936 menu "ARMv8.3 architectural features" !! 2738 #
>> 2739 # Timer Interrupt Frequency Configuration
>> 2740 #
1937 2741
1938 config ARM64_PTR_AUTH !! 2742 choice
1939 bool "Enable support for pointer auth !! 2743 prompt "Timer frequency"
1940 default y !! 2744 default HZ_250
1941 help 2745 help
1942 Pointer authentication (part of the !! 2746 Allows the configuration of the timer frequency.
1943 instructions for signing and authen <<
1944 keys, which can be used to mitigate <<
1945 and other attacks. <<
1946 2747
1947 This option enables these instructi !! 2748 config HZ_24
1948 Choosing this option will cause the !! 2749 bool "24 HZ" if SYS_SUPPORTS_24HZ || SYS_SUPPORTS_ARBIT_HZ
1949 for each process at exec() time, wi <<
1950 context-switched along with the pro <<
1951 2750
1952 The feature is detected at runtime. !! 2751 config HZ_48
1953 hardware it will not be advertised !! 2752 bool "48 HZ" if SYS_SUPPORTS_48HZ || SYS_SUPPORTS_ARBIT_HZ
1954 be enabled. <<
1955 2753
1956 If the feature is present on the bo !! 2754 config HZ_100
1957 the late CPU will be parked. Also, !! 2755 bool "100 HZ" if SYS_SUPPORTS_100HZ || SYS_SUPPORTS_ARBIT_HZ
1958 address auth and the late CPU has t <<
1959 but with the feature disabled. On s <<
1960 not be selected. <<
1961 2756
1962 config ARM64_PTR_AUTH_KERNEL !! 2757 config HZ_128
1963 bool "Use pointer authentication for !! 2758 bool "128 HZ" if SYS_SUPPORTS_128HZ || SYS_SUPPORTS_ARBIT_HZ
1964 default y <<
1965 depends on ARM64_PTR_AUTH <<
1966 depends on (CC_HAS_SIGN_RETURN_ADDRES <<
1967 # Modern compilers insert a .note.gnu <<
1968 # which is only understood by binutil <<
1969 depends on LD_IS_LLD || LD_VERSION >= <<
1970 depends on !CC_IS_CLANG || AS_HAS_CFI <<
1971 depends on (!FUNCTION_GRAPH_TRACER || <<
1972 help <<
1973 If the compiler supports the -mbran <<
1974 -msign-return-address flag (e.g. GC <<
1975 will cause the kernel itself to be <<
1976 protection. In this case, and if th <<
1977 support pointer authentication, the <<
1978 disabled with minimal loss of prote <<
1979 2759
1980 This feature works with FUNCTION_GR !! 2760 config HZ_250
1981 DYNAMIC_FTRACE_WITH_ARGS is enabled !! 2761 bool "250 HZ" if SYS_SUPPORTS_250HZ || SYS_SUPPORTS_ARBIT_HZ
1982 2762
1983 config CC_HAS_BRANCH_PROT_PAC_RET !! 2763 config HZ_256
1984 # GCC 9 or later, clang 8 or later !! 2764 bool "256 HZ" if SYS_SUPPORTS_256HZ || SYS_SUPPORTS_ARBIT_HZ
1985 def_bool $(cc-option,-mbranch-protect <<
1986 2765
1987 config CC_HAS_SIGN_RETURN_ADDRESS !! 2766 config HZ_1000
1988 # GCC 7, 8 !! 2767 bool "1000 HZ" if SYS_SUPPORTS_1000HZ || SYS_SUPPORTS_ARBIT_HZ
1989 def_bool $(cc-option,-msign-return-ad <<
1990 2768
1991 config AS_HAS_ARMV8_3 !! 2769 config HZ_1024
1992 def_bool $(cc-option,-Wa$(comma)-marc !! 2770 bool "1024 HZ" if SYS_SUPPORTS_1024HZ || SYS_SUPPORTS_ARBIT_HZ
1993 2771
1994 config AS_HAS_CFI_NEGATE_RA_STATE !! 2772 endchoice
1995 def_bool $(as-instr,.cfi_startproc\n. <<
1996 2773
1997 config AS_HAS_LDAPR !! 2774 config SYS_SUPPORTS_24HZ
1998 def_bool $(as-instr,.arch_extension r !! 2775 bool
1999 2776
2000 endmenu # "ARMv8.3 architectural features" !! 2777 config SYS_SUPPORTS_48HZ
>> 2778 bool
2001 2779
2002 menu "ARMv8.4 architectural features" !! 2780 config SYS_SUPPORTS_100HZ
>> 2781 bool
2003 2782
2004 config ARM64_AMU_EXTN !! 2783 config SYS_SUPPORTS_128HZ
2005 bool "Enable support for the Activity !! 2784 bool
2006 default y <<
2007 help <<
2008 The activity monitors extension is <<
2009 by the ARMv8.4 CPU architecture. Th <<
2010 of the activity monitors architectu <<
2011 2785
2012 To enable the use of this extension !! 2786 config SYS_SUPPORTS_250HZ
>> 2787 bool
2013 2788
2014 Note that for architectural reasons !! 2789 config SYS_SUPPORTS_256HZ
2015 support when running on CPUs that p !! 2790 bool
2016 extension. The required support is <<
2017 * Version 1.5 and later of the AR <<
2018 2791
2019 For kernels that have this configur !! 2792 config SYS_SUPPORTS_1000HZ
2020 firmware, you may need to say N her !! 2793 bool
2021 Otherwise you may experience firmwa <<
2022 accessing the counter registers. Ev <<
2023 symptoms, the values returned by th <<
2024 correctly reflect reality. Most com <<
2025 indicating that the counter is not <<
2026 2794
2027 config AS_HAS_ARMV8_4 !! 2795 config SYS_SUPPORTS_1024HZ
2028 def_bool $(cc-option,-Wa$(comma)-marc !! 2796 bool
2029 2797
2030 config ARM64_TLB_RANGE !! 2798 config SYS_SUPPORTS_ARBIT_HZ
2031 bool "Enable support for tlbi range f !! 2799 bool
2032 default y !! 2800 default y if !SYS_SUPPORTS_24HZ && \
2033 depends on AS_HAS_ARMV8_4 !! 2801 !SYS_SUPPORTS_48HZ && \
2034 help !! 2802 !SYS_SUPPORTS_100HZ && \
2035 ARMv8.4-TLBI provides TLBI invalida !! 2803 !SYS_SUPPORTS_128HZ && \
2036 range of input addresses. !! 2804 !SYS_SUPPORTS_250HZ && \
>> 2805 !SYS_SUPPORTS_256HZ && \
>> 2806 !SYS_SUPPORTS_1000HZ && \
>> 2807 !SYS_SUPPORTS_1024HZ
2037 2808
2038 The feature introduces new assembly !! 2809 config HZ
2039 support when binutils >= 2.30. !! 2810 int
>> 2811 default 24 if HZ_24
>> 2812 default 48 if HZ_48
>> 2813 default 100 if HZ_100
>> 2814 default 128 if HZ_128
>> 2815 default 250 if HZ_250
>> 2816 default 256 if HZ_256
>> 2817 default 1000 if HZ_1000
>> 2818 default 1024 if HZ_1024
>> 2819
>> 2820 config SCHED_HRTICK
>> 2821 def_bool HIGH_RES_TIMERS
>> 2822
>> 2823 source "kernel/Kconfig.preempt"
>> 2824
>> 2825 config KEXEC
>> 2826 bool "Kexec system call"
>> 2827 select KEXEC_CORE
>> 2828 help
>> 2829 kexec is a system call that implements the ability to shutdown your
>> 2830 current kernel, and to start another kernel. It is like a reboot
>> 2831 but it is independent of the system firmware. And like a reboot
>> 2832 you can start any kernel with it, not just Linux.
>> 2833
>> 2834 The name comes from the similarity to the exec system call.
>> 2835
>> 2836 It is an ongoing process to be certain the hardware in a machine
>> 2837 is properly shutdown, so do not be surprised if this code does not
>> 2838 initially work for you. As of this writing the exact hardware
>> 2839 interface is strongly in flux, so no good recommendation can be
>> 2840 made.
>> 2841
>> 2842 config CRASH_DUMP
>> 2843 bool "Kernel crash dumps"
>> 2844 help
>> 2845 Generate crash dump after being started by kexec.
>> 2846 This should be normally only set in special crash dump kernels
>> 2847 which are loaded in the main kernel with kexec-tools into
>> 2848 a specially reserved region and then later executed after
>> 2849 a crash by kdump/kexec. The crash dump kernel must be compiled
>> 2850 to a memory address not used by the main kernel or firmware using
>> 2851 PHYSICAL_START.
>> 2852
>> 2853 config PHYSICAL_START
>> 2854 hex "Physical address where the kernel is loaded"
>> 2855 default "0xffffffff84000000"
>> 2856 depends on CRASH_DUMP
>> 2857 help
>> 2858 This gives the CKSEG0 or KSEG0 address where the kernel is loaded.
>> 2859 If you plan to use kernel for capturing the crash dump change
>> 2860 this value to start of the reserved region (the "X" value as
>> 2861 specified in the "crashkernel=YM@XM" command line boot parameter
>> 2862 passed to the panic-ed kernel).
>> 2863
>> 2864 config SECCOMP
>> 2865 bool "Enable seccomp to safely compute untrusted bytecode"
>> 2866 depends on PROC_FS
>> 2867 default y
>> 2868 help
>> 2869 This kernel feature is useful for number crunching applications
>> 2870 that may need to compute untrusted bytecode during their
>> 2871 execution. By using pipes or other transports made available to
>> 2872 the process as file descriptors supporting the read/write
>> 2873 syscalls, it's possible to isolate those applications in
>> 2874 their own address space using seccomp. Once seccomp is
>> 2875 enabled via /proc/<pid>/seccomp, it cannot be disabled
>> 2876 and the task is only allowed to execute a few safe syscalls
>> 2877 defined by each seccomp mode.
>> 2878
>> 2879 If unsure, say Y. Only embedded should say N here.
>> 2880
>> 2881 config MIPS_O32_FP64_SUPPORT
>> 2882 bool "Support for O32 binaries using 64-bit FP"
>> 2883 depends on 32BIT || MIPS32_O32
>> 2884 help
>> 2885 When this is enabled, the kernel will support use of 64-bit floating
>> 2886 point registers with binaries using the O32 ABI along with the
>> 2887 EF_MIPS_FP64 ELF header flag (typically built with -mfp64). On
>> 2888 32-bit MIPS systems this support is at the cost of increasing the
>> 2889 size and complexity of the compiled FPU emulator. Thus if you are
>> 2890 running a MIPS32 system and know that none of your userland binaries
>> 2891 will require 64-bit floating point, you may wish to reduce the size
>> 2892 of your kernel & potentially improve FP emulation performance by
>> 2893 saying N here.
>> 2894
>> 2895 Although binutils currently supports use of this flag the details
>> 2896 concerning its effect upon the O32 ABI in userland are still being
>> 2897 worked on. In order to avoid userland becoming dependant upon current
>> 2898 behaviour before the details have been finalised, this option should
>> 2899 be considered experimental and only enabled by those working upon
>> 2900 said details.
2040 2901
2041 endmenu # "ARMv8.4 architectural features" !! 2902 If unsure, say N.
2042 2903
2043 menu "ARMv8.5 architectural features" !! 2904 config USE_OF
>> 2905 bool
>> 2906 select OF
>> 2907 select OF_EARLY_FLATTREE
>> 2908 select IRQ_DOMAIN
2044 2909
2045 config AS_HAS_ARMV8_5 !! 2910 config BUILTIN_DTB
2046 def_bool $(cc-option,-Wa$(comma)-marc !! 2911 bool
2047 2912
2048 config ARM64_BTI !! 2913 choice
2049 bool "Branch Target Identification su !! 2914 prompt "Kernel appended dtb support" if USE_OF
2050 default y !! 2915 default MIPS_NO_APPENDED_DTB
2051 help <<
2052 Branch Target Identification (part <<
2053 provides a mechanism to limit the s <<
2054 branch instructions such as BR or B <<
2055 2916
2056 To make use of BTI on CPUs that sup !! 2917 config MIPS_NO_APPENDED_DTB
>> 2918 bool "None"
>> 2919 help
>> 2920 Do not enable appended dtb support.
>> 2921
>> 2922 config MIPS_ELF_APPENDED_DTB
>> 2923 bool "vmlinux"
>> 2924 help
>> 2925 With this option, the boot code will look for a device tree binary
>> 2926 DTB) included in the vmlinux ELF section .appended_dtb. By default
>> 2927 it is empty and the DTB can be appended using binutils command
>> 2928 objcopy:
>> 2929
>> 2930 objcopy --update-section .appended_dtb=<filename>.dtb vmlinux
>> 2931
>> 2932 This is meant as a backward compatiblity convenience for those
>> 2933 systems with a bootloader that can't be upgraded to accommodate
>> 2934 the documented boot protocol using a device tree.
>> 2935
>> 2936 config MIPS_RAW_APPENDED_DTB
>> 2937 bool "vmlinux.bin or vmlinuz.bin"
>> 2938 help
>> 2939 With this option, the boot code will look for a device tree binary
>> 2940 DTB) appended to raw vmlinux.bin or vmlinuz.bin.
>> 2941 (e.g. cat vmlinux.bin <filename>.dtb > vmlinux_w_dtb).
>> 2942
>> 2943 This is meant as a backward compatibility convenience for those
>> 2944 systems with a bootloader that can't be upgraded to accommodate
>> 2945 the documented boot protocol using a device tree.
>> 2946
>> 2947 Beware that there is very little in terms of protection against
>> 2948 this option being confused by leftover garbage in memory that might
>> 2949 look like a DTB header after a reboot if no actual DTB is appended
>> 2950 to vmlinux.bin. Do not leave this option active in a production kernel
>> 2951 if you don't intend to always append a DTB.
>> 2952 endchoice
2057 2953
2058 BTI is intended to provide compleme !! 2954 choice
2059 flow integrity protection mechanism !! 2955 prompt "Kernel command line type" if !CMDLINE_OVERRIDE
2060 authentication mechanism provided a !! 2956 default MIPS_CMDLINE_FROM_DTB if USE_OF && !ATH79 && !MACH_INGENIC && \
2061 For this reason, it does not make s !! 2957 !MIPS_MALTA && \
2062 also enabling support for pointer a !! 2958 !CAVIUM_OCTEON_SOC
2063 enabling this option you should als !! 2959 default MIPS_CMDLINE_FROM_BOOTLOADER
>> 2960
>> 2961 config MIPS_CMDLINE_FROM_DTB
>> 2962 depends on USE_OF
>> 2963 bool "Dtb kernel arguments if available"
>> 2964
>> 2965 config MIPS_CMDLINE_DTB_EXTEND
>> 2966 depends on USE_OF
>> 2967 bool "Extend dtb kernel arguments with bootloader arguments"
>> 2968
>> 2969 config MIPS_CMDLINE_FROM_BOOTLOADER
>> 2970 bool "Bootloader kernel arguments if available"
>> 2971
>> 2972 config MIPS_CMDLINE_BUILTIN_EXTEND
>> 2973 depends on CMDLINE_BOOL
>> 2974 bool "Extend builtin kernel arguments with bootloader arguments"
>> 2975 endchoice
2064 2976
2065 Userspace binaries must also be spe !! 2977 endmenu
2066 this mechanism. If you say N here <<
2067 BTI, such binaries can still run, b <<
2068 enforcement of branch destinations. <<
2069 2978
2070 config ARM64_BTI_KERNEL !! 2979 config LOCKDEP_SUPPORT
2071 bool "Use Branch Target Identificatio !! 2980 bool
2072 default y 2981 default y
2073 depends on ARM64_BTI <<
2074 depends on ARM64_PTR_AUTH_KERNEL <<
2075 depends on CC_HAS_BRANCH_PROT_PAC_RET <<
2076 # https://gcc.gnu.org/bugzilla/show_b <<
2077 depends on !CC_IS_GCC || GCC_VERSION <<
2078 # https://gcc.gnu.org/bugzilla/show_b <<
2079 depends on !CC_IS_GCC <<
2080 depends on (!FUNCTION_GRAPH_TRACER || <<
2081 help <<
2082 Build the kernel with Branch Target <<
2083 and enable enforcement of this for <<
2084 is enabled and the system supports <<
2085 modular code must have BTI enabled. <<
2086 <<
2087 config CC_HAS_BRANCH_PROT_PAC_RET_BTI <<
2088 # GCC 9 or later, clang 8 or later <<
2089 def_bool $(cc-option,-mbranch-protect <<
2090 2982
2091 config ARM64_E0PD !! 2983 config STACKTRACE_SUPPORT
2092 bool "Enable support for E0PD" !! 2984 bool
2093 default y 2985 default y
2094 help <<
2095 E0PD (part of the ARMv8.5 extension <<
2096 that EL0 accesses made via TTBR1 al <<
2097 providing similar benefits to KASLR <<
2098 with lower overhead and without dis <<
2099 kernel memory such as SPE. <<
2100 <<
2101 This option enables E0PD for TTBR1 <<
2102 2986
2103 config ARM64_AS_HAS_MTE !! 2987 config HAVE_LATENCYTOP_SUPPORT
2104 # Initial support for MTE went in bin !! 2988 bool
2105 # ".arch armv8.5-a+memtag" below. How <<
2106 # as a late addition to the final arc <<
2107 # is only supported in the newer 2.32 <<
2108 # versions, hence the extra "stgm" in <<
2109 def_bool $(as-instr,.arch armv8.5-a+m <<
2110 <<
2111 config ARM64_MTE <<
2112 bool "Memory Tagging Extension suppor <<
2113 default y 2989 default y
2114 depends on ARM64_AS_HAS_MTE && ARM64_ <<
2115 depends on AS_HAS_ARMV8_5 <<
2116 depends on AS_HAS_LSE_ATOMICS <<
2117 # Required for tag checking in the ua <<
2118 depends on ARM64_PAN <<
2119 select ARCH_HAS_SUBPAGE_FAULTS <<
2120 select ARCH_USES_HIGH_VMA_FLAGS <<
2121 select ARCH_USES_PG_ARCH_2 <<
2122 select ARCH_USES_PG_ARCH_3 <<
2123 help <<
2124 Memory Tagging (part of the ARMv8.5 <<
2125 architectural support for run-time, <<
2126 various classes of memory error to <<
2127 to eliminate vulnerabilities arisin <<
2128 languages. <<
2129 2990
2130 This option enables the support for !! 2991 config PGTABLE_LEVELS
2131 Extension at EL0 (i.e. for userspac !! 2992 int
>> 2993 default 4 if PAGE_SIZE_4KB && MIPS_VA_BITS_48
>> 2994 default 3 if 64BIT && !PAGE_SIZE_64KB
>> 2995 default 2
2132 2996
2133 Selecting this option allows the fe !! 2997 source "init/Kconfig"
2134 runtime. Any secondary CPU not impl <<
2135 not be allowed a late bring-up. <<
2136 2998
2137 Userspace binaries that want to use !! 2999 source "kernel/Kconfig.freezer"
2138 explicitly opt in. The mechanism fo <<
2139 described in: <<
2140 3000
2141 Documentation/arch/arm64/memory-tag !! 3001 menu "Bus options (PCI, PCMCIA, EISA, ISA, TC)"
2142 3002
2143 endmenu # "ARMv8.5 architectural features" !! 3003 config HW_HAS_EISA
>> 3004 bool
>> 3005 config HW_HAS_PCI
>> 3006 bool
2144 3007
2145 menu "ARMv8.7 architectural features" !! 3008 config PCI
>> 3009 bool "Support for PCI controller"
>> 3010 depends on HW_HAS_PCI
>> 3011 select PCI_DOMAINS
>> 3012 help
>> 3013 Find out whether you have a PCI motherboard. PCI is the name of a
>> 3014 bus system, i.e. the way the CPU talks to the other stuff inside
>> 3015 your box. Other bus systems are ISA, EISA, or VESA. If you have PCI,
>> 3016 say Y, otherwise N.
>> 3017
>> 3018 config HT_PCI
>> 3019 bool "Support for HT-linked PCI"
>> 3020 default y
>> 3021 depends on CPU_LOONGSON3
>> 3022 select PCI
>> 3023 select PCI_DOMAINS
>> 3024 help
>> 3025 Loongson family machines use Hyper-Transport bus for inter-core
>> 3026 connection and device connection. The PCI bus is a subordinate
>> 3027 linked at HT. Choose Y for Loongson-3 based machines.
2146 3028
2147 config ARM64_EPAN !! 3029 config PCI_DOMAINS
2148 bool "Enable support for Enhanced Pri !! 3030 bool
2149 default y <<
2150 depends on ARM64_PAN <<
2151 help <<
2152 Enhanced Privileged Access Never (E <<
2153 Access Never to be used with Execut <<
2154 <<
2155 The feature is detected at runtime, <<
2156 if the cpu does not implement the f <<
2157 endmenu # "ARMv8.7 architectural features" <<
2158 3031
2159 menu "ARMv8.9 architectural features" !! 3032 config PCI_DOMAINS_GENERIC
>> 3033 bool
2160 3034
2161 config ARM64_POE !! 3035 config PCI_DRIVERS_GENERIC
2162 prompt "Permission Overlay Extension" !! 3036 select PCI_DOMAINS_GENERIC if PCI_DOMAINS
2163 def_bool y !! 3037 bool
2164 select ARCH_USES_HIGH_VMA_FLAGS <<
2165 select ARCH_HAS_PKEYS <<
2166 help <<
2167 The Permission Overlay Extension is <<
2168 Protection Keys. Memory Protection <<
2169 enforcing page-based protections, b <<
2170 of the page tables when an applicat <<
2171 3038
2172 For details, see Documentation/core !! 3039 config PCI_DRIVERS_LEGACY
>> 3040 def_bool !PCI_DRIVERS_GENERIC
>> 3041 select NO_GENERIC_PCI_IOPORT_MAP
2173 3042
2174 If unsure, say y. !! 3043 source "drivers/pci/Kconfig"
2175 3044
2176 config ARCH_PKEY_BITS !! 3045 #
2177 int !! 3046 # ISA support is now enabled via select. Too many systems still have the one
2178 default 3 !! 3047 # or other ISA chip on the board that users don't know about so don't expect
>> 3048 # users to choose the right thing ...
>> 3049 #
>> 3050 config ISA
>> 3051 bool
2179 3052
2180 endmenu # "ARMv8.9 architectural features" !! 3053 config EISA
>> 3054 bool "EISA support"
>> 3055 depends on HW_HAS_EISA
>> 3056 select ISA
>> 3057 select GENERIC_ISA_DMA
>> 3058 ---help---
>> 3059 The Extended Industry Standard Architecture (EISA) bus was
>> 3060 developed as an open alternative to the IBM MicroChannel bus.
>> 3061
>> 3062 The EISA bus provided some of the features of the IBM MicroChannel
>> 3063 bus while maintaining backward compatibility with cards made for
>> 3064 the older ISA bus. The EISA bus saw limited use between 1988 and
>> 3065 1995 when it was made obsolete by the PCI bus.
>> 3066
>> 3067 Say Y here if you are building a kernel for an EISA-based machine.
>> 3068
>> 3069 Otherwise, say N.
>> 3070
>> 3071 source "drivers/eisa/Kconfig"
>> 3072
>> 3073 config TC
>> 3074 bool "TURBOchannel support"
>> 3075 depends on MACH_DECSTATION
>> 3076 help
>> 3077 TURBOchannel is a DEC (now Compaq (now HP)) bus for Alpha and MIPS
>> 3078 processors. TURBOchannel programming specifications are available
>> 3079 at:
>> 3080 <ftp://ftp.hp.com/pub/alphaserver/archive/triadd/>
>> 3081 and:
>> 3082 <http://www.computer-refuge.org/classiccmp/ftp.digital.com/pub/DEC/TriAdd/>
>> 3083 Linux driver support status is documented at:
>> 3084 <http://www.linux-mips.org/wiki/DECstation>
2181 3085
2182 config ARM64_SVE !! 3086 config MMU
2183 bool "ARM Scalable Vector Extension s !! 3087 bool
2184 default y 3088 default y
2185 help <<
2186 The Scalable Vector Extension (SVE) <<
2187 execution state which complements a <<
2188 of the base architecture to support <<
2189 additional vectorisation opportunit <<
2190 <<
2191 To enable use of this extension on <<
2192 <<
2193 On CPUs that support the SVE2 exten <<
2194 those too. <<
2195 3089
2196 Note that for architectural reasons !! 3090 config ARCH_MMAP_RND_BITS_MIN
2197 support when running on SVE capable !! 3091 default 12 if 64BIT
2198 is present in: !! 3092 default 8
2199 <<
2200 * version 1.5 and later of the AR <<
2201 * the AArch64 boot wrapper since <<
2202 ("bootwrapper: SVE: Enable SVE <<
2203 <<
2204 For other firmware implementations, <<
2205 or vendor. <<
2206 <<
2207 If you need the kernel to boot on S <<
2208 firmware, you may need to say N her <<
2209 fixed. Otherwise, you may experien <<
2210 booting the kernel. If unsure and <<
2211 symptoms, you should assume that it <<
2212 3093
2213 config ARM64_SME !! 3094 config ARCH_MMAP_RND_BITS_MAX
2214 bool "ARM Scalable Matrix Extension s !! 3095 default 18 if 64BIT
2215 default y !! 3096 default 15
2216 depends on ARM64_SVE <<
2217 depends on BROKEN <<
2218 help <<
2219 The Scalable Matrix Extension (SME) <<
2220 execution state which utilises a su <<
2221 instruction set, together with the <<
2222 register state capable of holding t <<
2223 enable various matrix operations. <<
2224 3097
2225 config ARM64_PSEUDO_NMI !! 3098 config ARCH_MMAP_RND_COMPAT_BITS_MIN
2226 bool "Support for NMI-like interrupts !! 3099 default 8
2227 select ARM_GIC_V3 <<
2228 help <<
2229 Adds support for mimicking Non-Mask <<
2230 GIC interrupt priority. This suppor <<
2231 ARM GIC. <<
2232 3100
2233 This high priority configuration fo !! 3101 config ARCH_MMAP_RND_COMPAT_BITS_MAX
2234 explicitly enabled by setting the k !! 3102 default 15
2235 "irqchip.gicv3_pseudo_nmi" to 1. <<
2236 3103
2237 If unsure, say N !! 3104 config I8253
>> 3105 bool
>> 3106 select CLKSRC_I8253
>> 3107 select CLKEVT_I8253
>> 3108 select MIPS_EXTERNAL_TIMER
2238 3109
2239 if ARM64_PSEUDO_NMI !! 3110 config ZONE_DMA
2240 config ARM64_DEBUG_PRIORITY_MASKING !! 3111 bool
2241 bool "Debug interrupt priority maskin <<
2242 help <<
2243 This adds runtime checks to functio <<
2244 interrupts when using priority mask <<
2245 the validity of ICC_PMR_EL1 when ca <<
2246 3112
2247 If unsure, say N !! 3113 config ZONE_DMA32
2248 endif # ARM64_PSEUDO_NMI !! 3114 bool
2249 3115
2250 config RELOCATABLE !! 3116 source "drivers/pcmcia/Kconfig"
2251 bool "Build a relocatable kernel imag <<
2252 select ARCH_HAS_RELR <<
2253 default y <<
2254 help <<
2255 This builds the kernel as a Positio <<
2256 which retains all relocation metada <<
2257 kernel binary at runtime to a diffe <<
2258 address it was linked at. <<
2259 Since AArch64 uses the RELA relocat <<
2260 relocation pass at runtime even if <<
2261 same address it was linked at. <<
2262 3117
2263 config RANDOMIZE_BASE !! 3118 config RAPIDIO
2264 bool "Randomize the address of the ke !! 3119 tristate "RapidIO support"
2265 select RELOCATABLE !! 3120 depends on PCI
>> 3121 default n
2266 help 3122 help
2267 Randomizes the virtual address at w !! 3123 If you say Y here, the kernel will include drivers and
2268 loaded, as a security feature that !! 3124 infrastructure code to support RapidIO interconnect devices.
2269 relying on knowledge of the locatio <<
2270 <<
2271 It is the bootloader's job to provi <<
2272 random u64 value in /chosen/kaslr-s <<
2273 <<
2274 When booting via the UEFI stub, it <<
2275 EFI_RNG_PROTOCOL implementation (if <<
2276 to the kernel proper. In addition, <<
2277 location of the kernel Image as wel <<
2278 3125
2279 If unsure, say N. !! 3126 source "drivers/rapidio/Kconfig"
2280 3127
2281 config RANDOMIZE_MODULE_REGION_FULL !! 3128 endmenu
2282 bool "Randomize the module region ove <<
2283 depends on RANDOMIZE_BASE <<
2284 default y <<
2285 help <<
2286 Randomizes the location of the modu <<
2287 covering the core kernel. This way, <<
2288 to leak information about the locat <<
2289 but it does imply that function cal <<
2290 kernel will need to be resolved via <<
2291 <<
2292 When this option is not set, the mo <<
2293 a limited range that contains the [ <<
2294 core kernel, so branch relocations <<
2295 the region is exhausted. In this pa <<
2296 exhaustion, modules might be able t <<
2297 3129
2298 config CC_HAVE_STACKPROTECTOR_SYSREG !! 3130 menu "Executable file formats"
2299 def_bool $(cc-option,-mstack-protecto <<
2300 3131
2301 config STACKPROTECTOR_PER_TASK !! 3132 source "fs/Kconfig.binfmt"
2302 def_bool y <<
2303 depends on STACKPROTECTOR && CC_HAVE_ <<
2304 3133
2305 config UNWIND_PATCH_PAC_INTO_SCS !! 3134 config TRAD_SIGNALS
2306 bool "Enable shadow call stack dynami !! 3135 bool
2307 # needs Clang with https://github.com <<
2308 depends on CC_IS_CLANG && CLANG_VERSI <<
2309 depends on ARM64_PTR_AUTH_KERNEL && C <<
2310 depends on SHADOW_CALL_STACK <<
2311 select UNWIND_TABLES <<
2312 select DYNAMIC_SCS <<
2313 <<
2314 config ARM64_CONTPTE <<
2315 bool "Contiguous PTE mappings for use <<
2316 depends on TRANSPARENT_HUGEPAGE <<
2317 default y <<
2318 help <<
2319 When enabled, user mappings are con <<
2320 bit, for any mappings that meet the <<
2321 This reduces TLB pressure and impro <<
2322 <<
2323 endmenu # "Kernel Features" <<
2324 <<
2325 menu "Boot options" <<
2326 <<
2327 config ARM64_ACPI_PARKING_PROTOCOL <<
2328 bool "Enable support for the ARM64 AC <<
2329 depends on ACPI <<
2330 help <<
2331 Enable support for the ARM64 ACPI p <<
2332 the kernel will not allow booting t <<
2333 protocol even if the corresponding <<
2334 MADT table. <<
2335 <<
2336 config CMDLINE <<
2337 string "Default kernel command string <<
2338 default "" <<
2339 help <<
2340 Provide a set of default command-li <<
2341 entering them here. As a minimum, y <<
2342 root device (e.g. root=/dev/nfs). <<
2343 3136
2344 choice !! 3137 config MIPS32_COMPAT
2345 prompt "Kernel command line type" !! 3138 bool
2346 depends on CMDLINE != "" <<
2347 default CMDLINE_FROM_BOOTLOADER <<
2348 help <<
2349 Choose how the kernel will handle t <<
2350 command line string. <<
2351 <<
2352 config CMDLINE_FROM_BOOTLOADER <<
2353 bool "Use bootloader kernel arguments <<
2354 help <<
2355 Uses the command-line options passe <<
2356 the boot loader doesn't provide any <<
2357 string provided in CMDLINE will be <<
2358 <<
2359 config CMDLINE_FORCE <<
2360 bool "Always use the default kernel c <<
2361 help <<
2362 Always use the default kernel comma <<
2363 loader passes other arguments to th <<
2364 This is useful if you cannot or don <<
2365 command-line options your boot load <<
2366 3139
2367 endchoice !! 3140 config COMPAT
>> 3141 bool
2368 3142
2369 config EFI_STUB !! 3143 config SYSVIPC_COMPAT
2370 bool 3144 bool
2371 3145
2372 config EFI !! 3146 config MIPS32_O32
2373 bool "UEFI runtime support" !! 3147 bool "Kernel support for o32 binaries"
2374 depends on OF && !CPU_BIG_ENDIAN !! 3148 depends on 64BIT
2375 depends on KERNEL_MODE_NEON !! 3149 select ARCH_WANT_OLD_COMPAT_IPC
2376 select ARCH_SUPPORTS_ACPI !! 3150 select COMPAT
2377 select LIBFDT !! 3151 select MIPS32_COMPAT
2378 select UCS2_STRING !! 3152 select SYSVIPC_COMPAT if SYSVIPC
2379 select EFI_PARAMS_FROM_FDT !! 3153 help
2380 select EFI_RUNTIME_WRAPPERS !! 3154 Select this option if you want to run o32 binaries. These are pure
2381 select EFI_STUB !! 3155 32-bit binaries as used by the 32-bit Linux/MIPS port. Most of
2382 select EFI_GENERIC_STUB !! 3156 existing binaries are in this format.
2383 imply IMA_SECURE_AND_OR_TRUSTED_BOOT <<
2384 default y <<
2385 help <<
2386 This option provides support for ru <<
2387 by UEFI firmware (such as non-volat <<
2388 clock, and platform reset). A UEFI <<
2389 allow the kernel to be booted as an <<
2390 is only useful on systems that have <<
2391 3157
2392 config COMPRESSED_INSTALL !! 3158 If unsure, say Y.
2393 bool "Install compressed image by def <<
2394 help <<
2395 This makes the regular "make instal <<
2396 image we built, not the legacy unco <<
2397 3159
2398 You can check that a compressed ima !! 3160 config MIPS32_N32
2399 "make zinstall" first, and verifyin !! 3161 bool "Kernel support for n32 binaries"
2400 in your environment before making " !! 3162 depends on 64BIT
2401 you. !! 3163 select COMPAT
>> 3164 select MIPS32_COMPAT
>> 3165 select SYSVIPC_COMPAT if SYSVIPC
>> 3166 help
>> 3167 Select this option if you want to run n32 binaries. These are
>> 3168 64-bit binaries using 32-bit quantities for addressing and certain
>> 3169 data that would normally be 64-bit. They are used in special
>> 3170 cases.
2402 3171
2403 config DMI !! 3172 If unsure, say N.
2404 bool "Enable support for SMBIOS (DMI) <<
2405 depends on EFI <<
2406 default y <<
2407 help <<
2408 This enables SMBIOS/DMI feature for <<
2409 3173
2410 This option is only useful on syste !! 3174 config BINFMT_ELF32
2411 However, even with this option, the !! 3175 bool
2412 continue to boot on existing non-UE !! 3176 default y if MIPS32_O32 || MIPS32_N32
>> 3177 select ELFCORE
2413 3178
2414 endmenu # "Boot options" !! 3179 endmenu
2415 3180
2416 menu "Power management options" 3181 menu "Power management options"
2417 3182
2418 source "kernel/power/Kconfig" <<
2419 <<
2420 config ARCH_HIBERNATION_POSSIBLE 3183 config ARCH_HIBERNATION_POSSIBLE
2421 def_bool y 3184 def_bool y
2422 depends on CPU_PM !! 3185 depends on SYS_SUPPORTS_HOTPLUG_CPU || !SMP
2423 <<
2424 config ARCH_HIBERNATION_HEADER <<
2425 def_bool y <<
2426 depends on HIBERNATION <<
2427 3186
2428 config ARCH_SUSPEND_POSSIBLE 3187 config ARCH_SUSPEND_POSSIBLE
2429 def_bool y 3188 def_bool y
>> 3189 depends on SYS_SUPPORTS_HOTPLUG_CPU || !SMP
>> 3190
>> 3191 source "kernel/power/Kconfig"
>> 3192
>> 3193 endmenu
2430 3194
2431 endmenu # "Power management options" !! 3195 config MIPS_EXTERNAL_TIMER
>> 3196 bool
2432 3197
2433 menu "CPU Power Management" 3198 menu "CPU Power Management"
2434 3199
>> 3200 if CPU_SUPPORTS_CPUFREQ && MIPS_EXTERNAL_TIMER
>> 3201 source "drivers/cpufreq/Kconfig"
>> 3202 endif
>> 3203
2435 source "drivers/cpuidle/Kconfig" 3204 source "drivers/cpuidle/Kconfig"
2436 3205
2437 source "drivers/cpufreq/Kconfig" !! 3206 endmenu
>> 3207
>> 3208 source "net/Kconfig"
>> 3209
>> 3210 source "drivers/Kconfig"
>> 3211
>> 3212 source "drivers/firmware/Kconfig"
>> 3213
>> 3214 source "fs/Kconfig"
>> 3215
>> 3216 source "arch/mips/Kconfig.debug"
2438 3217
2439 endmenu # "CPU Power Management" !! 3218 source "security/Kconfig"
2440 3219
2441 source "drivers/acpi/Kconfig" !! 3220 source "crypto/Kconfig"
2442 3221
2443 source "arch/arm64/kvm/Kconfig" !! 3222 source "lib/Kconfig"
2444 3223
>> 3224 source "arch/mips/kvm/Kconfig"
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