1 # SPDX-License-Identifier: GPL-2.0-only !! 1 # SPDX-License-Identifier: GPL-2.0
2 config ARM64 !! 2 config MIPS
3 def_bool y !! 3 bool
4 select ACPI_APMT if ACPI !! 4 default y
5 select ACPI_CCA_REQUIRED if ACPI <<
6 select ACPI_GENERIC_GSI if ACPI <<
7 select ACPI_GTDT if ACPI <<
8 select ACPI_HOTPLUG_CPU if ACPI_PROCES <<
9 select ACPI_IORT if ACPI <<
10 select ACPI_REDUCED_HARDWARE_ONLY if A <<
11 select ACPI_MCFG if (ACPI && PCI) <<
12 select ACPI_SPCR_TABLE if ACPI <<
13 select ACPI_PPTT if ACPI <<
14 select ARCH_HAS_DEBUG_WX <<
15 select ARCH_BINFMT_ELF_EXTRA_PHDRS <<
16 select ARCH_BINFMT_ELF_STATE 5 select ARCH_BINFMT_ELF_STATE
17 select ARCH_CORRECT_STACKTRACE_ON_KRET !! 6 select ARCH_CLOCKSOURCE_DATA
18 select ARCH_ENABLE_HUGEPAGE_MIGRATION !! 7 select ARCH_HAS_CPU_FINALIZE_INIT
19 select ARCH_ENABLE_MEMORY_HOTPLUG !! 8 select ARCH_DISCARD_MEMBLOCK
20 select ARCH_ENABLE_MEMORY_HOTREMOVE !! 9 select ARCH_HAS_ELF_RANDOMIZE
21 select ARCH_ENABLE_SPLIT_PMD_PTLOCK if <<
22 select ARCH_ENABLE_THP_MIGRATION if TR <<
23 select ARCH_HAS_CACHE_LINE_SIZE <<
24 select ARCH_HAS_CURRENT_STACK_POINTER <<
25 select ARCH_HAS_DEBUG_VIRTUAL <<
26 select ARCH_HAS_DEBUG_VM_PGTABLE <<
27 select ARCH_HAS_DMA_OPS if XEN <<
28 select ARCH_HAS_DMA_PREP_COHERENT <<
29 select ARCH_HAS_ACPI_TABLE_UPGRADE if <<
30 select ARCH_HAS_FAST_MULTIPLIER <<
31 select ARCH_HAS_FORTIFY_SOURCE <<
32 select ARCH_HAS_GCOV_PROFILE_ALL <<
33 select ARCH_HAS_GIGANTIC_PAGE <<
34 select ARCH_HAS_KCOV <<
35 select ARCH_HAS_KERNEL_FPU_SUPPORT if <<
36 select ARCH_HAS_KEEPINITRD <<
37 select ARCH_HAS_MEMBARRIER_SYNC_CORE <<
38 select ARCH_HAS_MEM_ENCRYPT <<
39 select ARCH_HAS_NMI_SAFE_THIS_CPU_OPS <<
40 select ARCH_HAS_NON_OVERLAPPING_ADDRES <<
41 select ARCH_HAS_PTE_DEVMAP <<
42 select ARCH_HAS_PTE_SPECIAL <<
43 select ARCH_HAS_HW_PTE_YOUNG <<
44 select ARCH_HAS_SETUP_DMA_OPS <<
45 select ARCH_HAS_SET_DIRECT_MAP <<
46 select ARCH_HAS_SET_MEMORY <<
47 select ARCH_STACKWALK <<
48 select ARCH_HAS_STRICT_KERNEL_RWX <<
49 select ARCH_HAS_STRICT_MODULE_RWX <<
50 select ARCH_HAS_SYNC_DMA_FOR_DEVICE <<
51 select ARCH_HAS_SYNC_DMA_FOR_CPU <<
52 select ARCH_HAS_SYSCALL_WRAPPER <<
53 select ARCH_HAS_TICK_BROADCAST if GENE 10 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
54 select ARCH_HAS_ZONE_DMA_SET if EXPERT !! 11 select ARCH_SUPPORTS_UPROBES
55 select ARCH_HAVE_ELF_PROT !! 12 select ARCH_USE_BUILTIN_BSWAP
56 select ARCH_HAVE_NMI_SAFE_CMPXCHG !! 13 select ARCH_USE_CMPXCHG_LOCKREF if 64BIT
57 select ARCH_HAVE_TRACE_MMIO_ACCESS <<
58 select ARCH_INLINE_READ_LOCK if !PREEM <<
59 select ARCH_INLINE_READ_LOCK_BH if !PR <<
60 select ARCH_INLINE_READ_LOCK_IRQ if !P <<
61 select ARCH_INLINE_READ_LOCK_IRQSAVE i <<
62 select ARCH_INLINE_READ_UNLOCK if !PRE <<
63 select ARCH_INLINE_READ_UNLOCK_BH if ! <<
64 select ARCH_INLINE_READ_UNLOCK_IRQ if <<
65 select ARCH_INLINE_READ_UNLOCK_IRQREST <<
66 select ARCH_INLINE_WRITE_LOCK if !PREE <<
67 select ARCH_INLINE_WRITE_LOCK_BH if !P <<
68 select ARCH_INLINE_WRITE_LOCK_IRQ if ! <<
69 select ARCH_INLINE_WRITE_LOCK_IRQSAVE <<
70 select ARCH_INLINE_WRITE_UNLOCK if !PR <<
71 select ARCH_INLINE_WRITE_UNLOCK_BH if <<
72 select ARCH_INLINE_WRITE_UNLOCK_IRQ if <<
73 select ARCH_INLINE_WRITE_UNLOCK_IRQRES <<
74 select ARCH_INLINE_SPIN_TRYLOCK if !PR <<
75 select ARCH_INLINE_SPIN_TRYLOCK_BH if <<
76 select ARCH_INLINE_SPIN_LOCK if !PREEM <<
77 select ARCH_INLINE_SPIN_LOCK_BH if !PR <<
78 select ARCH_INLINE_SPIN_LOCK_IRQ if !P <<
79 select ARCH_INLINE_SPIN_LOCK_IRQSAVE i <<
80 select ARCH_INLINE_SPIN_UNLOCK if !PRE <<
81 select ARCH_INLINE_SPIN_UNLOCK_BH if ! <<
82 select ARCH_INLINE_SPIN_UNLOCK_IRQ if <<
83 select ARCH_INLINE_SPIN_UNLOCK_IRQREST <<
84 select ARCH_KEEP_MEMBLOCK <<
85 select ARCH_MHP_MEMMAP_ON_MEMORY_ENABL <<
86 select ARCH_USE_CMPXCHG_LOCKREF <<
87 select ARCH_USE_GNU_PROPERTY <<
88 select ARCH_USE_MEMTEST <<
89 select ARCH_USE_QUEUED_RWLOCKS 14 select ARCH_USE_QUEUED_RWLOCKS
90 select ARCH_USE_QUEUED_SPINLOCKS 15 select ARCH_USE_QUEUED_SPINLOCKS
91 select ARCH_USE_SYM_ANNOTATIONS !! 16 select ARCH_WANT_IPC_PARSE_VERSION
92 select ARCH_SUPPORTS_DEBUG_PAGEALLOC !! 17 select BUILDTIME_EXTABLE_SORT
93 select ARCH_SUPPORTS_HUGETLBFS <<
94 select ARCH_SUPPORTS_MEMORY_FAILURE <<
95 select ARCH_SUPPORTS_SHADOW_CALL_STACK <<
96 select ARCH_SUPPORTS_LTO_CLANG if CPU_ <<
97 select ARCH_SUPPORTS_LTO_CLANG_THIN <<
98 select ARCH_SUPPORTS_CFI_CLANG <<
99 select ARCH_SUPPORTS_ATOMIC_RMW <<
100 select ARCH_SUPPORTS_INT128 if CC_HAS_ <<
101 select ARCH_SUPPORTS_NUMA_BALANCING <<
102 select ARCH_SUPPORTS_PAGE_TABLE_CHECK <<
103 select ARCH_SUPPORTS_PER_VMA_LOCK <<
104 select ARCH_SUPPORTS_HUGE_PFNMAP if TR <<
105 select ARCH_SUPPORTS_RT <<
106 select ARCH_WANT_BATCHED_UNMAP_TLB_FLU <<
107 select ARCH_WANT_COMPAT_IPC_PARSE_VERS <<
108 select ARCH_WANT_DEFAULT_BPF_JIT <<
109 select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_ <<
110 select ARCH_WANT_FRAME_POINTERS <<
111 select ARCH_WANT_HUGE_PMD_SHARE if ARM <<
112 select ARCH_WANT_LD_ORPHAN_WARN <<
113 select ARCH_WANTS_EXECMEM_LATE if EXEC <<
114 select ARCH_WANTS_NO_INSTR <<
115 select ARCH_WANTS_THP_SWAP if ARM64_4K <<
116 select ARCH_HAS_UBSAN <<
117 select ARM_AMBA <<
118 select ARM_ARCH_TIMER <<
119 select ARM_GIC <<
120 select AUDIT_ARCH_COMPAT_GENERIC <<
121 select ARM_GIC_V2M if PCI <<
122 select ARM_GIC_V3 <<
123 select ARM_GIC_V3_ITS if PCI <<
124 select ARM_PSCI_FW <<
125 select BUILDTIME_TABLE_SORT <<
126 select CLONE_BACKWARDS 18 select CLONE_BACKWARDS
127 select COMMON_CLK !! 19 select CPU_PM if CPU_IDLE
128 select CPU_PM if (SUSPEND || CPU_IDLE) !! 20 select DMA_DIRECT_OPS
129 select CPUMASK_OFFSTACK if NR_CPUS > 2 !! 21 select GENERIC_ATOMIC64 if !64BIT
130 select CRC32 !! 22 select GENERIC_CLOCKEVENTS
131 select DCACHE_WORD_ACCESS !! 23 select GENERIC_CMOS_UPDATE
132 select DYNAMIC_FTRACE if FUNCTION_TRAC <<
133 select DMA_BOUNCE_UNALIGNED_KMALLOC <<
134 select DMA_DIRECT_REMAP <<
135 select EDAC_SUPPORT <<
136 select FRAME_POINTER <<
137 select FUNCTION_ALIGNMENT_4B <<
138 select FUNCTION_ALIGNMENT_8B if DYNAMI <<
139 select GENERIC_ALLOCATOR <<
140 select GENERIC_ARCH_TOPOLOGY <<
141 select GENERIC_CLOCKEVENTS_BROADCAST <<
142 select GENERIC_CPU_AUTOPROBE 24 select GENERIC_CPU_AUTOPROBE
143 select GENERIC_CPU_DEVICES <<
144 select GENERIC_CPU_VULNERABILITIES <<
145 select GENERIC_EARLY_IOREMAP <<
146 select GENERIC_IDLE_POLL_SETUP <<
147 select GENERIC_IOREMAP <<
148 select GENERIC_IRQ_IPI <<
149 select GENERIC_IRQ_PROBE 25 select GENERIC_IRQ_PROBE
150 select GENERIC_IRQ_SHOW 26 select GENERIC_IRQ_SHOW
151 select GENERIC_IRQ_SHOW_LEVEL !! 27 select GENERIC_LIB_ASHLDI3
152 select GENERIC_LIB_DEVMEM_IS_ALLOWED !! 28 select GENERIC_LIB_ASHRDI3
>> 29 select GENERIC_LIB_CMPDI2
>> 30 select GENERIC_LIB_LSHRDI3
>> 31 select GENERIC_LIB_UCMPDI2
153 select GENERIC_PCI_IOMAP 32 select GENERIC_PCI_IOMAP
154 select GENERIC_PTDUMP !! 33 select GENERIC_SCHED_CLOCK if !CAVIUM_OCTEON_SOC
155 select GENERIC_SCHED_CLOCK <<
156 select GENERIC_SMP_IDLE_THREAD 34 select GENERIC_SMP_IDLE_THREAD
157 select GENERIC_TIME_VSYSCALL 35 select GENERIC_TIME_VSYSCALL
158 select GENERIC_GETTIMEOFDAY !! 36 select HANDLE_DOMAIN_IRQ
159 select GENERIC_VDSO_TIME_NS <<
160 select HARDIRQS_SW_RESEND <<
161 select HAS_IOPORT <<
162 select HAVE_MOVE_PMD <<
163 select HAVE_MOVE_PUD <<
164 select HAVE_PCI <<
165 select HAVE_ACPI_APEI if (ACPI && EFI) <<
166 select HAVE_ALIGNED_STRUCT_PAGE <<
167 select HAVE_ARCH_AUDITSYSCALL <<
168 select HAVE_ARCH_BITREVERSE <<
169 select HAVE_ARCH_COMPILER_H 37 select HAVE_ARCH_COMPILER_H
170 select HAVE_ARCH_HUGE_VMALLOC <<
171 select HAVE_ARCH_HUGE_VMAP <<
172 select HAVE_ARCH_JUMP_LABEL 38 select HAVE_ARCH_JUMP_LABEL
173 select HAVE_ARCH_JUMP_LABEL_RELATIVE <<
174 select HAVE_ARCH_KASAN <<
175 select HAVE_ARCH_KASAN_VMALLOC <<
176 select HAVE_ARCH_KASAN_SW_TAGS <<
177 select HAVE_ARCH_KASAN_HW_TAGS if ARM6 <<
178 # Some instrumentation may be unsound, <<
179 select HAVE_ARCH_KCSAN if EXPERT <<
180 select HAVE_ARCH_KFENCE <<
181 select HAVE_ARCH_KGDB 39 select HAVE_ARCH_KGDB
182 select HAVE_ARCH_MMAP_RND_BITS !! 40 select HAVE_ARCH_MMAP_RND_BITS if MMU
183 select HAVE_ARCH_MMAP_RND_COMPAT_BITS !! 41 select HAVE_ARCH_MMAP_RND_COMPAT_BITS if MMU && COMPAT
184 select HAVE_ARCH_PREL32_RELOCATIONS <<
185 select HAVE_ARCH_RANDOMIZE_KSTACK_OFFS <<
186 select HAVE_ARCH_SECCOMP_FILTER 42 select HAVE_ARCH_SECCOMP_FILTER
187 select HAVE_ARCH_STACKLEAK <<
188 select HAVE_ARCH_THREAD_STRUCT_WHITELI <<
189 select HAVE_ARCH_TRACEHOOK 43 select HAVE_ARCH_TRACEHOOK
190 select HAVE_ARCH_TRANSPARENT_HUGEPAGE !! 44 select HAVE_ARCH_TRANSPARENT_HUGEPAGE if CPU_SUPPORTS_HUGEPAGES && 64BIT
191 select HAVE_ARCH_VMAP_STACK !! 45 select HAVE_CBPF_JIT if (!64BIT && !CPU_MICROMIPS)
192 select HAVE_ARM_SMCCC !! 46 select HAVE_EBPF_JIT if (64BIT && !CPU_MICROMIPS)
193 select HAVE_ASM_MODVERSIONS !! 47 select HAVE_CONTEXT_TRACKING
194 select HAVE_EBPF_JIT !! 48 select HAVE_COPY_THREAD_TLS
195 select HAVE_C_RECORDMCOUNT 49 select HAVE_C_RECORDMCOUNT
196 select HAVE_CMPXCHG_DOUBLE <<
197 select HAVE_CMPXCHG_LOCAL <<
198 select HAVE_CONTEXT_TRACKING_USER <<
199 select HAVE_DEBUG_KMEMLEAK 50 select HAVE_DEBUG_KMEMLEAK
>> 51 select HAVE_DEBUG_STACKOVERFLOW
200 select HAVE_DMA_CONTIGUOUS 52 select HAVE_DMA_CONTIGUOUS
201 select HAVE_DYNAMIC_FTRACE 53 select HAVE_DYNAMIC_FTRACE
202 select HAVE_DYNAMIC_FTRACE_WITH_ARGS \ !! 54 select HAVE_EXIT_THREAD
203 if (GCC_SUPPORTS_DYNAMIC_FTRAC <<
204 CLANG_SUPPORTS_DYNAMIC_FTR <<
205 select HAVE_DYNAMIC_FTRACE_WITH_DIRECT <<
206 if DYNAMIC_FTRACE_WITH_ARGS && <<
207 select HAVE_DYNAMIC_FTRACE_WITH_CALL_O <<
208 if (DYNAMIC_FTRACE_WITH_ARGS & <<
209 (CC_IS_CLANG || !CC_OPTIMI <<
210 select FTRACE_MCOUNT_USE_PATCHABLE_FUN <<
211 if DYNAMIC_FTRACE_WITH_ARGS <<
212 select HAVE_SAMPLE_FTRACE_DIRECT <<
213 select HAVE_SAMPLE_FTRACE_DIRECT_MULTI <<
214 select HAVE_EFFICIENT_UNALIGNED_ACCESS <<
215 select HAVE_GUP_FAST <<
216 select HAVE_FTRACE_MCOUNT_RECORD 55 select HAVE_FTRACE_MCOUNT_RECORD
217 select HAVE_FUNCTION_TRACER <<
218 select HAVE_FUNCTION_ERROR_INJECTION <<
219 select HAVE_FUNCTION_GRAPH_TRACER 56 select HAVE_FUNCTION_GRAPH_TRACER
220 select HAVE_FUNCTION_GRAPH_RETVAL !! 57 select HAVE_FUNCTION_TRACER
221 select HAVE_GCC_PLUGINS !! 58 select HAVE_GENERIC_DMA_COHERENT
222 select HAVE_HARDLOCKUP_DETECTOR_PERF i !! 59 select HAVE_IDE
223 HW_PERF_EVENTS && HAVE_PERF_EV !! 60 select HAVE_IRQ_EXIT_ON_IRQ_STACK
224 select HAVE_HW_BREAKPOINT if PERF_EVEN <<
225 select HAVE_IOREMAP_PROT <<
226 select HAVE_IRQ_TIME_ACCOUNTING 61 select HAVE_IRQ_TIME_ACCOUNTING
>> 62 select HAVE_KPROBES
>> 63 select HAVE_KRETPROBES
>> 64 select HAVE_MEMBLOCK
>> 65 select HAVE_MEMBLOCK_NODE_MAP
227 select HAVE_MOD_ARCH_SPECIFIC 66 select HAVE_MOD_ARCH_SPECIFIC
228 select HAVE_NMI 67 select HAVE_NMI
>> 68 select HAVE_OPROFILE
229 select HAVE_PERF_EVENTS 69 select HAVE_PERF_EVENTS
230 select HAVE_PERF_EVENTS_NMI if ARM64_P <<
231 select HAVE_PERF_REGS <<
232 select HAVE_PERF_USER_STACK_DUMP <<
233 select HAVE_PREEMPT_DYNAMIC_KEY <<
234 select HAVE_REGS_AND_STACK_ACCESS_API 70 select HAVE_REGS_AND_STACK_ACCESS_API
235 select HAVE_POSIX_CPU_TIMERS_TASK_WORK <<
236 select HAVE_FUNCTION_ARG_ACCESS_API <<
237 select MMU_GATHER_RCU_TABLE_FREE <<
238 select HAVE_RSEQ 71 select HAVE_RSEQ
239 select HAVE_RUST if RUSTC_SUPPORTS_ARM <<
240 select HAVE_STACKPROTECTOR 72 select HAVE_STACKPROTECTOR
241 select HAVE_SYSCALL_TRACEPOINTS 73 select HAVE_SYSCALL_TRACEPOINTS
242 select HAVE_KPROBES !! 74 select HAVE_VIRT_CPU_ACCOUNTING_GEN if 64BIT || !SMP
243 select HAVE_KRETPROBES <<
244 select HAVE_GENERIC_VDSO <<
245 select HOTPLUG_CORE_SYNC_DEAD if HOTPL <<
246 select IRQ_DOMAIN <<
247 select IRQ_FORCED_THREADING 75 select IRQ_FORCED_THREADING
248 select KASAN_VMALLOC if KASAN !! 76 select MODULES_USE_ELF_RELA if MODULES && 64BIT
249 select LOCK_MM_AND_FIND_VMA !! 77 select MODULES_USE_ELF_REL if MODULES
250 select MODULES_USE_ELF_RELA !! 78 select PERF_USE_VMALLOC
251 select NEED_DMA_MAP_STATE !! 79 select RTC_LIB if !MACH_LOONGSON64
252 select NEED_SG_DMA_LENGTH <<
253 select OF <<
254 select OF_EARLY_FLATTREE <<
255 select PCI_DOMAINS_GENERIC if PCI <<
256 select PCI_ECAM if (ACPI && PCI) <<
257 select PCI_SYSCALL if PCI <<
258 select POWER_RESET <<
259 select POWER_SUPPLY <<
260 select SPARSE_IRQ <<
261 select SWIOTLB <<
262 select SYSCTL_EXCEPTION_TRACE 80 select SYSCTL_EXCEPTION_TRACE
263 select THREAD_INFO_IN_TASK !! 81 select VIRT_TO_BUS
264 select HAVE_ARCH_USERFAULTFD_MINOR if <<
265 select HAVE_ARCH_USERFAULTFD_WP if USE <<
266 select TRACE_IRQFLAGS_SUPPORT <<
267 select TRACE_IRQFLAGS_NMI_SUPPORT <<
268 select HAVE_SOFTIRQ_ON_OWN_STACK <<
269 select USER_STACKTRACE_SUPPORT <<
270 select VDSO_GETRANDOM <<
271 help <<
272 ARM 64-bit (AArch64) Linux support. <<
273 <<
274 config RUSTC_SUPPORTS_ARM64 <<
275 def_bool y <<
276 depends on CPU_LITTLE_ENDIAN <<
277 # Shadow call stack is only supported <<
278 # <<
279 # When using the UNWIND_PATCH_PAC_INTO <<
280 # required due to use of the -Zfixed-x <<
281 # <<
282 # Otherwise, rustc version 1.82+ is re <<
283 # -Zsanitizer=shadow-call-stack flag. <<
284 depends on !SHADOW_CALL_STACK || RUSTC <<
285 <<
286 config CLANG_SUPPORTS_DYNAMIC_FTRACE_WITH_ARGS <<
287 def_bool CC_IS_CLANG <<
288 # https://github.com/ClangBuiltLinux/l <<
289 depends on AS_IS_GNU || (AS_IS_LLVM && <<
290 <<
291 config GCC_SUPPORTS_DYNAMIC_FTRACE_WITH_ARGS <<
292 def_bool CC_IS_GCC <<
293 depends on $(cc-option,-fpatchable-fun <<
294 <<
295 config 64BIT <<
296 def_bool y <<
297 <<
298 config MMU <<
299 def_bool y <<
300 <<
301 config ARM64_CONT_PTE_SHIFT <<
302 int <<
303 default 5 if PAGE_SIZE_64KB <<
304 default 7 if PAGE_SIZE_16KB <<
305 default 4 <<
306 <<
307 config ARM64_CONT_PMD_SHIFT <<
308 int <<
309 default 5 if PAGE_SIZE_64KB <<
310 default 5 if PAGE_SIZE_16KB <<
311 default 4 <<
312 <<
313 config ARCH_MMAP_RND_BITS_MIN <<
314 default 14 if PAGE_SIZE_64KB <<
315 default 16 if PAGE_SIZE_16KB <<
316 default 18 <<
317 <<
318 # max bits determined by the following formula <<
319 # VA_BITS - PAGE_SHIFT - 3 <<
320 config ARCH_MMAP_RND_BITS_MAX <<
321 default 19 if ARM64_VA_BITS=36 <<
322 default 24 if ARM64_VA_BITS=39 <<
323 default 27 if ARM64_VA_BITS=42 <<
324 default 30 if ARM64_VA_BITS=47 <<
325 default 29 if ARM64_VA_BITS=48 && ARM6 <<
326 default 31 if ARM64_VA_BITS=48 && ARM6 <<
327 default 33 if ARM64_VA_BITS=48 <<
328 default 14 if ARM64_64K_PAGES <<
329 default 16 if ARM64_16K_PAGES <<
330 default 18 <<
331 <<
332 config ARCH_MMAP_RND_COMPAT_BITS_MIN <<
333 default 7 if ARM64_64K_PAGES <<
334 default 9 if ARM64_16K_PAGES <<
335 default 11 <<
336 <<
337 config ARCH_MMAP_RND_COMPAT_BITS_MAX <<
338 default 16 <<
339 <<
340 config NO_IOPORT_MAP <<
341 def_bool y if !PCI <<
342 <<
343 config STACKTRACE_SUPPORT <<
344 def_bool y <<
345 <<
346 config ILLEGAL_POINTER_VALUE <<
347 hex <<
348 default 0xdead000000000000 <<
349 <<
350 config LOCKDEP_SUPPORT <<
351 def_bool y <<
352 <<
353 config GENERIC_BUG <<
354 def_bool y <<
355 depends on BUG <<
356 82
357 config GENERIC_BUG_RELATIVE_POINTERS !! 83 menu "Machine selection"
358 def_bool y <<
359 depends on GENERIC_BUG <<
360 84
361 config GENERIC_HWEIGHT !! 85 choice
362 def_bool y !! 86 prompt "System type"
363 !! 87 default MIPS_GENERIC
364 config GENERIC_CSUM <<
365 def_bool y <<
366 88
367 config GENERIC_CALIBRATE_DELAY !! 89 config MIPS_GENERIC
368 def_bool y !! 90 bool "Generic board-agnostic MIPS kernel"
>> 91 select BOOT_RAW
>> 92 select BUILTIN_DTB
>> 93 select CEVT_R4K
>> 94 select CLKSRC_MIPS_GIC
>> 95 select COMMON_CLK
>> 96 select CPU_MIPSR2_IRQ_VI
>> 97 select CPU_MIPSR2_IRQ_EI
>> 98 select CSRC_R4K
>> 99 select DMA_PERDEV_COHERENT
>> 100 select HW_HAS_PCI
>> 101 select IRQ_MIPS_CPU
>> 102 select LIBFDT
>> 103 select MIPS_AUTO_PFN_OFFSET
>> 104 select MIPS_CPU_SCACHE
>> 105 select MIPS_GIC
>> 106 select MIPS_L1_CACHE_SHIFT_7
>> 107 select NO_EXCEPT_FILL
>> 108 select PCI_DRIVERS_GENERIC
>> 109 select PINCTRL
>> 110 select SMP_UP if SMP
>> 111 select SWAP_IO_SPACE
>> 112 select SYS_HAS_CPU_MIPS32_R1
>> 113 select SYS_HAS_CPU_MIPS32_R2
>> 114 select SYS_HAS_CPU_MIPS32_R6
>> 115 select SYS_HAS_CPU_MIPS64_R1
>> 116 select SYS_HAS_CPU_MIPS64_R2
>> 117 select SYS_HAS_CPU_MIPS64_R6
>> 118 select SYS_SUPPORTS_32BIT_KERNEL
>> 119 select SYS_SUPPORTS_64BIT_KERNEL
>> 120 select SYS_SUPPORTS_BIG_ENDIAN
>> 121 select SYS_SUPPORTS_HIGHMEM
>> 122 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 123 select SYS_SUPPORTS_MICROMIPS
>> 124 select SYS_SUPPORTS_MIPS_CPS
>> 125 select SYS_SUPPORTS_MIPS16
>> 126 select SYS_SUPPORTS_MULTITHREADING
>> 127 select SYS_SUPPORTS_RELOCATABLE
>> 128 select SYS_SUPPORTS_SMARTMIPS
>> 129 select USB_EHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
>> 130 select USB_EHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 131 select USB_OHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
>> 132 select USB_OHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 133 select USB_UHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
>> 134 select USB_UHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 135 select USE_OF
>> 136 help
>> 137 Select this to build a kernel which aims to support multiple boards,
>> 138 generally using a flattened device tree passed from the bootloader
>> 139 using the boot protocol defined in the UHI (Unified Hosting
>> 140 Interface) specification.
>> 141
>> 142 config MIPS_ALCHEMY
>> 143 bool "Alchemy processor based machines"
>> 144 select PHYS_ADDR_T_64BIT
>> 145 select CEVT_R4K
>> 146 select CSRC_R4K
>> 147 select IRQ_MIPS_CPU
>> 148 select DMA_MAYBE_COHERENT # Au1000,1500,1100 aren't, rest is
>> 149 select SYS_HAS_CPU_MIPS32_R1
>> 150 select SYS_SUPPORTS_32BIT_KERNEL
>> 151 select SYS_SUPPORTS_APM_EMULATION
>> 152 select GPIOLIB
>> 153 select SYS_SUPPORTS_ZBOOT
>> 154 select COMMON_CLK
369 155
370 config SMP !! 156 config AR7
371 def_bool y !! 157 bool "Texas Instruments AR7"
>> 158 select BOOT_ELF32
>> 159 select DMA_NONCOHERENT
>> 160 select CEVT_R4K
>> 161 select CSRC_R4K
>> 162 select IRQ_MIPS_CPU
>> 163 select NO_EXCEPT_FILL
>> 164 select SWAP_IO_SPACE
>> 165 select SYS_HAS_CPU_MIPS32_R1
>> 166 select SYS_HAS_EARLY_PRINTK
>> 167 select SYS_SUPPORTS_32BIT_KERNEL
>> 168 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 169 select SYS_SUPPORTS_MIPS16
>> 170 select SYS_SUPPORTS_ZBOOT_UART16550
>> 171 select GPIOLIB
>> 172 select VLYNQ
>> 173 select HAVE_CLK
>> 174 help
>> 175 Support for the Texas Instruments AR7 System-on-a-Chip
>> 176 family: TNETD7100, 7200 and 7300.
>> 177
>> 178 config ATH25
>> 179 bool "Atheros AR231x/AR531x SoC support"
>> 180 select CEVT_R4K
>> 181 select CSRC_R4K
>> 182 select DMA_NONCOHERENT
>> 183 select IRQ_MIPS_CPU
>> 184 select IRQ_DOMAIN
>> 185 select SYS_HAS_CPU_MIPS32_R1
>> 186 select SYS_SUPPORTS_BIG_ENDIAN
>> 187 select SYS_SUPPORTS_32BIT_KERNEL
>> 188 select SYS_HAS_EARLY_PRINTK
>> 189 help
>> 190 Support for Atheros AR231x and Atheros AR531x based boards
>> 191
>> 192 config ATH79
>> 193 bool "Atheros AR71XX/AR724X/AR913X based boards"
>> 194 select ARCH_HAS_RESET_CONTROLLER
>> 195 select BOOT_RAW
>> 196 select CEVT_R4K
>> 197 select CSRC_R4K
>> 198 select DMA_NONCOHERENT
>> 199 select GPIOLIB
>> 200 select PINCTRL
>> 201 select HAVE_CLK
>> 202 select COMMON_CLK
>> 203 select CLKDEV_LOOKUP
>> 204 select IRQ_MIPS_CPU
>> 205 select MIPS_MACHINE
>> 206 select SYS_HAS_CPU_MIPS32_R2
>> 207 select SYS_HAS_EARLY_PRINTK
>> 208 select SYS_SUPPORTS_32BIT_KERNEL
>> 209 select SYS_SUPPORTS_BIG_ENDIAN
>> 210 select SYS_SUPPORTS_MIPS16
>> 211 select SYS_SUPPORTS_ZBOOT_UART_PROM
>> 212 select USE_OF
>> 213 select USB_EHCI_ROOT_HUB_TT if USB_EHCI_HCD_PLATFORM
>> 214 help
>> 215 Support for the Atheros AR71XX/AR724X/AR913X SoCs.
>> 216
>> 217 config BMIPS_GENERIC
>> 218 bool "Broadcom Generic BMIPS kernel"
>> 219 select ARCH_HAS_SYNC_DMA_FOR_CPU_ALL
>> 220 select ARCH_HAS_PHYS_TO_DMA
>> 221 select BOOT_RAW
>> 222 select NO_EXCEPT_FILL
>> 223 select USE_OF
>> 224 select CEVT_R4K
>> 225 select CSRC_R4K
>> 226 select SYNC_R4K
>> 227 select COMMON_CLK
>> 228 select BCM6345_L1_IRQ
>> 229 select BCM7038_L1_IRQ
>> 230 select BCM7120_L2_IRQ
>> 231 select BRCMSTB_L2_IRQ
>> 232 select IRQ_MIPS_CPU
>> 233 select DMA_NONCOHERENT
>> 234 select SYS_SUPPORTS_32BIT_KERNEL
>> 235 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 236 select SYS_SUPPORTS_BIG_ENDIAN
>> 237 select SYS_SUPPORTS_HIGHMEM
>> 238 select SYS_HAS_CPU_BMIPS32_3300
>> 239 select SYS_HAS_CPU_BMIPS4350
>> 240 select SYS_HAS_CPU_BMIPS4380
>> 241 select SYS_HAS_CPU_BMIPS5000
>> 242 select SWAP_IO_SPACE
>> 243 select USB_EHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
>> 244 select USB_EHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 245 select USB_OHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
>> 246 select USB_OHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 247 select HARDIRQS_SW_RESEND
>> 248 help
>> 249 Build a generic DT-based kernel image that boots on select
>> 250 BCM33xx cable modem chips, BCM63xx DSL chips, and BCM7xxx set-top
>> 251 box chips. Note that CONFIG_CPU_BIG_ENDIAN/CONFIG_CPU_LITTLE_ENDIAN
>> 252 must be set appropriately for your board.
>> 253
>> 254 config BCM47XX
>> 255 bool "Broadcom BCM47XX based boards"
>> 256 select BOOT_RAW
>> 257 select CEVT_R4K
>> 258 select CSRC_R4K
>> 259 select DMA_NONCOHERENT
>> 260 select HW_HAS_PCI
>> 261 select IRQ_MIPS_CPU
>> 262 select SYS_HAS_CPU_MIPS32_R1
>> 263 select NO_EXCEPT_FILL
>> 264 select SYS_SUPPORTS_32BIT_KERNEL
>> 265 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 266 select SYS_SUPPORTS_MIPS16
>> 267 select SYS_SUPPORTS_ZBOOT
>> 268 select SYS_HAS_EARLY_PRINTK
>> 269 select USE_GENERIC_EARLY_PRINTK_8250
>> 270 select GPIOLIB
>> 271 select LEDS_GPIO_REGISTER
>> 272 select BCM47XX_NVRAM
>> 273 select BCM47XX_SPROM
>> 274 select BCM47XX_SSB if !BCM47XX_BCMA
>> 275 help
>> 276 Support for BCM47XX based boards
>> 277
>> 278 config BCM63XX
>> 279 bool "Broadcom BCM63XX based boards"
>> 280 select BOOT_RAW
>> 281 select CEVT_R4K
>> 282 select CSRC_R4K
>> 283 select SYNC_R4K
>> 284 select DMA_NONCOHERENT
>> 285 select IRQ_MIPS_CPU
>> 286 select SYS_SUPPORTS_32BIT_KERNEL
>> 287 select SYS_SUPPORTS_BIG_ENDIAN
>> 288 select SYS_HAS_EARLY_PRINTK
>> 289 select SYS_HAS_CPU_BMIPS32_3300
>> 290 select SYS_HAS_CPU_BMIPS4350
>> 291 select SYS_HAS_CPU_BMIPS4380
>> 292 select SWAP_IO_SPACE
>> 293 select GPIOLIB
>> 294 select HAVE_CLK
>> 295 select MIPS_L1_CACHE_SHIFT_4
>> 296 select CLKDEV_LOOKUP
>> 297 help
>> 298 Support for BCM63XX based boards
>> 299
>> 300 config MIPS_COBALT
>> 301 bool "Cobalt Server"
>> 302 select CEVT_R4K
>> 303 select CSRC_R4K
>> 304 select CEVT_GT641XX
>> 305 select DMA_NONCOHERENT
>> 306 select HW_HAS_PCI
>> 307 select I8253
>> 308 select I8259
>> 309 select IRQ_MIPS_CPU
>> 310 select IRQ_GT641XX
>> 311 select PCI_GT64XXX_PCI0
>> 312 select PCI
>> 313 select SYS_HAS_CPU_NEVADA
>> 314 select SYS_HAS_EARLY_PRINTK
>> 315 select SYS_SUPPORTS_32BIT_KERNEL
>> 316 select SYS_SUPPORTS_64BIT_KERNEL
>> 317 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 318 select USE_GENERIC_EARLY_PRINTK_8250
>> 319
>> 320 config MACH_DECSTATION
>> 321 bool "DECstations"
>> 322 select BOOT_ELF32
>> 323 select CEVT_DS1287
>> 324 select CEVT_R4K if CPU_R4X00
>> 325 select CSRC_IOASIC
>> 326 select CSRC_R4K if CPU_R4X00
>> 327 select CPU_DADDI_WORKAROUNDS if 64BIT
>> 328 select CPU_R4000_WORKAROUNDS if 64BIT
>> 329 select CPU_R4400_WORKAROUNDS if 64BIT
>> 330 select DMA_NONCOHERENT
>> 331 select NO_IOPORT_MAP
>> 332 select IRQ_MIPS_CPU
>> 333 select SYS_HAS_CPU_R3000
>> 334 select SYS_HAS_CPU_R4X00
>> 335 select SYS_SUPPORTS_32BIT_KERNEL
>> 336 select SYS_SUPPORTS_64BIT_KERNEL
>> 337 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 338 select SYS_SUPPORTS_128HZ
>> 339 select SYS_SUPPORTS_256HZ
>> 340 select SYS_SUPPORTS_1024HZ
>> 341 select MIPS_L1_CACHE_SHIFT_4
>> 342 help
>> 343 This enables support for DEC's MIPS based workstations. For details
>> 344 see the Linux/MIPS FAQ on <http://www.linux-mips.org/> and the
>> 345 DECstation porting pages on <http://decstation.unix-ag.org/>.
>> 346
>> 347 If you have one of the following DECstation Models you definitely
>> 348 want to choose R4xx0 for the CPU Type:
>> 349
>> 350 DECstation 5000/50
>> 351 DECstation 5000/150
>> 352 DECstation 5000/260
>> 353 DECsystem 5900/260
>> 354
>> 355 otherwise choose R3000.
>> 356
>> 357 config MACH_JAZZ
>> 358 bool "Jazz family of machines"
>> 359 select ARCH_MIGHT_HAVE_PC_PARPORT
>> 360 select ARCH_MIGHT_HAVE_PC_SERIO
>> 361 select FW_ARC
>> 362 select FW_ARC32
>> 363 select ARCH_MAY_HAVE_PC_FDC
>> 364 select CEVT_R4K
>> 365 select CSRC_R4K
>> 366 select DEFAULT_SGI_PARTITION if CPU_BIG_ENDIAN
>> 367 select GENERIC_ISA_DMA
>> 368 select HAVE_PCSPKR_PLATFORM
>> 369 select IRQ_MIPS_CPU
>> 370 select I8253
>> 371 select I8259
>> 372 select ISA
>> 373 select SYS_HAS_CPU_R4X00
>> 374 select SYS_SUPPORTS_32BIT_KERNEL
>> 375 select SYS_SUPPORTS_64BIT_KERNEL
>> 376 select SYS_SUPPORTS_100HZ
>> 377 help
>> 378 This a family of machines based on the MIPS R4030 chipset which was
>> 379 used by several vendors to build RISC/os and Windows NT workstations.
>> 380 Members include the Acer PICA, MIPS Magnum 4000, MIPS Millennium and
>> 381 Olivetti M700-10 workstations.
>> 382
>> 383 config MACH_INGENIC
>> 384 bool "Ingenic SoC based machines"
>> 385 select SYS_SUPPORTS_32BIT_KERNEL
>> 386 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 387 select SYS_SUPPORTS_ZBOOT_UART16550
>> 388 select DMA_NONCOHERENT
>> 389 select IRQ_MIPS_CPU
>> 390 select PINCTRL
>> 391 select GPIOLIB
>> 392 select COMMON_CLK
>> 393 select GENERIC_IRQ_CHIP
>> 394 select BUILTIN_DTB
>> 395 select USE_OF
>> 396 select LIBFDT
372 397
373 config KERNEL_MODE_NEON !! 398 config LANTIQ
374 def_bool y !! 399 bool "Lantiq based platforms"
>> 400 select DMA_NONCOHERENT
>> 401 select IRQ_MIPS_CPU
>> 402 select CEVT_R4K
>> 403 select CSRC_R4K
>> 404 select SYS_HAS_CPU_MIPS32_R1
>> 405 select SYS_HAS_CPU_MIPS32_R2
>> 406 select SYS_SUPPORTS_BIG_ENDIAN
>> 407 select SYS_SUPPORTS_32BIT_KERNEL
>> 408 select SYS_SUPPORTS_MIPS16
>> 409 select SYS_SUPPORTS_MULTITHREADING
>> 410 select SYS_SUPPORTS_VPE_LOADER
>> 411 select SYS_HAS_EARLY_PRINTK
>> 412 select GPIOLIB
>> 413 select SWAP_IO_SPACE
>> 414 select BOOT_RAW
>> 415 select CLKDEV_LOOKUP
>> 416 select USE_OF
>> 417 select PINCTRL
>> 418 select PINCTRL_LANTIQ
>> 419 select ARCH_HAS_RESET_CONTROLLER
>> 420 select RESET_CONTROLLER
>> 421
>> 422 config LASAT
>> 423 bool "LASAT Networks platforms"
>> 424 select CEVT_R4K
>> 425 select CRC32
>> 426 select CSRC_R4K
>> 427 select DMA_NONCOHERENT
>> 428 select SYS_HAS_EARLY_PRINTK
>> 429 select HW_HAS_PCI
>> 430 select IRQ_MIPS_CPU
>> 431 select PCI_GT64XXX_PCI0
>> 432 select MIPS_NILE4
>> 433 select R5000_CPU_SCACHE
>> 434 select SYS_HAS_CPU_R5000
>> 435 select SYS_SUPPORTS_32BIT_KERNEL
>> 436 select SYS_SUPPORTS_64BIT_KERNEL if BROKEN
>> 437 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 438
>> 439 config MACH_LOONGSON32
>> 440 bool "Loongson-1 family of machines"
>> 441 select SYS_SUPPORTS_ZBOOT
>> 442 help
>> 443 This enables support for the Loongson-1 family of machines.
>> 444
>> 445 Loongson-1 is a family of 32-bit MIPS-compatible SoCs developed by
>> 446 the Institute of Computing Technology (ICT), Chinese Academy of
>> 447 Sciences (CAS).
>> 448
>> 449 config MACH_LOONGSON64
>> 450 bool "Loongson-2/3 family of machines"
>> 451 select SYS_SUPPORTS_ZBOOT
>> 452 help
>> 453 This enables the support of Loongson-2/3 family of machines.
>> 454
>> 455 Loongson-2 is a family of single-core CPUs and Loongson-3 is a
>> 456 family of multi-core CPUs. They are both 64-bit general-purpose
>> 457 MIPS-compatible CPUs. Loongson-2/3 are developed by the Institute
>> 458 of Computing Technology (ICT), Chinese Academy of Sciences (CAS)
>> 459 in the People's Republic of China. The chief architect is Professor
>> 460 Weiwu Hu.
>> 461
>> 462 config MACH_PISTACHIO
>> 463 bool "IMG Pistachio SoC based boards"
>> 464 select BOOT_ELF32
>> 465 select BOOT_RAW
>> 466 select CEVT_R4K
>> 467 select CLKSRC_MIPS_GIC
>> 468 select COMMON_CLK
>> 469 select CSRC_R4K
>> 470 select DMA_NONCOHERENT
>> 471 select GPIOLIB
>> 472 select IRQ_MIPS_CPU
>> 473 select LIBFDT
>> 474 select MFD_SYSCON
>> 475 select MIPS_CPU_SCACHE
>> 476 select MIPS_GIC
>> 477 select PINCTRL
>> 478 select REGULATOR
>> 479 select SYS_HAS_CPU_MIPS32_R2
>> 480 select SYS_SUPPORTS_32BIT_KERNEL
>> 481 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 482 select SYS_SUPPORTS_MIPS_CPS
>> 483 select SYS_SUPPORTS_MULTITHREADING
>> 484 select SYS_SUPPORTS_RELOCATABLE
>> 485 select SYS_SUPPORTS_ZBOOT
>> 486 select SYS_HAS_EARLY_PRINTK
>> 487 select USE_GENERIC_EARLY_PRINTK_8250
>> 488 select USE_OF
>> 489 help
>> 490 This enables support for the IMG Pistachio SoC platform.
>> 491
>> 492 config MIPS_MALTA
>> 493 bool "MIPS Malta board"
>> 494 select ARCH_MAY_HAVE_PC_FDC
>> 495 select ARCH_MIGHT_HAVE_PC_PARPORT
>> 496 select ARCH_MIGHT_HAVE_PC_SERIO
>> 497 select BOOT_ELF32
>> 498 select BOOT_RAW
>> 499 select BUILTIN_DTB
>> 500 select CEVT_R4K
>> 501 select CSRC_R4K
>> 502 select CLKSRC_MIPS_GIC
>> 503 select COMMON_CLK
>> 504 select DMA_MAYBE_COHERENT
>> 505 select GENERIC_ISA_DMA
>> 506 select HAVE_PCSPKR_PLATFORM
>> 507 select IRQ_MIPS_CPU
>> 508 select MIPS_GIC
>> 509 select HW_HAS_PCI
>> 510 select I8253
>> 511 select I8259
>> 512 select MIPS_BONITO64
>> 513 select MIPS_CPU_SCACHE
>> 514 select MIPS_L1_CACHE_SHIFT_6
>> 515 select PCI_GT64XXX_PCI0
>> 516 select MIPS_MSC
>> 517 select SMP_UP if SMP
>> 518 select SWAP_IO_SPACE
>> 519 select SYS_HAS_CPU_MIPS32_R1
>> 520 select SYS_HAS_CPU_MIPS32_R2
>> 521 select SYS_HAS_CPU_MIPS32_R3_5
>> 522 select SYS_HAS_CPU_MIPS32_R5
>> 523 select SYS_HAS_CPU_MIPS32_R6
>> 524 select SYS_HAS_CPU_MIPS64_R1
>> 525 select SYS_HAS_CPU_MIPS64_R2
>> 526 select SYS_HAS_CPU_MIPS64_R6
>> 527 select SYS_HAS_CPU_NEVADA
>> 528 select SYS_HAS_CPU_RM7000
>> 529 select SYS_SUPPORTS_32BIT_KERNEL
>> 530 select SYS_SUPPORTS_64BIT_KERNEL
>> 531 select SYS_SUPPORTS_BIG_ENDIAN
>> 532 select SYS_SUPPORTS_HIGHMEM
>> 533 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 534 select SYS_SUPPORTS_MICROMIPS
>> 535 select SYS_SUPPORTS_MIPS_CMP
>> 536 select SYS_SUPPORTS_MIPS_CPS
>> 537 select SYS_SUPPORTS_MIPS16
>> 538 select SYS_SUPPORTS_MULTITHREADING
>> 539 select SYS_SUPPORTS_SMARTMIPS
>> 540 select SYS_SUPPORTS_VPE_LOADER
>> 541 select SYS_SUPPORTS_ZBOOT
>> 542 select SYS_SUPPORTS_RELOCATABLE
>> 543 select USE_OF
>> 544 select LIBFDT
>> 545 select ZONE_DMA32 if 64BIT
>> 546 select BUILTIN_DTB
>> 547 select LIBFDT
>> 548 help
>> 549 This enables support for the MIPS Technologies Malta evaluation
>> 550 board.
375 551
376 config FIX_EARLYCON_MEM !! 552 config MACH_PIC32
377 def_bool y !! 553 bool "Microchip PIC32 Family"
>> 554 help
>> 555 This enables support for the Microchip PIC32 family of platforms.
378 556
379 config PGTABLE_LEVELS !! 557 Microchip PIC32 is a family of general-purpose 32 bit MIPS core
380 int !! 558 microcontrollers.
381 default 2 if ARM64_16K_PAGES && ARM64_ !! 559
382 default 2 if ARM64_64K_PAGES && ARM64_ !! 560 config NEC_MARKEINS
383 default 3 if ARM64_64K_PAGES && (ARM64 !! 561 bool "NEC EMMA2RH Mark-eins board"
384 default 3 if ARM64_4K_PAGES && ARM64_V !! 562 select SOC_EMMA2RH
385 default 3 if ARM64_16K_PAGES && ARM64_ !! 563 select HW_HAS_PCI
386 default 4 if ARM64_16K_PAGES && (ARM64 !! 564 help
387 default 4 if !ARM64_64K_PAGES && ARM64 !! 565 This enables support for the NEC Electronics Mark-eins boards.
388 default 5 if ARM64_4K_PAGES && ARM64_V !! 566
>> 567 config MACH_VR41XX
>> 568 bool "NEC VR4100 series based machines"
>> 569 select CEVT_R4K
>> 570 select CSRC_R4K
>> 571 select SYS_HAS_CPU_VR41XX
>> 572 select SYS_SUPPORTS_MIPS16
>> 573 select GPIOLIB
>> 574
>> 575 config NXP_STB220
>> 576 bool "NXP STB220 board"
>> 577 select SOC_PNX833X
>> 578 help
>> 579 Support for NXP Semiconductors STB220 Development Board.
>> 580
>> 581 config NXP_STB225
>> 582 bool "NXP 225 board"
>> 583 select SOC_PNX833X
>> 584 select SOC_PNX8335
>> 585 help
>> 586 Support for NXP Semiconductors STB225 Development Board.
>> 587
>> 588 config PMC_MSP
>> 589 bool "PMC-Sierra MSP chipsets"
>> 590 select CEVT_R4K
>> 591 select CSRC_R4K
>> 592 select DMA_NONCOHERENT
>> 593 select SWAP_IO_SPACE
>> 594 select NO_EXCEPT_FILL
>> 595 select BOOT_RAW
>> 596 select SYS_HAS_CPU_MIPS32_R1
>> 597 select SYS_HAS_CPU_MIPS32_R2
>> 598 select SYS_SUPPORTS_32BIT_KERNEL
>> 599 select SYS_SUPPORTS_BIG_ENDIAN
>> 600 select SYS_SUPPORTS_MIPS16
>> 601 select IRQ_MIPS_CPU
>> 602 select SERIAL_8250
>> 603 select SERIAL_8250_CONSOLE
>> 604 select USB_EHCI_BIG_ENDIAN_MMIO
>> 605 select USB_EHCI_BIG_ENDIAN_DESC
>> 606 help
>> 607 This adds support for the PMC-Sierra family of Multi-Service
>> 608 Processor System-On-A-Chips. These parts include a number
>> 609 of integrated peripherals, interfaces and DSPs in addition to
>> 610 a variety of MIPS cores.
>> 611
>> 612 config RALINK
>> 613 bool "Ralink based machines"
>> 614 select CEVT_R4K
>> 615 select CSRC_R4K
>> 616 select BOOT_RAW
>> 617 select DMA_NONCOHERENT
>> 618 select IRQ_MIPS_CPU
>> 619 select USE_OF
>> 620 select SYS_HAS_CPU_MIPS32_R1
>> 621 select SYS_HAS_CPU_MIPS32_R2
>> 622 select SYS_SUPPORTS_32BIT_KERNEL
>> 623 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 624 select SYS_SUPPORTS_MIPS16
>> 625 select SYS_HAS_EARLY_PRINTK
>> 626 select CLKDEV_LOOKUP
>> 627 select ARCH_HAS_RESET_CONTROLLER
>> 628 select RESET_CONTROLLER
>> 629
>> 630 config SGI_IP22
>> 631 bool "SGI IP22 (Indy/Indigo2)"
>> 632 select FW_ARC
>> 633 select FW_ARC32
>> 634 select ARCH_MIGHT_HAVE_PC_SERIO
>> 635 select BOOT_ELF32
>> 636 select CEVT_R4K
>> 637 select CSRC_R4K
>> 638 select DEFAULT_SGI_PARTITION
>> 639 select DMA_NONCOHERENT
>> 640 select HW_HAS_EISA
>> 641 select I8253
>> 642 select I8259
>> 643 select IP22_CPU_SCACHE
>> 644 select IRQ_MIPS_CPU
>> 645 select GENERIC_ISA_DMA_SUPPORT_BROKEN
>> 646 select SGI_HAS_I8042
>> 647 select SGI_HAS_INDYDOG
>> 648 select SGI_HAS_HAL2
>> 649 select SGI_HAS_SEEQ
>> 650 select SGI_HAS_WD93
>> 651 select SGI_HAS_ZILOG
>> 652 select SWAP_IO_SPACE
>> 653 select SYS_HAS_CPU_R4X00
>> 654 select SYS_HAS_CPU_R5000
>> 655 #
>> 656 # Disable EARLY_PRINTK for now since it leads to overwritten prom
>> 657 # memory during early boot on some machines.
>> 658 #
>> 659 # See http://www.linux-mips.org/cgi-bin/mesg.cgi?a=linux-mips&i=20091119164009.GA15038%40deprecation.cyrius.com
>> 660 # for a more details discussion
>> 661 #
>> 662 # select SYS_HAS_EARLY_PRINTK
>> 663 select SYS_SUPPORTS_32BIT_KERNEL
>> 664 select SYS_SUPPORTS_64BIT_KERNEL
>> 665 select SYS_SUPPORTS_BIG_ENDIAN
>> 666 select MIPS_L1_CACHE_SHIFT_7
>> 667 help
>> 668 This are the SGI Indy, Challenge S and Indigo2, as well as certain
>> 669 OEM variants like the Tandem CMN B006S. To compile a Linux kernel
>> 670 that runs on these, say Y here.
>> 671
>> 672 config SGI_IP27
>> 673 bool "SGI IP27 (Origin200/2000)"
>> 674 select ARCH_HAS_PHYS_TO_DMA
>> 675 select FW_ARC
>> 676 select FW_ARC64
>> 677 select BOOT_ELF64
>> 678 select DEFAULT_SGI_PARTITION
>> 679 select SYS_HAS_EARLY_PRINTK
>> 680 select HW_HAS_PCI
>> 681 select NR_CPUS_DEFAULT_64
>> 682 select SYS_HAS_CPU_R10000
>> 683 select SYS_SUPPORTS_64BIT_KERNEL
>> 684 select SYS_SUPPORTS_BIG_ENDIAN
>> 685 select SYS_SUPPORTS_NUMA
>> 686 select SYS_SUPPORTS_SMP
>> 687 select MIPS_L1_CACHE_SHIFT_7
>> 688 help
>> 689 This are the SGI Origin 200, Origin 2000 and Onyx 2 Graphics
>> 690 workstations. To compile a Linux kernel that runs on these, say Y
>> 691 here.
>> 692
>> 693 config SGI_IP28
>> 694 bool "SGI IP28 (Indigo2 R10k)"
>> 695 select FW_ARC
>> 696 select FW_ARC64
>> 697 select ARCH_MIGHT_HAVE_PC_SERIO
>> 698 select BOOT_ELF64
>> 699 select CEVT_R4K
>> 700 select CSRC_R4K
>> 701 select DEFAULT_SGI_PARTITION
>> 702 select DMA_NONCOHERENT
>> 703 select GENERIC_ISA_DMA_SUPPORT_BROKEN
>> 704 select IRQ_MIPS_CPU
>> 705 select HW_HAS_EISA
>> 706 select I8253
>> 707 select I8259
>> 708 select SGI_HAS_I8042
>> 709 select SGI_HAS_INDYDOG
>> 710 select SGI_HAS_HAL2
>> 711 select SGI_HAS_SEEQ
>> 712 select SGI_HAS_WD93
>> 713 select SGI_HAS_ZILOG
>> 714 select SWAP_IO_SPACE
>> 715 select SYS_HAS_CPU_R10000
>> 716 #
>> 717 # Disable EARLY_PRINTK for now since it leads to overwritten prom
>> 718 # memory during early boot on some machines.
>> 719 #
>> 720 # See http://www.linux-mips.org/cgi-bin/mesg.cgi?a=linux-mips&i=20091119164009.GA15038%40deprecation.cyrius.com
>> 721 # for a more details discussion
>> 722 #
>> 723 # select SYS_HAS_EARLY_PRINTK
>> 724 select SYS_SUPPORTS_64BIT_KERNEL
>> 725 select SYS_SUPPORTS_BIG_ENDIAN
>> 726 select MIPS_L1_CACHE_SHIFT_7
>> 727 help
>> 728 This is the SGI Indigo2 with R10000 processor. To compile a Linux
>> 729 kernel that runs on these, say Y here.
>> 730
>> 731 config SGI_IP32
>> 732 bool "SGI IP32 (O2)"
>> 733 select ARCH_HAS_PHYS_TO_DMA
>> 734 select FW_ARC
>> 735 select FW_ARC32
>> 736 select BOOT_ELF32
>> 737 select CEVT_R4K
>> 738 select CSRC_R4K
>> 739 select DMA_NONCOHERENT
>> 740 select HW_HAS_PCI
>> 741 select IRQ_MIPS_CPU
>> 742 select R5000_CPU_SCACHE
>> 743 select RM7000_CPU_SCACHE
>> 744 select SYS_HAS_CPU_R5000
>> 745 select SYS_HAS_CPU_R10000 if BROKEN
>> 746 select SYS_HAS_CPU_RM7000
>> 747 select SYS_HAS_CPU_NEVADA
>> 748 select SYS_SUPPORTS_64BIT_KERNEL
>> 749 select SYS_SUPPORTS_BIG_ENDIAN
>> 750 help
>> 751 If you want this kernel to run on SGI O2 workstation, say Y here.
>> 752
>> 753 config SIBYTE_CRHINE
>> 754 bool "Sibyte BCM91120C-CRhine"
>> 755 select BOOT_ELF32
>> 756 select SIBYTE_BCM1120
>> 757 select SWAP_IO_SPACE
>> 758 select SYS_HAS_CPU_SB1
>> 759 select SYS_SUPPORTS_BIG_ENDIAN
>> 760 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 761
>> 762 config SIBYTE_CARMEL
>> 763 bool "Sibyte BCM91120x-Carmel"
>> 764 select BOOT_ELF32
>> 765 select SIBYTE_BCM1120
>> 766 select SWAP_IO_SPACE
>> 767 select SYS_HAS_CPU_SB1
>> 768 select SYS_SUPPORTS_BIG_ENDIAN
>> 769 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 770
>> 771 config SIBYTE_CRHONE
>> 772 bool "Sibyte BCM91125C-CRhone"
>> 773 select BOOT_ELF32
>> 774 select SIBYTE_BCM1125
>> 775 select SWAP_IO_SPACE
>> 776 select SYS_HAS_CPU_SB1
>> 777 select SYS_SUPPORTS_BIG_ENDIAN
>> 778 select SYS_SUPPORTS_HIGHMEM
>> 779 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 780
>> 781 config SIBYTE_RHONE
>> 782 bool "Sibyte BCM91125E-Rhone"
>> 783 select BOOT_ELF32
>> 784 select SIBYTE_BCM1125H
>> 785 select SWAP_IO_SPACE
>> 786 select SYS_HAS_CPU_SB1
>> 787 select SYS_SUPPORTS_BIG_ENDIAN
>> 788 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 789
>> 790 config SIBYTE_SWARM
>> 791 bool "Sibyte BCM91250A-SWARM"
>> 792 select BOOT_ELF32
>> 793 select HAVE_PATA_PLATFORM
>> 794 select SIBYTE_SB1250
>> 795 select SWAP_IO_SPACE
>> 796 select SYS_HAS_CPU_SB1
>> 797 select SYS_SUPPORTS_BIG_ENDIAN
>> 798 select SYS_SUPPORTS_HIGHMEM
>> 799 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 800 select ZONE_DMA32 if 64BIT
>> 801 select SWIOTLB if ARCH_DMA_ADDR_T_64BIT && PCI
>> 802
>> 803 config SIBYTE_LITTLESUR
>> 804 bool "Sibyte BCM91250C2-LittleSur"
>> 805 select BOOT_ELF32
>> 806 select HAVE_PATA_PLATFORM
>> 807 select SIBYTE_SB1250
>> 808 select SWAP_IO_SPACE
>> 809 select SYS_HAS_CPU_SB1
>> 810 select SYS_SUPPORTS_BIG_ENDIAN
>> 811 select SYS_SUPPORTS_HIGHMEM
>> 812 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 813 select ZONE_DMA32 if 64BIT
>> 814
>> 815 config SIBYTE_SENTOSA
>> 816 bool "Sibyte BCM91250E-Sentosa"
>> 817 select BOOT_ELF32
>> 818 select SIBYTE_SB1250
>> 819 select SWAP_IO_SPACE
>> 820 select SYS_HAS_CPU_SB1
>> 821 select SYS_SUPPORTS_BIG_ENDIAN
>> 822 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 823 select SWIOTLB if ARCH_DMA_ADDR_T_64BIT && PCI
>> 824
>> 825 config SIBYTE_BIGSUR
>> 826 bool "Sibyte BCM91480B-BigSur"
>> 827 select BOOT_ELF32
>> 828 select NR_CPUS_DEFAULT_4
>> 829 select SIBYTE_BCM1x80
>> 830 select SWAP_IO_SPACE
>> 831 select SYS_HAS_CPU_SB1
>> 832 select SYS_SUPPORTS_BIG_ENDIAN
>> 833 select SYS_SUPPORTS_HIGHMEM
>> 834 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 835 select ZONE_DMA32 if 64BIT
>> 836 select SWIOTLB if ARCH_DMA_ADDR_T_64BIT && PCI
>> 837
>> 838 config SNI_RM
>> 839 bool "SNI RM200/300/400"
>> 840 select FW_ARC if CPU_LITTLE_ENDIAN
>> 841 select FW_ARC32 if CPU_LITTLE_ENDIAN
>> 842 select FW_SNIPROM if CPU_BIG_ENDIAN
>> 843 select ARCH_MAY_HAVE_PC_FDC
>> 844 select ARCH_MIGHT_HAVE_PC_PARPORT
>> 845 select ARCH_MIGHT_HAVE_PC_SERIO
>> 846 select BOOT_ELF32
>> 847 select CEVT_R4K
>> 848 select CSRC_R4K
>> 849 select DEFAULT_SGI_PARTITION if CPU_BIG_ENDIAN
>> 850 select DMA_NONCOHERENT
>> 851 select GENERIC_ISA_DMA
>> 852 select HAVE_PCSPKR_PLATFORM
>> 853 select HW_HAS_EISA
>> 854 select HW_HAS_PCI
>> 855 select IRQ_MIPS_CPU
>> 856 select I8253
>> 857 select I8259
>> 858 select ISA
>> 859 select MIPS_L1_CACHE_SHIFT_6
>> 860 select SWAP_IO_SPACE if CPU_BIG_ENDIAN
>> 861 select SYS_HAS_CPU_R4X00
>> 862 select SYS_HAS_CPU_R5000
>> 863 select SYS_HAS_CPU_R10000
>> 864 select R5000_CPU_SCACHE
>> 865 select SYS_HAS_EARLY_PRINTK
>> 866 select SYS_SUPPORTS_32BIT_KERNEL
>> 867 select SYS_SUPPORTS_64BIT_KERNEL
>> 868 select SYS_SUPPORTS_BIG_ENDIAN
>> 869 select SYS_SUPPORTS_HIGHMEM
>> 870 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 871 help
>> 872 The SNI RM200/300/400 are MIPS-based machines manufactured by
>> 873 Siemens Nixdorf Informationssysteme (SNI), parent company of Pyramid
>> 874 Technology and now in turn merged with Fujitsu. Say Y here to
>> 875 support this machine type.
>> 876
>> 877 config MACH_TX39XX
>> 878 bool "Toshiba TX39 series based machines"
>> 879
>> 880 config MACH_TX49XX
>> 881 bool "Toshiba TX49 series based machines"
>> 882
>> 883 config MIKROTIK_RB532
>> 884 bool "Mikrotik RB532 boards"
>> 885 select CEVT_R4K
>> 886 select CSRC_R4K
>> 887 select DMA_NONCOHERENT
>> 888 select HW_HAS_PCI
>> 889 select IRQ_MIPS_CPU
>> 890 select SYS_HAS_CPU_MIPS32_R1
>> 891 select SYS_SUPPORTS_32BIT_KERNEL
>> 892 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 893 select SWAP_IO_SPACE
>> 894 select BOOT_RAW
>> 895 select GPIOLIB
>> 896 select MIPS_L1_CACHE_SHIFT_4
>> 897 help
>> 898 Support the Mikrotik(tm) RouterBoard 532 series,
>> 899 based on the IDT RC32434 SoC.
>> 900
>> 901 config CAVIUM_OCTEON_SOC
>> 902 bool "Cavium Networks Octeon SoC based boards"
>> 903 select CEVT_R4K
>> 904 select ARCH_HAS_PHYS_TO_DMA
>> 905 select HAS_RAPIDIO
>> 906 select PHYS_ADDR_T_64BIT
>> 907 select SYS_SUPPORTS_64BIT_KERNEL
>> 908 select SYS_SUPPORTS_BIG_ENDIAN
>> 909 select EDAC_SUPPORT
>> 910 select EDAC_ATOMIC_SCRUB
>> 911 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 912 select SYS_SUPPORTS_HOTPLUG_CPU if CPU_BIG_ENDIAN
>> 913 select SYS_HAS_EARLY_PRINTK
>> 914 select SYS_HAS_CPU_CAVIUM_OCTEON
>> 915 select HW_HAS_PCI
>> 916 select ZONE_DMA32
>> 917 select HOLES_IN_ZONE
>> 918 select GPIOLIB
>> 919 select LIBFDT
>> 920 select USE_OF
>> 921 select ARCH_SPARSEMEM_ENABLE
>> 922 select SYS_SUPPORTS_SMP
>> 923 select NR_CPUS_DEFAULT_64
>> 924 select MIPS_NR_CPU_NR_MAP_1024
>> 925 select BUILTIN_DTB
>> 926 select MTD_COMPLEX_MAPPINGS
>> 927 select SWIOTLB
>> 928 select SYS_SUPPORTS_RELOCATABLE
>> 929 help
>> 930 This option supports all of the Octeon reference boards from Cavium
>> 931 Networks. It builds a kernel that dynamically determines the Octeon
>> 932 CPU type and supports all known board reference implementations.
>> 933 Some of the supported boards are:
>> 934 EBT3000
>> 935 EBH3000
>> 936 EBH3100
>> 937 Thunder
>> 938 Kodama
>> 939 Hikari
>> 940 Say Y here for most Octeon reference boards.
>> 941
>> 942 config NLM_XLR_BOARD
>> 943 bool "Netlogic XLR/XLS based systems"
>> 944 select BOOT_ELF32
>> 945 select NLM_COMMON
>> 946 select SYS_HAS_CPU_XLR
>> 947 select SYS_SUPPORTS_SMP
>> 948 select HW_HAS_PCI
>> 949 select SWAP_IO_SPACE
>> 950 select SYS_SUPPORTS_32BIT_KERNEL
>> 951 select SYS_SUPPORTS_64BIT_KERNEL
>> 952 select PHYS_ADDR_T_64BIT
>> 953 select SYS_SUPPORTS_BIG_ENDIAN
>> 954 select SYS_SUPPORTS_HIGHMEM
>> 955 select NR_CPUS_DEFAULT_32
>> 956 select CEVT_R4K
>> 957 select CSRC_R4K
>> 958 select IRQ_MIPS_CPU
>> 959 select ZONE_DMA32 if 64BIT
>> 960 select SYNC_R4K
>> 961 select SYS_HAS_EARLY_PRINTK
>> 962 select SYS_SUPPORTS_ZBOOT
>> 963 select SYS_SUPPORTS_ZBOOT_UART16550
>> 964 help
>> 965 Support for systems based on Netlogic XLR and XLS processors.
>> 966 Say Y here if you have a XLR or XLS based board.
>> 967
>> 968 config NLM_XLP_BOARD
>> 969 bool "Netlogic XLP based systems"
>> 970 select BOOT_ELF32
>> 971 select NLM_COMMON
>> 972 select SYS_HAS_CPU_XLP
>> 973 select SYS_SUPPORTS_SMP
>> 974 select HW_HAS_PCI
>> 975 select SYS_SUPPORTS_32BIT_KERNEL
>> 976 select SYS_SUPPORTS_64BIT_KERNEL
>> 977 select PHYS_ADDR_T_64BIT
>> 978 select GPIOLIB
>> 979 select SYS_SUPPORTS_BIG_ENDIAN
>> 980 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 981 select SYS_SUPPORTS_HIGHMEM
>> 982 select NR_CPUS_DEFAULT_32
>> 983 select CEVT_R4K
>> 984 select CSRC_R4K
>> 985 select IRQ_MIPS_CPU
>> 986 select ZONE_DMA32 if 64BIT
>> 987 select SYNC_R4K
>> 988 select SYS_HAS_EARLY_PRINTK
>> 989 select USE_OF
>> 990 select SYS_SUPPORTS_ZBOOT
>> 991 select SYS_SUPPORTS_ZBOOT_UART16550
>> 992 help
>> 993 This board is based on Netlogic XLP Processor.
>> 994 Say Y here if you have a XLP based board.
>> 995
>> 996 config MIPS_PARAVIRT
>> 997 bool "Para-Virtualized guest system"
>> 998 select CEVT_R4K
>> 999 select CSRC_R4K
>> 1000 select SYS_SUPPORTS_64BIT_KERNEL
>> 1001 select SYS_SUPPORTS_32BIT_KERNEL
>> 1002 select SYS_SUPPORTS_BIG_ENDIAN
>> 1003 select SYS_SUPPORTS_SMP
>> 1004 select NR_CPUS_DEFAULT_4
>> 1005 select SYS_HAS_EARLY_PRINTK
>> 1006 select SYS_HAS_CPU_MIPS32_R2
>> 1007 select SYS_HAS_CPU_MIPS64_R2
>> 1008 select SYS_HAS_CPU_CAVIUM_OCTEON
>> 1009 select HW_HAS_PCI
>> 1010 select SWAP_IO_SPACE
>> 1011 help
>> 1012 This option supports guest running under ????
389 1013
390 config ARCH_SUPPORTS_UPROBES !! 1014 endchoice
391 def_bool y <<
392 1015
393 config ARCH_PROC_KCORE_TEXT !! 1016 source "arch/mips/alchemy/Kconfig"
394 def_bool y !! 1017 source "arch/mips/ath25/Kconfig"
>> 1018 source "arch/mips/ath79/Kconfig"
>> 1019 source "arch/mips/bcm47xx/Kconfig"
>> 1020 source "arch/mips/bcm63xx/Kconfig"
>> 1021 source "arch/mips/bmips/Kconfig"
>> 1022 source "arch/mips/generic/Kconfig"
>> 1023 source "arch/mips/jazz/Kconfig"
>> 1024 source "arch/mips/jz4740/Kconfig"
>> 1025 source "arch/mips/lantiq/Kconfig"
>> 1026 source "arch/mips/lasat/Kconfig"
>> 1027 source "arch/mips/pic32/Kconfig"
>> 1028 source "arch/mips/pistachio/Kconfig"
>> 1029 source "arch/mips/pmcs-msp71xx/Kconfig"
>> 1030 source "arch/mips/ralink/Kconfig"
>> 1031 source "arch/mips/sgi-ip27/Kconfig"
>> 1032 source "arch/mips/sibyte/Kconfig"
>> 1033 source "arch/mips/txx9/Kconfig"
>> 1034 source "arch/mips/vr41xx/Kconfig"
>> 1035 source "arch/mips/cavium-octeon/Kconfig"
>> 1036 source "arch/mips/loongson32/Kconfig"
>> 1037 source "arch/mips/loongson64/Kconfig"
>> 1038 source "arch/mips/netlogic/Kconfig"
>> 1039 source "arch/mips/paravirt/Kconfig"
395 1040
396 config BROKEN_GAS_INST !! 1041 endmenu
397 def_bool !$(as-instr,1:\n.inst 0\n.rep <<
398 1042
399 config BUILTIN_RETURN_ADDRESS_STRIPS_PAC !! 1043 config RWSEM_GENERIC_SPINLOCK
400 bool 1044 bool
401 # Clang's __builtin_return_address() s !! 1045 default y
402 # https://github.com/llvm/llvm-project <<
403 default y if CC_IS_CLANG <<
404 # GCC's __builtin_return_address() str <<
405 # and this was backported to 10.2.0, 9 <<
406 # https://gcc.gnu.org/bugzilla/show_bu <<
407 default y if CC_IS_GCC && (GCC_VERSION <<
408 default y if CC_IS_GCC && (GCC_VERSION <<
409 default y if CC_IS_GCC && (GCC_VERSION <<
410 default y if CC_IS_GCC && (GCC_VERSION <<
411 default n <<
412 <<
413 config KASAN_SHADOW_OFFSET <<
414 hex <<
415 depends on KASAN_GENERIC || KASAN_SW_T <<
416 default 0xdfff800000000000 if (ARM64_V <<
417 default 0xdfffc00000000000 if (ARM64_V <<
418 default 0xdffffe0000000000 if ARM64_VA <<
419 default 0xdfffffc000000000 if ARM64_VA <<
420 default 0xdffffff800000000 if ARM64_VA <<
421 default 0xefff800000000000 if (ARM64_V <<
422 default 0xefffc00000000000 if (ARM64_V <<
423 default 0xeffffe0000000000 if ARM64_VA <<
424 default 0xefffffc000000000 if ARM64_VA <<
425 default 0xeffffff800000000 if ARM64_VA <<
426 default 0xffffffffffffffff <<
427 <<
428 config UNWIND_TABLES <<
429 bool <<
430 <<
431 source "arch/arm64/Kconfig.platforms" <<
432 <<
433 menu "Kernel Features" <<
434 <<
435 menu "ARM errata workarounds via the alternati <<
436 <<
437 config AMPERE_ERRATUM_AC03_CPU_38 <<
438 bool "AmpereOne: AC03_CPU_38: Certain <<
439 default y <<
440 help <<
441 This option adds an alternative code <<
442 errata AC03_CPU_38 and AC04_CPU_10 o <<
443 <<
444 The affected design reports FEAT_HAF <<
445 ID_AA64MMFR1_EL1.HAFDBS, but (V)TCR_ <<
446 as required by the architecture. The <<
447 implementation suffers from an addit <<
448 A/D updates can occur after a PTE ha <<
449 <<
450 The workaround forces KVM to explici <<
451 which avoids enabling unadvertised h <<
452 at stage-2. <<
453 <<
454 If unsure, say Y. <<
455 1046
456 config ARM64_WORKAROUND_CLEAN_CACHE !! 1047 config RWSEM_XCHGADD_ALGORITHM
457 bool 1048 bool
458 1049
459 config ARM64_ERRATUM_826319 !! 1050 config GENERIC_HWEIGHT
460 bool "Cortex-A53: 826319: System might !! 1051 bool
461 default y 1052 default y
462 select ARM64_WORKAROUND_CLEAN_CACHE <<
463 help <<
464 This option adds an alternative code <<
465 erratum 826319 on Cortex-A53 parts u <<
466 AXI master interface and an L2 cache <<
467 <<
468 If a Cortex-A53 uses an AMBA AXI4 AC <<
469 and is unable to accept a certain wr <<
470 not progress on read data presented <<
471 system can deadlock. <<
472 <<
473 The workaround promotes data cache c <<
474 data cache clean-and-invalidate. <<
475 Please note that this does not neces <<
476 as it depends on the alternative fra <<
477 the kernel if an affected CPU is det <<
478 1053
479 If unsure, say Y. !! 1054 config GENERIC_CALIBRATE_DELAY
480 !! 1055 bool
481 config ARM64_ERRATUM_827319 <<
482 bool "Cortex-A53: 827319: Data cache c <<
483 default y 1056 default y
484 select ARM64_WORKAROUND_CLEAN_CACHE <<
485 help <<
486 This option adds an alternative code <<
487 erratum 827319 on Cortex-A53 parts u <<
488 master interface and an L2 cache. <<
489 <<
490 Under certain conditions this erratu <<
491 to occur at the same time as another <<
492 on the AMBA 5 CHI interface, which c <<
493 interconnect reorders the two transa <<
494 <<
495 The workaround promotes data cache c <<
496 data cache clean-and-invalidate. <<
497 Please note that this does not neces <<
498 as it depends on the alternative fra <<
499 the kernel if an affected CPU is det <<
500 1057
501 If unsure, say Y. !! 1058 config SCHED_OMIT_FRAME_POINTER
502 !! 1059 bool
503 config ARM64_ERRATUM_824069 <<
504 bool "Cortex-A53: 824069: Cache line m <<
505 default y 1060 default y
506 select ARM64_WORKAROUND_CLEAN_CACHE <<
507 help <<
508 This option adds an alternative code <<
509 erratum 824069 on Cortex-A53 parts u <<
510 to a coherent interconnect. <<
511 <<
512 If a Cortex-A53 processor is executi <<
513 write instruction at the same time a <<
514 cluster is executing a cache mainten <<
515 address, then this erratum might cau <<
516 incorrectly marked as dirty. <<
517 <<
518 The workaround promotes data cache c <<
519 data cache clean-and-invalidate. <<
520 Please note that this option does no <<
521 workaround, as it depends on the alt <<
522 only patch the kernel if an affected <<
523 1061
524 If unsure, say Y. !! 1062 #
>> 1063 # Select some configuration options automatically based on user selections.
>> 1064 #
>> 1065 config FW_ARC
>> 1066 bool
525 1067
526 config ARM64_ERRATUM_819472 !! 1068 config ARCH_MAY_HAVE_PC_FDC
527 bool "Cortex-A53: 819472: Store exclus !! 1069 bool
528 default y <<
529 select ARM64_WORKAROUND_CLEAN_CACHE <<
530 help <<
531 This option adds an alternative code <<
532 erratum 819472 on Cortex-A53 parts u <<
533 present when it is connected to a co <<
534 <<
535 If the processor is executing a load <<
536 the same time as a processor in anot <<
537 maintenance operation to the same ad <<
538 cause data corruption. <<
539 <<
540 The workaround promotes data cache c <<
541 data cache clean-and-invalidate. <<
542 Please note that this does not neces <<
543 as it depends on the alternative fra <<
544 the kernel if an affected CPU is det <<
545 1070
546 If unsure, say Y. !! 1071 config BOOT_RAW
>> 1072 bool
547 1073
548 config ARM64_ERRATUM_832075 !! 1074 config CEVT_BCM1480
549 bool "Cortex-A57: 832075: possible dea !! 1075 bool
550 default y <<
551 help <<
552 This option adds an alternative code <<
553 erratum 832075 on Cortex-A57 parts u <<
554 1076
555 Affected Cortex-A57 parts might dead !! 1077 config CEVT_DS1287
556 instructions to Write-Back memory ar !! 1078 bool
557 1079
558 The workaround is to promote device !! 1080 config CEVT_GT641XX
559 semantics. !! 1081 bool
560 Please note that this does not neces <<
561 as it depends on the alternative fra <<
562 the kernel if an affected CPU is det <<
563 1082
564 If unsure, say Y. !! 1083 config CEVT_R4K
>> 1084 bool
565 1085
566 config ARM64_ERRATUM_834220 !! 1086 config CEVT_SB1250
567 bool "Cortex-A57: 834220: Stage 2 tran !! 1087 bool
568 depends on KVM <<
569 help <<
570 This option adds an alternative code <<
571 erratum 834220 on Cortex-A57 parts u <<
572 <<
573 Affected Cortex-A57 parts might repo <<
574 fault as the result of a Stage 1 fau <<
575 page boundary when there is a permis <<
576 alignment fault at Stage 1 and a tra <<
577 <<
578 The workaround is to verify that the <<
579 doesn't generate a fault before hand <<
580 Please note that this does not neces <<
581 as it depends on the alternative fra <<
582 the kernel if an affected CPU is det <<
583 1088
584 If unsure, say N. !! 1089 config CEVT_TXX9
>> 1090 bool
585 1091
586 config ARM64_ERRATUM_1742098 !! 1092 config CSRC_BCM1480
587 bool "Cortex-A57/A72: 1742098: ELR rec !! 1093 bool
588 depends on COMPAT <<
589 default y <<
590 help <<
591 This option removes the AES hwcap fo <<
592 workaround erratum 1742098 on Cortex <<
593 <<
594 Affected parts may corrupt the AES s <<
595 taken between a pair of AES instruct <<
596 are only present if the cryptography <<
597 All software should have a fallback <<
598 that don't implement the cryptograph <<
599 1094
600 If unsure, say Y. !! 1095 config CSRC_IOASIC
>> 1096 bool
601 1097
602 config ARM64_ERRATUM_845719 !! 1098 config CSRC_R4K
603 bool "Cortex-A53: 845719: a load might !! 1099 bool
604 depends on COMPAT <<
605 default y <<
606 help <<
607 This option adds an alternative code <<
608 erratum 845719 on Cortex-A53 parts u <<
609 <<
610 When running a compat (AArch32) user <<
611 part, a load at EL0 from a virtual a <<
612 bits of the virtual address used by <<
613 might return incorrect data. <<
614 <<
615 The workaround is to write the conte <<
616 return to a 32-bit task. <<
617 Please note that this does not neces <<
618 as it depends on the alternative fra <<
619 the kernel if an affected CPU is det <<
620 1100
621 If unsure, say Y. !! 1101 config CSRC_SB1250
>> 1102 bool
622 1103
623 config ARM64_ERRATUM_843419 !! 1104 config MIPS_CLOCK_VSYSCALL
624 bool "Cortex-A53: 843419: A load or st !! 1105 def_bool CSRC_R4K || CLKSRC_MIPS_GIC
625 default y <<
626 help <<
627 This option links the kernel with '- <<
628 enables PLT support to replace certa <<
629 cause subsequent memory accesses to <<
630 Cortex-A53 parts up to r0p4. <<
631 1106
632 If unsure, say Y. !! 1107 config GPIO_TXX9
>> 1108 select GPIOLIB
>> 1109 bool
633 1110
634 config ARM64_LD_HAS_FIX_ERRATUM_843419 !! 1111 config FW_CFE
635 def_bool $(ld-option,--fix-cortex-a53- !! 1112 bool
636 1113
637 config ARM64_ERRATUM_1024718 !! 1114 config ARCH_SUPPORTS_UPROBES
638 bool "Cortex-A55: 1024718: Update of D !! 1115 bool
639 default y <<
640 help <<
641 This option adds a workaround for AR <<
642 1116
643 Affected Cortex-A55 cores (all revis !! 1117 config DMA_MAYBE_COHERENT
644 update of the hardware dirty bit whe !! 1118 select DMA_NONCOHERENT
645 without a break-before-make. The wor !! 1119 bool
646 of hardware DBM locally on the affec <<
647 this erratum will continue to use th <<
648 1120
649 If unsure, say Y. !! 1121 config DMA_PERDEV_COHERENT
>> 1122 bool
>> 1123 select DMA_MAYBE_COHERENT
650 1124
651 config ARM64_ERRATUM_1418040 !! 1125 config DMA_NONCOHERENT
652 bool "Cortex-A76/Neoverse-N1: MRC read !! 1126 bool
653 default y !! 1127 select ARCH_HAS_SYNC_DMA_FOR_DEVICE
654 depends on COMPAT !! 1128 select ARCH_HAS_SYNC_DMA_FOR_CPU
655 help !! 1129 select NEED_DMA_MAP_STATE
656 This option adds a workaround for AR !! 1130 select DMA_NONCOHERENT_MMAP
657 errata 1188873 and 1418040. !! 1131 select DMA_NONCOHERENT_CACHE_SYNC
>> 1132 select DMA_NONCOHERENT_OPS
658 1133
659 Affected Cortex-A76/Neoverse-N1 core !! 1134 config SYS_HAS_EARLY_PRINTK
660 cause register corruption when acces !! 1135 bool
661 from AArch32 userspace. <<
662 1136
663 If unsure, say Y. !! 1137 config SYS_SUPPORTS_HOTPLUG_CPU
>> 1138 bool
664 1139
665 config ARM64_WORKAROUND_SPECULATIVE_AT !! 1140 config MIPS_BONITO64
666 bool 1141 bool
667 1142
668 config ARM64_ERRATUM_1165522 !! 1143 config MIPS_MSC
669 bool "Cortex-A76: 1165522: Speculative !! 1144 bool
670 default y <<
671 select ARM64_WORKAROUND_SPECULATIVE_AT <<
672 help <<
673 This option adds a workaround for AR <<
674 1145
675 Affected Cortex-A76 cores (r0p0, r1p !! 1146 config MIPS_NILE4
676 corrupted TLBs by speculating an AT !! 1147 bool
677 context switch. <<
678 1148
679 If unsure, say Y. !! 1149 config SYNC_R4K
>> 1150 bool
680 1151
681 config ARM64_ERRATUM_1319367 !! 1152 config MIPS_MACHINE
682 bool "Cortex-A57/A72: 1319537: Specula !! 1153 def_bool n
683 default y <<
684 select ARM64_WORKAROUND_SPECULATIVE_AT <<
685 help <<
686 This option adds work arounds for AR <<
687 and A72 erratum 1319367 <<
688 1154
689 Cortex-A57 and A72 cores could end-u !! 1155 config NO_IOPORT_MAP
690 speculating an AT instruction during !! 1156 def_bool n
691 1157
692 If unsure, say Y. !! 1158 config GENERIC_CSUM
>> 1159 bool
693 1160
694 config ARM64_ERRATUM_1530923 !! 1161 config GENERIC_ISA_DMA
695 bool "Cortex-A55: 1530923: Speculative !! 1162 bool
696 default y !! 1163 select ZONE_DMA if GENERIC_ISA_DMA_SUPPORT_BROKEN=n
697 select ARM64_WORKAROUND_SPECULATIVE_AT !! 1164 select ISA_DMA_API
698 help <<
699 This option adds a workaround for AR <<
700 1165
701 Affected Cortex-A55 cores (r0p0, r0p !! 1166 config GENERIC_ISA_DMA_SUPPORT_BROKEN
702 corrupted TLBs by speculating an AT !! 1167 bool
703 context switch. !! 1168 select GENERIC_ISA_DMA
704 1169
705 If unsure, say Y. !! 1170 config ISA_DMA_API
>> 1171 bool
706 1172
707 config ARM64_WORKAROUND_REPEAT_TLBI !! 1173 config HOLES_IN_ZONE
708 bool 1174 bool
709 1175
710 config ARM64_ERRATUM_2441007 !! 1176 config SYS_SUPPORTS_RELOCATABLE
711 bool "Cortex-A55: Completion of affect !! 1177 bool
712 select ARM64_WORKAROUND_REPEAT_TLBI <<
713 help 1178 help
714 This option adds a workaround for AR !! 1179 Selected if the platform supports relocating the kernel.
715 !! 1180 The platform must provide plat_get_fdt() if it selects CONFIG_USE_OF
716 Under very rare circumstances, affec !! 1181 to allow access to command line and entropy sources.
717 may not handle a race between a brea <<
718 CPU, and another CPU accessing the s <<
719 store to a page that has been unmapp <<
720 <<
721 Work around this by adding the affec <<
722 TLB sequences to be done twice. <<
723 1182
724 If unsure, say N. !! 1183 config MIPS_CBPF_JIT
>> 1184 def_bool y
>> 1185 depends on BPF_JIT && HAVE_CBPF_JIT
725 1186
726 config ARM64_ERRATUM_1286807 !! 1187 config MIPS_EBPF_JIT
727 bool "Cortex-A76: Modification of the !! 1188 def_bool y
728 select ARM64_WORKAROUND_REPEAT_TLBI !! 1189 depends on BPF_JIT && HAVE_EBPF_JIT
729 help <<
730 This option adds a workaround for AR <<
731 <<
732 On the affected Cortex-A76 cores (r0 <<
733 address for a cacheable mapping of a <<
734 accessed by a core while another cor <<
735 address to a new physical page using <<
736 break-before-make sequence, then und <<
737 TLBI+DSB completes before a read usi <<
738 invalidated has been observed by oth <<
739 workaround repeats the TLBI+DSB oper <<
740 1190
741 If unsure, say N. <<
742 1191
743 config ARM64_ERRATUM_1463225 !! 1192 #
744 bool "Cortex-A76: Software Step might !! 1193 # Endianness selection. Sufficiently obscure so many users don't know what to
745 default y !! 1194 # answer,so we try hard to limit the available choices. Also the use of a
>> 1195 # choice statement should be more obvious to the user.
>> 1196 #
>> 1197 choice
>> 1198 prompt "Endianness selection"
746 help 1199 help
747 This option adds a workaround for Ar !! 1200 Some MIPS machines can be configured for either little or big endian
>> 1201 byte order. These modes require different kernels and a different
>> 1202 Linux distribution. In general there is one preferred byteorder for a
>> 1203 particular system but some systems are just as commonly used in the
>> 1204 one or the other endianness.
748 1205
749 On the affected Cortex-A76 cores (r0 !! 1206 config CPU_BIG_ENDIAN
750 of a system call instruction (SVC) c !! 1207 bool "Big endian"
751 subsequent interrupts when software !! 1208 depends on SYS_SUPPORTS_BIG_ENDIAN
752 exception handler of the system call <<
753 is enabled or VHE is in use. <<
754 1209
755 Work around the erratum by triggerin !! 1210 config CPU_LITTLE_ENDIAN
756 when handling a system call from a t !! 1211 bool "Little endian"
757 in a VHE configuration of the kernel !! 1212 depends on SYS_SUPPORTS_LITTLE_ENDIAN
758 1213
759 If unsure, say Y. !! 1214 endchoice
760 1215
761 config ARM64_ERRATUM_1542419 !! 1216 config EXPORT_UASM
762 bool "Neoverse-N1: workaround mis-orde !! 1217 bool
763 help <<
764 This option adds a workaround for AR <<
765 1542419. <<
766 1218
767 Affected Neoverse-N1 cores could exe !! 1219 config SYS_SUPPORTS_APM_EMULATION
768 modified by another CPU. The workaro !! 1220 bool
769 counterpart. <<
770 1221
771 Workaround the issue by hiding the D !! 1222 config SYS_SUPPORTS_BIG_ENDIAN
772 forces user-space to perform cache m !! 1223 bool
773 1224
774 If unsure, say N. !! 1225 config SYS_SUPPORTS_LITTLE_ENDIAN
>> 1226 bool
775 1227
776 config ARM64_ERRATUM_1508412 !! 1228 config SYS_SUPPORTS_HUGETLBFS
777 bool "Cortex-A77: 1508412: workaround !! 1229 bool
>> 1230 depends on CPU_SUPPORTS_HUGEPAGES && 64BIT
778 default y 1231 default y
779 help <<
780 This option adds a workaround for Ar <<
781 1232
782 Affected Cortex-A77 cores (r0p0, r1p !! 1233 config MIPS_HUGE_TLB_SUPPORT
783 of a store-exclusive or read of PAR_ !! 1234 def_bool HUGETLB_PAGE || TRANSPARENT_HUGEPAGE
784 non-cacheable memory attributes. The <<
785 counterpart. <<
786 1235
787 KVM guests must also have the workar !! 1236 config IRQ_CPU_RM7K
788 deadlock the system. !! 1237 bool
789 1238
790 Work around the issue by inserting D !! 1239 config IRQ_MSP_SLP
791 register reads and warning KVM users !! 1240 bool
792 to prevent a speculative PAR_EL1 rea <<
793 1241
794 If unsure, say Y. !! 1242 config IRQ_MSP_CIC
>> 1243 bool
795 1244
796 config ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MO !! 1245 config IRQ_TXX9
797 bool 1246 bool
798 1247
799 config ARM64_ERRATUM_2051678 !! 1248 config IRQ_GT641XX
800 bool "Cortex-A510: 2051678: disable Ha !! 1249 bool
801 default y <<
802 help <<
803 This options adds the workaround for <<
804 Affected Cortex-A510 might not respe <<
805 hardware update of the page table's <<
806 is to not enable the feature on affe <<
807 1250
808 If unsure, say Y. !! 1251 config PCI_GT64XXX_PCI0
>> 1252 bool
809 1253
810 config ARM64_ERRATUM_2077057 !! 1254 config NO_EXCEPT_FILL
811 bool "Cortex-A510: 2077057: workaround !! 1255 bool
812 default y <<
813 help <<
814 This option adds the workaround for <<
815 Affected Cortex-A510 may corrupt SPS <<
816 expected, but a Pointer Authenticati <<
817 erratum causes SPSR_EL1 to be copied <<
818 EL1 to cause a return to EL2 with a <<
819 1256
820 This can only happen when EL2 is ste !! 1257 config SOC_EMMA2RH
>> 1258 bool
>> 1259 select CEVT_R4K
>> 1260 select CSRC_R4K
>> 1261 select DMA_NONCOHERENT
>> 1262 select IRQ_MIPS_CPU
>> 1263 select SWAP_IO_SPACE
>> 1264 select SYS_HAS_CPU_R5500
>> 1265 select SYS_SUPPORTS_32BIT_KERNEL
>> 1266 select SYS_SUPPORTS_64BIT_KERNEL
>> 1267 select SYS_SUPPORTS_BIG_ENDIAN
821 1268
822 When these conditions occur, the SPS !! 1269 config SOC_PNX833X
823 previous guest entry, and can be res !! 1270 bool
>> 1271 select CEVT_R4K
>> 1272 select CSRC_R4K
>> 1273 select IRQ_MIPS_CPU
>> 1274 select DMA_NONCOHERENT
>> 1275 select SYS_HAS_CPU_MIPS32_R2
>> 1276 select SYS_SUPPORTS_32BIT_KERNEL
>> 1277 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 1278 select SYS_SUPPORTS_BIG_ENDIAN
>> 1279 select SYS_SUPPORTS_MIPS16
>> 1280 select CPU_MIPSR2_IRQ_VI
824 1281
825 If unsure, say Y. !! 1282 config SOC_PNX8335
>> 1283 bool
>> 1284 select SOC_PNX833X
826 1285
827 config ARM64_ERRATUM_2658417 !! 1286 config MIPS_SPRAM
828 bool "Cortex-A510: 2658417: remove BF1 !! 1287 bool
829 default y <<
830 help <<
831 This option adds the workaround for <<
832 Affected Cortex-A510 (r0p0 to r1p1) <<
833 BFMMLA or VMMLA instructions in rare <<
834 A510 CPUs are using shared neon hard <<
835 discoverable by the kernel, hide the <<
836 user-space should not be using these <<
837 1288
838 If unsure, say Y. !! 1289 config SWAP_IO_SPACE
>> 1290 bool
839 1291
840 config ARM64_ERRATUM_2119858 !! 1292 config SGI_HAS_INDYDOG
841 bool "Cortex-A710/X2: 2119858: workaro !! 1293 bool
842 default y <<
843 depends on CORESIGHT_TRBE <<
844 select ARM64_WORKAROUND_TRBE_OVERWRITE <<
845 help <<
846 This option adds the workaround for <<
847 1294
848 Affected Cortex-A710/X2 cores could !! 1295 config SGI_HAS_HAL2
849 data at the base of the buffer (poin !! 1296 bool
850 the event of a WRAP event. <<
851 1297
852 Work around the issue by always maki !! 1298 config SGI_HAS_SEEQ
853 256 bytes before enabling the buffer !! 1299 bool
854 the buffer with ETM ignore packets u <<
855 1300
856 If unsure, say Y. !! 1301 config SGI_HAS_WD93
>> 1302 bool
857 1303
858 config ARM64_ERRATUM_2139208 !! 1304 config SGI_HAS_ZILOG
859 bool "Neoverse-N2: 2139208: workaround !! 1305 bool
860 default y <<
861 depends on CORESIGHT_TRBE <<
862 select ARM64_WORKAROUND_TRBE_OVERWRITE <<
863 help <<
864 This option adds the workaround for <<
865 1306
866 Affected Neoverse-N2 cores could ove !! 1307 config SGI_HAS_I8042
867 data at the base of the buffer (poin !! 1308 bool
868 the event of a WRAP event. <<
869 1309
870 Work around the issue by always maki !! 1310 config DEFAULT_SGI_PARTITION
871 256 bytes before enabling the buffer !! 1311 bool
872 the buffer with ETM ignore packets u <<
873 1312
874 If unsure, say Y. !! 1313 config FW_ARC32
>> 1314 bool
875 1315
876 config ARM64_WORKAROUND_TSB_FLUSH_FAILURE !! 1316 config FW_SNIPROM
877 bool 1317 bool
878 1318
879 config ARM64_ERRATUM_2054223 !! 1319 config BOOT_ELF32
880 bool "Cortex-A710: 2054223: workaround !! 1320 bool
881 default y <<
882 select ARM64_WORKAROUND_TSB_FLUSH_FAIL <<
883 help <<
884 Enable workaround for ARM Cortex-A71 <<
885 1321
886 Affected cores may fail to flush the !! 1322 config MIPS_L1_CACHE_SHIFT_4
887 the PE is in trace prohibited state. !! 1323 bool
888 of the trace cached. <<
889 1324
890 Workaround is to issue two TSB conse !! 1325 config MIPS_L1_CACHE_SHIFT_5
>> 1326 bool
891 1327
892 If unsure, say Y. !! 1328 config MIPS_L1_CACHE_SHIFT_6
>> 1329 bool
893 1330
894 config ARM64_ERRATUM_2067961 !! 1331 config MIPS_L1_CACHE_SHIFT_7
895 bool "Neoverse-N2: 2067961: workaround !! 1332 bool
896 default y <<
897 select ARM64_WORKAROUND_TSB_FLUSH_FAIL <<
898 help <<
899 Enable workaround for ARM Neoverse-N <<
900 1333
901 Affected cores may fail to flush the !! 1334 config MIPS_L1_CACHE_SHIFT
902 the PE is in trace prohibited state. !! 1335 int
903 of the trace cached. !! 1336 default "7" if MIPS_L1_CACHE_SHIFT_7
>> 1337 default "6" if MIPS_L1_CACHE_SHIFT_6
>> 1338 default "5" if MIPS_L1_CACHE_SHIFT_5
>> 1339 default "4" if MIPS_L1_CACHE_SHIFT_4
>> 1340 default "5"
904 1341
905 Workaround is to issue two TSB conse !! 1342 config HAVE_STD_PC_SERIAL_PORT
>> 1343 bool
906 1344
907 If unsure, say Y. !! 1345 config ARC_CONSOLE
>> 1346 bool "ARC console support"
>> 1347 depends on SGI_IP22 || SGI_IP28 || (SNI_RM && CPU_LITTLE_ENDIAN)
908 1348
909 config ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANG !! 1349 config ARC_MEMORY
910 bool 1350 bool
911 !! 1351 depends on MACH_JAZZ || SNI_RM || SGI_IP32
912 config ARM64_ERRATUM_2253138 <<
913 bool "Neoverse-N2: 2253138: workaround <<
914 depends on CORESIGHT_TRBE <<
915 default y 1352 default y
916 select ARM64_WORKAROUND_TRBE_WRITE_OUT <<
917 help <<
918 This option adds the workaround for <<
919 1353
920 Affected Neoverse-N2 cores might wri !! 1354 config ARC_PROMLIB
921 for TRBE. Under some conditions, the !! 1355 bool
922 virtually addressed page following t !! 1356 depends on MACH_JAZZ || SNI_RM || SGI_IP22 || SGI_IP28 || SGI_IP32
923 (i.e., the TRBLIMITR_EL1.LIMIT), ins <<
924 <<
925 Work around this in the driver by al <<
926 page beyond the TRBLIMITR_EL1.LIMIT, <<
927 <<
928 If unsure, say Y. <<
929 <<
930 config ARM64_ERRATUM_2224489 <<
931 bool "Cortex-A710/X2: 2224489: workaro <<
932 depends on CORESIGHT_TRBE <<
933 default y 1357 default y
934 select ARM64_WORKAROUND_TRBE_WRITE_OUT <<
935 help <<
936 This option adds the workaround for <<
937 <<
938 Affected Cortex-A710/X2 cores might <<
939 for TRBE. Under some conditions, the <<
940 virtually addressed page following t <<
941 (i.e., the TRBLIMITR_EL1.LIMIT), ins <<
942 <<
943 Work around this in the driver by al <<
944 page beyond the TRBLIMITR_EL1.LIMIT, <<
945 1358
946 If unsure, say Y. !! 1359 config FW_ARC64
>> 1360 bool
947 1361
948 config ARM64_ERRATUM_2441009 !! 1362 config BOOT_ELF64
949 bool "Cortex-A510: Completion of affec !! 1363 bool
950 select ARM64_WORKAROUND_REPEAT_TLBI <<
951 help <<
952 This option adds a workaround for AR <<
953 <<
954 Under very rare circumstances, affec <<
955 may not handle a race between a brea <<
956 CPU, and another CPU accessing the s <<
957 store to a page that has been unmapp <<
958 1364
959 Work around this by adding the affec !! 1365 menu "CPU selection"
960 TLB sequences to be done twice. <<
961 1366
962 If unsure, say N. !! 1367 choice
>> 1368 prompt "CPU type"
>> 1369 default CPU_R4X00
963 1370
964 config ARM64_ERRATUM_2064142 !! 1371 config CPU_LOONGSON3
965 bool "Cortex-A510: 2064142: workaround !! 1372 bool "Loongson 3 CPU"
966 depends on CORESIGHT_TRBE !! 1373 depends on SYS_HAS_CPU_LOONGSON3
967 default y !! 1374 select ARCH_HAS_PHYS_TO_DMA
>> 1375 select CPU_SUPPORTS_64BIT_KERNEL
>> 1376 select CPU_SUPPORTS_HIGHMEM
>> 1377 select CPU_SUPPORTS_HUGEPAGES
>> 1378 select WEAK_ORDERING
>> 1379 select WEAK_REORDERING_BEYOND_LLSC
>> 1380 select MIPS_PGD_C0_CONTEXT
>> 1381 select MIPS_L1_CACHE_SHIFT_6
>> 1382 select MIPS_FP_SUPPORT
>> 1383 select GPIOLIB
>> 1384 select SWIOTLB
968 help 1385 help
969 This option adds the workaround for !! 1386 The Loongson 3 processor implements the MIPS64R2 instruction
970 !! 1387 set with many extensions.
971 Affected Cortex-A510 core might fail <<
972 TRBE has been disabled. Under some c <<
973 writes into TRBE registers TRBLIMITR <<
974 and TRBTRG_EL1 will be ignored and w <<
975 1388
976 Work around this in the driver by ex !! 1389 config LOONGSON3_ENHANCEMENT
977 is stopped and before performing a s !! 1390 bool "New Loongson 3 CPU Enhancements"
978 registers. !! 1391 default n
>> 1392 select CPU_MIPSR2
>> 1393 select CPU_HAS_PREFETCH
>> 1394 depends on CPU_LOONGSON3
>> 1395 help
>> 1396 New Loongson 3 CPU (since Loongson-3A R2, as opposed to Loongson-3A
>> 1397 R1, Loongson-3B R1 and Loongson-3B R2) has many enhancements, such as
>> 1398 FTLB, L1-VCache, EI/DI/Wait/Prefetch instruction, DSP/DSPv2 ASE, User
>> 1399 Local register, Read-Inhibit/Execute-Inhibit, SFB (Store Fill Buffer),
>> 1400 Fast TLB refill support, etc.
>> 1401
>> 1402 This option enable those enhancements which are not probed at run
>> 1403 time. If you want a generic kernel to run on all Loongson 3 machines,
>> 1404 please say 'N' here. If you want a high-performance kernel to run on
>> 1405 new Loongson 3 machines only, please say 'Y' here.
>> 1406
>> 1407 config CPU_LOONGSON2E
>> 1408 bool "Loongson 2E"
>> 1409 depends on SYS_HAS_CPU_LOONGSON2E
>> 1410 select CPU_LOONGSON2
>> 1411 help
>> 1412 The Loongson 2E processor implements the MIPS III instruction set
>> 1413 with many extensions.
>> 1414
>> 1415 It has an internal FPGA northbridge, which is compatible to
>> 1416 bonito64.
>> 1417
>> 1418 config CPU_LOONGSON2F
>> 1419 bool "Loongson 2F"
>> 1420 depends on SYS_HAS_CPU_LOONGSON2F
>> 1421 select CPU_LOONGSON2
>> 1422 select GPIOLIB
>> 1423 help
>> 1424 The Loongson 2F processor implements the MIPS III instruction set
>> 1425 with many extensions.
>> 1426
>> 1427 Loongson2F have built-in DDR2 and PCIX controller. The PCIX controller
>> 1428 have a similar programming interface with FPGA northbridge used in
>> 1429 Loongson2E.
>> 1430
>> 1431 config CPU_LOONGSON1B
>> 1432 bool "Loongson 1B"
>> 1433 depends on SYS_HAS_CPU_LOONGSON1B
>> 1434 select CPU_LOONGSON1
>> 1435 select LEDS_GPIO_REGISTER
>> 1436 help
>> 1437 The Loongson 1B is a 32-bit SoC, which implements the MIPS32
>> 1438 Release 1 instruction set and part of the MIPS32 Release 2
>> 1439 instruction set.
>> 1440
>> 1441 config CPU_LOONGSON1C
>> 1442 bool "Loongson 1C"
>> 1443 depends on SYS_HAS_CPU_LOONGSON1C
>> 1444 select CPU_LOONGSON1
>> 1445 select LEDS_GPIO_REGISTER
>> 1446 help
>> 1447 The Loongson 1C is a 32-bit SoC, which implements the MIPS32
>> 1448 Release 1 instruction set and part of the MIPS32 Release 2
>> 1449 instruction set.
>> 1450
>> 1451 config CPU_MIPS32_R1
>> 1452 bool "MIPS32 Release 1"
>> 1453 depends on SYS_HAS_CPU_MIPS32_R1
>> 1454 select CPU_HAS_PREFETCH
>> 1455 select CPU_SUPPORTS_32BIT_KERNEL
>> 1456 select CPU_SUPPORTS_HIGHMEM
>> 1457 help
>> 1458 Choose this option to build a kernel for release 1 or later of the
>> 1459 MIPS32 architecture. Most modern embedded systems with a 32-bit
>> 1460 MIPS processor are based on a MIPS32 processor. If you know the
>> 1461 specific type of processor in your system, choose those that one
>> 1462 otherwise CPU_MIPS32_R1 is a safe bet for any MIPS32 system.
>> 1463 Release 2 of the MIPS32 architecture is available since several
>> 1464 years so chances are you even have a MIPS32 Release 2 processor
>> 1465 in which case you should choose CPU_MIPS32_R2 instead for better
>> 1466 performance.
>> 1467
>> 1468 config CPU_MIPS32_R2
>> 1469 bool "MIPS32 Release 2"
>> 1470 depends on SYS_HAS_CPU_MIPS32_R2
>> 1471 select CPU_HAS_PREFETCH
>> 1472 select CPU_SUPPORTS_32BIT_KERNEL
>> 1473 select CPU_SUPPORTS_HIGHMEM
>> 1474 select CPU_SUPPORTS_MSA
>> 1475 select HAVE_KVM
>> 1476 help
>> 1477 Choose this option to build a kernel for release 2 or later of the
>> 1478 MIPS32 architecture. Most modern embedded systems with a 32-bit
>> 1479 MIPS processor are based on a MIPS32 processor. If you know the
>> 1480 specific type of processor in your system, choose those that one
>> 1481 otherwise CPU_MIPS32_R1 is a safe bet for any MIPS32 system.
>> 1482
>> 1483 config CPU_MIPS32_R6
>> 1484 bool "MIPS32 Release 6"
>> 1485 depends on SYS_HAS_CPU_MIPS32_R6
>> 1486 select CPU_HAS_PREFETCH
>> 1487 select CPU_SUPPORTS_32BIT_KERNEL
>> 1488 select CPU_SUPPORTS_HIGHMEM
>> 1489 select CPU_SUPPORTS_MSA
>> 1490 select GENERIC_CSUM
>> 1491 select HAVE_KVM
>> 1492 select MIPS_O32_FP64_SUPPORT
>> 1493 help
>> 1494 Choose this option to build a kernel for release 6 or later of the
>> 1495 MIPS32 architecture. New MIPS processors, starting with the Warrior
>> 1496 family, are based on a MIPS32r6 processor. If you own an older
>> 1497 processor, you probably need to select MIPS32r1 or MIPS32r2 instead.
>> 1498
>> 1499 config CPU_MIPS64_R1
>> 1500 bool "MIPS64 Release 1"
>> 1501 depends on SYS_HAS_CPU_MIPS64_R1
>> 1502 select CPU_HAS_PREFETCH
>> 1503 select CPU_SUPPORTS_32BIT_KERNEL
>> 1504 select CPU_SUPPORTS_64BIT_KERNEL
>> 1505 select CPU_SUPPORTS_HIGHMEM
>> 1506 select CPU_SUPPORTS_HUGEPAGES
>> 1507 help
>> 1508 Choose this option to build a kernel for release 1 or later of the
>> 1509 MIPS64 architecture. Many modern embedded systems with a 64-bit
>> 1510 MIPS processor are based on a MIPS64 processor. If you know the
>> 1511 specific type of processor in your system, choose those that one
>> 1512 otherwise CPU_MIPS64_R1 is a safe bet for any MIPS64 system.
>> 1513 Release 2 of the MIPS64 architecture is available since several
>> 1514 years so chances are you even have a MIPS64 Release 2 processor
>> 1515 in which case you should choose CPU_MIPS64_R2 instead for better
>> 1516 performance.
>> 1517
>> 1518 config CPU_MIPS64_R2
>> 1519 bool "MIPS64 Release 2"
>> 1520 depends on SYS_HAS_CPU_MIPS64_R2
>> 1521 select CPU_HAS_PREFETCH
>> 1522 select CPU_SUPPORTS_32BIT_KERNEL
>> 1523 select CPU_SUPPORTS_64BIT_KERNEL
>> 1524 select CPU_SUPPORTS_HIGHMEM
>> 1525 select CPU_SUPPORTS_HUGEPAGES
>> 1526 select CPU_SUPPORTS_MSA
>> 1527 select HAVE_KVM
>> 1528 help
>> 1529 Choose this option to build a kernel for release 2 or later of the
>> 1530 MIPS64 architecture. Many modern embedded systems with a 64-bit
>> 1531 MIPS processor are based on a MIPS64 processor. If you know the
>> 1532 specific type of processor in your system, choose those that one
>> 1533 otherwise CPU_MIPS64_R1 is a safe bet for any MIPS64 system.
>> 1534
>> 1535 config CPU_MIPS64_R6
>> 1536 bool "MIPS64 Release 6"
>> 1537 depends on SYS_HAS_CPU_MIPS64_R6
>> 1538 select CPU_HAS_PREFETCH
>> 1539 select CPU_SUPPORTS_32BIT_KERNEL
>> 1540 select CPU_SUPPORTS_64BIT_KERNEL
>> 1541 select CPU_SUPPORTS_HIGHMEM
>> 1542 select CPU_SUPPORTS_MSA
>> 1543 select GENERIC_CSUM
>> 1544 select MIPS_O32_FP64_SUPPORT if 32BIT || MIPS32_O32
>> 1545 select HAVE_KVM
>> 1546 help
>> 1547 Choose this option to build a kernel for release 6 or later of the
>> 1548 MIPS64 architecture. New MIPS processors, starting with the Warrior
>> 1549 family, are based on a MIPS64r6 processor. If you own an older
>> 1550 processor, you probably need to select MIPS64r1 or MIPS64r2 instead.
>> 1551
>> 1552 config CPU_R3000
>> 1553 bool "R3000"
>> 1554 depends on SYS_HAS_CPU_R3000
>> 1555 select CPU_HAS_WB
>> 1556 select CPU_SUPPORTS_32BIT_KERNEL
>> 1557 select CPU_SUPPORTS_HIGHMEM
>> 1558 help
>> 1559 Please make sure to pick the right CPU type. Linux/MIPS is not
>> 1560 designed to be generic, i.e. Kernels compiled for R3000 CPUs will
>> 1561 *not* work on R4000 machines and vice versa. However, since most
>> 1562 of the supported machines have an R4000 (or similar) CPU, R4x00
>> 1563 might be a safe bet. If the resulting kernel does not work,
>> 1564 try to recompile with R3000.
>> 1565
>> 1566 config CPU_TX39XX
>> 1567 bool "R39XX"
>> 1568 depends on SYS_HAS_CPU_TX39XX
>> 1569 select CPU_SUPPORTS_32BIT_KERNEL
>> 1570
>> 1571 config CPU_VR41XX
>> 1572 bool "R41xx"
>> 1573 depends on SYS_HAS_CPU_VR41XX
>> 1574 select CPU_SUPPORTS_32BIT_KERNEL
>> 1575 select CPU_SUPPORTS_64BIT_KERNEL
>> 1576 help
>> 1577 The options selects support for the NEC VR4100 series of processors.
>> 1578 Only choose this option if you have one of these processors as a
>> 1579 kernel built with this option will not run on any other type of
>> 1580 processor or vice versa.
>> 1581
>> 1582 config CPU_R4300
>> 1583 bool "R4300"
>> 1584 depends on SYS_HAS_CPU_R4300
>> 1585 select CPU_SUPPORTS_32BIT_KERNEL
>> 1586 select CPU_SUPPORTS_64BIT_KERNEL
>> 1587 help
>> 1588 MIPS Technologies R4300-series processors.
>> 1589
>> 1590 config CPU_R4X00
>> 1591 bool "R4x00"
>> 1592 depends on SYS_HAS_CPU_R4X00
>> 1593 select CPU_SUPPORTS_32BIT_KERNEL
>> 1594 select CPU_SUPPORTS_64BIT_KERNEL
>> 1595 select CPU_SUPPORTS_HUGEPAGES
>> 1596 help
>> 1597 MIPS Technologies R4000-series processors other than 4300, including
>> 1598 the R4000, R4400, R4600, and 4700.
>> 1599
>> 1600 config CPU_TX49XX
>> 1601 bool "R49XX"
>> 1602 depends on SYS_HAS_CPU_TX49XX
>> 1603 select CPU_HAS_PREFETCH
>> 1604 select CPU_SUPPORTS_32BIT_KERNEL
>> 1605 select CPU_SUPPORTS_64BIT_KERNEL
>> 1606 select CPU_SUPPORTS_HUGEPAGES
>> 1607
>> 1608 config CPU_R5000
>> 1609 bool "R5000"
>> 1610 depends on SYS_HAS_CPU_R5000
>> 1611 select CPU_SUPPORTS_32BIT_KERNEL
>> 1612 select CPU_SUPPORTS_64BIT_KERNEL
>> 1613 select CPU_SUPPORTS_HUGEPAGES
>> 1614 help
>> 1615 MIPS Technologies R5000-series processors other than the Nevada.
>> 1616
>> 1617 config CPU_R5432
>> 1618 bool "R5432"
>> 1619 depends on SYS_HAS_CPU_R5432
>> 1620 select CPU_SUPPORTS_32BIT_KERNEL
>> 1621 select CPU_SUPPORTS_64BIT_KERNEL
>> 1622 select CPU_SUPPORTS_HUGEPAGES
>> 1623
>> 1624 config CPU_R5500
>> 1625 bool "R5500"
>> 1626 depends on SYS_HAS_CPU_R5500
>> 1627 select CPU_SUPPORTS_32BIT_KERNEL
>> 1628 select CPU_SUPPORTS_64BIT_KERNEL
>> 1629 select CPU_SUPPORTS_HUGEPAGES
>> 1630 help
>> 1631 NEC VR5500 and VR5500A series processors implement 64-bit MIPS IV
>> 1632 instruction set.
>> 1633
>> 1634 config CPU_NEVADA
>> 1635 bool "RM52xx"
>> 1636 depends on SYS_HAS_CPU_NEVADA
>> 1637 select CPU_SUPPORTS_32BIT_KERNEL
>> 1638 select CPU_SUPPORTS_64BIT_KERNEL
>> 1639 select CPU_SUPPORTS_HUGEPAGES
>> 1640 help
>> 1641 QED / PMC-Sierra RM52xx-series ("Nevada") processors.
>> 1642
>> 1643 config CPU_R8000
>> 1644 bool "R8000"
>> 1645 depends on SYS_HAS_CPU_R8000
>> 1646 select CPU_HAS_PREFETCH
>> 1647 select CPU_SUPPORTS_64BIT_KERNEL
>> 1648 help
>> 1649 MIPS Technologies R8000 processors. Note these processors are
>> 1650 uncommon and the support for them is incomplete.
>> 1651
>> 1652 config CPU_R10000
>> 1653 bool "R10000"
>> 1654 depends on SYS_HAS_CPU_R10000
>> 1655 select CPU_HAS_PREFETCH
>> 1656 select CPU_SUPPORTS_32BIT_KERNEL
>> 1657 select CPU_SUPPORTS_64BIT_KERNEL
>> 1658 select CPU_SUPPORTS_HIGHMEM
>> 1659 select CPU_SUPPORTS_HUGEPAGES
>> 1660 help
>> 1661 MIPS Technologies R10000-series processors.
>> 1662
>> 1663 config CPU_RM7000
>> 1664 bool "RM7000"
>> 1665 depends on SYS_HAS_CPU_RM7000
>> 1666 select CPU_HAS_PREFETCH
>> 1667 select CPU_SUPPORTS_32BIT_KERNEL
>> 1668 select CPU_SUPPORTS_64BIT_KERNEL
>> 1669 select CPU_SUPPORTS_HIGHMEM
>> 1670 select CPU_SUPPORTS_HUGEPAGES
>> 1671
>> 1672 config CPU_SB1
>> 1673 bool "SB1"
>> 1674 depends on SYS_HAS_CPU_SB1
>> 1675 select CPU_SUPPORTS_32BIT_KERNEL
>> 1676 select CPU_SUPPORTS_64BIT_KERNEL
>> 1677 select CPU_SUPPORTS_HIGHMEM
>> 1678 select CPU_SUPPORTS_HUGEPAGES
>> 1679 select WEAK_ORDERING
>> 1680
>> 1681 config CPU_CAVIUM_OCTEON
>> 1682 bool "Cavium Octeon processor"
>> 1683 depends on SYS_HAS_CPU_CAVIUM_OCTEON
>> 1684 select CPU_HAS_PREFETCH
>> 1685 select CPU_SUPPORTS_64BIT_KERNEL
>> 1686 select WEAK_ORDERING
>> 1687 select CPU_SUPPORTS_HIGHMEM
>> 1688 select CPU_SUPPORTS_HUGEPAGES
>> 1689 select USB_EHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 1690 select USB_OHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 1691 select MIPS_L1_CACHE_SHIFT_7
>> 1692 select HAVE_KVM
>> 1693 help
>> 1694 The Cavium Octeon processor is a highly integrated chip containing
>> 1695 many ethernet hardware widgets for networking tasks. The processor
>> 1696 can have up to 16 Mips64v2 cores and 8 integrated gigabit ethernets.
>> 1697 Full details can be found at http://www.caviumnetworks.com.
>> 1698
>> 1699 config CPU_BMIPS
>> 1700 bool "Broadcom BMIPS"
>> 1701 depends on SYS_HAS_CPU_BMIPS
>> 1702 select CPU_MIPS32
>> 1703 select CPU_BMIPS32_3300 if SYS_HAS_CPU_BMIPS32_3300
>> 1704 select CPU_BMIPS4350 if SYS_HAS_CPU_BMIPS4350
>> 1705 select CPU_BMIPS4380 if SYS_HAS_CPU_BMIPS4380
>> 1706 select CPU_BMIPS5000 if SYS_HAS_CPU_BMIPS5000
>> 1707 select CPU_SUPPORTS_32BIT_KERNEL
>> 1708 select DMA_NONCOHERENT
>> 1709 select IRQ_MIPS_CPU
>> 1710 select SWAP_IO_SPACE
>> 1711 select WEAK_ORDERING
>> 1712 select CPU_SUPPORTS_HIGHMEM
>> 1713 select CPU_HAS_PREFETCH
>> 1714 select CPU_SUPPORTS_CPUFREQ
>> 1715 select MIPS_EXTERNAL_TIMER
>> 1716 help
>> 1717 Support for BMIPS32/3300/4350/4380 and BMIPS5000 processors.
>> 1718
>> 1719 config CPU_XLR
>> 1720 bool "Netlogic XLR SoC"
>> 1721 depends on SYS_HAS_CPU_XLR
>> 1722 select CPU_SUPPORTS_32BIT_KERNEL
>> 1723 select CPU_SUPPORTS_64BIT_KERNEL
>> 1724 select CPU_SUPPORTS_HIGHMEM
>> 1725 select CPU_SUPPORTS_HUGEPAGES
>> 1726 select WEAK_ORDERING
>> 1727 select WEAK_REORDERING_BEYOND_LLSC
>> 1728 help
>> 1729 Netlogic Microsystems XLR/XLS processors.
>> 1730
>> 1731 config CPU_XLP
>> 1732 bool "Netlogic XLP SoC"
>> 1733 depends on SYS_HAS_CPU_XLP
>> 1734 select CPU_SUPPORTS_32BIT_KERNEL
>> 1735 select CPU_SUPPORTS_64BIT_KERNEL
>> 1736 select CPU_SUPPORTS_HIGHMEM
>> 1737 select WEAK_ORDERING
>> 1738 select WEAK_REORDERING_BEYOND_LLSC
>> 1739 select CPU_HAS_PREFETCH
>> 1740 select CPU_MIPSR2
>> 1741 select CPU_SUPPORTS_HUGEPAGES
>> 1742 select MIPS_ASID_BITS_VARIABLE
>> 1743 help
>> 1744 Netlogic Microsystems XLP processors.
>> 1745 endchoice
979 1746
980 If unsure, say Y. !! 1747 config CPU_MIPS32_3_5_FEATURES
>> 1748 bool "MIPS32 Release 3.5 Features"
>> 1749 depends on SYS_HAS_CPU_MIPS32_R3_5
>> 1750 depends on CPU_MIPS32_R2 || CPU_MIPS32_R6
>> 1751 help
>> 1752 Choose this option to build a kernel for release 2 or later of the
>> 1753 MIPS32 architecture including features from the 3.5 release such as
>> 1754 support for Enhanced Virtual Addressing (EVA).
>> 1755
>> 1756 config CPU_MIPS32_3_5_EVA
>> 1757 bool "Enhanced Virtual Addressing (EVA)"
>> 1758 depends on CPU_MIPS32_3_5_FEATURES
>> 1759 select EVA
>> 1760 default y
>> 1761 help
>> 1762 Choose this option if you want to enable the Enhanced Virtual
>> 1763 Addressing (EVA) on your MIPS32 core (such as proAptiv).
>> 1764 One of its primary benefits is an increase in the maximum size
>> 1765 of lowmem (up to 3GB). If unsure, say 'N' here.
>> 1766
>> 1767 config CPU_MIPS32_R5_FEATURES
>> 1768 bool "MIPS32 Release 5 Features"
>> 1769 depends on SYS_HAS_CPU_MIPS32_R5
>> 1770 depends on CPU_MIPS32_R2
>> 1771 help
>> 1772 Choose this option to build a kernel for release 2 or later of the
>> 1773 MIPS32 architecture including features from release 5 such as
>> 1774 support for Extended Physical Addressing (XPA).
>> 1775
>> 1776 config CPU_MIPS32_R5_XPA
>> 1777 bool "Extended Physical Addressing (XPA)"
>> 1778 depends on CPU_MIPS32_R5_FEATURES
>> 1779 depends on !EVA
>> 1780 depends on !PAGE_SIZE_4KB
>> 1781 depends on SYS_SUPPORTS_HIGHMEM
>> 1782 select XPA
>> 1783 select HIGHMEM
>> 1784 select PHYS_ADDR_T_64BIT
>> 1785 default n
>> 1786 help
>> 1787 Choose this option if you want to enable the Extended Physical
>> 1788 Addressing (XPA) on your MIPS32 core (such as P5600 series). The
>> 1789 benefit is to increase physical addressing equal to or greater
>> 1790 than 40 bits. Note that this has the side effect of turning on
>> 1791 64-bit addressing which in turn makes the PTEs 64-bit in size.
>> 1792 If unsure, say 'N' here.
981 1793
982 config ARM64_ERRATUM_2038923 !! 1794 if CPU_LOONGSON2F
983 bool "Cortex-A510: 2038923: workaround !! 1795 config CPU_NOP_WORKAROUNDS
984 depends on CORESIGHT_TRBE !! 1796 bool
985 default y <<
986 help <<
987 This option adds the workaround for <<
988 <<
989 Affected Cortex-A510 core might caus <<
990 prohibited within the CPU. As a resu <<
991 might be corrupted. This happens aft <<
992 TRBLIMITR_EL1.E, followed by just a <<
993 execution changes from a context, in <<
994 isn't, or vice versa. In these menti <<
995 is prohibited is inconsistent betwee <<
996 the trace buffer state might be corr <<
997 <<
998 Work around this in the driver by pr <<
999 trace is prohibited or not based on <<
1000 change to TRBLIMITR_EL1.E with at l <<
1001 two ISB instructions if no ERET is <<
1002 1797
1003 If unsure, say Y. !! 1798 config CPU_JUMP_WORKAROUNDS
>> 1799 bool
1004 1800
1005 config ARM64_ERRATUM_1902691 !! 1801 config CPU_LOONGSON2F_WORKAROUNDS
1006 bool "Cortex-A510: 1902691: workaroun !! 1802 bool "Loongson 2F Workarounds"
1007 depends on CORESIGHT_TRBE <<
1008 default y 1803 default y
>> 1804 select CPU_NOP_WORKAROUNDS
>> 1805 select CPU_JUMP_WORKAROUNDS
1009 help 1806 help
1010 This option adds the workaround for !! 1807 Loongson 2F01 / 2F02 processors have the NOP & JUMP issues which
1011 !! 1808 require workarounds. Without workarounds the system may hang
1012 Affected Cortex-A510 core might cau !! 1809 unexpectedly. For more information please refer to the gas
1013 into the memory. Effectively TRBE i !! 1810 -mfix-loongson2f-nop and -mfix-loongson2f-jump options.
1014 trace data. !! 1811
>> 1812 Loongson 2F03 and later have fixed these issues and no workarounds
>> 1813 are needed. The workarounds have no significant side effect on them
>> 1814 but may decrease the performance of the system so this option should
>> 1815 be disabled unless the kernel is intended to be run on 2F01 or 2F02
>> 1816 systems.
1015 1817
1016 Work around this problem in the dri !! 1818 If unsure, please say Y.
1017 affected cpus. The firmware must ha !! 1819 endif # CPU_LOONGSON2F
1018 on such implementations. This will <<
1019 do this already. <<
1020 1820
1021 If unsure, say Y. !! 1821 config SYS_SUPPORTS_ZBOOT
>> 1822 bool
>> 1823 select HAVE_KERNEL_GZIP
>> 1824 select HAVE_KERNEL_BZIP2
>> 1825 select HAVE_KERNEL_LZ4
>> 1826 select HAVE_KERNEL_LZMA
>> 1827 select HAVE_KERNEL_LZO
>> 1828 select HAVE_KERNEL_XZ
1022 1829
1023 config ARM64_ERRATUM_2457168 !! 1830 config SYS_SUPPORTS_ZBOOT_UART16550
1024 bool "Cortex-A510: 2457168: workaroun !! 1831 bool
1025 depends on ARM64_AMU_EXTN !! 1832 select SYS_SUPPORTS_ZBOOT
1026 default y <<
1027 help <<
1028 This option adds the workaround for <<
1029 1833
1030 The AMU counter AMEVCNTR01 (constan !! 1834 config SYS_SUPPORTS_ZBOOT_UART_PROM
1031 as the system counter. On affected !! 1835 bool
1032 incorrectly giving a significantly !! 1836 select SYS_SUPPORTS_ZBOOT
1033 1837
1034 Work around this problem by returni !! 1838 config CPU_LOONGSON2
1035 key locations that results in disab !! 1839 bool
1036 is the same to firmware disabling a !! 1840 select CPU_SUPPORTS_32BIT_KERNEL
>> 1841 select CPU_SUPPORTS_64BIT_KERNEL
>> 1842 select CPU_SUPPORTS_HIGHMEM
>> 1843 select CPU_SUPPORTS_HUGEPAGES
>> 1844 select ARCH_HAS_PHYS_TO_DMA
1037 1845
1038 If unsure, say Y. !! 1846 config CPU_LOONGSON1
>> 1847 bool
>> 1848 select CPU_MIPS32
>> 1849 select CPU_MIPSR1
>> 1850 select CPU_HAS_PREFETCH
>> 1851 select CPU_SUPPORTS_32BIT_KERNEL
>> 1852 select CPU_SUPPORTS_HIGHMEM
>> 1853 select CPU_SUPPORTS_CPUFREQ
1039 1854
1040 config ARM64_ERRATUM_2645198 !! 1855 config CPU_BMIPS32_3300
1041 bool "Cortex-A715: 2645198: Workaroun !! 1856 select SMP_UP if SMP
1042 default y !! 1857 bool
1043 help <<
1044 This option adds the workaround for <<
1045 1858
1046 If a Cortex-A715 cpu sees a page ma !! 1859 config CPU_BMIPS4350
1047 to non-executable, it may corrupt t !! 1860 bool
1048 next instruction abort caused by pe !! 1861 select SYS_SUPPORTS_SMP
>> 1862 select SYS_SUPPORTS_HOTPLUG_CPU
1049 1863
1050 Only user-space does executable to !! 1864 config CPU_BMIPS4380
1051 mprotect() system call. Workaround !! 1865 bool
1052 TLB invalidation, for all changes t !! 1866 select MIPS_L1_CACHE_SHIFT_6
>> 1867 select SYS_SUPPORTS_SMP
>> 1868 select SYS_SUPPORTS_HOTPLUG_CPU
>> 1869 select CPU_HAS_RIXI
1053 1870
1054 If unsure, say Y. !! 1871 config CPU_BMIPS5000
>> 1872 bool
>> 1873 select MIPS_CPU_SCACHE
>> 1874 select MIPS_L1_CACHE_SHIFT_7
>> 1875 select SYS_SUPPORTS_SMP
>> 1876 select SYS_SUPPORTS_HOTPLUG_CPU
>> 1877 select CPU_HAS_RIXI
1055 1878
1056 config ARM64_WORKAROUND_SPECULATIVE_UNPRIV_LO !! 1879 config SYS_HAS_CPU_LOONGSON3
1057 bool 1880 bool
>> 1881 select CPU_SUPPORTS_CPUFREQ
>> 1882 select CPU_HAS_RIXI
1058 1883
1059 config ARM64_ERRATUM_2966298 !! 1884 config SYS_HAS_CPU_LOONGSON2E
1060 bool "Cortex-A520: 2966298: workaroun !! 1885 bool
1061 select ARM64_WORKAROUND_SPECULATIVE_U <<
1062 default y <<
1063 help <<
1064 This option adds the workaround for <<
1065 1886
1066 On an affected Cortex-A520 core, a !! 1887 config SYS_HAS_CPU_LOONGSON2F
1067 load might leak data from a privile !! 1888 bool
>> 1889 select CPU_SUPPORTS_CPUFREQ
>> 1890 select CPU_SUPPORTS_ADDRWINCFG if 64BIT
>> 1891 select CPU_SUPPORTS_UNCACHED_ACCELERATED
1068 1892
1069 Work around this problem by executi !! 1893 config SYS_HAS_CPU_LOONGSON1B
>> 1894 bool
1070 1895
1071 If unsure, say Y. !! 1896 config SYS_HAS_CPU_LOONGSON1C
>> 1897 bool
1072 1898
1073 config ARM64_ERRATUM_3117295 !! 1899 config SYS_HAS_CPU_MIPS32_R1
1074 bool "Cortex-A510: 3117295: workaroun !! 1900 bool
1075 select ARM64_WORKAROUND_SPECULATIVE_U <<
1076 default y <<
1077 help <<
1078 This option adds the workaround for <<
1079 1901
1080 On an affected Cortex-A510 core, a !! 1902 config SYS_HAS_CPU_MIPS32_R2
1081 load might leak data from a privile !! 1903 bool
1082 1904
1083 Work around this problem by executi !! 1905 config SYS_HAS_CPU_MIPS32_R3_5
>> 1906 bool
1084 1907
1085 If unsure, say Y. !! 1908 config SYS_HAS_CPU_MIPS32_R5
>> 1909 bool
1086 1910
1087 config ARM64_ERRATUM_3194386 !! 1911 config SYS_HAS_CPU_MIPS32_R6
1088 bool "Cortex-*/Neoverse-*: workaround !! 1912 bool
1089 default y <<
1090 help <<
1091 This option adds the workaround for <<
1092 1913
1093 * ARM Cortex-A76 erratum 3324349 !! 1914 config SYS_HAS_CPU_MIPS64_R1
1094 * ARM Cortex-A77 erratum 3324348 !! 1915 bool
1095 * ARM Cortex-A78 erratum 3324344 <<
1096 * ARM Cortex-A78C erratum 3324346 <<
1097 * ARM Cortex-A78C erratum 3324347 <<
1098 * ARM Cortex-A710 erratam 3324338 <<
1099 * ARM Cortex-A715 errartum 3456084 <<
1100 * ARM Cortex-A720 erratum 3456091 <<
1101 * ARM Cortex-A725 erratum 3456106 <<
1102 * ARM Cortex-X1 erratum 3324344 <<
1103 * ARM Cortex-X1C erratum 3324346 <<
1104 * ARM Cortex-X2 erratum 3324338 <<
1105 * ARM Cortex-X3 erratum 3324335 <<
1106 * ARM Cortex-X4 erratum 3194386 <<
1107 * ARM Cortex-X925 erratum 3324334 <<
1108 * ARM Neoverse-N1 erratum 3324349 <<
1109 * ARM Neoverse N2 erratum 3324339 <<
1110 * ARM Neoverse-N3 erratum 3456111 <<
1111 * ARM Neoverse-V1 erratum 3324341 <<
1112 * ARM Neoverse V2 erratum 3324336 <<
1113 * ARM Neoverse-V3 erratum 3312417 <<
1114 <<
1115 On affected cores "MSR SSBS, #0" in <<
1116 subsequent speculative instructions <<
1117 speculative store bypassing. <<
1118 <<
1119 Work around this problem by placing <<
1120 Instruction Synchronization Barrier <<
1121 SSBS. The presence of the SSBS spec <<
1122 from hwcaps and EL0 reads of ID_AA6 <<
1123 will use the PR_SPEC_STORE_BYPASS p <<
1124 1916
1125 If unsure, say Y. !! 1917 config SYS_HAS_CPU_MIPS64_R2
>> 1918 bool
1126 1919
1127 config CAVIUM_ERRATUM_22375 !! 1920 config SYS_HAS_CPU_MIPS64_R6
1128 bool "Cavium erratum 22375, 24313" !! 1921 bool
1129 default y <<
1130 help <<
1131 Enable workaround for errata 22375 <<
1132 1922
1133 This implements two gicv3-its errat !! 1923 config SYS_HAS_CPU_R3000
1134 with a small impact affecting only !! 1924 bool
1135 1925
1136 erratum 22375: only alloc 8MB tab !! 1926 config SYS_HAS_CPU_TX39XX
1137 erratum 24313: ignore memory acce !! 1927 bool
1138 1928
1139 The fixes are in ITS initialization !! 1929 config SYS_HAS_CPU_VR41XX
1140 type and table size provided by the !! 1930 bool
1141 1931
1142 If unsure, say Y. !! 1932 config SYS_HAS_CPU_R4300
>> 1933 bool
1143 1934
1144 config CAVIUM_ERRATUM_23144 !! 1935 config SYS_HAS_CPU_R4X00
1145 bool "Cavium erratum 23144: ITS SYNC !! 1936 bool
1146 depends on NUMA <<
1147 default y <<
1148 help <<
1149 ITS SYNC command hang for cross nod <<
1150 1937
1151 If unsure, say Y. !! 1938 config SYS_HAS_CPU_TX49XX
>> 1939 bool
1152 1940
1153 config CAVIUM_ERRATUM_23154 !! 1941 config SYS_HAS_CPU_R5000
1154 bool "Cavium errata 23154 and 38545: !! 1942 bool
1155 default y <<
1156 help <<
1157 The ThunderX GICv3 implementation r <<
1158 reading the IAR status to ensure da <<
1159 (access to icc_iar1_el1 is not sync <<
1160 1943
1161 It also suffers from erratum 38545 !! 1944 config SYS_HAS_CPU_R5432
1162 OcteonTX and OcteonTX2), resulting !! 1945 bool
1163 spuriously presented to the CPU int <<
1164 1946
1165 If unsure, say Y. !! 1947 config SYS_HAS_CPU_R5500
>> 1948 bool
1166 1949
1167 config CAVIUM_ERRATUM_27456 !! 1950 config SYS_HAS_CPU_NEVADA
1168 bool "Cavium erratum 27456: Broadcast !! 1951 bool
1169 default y <<
1170 help <<
1171 On ThunderX T88 pass 1.x through 2. <<
1172 instructions may cause the icache t <<
1173 contains data for a non-current ASI <<
1174 invalidate the icache when changing <<
1175 1952
1176 If unsure, say Y. !! 1953 config SYS_HAS_CPU_R8000
>> 1954 bool
1177 1955
1178 config CAVIUM_ERRATUM_30115 !! 1956 config SYS_HAS_CPU_R10000
1179 bool "Cavium erratum 30115: Guest may !! 1957 bool
1180 default y <<
1181 help <<
1182 On ThunderX T88 pass 1.x through 2. <<
1183 1.2, and T83 Pass 1.0, KVM guest ex <<
1184 interrupts in host. Trapping both G <<
1185 accesses sidesteps the issue. <<
1186 1958
1187 If unsure, say Y. !! 1959 config SYS_HAS_CPU_RM7000
>> 1960 bool
1188 1961
1189 config CAVIUM_TX2_ERRATUM_219 !! 1962 config SYS_HAS_CPU_SB1
1190 bool "Cavium ThunderX2 erratum 219: P !! 1963 bool
1191 default y <<
1192 help <<
1193 On Cavium ThunderX2, a load, store <<
1194 TTBR update and the corresponding c <<
1195 cause a spurious Data Abort to be d <<
1196 the CPU core. <<
1197 <<
1198 Work around the issue by avoiding t <<
1199 trapping KVM guest TTBRx_EL1 writes <<
1200 trap handler performs the correspon <<
1201 instruction and ensures context syn <<
1202 exception return. <<
1203 1964
1204 If unsure, say Y. !! 1965 config SYS_HAS_CPU_CAVIUM_OCTEON
>> 1966 bool
1205 1967
1206 config FUJITSU_ERRATUM_010001 !! 1968 config SYS_HAS_CPU_BMIPS
1207 bool "Fujitsu-A64FX erratum E#010001: !! 1969 bool
1208 default y <<
1209 help <<
1210 This option adds a workaround for F <<
1211 On some variants of the Fujitsu-A64 <<
1212 accesses may cause undefined fault <<
1213 This fault occurs under a specific <<
1214 load/store instruction performs an <<
1215 case-1 TTBR0_EL1 with TCR_EL1.NFD0 <<
1216 case-2 TTBR0_EL2 with TCR_EL2.NFD0 <<
1217 case-3 TTBR1_EL1 with TCR_EL1.NFD1 <<
1218 case-4 TTBR1_EL2 with TCR_EL2.NFD1 <<
1219 1970
1220 The workaround is to ensure these b !! 1971 config SYS_HAS_CPU_BMIPS32_3300
1221 The workaround only affects the Fuj !! 1972 bool
>> 1973 select SYS_HAS_CPU_BMIPS
1222 1974
1223 If unsure, say Y. !! 1975 config SYS_HAS_CPU_BMIPS4350
>> 1976 bool
>> 1977 select SYS_HAS_CPU_BMIPS
1224 1978
1225 config HISILICON_ERRATUM_161600802 !! 1979 config SYS_HAS_CPU_BMIPS4380
1226 bool "Hip07 161600802: Erroneous redi !! 1980 bool
1227 default y !! 1981 select SYS_HAS_CPU_BMIPS
1228 help <<
1229 The HiSilicon Hip07 SoC uses the wr <<
1230 when issued ITS commands such as VM <<
1231 a 128kB offset to be applied to the <<
1232 1982
1233 If unsure, say Y. !! 1983 config SYS_HAS_CPU_BMIPS5000
>> 1984 bool
>> 1985 select SYS_HAS_CPU_BMIPS
1234 1986
1235 config QCOM_FALKOR_ERRATUM_1003 !! 1987 config SYS_HAS_CPU_XLR
1236 bool "Falkor E1003: Incorrect transla !! 1988 bool
1237 default y <<
1238 help <<
1239 On Falkor v1, an incorrect ASID may <<
1240 and BADDR are changed together in T <<
1241 in TTBR1_EL1, this situation only o <<
1242 then only for entries in the walk c <<
1243 is unchanged. Work around the errat <<
1244 entries for the trampoline before e <<
1245 1989
1246 config QCOM_FALKOR_ERRATUM_1009 !! 1990 config SYS_HAS_CPU_XLP
1247 bool "Falkor E1009: Prematurely compl !! 1991 bool
1248 default y <<
1249 select ARM64_WORKAROUND_REPEAT_TLBI <<
1250 help <<
1251 On Falkor v1, the CPU may premature <<
1252 TLBI xxIS invalidate maintenance op <<
1253 one more time to fix the issue. <<
1254 1992
1255 If unsure, say Y. !! 1993 #
>> 1994 # CPU may reorder R->R, R->W, W->R, W->W
>> 1995 # Reordering beyond LL and SC is handled in WEAK_REORDERING_BEYOND_LLSC
>> 1996 #
>> 1997 config WEAK_ORDERING
>> 1998 bool
1256 1999
1257 config QCOM_QDF2400_ERRATUM_0065 !! 2000 #
1258 bool "QDF2400 E0065: Incorrect GITS_T !! 2001 # CPU may reorder reads and writes beyond LL/SC
1259 default y !! 2002 # CPU may reorder R->LL, R->LL, W->LL, W->LL, R->SC, R->SC, W->SC, W->SC
1260 help !! 2003 #
1261 On Qualcomm Datacenter Technologies !! 2004 config WEAK_REORDERING_BEYOND_LLSC
1262 ITE size incorrectly. The GITS_TYPE !! 2005 bool
1263 been indicated as 16Bytes (0xf), no !! 2006 endmenu
1264 2007
1265 If unsure, say Y. !! 2008 #
>> 2009 # These two indicate any level of the MIPS32 and MIPS64 architecture
>> 2010 #
>> 2011 config CPU_MIPS32
>> 2012 bool
>> 2013 default y if CPU_MIPS32_R1 || CPU_MIPS32_R2 || CPU_MIPS32_R6
1266 2014
1267 config QCOM_FALKOR_ERRATUM_E1041 !! 2015 config CPU_MIPS64
1268 bool "Falkor E1041: Speculative instr !! 2016 bool
1269 default y !! 2017 default y if CPU_MIPS64_R1 || CPU_MIPS64_R2 || CPU_MIPS64_R6
1270 help <<
1271 Falkor CPU may speculatively fetch <<
1272 memory location when MMU translatio <<
1273 to SCTLR_ELn[M]=0. Prefix an ISB in <<
1274 2018
1275 If unsure, say Y. !! 2019 #
>> 2020 # These two indicate the revision of the architecture, either Release 1 or Release 2
>> 2021 #
>> 2022 config CPU_MIPSR1
>> 2023 bool
>> 2024 default y if CPU_MIPS32_R1 || CPU_MIPS64_R1
1276 2025
1277 config NVIDIA_CARMEL_CNP_ERRATUM !! 2026 config CPU_MIPSR2
1278 bool "NVIDIA Carmel CNP: CNP on Carme !! 2027 bool
1279 default y !! 2028 default y if CPU_MIPS32_R2 || CPU_MIPS64_R2 || CPU_CAVIUM_OCTEON
1280 help !! 2029 select CPU_HAS_RIXI
1281 If CNP is enabled on Carmel cores, !! 2030 select MIPS_SPRAM
1282 invalidate shared TLB entries insta <<
1283 on standard ARM cores. <<
1284 2031
1285 If unsure, say Y. !! 2032 config CPU_MIPSR6
>> 2033 bool
>> 2034 default y if CPU_MIPS32_R6 || CPU_MIPS64_R6
>> 2035 select CPU_HAS_RIXI
>> 2036 select HAVE_ARCH_BITREVERSE
>> 2037 select MIPS_ASID_BITS_VARIABLE
>> 2038 select MIPS_CRC_SUPPORT
>> 2039 select MIPS_SPRAM
1286 2040
1287 config ROCKCHIP_ERRATUM_3588001 !! 2041 config EVA
1288 bool "Rockchip 3588001: GIC600 can no !! 2042 bool
1289 default y <<
1290 help <<
1291 The Rockchip RK3588 GIC600 SoC inte <<
1292 This means, that its sharability fe <<
1293 is supported by the IP itself. <<
1294 2043
1295 If unsure, say Y. !! 2044 config XPA
>> 2045 bool
1296 2046
1297 config SOCIONEXT_SYNQUACER_PREITS !! 2047 config SYS_SUPPORTS_32BIT_KERNEL
1298 bool "Socionext Synquacer: Workaround !! 2048 bool
1299 default y !! 2049 config SYS_SUPPORTS_64BIT_KERNEL
1300 help !! 2050 bool
1301 Socionext Synquacer SoCs implement !! 2051 config CPU_SUPPORTS_32BIT_KERNEL
1302 MSI doorbell writes with non-zero v !! 2052 bool
>> 2053 config CPU_SUPPORTS_64BIT_KERNEL
>> 2054 bool
>> 2055 config CPU_SUPPORTS_CPUFREQ
>> 2056 bool
>> 2057 config CPU_SUPPORTS_ADDRWINCFG
>> 2058 bool
>> 2059 config CPU_SUPPORTS_HUGEPAGES
>> 2060 bool
>> 2061 config CPU_SUPPORTS_UNCACHED_ACCELERATED
>> 2062 bool
>> 2063 config MIPS_PGD_C0_CONTEXT
>> 2064 bool
>> 2065 default y if 64BIT && (CPU_MIPSR2 || CPU_MIPSR6) && !CPU_XLP
1303 2066
1304 If unsure, say Y. !! 2067 #
>> 2068 # Set to y for ptrace access to watch registers.
>> 2069 #
>> 2070 config HARDWARE_WATCHPOINTS
>> 2071 bool
>> 2072 default y if CPU_MIPSR1 || CPU_MIPSR2 || CPU_MIPSR6
1305 2073
1306 endmenu # "ARM errata workarounds via the alt !! 2074 menu "Kernel type"
1307 2075
1308 choice 2076 choice
1309 prompt "Page size" !! 2077 prompt "Kernel code model"
1310 default ARM64_4K_PAGES <<
1311 help 2078 help
1312 Page size (translation granule) con !! 2079 You should only select this option if you have a workload that
1313 !! 2080 actually benefits from 64-bit processing or if your machine has
1314 config ARM64_4K_PAGES !! 2081 large memory. You will only be presented a single option in this
1315 bool "4KB" !! 2082 menu if your system does not support both 32-bit and 64-bit kernels.
1316 select HAVE_PAGE_SIZE_4KB !! 2083
>> 2084 config 32BIT
>> 2085 bool "32-bit kernel"
>> 2086 depends on CPU_SUPPORTS_32BIT_KERNEL && SYS_SUPPORTS_32BIT_KERNEL
>> 2087 select TRAD_SIGNALS
1317 help 2088 help
1318 This feature enables 4KB pages supp !! 2089 Select this option if you want to build a 32-bit kernel.
1319 2090
1320 config ARM64_16K_PAGES !! 2091 config 64BIT
1321 bool "16KB" !! 2092 bool "64-bit kernel"
1322 select HAVE_PAGE_SIZE_16KB !! 2093 depends on CPU_SUPPORTS_64BIT_KERNEL && SYS_SUPPORTS_64BIT_KERNEL
1323 help <<
1324 The system will use 16KB pages supp <<
1325 requires applications compiled with <<
1326 aligned segments. <<
1327 <<
1328 config ARM64_64K_PAGES <<
1329 bool "64KB" <<
1330 select HAVE_PAGE_SIZE_64KB <<
1331 help 2094 help
1332 This feature enables 64KB pages sup !! 2095 Select this option if you want to build a 64-bit kernel.
1333 allowing only two levels of page ta <<
1334 look-up. AArch32 emulation requires <<
1335 with 64K aligned segments. <<
1336 2096
1337 endchoice 2097 endchoice
1338 2098
>> 2099 config KVM_GUEST
>> 2100 bool "KVM Guest Kernel"
>> 2101 depends on BROKEN_ON_SMP
>> 2102 help
>> 2103 Select this option if building a guest kernel for KVM (Trap & Emulate)
>> 2104 mode.
>> 2105
>> 2106 config KVM_GUEST_TIMER_FREQ
>> 2107 int "Count/Compare Timer Frequency (MHz)"
>> 2108 depends on KVM_GUEST
>> 2109 default 100
>> 2110 help
>> 2111 Set this to non-zero if building a guest kernel for KVM to skip RTC
>> 2112 emulation when determining guest CPU Frequency. Instead, the guest's
>> 2113 timer frequency is specified directly.
>> 2114
>> 2115 config MIPS_VA_BITS_48
>> 2116 bool "48 bits virtual memory"
>> 2117 depends on 64BIT
>> 2118 help
>> 2119 Support a maximum at least 48 bits of application virtual
>> 2120 memory. Default is 40 bits or less, depending on the CPU.
>> 2121 For page sizes 16k and above, this option results in a small
>> 2122 memory overhead for page tables. For 4k page size, a fourth
>> 2123 level of page tables is added which imposes both a memory
>> 2124 overhead as well as slower TLB fault handling.
>> 2125
>> 2126 If unsure, say N.
>> 2127
1339 choice 2128 choice
1340 prompt "Virtual address space size" !! 2129 prompt "Kernel page size"
1341 default ARM64_VA_BITS_52 !! 2130 default PAGE_SIZE_4KB
1342 help <<
1343 Allows choosing one of multiple pos <<
1344 space sizes. The level of translati <<
1345 a combination of page size and virt <<
1346 <<
1347 config ARM64_VA_BITS_36 <<
1348 bool "36-bit" if EXPERT <<
1349 depends on PAGE_SIZE_16KB <<
1350 <<
1351 config ARM64_VA_BITS_39 <<
1352 bool "39-bit" <<
1353 depends on PAGE_SIZE_4KB <<
1354 <<
1355 config ARM64_VA_BITS_42 <<
1356 bool "42-bit" <<
1357 depends on PAGE_SIZE_64KB <<
1358 <<
1359 config ARM64_VA_BITS_47 <<
1360 bool "47-bit" <<
1361 depends on PAGE_SIZE_16KB <<
1362 <<
1363 config ARM64_VA_BITS_48 <<
1364 bool "48-bit" <<
1365 <<
1366 config ARM64_VA_BITS_52 <<
1367 bool "52-bit" <<
1368 depends on ARM64_PAN || !ARM64_SW_TTB <<
1369 help <<
1370 Enable 52-bit virtual addressing fo <<
1371 requested via a hint to mmap(). The <<
1372 virtual addresses for its own mappi <<
1373 this feature is available, otherwis <<
1374 <<
1375 NOTE: Enabling 52-bit virtual addre <<
1376 ARMv8.3 Pointer Authentication will <<
1377 reduced from 7 bits to 3 bits, whic <<
1378 impact on its susceptibility to bru <<
1379 2131
1380 If unsure, select 48-bit virtual ad !! 2132 config PAGE_SIZE_4KB
>> 2133 bool "4kB"
>> 2134 depends on !CPU_LOONGSON2 && !CPU_LOONGSON3
>> 2135 help
>> 2136 This option select the standard 4kB Linux page size. On some
>> 2137 R3000-family processors this is the only available page size. Using
>> 2138 4kB page size will minimize memory consumption and is therefore
>> 2139 recommended for low memory systems.
>> 2140
>> 2141 config PAGE_SIZE_8KB
>> 2142 bool "8kB"
>> 2143 depends on CPU_R8000 || CPU_CAVIUM_OCTEON
>> 2144 depends on !MIPS_VA_BITS_48
>> 2145 help
>> 2146 Using 8kB page size will result in higher performance kernel at
>> 2147 the price of higher memory consumption. This option is available
>> 2148 only on R8000 and cnMIPS processors. Note that you will need a
>> 2149 suitable Linux distribution to support this.
>> 2150
>> 2151 config PAGE_SIZE_16KB
>> 2152 bool "16kB"
>> 2153 depends on !CPU_R3000 && !CPU_TX39XX
>> 2154 help
>> 2155 Using 16kB page size will result in higher performance kernel at
>> 2156 the price of higher memory consumption. This option is available on
>> 2157 all non-R3000 family processors. Note that you will need a suitable
>> 2158 Linux distribution to support this.
>> 2159
>> 2160 config PAGE_SIZE_32KB
>> 2161 bool "32kB"
>> 2162 depends on CPU_CAVIUM_OCTEON
>> 2163 depends on !MIPS_VA_BITS_48
>> 2164 help
>> 2165 Using 32kB page size will result in higher performance kernel at
>> 2166 the price of higher memory consumption. This option is available
>> 2167 only on cnMIPS cores. Note that you will need a suitable Linux
>> 2168 distribution to support this.
>> 2169
>> 2170 config PAGE_SIZE_64KB
>> 2171 bool "64kB"
>> 2172 depends on !CPU_R3000 && !CPU_TX39XX
>> 2173 help
>> 2174 Using 64kB page size will result in higher performance kernel at
>> 2175 the price of higher memory consumption. This option is available on
>> 2176 all non-R3000 family processor. Not that at the time of this
>> 2177 writing this option is still high experimental.
1381 2178
1382 endchoice 2179 endchoice
1383 2180
1384 config ARM64_FORCE_52BIT !! 2181 config FORCE_MAX_ZONEORDER
1385 bool "Force 52-bit virtual addresses !! 2182 int "Maximum zone order"
1386 depends on ARM64_VA_BITS_52 && EXPERT !! 2183 range 14 64 if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_64KB
1387 help !! 2184 default "14" if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_64KB
1388 For systems with 52-bit userspace V !! 2185 range 13 64 if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_32KB
1389 to maintain compatibility with olde !! 2186 default "13" if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_32KB
1390 unless a hint is supplied to mmap. !! 2187 range 12 64 if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_16KB
1391 !! 2188 default "12" if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_16KB
1392 This configuration option disables !! 2189 range 11 64
1393 forces all userspace addresses to b !! 2190 default "11"
1394 should only enable this configurati !! 2191 help
1395 memory management code. If unsure s !! 2192 The kernel memory allocator divides physically contiguous memory
>> 2193 blocks into "zones", where each zone is a power of two number of
>> 2194 pages. This option selects the largest power of two that the kernel
>> 2195 keeps in the memory allocator. If you need to allocate very large
>> 2196 blocks of physically contiguous memory, then you may need to
>> 2197 increase this value.
1396 2198
1397 config ARM64_VA_BITS !! 2199 This config option is actually maximum order plus one. For example,
1398 int !! 2200 a value of 11 means that the largest free memory block is 2^10 pages.
1399 default 36 if ARM64_VA_BITS_36 <<
1400 default 39 if ARM64_VA_BITS_39 <<
1401 default 42 if ARM64_VA_BITS_42 <<
1402 default 47 if ARM64_VA_BITS_47 <<
1403 default 48 if ARM64_VA_BITS_48 <<
1404 default 52 if ARM64_VA_BITS_52 <<
1405 2201
1406 choice !! 2202 The page size is not necessarily 4KB. Keep this in mind
1407 prompt "Physical address space size" !! 2203 when choosing a value for this option.
1408 default ARM64_PA_BITS_48 <<
1409 help <<
1410 Choose the maximum physical address <<
1411 support. <<
1412 2204
1413 config ARM64_PA_BITS_48 !! 2205 config BOARD_SCACHE
1414 bool "48-bit" !! 2206 bool
1415 depends on ARM64_64K_PAGES || !ARM64_ <<
1416 <<
1417 config ARM64_PA_BITS_52 <<
1418 bool "52-bit" <<
1419 depends on ARM64_64K_PAGES || ARM64_V <<
1420 depends on ARM64_PAN || !ARM64_SW_TTB <<
1421 help <<
1422 Enable support for a 52-bit physica <<
1423 part of the ARMv8.2-LPA extension. <<
1424 <<
1425 With this enabled, the kernel will <<
1426 do not support ARMv8.2-LPA, but wit <<
1427 minor performance overhead). <<
1428 2207
1429 endchoice !! 2208 config IP22_CPU_SCACHE
>> 2209 bool
>> 2210 select BOARD_SCACHE
1430 2211
1431 config ARM64_PA_BITS !! 2212 #
1432 int !! 2213 # Support for a MIPS32 / MIPS64 style S-caches
1433 default 48 if ARM64_PA_BITS_48 !! 2214 #
1434 default 52 if ARM64_PA_BITS_52 !! 2215 config MIPS_CPU_SCACHE
>> 2216 bool
>> 2217 select BOARD_SCACHE
1435 2218
1436 config ARM64_LPA2 !! 2219 config R5000_CPU_SCACHE
1437 def_bool y !! 2220 bool
1438 depends on ARM64_PA_BITS_52 && !ARM64 !! 2221 select BOARD_SCACHE
1439 2222
1440 choice !! 2223 config RM7000_CPU_SCACHE
1441 prompt "Endianness" !! 2224 bool
1442 default CPU_LITTLE_ENDIAN !! 2225 select BOARD_SCACHE
1443 help <<
1444 Select the endianness of data acces <<
1445 applications will need to be compil <<
1446 that is selected here. <<
1447 2226
1448 config CPU_BIG_ENDIAN !! 2227 config SIBYTE_DMA_PAGEOPS
1449 bool "Build big-endian kernel" !! 2228 bool "Use DMA to clear/copy pages"
1450 # https://github.com/llvm/llvm-projec !! 2229 depends on CPU_SB1
1451 depends on AS_IS_GNU || AS_VERSION >= <<
1452 help 2230 help
1453 Say Y if you plan on running a kern !! 2231 Instead of using the CPU to zero and copy pages, use a Data Mover
>> 2232 channel. These DMA channels are otherwise unused by the standard
>> 2233 SiByte Linux port. Seems to give a small performance benefit.
1454 2234
1455 config CPU_LITTLE_ENDIAN !! 2235 config CPU_HAS_PREFETCH
1456 bool "Build little-endian kernel" !! 2236 bool
1457 help <<
1458 Say Y if you plan on running a kern <<
1459 This is usually the case for distri <<
1460 2237
1461 endchoice !! 2238 config CPU_GENERIC_DUMP_TLB
>> 2239 bool
>> 2240 default y if !(CPU_R3000 || CPU_R8000 || CPU_TX39XX)
1462 2241
1463 config SCHED_MC !! 2242 config CPU_R4K_FPU
1464 bool "Multi-core scheduler support" !! 2243 bool
1465 help !! 2244 default y if !(CPU_R3000 || CPU_TX39XX)
1466 Multi-core scheduler support improv <<
1467 making when dealing with multi-core <<
1468 increased overhead in some places. <<
1469 2245
1470 config SCHED_CLUSTER !! 2246 config CPU_R4K_CACHE_TLB
1471 bool "Cluster scheduler support" !! 2247 bool
1472 help !! 2248 default y if !(CPU_R3000 || CPU_R8000 || CPU_SB1 || CPU_TX39XX || CPU_CAVIUM_OCTEON)
1473 Cluster scheduler support improves !! 2249
1474 making when dealing with machines t !! 2250 config MIPS_MT_SMP
1475 Cluster usually means a couple of C !! 2251 bool "MIPS MT SMP support (1 TC on each available VPE)"
1476 by sharing mid-level caches, last-l !! 2252 default y
1477 busses. !! 2253 depends on SYS_SUPPORTS_MULTITHREADING && !CPU_MIPSR6 && !CPU_MICROMIPS
>> 2254 select CPU_MIPSR2_IRQ_VI
>> 2255 select CPU_MIPSR2_IRQ_EI
>> 2256 select SYNC_R4K
>> 2257 select MIPS_MT
>> 2258 select SMP
>> 2259 select SMP_UP
>> 2260 select SYS_SUPPORTS_SMP
>> 2261 select SYS_SUPPORTS_SCHED_SMT
>> 2262 select MIPS_PERF_SHARED_TC_COUNTERS
>> 2263 help
>> 2264 This is a kernel model which is known as SMVP. This is supported
>> 2265 on cores with the MT ASE and uses the available VPEs to implement
>> 2266 virtual processors which supports SMP. This is equivalent to the
>> 2267 Intel Hyperthreading feature. For further information go to
>> 2268 <http://www.imgtec.com/mips/mips-multithreading.asp>.
>> 2269
>> 2270 config MIPS_MT
>> 2271 bool
1478 2272
1479 config SCHED_SMT 2273 config SCHED_SMT
1480 bool "SMT scheduler support" !! 2274 bool "SMT (multithreading) scheduler support"
>> 2275 depends on SYS_SUPPORTS_SCHED_SMT
>> 2276 default n
1481 help 2277 help
1482 Improves the CPU scheduler's decisi !! 2278 SMT scheduler support improves the CPU scheduler's decision making
1483 MultiThreading at a cost of slightl !! 2279 when dealing with MIPS MT enabled cores at a cost of slightly
1484 places. If unsure say N here. !! 2280 increased overhead in some places. If unsure say N here.
1485 2281
1486 config NR_CPUS !! 2282 config SYS_SUPPORTS_SCHED_SMT
1487 int "Maximum number of CPUs (2-4096)" !! 2283 bool
1488 range 2 4096 <<
1489 default "512" <<
1490 2284
1491 config HOTPLUG_CPU !! 2285 config SYS_SUPPORTS_MULTITHREADING
1492 bool "Support for hot-pluggable CPUs" !! 2286 bool
1493 select GENERIC_IRQ_MIGRATION <<
1494 help <<
1495 Say Y here to experiment with turni <<
1496 can be controlled through /sys/devi <<
1497 2287
1498 # Common NUMA Features !! 2288 config MIPS_MT_FPAFF
1499 config NUMA !! 2289 bool "Dynamic FPU affinity for FP-intensive threads"
1500 bool "NUMA Memory Allocation and Sche !! 2290 default y
1501 select GENERIC_ARCH_NUMA !! 2291 depends on MIPS_MT_SMP
1502 select OF_NUMA <<
1503 select HAVE_SETUP_PER_CPU_AREA <<
1504 select NEED_PER_CPU_EMBED_FIRST_CHUNK <<
1505 select NEED_PER_CPU_PAGE_FIRST_CHUNK <<
1506 select USE_PERCPU_NUMA_NODE_ID <<
1507 help <<
1508 Enable NUMA (Non-Uniform Memory Acc <<
1509 <<
1510 The kernel will try to allocate mem <<
1511 local memory of the CPU and add som <<
1512 NUMA awareness to the kernel. <<
1513 2292
1514 config NODES_SHIFT !! 2293 config MIPSR2_TO_R6_EMULATOR
1515 int "Maximum NUMA Nodes (as a power o !! 2294 bool "MIPS R2-to-R6 emulator"
1516 range 1 10 !! 2295 depends on CPU_MIPSR6
1517 default "4" !! 2296 default y
1518 depends on NUMA <<
1519 help 2297 help
1520 Specify the maximum number of NUMA !! 2298 Choose this option if you want to run non-R6 MIPS userland code.
1521 system. Increases memory reserved !! 2299 Even if you say 'Y' here, the emulator will still be disabled by
>> 2300 default. You can enable it using the 'mipsr2emu' kernel option.
>> 2301 The only reason this is a build-time option is to save ~14K from the
>> 2302 final kernel image.
1522 2303
1523 source "kernel/Kconfig.hz" !! 2304 config SYS_SUPPORTS_VPE_LOADER
1524 !! 2305 bool
1525 config ARCH_SPARSEMEM_ENABLE !! 2306 depends on SYS_SUPPORTS_MULTITHREADING
1526 def_bool y !! 2307 help
1527 select SPARSEMEM_VMEMMAP_ENABLE !! 2308 Indicates that the platform supports the VPE loader, and provides
1528 select SPARSEMEM_VMEMMAP !! 2309 physical_memsize.
1529 2310
1530 config HW_PERF_EVENTS !! 2311 config MIPS_VPE_LOADER
1531 def_bool y !! 2312 bool "VPE loader support."
1532 depends on ARM_PMU !! 2313 depends on SYS_SUPPORTS_VPE_LOADER && MODULES
>> 2314 select CPU_MIPSR2_IRQ_VI
>> 2315 select CPU_MIPSR2_IRQ_EI
>> 2316 select MIPS_MT
>> 2317 help
>> 2318 Includes a loader for loading an elf relocatable object
>> 2319 onto another VPE and running it.
1533 2320
1534 # Supported by clang >= 7.0 or GCC >= 12.0.0 !! 2321 config MIPS_VPE_LOADER_CMP
1535 config CC_HAVE_SHADOW_CALL_STACK !! 2322 bool
1536 def_bool $(cc-option, -fsanitize=shad !! 2323 default "y"
>> 2324 depends on MIPS_VPE_LOADER && MIPS_CMP
1537 2325
1538 config PARAVIRT !! 2326 config MIPS_VPE_LOADER_MT
1539 bool "Enable paravirtualization code" !! 2327 bool
1540 help !! 2328 default "y"
1541 This changes the kernel so it can m !! 2329 depends on MIPS_VPE_LOADER && !MIPS_CMP
1542 under a hypervisor, potentially imp <<
1543 over full virtualization. <<
1544 2330
1545 config PARAVIRT_TIME_ACCOUNTING !! 2331 config MIPS_VPE_LOADER_TOM
1546 bool "Paravirtual steal time accounti !! 2332 bool "Load VPE program into memory hidden from linux"
1547 select PARAVIRT !! 2333 depends on MIPS_VPE_LOADER
>> 2334 default y
1548 help 2335 help
1549 Select this option to enable fine g !! 2336 The loader can use memory that is present but has been hidden from
1550 accounting. Time spent executing ot !! 2337 Linux using the kernel command line option "mem=xxMB". It's up to
1551 the current vCPU is discounted from !! 2338 you to ensure the amount you put in the option and the space your
1552 that, there can be a small performa !! 2339 program requires is less or equal to the amount physically present.
1553 2340
1554 If in doubt, say N here. !! 2341 config MIPS_VPE_APSP_API
>> 2342 bool "Enable support for AP/SP API (RTLX)"
>> 2343 depends on MIPS_VPE_LOADER
1555 2344
1556 config ARCH_SUPPORTS_KEXEC !! 2345 config MIPS_VPE_APSP_API_CMP
1557 def_bool PM_SLEEP_SMP !! 2346 bool
>> 2347 default "y"
>> 2348 depends on MIPS_VPE_APSP_API && MIPS_CMP
1558 2349
1559 config ARCH_SUPPORTS_KEXEC_FILE !! 2350 config MIPS_VPE_APSP_API_MT
1560 def_bool y !! 2351 bool
>> 2352 default "y"
>> 2353 depends on MIPS_VPE_APSP_API && !MIPS_CMP
1561 2354
1562 config ARCH_SELECTS_KEXEC_FILE !! 2355 config MIPS_CMP
1563 def_bool y !! 2356 bool "MIPS CMP framework support (DEPRECATED)"
1564 depends on KEXEC_FILE !! 2357 depends on SYS_SUPPORTS_MIPS_CMP && !CPU_MIPSR6
1565 select HAVE_IMA_KEXEC if IMA !! 2358 select SMP
>> 2359 select SYNC_R4K
>> 2360 select SYS_SUPPORTS_SMP
>> 2361 select WEAK_ORDERING
>> 2362 default n
>> 2363 help
>> 2364 Select this if you are using a bootloader which implements the "CMP
>> 2365 framework" protocol (ie. YAMON) and want your kernel to make use of
>> 2366 its ability to start secondary CPUs.
>> 2367
>> 2368 Unless you have a specific need, you should use CONFIG_MIPS_CPS
>> 2369 instead of this.
>> 2370
>> 2371 config MIPS_CPS
>> 2372 bool "MIPS Coherent Processing System support"
>> 2373 depends on SYS_SUPPORTS_MIPS_CPS
>> 2374 select MIPS_CM
>> 2375 select MIPS_CPS_PM if HOTPLUG_CPU
>> 2376 select SMP
>> 2377 select SYNC_R4K if (CEVT_R4K || CSRC_R4K)
>> 2378 select SYS_SUPPORTS_HOTPLUG_CPU
>> 2379 select SYS_SUPPORTS_SCHED_SMT if CPU_MIPSR6
>> 2380 select SYS_SUPPORTS_SMP
>> 2381 select WEAK_ORDERING
>> 2382 help
>> 2383 Select this if you wish to run an SMP kernel across multiple cores
>> 2384 within a MIPS Coherent Processing System. When this option is
>> 2385 enabled the kernel will probe for other cores and boot them with
>> 2386 no external assistance. It is safe to enable this when hardware
>> 2387 support is unavailable.
1566 2388
1567 config ARCH_SUPPORTS_KEXEC_SIG !! 2389 config MIPS_CPS_PM
1568 def_bool y !! 2390 depends on MIPS_CPS
>> 2391 bool
1569 2392
1570 config ARCH_SUPPORTS_KEXEC_IMAGE_VERIFY_SIG !! 2393 config MIPS_CM
1571 def_bool y !! 2394 bool
>> 2395 select MIPS_CPC
1572 2396
1573 config ARCH_DEFAULT_KEXEC_IMAGE_VERIFY_SIG !! 2397 config MIPS_CPC
1574 def_bool y !! 2398 bool
1575 2399
1576 config ARCH_SUPPORTS_CRASH_DUMP !! 2400 config SB1_PASS_2_WORKAROUNDS
1577 def_bool y !! 2401 bool
>> 2402 depends on CPU_SB1 && (CPU_SB1_PASS_2_2 || CPU_SB1_PASS_2)
>> 2403 default y
1578 2404
1579 config ARCH_HAS_GENERIC_CRASHKERNEL_RESERVATI !! 2405 config SB1_PASS_2_1_WORKAROUNDS
1580 def_bool CRASH_RESERVE !! 2406 bool
>> 2407 depends on CPU_SB1 && CPU_SB1_PASS_2
>> 2408 default y
1581 2409
1582 config TRANS_TABLE <<
1583 def_bool y <<
1584 depends on HIBERNATION || KEXEC_CORE <<
1585 2410
1586 config XEN_DOM0 !! 2411 choice
1587 def_bool y !! 2412 prompt "SmartMIPS or microMIPS ASE support"
1588 depends on XEN <<
1589 2413
1590 config XEN !! 2414 config CPU_NEEDS_NO_SMARTMIPS_OR_MICROMIPS
1591 bool "Xen guest support on ARM64" !! 2415 bool "None"
1592 depends on ARM64 && OF <<
1593 select SWIOTLB_XEN <<
1594 select PARAVIRT <<
1595 help 2416 help
1596 Say Y if you want to run Linux in a !! 2417 Select this if you want neither microMIPS nor SmartMIPS support
1597 2418
1598 # include/linux/mmzone.h requires the followi !! 2419 config CPU_HAS_SMARTMIPS
1599 # !! 2420 depends on SYS_SUPPORTS_SMARTMIPS
1600 # MAX_PAGE_ORDER + PAGE_SHIFT <= SECTION_SI !! 2421 bool "SmartMIPS"
1601 # !! 2422 help
1602 # so the maximum value of MAX_PAGE_ORDER is S !! 2423 SmartMIPS is a extension of the MIPS32 architecture aimed at
1603 # !! 2424 increased security at both hardware and software level for
1604 # | SECTION_SIZE_BITS | PAGE_SHIFT | m !! 2425 smartcards. Enabling this option will allow proper use of the
1605 # ----+-------------------+--------------+--- !! 2426 SmartMIPS instructions by Linux applications. However a kernel with
1606 # 4K | 27 | 12 | !! 2427 this option will not work on a MIPS core without SmartMIPS core. If
1607 # 16K | 27 | 14 | !! 2428 you don't know you probably don't have SmartMIPS and should say N
1608 # 64K | 29 | 16 | !! 2429 here.
1609 config ARCH_FORCE_MAX_ORDER !! 2430
1610 int !! 2431 config CPU_MICROMIPS
1611 default "13" if ARM64_64K_PAGES !! 2432 depends on 32BIT && SYS_SUPPORTS_MICROMIPS && !CPU_MIPSR6
1612 default "11" if ARM64_16K_PAGES !! 2433 bool "microMIPS"
1613 default "10" <<
1614 help 2434 help
1615 The kernel page allocator limits th !! 2435 When this option is enabled the kernel will be built using the
1616 contiguous allocations. The limit i !! 2436 microMIPS ISA
1617 defines the maximal power of two of <<
1618 allocated as a single contiguous bl <<
1619 overriding the default setting when <<
1620 large blocks of physically contiguo <<
1621 <<
1622 The maximal size of allocation cann <<
1623 section, so the value of MAX_PAGE_O <<
1624 <<
1625 MAX_PAGE_ORDER + PAGE_SHIFT <= SE <<
1626 2437
1627 Don't change if unsure. !! 2438 endchoice
1628 2439
1629 config UNMAP_KERNEL_AT_EL0 !! 2440 config CPU_HAS_MSA
1630 bool "Unmap kernel when running in us !! 2441 bool "Support for the MIPS SIMD Architecture"
1631 default y !! 2442 depends on CPU_SUPPORTS_MSA
1632 help !! 2443 depends on 64BIT || MIPS_O32_FP64_SUPPORT
1633 Speculation attacks against some hi !! 2444 help
1634 be used to bypass MMU permission ch !! 2445 MIPS SIMD Architecture (MSA) introduces 128 bit wide vector registers
1635 userspace. This can be defended aga !! 2446 and a set of SIMD instructions to operate on them. When this option
1636 when running in userspace, mapping !! 2447 is enabled the kernel will support allocating & switching MSA
1637 via a trampoline page in the vector !! 2448 vector register contexts. If you know that your kernel will only be
>> 2449 running on CPUs which do not support MSA or that your userland will
>> 2450 not be making use of it then you may wish to say N here to reduce
>> 2451 the size & complexity of your kernel.
1638 2452
1639 If unsure, say Y. 2453 If unsure, say Y.
1640 2454
1641 config MITIGATE_SPECTRE_BRANCH_HISTORY !! 2455 config CPU_HAS_WB
1642 bool "Mitigate Spectre style attacks !! 2456 bool
1643 default y <<
1644 help <<
1645 Speculation attacks against some hi <<
1646 make use of branch history to influ <<
1647 When taking an exception from user- <<
1648 or a firmware call overwrites the b <<
1649 <<
1650 config RODATA_FULL_DEFAULT_ENABLED <<
1651 bool "Apply r/o permissions of VM are <<
1652 default y <<
1653 help <<
1654 Apply read-only attributes of VM ar <<
1655 the backing pages as well. This pre <<
1656 from being modified (inadvertently <<
1657 mapping of the same memory page. Th <<
1658 be turned off at runtime by passing <<
1659 with rodata=full if this option is <<
1660 2457
1661 This requires the linear region to !! 2458 config XKS01
1662 which may adversely affect performa !! 2459 bool
1663 2460
1664 config ARM64_SW_TTBR0_PAN !! 2461 config CPU_HAS_RIXI
1665 bool "Emulate Privileged Access Never !! 2462 bool
1666 depends on !KCSAN <<
1667 help <<
1668 Enabling this option prevents the k <<
1669 user-space memory directly by point <<
1670 zeroed area and reserved ASID. The <<
1671 restore the valid TTBR0_EL1 tempora <<
1672 2463
1673 config ARM64_TAGGED_ADDR_ABI !! 2464 #
1674 bool "Enable the tagged user addresse !! 2465 # Vectored interrupt mode is an R2 feature
1675 default y !! 2466 #
1676 help !! 2467 config CPU_MIPSR2_IRQ_VI
1677 When this option is enabled, user a !! 2468 bool
1678 relaxed ABI via prctl() allowing ta <<
1679 to system calls as pointer argument <<
1680 Documentation/arch/arm64/tagged-add <<
1681 2469
1682 menuconfig COMPAT !! 2470 #
1683 bool "Kernel support for 32-bit EL0" !! 2471 # Extended interrupt mode is an R2 feature
1684 depends on ARM64_4K_PAGES || EXPERT !! 2472 #
1685 select HAVE_UID16 !! 2473 config CPU_MIPSR2_IRQ_EI
1686 select OLD_SIGSUSPEND3 !! 2474 bool
1687 select COMPAT_OLD_SIGACTION <<
1688 help <<
1689 This option enables support for a 3 <<
1690 kernel at EL1. AArch32-specific com <<
1691 the user helper functions, VFP supp <<
1692 handled appropriately by the kernel <<
1693 2475
1694 If you use a page size other than 4 !! 2476 config CPU_HAS_SYNC
1695 that you will only be able to execu !! 2477 bool
1696 with page size aligned segments. !! 2478 depends on !CPU_R3000
>> 2479 default y
1697 2480
1698 If you want to execute 32-bit users !! 2481 #
>> 2482 # CPU non-features
>> 2483 #
>> 2484 config CPU_DADDI_WORKAROUNDS
>> 2485 bool
1699 2486
1700 if COMPAT !! 2487 config CPU_R4000_WORKAROUNDS
>> 2488 bool
>> 2489 select CPU_R4400_WORKAROUNDS
1701 2490
1702 config KUSER_HELPERS !! 2491 config CPU_R4400_WORKAROUNDS
1703 bool "Enable kuser helpers page for 3 !! 2492 bool
1704 default y <<
1705 help <<
1706 Warning: disabling this option may <<
1707 2493
1708 Provide kuser helpers to compat tas !! 2494 config MIPS_ASID_SHIFT
1709 helper code to userspace in read on !! 2495 int
1710 to allow userspace to be independen !! 2496 default 6 if CPU_R3000 || CPU_TX39XX
1711 the system. This permits binaries t !! 2497 default 4 if CPU_R8000
1712 to ARMv8 without modification. !! 2498 default 0
1713 2499
1714 See Documentation/arch/arm/kernel_u !! 2500 config MIPS_ASID_BITS
>> 2501 int
>> 2502 default 0 if MIPS_ASID_BITS_VARIABLE
>> 2503 default 6 if CPU_R3000 || CPU_TX39XX
>> 2504 default 8
1715 2505
1716 However, the fixed address nature o !! 2506 config MIPS_ASID_BITS_VARIABLE
1717 by ROP (return orientated programmi !! 2507 bool
1718 exploits. <<
1719 2508
1720 If all of the binaries and librarie !! 2509 config MIPS_CRC_SUPPORT
1721 are built specifically for your pla !! 2510 bool
1722 these helpers, then you can turn th <<
1723 such exploits. However, in that cas <<
1724 relying on those helpers is run, it <<
1725 2511
1726 Say N here only if you are absolute !! 2512 #
1727 need these helpers; otherwise, the !! 2513 # - Highmem only makes sense for the 32-bit kernel.
>> 2514 # - The current highmem code will only work properly on physically indexed
>> 2515 # caches such as R3000, SB1, R7000 or those that look like they're virtually
>> 2516 # indexed such as R4000/R4400 SC and MC versions or R10000. So for the
>> 2517 # moment we protect the user and offer the highmem option only on machines
>> 2518 # where it's known to be safe. This will not offer highmem on a few systems
>> 2519 # such as MIPS32 and MIPS64 CPUs which may have virtual and physically
>> 2520 # indexed CPUs but we're playing safe.
>> 2521 # - We use SYS_SUPPORTS_HIGHMEM to offer highmem only for systems where we
>> 2522 # know they might have memory configurations that could make use of highmem
>> 2523 # support.
>> 2524 #
>> 2525 config HIGHMEM
>> 2526 bool "High Memory Support"
>> 2527 depends on 32BIT && CPU_SUPPORTS_HIGHMEM && SYS_SUPPORTS_HIGHMEM && !CPU_MIPS32_3_5_EVA
1728 2528
1729 config COMPAT_VDSO !! 2529 config CPU_SUPPORTS_HIGHMEM
1730 bool "Enable vDSO for 32-bit applicat !! 2530 bool
1731 depends on !CPU_BIG_ENDIAN <<
1732 depends on (CC_IS_CLANG && LD_IS_LLD) <<
1733 select GENERIC_COMPAT_VDSO <<
1734 default y <<
1735 help <<
1736 Place in the process address space <<
1737 ELF shared object providing fast im <<
1738 and clock_gettime. <<
1739 2531
1740 You must have a 32-bit build of gli !! 2532 config SYS_SUPPORTS_HIGHMEM
1741 to seamlessly take advantage of thi !! 2533 bool
1742 2534
1743 config THUMB2_COMPAT_VDSO !! 2535 config SYS_SUPPORTS_SMARTMIPS
1744 bool "Compile the 32-bit vDSO for Thu !! 2536 bool
1745 depends on COMPAT_VDSO <<
1746 default y <<
1747 help <<
1748 Compile the compat vDSO with '-mthu <<
1749 otherwise with '-marm'. <<
1750 2537
1751 config COMPAT_ALIGNMENT_FIXUPS !! 2538 config SYS_SUPPORTS_MICROMIPS
1752 bool "Fix up misaligned multi-word lo !! 2539 bool
1753 2540
1754 menuconfig ARMV8_DEPRECATED !! 2541 config SYS_SUPPORTS_MIPS16
1755 bool "Emulate deprecated/obsolete ARM !! 2542 bool
1756 depends on SYSCTL <<
1757 help 2543 help
1758 Legacy software support may require !! 2544 This option must be set if a kernel might be executed on a MIPS16-
1759 that have been deprecated or obsole !! 2545 enabled CPU even if MIPS16 is not actually being used. In other
>> 2546 words, it makes the kernel MIPS16-tolerant.
1760 2547
1761 Enable this config to enable select !! 2548 config CPU_SUPPORTS_MSA
1762 features. !! 2549 bool
1763 <<
1764 If unsure, say Y <<
1765 2550
1766 if ARMV8_DEPRECATED !! 2551 config ARCH_FLATMEM_ENABLE
>> 2552 def_bool y
>> 2553 depends on !NUMA && !CPU_LOONGSON2
1767 2554
1768 config SWP_EMULATION !! 2555 config ARCH_DISCONTIGMEM_ENABLE
1769 bool "Emulate SWP/SWPB instructions" !! 2556 bool
>> 2557 default y if SGI_IP27
1770 help 2558 help
1771 ARMv8 obsoletes the use of A32 SWP/ !! 2559 Say Y to support efficient handling of discontiguous physical memory,
1772 they are always undefined. Say Y he !! 2560 for architectures which are either NUMA (Non-Uniform Memory Access)
1773 emulation of these instructions for !! 2561 or have huge holes in the physical address space for other reasons.
1774 This feature can be controlled at r !! 2562 See <file:Documentation/vm/numa.rst> for more.
1775 sysctl which is disabled by default <<
1776 2563
1777 In some older versions of glibc [<= !! 2564 config ARCH_SPARSEMEM_ENABLE
1778 trylock() operations with the assum !! 2565 bool
1779 be preempted. This invalid assumpti !! 2566 select SPARSEMEM_STATIC
1780 with SWP emulation enabled, leading <<
1781 application. <<
1782 2567
1783 NOTE: when accessing uncached share !! 2568 config NUMA
1784 on an external transaction monitori !! 2569 bool "NUMA Support"
1785 monitor to maintain update atomicit !! 2570 depends on SYS_SUPPORTS_NUMA
1786 implement a global monitor, this op !! 2571 help
1787 perform SWP operations to uncached !! 2572 Say Y to compile the kernel to support NUMA (Non-Uniform Memory
>> 2573 Access). This option improves performance on systems with more
>> 2574 than two nodes; on two node systems it is generally better to
>> 2575 leave it disabled; on single node systems disable this option
>> 2576 disabled.
1788 2577
1789 If unsure, say Y !! 2578 config SYS_SUPPORTS_NUMA
>> 2579 bool
1790 2580
1791 config CP15_BARRIER_EMULATION !! 2581 config RELOCATABLE
1792 bool "Emulate CP15 Barrier instructio !! 2582 bool "Relocatable kernel"
>> 2583 depends on SYS_SUPPORTS_RELOCATABLE && (CPU_MIPS32_R2 || CPU_MIPS64_R2 || CPU_MIPS32_R6 || CPU_MIPS64_R6 || CAVIUM_OCTEON_SOC)
1793 help 2584 help
1794 The CP15 barrier instructions - CP1 !! 2585 This builds a kernel image that retains relocation information
1795 CP15DMB - are deprecated in ARMv8 ( !! 2586 so it can be loaded someplace besides the default 1MB.
1796 strongly recommended to use the ISB !! 2587 The relocations make the kernel binary about 15% larger,
1797 instructions instead. !! 2588 but are discarded at runtime
>> 2589
>> 2590 config RELOCATION_TABLE_SIZE
>> 2591 hex "Relocation table size"
>> 2592 depends on RELOCATABLE
>> 2593 range 0x0 0x01000000
>> 2594 default "0x00100000"
>> 2595 ---help---
>> 2596 A table of relocation data will be appended to the kernel binary
>> 2597 and parsed at boot to fix up the relocated kernel.
1798 2598
1799 Say Y here to enable software emula !! 2599 This option allows the amount of space reserved for the table to be
1800 instructions for AArch32 userspace !! 2600 adjusted, although the default of 1Mb should be ok in most cases.
1801 enabled, CP15 barrier usage is trac <<
1802 identify software that needs updati <<
1803 controlled at runtime with the abi. <<
1804 2601
1805 If unsure, say Y !! 2602 The build will fail and a valid size suggested if this is too small.
1806 2603
1807 config SETEND_EMULATION !! 2604 If unsure, leave at the default value.
1808 bool "Emulate SETEND instruction" <<
1809 help <<
1810 The SETEND instruction alters the d <<
1811 AArch32 EL0, and is deprecated in A <<
1812 2605
1813 Say Y here to enable software emula !! 2606 config RANDOMIZE_BASE
1814 for AArch32 userspace code. This fe !! 2607 bool "Randomize the address of the kernel image"
1815 at runtime with the abi.setend sysc !! 2608 depends on RELOCATABLE
>> 2609 ---help---
>> 2610 Randomizes the physical and virtual address at which the
>> 2611 kernel image is loaded, as a security feature that
>> 2612 deters exploit attempts relying on knowledge of the location
>> 2613 of kernel internals.
1816 2614
1817 Note: All the cpus on the system mu !! 2615 Entropy is generated using any coprocessor 0 registers available.
1818 for this feature to be enabled. If <<
1819 endian - is hotplugged in after thi <<
1820 be unexpected results in the applic <<
1821 2616
1822 If unsure, say Y !! 2617 The kernel will be offset by up to RANDOMIZE_BASE_MAX_OFFSET.
1823 endif # ARMV8_DEPRECATED <<
1824 2618
1825 endif # COMPAT !! 2619 If unsure, say N.
1826 2620
1827 menu "ARMv8.1 architectural features" !! 2621 config RANDOMIZE_BASE_MAX_OFFSET
>> 2622 hex "Maximum kASLR offset" if EXPERT
>> 2623 depends on RANDOMIZE_BASE
>> 2624 range 0x0 0x40000000 if EVA || 64BIT
>> 2625 range 0x0 0x08000000
>> 2626 default "0x01000000"
>> 2627 ---help---
>> 2628 When kASLR is active, this provides the maximum offset that will
>> 2629 be applied to the kernel image. It should be set according to the
>> 2630 amount of physical RAM available in the target system minus
>> 2631 PHYSICAL_START and must be a power of 2.
1828 2632
1829 config ARM64_HW_AFDBM !! 2633 This is limited by the size of KSEG0, 256Mb on 32-bit or 1Gb with
1830 bool "Support for hardware updates of !! 2634 EVA or 64-bit. The default is 16Mb.
1831 default y <<
1832 help <<
1833 The ARMv8.1 architecture extensions <<
1834 hardware updates of the access and <<
1835 table entries. When enabled in TCR_ <<
1836 capable processors, accesses to pag <<
1837 set this bit instead of raising an <<
1838 Similarly, writes to read-only page <<
1839 clear the read-only bit (AP[2]) ins <<
1840 permission fault. <<
1841 2635
1842 Kernels built with this configurati !! 2636 config NODES_SHIFT
1843 to work on pre-ARMv8.1 hardware and !! 2637 int
1844 minimal. If unsure, say Y. !! 2638 default "6"
>> 2639 depends on NEED_MULTIPLE_NODES
1845 2640
1846 config ARM64_PAN !! 2641 config HW_PERF_EVENTS
1847 bool "Enable support for Privileged A !! 2642 bool "Enable hardware performance counter support for perf events"
>> 2643 depends on PERF_EVENTS && !OPROFILE && (CPU_MIPS32 || CPU_MIPS64 || CPU_R10000 || CPU_SB1 || CPU_CAVIUM_OCTEON || CPU_XLP || CPU_LOONGSON3)
1848 default y 2644 default y
1849 help 2645 help
1850 Privileged Access Never (PAN; part !! 2646 Enable hardware performance counter support for perf events. If
1851 prevents the kernel or hypervisor f !! 2647 disabled, perf events will use software events only.
1852 memory directly. <<
1853 2648
1854 Choosing this option will cause any !! 2649 config SMP
1855 copy_to_user et al) memory access t !! 2650 bool "Multi-Processing support"
>> 2651 depends on SYS_SUPPORTS_SMP
>> 2652 help
>> 2653 This enables support for systems with more than one CPU. If you have
>> 2654 a system with only one CPU, say N. If you have a system with more
>> 2655 than one CPU, say Y.
>> 2656
>> 2657 If you say N here, the kernel will run on uni- and multiprocessor
>> 2658 machines, but will use only one CPU of a multiprocessor machine. If
>> 2659 you say Y here, the kernel will run on many, but not all,
>> 2660 uniprocessor machines. On a uniprocessor machine, the kernel
>> 2661 will run faster if you say N here.
1856 2662
1857 The feature is detected at runtime, !! 2663 People using multiprocessor machines who say Y here should also say
1858 instruction if the cpu does not imp !! 2664 Y to "Enhanced Real Time Clock Support", below.
1859 2665
1860 config AS_HAS_LSE_ATOMICS !! 2666 See also the SMP-HOWTO available at
1861 def_bool $(as-instr,.arch_extension l !! 2667 <http://www.tldp.org/docs.html#howto>.
1862 2668
1863 config ARM64_LSE_ATOMICS !! 2669 If you don't know what to do here, say N.
1864 bool <<
1865 default ARM64_USE_LSE_ATOMICS <<
1866 depends on AS_HAS_LSE_ATOMICS <<
1867 2670
1868 config ARM64_USE_LSE_ATOMICS !! 2671 config HOTPLUG_CPU
1869 bool "Atomic instructions" !! 2672 bool "Support for hot-pluggable CPUs"
1870 default y !! 2673 depends on SMP && SYS_SUPPORTS_HOTPLUG_CPU
1871 help 2674 help
1872 As part of the Large System Extensi !! 2675 Say Y here to allow turning CPUs off and on. CPUs can be
1873 atomic instructions that are design !! 2676 controlled through /sys/devices/system/cpu.
1874 very large systems. !! 2677 (Note: power management support will enable this option
>> 2678 automatically on SMP systems. )
>> 2679 Say N if you want to disable CPU hotplug.
1875 2680
1876 Say Y here to make use of these ins !! 2681 config SMP_UP
1877 atomic routines. This incurs a smal !! 2682 bool
1878 not support these instructions and <<
1879 built with binutils >= 2.25 in orde <<
1880 to be used. <<
1881 2683
1882 endmenu # "ARMv8.1 architectural features" !! 2684 config SYS_SUPPORTS_MIPS_CMP
>> 2685 bool
1883 2686
1884 menu "ARMv8.2 architectural features" !! 2687 config SYS_SUPPORTS_MIPS_CPS
>> 2688 bool
1885 2689
1886 config AS_HAS_ARMV8_2 !! 2690 config SYS_SUPPORTS_SMP
1887 def_bool $(cc-option,-Wa$(comma)-marc !! 2691 bool
1888 2692
1889 config AS_HAS_SHA3 !! 2693 config NR_CPUS_DEFAULT_4
1890 def_bool $(as-instr,.arch armv8.2-a+s !! 2694 bool
1891 2695
1892 config ARM64_PMEM !! 2696 config NR_CPUS_DEFAULT_8
1893 bool "Enable support for persistent m !! 2697 bool
1894 select ARCH_HAS_PMEM_API <<
1895 select ARCH_HAS_UACCESS_FLUSHCACHE <<
1896 help <<
1897 Say Y to enable support for the per <<
1898 ARMv8.2 DCPoP feature. <<
1899 2698
1900 The feature is detected at runtime, !! 2699 config NR_CPUS_DEFAULT_16
1901 operations if DC CVAP is not suppor !! 2700 bool
1902 DC CVAP itself if the system does n <<
1903 2701
1904 config ARM64_RAS_EXTN !! 2702 config NR_CPUS_DEFAULT_32
1905 bool "Enable support for RAS CPU Exte !! 2703 bool
1906 default y <<
1907 help <<
1908 CPUs that support the Reliability, <<
1909 (RAS) Extensions, part of ARMv8.2 a <<
1910 errors, classify them and report th <<
1911 2704
1912 On CPUs with these extensions syste !! 2705 config NR_CPUS_DEFAULT_64
1913 barriers to determine if faults are !! 2706 bool
1914 classification from a new set of re <<
1915 2707
1916 Selecting this feature will allow t !! 2708 config NR_CPUS
1917 and access the new registers if the !! 2709 int "Maximum number of CPUs (2-256)"
1918 Platform RAS features may additiona !! 2710 range 2 256
>> 2711 depends on SMP
>> 2712 default "4" if NR_CPUS_DEFAULT_4
>> 2713 default "8" if NR_CPUS_DEFAULT_8
>> 2714 default "16" if NR_CPUS_DEFAULT_16
>> 2715 default "32" if NR_CPUS_DEFAULT_32
>> 2716 default "64" if NR_CPUS_DEFAULT_64
>> 2717 help
>> 2718 This allows you to specify the maximum number of CPUs which this
>> 2719 kernel will support. The maximum supported value is 32 for 32-bit
>> 2720 kernel and 64 for 64-bit kernels; the minimum value which makes
>> 2721 sense is 1 for Qemu (useful only for kernel debugging purposes)
>> 2722 and 2 for all others.
>> 2723
>> 2724 This is purely to save memory - each supported CPU adds
>> 2725 approximately eight kilobytes to the kernel image. For best
>> 2726 performance should round up your number of processors to the next
>> 2727 power of two.
1919 2728
1920 config ARM64_CNP !! 2729 config MIPS_PERF_SHARED_TC_COUNTERS
1921 bool "Enable support for Common Not P !! 2730 bool
1922 default y <<
1923 depends on ARM64_PAN || !ARM64_SW_TTB <<
1924 help <<
1925 Common Not Private (CNP) allows tra <<
1926 be shared between different PEs in <<
1927 domain, so the hardware can use thi <<
1928 caching of such entries in the TLB. <<
1929 2731
1930 Selecting this option allows the CN !! 2732 config MIPS_NR_CPU_NR_MAP_1024
1931 at runtime, and does not affect PEs !! 2733 bool
1932 this feature. <<
1933 2734
1934 endmenu # "ARMv8.2 architectural features" !! 2735 config MIPS_NR_CPU_NR_MAP
>> 2736 int
>> 2737 depends on SMP
>> 2738 default 1024 if MIPS_NR_CPU_NR_MAP_1024
>> 2739 default NR_CPUS if !MIPS_NR_CPU_NR_MAP_1024
1935 2740
1936 menu "ARMv8.3 architectural features" !! 2741 #
>> 2742 # Timer Interrupt Frequency Configuration
>> 2743 #
1937 2744
1938 config ARM64_PTR_AUTH !! 2745 choice
1939 bool "Enable support for pointer auth !! 2746 prompt "Timer frequency"
1940 default y !! 2747 default HZ_250
1941 help 2748 help
1942 Pointer authentication (part of the !! 2749 Allows the configuration of the timer frequency.
1943 instructions for signing and authen <<
1944 keys, which can be used to mitigate <<
1945 and other attacks. <<
1946 2750
1947 This option enables these instructi !! 2751 config HZ_24
1948 Choosing this option will cause the !! 2752 bool "24 HZ" if SYS_SUPPORTS_24HZ || SYS_SUPPORTS_ARBIT_HZ
1949 for each process at exec() time, wi <<
1950 context-switched along with the pro <<
1951 2753
1952 The feature is detected at runtime. !! 2754 config HZ_48
1953 hardware it will not be advertised !! 2755 bool "48 HZ" if SYS_SUPPORTS_48HZ || SYS_SUPPORTS_ARBIT_HZ
1954 be enabled. <<
1955 2756
1956 If the feature is present on the bo !! 2757 config HZ_100
1957 the late CPU will be parked. Also, !! 2758 bool "100 HZ" if SYS_SUPPORTS_100HZ || SYS_SUPPORTS_ARBIT_HZ
1958 address auth and the late CPU has t <<
1959 but with the feature disabled. On s <<
1960 not be selected. <<
1961 2759
1962 config ARM64_PTR_AUTH_KERNEL !! 2760 config HZ_128
1963 bool "Use pointer authentication for !! 2761 bool "128 HZ" if SYS_SUPPORTS_128HZ || SYS_SUPPORTS_ARBIT_HZ
1964 default y <<
1965 depends on ARM64_PTR_AUTH <<
1966 depends on (CC_HAS_SIGN_RETURN_ADDRES <<
1967 # Modern compilers insert a .note.gnu <<
1968 # which is only understood by binutil <<
1969 depends on LD_IS_LLD || LD_VERSION >= <<
1970 depends on !CC_IS_CLANG || AS_HAS_CFI <<
1971 depends on (!FUNCTION_GRAPH_TRACER || <<
1972 help <<
1973 If the compiler supports the -mbran <<
1974 -msign-return-address flag (e.g. GC <<
1975 will cause the kernel itself to be <<
1976 protection. In this case, and if th <<
1977 support pointer authentication, the <<
1978 disabled with minimal loss of prote <<
1979 2762
1980 This feature works with FUNCTION_GR !! 2763 config HZ_250
1981 DYNAMIC_FTRACE_WITH_ARGS is enabled !! 2764 bool "250 HZ" if SYS_SUPPORTS_250HZ || SYS_SUPPORTS_ARBIT_HZ
1982 2765
1983 config CC_HAS_BRANCH_PROT_PAC_RET !! 2766 config HZ_256
1984 # GCC 9 or later, clang 8 or later !! 2767 bool "256 HZ" if SYS_SUPPORTS_256HZ || SYS_SUPPORTS_ARBIT_HZ
1985 def_bool $(cc-option,-mbranch-protect <<
1986 2768
1987 config CC_HAS_SIGN_RETURN_ADDRESS !! 2769 config HZ_1000
1988 # GCC 7, 8 !! 2770 bool "1000 HZ" if SYS_SUPPORTS_1000HZ || SYS_SUPPORTS_ARBIT_HZ
1989 def_bool $(cc-option,-msign-return-ad <<
1990 2771
1991 config AS_HAS_ARMV8_3 !! 2772 config HZ_1024
1992 def_bool $(cc-option,-Wa$(comma)-marc !! 2773 bool "1024 HZ" if SYS_SUPPORTS_1024HZ || SYS_SUPPORTS_ARBIT_HZ
1993 2774
1994 config AS_HAS_CFI_NEGATE_RA_STATE !! 2775 endchoice
1995 def_bool $(as-instr,.cfi_startproc\n. <<
1996 2776
1997 config AS_HAS_LDAPR !! 2777 config SYS_SUPPORTS_24HZ
1998 def_bool $(as-instr,.arch_extension r !! 2778 bool
1999 2779
2000 endmenu # "ARMv8.3 architectural features" !! 2780 config SYS_SUPPORTS_48HZ
>> 2781 bool
2001 2782
2002 menu "ARMv8.4 architectural features" !! 2783 config SYS_SUPPORTS_100HZ
>> 2784 bool
2003 2785
2004 config ARM64_AMU_EXTN !! 2786 config SYS_SUPPORTS_128HZ
2005 bool "Enable support for the Activity !! 2787 bool
2006 default y <<
2007 help <<
2008 The activity monitors extension is <<
2009 by the ARMv8.4 CPU architecture. Th <<
2010 of the activity monitors architectu <<
2011 2788
2012 To enable the use of this extension !! 2789 config SYS_SUPPORTS_250HZ
>> 2790 bool
2013 2791
2014 Note that for architectural reasons !! 2792 config SYS_SUPPORTS_256HZ
2015 support when running on CPUs that p !! 2793 bool
2016 extension. The required support is <<
2017 * Version 1.5 and later of the AR <<
2018 2794
2019 For kernels that have this configur !! 2795 config SYS_SUPPORTS_1000HZ
2020 firmware, you may need to say N her !! 2796 bool
2021 Otherwise you may experience firmwa <<
2022 accessing the counter registers. Ev <<
2023 symptoms, the values returned by th <<
2024 correctly reflect reality. Most com <<
2025 indicating that the counter is not <<
2026 2797
2027 config AS_HAS_ARMV8_4 !! 2798 config SYS_SUPPORTS_1024HZ
2028 def_bool $(cc-option,-Wa$(comma)-marc !! 2799 bool
2029 2800
2030 config ARM64_TLB_RANGE !! 2801 config SYS_SUPPORTS_ARBIT_HZ
2031 bool "Enable support for tlbi range f !! 2802 bool
2032 default y !! 2803 default y if !SYS_SUPPORTS_24HZ && \
2033 depends on AS_HAS_ARMV8_4 !! 2804 !SYS_SUPPORTS_48HZ && \
2034 help !! 2805 !SYS_SUPPORTS_100HZ && \
2035 ARMv8.4-TLBI provides TLBI invalida !! 2806 !SYS_SUPPORTS_128HZ && \
2036 range of input addresses. !! 2807 !SYS_SUPPORTS_250HZ && \
>> 2808 !SYS_SUPPORTS_256HZ && \
>> 2809 !SYS_SUPPORTS_1000HZ && \
>> 2810 !SYS_SUPPORTS_1024HZ
2037 2811
2038 The feature introduces new assembly !! 2812 config HZ
2039 support when binutils >= 2.30. !! 2813 int
>> 2814 default 24 if HZ_24
>> 2815 default 48 if HZ_48
>> 2816 default 100 if HZ_100
>> 2817 default 128 if HZ_128
>> 2818 default 250 if HZ_250
>> 2819 default 256 if HZ_256
>> 2820 default 1000 if HZ_1000
>> 2821 default 1024 if HZ_1024
>> 2822
>> 2823 config SCHED_HRTICK
>> 2824 def_bool HIGH_RES_TIMERS
>> 2825
>> 2826 config KEXEC
>> 2827 bool "Kexec system call"
>> 2828 select KEXEC_CORE
>> 2829 help
>> 2830 kexec is a system call that implements the ability to shutdown your
>> 2831 current kernel, and to start another kernel. It is like a reboot
>> 2832 but it is independent of the system firmware. And like a reboot
>> 2833 you can start any kernel with it, not just Linux.
>> 2834
>> 2835 The name comes from the similarity to the exec system call.
>> 2836
>> 2837 It is an ongoing process to be certain the hardware in a machine
>> 2838 is properly shutdown, so do not be surprised if this code does not
>> 2839 initially work for you. As of this writing the exact hardware
>> 2840 interface is strongly in flux, so no good recommendation can be
>> 2841 made.
>> 2842
>> 2843 config CRASH_DUMP
>> 2844 bool "Kernel crash dumps"
>> 2845 help
>> 2846 Generate crash dump after being started by kexec.
>> 2847 This should be normally only set in special crash dump kernels
>> 2848 which are loaded in the main kernel with kexec-tools into
>> 2849 a specially reserved region and then later executed after
>> 2850 a crash by kdump/kexec. The crash dump kernel must be compiled
>> 2851 to a memory address not used by the main kernel or firmware using
>> 2852 PHYSICAL_START.
>> 2853
>> 2854 config PHYSICAL_START
>> 2855 hex "Physical address where the kernel is loaded"
>> 2856 default "0xffffffff84000000"
>> 2857 depends on CRASH_DUMP
>> 2858 help
>> 2859 This gives the CKSEG0 or KSEG0 address where the kernel is loaded.
>> 2860 If you plan to use kernel for capturing the crash dump change
>> 2861 this value to start of the reserved region (the "X" value as
>> 2862 specified in the "crashkernel=YM@XM" command line boot parameter
>> 2863 passed to the panic-ed kernel).
>> 2864
>> 2865 config SECCOMP
>> 2866 bool "Enable seccomp to safely compute untrusted bytecode"
>> 2867 depends on PROC_FS
>> 2868 default y
>> 2869 help
>> 2870 This kernel feature is useful for number crunching applications
>> 2871 that may need to compute untrusted bytecode during their
>> 2872 execution. By using pipes or other transports made available to
>> 2873 the process as file descriptors supporting the read/write
>> 2874 syscalls, it's possible to isolate those applications in
>> 2875 their own address space using seccomp. Once seccomp is
>> 2876 enabled via /proc/<pid>/seccomp, it cannot be disabled
>> 2877 and the task is only allowed to execute a few safe syscalls
>> 2878 defined by each seccomp mode.
>> 2879
>> 2880 If unsure, say Y. Only embedded should say N here.
>> 2881
>> 2882 config MIPS_O32_FP64_SUPPORT
>> 2883 bool "Support for O32 binaries using 64-bit FP"
>> 2884 depends on 32BIT || MIPS32_O32
>> 2885 help
>> 2886 When this is enabled, the kernel will support use of 64-bit floating
>> 2887 point registers with binaries using the O32 ABI along with the
>> 2888 EF_MIPS_FP64 ELF header flag (typically built with -mfp64). On
>> 2889 32-bit MIPS systems this support is at the cost of increasing the
>> 2890 size and complexity of the compiled FPU emulator. Thus if you are
>> 2891 running a MIPS32 system and know that none of your userland binaries
>> 2892 will require 64-bit floating point, you may wish to reduce the size
>> 2893 of your kernel & potentially improve FP emulation performance by
>> 2894 saying N here.
>> 2895
>> 2896 Although binutils currently supports use of this flag the details
>> 2897 concerning its effect upon the O32 ABI in userland are still being
>> 2898 worked on. In order to avoid userland becoming dependant upon current
>> 2899 behaviour before the details have been finalised, this option should
>> 2900 be considered experimental and only enabled by those working upon
>> 2901 said details.
2040 2902
2041 endmenu # "ARMv8.4 architectural features" !! 2903 If unsure, say N.
2042 2904
2043 menu "ARMv8.5 architectural features" !! 2905 config USE_OF
>> 2906 bool
>> 2907 select OF
>> 2908 select OF_EARLY_FLATTREE
>> 2909 select IRQ_DOMAIN
2044 2910
2045 config AS_HAS_ARMV8_5 !! 2911 config BUILTIN_DTB
2046 def_bool $(cc-option,-Wa$(comma)-marc !! 2912 bool
2047 2913
2048 config ARM64_BTI !! 2914 choice
2049 bool "Branch Target Identification su !! 2915 prompt "Kernel appended dtb support" if USE_OF
2050 default y !! 2916 default MIPS_NO_APPENDED_DTB
2051 help <<
2052 Branch Target Identification (part <<
2053 provides a mechanism to limit the s <<
2054 branch instructions such as BR or B <<
2055 2917
2056 To make use of BTI on CPUs that sup !! 2918 config MIPS_NO_APPENDED_DTB
>> 2919 bool "None"
>> 2920 help
>> 2921 Do not enable appended dtb support.
>> 2922
>> 2923 config MIPS_ELF_APPENDED_DTB
>> 2924 bool "vmlinux"
>> 2925 help
>> 2926 With this option, the boot code will look for a device tree binary
>> 2927 DTB) included in the vmlinux ELF section .appended_dtb. By default
>> 2928 it is empty and the DTB can be appended using binutils command
>> 2929 objcopy:
>> 2930
>> 2931 objcopy --update-section .appended_dtb=<filename>.dtb vmlinux
>> 2932
>> 2933 This is meant as a backward compatiblity convenience for those
>> 2934 systems with a bootloader that can't be upgraded to accommodate
>> 2935 the documented boot protocol using a device tree.
>> 2936
>> 2937 config MIPS_RAW_APPENDED_DTB
>> 2938 bool "vmlinux.bin or vmlinuz.bin"
>> 2939 help
>> 2940 With this option, the boot code will look for a device tree binary
>> 2941 DTB) appended to raw vmlinux.bin or vmlinuz.bin.
>> 2942 (e.g. cat vmlinux.bin <filename>.dtb > vmlinux_w_dtb).
>> 2943
>> 2944 This is meant as a backward compatibility convenience for those
>> 2945 systems with a bootloader that can't be upgraded to accommodate
>> 2946 the documented boot protocol using a device tree.
>> 2947
>> 2948 Beware that there is very little in terms of protection against
>> 2949 this option being confused by leftover garbage in memory that might
>> 2950 look like a DTB header after a reboot if no actual DTB is appended
>> 2951 to vmlinux.bin. Do not leave this option active in a production kernel
>> 2952 if you don't intend to always append a DTB.
>> 2953 endchoice
2057 2954
2058 BTI is intended to provide compleme !! 2955 choice
2059 flow integrity protection mechanism !! 2956 prompt "Kernel command line type" if !CMDLINE_OVERRIDE
2060 authentication mechanism provided a !! 2957 default MIPS_CMDLINE_FROM_DTB if USE_OF && !ATH79 && !MACH_INGENIC && \
2061 For this reason, it does not make s !! 2958 !MIPS_MALTA && \
2062 also enabling support for pointer a !! 2959 !CAVIUM_OCTEON_SOC
2063 enabling this option you should als !! 2960 default MIPS_CMDLINE_FROM_BOOTLOADER
>> 2961
>> 2962 config MIPS_CMDLINE_FROM_DTB
>> 2963 depends on USE_OF
>> 2964 bool "Dtb kernel arguments if available"
>> 2965
>> 2966 config MIPS_CMDLINE_DTB_EXTEND
>> 2967 depends on USE_OF
>> 2968 bool "Extend dtb kernel arguments with bootloader arguments"
>> 2969
>> 2970 config MIPS_CMDLINE_FROM_BOOTLOADER
>> 2971 bool "Bootloader kernel arguments if available"
>> 2972
>> 2973 config MIPS_CMDLINE_BUILTIN_EXTEND
>> 2974 depends on CMDLINE_BOOL
>> 2975 bool "Extend builtin kernel arguments with bootloader arguments"
>> 2976 endchoice
2064 2977
2065 Userspace binaries must also be spe !! 2978 endmenu
2066 this mechanism. If you say N here <<
2067 BTI, such binaries can still run, b <<
2068 enforcement of branch destinations. <<
2069 2979
2070 config ARM64_BTI_KERNEL !! 2980 config LOCKDEP_SUPPORT
2071 bool "Use Branch Target Identificatio !! 2981 bool
2072 default y 2982 default y
2073 depends on ARM64_BTI <<
2074 depends on ARM64_PTR_AUTH_KERNEL <<
2075 depends on CC_HAS_BRANCH_PROT_PAC_RET <<
2076 # https://gcc.gnu.org/bugzilla/show_b <<
2077 depends on !CC_IS_GCC || GCC_VERSION <<
2078 # https://gcc.gnu.org/bugzilla/show_b <<
2079 depends on !CC_IS_GCC <<
2080 depends on (!FUNCTION_GRAPH_TRACER || <<
2081 help <<
2082 Build the kernel with Branch Target <<
2083 and enable enforcement of this for <<
2084 is enabled and the system supports <<
2085 modular code must have BTI enabled. <<
2086 <<
2087 config CC_HAS_BRANCH_PROT_PAC_RET_BTI <<
2088 # GCC 9 or later, clang 8 or later <<
2089 def_bool $(cc-option,-mbranch-protect <<
2090 2983
2091 config ARM64_E0PD !! 2984 config STACKTRACE_SUPPORT
2092 bool "Enable support for E0PD" !! 2985 bool
2093 default y 2986 default y
2094 help <<
2095 E0PD (part of the ARMv8.5 extension <<
2096 that EL0 accesses made via TTBR1 al <<
2097 providing similar benefits to KASLR <<
2098 with lower overhead and without dis <<
2099 kernel memory such as SPE. <<
2100 2987
2101 This option enables E0PD for TTBR1 !! 2988 config HAVE_LATENCYTOP_SUPPORT
2102 !! 2989 bool
2103 config ARM64_AS_HAS_MTE <<
2104 # Initial support for MTE went in bin <<
2105 # ".arch armv8.5-a+memtag" below. How <<
2106 # as a late addition to the final arc <<
2107 # is only supported in the newer 2.32 <<
2108 # versions, hence the extra "stgm" in <<
2109 def_bool $(as-instr,.arch armv8.5-a+m <<
2110 <<
2111 config ARM64_MTE <<
2112 bool "Memory Tagging Extension suppor <<
2113 default y 2990 default y
2114 depends on ARM64_AS_HAS_MTE && ARM64_ <<
2115 depends on AS_HAS_ARMV8_5 <<
2116 depends on AS_HAS_LSE_ATOMICS <<
2117 # Required for tag checking in the ua <<
2118 depends on ARM64_PAN <<
2119 select ARCH_HAS_SUBPAGE_FAULTS <<
2120 select ARCH_USES_HIGH_VMA_FLAGS <<
2121 select ARCH_USES_PG_ARCH_2 <<
2122 select ARCH_USES_PG_ARCH_3 <<
2123 help <<
2124 Memory Tagging (part of the ARMv8.5 <<
2125 architectural support for run-time, <<
2126 various classes of memory error to <<
2127 to eliminate vulnerabilities arisin <<
2128 languages. <<
2129 <<
2130 This option enables the support for <<
2131 Extension at EL0 (i.e. for userspac <<
2132 <<
2133 Selecting this option allows the fe <<
2134 runtime. Any secondary CPU not impl <<
2135 not be allowed a late bring-up. <<
2136 2991
2137 Userspace binaries that want to use !! 2992 config PGTABLE_LEVELS
2138 explicitly opt in. The mechanism fo !! 2993 int
2139 described in: !! 2994 default 4 if PAGE_SIZE_4KB && MIPS_VA_BITS_48
>> 2995 default 3 if 64BIT && (!PAGE_SIZE_64KB || MIPS_VA_BITS_48)
>> 2996 default 2
2140 2997
2141 Documentation/arch/arm64/memory-tag !! 2998 config MIPS_AUTO_PFN_OFFSET
>> 2999 bool
2142 3000
2143 endmenu # "ARMv8.5 architectural features" !! 3001 menu "Bus options (PCI, PCMCIA, EISA, ISA, TC)"
2144 3002
2145 menu "ARMv8.7 architectural features" !! 3003 config HW_HAS_EISA
>> 3004 bool
>> 3005 config HW_HAS_PCI
>> 3006 bool
2146 3007
2147 config ARM64_EPAN !! 3008 config PCI
2148 bool "Enable support for Enhanced Pri !! 3009 bool "Support for PCI controller"
2149 default y !! 3010 depends on HW_HAS_PCI
2150 depends on ARM64_PAN !! 3011 select PCI_DOMAINS
2151 help !! 3012 help
2152 Enhanced Privileged Access Never (E !! 3013 Find out whether you have a PCI motherboard. PCI is the name of a
2153 Access Never to be used with Execut !! 3014 bus system, i.e. the way the CPU talks to the other stuff inside
>> 3015 your box. Other bus systems are ISA, EISA, or VESA. If you have PCI,
>> 3016 say Y, otherwise N.
>> 3017
>> 3018 config HT_PCI
>> 3019 bool "Support for HT-linked PCI"
>> 3020 default y
>> 3021 depends on CPU_LOONGSON3
>> 3022 select PCI
>> 3023 select PCI_DOMAINS
>> 3024 help
>> 3025 Loongson family machines use Hyper-Transport bus for inter-core
>> 3026 connection and device connection. The PCI bus is a subordinate
>> 3027 linked at HT. Choose Y for Loongson-3 based machines.
2154 3028
2155 The feature is detected at runtime, !! 3029 config PCI_DOMAINS
2156 if the cpu does not implement the f !! 3030 bool
2157 endmenu # "ARMv8.7 architectural features" <<
2158 3031
2159 menu "ARMv8.9 architectural features" !! 3032 config PCI_DOMAINS_GENERIC
>> 3033 bool
2160 3034
2161 config ARM64_POE !! 3035 config PCI_DRIVERS_GENERIC
2162 prompt "Permission Overlay Extension" !! 3036 select PCI_DOMAINS_GENERIC if PCI_DOMAINS
2163 def_bool y !! 3037 bool
2164 select ARCH_USES_HIGH_VMA_FLAGS <<
2165 select ARCH_HAS_PKEYS <<
2166 help <<
2167 The Permission Overlay Extension is <<
2168 Protection Keys. Memory Protection <<
2169 enforcing page-based protections, b <<
2170 of the page tables when an applicat <<
2171 3038
2172 For details, see Documentation/core !! 3039 config PCI_DRIVERS_LEGACY
>> 3040 def_bool !PCI_DRIVERS_GENERIC
>> 3041 select NO_GENERIC_PCI_IOPORT_MAP
2173 3042
2174 If unsure, say y. !! 3043 source "drivers/pci/Kconfig"
2175 3044
2176 config ARCH_PKEY_BITS !! 3045 #
2177 int !! 3046 # ISA support is now enabled via select. Too many systems still have the one
2178 default 3 !! 3047 # or other ISA chip on the board that users don't know about so don't expect
>> 3048 # users to choose the right thing ...
>> 3049 #
>> 3050 config ISA
>> 3051 bool
2179 3052
2180 endmenu # "ARMv8.9 architectural features" !! 3053 config EISA
>> 3054 bool "EISA support"
>> 3055 depends on HW_HAS_EISA
>> 3056 select ISA
>> 3057 select GENERIC_ISA_DMA
>> 3058 ---help---
>> 3059 The Extended Industry Standard Architecture (EISA) bus was
>> 3060 developed as an open alternative to the IBM MicroChannel bus.
>> 3061
>> 3062 The EISA bus provided some of the features of the IBM MicroChannel
>> 3063 bus while maintaining backward compatibility with cards made for
>> 3064 the older ISA bus. The EISA bus saw limited use between 1988 and
>> 3065 1995 when it was made obsolete by the PCI bus.
>> 3066
>> 3067 Say Y here if you are building a kernel for an EISA-based machine.
>> 3068
>> 3069 Otherwise, say N.
>> 3070
>> 3071 source "drivers/eisa/Kconfig"
>> 3072
>> 3073 config TC
>> 3074 bool "TURBOchannel support"
>> 3075 depends on MACH_DECSTATION
>> 3076 help
>> 3077 TURBOchannel is a DEC (now Compaq (now HP)) bus for Alpha and MIPS
>> 3078 processors. TURBOchannel programming specifications are available
>> 3079 at:
>> 3080 <ftp://ftp.hp.com/pub/alphaserver/archive/triadd/>
>> 3081 and:
>> 3082 <http://www.computer-refuge.org/classiccmp/ftp.digital.com/pub/DEC/TriAdd/>
>> 3083 Linux driver support status is documented at:
>> 3084 <http://www.linux-mips.org/wiki/DECstation>
2181 3085
2182 config ARM64_SVE !! 3086 config MMU
2183 bool "ARM Scalable Vector Extension s !! 3087 bool
2184 default y 3088 default y
2185 help <<
2186 The Scalable Vector Extension (SVE) <<
2187 execution state which complements a <<
2188 of the base architecture to support <<
2189 additional vectorisation opportunit <<
2190 3089
2191 To enable use of this extension on !! 3090 config ARCH_MMAP_RND_BITS_MIN
2192 !! 3091 default 12 if 64BIT
2193 On CPUs that support the SVE2 exten !! 3092 default 8
2194 those too. <<
2195 <<
2196 Note that for architectural reasons <<
2197 support when running on SVE capable <<
2198 is present in: <<
2199 <<
2200 * version 1.5 and later of the AR <<
2201 * the AArch64 boot wrapper since <<
2202 ("bootwrapper: SVE: Enable SVE <<
2203 <<
2204 For other firmware implementations, <<
2205 or vendor. <<
2206 <<
2207 If you need the kernel to boot on S <<
2208 firmware, you may need to say N her <<
2209 fixed. Otherwise, you may experien <<
2210 booting the kernel. If unsure and <<
2211 symptoms, you should assume that it <<
2212 <<
2213 config ARM64_SME <<
2214 bool "ARM Scalable Matrix Extension s <<
2215 default y <<
2216 depends on ARM64_SVE <<
2217 depends on BROKEN <<
2218 help <<
2219 The Scalable Matrix Extension (SME) <<
2220 execution state which utilises a su <<
2221 instruction set, together with the <<
2222 register state capable of holding t <<
2223 enable various matrix operations. <<
2224 3093
2225 config ARM64_PSEUDO_NMI !! 3094 config ARCH_MMAP_RND_BITS_MAX
2226 bool "Support for NMI-like interrupts !! 3095 default 18 if 64BIT
2227 select ARM_GIC_V3 !! 3096 default 15
2228 help <<
2229 Adds support for mimicking Non-Mask <<
2230 GIC interrupt priority. This suppor <<
2231 ARM GIC. <<
2232 3097
2233 This high priority configuration fo !! 3098 config ARCH_MMAP_RND_COMPAT_BITS_MIN
2234 explicitly enabled by setting the k !! 3099 default 8
2235 "irqchip.gicv3_pseudo_nmi" to 1. <<
2236 3100
2237 If unsure, say N !! 3101 config ARCH_MMAP_RND_COMPAT_BITS_MAX
>> 3102 default 15
2238 3103
2239 if ARM64_PSEUDO_NMI !! 3104 config I8253
2240 config ARM64_DEBUG_PRIORITY_MASKING !! 3105 bool
2241 bool "Debug interrupt priority maskin !! 3106 select CLKSRC_I8253
2242 help !! 3107 select CLKEVT_I8253
2243 This adds runtime checks to functio !! 3108 select MIPS_EXTERNAL_TIMER
2244 interrupts when using priority mask <<
2245 the validity of ICC_PMR_EL1 when ca <<
2246 3109
2247 If unsure, say N !! 3110 config ZONE_DMA
2248 endif # ARM64_PSEUDO_NMI !! 3111 bool
2249 3112
2250 config RELOCATABLE !! 3113 config ZONE_DMA32
2251 bool "Build a relocatable kernel imag !! 3114 bool
2252 select ARCH_HAS_RELR <<
2253 default y <<
2254 help <<
2255 This builds the kernel as a Positio <<
2256 which retains all relocation metada <<
2257 kernel binary at runtime to a diffe <<
2258 address it was linked at. <<
2259 Since AArch64 uses the RELA relocat <<
2260 relocation pass at runtime even if <<
2261 same address it was linked at. <<
2262 3115
2263 config RANDOMIZE_BASE !! 3116 source "drivers/pcmcia/Kconfig"
2264 bool "Randomize the address of the ke <<
2265 select RELOCATABLE <<
2266 help <<
2267 Randomizes the virtual address at w <<
2268 loaded, as a security feature that <<
2269 relying on knowledge of the locatio <<
2270 <<
2271 It is the bootloader's job to provi <<
2272 random u64 value in /chosen/kaslr-s <<
2273 <<
2274 When booting via the UEFI stub, it <<
2275 EFI_RNG_PROTOCOL implementation (if <<
2276 to the kernel proper. In addition, <<
2277 location of the kernel Image as wel <<
2278 3117
2279 If unsure, say N. !! 3118 config HAS_RAPIDIO
>> 3119 bool
>> 3120 default n
2280 3121
2281 config RANDOMIZE_MODULE_REGION_FULL !! 3122 config RAPIDIO
2282 bool "Randomize the module region ove !! 3123 tristate "RapidIO support"
2283 depends on RANDOMIZE_BASE !! 3124 depends on HAS_RAPIDIO || PCI
2284 default y <<
2285 help 3125 help
2286 Randomizes the location of the modu !! 3126 If you say Y here, the kernel will include drivers and
2287 covering the core kernel. This way, !! 3127 infrastructure code to support RapidIO interconnect devices.
2288 to leak information about the locat <<
2289 but it does imply that function cal <<
2290 kernel will need to be resolved via <<
2291 <<
2292 When this option is not set, the mo <<
2293 a limited range that contains the [ <<
2294 core kernel, so branch relocations <<
2295 the region is exhausted. In this pa <<
2296 exhaustion, modules might be able t <<
2297 3128
2298 config CC_HAVE_STACKPROTECTOR_SYSREG !! 3129 source "drivers/rapidio/Kconfig"
2299 def_bool $(cc-option,-mstack-protecto <<
2300 3130
2301 config STACKPROTECTOR_PER_TASK !! 3131 endmenu
2302 def_bool y <<
2303 depends on STACKPROTECTOR && CC_HAVE_ <<
2304 <<
2305 config UNWIND_PATCH_PAC_INTO_SCS <<
2306 bool "Enable shadow call stack dynami <<
2307 # needs Clang with https://github.com <<
2308 depends on CC_IS_CLANG && CLANG_VERSI <<
2309 depends on ARM64_PTR_AUTH_KERNEL && C <<
2310 depends on SHADOW_CALL_STACK <<
2311 select UNWIND_TABLES <<
2312 select DYNAMIC_SCS <<
2313 <<
2314 config ARM64_CONTPTE <<
2315 bool "Contiguous PTE mappings for use <<
2316 depends on TRANSPARENT_HUGEPAGE <<
2317 default y <<
2318 help <<
2319 When enabled, user mappings are con <<
2320 bit, for any mappings that meet the <<
2321 This reduces TLB pressure and impro <<
2322 <<
2323 endmenu # "Kernel Features" <<
2324 <<
2325 menu "Boot options" <<
2326 <<
2327 config ARM64_ACPI_PARKING_PROTOCOL <<
2328 bool "Enable support for the ARM64 AC <<
2329 depends on ACPI <<
2330 help <<
2331 Enable support for the ARM64 ACPI p <<
2332 the kernel will not allow booting t <<
2333 protocol even if the corresponding <<
2334 MADT table. <<
2335 <<
2336 config CMDLINE <<
2337 string "Default kernel command string <<
2338 default "" <<
2339 help <<
2340 Provide a set of default command-li <<
2341 entering them here. As a minimum, y <<
2342 root device (e.g. root=/dev/nfs). <<
2343 3132
2344 choice !! 3133 config TRAD_SIGNALS
2345 prompt "Kernel command line type" !! 3134 bool
2346 depends on CMDLINE != "" <<
2347 default CMDLINE_FROM_BOOTLOADER <<
2348 help <<
2349 Choose how the kernel will handle t <<
2350 command line string. <<
2351 <<
2352 config CMDLINE_FROM_BOOTLOADER <<
2353 bool "Use bootloader kernel arguments <<
2354 help <<
2355 Uses the command-line options passe <<
2356 the boot loader doesn't provide any <<
2357 string provided in CMDLINE will be <<
2358 <<
2359 config CMDLINE_FORCE <<
2360 bool "Always use the default kernel c <<
2361 help <<
2362 Always use the default kernel comma <<
2363 loader passes other arguments to th <<
2364 This is useful if you cannot or don <<
2365 command-line options your boot load <<
2366 3135
2367 endchoice !! 3136 config MIPS32_COMPAT
>> 3137 bool
2368 3138
2369 config EFI_STUB !! 3139 config COMPAT
2370 bool 3140 bool
2371 3141
2372 config EFI !! 3142 config SYSVIPC_COMPAT
2373 bool "UEFI runtime support" !! 3143 bool
2374 depends on OF && !CPU_BIG_ENDIAN <<
2375 depends on KERNEL_MODE_NEON <<
2376 select ARCH_SUPPORTS_ACPI <<
2377 select LIBFDT <<
2378 select UCS2_STRING <<
2379 select EFI_PARAMS_FROM_FDT <<
2380 select EFI_RUNTIME_WRAPPERS <<
2381 select EFI_STUB <<
2382 select EFI_GENERIC_STUB <<
2383 imply IMA_SECURE_AND_OR_TRUSTED_BOOT <<
2384 default y <<
2385 help <<
2386 This option provides support for ru <<
2387 by UEFI firmware (such as non-volat <<
2388 clock, and platform reset). A UEFI <<
2389 allow the kernel to be booted as an <<
2390 is only useful on systems that have <<
2391 3144
2392 config COMPRESSED_INSTALL !! 3145 config MIPS32_O32
2393 bool "Install compressed image by def !! 3146 bool "Kernel support for o32 binaries"
2394 help !! 3147 depends on 64BIT
2395 This makes the regular "make instal !! 3148 select ARCH_WANT_OLD_COMPAT_IPC
2396 image we built, not the legacy unco !! 3149 select COMPAT
>> 3150 select MIPS32_COMPAT
>> 3151 select SYSVIPC_COMPAT if SYSVIPC
>> 3152 help
>> 3153 Select this option if you want to run o32 binaries. These are pure
>> 3154 32-bit binaries as used by the 32-bit Linux/MIPS port. Most of
>> 3155 existing binaries are in this format.
2397 3156
2398 You can check that a compressed ima !! 3157 If unsure, say Y.
2399 "make zinstall" first, and verifyin <<
2400 in your environment before making " <<
2401 you. <<
2402 3158
2403 config DMI !! 3159 config MIPS32_N32
2404 bool "Enable support for SMBIOS (DMI) !! 3160 bool "Kernel support for n32 binaries"
2405 depends on EFI !! 3161 depends on 64BIT
2406 default y !! 3162 select ARCH_WANT_COMPAT_IPC_PARSE_VERSION
2407 help !! 3163 select COMPAT
2408 This enables SMBIOS/DMI feature for !! 3164 select MIPS32_COMPAT
>> 3165 select SYSVIPC_COMPAT if SYSVIPC
>> 3166 help
>> 3167 Select this option if you want to run n32 binaries. These are
>> 3168 64-bit binaries using 32-bit quantities for addressing and certain
>> 3169 data that would normally be 64-bit. They are used in special
>> 3170 cases.
2409 3171
2410 This option is only useful on syste !! 3172 If unsure, say N.
2411 However, even with this option, the <<
2412 continue to boot on existing non-UE <<
2413 3173
2414 endmenu # "Boot options" !! 3174 config BINFMT_ELF32
>> 3175 bool
>> 3176 default y if MIPS32_O32 || MIPS32_N32
>> 3177 select ELFCORE
2415 3178
2416 menu "Power management options" 3179 menu "Power management options"
2417 3180
2418 source "kernel/power/Kconfig" <<
2419 <<
2420 config ARCH_HIBERNATION_POSSIBLE 3181 config ARCH_HIBERNATION_POSSIBLE
2421 def_bool y 3182 def_bool y
2422 depends on CPU_PM !! 3183 depends on SYS_SUPPORTS_HOTPLUG_CPU || !SMP
2423 <<
2424 config ARCH_HIBERNATION_HEADER <<
2425 def_bool y <<
2426 depends on HIBERNATION <<
2427 3184
2428 config ARCH_SUSPEND_POSSIBLE 3185 config ARCH_SUSPEND_POSSIBLE
2429 def_bool y 3186 def_bool y
>> 3187 depends on SYS_SUPPORTS_HOTPLUG_CPU || !SMP
2430 3188
2431 endmenu # "Power management options" !! 3189 source "kernel/power/Kconfig"
2432 3190
2433 menu "CPU Power Management" !! 3191 endmenu
2434 3192
2435 source "drivers/cpuidle/Kconfig" !! 3193 config MIPS_EXTERNAL_TIMER
>> 3194 bool
2436 3195
>> 3196 menu "CPU Power Management"
>> 3197
>> 3198 if CPU_SUPPORTS_CPUFREQ && MIPS_EXTERNAL_TIMER
2437 source "drivers/cpufreq/Kconfig" 3199 source "drivers/cpufreq/Kconfig"
>> 3200 endif
2438 3201
2439 endmenu # "CPU Power Management" !! 3202 source "drivers/cpuidle/Kconfig"
2440 3203
2441 source "drivers/acpi/Kconfig" !! 3204 endmenu
2442 3205
2443 source "arch/arm64/kvm/Kconfig" !! 3206 source "drivers/firmware/Kconfig"
2444 3207
>> 3208 source "arch/mips/kvm/Kconfig"
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