1 # SPDX-License-Identifier: GPL-2.0-only !! 1 # SPDX-License-Identifier: GPL-2.0
2 config ARM64 !! 2 config MIPS
3 def_bool y !! 3 bool
4 select ACPI_APMT if ACPI !! 4 default y
5 select ACPI_CCA_REQUIRED if ACPI <<
6 select ACPI_GENERIC_GSI if ACPI <<
7 select ACPI_GTDT if ACPI <<
8 select ACPI_HOTPLUG_CPU if ACPI_PROCES <<
9 select ACPI_IORT if ACPI <<
10 select ACPI_REDUCED_HARDWARE_ONLY if A <<
11 select ACPI_MCFG if (ACPI && PCI) <<
12 select ACPI_SPCR_TABLE if ACPI <<
13 select ACPI_PPTT if ACPI <<
14 select ARCH_HAS_DEBUG_WX <<
15 select ARCH_BINFMT_ELF_EXTRA_PHDRS <<
16 select ARCH_BINFMT_ELF_STATE 5 select ARCH_BINFMT_ELF_STATE
17 select ARCH_CORRECT_STACKTRACE_ON_KRET !! 6 select ARCH_CLOCKSOURCE_DATA
18 select ARCH_ENABLE_HUGEPAGE_MIGRATION !! 7 select ARCH_DISCARD_MEMBLOCK
19 select ARCH_ENABLE_MEMORY_HOTPLUG !! 8 select ARCH_HAS_ELF_RANDOMIZE
20 select ARCH_ENABLE_MEMORY_HOTREMOVE <<
21 select ARCH_ENABLE_SPLIT_PMD_PTLOCK if <<
22 select ARCH_ENABLE_THP_MIGRATION if TR <<
23 select ARCH_HAS_CACHE_LINE_SIZE <<
24 select ARCH_HAS_CURRENT_STACK_POINTER <<
25 select ARCH_HAS_DEBUG_VIRTUAL <<
26 select ARCH_HAS_DEBUG_VM_PGTABLE <<
27 select ARCH_HAS_DMA_OPS if XEN <<
28 select ARCH_HAS_DMA_PREP_COHERENT <<
29 select ARCH_HAS_ACPI_TABLE_UPGRADE if <<
30 select ARCH_HAS_FAST_MULTIPLIER <<
31 select ARCH_HAS_FORTIFY_SOURCE <<
32 select ARCH_HAS_GCOV_PROFILE_ALL <<
33 select ARCH_HAS_GIGANTIC_PAGE <<
34 select ARCH_HAS_KCOV <<
35 select ARCH_HAS_KERNEL_FPU_SUPPORT if <<
36 select ARCH_HAS_KEEPINITRD <<
37 select ARCH_HAS_MEMBARRIER_SYNC_CORE <<
38 select ARCH_HAS_MEM_ENCRYPT <<
39 select ARCH_HAS_NMI_SAFE_THIS_CPU_OPS <<
40 select ARCH_HAS_NON_OVERLAPPING_ADDRES <<
41 select ARCH_HAS_PTE_DEVMAP <<
42 select ARCH_HAS_PTE_SPECIAL <<
43 select ARCH_HAS_HW_PTE_YOUNG <<
44 select ARCH_HAS_SETUP_DMA_OPS <<
45 select ARCH_HAS_SET_DIRECT_MAP <<
46 select ARCH_HAS_SET_MEMORY <<
47 select ARCH_STACKWALK <<
48 select ARCH_HAS_STRICT_KERNEL_RWX <<
49 select ARCH_HAS_STRICT_MODULE_RWX <<
50 select ARCH_HAS_SYNC_DMA_FOR_DEVICE <<
51 select ARCH_HAS_SYNC_DMA_FOR_CPU <<
52 select ARCH_HAS_SYSCALL_WRAPPER <<
53 select ARCH_HAS_TICK_BROADCAST if GENE 9 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
54 select ARCH_HAS_ZONE_DMA_SET if EXPERT !! 10 select ARCH_SUPPORTS_UPROBES
55 select ARCH_HAVE_ELF_PROT !! 11 select ARCH_USE_BUILTIN_BSWAP
56 select ARCH_HAVE_NMI_SAFE_CMPXCHG !! 12 select ARCH_USE_CMPXCHG_LOCKREF if 64BIT
57 select ARCH_HAVE_TRACE_MMIO_ACCESS <<
58 select ARCH_INLINE_READ_LOCK if !PREEM <<
59 select ARCH_INLINE_READ_LOCK_BH if !PR <<
60 select ARCH_INLINE_READ_LOCK_IRQ if !P <<
61 select ARCH_INLINE_READ_LOCK_IRQSAVE i <<
62 select ARCH_INLINE_READ_UNLOCK if !PRE <<
63 select ARCH_INLINE_READ_UNLOCK_BH if ! <<
64 select ARCH_INLINE_READ_UNLOCK_IRQ if <<
65 select ARCH_INLINE_READ_UNLOCK_IRQREST <<
66 select ARCH_INLINE_WRITE_LOCK if !PREE <<
67 select ARCH_INLINE_WRITE_LOCK_BH if !P <<
68 select ARCH_INLINE_WRITE_LOCK_IRQ if ! <<
69 select ARCH_INLINE_WRITE_LOCK_IRQSAVE <<
70 select ARCH_INLINE_WRITE_UNLOCK if !PR <<
71 select ARCH_INLINE_WRITE_UNLOCK_BH if <<
72 select ARCH_INLINE_WRITE_UNLOCK_IRQ if <<
73 select ARCH_INLINE_WRITE_UNLOCK_IRQRES <<
74 select ARCH_INLINE_SPIN_TRYLOCK if !PR <<
75 select ARCH_INLINE_SPIN_TRYLOCK_BH if <<
76 select ARCH_INLINE_SPIN_LOCK if !PREEM <<
77 select ARCH_INLINE_SPIN_LOCK_BH if !PR <<
78 select ARCH_INLINE_SPIN_LOCK_IRQ if !P <<
79 select ARCH_INLINE_SPIN_LOCK_IRQSAVE i <<
80 select ARCH_INLINE_SPIN_UNLOCK if !PRE <<
81 select ARCH_INLINE_SPIN_UNLOCK_BH if ! <<
82 select ARCH_INLINE_SPIN_UNLOCK_IRQ if <<
83 select ARCH_INLINE_SPIN_UNLOCK_IRQREST <<
84 select ARCH_KEEP_MEMBLOCK <<
85 select ARCH_MHP_MEMMAP_ON_MEMORY_ENABL <<
86 select ARCH_USE_CMPXCHG_LOCKREF <<
87 select ARCH_USE_GNU_PROPERTY <<
88 select ARCH_USE_MEMTEST <<
89 select ARCH_USE_QUEUED_RWLOCKS 13 select ARCH_USE_QUEUED_RWLOCKS
90 select ARCH_USE_QUEUED_SPINLOCKS 14 select ARCH_USE_QUEUED_SPINLOCKS
91 select ARCH_USE_SYM_ANNOTATIONS !! 15 select ARCH_WANT_IPC_PARSE_VERSION
92 select ARCH_SUPPORTS_DEBUG_PAGEALLOC !! 16 select BUILDTIME_EXTABLE_SORT
93 select ARCH_SUPPORTS_HUGETLBFS <<
94 select ARCH_SUPPORTS_MEMORY_FAILURE <<
95 select ARCH_SUPPORTS_SHADOW_CALL_STACK <<
96 select ARCH_SUPPORTS_LTO_CLANG if CPU_ <<
97 select ARCH_SUPPORTS_LTO_CLANG_THIN <<
98 select ARCH_SUPPORTS_CFI_CLANG <<
99 select ARCH_SUPPORTS_ATOMIC_RMW <<
100 select ARCH_SUPPORTS_INT128 if CC_HAS_ <<
101 select ARCH_SUPPORTS_NUMA_BALANCING <<
102 select ARCH_SUPPORTS_PAGE_TABLE_CHECK <<
103 select ARCH_SUPPORTS_PER_VMA_LOCK <<
104 select ARCH_SUPPORTS_HUGE_PFNMAP if TR <<
105 select ARCH_SUPPORTS_RT <<
106 select ARCH_WANT_BATCHED_UNMAP_TLB_FLU <<
107 select ARCH_WANT_COMPAT_IPC_PARSE_VERS <<
108 select ARCH_WANT_DEFAULT_BPF_JIT <<
109 select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_ <<
110 select ARCH_WANT_FRAME_POINTERS <<
111 select ARCH_WANT_HUGE_PMD_SHARE if ARM <<
112 select ARCH_WANT_LD_ORPHAN_WARN <<
113 select ARCH_WANTS_EXECMEM_LATE if EXEC <<
114 select ARCH_WANTS_NO_INSTR <<
115 select ARCH_WANTS_THP_SWAP if ARM64_4K <<
116 select ARCH_HAS_UBSAN <<
117 select ARM_AMBA <<
118 select ARM_ARCH_TIMER <<
119 select ARM_GIC <<
120 select AUDIT_ARCH_COMPAT_GENERIC <<
121 select ARM_GIC_V2M if PCI <<
122 select ARM_GIC_V3 <<
123 select ARM_GIC_V3_ITS if PCI <<
124 select ARM_PSCI_FW <<
125 select BUILDTIME_TABLE_SORT <<
126 select CLONE_BACKWARDS 17 select CLONE_BACKWARDS
127 select COMMON_CLK !! 18 select CPU_PM if CPU_IDLE
128 select CPU_PM if (SUSPEND || CPU_IDLE) !! 19 select DMA_DIRECT_OPS
129 select CPUMASK_OFFSTACK if NR_CPUS > 2 !! 20 select GENERIC_ATOMIC64 if !64BIT
130 select CRC32 !! 21 select GENERIC_CLOCKEVENTS
131 select DCACHE_WORD_ACCESS !! 22 select GENERIC_CMOS_UPDATE
132 select DYNAMIC_FTRACE if FUNCTION_TRAC <<
133 select DMA_BOUNCE_UNALIGNED_KMALLOC <<
134 select DMA_DIRECT_REMAP <<
135 select EDAC_SUPPORT <<
136 select FRAME_POINTER <<
137 select FUNCTION_ALIGNMENT_4B <<
138 select FUNCTION_ALIGNMENT_8B if DYNAMI <<
139 select GENERIC_ALLOCATOR <<
140 select GENERIC_ARCH_TOPOLOGY <<
141 select GENERIC_CLOCKEVENTS_BROADCAST <<
142 select GENERIC_CPU_AUTOPROBE 23 select GENERIC_CPU_AUTOPROBE
143 select GENERIC_CPU_DEVICES !! 24 select GENERIC_IOMAP
144 select GENERIC_CPU_VULNERABILITIES <<
145 select GENERIC_EARLY_IOREMAP <<
146 select GENERIC_IDLE_POLL_SETUP <<
147 select GENERIC_IOREMAP <<
148 select GENERIC_IRQ_IPI <<
149 select GENERIC_IRQ_PROBE 25 select GENERIC_IRQ_PROBE
150 select GENERIC_IRQ_SHOW 26 select GENERIC_IRQ_SHOW
151 select GENERIC_IRQ_SHOW_LEVEL !! 27 select GENERIC_LIB_ASHLDI3
152 select GENERIC_LIB_DEVMEM_IS_ALLOWED !! 28 select GENERIC_LIB_ASHRDI3
153 select GENERIC_PCI_IOMAP !! 29 select GENERIC_LIB_CMPDI2
154 select GENERIC_PTDUMP !! 30 select GENERIC_LIB_LSHRDI3
155 select GENERIC_SCHED_CLOCK !! 31 select GENERIC_LIB_UCMPDI2
>> 32 select GENERIC_SCHED_CLOCK if !CAVIUM_OCTEON_SOC
156 select GENERIC_SMP_IDLE_THREAD 33 select GENERIC_SMP_IDLE_THREAD
157 select GENERIC_TIME_VSYSCALL 34 select GENERIC_TIME_VSYSCALL
158 select GENERIC_GETTIMEOFDAY !! 35 select HANDLE_DOMAIN_IRQ
159 select GENERIC_VDSO_TIME_NS <<
160 select HARDIRQS_SW_RESEND <<
161 select HAS_IOPORT <<
162 select HAVE_MOVE_PMD <<
163 select HAVE_MOVE_PUD <<
164 select HAVE_PCI <<
165 select HAVE_ACPI_APEI if (ACPI && EFI) <<
166 select HAVE_ALIGNED_STRUCT_PAGE <<
167 select HAVE_ARCH_AUDITSYSCALL <<
168 select HAVE_ARCH_BITREVERSE <<
169 select HAVE_ARCH_COMPILER_H 36 select HAVE_ARCH_COMPILER_H
170 select HAVE_ARCH_HUGE_VMALLOC <<
171 select HAVE_ARCH_HUGE_VMAP <<
172 select HAVE_ARCH_JUMP_LABEL 37 select HAVE_ARCH_JUMP_LABEL
173 select HAVE_ARCH_JUMP_LABEL_RELATIVE <<
174 select HAVE_ARCH_KASAN <<
175 select HAVE_ARCH_KASAN_VMALLOC <<
176 select HAVE_ARCH_KASAN_SW_TAGS <<
177 select HAVE_ARCH_KASAN_HW_TAGS if ARM6 <<
178 # Some instrumentation may be unsound, <<
179 select HAVE_ARCH_KCSAN if EXPERT <<
180 select HAVE_ARCH_KFENCE <<
181 select HAVE_ARCH_KGDB 38 select HAVE_ARCH_KGDB
182 select HAVE_ARCH_MMAP_RND_BITS !! 39 select HAVE_ARCH_MMAP_RND_BITS if MMU
183 select HAVE_ARCH_MMAP_RND_COMPAT_BITS !! 40 select HAVE_ARCH_MMAP_RND_COMPAT_BITS if MMU && COMPAT
184 select HAVE_ARCH_PREL32_RELOCATIONS <<
185 select HAVE_ARCH_RANDOMIZE_KSTACK_OFFS <<
186 select HAVE_ARCH_SECCOMP_FILTER 41 select HAVE_ARCH_SECCOMP_FILTER
187 select HAVE_ARCH_STACKLEAK <<
188 select HAVE_ARCH_THREAD_STRUCT_WHITELI <<
189 select HAVE_ARCH_TRACEHOOK 42 select HAVE_ARCH_TRACEHOOK
190 select HAVE_ARCH_TRANSPARENT_HUGEPAGE !! 43 select HAVE_ARCH_TRANSPARENT_HUGEPAGE if CPU_SUPPORTS_HUGEPAGES && 64BIT
191 select HAVE_ARCH_VMAP_STACK !! 44 select HAVE_CBPF_JIT if (!64BIT && !CPU_MICROMIPS)
192 select HAVE_ARM_SMCCC !! 45 select HAVE_EBPF_JIT if (64BIT && !CPU_MICROMIPS)
193 select HAVE_ASM_MODVERSIONS !! 46 select HAVE_CONTEXT_TRACKING
194 select HAVE_EBPF_JIT !! 47 select HAVE_COPY_THREAD_TLS
195 select HAVE_C_RECORDMCOUNT 48 select HAVE_C_RECORDMCOUNT
196 select HAVE_CMPXCHG_DOUBLE <<
197 select HAVE_CMPXCHG_LOCAL <<
198 select HAVE_CONTEXT_TRACKING_USER <<
199 select HAVE_DEBUG_KMEMLEAK 49 select HAVE_DEBUG_KMEMLEAK
>> 50 select HAVE_DEBUG_STACKOVERFLOW
200 select HAVE_DMA_CONTIGUOUS 51 select HAVE_DMA_CONTIGUOUS
201 select HAVE_DYNAMIC_FTRACE 52 select HAVE_DYNAMIC_FTRACE
202 select HAVE_DYNAMIC_FTRACE_WITH_ARGS \ !! 53 select HAVE_EXIT_THREAD
203 if (GCC_SUPPORTS_DYNAMIC_FTRAC <<
204 CLANG_SUPPORTS_DYNAMIC_FTR <<
205 select HAVE_DYNAMIC_FTRACE_WITH_DIRECT <<
206 if DYNAMIC_FTRACE_WITH_ARGS && <<
207 select HAVE_DYNAMIC_FTRACE_WITH_CALL_O <<
208 if (DYNAMIC_FTRACE_WITH_ARGS & <<
209 (CC_IS_CLANG || !CC_OPTIMI <<
210 select FTRACE_MCOUNT_USE_PATCHABLE_FUN <<
211 if DYNAMIC_FTRACE_WITH_ARGS <<
212 select HAVE_SAMPLE_FTRACE_DIRECT <<
213 select HAVE_SAMPLE_FTRACE_DIRECT_MULTI <<
214 select HAVE_EFFICIENT_UNALIGNED_ACCESS <<
215 select HAVE_GUP_FAST <<
216 select HAVE_FTRACE_MCOUNT_RECORD 54 select HAVE_FTRACE_MCOUNT_RECORD
217 select HAVE_FUNCTION_TRACER <<
218 select HAVE_FUNCTION_ERROR_INJECTION <<
219 select HAVE_FUNCTION_GRAPH_TRACER 55 select HAVE_FUNCTION_GRAPH_TRACER
220 select HAVE_FUNCTION_GRAPH_RETVAL !! 56 select HAVE_FUNCTION_TRACER
221 select HAVE_GCC_PLUGINS !! 57 select HAVE_GENERIC_DMA_COHERENT
222 select HAVE_HARDLOCKUP_DETECTOR_PERF i !! 58 select HAVE_IDE
223 HW_PERF_EVENTS && HAVE_PERF_EV !! 59 select HAVE_IRQ_EXIT_ON_IRQ_STACK
224 select HAVE_HW_BREAKPOINT if PERF_EVEN <<
225 select HAVE_IOREMAP_PROT <<
226 select HAVE_IRQ_TIME_ACCOUNTING 60 select HAVE_IRQ_TIME_ACCOUNTING
>> 61 select HAVE_KPROBES
>> 62 select HAVE_KRETPROBES
>> 63 select HAVE_MEMBLOCK_NODE_MAP
227 select HAVE_MOD_ARCH_SPECIFIC 64 select HAVE_MOD_ARCH_SPECIFIC
228 select HAVE_NMI 65 select HAVE_NMI
>> 66 select HAVE_OPROFILE
229 select HAVE_PERF_EVENTS 67 select HAVE_PERF_EVENTS
230 select HAVE_PERF_EVENTS_NMI if ARM64_P <<
231 select HAVE_PERF_REGS <<
232 select HAVE_PERF_USER_STACK_DUMP <<
233 select HAVE_PREEMPT_DYNAMIC_KEY <<
234 select HAVE_REGS_AND_STACK_ACCESS_API 68 select HAVE_REGS_AND_STACK_ACCESS_API
235 select HAVE_POSIX_CPU_TIMERS_TASK_WORK <<
236 select HAVE_FUNCTION_ARG_ACCESS_API <<
237 select MMU_GATHER_RCU_TABLE_FREE <<
238 select HAVE_RSEQ 69 select HAVE_RSEQ
239 select HAVE_RUST if RUSTC_SUPPORTS_ARM <<
240 select HAVE_STACKPROTECTOR 70 select HAVE_STACKPROTECTOR
241 select HAVE_SYSCALL_TRACEPOINTS 71 select HAVE_SYSCALL_TRACEPOINTS
242 select HAVE_KPROBES !! 72 select HAVE_VIRT_CPU_ACCOUNTING_GEN if 64BIT || !SMP
243 select HAVE_KRETPROBES <<
244 select HAVE_GENERIC_VDSO <<
245 select HOTPLUG_CORE_SYNC_DEAD if HOTPL <<
246 select IRQ_DOMAIN <<
247 select IRQ_FORCED_THREADING 73 select IRQ_FORCED_THREADING
248 select KASAN_VMALLOC if KASAN !! 74 select MODULES_USE_ELF_RELA if MODULES && 64BIT
249 select LOCK_MM_AND_FIND_VMA !! 75 select MODULES_USE_ELF_REL if MODULES
250 select MODULES_USE_ELF_RELA !! 76 select PERF_USE_VMALLOC
251 select NEED_DMA_MAP_STATE !! 77 select RTC_LIB
252 select NEED_SG_DMA_LENGTH <<
253 select OF <<
254 select OF_EARLY_FLATTREE <<
255 select PCI_DOMAINS_GENERIC if PCI <<
256 select PCI_ECAM if (ACPI && PCI) <<
257 select PCI_SYSCALL if PCI <<
258 select POWER_RESET <<
259 select POWER_SUPPLY <<
260 select SPARSE_IRQ <<
261 select SWIOTLB <<
262 select SYSCTL_EXCEPTION_TRACE 78 select SYSCTL_EXCEPTION_TRACE
263 select THREAD_INFO_IN_TASK !! 79 select VIRT_TO_BUS
264 select HAVE_ARCH_USERFAULTFD_MINOR if <<
265 select HAVE_ARCH_USERFAULTFD_WP if USE <<
266 select TRACE_IRQFLAGS_SUPPORT <<
267 select TRACE_IRQFLAGS_NMI_SUPPORT <<
268 select HAVE_SOFTIRQ_ON_OWN_STACK <<
269 select USER_STACKTRACE_SUPPORT <<
270 select VDSO_GETRANDOM <<
271 help <<
272 ARM 64-bit (AArch64) Linux support. <<
273 <<
274 config RUSTC_SUPPORTS_ARM64 <<
275 def_bool y <<
276 depends on CPU_LITTLE_ENDIAN <<
277 # Shadow call stack is only supported <<
278 # <<
279 # When using the UNWIND_PATCH_PAC_INTO <<
280 # required due to use of the -Zfixed-x <<
281 # <<
282 # Otherwise, rustc version 1.82+ is re <<
283 # -Zsanitizer=shadow-call-stack flag. <<
284 depends on !SHADOW_CALL_STACK || RUSTC <<
285 <<
286 config CLANG_SUPPORTS_DYNAMIC_FTRACE_WITH_ARGS <<
287 def_bool CC_IS_CLANG <<
288 # https://github.com/ClangBuiltLinux/l <<
289 depends on AS_IS_GNU || (AS_IS_LLVM && <<
290 <<
291 config GCC_SUPPORTS_DYNAMIC_FTRACE_WITH_ARGS <<
292 def_bool CC_IS_GCC <<
293 depends on $(cc-option,-fpatchable-fun <<
294 <<
295 config 64BIT <<
296 def_bool y <<
297 <<
298 config MMU <<
299 def_bool y <<
300 <<
301 config ARM64_CONT_PTE_SHIFT <<
302 int <<
303 default 5 if PAGE_SIZE_64KB <<
304 default 7 if PAGE_SIZE_16KB <<
305 default 4 <<
306 <<
307 config ARM64_CONT_PMD_SHIFT <<
308 int <<
309 default 5 if PAGE_SIZE_64KB <<
310 default 5 if PAGE_SIZE_16KB <<
311 default 4 <<
312 <<
313 config ARCH_MMAP_RND_BITS_MIN <<
314 default 14 if PAGE_SIZE_64KB <<
315 default 16 if PAGE_SIZE_16KB <<
316 default 18 <<
317 <<
318 # max bits determined by the following formula <<
319 # VA_BITS - PAGE_SHIFT - 3 <<
320 config ARCH_MMAP_RND_BITS_MAX <<
321 default 19 if ARM64_VA_BITS=36 <<
322 default 24 if ARM64_VA_BITS=39 <<
323 default 27 if ARM64_VA_BITS=42 <<
324 default 30 if ARM64_VA_BITS=47 <<
325 default 29 if ARM64_VA_BITS=48 && ARM6 <<
326 default 31 if ARM64_VA_BITS=48 && ARM6 <<
327 default 33 if ARM64_VA_BITS=48 <<
328 default 14 if ARM64_64K_PAGES <<
329 default 16 if ARM64_16K_PAGES <<
330 default 18 <<
331 <<
332 config ARCH_MMAP_RND_COMPAT_BITS_MIN <<
333 default 7 if ARM64_64K_PAGES <<
334 default 9 if ARM64_16K_PAGES <<
335 default 11 <<
336 <<
337 config ARCH_MMAP_RND_COMPAT_BITS_MAX <<
338 default 16 <<
339 <<
340 config NO_IOPORT_MAP <<
341 def_bool y if !PCI <<
342 <<
343 config STACKTRACE_SUPPORT <<
344 def_bool y <<
345 <<
346 config ILLEGAL_POINTER_VALUE <<
347 hex <<
348 default 0xdead000000000000 <<
349 <<
350 config LOCKDEP_SUPPORT <<
351 def_bool y <<
352 <<
353 config GENERIC_BUG <<
354 def_bool y <<
355 depends on BUG <<
356 80
357 config GENERIC_BUG_RELATIVE_POINTERS !! 81 menu "Machine selection"
358 def_bool y <<
359 depends on GENERIC_BUG <<
360 82
361 config GENERIC_HWEIGHT !! 83 choice
362 def_bool y !! 84 prompt "System type"
363 !! 85 default MIPS_GENERIC
364 config GENERIC_CSUM <<
365 def_bool y <<
366 86
367 config GENERIC_CALIBRATE_DELAY !! 87 config MIPS_GENERIC
368 def_bool y !! 88 bool "Generic board-agnostic MIPS kernel"
>> 89 select BOOT_RAW
>> 90 select BUILTIN_DTB
>> 91 select CEVT_R4K
>> 92 select CLKSRC_MIPS_GIC
>> 93 select COMMON_CLK
>> 94 select CPU_MIPSR2_IRQ_VI
>> 95 select CPU_MIPSR2_IRQ_EI
>> 96 select CSRC_R4K
>> 97 select DMA_PERDEV_COHERENT
>> 98 select HW_HAS_PCI
>> 99 select IRQ_MIPS_CPU
>> 100 select LIBFDT
>> 101 select MIPS_AUTO_PFN_OFFSET
>> 102 select MIPS_CPU_SCACHE
>> 103 select MIPS_GIC
>> 104 select MIPS_L1_CACHE_SHIFT_7
>> 105 select NO_EXCEPT_FILL
>> 106 select PCI_DRIVERS_GENERIC
>> 107 select PINCTRL
>> 108 select SMP_UP if SMP
>> 109 select SWAP_IO_SPACE
>> 110 select SYS_HAS_CPU_MIPS32_R1
>> 111 select SYS_HAS_CPU_MIPS32_R2
>> 112 select SYS_HAS_CPU_MIPS32_R6
>> 113 select SYS_HAS_CPU_MIPS64_R1
>> 114 select SYS_HAS_CPU_MIPS64_R2
>> 115 select SYS_HAS_CPU_MIPS64_R6
>> 116 select SYS_SUPPORTS_32BIT_KERNEL
>> 117 select SYS_SUPPORTS_64BIT_KERNEL
>> 118 select SYS_SUPPORTS_BIG_ENDIAN
>> 119 select SYS_SUPPORTS_HIGHMEM
>> 120 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 121 select SYS_SUPPORTS_MICROMIPS
>> 122 select SYS_SUPPORTS_MIPS_CPS
>> 123 select SYS_SUPPORTS_MIPS16
>> 124 select SYS_SUPPORTS_MULTITHREADING
>> 125 select SYS_SUPPORTS_RELOCATABLE
>> 126 select SYS_SUPPORTS_SMARTMIPS
>> 127 select USB_EHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
>> 128 select USB_EHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 129 select USB_OHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
>> 130 select USB_OHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 131 select USB_UHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
>> 132 select USB_UHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 133 select USE_OF
>> 134 select UHI_BOOT
>> 135 help
>> 136 Select this to build a kernel which aims to support multiple boards,
>> 137 generally using a flattened device tree passed from the bootloader
>> 138 using the boot protocol defined in the UHI (Unified Hosting
>> 139 Interface) specification.
>> 140
>> 141 config MIPS_ALCHEMY
>> 142 bool "Alchemy processor based machines"
>> 143 select PHYS_ADDR_T_64BIT
>> 144 select CEVT_R4K
>> 145 select CSRC_R4K
>> 146 select IRQ_MIPS_CPU
>> 147 select DMA_MAYBE_COHERENT # Au1000,1500,1100 aren't, rest is
>> 148 select SYS_HAS_CPU_MIPS32_R1
>> 149 select SYS_SUPPORTS_32BIT_KERNEL
>> 150 select SYS_SUPPORTS_APM_EMULATION
>> 151 select GPIOLIB
>> 152 select SYS_SUPPORTS_ZBOOT
>> 153 select COMMON_CLK
369 154
370 config SMP !! 155 config AR7
371 def_bool y !! 156 bool "Texas Instruments AR7"
>> 157 select BOOT_ELF32
>> 158 select DMA_NONCOHERENT
>> 159 select CEVT_R4K
>> 160 select CSRC_R4K
>> 161 select IRQ_MIPS_CPU
>> 162 select NO_EXCEPT_FILL
>> 163 select SWAP_IO_SPACE
>> 164 select SYS_HAS_CPU_MIPS32_R1
>> 165 select SYS_HAS_EARLY_PRINTK
>> 166 select SYS_SUPPORTS_32BIT_KERNEL
>> 167 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 168 select SYS_SUPPORTS_MIPS16
>> 169 select SYS_SUPPORTS_ZBOOT_UART16550
>> 170 select GPIOLIB
>> 171 select VLYNQ
>> 172 select HAVE_CLK
>> 173 help
>> 174 Support for the Texas Instruments AR7 System-on-a-Chip
>> 175 family: TNETD7100, 7200 and 7300.
>> 176
>> 177 config ATH25
>> 178 bool "Atheros AR231x/AR531x SoC support"
>> 179 select CEVT_R4K
>> 180 select CSRC_R4K
>> 181 select DMA_NONCOHERENT
>> 182 select IRQ_MIPS_CPU
>> 183 select IRQ_DOMAIN
>> 184 select SYS_HAS_CPU_MIPS32_R1
>> 185 select SYS_SUPPORTS_BIG_ENDIAN
>> 186 select SYS_SUPPORTS_32BIT_KERNEL
>> 187 select SYS_HAS_EARLY_PRINTK
>> 188 help
>> 189 Support for Atheros AR231x and Atheros AR531x based boards
>> 190
>> 191 config ATH79
>> 192 bool "Atheros AR71XX/AR724X/AR913X based boards"
>> 193 select ARCH_HAS_RESET_CONTROLLER
>> 194 select BOOT_RAW
>> 195 select CEVT_R4K
>> 196 select CSRC_R4K
>> 197 select DMA_NONCOHERENT
>> 198 select GPIOLIB
>> 199 select PINCTRL
>> 200 select HAVE_CLK
>> 201 select COMMON_CLK
>> 202 select CLKDEV_LOOKUP
>> 203 select IRQ_MIPS_CPU
>> 204 select MIPS_MACHINE
>> 205 select SYS_HAS_CPU_MIPS32_R2
>> 206 select SYS_HAS_EARLY_PRINTK
>> 207 select SYS_SUPPORTS_32BIT_KERNEL
>> 208 select SYS_SUPPORTS_BIG_ENDIAN
>> 209 select SYS_SUPPORTS_MIPS16
>> 210 select SYS_SUPPORTS_ZBOOT_UART_PROM
>> 211 select USE_OF
>> 212 select USB_EHCI_ROOT_HUB_TT if USB_EHCI_HCD_PLATFORM
>> 213 help
>> 214 Support for the Atheros AR71XX/AR724X/AR913X SoCs.
>> 215
>> 216 config BMIPS_GENERIC
>> 217 bool "Broadcom Generic BMIPS kernel"
>> 218 select ARCH_HAS_SYNC_DMA_FOR_CPU_ALL
>> 219 select ARCH_HAS_PHYS_TO_DMA
>> 220 select BOOT_RAW
>> 221 select NO_EXCEPT_FILL
>> 222 select USE_OF
>> 223 select CEVT_R4K
>> 224 select CSRC_R4K
>> 225 select SYNC_R4K
>> 226 select COMMON_CLK
>> 227 select BCM6345_L1_IRQ
>> 228 select BCM7038_L1_IRQ
>> 229 select BCM7120_L2_IRQ
>> 230 select BRCMSTB_L2_IRQ
>> 231 select IRQ_MIPS_CPU
>> 232 select DMA_NONCOHERENT
>> 233 select SYS_SUPPORTS_32BIT_KERNEL
>> 234 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 235 select SYS_SUPPORTS_BIG_ENDIAN
>> 236 select SYS_SUPPORTS_HIGHMEM
>> 237 select SYS_HAS_CPU_BMIPS32_3300
>> 238 select SYS_HAS_CPU_BMIPS4350
>> 239 select SYS_HAS_CPU_BMIPS4380
>> 240 select SYS_HAS_CPU_BMIPS5000
>> 241 select SWAP_IO_SPACE
>> 242 select USB_EHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
>> 243 select USB_EHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 244 select USB_OHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
>> 245 select USB_OHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 246 select HARDIRQS_SW_RESEND
>> 247 help
>> 248 Build a generic DT-based kernel image that boots on select
>> 249 BCM33xx cable modem chips, BCM63xx DSL chips, and BCM7xxx set-top
>> 250 box chips. Note that CONFIG_CPU_BIG_ENDIAN/CONFIG_CPU_LITTLE_ENDIAN
>> 251 must be set appropriately for your board.
>> 252
>> 253 config BCM47XX
>> 254 bool "Broadcom BCM47XX based boards"
>> 255 select BOOT_RAW
>> 256 select CEVT_R4K
>> 257 select CSRC_R4K
>> 258 select DMA_NONCOHERENT
>> 259 select HW_HAS_PCI
>> 260 select IRQ_MIPS_CPU
>> 261 select SYS_HAS_CPU_MIPS32_R1
>> 262 select NO_EXCEPT_FILL
>> 263 select SYS_SUPPORTS_32BIT_KERNEL
>> 264 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 265 select SYS_SUPPORTS_MIPS16
>> 266 select SYS_SUPPORTS_ZBOOT
>> 267 select SYS_HAS_EARLY_PRINTK
>> 268 select USE_GENERIC_EARLY_PRINTK_8250
>> 269 select GPIOLIB
>> 270 select LEDS_GPIO_REGISTER
>> 271 select BCM47XX_NVRAM
>> 272 select BCM47XX_SPROM
>> 273 select BCM47XX_SSB if !BCM47XX_BCMA
>> 274 help
>> 275 Support for BCM47XX based boards
>> 276
>> 277 config BCM63XX
>> 278 bool "Broadcom BCM63XX based boards"
>> 279 select BOOT_RAW
>> 280 select CEVT_R4K
>> 281 select CSRC_R4K
>> 282 select SYNC_R4K
>> 283 select DMA_NONCOHERENT
>> 284 select IRQ_MIPS_CPU
>> 285 select SYS_SUPPORTS_32BIT_KERNEL
>> 286 select SYS_SUPPORTS_BIG_ENDIAN
>> 287 select SYS_HAS_EARLY_PRINTK
>> 288 select SWAP_IO_SPACE
>> 289 select GPIOLIB
>> 290 select HAVE_CLK
>> 291 select MIPS_L1_CACHE_SHIFT_4
>> 292 select CLKDEV_LOOKUP
>> 293 help
>> 294 Support for BCM63XX based boards
>> 295
>> 296 config MIPS_COBALT
>> 297 bool "Cobalt Server"
>> 298 select CEVT_R4K
>> 299 select CSRC_R4K
>> 300 select CEVT_GT641XX
>> 301 select DMA_NONCOHERENT
>> 302 select HW_HAS_PCI
>> 303 select I8253
>> 304 select I8259
>> 305 select IRQ_MIPS_CPU
>> 306 select IRQ_GT641XX
>> 307 select PCI_GT64XXX_PCI0
>> 308 select PCI
>> 309 select SYS_HAS_CPU_NEVADA
>> 310 select SYS_HAS_EARLY_PRINTK
>> 311 select SYS_SUPPORTS_32BIT_KERNEL
>> 312 select SYS_SUPPORTS_64BIT_KERNEL
>> 313 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 314 select USE_GENERIC_EARLY_PRINTK_8250
>> 315
>> 316 config MACH_DECSTATION
>> 317 bool "DECstations"
>> 318 select BOOT_ELF32
>> 319 select CEVT_DS1287
>> 320 select CEVT_R4K if CPU_R4X00
>> 321 select CSRC_IOASIC
>> 322 select CSRC_R4K if CPU_R4X00
>> 323 select CPU_DADDI_WORKAROUNDS if 64BIT
>> 324 select CPU_R4000_WORKAROUNDS if 64BIT
>> 325 select CPU_R4400_WORKAROUNDS if 64BIT
>> 326 select DMA_NONCOHERENT
>> 327 select NO_IOPORT_MAP
>> 328 select IRQ_MIPS_CPU
>> 329 select SYS_HAS_CPU_R3000
>> 330 select SYS_HAS_CPU_R4X00
>> 331 select SYS_SUPPORTS_32BIT_KERNEL
>> 332 select SYS_SUPPORTS_64BIT_KERNEL
>> 333 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 334 select SYS_SUPPORTS_128HZ
>> 335 select SYS_SUPPORTS_256HZ
>> 336 select SYS_SUPPORTS_1024HZ
>> 337 select MIPS_L1_CACHE_SHIFT_4
>> 338 help
>> 339 This enables support for DEC's MIPS based workstations. For details
>> 340 see the Linux/MIPS FAQ on <http://www.linux-mips.org/> and the
>> 341 DECstation porting pages on <http://decstation.unix-ag.org/>.
>> 342
>> 343 If you have one of the following DECstation Models you definitely
>> 344 want to choose R4xx0 for the CPU Type:
>> 345
>> 346 DECstation 5000/50
>> 347 DECstation 5000/150
>> 348 DECstation 5000/260
>> 349 DECsystem 5900/260
>> 350
>> 351 otherwise choose R3000.
>> 352
>> 353 config MACH_JAZZ
>> 354 bool "Jazz family of machines"
>> 355 select ARCH_MIGHT_HAVE_PC_PARPORT
>> 356 select ARCH_MIGHT_HAVE_PC_SERIO
>> 357 select FW_ARC
>> 358 select FW_ARC32
>> 359 select ARCH_MAY_HAVE_PC_FDC
>> 360 select CEVT_R4K
>> 361 select CSRC_R4K
>> 362 select DEFAULT_SGI_PARTITION if CPU_BIG_ENDIAN
>> 363 select GENERIC_ISA_DMA
>> 364 select HAVE_PCSPKR_PLATFORM
>> 365 select IRQ_MIPS_CPU
>> 366 select I8253
>> 367 select I8259
>> 368 select ISA
>> 369 select SYS_HAS_CPU_R4X00
>> 370 select SYS_SUPPORTS_32BIT_KERNEL
>> 371 select SYS_SUPPORTS_64BIT_KERNEL
>> 372 select SYS_SUPPORTS_100HZ
>> 373 help
>> 374 This a family of machines based on the MIPS R4030 chipset which was
>> 375 used by several vendors to build RISC/os and Windows NT workstations.
>> 376 Members include the Acer PICA, MIPS Magnum 4000, MIPS Millennium and
>> 377 Olivetti M700-10 workstations.
>> 378
>> 379 config MACH_INGENIC
>> 380 bool "Ingenic SoC based machines"
>> 381 select SYS_SUPPORTS_32BIT_KERNEL
>> 382 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 383 select SYS_SUPPORTS_ZBOOT_UART16550
>> 384 select DMA_NONCOHERENT
>> 385 select IRQ_MIPS_CPU
>> 386 select PINCTRL
>> 387 select GPIOLIB
>> 388 select COMMON_CLK
>> 389 select GENERIC_IRQ_CHIP
>> 390 select BUILTIN_DTB
>> 391 select USE_OF
>> 392 select LIBFDT
372 393
373 config KERNEL_MODE_NEON !! 394 config LANTIQ
374 def_bool y !! 395 bool "Lantiq based platforms"
>> 396 select DMA_NONCOHERENT
>> 397 select IRQ_MIPS_CPU
>> 398 select CEVT_R4K
>> 399 select CSRC_R4K
>> 400 select SYS_HAS_CPU_MIPS32_R1
>> 401 select SYS_HAS_CPU_MIPS32_R2
>> 402 select SYS_SUPPORTS_BIG_ENDIAN
>> 403 select SYS_SUPPORTS_32BIT_KERNEL
>> 404 select SYS_SUPPORTS_MIPS16
>> 405 select SYS_SUPPORTS_MULTITHREADING
>> 406 select SYS_SUPPORTS_VPE_LOADER
>> 407 select SYS_HAS_EARLY_PRINTK
>> 408 select GPIOLIB
>> 409 select SWAP_IO_SPACE
>> 410 select BOOT_RAW
>> 411 select CLKDEV_LOOKUP
>> 412 select USE_OF
>> 413 select PINCTRL
>> 414 select PINCTRL_LANTIQ
>> 415 select ARCH_HAS_RESET_CONTROLLER
>> 416 select RESET_CONTROLLER
>> 417
>> 418 config LASAT
>> 419 bool "LASAT Networks platforms"
>> 420 select CEVT_R4K
>> 421 select CRC32
>> 422 select CSRC_R4K
>> 423 select DMA_NONCOHERENT
>> 424 select SYS_HAS_EARLY_PRINTK
>> 425 select HW_HAS_PCI
>> 426 select IRQ_MIPS_CPU
>> 427 select PCI_GT64XXX_PCI0
>> 428 select MIPS_NILE4
>> 429 select R5000_CPU_SCACHE
>> 430 select SYS_HAS_CPU_R5000
>> 431 select SYS_SUPPORTS_32BIT_KERNEL
>> 432 select SYS_SUPPORTS_64BIT_KERNEL if BROKEN
>> 433 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 434
>> 435 config MACH_LOONGSON32
>> 436 bool "Loongson-1 family of machines"
>> 437 select SYS_SUPPORTS_ZBOOT
>> 438 help
>> 439 This enables support for the Loongson-1 family of machines.
>> 440
>> 441 Loongson-1 is a family of 32-bit MIPS-compatible SoCs developed by
>> 442 the Institute of Computing Technology (ICT), Chinese Academy of
>> 443 Sciences (CAS).
>> 444
>> 445 config MACH_LOONGSON64
>> 446 bool "Loongson-2/3 family of machines"
>> 447 select SYS_SUPPORTS_ZBOOT
>> 448 help
>> 449 This enables the support of Loongson-2/3 family of machines.
>> 450
>> 451 Loongson-2 is a family of single-core CPUs and Loongson-3 is a
>> 452 family of multi-core CPUs. They are both 64-bit general-purpose
>> 453 MIPS-compatible CPUs. Loongson-2/3 are developed by the Institute
>> 454 of Computing Technology (ICT), Chinese Academy of Sciences (CAS)
>> 455 in the People's Republic of China. The chief architect is Professor
>> 456 Weiwu Hu.
>> 457
>> 458 config MACH_PISTACHIO
>> 459 bool "IMG Pistachio SoC based boards"
>> 460 select BOOT_ELF32
>> 461 select BOOT_RAW
>> 462 select CEVT_R4K
>> 463 select CLKSRC_MIPS_GIC
>> 464 select COMMON_CLK
>> 465 select CSRC_R4K
>> 466 select DMA_NONCOHERENT
>> 467 select GPIOLIB
>> 468 select IRQ_MIPS_CPU
>> 469 select LIBFDT
>> 470 select MFD_SYSCON
>> 471 select MIPS_CPU_SCACHE
>> 472 select MIPS_GIC
>> 473 select PINCTRL
>> 474 select REGULATOR
>> 475 select SYS_HAS_CPU_MIPS32_R2
>> 476 select SYS_SUPPORTS_32BIT_KERNEL
>> 477 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 478 select SYS_SUPPORTS_MIPS_CPS
>> 479 select SYS_SUPPORTS_MULTITHREADING
>> 480 select SYS_SUPPORTS_RELOCATABLE
>> 481 select SYS_SUPPORTS_ZBOOT
>> 482 select SYS_HAS_EARLY_PRINTK
>> 483 select USE_GENERIC_EARLY_PRINTK_8250
>> 484 select USE_OF
>> 485 help
>> 486 This enables support for the IMG Pistachio SoC platform.
>> 487
>> 488 config MIPS_MALTA
>> 489 bool "MIPS Malta board"
>> 490 select ARCH_MAY_HAVE_PC_FDC
>> 491 select ARCH_MIGHT_HAVE_PC_PARPORT
>> 492 select ARCH_MIGHT_HAVE_PC_SERIO
>> 493 select BOOT_ELF32
>> 494 select BOOT_RAW
>> 495 select BUILTIN_DTB
>> 496 select CEVT_R4K
>> 497 select CSRC_R4K
>> 498 select CLKSRC_MIPS_GIC
>> 499 select COMMON_CLK
>> 500 select DMA_MAYBE_COHERENT
>> 501 select GENERIC_ISA_DMA
>> 502 select HAVE_PCSPKR_PLATFORM
>> 503 select IRQ_MIPS_CPU
>> 504 select MIPS_GIC
>> 505 select HW_HAS_PCI
>> 506 select I8253
>> 507 select I8259
>> 508 select MIPS_BONITO64
>> 509 select MIPS_CPU_SCACHE
>> 510 select MIPS_L1_CACHE_SHIFT_6
>> 511 select PCI_GT64XXX_PCI0
>> 512 select MIPS_MSC
>> 513 select SMP_UP if SMP
>> 514 select SWAP_IO_SPACE
>> 515 select SYS_HAS_CPU_MIPS32_R1
>> 516 select SYS_HAS_CPU_MIPS32_R2
>> 517 select SYS_HAS_CPU_MIPS32_R3_5
>> 518 select SYS_HAS_CPU_MIPS32_R5
>> 519 select SYS_HAS_CPU_MIPS32_R6
>> 520 select SYS_HAS_CPU_MIPS64_R1
>> 521 select SYS_HAS_CPU_MIPS64_R2
>> 522 select SYS_HAS_CPU_MIPS64_R6
>> 523 select SYS_HAS_CPU_NEVADA
>> 524 select SYS_HAS_CPU_RM7000
>> 525 select SYS_SUPPORTS_32BIT_KERNEL
>> 526 select SYS_SUPPORTS_64BIT_KERNEL
>> 527 select SYS_SUPPORTS_BIG_ENDIAN
>> 528 select SYS_SUPPORTS_HIGHMEM
>> 529 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 530 select SYS_SUPPORTS_MICROMIPS
>> 531 select SYS_SUPPORTS_MIPS_CMP
>> 532 select SYS_SUPPORTS_MIPS_CPS
>> 533 select SYS_SUPPORTS_MIPS16
>> 534 select SYS_SUPPORTS_MULTITHREADING
>> 535 select SYS_SUPPORTS_SMARTMIPS
>> 536 select SYS_SUPPORTS_VPE_LOADER
>> 537 select SYS_SUPPORTS_ZBOOT
>> 538 select SYS_SUPPORTS_RELOCATABLE
>> 539 select USE_OF
>> 540 select LIBFDT
>> 541 select ZONE_DMA32 if 64BIT
>> 542 select BUILTIN_DTB
>> 543 select LIBFDT
>> 544 help
>> 545 This enables support for the MIPS Technologies Malta evaluation
>> 546 board.
375 547
376 config FIX_EARLYCON_MEM !! 548 config MACH_PIC32
377 def_bool y !! 549 bool "Microchip PIC32 Family"
>> 550 help
>> 551 This enables support for the Microchip PIC32 family of platforms.
378 552
379 config PGTABLE_LEVELS !! 553 Microchip PIC32 is a family of general-purpose 32 bit MIPS core
380 int !! 554 microcontrollers.
381 default 2 if ARM64_16K_PAGES && ARM64_ !! 555
382 default 2 if ARM64_64K_PAGES && ARM64_ !! 556 config NEC_MARKEINS
383 default 3 if ARM64_64K_PAGES && (ARM64 !! 557 bool "NEC EMMA2RH Mark-eins board"
384 default 3 if ARM64_4K_PAGES && ARM64_V !! 558 select SOC_EMMA2RH
385 default 3 if ARM64_16K_PAGES && ARM64_ !! 559 select HW_HAS_PCI
386 default 4 if ARM64_16K_PAGES && (ARM64 !! 560 help
387 default 4 if !ARM64_64K_PAGES && ARM64 !! 561 This enables support for the NEC Electronics Mark-eins boards.
388 default 5 if ARM64_4K_PAGES && ARM64_V !! 562
>> 563 config MACH_VR41XX
>> 564 bool "NEC VR4100 series based machines"
>> 565 select CEVT_R4K
>> 566 select CSRC_R4K
>> 567 select SYS_HAS_CPU_VR41XX
>> 568 select SYS_SUPPORTS_MIPS16
>> 569 select GPIOLIB
>> 570
>> 571 config NXP_STB220
>> 572 bool "NXP STB220 board"
>> 573 select SOC_PNX833X
>> 574 help
>> 575 Support for NXP Semiconductors STB220 Development Board.
>> 576
>> 577 config NXP_STB225
>> 578 bool "NXP 225 board"
>> 579 select SOC_PNX833X
>> 580 select SOC_PNX8335
>> 581 help
>> 582 Support for NXP Semiconductors STB225 Development Board.
>> 583
>> 584 config PMC_MSP
>> 585 bool "PMC-Sierra MSP chipsets"
>> 586 select CEVT_R4K
>> 587 select CSRC_R4K
>> 588 select DMA_NONCOHERENT
>> 589 select SWAP_IO_SPACE
>> 590 select NO_EXCEPT_FILL
>> 591 select BOOT_RAW
>> 592 select SYS_HAS_CPU_MIPS32_R1
>> 593 select SYS_HAS_CPU_MIPS32_R2
>> 594 select SYS_SUPPORTS_32BIT_KERNEL
>> 595 select SYS_SUPPORTS_BIG_ENDIAN
>> 596 select SYS_SUPPORTS_MIPS16
>> 597 select IRQ_MIPS_CPU
>> 598 select SERIAL_8250
>> 599 select SERIAL_8250_CONSOLE
>> 600 select USB_EHCI_BIG_ENDIAN_MMIO
>> 601 select USB_EHCI_BIG_ENDIAN_DESC
>> 602 help
>> 603 This adds support for the PMC-Sierra family of Multi-Service
>> 604 Processor System-On-A-Chips. These parts include a number
>> 605 of integrated peripherals, interfaces and DSPs in addition to
>> 606 a variety of MIPS cores.
>> 607
>> 608 config RALINK
>> 609 bool "Ralink based machines"
>> 610 select CEVT_R4K
>> 611 select CSRC_R4K
>> 612 select BOOT_RAW
>> 613 select DMA_NONCOHERENT
>> 614 select IRQ_MIPS_CPU
>> 615 select USE_OF
>> 616 select SYS_HAS_CPU_MIPS32_R1
>> 617 select SYS_HAS_CPU_MIPS32_R2
>> 618 select SYS_SUPPORTS_32BIT_KERNEL
>> 619 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 620 select SYS_SUPPORTS_MIPS16
>> 621 select SYS_HAS_EARLY_PRINTK
>> 622 select CLKDEV_LOOKUP
>> 623 select ARCH_HAS_RESET_CONTROLLER
>> 624 select RESET_CONTROLLER
>> 625
>> 626 config SGI_IP22
>> 627 bool "SGI IP22 (Indy/Indigo2)"
>> 628 select FW_ARC
>> 629 select FW_ARC32
>> 630 select ARCH_MIGHT_HAVE_PC_SERIO
>> 631 select BOOT_ELF32
>> 632 select CEVT_R4K
>> 633 select CSRC_R4K
>> 634 select DEFAULT_SGI_PARTITION
>> 635 select DMA_NONCOHERENT
>> 636 select HW_HAS_EISA
>> 637 select I8253
>> 638 select I8259
>> 639 select IP22_CPU_SCACHE
>> 640 select IRQ_MIPS_CPU
>> 641 select GENERIC_ISA_DMA_SUPPORT_BROKEN
>> 642 select SGI_HAS_I8042
>> 643 select SGI_HAS_INDYDOG
>> 644 select SGI_HAS_HAL2
>> 645 select SGI_HAS_SEEQ
>> 646 select SGI_HAS_WD93
>> 647 select SGI_HAS_ZILOG
>> 648 select SWAP_IO_SPACE
>> 649 select SYS_HAS_CPU_R4X00
>> 650 select SYS_HAS_CPU_R5000
>> 651 #
>> 652 # Disable EARLY_PRINTK for now since it leads to overwritten prom
>> 653 # memory during early boot on some machines.
>> 654 #
>> 655 # See http://www.linux-mips.org/cgi-bin/mesg.cgi?a=linux-mips&i=20091119164009.GA15038%40deprecation.cyrius.com
>> 656 # for a more details discussion
>> 657 #
>> 658 # select SYS_HAS_EARLY_PRINTK
>> 659 select SYS_SUPPORTS_32BIT_KERNEL
>> 660 select SYS_SUPPORTS_64BIT_KERNEL
>> 661 select SYS_SUPPORTS_BIG_ENDIAN
>> 662 select MIPS_L1_CACHE_SHIFT_7
>> 663 help
>> 664 This are the SGI Indy, Challenge S and Indigo2, as well as certain
>> 665 OEM variants like the Tandem CMN B006S. To compile a Linux kernel
>> 666 that runs on these, say Y here.
>> 667
>> 668 config SGI_IP27
>> 669 bool "SGI IP27 (Origin200/2000)"
>> 670 select ARCH_HAS_PHYS_TO_DMA
>> 671 select FW_ARC
>> 672 select FW_ARC64
>> 673 select BOOT_ELF64
>> 674 select DEFAULT_SGI_PARTITION
>> 675 select SYS_HAS_EARLY_PRINTK
>> 676 select HW_HAS_PCI
>> 677 select NR_CPUS_DEFAULT_64
>> 678 select SYS_HAS_CPU_R10000
>> 679 select SYS_SUPPORTS_64BIT_KERNEL
>> 680 select SYS_SUPPORTS_BIG_ENDIAN
>> 681 select SYS_SUPPORTS_NUMA
>> 682 select SYS_SUPPORTS_SMP
>> 683 select MIPS_L1_CACHE_SHIFT_7
>> 684 help
>> 685 This are the SGI Origin 200, Origin 2000 and Onyx 2 Graphics
>> 686 workstations. To compile a Linux kernel that runs on these, say Y
>> 687 here.
>> 688
>> 689 config SGI_IP28
>> 690 bool "SGI IP28 (Indigo2 R10k)"
>> 691 select FW_ARC
>> 692 select FW_ARC64
>> 693 select ARCH_MIGHT_HAVE_PC_SERIO
>> 694 select BOOT_ELF64
>> 695 select CEVT_R4K
>> 696 select CSRC_R4K
>> 697 select DEFAULT_SGI_PARTITION
>> 698 select DMA_NONCOHERENT
>> 699 select GENERIC_ISA_DMA_SUPPORT_BROKEN
>> 700 select IRQ_MIPS_CPU
>> 701 select HW_HAS_EISA
>> 702 select I8253
>> 703 select I8259
>> 704 select SGI_HAS_I8042
>> 705 select SGI_HAS_INDYDOG
>> 706 select SGI_HAS_HAL2
>> 707 select SGI_HAS_SEEQ
>> 708 select SGI_HAS_WD93
>> 709 select SGI_HAS_ZILOG
>> 710 select SWAP_IO_SPACE
>> 711 select SYS_HAS_CPU_R10000
>> 712 #
>> 713 # Disable EARLY_PRINTK for now since it leads to overwritten prom
>> 714 # memory during early boot on some machines.
>> 715 #
>> 716 # See http://www.linux-mips.org/cgi-bin/mesg.cgi?a=linux-mips&i=20091119164009.GA15038%40deprecation.cyrius.com
>> 717 # for a more details discussion
>> 718 #
>> 719 # select SYS_HAS_EARLY_PRINTK
>> 720 select SYS_SUPPORTS_64BIT_KERNEL
>> 721 select SYS_SUPPORTS_BIG_ENDIAN
>> 722 select MIPS_L1_CACHE_SHIFT_7
>> 723 help
>> 724 This is the SGI Indigo2 with R10000 processor. To compile a Linux
>> 725 kernel that runs on these, say Y here.
>> 726
>> 727 config SGI_IP32
>> 728 bool "SGI IP32 (O2)"
>> 729 select ARCH_HAS_PHYS_TO_DMA
>> 730 select FW_ARC
>> 731 select FW_ARC32
>> 732 select BOOT_ELF32
>> 733 select CEVT_R4K
>> 734 select CSRC_R4K
>> 735 select DMA_NONCOHERENT
>> 736 select HW_HAS_PCI
>> 737 select IRQ_MIPS_CPU
>> 738 select R5000_CPU_SCACHE
>> 739 select RM7000_CPU_SCACHE
>> 740 select SYS_HAS_CPU_R5000
>> 741 select SYS_HAS_CPU_R10000 if BROKEN
>> 742 select SYS_HAS_CPU_RM7000
>> 743 select SYS_HAS_CPU_NEVADA
>> 744 select SYS_SUPPORTS_64BIT_KERNEL
>> 745 select SYS_SUPPORTS_BIG_ENDIAN
>> 746 help
>> 747 If you want this kernel to run on SGI O2 workstation, say Y here.
>> 748
>> 749 config SIBYTE_CRHINE
>> 750 bool "Sibyte BCM91120C-CRhine"
>> 751 select BOOT_ELF32
>> 752 select SIBYTE_BCM1120
>> 753 select SWAP_IO_SPACE
>> 754 select SYS_HAS_CPU_SB1
>> 755 select SYS_SUPPORTS_BIG_ENDIAN
>> 756 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 757
>> 758 config SIBYTE_CARMEL
>> 759 bool "Sibyte BCM91120x-Carmel"
>> 760 select BOOT_ELF32
>> 761 select SIBYTE_BCM1120
>> 762 select SWAP_IO_SPACE
>> 763 select SYS_HAS_CPU_SB1
>> 764 select SYS_SUPPORTS_BIG_ENDIAN
>> 765 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 766
>> 767 config SIBYTE_CRHONE
>> 768 bool "Sibyte BCM91125C-CRhone"
>> 769 select BOOT_ELF32
>> 770 select SIBYTE_BCM1125
>> 771 select SWAP_IO_SPACE
>> 772 select SYS_HAS_CPU_SB1
>> 773 select SYS_SUPPORTS_BIG_ENDIAN
>> 774 select SYS_SUPPORTS_HIGHMEM
>> 775 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 776
>> 777 config SIBYTE_RHONE
>> 778 bool "Sibyte BCM91125E-Rhone"
>> 779 select BOOT_ELF32
>> 780 select SIBYTE_BCM1125H
>> 781 select SWAP_IO_SPACE
>> 782 select SYS_HAS_CPU_SB1
>> 783 select SYS_SUPPORTS_BIG_ENDIAN
>> 784 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 785
>> 786 config SIBYTE_SWARM
>> 787 bool "Sibyte BCM91250A-SWARM"
>> 788 select BOOT_ELF32
>> 789 select HAVE_PATA_PLATFORM
>> 790 select SIBYTE_SB1250
>> 791 select SWAP_IO_SPACE
>> 792 select SYS_HAS_CPU_SB1
>> 793 select SYS_SUPPORTS_BIG_ENDIAN
>> 794 select SYS_SUPPORTS_HIGHMEM
>> 795 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 796 select ZONE_DMA32 if 64BIT
>> 797 select SWIOTLB if ARCH_DMA_ADDR_T_64BIT && PCI
>> 798
>> 799 config SIBYTE_LITTLESUR
>> 800 bool "Sibyte BCM91250C2-LittleSur"
>> 801 select BOOT_ELF32
>> 802 select HAVE_PATA_PLATFORM
>> 803 select SIBYTE_SB1250
>> 804 select SWAP_IO_SPACE
>> 805 select SYS_HAS_CPU_SB1
>> 806 select SYS_SUPPORTS_BIG_ENDIAN
>> 807 select SYS_SUPPORTS_HIGHMEM
>> 808 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 809
>> 810 config SIBYTE_SENTOSA
>> 811 bool "Sibyte BCM91250E-Sentosa"
>> 812 select BOOT_ELF32
>> 813 select SIBYTE_SB1250
>> 814 select SWAP_IO_SPACE
>> 815 select SYS_HAS_CPU_SB1
>> 816 select SYS_SUPPORTS_BIG_ENDIAN
>> 817 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 818 select SWIOTLB if ARCH_DMA_ADDR_T_64BIT && PCI
>> 819
>> 820 config SIBYTE_BIGSUR
>> 821 bool "Sibyte BCM91480B-BigSur"
>> 822 select BOOT_ELF32
>> 823 select NR_CPUS_DEFAULT_4
>> 824 select SIBYTE_BCM1x80
>> 825 select SWAP_IO_SPACE
>> 826 select SYS_HAS_CPU_SB1
>> 827 select SYS_SUPPORTS_BIG_ENDIAN
>> 828 select SYS_SUPPORTS_HIGHMEM
>> 829 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 830 select ZONE_DMA32 if 64BIT
>> 831 select SWIOTLB if ARCH_DMA_ADDR_T_64BIT && PCI
>> 832
>> 833 config SNI_RM
>> 834 bool "SNI RM200/300/400"
>> 835 select FW_ARC if CPU_LITTLE_ENDIAN
>> 836 select FW_ARC32 if CPU_LITTLE_ENDIAN
>> 837 select FW_SNIPROM if CPU_BIG_ENDIAN
>> 838 select ARCH_MAY_HAVE_PC_FDC
>> 839 select ARCH_MIGHT_HAVE_PC_PARPORT
>> 840 select ARCH_MIGHT_HAVE_PC_SERIO
>> 841 select BOOT_ELF32
>> 842 select CEVT_R4K
>> 843 select CSRC_R4K
>> 844 select DEFAULT_SGI_PARTITION if CPU_BIG_ENDIAN
>> 845 select DMA_NONCOHERENT
>> 846 select GENERIC_ISA_DMA
>> 847 select HAVE_PCSPKR_PLATFORM
>> 848 select HW_HAS_EISA
>> 849 select HW_HAS_PCI
>> 850 select IRQ_MIPS_CPU
>> 851 select I8253
>> 852 select I8259
>> 853 select ISA
>> 854 select SWAP_IO_SPACE if CPU_BIG_ENDIAN
>> 855 select SYS_HAS_CPU_R4X00
>> 856 select SYS_HAS_CPU_R5000
>> 857 select SYS_HAS_CPU_R10000
>> 858 select R5000_CPU_SCACHE
>> 859 select SYS_HAS_EARLY_PRINTK
>> 860 select SYS_SUPPORTS_32BIT_KERNEL
>> 861 select SYS_SUPPORTS_64BIT_KERNEL
>> 862 select SYS_SUPPORTS_BIG_ENDIAN
>> 863 select SYS_SUPPORTS_HIGHMEM
>> 864 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 865 help
>> 866 The SNI RM200/300/400 are MIPS-based machines manufactured by
>> 867 Siemens Nixdorf Informationssysteme (SNI), parent company of Pyramid
>> 868 Technology and now in turn merged with Fujitsu. Say Y here to
>> 869 support this machine type.
>> 870
>> 871 config MACH_TX39XX
>> 872 bool "Toshiba TX39 series based machines"
>> 873
>> 874 config MACH_TX49XX
>> 875 bool "Toshiba TX49 series based machines"
>> 876
>> 877 config MIKROTIK_RB532
>> 878 bool "Mikrotik RB532 boards"
>> 879 select CEVT_R4K
>> 880 select CSRC_R4K
>> 881 select DMA_NONCOHERENT
>> 882 select HW_HAS_PCI
>> 883 select IRQ_MIPS_CPU
>> 884 select SYS_HAS_CPU_MIPS32_R1
>> 885 select SYS_SUPPORTS_32BIT_KERNEL
>> 886 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 887 select SWAP_IO_SPACE
>> 888 select BOOT_RAW
>> 889 select GPIOLIB
>> 890 select MIPS_L1_CACHE_SHIFT_4
>> 891 help
>> 892 Support the Mikrotik(tm) RouterBoard 532 series,
>> 893 based on the IDT RC32434 SoC.
>> 894
>> 895 config CAVIUM_OCTEON_SOC
>> 896 bool "Cavium Networks Octeon SoC based boards"
>> 897 select CEVT_R4K
>> 898 select ARCH_HAS_PHYS_TO_DMA
>> 899 select HAS_RAPIDIO
>> 900 select PHYS_ADDR_T_64BIT
>> 901 select SYS_SUPPORTS_64BIT_KERNEL
>> 902 select SYS_SUPPORTS_BIG_ENDIAN
>> 903 select EDAC_SUPPORT
>> 904 select EDAC_ATOMIC_SCRUB
>> 905 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 906 select SYS_SUPPORTS_HOTPLUG_CPU if CPU_BIG_ENDIAN
>> 907 select SYS_HAS_EARLY_PRINTK
>> 908 select SYS_HAS_CPU_CAVIUM_OCTEON
>> 909 select HW_HAS_PCI
>> 910 select ZONE_DMA32
>> 911 select HOLES_IN_ZONE
>> 912 select GPIOLIB
>> 913 select LIBFDT
>> 914 select USE_OF
>> 915 select ARCH_SPARSEMEM_ENABLE
>> 916 select SYS_SUPPORTS_SMP
>> 917 select NR_CPUS_DEFAULT_64
>> 918 select MIPS_NR_CPU_NR_MAP_1024
>> 919 select BUILTIN_DTB
>> 920 select MTD_COMPLEX_MAPPINGS
>> 921 select SWIOTLB
>> 922 select SYS_SUPPORTS_RELOCATABLE
>> 923 help
>> 924 This option supports all of the Octeon reference boards from Cavium
>> 925 Networks. It builds a kernel that dynamically determines the Octeon
>> 926 CPU type and supports all known board reference implementations.
>> 927 Some of the supported boards are:
>> 928 EBT3000
>> 929 EBH3000
>> 930 EBH3100
>> 931 Thunder
>> 932 Kodama
>> 933 Hikari
>> 934 Say Y here for most Octeon reference boards.
>> 935
>> 936 config NLM_XLR_BOARD
>> 937 bool "Netlogic XLR/XLS based systems"
>> 938 select BOOT_ELF32
>> 939 select NLM_COMMON
>> 940 select SYS_HAS_CPU_XLR
>> 941 select SYS_SUPPORTS_SMP
>> 942 select HW_HAS_PCI
>> 943 select SWAP_IO_SPACE
>> 944 select SYS_SUPPORTS_32BIT_KERNEL
>> 945 select SYS_SUPPORTS_64BIT_KERNEL
>> 946 select PHYS_ADDR_T_64BIT
>> 947 select SYS_SUPPORTS_BIG_ENDIAN
>> 948 select SYS_SUPPORTS_HIGHMEM
>> 949 select NR_CPUS_DEFAULT_32
>> 950 select CEVT_R4K
>> 951 select CSRC_R4K
>> 952 select IRQ_MIPS_CPU
>> 953 select ZONE_DMA32 if 64BIT
>> 954 select SYNC_R4K
>> 955 select SYS_HAS_EARLY_PRINTK
>> 956 select SYS_SUPPORTS_ZBOOT
>> 957 select SYS_SUPPORTS_ZBOOT_UART16550
>> 958 help
>> 959 Support for systems based on Netlogic XLR and XLS processors.
>> 960 Say Y here if you have a XLR or XLS based board.
>> 961
>> 962 config NLM_XLP_BOARD
>> 963 bool "Netlogic XLP based systems"
>> 964 select BOOT_ELF32
>> 965 select NLM_COMMON
>> 966 select SYS_HAS_CPU_XLP
>> 967 select SYS_SUPPORTS_SMP
>> 968 select HW_HAS_PCI
>> 969 select SYS_SUPPORTS_32BIT_KERNEL
>> 970 select SYS_SUPPORTS_64BIT_KERNEL
>> 971 select PHYS_ADDR_T_64BIT
>> 972 select GPIOLIB
>> 973 select SYS_SUPPORTS_BIG_ENDIAN
>> 974 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 975 select SYS_SUPPORTS_HIGHMEM
>> 976 select NR_CPUS_DEFAULT_32
>> 977 select CEVT_R4K
>> 978 select CSRC_R4K
>> 979 select IRQ_MIPS_CPU
>> 980 select ZONE_DMA32 if 64BIT
>> 981 select SYNC_R4K
>> 982 select SYS_HAS_EARLY_PRINTK
>> 983 select USE_OF
>> 984 select SYS_SUPPORTS_ZBOOT
>> 985 select SYS_SUPPORTS_ZBOOT_UART16550
>> 986 help
>> 987 This board is based on Netlogic XLP Processor.
>> 988 Say Y here if you have a XLP based board.
>> 989
>> 990 config MIPS_PARAVIRT
>> 991 bool "Para-Virtualized guest system"
>> 992 select CEVT_R4K
>> 993 select CSRC_R4K
>> 994 select SYS_SUPPORTS_64BIT_KERNEL
>> 995 select SYS_SUPPORTS_32BIT_KERNEL
>> 996 select SYS_SUPPORTS_BIG_ENDIAN
>> 997 select SYS_SUPPORTS_SMP
>> 998 select NR_CPUS_DEFAULT_4
>> 999 select SYS_HAS_EARLY_PRINTK
>> 1000 select SYS_HAS_CPU_MIPS32_R2
>> 1001 select SYS_HAS_CPU_MIPS64_R2
>> 1002 select SYS_HAS_CPU_CAVIUM_OCTEON
>> 1003 select HW_HAS_PCI
>> 1004 select SWAP_IO_SPACE
>> 1005 help
>> 1006 This option supports guest running under ????
389 1007
390 config ARCH_SUPPORTS_UPROBES !! 1008 endchoice
391 def_bool y <<
392 1009
393 config ARCH_PROC_KCORE_TEXT !! 1010 source "arch/mips/alchemy/Kconfig"
394 def_bool y !! 1011 source "arch/mips/ath25/Kconfig"
>> 1012 source "arch/mips/ath79/Kconfig"
>> 1013 source "arch/mips/bcm47xx/Kconfig"
>> 1014 source "arch/mips/bcm63xx/Kconfig"
>> 1015 source "arch/mips/bmips/Kconfig"
>> 1016 source "arch/mips/generic/Kconfig"
>> 1017 source "arch/mips/jazz/Kconfig"
>> 1018 source "arch/mips/jz4740/Kconfig"
>> 1019 source "arch/mips/lantiq/Kconfig"
>> 1020 source "arch/mips/lasat/Kconfig"
>> 1021 source "arch/mips/pic32/Kconfig"
>> 1022 source "arch/mips/pistachio/Kconfig"
>> 1023 source "arch/mips/pmcs-msp71xx/Kconfig"
>> 1024 source "arch/mips/ralink/Kconfig"
>> 1025 source "arch/mips/sgi-ip27/Kconfig"
>> 1026 source "arch/mips/sibyte/Kconfig"
>> 1027 source "arch/mips/txx9/Kconfig"
>> 1028 source "arch/mips/vr41xx/Kconfig"
>> 1029 source "arch/mips/cavium-octeon/Kconfig"
>> 1030 source "arch/mips/loongson32/Kconfig"
>> 1031 source "arch/mips/loongson64/Kconfig"
>> 1032 source "arch/mips/netlogic/Kconfig"
>> 1033 source "arch/mips/paravirt/Kconfig"
395 1034
396 config BROKEN_GAS_INST !! 1035 endmenu
397 def_bool !$(as-instr,1:\n.inst 0\n.rep <<
398 1036
399 config BUILTIN_RETURN_ADDRESS_STRIPS_PAC !! 1037 config RWSEM_GENERIC_SPINLOCK
400 bool 1038 bool
401 # Clang's __builtin_return_address() s !! 1039 default y
402 # https://github.com/llvm/llvm-project <<
403 default y if CC_IS_CLANG <<
404 # GCC's __builtin_return_address() str <<
405 # and this was backported to 10.2.0, 9 <<
406 # https://gcc.gnu.org/bugzilla/show_bu <<
407 default y if CC_IS_GCC && (GCC_VERSION <<
408 default y if CC_IS_GCC && (GCC_VERSION <<
409 default y if CC_IS_GCC && (GCC_VERSION <<
410 default y if CC_IS_GCC && (GCC_VERSION <<
411 default n <<
412 <<
413 config KASAN_SHADOW_OFFSET <<
414 hex <<
415 depends on KASAN_GENERIC || KASAN_SW_T <<
416 default 0xdfff800000000000 if (ARM64_V <<
417 default 0xdfffc00000000000 if (ARM64_V <<
418 default 0xdffffe0000000000 if ARM64_VA <<
419 default 0xdfffffc000000000 if ARM64_VA <<
420 default 0xdffffff800000000 if ARM64_VA <<
421 default 0xefff800000000000 if (ARM64_V <<
422 default 0xefffc00000000000 if (ARM64_V <<
423 default 0xeffffe0000000000 if ARM64_VA <<
424 default 0xefffffc000000000 if ARM64_VA <<
425 default 0xeffffff800000000 if ARM64_VA <<
426 default 0xffffffffffffffff <<
427 <<
428 config UNWIND_TABLES <<
429 bool <<
430 <<
431 source "arch/arm64/Kconfig.platforms" <<
432 <<
433 menu "Kernel Features" <<
434 <<
435 menu "ARM errata workarounds via the alternati <<
436 <<
437 config AMPERE_ERRATUM_AC03_CPU_38 <<
438 bool "AmpereOne: AC03_CPU_38: Certain <<
439 default y <<
440 help <<
441 This option adds an alternative code <<
442 errata AC03_CPU_38 and AC04_CPU_10 o <<
443 <<
444 The affected design reports FEAT_HAF <<
445 ID_AA64MMFR1_EL1.HAFDBS, but (V)TCR_ <<
446 as required by the architecture. The <<
447 implementation suffers from an addit <<
448 A/D updates can occur after a PTE ha <<
449 <<
450 The workaround forces KVM to explici <<
451 which avoids enabling unadvertised h <<
452 at stage-2. <<
453 <<
454 If unsure, say Y. <<
455 1040
456 config ARM64_WORKAROUND_CLEAN_CACHE !! 1041 config RWSEM_XCHGADD_ALGORITHM
457 bool 1042 bool
458 1043
459 config ARM64_ERRATUM_826319 !! 1044 config GENERIC_HWEIGHT
460 bool "Cortex-A53: 826319: System might !! 1045 bool
461 default y 1046 default y
462 select ARM64_WORKAROUND_CLEAN_CACHE <<
463 help <<
464 This option adds an alternative code <<
465 erratum 826319 on Cortex-A53 parts u <<
466 AXI master interface and an L2 cache <<
467 <<
468 If a Cortex-A53 uses an AMBA AXI4 AC <<
469 and is unable to accept a certain wr <<
470 not progress on read data presented <<
471 system can deadlock. <<
472 <<
473 The workaround promotes data cache c <<
474 data cache clean-and-invalidate. <<
475 Please note that this does not neces <<
476 as it depends on the alternative fra <<
477 the kernel if an affected CPU is det <<
478 1047
479 If unsure, say Y. !! 1048 config GENERIC_CALIBRATE_DELAY
480 !! 1049 bool
481 config ARM64_ERRATUM_827319 <<
482 bool "Cortex-A53: 827319: Data cache c <<
483 default y 1050 default y
484 select ARM64_WORKAROUND_CLEAN_CACHE <<
485 help <<
486 This option adds an alternative code <<
487 erratum 827319 on Cortex-A53 parts u <<
488 master interface and an L2 cache. <<
489 <<
490 Under certain conditions this erratu <<
491 to occur at the same time as another <<
492 on the AMBA 5 CHI interface, which c <<
493 interconnect reorders the two transa <<
494 <<
495 The workaround promotes data cache c <<
496 data cache clean-and-invalidate. <<
497 Please note that this does not neces <<
498 as it depends on the alternative fra <<
499 the kernel if an affected CPU is det <<
500 1051
501 If unsure, say Y. !! 1052 config SCHED_OMIT_FRAME_POINTER
502 !! 1053 bool
503 config ARM64_ERRATUM_824069 <<
504 bool "Cortex-A53: 824069: Cache line m <<
505 default y 1054 default y
506 select ARM64_WORKAROUND_CLEAN_CACHE <<
507 help <<
508 This option adds an alternative code <<
509 erratum 824069 on Cortex-A53 parts u <<
510 to a coherent interconnect. <<
511 <<
512 If a Cortex-A53 processor is executi <<
513 write instruction at the same time a <<
514 cluster is executing a cache mainten <<
515 address, then this erratum might cau <<
516 incorrectly marked as dirty. <<
517 <<
518 The workaround promotes data cache c <<
519 data cache clean-and-invalidate. <<
520 Please note that this option does no <<
521 workaround, as it depends on the alt <<
522 only patch the kernel if an affected <<
523 1055
524 If unsure, say Y. !! 1056 #
>> 1057 # Select some configuration options automatically based on user selections.
>> 1058 #
>> 1059 config FW_ARC
>> 1060 bool
525 1061
526 config ARM64_ERRATUM_819472 !! 1062 config ARCH_MAY_HAVE_PC_FDC
527 bool "Cortex-A53: 819472: Store exclus !! 1063 bool
528 default y <<
529 select ARM64_WORKAROUND_CLEAN_CACHE <<
530 help <<
531 This option adds an alternative code <<
532 erratum 819472 on Cortex-A53 parts u <<
533 present when it is connected to a co <<
534 <<
535 If the processor is executing a load <<
536 the same time as a processor in anot <<
537 maintenance operation to the same ad <<
538 cause data corruption. <<
539 <<
540 The workaround promotes data cache c <<
541 data cache clean-and-invalidate. <<
542 Please note that this does not neces <<
543 as it depends on the alternative fra <<
544 the kernel if an affected CPU is det <<
545 1064
546 If unsure, say Y. !! 1065 config BOOT_RAW
>> 1066 bool
547 1067
548 config ARM64_ERRATUM_832075 !! 1068 config CEVT_BCM1480
549 bool "Cortex-A57: 832075: possible dea !! 1069 bool
550 default y <<
551 help <<
552 This option adds an alternative code <<
553 erratum 832075 on Cortex-A57 parts u <<
554 1070
555 Affected Cortex-A57 parts might dead !! 1071 config CEVT_DS1287
556 instructions to Write-Back memory ar !! 1072 bool
557 1073
558 The workaround is to promote device !! 1074 config CEVT_GT641XX
559 semantics. !! 1075 bool
560 Please note that this does not neces <<
561 as it depends on the alternative fra <<
562 the kernel if an affected CPU is det <<
563 1076
564 If unsure, say Y. !! 1077 config CEVT_R4K
>> 1078 bool
565 1079
566 config ARM64_ERRATUM_834220 !! 1080 config CEVT_SB1250
567 bool "Cortex-A57: 834220: Stage 2 tran !! 1081 bool
568 depends on KVM <<
569 help <<
570 This option adds an alternative code <<
571 erratum 834220 on Cortex-A57 parts u <<
572 <<
573 Affected Cortex-A57 parts might repo <<
574 fault as the result of a Stage 1 fau <<
575 page boundary when there is a permis <<
576 alignment fault at Stage 1 and a tra <<
577 <<
578 The workaround is to verify that the <<
579 doesn't generate a fault before hand <<
580 Please note that this does not neces <<
581 as it depends on the alternative fra <<
582 the kernel if an affected CPU is det <<
583 1082
584 If unsure, say N. !! 1083 config CEVT_TXX9
>> 1084 bool
585 1085
586 config ARM64_ERRATUM_1742098 !! 1086 config CSRC_BCM1480
587 bool "Cortex-A57/A72: 1742098: ELR rec !! 1087 bool
588 depends on COMPAT <<
589 default y <<
590 help <<
591 This option removes the AES hwcap fo <<
592 workaround erratum 1742098 on Cortex <<
593 <<
594 Affected parts may corrupt the AES s <<
595 taken between a pair of AES instruct <<
596 are only present if the cryptography <<
597 All software should have a fallback <<
598 that don't implement the cryptograph <<
599 1088
600 If unsure, say Y. !! 1089 config CSRC_IOASIC
>> 1090 bool
601 1091
602 config ARM64_ERRATUM_845719 !! 1092 config CSRC_R4K
603 bool "Cortex-A53: 845719: a load might !! 1093 bool
604 depends on COMPAT <<
605 default y <<
606 help <<
607 This option adds an alternative code <<
608 erratum 845719 on Cortex-A53 parts u <<
609 <<
610 When running a compat (AArch32) user <<
611 part, a load at EL0 from a virtual a <<
612 bits of the virtual address used by <<
613 might return incorrect data. <<
614 <<
615 The workaround is to write the conte <<
616 return to a 32-bit task. <<
617 Please note that this does not neces <<
618 as it depends on the alternative fra <<
619 the kernel if an affected CPU is det <<
620 1094
621 If unsure, say Y. !! 1095 config CSRC_SB1250
>> 1096 bool
622 1097
623 config ARM64_ERRATUM_843419 !! 1098 config MIPS_CLOCK_VSYSCALL
624 bool "Cortex-A53: 843419: A load or st !! 1099 def_bool CSRC_R4K || CLKSRC_MIPS_GIC
625 default y <<
626 help <<
627 This option links the kernel with '- <<
628 enables PLT support to replace certa <<
629 cause subsequent memory accesses to <<
630 Cortex-A53 parts up to r0p4. <<
631 1100
632 If unsure, say Y. !! 1101 config GPIO_TXX9
>> 1102 select GPIOLIB
>> 1103 bool
633 1104
634 config ARM64_LD_HAS_FIX_ERRATUM_843419 !! 1105 config FW_CFE
635 def_bool $(ld-option,--fix-cortex-a53- !! 1106 bool
636 1107
637 config ARM64_ERRATUM_1024718 !! 1108 config ARCH_SUPPORTS_UPROBES
638 bool "Cortex-A55: 1024718: Update of D !! 1109 bool
639 default y <<
640 help <<
641 This option adds a workaround for AR <<
642 1110
643 Affected Cortex-A55 cores (all revis !! 1111 config DMA_MAYBE_COHERENT
644 update of the hardware dirty bit whe !! 1112 select ARCH_HAS_DMA_COHERENCE_H
645 without a break-before-make. The wor !! 1113 select DMA_NONCOHERENT
646 of hardware DBM locally on the affec !! 1114 bool
647 this erratum will continue to use th <<
648 1115
649 If unsure, say Y. !! 1116 config DMA_PERDEV_COHERENT
>> 1117 bool
>> 1118 select DMA_NONCOHERENT
650 1119
651 config ARM64_ERRATUM_1418040 !! 1120 config DMA_NONCOHERENT
652 bool "Cortex-A76/Neoverse-N1: MRC read !! 1121 bool
653 default y !! 1122 select ARCH_HAS_DMA_MMAP_PGPROT
654 depends on COMPAT !! 1123 select ARCH_HAS_SYNC_DMA_FOR_DEVICE
655 help !! 1124 select ARCH_HAS_SYNC_DMA_FOR_CPU
656 This option adds a workaround for AR !! 1125 select NEED_DMA_MAP_STATE
657 errata 1188873 and 1418040. !! 1126 select ARCH_HAS_DMA_COHERENT_TO_PFN
>> 1127 select DMA_NONCOHERENT_CACHE_SYNC
658 1128
659 Affected Cortex-A76/Neoverse-N1 core !! 1129 config SYS_HAS_EARLY_PRINTK
660 cause register corruption when acces !! 1130 bool
661 from AArch32 userspace. <<
662 1131
663 If unsure, say Y. !! 1132 config SYS_SUPPORTS_HOTPLUG_CPU
>> 1133 bool
664 1134
665 config ARM64_WORKAROUND_SPECULATIVE_AT !! 1135 config MIPS_BONITO64
666 bool 1136 bool
667 1137
668 config ARM64_ERRATUM_1165522 !! 1138 config MIPS_MSC
669 bool "Cortex-A76: 1165522: Speculative !! 1139 bool
670 default y <<
671 select ARM64_WORKAROUND_SPECULATIVE_AT <<
672 help <<
673 This option adds a workaround for AR <<
674 1140
675 Affected Cortex-A76 cores (r0p0, r1p !! 1141 config MIPS_NILE4
676 corrupted TLBs by speculating an AT !! 1142 bool
677 context switch. <<
678 1143
679 If unsure, say Y. !! 1144 config SYNC_R4K
>> 1145 bool
680 1146
681 config ARM64_ERRATUM_1319367 !! 1147 config MIPS_MACHINE
682 bool "Cortex-A57/A72: 1319537: Specula !! 1148 def_bool n
683 default y <<
684 select ARM64_WORKAROUND_SPECULATIVE_AT <<
685 help <<
686 This option adds work arounds for AR <<
687 and A72 erratum 1319367 <<
688 1149
689 Cortex-A57 and A72 cores could end-u !! 1150 config NO_IOPORT_MAP
690 speculating an AT instruction during !! 1151 def_bool n
691 1152
692 If unsure, say Y. !! 1153 config GENERIC_CSUM
>> 1154 bool
>> 1155 default y if !CPU_HAS_LOAD_STORE_LR
693 1156
694 config ARM64_ERRATUM_1530923 !! 1157 config GENERIC_ISA_DMA
695 bool "Cortex-A55: 1530923: Speculative !! 1158 bool
696 default y !! 1159 select ZONE_DMA if GENERIC_ISA_DMA_SUPPORT_BROKEN=n
697 select ARM64_WORKAROUND_SPECULATIVE_AT !! 1160 select ISA_DMA_API
698 help <<
699 This option adds a workaround for AR <<
700 1161
701 Affected Cortex-A55 cores (r0p0, r0p !! 1162 config GENERIC_ISA_DMA_SUPPORT_BROKEN
702 corrupted TLBs by speculating an AT !! 1163 bool
703 context switch. !! 1164 select GENERIC_ISA_DMA
704 1165
705 If unsure, say Y. !! 1166 config ISA_DMA_API
>> 1167 bool
706 1168
707 config ARM64_WORKAROUND_REPEAT_TLBI !! 1169 config HOLES_IN_ZONE
708 bool 1170 bool
709 1171
710 config ARM64_ERRATUM_2441007 !! 1172 config SYS_SUPPORTS_RELOCATABLE
711 bool "Cortex-A55: Completion of affect !! 1173 bool
712 select ARM64_WORKAROUND_REPEAT_TLBI <<
713 help 1174 help
714 This option adds a workaround for AR !! 1175 Selected if the platform supports relocating the kernel.
715 !! 1176 The platform must provide plat_get_fdt() if it selects CONFIG_USE_OF
716 Under very rare circumstances, affec !! 1177 to allow access to command line and entropy sources.
717 may not handle a race between a brea <<
718 CPU, and another CPU accessing the s <<
719 store to a page that has been unmapp <<
720 <<
721 Work around this by adding the affec <<
722 TLB sequences to be done twice. <<
723 1178
724 If unsure, say N. !! 1179 config MIPS_CBPF_JIT
>> 1180 def_bool y
>> 1181 depends on BPF_JIT && HAVE_CBPF_JIT
725 1182
726 config ARM64_ERRATUM_1286807 !! 1183 config MIPS_EBPF_JIT
727 bool "Cortex-A76: Modification of the !! 1184 def_bool y
728 select ARM64_WORKAROUND_REPEAT_TLBI !! 1185 depends on BPF_JIT && HAVE_EBPF_JIT
729 help <<
730 This option adds a workaround for AR <<
731 <<
732 On the affected Cortex-A76 cores (r0 <<
733 address for a cacheable mapping of a <<
734 accessed by a core while another cor <<
735 address to a new physical page using <<
736 break-before-make sequence, then und <<
737 TLBI+DSB completes before a read usi <<
738 invalidated has been observed by oth <<
739 workaround repeats the TLBI+DSB oper <<
740 1186
741 If unsure, say N. <<
742 1187
743 config ARM64_ERRATUM_1463225 !! 1188 #
744 bool "Cortex-A76: Software Step might !! 1189 # Endianness selection. Sufficiently obscure so many users don't know what to
745 default y !! 1190 # answer,so we try hard to limit the available choices. Also the use of a
>> 1191 # choice statement should be more obvious to the user.
>> 1192 #
>> 1193 choice
>> 1194 prompt "Endianness selection"
746 help 1195 help
747 This option adds a workaround for Ar !! 1196 Some MIPS machines can be configured for either little or big endian
>> 1197 byte order. These modes require different kernels and a different
>> 1198 Linux distribution. In general there is one preferred byteorder for a
>> 1199 particular system but some systems are just as commonly used in the
>> 1200 one or the other endianness.
748 1201
749 On the affected Cortex-A76 cores (r0 !! 1202 config CPU_BIG_ENDIAN
750 of a system call instruction (SVC) c !! 1203 bool "Big endian"
751 subsequent interrupts when software !! 1204 depends on SYS_SUPPORTS_BIG_ENDIAN
752 exception handler of the system call <<
753 is enabled or VHE is in use. <<
754 1205
755 Work around the erratum by triggerin !! 1206 config CPU_LITTLE_ENDIAN
756 when handling a system call from a t !! 1207 bool "Little endian"
757 in a VHE configuration of the kernel !! 1208 depends on SYS_SUPPORTS_LITTLE_ENDIAN
758 1209
759 If unsure, say Y. !! 1210 endchoice
760 1211
761 config ARM64_ERRATUM_1542419 !! 1212 config EXPORT_UASM
762 bool "Neoverse-N1: workaround mis-orde !! 1213 bool
763 help <<
764 This option adds a workaround for AR <<
765 1542419. <<
766 1214
767 Affected Neoverse-N1 cores could exe !! 1215 config SYS_SUPPORTS_APM_EMULATION
768 modified by another CPU. The workaro !! 1216 bool
769 counterpart. <<
770 1217
771 Workaround the issue by hiding the D !! 1218 config SYS_SUPPORTS_BIG_ENDIAN
772 forces user-space to perform cache m !! 1219 bool
773 1220
774 If unsure, say N. !! 1221 config SYS_SUPPORTS_LITTLE_ENDIAN
>> 1222 bool
775 1223
776 config ARM64_ERRATUM_1508412 !! 1224 config SYS_SUPPORTS_HUGETLBFS
777 bool "Cortex-A77: 1508412: workaround !! 1225 bool
>> 1226 depends on CPU_SUPPORTS_HUGEPAGES && 64BIT
778 default y 1227 default y
779 help <<
780 This option adds a workaround for Ar <<
781 1228
782 Affected Cortex-A77 cores (r0p0, r1p !! 1229 config MIPS_HUGE_TLB_SUPPORT
783 of a store-exclusive or read of PAR_ !! 1230 def_bool HUGETLB_PAGE || TRANSPARENT_HUGEPAGE
784 non-cacheable memory attributes. The <<
785 counterpart. <<
786 1231
787 KVM guests must also have the workar !! 1232 config IRQ_CPU_RM7K
788 deadlock the system. !! 1233 bool
789 1234
790 Work around the issue by inserting D !! 1235 config IRQ_MSP_SLP
791 register reads and warning KVM users !! 1236 bool
792 to prevent a speculative PAR_EL1 rea <<
793 1237
794 If unsure, say Y. !! 1238 config IRQ_MSP_CIC
>> 1239 bool
795 1240
796 config ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MO !! 1241 config IRQ_TXX9
797 bool 1242 bool
798 1243
799 config ARM64_ERRATUM_2051678 !! 1244 config IRQ_GT641XX
800 bool "Cortex-A510: 2051678: disable Ha !! 1245 bool
801 default y <<
802 help <<
803 This options adds the workaround for <<
804 Affected Cortex-A510 might not respe <<
805 hardware update of the page table's <<
806 is to not enable the feature on affe <<
807 1246
808 If unsure, say Y. !! 1247 config PCI_GT64XXX_PCI0
>> 1248 bool
809 1249
810 config ARM64_ERRATUM_2077057 !! 1250 config NO_EXCEPT_FILL
811 bool "Cortex-A510: 2077057: workaround !! 1251 bool
812 default y <<
813 help <<
814 This option adds the workaround for <<
815 Affected Cortex-A510 may corrupt SPS <<
816 expected, but a Pointer Authenticati <<
817 erratum causes SPSR_EL1 to be copied <<
818 EL1 to cause a return to EL2 with a <<
819 1252
820 This can only happen when EL2 is ste !! 1253 config SOC_EMMA2RH
>> 1254 bool
>> 1255 select CEVT_R4K
>> 1256 select CSRC_R4K
>> 1257 select DMA_NONCOHERENT
>> 1258 select IRQ_MIPS_CPU
>> 1259 select SWAP_IO_SPACE
>> 1260 select SYS_HAS_CPU_R5500
>> 1261 select SYS_SUPPORTS_32BIT_KERNEL
>> 1262 select SYS_SUPPORTS_64BIT_KERNEL
>> 1263 select SYS_SUPPORTS_BIG_ENDIAN
821 1264
822 When these conditions occur, the SPS !! 1265 config SOC_PNX833X
823 previous guest entry, and can be res !! 1266 bool
>> 1267 select CEVT_R4K
>> 1268 select CSRC_R4K
>> 1269 select IRQ_MIPS_CPU
>> 1270 select DMA_NONCOHERENT
>> 1271 select SYS_HAS_CPU_MIPS32_R2
>> 1272 select SYS_SUPPORTS_32BIT_KERNEL
>> 1273 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 1274 select SYS_SUPPORTS_BIG_ENDIAN
>> 1275 select SYS_SUPPORTS_MIPS16
>> 1276 select CPU_MIPSR2_IRQ_VI
824 1277
825 If unsure, say Y. !! 1278 config SOC_PNX8335
>> 1279 bool
>> 1280 select SOC_PNX833X
826 1281
827 config ARM64_ERRATUM_2658417 !! 1282 config MIPS_SPRAM
828 bool "Cortex-A510: 2658417: remove BF1 !! 1283 bool
829 default y <<
830 help <<
831 This option adds the workaround for <<
832 Affected Cortex-A510 (r0p0 to r1p1) <<
833 BFMMLA or VMMLA instructions in rare <<
834 A510 CPUs are using shared neon hard <<
835 discoverable by the kernel, hide the <<
836 user-space should not be using these <<
837 1284
838 If unsure, say Y. !! 1285 config SWAP_IO_SPACE
>> 1286 bool
839 1287
840 config ARM64_ERRATUM_2119858 !! 1288 config SGI_HAS_INDYDOG
841 bool "Cortex-A710/X2: 2119858: workaro !! 1289 bool
842 default y <<
843 depends on CORESIGHT_TRBE <<
844 select ARM64_WORKAROUND_TRBE_OVERWRITE <<
845 help <<
846 This option adds the workaround for <<
847 1290
848 Affected Cortex-A710/X2 cores could !! 1291 config SGI_HAS_HAL2
849 data at the base of the buffer (poin !! 1292 bool
850 the event of a WRAP event. <<
851 1293
852 Work around the issue by always maki !! 1294 config SGI_HAS_SEEQ
853 256 bytes before enabling the buffer !! 1295 bool
854 the buffer with ETM ignore packets u <<
855 1296
856 If unsure, say Y. !! 1297 config SGI_HAS_WD93
>> 1298 bool
857 1299
858 config ARM64_ERRATUM_2139208 !! 1300 config SGI_HAS_ZILOG
859 bool "Neoverse-N2: 2139208: workaround !! 1301 bool
860 default y <<
861 depends on CORESIGHT_TRBE <<
862 select ARM64_WORKAROUND_TRBE_OVERWRITE <<
863 help <<
864 This option adds the workaround for <<
865 1302
866 Affected Neoverse-N2 cores could ove !! 1303 config SGI_HAS_I8042
867 data at the base of the buffer (poin !! 1304 bool
868 the event of a WRAP event. <<
869 1305
870 Work around the issue by always maki !! 1306 config DEFAULT_SGI_PARTITION
871 256 bytes before enabling the buffer !! 1307 bool
872 the buffer with ETM ignore packets u <<
873 1308
874 If unsure, say Y. !! 1309 config FW_ARC32
>> 1310 bool
875 1311
876 config ARM64_WORKAROUND_TSB_FLUSH_FAILURE !! 1312 config FW_SNIPROM
877 bool 1313 bool
878 1314
879 config ARM64_ERRATUM_2054223 !! 1315 config BOOT_ELF32
880 bool "Cortex-A710: 2054223: workaround !! 1316 bool
881 default y <<
882 select ARM64_WORKAROUND_TSB_FLUSH_FAIL <<
883 help <<
884 Enable workaround for ARM Cortex-A71 <<
885 1317
886 Affected cores may fail to flush the !! 1318 config MIPS_L1_CACHE_SHIFT_4
887 the PE is in trace prohibited state. !! 1319 bool
888 of the trace cached. <<
889 1320
890 Workaround is to issue two TSB conse !! 1321 config MIPS_L1_CACHE_SHIFT_5
>> 1322 bool
891 1323
892 If unsure, say Y. !! 1324 config MIPS_L1_CACHE_SHIFT_6
>> 1325 bool
893 1326
894 config ARM64_ERRATUM_2067961 !! 1327 config MIPS_L1_CACHE_SHIFT_7
895 bool "Neoverse-N2: 2067961: workaround !! 1328 bool
896 default y <<
897 select ARM64_WORKAROUND_TSB_FLUSH_FAIL <<
898 help <<
899 Enable workaround for ARM Neoverse-N <<
900 1329
901 Affected cores may fail to flush the !! 1330 config MIPS_L1_CACHE_SHIFT
902 the PE is in trace prohibited state. !! 1331 int
903 of the trace cached. !! 1332 default "7" if MIPS_L1_CACHE_SHIFT_7
>> 1333 default "6" if MIPS_L1_CACHE_SHIFT_6
>> 1334 default "5" if MIPS_L1_CACHE_SHIFT_5
>> 1335 default "4" if MIPS_L1_CACHE_SHIFT_4
>> 1336 default "5"
904 1337
905 Workaround is to issue two TSB conse !! 1338 config HAVE_STD_PC_SERIAL_PORT
>> 1339 bool
906 1340
907 If unsure, say Y. !! 1341 config ARC_CONSOLE
>> 1342 bool "ARC console support"
>> 1343 depends on SGI_IP22 || SGI_IP28 || (SNI_RM && CPU_LITTLE_ENDIAN)
908 1344
909 config ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANG !! 1345 config ARC_MEMORY
910 bool 1346 bool
911 !! 1347 depends on MACH_JAZZ || SNI_RM || SGI_IP32
912 config ARM64_ERRATUM_2253138 <<
913 bool "Neoverse-N2: 2253138: workaround <<
914 depends on CORESIGHT_TRBE <<
915 default y 1348 default y
916 select ARM64_WORKAROUND_TRBE_WRITE_OUT <<
917 help <<
918 This option adds the workaround for <<
919 1349
920 Affected Neoverse-N2 cores might wri !! 1350 config ARC_PROMLIB
921 for TRBE. Under some conditions, the !! 1351 bool
922 virtually addressed page following t !! 1352 depends on MACH_JAZZ || SNI_RM || SGI_IP22 || SGI_IP28 || SGI_IP32
923 (i.e., the TRBLIMITR_EL1.LIMIT), ins <<
924 <<
925 Work around this in the driver by al <<
926 page beyond the TRBLIMITR_EL1.LIMIT, <<
927 <<
928 If unsure, say Y. <<
929 <<
930 config ARM64_ERRATUM_2224489 <<
931 bool "Cortex-A710/X2: 2224489: workaro <<
932 depends on CORESIGHT_TRBE <<
933 default y 1353 default y
934 select ARM64_WORKAROUND_TRBE_WRITE_OUT <<
935 help <<
936 This option adds the workaround for <<
937 <<
938 Affected Cortex-A710/X2 cores might <<
939 for TRBE. Under some conditions, the <<
940 virtually addressed page following t <<
941 (i.e., the TRBLIMITR_EL1.LIMIT), ins <<
942 <<
943 Work around this in the driver by al <<
944 page beyond the TRBLIMITR_EL1.LIMIT, <<
945 1354
946 If unsure, say Y. !! 1355 config FW_ARC64
>> 1356 bool
947 1357
948 config ARM64_ERRATUM_2441009 !! 1358 config BOOT_ELF64
949 bool "Cortex-A510: Completion of affec !! 1359 bool
950 select ARM64_WORKAROUND_REPEAT_TLBI <<
951 help <<
952 This option adds a workaround for AR <<
953 <<
954 Under very rare circumstances, affec <<
955 may not handle a race between a brea <<
956 CPU, and another CPU accessing the s <<
957 store to a page that has been unmapp <<
958 1360
959 Work around this by adding the affec !! 1361 menu "CPU selection"
960 TLB sequences to be done twice. <<
961 1362
962 If unsure, say N. !! 1363 choice
>> 1364 prompt "CPU type"
>> 1365 default CPU_R4X00
963 1366
964 config ARM64_ERRATUM_2064142 !! 1367 config CPU_LOONGSON3
965 bool "Cortex-A510: 2064142: workaround !! 1368 bool "Loongson 3 CPU"
966 depends on CORESIGHT_TRBE !! 1369 depends on SYS_HAS_CPU_LOONGSON3
967 default y !! 1370 select ARCH_HAS_PHYS_TO_DMA
>> 1371 select CPU_SUPPORTS_64BIT_KERNEL
>> 1372 select CPU_SUPPORTS_HIGHMEM
>> 1373 select CPU_SUPPORTS_HUGEPAGES
>> 1374 select CPU_HAS_LOAD_STORE_LR
>> 1375 select WEAK_ORDERING
>> 1376 select WEAK_REORDERING_BEYOND_LLSC
>> 1377 select MIPS_PGD_C0_CONTEXT
>> 1378 select MIPS_L1_CACHE_SHIFT_6
>> 1379 select GPIOLIB
>> 1380 select SWIOTLB
968 help 1381 help
969 This option adds the workaround for !! 1382 The Loongson 3 processor implements the MIPS64R2 instruction
970 !! 1383 set with many extensions.
971 Affected Cortex-A510 core might fail <<
972 TRBE has been disabled. Under some c <<
973 writes into TRBE registers TRBLIMITR <<
974 and TRBTRG_EL1 will be ignored and w <<
975 1384
976 Work around this in the driver by ex !! 1385 config LOONGSON3_ENHANCEMENT
977 is stopped and before performing a s !! 1386 bool "New Loongson 3 CPU Enhancements"
978 registers. !! 1387 default n
>> 1388 select CPU_MIPSR2
>> 1389 select CPU_HAS_PREFETCH
>> 1390 depends on CPU_LOONGSON3
>> 1391 help
>> 1392 New Loongson 3 CPU (since Loongson-3A R2, as opposed to Loongson-3A
>> 1393 R1, Loongson-3B R1 and Loongson-3B R2) has many enhancements, such as
>> 1394 FTLB, L1-VCache, EI/DI/Wait/Prefetch instruction, DSP/DSPv2 ASE, User
>> 1395 Local register, Read-Inhibit/Execute-Inhibit, SFB (Store Fill Buffer),
>> 1396 Fast TLB refill support, etc.
>> 1397
>> 1398 This option enable those enhancements which are not probed at run
>> 1399 time. If you want a generic kernel to run on all Loongson 3 machines,
>> 1400 please say 'N' here. If you want a high-performance kernel to run on
>> 1401 new Loongson 3 machines only, please say 'Y' here.
>> 1402
>> 1403 config CPU_LOONGSON2E
>> 1404 bool "Loongson 2E"
>> 1405 depends on SYS_HAS_CPU_LOONGSON2E
>> 1406 select CPU_LOONGSON2
>> 1407 help
>> 1408 The Loongson 2E processor implements the MIPS III instruction set
>> 1409 with many extensions.
>> 1410
>> 1411 It has an internal FPGA northbridge, which is compatible to
>> 1412 bonito64.
>> 1413
>> 1414 config CPU_LOONGSON2F
>> 1415 bool "Loongson 2F"
>> 1416 depends on SYS_HAS_CPU_LOONGSON2F
>> 1417 select CPU_LOONGSON2
>> 1418 select GPIOLIB
>> 1419 help
>> 1420 The Loongson 2F processor implements the MIPS III instruction set
>> 1421 with many extensions.
>> 1422
>> 1423 Loongson2F have built-in DDR2 and PCIX controller. The PCIX controller
>> 1424 have a similar programming interface with FPGA northbridge used in
>> 1425 Loongson2E.
>> 1426
>> 1427 config CPU_LOONGSON1B
>> 1428 bool "Loongson 1B"
>> 1429 depends on SYS_HAS_CPU_LOONGSON1B
>> 1430 select CPU_LOONGSON1
>> 1431 select LEDS_GPIO_REGISTER
>> 1432 help
>> 1433 The Loongson 1B is a 32-bit SoC, which implements the MIPS32
>> 1434 Release 1 instruction set and part of the MIPS32 Release 2
>> 1435 instruction set.
>> 1436
>> 1437 config CPU_LOONGSON1C
>> 1438 bool "Loongson 1C"
>> 1439 depends on SYS_HAS_CPU_LOONGSON1C
>> 1440 select CPU_LOONGSON1
>> 1441 select LEDS_GPIO_REGISTER
>> 1442 help
>> 1443 The Loongson 1C is a 32-bit SoC, which implements the MIPS32
>> 1444 Release 1 instruction set and part of the MIPS32 Release 2
>> 1445 instruction set.
>> 1446
>> 1447 config CPU_MIPS32_R1
>> 1448 bool "MIPS32 Release 1"
>> 1449 depends on SYS_HAS_CPU_MIPS32_R1
>> 1450 select CPU_HAS_PREFETCH
>> 1451 select CPU_HAS_LOAD_STORE_LR
>> 1452 select CPU_SUPPORTS_32BIT_KERNEL
>> 1453 select CPU_SUPPORTS_HIGHMEM
>> 1454 help
>> 1455 Choose this option to build a kernel for release 1 or later of the
>> 1456 MIPS32 architecture. Most modern embedded systems with a 32-bit
>> 1457 MIPS processor are based on a MIPS32 processor. If you know the
>> 1458 specific type of processor in your system, choose those that one
>> 1459 otherwise CPU_MIPS32_R1 is a safe bet for any MIPS32 system.
>> 1460 Release 2 of the MIPS32 architecture is available since several
>> 1461 years so chances are you even have a MIPS32 Release 2 processor
>> 1462 in which case you should choose CPU_MIPS32_R2 instead for better
>> 1463 performance.
>> 1464
>> 1465 config CPU_MIPS32_R2
>> 1466 bool "MIPS32 Release 2"
>> 1467 depends on SYS_HAS_CPU_MIPS32_R2
>> 1468 select CPU_HAS_PREFETCH
>> 1469 select CPU_HAS_LOAD_STORE_LR
>> 1470 select CPU_SUPPORTS_32BIT_KERNEL
>> 1471 select CPU_SUPPORTS_HIGHMEM
>> 1472 select CPU_SUPPORTS_MSA
>> 1473 select HAVE_KVM
>> 1474 help
>> 1475 Choose this option to build a kernel for release 2 or later of the
>> 1476 MIPS32 architecture. Most modern embedded systems with a 32-bit
>> 1477 MIPS processor are based on a MIPS32 processor. If you know the
>> 1478 specific type of processor in your system, choose those that one
>> 1479 otherwise CPU_MIPS32_R1 is a safe bet for any MIPS32 system.
>> 1480
>> 1481 config CPU_MIPS32_R6
>> 1482 bool "MIPS32 Release 6"
>> 1483 depends on SYS_HAS_CPU_MIPS32_R6
>> 1484 select CPU_HAS_PREFETCH
>> 1485 select CPU_SUPPORTS_32BIT_KERNEL
>> 1486 select CPU_SUPPORTS_HIGHMEM
>> 1487 select CPU_SUPPORTS_MSA
>> 1488 select HAVE_KVM
>> 1489 select MIPS_O32_FP64_SUPPORT
>> 1490 help
>> 1491 Choose this option to build a kernel for release 6 or later of the
>> 1492 MIPS32 architecture. New MIPS processors, starting with the Warrior
>> 1493 family, are based on a MIPS32r6 processor. If you own an older
>> 1494 processor, you probably need to select MIPS32r1 or MIPS32r2 instead.
>> 1495
>> 1496 config CPU_MIPS64_R1
>> 1497 bool "MIPS64 Release 1"
>> 1498 depends on SYS_HAS_CPU_MIPS64_R1
>> 1499 select CPU_HAS_PREFETCH
>> 1500 select CPU_HAS_LOAD_STORE_LR
>> 1501 select CPU_SUPPORTS_32BIT_KERNEL
>> 1502 select CPU_SUPPORTS_64BIT_KERNEL
>> 1503 select CPU_SUPPORTS_HIGHMEM
>> 1504 select CPU_SUPPORTS_HUGEPAGES
>> 1505 help
>> 1506 Choose this option to build a kernel for release 1 or later of the
>> 1507 MIPS64 architecture. Many modern embedded systems with a 64-bit
>> 1508 MIPS processor are based on a MIPS64 processor. If you know the
>> 1509 specific type of processor in your system, choose those that one
>> 1510 otherwise CPU_MIPS64_R1 is a safe bet for any MIPS64 system.
>> 1511 Release 2 of the MIPS64 architecture is available since several
>> 1512 years so chances are you even have a MIPS64 Release 2 processor
>> 1513 in which case you should choose CPU_MIPS64_R2 instead for better
>> 1514 performance.
>> 1515
>> 1516 config CPU_MIPS64_R2
>> 1517 bool "MIPS64 Release 2"
>> 1518 depends on SYS_HAS_CPU_MIPS64_R2
>> 1519 select CPU_HAS_PREFETCH
>> 1520 select CPU_HAS_LOAD_STORE_LR
>> 1521 select CPU_SUPPORTS_32BIT_KERNEL
>> 1522 select CPU_SUPPORTS_64BIT_KERNEL
>> 1523 select CPU_SUPPORTS_HIGHMEM
>> 1524 select CPU_SUPPORTS_HUGEPAGES
>> 1525 select CPU_SUPPORTS_MSA
>> 1526 select HAVE_KVM
>> 1527 help
>> 1528 Choose this option to build a kernel for release 2 or later of the
>> 1529 MIPS64 architecture. Many modern embedded systems with a 64-bit
>> 1530 MIPS processor are based on a MIPS64 processor. If you know the
>> 1531 specific type of processor in your system, choose those that one
>> 1532 otherwise CPU_MIPS64_R1 is a safe bet for any MIPS64 system.
>> 1533
>> 1534 config CPU_MIPS64_R6
>> 1535 bool "MIPS64 Release 6"
>> 1536 depends on SYS_HAS_CPU_MIPS64_R6
>> 1537 select CPU_HAS_PREFETCH
>> 1538 select CPU_SUPPORTS_32BIT_KERNEL
>> 1539 select CPU_SUPPORTS_64BIT_KERNEL
>> 1540 select CPU_SUPPORTS_HIGHMEM
>> 1541 select CPU_SUPPORTS_MSA
>> 1542 select MIPS_O32_FP64_SUPPORT if 32BIT || MIPS32_O32
>> 1543 select HAVE_KVM
>> 1544 help
>> 1545 Choose this option to build a kernel for release 6 or later of the
>> 1546 MIPS64 architecture. New MIPS processors, starting with the Warrior
>> 1547 family, are based on a MIPS64r6 processor. If you own an older
>> 1548 processor, you probably need to select MIPS64r1 or MIPS64r2 instead.
>> 1549
>> 1550 config CPU_R3000
>> 1551 bool "R3000"
>> 1552 depends on SYS_HAS_CPU_R3000
>> 1553 select CPU_HAS_WB
>> 1554 select CPU_HAS_LOAD_STORE_LR
>> 1555 select CPU_SUPPORTS_32BIT_KERNEL
>> 1556 select CPU_SUPPORTS_HIGHMEM
>> 1557 help
>> 1558 Please make sure to pick the right CPU type. Linux/MIPS is not
>> 1559 designed to be generic, i.e. Kernels compiled for R3000 CPUs will
>> 1560 *not* work on R4000 machines and vice versa. However, since most
>> 1561 of the supported machines have an R4000 (or similar) CPU, R4x00
>> 1562 might be a safe bet. If the resulting kernel does not work,
>> 1563 try to recompile with R3000.
>> 1564
>> 1565 config CPU_TX39XX
>> 1566 bool "R39XX"
>> 1567 depends on SYS_HAS_CPU_TX39XX
>> 1568 select CPU_SUPPORTS_32BIT_KERNEL
>> 1569 select CPU_HAS_LOAD_STORE_LR
>> 1570
>> 1571 config CPU_VR41XX
>> 1572 bool "R41xx"
>> 1573 depends on SYS_HAS_CPU_VR41XX
>> 1574 select CPU_SUPPORTS_32BIT_KERNEL
>> 1575 select CPU_SUPPORTS_64BIT_KERNEL
>> 1576 select CPU_HAS_LOAD_STORE_LR
>> 1577 help
>> 1578 The options selects support for the NEC VR4100 series of processors.
>> 1579 Only choose this option if you have one of these processors as a
>> 1580 kernel built with this option will not run on any other type of
>> 1581 processor or vice versa.
>> 1582
>> 1583 config CPU_R4300
>> 1584 bool "R4300"
>> 1585 depends on SYS_HAS_CPU_R4300
>> 1586 select CPU_SUPPORTS_32BIT_KERNEL
>> 1587 select CPU_SUPPORTS_64BIT_KERNEL
>> 1588 select CPU_HAS_LOAD_STORE_LR
>> 1589 help
>> 1590 MIPS Technologies R4300-series processors.
>> 1591
>> 1592 config CPU_R4X00
>> 1593 bool "R4x00"
>> 1594 depends on SYS_HAS_CPU_R4X00
>> 1595 select CPU_SUPPORTS_32BIT_KERNEL
>> 1596 select CPU_SUPPORTS_64BIT_KERNEL
>> 1597 select CPU_SUPPORTS_HUGEPAGES
>> 1598 select CPU_HAS_LOAD_STORE_LR
>> 1599 help
>> 1600 MIPS Technologies R4000-series processors other than 4300, including
>> 1601 the R4000, R4400, R4600, and 4700.
>> 1602
>> 1603 config CPU_TX49XX
>> 1604 bool "R49XX"
>> 1605 depends on SYS_HAS_CPU_TX49XX
>> 1606 select CPU_HAS_PREFETCH
>> 1607 select CPU_HAS_LOAD_STORE_LR
>> 1608 select CPU_SUPPORTS_32BIT_KERNEL
>> 1609 select CPU_SUPPORTS_64BIT_KERNEL
>> 1610 select CPU_SUPPORTS_HUGEPAGES
>> 1611
>> 1612 config CPU_R5000
>> 1613 bool "R5000"
>> 1614 depends on SYS_HAS_CPU_R5000
>> 1615 select CPU_SUPPORTS_32BIT_KERNEL
>> 1616 select CPU_SUPPORTS_64BIT_KERNEL
>> 1617 select CPU_SUPPORTS_HUGEPAGES
>> 1618 select CPU_HAS_LOAD_STORE_LR
>> 1619 help
>> 1620 MIPS Technologies R5000-series processors other than the Nevada.
>> 1621
>> 1622 config CPU_R5432
>> 1623 bool "R5432"
>> 1624 depends on SYS_HAS_CPU_R5432
>> 1625 select CPU_SUPPORTS_32BIT_KERNEL
>> 1626 select CPU_SUPPORTS_64BIT_KERNEL
>> 1627 select CPU_SUPPORTS_HUGEPAGES
>> 1628 select CPU_HAS_LOAD_STORE_LR
>> 1629
>> 1630 config CPU_R5500
>> 1631 bool "R5500"
>> 1632 depends on SYS_HAS_CPU_R5500
>> 1633 select CPU_SUPPORTS_32BIT_KERNEL
>> 1634 select CPU_SUPPORTS_64BIT_KERNEL
>> 1635 select CPU_SUPPORTS_HUGEPAGES
>> 1636 select CPU_HAS_LOAD_STORE_LR
>> 1637 help
>> 1638 NEC VR5500 and VR5500A series processors implement 64-bit MIPS IV
>> 1639 instruction set.
>> 1640
>> 1641 config CPU_NEVADA
>> 1642 bool "RM52xx"
>> 1643 depends on SYS_HAS_CPU_NEVADA
>> 1644 select CPU_SUPPORTS_32BIT_KERNEL
>> 1645 select CPU_SUPPORTS_64BIT_KERNEL
>> 1646 select CPU_SUPPORTS_HUGEPAGES
>> 1647 select CPU_HAS_LOAD_STORE_LR
>> 1648 help
>> 1649 QED / PMC-Sierra RM52xx-series ("Nevada") processors.
>> 1650
>> 1651 config CPU_R8000
>> 1652 bool "R8000"
>> 1653 depends on SYS_HAS_CPU_R8000
>> 1654 select CPU_HAS_PREFETCH
>> 1655 select CPU_HAS_LOAD_STORE_LR
>> 1656 select CPU_SUPPORTS_64BIT_KERNEL
>> 1657 help
>> 1658 MIPS Technologies R8000 processors. Note these processors are
>> 1659 uncommon and the support for them is incomplete.
>> 1660
>> 1661 config CPU_R10000
>> 1662 bool "R10000"
>> 1663 depends on SYS_HAS_CPU_R10000
>> 1664 select CPU_HAS_PREFETCH
>> 1665 select CPU_HAS_LOAD_STORE_LR
>> 1666 select CPU_SUPPORTS_32BIT_KERNEL
>> 1667 select CPU_SUPPORTS_64BIT_KERNEL
>> 1668 select CPU_SUPPORTS_HIGHMEM
>> 1669 select CPU_SUPPORTS_HUGEPAGES
>> 1670 help
>> 1671 MIPS Technologies R10000-series processors.
>> 1672
>> 1673 config CPU_RM7000
>> 1674 bool "RM7000"
>> 1675 depends on SYS_HAS_CPU_RM7000
>> 1676 select CPU_HAS_PREFETCH
>> 1677 select CPU_HAS_LOAD_STORE_LR
>> 1678 select CPU_SUPPORTS_32BIT_KERNEL
>> 1679 select CPU_SUPPORTS_64BIT_KERNEL
>> 1680 select CPU_SUPPORTS_HIGHMEM
>> 1681 select CPU_SUPPORTS_HUGEPAGES
>> 1682
>> 1683 config CPU_SB1
>> 1684 bool "SB1"
>> 1685 depends on SYS_HAS_CPU_SB1
>> 1686 select CPU_HAS_LOAD_STORE_LR
>> 1687 select CPU_SUPPORTS_32BIT_KERNEL
>> 1688 select CPU_SUPPORTS_64BIT_KERNEL
>> 1689 select CPU_SUPPORTS_HIGHMEM
>> 1690 select CPU_SUPPORTS_HUGEPAGES
>> 1691 select WEAK_ORDERING
>> 1692
>> 1693 config CPU_CAVIUM_OCTEON
>> 1694 bool "Cavium Octeon processor"
>> 1695 depends on SYS_HAS_CPU_CAVIUM_OCTEON
>> 1696 select CPU_HAS_PREFETCH
>> 1697 select CPU_HAS_LOAD_STORE_LR
>> 1698 select CPU_SUPPORTS_64BIT_KERNEL
>> 1699 select WEAK_ORDERING
>> 1700 select CPU_SUPPORTS_HIGHMEM
>> 1701 select CPU_SUPPORTS_HUGEPAGES
>> 1702 select USB_EHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 1703 select USB_OHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 1704 select MIPS_L1_CACHE_SHIFT_7
>> 1705 select HAVE_KVM
>> 1706 help
>> 1707 The Cavium Octeon processor is a highly integrated chip containing
>> 1708 many ethernet hardware widgets for networking tasks. The processor
>> 1709 can have up to 16 Mips64v2 cores and 8 integrated gigabit ethernets.
>> 1710 Full details can be found at http://www.caviumnetworks.com.
>> 1711
>> 1712 config CPU_BMIPS
>> 1713 bool "Broadcom BMIPS"
>> 1714 depends on SYS_HAS_CPU_BMIPS
>> 1715 select CPU_MIPS32
>> 1716 select CPU_BMIPS32_3300 if SYS_HAS_CPU_BMIPS32_3300
>> 1717 select CPU_BMIPS4350 if SYS_HAS_CPU_BMIPS4350
>> 1718 select CPU_BMIPS4380 if SYS_HAS_CPU_BMIPS4380
>> 1719 select CPU_BMIPS5000 if SYS_HAS_CPU_BMIPS5000
>> 1720 select CPU_SUPPORTS_32BIT_KERNEL
>> 1721 select DMA_NONCOHERENT
>> 1722 select IRQ_MIPS_CPU
>> 1723 select SWAP_IO_SPACE
>> 1724 select WEAK_ORDERING
>> 1725 select CPU_SUPPORTS_HIGHMEM
>> 1726 select CPU_HAS_PREFETCH
>> 1727 select CPU_HAS_LOAD_STORE_LR
>> 1728 select CPU_SUPPORTS_CPUFREQ
>> 1729 select MIPS_EXTERNAL_TIMER
>> 1730 help
>> 1731 Support for BMIPS32/3300/4350/4380 and BMIPS5000 processors.
>> 1732
>> 1733 config CPU_XLR
>> 1734 bool "Netlogic XLR SoC"
>> 1735 depends on SYS_HAS_CPU_XLR
>> 1736 select CPU_HAS_LOAD_STORE_LR
>> 1737 select CPU_SUPPORTS_32BIT_KERNEL
>> 1738 select CPU_SUPPORTS_64BIT_KERNEL
>> 1739 select CPU_SUPPORTS_HIGHMEM
>> 1740 select CPU_SUPPORTS_HUGEPAGES
>> 1741 select WEAK_ORDERING
>> 1742 select WEAK_REORDERING_BEYOND_LLSC
>> 1743 help
>> 1744 Netlogic Microsystems XLR/XLS processors.
>> 1745
>> 1746 config CPU_XLP
>> 1747 bool "Netlogic XLP SoC"
>> 1748 depends on SYS_HAS_CPU_XLP
>> 1749 select CPU_SUPPORTS_32BIT_KERNEL
>> 1750 select CPU_SUPPORTS_64BIT_KERNEL
>> 1751 select CPU_SUPPORTS_HIGHMEM
>> 1752 select WEAK_ORDERING
>> 1753 select WEAK_REORDERING_BEYOND_LLSC
>> 1754 select CPU_HAS_PREFETCH
>> 1755 select CPU_HAS_LOAD_STORE_LR
>> 1756 select CPU_MIPSR2
>> 1757 select CPU_SUPPORTS_HUGEPAGES
>> 1758 select MIPS_ASID_BITS_VARIABLE
>> 1759 help
>> 1760 Netlogic Microsystems XLP processors.
>> 1761 endchoice
979 1762
980 If unsure, say Y. !! 1763 config CPU_MIPS32_3_5_FEATURES
>> 1764 bool "MIPS32 Release 3.5 Features"
>> 1765 depends on SYS_HAS_CPU_MIPS32_R3_5
>> 1766 depends on CPU_MIPS32_R2 || CPU_MIPS32_R6
>> 1767 help
>> 1768 Choose this option to build a kernel for release 2 or later of the
>> 1769 MIPS32 architecture including features from the 3.5 release such as
>> 1770 support for Enhanced Virtual Addressing (EVA).
>> 1771
>> 1772 config CPU_MIPS32_3_5_EVA
>> 1773 bool "Enhanced Virtual Addressing (EVA)"
>> 1774 depends on CPU_MIPS32_3_5_FEATURES
>> 1775 select EVA
>> 1776 default y
>> 1777 help
>> 1778 Choose this option if you want to enable the Enhanced Virtual
>> 1779 Addressing (EVA) on your MIPS32 core (such as proAptiv).
>> 1780 One of its primary benefits is an increase in the maximum size
>> 1781 of lowmem (up to 3GB). If unsure, say 'N' here.
>> 1782
>> 1783 config CPU_MIPS32_R5_FEATURES
>> 1784 bool "MIPS32 Release 5 Features"
>> 1785 depends on SYS_HAS_CPU_MIPS32_R5
>> 1786 depends on CPU_MIPS32_R2
>> 1787 help
>> 1788 Choose this option to build a kernel for release 2 or later of the
>> 1789 MIPS32 architecture including features from release 5 such as
>> 1790 support for Extended Physical Addressing (XPA).
>> 1791
>> 1792 config CPU_MIPS32_R5_XPA
>> 1793 bool "Extended Physical Addressing (XPA)"
>> 1794 depends on CPU_MIPS32_R5_FEATURES
>> 1795 depends on !EVA
>> 1796 depends on !PAGE_SIZE_4KB
>> 1797 depends on SYS_SUPPORTS_HIGHMEM
>> 1798 select XPA
>> 1799 select HIGHMEM
>> 1800 select PHYS_ADDR_T_64BIT
>> 1801 default n
>> 1802 help
>> 1803 Choose this option if you want to enable the Extended Physical
>> 1804 Addressing (XPA) on your MIPS32 core (such as P5600 series). The
>> 1805 benefit is to increase physical addressing equal to or greater
>> 1806 than 40 bits. Note that this has the side effect of turning on
>> 1807 64-bit addressing which in turn makes the PTEs 64-bit in size.
>> 1808 If unsure, say 'N' here.
981 1809
982 config ARM64_ERRATUM_2038923 !! 1810 if CPU_LOONGSON2F
983 bool "Cortex-A510: 2038923: workaround !! 1811 config CPU_NOP_WORKAROUNDS
984 depends on CORESIGHT_TRBE !! 1812 bool
985 default y <<
986 help <<
987 This option adds the workaround for <<
988 <<
989 Affected Cortex-A510 core might caus <<
990 prohibited within the CPU. As a resu <<
991 might be corrupted. This happens aft <<
992 TRBLIMITR_EL1.E, followed by just a <<
993 execution changes from a context, in <<
994 isn't, or vice versa. In these menti <<
995 is prohibited is inconsistent betwee <<
996 the trace buffer state might be corr <<
997 <<
998 Work around this in the driver by pr <<
999 trace is prohibited or not based on <<
1000 change to TRBLIMITR_EL1.E with at l <<
1001 two ISB instructions if no ERET is <<
1002 1813
1003 If unsure, say Y. !! 1814 config CPU_JUMP_WORKAROUNDS
>> 1815 bool
1004 1816
1005 config ARM64_ERRATUM_1902691 !! 1817 config CPU_LOONGSON2F_WORKAROUNDS
1006 bool "Cortex-A510: 1902691: workaroun !! 1818 bool "Loongson 2F Workarounds"
1007 depends on CORESIGHT_TRBE <<
1008 default y 1819 default y
>> 1820 select CPU_NOP_WORKAROUNDS
>> 1821 select CPU_JUMP_WORKAROUNDS
1009 help 1822 help
1010 This option adds the workaround for !! 1823 Loongson 2F01 / 2F02 processors have the NOP & JUMP issues which
1011 !! 1824 require workarounds. Without workarounds the system may hang
1012 Affected Cortex-A510 core might cau !! 1825 unexpectedly. For more information please refer to the gas
1013 into the memory. Effectively TRBE i !! 1826 -mfix-loongson2f-nop and -mfix-loongson2f-jump options.
1014 trace data. !! 1827
>> 1828 Loongson 2F03 and later have fixed these issues and no workarounds
>> 1829 are needed. The workarounds have no significant side effect on them
>> 1830 but may decrease the performance of the system so this option should
>> 1831 be disabled unless the kernel is intended to be run on 2F01 or 2F02
>> 1832 systems.
1015 1833
1016 Work around this problem in the dri !! 1834 If unsure, please say Y.
1017 affected cpus. The firmware must ha !! 1835 endif # CPU_LOONGSON2F
1018 on such implementations. This will <<
1019 do this already. <<
1020 1836
1021 If unsure, say Y. !! 1837 config SYS_SUPPORTS_ZBOOT
>> 1838 bool
>> 1839 select HAVE_KERNEL_GZIP
>> 1840 select HAVE_KERNEL_BZIP2
>> 1841 select HAVE_KERNEL_LZ4
>> 1842 select HAVE_KERNEL_LZMA
>> 1843 select HAVE_KERNEL_LZO
>> 1844 select HAVE_KERNEL_XZ
1022 1845
1023 config ARM64_ERRATUM_2457168 !! 1846 config SYS_SUPPORTS_ZBOOT_UART16550
1024 bool "Cortex-A510: 2457168: workaroun !! 1847 bool
1025 depends on ARM64_AMU_EXTN !! 1848 select SYS_SUPPORTS_ZBOOT
1026 default y <<
1027 help <<
1028 This option adds the workaround for <<
1029 1849
1030 The AMU counter AMEVCNTR01 (constan !! 1850 config SYS_SUPPORTS_ZBOOT_UART_PROM
1031 as the system counter. On affected !! 1851 bool
1032 incorrectly giving a significantly !! 1852 select SYS_SUPPORTS_ZBOOT
1033 1853
1034 Work around this problem by returni !! 1854 config CPU_LOONGSON2
1035 key locations that results in disab !! 1855 bool
1036 is the same to firmware disabling a !! 1856 select CPU_SUPPORTS_32BIT_KERNEL
>> 1857 select CPU_SUPPORTS_64BIT_KERNEL
>> 1858 select CPU_SUPPORTS_HIGHMEM
>> 1859 select CPU_SUPPORTS_HUGEPAGES
>> 1860 select ARCH_HAS_PHYS_TO_DMA
>> 1861 select CPU_HAS_LOAD_STORE_LR
1037 1862
1038 If unsure, say Y. !! 1863 config CPU_LOONGSON1
>> 1864 bool
>> 1865 select CPU_MIPS32
>> 1866 select CPU_MIPSR1
>> 1867 select CPU_HAS_PREFETCH
>> 1868 select CPU_HAS_LOAD_STORE_LR
>> 1869 select CPU_SUPPORTS_32BIT_KERNEL
>> 1870 select CPU_SUPPORTS_HIGHMEM
>> 1871 select CPU_SUPPORTS_CPUFREQ
1039 1872
1040 config ARM64_ERRATUM_2645198 !! 1873 config CPU_BMIPS32_3300
1041 bool "Cortex-A715: 2645198: Workaroun !! 1874 select SMP_UP if SMP
1042 default y !! 1875 bool
1043 help <<
1044 This option adds the workaround for <<
1045 1876
1046 If a Cortex-A715 cpu sees a page ma !! 1877 config CPU_BMIPS4350
1047 to non-executable, it may corrupt t !! 1878 bool
1048 next instruction abort caused by pe !! 1879 select SYS_SUPPORTS_SMP
>> 1880 select SYS_SUPPORTS_HOTPLUG_CPU
1049 1881
1050 Only user-space does executable to !! 1882 config CPU_BMIPS4380
1051 mprotect() system call. Workaround !! 1883 bool
1052 TLB invalidation, for all changes t !! 1884 select MIPS_L1_CACHE_SHIFT_6
>> 1885 select SYS_SUPPORTS_SMP
>> 1886 select SYS_SUPPORTS_HOTPLUG_CPU
>> 1887 select CPU_HAS_RIXI
1053 1888
1054 If unsure, say Y. !! 1889 config CPU_BMIPS5000
>> 1890 bool
>> 1891 select MIPS_CPU_SCACHE
>> 1892 select MIPS_L1_CACHE_SHIFT_7
>> 1893 select SYS_SUPPORTS_SMP
>> 1894 select SYS_SUPPORTS_HOTPLUG_CPU
>> 1895 select CPU_HAS_RIXI
1055 1896
1056 config ARM64_WORKAROUND_SPECULATIVE_UNPRIV_LO !! 1897 config SYS_HAS_CPU_LOONGSON3
1057 bool 1898 bool
>> 1899 select CPU_SUPPORTS_CPUFREQ
>> 1900 select CPU_HAS_RIXI
1058 1901
1059 config ARM64_ERRATUM_2966298 !! 1902 config SYS_HAS_CPU_LOONGSON2E
1060 bool "Cortex-A520: 2966298: workaroun !! 1903 bool
1061 select ARM64_WORKAROUND_SPECULATIVE_U <<
1062 default y <<
1063 help <<
1064 This option adds the workaround for <<
1065 1904
1066 On an affected Cortex-A520 core, a !! 1905 config SYS_HAS_CPU_LOONGSON2F
1067 load might leak data from a privile !! 1906 bool
>> 1907 select CPU_SUPPORTS_CPUFREQ
>> 1908 select CPU_SUPPORTS_ADDRWINCFG if 64BIT
>> 1909 select CPU_SUPPORTS_UNCACHED_ACCELERATED
1068 1910
1069 Work around this problem by executi !! 1911 config SYS_HAS_CPU_LOONGSON1B
>> 1912 bool
1070 1913
1071 If unsure, say Y. !! 1914 config SYS_HAS_CPU_LOONGSON1C
>> 1915 bool
1072 1916
1073 config ARM64_ERRATUM_3117295 !! 1917 config SYS_HAS_CPU_MIPS32_R1
1074 bool "Cortex-A510: 3117295: workaroun !! 1918 bool
1075 select ARM64_WORKAROUND_SPECULATIVE_U <<
1076 default y <<
1077 help <<
1078 This option adds the workaround for <<
1079 1919
1080 On an affected Cortex-A510 core, a !! 1920 config SYS_HAS_CPU_MIPS32_R2
1081 load might leak data from a privile !! 1921 bool
1082 1922
1083 Work around this problem by executi !! 1923 config SYS_HAS_CPU_MIPS32_R3_5
>> 1924 bool
1084 1925
1085 If unsure, say Y. !! 1926 config SYS_HAS_CPU_MIPS32_R5
>> 1927 bool
1086 1928
1087 config ARM64_ERRATUM_3194386 !! 1929 config SYS_HAS_CPU_MIPS32_R6
1088 bool "Cortex-*/Neoverse-*: workaround !! 1930 bool
1089 default y <<
1090 help <<
1091 This option adds the workaround for <<
1092 1931
1093 * ARM Cortex-A76 erratum 3324349 !! 1932 config SYS_HAS_CPU_MIPS64_R1
1094 * ARM Cortex-A77 erratum 3324348 !! 1933 bool
1095 * ARM Cortex-A78 erratum 3324344 <<
1096 * ARM Cortex-A78C erratum 3324346 <<
1097 * ARM Cortex-A78C erratum 3324347 <<
1098 * ARM Cortex-A710 erratam 3324338 <<
1099 * ARM Cortex-A715 errartum 3456084 <<
1100 * ARM Cortex-A720 erratum 3456091 <<
1101 * ARM Cortex-A725 erratum 3456106 <<
1102 * ARM Cortex-X1 erratum 3324344 <<
1103 * ARM Cortex-X1C erratum 3324346 <<
1104 * ARM Cortex-X2 erratum 3324338 <<
1105 * ARM Cortex-X3 erratum 3324335 <<
1106 * ARM Cortex-X4 erratum 3194386 <<
1107 * ARM Cortex-X925 erratum 3324334 <<
1108 * ARM Neoverse-N1 erratum 3324349 <<
1109 * ARM Neoverse N2 erratum 3324339 <<
1110 * ARM Neoverse-N3 erratum 3456111 <<
1111 * ARM Neoverse-V1 erratum 3324341 <<
1112 * ARM Neoverse V2 erratum 3324336 <<
1113 * ARM Neoverse-V3 erratum 3312417 <<
1114 <<
1115 On affected cores "MSR SSBS, #0" in <<
1116 subsequent speculative instructions <<
1117 speculative store bypassing. <<
1118 <<
1119 Work around this problem by placing <<
1120 Instruction Synchronization Barrier <<
1121 SSBS. The presence of the SSBS spec <<
1122 from hwcaps and EL0 reads of ID_AA6 <<
1123 will use the PR_SPEC_STORE_BYPASS p <<
1124 1934
1125 If unsure, say Y. !! 1935 config SYS_HAS_CPU_MIPS64_R2
>> 1936 bool
1126 1937
1127 config CAVIUM_ERRATUM_22375 !! 1938 config SYS_HAS_CPU_MIPS64_R6
1128 bool "Cavium erratum 22375, 24313" !! 1939 bool
1129 default y <<
1130 help <<
1131 Enable workaround for errata 22375 <<
1132 1940
1133 This implements two gicv3-its errat !! 1941 config SYS_HAS_CPU_R3000
1134 with a small impact affecting only !! 1942 bool
1135 1943
1136 erratum 22375: only alloc 8MB tab !! 1944 config SYS_HAS_CPU_TX39XX
1137 erratum 24313: ignore memory acce !! 1945 bool
1138 1946
1139 The fixes are in ITS initialization !! 1947 config SYS_HAS_CPU_VR41XX
1140 type and table size provided by the !! 1948 bool
1141 1949
1142 If unsure, say Y. !! 1950 config SYS_HAS_CPU_R4300
>> 1951 bool
1143 1952
1144 config CAVIUM_ERRATUM_23144 !! 1953 config SYS_HAS_CPU_R4X00
1145 bool "Cavium erratum 23144: ITS SYNC !! 1954 bool
1146 depends on NUMA <<
1147 default y <<
1148 help <<
1149 ITS SYNC command hang for cross nod <<
1150 1955
1151 If unsure, say Y. !! 1956 config SYS_HAS_CPU_TX49XX
>> 1957 bool
1152 1958
1153 config CAVIUM_ERRATUM_23154 !! 1959 config SYS_HAS_CPU_R5000
1154 bool "Cavium errata 23154 and 38545: !! 1960 bool
1155 default y <<
1156 help <<
1157 The ThunderX GICv3 implementation r <<
1158 reading the IAR status to ensure da <<
1159 (access to icc_iar1_el1 is not sync <<
1160 1961
1161 It also suffers from erratum 38545 !! 1962 config SYS_HAS_CPU_R5432
1162 OcteonTX and OcteonTX2), resulting !! 1963 bool
1163 spuriously presented to the CPU int <<
1164 1964
1165 If unsure, say Y. !! 1965 config SYS_HAS_CPU_R5500
>> 1966 bool
1166 1967
1167 config CAVIUM_ERRATUM_27456 !! 1968 config SYS_HAS_CPU_NEVADA
1168 bool "Cavium erratum 27456: Broadcast !! 1969 bool
1169 default y <<
1170 help <<
1171 On ThunderX T88 pass 1.x through 2. <<
1172 instructions may cause the icache t <<
1173 contains data for a non-current ASI <<
1174 invalidate the icache when changing <<
1175 1970
1176 If unsure, say Y. !! 1971 config SYS_HAS_CPU_R8000
>> 1972 bool
1177 1973
1178 config CAVIUM_ERRATUM_30115 !! 1974 config SYS_HAS_CPU_R10000
1179 bool "Cavium erratum 30115: Guest may !! 1975 bool
1180 default y <<
1181 help <<
1182 On ThunderX T88 pass 1.x through 2. <<
1183 1.2, and T83 Pass 1.0, KVM guest ex <<
1184 interrupts in host. Trapping both G <<
1185 accesses sidesteps the issue. <<
1186 1976
1187 If unsure, say Y. !! 1977 config SYS_HAS_CPU_RM7000
>> 1978 bool
1188 1979
1189 config CAVIUM_TX2_ERRATUM_219 !! 1980 config SYS_HAS_CPU_SB1
1190 bool "Cavium ThunderX2 erratum 219: P !! 1981 bool
1191 default y <<
1192 help <<
1193 On Cavium ThunderX2, a load, store <<
1194 TTBR update and the corresponding c <<
1195 cause a spurious Data Abort to be d <<
1196 the CPU core. <<
1197 <<
1198 Work around the issue by avoiding t <<
1199 trapping KVM guest TTBRx_EL1 writes <<
1200 trap handler performs the correspon <<
1201 instruction and ensures context syn <<
1202 exception return. <<
1203 1982
1204 If unsure, say Y. !! 1983 config SYS_HAS_CPU_CAVIUM_OCTEON
>> 1984 bool
1205 1985
1206 config FUJITSU_ERRATUM_010001 !! 1986 config SYS_HAS_CPU_BMIPS
1207 bool "Fujitsu-A64FX erratum E#010001: !! 1987 bool
1208 default y <<
1209 help <<
1210 This option adds a workaround for F <<
1211 On some variants of the Fujitsu-A64 <<
1212 accesses may cause undefined fault <<
1213 This fault occurs under a specific <<
1214 load/store instruction performs an <<
1215 case-1 TTBR0_EL1 with TCR_EL1.NFD0 <<
1216 case-2 TTBR0_EL2 with TCR_EL2.NFD0 <<
1217 case-3 TTBR1_EL1 with TCR_EL1.NFD1 <<
1218 case-4 TTBR1_EL2 with TCR_EL2.NFD1 <<
1219 1988
1220 The workaround is to ensure these b !! 1989 config SYS_HAS_CPU_BMIPS32_3300
1221 The workaround only affects the Fuj !! 1990 bool
>> 1991 select SYS_HAS_CPU_BMIPS
1222 1992
1223 If unsure, say Y. !! 1993 config SYS_HAS_CPU_BMIPS4350
>> 1994 bool
>> 1995 select SYS_HAS_CPU_BMIPS
1224 1996
1225 config HISILICON_ERRATUM_161600802 !! 1997 config SYS_HAS_CPU_BMIPS4380
1226 bool "Hip07 161600802: Erroneous redi !! 1998 bool
1227 default y !! 1999 select SYS_HAS_CPU_BMIPS
1228 help <<
1229 The HiSilicon Hip07 SoC uses the wr <<
1230 when issued ITS commands such as VM <<
1231 a 128kB offset to be applied to the <<
1232 2000
1233 If unsure, say Y. !! 2001 config SYS_HAS_CPU_BMIPS5000
>> 2002 bool
>> 2003 select SYS_HAS_CPU_BMIPS
1234 2004
1235 config QCOM_FALKOR_ERRATUM_1003 !! 2005 config SYS_HAS_CPU_XLR
1236 bool "Falkor E1003: Incorrect transla !! 2006 bool
1237 default y <<
1238 help <<
1239 On Falkor v1, an incorrect ASID may <<
1240 and BADDR are changed together in T <<
1241 in TTBR1_EL1, this situation only o <<
1242 then only for entries in the walk c <<
1243 is unchanged. Work around the errat <<
1244 entries for the trampoline before e <<
1245 2007
1246 config QCOM_FALKOR_ERRATUM_1009 !! 2008 config SYS_HAS_CPU_XLP
1247 bool "Falkor E1009: Prematurely compl !! 2009 bool
1248 default y <<
1249 select ARM64_WORKAROUND_REPEAT_TLBI <<
1250 help <<
1251 On Falkor v1, the CPU may premature <<
1252 TLBI xxIS invalidate maintenance op <<
1253 one more time to fix the issue. <<
1254 2010
1255 If unsure, say Y. !! 2011 #
>> 2012 # CPU may reorder R->R, R->W, W->R, W->W
>> 2013 # Reordering beyond LL and SC is handled in WEAK_REORDERING_BEYOND_LLSC
>> 2014 #
>> 2015 config WEAK_ORDERING
>> 2016 bool
1256 2017
1257 config QCOM_QDF2400_ERRATUM_0065 !! 2018 #
1258 bool "QDF2400 E0065: Incorrect GITS_T !! 2019 # CPU may reorder reads and writes beyond LL/SC
1259 default y !! 2020 # CPU may reorder R->LL, R->LL, W->LL, W->LL, R->SC, R->SC, W->SC, W->SC
1260 help !! 2021 #
1261 On Qualcomm Datacenter Technologies !! 2022 config WEAK_REORDERING_BEYOND_LLSC
1262 ITE size incorrectly. The GITS_TYPE !! 2023 bool
1263 been indicated as 16Bytes (0xf), no !! 2024 endmenu
1264 2025
1265 If unsure, say Y. !! 2026 #
>> 2027 # These two indicate any level of the MIPS32 and MIPS64 architecture
>> 2028 #
>> 2029 config CPU_MIPS32
>> 2030 bool
>> 2031 default y if CPU_MIPS32_R1 || CPU_MIPS32_R2 || CPU_MIPS32_R6
1266 2032
1267 config QCOM_FALKOR_ERRATUM_E1041 !! 2033 config CPU_MIPS64
1268 bool "Falkor E1041: Speculative instr !! 2034 bool
1269 default y !! 2035 default y if CPU_MIPS64_R1 || CPU_MIPS64_R2 || CPU_MIPS64_R6
1270 help <<
1271 Falkor CPU may speculatively fetch <<
1272 memory location when MMU translatio <<
1273 to SCTLR_ELn[M]=0. Prefix an ISB in <<
1274 2036
1275 If unsure, say Y. !! 2037 #
>> 2038 # These two indicate the revision of the architecture, either Release 1 or Release 2
>> 2039 #
>> 2040 config CPU_MIPSR1
>> 2041 bool
>> 2042 default y if CPU_MIPS32_R1 || CPU_MIPS64_R1
1276 2043
1277 config NVIDIA_CARMEL_CNP_ERRATUM !! 2044 config CPU_MIPSR2
1278 bool "NVIDIA Carmel CNP: CNP on Carme !! 2045 bool
1279 default y !! 2046 default y if CPU_MIPS32_R2 || CPU_MIPS64_R2 || CPU_CAVIUM_OCTEON
1280 help !! 2047 select CPU_HAS_RIXI
1281 If CNP is enabled on Carmel cores, !! 2048 select MIPS_SPRAM
1282 invalidate shared TLB entries insta <<
1283 on standard ARM cores. <<
1284 2049
1285 If unsure, say Y. !! 2050 config CPU_MIPSR6
>> 2051 bool
>> 2052 default y if CPU_MIPS32_R6 || CPU_MIPS64_R6
>> 2053 select CPU_HAS_RIXI
>> 2054 select HAVE_ARCH_BITREVERSE
>> 2055 select MIPS_ASID_BITS_VARIABLE
>> 2056 select MIPS_CRC_SUPPORT
>> 2057 select MIPS_SPRAM
1286 2058
1287 config ROCKCHIP_ERRATUM_3588001 !! 2059 config EVA
1288 bool "Rockchip 3588001: GIC600 can no !! 2060 bool
1289 default y <<
1290 help <<
1291 The Rockchip RK3588 GIC600 SoC inte <<
1292 This means, that its sharability fe <<
1293 is supported by the IP itself. <<
1294 2061
1295 If unsure, say Y. !! 2062 config XPA
>> 2063 bool
1296 2064
1297 config SOCIONEXT_SYNQUACER_PREITS !! 2065 config SYS_SUPPORTS_32BIT_KERNEL
1298 bool "Socionext Synquacer: Workaround !! 2066 bool
1299 default y !! 2067 config SYS_SUPPORTS_64BIT_KERNEL
1300 help !! 2068 bool
1301 Socionext Synquacer SoCs implement !! 2069 config CPU_SUPPORTS_32BIT_KERNEL
1302 MSI doorbell writes with non-zero v !! 2070 bool
>> 2071 config CPU_SUPPORTS_64BIT_KERNEL
>> 2072 bool
>> 2073 config CPU_SUPPORTS_CPUFREQ
>> 2074 bool
>> 2075 config CPU_SUPPORTS_ADDRWINCFG
>> 2076 bool
>> 2077 config CPU_SUPPORTS_HUGEPAGES
>> 2078 bool
>> 2079 config CPU_SUPPORTS_UNCACHED_ACCELERATED
>> 2080 bool
>> 2081 config MIPS_PGD_C0_CONTEXT
>> 2082 bool
>> 2083 default y if 64BIT && (CPU_MIPSR2 || CPU_MIPSR6) && !CPU_XLP
1303 2084
1304 If unsure, say Y. !! 2085 #
>> 2086 # Set to y for ptrace access to watch registers.
>> 2087 #
>> 2088 config HARDWARE_WATCHPOINTS
>> 2089 bool
>> 2090 default y if CPU_MIPSR1 || CPU_MIPSR2 || CPU_MIPSR6
1305 2091
1306 endmenu # "ARM errata workarounds via the alt !! 2092 menu "Kernel type"
1307 2093
1308 choice 2094 choice
1309 prompt "Page size" !! 2095 prompt "Kernel code model"
1310 default ARM64_4K_PAGES <<
1311 help 2096 help
1312 Page size (translation granule) con !! 2097 You should only select this option if you have a workload that
1313 !! 2098 actually benefits from 64-bit processing or if your machine has
1314 config ARM64_4K_PAGES !! 2099 large memory. You will only be presented a single option in this
1315 bool "4KB" !! 2100 menu if your system does not support both 32-bit and 64-bit kernels.
1316 select HAVE_PAGE_SIZE_4KB !! 2101
>> 2102 config 32BIT
>> 2103 bool "32-bit kernel"
>> 2104 depends on CPU_SUPPORTS_32BIT_KERNEL && SYS_SUPPORTS_32BIT_KERNEL
>> 2105 select TRAD_SIGNALS
1317 help 2106 help
1318 This feature enables 4KB pages supp !! 2107 Select this option if you want to build a 32-bit kernel.
1319 2108
1320 config ARM64_16K_PAGES !! 2109 config 64BIT
1321 bool "16KB" !! 2110 bool "64-bit kernel"
1322 select HAVE_PAGE_SIZE_16KB !! 2111 depends on CPU_SUPPORTS_64BIT_KERNEL && SYS_SUPPORTS_64BIT_KERNEL
1323 help <<
1324 The system will use 16KB pages supp <<
1325 requires applications compiled with <<
1326 aligned segments. <<
1327 <<
1328 config ARM64_64K_PAGES <<
1329 bool "64KB" <<
1330 select HAVE_PAGE_SIZE_64KB <<
1331 help 2112 help
1332 This feature enables 64KB pages sup !! 2113 Select this option if you want to build a 64-bit kernel.
1333 allowing only two levels of page ta <<
1334 look-up. AArch32 emulation requires <<
1335 with 64K aligned segments. <<
1336 2114
1337 endchoice 2115 endchoice
1338 2116
>> 2117 config KVM_GUEST
>> 2118 bool "KVM Guest Kernel"
>> 2119 depends on BROKEN_ON_SMP
>> 2120 help
>> 2121 Select this option if building a guest kernel for KVM (Trap & Emulate)
>> 2122 mode.
>> 2123
>> 2124 config KVM_GUEST_TIMER_FREQ
>> 2125 int "Count/Compare Timer Frequency (MHz)"
>> 2126 depends on KVM_GUEST
>> 2127 default 100
>> 2128 help
>> 2129 Set this to non-zero if building a guest kernel for KVM to skip RTC
>> 2130 emulation when determining guest CPU Frequency. Instead, the guest's
>> 2131 timer frequency is specified directly.
>> 2132
>> 2133 config MIPS_VA_BITS_48
>> 2134 bool "48 bits virtual memory"
>> 2135 depends on 64BIT
>> 2136 help
>> 2137 Support a maximum at least 48 bits of application virtual
>> 2138 memory. Default is 40 bits or less, depending on the CPU.
>> 2139 For page sizes 16k and above, this option results in a small
>> 2140 memory overhead for page tables. For 4k page size, a fourth
>> 2141 level of page tables is added which imposes both a memory
>> 2142 overhead as well as slower TLB fault handling.
>> 2143
>> 2144 If unsure, say N.
>> 2145
1339 choice 2146 choice
1340 prompt "Virtual address space size" !! 2147 prompt "Kernel page size"
1341 default ARM64_VA_BITS_52 !! 2148 default PAGE_SIZE_4KB
1342 help <<
1343 Allows choosing one of multiple pos <<
1344 space sizes. The level of translati <<
1345 a combination of page size and virt <<
1346 <<
1347 config ARM64_VA_BITS_36 <<
1348 bool "36-bit" if EXPERT <<
1349 depends on PAGE_SIZE_16KB <<
1350 <<
1351 config ARM64_VA_BITS_39 <<
1352 bool "39-bit" <<
1353 depends on PAGE_SIZE_4KB <<
1354 <<
1355 config ARM64_VA_BITS_42 <<
1356 bool "42-bit" <<
1357 depends on PAGE_SIZE_64KB <<
1358 <<
1359 config ARM64_VA_BITS_47 <<
1360 bool "47-bit" <<
1361 depends on PAGE_SIZE_16KB <<
1362 <<
1363 config ARM64_VA_BITS_48 <<
1364 bool "48-bit" <<
1365 <<
1366 config ARM64_VA_BITS_52 <<
1367 bool "52-bit" <<
1368 depends on ARM64_PAN || !ARM64_SW_TTB <<
1369 help <<
1370 Enable 52-bit virtual addressing fo <<
1371 requested via a hint to mmap(). The <<
1372 virtual addresses for its own mappi <<
1373 this feature is available, otherwis <<
1374 <<
1375 NOTE: Enabling 52-bit virtual addre <<
1376 ARMv8.3 Pointer Authentication will <<
1377 reduced from 7 bits to 3 bits, whic <<
1378 impact on its susceptibility to bru <<
1379 2149
1380 If unsure, select 48-bit virtual ad !! 2150 config PAGE_SIZE_4KB
>> 2151 bool "4kB"
>> 2152 depends on !CPU_LOONGSON2 && !CPU_LOONGSON3
>> 2153 help
>> 2154 This option select the standard 4kB Linux page size. On some
>> 2155 R3000-family processors this is the only available page size. Using
>> 2156 4kB page size will minimize memory consumption and is therefore
>> 2157 recommended for low memory systems.
>> 2158
>> 2159 config PAGE_SIZE_8KB
>> 2160 bool "8kB"
>> 2161 depends on CPU_R8000 || CPU_CAVIUM_OCTEON
>> 2162 depends on !MIPS_VA_BITS_48
>> 2163 help
>> 2164 Using 8kB page size will result in higher performance kernel at
>> 2165 the price of higher memory consumption. This option is available
>> 2166 only on R8000 and cnMIPS processors. Note that you will need a
>> 2167 suitable Linux distribution to support this.
>> 2168
>> 2169 config PAGE_SIZE_16KB
>> 2170 bool "16kB"
>> 2171 depends on !CPU_R3000 && !CPU_TX39XX
>> 2172 help
>> 2173 Using 16kB page size will result in higher performance kernel at
>> 2174 the price of higher memory consumption. This option is available on
>> 2175 all non-R3000 family processors. Note that you will need a suitable
>> 2176 Linux distribution to support this.
>> 2177
>> 2178 config PAGE_SIZE_32KB
>> 2179 bool "32kB"
>> 2180 depends on CPU_CAVIUM_OCTEON
>> 2181 depends on !MIPS_VA_BITS_48
>> 2182 help
>> 2183 Using 32kB page size will result in higher performance kernel at
>> 2184 the price of higher memory consumption. This option is available
>> 2185 only on cnMIPS cores. Note that you will need a suitable Linux
>> 2186 distribution to support this.
>> 2187
>> 2188 config PAGE_SIZE_64KB
>> 2189 bool "64kB"
>> 2190 depends on !CPU_R3000 && !CPU_TX39XX
>> 2191 help
>> 2192 Using 64kB page size will result in higher performance kernel at
>> 2193 the price of higher memory consumption. This option is available on
>> 2194 all non-R3000 family processor. Not that at the time of this
>> 2195 writing this option is still high experimental.
1381 2196
1382 endchoice 2197 endchoice
1383 2198
1384 config ARM64_FORCE_52BIT !! 2199 config FORCE_MAX_ZONEORDER
1385 bool "Force 52-bit virtual addresses !! 2200 int "Maximum zone order"
1386 depends on ARM64_VA_BITS_52 && EXPERT !! 2201 range 14 64 if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_64KB
1387 help !! 2202 default "14" if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_64KB
1388 For systems with 52-bit userspace V !! 2203 range 13 64 if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_32KB
1389 to maintain compatibility with olde !! 2204 default "13" if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_32KB
1390 unless a hint is supplied to mmap. !! 2205 range 12 64 if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_16KB
1391 !! 2206 default "12" if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_16KB
1392 This configuration option disables !! 2207 range 11 64
1393 forces all userspace addresses to b !! 2208 default "11"
1394 should only enable this configurati !! 2209 help
1395 memory management code. If unsure s !! 2210 The kernel memory allocator divides physically contiguous memory
>> 2211 blocks into "zones", where each zone is a power of two number of
>> 2212 pages. This option selects the largest power of two that the kernel
>> 2213 keeps in the memory allocator. If you need to allocate very large
>> 2214 blocks of physically contiguous memory, then you may need to
>> 2215 increase this value.
1396 2216
1397 config ARM64_VA_BITS !! 2217 This config option is actually maximum order plus one. For example,
1398 int !! 2218 a value of 11 means that the largest free memory block is 2^10 pages.
1399 default 36 if ARM64_VA_BITS_36 <<
1400 default 39 if ARM64_VA_BITS_39 <<
1401 default 42 if ARM64_VA_BITS_42 <<
1402 default 47 if ARM64_VA_BITS_47 <<
1403 default 48 if ARM64_VA_BITS_48 <<
1404 default 52 if ARM64_VA_BITS_52 <<
1405 2219
1406 choice !! 2220 The page size is not necessarily 4KB. Keep this in mind
1407 prompt "Physical address space size" !! 2221 when choosing a value for this option.
1408 default ARM64_PA_BITS_48 <<
1409 help <<
1410 Choose the maximum physical address <<
1411 support. <<
1412 2222
1413 config ARM64_PA_BITS_48 !! 2223 config BOARD_SCACHE
1414 bool "48-bit" !! 2224 bool
1415 depends on ARM64_64K_PAGES || !ARM64_ <<
1416 <<
1417 config ARM64_PA_BITS_52 <<
1418 bool "52-bit" <<
1419 depends on ARM64_64K_PAGES || ARM64_V <<
1420 depends on ARM64_PAN || !ARM64_SW_TTB <<
1421 help <<
1422 Enable support for a 52-bit physica <<
1423 part of the ARMv8.2-LPA extension. <<
1424 <<
1425 With this enabled, the kernel will <<
1426 do not support ARMv8.2-LPA, but wit <<
1427 minor performance overhead). <<
1428 2225
1429 endchoice !! 2226 config IP22_CPU_SCACHE
>> 2227 bool
>> 2228 select BOARD_SCACHE
1430 2229
1431 config ARM64_PA_BITS !! 2230 #
1432 int !! 2231 # Support for a MIPS32 / MIPS64 style S-caches
1433 default 48 if ARM64_PA_BITS_48 !! 2232 #
1434 default 52 if ARM64_PA_BITS_52 !! 2233 config MIPS_CPU_SCACHE
>> 2234 bool
>> 2235 select BOARD_SCACHE
1435 2236
1436 config ARM64_LPA2 !! 2237 config R5000_CPU_SCACHE
1437 def_bool y !! 2238 bool
1438 depends on ARM64_PA_BITS_52 && !ARM64 !! 2239 select BOARD_SCACHE
1439 2240
1440 choice !! 2241 config RM7000_CPU_SCACHE
1441 prompt "Endianness" !! 2242 bool
1442 default CPU_LITTLE_ENDIAN !! 2243 select BOARD_SCACHE
1443 help <<
1444 Select the endianness of data acces <<
1445 applications will need to be compil <<
1446 that is selected here. <<
1447 2244
1448 config CPU_BIG_ENDIAN !! 2245 config SIBYTE_DMA_PAGEOPS
1449 bool "Build big-endian kernel" !! 2246 bool "Use DMA to clear/copy pages"
1450 # https://github.com/llvm/llvm-projec !! 2247 depends on CPU_SB1
1451 depends on AS_IS_GNU || AS_VERSION >= <<
1452 help 2248 help
1453 Say Y if you plan on running a kern !! 2249 Instead of using the CPU to zero and copy pages, use a Data Mover
>> 2250 channel. These DMA channels are otherwise unused by the standard
>> 2251 SiByte Linux port. Seems to give a small performance benefit.
1454 2252
1455 config CPU_LITTLE_ENDIAN !! 2253 config CPU_HAS_PREFETCH
1456 bool "Build little-endian kernel" !! 2254 bool
1457 help <<
1458 Say Y if you plan on running a kern <<
1459 This is usually the case for distri <<
1460 2255
1461 endchoice !! 2256 config CPU_GENERIC_DUMP_TLB
>> 2257 bool
>> 2258 default y if !(CPU_R3000 || CPU_R8000 || CPU_TX39XX)
1462 2259
1463 config SCHED_MC !! 2260 config CPU_R4K_FPU
1464 bool "Multi-core scheduler support" !! 2261 bool
1465 help !! 2262 default y if !(CPU_R3000 || CPU_TX39XX)
1466 Multi-core scheduler support improv <<
1467 making when dealing with multi-core <<
1468 increased overhead in some places. <<
1469 2263
1470 config SCHED_CLUSTER !! 2264 config CPU_R4K_CACHE_TLB
1471 bool "Cluster scheduler support" !! 2265 bool
1472 help !! 2266 default y if !(CPU_R3000 || CPU_R8000 || CPU_SB1 || CPU_TX39XX || CPU_CAVIUM_OCTEON)
1473 Cluster scheduler support improves !! 2267
1474 making when dealing with machines t !! 2268 config MIPS_MT_SMP
1475 Cluster usually means a couple of C !! 2269 bool "MIPS MT SMP support (1 TC on each available VPE)"
1476 by sharing mid-level caches, last-l !! 2270 default y
1477 busses. !! 2271 depends on SYS_SUPPORTS_MULTITHREADING && !CPU_MIPSR6 && !CPU_MICROMIPS
>> 2272 select CPU_MIPSR2_IRQ_VI
>> 2273 select CPU_MIPSR2_IRQ_EI
>> 2274 select SYNC_R4K
>> 2275 select MIPS_MT
>> 2276 select SMP
>> 2277 select SMP_UP
>> 2278 select SYS_SUPPORTS_SMP
>> 2279 select SYS_SUPPORTS_SCHED_SMT
>> 2280 select MIPS_PERF_SHARED_TC_COUNTERS
>> 2281 help
>> 2282 This is a kernel model which is known as SMVP. This is supported
>> 2283 on cores with the MT ASE and uses the available VPEs to implement
>> 2284 virtual processors which supports SMP. This is equivalent to the
>> 2285 Intel Hyperthreading feature. For further information go to
>> 2286 <http://www.imgtec.com/mips/mips-multithreading.asp>.
>> 2287
>> 2288 config MIPS_MT
>> 2289 bool
1478 2290
1479 config SCHED_SMT 2291 config SCHED_SMT
1480 bool "SMT scheduler support" !! 2292 bool "SMT (multithreading) scheduler support"
>> 2293 depends on SYS_SUPPORTS_SCHED_SMT
>> 2294 default n
1481 help 2295 help
1482 Improves the CPU scheduler's decisi !! 2296 SMT scheduler support improves the CPU scheduler's decision making
1483 MultiThreading at a cost of slightl !! 2297 when dealing with MIPS MT enabled cores at a cost of slightly
1484 places. If unsure say N here. !! 2298 increased overhead in some places. If unsure say N here.
1485 2299
1486 config NR_CPUS !! 2300 config SYS_SUPPORTS_SCHED_SMT
1487 int "Maximum number of CPUs (2-4096)" !! 2301 bool
1488 range 2 4096 <<
1489 default "512" <<
1490 2302
1491 config HOTPLUG_CPU !! 2303 config SYS_SUPPORTS_MULTITHREADING
1492 bool "Support for hot-pluggable CPUs" !! 2304 bool
1493 select GENERIC_IRQ_MIGRATION <<
1494 help <<
1495 Say Y here to experiment with turni <<
1496 can be controlled through /sys/devi <<
1497 2305
1498 # Common NUMA Features !! 2306 config MIPS_MT_FPAFF
1499 config NUMA !! 2307 bool "Dynamic FPU affinity for FP-intensive threads"
1500 bool "NUMA Memory Allocation and Sche !! 2308 default y
1501 select GENERIC_ARCH_NUMA !! 2309 depends on MIPS_MT_SMP
1502 select OF_NUMA <<
1503 select HAVE_SETUP_PER_CPU_AREA <<
1504 select NEED_PER_CPU_EMBED_FIRST_CHUNK <<
1505 select NEED_PER_CPU_PAGE_FIRST_CHUNK <<
1506 select USE_PERCPU_NUMA_NODE_ID <<
1507 help <<
1508 Enable NUMA (Non-Uniform Memory Acc <<
1509 <<
1510 The kernel will try to allocate mem <<
1511 local memory of the CPU and add som <<
1512 NUMA awareness to the kernel. <<
1513 2310
1514 config NODES_SHIFT !! 2311 config MIPSR2_TO_R6_EMULATOR
1515 int "Maximum NUMA Nodes (as a power o !! 2312 bool "MIPS R2-to-R6 emulator"
1516 range 1 10 !! 2313 depends on CPU_MIPSR6
1517 default "4" !! 2314 default y
1518 depends on NUMA <<
1519 help 2315 help
1520 Specify the maximum number of NUMA !! 2316 Choose this option if you want to run non-R6 MIPS userland code.
1521 system. Increases memory reserved !! 2317 Even if you say 'Y' here, the emulator will still be disabled by
>> 2318 default. You can enable it using the 'mipsr2emu' kernel option.
>> 2319 The only reason this is a build-time option is to save ~14K from the
>> 2320 final kernel image.
1522 2321
1523 source "kernel/Kconfig.hz" !! 2322 config SYS_SUPPORTS_VPE_LOADER
1524 !! 2323 bool
1525 config ARCH_SPARSEMEM_ENABLE !! 2324 depends on SYS_SUPPORTS_MULTITHREADING
1526 def_bool y !! 2325 help
1527 select SPARSEMEM_VMEMMAP_ENABLE !! 2326 Indicates that the platform supports the VPE loader, and provides
1528 select SPARSEMEM_VMEMMAP !! 2327 physical_memsize.
1529 2328
1530 config HW_PERF_EVENTS !! 2329 config MIPS_VPE_LOADER
1531 def_bool y !! 2330 bool "VPE loader support."
1532 depends on ARM_PMU !! 2331 depends on SYS_SUPPORTS_VPE_LOADER && MODULES
>> 2332 select CPU_MIPSR2_IRQ_VI
>> 2333 select CPU_MIPSR2_IRQ_EI
>> 2334 select MIPS_MT
>> 2335 help
>> 2336 Includes a loader for loading an elf relocatable object
>> 2337 onto another VPE and running it.
1533 2338
1534 # Supported by clang >= 7.0 or GCC >= 12.0.0 !! 2339 config MIPS_VPE_LOADER_CMP
1535 config CC_HAVE_SHADOW_CALL_STACK !! 2340 bool
1536 def_bool $(cc-option, -fsanitize=shad !! 2341 default "y"
>> 2342 depends on MIPS_VPE_LOADER && MIPS_CMP
1537 2343
1538 config PARAVIRT !! 2344 config MIPS_VPE_LOADER_MT
1539 bool "Enable paravirtualization code" !! 2345 bool
1540 help !! 2346 default "y"
1541 This changes the kernel so it can m !! 2347 depends on MIPS_VPE_LOADER && !MIPS_CMP
1542 under a hypervisor, potentially imp <<
1543 over full virtualization. <<
1544 2348
1545 config PARAVIRT_TIME_ACCOUNTING !! 2349 config MIPS_VPE_LOADER_TOM
1546 bool "Paravirtual steal time accounti !! 2350 bool "Load VPE program into memory hidden from linux"
1547 select PARAVIRT !! 2351 depends on MIPS_VPE_LOADER
>> 2352 default y
1548 help 2353 help
1549 Select this option to enable fine g !! 2354 The loader can use memory that is present but has been hidden from
1550 accounting. Time spent executing ot !! 2355 Linux using the kernel command line option "mem=xxMB". It's up to
1551 the current vCPU is discounted from !! 2356 you to ensure the amount you put in the option and the space your
1552 that, there can be a small performa !! 2357 program requires is less or equal to the amount physically present.
1553 2358
1554 If in doubt, say N here. !! 2359 config MIPS_VPE_APSP_API
>> 2360 bool "Enable support for AP/SP API (RTLX)"
>> 2361 depends on MIPS_VPE_LOADER
1555 2362
1556 config ARCH_SUPPORTS_KEXEC !! 2363 config MIPS_VPE_APSP_API_CMP
1557 def_bool PM_SLEEP_SMP !! 2364 bool
>> 2365 default "y"
>> 2366 depends on MIPS_VPE_APSP_API && MIPS_CMP
1558 2367
1559 config ARCH_SUPPORTS_KEXEC_FILE !! 2368 config MIPS_VPE_APSP_API_MT
1560 def_bool y !! 2369 bool
>> 2370 default "y"
>> 2371 depends on MIPS_VPE_APSP_API && !MIPS_CMP
1561 2372
1562 config ARCH_SELECTS_KEXEC_FILE !! 2373 config MIPS_CMP
1563 def_bool y !! 2374 bool "MIPS CMP framework support (DEPRECATED)"
1564 depends on KEXEC_FILE !! 2375 depends on SYS_SUPPORTS_MIPS_CMP && !CPU_MIPSR6
1565 select HAVE_IMA_KEXEC if IMA !! 2376 select SMP
>> 2377 select SYNC_R4K
>> 2378 select SYS_SUPPORTS_SMP
>> 2379 select WEAK_ORDERING
>> 2380 default n
>> 2381 help
>> 2382 Select this if you are using a bootloader which implements the "CMP
>> 2383 framework" protocol (ie. YAMON) and want your kernel to make use of
>> 2384 its ability to start secondary CPUs.
>> 2385
>> 2386 Unless you have a specific need, you should use CONFIG_MIPS_CPS
>> 2387 instead of this.
>> 2388
>> 2389 config MIPS_CPS
>> 2390 bool "MIPS Coherent Processing System support"
>> 2391 depends on SYS_SUPPORTS_MIPS_CPS
>> 2392 select MIPS_CM
>> 2393 select MIPS_CPS_PM if HOTPLUG_CPU
>> 2394 select SMP
>> 2395 select SYNC_R4K if (CEVT_R4K || CSRC_R4K)
>> 2396 select SYS_SUPPORTS_HOTPLUG_CPU
>> 2397 select SYS_SUPPORTS_SCHED_SMT if CPU_MIPSR6
>> 2398 select SYS_SUPPORTS_SMP
>> 2399 select WEAK_ORDERING
>> 2400 help
>> 2401 Select this if you wish to run an SMP kernel across multiple cores
>> 2402 within a MIPS Coherent Processing System. When this option is
>> 2403 enabled the kernel will probe for other cores and boot them with
>> 2404 no external assistance. It is safe to enable this when hardware
>> 2405 support is unavailable.
1566 2406
1567 config ARCH_SUPPORTS_KEXEC_SIG !! 2407 config MIPS_CPS_PM
1568 def_bool y !! 2408 depends on MIPS_CPS
>> 2409 bool
1569 2410
1570 config ARCH_SUPPORTS_KEXEC_IMAGE_VERIFY_SIG !! 2411 config MIPS_CM
1571 def_bool y !! 2412 bool
>> 2413 select MIPS_CPC
1572 2414
1573 config ARCH_DEFAULT_KEXEC_IMAGE_VERIFY_SIG !! 2415 config MIPS_CPC
1574 def_bool y !! 2416 bool
1575 2417
1576 config ARCH_SUPPORTS_CRASH_DUMP !! 2418 config SB1_PASS_2_WORKAROUNDS
1577 def_bool y !! 2419 bool
>> 2420 depends on CPU_SB1 && (CPU_SB1_PASS_2_2 || CPU_SB1_PASS_2)
>> 2421 default y
1578 2422
1579 config ARCH_HAS_GENERIC_CRASHKERNEL_RESERVATI !! 2423 config SB1_PASS_2_1_WORKAROUNDS
1580 def_bool CRASH_RESERVE !! 2424 bool
>> 2425 depends on CPU_SB1 && CPU_SB1_PASS_2
>> 2426 default y
1581 2427
1582 config TRANS_TABLE <<
1583 def_bool y <<
1584 depends on HIBERNATION || KEXEC_CORE <<
1585 2428
1586 config XEN_DOM0 !! 2429 choice
1587 def_bool y !! 2430 prompt "SmartMIPS or microMIPS ASE support"
1588 depends on XEN <<
1589 2431
1590 config XEN !! 2432 config CPU_NEEDS_NO_SMARTMIPS_OR_MICROMIPS
1591 bool "Xen guest support on ARM64" !! 2433 bool "None"
1592 depends on ARM64 && OF <<
1593 select SWIOTLB_XEN <<
1594 select PARAVIRT <<
1595 help 2434 help
1596 Say Y if you want to run Linux in a !! 2435 Select this if you want neither microMIPS nor SmartMIPS support
1597 2436
1598 # include/linux/mmzone.h requires the followi !! 2437 config CPU_HAS_SMARTMIPS
1599 # !! 2438 depends on SYS_SUPPORTS_SMARTMIPS
1600 # MAX_PAGE_ORDER + PAGE_SHIFT <= SECTION_SI !! 2439 bool "SmartMIPS"
1601 # !! 2440 help
1602 # so the maximum value of MAX_PAGE_ORDER is S !! 2441 SmartMIPS is a extension of the MIPS32 architecture aimed at
1603 # !! 2442 increased security at both hardware and software level for
1604 # | SECTION_SIZE_BITS | PAGE_SHIFT | m !! 2443 smartcards. Enabling this option will allow proper use of the
1605 # ----+-------------------+--------------+--- !! 2444 SmartMIPS instructions by Linux applications. However a kernel with
1606 # 4K | 27 | 12 | !! 2445 this option will not work on a MIPS core without SmartMIPS core. If
1607 # 16K | 27 | 14 | !! 2446 you don't know you probably don't have SmartMIPS and should say N
1608 # 64K | 29 | 16 | !! 2447 here.
1609 config ARCH_FORCE_MAX_ORDER !! 2448
1610 int !! 2449 config CPU_MICROMIPS
1611 default "13" if ARM64_64K_PAGES !! 2450 depends on 32BIT && SYS_SUPPORTS_MICROMIPS && !CPU_MIPSR6
1612 default "11" if ARM64_16K_PAGES !! 2451 bool "microMIPS"
1613 default "10" <<
1614 help 2452 help
1615 The kernel page allocator limits th !! 2453 When this option is enabled the kernel will be built using the
1616 contiguous allocations. The limit i !! 2454 microMIPS ISA
1617 defines the maximal power of two of <<
1618 allocated as a single contiguous bl <<
1619 overriding the default setting when <<
1620 large blocks of physically contiguo <<
1621 <<
1622 The maximal size of allocation cann <<
1623 section, so the value of MAX_PAGE_O <<
1624 <<
1625 MAX_PAGE_ORDER + PAGE_SHIFT <= SE <<
1626 2455
1627 Don't change if unsure. !! 2456 endchoice
1628 2457
1629 config UNMAP_KERNEL_AT_EL0 !! 2458 config CPU_HAS_MSA
1630 bool "Unmap kernel when running in us !! 2459 bool "Support for the MIPS SIMD Architecture"
1631 default y !! 2460 depends on CPU_SUPPORTS_MSA
1632 help !! 2461 depends on 64BIT || MIPS_O32_FP64_SUPPORT
1633 Speculation attacks against some hi !! 2462 help
1634 be used to bypass MMU permission ch !! 2463 MIPS SIMD Architecture (MSA) introduces 128 bit wide vector registers
1635 userspace. This can be defended aga !! 2464 and a set of SIMD instructions to operate on them. When this option
1636 when running in userspace, mapping !! 2465 is enabled the kernel will support allocating & switching MSA
1637 via a trampoline page in the vector !! 2466 vector register contexts. If you know that your kernel will only be
>> 2467 running on CPUs which do not support MSA or that your userland will
>> 2468 not be making use of it then you may wish to say N here to reduce
>> 2469 the size & complexity of your kernel.
1638 2470
1639 If unsure, say Y. 2471 If unsure, say Y.
1640 2472
1641 config MITIGATE_SPECTRE_BRANCH_HISTORY !! 2473 config CPU_HAS_WB
1642 bool "Mitigate Spectre style attacks !! 2474 bool
1643 default y <<
1644 help <<
1645 Speculation attacks against some hi <<
1646 make use of branch history to influ <<
1647 When taking an exception from user- <<
1648 or a firmware call overwrites the b <<
1649 2475
1650 config RODATA_FULL_DEFAULT_ENABLED !! 2476 config XKS01
1651 bool "Apply r/o permissions of VM are !! 2477 bool
1652 default y <<
1653 help <<
1654 Apply read-only attributes of VM ar <<
1655 the backing pages as well. This pre <<
1656 from being modified (inadvertently <<
1657 mapping of the same memory page. Th <<
1658 be turned off at runtime by passing <<
1659 with rodata=full if this option is <<
1660 2478
1661 This requires the linear region to !! 2479 config CPU_HAS_RIXI
1662 which may adversely affect performa !! 2480 bool
1663 2481
1664 config ARM64_SW_TTBR0_PAN !! 2482 config CPU_HAS_LOAD_STORE_LR
1665 bool "Emulate Privileged Access Never !! 2483 bool
1666 depends on !KCSAN <<
1667 help 2484 help
1668 Enabling this option prevents the k !! 2485 CPU has support for unaligned load and store instructions:
1669 user-space memory directly by point !! 2486 LWL, LWR, SWL, SWR (Load/store word left/right).
1670 zeroed area and reserved ASID. The !! 2487 LDL, LDR, SDL, SDR (Load/store doubleword left/right, for 64bit systems).
1671 restore the valid TTBR0_EL1 tempora <<
1672 2488
1673 config ARM64_TAGGED_ADDR_ABI !! 2489 #
1674 bool "Enable the tagged user addresse !! 2490 # Vectored interrupt mode is an R2 feature
1675 default y !! 2491 #
1676 help !! 2492 config CPU_MIPSR2_IRQ_VI
1677 When this option is enabled, user a !! 2493 bool
1678 relaxed ABI via prctl() allowing ta <<
1679 to system calls as pointer argument <<
1680 Documentation/arch/arm64/tagged-add <<
1681 2494
1682 menuconfig COMPAT !! 2495 #
1683 bool "Kernel support for 32-bit EL0" !! 2496 # Extended interrupt mode is an R2 feature
1684 depends on ARM64_4K_PAGES || EXPERT !! 2497 #
1685 select HAVE_UID16 !! 2498 config CPU_MIPSR2_IRQ_EI
1686 select OLD_SIGSUSPEND3 !! 2499 bool
1687 select COMPAT_OLD_SIGACTION <<
1688 help <<
1689 This option enables support for a 3 <<
1690 kernel at EL1. AArch32-specific com <<
1691 the user helper functions, VFP supp <<
1692 handled appropriately by the kernel <<
1693 2500
1694 If you use a page size other than 4 !! 2501 config CPU_HAS_SYNC
1695 that you will only be able to execu !! 2502 bool
1696 with page size aligned segments. !! 2503 depends on !CPU_R3000
>> 2504 default y
1697 2505
1698 If you want to execute 32-bit users !! 2506 #
>> 2507 # CPU non-features
>> 2508 #
>> 2509 config CPU_DADDI_WORKAROUNDS
>> 2510 bool
1699 2511
1700 if COMPAT !! 2512 config CPU_R4000_WORKAROUNDS
>> 2513 bool
>> 2514 select CPU_R4400_WORKAROUNDS
1701 2515
1702 config KUSER_HELPERS !! 2516 config CPU_R4400_WORKAROUNDS
1703 bool "Enable kuser helpers page for 3 !! 2517 bool
1704 default y <<
1705 help <<
1706 Warning: disabling this option may <<
1707 2518
1708 Provide kuser helpers to compat tas !! 2519 config MIPS_ASID_SHIFT
1709 helper code to userspace in read on !! 2520 int
1710 to allow userspace to be independen !! 2521 default 6 if CPU_R3000 || CPU_TX39XX
1711 the system. This permits binaries t !! 2522 default 4 if CPU_R8000
1712 to ARMv8 without modification. !! 2523 default 0
1713 2524
1714 See Documentation/arch/arm/kernel_u !! 2525 config MIPS_ASID_BITS
>> 2526 int
>> 2527 default 0 if MIPS_ASID_BITS_VARIABLE
>> 2528 default 6 if CPU_R3000 || CPU_TX39XX
>> 2529 default 8
1715 2530
1716 However, the fixed address nature o !! 2531 config MIPS_ASID_BITS_VARIABLE
1717 by ROP (return orientated programmi !! 2532 bool
1718 exploits. <<
1719 2533
1720 If all of the binaries and librarie !! 2534 config MIPS_CRC_SUPPORT
1721 are built specifically for your pla !! 2535 bool
1722 these helpers, then you can turn th <<
1723 such exploits. However, in that cas <<
1724 relying on those helpers is run, it <<
1725 2536
1726 Say N here only if you are absolute !! 2537 #
1727 need these helpers; otherwise, the !! 2538 # - Highmem only makes sense for the 32-bit kernel.
>> 2539 # - The current highmem code will only work properly on physically indexed
>> 2540 # caches such as R3000, SB1, R7000 or those that look like they're virtually
>> 2541 # indexed such as R4000/R4400 SC and MC versions or R10000. So for the
>> 2542 # moment we protect the user and offer the highmem option only on machines
>> 2543 # where it's known to be safe. This will not offer highmem on a few systems
>> 2544 # such as MIPS32 and MIPS64 CPUs which may have virtual and physically
>> 2545 # indexed CPUs but we're playing safe.
>> 2546 # - We use SYS_SUPPORTS_HIGHMEM to offer highmem only for systems where we
>> 2547 # know they might have memory configurations that could make use of highmem
>> 2548 # support.
>> 2549 #
>> 2550 config HIGHMEM
>> 2551 bool "High Memory Support"
>> 2552 depends on 32BIT && CPU_SUPPORTS_HIGHMEM && SYS_SUPPORTS_HIGHMEM && !CPU_MIPS32_3_5_EVA
1728 2553
1729 config COMPAT_VDSO !! 2554 config CPU_SUPPORTS_HIGHMEM
1730 bool "Enable vDSO for 32-bit applicat !! 2555 bool
1731 depends on !CPU_BIG_ENDIAN <<
1732 depends on (CC_IS_CLANG && LD_IS_LLD) <<
1733 select GENERIC_COMPAT_VDSO <<
1734 default y <<
1735 help <<
1736 Place in the process address space <<
1737 ELF shared object providing fast im <<
1738 and clock_gettime. <<
1739 2556
1740 You must have a 32-bit build of gli !! 2557 config SYS_SUPPORTS_HIGHMEM
1741 to seamlessly take advantage of thi !! 2558 bool
1742 2559
1743 config THUMB2_COMPAT_VDSO !! 2560 config SYS_SUPPORTS_SMARTMIPS
1744 bool "Compile the 32-bit vDSO for Thu !! 2561 bool
1745 depends on COMPAT_VDSO <<
1746 default y <<
1747 help <<
1748 Compile the compat vDSO with '-mthu <<
1749 otherwise with '-marm'. <<
1750 2562
1751 config COMPAT_ALIGNMENT_FIXUPS !! 2563 config SYS_SUPPORTS_MICROMIPS
1752 bool "Fix up misaligned multi-word lo !! 2564 bool
1753 2565
1754 menuconfig ARMV8_DEPRECATED !! 2566 config SYS_SUPPORTS_MIPS16
1755 bool "Emulate deprecated/obsolete ARM !! 2567 bool
1756 depends on SYSCTL <<
1757 help 2568 help
1758 Legacy software support may require !! 2569 This option must be set if a kernel might be executed on a MIPS16-
1759 that have been deprecated or obsole !! 2570 enabled CPU even if MIPS16 is not actually being used. In other
1760 !! 2571 words, it makes the kernel MIPS16-tolerant.
1761 Enable this config to enable select <<
1762 features. <<
1763 2572
1764 If unsure, say Y !! 2573 config CPU_SUPPORTS_MSA
>> 2574 bool
1765 2575
1766 if ARMV8_DEPRECATED !! 2576 config ARCH_FLATMEM_ENABLE
>> 2577 def_bool y
>> 2578 depends on !NUMA && !CPU_LOONGSON2
1767 2579
1768 config SWP_EMULATION !! 2580 config ARCH_DISCONTIGMEM_ENABLE
1769 bool "Emulate SWP/SWPB instructions" !! 2581 bool
>> 2582 default y if SGI_IP27
1770 help 2583 help
1771 ARMv8 obsoletes the use of A32 SWP/ !! 2584 Say Y to support efficient handling of discontiguous physical memory,
1772 they are always undefined. Say Y he !! 2585 for architectures which are either NUMA (Non-Uniform Memory Access)
1773 emulation of these instructions for !! 2586 or have huge holes in the physical address space for other reasons.
1774 This feature can be controlled at r !! 2587 See <file:Documentation/vm/numa.rst> for more.
1775 sysctl which is disabled by default <<
1776 2588
1777 In some older versions of glibc [<= !! 2589 config ARCH_SPARSEMEM_ENABLE
1778 trylock() operations with the assum !! 2590 bool
1779 be preempted. This invalid assumpti !! 2591 select SPARSEMEM_STATIC
1780 with SWP emulation enabled, leading <<
1781 application. <<
1782 2592
1783 NOTE: when accessing uncached share !! 2593 config NUMA
1784 on an external transaction monitori !! 2594 bool "NUMA Support"
1785 monitor to maintain update atomicit !! 2595 depends on SYS_SUPPORTS_NUMA
1786 implement a global monitor, this op !! 2596 help
1787 perform SWP operations to uncached !! 2597 Say Y to compile the kernel to support NUMA (Non-Uniform Memory
>> 2598 Access). This option improves performance on systems with more
>> 2599 than two nodes; on two node systems it is generally better to
>> 2600 leave it disabled; on single node systems disable this option
>> 2601 disabled.
1788 2602
1789 If unsure, say Y !! 2603 config SYS_SUPPORTS_NUMA
>> 2604 bool
1790 2605
1791 config CP15_BARRIER_EMULATION !! 2606 config RELOCATABLE
1792 bool "Emulate CP15 Barrier instructio !! 2607 bool "Relocatable kernel"
>> 2608 depends on SYS_SUPPORTS_RELOCATABLE && (CPU_MIPS32_R2 || CPU_MIPS64_R2 || CPU_MIPS32_R6 || CPU_MIPS64_R6 || CAVIUM_OCTEON_SOC)
1793 help 2609 help
1794 The CP15 barrier instructions - CP1 !! 2610 This builds a kernel image that retains relocation information
1795 CP15DMB - are deprecated in ARMv8 ( !! 2611 so it can be loaded someplace besides the default 1MB.
1796 strongly recommended to use the ISB !! 2612 The relocations make the kernel binary about 15% larger,
1797 instructions instead. !! 2613 but are discarded at runtime
>> 2614
>> 2615 config RELOCATION_TABLE_SIZE
>> 2616 hex "Relocation table size"
>> 2617 depends on RELOCATABLE
>> 2618 range 0x0 0x01000000
>> 2619 default "0x00100000"
>> 2620 ---help---
>> 2621 A table of relocation data will be appended to the kernel binary
>> 2622 and parsed at boot to fix up the relocated kernel.
1798 2623
1799 Say Y here to enable software emula !! 2624 This option allows the amount of space reserved for the table to be
1800 instructions for AArch32 userspace !! 2625 adjusted, although the default of 1Mb should be ok in most cases.
1801 enabled, CP15 barrier usage is trac <<
1802 identify software that needs updati <<
1803 controlled at runtime with the abi. <<
1804 2626
1805 If unsure, say Y !! 2627 The build will fail and a valid size suggested if this is too small.
1806 2628
1807 config SETEND_EMULATION !! 2629 If unsure, leave at the default value.
1808 bool "Emulate SETEND instruction" <<
1809 help <<
1810 The SETEND instruction alters the d <<
1811 AArch32 EL0, and is deprecated in A <<
1812 2630
1813 Say Y here to enable software emula !! 2631 config RANDOMIZE_BASE
1814 for AArch32 userspace code. This fe !! 2632 bool "Randomize the address of the kernel image"
1815 at runtime with the abi.setend sysc !! 2633 depends on RELOCATABLE
>> 2634 ---help---
>> 2635 Randomizes the physical and virtual address at which the
>> 2636 kernel image is loaded, as a security feature that
>> 2637 deters exploit attempts relying on knowledge of the location
>> 2638 of kernel internals.
1816 2639
1817 Note: All the cpus on the system mu !! 2640 Entropy is generated using any coprocessor 0 registers available.
1818 for this feature to be enabled. If <<
1819 endian - is hotplugged in after thi <<
1820 be unexpected results in the applic <<
1821 2641
1822 If unsure, say Y !! 2642 The kernel will be offset by up to RANDOMIZE_BASE_MAX_OFFSET.
1823 endif # ARMV8_DEPRECATED <<
1824 2643
1825 endif # COMPAT !! 2644 If unsure, say N.
1826 2645
1827 menu "ARMv8.1 architectural features" !! 2646 config RANDOMIZE_BASE_MAX_OFFSET
>> 2647 hex "Maximum kASLR offset" if EXPERT
>> 2648 depends on RANDOMIZE_BASE
>> 2649 range 0x0 0x40000000 if EVA || 64BIT
>> 2650 range 0x0 0x08000000
>> 2651 default "0x01000000"
>> 2652 ---help---
>> 2653 When kASLR is active, this provides the maximum offset that will
>> 2654 be applied to the kernel image. It should be set according to the
>> 2655 amount of physical RAM available in the target system minus
>> 2656 PHYSICAL_START and must be a power of 2.
1828 2657
1829 config ARM64_HW_AFDBM !! 2658 This is limited by the size of KSEG0, 256Mb on 32-bit or 1Gb with
1830 bool "Support for hardware updates of !! 2659 EVA or 64-bit. The default is 16Mb.
1831 default y <<
1832 help <<
1833 The ARMv8.1 architecture extensions <<
1834 hardware updates of the access and <<
1835 table entries. When enabled in TCR_ <<
1836 capable processors, accesses to pag <<
1837 set this bit instead of raising an <<
1838 Similarly, writes to read-only page <<
1839 clear the read-only bit (AP[2]) ins <<
1840 permission fault. <<
1841 2660
1842 Kernels built with this configurati !! 2661 config NODES_SHIFT
1843 to work on pre-ARMv8.1 hardware and !! 2662 int
1844 minimal. If unsure, say Y. !! 2663 default "6"
>> 2664 depends on NEED_MULTIPLE_NODES
1845 2665
1846 config ARM64_PAN !! 2666 config HW_PERF_EVENTS
1847 bool "Enable support for Privileged A !! 2667 bool "Enable hardware performance counter support for perf events"
>> 2668 depends on PERF_EVENTS && !OPROFILE && (CPU_MIPS32 || CPU_MIPS64 || CPU_R10000 || CPU_SB1 || CPU_CAVIUM_OCTEON || CPU_XLP || CPU_LOONGSON3)
1848 default y 2669 default y
1849 help 2670 help
1850 Privileged Access Never (PAN; part !! 2671 Enable hardware performance counter support for perf events. If
1851 prevents the kernel or hypervisor f !! 2672 disabled, perf events will use software events only.
1852 memory directly. <<
1853 2673
1854 Choosing this option will cause any !! 2674 config SMP
1855 copy_to_user et al) memory access t !! 2675 bool "Multi-Processing support"
>> 2676 depends on SYS_SUPPORTS_SMP
>> 2677 help
>> 2678 This enables support for systems with more than one CPU. If you have
>> 2679 a system with only one CPU, say N. If you have a system with more
>> 2680 than one CPU, say Y.
>> 2681
>> 2682 If you say N here, the kernel will run on uni- and multiprocessor
>> 2683 machines, but will use only one CPU of a multiprocessor machine. If
>> 2684 you say Y here, the kernel will run on many, but not all,
>> 2685 uniprocessor machines. On a uniprocessor machine, the kernel
>> 2686 will run faster if you say N here.
1856 2687
1857 The feature is detected at runtime, !! 2688 People using multiprocessor machines who say Y here should also say
1858 instruction if the cpu does not imp !! 2689 Y to "Enhanced Real Time Clock Support", below.
1859 2690
1860 config AS_HAS_LSE_ATOMICS !! 2691 See also the SMP-HOWTO available at
1861 def_bool $(as-instr,.arch_extension l !! 2692 <http://www.tldp.org/docs.html#howto>.
1862 2693
1863 config ARM64_LSE_ATOMICS !! 2694 If you don't know what to do here, say N.
1864 bool <<
1865 default ARM64_USE_LSE_ATOMICS <<
1866 depends on AS_HAS_LSE_ATOMICS <<
1867 2695
1868 config ARM64_USE_LSE_ATOMICS !! 2696 config HOTPLUG_CPU
1869 bool "Atomic instructions" !! 2697 bool "Support for hot-pluggable CPUs"
1870 default y !! 2698 depends on SMP && SYS_SUPPORTS_HOTPLUG_CPU
1871 help 2699 help
1872 As part of the Large System Extensi !! 2700 Say Y here to allow turning CPUs off and on. CPUs can be
1873 atomic instructions that are design !! 2701 controlled through /sys/devices/system/cpu.
1874 very large systems. !! 2702 (Note: power management support will enable this option
>> 2703 automatically on SMP systems. )
>> 2704 Say N if you want to disable CPU hotplug.
1875 2705
1876 Say Y here to make use of these ins !! 2706 config SMP_UP
1877 atomic routines. This incurs a smal !! 2707 bool
1878 not support these instructions and <<
1879 built with binutils >= 2.25 in orde <<
1880 to be used. <<
1881 2708
1882 endmenu # "ARMv8.1 architectural features" !! 2709 config SYS_SUPPORTS_MIPS_CMP
>> 2710 bool
1883 2711
1884 menu "ARMv8.2 architectural features" !! 2712 config SYS_SUPPORTS_MIPS_CPS
>> 2713 bool
1885 2714
1886 config AS_HAS_ARMV8_2 !! 2715 config SYS_SUPPORTS_SMP
1887 def_bool $(cc-option,-Wa$(comma)-marc !! 2716 bool
1888 2717
1889 config AS_HAS_SHA3 !! 2718 config NR_CPUS_DEFAULT_4
1890 def_bool $(as-instr,.arch armv8.2-a+s !! 2719 bool
1891 2720
1892 config ARM64_PMEM !! 2721 config NR_CPUS_DEFAULT_8
1893 bool "Enable support for persistent m !! 2722 bool
1894 select ARCH_HAS_PMEM_API <<
1895 select ARCH_HAS_UACCESS_FLUSHCACHE <<
1896 help <<
1897 Say Y to enable support for the per <<
1898 ARMv8.2 DCPoP feature. <<
1899 2723
1900 The feature is detected at runtime, !! 2724 config NR_CPUS_DEFAULT_16
1901 operations if DC CVAP is not suppor !! 2725 bool
1902 DC CVAP itself if the system does n <<
1903 2726
1904 config ARM64_RAS_EXTN !! 2727 config NR_CPUS_DEFAULT_32
1905 bool "Enable support for RAS CPU Exte !! 2728 bool
1906 default y <<
1907 help <<
1908 CPUs that support the Reliability, <<
1909 (RAS) Extensions, part of ARMv8.2 a <<
1910 errors, classify them and report th <<
1911 2729
1912 On CPUs with these extensions syste !! 2730 config NR_CPUS_DEFAULT_64
1913 barriers to determine if faults are !! 2731 bool
1914 classification from a new set of re <<
1915 2732
1916 Selecting this feature will allow t !! 2733 config NR_CPUS
1917 and access the new registers if the !! 2734 int "Maximum number of CPUs (2-256)"
1918 Platform RAS features may additiona !! 2735 range 2 256
>> 2736 depends on SMP
>> 2737 default "4" if NR_CPUS_DEFAULT_4
>> 2738 default "8" if NR_CPUS_DEFAULT_8
>> 2739 default "16" if NR_CPUS_DEFAULT_16
>> 2740 default "32" if NR_CPUS_DEFAULT_32
>> 2741 default "64" if NR_CPUS_DEFAULT_64
>> 2742 help
>> 2743 This allows you to specify the maximum number of CPUs which this
>> 2744 kernel will support. The maximum supported value is 32 for 32-bit
>> 2745 kernel and 64 for 64-bit kernels; the minimum value which makes
>> 2746 sense is 1 for Qemu (useful only for kernel debugging purposes)
>> 2747 and 2 for all others.
>> 2748
>> 2749 This is purely to save memory - each supported CPU adds
>> 2750 approximately eight kilobytes to the kernel image. For best
>> 2751 performance should round up your number of processors to the next
>> 2752 power of two.
1919 2753
1920 config ARM64_CNP !! 2754 config MIPS_PERF_SHARED_TC_COUNTERS
1921 bool "Enable support for Common Not P !! 2755 bool
1922 default y <<
1923 depends on ARM64_PAN || !ARM64_SW_TTB <<
1924 help <<
1925 Common Not Private (CNP) allows tra <<
1926 be shared between different PEs in <<
1927 domain, so the hardware can use thi <<
1928 caching of such entries in the TLB. <<
1929 2756
1930 Selecting this option allows the CN !! 2757 config MIPS_NR_CPU_NR_MAP_1024
1931 at runtime, and does not affect PEs !! 2758 bool
1932 this feature. <<
1933 2759
1934 endmenu # "ARMv8.2 architectural features" !! 2760 config MIPS_NR_CPU_NR_MAP
>> 2761 int
>> 2762 depends on SMP
>> 2763 default 1024 if MIPS_NR_CPU_NR_MAP_1024
>> 2764 default NR_CPUS if !MIPS_NR_CPU_NR_MAP_1024
1935 2765
1936 menu "ARMv8.3 architectural features" !! 2766 #
>> 2767 # Timer Interrupt Frequency Configuration
>> 2768 #
1937 2769
1938 config ARM64_PTR_AUTH !! 2770 choice
1939 bool "Enable support for pointer auth !! 2771 prompt "Timer frequency"
1940 default y !! 2772 default HZ_250
1941 help 2773 help
1942 Pointer authentication (part of the !! 2774 Allows the configuration of the timer frequency.
1943 instructions for signing and authen <<
1944 keys, which can be used to mitigate <<
1945 and other attacks. <<
1946 2775
1947 This option enables these instructi !! 2776 config HZ_24
1948 Choosing this option will cause the !! 2777 bool "24 HZ" if SYS_SUPPORTS_24HZ || SYS_SUPPORTS_ARBIT_HZ
1949 for each process at exec() time, wi <<
1950 context-switched along with the pro <<
1951 2778
1952 The feature is detected at runtime. !! 2779 config HZ_48
1953 hardware it will not be advertised !! 2780 bool "48 HZ" if SYS_SUPPORTS_48HZ || SYS_SUPPORTS_ARBIT_HZ
1954 be enabled. <<
1955 2781
1956 If the feature is present on the bo !! 2782 config HZ_100
1957 the late CPU will be parked. Also, !! 2783 bool "100 HZ" if SYS_SUPPORTS_100HZ || SYS_SUPPORTS_ARBIT_HZ
1958 address auth and the late CPU has t <<
1959 but with the feature disabled. On s <<
1960 not be selected. <<
1961 2784
1962 config ARM64_PTR_AUTH_KERNEL !! 2785 config HZ_128
1963 bool "Use pointer authentication for !! 2786 bool "128 HZ" if SYS_SUPPORTS_128HZ || SYS_SUPPORTS_ARBIT_HZ
1964 default y <<
1965 depends on ARM64_PTR_AUTH <<
1966 depends on (CC_HAS_SIGN_RETURN_ADDRES <<
1967 # Modern compilers insert a .note.gnu <<
1968 # which is only understood by binutil <<
1969 depends on LD_IS_LLD || LD_VERSION >= <<
1970 depends on !CC_IS_CLANG || AS_HAS_CFI <<
1971 depends on (!FUNCTION_GRAPH_TRACER || <<
1972 help <<
1973 If the compiler supports the -mbran <<
1974 -msign-return-address flag (e.g. GC <<
1975 will cause the kernel itself to be <<
1976 protection. In this case, and if th <<
1977 support pointer authentication, the <<
1978 disabled with minimal loss of prote <<
1979 2787
1980 This feature works with FUNCTION_GR !! 2788 config HZ_250
1981 DYNAMIC_FTRACE_WITH_ARGS is enabled !! 2789 bool "250 HZ" if SYS_SUPPORTS_250HZ || SYS_SUPPORTS_ARBIT_HZ
1982 2790
1983 config CC_HAS_BRANCH_PROT_PAC_RET !! 2791 config HZ_256
1984 # GCC 9 or later, clang 8 or later !! 2792 bool "256 HZ" if SYS_SUPPORTS_256HZ || SYS_SUPPORTS_ARBIT_HZ
1985 def_bool $(cc-option,-mbranch-protect <<
1986 2793
1987 config CC_HAS_SIGN_RETURN_ADDRESS !! 2794 config HZ_1000
1988 # GCC 7, 8 !! 2795 bool "1000 HZ" if SYS_SUPPORTS_1000HZ || SYS_SUPPORTS_ARBIT_HZ
1989 def_bool $(cc-option,-msign-return-ad <<
1990 2796
1991 config AS_HAS_ARMV8_3 !! 2797 config HZ_1024
1992 def_bool $(cc-option,-Wa$(comma)-marc !! 2798 bool "1024 HZ" if SYS_SUPPORTS_1024HZ || SYS_SUPPORTS_ARBIT_HZ
1993 2799
1994 config AS_HAS_CFI_NEGATE_RA_STATE !! 2800 endchoice
1995 def_bool $(as-instr,.cfi_startproc\n. <<
1996 <<
1997 config AS_HAS_LDAPR <<
1998 def_bool $(as-instr,.arch_extension r <<
1999 2801
2000 endmenu # "ARMv8.3 architectural features" !! 2802 config SYS_SUPPORTS_24HZ
>> 2803 bool
2001 2804
2002 menu "ARMv8.4 architectural features" !! 2805 config SYS_SUPPORTS_48HZ
>> 2806 bool
2003 2807
2004 config ARM64_AMU_EXTN !! 2808 config SYS_SUPPORTS_100HZ
2005 bool "Enable support for the Activity !! 2809 bool
2006 default y <<
2007 help <<
2008 The activity monitors extension is <<
2009 by the ARMv8.4 CPU architecture. Th <<
2010 of the activity monitors architectu <<
2011 2810
2012 To enable the use of this extension !! 2811 config SYS_SUPPORTS_128HZ
>> 2812 bool
2013 2813
2014 Note that for architectural reasons !! 2814 config SYS_SUPPORTS_250HZ
2015 support when running on CPUs that p !! 2815 bool
2016 extension. The required support is <<
2017 * Version 1.5 and later of the AR <<
2018 2816
2019 For kernels that have this configur !! 2817 config SYS_SUPPORTS_256HZ
2020 firmware, you may need to say N her !! 2818 bool
2021 Otherwise you may experience firmwa <<
2022 accessing the counter registers. Ev <<
2023 symptoms, the values returned by th <<
2024 correctly reflect reality. Most com <<
2025 indicating that the counter is not <<
2026 2819
2027 config AS_HAS_ARMV8_4 !! 2820 config SYS_SUPPORTS_1000HZ
2028 def_bool $(cc-option,-Wa$(comma)-marc !! 2821 bool
2029 2822
2030 config ARM64_TLB_RANGE !! 2823 config SYS_SUPPORTS_1024HZ
2031 bool "Enable support for tlbi range f !! 2824 bool
2032 default y <<
2033 depends on AS_HAS_ARMV8_4 <<
2034 help <<
2035 ARMv8.4-TLBI provides TLBI invalida <<
2036 range of input addresses. <<
2037 2825
2038 The feature introduces new assembly !! 2826 config SYS_SUPPORTS_ARBIT_HZ
2039 support when binutils >= 2.30. !! 2827 bool
>> 2828 default y if !SYS_SUPPORTS_24HZ && \
>> 2829 !SYS_SUPPORTS_48HZ && \
>> 2830 !SYS_SUPPORTS_100HZ && \
>> 2831 !SYS_SUPPORTS_128HZ && \
>> 2832 !SYS_SUPPORTS_250HZ && \
>> 2833 !SYS_SUPPORTS_256HZ && \
>> 2834 !SYS_SUPPORTS_1000HZ && \
>> 2835 !SYS_SUPPORTS_1024HZ
2040 2836
2041 endmenu # "ARMv8.4 architectural features" !! 2837 config HZ
>> 2838 int
>> 2839 default 24 if HZ_24
>> 2840 default 48 if HZ_48
>> 2841 default 100 if HZ_100
>> 2842 default 128 if HZ_128
>> 2843 default 250 if HZ_250
>> 2844 default 256 if HZ_256
>> 2845 default 1000 if HZ_1000
>> 2846 default 1024 if HZ_1024
>> 2847
>> 2848 config SCHED_HRTICK
>> 2849 def_bool HIGH_RES_TIMERS
>> 2850
>> 2851 config KEXEC
>> 2852 bool "Kexec system call"
>> 2853 select KEXEC_CORE
>> 2854 help
>> 2855 kexec is a system call that implements the ability to shutdown your
>> 2856 current kernel, and to start another kernel. It is like a reboot
>> 2857 but it is independent of the system firmware. And like a reboot
>> 2858 you can start any kernel with it, not just Linux.
>> 2859
>> 2860 The name comes from the similarity to the exec system call.
>> 2861
>> 2862 It is an ongoing process to be certain the hardware in a machine
>> 2863 is properly shutdown, so do not be surprised if this code does not
>> 2864 initially work for you. As of this writing the exact hardware
>> 2865 interface is strongly in flux, so no good recommendation can be
>> 2866 made.
>> 2867
>> 2868 config CRASH_DUMP
>> 2869 bool "Kernel crash dumps"
>> 2870 help
>> 2871 Generate crash dump after being started by kexec.
>> 2872 This should be normally only set in special crash dump kernels
>> 2873 which are loaded in the main kernel with kexec-tools into
>> 2874 a specially reserved region and then later executed after
>> 2875 a crash by kdump/kexec. The crash dump kernel must be compiled
>> 2876 to a memory address not used by the main kernel or firmware using
>> 2877 PHYSICAL_START.
>> 2878
>> 2879 config PHYSICAL_START
>> 2880 hex "Physical address where the kernel is loaded"
>> 2881 default "0xffffffff84000000"
>> 2882 depends on CRASH_DUMP
>> 2883 help
>> 2884 This gives the CKSEG0 or KSEG0 address where the kernel is loaded.
>> 2885 If you plan to use kernel for capturing the crash dump change
>> 2886 this value to start of the reserved region (the "X" value as
>> 2887 specified in the "crashkernel=YM@XM" command line boot parameter
>> 2888 passed to the panic-ed kernel).
>> 2889
>> 2890 config SECCOMP
>> 2891 bool "Enable seccomp to safely compute untrusted bytecode"
>> 2892 depends on PROC_FS
>> 2893 default y
>> 2894 help
>> 2895 This kernel feature is useful for number crunching applications
>> 2896 that may need to compute untrusted bytecode during their
>> 2897 execution. By using pipes or other transports made available to
>> 2898 the process as file descriptors supporting the read/write
>> 2899 syscalls, it's possible to isolate those applications in
>> 2900 their own address space using seccomp. Once seccomp is
>> 2901 enabled via /proc/<pid>/seccomp, it cannot be disabled
>> 2902 and the task is only allowed to execute a few safe syscalls
>> 2903 defined by each seccomp mode.
>> 2904
>> 2905 If unsure, say Y. Only embedded should say N here.
>> 2906
>> 2907 config MIPS_O32_FP64_SUPPORT
>> 2908 bool "Support for O32 binaries using 64-bit FP"
>> 2909 depends on 32BIT || MIPS32_O32
>> 2910 help
>> 2911 When this is enabled, the kernel will support use of 64-bit floating
>> 2912 point registers with binaries using the O32 ABI along with the
>> 2913 EF_MIPS_FP64 ELF header flag (typically built with -mfp64). On
>> 2914 32-bit MIPS systems this support is at the cost of increasing the
>> 2915 size and complexity of the compiled FPU emulator. Thus if you are
>> 2916 running a MIPS32 system and know that none of your userland binaries
>> 2917 will require 64-bit floating point, you may wish to reduce the size
>> 2918 of your kernel & potentially improve FP emulation performance by
>> 2919 saying N here.
>> 2920
>> 2921 Although binutils currently supports use of this flag the details
>> 2922 concerning its effect upon the O32 ABI in userland are still being
>> 2923 worked on. In order to avoid userland becoming dependant upon current
>> 2924 behaviour before the details have been finalised, this option should
>> 2925 be considered experimental and only enabled by those working upon
>> 2926 said details.
2042 2927
2043 menu "ARMv8.5 architectural features" !! 2928 If unsure, say N.
2044 2929
2045 config AS_HAS_ARMV8_5 !! 2930 config USE_OF
2046 def_bool $(cc-option,-Wa$(comma)-marc !! 2931 bool
>> 2932 select OF
>> 2933 select OF_EARLY_FLATTREE
>> 2934 select IRQ_DOMAIN
2047 2935
2048 config ARM64_BTI !! 2936 config UHI_BOOT
2049 bool "Branch Target Identification su !! 2937 bool
2050 default y <<
2051 help <<
2052 Branch Target Identification (part <<
2053 provides a mechanism to limit the s <<
2054 branch instructions such as BR or B <<
2055 2938
2056 To make use of BTI on CPUs that sup !! 2939 config BUILTIN_DTB
>> 2940 bool
2057 2941
2058 BTI is intended to provide compleme !! 2942 choice
2059 flow integrity protection mechanism !! 2943 prompt "Kernel appended dtb support" if USE_OF
2060 authentication mechanism provided a !! 2944 default MIPS_NO_APPENDED_DTB
2061 For this reason, it does not make s <<
2062 also enabling support for pointer a <<
2063 enabling this option you should als <<
2064 2945
2065 Userspace binaries must also be spe !! 2946 config MIPS_NO_APPENDED_DTB
2066 this mechanism. If you say N here !! 2947 bool "None"
2067 BTI, such binaries can still run, b !! 2948 help
2068 enforcement of branch destinations. !! 2949 Do not enable appended dtb support.
>> 2950
>> 2951 config MIPS_ELF_APPENDED_DTB
>> 2952 bool "vmlinux"
>> 2953 help
>> 2954 With this option, the boot code will look for a device tree binary
>> 2955 DTB) included in the vmlinux ELF section .appended_dtb. By default
>> 2956 it is empty and the DTB can be appended using binutils command
>> 2957 objcopy:
>> 2958
>> 2959 objcopy --update-section .appended_dtb=<filename>.dtb vmlinux
>> 2960
>> 2961 This is meant as a backward compatiblity convenience for those
>> 2962 systems with a bootloader that can't be upgraded to accommodate
>> 2963 the documented boot protocol using a device tree.
>> 2964
>> 2965 config MIPS_RAW_APPENDED_DTB
>> 2966 bool "vmlinux.bin or vmlinuz.bin"
>> 2967 help
>> 2968 With this option, the boot code will look for a device tree binary
>> 2969 DTB) appended to raw vmlinux.bin or vmlinuz.bin.
>> 2970 (e.g. cat vmlinux.bin <filename>.dtb > vmlinux_w_dtb).
>> 2971
>> 2972 This is meant as a backward compatibility convenience for those
>> 2973 systems with a bootloader that can't be upgraded to accommodate
>> 2974 the documented boot protocol using a device tree.
>> 2975
>> 2976 Beware that there is very little in terms of protection against
>> 2977 this option being confused by leftover garbage in memory that might
>> 2978 look like a DTB header after a reboot if no actual DTB is appended
>> 2979 to vmlinux.bin. Do not leave this option active in a production kernel
>> 2980 if you don't intend to always append a DTB.
>> 2981 endchoice
2069 2982
2070 config ARM64_BTI_KERNEL !! 2983 choice
2071 bool "Use Branch Target Identificatio !! 2984 prompt "Kernel command line type" if !CMDLINE_OVERRIDE
2072 default y !! 2985 default MIPS_CMDLINE_FROM_DTB if USE_OF && !ATH79 && !MACH_INGENIC && \
2073 depends on ARM64_BTI !! 2986 !MIPS_MALTA && \
2074 depends on ARM64_PTR_AUTH_KERNEL !! 2987 !CAVIUM_OCTEON_SOC
2075 depends on CC_HAS_BRANCH_PROT_PAC_RET !! 2988 default MIPS_CMDLINE_FROM_BOOTLOADER
2076 # https://gcc.gnu.org/bugzilla/show_b !! 2989
2077 depends on !CC_IS_GCC || GCC_VERSION !! 2990 config MIPS_CMDLINE_FROM_DTB
2078 # https://gcc.gnu.org/bugzilla/show_b !! 2991 depends on USE_OF
2079 depends on !CC_IS_GCC !! 2992 bool "Dtb kernel arguments if available"
2080 depends on (!FUNCTION_GRAPH_TRACER || !! 2993
2081 help !! 2994 config MIPS_CMDLINE_DTB_EXTEND
2082 Build the kernel with Branch Target !! 2995 depends on USE_OF
2083 and enable enforcement of this for !! 2996 bool "Extend dtb kernel arguments with bootloader arguments"
2084 is enabled and the system supports !! 2997
2085 modular code must have BTI enabled. !! 2998 config MIPS_CMDLINE_FROM_BOOTLOADER
>> 2999 bool "Bootloader kernel arguments if available"
>> 3000
>> 3001 config MIPS_CMDLINE_BUILTIN_EXTEND
>> 3002 depends on CMDLINE_BOOL
>> 3003 bool "Extend builtin kernel arguments with bootloader arguments"
>> 3004 endchoice
2086 3005
2087 config CC_HAS_BRANCH_PROT_PAC_RET_BTI !! 3006 endmenu
2088 # GCC 9 or later, clang 8 or later <<
2089 def_bool $(cc-option,-mbranch-protect <<
2090 3007
2091 config ARM64_E0PD !! 3008 config LOCKDEP_SUPPORT
2092 bool "Enable support for E0PD" !! 3009 bool
2093 default y 3010 default y
2094 help <<
2095 E0PD (part of the ARMv8.5 extension <<
2096 that EL0 accesses made via TTBR1 al <<
2097 providing similar benefits to KASLR <<
2098 with lower overhead and without dis <<
2099 kernel memory such as SPE. <<
2100 <<
2101 This option enables E0PD for TTBR1 <<
2102 <<
2103 config ARM64_AS_HAS_MTE <<
2104 # Initial support for MTE went in bin <<
2105 # ".arch armv8.5-a+memtag" below. How <<
2106 # as a late addition to the final arc <<
2107 # is only supported in the newer 2.32 <<
2108 # versions, hence the extra "stgm" in <<
2109 def_bool $(as-instr,.arch armv8.5-a+m <<
2110 3011
2111 config ARM64_MTE !! 3012 config STACKTRACE_SUPPORT
2112 bool "Memory Tagging Extension suppor !! 3013 bool
2113 default y 3014 default y
2114 depends on ARM64_AS_HAS_MTE && ARM64_ <<
2115 depends on AS_HAS_ARMV8_5 <<
2116 depends on AS_HAS_LSE_ATOMICS <<
2117 # Required for tag checking in the ua <<
2118 depends on ARM64_PAN <<
2119 select ARCH_HAS_SUBPAGE_FAULTS <<
2120 select ARCH_USES_HIGH_VMA_FLAGS <<
2121 select ARCH_USES_PG_ARCH_2 <<
2122 select ARCH_USES_PG_ARCH_3 <<
2123 help <<
2124 Memory Tagging (part of the ARMv8.5 <<
2125 architectural support for run-time, <<
2126 various classes of memory error to <<
2127 to eliminate vulnerabilities arisin <<
2128 languages. <<
2129 3015
2130 This option enables the support for !! 3016 config HAVE_LATENCYTOP_SUPPORT
2131 Extension at EL0 (i.e. for userspac !! 3017 bool
2132 <<
2133 Selecting this option allows the fe <<
2134 runtime. Any secondary CPU not impl <<
2135 not be allowed a late bring-up. <<
2136 <<
2137 Userspace binaries that want to use <<
2138 explicitly opt in. The mechanism fo <<
2139 described in: <<
2140 <<
2141 Documentation/arch/arm64/memory-tag <<
2142 <<
2143 endmenu # "ARMv8.5 architectural features" <<
2144 <<
2145 menu "ARMv8.7 architectural features" <<
2146 <<
2147 config ARM64_EPAN <<
2148 bool "Enable support for Enhanced Pri <<
2149 default y 3018 default y
2150 depends on ARM64_PAN <<
2151 help <<
2152 Enhanced Privileged Access Never (E <<
2153 Access Never to be used with Execut <<
2154 <<
2155 The feature is detected at runtime, <<
2156 if the cpu does not implement the f <<
2157 endmenu # "ARMv8.7 architectural features" <<
2158 3019
2159 menu "ARMv8.9 architectural features" !! 3020 config PGTABLE_LEVELS
2160 !! 3021 int
2161 config ARM64_POE !! 3022 default 4 if PAGE_SIZE_4KB && MIPS_VA_BITS_48
2162 prompt "Permission Overlay Extension" !! 3023 default 3 if 64BIT && !PAGE_SIZE_64KB
2163 def_bool y !! 3024 default 2
2164 select ARCH_USES_HIGH_VMA_FLAGS <<
2165 select ARCH_HAS_PKEYS <<
2166 help <<
2167 The Permission Overlay Extension is <<
2168 Protection Keys. Memory Protection <<
2169 enforcing page-based protections, b <<
2170 of the page tables when an applicat <<
2171 3025
2172 For details, see Documentation/core !! 3026 config MIPS_AUTO_PFN_OFFSET
>> 3027 bool
2173 3028
2174 If unsure, say y. !! 3029 menu "Bus options (PCI, PCMCIA, EISA, ISA, TC)"
2175 3030
2176 config ARCH_PKEY_BITS !! 3031 config HW_HAS_EISA
2177 int !! 3032 bool
2178 default 3 !! 3033 config HW_HAS_PCI
>> 3034 bool
2179 3035
2180 endmenu # "ARMv8.9 architectural features" !! 3036 config PCI
>> 3037 bool "Support for PCI controller"
>> 3038 depends on HW_HAS_PCI
>> 3039 select PCI_DOMAINS
>> 3040 help
>> 3041 Find out whether you have a PCI motherboard. PCI is the name of a
>> 3042 bus system, i.e. the way the CPU talks to the other stuff inside
>> 3043 your box. Other bus systems are ISA, EISA, or VESA. If you have PCI,
>> 3044 say Y, otherwise N.
>> 3045
>> 3046 config HT_PCI
>> 3047 bool "Support for HT-linked PCI"
>> 3048 default y
>> 3049 depends on CPU_LOONGSON3
>> 3050 select PCI
>> 3051 select PCI_DOMAINS
>> 3052 help
>> 3053 Loongson family machines use Hyper-Transport bus for inter-core
>> 3054 connection and device connection. The PCI bus is a subordinate
>> 3055 linked at HT. Choose Y for Loongson-3 based machines.
2181 3056
2182 config ARM64_SVE !! 3057 config PCI_DOMAINS
2183 bool "ARM Scalable Vector Extension s !! 3058 bool
2184 default y <<
2185 help <<
2186 The Scalable Vector Extension (SVE) <<
2187 execution state which complements a <<
2188 of the base architecture to support <<
2189 additional vectorisation opportunit <<
2190 3059
2191 To enable use of this extension on !! 3060 config PCI_DOMAINS_GENERIC
>> 3061 bool
2192 3062
2193 On CPUs that support the SVE2 exten !! 3063 config PCI_DRIVERS_GENERIC
2194 those too. !! 3064 select PCI_DOMAINS_GENERIC if PCI_DOMAINS
>> 3065 bool
2195 3066
2196 Note that for architectural reasons !! 3067 config PCI_DRIVERS_LEGACY
2197 support when running on SVE capable !! 3068 def_bool !PCI_DRIVERS_GENERIC
2198 is present in: !! 3069 select NO_GENERIC_PCI_IOPORT_MAP
2199 3070
2200 * version 1.5 and later of the AR !! 3071 source "drivers/pci/Kconfig"
2201 * the AArch64 boot wrapper since <<
2202 ("bootwrapper: SVE: Enable SVE <<
2203 3072
2204 For other firmware implementations, !! 3073 #
2205 or vendor. !! 3074 # ISA support is now enabled via select. Too many systems still have the one
>> 3075 # or other ISA chip on the board that users don't know about so don't expect
>> 3076 # users to choose the right thing ...
>> 3077 #
>> 3078 config ISA
>> 3079 bool
2206 3080
2207 If you need the kernel to boot on S !! 3081 config EISA
2208 firmware, you may need to say N her !! 3082 bool "EISA support"
2209 fixed. Otherwise, you may experien !! 3083 depends on HW_HAS_EISA
2210 booting the kernel. If unsure and !! 3084 select ISA
2211 symptoms, you should assume that it !! 3085 select GENERIC_ISA_DMA
>> 3086 ---help---
>> 3087 The Extended Industry Standard Architecture (EISA) bus was
>> 3088 developed as an open alternative to the IBM MicroChannel bus.
>> 3089
>> 3090 The EISA bus provided some of the features of the IBM MicroChannel
>> 3091 bus while maintaining backward compatibility with cards made for
>> 3092 the older ISA bus. The EISA bus saw limited use between 1988 and
>> 3093 1995 when it was made obsolete by the PCI bus.
>> 3094
>> 3095 Say Y here if you are building a kernel for an EISA-based machine.
>> 3096
>> 3097 Otherwise, say N.
>> 3098
>> 3099 source "drivers/eisa/Kconfig"
>> 3100
>> 3101 config TC
>> 3102 bool "TURBOchannel support"
>> 3103 depends on MACH_DECSTATION
>> 3104 help
>> 3105 TURBOchannel is a DEC (now Compaq (now HP)) bus for Alpha and MIPS
>> 3106 processors. TURBOchannel programming specifications are available
>> 3107 at:
>> 3108 <ftp://ftp.hp.com/pub/alphaserver/archive/triadd/>
>> 3109 and:
>> 3110 <http://www.computer-refuge.org/classiccmp/ftp.digital.com/pub/DEC/TriAdd/>
>> 3111 Linux driver support status is documented at:
>> 3112 <http://www.linux-mips.org/wiki/DECstation>
2212 3113
2213 config ARM64_SME !! 3114 config MMU
2214 bool "ARM Scalable Matrix Extension s !! 3115 bool
2215 default y 3116 default y
2216 depends on ARM64_SVE <<
2217 depends on BROKEN <<
2218 help <<
2219 The Scalable Matrix Extension (SME) <<
2220 execution state which utilises a su <<
2221 instruction set, together with the <<
2222 register state capable of holding t <<
2223 enable various matrix operations. <<
2224 3117
2225 config ARM64_PSEUDO_NMI !! 3118 config ARCH_MMAP_RND_BITS_MIN
2226 bool "Support for NMI-like interrupts !! 3119 default 12 if 64BIT
2227 select ARM_GIC_V3 !! 3120 default 8
2228 help <<
2229 Adds support for mimicking Non-Mask <<
2230 GIC interrupt priority. This suppor <<
2231 ARM GIC. <<
2232 3121
2233 This high priority configuration fo !! 3122 config ARCH_MMAP_RND_BITS_MAX
2234 explicitly enabled by setting the k !! 3123 default 18 if 64BIT
2235 "irqchip.gicv3_pseudo_nmi" to 1. !! 3124 default 15
2236 3125
2237 If unsure, say N !! 3126 config ARCH_MMAP_RND_COMPAT_BITS_MIN
>> 3127 default 8
2238 3128
2239 if ARM64_PSEUDO_NMI !! 3129 config ARCH_MMAP_RND_COMPAT_BITS_MAX
2240 config ARM64_DEBUG_PRIORITY_MASKING !! 3130 default 15
2241 bool "Debug interrupt priority maskin <<
2242 help <<
2243 This adds runtime checks to functio <<
2244 interrupts when using priority mask <<
2245 the validity of ICC_PMR_EL1 when ca <<
2246 3131
2247 If unsure, say N !! 3132 config I8253
2248 endif # ARM64_PSEUDO_NMI !! 3133 bool
>> 3134 select CLKSRC_I8253
>> 3135 select CLKEVT_I8253
>> 3136 select MIPS_EXTERNAL_TIMER
2249 3137
2250 config RELOCATABLE !! 3138 config ZONE_DMA
2251 bool "Build a relocatable kernel imag !! 3139 bool
2252 select ARCH_HAS_RELR <<
2253 default y <<
2254 help <<
2255 This builds the kernel as a Positio <<
2256 which retains all relocation metada <<
2257 kernel binary at runtime to a diffe <<
2258 address it was linked at. <<
2259 Since AArch64 uses the RELA relocat <<
2260 relocation pass at runtime even if <<
2261 same address it was linked at. <<
2262 3140
2263 config RANDOMIZE_BASE !! 3141 config ZONE_DMA32
2264 bool "Randomize the address of the ke !! 3142 bool
2265 select RELOCATABLE <<
2266 help <<
2267 Randomizes the virtual address at w <<
2268 loaded, as a security feature that <<
2269 relying on knowledge of the locatio <<
2270 <<
2271 It is the bootloader's job to provi <<
2272 random u64 value in /chosen/kaslr-s <<
2273 <<
2274 When booting via the UEFI stub, it <<
2275 EFI_RNG_PROTOCOL implementation (if <<
2276 to the kernel proper. In addition, <<
2277 location of the kernel Image as wel <<
2278 3143
2279 If unsure, say N. !! 3144 source "drivers/pcmcia/Kconfig"
2280 3145
2281 config RANDOMIZE_MODULE_REGION_FULL !! 3146 config HAS_RAPIDIO
2282 bool "Randomize the module region ove !! 3147 bool
2283 depends on RANDOMIZE_BASE !! 3148 default n
2284 default y <<
2285 help <<
2286 Randomizes the location of the modu <<
2287 covering the core kernel. This way, <<
2288 to leak information about the locat <<
2289 but it does imply that function cal <<
2290 kernel will need to be resolved via <<
2291 <<
2292 When this option is not set, the mo <<
2293 a limited range that contains the [ <<
2294 core kernel, so branch relocations <<
2295 the region is exhausted. In this pa <<
2296 exhaustion, modules might be able t <<
2297 3149
2298 config CC_HAVE_STACKPROTECTOR_SYSREG !! 3150 config RAPIDIO
2299 def_bool $(cc-option,-mstack-protecto !! 3151 tristate "RapidIO support"
>> 3152 depends on HAS_RAPIDIO || PCI
>> 3153 help
>> 3154 If you say Y here, the kernel will include drivers and
>> 3155 infrastructure code to support RapidIO interconnect devices.
2300 3156
2301 config STACKPROTECTOR_PER_TASK !! 3157 source "drivers/rapidio/Kconfig"
2302 def_bool y <<
2303 depends on STACKPROTECTOR && CC_HAVE_ <<
2304 3158
2305 config UNWIND_PATCH_PAC_INTO_SCS !! 3159 endmenu
2306 bool "Enable shadow call stack dynami <<
2307 # needs Clang with https://github.com <<
2308 depends on CC_IS_CLANG && CLANG_VERSI <<
2309 depends on ARM64_PTR_AUTH_KERNEL && C <<
2310 depends on SHADOW_CALL_STACK <<
2311 select UNWIND_TABLES <<
2312 select DYNAMIC_SCS <<
2313 <<
2314 config ARM64_CONTPTE <<
2315 bool "Contiguous PTE mappings for use <<
2316 depends on TRANSPARENT_HUGEPAGE <<
2317 default y <<
2318 help <<
2319 When enabled, user mappings are con <<
2320 bit, for any mappings that meet the <<
2321 This reduces TLB pressure and impro <<
2322 <<
2323 endmenu # "Kernel Features" <<
2324 <<
2325 menu "Boot options" <<
2326 <<
2327 config ARM64_ACPI_PARKING_PROTOCOL <<
2328 bool "Enable support for the ARM64 AC <<
2329 depends on ACPI <<
2330 help <<
2331 Enable support for the ARM64 ACPI p <<
2332 the kernel will not allow booting t <<
2333 protocol even if the corresponding <<
2334 MADT table. <<
2335 <<
2336 config CMDLINE <<
2337 string "Default kernel command string <<
2338 default "" <<
2339 help <<
2340 Provide a set of default command-li <<
2341 entering them here. As a minimum, y <<
2342 root device (e.g. root=/dev/nfs). <<
2343 3160
2344 choice !! 3161 config TRAD_SIGNALS
2345 prompt "Kernel command line type" !! 3162 bool
2346 depends on CMDLINE != "" <<
2347 default CMDLINE_FROM_BOOTLOADER <<
2348 help <<
2349 Choose how the kernel will handle t <<
2350 command line string. <<
2351 <<
2352 config CMDLINE_FROM_BOOTLOADER <<
2353 bool "Use bootloader kernel arguments <<
2354 help <<
2355 Uses the command-line options passe <<
2356 the boot loader doesn't provide any <<
2357 string provided in CMDLINE will be <<
2358 <<
2359 config CMDLINE_FORCE <<
2360 bool "Always use the default kernel c <<
2361 help <<
2362 Always use the default kernel comma <<
2363 loader passes other arguments to th <<
2364 This is useful if you cannot or don <<
2365 command-line options your boot load <<
2366 3163
2367 endchoice !! 3164 config MIPS32_COMPAT
>> 3165 bool
2368 3166
2369 config EFI_STUB !! 3167 config COMPAT
2370 bool 3168 bool
2371 3169
2372 config EFI !! 3170 config SYSVIPC_COMPAT
2373 bool "UEFI runtime support" !! 3171 bool
2374 depends on OF && !CPU_BIG_ENDIAN <<
2375 depends on KERNEL_MODE_NEON <<
2376 select ARCH_SUPPORTS_ACPI <<
2377 select LIBFDT <<
2378 select UCS2_STRING <<
2379 select EFI_PARAMS_FROM_FDT <<
2380 select EFI_RUNTIME_WRAPPERS <<
2381 select EFI_STUB <<
2382 select EFI_GENERIC_STUB <<
2383 imply IMA_SECURE_AND_OR_TRUSTED_BOOT <<
2384 default y <<
2385 help <<
2386 This option provides support for ru <<
2387 by UEFI firmware (such as non-volat <<
2388 clock, and platform reset). A UEFI <<
2389 allow the kernel to be booted as an <<
2390 is only useful on systems that have <<
2391 3172
2392 config COMPRESSED_INSTALL !! 3173 config MIPS32_O32
2393 bool "Install compressed image by def !! 3174 bool "Kernel support for o32 binaries"
2394 help !! 3175 depends on 64BIT
2395 This makes the regular "make instal !! 3176 select ARCH_WANT_OLD_COMPAT_IPC
2396 image we built, not the legacy unco !! 3177 select COMPAT
>> 3178 select MIPS32_COMPAT
>> 3179 select SYSVIPC_COMPAT if SYSVIPC
>> 3180 help
>> 3181 Select this option if you want to run o32 binaries. These are pure
>> 3182 32-bit binaries as used by the 32-bit Linux/MIPS port. Most of
>> 3183 existing binaries are in this format.
2397 3184
2398 You can check that a compressed ima !! 3185 If unsure, say Y.
2399 "make zinstall" first, and verifyin <<
2400 in your environment before making " <<
2401 you. <<
2402 3186
2403 config DMI !! 3187 config MIPS32_N32
2404 bool "Enable support for SMBIOS (DMI) !! 3188 bool "Kernel support for n32 binaries"
2405 depends on EFI !! 3189 depends on 64BIT
2406 default y !! 3190 select ARCH_WANT_COMPAT_IPC_PARSE_VERSION
2407 help !! 3191 select COMPAT
2408 This enables SMBIOS/DMI feature for !! 3192 select MIPS32_COMPAT
>> 3193 select SYSVIPC_COMPAT if SYSVIPC
>> 3194 help
>> 3195 Select this option if you want to run n32 binaries. These are
>> 3196 64-bit binaries using 32-bit quantities for addressing and certain
>> 3197 data that would normally be 64-bit. They are used in special
>> 3198 cases.
2409 3199
2410 This option is only useful on syste !! 3200 If unsure, say N.
2411 However, even with this option, the <<
2412 continue to boot on existing non-UE <<
2413 3201
2414 endmenu # "Boot options" !! 3202 config BINFMT_ELF32
>> 3203 bool
>> 3204 default y if MIPS32_O32 || MIPS32_N32
>> 3205 select ELFCORE
2415 3206
2416 menu "Power management options" 3207 menu "Power management options"
2417 3208
2418 source "kernel/power/Kconfig" <<
2419 <<
2420 config ARCH_HIBERNATION_POSSIBLE 3209 config ARCH_HIBERNATION_POSSIBLE
2421 def_bool y 3210 def_bool y
2422 depends on CPU_PM !! 3211 depends on SYS_SUPPORTS_HOTPLUG_CPU || !SMP
2423 <<
2424 config ARCH_HIBERNATION_HEADER <<
2425 def_bool y <<
2426 depends on HIBERNATION <<
2427 3212
2428 config ARCH_SUSPEND_POSSIBLE 3213 config ARCH_SUSPEND_POSSIBLE
2429 def_bool y 3214 def_bool y
>> 3215 depends on SYS_SUPPORTS_HOTPLUG_CPU || !SMP
2430 3216
2431 endmenu # "Power management options" !! 3217 source "kernel/power/Kconfig"
2432 3218
2433 menu "CPU Power Management" !! 3219 endmenu
2434 3220
2435 source "drivers/cpuidle/Kconfig" !! 3221 config MIPS_EXTERNAL_TIMER
>> 3222 bool
2436 3223
>> 3224 menu "CPU Power Management"
>> 3225
>> 3226 if CPU_SUPPORTS_CPUFREQ && MIPS_EXTERNAL_TIMER
2437 source "drivers/cpufreq/Kconfig" 3227 source "drivers/cpufreq/Kconfig"
>> 3228 endif
2438 3229
2439 endmenu # "CPU Power Management" !! 3230 source "drivers/cpuidle/Kconfig"
2440 3231
2441 source "drivers/acpi/Kconfig" !! 3232 endmenu
2442 3233
2443 source "arch/arm64/kvm/Kconfig" !! 3234 source "drivers/firmware/Kconfig"
2444 3235
>> 3236 source "arch/mips/kvm/Kconfig"
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