1 # SPDX-License-Identifier: GPL-2.0-only !! 1 config MIPS
2 config ARM64 !! 2 bool
3 def_bool y !! 3 default y
4 select ACPI_APMT if ACPI !! 4 select ARCH_SUPPORTS_UPROBES
5 select ACPI_CCA_REQUIRED if ACPI !! 5 select ARCH_MIGHT_HAVE_PC_PARPORT
6 select ACPI_GENERIC_GSI if ACPI !! 6 select ARCH_MIGHT_HAVE_PC_SERIO
7 select ACPI_GTDT if ACPI !! 7 select ARCH_USE_CMPXCHG_LOCKREF if 64BIT
8 select ACPI_HOTPLUG_CPU if ACPI_PROCES !! 8 select ARCH_USE_BUILTIN_BSWAP
9 select ACPI_IORT if ACPI !! 9 select HAVE_CONTEXT_TRACKING
10 select ACPI_REDUCED_HARDWARE_ONLY if A !! 10 select HAVE_GENERIC_DMA_COHERENT
11 select ACPI_MCFG if (ACPI && PCI) !! 11 select HAVE_IDE
12 select ACPI_SPCR_TABLE if ACPI !! 12 select HAVE_IRQ_EXIT_ON_IRQ_STACK
13 select ACPI_PPTT if ACPI !! 13 select HAVE_OPROFILE
14 select ARCH_HAS_DEBUG_WX !! 14 select HAVE_PERF_EVENTS
15 select ARCH_BINFMT_ELF_EXTRA_PHDRS !! 15 select PERF_USE_VMALLOC
16 select ARCH_BINFMT_ELF_STATE <<
17 select ARCH_CORRECT_STACKTRACE_ON_KRET <<
18 select ARCH_ENABLE_HUGEPAGE_MIGRATION <<
19 select ARCH_ENABLE_MEMORY_HOTPLUG <<
20 select ARCH_ENABLE_MEMORY_HOTREMOVE <<
21 select ARCH_ENABLE_SPLIT_PMD_PTLOCK if <<
22 select ARCH_ENABLE_THP_MIGRATION if TR <<
23 select ARCH_HAS_CACHE_LINE_SIZE <<
24 select ARCH_HAS_CURRENT_STACK_POINTER <<
25 select ARCH_HAS_DEBUG_VIRTUAL <<
26 select ARCH_HAS_DEBUG_VM_PGTABLE <<
27 select ARCH_HAS_DMA_OPS if XEN <<
28 select ARCH_HAS_DMA_PREP_COHERENT <<
29 select ARCH_HAS_ACPI_TABLE_UPGRADE if <<
30 select ARCH_HAS_FAST_MULTIPLIER <<
31 select ARCH_HAS_FORTIFY_SOURCE <<
32 select ARCH_HAS_GCOV_PROFILE_ALL <<
33 select ARCH_HAS_GIGANTIC_PAGE <<
34 select ARCH_HAS_KCOV <<
35 select ARCH_HAS_KERNEL_FPU_SUPPORT if <<
36 select ARCH_HAS_KEEPINITRD <<
37 select ARCH_HAS_MEMBARRIER_SYNC_CORE <<
38 select ARCH_HAS_MEM_ENCRYPT <<
39 select ARCH_HAS_NMI_SAFE_THIS_CPU_OPS <<
40 select ARCH_HAS_NON_OVERLAPPING_ADDRES <<
41 select ARCH_HAS_PTE_DEVMAP <<
42 select ARCH_HAS_PTE_SPECIAL <<
43 select ARCH_HAS_HW_PTE_YOUNG <<
44 select ARCH_HAS_SETUP_DMA_OPS <<
45 select ARCH_HAS_SET_DIRECT_MAP <<
46 select ARCH_HAS_SET_MEMORY <<
47 select ARCH_STACKWALK <<
48 select ARCH_HAS_STRICT_KERNEL_RWX <<
49 select ARCH_HAS_STRICT_MODULE_RWX <<
50 select ARCH_HAS_SYNC_DMA_FOR_DEVICE <<
51 select ARCH_HAS_SYNC_DMA_FOR_CPU <<
52 select ARCH_HAS_SYSCALL_WRAPPER <<
53 select ARCH_HAS_TICK_BROADCAST if GENE <<
54 select ARCH_HAS_ZONE_DMA_SET if EXPERT <<
55 select ARCH_HAVE_ELF_PROT <<
56 select ARCH_HAVE_NMI_SAFE_CMPXCHG <<
57 select ARCH_HAVE_TRACE_MMIO_ACCESS <<
58 select ARCH_INLINE_READ_LOCK if !PREEM <<
59 select ARCH_INLINE_READ_LOCK_BH if !PR <<
60 select ARCH_INLINE_READ_LOCK_IRQ if !P <<
61 select ARCH_INLINE_READ_LOCK_IRQSAVE i <<
62 select ARCH_INLINE_READ_UNLOCK if !PRE <<
63 select ARCH_INLINE_READ_UNLOCK_BH if ! <<
64 select ARCH_INLINE_READ_UNLOCK_IRQ if <<
65 select ARCH_INLINE_READ_UNLOCK_IRQREST <<
66 select ARCH_INLINE_WRITE_LOCK if !PREE <<
67 select ARCH_INLINE_WRITE_LOCK_BH if !P <<
68 select ARCH_INLINE_WRITE_LOCK_IRQ if ! <<
69 select ARCH_INLINE_WRITE_LOCK_IRQSAVE <<
70 select ARCH_INLINE_WRITE_UNLOCK if !PR <<
71 select ARCH_INLINE_WRITE_UNLOCK_BH if <<
72 select ARCH_INLINE_WRITE_UNLOCK_IRQ if <<
73 select ARCH_INLINE_WRITE_UNLOCK_IRQRES <<
74 select ARCH_INLINE_SPIN_TRYLOCK if !PR <<
75 select ARCH_INLINE_SPIN_TRYLOCK_BH if <<
76 select ARCH_INLINE_SPIN_LOCK if !PREEM <<
77 select ARCH_INLINE_SPIN_LOCK_BH if !PR <<
78 select ARCH_INLINE_SPIN_LOCK_IRQ if !P <<
79 select ARCH_INLINE_SPIN_LOCK_IRQSAVE i <<
80 select ARCH_INLINE_SPIN_UNLOCK if !PRE <<
81 select ARCH_INLINE_SPIN_UNLOCK_BH if ! <<
82 select ARCH_INLINE_SPIN_UNLOCK_IRQ if <<
83 select ARCH_INLINE_SPIN_UNLOCK_IRQREST <<
84 select ARCH_KEEP_MEMBLOCK <<
85 select ARCH_MHP_MEMMAP_ON_MEMORY_ENABL <<
86 select ARCH_USE_CMPXCHG_LOCKREF <<
87 select ARCH_USE_GNU_PROPERTY <<
88 select ARCH_USE_MEMTEST <<
89 select ARCH_USE_QUEUED_RWLOCKS <<
90 select ARCH_USE_QUEUED_SPINLOCKS <<
91 select ARCH_USE_SYM_ANNOTATIONS <<
92 select ARCH_SUPPORTS_DEBUG_PAGEALLOC <<
93 select ARCH_SUPPORTS_HUGETLBFS <<
94 select ARCH_SUPPORTS_MEMORY_FAILURE <<
95 select ARCH_SUPPORTS_SHADOW_CALL_STACK <<
96 select ARCH_SUPPORTS_LTO_CLANG if CPU_ <<
97 select ARCH_SUPPORTS_LTO_CLANG_THIN <<
98 select ARCH_SUPPORTS_CFI_CLANG <<
99 select ARCH_SUPPORTS_ATOMIC_RMW <<
100 select ARCH_SUPPORTS_INT128 if CC_HAS_ <<
101 select ARCH_SUPPORTS_NUMA_BALANCING <<
102 select ARCH_SUPPORTS_PAGE_TABLE_CHECK <<
103 select ARCH_SUPPORTS_PER_VMA_LOCK <<
104 select ARCH_SUPPORTS_HUGE_PFNMAP if TR <<
105 select ARCH_SUPPORTS_RT <<
106 select ARCH_WANT_BATCHED_UNMAP_TLB_FLU <<
107 select ARCH_WANT_COMPAT_IPC_PARSE_VERS <<
108 select ARCH_WANT_DEFAULT_BPF_JIT <<
109 select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_ <<
110 select ARCH_WANT_FRAME_POINTERS <<
111 select ARCH_WANT_HUGE_PMD_SHARE if ARM <<
112 select ARCH_WANT_LD_ORPHAN_WARN <<
113 select ARCH_WANTS_EXECMEM_LATE if EXEC <<
114 select ARCH_WANTS_NO_INSTR <<
115 select ARCH_WANTS_THP_SWAP if ARM64_4K <<
116 select ARCH_HAS_UBSAN <<
117 select ARM_AMBA <<
118 select ARM_ARCH_TIMER <<
119 select ARM_GIC <<
120 select AUDIT_ARCH_COMPAT_GENERIC <<
121 select ARM_GIC_V2M if PCI <<
122 select ARM_GIC_V3 <<
123 select ARM_GIC_V3_ITS if PCI <<
124 select ARM_PSCI_FW <<
125 select BUILDTIME_TABLE_SORT <<
126 select CLONE_BACKWARDS <<
127 select COMMON_CLK <<
128 select CPU_PM if (SUSPEND || CPU_IDLE) <<
129 select CPUMASK_OFFSTACK if NR_CPUS > 2 <<
130 select CRC32 <<
131 select DCACHE_WORD_ACCESS <<
132 select DYNAMIC_FTRACE if FUNCTION_TRAC <<
133 select DMA_BOUNCE_UNALIGNED_KMALLOC <<
134 select DMA_DIRECT_REMAP <<
135 select EDAC_SUPPORT <<
136 select FRAME_POINTER <<
137 select FUNCTION_ALIGNMENT_4B <<
138 select FUNCTION_ALIGNMENT_8B if DYNAMI <<
139 select GENERIC_ALLOCATOR <<
140 select GENERIC_ARCH_TOPOLOGY <<
141 select GENERIC_CLOCKEVENTS_BROADCAST <<
142 select GENERIC_CPU_AUTOPROBE <<
143 select GENERIC_CPU_DEVICES <<
144 select GENERIC_CPU_VULNERABILITIES <<
145 select GENERIC_EARLY_IOREMAP <<
146 select GENERIC_IDLE_POLL_SETUP <<
147 select GENERIC_IOREMAP <<
148 select GENERIC_IRQ_IPI <<
149 select GENERIC_IRQ_PROBE <<
150 select GENERIC_IRQ_SHOW <<
151 select GENERIC_IRQ_SHOW_LEVEL <<
152 select GENERIC_LIB_DEVMEM_IS_ALLOWED <<
153 select GENERIC_PCI_IOMAP <<
154 select GENERIC_PTDUMP <<
155 select GENERIC_SCHED_CLOCK <<
156 select GENERIC_SMP_IDLE_THREAD <<
157 select GENERIC_TIME_VSYSCALL <<
158 select GENERIC_GETTIMEOFDAY <<
159 select GENERIC_VDSO_TIME_NS <<
160 select HARDIRQS_SW_RESEND <<
161 select HAS_IOPORT <<
162 select HAVE_MOVE_PMD <<
163 select HAVE_MOVE_PUD <<
164 select HAVE_PCI <<
165 select HAVE_ACPI_APEI if (ACPI && EFI) <<
166 select HAVE_ALIGNED_STRUCT_PAGE <<
167 select HAVE_ARCH_AUDITSYSCALL <<
168 select HAVE_ARCH_BITREVERSE <<
169 select HAVE_ARCH_COMPILER_H 16 select HAVE_ARCH_COMPILER_H
170 select HAVE_ARCH_HUGE_VMALLOC <<
171 select HAVE_ARCH_HUGE_VMAP <<
172 select HAVE_ARCH_JUMP_LABEL <<
173 select HAVE_ARCH_JUMP_LABEL_RELATIVE <<
174 select HAVE_ARCH_KASAN <<
175 select HAVE_ARCH_KASAN_VMALLOC <<
176 select HAVE_ARCH_KASAN_SW_TAGS <<
177 select HAVE_ARCH_KASAN_HW_TAGS if ARM6 <<
178 # Some instrumentation may be unsound, <<
179 select HAVE_ARCH_KCSAN if EXPERT <<
180 select HAVE_ARCH_KFENCE <<
181 select HAVE_ARCH_KGDB 17 select HAVE_ARCH_KGDB
182 select HAVE_ARCH_MMAP_RND_BITS <<
183 select HAVE_ARCH_MMAP_RND_COMPAT_BITS <<
184 select HAVE_ARCH_PREL32_RELOCATIONS <<
185 select HAVE_ARCH_RANDOMIZE_KSTACK_OFFS <<
186 select HAVE_ARCH_SECCOMP_FILTER 18 select HAVE_ARCH_SECCOMP_FILTER
187 select HAVE_ARCH_STACKLEAK <<
188 select HAVE_ARCH_THREAD_STRUCT_WHITELI <<
189 select HAVE_ARCH_TRACEHOOK 19 select HAVE_ARCH_TRACEHOOK
190 select HAVE_ARCH_TRANSPARENT_HUGEPAGE !! 20 select HAVE_CBPF_JIT if !CPU_MICROMIPS
191 select HAVE_ARCH_VMAP_STACK !! 21 select HAVE_FUNCTION_TRACER
192 select HAVE_ARM_SMCCC <<
193 select HAVE_ASM_MODVERSIONS <<
194 select HAVE_EBPF_JIT <<
195 select HAVE_C_RECORDMCOUNT <<
196 select HAVE_CMPXCHG_DOUBLE <<
197 select HAVE_CMPXCHG_LOCAL <<
198 select HAVE_CONTEXT_TRACKING_USER <<
199 select HAVE_DEBUG_KMEMLEAK <<
200 select HAVE_DMA_CONTIGUOUS <<
201 select HAVE_DYNAMIC_FTRACE 22 select HAVE_DYNAMIC_FTRACE
202 select HAVE_DYNAMIC_FTRACE_WITH_ARGS \ <<
203 if (GCC_SUPPORTS_DYNAMIC_FTRAC <<
204 CLANG_SUPPORTS_DYNAMIC_FTR <<
205 select HAVE_DYNAMIC_FTRACE_WITH_DIRECT <<
206 if DYNAMIC_FTRACE_WITH_ARGS && <<
207 select HAVE_DYNAMIC_FTRACE_WITH_CALL_O <<
208 if (DYNAMIC_FTRACE_WITH_ARGS & <<
209 (CC_IS_CLANG || !CC_OPTIMI <<
210 select FTRACE_MCOUNT_USE_PATCHABLE_FUN <<
211 if DYNAMIC_FTRACE_WITH_ARGS <<
212 select HAVE_SAMPLE_FTRACE_DIRECT <<
213 select HAVE_SAMPLE_FTRACE_DIRECT_MULTI <<
214 select HAVE_EFFICIENT_UNALIGNED_ACCESS <<
215 select HAVE_GUP_FAST <<
216 select HAVE_FTRACE_MCOUNT_RECORD 23 select HAVE_FTRACE_MCOUNT_RECORD
217 select HAVE_FUNCTION_TRACER !! 24 select HAVE_C_RECORDMCOUNT
218 select HAVE_FUNCTION_ERROR_INJECTION <<
219 select HAVE_FUNCTION_GRAPH_TRACER 25 select HAVE_FUNCTION_GRAPH_TRACER
220 select HAVE_FUNCTION_GRAPH_RETVAL <<
221 select HAVE_GCC_PLUGINS <<
222 select HAVE_HARDLOCKUP_DETECTOR_PERF i <<
223 HW_PERF_EVENTS && HAVE_PERF_EV <<
224 select HAVE_HW_BREAKPOINT if PERF_EVEN <<
225 select HAVE_IOREMAP_PROT <<
226 select HAVE_IRQ_TIME_ACCOUNTING <<
227 select HAVE_MOD_ARCH_SPECIFIC <<
228 select HAVE_NMI <<
229 select HAVE_PERF_EVENTS <<
230 select HAVE_PERF_EVENTS_NMI if ARM64_P <<
231 select HAVE_PERF_REGS <<
232 select HAVE_PERF_USER_STACK_DUMP <<
233 select HAVE_PREEMPT_DYNAMIC_KEY <<
234 select HAVE_REGS_AND_STACK_ACCESS_API <<
235 select HAVE_POSIX_CPU_TIMERS_TASK_WORK <<
236 select HAVE_FUNCTION_ARG_ACCESS_API <<
237 select MMU_GATHER_RCU_TABLE_FREE <<
238 select HAVE_RSEQ <<
239 select HAVE_RUST if RUSTC_SUPPORTS_ARM <<
240 select HAVE_STACKPROTECTOR <<
241 select HAVE_SYSCALL_TRACEPOINTS <<
242 select HAVE_KPROBES 26 select HAVE_KPROBES
243 select HAVE_KRETPROBES 27 select HAVE_KRETPROBES
244 select HAVE_GENERIC_VDSO !! 28 select HAVE_SYSCALL_TRACEPOINTS
245 select HOTPLUG_CORE_SYNC_DEAD if HOTPL !! 29 select HAVE_DEBUG_KMEMLEAK
246 select IRQ_DOMAIN !! 30 select HAVE_SYSCALL_TRACEPOINTS
>> 31 select ARCH_HAS_ELF_RANDOMIZE
>> 32 select HAVE_ARCH_TRANSPARENT_HUGEPAGE if CPU_SUPPORTS_HUGEPAGES && 64BIT
>> 33 select RTC_LIB if !MACH_LOONGSON64
>> 34 select GENERIC_ATOMIC64 if !64BIT
>> 35 select HAVE_DMA_CONTIGUOUS
>> 36 select HAVE_DMA_API_DEBUG
>> 37 select GENERIC_IRQ_PROBE
>> 38 select GENERIC_IRQ_SHOW
>> 39 select GENERIC_PCI_IOMAP
>> 40 select HAVE_ARCH_JUMP_LABEL
>> 41 select ARCH_WANT_IPC_PARSE_VERSION
247 select IRQ_FORCED_THREADING 42 select IRQ_FORCED_THREADING
248 select KASAN_VMALLOC if KASAN !! 43 select HAVE_MEMBLOCK
249 select LOCK_MM_AND_FIND_VMA !! 44 select HAVE_MEMBLOCK_NODE_MAP
250 select MODULES_USE_ELF_RELA !! 45 select ARCH_DISCARD_MEMBLOCK
251 select NEED_DMA_MAP_STATE !! 46 select GENERIC_SMP_IDLE_THREAD
252 select NEED_SG_DMA_LENGTH !! 47 select BUILDTIME_EXTABLE_SORT
253 select OF !! 48 select GENERIC_CLOCKEVENTS
254 select OF_EARLY_FLATTREE !! 49 select GENERIC_SCHED_CLOCK if !CAVIUM_OCTEON_SOC
255 select PCI_DOMAINS_GENERIC if PCI !! 50 select GENERIC_CMOS_UPDATE
256 select PCI_ECAM if (ACPI && PCI) !! 51 select HAVE_MOD_ARCH_SPECIFIC
257 select PCI_SYSCALL if PCI !! 52 select HAVE_NMI
258 select POWER_RESET !! 53 select VIRT_TO_BUS
259 select POWER_SUPPLY !! 54 select MODULES_USE_ELF_REL if MODULES
260 select SPARSE_IRQ !! 55 select MODULES_USE_ELF_RELA if MODULES && 64BIT
261 select SWIOTLB !! 56 select CLONE_BACKWARDS
>> 57 select HAVE_DEBUG_STACKOVERFLOW
>> 58 select HAVE_CC_STACKPROTECTOR
>> 59 select CPU_PM if CPU_IDLE
>> 60 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
>> 61 select ARCH_BINFMT_ELF_STATE
262 select SYSCTL_EXCEPTION_TRACE 62 select SYSCTL_EXCEPTION_TRACE
263 select THREAD_INFO_IN_TASK !! 63 select HAVE_VIRT_CPU_ACCOUNTING_GEN
264 select HAVE_ARCH_USERFAULTFD_MINOR if !! 64 select HAVE_IRQ_TIME_ACCOUNTING
265 select HAVE_ARCH_USERFAULTFD_WP if USE !! 65 select GENERIC_TIME_VSYSCALL
266 select TRACE_IRQFLAGS_SUPPORT !! 66 select ARCH_CLOCKSOURCE_DATA
267 select TRACE_IRQFLAGS_NMI_SUPPORT !! 67 select HANDLE_DOMAIN_IRQ
268 select HAVE_SOFTIRQ_ON_OWN_STACK !! 68 select HAVE_EXIT_THREAD
269 select USER_STACKTRACE_SUPPORT !! 69 select HAVE_REGS_AND_STACK_ACCESS_API
270 select VDSO_GETRANDOM !! 70 select HAVE_ARCH_HARDENED_USERCOPY
271 help <<
272 ARM 64-bit (AArch64) Linux support. <<
273 <<
274 config RUSTC_SUPPORTS_ARM64 <<
275 def_bool y <<
276 depends on CPU_LITTLE_ENDIAN <<
277 # Shadow call stack is only supported <<
278 # <<
279 # When using the UNWIND_PATCH_PAC_INTO <<
280 # required due to use of the -Zfixed-x <<
281 # <<
282 # Otherwise, rustc version 1.82+ is re <<
283 # -Zsanitizer=shadow-call-stack flag. <<
284 depends on !SHADOW_CALL_STACK || RUSTC <<
285 <<
286 config CLANG_SUPPORTS_DYNAMIC_FTRACE_WITH_ARGS <<
287 def_bool CC_IS_CLANG <<
288 # https://github.com/ClangBuiltLinux/l <<
289 depends on AS_IS_GNU || (AS_IS_LLVM && <<
290 <<
291 config GCC_SUPPORTS_DYNAMIC_FTRACE_WITH_ARGS <<
292 def_bool CC_IS_GCC <<
293 depends on $(cc-option,-fpatchable-fun <<
294 <<
295 config 64BIT <<
296 def_bool y <<
297 <<
298 config MMU <<
299 def_bool y <<
300 <<
301 config ARM64_CONT_PTE_SHIFT <<
302 int <<
303 default 5 if PAGE_SIZE_64KB <<
304 default 7 if PAGE_SIZE_16KB <<
305 default 4 <<
306 <<
307 config ARM64_CONT_PMD_SHIFT <<
308 int <<
309 default 5 if PAGE_SIZE_64KB <<
310 default 5 if PAGE_SIZE_16KB <<
311 default 4 <<
312 <<
313 config ARCH_MMAP_RND_BITS_MIN <<
314 default 14 if PAGE_SIZE_64KB <<
315 default 16 if PAGE_SIZE_16KB <<
316 default 18 <<
317 <<
318 # max bits determined by the following formula <<
319 # VA_BITS - PAGE_SHIFT - 3 <<
320 config ARCH_MMAP_RND_BITS_MAX <<
321 default 19 if ARM64_VA_BITS=36 <<
322 default 24 if ARM64_VA_BITS=39 <<
323 default 27 if ARM64_VA_BITS=42 <<
324 default 30 if ARM64_VA_BITS=47 <<
325 default 29 if ARM64_VA_BITS=48 && ARM6 <<
326 default 31 if ARM64_VA_BITS=48 && ARM6 <<
327 default 33 if ARM64_VA_BITS=48 <<
328 default 14 if ARM64_64K_PAGES <<
329 default 16 if ARM64_16K_PAGES <<
330 default 18 <<
331 <<
332 config ARCH_MMAP_RND_COMPAT_BITS_MIN <<
333 default 7 if ARM64_64K_PAGES <<
334 default 9 if ARM64_16K_PAGES <<
335 default 11 <<
336 <<
337 config ARCH_MMAP_RND_COMPAT_BITS_MAX <<
338 default 16 <<
339 <<
340 config NO_IOPORT_MAP <<
341 def_bool y if !PCI <<
342 <<
343 config STACKTRACE_SUPPORT <<
344 def_bool y <<
345 <<
346 config ILLEGAL_POINTER_VALUE <<
347 hex <<
348 default 0xdead000000000000 <<
349 71
350 config LOCKDEP_SUPPORT !! 72 menu "Machine selection"
351 def_bool y <<
352 73
353 config GENERIC_BUG !! 74 choice
354 def_bool y !! 75 prompt "System type"
355 depends on BUG !! 76 default SGI_IP22
356 <<
357 config GENERIC_BUG_RELATIVE_POINTERS <<
358 def_bool y <<
359 depends on GENERIC_BUG <<
360 77
361 config GENERIC_HWEIGHT !! 78 config MIPS_GENERIC
362 def_bool y !! 79 bool "Generic board-agnostic MIPS kernel"
>> 80 select BOOT_RAW
>> 81 select BUILTIN_DTB
>> 82 select CEVT_R4K
>> 83 select CLKSRC_MIPS_GIC
>> 84 select COMMON_CLK
>> 85 select CPU_MIPSR2_IRQ_VI
>> 86 select CPU_MIPSR2_IRQ_EI
>> 87 select CSRC_R4K
>> 88 select DMA_PERDEV_COHERENT
>> 89 select HW_HAS_PCI
>> 90 select IRQ_MIPS_CPU
>> 91 select LIBFDT
>> 92 select MIPS_CPU_SCACHE
>> 93 select MIPS_GIC
>> 94 select MIPS_L1_CACHE_SHIFT_7
>> 95 select NO_EXCEPT_FILL
>> 96 select PCI_DRIVERS_GENERIC
>> 97 select PINCTRL
>> 98 select SMP_UP if SMP
>> 99 select SWAP_IO_SPACE
>> 100 select SYS_HAS_CPU_MIPS32_R1
>> 101 select SYS_HAS_CPU_MIPS32_R2
>> 102 select SYS_HAS_CPU_MIPS32_R6
>> 103 select SYS_HAS_CPU_MIPS64_R1
>> 104 select SYS_HAS_CPU_MIPS64_R2
>> 105 select SYS_HAS_CPU_MIPS64_R6
>> 106 select SYS_SUPPORTS_32BIT_KERNEL
>> 107 select SYS_SUPPORTS_64BIT_KERNEL
>> 108 select SYS_SUPPORTS_BIG_ENDIAN
>> 109 select SYS_SUPPORTS_HIGHMEM
>> 110 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 111 select SYS_SUPPORTS_MICROMIPS
>> 112 select SYS_SUPPORTS_MIPS_CPS
>> 113 select SYS_SUPPORTS_MIPS16
>> 114 select SYS_SUPPORTS_MULTITHREADING
>> 115 select SYS_SUPPORTS_RELOCATABLE
>> 116 select SYS_SUPPORTS_SMARTMIPS
>> 117 select USB_EHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
>> 118 select USB_EHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 119 select USB_OHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
>> 120 select USB_OHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 121 select USB_UHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
>> 122 select USB_UHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 123 select USE_OF
>> 124 help
>> 125 Select this to build a kernel which aims to support multiple boards,
>> 126 generally using a flattened device tree passed from the bootloader
>> 127 using the boot protocol defined in the UHI (Unified Hosting
>> 128 Interface) specification.
>> 129
>> 130 config MIPS_ALCHEMY
>> 131 bool "Alchemy processor based machines"
>> 132 select ARCH_PHYS_ADDR_T_64BIT
>> 133 select CEVT_R4K
>> 134 select CSRC_R4K
>> 135 select IRQ_MIPS_CPU
>> 136 select DMA_MAYBE_COHERENT # Au1000,1500,1100 aren't, rest is
>> 137 select SYS_HAS_CPU_MIPS32_R1
>> 138 select SYS_SUPPORTS_32BIT_KERNEL
>> 139 select SYS_SUPPORTS_APM_EMULATION
>> 140 select GPIOLIB
>> 141 select SYS_SUPPORTS_ZBOOT
>> 142 select COMMON_CLK
363 143
364 config GENERIC_CSUM !! 144 config AR7
365 def_bool y !! 145 bool "Texas Instruments AR7"
>> 146 select BOOT_ELF32
>> 147 select DMA_NONCOHERENT
>> 148 select CEVT_R4K
>> 149 select CSRC_R4K
>> 150 select IRQ_MIPS_CPU
>> 151 select NO_EXCEPT_FILL
>> 152 select SWAP_IO_SPACE
>> 153 select SYS_HAS_CPU_MIPS32_R1
>> 154 select SYS_HAS_EARLY_PRINTK
>> 155 select SYS_SUPPORTS_32BIT_KERNEL
>> 156 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 157 select SYS_SUPPORTS_MIPS16
>> 158 select SYS_SUPPORTS_ZBOOT_UART16550
>> 159 select GPIOLIB
>> 160 select VLYNQ
>> 161 select HAVE_CLK
>> 162 help
>> 163 Support for the Texas Instruments AR7 System-on-a-Chip
>> 164 family: TNETD7100, 7200 and 7300.
>> 165
>> 166 config ATH25
>> 167 bool "Atheros AR231x/AR531x SoC support"
>> 168 select CEVT_R4K
>> 169 select CSRC_R4K
>> 170 select DMA_NONCOHERENT
>> 171 select IRQ_MIPS_CPU
>> 172 select IRQ_DOMAIN
>> 173 select SYS_HAS_CPU_MIPS32_R1
>> 174 select SYS_SUPPORTS_BIG_ENDIAN
>> 175 select SYS_SUPPORTS_32BIT_KERNEL
>> 176 select SYS_HAS_EARLY_PRINTK
>> 177 help
>> 178 Support for Atheros AR231x and Atheros AR531x based boards
>> 179
>> 180 config ATH79
>> 181 bool "Atheros AR71XX/AR724X/AR913X based boards"
>> 182 select ARCH_HAS_RESET_CONTROLLER
>> 183 select BOOT_RAW
>> 184 select CEVT_R4K
>> 185 select CSRC_R4K
>> 186 select DMA_NONCOHERENT
>> 187 select GPIOLIB
>> 188 select HAVE_CLK
>> 189 select COMMON_CLK
>> 190 select CLKDEV_LOOKUP
>> 191 select IRQ_MIPS_CPU
>> 192 select MIPS_MACHINE
>> 193 select SYS_HAS_CPU_MIPS32_R2
>> 194 select SYS_HAS_EARLY_PRINTK
>> 195 select SYS_SUPPORTS_32BIT_KERNEL
>> 196 select SYS_SUPPORTS_BIG_ENDIAN
>> 197 select SYS_SUPPORTS_MIPS16
>> 198 select SYS_SUPPORTS_ZBOOT_UART_PROM
>> 199 select USE_OF
>> 200 help
>> 201 Support for the Atheros AR71XX/AR724X/AR913X SoCs.
>> 202
>> 203 config BMIPS_GENERIC
>> 204 bool "Broadcom Generic BMIPS kernel"
>> 205 select BOOT_RAW
>> 206 select NO_EXCEPT_FILL
>> 207 select USE_OF
>> 208 select CEVT_R4K
>> 209 select CSRC_R4K
>> 210 select SYNC_R4K
>> 211 select COMMON_CLK
>> 212 select BCM6345_L1_IRQ
>> 213 select BCM7038_L1_IRQ
>> 214 select BCM7120_L2_IRQ
>> 215 select BRCMSTB_L2_IRQ
>> 216 select IRQ_MIPS_CPU
>> 217 select DMA_NONCOHERENT
>> 218 select SYS_SUPPORTS_32BIT_KERNEL
>> 219 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 220 select SYS_SUPPORTS_BIG_ENDIAN
>> 221 select SYS_SUPPORTS_HIGHMEM
>> 222 select SYS_HAS_CPU_BMIPS32_3300
>> 223 select SYS_HAS_CPU_BMIPS4350
>> 224 select SYS_HAS_CPU_BMIPS4380
>> 225 select SYS_HAS_CPU_BMIPS5000
>> 226 select SWAP_IO_SPACE
>> 227 select USB_EHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
>> 228 select USB_EHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 229 select USB_OHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
>> 230 select USB_OHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 231 help
>> 232 Build a generic DT-based kernel image that boots on select
>> 233 BCM33xx cable modem chips, BCM63xx DSL chips, and BCM7xxx set-top
>> 234 box chips. Note that CONFIG_CPU_BIG_ENDIAN/CONFIG_CPU_LITTLE_ENDIAN
>> 235 must be set appropriately for your board.
>> 236
>> 237 config BCM47XX
>> 238 bool "Broadcom BCM47XX based boards"
>> 239 select BOOT_RAW
>> 240 select CEVT_R4K
>> 241 select CSRC_R4K
>> 242 select DMA_NONCOHERENT
>> 243 select HW_HAS_PCI
>> 244 select IRQ_MIPS_CPU
>> 245 select SYS_HAS_CPU_MIPS32_R1
>> 246 select NO_EXCEPT_FILL
>> 247 select SYS_SUPPORTS_32BIT_KERNEL
>> 248 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 249 select SYS_SUPPORTS_MIPS16
>> 250 select SYS_HAS_EARLY_PRINTK
>> 251 select USE_GENERIC_EARLY_PRINTK_8250
>> 252 select GPIOLIB
>> 253 select LEDS_GPIO_REGISTER
>> 254 select BCM47XX_NVRAM
>> 255 select BCM47XX_SPROM
>> 256 help
>> 257 Support for BCM47XX based boards
>> 258
>> 259 config BCM63XX
>> 260 bool "Broadcom BCM63XX based boards"
>> 261 select BOOT_RAW
>> 262 select CEVT_R4K
>> 263 select CSRC_R4K
>> 264 select SYNC_R4K
>> 265 select DMA_NONCOHERENT
>> 266 select IRQ_MIPS_CPU
>> 267 select SYS_SUPPORTS_32BIT_KERNEL
>> 268 select SYS_SUPPORTS_BIG_ENDIAN
>> 269 select SYS_HAS_EARLY_PRINTK
>> 270 select SYS_HAS_CPU_BMIPS32_3300
>> 271 select SYS_HAS_CPU_BMIPS4350
>> 272 select SYS_HAS_CPU_BMIPS4380
>> 273 select SWAP_IO_SPACE
>> 274 select GPIOLIB
>> 275 select HAVE_CLK
>> 276 select MIPS_L1_CACHE_SHIFT_4
>> 277 help
>> 278 Support for BCM63XX based boards
>> 279
>> 280 config MIPS_COBALT
>> 281 bool "Cobalt Server"
>> 282 select CEVT_R4K
>> 283 select CSRC_R4K
>> 284 select CEVT_GT641XX
>> 285 select DMA_NONCOHERENT
>> 286 select HW_HAS_PCI
>> 287 select I8253
>> 288 select I8259
>> 289 select IRQ_MIPS_CPU
>> 290 select IRQ_GT641XX
>> 291 select PCI_GT64XXX_PCI0
>> 292 select PCI
>> 293 select SYS_HAS_CPU_NEVADA
>> 294 select SYS_HAS_EARLY_PRINTK
>> 295 select SYS_SUPPORTS_32BIT_KERNEL
>> 296 select SYS_SUPPORTS_64BIT_KERNEL
>> 297 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 298 select USE_GENERIC_EARLY_PRINTK_8250
>> 299
>> 300 config MACH_DECSTATION
>> 301 bool "DECstations"
>> 302 select BOOT_ELF32
>> 303 select CEVT_DS1287
>> 304 select CEVT_R4K if CPU_R4X00
>> 305 select CSRC_IOASIC
>> 306 select CSRC_R4K if CPU_R4X00
>> 307 select CPU_DADDI_WORKAROUNDS if 64BIT
>> 308 select CPU_R4000_WORKAROUNDS if 64BIT
>> 309 select CPU_R4400_WORKAROUNDS if 64BIT
>> 310 select DMA_NONCOHERENT
>> 311 select NO_IOPORT_MAP
>> 312 select IRQ_MIPS_CPU
>> 313 select SYS_HAS_CPU_R3000
>> 314 select SYS_HAS_CPU_R4X00
>> 315 select SYS_SUPPORTS_32BIT_KERNEL
>> 316 select SYS_SUPPORTS_64BIT_KERNEL
>> 317 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 318 select SYS_SUPPORTS_128HZ
>> 319 select SYS_SUPPORTS_256HZ
>> 320 select SYS_SUPPORTS_1024HZ
>> 321 select MIPS_L1_CACHE_SHIFT_4
>> 322 help
>> 323 This enables support for DEC's MIPS based workstations. For details
>> 324 see the Linux/MIPS FAQ on <http://www.linux-mips.org/> and the
>> 325 DECstation porting pages on <http://decstation.unix-ag.org/>.
>> 326
>> 327 If you have one of the following DECstation Models you definitely
>> 328 want to choose R4xx0 for the CPU Type:
>> 329
>> 330 DECstation 5000/50
>> 331 DECstation 5000/150
>> 332 DECstation 5000/260
>> 333 DECsystem 5900/260
>> 334
>> 335 otherwise choose R3000.
>> 336
>> 337 config MACH_JAZZ
>> 338 bool "Jazz family of machines"
>> 339 select FW_ARC
>> 340 select FW_ARC32
>> 341 select ARCH_MAY_HAVE_PC_FDC
>> 342 select CEVT_R4K
>> 343 select CSRC_R4K
>> 344 select DEFAULT_SGI_PARTITION if CPU_BIG_ENDIAN
>> 345 select GENERIC_ISA_DMA
>> 346 select HAVE_PCSPKR_PLATFORM
>> 347 select IRQ_MIPS_CPU
>> 348 select I8253
>> 349 select I8259
>> 350 select ISA
>> 351 select SYS_HAS_CPU_R4X00
>> 352 select SYS_SUPPORTS_32BIT_KERNEL
>> 353 select SYS_SUPPORTS_64BIT_KERNEL
>> 354 select SYS_SUPPORTS_100HZ
>> 355 help
>> 356 This a family of machines based on the MIPS R4030 chipset which was
>> 357 used by several vendors to build RISC/os and Windows NT workstations.
>> 358 Members include the Acer PICA, MIPS Magnum 4000, MIPS Millennium and
>> 359 Olivetti M700-10 workstations.
>> 360
>> 361 config MACH_INGENIC
>> 362 bool "Ingenic SoC based machines"
>> 363 select SYS_SUPPORTS_32BIT_KERNEL
>> 364 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 365 select SYS_SUPPORTS_ZBOOT_UART16550
>> 366 select DMA_NONCOHERENT
>> 367 select IRQ_MIPS_CPU
>> 368 select GPIOLIB
>> 369 select COMMON_CLK
>> 370 select GENERIC_IRQ_CHIP
>> 371 select BUILTIN_DTB
>> 372 select USE_OF
>> 373 select LIBFDT
366 374
367 config GENERIC_CALIBRATE_DELAY !! 375 config LANTIQ
368 def_bool y !! 376 bool "Lantiq based platforms"
>> 377 select DMA_NONCOHERENT
>> 378 select IRQ_MIPS_CPU
>> 379 select CEVT_R4K
>> 380 select CSRC_R4K
>> 381 select SYS_HAS_CPU_MIPS32_R1
>> 382 select SYS_HAS_CPU_MIPS32_R2
>> 383 select SYS_SUPPORTS_BIG_ENDIAN
>> 384 select SYS_SUPPORTS_32BIT_KERNEL
>> 385 select SYS_SUPPORTS_MIPS16
>> 386 select SYS_SUPPORTS_MULTITHREADING
>> 387 select SYS_HAS_EARLY_PRINTK
>> 388 select GPIOLIB
>> 389 select SWAP_IO_SPACE
>> 390 select BOOT_RAW
>> 391 select CLKDEV_LOOKUP
>> 392 select USE_OF
>> 393 select PINCTRL
>> 394 select PINCTRL_LANTIQ
>> 395 select ARCH_HAS_RESET_CONTROLLER
>> 396 select RESET_CONTROLLER
>> 397
>> 398 config LASAT
>> 399 bool "LASAT Networks platforms"
>> 400 select CEVT_R4K
>> 401 select CRC32
>> 402 select CSRC_R4K
>> 403 select DMA_NONCOHERENT
>> 404 select SYS_HAS_EARLY_PRINTK
>> 405 select HW_HAS_PCI
>> 406 select IRQ_MIPS_CPU
>> 407 select PCI_GT64XXX_PCI0
>> 408 select MIPS_NILE4
>> 409 select R5000_CPU_SCACHE
>> 410 select SYS_HAS_CPU_R5000
>> 411 select SYS_SUPPORTS_32BIT_KERNEL
>> 412 select SYS_SUPPORTS_64BIT_KERNEL if BROKEN
>> 413 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 414
>> 415 config MACH_LOONGSON32
>> 416 bool "Loongson-1 family of machines"
>> 417 select SYS_SUPPORTS_ZBOOT
>> 418 help
>> 419 This enables support for the Loongson-1 family of machines.
>> 420
>> 421 Loongson-1 is a family of 32-bit MIPS-compatible SoCs developed by
>> 422 the Institute of Computing Technology (ICT), Chinese Academy of
>> 423 Sciences (CAS).
>> 424
>> 425 config MACH_LOONGSON64
>> 426 bool "Loongson-2/3 family of machines"
>> 427 select SYS_SUPPORTS_ZBOOT
>> 428 help
>> 429 This enables the support of Loongson-2/3 family of machines.
>> 430
>> 431 Loongson-2 is a family of single-core CPUs and Loongson-3 is a
>> 432 family of multi-core CPUs. They are both 64-bit general-purpose
>> 433 MIPS-compatible CPUs. Loongson-2/3 are developed by the Institute
>> 434 of Computing Technology (ICT), Chinese Academy of Sciences (CAS)
>> 435 in the People's Republic of China. The chief architect is Professor
>> 436 Weiwu Hu.
>> 437
>> 438 config MACH_PISTACHIO
>> 439 bool "IMG Pistachio SoC based boards"
>> 440 select BOOT_ELF32
>> 441 select BOOT_RAW
>> 442 select CEVT_R4K
>> 443 select CLKSRC_MIPS_GIC
>> 444 select COMMON_CLK
>> 445 select CSRC_R4K
>> 446 select DMA_NONCOHERENT
>> 447 select GPIOLIB
>> 448 select IRQ_MIPS_CPU
>> 449 select LIBFDT
>> 450 select MFD_SYSCON
>> 451 select MIPS_CPU_SCACHE
>> 452 select MIPS_GIC
>> 453 select PINCTRL
>> 454 select REGULATOR
>> 455 select SYS_HAS_CPU_MIPS32_R2
>> 456 select SYS_SUPPORTS_32BIT_KERNEL
>> 457 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 458 select SYS_SUPPORTS_MIPS_CPS
>> 459 select SYS_SUPPORTS_MULTITHREADING
>> 460 select SYS_SUPPORTS_RELOCATABLE
>> 461 select SYS_SUPPORTS_ZBOOT
>> 462 select SYS_HAS_EARLY_PRINTK
>> 463 select USE_GENERIC_EARLY_PRINTK_8250
>> 464 select USE_OF
>> 465 help
>> 466 This enables support for the IMG Pistachio SoC platform.
>> 467
>> 468 config MACH_XILFPGA
>> 469 bool "MIPSfpga Xilinx based boards"
>> 470 select BOOT_ELF32
>> 471 select BOOT_RAW
>> 472 select BUILTIN_DTB
>> 473 select CEVT_R4K
>> 474 select COMMON_CLK
>> 475 select CSRC_R4K
>> 476 select GPIOLIB
>> 477 select IRQ_MIPS_CPU
>> 478 select LIBFDT
>> 479 select MIPS_CPU_SCACHE
>> 480 select SYS_HAS_EARLY_PRINTK
>> 481 select SYS_HAS_CPU_MIPS32_R2
>> 482 select SYS_SUPPORTS_32BIT_KERNEL
>> 483 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 484 select SYS_SUPPORTS_ZBOOT_UART16550
>> 485 select USE_OF
>> 486 select USE_GENERIC_EARLY_PRINTK_8250
>> 487 help
>> 488 This enables support for the IMG University Program MIPSfpga platform.
>> 489
>> 490 config MIPS_MALTA
>> 491 bool "MIPS Malta board"
>> 492 select ARCH_MAY_HAVE_PC_FDC
>> 493 select BOOT_ELF32
>> 494 select BOOT_RAW
>> 495 select BUILTIN_DTB
>> 496 select CEVT_R4K
>> 497 select CSRC_R4K
>> 498 select CLKSRC_MIPS_GIC
>> 499 select COMMON_CLK
>> 500 select DMA_MAYBE_COHERENT
>> 501 select GENERIC_ISA_DMA
>> 502 select HAVE_PCSPKR_PLATFORM
>> 503 select IRQ_MIPS_CPU
>> 504 select MIPS_GIC
>> 505 select HW_HAS_PCI
>> 506 select I8253
>> 507 select I8259
>> 508 select MIPS_BONITO64
>> 509 select MIPS_CPU_SCACHE
>> 510 select MIPS_L1_CACHE_SHIFT_6
>> 511 select PCI_GT64XXX_PCI0
>> 512 select MIPS_MSC
>> 513 select SMP_UP if SMP
>> 514 select SWAP_IO_SPACE
>> 515 select SYS_HAS_CPU_MIPS32_R1
>> 516 select SYS_HAS_CPU_MIPS32_R2
>> 517 select SYS_HAS_CPU_MIPS32_R3_5
>> 518 select SYS_HAS_CPU_MIPS32_R5
>> 519 select SYS_HAS_CPU_MIPS32_R6
>> 520 select SYS_HAS_CPU_MIPS64_R1
>> 521 select SYS_HAS_CPU_MIPS64_R2
>> 522 select SYS_HAS_CPU_MIPS64_R6
>> 523 select SYS_HAS_CPU_NEVADA
>> 524 select SYS_HAS_CPU_RM7000
>> 525 select SYS_SUPPORTS_32BIT_KERNEL
>> 526 select SYS_SUPPORTS_64BIT_KERNEL
>> 527 select SYS_SUPPORTS_BIG_ENDIAN
>> 528 select SYS_SUPPORTS_HIGHMEM
>> 529 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 530 select SYS_SUPPORTS_MICROMIPS
>> 531 select SYS_SUPPORTS_MIPS_CMP
>> 532 select SYS_SUPPORTS_MIPS_CPS
>> 533 select SYS_SUPPORTS_MIPS16
>> 534 select SYS_SUPPORTS_MULTITHREADING
>> 535 select SYS_SUPPORTS_SMARTMIPS
>> 536 select SYS_SUPPORTS_ZBOOT
>> 537 select SYS_SUPPORTS_RELOCATABLE
>> 538 select USE_OF
>> 539 select LIBFDT
>> 540 select ZONE_DMA32 if 64BIT
>> 541 select BUILTIN_DTB
>> 542 select LIBFDT
>> 543 help
>> 544 This enables support for the MIPS Technologies Malta evaluation
>> 545 board.
369 546
370 config SMP !! 547 config MACH_PIC32
371 def_bool y !! 548 bool "Microchip PIC32 Family"
>> 549 help
>> 550 This enables support for the Microchip PIC32 family of platforms.
372 551
373 config KERNEL_MODE_NEON !! 552 Microchip PIC32 is a family of general-purpose 32 bit MIPS core
374 def_bool y !! 553 microcontrollers.
>> 554
>> 555 config NEC_MARKEINS
>> 556 bool "NEC EMMA2RH Mark-eins board"
>> 557 select SOC_EMMA2RH
>> 558 select HW_HAS_PCI
>> 559 help
>> 560 This enables support for the NEC Electronics Mark-eins boards.
>> 561
>> 562 config MACH_VR41XX
>> 563 bool "NEC VR4100 series based machines"
>> 564 select CEVT_R4K
>> 565 select CSRC_R4K
>> 566 select SYS_HAS_CPU_VR41XX
>> 567 select SYS_SUPPORTS_MIPS16
>> 568 select GPIOLIB
>> 569
>> 570 config NXP_STB220
>> 571 bool "NXP STB220 board"
>> 572 select SOC_PNX833X
>> 573 help
>> 574 Support for NXP Semiconductors STB220 Development Board.
>> 575
>> 576 config NXP_STB225
>> 577 bool "NXP 225 board"
>> 578 select SOC_PNX833X
>> 579 select SOC_PNX8335
>> 580 help
>> 581 Support for NXP Semiconductors STB225 Development Board.
>> 582
>> 583 config PMC_MSP
>> 584 bool "PMC-Sierra MSP chipsets"
>> 585 select CEVT_R4K
>> 586 select CSRC_R4K
>> 587 select DMA_NONCOHERENT
>> 588 select SWAP_IO_SPACE
>> 589 select NO_EXCEPT_FILL
>> 590 select BOOT_RAW
>> 591 select SYS_HAS_CPU_MIPS32_R1
>> 592 select SYS_HAS_CPU_MIPS32_R2
>> 593 select SYS_SUPPORTS_32BIT_KERNEL
>> 594 select SYS_SUPPORTS_BIG_ENDIAN
>> 595 select SYS_SUPPORTS_MIPS16
>> 596 select IRQ_MIPS_CPU
>> 597 select SERIAL_8250
>> 598 select SERIAL_8250_CONSOLE
>> 599 select USB_EHCI_BIG_ENDIAN_MMIO
>> 600 select USB_EHCI_BIG_ENDIAN_DESC
>> 601 help
>> 602 This adds support for the PMC-Sierra family of Multi-Service
>> 603 Processor System-On-A-Chips. These parts include a number
>> 604 of integrated peripherals, interfaces and DSPs in addition to
>> 605 a variety of MIPS cores.
>> 606
>> 607 config RALINK
>> 608 bool "Ralink based machines"
>> 609 select CEVT_R4K
>> 610 select CSRC_R4K
>> 611 select BOOT_RAW
>> 612 select DMA_NONCOHERENT
>> 613 select IRQ_MIPS_CPU
>> 614 select USE_OF
>> 615 select SYS_HAS_CPU_MIPS32_R1
>> 616 select SYS_HAS_CPU_MIPS32_R2
>> 617 select SYS_SUPPORTS_32BIT_KERNEL
>> 618 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 619 select SYS_SUPPORTS_MIPS16
>> 620 select SYS_HAS_EARLY_PRINTK
>> 621 select CLKDEV_LOOKUP
>> 622 select ARCH_HAS_RESET_CONTROLLER
>> 623 select RESET_CONTROLLER
>> 624
>> 625 config SGI_IP22
>> 626 bool "SGI IP22 (Indy/Indigo2)"
>> 627 select FW_ARC
>> 628 select FW_ARC32
>> 629 select BOOT_ELF32
>> 630 select CEVT_R4K
>> 631 select CSRC_R4K
>> 632 select DEFAULT_SGI_PARTITION
>> 633 select DMA_NONCOHERENT
>> 634 select HW_HAS_EISA
>> 635 select I8253
>> 636 select I8259
>> 637 select IP22_CPU_SCACHE
>> 638 select IRQ_MIPS_CPU
>> 639 select GENERIC_ISA_DMA_SUPPORT_BROKEN
>> 640 select SGI_HAS_I8042
>> 641 select SGI_HAS_INDYDOG
>> 642 select SGI_HAS_HAL2
>> 643 select SGI_HAS_SEEQ
>> 644 select SGI_HAS_WD93
>> 645 select SGI_HAS_ZILOG
>> 646 select SWAP_IO_SPACE
>> 647 select SYS_HAS_CPU_R4X00
>> 648 select SYS_HAS_CPU_R5000
>> 649 #
>> 650 # Disable EARLY_PRINTK for now since it leads to overwritten prom
>> 651 # memory during early boot on some machines.
>> 652 #
>> 653 # See http://www.linux-mips.org/cgi-bin/mesg.cgi?a=linux-mips&i=20091119164009.GA15038%40deprecation.cyrius.com
>> 654 # for a more details discussion
>> 655 #
>> 656 # select SYS_HAS_EARLY_PRINTK
>> 657 select SYS_SUPPORTS_32BIT_KERNEL
>> 658 select SYS_SUPPORTS_64BIT_KERNEL
>> 659 select SYS_SUPPORTS_BIG_ENDIAN
>> 660 select MIPS_L1_CACHE_SHIFT_7
>> 661 help
>> 662 This are the SGI Indy, Challenge S and Indigo2, as well as certain
>> 663 OEM variants like the Tandem CMN B006S. To compile a Linux kernel
>> 664 that runs on these, say Y here.
>> 665
>> 666 config SGI_IP27
>> 667 bool "SGI IP27 (Origin200/2000)"
>> 668 select FW_ARC
>> 669 select FW_ARC64
>> 670 select BOOT_ELF64
>> 671 select DEFAULT_SGI_PARTITION
>> 672 select DMA_COHERENT
>> 673 select SYS_HAS_EARLY_PRINTK
>> 674 select HW_HAS_PCI
>> 675 select NR_CPUS_DEFAULT_64
>> 676 select SYS_HAS_CPU_R10000
>> 677 select SYS_SUPPORTS_64BIT_KERNEL
>> 678 select SYS_SUPPORTS_BIG_ENDIAN
>> 679 select SYS_SUPPORTS_NUMA
>> 680 select SYS_SUPPORTS_SMP
>> 681 select MIPS_L1_CACHE_SHIFT_7
>> 682 help
>> 683 This are the SGI Origin 200, Origin 2000 and Onyx 2 Graphics
>> 684 workstations. To compile a Linux kernel that runs on these, say Y
>> 685 here.
>> 686
>> 687 config SGI_IP28
>> 688 bool "SGI IP28 (Indigo2 R10k)"
>> 689 select FW_ARC
>> 690 select FW_ARC64
>> 691 select BOOT_ELF64
>> 692 select CEVT_R4K
>> 693 select CSRC_R4K
>> 694 select DEFAULT_SGI_PARTITION
>> 695 select DMA_NONCOHERENT
>> 696 select GENERIC_ISA_DMA_SUPPORT_BROKEN
>> 697 select IRQ_MIPS_CPU
>> 698 select HW_HAS_EISA
>> 699 select I8253
>> 700 select I8259
>> 701 select SGI_HAS_I8042
>> 702 select SGI_HAS_INDYDOG
>> 703 select SGI_HAS_HAL2
>> 704 select SGI_HAS_SEEQ
>> 705 select SGI_HAS_WD93
>> 706 select SGI_HAS_ZILOG
>> 707 select SWAP_IO_SPACE
>> 708 select SYS_HAS_CPU_R10000
>> 709 #
>> 710 # Disable EARLY_PRINTK for now since it leads to overwritten prom
>> 711 # memory during early boot on some machines.
>> 712 #
>> 713 # See http://www.linux-mips.org/cgi-bin/mesg.cgi?a=linux-mips&i=20091119164009.GA15038%40deprecation.cyrius.com
>> 714 # for a more details discussion
>> 715 #
>> 716 # select SYS_HAS_EARLY_PRINTK
>> 717 select SYS_SUPPORTS_64BIT_KERNEL
>> 718 select SYS_SUPPORTS_BIG_ENDIAN
>> 719 select MIPS_L1_CACHE_SHIFT_7
>> 720 help
>> 721 This is the SGI Indigo2 with R10000 processor. To compile a Linux
>> 722 kernel that runs on these, say Y here.
>> 723
>> 724 config SGI_IP32
>> 725 bool "SGI IP32 (O2)"
>> 726 select FW_ARC
>> 727 select FW_ARC32
>> 728 select BOOT_ELF32
>> 729 select CEVT_R4K
>> 730 select CSRC_R4K
>> 731 select DMA_NONCOHERENT
>> 732 select HW_HAS_PCI
>> 733 select IRQ_MIPS_CPU
>> 734 select R5000_CPU_SCACHE
>> 735 select RM7000_CPU_SCACHE
>> 736 select SYS_HAS_CPU_R5000
>> 737 select SYS_HAS_CPU_R10000 if BROKEN
>> 738 select SYS_HAS_CPU_RM7000
>> 739 select SYS_HAS_CPU_NEVADA
>> 740 select SYS_SUPPORTS_64BIT_KERNEL
>> 741 select SYS_SUPPORTS_BIG_ENDIAN
>> 742 help
>> 743 If you want this kernel to run on SGI O2 workstation, say Y here.
>> 744
>> 745 config SIBYTE_CRHINE
>> 746 bool "Sibyte BCM91120C-CRhine"
>> 747 select BOOT_ELF32
>> 748 select DMA_COHERENT
>> 749 select SIBYTE_BCM1120
>> 750 select SWAP_IO_SPACE
>> 751 select SYS_HAS_CPU_SB1
>> 752 select SYS_SUPPORTS_BIG_ENDIAN
>> 753 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 754
>> 755 config SIBYTE_CARMEL
>> 756 bool "Sibyte BCM91120x-Carmel"
>> 757 select BOOT_ELF32
>> 758 select DMA_COHERENT
>> 759 select SIBYTE_BCM1120
>> 760 select SWAP_IO_SPACE
>> 761 select SYS_HAS_CPU_SB1
>> 762 select SYS_SUPPORTS_BIG_ENDIAN
>> 763 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 764
>> 765 config SIBYTE_CRHONE
>> 766 bool "Sibyte BCM91125C-CRhone"
>> 767 select BOOT_ELF32
>> 768 select DMA_COHERENT
>> 769 select SIBYTE_BCM1125
>> 770 select SWAP_IO_SPACE
>> 771 select SYS_HAS_CPU_SB1
>> 772 select SYS_SUPPORTS_BIG_ENDIAN
>> 773 select SYS_SUPPORTS_HIGHMEM
>> 774 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 775
>> 776 config SIBYTE_RHONE
>> 777 bool "Sibyte BCM91125E-Rhone"
>> 778 select BOOT_ELF32
>> 779 select DMA_COHERENT
>> 780 select SIBYTE_BCM1125H
>> 781 select SWAP_IO_SPACE
>> 782 select SYS_HAS_CPU_SB1
>> 783 select SYS_SUPPORTS_BIG_ENDIAN
>> 784 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 785
>> 786 config SIBYTE_SWARM
>> 787 bool "Sibyte BCM91250A-SWARM"
>> 788 select BOOT_ELF32
>> 789 select DMA_COHERENT
>> 790 select HAVE_PATA_PLATFORM
>> 791 select SIBYTE_SB1250
>> 792 select SWAP_IO_SPACE
>> 793 select SYS_HAS_CPU_SB1
>> 794 select SYS_SUPPORTS_BIG_ENDIAN
>> 795 select SYS_SUPPORTS_HIGHMEM
>> 796 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 797 select ZONE_DMA32 if 64BIT
>> 798
>> 799 config SIBYTE_LITTLESUR
>> 800 bool "Sibyte BCM91250C2-LittleSur"
>> 801 select BOOT_ELF32
>> 802 select DMA_COHERENT
>> 803 select HAVE_PATA_PLATFORM
>> 804 select SIBYTE_SB1250
>> 805 select SWAP_IO_SPACE
>> 806 select SYS_HAS_CPU_SB1
>> 807 select SYS_SUPPORTS_BIG_ENDIAN
>> 808 select SYS_SUPPORTS_HIGHMEM
>> 809 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 810 select ZONE_DMA32 if 64BIT
>> 811
>> 812 config SIBYTE_SENTOSA
>> 813 bool "Sibyte BCM91250E-Sentosa"
>> 814 select BOOT_ELF32
>> 815 select DMA_COHERENT
>> 816 select SIBYTE_SB1250
>> 817 select SWAP_IO_SPACE
>> 818 select SYS_HAS_CPU_SB1
>> 819 select SYS_SUPPORTS_BIG_ENDIAN
>> 820 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 821
>> 822 config SIBYTE_BIGSUR
>> 823 bool "Sibyte BCM91480B-BigSur"
>> 824 select BOOT_ELF32
>> 825 select DMA_COHERENT
>> 826 select NR_CPUS_DEFAULT_4
>> 827 select SIBYTE_BCM1x80
>> 828 select SWAP_IO_SPACE
>> 829 select SYS_HAS_CPU_SB1
>> 830 select SYS_SUPPORTS_BIG_ENDIAN
>> 831 select SYS_SUPPORTS_HIGHMEM
>> 832 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 833 select ZONE_DMA32 if 64BIT
>> 834
>> 835 config SNI_RM
>> 836 bool "SNI RM200/300/400"
>> 837 select FW_ARC if CPU_LITTLE_ENDIAN
>> 838 select FW_ARC32 if CPU_LITTLE_ENDIAN
>> 839 select FW_SNIPROM if CPU_BIG_ENDIAN
>> 840 select ARCH_MAY_HAVE_PC_FDC
>> 841 select BOOT_ELF32
>> 842 select CEVT_R4K
>> 843 select CSRC_R4K
>> 844 select DEFAULT_SGI_PARTITION if CPU_BIG_ENDIAN
>> 845 select DMA_NONCOHERENT
>> 846 select GENERIC_ISA_DMA
>> 847 select HAVE_PCSPKR_PLATFORM
>> 848 select HW_HAS_EISA
>> 849 select HW_HAS_PCI
>> 850 select IRQ_MIPS_CPU
>> 851 select I8253
>> 852 select I8259
>> 853 select ISA
>> 854 select MIPS_L1_CACHE_SHIFT_6
>> 855 select SWAP_IO_SPACE if CPU_BIG_ENDIAN
>> 856 select SYS_HAS_CPU_R4X00
>> 857 select SYS_HAS_CPU_R5000
>> 858 select SYS_HAS_CPU_R10000
>> 859 select R5000_CPU_SCACHE
>> 860 select SYS_HAS_EARLY_PRINTK
>> 861 select SYS_SUPPORTS_32BIT_KERNEL
>> 862 select SYS_SUPPORTS_64BIT_KERNEL
>> 863 select SYS_SUPPORTS_BIG_ENDIAN
>> 864 select SYS_SUPPORTS_HIGHMEM
>> 865 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 866 help
>> 867 The SNI RM200/300/400 are MIPS-based machines manufactured by
>> 868 Siemens Nixdorf Informationssysteme (SNI), parent company of Pyramid
>> 869 Technology and now in turn merged with Fujitsu. Say Y here to
>> 870 support this machine type.
>> 871
>> 872 config MACH_TX39XX
>> 873 bool "Toshiba TX39 series based machines"
>> 874
>> 875 config MACH_TX49XX
>> 876 bool "Toshiba TX49 series based machines"
>> 877
>> 878 config MIKROTIK_RB532
>> 879 bool "Mikrotik RB532 boards"
>> 880 select CEVT_R4K
>> 881 select CSRC_R4K
>> 882 select DMA_NONCOHERENT
>> 883 select HW_HAS_PCI
>> 884 select IRQ_MIPS_CPU
>> 885 select SYS_HAS_CPU_MIPS32_R1
>> 886 select SYS_SUPPORTS_32BIT_KERNEL
>> 887 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 888 select SWAP_IO_SPACE
>> 889 select BOOT_RAW
>> 890 select GPIOLIB
>> 891 select MIPS_L1_CACHE_SHIFT_4
>> 892 help
>> 893 Support the Mikrotik(tm) RouterBoard 532 series,
>> 894 based on the IDT RC32434 SoC.
>> 895
>> 896 config CAVIUM_OCTEON_SOC
>> 897 bool "Cavium Networks Octeon SoC based boards"
>> 898 select CEVT_R4K
>> 899 select ARCH_PHYS_ADDR_T_64BIT
>> 900 select DMA_COHERENT
>> 901 select SYS_SUPPORTS_64BIT_KERNEL
>> 902 select SYS_SUPPORTS_BIG_ENDIAN
>> 903 select EDAC_SUPPORT
>> 904 select EDAC_ATOMIC_SCRUB
>> 905 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 906 select SYS_SUPPORTS_HOTPLUG_CPU if CPU_BIG_ENDIAN
>> 907 select SYS_HAS_EARLY_PRINTK
>> 908 select SYS_HAS_CPU_CAVIUM_OCTEON
>> 909 select HW_HAS_PCI
>> 910 select ZONE_DMA32
>> 911 select HOLES_IN_ZONE
>> 912 select GPIOLIB
>> 913 select LIBFDT
>> 914 select USE_OF
>> 915 select ARCH_SPARSEMEM_ENABLE
>> 916 select SYS_SUPPORTS_SMP
>> 917 select NR_CPUS_DEFAULT_16
>> 918 select BUILTIN_DTB
>> 919 select MTD_COMPLEX_MAPPINGS
>> 920 help
>> 921 This option supports all of the Octeon reference boards from Cavium
>> 922 Networks. It builds a kernel that dynamically determines the Octeon
>> 923 CPU type and supports all known board reference implementations.
>> 924 Some of the supported boards are:
>> 925 EBT3000
>> 926 EBH3000
>> 927 EBH3100
>> 928 Thunder
>> 929 Kodama
>> 930 Hikari
>> 931 Say Y here for most Octeon reference boards.
>> 932
>> 933 config NLM_XLR_BOARD
>> 934 bool "Netlogic XLR/XLS based systems"
>> 935 select BOOT_ELF32
>> 936 select NLM_COMMON
>> 937 select SYS_HAS_CPU_XLR
>> 938 select SYS_SUPPORTS_SMP
>> 939 select HW_HAS_PCI
>> 940 select SWAP_IO_SPACE
>> 941 select SYS_SUPPORTS_32BIT_KERNEL
>> 942 select SYS_SUPPORTS_64BIT_KERNEL
>> 943 select ARCH_PHYS_ADDR_T_64BIT
>> 944 select SYS_SUPPORTS_BIG_ENDIAN
>> 945 select SYS_SUPPORTS_HIGHMEM
>> 946 select DMA_COHERENT
>> 947 select NR_CPUS_DEFAULT_32
>> 948 select CEVT_R4K
>> 949 select CSRC_R4K
>> 950 select IRQ_MIPS_CPU
>> 951 select ZONE_DMA32 if 64BIT
>> 952 select SYNC_R4K
>> 953 select SYS_HAS_EARLY_PRINTK
>> 954 select SYS_SUPPORTS_ZBOOT
>> 955 select SYS_SUPPORTS_ZBOOT_UART16550
>> 956 help
>> 957 Support for systems based on Netlogic XLR and XLS processors.
>> 958 Say Y here if you have a XLR or XLS based board.
>> 959
>> 960 config NLM_XLP_BOARD
>> 961 bool "Netlogic XLP based systems"
>> 962 select BOOT_ELF32
>> 963 select NLM_COMMON
>> 964 select SYS_HAS_CPU_XLP
>> 965 select SYS_SUPPORTS_SMP
>> 966 select HW_HAS_PCI
>> 967 select SYS_SUPPORTS_32BIT_KERNEL
>> 968 select SYS_SUPPORTS_64BIT_KERNEL
>> 969 select ARCH_PHYS_ADDR_T_64BIT
>> 970 select GPIOLIB
>> 971 select SYS_SUPPORTS_BIG_ENDIAN
>> 972 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 973 select SYS_SUPPORTS_HIGHMEM
>> 974 select DMA_COHERENT
>> 975 select NR_CPUS_DEFAULT_32
>> 976 select CEVT_R4K
>> 977 select CSRC_R4K
>> 978 select IRQ_MIPS_CPU
>> 979 select ZONE_DMA32 if 64BIT
>> 980 select SYNC_R4K
>> 981 select SYS_HAS_EARLY_PRINTK
>> 982 select USE_OF
>> 983 select SYS_SUPPORTS_ZBOOT
>> 984 select SYS_SUPPORTS_ZBOOT_UART16550
>> 985 help
>> 986 This board is based on Netlogic XLP Processor.
>> 987 Say Y here if you have a XLP based board.
>> 988
>> 989 config MIPS_PARAVIRT
>> 990 bool "Para-Virtualized guest system"
>> 991 select CEVT_R4K
>> 992 select CSRC_R4K
>> 993 select DMA_COHERENT
>> 994 select SYS_SUPPORTS_64BIT_KERNEL
>> 995 select SYS_SUPPORTS_32BIT_KERNEL
>> 996 select SYS_SUPPORTS_BIG_ENDIAN
>> 997 select SYS_SUPPORTS_SMP
>> 998 select NR_CPUS_DEFAULT_4
>> 999 select SYS_HAS_EARLY_PRINTK
>> 1000 select SYS_HAS_CPU_MIPS32_R2
>> 1001 select SYS_HAS_CPU_MIPS64_R2
>> 1002 select SYS_HAS_CPU_CAVIUM_OCTEON
>> 1003 select HW_HAS_PCI
>> 1004 select SWAP_IO_SPACE
>> 1005 help
>> 1006 This option supports guest running under ????
375 1007
376 config FIX_EARLYCON_MEM !! 1008 endchoice
377 def_bool y <<
378 1009
379 config PGTABLE_LEVELS !! 1010 source "arch/mips/alchemy/Kconfig"
380 int !! 1011 source "arch/mips/ath25/Kconfig"
381 default 2 if ARM64_16K_PAGES && ARM64_ !! 1012 source "arch/mips/ath79/Kconfig"
382 default 2 if ARM64_64K_PAGES && ARM64_ !! 1013 source "arch/mips/bcm47xx/Kconfig"
383 default 3 if ARM64_64K_PAGES && (ARM64 !! 1014 source "arch/mips/bcm63xx/Kconfig"
384 default 3 if ARM64_4K_PAGES && ARM64_V !! 1015 source "arch/mips/bmips/Kconfig"
385 default 3 if ARM64_16K_PAGES && ARM64_ !! 1016 source "arch/mips/generic/Kconfig"
386 default 4 if ARM64_16K_PAGES && (ARM64 !! 1017 source "arch/mips/jazz/Kconfig"
387 default 4 if !ARM64_64K_PAGES && ARM64 !! 1018 source "arch/mips/jz4740/Kconfig"
388 default 5 if ARM64_4K_PAGES && ARM64_V !! 1019 source "arch/mips/lantiq/Kconfig"
>> 1020 source "arch/mips/lasat/Kconfig"
>> 1021 source "arch/mips/pic32/Kconfig"
>> 1022 source "arch/mips/pistachio/Kconfig"
>> 1023 source "arch/mips/pmcs-msp71xx/Kconfig"
>> 1024 source "arch/mips/ralink/Kconfig"
>> 1025 source "arch/mips/sgi-ip27/Kconfig"
>> 1026 source "arch/mips/sibyte/Kconfig"
>> 1027 source "arch/mips/txx9/Kconfig"
>> 1028 source "arch/mips/vr41xx/Kconfig"
>> 1029 source "arch/mips/cavium-octeon/Kconfig"
>> 1030 source "arch/mips/loongson32/Kconfig"
>> 1031 source "arch/mips/loongson64/Kconfig"
>> 1032 source "arch/mips/netlogic/Kconfig"
>> 1033 source "arch/mips/paravirt/Kconfig"
>> 1034 source "arch/mips/xilfpga/Kconfig"
389 1035
390 config ARCH_SUPPORTS_UPROBES !! 1036 endmenu
391 def_bool y <<
392 1037
393 config ARCH_PROC_KCORE_TEXT !! 1038 config RWSEM_GENERIC_SPINLOCK
394 def_bool y !! 1039 bool
>> 1040 default y
395 1041
396 config BROKEN_GAS_INST !! 1042 config RWSEM_XCHGADD_ALGORITHM
397 def_bool !$(as-instr,1:\n.inst 0\n.rep !! 1043 bool
398 1044
399 config BUILTIN_RETURN_ADDRESS_STRIPS_PAC !! 1045 config ARCH_HAS_ILOG2_U32
400 bool 1046 bool
401 # Clang's __builtin_return_address() s <<
402 # https://github.com/llvm/llvm-project <<
403 default y if CC_IS_CLANG <<
404 # GCC's __builtin_return_address() str <<
405 # and this was backported to 10.2.0, 9 <<
406 # https://gcc.gnu.org/bugzilla/show_bu <<
407 default y if CC_IS_GCC && (GCC_VERSION <<
408 default y if CC_IS_GCC && (GCC_VERSION <<
409 default y if CC_IS_GCC && (GCC_VERSION <<
410 default y if CC_IS_GCC && (GCC_VERSION <<
411 default n 1047 default n
412 1048
413 config KASAN_SHADOW_OFFSET !! 1049 config ARCH_HAS_ILOG2_U64
414 hex <<
415 depends on KASAN_GENERIC || KASAN_SW_T <<
416 default 0xdfff800000000000 if (ARM64_V <<
417 default 0xdfffc00000000000 if (ARM64_V <<
418 default 0xdffffe0000000000 if ARM64_VA <<
419 default 0xdfffffc000000000 if ARM64_VA <<
420 default 0xdffffff800000000 if ARM64_VA <<
421 default 0xefff800000000000 if (ARM64_V <<
422 default 0xefffc00000000000 if (ARM64_V <<
423 default 0xeffffe0000000000 if ARM64_VA <<
424 default 0xefffffc000000000 if ARM64_VA <<
425 default 0xeffffff800000000 if ARM64_VA <<
426 default 0xffffffffffffffff <<
427 <<
428 config UNWIND_TABLES <<
429 bool <<
430 <<
431 source "arch/arm64/Kconfig.platforms" <<
432 <<
433 menu "Kernel Features" <<
434 <<
435 menu "ARM errata workarounds via the alternati <<
436 <<
437 config AMPERE_ERRATUM_AC03_CPU_38 <<
438 bool "AmpereOne: AC03_CPU_38: Certain <<
439 default y <<
440 help <<
441 This option adds an alternative code <<
442 errata AC03_CPU_38 and AC04_CPU_10 o <<
443 <<
444 The affected design reports FEAT_HAF <<
445 ID_AA64MMFR1_EL1.HAFDBS, but (V)TCR_ <<
446 as required by the architecture. The <<
447 implementation suffers from an addit <<
448 A/D updates can occur after a PTE ha <<
449 <<
450 The workaround forces KVM to explici <<
451 which avoids enabling unadvertised h <<
452 at stage-2. <<
453 <<
454 If unsure, say Y. <<
455 <<
456 config ARM64_WORKAROUND_CLEAN_CACHE <<
457 bool 1050 bool
>> 1051 default n
458 1052
459 config ARM64_ERRATUM_826319 !! 1053 config GENERIC_HWEIGHT
460 bool "Cortex-A53: 826319: System might !! 1054 bool
461 default y 1055 default y
462 select ARM64_WORKAROUND_CLEAN_CACHE <<
463 help <<
464 This option adds an alternative code <<
465 erratum 826319 on Cortex-A53 parts u <<
466 AXI master interface and an L2 cache <<
467 <<
468 If a Cortex-A53 uses an AMBA AXI4 AC <<
469 and is unable to accept a certain wr <<
470 not progress on read data presented <<
471 system can deadlock. <<
472 1056
473 The workaround promotes data cache c !! 1057 config GENERIC_CALIBRATE_DELAY
474 data cache clean-and-invalidate. !! 1058 bool
475 Please note that this does not neces <<
476 as it depends on the alternative fra <<
477 the kernel if an affected CPU is det <<
478 <<
479 If unsure, say Y. <<
480 <<
481 config ARM64_ERRATUM_827319 <<
482 bool "Cortex-A53: 827319: Data cache c <<
483 default y 1059 default y
484 select ARM64_WORKAROUND_CLEAN_CACHE <<
485 help <<
486 This option adds an alternative code <<
487 erratum 827319 on Cortex-A53 parts u <<
488 master interface and an L2 cache. <<
489 <<
490 Under certain conditions this erratu <<
491 to occur at the same time as another <<
492 on the AMBA 5 CHI interface, which c <<
493 interconnect reorders the two transa <<
494 <<
495 The workaround promotes data cache c <<
496 data cache clean-and-invalidate. <<
497 Please note that this does not neces <<
498 as it depends on the alternative fra <<
499 the kernel if an affected CPU is det <<
500 <<
501 If unsure, say Y. <<
502 1060
503 config ARM64_ERRATUM_824069 !! 1061 config SCHED_OMIT_FRAME_POINTER
504 bool "Cortex-A53: 824069: Cache line m !! 1062 bool
505 default y 1063 default y
506 select ARM64_WORKAROUND_CLEAN_CACHE <<
507 help <<
508 This option adds an alternative code <<
509 erratum 824069 on Cortex-A53 parts u <<
510 to a coherent interconnect. <<
511 <<
512 If a Cortex-A53 processor is executi <<
513 write instruction at the same time a <<
514 cluster is executing a cache mainten <<
515 address, then this erratum might cau <<
516 incorrectly marked as dirty. <<
517 <<
518 The workaround promotes data cache c <<
519 data cache clean-and-invalidate. <<
520 Please note that this option does no <<
521 workaround, as it depends on the alt <<
522 only patch the kernel if an affected <<
523 <<
524 If unsure, say Y. <<
525 1064
526 config ARM64_ERRATUM_819472 !! 1065 #
527 bool "Cortex-A53: 819472: Store exclus !! 1066 # Select some configuration options automatically based on user selections.
528 default y !! 1067 #
529 select ARM64_WORKAROUND_CLEAN_CACHE !! 1068 config FW_ARC
530 help !! 1069 bool
531 This option adds an alternative code <<
532 erratum 819472 on Cortex-A53 parts u <<
533 present when it is connected to a co <<
534 <<
535 If the processor is executing a load <<
536 the same time as a processor in anot <<
537 maintenance operation to the same ad <<
538 cause data corruption. <<
539 <<
540 The workaround promotes data cache c <<
541 data cache clean-and-invalidate. <<
542 Please note that this does not neces <<
543 as it depends on the alternative fra <<
544 the kernel if an affected CPU is det <<
545 1070
546 If unsure, say Y. !! 1071 config ARCH_MAY_HAVE_PC_FDC
>> 1072 bool
547 1073
548 config ARM64_ERRATUM_832075 !! 1074 config BOOT_RAW
549 bool "Cortex-A57: 832075: possible dea !! 1075 bool
550 default y <<
551 help <<
552 This option adds an alternative code <<
553 erratum 832075 on Cortex-A57 parts u <<
554 1076
555 Affected Cortex-A57 parts might dead !! 1077 config CEVT_BCM1480
556 instructions to Write-Back memory ar !! 1078 bool
557 1079
558 The workaround is to promote device !! 1080 config CEVT_DS1287
559 semantics. !! 1081 bool
560 Please note that this does not neces <<
561 as it depends on the alternative fra <<
562 the kernel if an affected CPU is det <<
563 1082
564 If unsure, say Y. !! 1083 config CEVT_GT641XX
>> 1084 bool
565 1085
566 config ARM64_ERRATUM_834220 !! 1086 config CEVT_R4K
567 bool "Cortex-A57: 834220: Stage 2 tran !! 1087 bool
568 depends on KVM <<
569 help <<
570 This option adds an alternative code <<
571 erratum 834220 on Cortex-A57 parts u <<
572 <<
573 Affected Cortex-A57 parts might repo <<
574 fault as the result of a Stage 1 fau <<
575 page boundary when there is a permis <<
576 alignment fault at Stage 1 and a tra <<
577 <<
578 The workaround is to verify that the <<
579 doesn't generate a fault before hand <<
580 Please note that this does not neces <<
581 as it depends on the alternative fra <<
582 the kernel if an affected CPU is det <<
583 1088
584 If unsure, say N. !! 1089 config CEVT_SB1250
>> 1090 bool
585 1091
586 config ARM64_ERRATUM_1742098 !! 1092 config CEVT_TXX9
587 bool "Cortex-A57/A72: 1742098: ELR rec !! 1093 bool
588 depends on COMPAT <<
589 default y <<
590 help <<
591 This option removes the AES hwcap fo <<
592 workaround erratum 1742098 on Cortex <<
593 <<
594 Affected parts may corrupt the AES s <<
595 taken between a pair of AES instruct <<
596 are only present if the cryptography <<
597 All software should have a fallback <<
598 that don't implement the cryptograph <<
599 1094
600 If unsure, say Y. !! 1095 config CSRC_BCM1480
>> 1096 bool
601 1097
602 config ARM64_ERRATUM_845719 !! 1098 config CSRC_IOASIC
603 bool "Cortex-A53: 845719: a load might !! 1099 bool
604 depends on COMPAT <<
605 default y <<
606 help <<
607 This option adds an alternative code <<
608 erratum 845719 on Cortex-A53 parts u <<
609 <<
610 When running a compat (AArch32) user <<
611 part, a load at EL0 from a virtual a <<
612 bits of the virtual address used by <<
613 might return incorrect data. <<
614 <<
615 The workaround is to write the conte <<
616 return to a 32-bit task. <<
617 Please note that this does not neces <<
618 as it depends on the alternative fra <<
619 the kernel if an affected CPU is det <<
620 1100
621 If unsure, say Y. !! 1101 config CSRC_R4K
>> 1102 bool
622 1103
623 config ARM64_ERRATUM_843419 !! 1104 config CSRC_SB1250
624 bool "Cortex-A53: 843419: A load or st !! 1105 bool
625 default y <<
626 help <<
627 This option links the kernel with '- <<
628 enables PLT support to replace certa <<
629 cause subsequent memory accesses to <<
630 Cortex-A53 parts up to r0p4. <<
631 1106
632 If unsure, say Y. !! 1107 config MIPS_CLOCK_VSYSCALL
>> 1108 def_bool CSRC_R4K || CLKSRC_MIPS_GIC
633 1109
634 config ARM64_LD_HAS_FIX_ERRATUM_843419 !! 1110 config GPIO_TXX9
635 def_bool $(ld-option,--fix-cortex-a53- !! 1111 select GPIOLIB
>> 1112 bool
636 1113
637 config ARM64_ERRATUM_1024718 !! 1114 config FW_CFE
638 bool "Cortex-A55: 1024718: Update of D !! 1115 bool
639 default y <<
640 help <<
641 This option adds a workaround for AR <<
642 1116
643 Affected Cortex-A55 cores (all revis !! 1117 config ARCH_DMA_ADDR_T_64BIT
644 update of the hardware dirty bit whe !! 1118 def_bool (HIGHMEM && ARCH_PHYS_ADDR_T_64BIT) || 64BIT
645 without a break-before-make. The wor <<
646 of hardware DBM locally on the affec <<
647 this erratum will continue to use th <<
648 1119
649 If unsure, say Y. !! 1120 config ARCH_SUPPORTS_UPROBES
>> 1121 bool
650 1122
651 config ARM64_ERRATUM_1418040 !! 1123 config DMA_MAYBE_COHERENT
652 bool "Cortex-A76/Neoverse-N1: MRC read !! 1124 select DMA_NONCOHERENT
653 default y !! 1125 bool
654 depends on COMPAT <<
655 help <<
656 This option adds a workaround for AR <<
657 errata 1188873 and 1418040. <<
658 1126
659 Affected Cortex-A76/Neoverse-N1 core !! 1127 config DMA_PERDEV_COHERENT
660 cause register corruption when acces !! 1128 bool
661 from AArch32 userspace. !! 1129 select DMA_MAYBE_COHERENT
662 1130
663 If unsure, say Y. !! 1131 config DMA_COHERENT
>> 1132 bool
664 1133
665 config ARM64_WORKAROUND_SPECULATIVE_AT !! 1134 config DMA_NONCOHERENT
666 bool 1135 bool
>> 1136 select NEED_DMA_MAP_STATE
667 1137
668 config ARM64_ERRATUM_1165522 !! 1138 config NEED_DMA_MAP_STATE
669 bool "Cortex-A76: 1165522: Speculative !! 1139 bool
670 default y <<
671 select ARM64_WORKAROUND_SPECULATIVE_AT <<
672 help <<
673 This option adds a workaround for AR <<
674 1140
675 Affected Cortex-A76 cores (r0p0, r1p !! 1141 config SYS_HAS_EARLY_PRINTK
676 corrupted TLBs by speculating an AT !! 1142 bool
677 context switch. <<
678 1143
679 If unsure, say Y. !! 1144 config SYS_SUPPORTS_HOTPLUG_CPU
>> 1145 bool
680 1146
681 config ARM64_ERRATUM_1319367 !! 1147 config MIPS_BONITO64
682 bool "Cortex-A57/A72: 1319537: Specula !! 1148 bool
683 default y <<
684 select ARM64_WORKAROUND_SPECULATIVE_AT <<
685 help <<
686 This option adds work arounds for AR <<
687 and A72 erratum 1319367 <<
688 1149
689 Cortex-A57 and A72 cores could end-u !! 1150 config MIPS_MSC
690 speculating an AT instruction during !! 1151 bool
691 1152
692 If unsure, say Y. !! 1153 config MIPS_NILE4
>> 1154 bool
693 1155
694 config ARM64_ERRATUM_1530923 !! 1156 config SYNC_R4K
695 bool "Cortex-A55: 1530923: Speculative !! 1157 bool
696 default y <<
697 select ARM64_WORKAROUND_SPECULATIVE_AT <<
698 help <<
699 This option adds a workaround for AR <<
700 1158
701 Affected Cortex-A55 cores (r0p0, r0p !! 1159 config MIPS_MACHINE
702 corrupted TLBs by speculating an AT !! 1160 def_bool n
703 context switch. <<
704 1161
705 If unsure, say Y. !! 1162 config NO_IOPORT_MAP
>> 1163 def_bool n
706 1164
707 config ARM64_WORKAROUND_REPEAT_TLBI !! 1165 config GENERIC_CSUM
708 bool 1166 bool
709 1167
710 config ARM64_ERRATUM_2441007 !! 1168 config GENERIC_ISA_DMA
711 bool "Cortex-A55: Completion of affect !! 1169 bool
712 select ARM64_WORKAROUND_REPEAT_TLBI !! 1170 select ZONE_DMA if GENERIC_ISA_DMA_SUPPORT_BROKEN=n
713 help !! 1171 select ISA_DMA_API
714 This option adds a workaround for AR <<
715 <<
716 Under very rare circumstances, affec <<
717 may not handle a race between a brea <<
718 CPU, and another CPU accessing the s <<
719 store to a page that has been unmapp <<
720 1172
721 Work around this by adding the affec !! 1173 config GENERIC_ISA_DMA_SUPPORT_BROKEN
722 TLB sequences to be done twice. !! 1174 bool
>> 1175 select GENERIC_ISA_DMA
723 1176
724 If unsure, say N. !! 1177 config ISA_DMA_API
>> 1178 bool
725 1179
726 config ARM64_ERRATUM_1286807 !! 1180 config HOLES_IN_ZONE
727 bool "Cortex-A76: Modification of the !! 1181 bool
728 select ARM64_WORKAROUND_REPEAT_TLBI <<
729 help <<
730 This option adds a workaround for AR <<
731 <<
732 On the affected Cortex-A76 cores (r0 <<
733 address for a cacheable mapping of a <<
734 accessed by a core while another cor <<
735 address to a new physical page using <<
736 break-before-make sequence, then und <<
737 TLBI+DSB completes before a read usi <<
738 invalidated has been observed by oth <<
739 workaround repeats the TLBI+DSB oper <<
740 1182
741 If unsure, say N. !! 1183 config SYS_SUPPORTS_RELOCATABLE
>> 1184 bool
>> 1185 help
>> 1186 Selected if the platform supports relocating the kernel.
>> 1187 The platform must provide plat_get_fdt() if it selects CONFIG_USE_OF
>> 1188 to allow access to command line and entropy sources.
742 1189
743 config ARM64_ERRATUM_1463225 !! 1190 #
744 bool "Cortex-A76: Software Step might !! 1191 # Endianness selection. Sufficiently obscure so many users don't know what to
745 default y !! 1192 # answer,so we try hard to limit the available choices. Also the use of a
>> 1193 # choice statement should be more obvious to the user.
>> 1194 #
>> 1195 choice
>> 1196 prompt "Endianness selection"
746 help 1197 help
747 This option adds a workaround for Ar !! 1198 Some MIPS machines can be configured for either little or big endian
>> 1199 byte order. These modes require different kernels and a different
>> 1200 Linux distribution. In general there is one preferred byteorder for a
>> 1201 particular system but some systems are just as commonly used in the
>> 1202 one or the other endianness.
748 1203
749 On the affected Cortex-A76 cores (r0 !! 1204 config CPU_BIG_ENDIAN
750 of a system call instruction (SVC) c !! 1205 bool "Big endian"
751 subsequent interrupts when software !! 1206 depends on SYS_SUPPORTS_BIG_ENDIAN
752 exception handler of the system call <<
753 is enabled or VHE is in use. <<
754 1207
755 Work around the erratum by triggerin !! 1208 config CPU_LITTLE_ENDIAN
756 when handling a system call from a t !! 1209 bool "Little endian"
757 in a VHE configuration of the kernel !! 1210 depends on SYS_SUPPORTS_LITTLE_ENDIAN
758 1211
759 If unsure, say Y. !! 1212 endchoice
760 1213
761 config ARM64_ERRATUM_1542419 !! 1214 config EXPORT_UASM
762 bool "Neoverse-N1: workaround mis-orde !! 1215 bool
763 help <<
764 This option adds a workaround for AR <<
765 1542419. <<
766 1216
767 Affected Neoverse-N1 cores could exe !! 1217 config SYS_SUPPORTS_APM_EMULATION
768 modified by another CPU. The workaro !! 1218 bool
769 counterpart. <<
770 1219
771 Workaround the issue by hiding the D !! 1220 config SYS_SUPPORTS_BIG_ENDIAN
772 forces user-space to perform cache m !! 1221 bool
773 1222
774 If unsure, say N. !! 1223 config SYS_SUPPORTS_LITTLE_ENDIAN
>> 1224 bool
775 1225
776 config ARM64_ERRATUM_1508412 !! 1226 config SYS_SUPPORTS_HUGETLBFS
777 bool "Cortex-A77: 1508412: workaround !! 1227 bool
>> 1228 depends on CPU_SUPPORTS_HUGEPAGES && 64BIT
778 default y 1229 default y
779 help <<
780 This option adds a workaround for Ar <<
781 1230
782 Affected Cortex-A77 cores (r0p0, r1p !! 1231 config MIPS_HUGE_TLB_SUPPORT
783 of a store-exclusive or read of PAR_ !! 1232 def_bool HUGETLB_PAGE || TRANSPARENT_HUGEPAGE
784 non-cacheable memory attributes. The <<
785 counterpart. <<
786 1233
787 KVM guests must also have the workar !! 1234 config IRQ_CPU_RM7K
788 deadlock the system. !! 1235 bool
789 1236
790 Work around the issue by inserting D !! 1237 config IRQ_MSP_SLP
791 register reads and warning KVM users !! 1238 bool
792 to prevent a speculative PAR_EL1 rea <<
793 1239
794 If unsure, say Y. !! 1240 config IRQ_MSP_CIC
>> 1241 bool
795 1242
796 config ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MO !! 1243 config IRQ_TXX9
797 bool 1244 bool
798 1245
799 config ARM64_ERRATUM_2051678 !! 1246 config IRQ_GT641XX
800 bool "Cortex-A510: 2051678: disable Ha !! 1247 bool
801 default y <<
802 help <<
803 This options adds the workaround for <<
804 Affected Cortex-A510 might not respe <<
805 hardware update of the page table's <<
806 is to not enable the feature on affe <<
807 1248
808 If unsure, say Y. !! 1249 config PCI_GT64XXX_PCI0
>> 1250 bool
809 1251
810 config ARM64_ERRATUM_2077057 !! 1252 config NO_EXCEPT_FILL
811 bool "Cortex-A510: 2077057: workaround !! 1253 bool
812 default y <<
813 help <<
814 This option adds the workaround for <<
815 Affected Cortex-A510 may corrupt SPS <<
816 expected, but a Pointer Authenticati <<
817 erratum causes SPSR_EL1 to be copied <<
818 EL1 to cause a return to EL2 with a <<
819 1254
820 This can only happen when EL2 is ste !! 1255 config SOC_EMMA2RH
>> 1256 bool
>> 1257 select CEVT_R4K
>> 1258 select CSRC_R4K
>> 1259 select DMA_NONCOHERENT
>> 1260 select IRQ_MIPS_CPU
>> 1261 select SWAP_IO_SPACE
>> 1262 select SYS_HAS_CPU_R5500
>> 1263 select SYS_SUPPORTS_32BIT_KERNEL
>> 1264 select SYS_SUPPORTS_64BIT_KERNEL
>> 1265 select SYS_SUPPORTS_BIG_ENDIAN
821 1266
822 When these conditions occur, the SPS !! 1267 config SOC_PNX833X
823 previous guest entry, and can be res !! 1268 bool
>> 1269 select CEVT_R4K
>> 1270 select CSRC_R4K
>> 1271 select IRQ_MIPS_CPU
>> 1272 select DMA_NONCOHERENT
>> 1273 select SYS_HAS_CPU_MIPS32_R2
>> 1274 select SYS_SUPPORTS_32BIT_KERNEL
>> 1275 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 1276 select SYS_SUPPORTS_BIG_ENDIAN
>> 1277 select SYS_SUPPORTS_MIPS16
>> 1278 select CPU_MIPSR2_IRQ_VI
824 1279
825 If unsure, say Y. !! 1280 config SOC_PNX8335
>> 1281 bool
>> 1282 select SOC_PNX833X
826 1283
827 config ARM64_ERRATUM_2658417 !! 1284 config MIPS_SPRAM
828 bool "Cortex-A510: 2658417: remove BF1 !! 1285 bool
829 default y <<
830 help <<
831 This option adds the workaround for <<
832 Affected Cortex-A510 (r0p0 to r1p1) <<
833 BFMMLA or VMMLA instructions in rare <<
834 A510 CPUs are using shared neon hard <<
835 discoverable by the kernel, hide the <<
836 user-space should not be using these <<
837 1286
838 If unsure, say Y. !! 1287 config SWAP_IO_SPACE
>> 1288 bool
839 1289
840 config ARM64_ERRATUM_2119858 !! 1290 config SGI_HAS_INDYDOG
841 bool "Cortex-A710/X2: 2119858: workaro !! 1291 bool
842 default y <<
843 depends on CORESIGHT_TRBE <<
844 select ARM64_WORKAROUND_TRBE_OVERWRITE <<
845 help <<
846 This option adds the workaround for <<
847 1292
848 Affected Cortex-A710/X2 cores could !! 1293 config SGI_HAS_HAL2
849 data at the base of the buffer (poin !! 1294 bool
850 the event of a WRAP event. <<
851 1295
852 Work around the issue by always maki !! 1296 config SGI_HAS_SEEQ
853 256 bytes before enabling the buffer !! 1297 bool
854 the buffer with ETM ignore packets u <<
855 1298
856 If unsure, say Y. !! 1299 config SGI_HAS_WD93
>> 1300 bool
857 1301
858 config ARM64_ERRATUM_2139208 !! 1302 config SGI_HAS_ZILOG
859 bool "Neoverse-N2: 2139208: workaround !! 1303 bool
860 default y <<
861 depends on CORESIGHT_TRBE <<
862 select ARM64_WORKAROUND_TRBE_OVERWRITE <<
863 help <<
864 This option adds the workaround for <<
865 1304
866 Affected Neoverse-N2 cores could ove !! 1305 config SGI_HAS_I8042
867 data at the base of the buffer (poin !! 1306 bool
868 the event of a WRAP event. <<
869 1307
870 Work around the issue by always maki !! 1308 config DEFAULT_SGI_PARTITION
871 256 bytes before enabling the buffer !! 1309 bool
872 the buffer with ETM ignore packets u <<
873 1310
874 If unsure, say Y. !! 1311 config FW_ARC32
>> 1312 bool
875 1313
876 config ARM64_WORKAROUND_TSB_FLUSH_FAILURE !! 1314 config FW_SNIPROM
877 bool 1315 bool
878 1316
879 config ARM64_ERRATUM_2054223 !! 1317 config BOOT_ELF32
880 bool "Cortex-A710: 2054223: workaround !! 1318 bool
881 default y <<
882 select ARM64_WORKAROUND_TSB_FLUSH_FAIL <<
883 help <<
884 Enable workaround for ARM Cortex-A71 <<
885 1319
886 Affected cores may fail to flush the !! 1320 config MIPS_L1_CACHE_SHIFT_4
887 the PE is in trace prohibited state. !! 1321 bool
888 of the trace cached. <<
889 1322
890 Workaround is to issue two TSB conse !! 1323 config MIPS_L1_CACHE_SHIFT_5
>> 1324 bool
891 1325
892 If unsure, say Y. !! 1326 config MIPS_L1_CACHE_SHIFT_6
>> 1327 bool
893 1328
894 config ARM64_ERRATUM_2067961 !! 1329 config MIPS_L1_CACHE_SHIFT_7
895 bool "Neoverse-N2: 2067961: workaround !! 1330 bool
896 default y <<
897 select ARM64_WORKAROUND_TSB_FLUSH_FAIL <<
898 help <<
899 Enable workaround for ARM Neoverse-N <<
900 1331
901 Affected cores may fail to flush the !! 1332 config MIPS_L1_CACHE_SHIFT
902 the PE is in trace prohibited state. !! 1333 int
903 of the trace cached. !! 1334 default "7" if MIPS_L1_CACHE_SHIFT_7
>> 1335 default "6" if MIPS_L1_CACHE_SHIFT_6
>> 1336 default "5" if MIPS_L1_CACHE_SHIFT_5
>> 1337 default "4" if MIPS_L1_CACHE_SHIFT_4
>> 1338 default "5"
904 1339
905 Workaround is to issue two TSB conse !! 1340 config HAVE_STD_PC_SERIAL_PORT
>> 1341 bool
906 1342
907 If unsure, say Y. !! 1343 config ARC_CONSOLE
>> 1344 bool "ARC console support"
>> 1345 depends on SGI_IP22 || SGI_IP28 || (SNI_RM && CPU_LITTLE_ENDIAN)
908 1346
909 config ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANG !! 1347 config ARC_MEMORY
910 bool 1348 bool
911 !! 1349 depends on MACH_JAZZ || SNI_RM || SGI_IP32
912 config ARM64_ERRATUM_2253138 <<
913 bool "Neoverse-N2: 2253138: workaround <<
914 depends on CORESIGHT_TRBE <<
915 default y 1350 default y
916 select ARM64_WORKAROUND_TRBE_WRITE_OUT <<
917 help <<
918 This option adds the workaround for <<
919 <<
920 Affected Neoverse-N2 cores might wri <<
921 for TRBE. Under some conditions, the <<
922 virtually addressed page following t <<
923 (i.e., the TRBLIMITR_EL1.LIMIT), ins <<
924 <<
925 Work around this in the driver by al <<
926 page beyond the TRBLIMITR_EL1.LIMIT, <<
927 <<
928 If unsure, say Y. <<
929 1351
930 config ARM64_ERRATUM_2224489 !! 1352 config ARC_PROMLIB
931 bool "Cortex-A710/X2: 2224489: workaro !! 1353 bool
932 depends on CORESIGHT_TRBE !! 1354 depends on MACH_JAZZ || SNI_RM || SGI_IP22 || SGI_IP28 || SGI_IP32
933 default y 1355 default y
934 select ARM64_WORKAROUND_TRBE_WRITE_OUT <<
935 help <<
936 This option adds the workaround for <<
937 <<
938 Affected Cortex-A710/X2 cores might <<
939 for TRBE. Under some conditions, the <<
940 virtually addressed page following t <<
941 (i.e., the TRBLIMITR_EL1.LIMIT), ins <<
942 1356
943 Work around this in the driver by al !! 1357 config FW_ARC64
944 page beyond the TRBLIMITR_EL1.LIMIT, !! 1358 bool
945 <<
946 If unsure, say Y. <<
947 1359
948 config ARM64_ERRATUM_2441009 !! 1360 config BOOT_ELF64
949 bool "Cortex-A510: Completion of affec !! 1361 bool
950 select ARM64_WORKAROUND_REPEAT_TLBI <<
951 help <<
952 This option adds a workaround for AR <<
953 <<
954 Under very rare circumstances, affec <<
955 may not handle a race between a brea <<
956 CPU, and another CPU accessing the s <<
957 store to a page that has been unmapp <<
958 1362
959 Work around this by adding the affec !! 1363 menu "CPU selection"
960 TLB sequences to be done twice. <<
961 1364
962 If unsure, say N. !! 1365 choice
>> 1366 prompt "CPU type"
>> 1367 default CPU_R4X00
963 1368
964 config ARM64_ERRATUM_2064142 !! 1369 config CPU_LOONGSON3
965 bool "Cortex-A510: 2064142: workaround !! 1370 bool "Loongson 3 CPU"
966 depends on CORESIGHT_TRBE !! 1371 depends on SYS_HAS_CPU_LOONGSON3
967 default y !! 1372 select CPU_SUPPORTS_64BIT_KERNEL
>> 1373 select CPU_SUPPORTS_HIGHMEM
>> 1374 select CPU_SUPPORTS_HUGEPAGES
>> 1375 select WEAK_ORDERING
>> 1376 select WEAK_REORDERING_BEYOND_LLSC
>> 1377 select MIPS_PGD_C0_CONTEXT
>> 1378 select MIPS_L1_CACHE_SHIFT_6
>> 1379 select MIPS_FP_SUPPORT
>> 1380 select GPIOLIB
968 help 1381 help
969 This option adds the workaround for !! 1382 The Loongson 3 processor implements the MIPS64R2 instruction
970 !! 1383 set with many extensions.
971 Affected Cortex-A510 core might fail <<
972 TRBE has been disabled. Under some c <<
973 writes into TRBE registers TRBLIMITR <<
974 and TRBTRG_EL1 will be ignored and w <<
975 1384
976 Work around this in the driver by ex !! 1385 config LOONGSON3_ENHANCEMENT
977 is stopped and before performing a s !! 1386 bool "New Loongson 3 CPU Enhancements"
978 registers. !! 1387 default n
>> 1388 select CPU_MIPSR2
>> 1389 select CPU_HAS_PREFETCH
>> 1390 depends on CPU_LOONGSON3
>> 1391 help
>> 1392 New Loongson 3 CPU (since Loongson-3A R2, as opposed to Loongson-3A
>> 1393 R1, Loongson-3B R1 and Loongson-3B R2) has many enhancements, such as
>> 1394 FTLB, L1-VCache, EI/DI/Wait/Prefetch instruction, DSP/DSPv2 ASE, User
>> 1395 Local register, Read-Inhibit/Execute-Inhibit, SFB (Store Fill Buffer),
>> 1396 Fast TLB refill support, etc.
>> 1397
>> 1398 This option enable those enhancements which are not probed at run
>> 1399 time. If you want a generic kernel to run on all Loongson 3 machines,
>> 1400 please say 'N' here. If you want a high-performance kernel to run on
>> 1401 new Loongson 3 machines only, please say 'Y' here.
>> 1402
>> 1403 config CPU_LOONGSON2E
>> 1404 bool "Loongson 2E"
>> 1405 depends on SYS_HAS_CPU_LOONGSON2E
>> 1406 select CPU_LOONGSON2
>> 1407 help
>> 1408 The Loongson 2E processor implements the MIPS III instruction set
>> 1409 with many extensions.
>> 1410
>> 1411 It has an internal FPGA northbridge, which is compatible to
>> 1412 bonito64.
>> 1413
>> 1414 config CPU_LOONGSON2F
>> 1415 bool "Loongson 2F"
>> 1416 depends on SYS_HAS_CPU_LOONGSON2F
>> 1417 select CPU_LOONGSON2
>> 1418 select GPIOLIB
>> 1419 help
>> 1420 The Loongson 2F processor implements the MIPS III instruction set
>> 1421 with many extensions.
>> 1422
>> 1423 Loongson2F have built-in DDR2 and PCIX controller. The PCIX controller
>> 1424 have a similar programming interface with FPGA northbridge used in
>> 1425 Loongson2E.
>> 1426
>> 1427 config CPU_LOONGSON1B
>> 1428 bool "Loongson 1B"
>> 1429 depends on SYS_HAS_CPU_LOONGSON1B
>> 1430 select CPU_LOONGSON1
>> 1431 select LEDS_GPIO_REGISTER
>> 1432 help
>> 1433 The Loongson 1B is a 32-bit SoC, which implements the MIPS32
>> 1434 release 2 instruction set.
>> 1435
>> 1436 config CPU_LOONGSON1C
>> 1437 bool "Loongson 1C"
>> 1438 depends on SYS_HAS_CPU_LOONGSON1C
>> 1439 select CPU_LOONGSON1
>> 1440 select ARCH_WANT_OPTIONAL_GPIOLIB
>> 1441 select LEDS_GPIO_REGISTER
>> 1442 help
>> 1443 The Loongson 1C is a 32-bit SoC, which implements the MIPS32
>> 1444 release 2 instruction set.
>> 1445
>> 1446 config CPU_MIPS32_R1
>> 1447 bool "MIPS32 Release 1"
>> 1448 depends on SYS_HAS_CPU_MIPS32_R1
>> 1449 select CPU_HAS_PREFETCH
>> 1450 select CPU_SUPPORTS_32BIT_KERNEL
>> 1451 select CPU_SUPPORTS_HIGHMEM
>> 1452 help
>> 1453 Choose this option to build a kernel for release 1 or later of the
>> 1454 MIPS32 architecture. Most modern embedded systems with a 32-bit
>> 1455 MIPS processor are based on a MIPS32 processor. If you know the
>> 1456 specific type of processor in your system, choose those that one
>> 1457 otherwise CPU_MIPS32_R1 is a safe bet for any MIPS32 system.
>> 1458 Release 2 of the MIPS32 architecture is available since several
>> 1459 years so chances are you even have a MIPS32 Release 2 processor
>> 1460 in which case you should choose CPU_MIPS32_R2 instead for better
>> 1461 performance.
>> 1462
>> 1463 config CPU_MIPS32_R2
>> 1464 bool "MIPS32 Release 2"
>> 1465 depends on SYS_HAS_CPU_MIPS32_R2
>> 1466 select CPU_HAS_PREFETCH
>> 1467 select CPU_SUPPORTS_32BIT_KERNEL
>> 1468 select CPU_SUPPORTS_HIGHMEM
>> 1469 select CPU_SUPPORTS_MSA
>> 1470 select HAVE_KVM
>> 1471 help
>> 1472 Choose this option to build a kernel for release 2 or later of the
>> 1473 MIPS32 architecture. Most modern embedded systems with a 32-bit
>> 1474 MIPS processor are based on a MIPS32 processor. If you know the
>> 1475 specific type of processor in your system, choose those that one
>> 1476 otherwise CPU_MIPS32_R1 is a safe bet for any MIPS32 system.
>> 1477
>> 1478 config CPU_MIPS32_R6
>> 1479 bool "MIPS32 Release 6"
>> 1480 depends on SYS_HAS_CPU_MIPS32_R6
>> 1481 select CPU_HAS_PREFETCH
>> 1482 select CPU_SUPPORTS_32BIT_KERNEL
>> 1483 select CPU_SUPPORTS_HIGHMEM
>> 1484 select CPU_SUPPORTS_MSA
>> 1485 select GENERIC_CSUM
>> 1486 select HAVE_KVM
>> 1487 select MIPS_O32_FP64_SUPPORT
>> 1488 help
>> 1489 Choose this option to build a kernel for release 6 or later of the
>> 1490 MIPS32 architecture. New MIPS processors, starting with the Warrior
>> 1491 family, are based on a MIPS32r6 processor. If you own an older
>> 1492 processor, you probably need to select MIPS32r1 or MIPS32r2 instead.
>> 1493
>> 1494 config CPU_MIPS64_R1
>> 1495 bool "MIPS64 Release 1"
>> 1496 depends on SYS_HAS_CPU_MIPS64_R1
>> 1497 select CPU_HAS_PREFETCH
>> 1498 select CPU_SUPPORTS_32BIT_KERNEL
>> 1499 select CPU_SUPPORTS_64BIT_KERNEL
>> 1500 select CPU_SUPPORTS_HIGHMEM
>> 1501 select CPU_SUPPORTS_HUGEPAGES
>> 1502 help
>> 1503 Choose this option to build a kernel for release 1 or later of the
>> 1504 MIPS64 architecture. Many modern embedded systems with a 64-bit
>> 1505 MIPS processor are based on a MIPS64 processor. If you know the
>> 1506 specific type of processor in your system, choose those that one
>> 1507 otherwise CPU_MIPS64_R1 is a safe bet for any MIPS64 system.
>> 1508 Release 2 of the MIPS64 architecture is available since several
>> 1509 years so chances are you even have a MIPS64 Release 2 processor
>> 1510 in which case you should choose CPU_MIPS64_R2 instead for better
>> 1511 performance.
>> 1512
>> 1513 config CPU_MIPS64_R2
>> 1514 bool "MIPS64 Release 2"
>> 1515 depends on SYS_HAS_CPU_MIPS64_R2
>> 1516 select CPU_HAS_PREFETCH
>> 1517 select CPU_SUPPORTS_32BIT_KERNEL
>> 1518 select CPU_SUPPORTS_64BIT_KERNEL
>> 1519 select CPU_SUPPORTS_HIGHMEM
>> 1520 select CPU_SUPPORTS_HUGEPAGES
>> 1521 select CPU_SUPPORTS_MSA
>> 1522 select HAVE_KVM
>> 1523 help
>> 1524 Choose this option to build a kernel for release 2 or later of the
>> 1525 MIPS64 architecture. Many modern embedded systems with a 64-bit
>> 1526 MIPS processor are based on a MIPS64 processor. If you know the
>> 1527 specific type of processor in your system, choose those that one
>> 1528 otherwise CPU_MIPS64_R1 is a safe bet for any MIPS64 system.
>> 1529
>> 1530 config CPU_MIPS64_R6
>> 1531 bool "MIPS64 Release 6"
>> 1532 depends on SYS_HAS_CPU_MIPS64_R6
>> 1533 select CPU_HAS_PREFETCH
>> 1534 select CPU_SUPPORTS_32BIT_KERNEL
>> 1535 select CPU_SUPPORTS_64BIT_KERNEL
>> 1536 select CPU_SUPPORTS_HIGHMEM
>> 1537 select CPU_SUPPORTS_MSA
>> 1538 select GENERIC_CSUM
>> 1539 select MIPS_O32_FP64_SUPPORT if 32BIT || MIPS32_O32
>> 1540 select HAVE_KVM
>> 1541 help
>> 1542 Choose this option to build a kernel for release 6 or later of the
>> 1543 MIPS64 architecture. New MIPS processors, starting with the Warrior
>> 1544 family, are based on a MIPS64r6 processor. If you own an older
>> 1545 processor, you probably need to select MIPS64r1 or MIPS64r2 instead.
>> 1546
>> 1547 config CPU_R3000
>> 1548 bool "R3000"
>> 1549 depends on SYS_HAS_CPU_R3000
>> 1550 select CPU_HAS_WB
>> 1551 select CPU_SUPPORTS_32BIT_KERNEL
>> 1552 select CPU_SUPPORTS_HIGHMEM
>> 1553 help
>> 1554 Please make sure to pick the right CPU type. Linux/MIPS is not
>> 1555 designed to be generic, i.e. Kernels compiled for R3000 CPUs will
>> 1556 *not* work on R4000 machines and vice versa. However, since most
>> 1557 of the supported machines have an R4000 (or similar) CPU, R4x00
>> 1558 might be a safe bet. If the resulting kernel does not work,
>> 1559 try to recompile with R3000.
>> 1560
>> 1561 config CPU_TX39XX
>> 1562 bool "R39XX"
>> 1563 depends on SYS_HAS_CPU_TX39XX
>> 1564 select CPU_SUPPORTS_32BIT_KERNEL
>> 1565
>> 1566 config CPU_VR41XX
>> 1567 bool "R41xx"
>> 1568 depends on SYS_HAS_CPU_VR41XX
>> 1569 select CPU_SUPPORTS_32BIT_KERNEL
>> 1570 select CPU_SUPPORTS_64BIT_KERNEL
>> 1571 help
>> 1572 The options selects support for the NEC VR4100 series of processors.
>> 1573 Only choose this option if you have one of these processors as a
>> 1574 kernel built with this option will not run on any other type of
>> 1575 processor or vice versa.
>> 1576
>> 1577 config CPU_R4300
>> 1578 bool "R4300"
>> 1579 depends on SYS_HAS_CPU_R4300
>> 1580 select CPU_SUPPORTS_32BIT_KERNEL
>> 1581 select CPU_SUPPORTS_64BIT_KERNEL
>> 1582 help
>> 1583 MIPS Technologies R4300-series processors.
>> 1584
>> 1585 config CPU_R4X00
>> 1586 bool "R4x00"
>> 1587 depends on SYS_HAS_CPU_R4X00
>> 1588 select CPU_SUPPORTS_32BIT_KERNEL
>> 1589 select CPU_SUPPORTS_64BIT_KERNEL
>> 1590 select CPU_SUPPORTS_HUGEPAGES
>> 1591 help
>> 1592 MIPS Technologies R4000-series processors other than 4300, including
>> 1593 the R4000, R4400, R4600, and 4700.
>> 1594
>> 1595 config CPU_TX49XX
>> 1596 bool "R49XX"
>> 1597 depends on SYS_HAS_CPU_TX49XX
>> 1598 select CPU_HAS_PREFETCH
>> 1599 select CPU_SUPPORTS_32BIT_KERNEL
>> 1600 select CPU_SUPPORTS_64BIT_KERNEL
>> 1601 select CPU_SUPPORTS_HUGEPAGES
>> 1602
>> 1603 config CPU_R5000
>> 1604 bool "R5000"
>> 1605 depends on SYS_HAS_CPU_R5000
>> 1606 select CPU_SUPPORTS_32BIT_KERNEL
>> 1607 select CPU_SUPPORTS_64BIT_KERNEL
>> 1608 select CPU_SUPPORTS_HUGEPAGES
>> 1609 help
>> 1610 MIPS Technologies R5000-series processors other than the Nevada.
>> 1611
>> 1612 config CPU_R5432
>> 1613 bool "R5432"
>> 1614 depends on SYS_HAS_CPU_R5432
>> 1615 select CPU_SUPPORTS_32BIT_KERNEL
>> 1616 select CPU_SUPPORTS_64BIT_KERNEL
>> 1617 select CPU_SUPPORTS_HUGEPAGES
>> 1618
>> 1619 config CPU_R5500
>> 1620 bool "R5500"
>> 1621 depends on SYS_HAS_CPU_R5500
>> 1622 select CPU_SUPPORTS_32BIT_KERNEL
>> 1623 select CPU_SUPPORTS_64BIT_KERNEL
>> 1624 select CPU_SUPPORTS_HUGEPAGES
>> 1625 help
>> 1626 NEC VR5500 and VR5500A series processors implement 64-bit MIPS IV
>> 1627 instruction set.
>> 1628
>> 1629 config CPU_R6000
>> 1630 bool "R6000"
>> 1631 depends on SYS_HAS_CPU_R6000
>> 1632 select CPU_SUPPORTS_32BIT_KERNEL
>> 1633 help
>> 1634 MIPS Technologies R6000 and R6000A series processors. Note these
>> 1635 processors are extremely rare and the support for them is incomplete.
>> 1636
>> 1637 config CPU_NEVADA
>> 1638 bool "RM52xx"
>> 1639 depends on SYS_HAS_CPU_NEVADA
>> 1640 select CPU_SUPPORTS_32BIT_KERNEL
>> 1641 select CPU_SUPPORTS_64BIT_KERNEL
>> 1642 select CPU_SUPPORTS_HUGEPAGES
>> 1643 help
>> 1644 QED / PMC-Sierra RM52xx-series ("Nevada") processors.
>> 1645
>> 1646 config CPU_R8000
>> 1647 bool "R8000"
>> 1648 depends on SYS_HAS_CPU_R8000
>> 1649 select CPU_HAS_PREFETCH
>> 1650 select CPU_SUPPORTS_64BIT_KERNEL
>> 1651 help
>> 1652 MIPS Technologies R8000 processors. Note these processors are
>> 1653 uncommon and the support for them is incomplete.
>> 1654
>> 1655 config CPU_R10000
>> 1656 bool "R10000"
>> 1657 depends on SYS_HAS_CPU_R10000
>> 1658 select CPU_HAS_PREFETCH
>> 1659 select CPU_SUPPORTS_32BIT_KERNEL
>> 1660 select CPU_SUPPORTS_64BIT_KERNEL
>> 1661 select CPU_SUPPORTS_HIGHMEM
>> 1662 select CPU_SUPPORTS_HUGEPAGES
>> 1663 help
>> 1664 MIPS Technologies R10000-series processors.
>> 1665
>> 1666 config CPU_RM7000
>> 1667 bool "RM7000"
>> 1668 depends on SYS_HAS_CPU_RM7000
>> 1669 select CPU_HAS_PREFETCH
>> 1670 select CPU_SUPPORTS_32BIT_KERNEL
>> 1671 select CPU_SUPPORTS_64BIT_KERNEL
>> 1672 select CPU_SUPPORTS_HIGHMEM
>> 1673 select CPU_SUPPORTS_HUGEPAGES
>> 1674
>> 1675 config CPU_SB1
>> 1676 bool "SB1"
>> 1677 depends on SYS_HAS_CPU_SB1
>> 1678 select CPU_SUPPORTS_32BIT_KERNEL
>> 1679 select CPU_SUPPORTS_64BIT_KERNEL
>> 1680 select CPU_SUPPORTS_HIGHMEM
>> 1681 select CPU_SUPPORTS_HUGEPAGES
>> 1682 select WEAK_ORDERING
>> 1683
>> 1684 config CPU_CAVIUM_OCTEON
>> 1685 bool "Cavium Octeon processor"
>> 1686 depends on SYS_HAS_CPU_CAVIUM_OCTEON
>> 1687 select CPU_HAS_PREFETCH
>> 1688 select CPU_SUPPORTS_64BIT_KERNEL
>> 1689 select WEAK_ORDERING
>> 1690 select CPU_SUPPORTS_HIGHMEM
>> 1691 select CPU_SUPPORTS_HUGEPAGES
>> 1692 select USB_EHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 1693 select USB_OHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 1694 select MIPS_L1_CACHE_SHIFT_7
>> 1695 help
>> 1696 The Cavium Octeon processor is a highly integrated chip containing
>> 1697 many ethernet hardware widgets for networking tasks. The processor
>> 1698 can have up to 16 Mips64v2 cores and 8 integrated gigabit ethernets.
>> 1699 Full details can be found at http://www.caviumnetworks.com.
>> 1700
>> 1701 config CPU_BMIPS
>> 1702 bool "Broadcom BMIPS"
>> 1703 depends on SYS_HAS_CPU_BMIPS
>> 1704 select CPU_MIPS32
>> 1705 select CPU_BMIPS32_3300 if SYS_HAS_CPU_BMIPS32_3300
>> 1706 select CPU_BMIPS4350 if SYS_HAS_CPU_BMIPS4350
>> 1707 select CPU_BMIPS4380 if SYS_HAS_CPU_BMIPS4380
>> 1708 select CPU_BMIPS5000 if SYS_HAS_CPU_BMIPS5000
>> 1709 select CPU_SUPPORTS_32BIT_KERNEL
>> 1710 select DMA_NONCOHERENT
>> 1711 select IRQ_MIPS_CPU
>> 1712 select SWAP_IO_SPACE
>> 1713 select WEAK_ORDERING
>> 1714 select CPU_SUPPORTS_HIGHMEM
>> 1715 select CPU_HAS_PREFETCH
>> 1716 help
>> 1717 Support for BMIPS32/3300/4350/4380 and BMIPS5000 processors.
>> 1718
>> 1719 config CPU_XLR
>> 1720 bool "Netlogic XLR SoC"
>> 1721 depends on SYS_HAS_CPU_XLR
>> 1722 select CPU_SUPPORTS_32BIT_KERNEL
>> 1723 select CPU_SUPPORTS_64BIT_KERNEL
>> 1724 select CPU_SUPPORTS_HIGHMEM
>> 1725 select CPU_SUPPORTS_HUGEPAGES
>> 1726 select WEAK_ORDERING
>> 1727 select WEAK_REORDERING_BEYOND_LLSC
>> 1728 help
>> 1729 Netlogic Microsystems XLR/XLS processors.
>> 1730
>> 1731 config CPU_XLP
>> 1732 bool "Netlogic XLP SoC"
>> 1733 depends on SYS_HAS_CPU_XLP
>> 1734 select CPU_SUPPORTS_32BIT_KERNEL
>> 1735 select CPU_SUPPORTS_64BIT_KERNEL
>> 1736 select CPU_SUPPORTS_HIGHMEM
>> 1737 select WEAK_ORDERING
>> 1738 select WEAK_REORDERING_BEYOND_LLSC
>> 1739 select CPU_HAS_PREFETCH
>> 1740 select CPU_MIPSR2
>> 1741 select CPU_SUPPORTS_HUGEPAGES
>> 1742 select MIPS_ASID_BITS_VARIABLE
>> 1743 help
>> 1744 Netlogic Microsystems XLP processors.
>> 1745 endchoice
979 1746
980 If unsure, say Y. !! 1747 config CPU_MIPS32_3_5_FEATURES
>> 1748 bool "MIPS32 Release 3.5 Features"
>> 1749 depends on SYS_HAS_CPU_MIPS32_R3_5
>> 1750 depends on CPU_MIPS32_R2 || CPU_MIPS32_R6
>> 1751 help
>> 1752 Choose this option to build a kernel for release 2 or later of the
>> 1753 MIPS32 architecture including features from the 3.5 release such as
>> 1754 support for Enhanced Virtual Addressing (EVA).
>> 1755
>> 1756 config CPU_MIPS32_3_5_EVA
>> 1757 bool "Enhanced Virtual Addressing (EVA)"
>> 1758 depends on CPU_MIPS32_3_5_FEATURES
>> 1759 select EVA
>> 1760 default y
>> 1761 help
>> 1762 Choose this option if you want to enable the Enhanced Virtual
>> 1763 Addressing (EVA) on your MIPS32 core (such as proAptiv).
>> 1764 One of its primary benefits is an increase in the maximum size
>> 1765 of lowmem (up to 3GB). If unsure, say 'N' here.
>> 1766
>> 1767 config CPU_MIPS32_R5_FEATURES
>> 1768 bool "MIPS32 Release 5 Features"
>> 1769 depends on SYS_HAS_CPU_MIPS32_R5
>> 1770 depends on CPU_MIPS32_R2
>> 1771 help
>> 1772 Choose this option to build a kernel for release 2 or later of the
>> 1773 MIPS32 architecture including features from release 5 such as
>> 1774 support for Extended Physical Addressing (XPA).
>> 1775
>> 1776 config CPU_MIPS32_R5_XPA
>> 1777 bool "Extended Physical Addressing (XPA)"
>> 1778 depends on CPU_MIPS32_R5_FEATURES
>> 1779 depends on !EVA
>> 1780 depends on !PAGE_SIZE_4KB
>> 1781 depends on SYS_SUPPORTS_HIGHMEM
>> 1782 select XPA
>> 1783 select HIGHMEM
>> 1784 select ARCH_PHYS_ADDR_T_64BIT
>> 1785 default n
>> 1786 help
>> 1787 Choose this option if you want to enable the Extended Physical
>> 1788 Addressing (XPA) on your MIPS32 core (such as P5600 series). The
>> 1789 benefit is to increase physical addressing equal to or greater
>> 1790 than 40 bits. Note that this has the side effect of turning on
>> 1791 64-bit addressing which in turn makes the PTEs 64-bit in size.
>> 1792 If unsure, say 'N' here.
981 1793
982 config ARM64_ERRATUM_2038923 !! 1794 if CPU_LOONGSON2F
983 bool "Cortex-A510: 2038923: workaround !! 1795 config CPU_NOP_WORKAROUNDS
984 depends on CORESIGHT_TRBE !! 1796 bool
985 default y <<
986 help <<
987 This option adds the workaround for <<
988 <<
989 Affected Cortex-A510 core might caus <<
990 prohibited within the CPU. As a resu <<
991 might be corrupted. This happens aft <<
992 TRBLIMITR_EL1.E, followed by just a <<
993 execution changes from a context, in <<
994 isn't, or vice versa. In these menti <<
995 is prohibited is inconsistent betwee <<
996 the trace buffer state might be corr <<
997 <<
998 Work around this in the driver by pr <<
999 trace is prohibited or not based on <<
1000 change to TRBLIMITR_EL1.E with at l <<
1001 two ISB instructions if no ERET is <<
1002 1797
1003 If unsure, say Y. !! 1798 config CPU_JUMP_WORKAROUNDS
>> 1799 bool
1004 1800
1005 config ARM64_ERRATUM_1902691 !! 1801 config CPU_LOONGSON2F_WORKAROUNDS
1006 bool "Cortex-A510: 1902691: workaroun !! 1802 bool "Loongson 2F Workarounds"
1007 depends on CORESIGHT_TRBE <<
1008 default y 1803 default y
>> 1804 select CPU_NOP_WORKAROUNDS
>> 1805 select CPU_JUMP_WORKAROUNDS
1009 help 1806 help
1010 This option adds the workaround for !! 1807 Loongson 2F01 / 2F02 processors have the NOP & JUMP issues which
>> 1808 require workarounds. Without workarounds the system may hang
>> 1809 unexpectedly. For more information please refer to the gas
>> 1810 -mfix-loongson2f-nop and -mfix-loongson2f-jump options.
>> 1811
>> 1812 Loongson 2F03 and later have fixed these issues and no workarounds
>> 1813 are needed. The workarounds have no significant side effect on them
>> 1814 but may decrease the performance of the system so this option should
>> 1815 be disabled unless the kernel is intended to be run on 2F01 or 2F02
>> 1816 systems.
1011 1817
1012 Affected Cortex-A510 core might cau !! 1818 If unsure, please say Y.
1013 into the memory. Effectively TRBE i !! 1819 endif # CPU_LOONGSON2F
1014 trace data. <<
1015 1820
1016 Work around this problem in the dri !! 1821 config SYS_SUPPORTS_ZBOOT
1017 affected cpus. The firmware must ha !! 1822 bool
1018 on such implementations. This will !! 1823 select HAVE_KERNEL_GZIP
1019 do this already. !! 1824 select HAVE_KERNEL_BZIP2
>> 1825 select HAVE_KERNEL_LZ4
>> 1826 select HAVE_KERNEL_LZMA
>> 1827 select HAVE_KERNEL_LZO
>> 1828 select HAVE_KERNEL_XZ
1020 1829
1021 If unsure, say Y. !! 1830 config SYS_SUPPORTS_ZBOOT_UART16550
>> 1831 bool
>> 1832 select SYS_SUPPORTS_ZBOOT
1022 1833
1023 config ARM64_ERRATUM_2457168 !! 1834 config SYS_SUPPORTS_ZBOOT_UART_PROM
1024 bool "Cortex-A510: 2457168: workaroun !! 1835 bool
1025 depends on ARM64_AMU_EXTN !! 1836 select SYS_SUPPORTS_ZBOOT
1026 default y <<
1027 help <<
1028 This option adds the workaround for <<
1029 1837
1030 The AMU counter AMEVCNTR01 (constan !! 1838 config CPU_LOONGSON2
1031 as the system counter. On affected !! 1839 bool
1032 incorrectly giving a significantly !! 1840 select CPU_SUPPORTS_32BIT_KERNEL
>> 1841 select CPU_SUPPORTS_64BIT_KERNEL
>> 1842 select CPU_SUPPORTS_HIGHMEM
>> 1843 select CPU_SUPPORTS_HUGEPAGES
1033 1844
1034 Work around this problem by returni !! 1845 config CPU_LOONGSON1
1035 key locations that results in disab !! 1846 bool
1036 is the same to firmware disabling a !! 1847 select CPU_MIPS32
>> 1848 select CPU_MIPSR2
>> 1849 select CPU_HAS_PREFETCH
>> 1850 select CPU_SUPPORTS_32BIT_KERNEL
>> 1851 select CPU_SUPPORTS_HIGHMEM
>> 1852 select CPU_SUPPORTS_CPUFREQ
1037 1853
1038 If unsure, say Y. !! 1854 config CPU_BMIPS32_3300
>> 1855 select SMP_UP if SMP
>> 1856 bool
1039 1857
1040 config ARM64_ERRATUM_2645198 !! 1858 config CPU_BMIPS4350
1041 bool "Cortex-A715: 2645198: Workaroun !! 1859 bool
1042 default y !! 1860 select SYS_SUPPORTS_SMP
1043 help !! 1861 select SYS_SUPPORTS_HOTPLUG_CPU
1044 This option adds the workaround for <<
1045 1862
1046 If a Cortex-A715 cpu sees a page ma !! 1863 config CPU_BMIPS4380
1047 to non-executable, it may corrupt t !! 1864 bool
1048 next instruction abort caused by pe !! 1865 select MIPS_L1_CACHE_SHIFT_6
>> 1866 select SYS_SUPPORTS_SMP
>> 1867 select SYS_SUPPORTS_HOTPLUG_CPU
>> 1868 select CPU_HAS_RIXI
1049 1869
1050 Only user-space does executable to !! 1870 config CPU_BMIPS5000
1051 mprotect() system call. Workaround !! 1871 bool
1052 TLB invalidation, for all changes t !! 1872 select MIPS_CPU_SCACHE
>> 1873 select MIPS_L1_CACHE_SHIFT_7
>> 1874 select SYS_SUPPORTS_SMP
>> 1875 select SYS_SUPPORTS_HOTPLUG_CPU
>> 1876 select CPU_HAS_RIXI
1053 1877
1054 If unsure, say Y. !! 1878 config SYS_HAS_CPU_LOONGSON3
>> 1879 bool
>> 1880 select CPU_SUPPORTS_CPUFREQ
>> 1881 select CPU_HAS_RIXI
1055 1882
1056 config ARM64_WORKAROUND_SPECULATIVE_UNPRIV_LO !! 1883 config SYS_HAS_CPU_LOONGSON2E
1057 bool 1884 bool
1058 1885
1059 config ARM64_ERRATUM_2966298 !! 1886 config SYS_HAS_CPU_LOONGSON2F
1060 bool "Cortex-A520: 2966298: workaroun !! 1887 bool
1061 select ARM64_WORKAROUND_SPECULATIVE_U !! 1888 select CPU_SUPPORTS_CPUFREQ
1062 default y !! 1889 select CPU_SUPPORTS_ADDRWINCFG if 64BIT
1063 help !! 1890 select CPU_SUPPORTS_UNCACHED_ACCELERATED
1064 This option adds the workaround for <<
1065 1891
1066 On an affected Cortex-A520 core, a !! 1892 config SYS_HAS_CPU_LOONGSON1B
1067 load might leak data from a privile !! 1893 bool
1068 1894
1069 Work around this problem by executi !! 1895 config SYS_HAS_CPU_LOONGSON1C
>> 1896 bool
1070 1897
1071 If unsure, say Y. !! 1898 config SYS_HAS_CPU_MIPS32_R1
>> 1899 bool
1072 1900
1073 config ARM64_ERRATUM_3117295 !! 1901 config SYS_HAS_CPU_MIPS32_R2
1074 bool "Cortex-A510: 3117295: workaroun !! 1902 bool
1075 select ARM64_WORKAROUND_SPECULATIVE_U <<
1076 default y <<
1077 help <<
1078 This option adds the workaround for <<
1079 1903
1080 On an affected Cortex-A510 core, a !! 1904 config SYS_HAS_CPU_MIPS32_R3_5
1081 load might leak data from a privile !! 1905 bool
1082 1906
1083 Work around this problem by executi !! 1907 config SYS_HAS_CPU_MIPS32_R5
>> 1908 bool
1084 1909
1085 If unsure, say Y. !! 1910 config SYS_HAS_CPU_MIPS32_R6
>> 1911 bool
1086 1912
1087 config ARM64_ERRATUM_3194386 !! 1913 config SYS_HAS_CPU_MIPS64_R1
1088 bool "Cortex-*/Neoverse-*: workaround !! 1914 bool
1089 default y <<
1090 help <<
1091 This option adds the workaround for <<
1092 1915
1093 * ARM Cortex-A76 erratum 3324349 !! 1916 config SYS_HAS_CPU_MIPS64_R2
1094 * ARM Cortex-A77 erratum 3324348 !! 1917 bool
1095 * ARM Cortex-A78 erratum 3324344 <<
1096 * ARM Cortex-A78C erratum 3324346 <<
1097 * ARM Cortex-A78C erratum 3324347 <<
1098 * ARM Cortex-A710 erratam 3324338 <<
1099 * ARM Cortex-A715 errartum 3456084 <<
1100 * ARM Cortex-A720 erratum 3456091 <<
1101 * ARM Cortex-A725 erratum 3456106 <<
1102 * ARM Cortex-X1 erratum 3324344 <<
1103 * ARM Cortex-X1C erratum 3324346 <<
1104 * ARM Cortex-X2 erratum 3324338 <<
1105 * ARM Cortex-X3 erratum 3324335 <<
1106 * ARM Cortex-X4 erratum 3194386 <<
1107 * ARM Cortex-X925 erratum 3324334 <<
1108 * ARM Neoverse-N1 erratum 3324349 <<
1109 * ARM Neoverse N2 erratum 3324339 <<
1110 * ARM Neoverse-N3 erratum 3456111 <<
1111 * ARM Neoverse-V1 erratum 3324341 <<
1112 * ARM Neoverse V2 erratum 3324336 <<
1113 * ARM Neoverse-V3 erratum 3312417 <<
1114 <<
1115 On affected cores "MSR SSBS, #0" in <<
1116 subsequent speculative instructions <<
1117 speculative store bypassing. <<
1118 <<
1119 Work around this problem by placing <<
1120 Instruction Synchronization Barrier <<
1121 SSBS. The presence of the SSBS spec <<
1122 from hwcaps and EL0 reads of ID_AA6 <<
1123 will use the PR_SPEC_STORE_BYPASS p <<
1124 1918
1125 If unsure, say Y. !! 1919 config SYS_HAS_CPU_MIPS64_R6
>> 1920 bool
1126 1921
1127 config CAVIUM_ERRATUM_22375 !! 1922 config SYS_HAS_CPU_R3000
1128 bool "Cavium erratum 22375, 24313" !! 1923 bool
1129 default y <<
1130 help <<
1131 Enable workaround for errata 22375 <<
1132 1924
1133 This implements two gicv3-its errat !! 1925 config SYS_HAS_CPU_TX39XX
1134 with a small impact affecting only !! 1926 bool
1135 1927
1136 erratum 22375: only alloc 8MB tab !! 1928 config SYS_HAS_CPU_VR41XX
1137 erratum 24313: ignore memory acce !! 1929 bool
1138 1930
1139 The fixes are in ITS initialization !! 1931 config SYS_HAS_CPU_R4300
1140 type and table size provided by the !! 1932 bool
1141 1933
1142 If unsure, say Y. !! 1934 config SYS_HAS_CPU_R4X00
>> 1935 bool
1143 1936
1144 config CAVIUM_ERRATUM_23144 !! 1937 config SYS_HAS_CPU_TX49XX
1145 bool "Cavium erratum 23144: ITS SYNC !! 1938 bool
1146 depends on NUMA <<
1147 default y <<
1148 help <<
1149 ITS SYNC command hang for cross nod <<
1150 1939
1151 If unsure, say Y. !! 1940 config SYS_HAS_CPU_R5000
>> 1941 bool
1152 1942
1153 config CAVIUM_ERRATUM_23154 !! 1943 config SYS_HAS_CPU_R5432
1154 bool "Cavium errata 23154 and 38545: !! 1944 bool
1155 default y <<
1156 help <<
1157 The ThunderX GICv3 implementation r <<
1158 reading the IAR status to ensure da <<
1159 (access to icc_iar1_el1 is not sync <<
1160 1945
1161 It also suffers from erratum 38545 !! 1946 config SYS_HAS_CPU_R5500
1162 OcteonTX and OcteonTX2), resulting !! 1947 bool
1163 spuriously presented to the CPU int <<
1164 1948
1165 If unsure, say Y. !! 1949 config SYS_HAS_CPU_R6000
>> 1950 bool
1166 1951
1167 config CAVIUM_ERRATUM_27456 !! 1952 config SYS_HAS_CPU_NEVADA
1168 bool "Cavium erratum 27456: Broadcast !! 1953 bool
1169 default y <<
1170 help <<
1171 On ThunderX T88 pass 1.x through 2. <<
1172 instructions may cause the icache t <<
1173 contains data for a non-current ASI <<
1174 invalidate the icache when changing <<
1175 1954
1176 If unsure, say Y. !! 1955 config SYS_HAS_CPU_R8000
>> 1956 bool
1177 1957
1178 config CAVIUM_ERRATUM_30115 !! 1958 config SYS_HAS_CPU_R10000
1179 bool "Cavium erratum 30115: Guest may !! 1959 bool
1180 default y <<
1181 help <<
1182 On ThunderX T88 pass 1.x through 2. <<
1183 1.2, and T83 Pass 1.0, KVM guest ex <<
1184 interrupts in host. Trapping both G <<
1185 accesses sidesteps the issue. <<
1186 1960
1187 If unsure, say Y. !! 1961 config SYS_HAS_CPU_RM7000
>> 1962 bool
1188 1963
1189 config CAVIUM_TX2_ERRATUM_219 !! 1964 config SYS_HAS_CPU_SB1
1190 bool "Cavium ThunderX2 erratum 219: P !! 1965 bool
1191 default y <<
1192 help <<
1193 On Cavium ThunderX2, a load, store <<
1194 TTBR update and the corresponding c <<
1195 cause a spurious Data Abort to be d <<
1196 the CPU core. <<
1197 <<
1198 Work around the issue by avoiding t <<
1199 trapping KVM guest TTBRx_EL1 writes <<
1200 trap handler performs the correspon <<
1201 instruction and ensures context syn <<
1202 exception return. <<
1203 1966
1204 If unsure, say Y. !! 1967 config SYS_HAS_CPU_CAVIUM_OCTEON
>> 1968 bool
1205 1969
1206 config FUJITSU_ERRATUM_010001 !! 1970 config SYS_HAS_CPU_BMIPS
1207 bool "Fujitsu-A64FX erratum E#010001: !! 1971 bool
1208 default y <<
1209 help <<
1210 This option adds a workaround for F <<
1211 On some variants of the Fujitsu-A64 <<
1212 accesses may cause undefined fault <<
1213 This fault occurs under a specific <<
1214 load/store instruction performs an <<
1215 case-1 TTBR0_EL1 with TCR_EL1.NFD0 <<
1216 case-2 TTBR0_EL2 with TCR_EL2.NFD0 <<
1217 case-3 TTBR1_EL1 with TCR_EL1.NFD1 <<
1218 case-4 TTBR1_EL2 with TCR_EL2.NFD1 <<
1219 1972
1220 The workaround is to ensure these b !! 1973 config SYS_HAS_CPU_BMIPS32_3300
1221 The workaround only affects the Fuj !! 1974 bool
>> 1975 select SYS_HAS_CPU_BMIPS
1222 1976
1223 If unsure, say Y. !! 1977 config SYS_HAS_CPU_BMIPS4350
>> 1978 bool
>> 1979 select SYS_HAS_CPU_BMIPS
1224 1980
1225 config HISILICON_ERRATUM_161600802 !! 1981 config SYS_HAS_CPU_BMIPS4380
1226 bool "Hip07 161600802: Erroneous redi !! 1982 bool
1227 default y !! 1983 select SYS_HAS_CPU_BMIPS
1228 help <<
1229 The HiSilicon Hip07 SoC uses the wr <<
1230 when issued ITS commands such as VM <<
1231 a 128kB offset to be applied to the <<
1232 1984
1233 If unsure, say Y. !! 1985 config SYS_HAS_CPU_BMIPS5000
>> 1986 bool
>> 1987 select SYS_HAS_CPU_BMIPS
1234 1988
1235 config QCOM_FALKOR_ERRATUM_1003 !! 1989 config SYS_HAS_CPU_XLR
1236 bool "Falkor E1003: Incorrect transla !! 1990 bool
1237 default y <<
1238 help <<
1239 On Falkor v1, an incorrect ASID may <<
1240 and BADDR are changed together in T <<
1241 in TTBR1_EL1, this situation only o <<
1242 then only for entries in the walk c <<
1243 is unchanged. Work around the errat <<
1244 entries for the trampoline before e <<
1245 1991
1246 config QCOM_FALKOR_ERRATUM_1009 !! 1992 config SYS_HAS_CPU_XLP
1247 bool "Falkor E1009: Prematurely compl !! 1993 bool
>> 1994
>> 1995 config MIPS_MALTA_PM
>> 1996 depends on MIPS_MALTA
>> 1997 depends on PCI
>> 1998 bool
1248 default y 1999 default y
1249 select ARM64_WORKAROUND_REPEAT_TLBI <<
1250 help <<
1251 On Falkor v1, the CPU may premature <<
1252 TLBI xxIS invalidate maintenance op <<
1253 one more time to fix the issue. <<
1254 2000
1255 If unsure, say Y. !! 2001 #
>> 2002 # CPU may reorder R->R, R->W, W->R, W->W
>> 2003 # Reordering beyond LL and SC is handled in WEAK_REORDERING_BEYOND_LLSC
>> 2004 #
>> 2005 config WEAK_ORDERING
>> 2006 bool
1256 2007
1257 config QCOM_QDF2400_ERRATUM_0065 !! 2008 #
1258 bool "QDF2400 E0065: Incorrect GITS_T !! 2009 # CPU may reorder reads and writes beyond LL/SC
1259 default y !! 2010 # CPU may reorder R->LL, R->LL, W->LL, W->LL, R->SC, R->SC, W->SC, W->SC
1260 help !! 2011 #
1261 On Qualcomm Datacenter Technologies !! 2012 config WEAK_REORDERING_BEYOND_LLSC
1262 ITE size incorrectly. The GITS_TYPE !! 2013 bool
1263 been indicated as 16Bytes (0xf), no !! 2014 endmenu
1264 2015
1265 If unsure, say Y. !! 2016 #
>> 2017 # These two indicate any level of the MIPS32 and MIPS64 architecture
>> 2018 #
>> 2019 config CPU_MIPS32
>> 2020 bool
>> 2021 default y if CPU_MIPS32_R1 || CPU_MIPS32_R2 || CPU_MIPS32_R6
1266 2022
1267 config QCOM_FALKOR_ERRATUM_E1041 !! 2023 config CPU_MIPS64
1268 bool "Falkor E1041: Speculative instr !! 2024 bool
1269 default y !! 2025 default y if CPU_MIPS64_R1 || CPU_MIPS64_R2 || CPU_MIPS64_R6
1270 help <<
1271 Falkor CPU may speculatively fetch <<
1272 memory location when MMU translatio <<
1273 to SCTLR_ELn[M]=0. Prefix an ISB in <<
1274 2026
1275 If unsure, say Y. !! 2027 #
>> 2028 # These two indicate the revision of the architecture, either Release 1 or Release 2
>> 2029 #
>> 2030 config CPU_MIPSR1
>> 2031 bool
>> 2032 default y if CPU_MIPS32_R1 || CPU_MIPS64_R1
1276 2033
1277 config NVIDIA_CARMEL_CNP_ERRATUM !! 2034 config CPU_MIPSR2
1278 bool "NVIDIA Carmel CNP: CNP on Carme !! 2035 bool
1279 default y !! 2036 default y if CPU_MIPS32_R2 || CPU_MIPS64_R2 || CPU_CAVIUM_OCTEON
1280 help !! 2037 select CPU_HAS_RIXI
1281 If CNP is enabled on Carmel cores, !! 2038 select MIPS_SPRAM
1282 invalidate shared TLB entries insta <<
1283 on standard ARM cores. <<
1284 2039
1285 If unsure, say Y. !! 2040 config CPU_MIPSR6
>> 2041 bool
>> 2042 default y if CPU_MIPS32_R6 || CPU_MIPS64_R6
>> 2043 select CPU_HAS_RIXI
>> 2044 select HAVE_ARCH_BITREVERSE
>> 2045 select MIPS_ASID_BITS_VARIABLE
>> 2046 select MIPS_SPRAM
1286 2047
1287 config ROCKCHIP_ERRATUM_3588001 !! 2048 config EVA
1288 bool "Rockchip 3588001: GIC600 can no !! 2049 bool
1289 default y <<
1290 help <<
1291 The Rockchip RK3588 GIC600 SoC inte <<
1292 This means, that its sharability fe <<
1293 is supported by the IP itself. <<
1294 2050
1295 If unsure, say Y. !! 2051 config XPA
>> 2052 bool
1296 2053
1297 config SOCIONEXT_SYNQUACER_PREITS !! 2054 config SYS_SUPPORTS_32BIT_KERNEL
1298 bool "Socionext Synquacer: Workaround !! 2055 bool
1299 default y !! 2056 config SYS_SUPPORTS_64BIT_KERNEL
1300 help !! 2057 bool
1301 Socionext Synquacer SoCs implement !! 2058 config CPU_SUPPORTS_32BIT_KERNEL
1302 MSI doorbell writes with non-zero v !! 2059 bool
>> 2060 config CPU_SUPPORTS_64BIT_KERNEL
>> 2061 bool
>> 2062 config CPU_SUPPORTS_CPUFREQ
>> 2063 bool
>> 2064 config CPU_SUPPORTS_ADDRWINCFG
>> 2065 bool
>> 2066 config CPU_SUPPORTS_HUGEPAGES
>> 2067 bool
>> 2068 config CPU_SUPPORTS_UNCACHED_ACCELERATED
>> 2069 bool
>> 2070 config MIPS_PGD_C0_CONTEXT
>> 2071 bool
>> 2072 default y if 64BIT && CPU_MIPSR2 && !CPU_XLP
1303 2073
1304 If unsure, say Y. !! 2074 #
>> 2075 # Set to y for ptrace access to watch registers.
>> 2076 #
>> 2077 config HARDWARE_WATCHPOINTS
>> 2078 bool
>> 2079 default y if CPU_MIPSR1 || CPU_MIPSR2 || CPU_MIPSR6
1305 2080
1306 endmenu # "ARM errata workarounds via the alt !! 2081 menu "Kernel type"
1307 2082
1308 choice 2083 choice
1309 prompt "Page size" !! 2084 prompt "Kernel code model"
1310 default ARM64_4K_PAGES <<
1311 help 2085 help
1312 Page size (translation granule) con !! 2086 You should only select this option if you have a workload that
1313 !! 2087 actually benefits from 64-bit processing or if your machine has
1314 config ARM64_4K_PAGES !! 2088 large memory. You will only be presented a single option in this
1315 bool "4KB" !! 2089 menu if your system does not support both 32-bit and 64-bit kernels.
1316 select HAVE_PAGE_SIZE_4KB !! 2090
1317 help !! 2091 config 32BIT
1318 This feature enables 4KB pages supp !! 2092 bool "32-bit kernel"
1319 !! 2093 depends on CPU_SUPPORTS_32BIT_KERNEL && SYS_SUPPORTS_32BIT_KERNEL
1320 config ARM64_16K_PAGES !! 2094 select TRAD_SIGNALS
1321 bool "16KB" <<
1322 select HAVE_PAGE_SIZE_16KB <<
1323 help 2095 help
1324 The system will use 16KB pages supp !! 2096 Select this option if you want to build a 32-bit kernel.
1325 requires applications compiled with <<
1326 aligned segments. <<
1327 2097
1328 config ARM64_64K_PAGES !! 2098 config 64BIT
1329 bool "64KB" !! 2099 bool "64-bit kernel"
1330 select HAVE_PAGE_SIZE_64KB !! 2100 depends on CPU_SUPPORTS_64BIT_KERNEL && SYS_SUPPORTS_64BIT_KERNEL
1331 help 2101 help
1332 This feature enables 64KB pages sup !! 2102 Select this option if you want to build a 64-bit kernel.
1333 allowing only two levels of page ta <<
1334 look-up. AArch32 emulation requires <<
1335 with 64K aligned segments. <<
1336 2103
1337 endchoice 2104 endchoice
1338 2105
>> 2106 config KVM_GUEST
>> 2107 bool "KVM Guest Kernel"
>> 2108 depends on BROKEN_ON_SMP
>> 2109 help
>> 2110 Select this option if building a guest kernel for KVM (Trap & Emulate)
>> 2111 mode.
>> 2112
>> 2113 config KVM_GUEST_TIMER_FREQ
>> 2114 int "Count/Compare Timer Frequency (MHz)"
>> 2115 depends on KVM_GUEST
>> 2116 default 100
>> 2117 help
>> 2118 Set this to non-zero if building a guest kernel for KVM to skip RTC
>> 2119 emulation when determining guest CPU Frequency. Instead, the guest's
>> 2120 timer frequency is specified directly.
>> 2121
>> 2122 config MIPS_VA_BITS_48
>> 2123 bool "48 bits virtual memory"
>> 2124 depends on 64BIT
>> 2125 help
>> 2126 Support a maximum at least 48 bits of application virtual memory.
>> 2127 Default is 40 bits or less, depending on the CPU.
>> 2128 This option result in a small memory overhead for page tables.
>> 2129 This option is only supported with 16k and 64k page sizes.
>> 2130 If unsure, say N.
>> 2131
1339 choice 2132 choice
1340 prompt "Virtual address space size" !! 2133 prompt "Kernel page size"
1341 default ARM64_VA_BITS_52 !! 2134 default PAGE_SIZE_4KB
1342 help <<
1343 Allows choosing one of multiple pos <<
1344 space sizes. The level of translati <<
1345 a combination of page size and virt <<
1346 <<
1347 config ARM64_VA_BITS_36 <<
1348 bool "36-bit" if EXPERT <<
1349 depends on PAGE_SIZE_16KB <<
1350 <<
1351 config ARM64_VA_BITS_39 <<
1352 bool "39-bit" <<
1353 depends on PAGE_SIZE_4KB <<
1354 <<
1355 config ARM64_VA_BITS_42 <<
1356 bool "42-bit" <<
1357 depends on PAGE_SIZE_64KB <<
1358 <<
1359 config ARM64_VA_BITS_47 <<
1360 bool "47-bit" <<
1361 depends on PAGE_SIZE_16KB <<
1362 <<
1363 config ARM64_VA_BITS_48 <<
1364 bool "48-bit" <<
1365 <<
1366 config ARM64_VA_BITS_52 <<
1367 bool "52-bit" <<
1368 depends on ARM64_PAN || !ARM64_SW_TTB <<
1369 help <<
1370 Enable 52-bit virtual addressing fo <<
1371 requested via a hint to mmap(). The <<
1372 virtual addresses for its own mappi <<
1373 this feature is available, otherwis <<
1374 <<
1375 NOTE: Enabling 52-bit virtual addre <<
1376 ARMv8.3 Pointer Authentication will <<
1377 reduced from 7 bits to 3 bits, whic <<
1378 impact on its susceptibility to bru <<
1379 2135
1380 If unsure, select 48-bit virtual ad !! 2136 config PAGE_SIZE_4KB
>> 2137 bool "4kB"
>> 2138 depends on !CPU_LOONGSON2 && !CPU_LOONGSON3
>> 2139 depends on !MIPS_VA_BITS_48
>> 2140 help
>> 2141 This option select the standard 4kB Linux page size. On some
>> 2142 R3000-family processors this is the only available page size. Using
>> 2143 4kB page size will minimize memory consumption and is therefore
>> 2144 recommended for low memory systems.
>> 2145
>> 2146 config PAGE_SIZE_8KB
>> 2147 bool "8kB"
>> 2148 depends on CPU_R8000 || CPU_CAVIUM_OCTEON
>> 2149 depends on !MIPS_VA_BITS_48
>> 2150 help
>> 2151 Using 8kB page size will result in higher performance kernel at
>> 2152 the price of higher memory consumption. This option is available
>> 2153 only on R8000 and cnMIPS processors. Note that you will need a
>> 2154 suitable Linux distribution to support this.
>> 2155
>> 2156 config PAGE_SIZE_16KB
>> 2157 bool "16kB"
>> 2158 depends on !CPU_R3000 && !CPU_TX39XX
>> 2159 help
>> 2160 Using 16kB page size will result in higher performance kernel at
>> 2161 the price of higher memory consumption. This option is available on
>> 2162 all non-R3000 family processors. Note that you will need a suitable
>> 2163 Linux distribution to support this.
>> 2164
>> 2165 config PAGE_SIZE_32KB
>> 2166 bool "32kB"
>> 2167 depends on CPU_CAVIUM_OCTEON
>> 2168 depends on !MIPS_VA_BITS_48
>> 2169 help
>> 2170 Using 32kB page size will result in higher performance kernel at
>> 2171 the price of higher memory consumption. This option is available
>> 2172 only on cnMIPS cores. Note that you will need a suitable Linux
>> 2173 distribution to support this.
>> 2174
>> 2175 config PAGE_SIZE_64KB
>> 2176 bool "64kB"
>> 2177 depends on !CPU_R3000 && !CPU_TX39XX && !CPU_R6000
>> 2178 help
>> 2179 Using 64kB page size will result in higher performance kernel at
>> 2180 the price of higher memory consumption. This option is available on
>> 2181 all non-R3000 family processor. Not that at the time of this
>> 2182 writing this option is still high experimental.
1381 2183
1382 endchoice 2184 endchoice
1383 2185
1384 config ARM64_FORCE_52BIT !! 2186 config FORCE_MAX_ZONEORDER
1385 bool "Force 52-bit virtual addresses !! 2187 int "Maximum zone order"
1386 depends on ARM64_VA_BITS_52 && EXPERT !! 2188 range 14 64 if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_64KB
1387 help !! 2189 default "14" if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_64KB
1388 For systems with 52-bit userspace V !! 2190 range 13 64 if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_32KB
1389 to maintain compatibility with olde !! 2191 default "13" if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_32KB
1390 unless a hint is supplied to mmap. !! 2192 range 12 64 if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_16KB
1391 !! 2193 default "12" if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_16KB
1392 This configuration option disables !! 2194 range 11 64
1393 forces all userspace addresses to b !! 2195 default "11"
1394 should only enable this configurati !! 2196 help
1395 memory management code. If unsure s !! 2197 The kernel memory allocator divides physically contiguous memory
>> 2198 blocks into "zones", where each zone is a power of two number of
>> 2199 pages. This option selects the largest power of two that the kernel
>> 2200 keeps in the memory allocator. If you need to allocate very large
>> 2201 blocks of physically contiguous memory, then you may need to
>> 2202 increase this value.
1396 2203
1397 config ARM64_VA_BITS !! 2204 This config option is actually maximum order plus one. For example,
1398 int !! 2205 a value of 11 means that the largest free memory block is 2^10 pages.
1399 default 36 if ARM64_VA_BITS_36 <<
1400 default 39 if ARM64_VA_BITS_39 <<
1401 default 42 if ARM64_VA_BITS_42 <<
1402 default 47 if ARM64_VA_BITS_47 <<
1403 default 48 if ARM64_VA_BITS_48 <<
1404 default 52 if ARM64_VA_BITS_52 <<
1405 2206
1406 choice !! 2207 The page size is not necessarily 4KB. Keep this in mind
1407 prompt "Physical address space size" !! 2208 when choosing a value for this option.
1408 default ARM64_PA_BITS_48 <<
1409 help <<
1410 Choose the maximum physical address <<
1411 support. <<
1412 2209
1413 config ARM64_PA_BITS_48 !! 2210 config BOARD_SCACHE
1414 bool "48-bit" !! 2211 bool
1415 depends on ARM64_64K_PAGES || !ARM64_ <<
1416 <<
1417 config ARM64_PA_BITS_52 <<
1418 bool "52-bit" <<
1419 depends on ARM64_64K_PAGES || ARM64_V <<
1420 depends on ARM64_PAN || !ARM64_SW_TTB <<
1421 help <<
1422 Enable support for a 52-bit physica <<
1423 part of the ARMv8.2-LPA extension. <<
1424 <<
1425 With this enabled, the kernel will <<
1426 do not support ARMv8.2-LPA, but wit <<
1427 minor performance overhead). <<
1428 2212
1429 endchoice !! 2213 config IP22_CPU_SCACHE
>> 2214 bool
>> 2215 select BOARD_SCACHE
1430 2216
1431 config ARM64_PA_BITS !! 2217 #
1432 int !! 2218 # Support for a MIPS32 / MIPS64 style S-caches
1433 default 48 if ARM64_PA_BITS_48 !! 2219 #
1434 default 52 if ARM64_PA_BITS_52 !! 2220 config MIPS_CPU_SCACHE
>> 2221 bool
>> 2222 select BOARD_SCACHE
1435 2223
1436 config ARM64_LPA2 !! 2224 config R5000_CPU_SCACHE
1437 def_bool y !! 2225 bool
1438 depends on ARM64_PA_BITS_52 && !ARM64 !! 2226 select BOARD_SCACHE
1439 2227
1440 choice !! 2228 config RM7000_CPU_SCACHE
1441 prompt "Endianness" !! 2229 bool
1442 default CPU_LITTLE_ENDIAN !! 2230 select BOARD_SCACHE
1443 help <<
1444 Select the endianness of data acces <<
1445 applications will need to be compil <<
1446 that is selected here. <<
1447 2231
1448 config CPU_BIG_ENDIAN !! 2232 config SIBYTE_DMA_PAGEOPS
1449 bool "Build big-endian kernel" !! 2233 bool "Use DMA to clear/copy pages"
1450 # https://github.com/llvm/llvm-projec !! 2234 depends on CPU_SB1
1451 depends on AS_IS_GNU || AS_VERSION >= <<
1452 help 2235 help
1453 Say Y if you plan on running a kern !! 2236 Instead of using the CPU to zero and copy pages, use a Data Mover
>> 2237 channel. These DMA channels are otherwise unused by the standard
>> 2238 SiByte Linux port. Seems to give a small performance benefit.
1454 2239
1455 config CPU_LITTLE_ENDIAN !! 2240 config CPU_HAS_PREFETCH
1456 bool "Build little-endian kernel" !! 2241 bool
1457 help <<
1458 Say Y if you plan on running a kern <<
1459 This is usually the case for distri <<
1460 2242
1461 endchoice !! 2243 config CPU_GENERIC_DUMP_TLB
>> 2244 bool
>> 2245 default y if !(CPU_R3000 || CPU_R6000 || CPU_R8000 || CPU_TX39XX)
1462 2246
1463 config SCHED_MC !! 2247 config CPU_R4K_FPU
1464 bool "Multi-core scheduler support" !! 2248 bool
1465 help !! 2249 default y if !(CPU_R3000 || CPU_R6000 || CPU_TX39XX || CPU_CAVIUM_OCTEON)
1466 Multi-core scheduler support improv <<
1467 making when dealing with multi-core <<
1468 increased overhead in some places. <<
1469 2250
1470 config SCHED_CLUSTER !! 2251 config CPU_R4K_CACHE_TLB
1471 bool "Cluster scheduler support" !! 2252 bool
1472 help !! 2253 default y if !(CPU_R3000 || CPU_R8000 || CPU_SB1 || CPU_TX39XX || CPU_CAVIUM_OCTEON)
1473 Cluster scheduler support improves <<
1474 making when dealing with machines t <<
1475 Cluster usually means a couple of C <<
1476 by sharing mid-level caches, last-l <<
1477 busses. <<
1478 2254
1479 config SCHED_SMT !! 2255 config MIPS_MT_SMP
1480 bool "SMT scheduler support" !! 2256 bool "MIPS MT SMP support (1 TC on each available VPE)"
1481 help !! 2257 depends on SYS_SUPPORTS_MULTITHREADING && !CPU_MIPSR6
1482 Improves the CPU scheduler's decisi !! 2258 select CPU_MIPSR2_IRQ_VI
1483 MultiThreading at a cost of slightl !! 2259 select CPU_MIPSR2_IRQ_EI
1484 places. If unsure say N here. !! 2260 select SYNC_R4K
>> 2261 select MIPS_MT
>> 2262 select SMP
>> 2263 select SMP_UP
>> 2264 select SYS_SUPPORTS_SMP
>> 2265 select SYS_SUPPORTS_SCHED_SMT
>> 2266 select MIPS_PERF_SHARED_TC_COUNTERS
>> 2267 help
>> 2268 This is a kernel model which is known as SMVP. This is supported
>> 2269 on cores with the MT ASE and uses the available VPEs to implement
>> 2270 virtual processors which supports SMP. This is equivalent to the
>> 2271 Intel Hyperthreading feature. For further information go to
>> 2272 <http://www.imgtec.com/mips/mips-multithreading.asp>.
1485 2273
1486 config NR_CPUS !! 2274 config MIPS_MT
1487 int "Maximum number of CPUs (2-4096)" !! 2275 bool
1488 range 2 4096 <<
1489 default "512" <<
1490 2276
1491 config HOTPLUG_CPU !! 2277 config SCHED_SMT
1492 bool "Support for hot-pluggable CPUs" !! 2278 bool "SMT (multithreading) scheduler support"
1493 select GENERIC_IRQ_MIGRATION !! 2279 depends on SYS_SUPPORTS_SCHED_SMT
>> 2280 default n
1494 help 2281 help
1495 Say Y here to experiment with turni !! 2282 SMT scheduler support improves the CPU scheduler's decision making
1496 can be controlled through /sys/devi !! 2283 when dealing with MIPS MT enabled cores at a cost of slightly
>> 2284 increased overhead in some places. If unsure say N here.
1497 2285
1498 # Common NUMA Features !! 2286 config SYS_SUPPORTS_SCHED_SMT
1499 config NUMA !! 2287 bool
1500 bool "NUMA Memory Allocation and Sche <<
1501 select GENERIC_ARCH_NUMA <<
1502 select OF_NUMA <<
1503 select HAVE_SETUP_PER_CPU_AREA <<
1504 select NEED_PER_CPU_EMBED_FIRST_CHUNK <<
1505 select NEED_PER_CPU_PAGE_FIRST_CHUNK <<
1506 select USE_PERCPU_NUMA_NODE_ID <<
1507 help <<
1508 Enable NUMA (Non-Uniform Memory Acc <<
1509 <<
1510 The kernel will try to allocate mem <<
1511 local memory of the CPU and add som <<
1512 NUMA awareness to the kernel. <<
1513 2288
1514 config NODES_SHIFT !! 2289 config SYS_SUPPORTS_MULTITHREADING
1515 int "Maximum NUMA Nodes (as a power o !! 2290 bool
1516 range 1 10 <<
1517 default "4" <<
1518 depends on NUMA <<
1519 help <<
1520 Specify the maximum number of NUMA <<
1521 system. Increases memory reserved <<
1522 2291
1523 source "kernel/Kconfig.hz" !! 2292 config MIPS_MT_FPAFF
>> 2293 bool "Dynamic FPU affinity for FP-intensive threads"
>> 2294 default y
>> 2295 depends on MIPS_MT_SMP
1524 2296
1525 config ARCH_SPARSEMEM_ENABLE !! 2297 config MIPSR2_TO_R6_EMULATOR
1526 def_bool y !! 2298 bool "MIPS R2-to-R6 emulator"
1527 select SPARSEMEM_VMEMMAP_ENABLE !! 2299 depends on CPU_MIPSR6 && !SMP
1528 select SPARSEMEM_VMEMMAP !! 2300 default y
>> 2301 help
>> 2302 Choose this option if you want to run non-R6 MIPS userland code.
>> 2303 Even if you say 'Y' here, the emulator will still be disabled by
>> 2304 default. You can enable it using the 'mipsr2emu' kernel option.
>> 2305 The only reason this is a build-time option is to save ~14K from the
>> 2306 final kernel image.
>> 2307 comment "MIPS R2-to-R6 emulator is only available for UP kernels"
>> 2308 depends on SMP && CPU_MIPSR6
>> 2309
>> 2310 config MIPS_VPE_LOADER
>> 2311 bool "VPE loader support."
>> 2312 depends on SYS_SUPPORTS_MULTITHREADING && MODULES
>> 2313 select CPU_MIPSR2_IRQ_VI
>> 2314 select CPU_MIPSR2_IRQ_EI
>> 2315 select MIPS_MT
>> 2316 help
>> 2317 Includes a loader for loading an elf relocatable object
>> 2318 onto another VPE and running it.
1529 2319
1530 config HW_PERF_EVENTS !! 2320 config MIPS_VPE_LOADER_CMP
1531 def_bool y !! 2321 bool
1532 depends on ARM_PMU !! 2322 default "y"
>> 2323 depends on MIPS_VPE_LOADER && MIPS_CMP
1533 2324
1534 # Supported by clang >= 7.0 or GCC >= 12.0.0 !! 2325 config MIPS_VPE_LOADER_MT
1535 config CC_HAVE_SHADOW_CALL_STACK !! 2326 bool
1536 def_bool $(cc-option, -fsanitize=shad !! 2327 default "y"
>> 2328 depends on MIPS_VPE_LOADER && !MIPS_CMP
1537 2329
1538 config PARAVIRT !! 2330 config MIPS_VPE_LOADER_TOM
1539 bool "Enable paravirtualization code" !! 2331 bool "Load VPE program into memory hidden from linux"
>> 2332 depends on MIPS_VPE_LOADER
>> 2333 default y
1540 help 2334 help
1541 This changes the kernel so it can m !! 2335 The loader can use memory that is present but has been hidden from
1542 under a hypervisor, potentially imp !! 2336 Linux using the kernel command line option "mem=xxMB". It's up to
1543 over full virtualization. !! 2337 you to ensure the amount you put in the option and the space your
>> 2338 program requires is less or equal to the amount physically present.
1544 2339
1545 config PARAVIRT_TIME_ACCOUNTING !! 2340 config MIPS_VPE_APSP_API
1546 bool "Paravirtual steal time accounti !! 2341 bool "Enable support for AP/SP API (RTLX)"
1547 select PARAVIRT !! 2342 depends on MIPS_VPE_LOADER
1548 help 2343 help
1549 Select this option to enable fine g <<
1550 accounting. Time spent executing ot <<
1551 the current vCPU is discounted from <<
1552 that, there can be a small performa <<
1553 <<
1554 If in doubt, say N here. <<
1555 <<
1556 config ARCH_SUPPORTS_KEXEC <<
1557 def_bool PM_SLEEP_SMP <<
1558 <<
1559 config ARCH_SUPPORTS_KEXEC_FILE <<
1560 def_bool y <<
1561 <<
1562 config ARCH_SELECTS_KEXEC_FILE <<
1563 def_bool y <<
1564 depends on KEXEC_FILE <<
1565 select HAVE_IMA_KEXEC if IMA <<
1566 2344
1567 config ARCH_SUPPORTS_KEXEC_SIG !! 2345 config MIPS_VPE_APSP_API_CMP
1568 def_bool y !! 2346 bool
1569 !! 2347 default "y"
1570 config ARCH_SUPPORTS_KEXEC_IMAGE_VERIFY_SIG !! 2348 depends on MIPS_VPE_APSP_API && MIPS_CMP
1571 def_bool y <<
1572 <<
1573 config ARCH_DEFAULT_KEXEC_IMAGE_VERIFY_SIG <<
1574 def_bool y <<
1575 <<
1576 config ARCH_SUPPORTS_CRASH_DUMP <<
1577 def_bool y <<
1578 <<
1579 config ARCH_HAS_GENERIC_CRASHKERNEL_RESERVATI <<
1580 def_bool CRASH_RESERVE <<
1581 <<
1582 config TRANS_TABLE <<
1583 def_bool y <<
1584 depends on HIBERNATION || KEXEC_CORE <<
1585 <<
1586 config XEN_DOM0 <<
1587 def_bool y <<
1588 depends on XEN <<
1589 2349
1590 config XEN !! 2350 config MIPS_VPE_APSP_API_MT
1591 bool "Xen guest support on ARM64" !! 2351 bool
1592 depends on ARM64 && OF !! 2352 default "y"
1593 select SWIOTLB_XEN !! 2353 depends on MIPS_VPE_APSP_API && !MIPS_CMP
1594 select PARAVIRT <<
1595 help <<
1596 Say Y if you want to run Linux in a <<
1597 2354
1598 # include/linux/mmzone.h requires the followi !! 2355 config MIPS_CMP
1599 # !! 2356 bool "MIPS CMP framework support (DEPRECATED)"
1600 # MAX_PAGE_ORDER + PAGE_SHIFT <= SECTION_SI !! 2357 depends on SYS_SUPPORTS_MIPS_CMP && !CPU_MIPSR6
1601 # !! 2358 select SMP
1602 # so the maximum value of MAX_PAGE_ORDER is S !! 2359 select SYNC_R4K
1603 # !! 2360 select SYS_SUPPORTS_SMP
1604 # | SECTION_SIZE_BITS | PAGE_SHIFT | m !! 2361 select WEAK_ORDERING
1605 # ----+-------------------+--------------+--- !! 2362 default n
1606 # 4K | 27 | 12 | <<
1607 # 16K | 27 | 14 | <<
1608 # 64K | 29 | 16 | <<
1609 config ARCH_FORCE_MAX_ORDER <<
1610 int <<
1611 default "13" if ARM64_64K_PAGES <<
1612 default "11" if ARM64_16K_PAGES <<
1613 default "10" <<
1614 help 2363 help
1615 The kernel page allocator limits th !! 2364 Select this if you are using a bootloader which implements the "CMP
1616 contiguous allocations. The limit i !! 2365 framework" protocol (ie. YAMON) and want your kernel to make use of
1617 defines the maximal power of two of !! 2366 its ability to start secondary CPUs.
1618 allocated as a single contiguous bl !! 2367
1619 overriding the default setting when !! 2368 Unless you have a specific need, you should use CONFIG_MIPS_CPS
1620 large blocks of physically contiguo !! 2369 instead of this.
1621 !! 2370
1622 The maximal size of allocation cann !! 2371 config MIPS_CPS
1623 section, so the value of MAX_PAGE_O !! 2372 bool "MIPS Coherent Processing System support"
>> 2373 depends on SYS_SUPPORTS_MIPS_CPS
>> 2374 select MIPS_CM
>> 2375 select MIPS_CPC
>> 2376 select MIPS_CPS_PM if HOTPLUG_CPU
>> 2377 select SMP
>> 2378 select SYNC_R4K if (CEVT_R4K || CSRC_R4K)
>> 2379 select SYS_SUPPORTS_HOTPLUG_CPU
>> 2380 select SYS_SUPPORTS_SMP
>> 2381 select WEAK_ORDERING
>> 2382 help
>> 2383 Select this if you wish to run an SMP kernel across multiple cores
>> 2384 within a MIPS Coherent Processing System. When this option is
>> 2385 enabled the kernel will probe for other cores and boot them with
>> 2386 no external assistance. It is safe to enable this when hardware
>> 2387 support is unavailable.
>> 2388
>> 2389 config MIPS_CPS_PM
>> 2390 depends on MIPS_CPS
>> 2391 select MIPS_CPC
>> 2392 bool
1624 2393
1625 MAX_PAGE_ORDER + PAGE_SHIFT <= SE !! 2394 config MIPS_CM
>> 2395 bool
1626 2396
1627 Don't change if unsure. !! 2397 config MIPS_CPC
>> 2398 bool
1628 2399
1629 config UNMAP_KERNEL_AT_EL0 !! 2400 config SB1_PASS_2_WORKAROUNDS
1630 bool "Unmap kernel when running in us !! 2401 bool
>> 2402 depends on CPU_SB1 && (CPU_SB1_PASS_2_2 || CPU_SB1_PASS_2)
1631 default y 2403 default y
1632 help <<
1633 Speculation attacks against some hi <<
1634 be used to bypass MMU permission ch <<
1635 userspace. This can be defended aga <<
1636 when running in userspace, mapping <<
1637 via a trampoline page in the vector <<
1638 2404
1639 If unsure, say Y. !! 2405 config SB1_PASS_2_1_WORKAROUNDS
1640 !! 2406 bool
1641 config MITIGATE_SPECTRE_BRANCH_HISTORY !! 2407 depends on CPU_SB1 && CPU_SB1_PASS_2
1642 bool "Mitigate Spectre style attacks <<
1643 default y 2408 default y
1644 help <<
1645 Speculation attacks against some hi <<
1646 make use of branch history to influ <<
1647 When taking an exception from user- <<
1648 or a firmware call overwrites the b <<
1649 2409
1650 config RODATA_FULL_DEFAULT_ENABLED <<
1651 bool "Apply r/o permissions of VM are <<
1652 default y <<
1653 help <<
1654 Apply read-only attributes of VM ar <<
1655 the backing pages as well. This pre <<
1656 from being modified (inadvertently <<
1657 mapping of the same memory page. Th <<
1658 be turned off at runtime by passing <<
1659 with rodata=full if this option is <<
1660 2410
1661 This requires the linear region to !! 2411 config ARCH_PHYS_ADDR_T_64BIT
1662 which may adversely affect performa !! 2412 bool
1663 2413
1664 config ARM64_SW_TTBR0_PAN !! 2414 choice
1665 bool "Emulate Privileged Access Never !! 2415 prompt "SmartMIPS or microMIPS ASE support"
1666 depends on !KCSAN <<
1667 help <<
1668 Enabling this option prevents the k <<
1669 user-space memory directly by point <<
1670 zeroed area and reserved ASID. The <<
1671 restore the valid TTBR0_EL1 tempora <<
1672 2416
1673 config ARM64_TAGGED_ADDR_ABI !! 2417 config CPU_NEEDS_NO_SMARTMIPS_OR_MICROMIPS
1674 bool "Enable the tagged user addresse !! 2418 bool "None"
1675 default y <<
1676 help 2419 help
1677 When this option is enabled, user a !! 2420 Select this if you want neither microMIPS nor SmartMIPS support
1678 relaxed ABI via prctl() allowing ta <<
1679 to system calls as pointer argument <<
1680 Documentation/arch/arm64/tagged-add <<
1681 2421
1682 menuconfig COMPAT !! 2422 config CPU_HAS_SMARTMIPS
1683 bool "Kernel support for 32-bit EL0" !! 2423 depends on SYS_SUPPORTS_SMARTMIPS
1684 depends on ARM64_4K_PAGES || EXPERT !! 2424 bool "SmartMIPS"
1685 select HAVE_UID16 !! 2425 help
1686 select OLD_SIGSUSPEND3 !! 2426 SmartMIPS is a extension of the MIPS32 architecture aimed at
1687 select COMPAT_OLD_SIGACTION !! 2427 increased security at both hardware and software level for
>> 2428 smartcards. Enabling this option will allow proper use of the
>> 2429 SmartMIPS instructions by Linux applications. However a kernel with
>> 2430 this option will not work on a MIPS core without SmartMIPS core. If
>> 2431 you don't know you probably don't have SmartMIPS and should say N
>> 2432 here.
>> 2433
>> 2434 config CPU_MICROMIPS
>> 2435 depends on 32BIT && SYS_SUPPORTS_MICROMIPS && !CPU_MIPSR6
>> 2436 bool "microMIPS"
1688 help 2437 help
1689 This option enables support for a 3 !! 2438 When this option is enabled the kernel will be built using the
1690 kernel at EL1. AArch32-specific com !! 2439 microMIPS ISA
1691 the user helper functions, VFP supp <<
1692 handled appropriately by the kernel <<
1693 <<
1694 If you use a page size other than 4 <<
1695 that you will only be able to execu <<
1696 with page size aligned segments. <<
1697 2440
1698 If you want to execute 32-bit users !! 2441 endchoice
1699 2442
1700 if COMPAT !! 2443 config CPU_HAS_MSA
>> 2444 bool "Support for the MIPS SIMD Architecture"
>> 2445 depends on CPU_SUPPORTS_MSA
>> 2446 depends on 64BIT || MIPS_O32_FP64_SUPPORT
>> 2447 help
>> 2448 MIPS SIMD Architecture (MSA) introduces 128 bit wide vector registers
>> 2449 and a set of SIMD instructions to operate on them. When this option
>> 2450 is enabled the kernel will support allocating & switching MSA
>> 2451 vector register contexts. If you know that your kernel will only be
>> 2452 running on CPUs which do not support MSA or that your userland will
>> 2453 not be making use of it then you may wish to say N here to reduce
>> 2454 the size & complexity of your kernel.
1701 2455
1702 config KUSER_HELPERS !! 2456 If unsure, say Y.
1703 bool "Enable kuser helpers page for 3 <<
1704 default y <<
1705 help <<
1706 Warning: disabling this option may <<
1707 2457
1708 Provide kuser helpers to compat tas !! 2458 config CPU_HAS_WB
1709 helper code to userspace in read on !! 2459 bool
1710 to allow userspace to be independen <<
1711 the system. This permits binaries t <<
1712 to ARMv8 without modification. <<
1713 2460
1714 See Documentation/arch/arm/kernel_u !! 2461 config XKS01
>> 2462 bool
1715 2463
1716 However, the fixed address nature o !! 2464 config CPU_HAS_RIXI
1717 by ROP (return orientated programmi !! 2465 bool
1718 exploits. <<
1719 2466
1720 If all of the binaries and librarie !! 2467 #
1721 are built specifically for your pla !! 2468 # Vectored interrupt mode is an R2 feature
1722 these helpers, then you can turn th !! 2469 #
1723 such exploits. However, in that cas !! 2470 config CPU_MIPSR2_IRQ_VI
1724 relying on those helpers is run, it !! 2471 bool
1725 2472
1726 Say N here only if you are absolute !! 2473 #
1727 need these helpers; otherwise, the !! 2474 # Extended interrupt mode is an R2 feature
>> 2475 #
>> 2476 config CPU_MIPSR2_IRQ_EI
>> 2477 bool
1728 2478
1729 config COMPAT_VDSO !! 2479 config CPU_HAS_SYNC
1730 bool "Enable vDSO for 32-bit applicat !! 2480 bool
1731 depends on !CPU_BIG_ENDIAN !! 2481 depends on !CPU_R3000
1732 depends on (CC_IS_CLANG && LD_IS_LLD) <<
1733 select GENERIC_COMPAT_VDSO <<
1734 default y 2482 default y
1735 help <<
1736 Place in the process address space <<
1737 ELF shared object providing fast im <<
1738 and clock_gettime. <<
1739 2483
1740 You must have a 32-bit build of gli !! 2484 #
1741 to seamlessly take advantage of thi !! 2485 # CPU non-features
>> 2486 #
>> 2487 config CPU_DADDI_WORKAROUNDS
>> 2488 bool
1742 2489
1743 config THUMB2_COMPAT_VDSO !! 2490 config CPU_R4000_WORKAROUNDS
1744 bool "Compile the 32-bit vDSO for Thu !! 2491 bool
1745 depends on COMPAT_VDSO !! 2492 select CPU_R4400_WORKAROUNDS
1746 default y <<
1747 help <<
1748 Compile the compat vDSO with '-mthu <<
1749 otherwise with '-marm'. <<
1750 2493
1751 config COMPAT_ALIGNMENT_FIXUPS !! 2494 config CPU_R4400_WORKAROUNDS
1752 bool "Fix up misaligned multi-word lo !! 2495 bool
1753 2496
1754 menuconfig ARMV8_DEPRECATED !! 2497 config MIPS_ASID_SHIFT
1755 bool "Emulate deprecated/obsolete ARM !! 2498 int
1756 depends on SYSCTL !! 2499 default 6 if CPU_R3000 || CPU_TX39XX
1757 help !! 2500 default 4 if CPU_R8000
1758 Legacy software support may require !! 2501 default 0
1759 that have been deprecated or obsole <<
1760 2502
1761 Enable this config to enable select !! 2503 config MIPS_ASID_BITS
1762 features. !! 2504 int
>> 2505 default 0 if MIPS_ASID_BITS_VARIABLE
>> 2506 default 6 if CPU_R3000 || CPU_TX39XX
>> 2507 default 8
1763 2508
1764 If unsure, say Y !! 2509 config MIPS_ASID_BITS_VARIABLE
>> 2510 bool
1765 2511
1766 if ARMV8_DEPRECATED !! 2512 #
>> 2513 # - Highmem only makes sense for the 32-bit kernel.
>> 2514 # - The current highmem code will only work properly on physically indexed
>> 2515 # caches such as R3000, SB1, R7000 or those that look like they're virtually
>> 2516 # indexed such as R4000/R4400 SC and MC versions or R10000. So for the
>> 2517 # moment we protect the user and offer the highmem option only on machines
>> 2518 # where it's known to be safe. This will not offer highmem on a few systems
>> 2519 # such as MIPS32 and MIPS64 CPUs which may have virtual and physically
>> 2520 # indexed CPUs but we're playing safe.
>> 2521 # - We use SYS_SUPPORTS_HIGHMEM to offer highmem only for systems where we
>> 2522 # know they might have memory configurations that could make use of highmem
>> 2523 # support.
>> 2524 #
>> 2525 config HIGHMEM
>> 2526 bool "High Memory Support"
>> 2527 depends on 32BIT && CPU_SUPPORTS_HIGHMEM && SYS_SUPPORTS_HIGHMEM && !CPU_MIPS32_3_5_EVA
1767 2528
1768 config SWP_EMULATION !! 2529 config CPU_SUPPORTS_HIGHMEM
1769 bool "Emulate SWP/SWPB instructions" !! 2530 bool
1770 help <<
1771 ARMv8 obsoletes the use of A32 SWP/ <<
1772 they are always undefined. Say Y he <<
1773 emulation of these instructions for <<
1774 This feature can be controlled at r <<
1775 sysctl which is disabled by default <<
1776 2531
1777 In some older versions of glibc [<= !! 2532 config SYS_SUPPORTS_HIGHMEM
1778 trylock() operations with the assum !! 2533 bool
1779 be preempted. This invalid assumpti <<
1780 with SWP emulation enabled, leading <<
1781 application. <<
1782 2534
1783 NOTE: when accessing uncached share !! 2535 config SYS_SUPPORTS_SMARTMIPS
1784 on an external transaction monitori !! 2536 bool
1785 monitor to maintain update atomicit <<
1786 implement a global monitor, this op <<
1787 perform SWP operations to uncached <<
1788 2537
1789 If unsure, say Y !! 2538 config SYS_SUPPORTS_MICROMIPS
>> 2539 bool
1790 2540
1791 config CP15_BARRIER_EMULATION !! 2541 config SYS_SUPPORTS_MIPS16
1792 bool "Emulate CP15 Barrier instructio !! 2542 bool
1793 help 2543 help
1794 The CP15 barrier instructions - CP1 !! 2544 This option must be set if a kernel might be executed on a MIPS16-
1795 CP15DMB - are deprecated in ARMv8 ( !! 2545 enabled CPU even if MIPS16 is not actually being used. In other
1796 strongly recommended to use the ISB !! 2546 words, it makes the kernel MIPS16-tolerant.
1797 instructions instead. <<
1798 2547
1799 Say Y here to enable software emula !! 2548 config CPU_SUPPORTS_MSA
1800 instructions for AArch32 userspace !! 2549 bool
1801 enabled, CP15 barrier usage is trac <<
1802 identify software that needs updati <<
1803 controlled at runtime with the abi. <<
1804 2550
1805 If unsure, say Y !! 2551 config ARCH_FLATMEM_ENABLE
>> 2552 def_bool y
>> 2553 depends on !NUMA && !CPU_LOONGSON2
1806 2554
1807 config SETEND_EMULATION !! 2555 config ARCH_DISCONTIGMEM_ENABLE
1808 bool "Emulate SETEND instruction" !! 2556 bool
>> 2557 default y if SGI_IP27
1809 help 2558 help
1810 The SETEND instruction alters the d !! 2559 Say Y to support efficient handling of discontiguous physical memory,
1811 AArch32 EL0, and is deprecated in A !! 2560 for architectures which are either NUMA (Non-Uniform Memory Access)
1812 !! 2561 or have huge holes in the physical address space for other reasons.
1813 Say Y here to enable software emula !! 2562 See <file:Documentation/vm/numa> for more.
1814 for AArch32 userspace code. This fe <<
1815 at runtime with the abi.setend sysc <<
1816 2563
1817 Note: All the cpus on the system mu !! 2564 config ARCH_SPARSEMEM_ENABLE
1818 for this feature to be enabled. If !! 2565 bool
1819 endian - is hotplugged in after thi !! 2566 select SPARSEMEM_STATIC
1820 be unexpected results in the applic <<
1821 <<
1822 If unsure, say Y <<
1823 endif # ARMV8_DEPRECATED <<
1824 <<
1825 endif # COMPAT <<
1826 <<
1827 menu "ARMv8.1 architectural features" <<
1828 2567
1829 config ARM64_HW_AFDBM !! 2568 config NUMA
1830 bool "Support for hardware updates of !! 2569 bool "NUMA Support"
1831 default y !! 2570 depends on SYS_SUPPORTS_NUMA
1832 help 2571 help
1833 The ARMv8.1 architecture extensions !! 2572 Say Y to compile the kernel to support NUMA (Non-Uniform Memory
1834 hardware updates of the access and !! 2573 Access). This option improves performance on systems with more
1835 table entries. When enabled in TCR_ !! 2574 than two nodes; on two node systems it is generally better to
1836 capable processors, accesses to pag !! 2575 leave it disabled; on single node systems disable this option
1837 set this bit instead of raising an !! 2576 disabled.
1838 Similarly, writes to read-only page <<
1839 clear the read-only bit (AP[2]) ins <<
1840 permission fault. <<
1841 2577
1842 Kernels built with this configurati !! 2578 config SYS_SUPPORTS_NUMA
1843 to work on pre-ARMv8.1 hardware and !! 2579 bool
1844 minimal. If unsure, say Y. <<
1845 2580
1846 config ARM64_PAN !! 2581 config RELOCATABLE
1847 bool "Enable support for Privileged A !! 2582 bool "Relocatable kernel"
1848 default y !! 2583 depends on SYS_SUPPORTS_RELOCATABLE && (CPU_MIPS32_R2 || CPU_MIPS64_R2 || CPU_MIPS32_R6 || CPU_MIPS64_R6)
1849 help 2584 help
1850 Privileged Access Never (PAN; part !! 2585 This builds a kernel image that retains relocation information
1851 prevents the kernel or hypervisor f !! 2586 so it can be loaded someplace besides the default 1MB.
1852 memory directly. !! 2587 The relocations make the kernel binary about 15% larger,
1853 !! 2588 but are discarded at runtime
1854 Choosing this option will cause any !! 2589
1855 copy_to_user et al) memory access t !! 2590 config RELOCATION_TABLE_SIZE
>> 2591 hex "Relocation table size"
>> 2592 depends on RELOCATABLE
>> 2593 range 0x0 0x01000000
>> 2594 default "0x00100000"
>> 2595 ---help---
>> 2596 A table of relocation data will be appended to the kernel binary
>> 2597 and parsed at boot to fix up the relocated kernel.
1856 2598
1857 The feature is detected at runtime, !! 2599 This option allows the amount of space reserved for the table to be
1858 instruction if the cpu does not imp !! 2600 adjusted, although the default of 1Mb should be ok in most cases.
1859 2601
1860 config AS_HAS_LSE_ATOMICS !! 2602 The build will fail and a valid size suggested if this is too small.
1861 def_bool $(as-instr,.arch_extension l <<
1862 2603
1863 config ARM64_LSE_ATOMICS !! 2604 If unsure, leave at the default value.
1864 bool <<
1865 default ARM64_USE_LSE_ATOMICS <<
1866 depends on AS_HAS_LSE_ATOMICS <<
1867 2605
1868 config ARM64_USE_LSE_ATOMICS !! 2606 config RANDOMIZE_BASE
1869 bool "Atomic instructions" !! 2607 bool "Randomize the address of the kernel image"
1870 default y !! 2608 depends on RELOCATABLE
1871 help !! 2609 ---help---
1872 As part of the Large System Extensi !! 2610 Randomizes the physical and virtual address at which the
1873 atomic instructions that are design !! 2611 kernel image is loaded, as a security feature that
1874 very large systems. !! 2612 deters exploit attempts relying on knowledge of the location
1875 !! 2613 of kernel internals.
1876 Say Y here to make use of these ins <<
1877 atomic routines. This incurs a smal <<
1878 not support these instructions and <<
1879 built with binutils >= 2.25 in orde <<
1880 to be used. <<
1881 2614
1882 endmenu # "ARMv8.1 architectural features" !! 2615 Entropy is generated using any coprocessor 0 registers available.
1883 2616
1884 menu "ARMv8.2 architectural features" !! 2617 The kernel will be offset by up to RANDOMIZE_BASE_MAX_OFFSET.
1885 2618
1886 config AS_HAS_ARMV8_2 !! 2619 If unsure, say N.
1887 def_bool $(cc-option,-Wa$(comma)-marc <<
1888 2620
1889 config AS_HAS_SHA3 !! 2621 config RANDOMIZE_BASE_MAX_OFFSET
1890 def_bool $(as-instr,.arch armv8.2-a+s !! 2622 hex "Maximum kASLR offset" if EXPERT
>> 2623 depends on RANDOMIZE_BASE
>> 2624 range 0x0 0x40000000 if EVA || 64BIT
>> 2625 range 0x0 0x08000000
>> 2626 default "0x01000000"
>> 2627 ---help---
>> 2628 When kASLR is active, this provides the maximum offset that will
>> 2629 be applied to the kernel image. It should be set according to the
>> 2630 amount of physical RAM available in the target system minus
>> 2631 PHYSICAL_START and must be a power of 2.
1891 2632
1892 config ARM64_PMEM !! 2633 This is limited by the size of KSEG0, 256Mb on 32-bit or 1Gb with
1893 bool "Enable support for persistent m !! 2634 EVA or 64-bit. The default is 16Mb.
1894 select ARCH_HAS_PMEM_API <<
1895 select ARCH_HAS_UACCESS_FLUSHCACHE <<
1896 help <<
1897 Say Y to enable support for the per <<
1898 ARMv8.2 DCPoP feature. <<
1899 2635
1900 The feature is detected at runtime, !! 2636 config NODES_SHIFT
1901 operations if DC CVAP is not suppor !! 2637 int
1902 DC CVAP itself if the system does n !! 2638 default "6"
>> 2639 depends on NEED_MULTIPLE_NODES
1903 2640
1904 config ARM64_RAS_EXTN !! 2641 config HW_PERF_EVENTS
1905 bool "Enable support for RAS CPU Exte !! 2642 bool "Enable hardware performance counter support for perf events"
>> 2643 depends on PERF_EVENTS && !OPROFILE && (CPU_MIPS32 || CPU_MIPS64 || CPU_R10000 || CPU_SB1 || CPU_CAVIUM_OCTEON || CPU_XLP || CPU_LOONGSON3)
1906 default y 2644 default y
1907 help 2645 help
1908 CPUs that support the Reliability, !! 2646 Enable hardware performance counter support for perf events. If
1909 (RAS) Extensions, part of ARMv8.2 a !! 2647 disabled, perf events will use software events only.
1910 errors, classify them and report th <<
1911 <<
1912 On CPUs with these extensions syste <<
1913 barriers to determine if faults are <<
1914 classification from a new set of re <<
1915 2648
1916 Selecting this feature will allow t !! 2649 source "mm/Kconfig"
1917 and access the new registers if the <<
1918 Platform RAS features may additiona <<
1919 2650
1920 config ARM64_CNP !! 2651 config SMP
1921 bool "Enable support for Common Not P !! 2652 bool "Multi-Processing support"
1922 default y !! 2653 depends on SYS_SUPPORTS_SMP
1923 depends on ARM64_PAN || !ARM64_SW_TTB <<
1924 help 2654 help
1925 Common Not Private (CNP) allows tra !! 2655 This enables support for systems with more than one CPU. If you have
1926 be shared between different PEs in !! 2656 a system with only one CPU, say N. If you have a system with more
1927 domain, so the hardware can use thi !! 2657 than one CPU, say Y.
1928 caching of such entries in the TLB. !! 2658
>> 2659 If you say N here, the kernel will run on uni- and multiprocessor
>> 2660 machines, but will use only one CPU of a multiprocessor machine. If
>> 2661 you say Y here, the kernel will run on many, but not all,
>> 2662 uniprocessor machines. On a uniprocessor machine, the kernel
>> 2663 will run faster if you say N here.
1929 2664
1930 Selecting this option allows the CN !! 2665 People using multiprocessor machines who say Y here should also say
1931 at runtime, and does not affect PEs !! 2666 Y to "Enhanced Real Time Clock Support", below.
1932 this feature. <<
1933 2667
1934 endmenu # "ARMv8.2 architectural features" !! 2668 See also the SMP-HOWTO available at
>> 2669 <http://www.tldp.org/docs.html#howto>.
1935 2670
1936 menu "ARMv8.3 architectural features" !! 2671 If you don't know what to do here, say N.
1937 2672
1938 config ARM64_PTR_AUTH !! 2673 config HOTPLUG_CPU
1939 bool "Enable support for pointer auth !! 2674 bool "Support for hot-pluggable CPUs"
1940 default y !! 2675 depends on SMP && SYS_SUPPORTS_HOTPLUG_CPU
1941 help 2676 help
1942 Pointer authentication (part of the !! 2677 Say Y here to allow turning CPUs off and on. CPUs can be
1943 instructions for signing and authen !! 2678 controlled through /sys/devices/system/cpu.
1944 keys, which can be used to mitigate !! 2679 (Note: power management support will enable this option
1945 and other attacks. !! 2680 automatically on SMP systems. )
>> 2681 Say N if you want to disable CPU hotplug.
1946 2682
1947 This option enables these instructi !! 2683 config SMP_UP
1948 Choosing this option will cause the !! 2684 bool
1949 for each process at exec() time, wi <<
1950 context-switched along with the pro <<
1951 2685
1952 The feature is detected at runtime. !! 2686 config SYS_SUPPORTS_MIPS_CMP
1953 hardware it will not be advertised !! 2687 bool
1954 be enabled. <<
1955 2688
1956 If the feature is present on the bo !! 2689 config SYS_SUPPORTS_MIPS_CPS
1957 the late CPU will be parked. Also, !! 2690 bool
1958 address auth and the late CPU has t <<
1959 but with the feature disabled. On s <<
1960 not be selected. <<
1961 2691
1962 config ARM64_PTR_AUTH_KERNEL !! 2692 config SYS_SUPPORTS_SMP
1963 bool "Use pointer authentication for !! 2693 bool
1964 default y <<
1965 depends on ARM64_PTR_AUTH <<
1966 depends on (CC_HAS_SIGN_RETURN_ADDRES <<
1967 # Modern compilers insert a .note.gnu <<
1968 # which is only understood by binutil <<
1969 depends on LD_IS_LLD || LD_VERSION >= <<
1970 depends on !CC_IS_CLANG || AS_HAS_CFI <<
1971 depends on (!FUNCTION_GRAPH_TRACER || <<
1972 help <<
1973 If the compiler supports the -mbran <<
1974 -msign-return-address flag (e.g. GC <<
1975 will cause the kernel itself to be <<
1976 protection. In this case, and if th <<
1977 support pointer authentication, the <<
1978 disabled with minimal loss of prote <<
1979 2694
1980 This feature works with FUNCTION_GR !! 2695 config NR_CPUS_DEFAULT_4
1981 DYNAMIC_FTRACE_WITH_ARGS is enabled !! 2696 bool
1982 2697
1983 config CC_HAS_BRANCH_PROT_PAC_RET !! 2698 config NR_CPUS_DEFAULT_8
1984 # GCC 9 or later, clang 8 or later !! 2699 bool
1985 def_bool $(cc-option,-mbranch-protect <<
1986 2700
1987 config CC_HAS_SIGN_RETURN_ADDRESS !! 2701 config NR_CPUS_DEFAULT_16
1988 # GCC 7, 8 !! 2702 bool
1989 def_bool $(cc-option,-msign-return-ad <<
1990 2703
1991 config AS_HAS_ARMV8_3 !! 2704 config NR_CPUS_DEFAULT_32
1992 def_bool $(cc-option,-Wa$(comma)-marc !! 2705 bool
1993 2706
1994 config AS_HAS_CFI_NEGATE_RA_STATE !! 2707 config NR_CPUS_DEFAULT_64
1995 def_bool $(as-instr,.cfi_startproc\n. !! 2708 bool
1996 2709
1997 config AS_HAS_LDAPR !! 2710 config NR_CPUS
1998 def_bool $(as-instr,.arch_extension r !! 2711 int "Maximum number of CPUs (2-256)"
>> 2712 range 2 256
>> 2713 depends on SMP
>> 2714 default "4" if NR_CPUS_DEFAULT_4
>> 2715 default "8" if NR_CPUS_DEFAULT_8
>> 2716 default "16" if NR_CPUS_DEFAULT_16
>> 2717 default "32" if NR_CPUS_DEFAULT_32
>> 2718 default "64" if NR_CPUS_DEFAULT_64
>> 2719 help
>> 2720 This allows you to specify the maximum number of CPUs which this
>> 2721 kernel will support. The maximum supported value is 32 for 32-bit
>> 2722 kernel and 64 for 64-bit kernels; the minimum value which makes
>> 2723 sense is 1 for Qemu (useful only for kernel debugging purposes)
>> 2724 and 2 for all others.
>> 2725
>> 2726 This is purely to save memory - each supported CPU adds
>> 2727 approximately eight kilobytes to the kernel image. For best
>> 2728 performance should round up your number of processors to the next
>> 2729 power of two.
1999 2730
2000 endmenu # "ARMv8.3 architectural features" !! 2731 config MIPS_PERF_SHARED_TC_COUNTERS
>> 2732 bool
2001 2733
2002 menu "ARMv8.4 architectural features" !! 2734 #
>> 2735 # Timer Interrupt Frequency Configuration
>> 2736 #
2003 2737
2004 config ARM64_AMU_EXTN !! 2738 choice
2005 bool "Enable support for the Activity !! 2739 prompt "Timer frequency"
2006 default y !! 2740 default HZ_250
2007 help 2741 help
2008 The activity monitors extension is !! 2742 Allows the configuration of the timer frequency.
2009 by the ARMv8.4 CPU architecture. Th <<
2010 of the activity monitors architectu <<
2011 2743
2012 To enable the use of this extension !! 2744 config HZ_24
>> 2745 bool "24 HZ" if SYS_SUPPORTS_24HZ || SYS_SUPPORTS_ARBIT_HZ
2013 2746
2014 Note that for architectural reasons !! 2747 config HZ_48
2015 support when running on CPUs that p !! 2748 bool "48 HZ" if SYS_SUPPORTS_48HZ || SYS_SUPPORTS_ARBIT_HZ
2016 extension. The required support is <<
2017 * Version 1.5 and later of the AR <<
2018 2749
2019 For kernels that have this configur !! 2750 config HZ_100
2020 firmware, you may need to say N her !! 2751 bool "100 HZ" if SYS_SUPPORTS_100HZ || SYS_SUPPORTS_ARBIT_HZ
2021 Otherwise you may experience firmwa <<
2022 accessing the counter registers. Ev <<
2023 symptoms, the values returned by th <<
2024 correctly reflect reality. Most com <<
2025 indicating that the counter is not <<
2026 2752
2027 config AS_HAS_ARMV8_4 !! 2753 config HZ_128
2028 def_bool $(cc-option,-Wa$(comma)-marc !! 2754 bool "128 HZ" if SYS_SUPPORTS_128HZ || SYS_SUPPORTS_ARBIT_HZ
2029 2755
2030 config ARM64_TLB_RANGE !! 2756 config HZ_250
2031 bool "Enable support for tlbi range f !! 2757 bool "250 HZ" if SYS_SUPPORTS_250HZ || SYS_SUPPORTS_ARBIT_HZ
2032 default y <<
2033 depends on AS_HAS_ARMV8_4 <<
2034 help <<
2035 ARMv8.4-TLBI provides TLBI invalida <<
2036 range of input addresses. <<
2037 2758
2038 The feature introduces new assembly !! 2759 config HZ_256
2039 support when binutils >= 2.30. !! 2760 bool "256 HZ" if SYS_SUPPORTS_256HZ || SYS_SUPPORTS_ARBIT_HZ
2040 2761
2041 endmenu # "ARMv8.4 architectural features" !! 2762 config HZ_1000
>> 2763 bool "1000 HZ" if SYS_SUPPORTS_1000HZ || SYS_SUPPORTS_ARBIT_HZ
2042 2764
2043 menu "ARMv8.5 architectural features" !! 2765 config HZ_1024
>> 2766 bool "1024 HZ" if SYS_SUPPORTS_1024HZ || SYS_SUPPORTS_ARBIT_HZ
2044 2767
2045 config AS_HAS_ARMV8_5 !! 2768 endchoice
2046 def_bool $(cc-option,-Wa$(comma)-marc <<
2047 2769
2048 config ARM64_BTI !! 2770 config SYS_SUPPORTS_24HZ
2049 bool "Branch Target Identification su !! 2771 bool
2050 default y <<
2051 help <<
2052 Branch Target Identification (part <<
2053 provides a mechanism to limit the s <<
2054 branch instructions such as BR or B <<
2055 2772
2056 To make use of BTI on CPUs that sup !! 2773 config SYS_SUPPORTS_48HZ
>> 2774 bool
2057 2775
2058 BTI is intended to provide compleme !! 2776 config SYS_SUPPORTS_100HZ
2059 flow integrity protection mechanism !! 2777 bool
2060 authentication mechanism provided a <<
2061 For this reason, it does not make s <<
2062 also enabling support for pointer a <<
2063 enabling this option you should als <<
2064 2778
2065 Userspace binaries must also be spe !! 2779 config SYS_SUPPORTS_128HZ
2066 this mechanism. If you say N here !! 2780 bool
2067 BTI, such binaries can still run, b <<
2068 enforcement of branch destinations. <<
2069 2781
2070 config ARM64_BTI_KERNEL !! 2782 config SYS_SUPPORTS_250HZ
2071 bool "Use Branch Target Identificatio !! 2783 bool
2072 default y <<
2073 depends on ARM64_BTI <<
2074 depends on ARM64_PTR_AUTH_KERNEL <<
2075 depends on CC_HAS_BRANCH_PROT_PAC_RET <<
2076 # https://gcc.gnu.org/bugzilla/show_b <<
2077 depends on !CC_IS_GCC || GCC_VERSION <<
2078 # https://gcc.gnu.org/bugzilla/show_b <<
2079 depends on !CC_IS_GCC <<
2080 depends on (!FUNCTION_GRAPH_TRACER || <<
2081 help <<
2082 Build the kernel with Branch Target <<
2083 and enable enforcement of this for <<
2084 is enabled and the system supports <<
2085 modular code must have BTI enabled. <<
2086 2784
2087 config CC_HAS_BRANCH_PROT_PAC_RET_BTI !! 2785 config SYS_SUPPORTS_256HZ
2088 # GCC 9 or later, clang 8 or later !! 2786 bool
2089 def_bool $(cc-option,-mbranch-protect <<
2090 2787
2091 config ARM64_E0PD !! 2788 config SYS_SUPPORTS_1000HZ
2092 bool "Enable support for E0PD" !! 2789 bool
2093 default y <<
2094 help <<
2095 E0PD (part of the ARMv8.5 extension <<
2096 that EL0 accesses made via TTBR1 al <<
2097 providing similar benefits to KASLR <<
2098 with lower overhead and without dis <<
2099 kernel memory such as SPE. <<
2100 2790
2101 This option enables E0PD for TTBR1 !! 2791 config SYS_SUPPORTS_1024HZ
>> 2792 bool
2102 2793
2103 config ARM64_AS_HAS_MTE !! 2794 config SYS_SUPPORTS_ARBIT_HZ
2104 # Initial support for MTE went in bin !! 2795 bool
2105 # ".arch armv8.5-a+memtag" below. How !! 2796 default y if !SYS_SUPPORTS_24HZ && \
2106 # as a late addition to the final arc !! 2797 !SYS_SUPPORTS_48HZ && \
2107 # is only supported in the newer 2.32 !! 2798 !SYS_SUPPORTS_100HZ && \
2108 # versions, hence the extra "stgm" in !! 2799 !SYS_SUPPORTS_128HZ && \
2109 def_bool $(as-instr,.arch armv8.5-a+m !! 2800 !SYS_SUPPORTS_250HZ && \
>> 2801 !SYS_SUPPORTS_256HZ && \
>> 2802 !SYS_SUPPORTS_1000HZ && \
>> 2803 !SYS_SUPPORTS_1024HZ
2110 2804
2111 config ARM64_MTE !! 2805 config HZ
2112 bool "Memory Tagging Extension suppor !! 2806 int
2113 default y !! 2807 default 24 if HZ_24
2114 depends on ARM64_AS_HAS_MTE && ARM64_ !! 2808 default 48 if HZ_48
2115 depends on AS_HAS_ARMV8_5 !! 2809 default 100 if HZ_100
2116 depends on AS_HAS_LSE_ATOMICS !! 2810 default 128 if HZ_128
2117 # Required for tag checking in the ua !! 2811 default 250 if HZ_250
2118 depends on ARM64_PAN !! 2812 default 256 if HZ_256
2119 select ARCH_HAS_SUBPAGE_FAULTS !! 2813 default 1000 if HZ_1000
2120 select ARCH_USES_HIGH_VMA_FLAGS !! 2814 default 1024 if HZ_1024
2121 select ARCH_USES_PG_ARCH_2 !! 2815
2122 select ARCH_USES_PG_ARCH_3 !! 2816 config SCHED_HRTICK
2123 help !! 2817 def_bool HIGH_RES_TIMERS
2124 Memory Tagging (part of the ARMv8.5 !! 2818
2125 architectural support for run-time, !! 2819 source "kernel/Kconfig.preempt"
2126 various classes of memory error to !! 2820
2127 to eliminate vulnerabilities arisin !! 2821 config KEXEC
2128 languages. !! 2822 bool "Kexec system call"
>> 2823 select KEXEC_CORE
>> 2824 help
>> 2825 kexec is a system call that implements the ability to shutdown your
>> 2826 current kernel, and to start another kernel. It is like a reboot
>> 2827 but it is independent of the system firmware. And like a reboot
>> 2828 you can start any kernel with it, not just Linux.
>> 2829
>> 2830 The name comes from the similarity to the exec system call.
>> 2831
>> 2832 It is an ongoing process to be certain the hardware in a machine
>> 2833 is properly shutdown, so do not be surprised if this code does not
>> 2834 initially work for you. As of this writing the exact hardware
>> 2835 interface is strongly in flux, so no good recommendation can be
>> 2836 made.
>> 2837
>> 2838 config CRASH_DUMP
>> 2839 bool "Kernel crash dumps"
>> 2840 help
>> 2841 Generate crash dump after being started by kexec.
>> 2842 This should be normally only set in special crash dump kernels
>> 2843 which are loaded in the main kernel with kexec-tools into
>> 2844 a specially reserved region and then later executed after
>> 2845 a crash by kdump/kexec. The crash dump kernel must be compiled
>> 2846 to a memory address not used by the main kernel or firmware using
>> 2847 PHYSICAL_START.
>> 2848
>> 2849 config PHYSICAL_START
>> 2850 hex "Physical address where the kernel is loaded"
>> 2851 default "0xffffffff84000000" if 64BIT
>> 2852 default "0x84000000" if 32BIT
>> 2853 depends on CRASH_DUMP
>> 2854 help
>> 2855 This gives the CKSEG0 or KSEG0 address where the kernel is loaded.
>> 2856 If you plan to use kernel for capturing the crash dump change
>> 2857 this value to start of the reserved region (the "X" value as
>> 2858 specified in the "crashkernel=YM@XM" command line boot parameter
>> 2859 passed to the panic-ed kernel).
>> 2860
>> 2861 config SECCOMP
>> 2862 bool "Enable seccomp to safely compute untrusted bytecode"
>> 2863 depends on PROC_FS
>> 2864 default y
>> 2865 help
>> 2866 This kernel feature is useful for number crunching applications
>> 2867 that may need to compute untrusted bytecode during their
>> 2868 execution. By using pipes or other transports made available to
>> 2869 the process as file descriptors supporting the read/write
>> 2870 syscalls, it's possible to isolate those applications in
>> 2871 their own address space using seccomp. Once seccomp is
>> 2872 enabled via /proc/<pid>/seccomp, it cannot be disabled
>> 2873 and the task is only allowed to execute a few safe syscalls
>> 2874 defined by each seccomp mode.
>> 2875
>> 2876 If unsure, say Y. Only embedded should say N here.
>> 2877
>> 2878 config MIPS_O32_FP64_SUPPORT
>> 2879 bool "Support for O32 binaries using 64-bit FP"
>> 2880 depends on 32BIT || MIPS32_O32
>> 2881 help
>> 2882 When this is enabled, the kernel will support use of 64-bit floating
>> 2883 point registers with binaries using the O32 ABI along with the
>> 2884 EF_MIPS_FP64 ELF header flag (typically built with -mfp64). On
>> 2885 32-bit MIPS systems this support is at the cost of increasing the
>> 2886 size and complexity of the compiled FPU emulator. Thus if you are
>> 2887 running a MIPS32 system and know that none of your userland binaries
>> 2888 will require 64-bit floating point, you may wish to reduce the size
>> 2889 of your kernel & potentially improve FP emulation performance by
>> 2890 saying N here.
>> 2891
>> 2892 Although binutils currently supports use of this flag the details
>> 2893 concerning its effect upon the O32 ABI in userland are still being
>> 2894 worked on. In order to avoid userland becoming dependant upon current
>> 2895 behaviour before the details have been finalised, this option should
>> 2896 be considered experimental and only enabled by those working upon
>> 2897 said details.
2129 2898
2130 This option enables the support for !! 2899 If unsure, say N.
2131 Extension at EL0 (i.e. for userspac <<
2132 2900
2133 Selecting this option allows the fe !! 2901 config USE_OF
2134 runtime. Any secondary CPU not impl !! 2902 bool
2135 not be allowed a late bring-up. !! 2903 select OF
>> 2904 select OF_EARLY_FLATTREE
>> 2905 select IRQ_DOMAIN
2136 2906
2137 Userspace binaries that want to use !! 2907 config BUILTIN_DTB
2138 explicitly opt in. The mechanism fo !! 2908 bool
2139 described in: <<
2140 2909
2141 Documentation/arch/arm64/memory-tag !! 2910 choice
>> 2911 prompt "Kernel appended dtb support" if USE_OF
>> 2912 default MIPS_NO_APPENDED_DTB
2142 2913
2143 endmenu # "ARMv8.5 architectural features" !! 2914 config MIPS_NO_APPENDED_DTB
>> 2915 bool "None"
>> 2916 help
>> 2917 Do not enable appended dtb support.
>> 2918
>> 2919 config MIPS_ELF_APPENDED_DTB
>> 2920 bool "vmlinux"
>> 2921 help
>> 2922 With this option, the boot code will look for a device tree binary
>> 2923 DTB) included in the vmlinux ELF section .appended_dtb. By default
>> 2924 it is empty and the DTB can be appended using binutils command
>> 2925 objcopy:
>> 2926
>> 2927 objcopy --update-section .appended_dtb=<filename>.dtb vmlinux
>> 2928
>> 2929 This is meant as a backward compatiblity convenience for those
>> 2930 systems with a bootloader that can't be upgraded to accommodate
>> 2931 the documented boot protocol using a device tree.
>> 2932
>> 2933 config MIPS_RAW_APPENDED_DTB
>> 2934 bool "vmlinux.bin or vmlinuz.bin"
>> 2935 help
>> 2936 With this option, the boot code will look for a device tree binary
>> 2937 DTB) appended to raw vmlinux.bin or vmlinuz.bin.
>> 2938 (e.g. cat vmlinux.bin <filename>.dtb > vmlinux_w_dtb).
>> 2939
>> 2940 This is meant as a backward compatibility convenience for those
>> 2941 systems with a bootloader that can't be upgraded to accommodate
>> 2942 the documented boot protocol using a device tree.
>> 2943
>> 2944 Beware that there is very little in terms of protection against
>> 2945 this option being confused by leftover garbage in memory that might
>> 2946 look like a DTB header after a reboot if no actual DTB is appended
>> 2947 to vmlinux.bin. Do not leave this option active in a production kernel
>> 2948 if you don't intend to always append a DTB.
>> 2949 endchoice
2144 2950
2145 menu "ARMv8.7 architectural features" !! 2951 choice
>> 2952 prompt "Kernel command line type" if !CMDLINE_OVERRIDE
>> 2953 default MIPS_CMDLINE_FROM_DTB if USE_OF && !ATH79 && !MACH_INGENIC && \
>> 2954 !MIPS_MALTA && \
>> 2955 !CAVIUM_OCTEON_SOC
>> 2956 default MIPS_CMDLINE_FROM_BOOTLOADER
>> 2957
>> 2958 config MIPS_CMDLINE_FROM_DTB
>> 2959 depends on USE_OF
>> 2960 bool "Dtb kernel arguments if available"
>> 2961
>> 2962 config MIPS_CMDLINE_DTB_EXTEND
>> 2963 depends on USE_OF
>> 2964 bool "Extend dtb kernel arguments with bootloader arguments"
>> 2965
>> 2966 config MIPS_CMDLINE_FROM_BOOTLOADER
>> 2967 bool "Bootloader kernel arguments if available"
>> 2968
>> 2969 config MIPS_CMDLINE_BUILTIN_EXTEND
>> 2970 depends on CMDLINE_BOOL
>> 2971 bool "Extend builtin kernel arguments with bootloader arguments"
>> 2972 endchoice
2146 2973
2147 config ARM64_EPAN !! 2974 endmenu
2148 bool "Enable support for Enhanced Pri <<
2149 default y <<
2150 depends on ARM64_PAN <<
2151 help <<
2152 Enhanced Privileged Access Never (E <<
2153 Access Never to be used with Execut <<
2154 2975
2155 The feature is detected at runtime, !! 2976 config LOCKDEP_SUPPORT
2156 if the cpu does not implement the f !! 2977 bool
2157 endmenu # "ARMv8.7 architectural features" !! 2978 default y
2158 2979
2159 menu "ARMv8.9 architectural features" !! 2980 config STACKTRACE_SUPPORT
>> 2981 bool
>> 2982 default y
2160 2983
2161 config ARM64_POE !! 2984 config HAVE_LATENCYTOP_SUPPORT
2162 prompt "Permission Overlay Extension" !! 2985 bool
2163 def_bool y !! 2986 default y
2164 select ARCH_USES_HIGH_VMA_FLAGS <<
2165 select ARCH_HAS_PKEYS <<
2166 help <<
2167 The Permission Overlay Extension is <<
2168 Protection Keys. Memory Protection <<
2169 enforcing page-based protections, b <<
2170 of the page tables when an applicat <<
2171 2987
2172 For details, see Documentation/core !! 2988 config PGTABLE_LEVELS
>> 2989 int
>> 2990 default 3 if 64BIT && !PAGE_SIZE_64KB
>> 2991 default 2
2173 2992
2174 If unsure, say y. !! 2993 source "init/Kconfig"
2175 2994
2176 config ARCH_PKEY_BITS !! 2995 source "kernel/Kconfig.freezer"
2177 int <<
2178 default 3 <<
2179 2996
2180 endmenu # "ARMv8.9 architectural features" !! 2997 menu "Bus options (PCI, PCMCIA, EISA, ISA, TC)"
2181 2998
2182 config ARM64_SVE !! 2999 config HW_HAS_EISA
2183 bool "ARM Scalable Vector Extension s !! 3000 bool
2184 default y !! 3001 config HW_HAS_PCI
2185 help !! 3002 bool
2186 The Scalable Vector Extension (SVE) <<
2187 execution state which complements a <<
2188 of the base architecture to support <<
2189 additional vectorisation opportunit <<
2190 3003
2191 To enable use of this extension on !! 3004 config PCI
>> 3005 bool "Support for PCI controller"
>> 3006 depends on HW_HAS_PCI
>> 3007 select PCI_DOMAINS
>> 3008 help
>> 3009 Find out whether you have a PCI motherboard. PCI is the name of a
>> 3010 bus system, i.e. the way the CPU talks to the other stuff inside
>> 3011 your box. Other bus systems are ISA, EISA, or VESA. If you have PCI,
>> 3012 say Y, otherwise N.
>> 3013
>> 3014 config HT_PCI
>> 3015 bool "Support for HT-linked PCI"
>> 3016 default y
>> 3017 depends on CPU_LOONGSON3
>> 3018 select PCI
>> 3019 select PCI_DOMAINS
>> 3020 help
>> 3021 Loongson family machines use Hyper-Transport bus for inter-core
>> 3022 connection and device connection. The PCI bus is a subordinate
>> 3023 linked at HT. Choose Y for Loongson-3 based machines.
2192 3024
2193 On CPUs that support the SVE2 exten !! 3025 config PCI_DOMAINS
2194 those too. !! 3026 bool
2195 3027
2196 Note that for architectural reasons !! 3028 config PCI_DOMAINS_GENERIC
2197 support when running on SVE capable !! 3029 bool
2198 is present in: <<
2199 3030
2200 * version 1.5 and later of the AR !! 3031 config PCI_DRIVERS_GENERIC
2201 * the AArch64 boot wrapper since !! 3032 select PCI_DOMAINS_GENERIC if PCI_DOMAINS
2202 ("bootwrapper: SVE: Enable SVE !! 3033 bool
2203 3034
2204 For other firmware implementations, !! 3035 config PCI_DRIVERS_LEGACY
2205 or vendor. !! 3036 def_bool !PCI_DRIVERS_GENERIC
>> 3037 select NO_GENERIC_PCI_IOPORT_MAP
2206 3038
2207 If you need the kernel to boot on S !! 3039 source "drivers/pci/Kconfig"
2208 firmware, you may need to say N her <<
2209 fixed. Otherwise, you may experien <<
2210 booting the kernel. If unsure and <<
2211 symptoms, you should assume that it <<
2212 3040
2213 config ARM64_SME !! 3041 #
2214 bool "ARM Scalable Matrix Extension s !! 3042 # ISA support is now enabled via select. Too many systems still have the one
2215 default y !! 3043 # or other ISA chip on the board that users don't know about so don't expect
2216 depends on ARM64_SVE !! 3044 # users to choose the right thing ...
2217 depends on BROKEN !! 3045 #
2218 help !! 3046 config ISA
2219 The Scalable Matrix Extension (SME) !! 3047 bool
2220 execution state which utilises a su <<
2221 instruction set, together with the <<
2222 register state capable of holding t <<
2223 enable various matrix operations. <<
2224 3048
2225 config ARM64_PSEUDO_NMI !! 3049 config EISA
2226 bool "Support for NMI-like interrupts !! 3050 bool "EISA support"
2227 select ARM_GIC_V3 !! 3051 depends on HW_HAS_EISA
2228 help !! 3052 select ISA
2229 Adds support for mimicking Non-Mask !! 3053 select GENERIC_ISA_DMA
2230 GIC interrupt priority. This suppor !! 3054 ---help---
2231 ARM GIC. !! 3055 The Extended Industry Standard Architecture (EISA) bus was
>> 3056 developed as an open alternative to the IBM MicroChannel bus.
>> 3057
>> 3058 The EISA bus provided some of the features of the IBM MicroChannel
>> 3059 bus while maintaining backward compatibility with cards made for
>> 3060 the older ISA bus. The EISA bus saw limited use between 1988 and
>> 3061 1995 when it was made obsolete by the PCI bus.
>> 3062
>> 3063 Say Y here if you are building a kernel for an EISA-based machine.
>> 3064
>> 3065 Otherwise, say N.
>> 3066
>> 3067 source "drivers/eisa/Kconfig"
>> 3068
>> 3069 config TC
>> 3070 bool "TURBOchannel support"
>> 3071 depends on MACH_DECSTATION
>> 3072 help
>> 3073 TURBOchannel is a DEC (now Compaq (now HP)) bus for Alpha and MIPS
>> 3074 processors. TURBOchannel programming specifications are available
>> 3075 at:
>> 3076 <ftp://ftp.hp.com/pub/alphaserver/archive/triadd/>
>> 3077 and:
>> 3078 <http://www.computer-refuge.org/classiccmp/ftp.digital.com/pub/DEC/TriAdd/>
>> 3079 Linux driver support status is documented at:
>> 3080 <http://www.linux-mips.org/wiki/DECstation>
2232 3081
2233 This high priority configuration fo !! 3082 config MMU
2234 explicitly enabled by setting the k !! 3083 bool
2235 "irqchip.gicv3_pseudo_nmi" to 1. !! 3084 default y
2236 3085
2237 If unsure, say N !! 3086 config I8253
>> 3087 bool
>> 3088 select CLKSRC_I8253
>> 3089 select CLKEVT_I8253
>> 3090 select MIPS_EXTERNAL_TIMER
2238 3091
2239 if ARM64_PSEUDO_NMI !! 3092 config ZONE_DMA
2240 config ARM64_DEBUG_PRIORITY_MASKING !! 3093 bool
2241 bool "Debug interrupt priority maskin <<
2242 help <<
2243 This adds runtime checks to functio <<
2244 interrupts when using priority mask <<
2245 the validity of ICC_PMR_EL1 when ca <<
2246 3094
2247 If unsure, say N !! 3095 config ZONE_DMA32
2248 endif # ARM64_PSEUDO_NMI !! 3096 bool
2249 3097
2250 config RELOCATABLE !! 3098 source "drivers/pcmcia/Kconfig"
2251 bool "Build a relocatable kernel imag <<
2252 select ARCH_HAS_RELR <<
2253 default y <<
2254 help <<
2255 This builds the kernel as a Positio <<
2256 which retains all relocation metada <<
2257 kernel binary at runtime to a diffe <<
2258 address it was linked at. <<
2259 Since AArch64 uses the RELA relocat <<
2260 relocation pass at runtime even if <<
2261 same address it was linked at. <<
2262 3099
2263 config RANDOMIZE_BASE !! 3100 config RAPIDIO
2264 bool "Randomize the address of the ke !! 3101 tristate "RapidIO support"
2265 select RELOCATABLE !! 3102 depends on PCI
>> 3103 default n
2266 help 3104 help
2267 Randomizes the virtual address at w !! 3105 If you say Y here, the kernel will include drivers and
2268 loaded, as a security feature that !! 3106 infrastructure code to support RapidIO interconnect devices.
2269 relying on knowledge of the locatio <<
2270 <<
2271 It is the bootloader's job to provi <<
2272 random u64 value in /chosen/kaslr-s <<
2273 <<
2274 When booting via the UEFI stub, it <<
2275 EFI_RNG_PROTOCOL implementation (if <<
2276 to the kernel proper. In addition, <<
2277 location of the kernel Image as wel <<
2278 3107
2279 If unsure, say N. !! 3108 source "drivers/rapidio/Kconfig"
2280 3109
2281 config RANDOMIZE_MODULE_REGION_FULL !! 3110 endmenu
2282 bool "Randomize the module region ove <<
2283 depends on RANDOMIZE_BASE <<
2284 default y <<
2285 help <<
2286 Randomizes the location of the modu <<
2287 covering the core kernel. This way, <<
2288 to leak information about the locat <<
2289 but it does imply that function cal <<
2290 kernel will need to be resolved via <<
2291 <<
2292 When this option is not set, the mo <<
2293 a limited range that contains the [ <<
2294 core kernel, so branch relocations <<
2295 the region is exhausted. In this pa <<
2296 exhaustion, modules might be able t <<
2297 3111
2298 config CC_HAVE_STACKPROTECTOR_SYSREG !! 3112 menu "Executable file formats"
2299 def_bool $(cc-option,-mstack-protecto <<
2300 3113
2301 config STACKPROTECTOR_PER_TASK !! 3114 source "fs/Kconfig.binfmt"
2302 def_bool y <<
2303 depends on STACKPROTECTOR && CC_HAVE_ <<
2304 3115
2305 config UNWIND_PATCH_PAC_INTO_SCS !! 3116 config TRAD_SIGNALS
2306 bool "Enable shadow call stack dynami !! 3117 bool
2307 # needs Clang with https://github.com <<
2308 depends on CC_IS_CLANG && CLANG_VERSI <<
2309 depends on ARM64_PTR_AUTH_KERNEL && C <<
2310 depends on SHADOW_CALL_STACK <<
2311 select UNWIND_TABLES <<
2312 select DYNAMIC_SCS <<
2313 <<
2314 config ARM64_CONTPTE <<
2315 bool "Contiguous PTE mappings for use <<
2316 depends on TRANSPARENT_HUGEPAGE <<
2317 default y <<
2318 help <<
2319 When enabled, user mappings are con <<
2320 bit, for any mappings that meet the <<
2321 This reduces TLB pressure and impro <<
2322 <<
2323 endmenu # "Kernel Features" <<
2324 <<
2325 menu "Boot options" <<
2326 <<
2327 config ARM64_ACPI_PARKING_PROTOCOL <<
2328 bool "Enable support for the ARM64 AC <<
2329 depends on ACPI <<
2330 help <<
2331 Enable support for the ARM64 ACPI p <<
2332 the kernel will not allow booting t <<
2333 protocol even if the corresponding <<
2334 MADT table. <<
2335 <<
2336 config CMDLINE <<
2337 string "Default kernel command string <<
2338 default "" <<
2339 help <<
2340 Provide a set of default command-li <<
2341 entering them here. As a minimum, y <<
2342 root device (e.g. root=/dev/nfs). <<
2343 3118
2344 choice !! 3119 config MIPS32_COMPAT
2345 prompt "Kernel command line type" !! 3120 bool
2346 depends on CMDLINE != "" <<
2347 default CMDLINE_FROM_BOOTLOADER <<
2348 help <<
2349 Choose how the kernel will handle t <<
2350 command line string. <<
2351 <<
2352 config CMDLINE_FROM_BOOTLOADER <<
2353 bool "Use bootloader kernel arguments <<
2354 help <<
2355 Uses the command-line options passe <<
2356 the boot loader doesn't provide any <<
2357 string provided in CMDLINE will be <<
2358 <<
2359 config CMDLINE_FORCE <<
2360 bool "Always use the default kernel c <<
2361 help <<
2362 Always use the default kernel comma <<
2363 loader passes other arguments to th <<
2364 This is useful if you cannot or don <<
2365 command-line options your boot load <<
2366 3121
2367 endchoice !! 3122 config COMPAT
>> 3123 bool
2368 3124
2369 config EFI_STUB !! 3125 config SYSVIPC_COMPAT
2370 bool 3126 bool
2371 3127
2372 config EFI !! 3128 config MIPS32_O32
2373 bool "UEFI runtime support" !! 3129 bool "Kernel support for o32 binaries"
2374 depends on OF && !CPU_BIG_ENDIAN !! 3130 depends on 64BIT
2375 depends on KERNEL_MODE_NEON !! 3131 select ARCH_WANT_OLD_COMPAT_IPC
2376 select ARCH_SUPPORTS_ACPI !! 3132 select COMPAT
2377 select LIBFDT !! 3133 select MIPS32_COMPAT
2378 select UCS2_STRING !! 3134 select SYSVIPC_COMPAT if SYSVIPC
2379 select EFI_PARAMS_FROM_FDT !! 3135 help
2380 select EFI_RUNTIME_WRAPPERS !! 3136 Select this option if you want to run o32 binaries. These are pure
2381 select EFI_STUB !! 3137 32-bit binaries as used by the 32-bit Linux/MIPS port. Most of
2382 select EFI_GENERIC_STUB !! 3138 existing binaries are in this format.
2383 imply IMA_SECURE_AND_OR_TRUSTED_BOOT <<
2384 default y <<
2385 help <<
2386 This option provides support for ru <<
2387 by UEFI firmware (such as non-volat <<
2388 clock, and platform reset). A UEFI <<
2389 allow the kernel to be booted as an <<
2390 is only useful on systems that have <<
2391 3139
2392 config COMPRESSED_INSTALL !! 3140 If unsure, say Y.
2393 bool "Install compressed image by def <<
2394 help <<
2395 This makes the regular "make instal <<
2396 image we built, not the legacy unco <<
2397 3141
2398 You can check that a compressed ima !! 3142 config MIPS32_N32
2399 "make zinstall" first, and verifyin !! 3143 bool "Kernel support for n32 binaries"
2400 in your environment before making " !! 3144 depends on 64BIT
2401 you. !! 3145 select ARCH_WANT_COMPAT_IPC_PARSE_VERSION
>> 3146 select COMPAT
>> 3147 select MIPS32_COMPAT
>> 3148 select SYSVIPC_COMPAT if SYSVIPC
>> 3149 help
>> 3150 Select this option if you want to run n32 binaries. These are
>> 3151 64-bit binaries using 32-bit quantities for addressing and certain
>> 3152 data that would normally be 64-bit. They are used in special
>> 3153 cases.
2402 3154
2403 config DMI !! 3155 If unsure, say N.
2404 bool "Enable support for SMBIOS (DMI) <<
2405 depends on EFI <<
2406 default y <<
2407 help <<
2408 This enables SMBIOS/DMI feature for <<
2409 3156
2410 This option is only useful on syste !! 3157 config BINFMT_ELF32
2411 However, even with this option, the !! 3158 bool
2412 continue to boot on existing non-UE !! 3159 default y if MIPS32_O32 || MIPS32_N32
>> 3160 select ELFCORE
2413 3161
2414 endmenu # "Boot options" !! 3162 endmenu
2415 3163
2416 menu "Power management options" 3164 menu "Power management options"
2417 3165
2418 source "kernel/power/Kconfig" <<
2419 <<
2420 config ARCH_HIBERNATION_POSSIBLE 3166 config ARCH_HIBERNATION_POSSIBLE
2421 def_bool y 3167 def_bool y
2422 depends on CPU_PM !! 3168 depends on SYS_SUPPORTS_HOTPLUG_CPU || !SMP
2423 <<
2424 config ARCH_HIBERNATION_HEADER <<
2425 def_bool y <<
2426 depends on HIBERNATION <<
2427 3169
2428 config ARCH_SUSPEND_POSSIBLE 3170 config ARCH_SUSPEND_POSSIBLE
2429 def_bool y 3171 def_bool y
>> 3172 depends on SYS_SUPPORTS_HOTPLUG_CPU || !SMP
>> 3173
>> 3174 source "kernel/power/Kconfig"
>> 3175
>> 3176 endmenu
2430 3177
2431 endmenu # "Power management options" !! 3178 config MIPS_EXTERNAL_TIMER
>> 3179 bool
2432 3180
2433 menu "CPU Power Management" 3181 menu "CPU Power Management"
2434 3182
>> 3183 if CPU_SUPPORTS_CPUFREQ && MIPS_EXTERNAL_TIMER
>> 3184 source "drivers/cpufreq/Kconfig"
>> 3185 endif
>> 3186
2435 source "drivers/cpuidle/Kconfig" 3187 source "drivers/cpuidle/Kconfig"
2436 3188
2437 source "drivers/cpufreq/Kconfig" !! 3189 endmenu
>> 3190
>> 3191 source "net/Kconfig"
>> 3192
>> 3193 source "drivers/Kconfig"
>> 3194
>> 3195 source "drivers/firmware/Kconfig"
>> 3196
>> 3197 source "fs/Kconfig"
>> 3198
>> 3199 source "arch/mips/Kconfig.debug"
2438 3200
2439 endmenu # "CPU Power Management" !! 3201 source "security/Kconfig"
2440 3202
2441 source "drivers/acpi/Kconfig" !! 3203 source "crypto/Kconfig"
2442 3204
2443 source "arch/arm64/kvm/Kconfig" !! 3205 source "lib/Kconfig"
2444 3206
>> 3207 source "arch/mips/kvm/Kconfig"
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