1 # SPDX-License-Identifier: GPL-2.0-only !! 1 # SPDX-License-Identifier: GPL-2.0
2 config ARM64 !! 2 config MIPS
3 def_bool y !! 3 bool
4 select ACPI_APMT if ACPI !! 4 default y
5 select ACPI_CCA_REQUIRED if ACPI !! 5 select ARCH_32BIT_OFF_T if !64BIT
6 select ACPI_GENERIC_GSI if ACPI !! 6 select ARCH_BINFMT_ELF_STATE if MIPS_FP_SUPPORT
7 select ACPI_GTDT if ACPI !! 7 select ARCH_CLOCKSOURCE_DATA
8 select ACPI_HOTPLUG_CPU if ACPI_PROCES !! 8 select ARCH_DISCARD_MEMBLOCK
9 select ACPI_IORT if ACPI !! 9 select ARCH_HAS_ELF_RANDOMIZE
10 select ACPI_REDUCED_HARDWARE_ONLY if A <<
11 select ACPI_MCFG if (ACPI && PCI) <<
12 select ACPI_SPCR_TABLE if ACPI <<
13 select ACPI_PPTT if ACPI <<
14 select ARCH_HAS_DEBUG_WX <<
15 select ARCH_BINFMT_ELF_EXTRA_PHDRS <<
16 select ARCH_BINFMT_ELF_STATE <<
17 select ARCH_CORRECT_STACKTRACE_ON_KRET <<
18 select ARCH_ENABLE_HUGEPAGE_MIGRATION <<
19 select ARCH_ENABLE_MEMORY_HOTPLUG <<
20 select ARCH_ENABLE_MEMORY_HOTREMOVE <<
21 select ARCH_ENABLE_SPLIT_PMD_PTLOCK if <<
22 select ARCH_ENABLE_THP_MIGRATION if TR <<
23 select ARCH_HAS_CACHE_LINE_SIZE <<
24 select ARCH_HAS_CURRENT_STACK_POINTER <<
25 select ARCH_HAS_DEBUG_VIRTUAL <<
26 select ARCH_HAS_DEBUG_VM_PGTABLE <<
27 select ARCH_HAS_DMA_OPS if XEN <<
28 select ARCH_HAS_DMA_PREP_COHERENT <<
29 select ARCH_HAS_ACPI_TABLE_UPGRADE if <<
30 select ARCH_HAS_FAST_MULTIPLIER <<
31 select ARCH_HAS_FORTIFY_SOURCE <<
32 select ARCH_HAS_GCOV_PROFILE_ALL <<
33 select ARCH_HAS_GIGANTIC_PAGE <<
34 select ARCH_HAS_KCOV <<
35 select ARCH_HAS_KERNEL_FPU_SUPPORT if <<
36 select ARCH_HAS_KEEPINITRD <<
37 select ARCH_HAS_MEMBARRIER_SYNC_CORE <<
38 select ARCH_HAS_MEM_ENCRYPT <<
39 select ARCH_HAS_NMI_SAFE_THIS_CPU_OPS <<
40 select ARCH_HAS_NON_OVERLAPPING_ADDRES <<
41 select ARCH_HAS_PTE_DEVMAP <<
42 select ARCH_HAS_PTE_SPECIAL <<
43 select ARCH_HAS_HW_PTE_YOUNG <<
44 select ARCH_HAS_SETUP_DMA_OPS <<
45 select ARCH_HAS_SET_DIRECT_MAP <<
46 select ARCH_HAS_SET_MEMORY <<
47 select ARCH_STACKWALK <<
48 select ARCH_HAS_STRICT_KERNEL_RWX <<
49 select ARCH_HAS_STRICT_MODULE_RWX <<
50 select ARCH_HAS_SYNC_DMA_FOR_DEVICE <<
51 select ARCH_HAS_SYNC_DMA_FOR_CPU <<
52 select ARCH_HAS_SYSCALL_WRAPPER <<
53 select ARCH_HAS_TICK_BROADCAST if GENE 10 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
54 select ARCH_HAS_ZONE_DMA_SET if EXPERT !! 11 select ARCH_HAS_UBSAN_SANITIZE_ALL
55 select ARCH_HAVE_ELF_PROT !! 12 select ARCH_SUPPORTS_UPROBES
56 select ARCH_HAVE_NMI_SAFE_CMPXCHG !! 13 select ARCH_USE_BUILTIN_BSWAP
57 select ARCH_HAVE_TRACE_MMIO_ACCESS !! 14 select ARCH_USE_CMPXCHG_LOCKREF if 64BIT
58 select ARCH_INLINE_READ_LOCK if !PREEM <<
59 select ARCH_INLINE_READ_LOCK_BH if !PR <<
60 select ARCH_INLINE_READ_LOCK_IRQ if !P <<
61 select ARCH_INLINE_READ_LOCK_IRQSAVE i <<
62 select ARCH_INLINE_READ_UNLOCK if !PRE <<
63 select ARCH_INLINE_READ_UNLOCK_BH if ! <<
64 select ARCH_INLINE_READ_UNLOCK_IRQ if <<
65 select ARCH_INLINE_READ_UNLOCK_IRQREST <<
66 select ARCH_INLINE_WRITE_LOCK if !PREE <<
67 select ARCH_INLINE_WRITE_LOCK_BH if !P <<
68 select ARCH_INLINE_WRITE_LOCK_IRQ if ! <<
69 select ARCH_INLINE_WRITE_LOCK_IRQSAVE <<
70 select ARCH_INLINE_WRITE_UNLOCK if !PR <<
71 select ARCH_INLINE_WRITE_UNLOCK_BH if <<
72 select ARCH_INLINE_WRITE_UNLOCK_IRQ if <<
73 select ARCH_INLINE_WRITE_UNLOCK_IRQRES <<
74 select ARCH_INLINE_SPIN_TRYLOCK if !PR <<
75 select ARCH_INLINE_SPIN_TRYLOCK_BH if <<
76 select ARCH_INLINE_SPIN_LOCK if !PREEM <<
77 select ARCH_INLINE_SPIN_LOCK_BH if !PR <<
78 select ARCH_INLINE_SPIN_LOCK_IRQ if !P <<
79 select ARCH_INLINE_SPIN_LOCK_IRQSAVE i <<
80 select ARCH_INLINE_SPIN_UNLOCK if !PRE <<
81 select ARCH_INLINE_SPIN_UNLOCK_BH if ! <<
82 select ARCH_INLINE_SPIN_UNLOCK_IRQ if <<
83 select ARCH_INLINE_SPIN_UNLOCK_IRQREST <<
84 select ARCH_KEEP_MEMBLOCK <<
85 select ARCH_MHP_MEMMAP_ON_MEMORY_ENABL <<
86 select ARCH_USE_CMPXCHG_LOCKREF <<
87 select ARCH_USE_GNU_PROPERTY <<
88 select ARCH_USE_MEMTEST <<
89 select ARCH_USE_QUEUED_RWLOCKS 15 select ARCH_USE_QUEUED_RWLOCKS
90 select ARCH_USE_QUEUED_SPINLOCKS 16 select ARCH_USE_QUEUED_SPINLOCKS
91 select ARCH_USE_SYM_ANNOTATIONS !! 17 select ARCH_WANT_IPC_PARSE_VERSION
92 select ARCH_SUPPORTS_DEBUG_PAGEALLOC !! 18 select BUILDTIME_EXTABLE_SORT
93 select ARCH_SUPPORTS_HUGETLBFS <<
94 select ARCH_SUPPORTS_MEMORY_FAILURE <<
95 select ARCH_SUPPORTS_SHADOW_CALL_STACK <<
96 select ARCH_SUPPORTS_LTO_CLANG if CPU_ <<
97 select ARCH_SUPPORTS_LTO_CLANG_THIN <<
98 select ARCH_SUPPORTS_CFI_CLANG <<
99 select ARCH_SUPPORTS_ATOMIC_RMW <<
100 select ARCH_SUPPORTS_INT128 if CC_HAS_ <<
101 select ARCH_SUPPORTS_NUMA_BALANCING <<
102 select ARCH_SUPPORTS_PAGE_TABLE_CHECK <<
103 select ARCH_SUPPORTS_PER_VMA_LOCK <<
104 select ARCH_SUPPORTS_HUGE_PFNMAP if TR <<
105 select ARCH_SUPPORTS_RT <<
106 select ARCH_WANT_BATCHED_UNMAP_TLB_FLU <<
107 select ARCH_WANT_COMPAT_IPC_PARSE_VERS <<
108 select ARCH_WANT_DEFAULT_BPF_JIT <<
109 select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_ <<
110 select ARCH_WANT_FRAME_POINTERS <<
111 select ARCH_WANT_HUGE_PMD_SHARE if ARM <<
112 select ARCH_WANT_LD_ORPHAN_WARN <<
113 select ARCH_WANTS_EXECMEM_LATE if EXEC <<
114 select ARCH_WANTS_NO_INSTR <<
115 select ARCH_WANTS_THP_SWAP if ARM64_4K <<
116 select ARCH_HAS_UBSAN <<
117 select ARM_AMBA <<
118 select ARM_ARCH_TIMER <<
119 select ARM_GIC <<
120 select AUDIT_ARCH_COMPAT_GENERIC <<
121 select ARM_GIC_V2M if PCI <<
122 select ARM_GIC_V3 <<
123 select ARM_GIC_V3_ITS if PCI <<
124 select ARM_PSCI_FW <<
125 select BUILDTIME_TABLE_SORT <<
126 select CLONE_BACKWARDS 19 select CLONE_BACKWARDS
127 select COMMON_CLK !! 20 select CPU_NO_EFFICIENT_FFS if (TARGET_ISA_REV < 1)
128 select CPU_PM if (SUSPEND || CPU_IDLE) !! 21 select CPU_PM if CPU_IDLE
129 select CPUMASK_OFFSTACK if NR_CPUS > 2 !! 22 select GENERIC_ATOMIC64 if !64BIT
130 select CRC32 !! 23 select GENERIC_CLOCKEVENTS
131 select DCACHE_WORD_ACCESS !! 24 select GENERIC_CMOS_UPDATE
132 select DYNAMIC_FTRACE if FUNCTION_TRAC <<
133 select DMA_BOUNCE_UNALIGNED_KMALLOC <<
134 select DMA_DIRECT_REMAP <<
135 select EDAC_SUPPORT <<
136 select FRAME_POINTER <<
137 select FUNCTION_ALIGNMENT_4B <<
138 select FUNCTION_ALIGNMENT_8B if DYNAMI <<
139 select GENERIC_ALLOCATOR <<
140 select GENERIC_ARCH_TOPOLOGY <<
141 select GENERIC_CLOCKEVENTS_BROADCAST <<
142 select GENERIC_CPU_AUTOPROBE 25 select GENERIC_CPU_AUTOPROBE
143 select GENERIC_CPU_DEVICES !! 26 select GENERIC_IOMAP
144 select GENERIC_CPU_VULNERABILITIES <<
145 select GENERIC_EARLY_IOREMAP <<
146 select GENERIC_IDLE_POLL_SETUP <<
147 select GENERIC_IOREMAP <<
148 select GENERIC_IRQ_IPI <<
149 select GENERIC_IRQ_PROBE 27 select GENERIC_IRQ_PROBE
150 select GENERIC_IRQ_SHOW 28 select GENERIC_IRQ_SHOW
151 select GENERIC_IRQ_SHOW_LEVEL !! 29 select GENERIC_ISA_DMA if EISA
152 select GENERIC_LIB_DEVMEM_IS_ALLOWED !! 30 select GENERIC_LIB_ASHLDI3
153 select GENERIC_PCI_IOMAP !! 31 select GENERIC_LIB_ASHRDI3
154 select GENERIC_PTDUMP !! 32 select GENERIC_LIB_CMPDI2
155 select GENERIC_SCHED_CLOCK !! 33 select GENERIC_LIB_LSHRDI3
>> 34 select GENERIC_LIB_UCMPDI2
>> 35 select GENERIC_SCHED_CLOCK if !CAVIUM_OCTEON_SOC
156 select GENERIC_SMP_IDLE_THREAD 36 select GENERIC_SMP_IDLE_THREAD
157 select GENERIC_TIME_VSYSCALL 37 select GENERIC_TIME_VSYSCALL
158 select GENERIC_GETTIMEOFDAY !! 38 select HANDLE_DOMAIN_IRQ
159 select GENERIC_VDSO_TIME_NS <<
160 select HARDIRQS_SW_RESEND <<
161 select HAS_IOPORT <<
162 select HAVE_MOVE_PMD <<
163 select HAVE_MOVE_PUD <<
164 select HAVE_PCI <<
165 select HAVE_ACPI_APEI if (ACPI && EFI) <<
166 select HAVE_ALIGNED_STRUCT_PAGE <<
167 select HAVE_ARCH_AUDITSYSCALL <<
168 select HAVE_ARCH_BITREVERSE <<
169 select HAVE_ARCH_COMPILER_H 39 select HAVE_ARCH_COMPILER_H
170 select HAVE_ARCH_HUGE_VMALLOC <<
171 select HAVE_ARCH_HUGE_VMAP <<
172 select HAVE_ARCH_JUMP_LABEL 40 select HAVE_ARCH_JUMP_LABEL
173 select HAVE_ARCH_JUMP_LABEL_RELATIVE <<
174 select HAVE_ARCH_KASAN <<
175 select HAVE_ARCH_KASAN_VMALLOC <<
176 select HAVE_ARCH_KASAN_SW_TAGS <<
177 select HAVE_ARCH_KASAN_HW_TAGS if ARM6 <<
178 # Some instrumentation may be unsound, <<
179 select HAVE_ARCH_KCSAN if EXPERT <<
180 select HAVE_ARCH_KFENCE <<
181 select HAVE_ARCH_KGDB 41 select HAVE_ARCH_KGDB
182 select HAVE_ARCH_MMAP_RND_BITS !! 42 select HAVE_ARCH_MMAP_RND_BITS if MMU
183 select HAVE_ARCH_MMAP_RND_COMPAT_BITS !! 43 select HAVE_ARCH_MMAP_RND_COMPAT_BITS if MMU && COMPAT
184 select HAVE_ARCH_PREL32_RELOCATIONS <<
185 select HAVE_ARCH_RANDOMIZE_KSTACK_OFFS <<
186 select HAVE_ARCH_SECCOMP_FILTER 44 select HAVE_ARCH_SECCOMP_FILTER
187 select HAVE_ARCH_STACKLEAK <<
188 select HAVE_ARCH_THREAD_STRUCT_WHITELI <<
189 select HAVE_ARCH_TRACEHOOK 45 select HAVE_ARCH_TRACEHOOK
190 select HAVE_ARCH_TRANSPARENT_HUGEPAGE !! 46 select HAVE_ARCH_TRANSPARENT_HUGEPAGE if CPU_SUPPORTS_HUGEPAGES && 64BIT
191 select HAVE_ARCH_VMAP_STACK !! 47 select HAVE_CBPF_JIT if (!64BIT && !CPU_MICROMIPS)
192 select HAVE_ARM_SMCCC !! 48 select HAVE_EBPF_JIT if (64BIT && !CPU_MICROMIPS)
193 select HAVE_ASM_MODVERSIONS !! 49 select HAVE_CONTEXT_TRACKING
194 select HAVE_EBPF_JIT !! 50 select HAVE_COPY_THREAD_TLS
195 select HAVE_C_RECORDMCOUNT 51 select HAVE_C_RECORDMCOUNT
196 select HAVE_CMPXCHG_DOUBLE <<
197 select HAVE_CMPXCHG_LOCAL <<
198 select HAVE_CONTEXT_TRACKING_USER <<
199 select HAVE_DEBUG_KMEMLEAK 52 select HAVE_DEBUG_KMEMLEAK
>> 53 select HAVE_DEBUG_STACKOVERFLOW
200 select HAVE_DMA_CONTIGUOUS 54 select HAVE_DMA_CONTIGUOUS
201 select HAVE_DYNAMIC_FTRACE 55 select HAVE_DYNAMIC_FTRACE
202 select HAVE_DYNAMIC_FTRACE_WITH_ARGS \ !! 56 select HAVE_EXIT_THREAD
203 if (GCC_SUPPORTS_DYNAMIC_FTRAC <<
204 CLANG_SUPPORTS_DYNAMIC_FTR <<
205 select HAVE_DYNAMIC_FTRACE_WITH_DIRECT <<
206 if DYNAMIC_FTRACE_WITH_ARGS && <<
207 select HAVE_DYNAMIC_FTRACE_WITH_CALL_O <<
208 if (DYNAMIC_FTRACE_WITH_ARGS & <<
209 (CC_IS_CLANG || !CC_OPTIMI <<
210 select FTRACE_MCOUNT_USE_PATCHABLE_FUN <<
211 if DYNAMIC_FTRACE_WITH_ARGS <<
212 select HAVE_SAMPLE_FTRACE_DIRECT <<
213 select HAVE_SAMPLE_FTRACE_DIRECT_MULTI <<
214 select HAVE_EFFICIENT_UNALIGNED_ACCESS <<
215 select HAVE_GUP_FAST <<
216 select HAVE_FTRACE_MCOUNT_RECORD 57 select HAVE_FTRACE_MCOUNT_RECORD
217 select HAVE_FUNCTION_TRACER <<
218 select HAVE_FUNCTION_ERROR_INJECTION <<
219 select HAVE_FUNCTION_GRAPH_TRACER 58 select HAVE_FUNCTION_GRAPH_TRACER
220 select HAVE_FUNCTION_GRAPH_RETVAL !! 59 select HAVE_FUNCTION_TRACER
221 select HAVE_GCC_PLUGINS !! 60 select HAVE_IDE
222 select HAVE_HARDLOCKUP_DETECTOR_PERF i <<
223 HW_PERF_EVENTS && HAVE_PERF_EV <<
224 select HAVE_HW_BREAKPOINT if PERF_EVEN <<
225 select HAVE_IOREMAP_PROT 61 select HAVE_IOREMAP_PROT
>> 62 select HAVE_IRQ_EXIT_ON_IRQ_STACK
226 select HAVE_IRQ_TIME_ACCOUNTING 63 select HAVE_IRQ_TIME_ACCOUNTING
>> 64 select HAVE_KPROBES
>> 65 select HAVE_KRETPROBES
>> 66 select HAVE_LD_DEAD_CODE_DATA_ELIMINATION
>> 67 select HAVE_MEMBLOCK_NODE_MAP
227 select HAVE_MOD_ARCH_SPECIFIC 68 select HAVE_MOD_ARCH_SPECIFIC
228 select HAVE_NMI 69 select HAVE_NMI
>> 70 select HAVE_OPROFILE
229 select HAVE_PERF_EVENTS 71 select HAVE_PERF_EVENTS
230 select HAVE_PERF_EVENTS_NMI if ARM64_P <<
231 select HAVE_PERF_REGS <<
232 select HAVE_PERF_USER_STACK_DUMP <<
233 select HAVE_PREEMPT_DYNAMIC_KEY <<
234 select HAVE_REGS_AND_STACK_ACCESS_API 72 select HAVE_REGS_AND_STACK_ACCESS_API
235 select HAVE_POSIX_CPU_TIMERS_TASK_WORK <<
236 select HAVE_FUNCTION_ARG_ACCESS_API <<
237 select MMU_GATHER_RCU_TABLE_FREE <<
238 select HAVE_RSEQ 73 select HAVE_RSEQ
239 select HAVE_RUST if RUSTC_SUPPORTS_ARM <<
240 select HAVE_STACKPROTECTOR 74 select HAVE_STACKPROTECTOR
241 select HAVE_SYSCALL_TRACEPOINTS 75 select HAVE_SYSCALL_TRACEPOINTS
242 select HAVE_KPROBES !! 76 select HAVE_VIRT_CPU_ACCOUNTING_GEN if 64BIT || !SMP
243 select HAVE_KRETPROBES <<
244 select HAVE_GENERIC_VDSO <<
245 select HOTPLUG_CORE_SYNC_DEAD if HOTPL <<
246 select IRQ_DOMAIN <<
247 select IRQ_FORCED_THREADING 77 select IRQ_FORCED_THREADING
248 select KASAN_VMALLOC if KASAN !! 78 select ISA if EISA
249 select LOCK_MM_AND_FIND_VMA !! 79 select MODULES_USE_ELF_RELA if MODULES && 64BIT
250 select MODULES_USE_ELF_RELA !! 80 select MODULES_USE_ELF_REL if MODULES
251 select NEED_DMA_MAP_STATE !! 81 select PERF_USE_VMALLOC
252 select NEED_SG_DMA_LENGTH !! 82 select RTC_LIB
253 select OF <<
254 select OF_EARLY_FLATTREE <<
255 select PCI_DOMAINS_GENERIC if PCI <<
256 select PCI_ECAM if (ACPI && PCI) <<
257 select PCI_SYSCALL if PCI <<
258 select POWER_RESET <<
259 select POWER_SUPPLY <<
260 select SPARSE_IRQ <<
261 select SWIOTLB <<
262 select SYSCTL_EXCEPTION_TRACE 83 select SYSCTL_EXCEPTION_TRACE
263 select THREAD_INFO_IN_TASK !! 84 select VIRT_TO_BUS
264 select HAVE_ARCH_USERFAULTFD_MINOR if <<
265 select HAVE_ARCH_USERFAULTFD_WP if USE <<
266 select TRACE_IRQFLAGS_SUPPORT <<
267 select TRACE_IRQFLAGS_NMI_SUPPORT <<
268 select HAVE_SOFTIRQ_ON_OWN_STACK <<
269 select USER_STACKTRACE_SUPPORT <<
270 select VDSO_GETRANDOM <<
271 help <<
272 ARM 64-bit (AArch64) Linux support. <<
273 <<
274 config RUSTC_SUPPORTS_ARM64 <<
275 def_bool y <<
276 depends on CPU_LITTLE_ENDIAN <<
277 # Shadow call stack is only supported <<
278 # <<
279 # When using the UNWIND_PATCH_PAC_INTO <<
280 # required due to use of the -Zfixed-x <<
281 # <<
282 # Otherwise, rustc version 1.82+ is re <<
283 # -Zsanitizer=shadow-call-stack flag. <<
284 depends on !SHADOW_CALL_STACK || RUSTC <<
285 <<
286 config CLANG_SUPPORTS_DYNAMIC_FTRACE_WITH_ARGS <<
287 def_bool CC_IS_CLANG <<
288 # https://github.com/ClangBuiltLinux/l <<
289 depends on AS_IS_GNU || (AS_IS_LLVM && <<
290 <<
291 config GCC_SUPPORTS_DYNAMIC_FTRACE_WITH_ARGS <<
292 def_bool CC_IS_GCC <<
293 depends on $(cc-option,-fpatchable-fun <<
294 <<
295 config 64BIT <<
296 def_bool y <<
297 <<
298 config MMU <<
299 def_bool y <<
300 <<
301 config ARM64_CONT_PTE_SHIFT <<
302 int <<
303 default 5 if PAGE_SIZE_64KB <<
304 default 7 if PAGE_SIZE_16KB <<
305 default 4 <<
306 <<
307 config ARM64_CONT_PMD_SHIFT <<
308 int <<
309 default 5 if PAGE_SIZE_64KB <<
310 default 5 if PAGE_SIZE_16KB <<
311 default 4 <<
312 <<
313 config ARCH_MMAP_RND_BITS_MIN <<
314 default 14 if PAGE_SIZE_64KB <<
315 default 16 if PAGE_SIZE_16KB <<
316 default 18 <<
317 <<
318 # max bits determined by the following formula <<
319 # VA_BITS - PAGE_SHIFT - 3 <<
320 config ARCH_MMAP_RND_BITS_MAX <<
321 default 19 if ARM64_VA_BITS=36 <<
322 default 24 if ARM64_VA_BITS=39 <<
323 default 27 if ARM64_VA_BITS=42 <<
324 default 30 if ARM64_VA_BITS=47 <<
325 default 29 if ARM64_VA_BITS=48 && ARM6 <<
326 default 31 if ARM64_VA_BITS=48 && ARM6 <<
327 default 33 if ARM64_VA_BITS=48 <<
328 default 14 if ARM64_64K_PAGES <<
329 default 16 if ARM64_16K_PAGES <<
330 default 18 <<
331 <<
332 config ARCH_MMAP_RND_COMPAT_BITS_MIN <<
333 default 7 if ARM64_64K_PAGES <<
334 default 9 if ARM64_16K_PAGES <<
335 default 11 <<
336 <<
337 config ARCH_MMAP_RND_COMPAT_BITS_MAX <<
338 default 16 <<
339 <<
340 config NO_IOPORT_MAP <<
341 def_bool y if !PCI <<
342 <<
343 config STACKTRACE_SUPPORT <<
344 def_bool y <<
345 85
346 config ILLEGAL_POINTER_VALUE !! 86 menu "Machine selection"
347 hex <<
348 default 0xdead000000000000 <<
349 87
350 config LOCKDEP_SUPPORT !! 88 choice
351 def_bool y !! 89 prompt "System type"
352 !! 90 default MIPS_GENERIC
353 config GENERIC_BUG <<
354 def_bool y <<
355 depends on BUG <<
356 <<
357 config GENERIC_BUG_RELATIVE_POINTERS <<
358 def_bool y <<
359 depends on GENERIC_BUG <<
360 <<
361 config GENERIC_HWEIGHT <<
362 def_bool y <<
363 <<
364 config GENERIC_CSUM <<
365 def_bool y <<
366 <<
367 config GENERIC_CALIBRATE_DELAY <<
368 def_bool y <<
369 91
370 config SMP !! 92 config MIPS_GENERIC
371 def_bool y !! 93 bool "Generic board-agnostic MIPS kernel"
>> 94 select BOOT_RAW
>> 95 select BUILTIN_DTB
>> 96 select CEVT_R4K
>> 97 select CLKSRC_MIPS_GIC
>> 98 select COMMON_CLK
>> 99 select CPU_MIPSR2_IRQ_VI
>> 100 select CPU_MIPSR2_IRQ_EI
>> 101 select CSRC_R4K
>> 102 select DMA_PERDEV_COHERENT
>> 103 select HAVE_PCI
>> 104 select IRQ_MIPS_CPU
>> 105 select LIBFDT
>> 106 select MIPS_AUTO_PFN_OFFSET
>> 107 select MIPS_CPU_SCACHE
>> 108 select MIPS_GIC
>> 109 select MIPS_L1_CACHE_SHIFT_7
>> 110 select NO_EXCEPT_FILL
>> 111 select PCI_DRIVERS_GENERIC
>> 112 select PINCTRL
>> 113 select SMP_UP if SMP
>> 114 select SWAP_IO_SPACE
>> 115 select SYS_HAS_CPU_MIPS32_R1
>> 116 select SYS_HAS_CPU_MIPS32_R2
>> 117 select SYS_HAS_CPU_MIPS32_R6
>> 118 select SYS_HAS_CPU_MIPS64_R1
>> 119 select SYS_HAS_CPU_MIPS64_R2
>> 120 select SYS_HAS_CPU_MIPS64_R6
>> 121 select SYS_SUPPORTS_32BIT_KERNEL
>> 122 select SYS_SUPPORTS_64BIT_KERNEL
>> 123 select SYS_SUPPORTS_BIG_ENDIAN
>> 124 select SYS_SUPPORTS_HIGHMEM
>> 125 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 126 select SYS_SUPPORTS_MICROMIPS
>> 127 select SYS_SUPPORTS_MIPS_CPS
>> 128 select SYS_SUPPORTS_MIPS16
>> 129 select SYS_SUPPORTS_MULTITHREADING
>> 130 select SYS_SUPPORTS_RELOCATABLE
>> 131 select SYS_SUPPORTS_SMARTMIPS
>> 132 select USB_EHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
>> 133 select USB_EHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 134 select USB_OHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
>> 135 select USB_OHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 136 select USB_UHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
>> 137 select USB_UHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 138 select USE_OF
>> 139 select UHI_BOOT
>> 140 help
>> 141 Select this to build a kernel which aims to support multiple boards,
>> 142 generally using a flattened device tree passed from the bootloader
>> 143 using the boot protocol defined in the UHI (Unified Hosting
>> 144 Interface) specification.
>> 145
>> 146 config MIPS_ALCHEMY
>> 147 bool "Alchemy processor based machines"
>> 148 select PHYS_ADDR_T_64BIT
>> 149 select CEVT_R4K
>> 150 select CSRC_R4K
>> 151 select IRQ_MIPS_CPU
>> 152 select DMA_MAYBE_COHERENT # Au1000,1500,1100 aren't, rest is
>> 153 select SYS_HAS_CPU_MIPS32_R1
>> 154 select SYS_SUPPORTS_32BIT_KERNEL
>> 155 select SYS_SUPPORTS_APM_EMULATION
>> 156 select GPIOLIB
>> 157 select SYS_SUPPORTS_ZBOOT
>> 158 select COMMON_CLK
372 159
373 config KERNEL_MODE_NEON !! 160 config AR7
374 def_bool y !! 161 bool "Texas Instruments AR7"
>> 162 select BOOT_ELF32
>> 163 select DMA_NONCOHERENT
>> 164 select CEVT_R4K
>> 165 select CSRC_R4K
>> 166 select IRQ_MIPS_CPU
>> 167 select NO_EXCEPT_FILL
>> 168 select SWAP_IO_SPACE
>> 169 select SYS_HAS_CPU_MIPS32_R1
>> 170 select SYS_HAS_EARLY_PRINTK
>> 171 select SYS_SUPPORTS_32BIT_KERNEL
>> 172 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 173 select SYS_SUPPORTS_MIPS16
>> 174 select SYS_SUPPORTS_ZBOOT_UART16550
>> 175 select GPIOLIB
>> 176 select VLYNQ
>> 177 select HAVE_CLK
>> 178 help
>> 179 Support for the Texas Instruments AR7 System-on-a-Chip
>> 180 family: TNETD7100, 7200 and 7300.
>> 181
>> 182 config ATH25
>> 183 bool "Atheros AR231x/AR531x SoC support"
>> 184 select CEVT_R4K
>> 185 select CSRC_R4K
>> 186 select DMA_NONCOHERENT
>> 187 select IRQ_MIPS_CPU
>> 188 select IRQ_DOMAIN
>> 189 select SYS_HAS_CPU_MIPS32_R1
>> 190 select SYS_SUPPORTS_BIG_ENDIAN
>> 191 select SYS_SUPPORTS_32BIT_KERNEL
>> 192 select SYS_HAS_EARLY_PRINTK
>> 193 help
>> 194 Support for Atheros AR231x and Atheros AR531x based boards
>> 195
>> 196 config ATH79
>> 197 bool "Atheros AR71XX/AR724X/AR913X based boards"
>> 198 select ARCH_HAS_RESET_CONTROLLER
>> 199 select BOOT_RAW
>> 200 select CEVT_R4K
>> 201 select CSRC_R4K
>> 202 select DMA_NONCOHERENT
>> 203 select GPIOLIB
>> 204 select PINCTRL
>> 205 select HAVE_CLK
>> 206 select COMMON_CLK
>> 207 select CLKDEV_LOOKUP
>> 208 select IRQ_MIPS_CPU
>> 209 select SYS_HAS_CPU_MIPS32_R2
>> 210 select SYS_HAS_EARLY_PRINTK
>> 211 select SYS_SUPPORTS_32BIT_KERNEL
>> 212 select SYS_SUPPORTS_BIG_ENDIAN
>> 213 select SYS_SUPPORTS_MIPS16
>> 214 select SYS_SUPPORTS_ZBOOT_UART_PROM
>> 215 select USE_OF
>> 216 select USB_EHCI_ROOT_HUB_TT if USB_EHCI_HCD_PLATFORM
>> 217 help
>> 218 Support for the Atheros AR71XX/AR724X/AR913X SoCs.
>> 219
>> 220 config BMIPS_GENERIC
>> 221 bool "Broadcom Generic BMIPS kernel"
>> 222 select ARCH_HAS_SYNC_DMA_FOR_CPU_ALL
>> 223 select ARCH_HAS_PHYS_TO_DMA
>> 224 select BOOT_RAW
>> 225 select NO_EXCEPT_FILL
>> 226 select USE_OF
>> 227 select CEVT_R4K
>> 228 select CSRC_R4K
>> 229 select SYNC_R4K
>> 230 select COMMON_CLK
>> 231 select BCM6345_L1_IRQ
>> 232 select BCM7038_L1_IRQ
>> 233 select BCM7120_L2_IRQ
>> 234 select BRCMSTB_L2_IRQ
>> 235 select IRQ_MIPS_CPU
>> 236 select DMA_NONCOHERENT
>> 237 select SYS_SUPPORTS_32BIT_KERNEL
>> 238 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 239 select SYS_SUPPORTS_BIG_ENDIAN
>> 240 select SYS_SUPPORTS_HIGHMEM
>> 241 select SYS_HAS_CPU_BMIPS32_3300
>> 242 select SYS_HAS_CPU_BMIPS4350
>> 243 select SYS_HAS_CPU_BMIPS4380
>> 244 select SYS_HAS_CPU_BMIPS5000
>> 245 select SWAP_IO_SPACE
>> 246 select USB_EHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
>> 247 select USB_EHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 248 select USB_OHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
>> 249 select USB_OHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 250 select HARDIRQS_SW_RESEND
>> 251 help
>> 252 Build a generic DT-based kernel image that boots on select
>> 253 BCM33xx cable modem chips, BCM63xx DSL chips, and BCM7xxx set-top
>> 254 box chips. Note that CONFIG_CPU_BIG_ENDIAN/CONFIG_CPU_LITTLE_ENDIAN
>> 255 must be set appropriately for your board.
>> 256
>> 257 config BCM47XX
>> 258 bool "Broadcom BCM47XX based boards"
>> 259 select BOOT_RAW
>> 260 select CEVT_R4K
>> 261 select CSRC_R4K
>> 262 select DMA_NONCOHERENT
>> 263 select HAVE_PCI
>> 264 select IRQ_MIPS_CPU
>> 265 select SYS_HAS_CPU_MIPS32_R1
>> 266 select NO_EXCEPT_FILL
>> 267 select SYS_SUPPORTS_32BIT_KERNEL
>> 268 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 269 select SYS_SUPPORTS_MIPS16
>> 270 select SYS_SUPPORTS_ZBOOT
>> 271 select SYS_HAS_EARLY_PRINTK
>> 272 select USE_GENERIC_EARLY_PRINTK_8250
>> 273 select GPIOLIB
>> 274 select LEDS_GPIO_REGISTER
>> 275 select BCM47XX_NVRAM
>> 276 select BCM47XX_SPROM
>> 277 select BCM47XX_SSB if !BCM47XX_BCMA
>> 278 help
>> 279 Support for BCM47XX based boards
>> 280
>> 281 config BCM63XX
>> 282 bool "Broadcom BCM63XX based boards"
>> 283 select BOOT_RAW
>> 284 select CEVT_R4K
>> 285 select CSRC_R4K
>> 286 select SYNC_R4K
>> 287 select DMA_NONCOHERENT
>> 288 select IRQ_MIPS_CPU
>> 289 select SYS_SUPPORTS_32BIT_KERNEL
>> 290 select SYS_SUPPORTS_BIG_ENDIAN
>> 291 select SYS_HAS_EARLY_PRINTK
>> 292 select SWAP_IO_SPACE
>> 293 select GPIOLIB
>> 294 select HAVE_CLK
>> 295 select MIPS_L1_CACHE_SHIFT_4
>> 296 select CLKDEV_LOOKUP
>> 297 help
>> 298 Support for BCM63XX based boards
>> 299
>> 300 config MIPS_COBALT
>> 301 bool "Cobalt Server"
>> 302 select CEVT_R4K
>> 303 select CSRC_R4K
>> 304 select CEVT_GT641XX
>> 305 select DMA_NONCOHERENT
>> 306 select FORCE_PCI
>> 307 select I8253
>> 308 select I8259
>> 309 select IRQ_MIPS_CPU
>> 310 select IRQ_GT641XX
>> 311 select PCI_GT64XXX_PCI0
>> 312 select SYS_HAS_CPU_NEVADA
>> 313 select SYS_HAS_EARLY_PRINTK
>> 314 select SYS_SUPPORTS_32BIT_KERNEL
>> 315 select SYS_SUPPORTS_64BIT_KERNEL
>> 316 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 317 select USE_GENERIC_EARLY_PRINTK_8250
>> 318
>> 319 config MACH_DECSTATION
>> 320 bool "DECstations"
>> 321 select BOOT_ELF32
>> 322 select CEVT_DS1287
>> 323 select CEVT_R4K if CPU_R4X00
>> 324 select CSRC_IOASIC
>> 325 select CSRC_R4K if CPU_R4X00
>> 326 select CPU_DADDI_WORKAROUNDS if 64BIT
>> 327 select CPU_R4000_WORKAROUNDS if 64BIT
>> 328 select CPU_R4400_WORKAROUNDS if 64BIT
>> 329 select DMA_NONCOHERENT
>> 330 select NO_IOPORT_MAP
>> 331 select IRQ_MIPS_CPU
>> 332 select SYS_HAS_CPU_R3000
>> 333 select SYS_HAS_CPU_R4X00
>> 334 select SYS_SUPPORTS_32BIT_KERNEL
>> 335 select SYS_SUPPORTS_64BIT_KERNEL
>> 336 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 337 select SYS_SUPPORTS_128HZ
>> 338 select SYS_SUPPORTS_256HZ
>> 339 select SYS_SUPPORTS_1024HZ
>> 340 select MIPS_L1_CACHE_SHIFT_4
>> 341 help
>> 342 This enables support for DEC's MIPS based workstations. For details
>> 343 see the Linux/MIPS FAQ on <http://www.linux-mips.org/> and the
>> 344 DECstation porting pages on <http://decstation.unix-ag.org/>.
>> 345
>> 346 If you have one of the following DECstation Models you definitely
>> 347 want to choose R4xx0 for the CPU Type:
>> 348
>> 349 DECstation 5000/50
>> 350 DECstation 5000/150
>> 351 DECstation 5000/260
>> 352 DECsystem 5900/260
>> 353
>> 354 otherwise choose R3000.
>> 355
>> 356 config MACH_JAZZ
>> 357 bool "Jazz family of machines"
>> 358 select ARCH_MIGHT_HAVE_PC_PARPORT
>> 359 select ARCH_MIGHT_HAVE_PC_SERIO
>> 360 select FW_ARC
>> 361 select FW_ARC32
>> 362 select ARCH_MAY_HAVE_PC_FDC
>> 363 select CEVT_R4K
>> 364 select CSRC_R4K
>> 365 select DEFAULT_SGI_PARTITION if CPU_BIG_ENDIAN
>> 366 select GENERIC_ISA_DMA
>> 367 select HAVE_PCSPKR_PLATFORM
>> 368 select IRQ_MIPS_CPU
>> 369 select I8253
>> 370 select I8259
>> 371 select ISA
>> 372 select SYS_HAS_CPU_R4X00
>> 373 select SYS_SUPPORTS_32BIT_KERNEL
>> 374 select SYS_SUPPORTS_64BIT_KERNEL
>> 375 select SYS_SUPPORTS_100HZ
>> 376 help
>> 377 This a family of machines based on the MIPS R4030 chipset which was
>> 378 used by several vendors to build RISC/os and Windows NT workstations.
>> 379 Members include the Acer PICA, MIPS Magnum 4000, MIPS Millennium and
>> 380 Olivetti M700-10 workstations.
>> 381
>> 382 config MACH_INGENIC
>> 383 bool "Ingenic SoC based machines"
>> 384 select SYS_SUPPORTS_32BIT_KERNEL
>> 385 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 386 select SYS_SUPPORTS_ZBOOT_UART16550
>> 387 select DMA_NONCOHERENT
>> 388 select IRQ_MIPS_CPU
>> 389 select PINCTRL
>> 390 select GPIOLIB
>> 391 select COMMON_CLK
>> 392 select GENERIC_IRQ_CHIP
>> 393 select BUILTIN_DTB if MIPS_NO_APPENDED_DTB
>> 394 select USE_OF
>> 395 select LIBFDT
375 396
376 config FIX_EARLYCON_MEM !! 397 config LANTIQ
377 def_bool y !! 398 bool "Lantiq based platforms"
>> 399 select DMA_NONCOHERENT
>> 400 select IRQ_MIPS_CPU
>> 401 select CEVT_R4K
>> 402 select CSRC_R4K
>> 403 select SYS_HAS_CPU_MIPS32_R1
>> 404 select SYS_HAS_CPU_MIPS32_R2
>> 405 select SYS_SUPPORTS_BIG_ENDIAN
>> 406 select SYS_SUPPORTS_32BIT_KERNEL
>> 407 select SYS_SUPPORTS_MIPS16
>> 408 select SYS_SUPPORTS_MULTITHREADING
>> 409 select SYS_SUPPORTS_VPE_LOADER
>> 410 select SYS_HAS_EARLY_PRINTK
>> 411 select GPIOLIB
>> 412 select SWAP_IO_SPACE
>> 413 select BOOT_RAW
>> 414 select CLKDEV_LOOKUP
>> 415 select USE_OF
>> 416 select PINCTRL
>> 417 select PINCTRL_LANTIQ
>> 418 select ARCH_HAS_RESET_CONTROLLER
>> 419 select RESET_CONTROLLER
>> 420
>> 421 config LASAT
>> 422 bool "LASAT Networks platforms"
>> 423 select CEVT_R4K
>> 424 select CRC32
>> 425 select CSRC_R4K
>> 426 select DMA_NONCOHERENT
>> 427 select SYS_HAS_EARLY_PRINTK
>> 428 select HAVE_PCI
>> 429 select IRQ_MIPS_CPU
>> 430 select PCI_GT64XXX_PCI0
>> 431 select MIPS_NILE4
>> 432 select R5000_CPU_SCACHE
>> 433 select SYS_HAS_CPU_R5000
>> 434 select SYS_SUPPORTS_32BIT_KERNEL
>> 435 select SYS_SUPPORTS_64BIT_KERNEL if BROKEN
>> 436 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 437
>> 438 config MACH_LOONGSON32
>> 439 bool "Loongson-1 family of machines"
>> 440 select SYS_SUPPORTS_ZBOOT
>> 441 help
>> 442 This enables support for the Loongson-1 family of machines.
>> 443
>> 444 Loongson-1 is a family of 32-bit MIPS-compatible SoCs developed by
>> 445 the Institute of Computing Technology (ICT), Chinese Academy of
>> 446 Sciences (CAS).
>> 447
>> 448 config MACH_LOONGSON64
>> 449 bool "Loongson-2/3 family of machines"
>> 450 select SYS_SUPPORTS_ZBOOT
>> 451 help
>> 452 This enables the support of Loongson-2/3 family of machines.
>> 453
>> 454 Loongson-2 is a family of single-core CPUs and Loongson-3 is a
>> 455 family of multi-core CPUs. They are both 64-bit general-purpose
>> 456 MIPS-compatible CPUs. Loongson-2/3 are developed by the Institute
>> 457 of Computing Technology (ICT), Chinese Academy of Sciences (CAS)
>> 458 in the People's Republic of China. The chief architect is Professor
>> 459 Weiwu Hu.
>> 460
>> 461 config MACH_PISTACHIO
>> 462 bool "IMG Pistachio SoC based boards"
>> 463 select BOOT_ELF32
>> 464 select BOOT_RAW
>> 465 select CEVT_R4K
>> 466 select CLKSRC_MIPS_GIC
>> 467 select COMMON_CLK
>> 468 select CSRC_R4K
>> 469 select DMA_NONCOHERENT
>> 470 select GPIOLIB
>> 471 select IRQ_MIPS_CPU
>> 472 select LIBFDT
>> 473 select MFD_SYSCON
>> 474 select MIPS_CPU_SCACHE
>> 475 select MIPS_GIC
>> 476 select PINCTRL
>> 477 select REGULATOR
>> 478 select SYS_HAS_CPU_MIPS32_R2
>> 479 select SYS_SUPPORTS_32BIT_KERNEL
>> 480 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 481 select SYS_SUPPORTS_MIPS_CPS
>> 482 select SYS_SUPPORTS_MULTITHREADING
>> 483 select SYS_SUPPORTS_RELOCATABLE
>> 484 select SYS_SUPPORTS_ZBOOT
>> 485 select SYS_HAS_EARLY_PRINTK
>> 486 select USE_GENERIC_EARLY_PRINTK_8250
>> 487 select USE_OF
>> 488 help
>> 489 This enables support for the IMG Pistachio SoC platform.
>> 490
>> 491 config MIPS_MALTA
>> 492 bool "MIPS Malta board"
>> 493 select ARCH_MAY_HAVE_PC_FDC
>> 494 select ARCH_MIGHT_HAVE_PC_PARPORT
>> 495 select ARCH_MIGHT_HAVE_PC_SERIO
>> 496 select BOOT_ELF32
>> 497 select BOOT_RAW
>> 498 select BUILTIN_DTB
>> 499 select CEVT_R4K
>> 500 select CLKSRC_MIPS_GIC
>> 501 select COMMON_CLK
>> 502 select CSRC_R4K
>> 503 select DMA_MAYBE_COHERENT
>> 504 select GENERIC_ISA_DMA
>> 505 select HAVE_PCSPKR_PLATFORM
>> 506 select HAVE_PCI
>> 507 select I8253
>> 508 select I8259
>> 509 select IRQ_MIPS_CPU
>> 510 select LIBFDT
>> 511 select MIPS_BONITO64
>> 512 select MIPS_CPU_SCACHE
>> 513 select MIPS_GIC
>> 514 select MIPS_L1_CACHE_SHIFT_6
>> 515 select MIPS_MSC
>> 516 select PCI_GT64XXX_PCI0
>> 517 select SMP_UP if SMP
>> 518 select SWAP_IO_SPACE
>> 519 select SYS_HAS_CPU_MIPS32_R1
>> 520 select SYS_HAS_CPU_MIPS32_R2
>> 521 select SYS_HAS_CPU_MIPS32_R3_5
>> 522 select SYS_HAS_CPU_MIPS32_R5
>> 523 select SYS_HAS_CPU_MIPS32_R6
>> 524 select SYS_HAS_CPU_MIPS64_R1
>> 525 select SYS_HAS_CPU_MIPS64_R2
>> 526 select SYS_HAS_CPU_MIPS64_R6
>> 527 select SYS_HAS_CPU_NEVADA
>> 528 select SYS_HAS_CPU_RM7000
>> 529 select SYS_SUPPORTS_32BIT_KERNEL
>> 530 select SYS_SUPPORTS_64BIT_KERNEL
>> 531 select SYS_SUPPORTS_BIG_ENDIAN
>> 532 select SYS_SUPPORTS_HIGHMEM
>> 533 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 534 select SYS_SUPPORTS_MICROMIPS
>> 535 select SYS_SUPPORTS_MIPS16
>> 536 select SYS_SUPPORTS_MIPS_CMP
>> 537 select SYS_SUPPORTS_MIPS_CPS
>> 538 select SYS_SUPPORTS_MULTITHREADING
>> 539 select SYS_SUPPORTS_RELOCATABLE
>> 540 select SYS_SUPPORTS_SMARTMIPS
>> 541 select SYS_SUPPORTS_VPE_LOADER
>> 542 select SYS_SUPPORTS_ZBOOT
>> 543 select USE_OF
>> 544 select ZONE_DMA32 if 64BIT
>> 545 help
>> 546 This enables support for the MIPS Technologies Malta evaluation
>> 547 board.
>> 548
>> 549 config MACH_PIC32
>> 550 bool "Microchip PIC32 Family"
>> 551 help
>> 552 This enables support for the Microchip PIC32 family of platforms.
>> 553
>> 554 Microchip PIC32 is a family of general-purpose 32 bit MIPS core
>> 555 microcontrollers.
>> 556
>> 557 config NEC_MARKEINS
>> 558 bool "NEC EMMA2RH Mark-eins board"
>> 559 select SOC_EMMA2RH
>> 560 select HAVE_PCI
>> 561 help
>> 562 This enables support for the NEC Electronics Mark-eins boards.
378 563
379 config PGTABLE_LEVELS !! 564 config MACH_VR41XX
380 int !! 565 bool "NEC VR4100 series based machines"
381 default 2 if ARM64_16K_PAGES && ARM64_ !! 566 select CEVT_R4K
382 default 2 if ARM64_64K_PAGES && ARM64_ !! 567 select CSRC_R4K
383 default 3 if ARM64_64K_PAGES && (ARM64 !! 568 select SYS_HAS_CPU_VR41XX
384 default 3 if ARM64_4K_PAGES && ARM64_V !! 569 select SYS_SUPPORTS_MIPS16
385 default 3 if ARM64_16K_PAGES && ARM64_ !! 570 select GPIOLIB
386 default 4 if ARM64_16K_PAGES && (ARM64 !! 571
387 default 4 if !ARM64_64K_PAGES && ARM64 !! 572 config NXP_STB220
388 default 5 if ARM64_4K_PAGES && ARM64_V !! 573 bool "NXP STB220 board"
>> 574 select SOC_PNX833X
>> 575 help
>> 576 Support for NXP Semiconductors STB220 Development Board.
>> 577
>> 578 config NXP_STB225
>> 579 bool "NXP 225 board"
>> 580 select SOC_PNX833X
>> 581 select SOC_PNX8335
>> 582 help
>> 583 Support for NXP Semiconductors STB225 Development Board.
>> 584
>> 585 config PMC_MSP
>> 586 bool "PMC-Sierra MSP chipsets"
>> 587 select CEVT_R4K
>> 588 select CSRC_R4K
>> 589 select DMA_NONCOHERENT
>> 590 select SWAP_IO_SPACE
>> 591 select NO_EXCEPT_FILL
>> 592 select BOOT_RAW
>> 593 select SYS_HAS_CPU_MIPS32_R1
>> 594 select SYS_HAS_CPU_MIPS32_R2
>> 595 select SYS_SUPPORTS_32BIT_KERNEL
>> 596 select SYS_SUPPORTS_BIG_ENDIAN
>> 597 select SYS_SUPPORTS_MIPS16
>> 598 select IRQ_MIPS_CPU
>> 599 select SERIAL_8250
>> 600 select SERIAL_8250_CONSOLE
>> 601 select USB_EHCI_BIG_ENDIAN_MMIO
>> 602 select USB_EHCI_BIG_ENDIAN_DESC
>> 603 help
>> 604 This adds support for the PMC-Sierra family of Multi-Service
>> 605 Processor System-On-A-Chips. These parts include a number
>> 606 of integrated peripherals, interfaces and DSPs in addition to
>> 607 a variety of MIPS cores.
>> 608
>> 609 config RALINK
>> 610 bool "Ralink based machines"
>> 611 select CEVT_R4K
>> 612 select CSRC_R4K
>> 613 select BOOT_RAW
>> 614 select DMA_NONCOHERENT
>> 615 select IRQ_MIPS_CPU
>> 616 select USE_OF
>> 617 select SYS_HAS_CPU_MIPS32_R1
>> 618 select SYS_HAS_CPU_MIPS32_R2
>> 619 select SYS_SUPPORTS_32BIT_KERNEL
>> 620 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 621 select SYS_SUPPORTS_MIPS16
>> 622 select SYS_HAS_EARLY_PRINTK
>> 623 select CLKDEV_LOOKUP
>> 624 select ARCH_HAS_RESET_CONTROLLER
>> 625 select RESET_CONTROLLER
>> 626
>> 627 config SGI_IP22
>> 628 bool "SGI IP22 (Indy/Indigo2)"
>> 629 select FW_ARC
>> 630 select FW_ARC32
>> 631 select ARCH_MIGHT_HAVE_PC_SERIO
>> 632 select BOOT_ELF32
>> 633 select CEVT_R4K
>> 634 select CSRC_R4K
>> 635 select DEFAULT_SGI_PARTITION
>> 636 select DMA_NONCOHERENT
>> 637 select HAVE_EISA
>> 638 select I8253
>> 639 select I8259
>> 640 select IP22_CPU_SCACHE
>> 641 select IRQ_MIPS_CPU
>> 642 select GENERIC_ISA_DMA_SUPPORT_BROKEN
>> 643 select SGI_HAS_I8042
>> 644 select SGI_HAS_INDYDOG
>> 645 select SGI_HAS_HAL2
>> 646 select SGI_HAS_SEEQ
>> 647 select SGI_HAS_WD93
>> 648 select SGI_HAS_ZILOG
>> 649 select SWAP_IO_SPACE
>> 650 select SYS_HAS_CPU_R4X00
>> 651 select SYS_HAS_CPU_R5000
>> 652 #
>> 653 # Disable EARLY_PRINTK for now since it leads to overwritten prom
>> 654 # memory during early boot on some machines.
>> 655 #
>> 656 # See http://www.linux-mips.org/cgi-bin/mesg.cgi?a=linux-mips&i=20091119164009.GA15038%40deprecation.cyrius.com
>> 657 # for a more details discussion
>> 658 #
>> 659 # select SYS_HAS_EARLY_PRINTK
>> 660 select SYS_SUPPORTS_32BIT_KERNEL
>> 661 select SYS_SUPPORTS_64BIT_KERNEL
>> 662 select SYS_SUPPORTS_BIG_ENDIAN
>> 663 select MIPS_L1_CACHE_SHIFT_7
>> 664 help
>> 665 This are the SGI Indy, Challenge S and Indigo2, as well as certain
>> 666 OEM variants like the Tandem CMN B006S. To compile a Linux kernel
>> 667 that runs on these, say Y here.
>> 668
>> 669 config SGI_IP27
>> 670 bool "SGI IP27 (Origin200/2000)"
>> 671 select ARCH_HAS_PHYS_TO_DMA
>> 672 select FW_ARC
>> 673 select FW_ARC64
>> 674 select BOOT_ELF64
>> 675 select DEFAULT_SGI_PARTITION
>> 676 select SYS_HAS_EARLY_PRINTK
>> 677 select HAVE_PCI
>> 678 select IRQ_MIPS_CPU
>> 679 select NR_CPUS_DEFAULT_64
>> 680 select SYS_HAS_CPU_R10000
>> 681 select SYS_SUPPORTS_64BIT_KERNEL
>> 682 select SYS_SUPPORTS_BIG_ENDIAN
>> 683 select SYS_SUPPORTS_NUMA
>> 684 select SYS_SUPPORTS_SMP
>> 685 select MIPS_L1_CACHE_SHIFT_7
>> 686 help
>> 687 This are the SGI Origin 200, Origin 2000 and Onyx 2 Graphics
>> 688 workstations. To compile a Linux kernel that runs on these, say Y
>> 689 here.
>> 690
>> 691 config SGI_IP28
>> 692 bool "SGI IP28 (Indigo2 R10k)"
>> 693 select FW_ARC
>> 694 select FW_ARC64
>> 695 select ARCH_MIGHT_HAVE_PC_SERIO
>> 696 select BOOT_ELF64
>> 697 select CEVT_R4K
>> 698 select CSRC_R4K
>> 699 select DEFAULT_SGI_PARTITION
>> 700 select DMA_NONCOHERENT
>> 701 select GENERIC_ISA_DMA_SUPPORT_BROKEN
>> 702 select IRQ_MIPS_CPU
>> 703 select HAVE_EISA
>> 704 select I8253
>> 705 select I8259
>> 706 select SGI_HAS_I8042
>> 707 select SGI_HAS_INDYDOG
>> 708 select SGI_HAS_HAL2
>> 709 select SGI_HAS_SEEQ
>> 710 select SGI_HAS_WD93
>> 711 select SGI_HAS_ZILOG
>> 712 select SWAP_IO_SPACE
>> 713 select SYS_HAS_CPU_R10000
>> 714 #
>> 715 # Disable EARLY_PRINTK for now since it leads to overwritten prom
>> 716 # memory during early boot on some machines.
>> 717 #
>> 718 # See http://www.linux-mips.org/cgi-bin/mesg.cgi?a=linux-mips&i=20091119164009.GA15038%40deprecation.cyrius.com
>> 719 # for a more details discussion
>> 720 #
>> 721 # select SYS_HAS_EARLY_PRINTK
>> 722 select SYS_SUPPORTS_64BIT_KERNEL
>> 723 select SYS_SUPPORTS_BIG_ENDIAN
>> 724 select MIPS_L1_CACHE_SHIFT_7
>> 725 help
>> 726 This is the SGI Indigo2 with R10000 processor. To compile a Linux
>> 727 kernel that runs on these, say Y here.
>> 728
>> 729 config SGI_IP32
>> 730 bool "SGI IP32 (O2)"
>> 731 select ARCH_HAS_PHYS_TO_DMA
>> 732 select FW_ARC
>> 733 select FW_ARC32
>> 734 select BOOT_ELF32
>> 735 select CEVT_R4K
>> 736 select CSRC_R4K
>> 737 select DMA_NONCOHERENT
>> 738 select HAVE_PCI
>> 739 select IRQ_MIPS_CPU
>> 740 select R5000_CPU_SCACHE
>> 741 select RM7000_CPU_SCACHE
>> 742 select SYS_HAS_CPU_R5000
>> 743 select SYS_HAS_CPU_R10000 if BROKEN
>> 744 select SYS_HAS_CPU_RM7000
>> 745 select SYS_HAS_CPU_NEVADA
>> 746 select SYS_SUPPORTS_64BIT_KERNEL
>> 747 select SYS_SUPPORTS_BIG_ENDIAN
>> 748 help
>> 749 If you want this kernel to run on SGI O2 workstation, say Y here.
>> 750
>> 751 config SIBYTE_CRHINE
>> 752 bool "Sibyte BCM91120C-CRhine"
>> 753 select BOOT_ELF32
>> 754 select SIBYTE_BCM1120
>> 755 select SWAP_IO_SPACE
>> 756 select SYS_HAS_CPU_SB1
>> 757 select SYS_SUPPORTS_BIG_ENDIAN
>> 758 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 759
>> 760 config SIBYTE_CARMEL
>> 761 bool "Sibyte BCM91120x-Carmel"
>> 762 select BOOT_ELF32
>> 763 select SIBYTE_BCM1120
>> 764 select SWAP_IO_SPACE
>> 765 select SYS_HAS_CPU_SB1
>> 766 select SYS_SUPPORTS_BIG_ENDIAN
>> 767 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 768
>> 769 config SIBYTE_CRHONE
>> 770 bool "Sibyte BCM91125C-CRhone"
>> 771 select BOOT_ELF32
>> 772 select SIBYTE_BCM1125
>> 773 select SWAP_IO_SPACE
>> 774 select SYS_HAS_CPU_SB1
>> 775 select SYS_SUPPORTS_BIG_ENDIAN
>> 776 select SYS_SUPPORTS_HIGHMEM
>> 777 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 778
>> 779 config SIBYTE_RHONE
>> 780 bool "Sibyte BCM91125E-Rhone"
>> 781 select BOOT_ELF32
>> 782 select SIBYTE_BCM1125H
>> 783 select SWAP_IO_SPACE
>> 784 select SYS_HAS_CPU_SB1
>> 785 select SYS_SUPPORTS_BIG_ENDIAN
>> 786 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 787
>> 788 config SIBYTE_SWARM
>> 789 bool "Sibyte BCM91250A-SWARM"
>> 790 select BOOT_ELF32
>> 791 select HAVE_PATA_PLATFORM
>> 792 select SIBYTE_SB1250
>> 793 select SWAP_IO_SPACE
>> 794 select SYS_HAS_CPU_SB1
>> 795 select SYS_SUPPORTS_BIG_ENDIAN
>> 796 select SYS_SUPPORTS_HIGHMEM
>> 797 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 798 select ZONE_DMA32 if 64BIT
>> 799 select SWIOTLB if ARCH_DMA_ADDR_T_64BIT && PCI
>> 800
>> 801 config SIBYTE_LITTLESUR
>> 802 bool "Sibyte BCM91250C2-LittleSur"
>> 803 select BOOT_ELF32
>> 804 select HAVE_PATA_PLATFORM
>> 805 select SIBYTE_SB1250
>> 806 select SWAP_IO_SPACE
>> 807 select SYS_HAS_CPU_SB1
>> 808 select SYS_SUPPORTS_BIG_ENDIAN
>> 809 select SYS_SUPPORTS_HIGHMEM
>> 810 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 811 select ZONE_DMA32 if 64BIT
>> 812
>> 813 config SIBYTE_SENTOSA
>> 814 bool "Sibyte BCM91250E-Sentosa"
>> 815 select BOOT_ELF32
>> 816 select SIBYTE_SB1250
>> 817 select SWAP_IO_SPACE
>> 818 select SYS_HAS_CPU_SB1
>> 819 select SYS_SUPPORTS_BIG_ENDIAN
>> 820 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 821 select SWIOTLB if ARCH_DMA_ADDR_T_64BIT && PCI
>> 822
>> 823 config SIBYTE_BIGSUR
>> 824 bool "Sibyte BCM91480B-BigSur"
>> 825 select BOOT_ELF32
>> 826 select NR_CPUS_DEFAULT_4
>> 827 select SIBYTE_BCM1x80
>> 828 select SWAP_IO_SPACE
>> 829 select SYS_HAS_CPU_SB1
>> 830 select SYS_SUPPORTS_BIG_ENDIAN
>> 831 select SYS_SUPPORTS_HIGHMEM
>> 832 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 833 select ZONE_DMA32 if 64BIT
>> 834 select SWIOTLB if ARCH_DMA_ADDR_T_64BIT && PCI
>> 835
>> 836 config SNI_RM
>> 837 bool "SNI RM200/300/400"
>> 838 select FW_ARC if CPU_LITTLE_ENDIAN
>> 839 select FW_ARC32 if CPU_LITTLE_ENDIAN
>> 840 select FW_SNIPROM if CPU_BIG_ENDIAN
>> 841 select ARCH_MAY_HAVE_PC_FDC
>> 842 select ARCH_MIGHT_HAVE_PC_PARPORT
>> 843 select ARCH_MIGHT_HAVE_PC_SERIO
>> 844 select BOOT_ELF32
>> 845 select CEVT_R4K
>> 846 select CSRC_R4K
>> 847 select DEFAULT_SGI_PARTITION if CPU_BIG_ENDIAN
>> 848 select DMA_NONCOHERENT
>> 849 select GENERIC_ISA_DMA
>> 850 select HAVE_EISA
>> 851 select HAVE_PCSPKR_PLATFORM
>> 852 select HAVE_PCI
>> 853 select IRQ_MIPS_CPU
>> 854 select I8253
>> 855 select I8259
>> 856 select ISA
>> 857 select SWAP_IO_SPACE if CPU_BIG_ENDIAN
>> 858 select SYS_HAS_CPU_R4X00
>> 859 select SYS_HAS_CPU_R5000
>> 860 select SYS_HAS_CPU_R10000
>> 861 select R5000_CPU_SCACHE
>> 862 select SYS_HAS_EARLY_PRINTK
>> 863 select SYS_SUPPORTS_32BIT_KERNEL
>> 864 select SYS_SUPPORTS_64BIT_KERNEL
>> 865 select SYS_SUPPORTS_BIG_ENDIAN
>> 866 select SYS_SUPPORTS_HIGHMEM
>> 867 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 868 help
>> 869 The SNI RM200/300/400 are MIPS-based machines manufactured by
>> 870 Siemens Nixdorf Informationssysteme (SNI), parent company of Pyramid
>> 871 Technology and now in turn merged with Fujitsu. Say Y here to
>> 872 support this machine type.
>> 873
>> 874 config MACH_TX39XX
>> 875 bool "Toshiba TX39 series based machines"
>> 876
>> 877 config MACH_TX49XX
>> 878 bool "Toshiba TX49 series based machines"
>> 879
>> 880 config MIKROTIK_RB532
>> 881 bool "Mikrotik RB532 boards"
>> 882 select CEVT_R4K
>> 883 select CSRC_R4K
>> 884 select DMA_NONCOHERENT
>> 885 select HAVE_PCI
>> 886 select IRQ_MIPS_CPU
>> 887 select SYS_HAS_CPU_MIPS32_R1
>> 888 select SYS_SUPPORTS_32BIT_KERNEL
>> 889 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 890 select SWAP_IO_SPACE
>> 891 select BOOT_RAW
>> 892 select GPIOLIB
>> 893 select MIPS_L1_CACHE_SHIFT_4
>> 894 help
>> 895 Support the Mikrotik(tm) RouterBoard 532 series,
>> 896 based on the IDT RC32434 SoC.
>> 897
>> 898 config CAVIUM_OCTEON_SOC
>> 899 bool "Cavium Networks Octeon SoC based boards"
>> 900 select CEVT_R4K
>> 901 select ARCH_HAS_PHYS_TO_DMA
>> 902 select HAVE_RAPIDIO
>> 903 select PHYS_ADDR_T_64BIT
>> 904 select SYS_SUPPORTS_64BIT_KERNEL
>> 905 select SYS_SUPPORTS_BIG_ENDIAN
>> 906 select EDAC_SUPPORT
>> 907 select EDAC_ATOMIC_SCRUB
>> 908 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 909 select SYS_SUPPORTS_HOTPLUG_CPU if CPU_BIG_ENDIAN
>> 910 select SYS_HAS_EARLY_PRINTK
>> 911 select SYS_HAS_CPU_CAVIUM_OCTEON
>> 912 select HAVE_PCI
>> 913 select ZONE_DMA32
>> 914 select HOLES_IN_ZONE
>> 915 select GPIOLIB
>> 916 select LIBFDT
>> 917 select USE_OF
>> 918 select ARCH_SPARSEMEM_ENABLE
>> 919 select SYS_SUPPORTS_SMP
>> 920 select NR_CPUS_DEFAULT_64
>> 921 select MIPS_NR_CPU_NR_MAP_1024
>> 922 select BUILTIN_DTB
>> 923 select MTD_COMPLEX_MAPPINGS
>> 924 select SWIOTLB
>> 925 select SYS_SUPPORTS_RELOCATABLE
>> 926 help
>> 927 This option supports all of the Octeon reference boards from Cavium
>> 928 Networks. It builds a kernel that dynamically determines the Octeon
>> 929 CPU type and supports all known board reference implementations.
>> 930 Some of the supported boards are:
>> 931 EBT3000
>> 932 EBH3000
>> 933 EBH3100
>> 934 Thunder
>> 935 Kodama
>> 936 Hikari
>> 937 Say Y here for most Octeon reference boards.
>> 938
>> 939 config NLM_XLR_BOARD
>> 940 bool "Netlogic XLR/XLS based systems"
>> 941 select BOOT_ELF32
>> 942 select NLM_COMMON
>> 943 select SYS_HAS_CPU_XLR
>> 944 select SYS_SUPPORTS_SMP
>> 945 select HAVE_PCI
>> 946 select SWAP_IO_SPACE
>> 947 select SYS_SUPPORTS_32BIT_KERNEL
>> 948 select SYS_SUPPORTS_64BIT_KERNEL
>> 949 select PHYS_ADDR_T_64BIT
>> 950 select SYS_SUPPORTS_BIG_ENDIAN
>> 951 select SYS_SUPPORTS_HIGHMEM
>> 952 select NR_CPUS_DEFAULT_32
>> 953 select CEVT_R4K
>> 954 select CSRC_R4K
>> 955 select IRQ_MIPS_CPU
>> 956 select ZONE_DMA32 if 64BIT
>> 957 select SYNC_R4K
>> 958 select SYS_HAS_EARLY_PRINTK
>> 959 select SYS_SUPPORTS_ZBOOT
>> 960 select SYS_SUPPORTS_ZBOOT_UART16550
>> 961 help
>> 962 Support for systems based on Netlogic XLR and XLS processors.
>> 963 Say Y here if you have a XLR or XLS based board.
>> 964
>> 965 config NLM_XLP_BOARD
>> 966 bool "Netlogic XLP based systems"
>> 967 select BOOT_ELF32
>> 968 select NLM_COMMON
>> 969 select SYS_HAS_CPU_XLP
>> 970 select SYS_SUPPORTS_SMP
>> 971 select HAVE_PCI
>> 972 select SYS_SUPPORTS_32BIT_KERNEL
>> 973 select SYS_SUPPORTS_64BIT_KERNEL
>> 974 select PHYS_ADDR_T_64BIT
>> 975 select GPIOLIB
>> 976 select SYS_SUPPORTS_BIG_ENDIAN
>> 977 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 978 select SYS_SUPPORTS_HIGHMEM
>> 979 select NR_CPUS_DEFAULT_32
>> 980 select CEVT_R4K
>> 981 select CSRC_R4K
>> 982 select IRQ_MIPS_CPU
>> 983 select ZONE_DMA32 if 64BIT
>> 984 select SYNC_R4K
>> 985 select SYS_HAS_EARLY_PRINTK
>> 986 select USE_OF
>> 987 select SYS_SUPPORTS_ZBOOT
>> 988 select SYS_SUPPORTS_ZBOOT_UART16550
>> 989 help
>> 990 This board is based on Netlogic XLP Processor.
>> 991 Say Y here if you have a XLP based board.
>> 992
>> 993 config MIPS_PARAVIRT
>> 994 bool "Para-Virtualized guest system"
>> 995 select CEVT_R4K
>> 996 select CSRC_R4K
>> 997 select SYS_SUPPORTS_64BIT_KERNEL
>> 998 select SYS_SUPPORTS_32BIT_KERNEL
>> 999 select SYS_SUPPORTS_BIG_ENDIAN
>> 1000 select SYS_SUPPORTS_SMP
>> 1001 select NR_CPUS_DEFAULT_4
>> 1002 select SYS_HAS_EARLY_PRINTK
>> 1003 select SYS_HAS_CPU_MIPS32_R2
>> 1004 select SYS_HAS_CPU_MIPS64_R2
>> 1005 select SYS_HAS_CPU_CAVIUM_OCTEON
>> 1006 select HAVE_PCI
>> 1007 select SWAP_IO_SPACE
>> 1008 help
>> 1009 This option supports guest running under ????
389 1010
390 config ARCH_SUPPORTS_UPROBES !! 1011 endchoice
391 def_bool y <<
392 1012
393 config ARCH_PROC_KCORE_TEXT !! 1013 source "arch/mips/alchemy/Kconfig"
394 def_bool y !! 1014 source "arch/mips/ath25/Kconfig"
>> 1015 source "arch/mips/ath79/Kconfig"
>> 1016 source "arch/mips/bcm47xx/Kconfig"
>> 1017 source "arch/mips/bcm63xx/Kconfig"
>> 1018 source "arch/mips/bmips/Kconfig"
>> 1019 source "arch/mips/generic/Kconfig"
>> 1020 source "arch/mips/jazz/Kconfig"
>> 1021 source "arch/mips/jz4740/Kconfig"
>> 1022 source "arch/mips/lantiq/Kconfig"
>> 1023 source "arch/mips/lasat/Kconfig"
>> 1024 source "arch/mips/pic32/Kconfig"
>> 1025 source "arch/mips/pistachio/Kconfig"
>> 1026 source "arch/mips/pmcs-msp71xx/Kconfig"
>> 1027 source "arch/mips/ralink/Kconfig"
>> 1028 source "arch/mips/sgi-ip27/Kconfig"
>> 1029 source "arch/mips/sibyte/Kconfig"
>> 1030 source "arch/mips/txx9/Kconfig"
>> 1031 source "arch/mips/vr41xx/Kconfig"
>> 1032 source "arch/mips/cavium-octeon/Kconfig"
>> 1033 source "arch/mips/loongson32/Kconfig"
>> 1034 source "arch/mips/loongson64/Kconfig"
>> 1035 source "arch/mips/netlogic/Kconfig"
>> 1036 source "arch/mips/paravirt/Kconfig"
395 1037
396 config BROKEN_GAS_INST !! 1038 endmenu
397 def_bool !$(as-instr,1:\n.inst 0\n.rep <<
398 1039
399 config BUILTIN_RETURN_ADDRESS_STRIPS_PAC !! 1040 config RWSEM_GENERIC_SPINLOCK
400 bool 1041 bool
401 # Clang's __builtin_return_address() s !! 1042 default y
402 # https://github.com/llvm/llvm-project <<
403 default y if CC_IS_CLANG <<
404 # GCC's __builtin_return_address() str <<
405 # and this was backported to 10.2.0, 9 <<
406 # https://gcc.gnu.org/bugzilla/show_bu <<
407 default y if CC_IS_GCC && (GCC_VERSION <<
408 default y if CC_IS_GCC && (GCC_VERSION <<
409 default y if CC_IS_GCC && (GCC_VERSION <<
410 default y if CC_IS_GCC && (GCC_VERSION <<
411 default n <<
412 <<
413 config KASAN_SHADOW_OFFSET <<
414 hex <<
415 depends on KASAN_GENERIC || KASAN_SW_T <<
416 default 0xdfff800000000000 if (ARM64_V <<
417 default 0xdfffc00000000000 if (ARM64_V <<
418 default 0xdffffe0000000000 if ARM64_VA <<
419 default 0xdfffffc000000000 if ARM64_VA <<
420 default 0xdffffff800000000 if ARM64_VA <<
421 default 0xefff800000000000 if (ARM64_V <<
422 default 0xefffc00000000000 if (ARM64_V <<
423 default 0xeffffe0000000000 if ARM64_VA <<
424 default 0xefffffc000000000 if ARM64_VA <<
425 default 0xeffffff800000000 if ARM64_VA <<
426 default 0xffffffffffffffff <<
427 <<
428 config UNWIND_TABLES <<
429 bool <<
430 <<
431 source "arch/arm64/Kconfig.platforms" <<
432 <<
433 menu "Kernel Features" <<
434 <<
435 menu "ARM errata workarounds via the alternati <<
436 <<
437 config AMPERE_ERRATUM_AC03_CPU_38 <<
438 bool "AmpereOne: AC03_CPU_38: Certain <<
439 default y <<
440 help <<
441 This option adds an alternative code <<
442 errata AC03_CPU_38 and AC04_CPU_10 o <<
443 <<
444 The affected design reports FEAT_HAF <<
445 ID_AA64MMFR1_EL1.HAFDBS, but (V)TCR_ <<
446 as required by the architecture. The <<
447 implementation suffers from an addit <<
448 A/D updates can occur after a PTE ha <<
449 <<
450 The workaround forces KVM to explici <<
451 which avoids enabling unadvertised h <<
452 at stage-2. <<
453 <<
454 If unsure, say Y. <<
455 1043
456 config ARM64_WORKAROUND_CLEAN_CACHE !! 1044 config RWSEM_XCHGADD_ALGORITHM
457 bool 1045 bool
458 1046
459 config ARM64_ERRATUM_826319 !! 1047 config GENERIC_HWEIGHT
460 bool "Cortex-A53: 826319: System might !! 1048 bool
461 default y 1049 default y
462 select ARM64_WORKAROUND_CLEAN_CACHE <<
463 help <<
464 This option adds an alternative code <<
465 erratum 826319 on Cortex-A53 parts u <<
466 AXI master interface and an L2 cache <<
467 <<
468 If a Cortex-A53 uses an AMBA AXI4 AC <<
469 and is unable to accept a certain wr <<
470 not progress on read data presented <<
471 system can deadlock. <<
472 1050
473 The workaround promotes data cache c !! 1051 config GENERIC_CALIBRATE_DELAY
474 data cache clean-and-invalidate. !! 1052 bool
475 Please note that this does not neces <<
476 as it depends on the alternative fra <<
477 the kernel if an affected CPU is det <<
478 <<
479 If unsure, say Y. <<
480 <<
481 config ARM64_ERRATUM_827319 <<
482 bool "Cortex-A53: 827319: Data cache c <<
483 default y 1053 default y
484 select ARM64_WORKAROUND_CLEAN_CACHE <<
485 help <<
486 This option adds an alternative code <<
487 erratum 827319 on Cortex-A53 parts u <<
488 master interface and an L2 cache. <<
489 <<
490 Under certain conditions this erratu <<
491 to occur at the same time as another <<
492 on the AMBA 5 CHI interface, which c <<
493 interconnect reorders the two transa <<
494 <<
495 The workaround promotes data cache c <<
496 data cache clean-and-invalidate. <<
497 Please note that this does not neces <<
498 as it depends on the alternative fra <<
499 the kernel if an affected CPU is det <<
500 1054
501 If unsure, say Y. !! 1055 config SCHED_OMIT_FRAME_POINTER
502 !! 1056 bool
503 config ARM64_ERRATUM_824069 <<
504 bool "Cortex-A53: 824069: Cache line m <<
505 default y 1057 default y
506 select ARM64_WORKAROUND_CLEAN_CACHE <<
507 help <<
508 This option adds an alternative code <<
509 erratum 824069 on Cortex-A53 parts u <<
510 to a coherent interconnect. <<
511 <<
512 If a Cortex-A53 processor is executi <<
513 write instruction at the same time a <<
514 cluster is executing a cache mainten <<
515 address, then this erratum might cau <<
516 incorrectly marked as dirty. <<
517 <<
518 The workaround promotes data cache c <<
519 data cache clean-and-invalidate. <<
520 Please note that this option does no <<
521 workaround, as it depends on the alt <<
522 only patch the kernel if an affected <<
523 1058
524 If unsure, say Y. !! 1059 #
>> 1060 # Select some configuration options automatically based on user selections.
>> 1061 #
>> 1062 config FW_ARC
>> 1063 bool
525 1064
526 config ARM64_ERRATUM_819472 !! 1065 config ARCH_MAY_HAVE_PC_FDC
527 bool "Cortex-A53: 819472: Store exclus !! 1066 bool
528 default y <<
529 select ARM64_WORKAROUND_CLEAN_CACHE <<
530 help <<
531 This option adds an alternative code <<
532 erratum 819472 on Cortex-A53 parts u <<
533 present when it is connected to a co <<
534 <<
535 If the processor is executing a load <<
536 the same time as a processor in anot <<
537 maintenance operation to the same ad <<
538 cause data corruption. <<
539 <<
540 The workaround promotes data cache c <<
541 data cache clean-and-invalidate. <<
542 Please note that this does not neces <<
543 as it depends on the alternative fra <<
544 the kernel if an affected CPU is det <<
545 1067
546 If unsure, say Y. !! 1068 config BOOT_RAW
>> 1069 bool
547 1070
548 config ARM64_ERRATUM_832075 !! 1071 config CEVT_BCM1480
549 bool "Cortex-A57: 832075: possible dea !! 1072 bool
550 default y <<
551 help <<
552 This option adds an alternative code <<
553 erratum 832075 on Cortex-A57 parts u <<
554 1073
555 Affected Cortex-A57 parts might dead !! 1074 config CEVT_DS1287
556 instructions to Write-Back memory ar !! 1075 bool
557 1076
558 The workaround is to promote device !! 1077 config CEVT_GT641XX
559 semantics. !! 1078 bool
560 Please note that this does not neces <<
561 as it depends on the alternative fra <<
562 the kernel if an affected CPU is det <<
563 1079
564 If unsure, say Y. !! 1080 config CEVT_R4K
>> 1081 bool
565 1082
566 config ARM64_ERRATUM_834220 !! 1083 config CEVT_SB1250
567 bool "Cortex-A57: 834220: Stage 2 tran !! 1084 bool
568 depends on KVM <<
569 help <<
570 This option adds an alternative code <<
571 erratum 834220 on Cortex-A57 parts u <<
572 <<
573 Affected Cortex-A57 parts might repo <<
574 fault as the result of a Stage 1 fau <<
575 page boundary when there is a permis <<
576 alignment fault at Stage 1 and a tra <<
577 <<
578 The workaround is to verify that the <<
579 doesn't generate a fault before hand <<
580 Please note that this does not neces <<
581 as it depends on the alternative fra <<
582 the kernel if an affected CPU is det <<
583 1085
584 If unsure, say N. !! 1086 config CEVT_TXX9
>> 1087 bool
585 1088
586 config ARM64_ERRATUM_1742098 !! 1089 config CSRC_BCM1480
587 bool "Cortex-A57/A72: 1742098: ELR rec !! 1090 bool
588 depends on COMPAT <<
589 default y <<
590 help <<
591 This option removes the AES hwcap fo <<
592 workaround erratum 1742098 on Cortex <<
593 <<
594 Affected parts may corrupt the AES s <<
595 taken between a pair of AES instruct <<
596 are only present if the cryptography <<
597 All software should have a fallback <<
598 that don't implement the cryptograph <<
599 1091
600 If unsure, say Y. !! 1092 config CSRC_IOASIC
>> 1093 bool
601 1094
602 config ARM64_ERRATUM_845719 !! 1095 config CSRC_R4K
603 bool "Cortex-A53: 845719: a load might !! 1096 bool
604 depends on COMPAT <<
605 default y <<
606 help <<
607 This option adds an alternative code <<
608 erratum 845719 on Cortex-A53 parts u <<
609 <<
610 When running a compat (AArch32) user <<
611 part, a load at EL0 from a virtual a <<
612 bits of the virtual address used by <<
613 might return incorrect data. <<
614 <<
615 The workaround is to write the conte <<
616 return to a 32-bit task. <<
617 Please note that this does not neces <<
618 as it depends on the alternative fra <<
619 the kernel if an affected CPU is det <<
620 1097
621 If unsure, say Y. !! 1098 config CSRC_SB1250
>> 1099 bool
622 1100
623 config ARM64_ERRATUM_843419 !! 1101 config MIPS_CLOCK_VSYSCALL
624 bool "Cortex-A53: 843419: A load or st !! 1102 def_bool CSRC_R4K || CLKSRC_MIPS_GIC
625 default y <<
626 help <<
627 This option links the kernel with '- <<
628 enables PLT support to replace certa <<
629 cause subsequent memory accesses to <<
630 Cortex-A53 parts up to r0p4. <<
631 1103
632 If unsure, say Y. !! 1104 config GPIO_TXX9
>> 1105 select GPIOLIB
>> 1106 bool
633 1107
634 config ARM64_LD_HAS_FIX_ERRATUM_843419 !! 1108 config FW_CFE
635 def_bool $(ld-option,--fix-cortex-a53- !! 1109 bool
636 1110
637 config ARM64_ERRATUM_1024718 !! 1111 config ARCH_SUPPORTS_UPROBES
638 bool "Cortex-A55: 1024718: Update of D !! 1112 bool
639 default y <<
640 help <<
641 This option adds a workaround for AR <<
642 1113
643 Affected Cortex-A55 cores (all revis !! 1114 config DMA_MAYBE_COHERENT
644 update of the hardware dirty bit whe !! 1115 select ARCH_HAS_DMA_COHERENCE_H
645 without a break-before-make. The wor !! 1116 select DMA_NONCOHERENT
646 of hardware DBM locally on the affec !! 1117 bool
647 this erratum will continue to use th <<
648 1118
649 If unsure, say Y. !! 1119 config DMA_PERDEV_COHERENT
>> 1120 bool
>> 1121 select ARCH_HAS_SETUP_DMA_OPS
>> 1122 select DMA_NONCOHERENT
650 1123
651 config ARM64_ERRATUM_1418040 !! 1124 config DMA_NONCOHERENT
652 bool "Cortex-A76/Neoverse-N1: MRC read !! 1125 bool
653 default y !! 1126 select ARCH_HAS_DMA_MMAP_PGPROT
654 depends on COMPAT !! 1127 select ARCH_HAS_SYNC_DMA_FOR_DEVICE
655 help !! 1128 select NEED_DMA_MAP_STATE
656 This option adds a workaround for AR !! 1129 select ARCH_HAS_DMA_COHERENT_TO_PFN
657 errata 1188873 and 1418040. !! 1130 select DMA_NONCOHERENT_CACHE_SYNC
658 1131
659 Affected Cortex-A76/Neoverse-N1 core !! 1132 config SYS_HAS_EARLY_PRINTK
660 cause register corruption when acces !! 1133 bool
661 from AArch32 userspace. <<
662 1134
663 If unsure, say Y. !! 1135 config SYS_SUPPORTS_HOTPLUG_CPU
>> 1136 bool
664 1137
665 config ARM64_WORKAROUND_SPECULATIVE_AT !! 1138 config MIPS_BONITO64
666 bool 1139 bool
667 1140
668 config ARM64_ERRATUM_1165522 !! 1141 config MIPS_MSC
669 bool "Cortex-A76: 1165522: Speculative !! 1142 bool
670 default y <<
671 select ARM64_WORKAROUND_SPECULATIVE_AT <<
672 help <<
673 This option adds a workaround for AR <<
674 1143
675 Affected Cortex-A76 cores (r0p0, r1p !! 1144 config MIPS_NILE4
676 corrupted TLBs by speculating an AT !! 1145 bool
677 context switch. <<
678 1146
679 If unsure, say Y. !! 1147 config SYNC_R4K
>> 1148 bool
680 1149
681 config ARM64_ERRATUM_1319367 !! 1150 config MIPS_MACHINE
682 bool "Cortex-A57/A72: 1319537: Specula !! 1151 def_bool n
683 default y <<
684 select ARM64_WORKAROUND_SPECULATIVE_AT <<
685 help <<
686 This option adds work arounds for AR <<
687 and A72 erratum 1319367 <<
688 1152
689 Cortex-A57 and A72 cores could end-u !! 1153 config NO_IOPORT_MAP
690 speculating an AT instruction during !! 1154 def_bool n
691 1155
692 If unsure, say Y. !! 1156 config GENERIC_CSUM
>> 1157 bool
>> 1158 default y if !CPU_HAS_LOAD_STORE_LR
693 1159
694 config ARM64_ERRATUM_1530923 !! 1160 config GENERIC_ISA_DMA
695 bool "Cortex-A55: 1530923: Speculative !! 1161 bool
696 default y !! 1162 select ZONE_DMA if GENERIC_ISA_DMA_SUPPORT_BROKEN=n
697 select ARM64_WORKAROUND_SPECULATIVE_AT !! 1163 select ISA_DMA_API
698 help <<
699 This option adds a workaround for AR <<
700 1164
701 Affected Cortex-A55 cores (r0p0, r0p !! 1165 config GENERIC_ISA_DMA_SUPPORT_BROKEN
702 corrupted TLBs by speculating an AT !! 1166 bool
703 context switch. !! 1167 select GENERIC_ISA_DMA
704 1168
705 If unsure, say Y. !! 1169 config ISA_DMA_API
>> 1170 bool
706 1171
707 config ARM64_WORKAROUND_REPEAT_TLBI !! 1172 config HOLES_IN_ZONE
708 bool 1173 bool
709 1174
710 config ARM64_ERRATUM_2441007 !! 1175 config SYS_SUPPORTS_RELOCATABLE
711 bool "Cortex-A55: Completion of affect !! 1176 bool
712 select ARM64_WORKAROUND_REPEAT_TLBI <<
713 help 1177 help
714 This option adds a workaround for AR !! 1178 Selected if the platform supports relocating the kernel.
715 !! 1179 The platform must provide plat_get_fdt() if it selects CONFIG_USE_OF
716 Under very rare circumstances, affec !! 1180 to allow access to command line and entropy sources.
717 may not handle a race between a brea <<
718 CPU, and another CPU accessing the s <<
719 store to a page that has been unmapp <<
720 1181
721 Work around this by adding the affec !! 1182 config MIPS_CBPF_JIT
722 TLB sequences to be done twice. !! 1183 def_bool y
723 !! 1184 depends on BPF_JIT && HAVE_CBPF_JIT
724 If unsure, say N. <<
725 1185
726 config ARM64_ERRATUM_1286807 !! 1186 config MIPS_EBPF_JIT
727 bool "Cortex-A76: Modification of the !! 1187 def_bool y
728 select ARM64_WORKAROUND_REPEAT_TLBI !! 1188 depends on BPF_JIT && HAVE_EBPF_JIT
729 help <<
730 This option adds a workaround for AR <<
731 <<
732 On the affected Cortex-A76 cores (r0 <<
733 address for a cacheable mapping of a <<
734 accessed by a core while another cor <<
735 address to a new physical page using <<
736 break-before-make sequence, then und <<
737 TLBI+DSB completes before a read usi <<
738 invalidated has been observed by oth <<
739 workaround repeats the TLBI+DSB oper <<
740 1189
741 If unsure, say N. <<
742 1190
743 config ARM64_ERRATUM_1463225 !! 1191 #
744 bool "Cortex-A76: Software Step might !! 1192 # Endianness selection. Sufficiently obscure so many users don't know what to
745 default y !! 1193 # answer,so we try hard to limit the available choices. Also the use of a
>> 1194 # choice statement should be more obvious to the user.
>> 1195 #
>> 1196 choice
>> 1197 prompt "Endianness selection"
746 help 1198 help
747 This option adds a workaround for Ar !! 1199 Some MIPS machines can be configured for either little or big endian
>> 1200 byte order. These modes require different kernels and a different
>> 1201 Linux distribution. In general there is one preferred byteorder for a
>> 1202 particular system but some systems are just as commonly used in the
>> 1203 one or the other endianness.
748 1204
749 On the affected Cortex-A76 cores (r0 !! 1205 config CPU_BIG_ENDIAN
750 of a system call instruction (SVC) c !! 1206 bool "Big endian"
751 subsequent interrupts when software !! 1207 depends on SYS_SUPPORTS_BIG_ENDIAN
752 exception handler of the system call <<
753 is enabled or VHE is in use. <<
754 1208
755 Work around the erratum by triggerin !! 1209 config CPU_LITTLE_ENDIAN
756 when handling a system call from a t !! 1210 bool "Little endian"
757 in a VHE configuration of the kernel !! 1211 depends on SYS_SUPPORTS_LITTLE_ENDIAN
758 1212
759 If unsure, say Y. !! 1213 endchoice
760 1214
761 config ARM64_ERRATUM_1542419 !! 1215 config EXPORT_UASM
762 bool "Neoverse-N1: workaround mis-orde !! 1216 bool
763 help <<
764 This option adds a workaround for AR <<
765 1542419. <<
766 1217
767 Affected Neoverse-N1 cores could exe !! 1218 config SYS_SUPPORTS_APM_EMULATION
768 modified by another CPU. The workaro !! 1219 bool
769 counterpart. <<
770 1220
771 Workaround the issue by hiding the D !! 1221 config SYS_SUPPORTS_BIG_ENDIAN
772 forces user-space to perform cache m !! 1222 bool
773 1223
774 If unsure, say N. !! 1224 config SYS_SUPPORTS_LITTLE_ENDIAN
>> 1225 bool
775 1226
776 config ARM64_ERRATUM_1508412 !! 1227 config SYS_SUPPORTS_HUGETLBFS
777 bool "Cortex-A77: 1508412: workaround !! 1228 bool
>> 1229 depends on CPU_SUPPORTS_HUGEPAGES && 64BIT
778 default y 1230 default y
779 help <<
780 This option adds a workaround for Ar <<
781 1231
782 Affected Cortex-A77 cores (r0p0, r1p !! 1232 config MIPS_HUGE_TLB_SUPPORT
783 of a store-exclusive or read of PAR_ !! 1233 def_bool HUGETLB_PAGE || TRANSPARENT_HUGEPAGE
784 non-cacheable memory attributes. The <<
785 counterpart. <<
786 1234
787 KVM guests must also have the workar !! 1235 config IRQ_CPU_RM7K
788 deadlock the system. !! 1236 bool
789 1237
790 Work around the issue by inserting D !! 1238 config IRQ_MSP_SLP
791 register reads and warning KVM users !! 1239 bool
792 to prevent a speculative PAR_EL1 rea <<
793 1240
794 If unsure, say Y. !! 1241 config IRQ_MSP_CIC
>> 1242 bool
795 1243
796 config ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MO !! 1244 config IRQ_TXX9
797 bool 1245 bool
798 1246
799 config ARM64_ERRATUM_2051678 !! 1247 config IRQ_GT641XX
800 bool "Cortex-A510: 2051678: disable Ha !! 1248 bool
801 default y <<
802 help <<
803 This options adds the workaround for <<
804 Affected Cortex-A510 might not respe <<
805 hardware update of the page table's <<
806 is to not enable the feature on affe <<
807 1249
808 If unsure, say Y. !! 1250 config PCI_GT64XXX_PCI0
>> 1251 bool
809 1252
810 config ARM64_ERRATUM_2077057 !! 1253 config NO_EXCEPT_FILL
811 bool "Cortex-A510: 2077057: workaround !! 1254 bool
812 default y <<
813 help <<
814 This option adds the workaround for <<
815 Affected Cortex-A510 may corrupt SPS <<
816 expected, but a Pointer Authenticati <<
817 erratum causes SPSR_EL1 to be copied <<
818 EL1 to cause a return to EL2 with a <<
819 1255
820 This can only happen when EL2 is ste !! 1256 config SOC_EMMA2RH
>> 1257 bool
>> 1258 select CEVT_R4K
>> 1259 select CSRC_R4K
>> 1260 select DMA_NONCOHERENT
>> 1261 select IRQ_MIPS_CPU
>> 1262 select SWAP_IO_SPACE
>> 1263 select SYS_HAS_CPU_R5500
>> 1264 select SYS_SUPPORTS_32BIT_KERNEL
>> 1265 select SYS_SUPPORTS_64BIT_KERNEL
>> 1266 select SYS_SUPPORTS_BIG_ENDIAN
821 1267
822 When these conditions occur, the SPS !! 1268 config SOC_PNX833X
823 previous guest entry, and can be res !! 1269 bool
>> 1270 select CEVT_R4K
>> 1271 select CSRC_R4K
>> 1272 select IRQ_MIPS_CPU
>> 1273 select DMA_NONCOHERENT
>> 1274 select SYS_HAS_CPU_MIPS32_R2
>> 1275 select SYS_SUPPORTS_32BIT_KERNEL
>> 1276 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 1277 select SYS_SUPPORTS_BIG_ENDIAN
>> 1278 select SYS_SUPPORTS_MIPS16
>> 1279 select CPU_MIPSR2_IRQ_VI
824 1280
825 If unsure, say Y. !! 1281 config SOC_PNX8335
>> 1282 bool
>> 1283 select SOC_PNX833X
826 1284
827 config ARM64_ERRATUM_2658417 !! 1285 config MIPS_SPRAM
828 bool "Cortex-A510: 2658417: remove BF1 !! 1286 bool
829 default y <<
830 help <<
831 This option adds the workaround for <<
832 Affected Cortex-A510 (r0p0 to r1p1) <<
833 BFMMLA or VMMLA instructions in rare <<
834 A510 CPUs are using shared neon hard <<
835 discoverable by the kernel, hide the <<
836 user-space should not be using these <<
837 1287
838 If unsure, say Y. !! 1288 config SWAP_IO_SPACE
>> 1289 bool
839 1290
840 config ARM64_ERRATUM_2119858 !! 1291 config SGI_HAS_INDYDOG
841 bool "Cortex-A710/X2: 2119858: workaro !! 1292 bool
842 default y <<
843 depends on CORESIGHT_TRBE <<
844 select ARM64_WORKAROUND_TRBE_OVERWRITE <<
845 help <<
846 This option adds the workaround for <<
847 1293
848 Affected Cortex-A710/X2 cores could !! 1294 config SGI_HAS_HAL2
849 data at the base of the buffer (poin !! 1295 bool
850 the event of a WRAP event. <<
851 1296
852 Work around the issue by always maki !! 1297 config SGI_HAS_SEEQ
853 256 bytes before enabling the buffer !! 1298 bool
854 the buffer with ETM ignore packets u <<
855 1299
856 If unsure, say Y. !! 1300 config SGI_HAS_WD93
>> 1301 bool
857 1302
858 config ARM64_ERRATUM_2139208 !! 1303 config SGI_HAS_ZILOG
859 bool "Neoverse-N2: 2139208: workaround !! 1304 bool
860 default y <<
861 depends on CORESIGHT_TRBE <<
862 select ARM64_WORKAROUND_TRBE_OVERWRITE <<
863 help <<
864 This option adds the workaround for <<
865 1305
866 Affected Neoverse-N2 cores could ove !! 1306 config SGI_HAS_I8042
867 data at the base of the buffer (poin !! 1307 bool
868 the event of a WRAP event. <<
869 1308
870 Work around the issue by always maki !! 1309 config DEFAULT_SGI_PARTITION
871 256 bytes before enabling the buffer !! 1310 bool
872 the buffer with ETM ignore packets u <<
873 1311
874 If unsure, say Y. !! 1312 config FW_ARC32
>> 1313 bool
875 1314
876 config ARM64_WORKAROUND_TSB_FLUSH_FAILURE !! 1315 config FW_SNIPROM
877 bool 1316 bool
878 1317
879 config ARM64_ERRATUM_2054223 !! 1318 config BOOT_ELF32
880 bool "Cortex-A710: 2054223: workaround !! 1319 bool
881 default y <<
882 select ARM64_WORKAROUND_TSB_FLUSH_FAIL <<
883 help <<
884 Enable workaround for ARM Cortex-A71 <<
885 1320
886 Affected cores may fail to flush the !! 1321 config MIPS_L1_CACHE_SHIFT_4
887 the PE is in trace prohibited state. !! 1322 bool
888 of the trace cached. <<
889 1323
890 Workaround is to issue two TSB conse !! 1324 config MIPS_L1_CACHE_SHIFT_5
>> 1325 bool
891 1326
892 If unsure, say Y. !! 1327 config MIPS_L1_CACHE_SHIFT_6
>> 1328 bool
893 1329
894 config ARM64_ERRATUM_2067961 !! 1330 config MIPS_L1_CACHE_SHIFT_7
895 bool "Neoverse-N2: 2067961: workaround !! 1331 bool
896 default y <<
897 select ARM64_WORKAROUND_TSB_FLUSH_FAIL <<
898 help <<
899 Enable workaround for ARM Neoverse-N <<
900 1332
901 Affected cores may fail to flush the !! 1333 config MIPS_L1_CACHE_SHIFT
902 the PE is in trace prohibited state. !! 1334 int
903 of the trace cached. !! 1335 default "7" if MIPS_L1_CACHE_SHIFT_7
>> 1336 default "6" if MIPS_L1_CACHE_SHIFT_6
>> 1337 default "5" if MIPS_L1_CACHE_SHIFT_5
>> 1338 default "4" if MIPS_L1_CACHE_SHIFT_4
>> 1339 default "5"
904 1340
905 Workaround is to issue two TSB conse !! 1341 config HAVE_STD_PC_SERIAL_PORT
>> 1342 bool
906 1343
907 If unsure, say Y. !! 1344 config ARC_CONSOLE
>> 1345 bool "ARC console support"
>> 1346 depends on SGI_IP22 || SGI_IP28 || (SNI_RM && CPU_LITTLE_ENDIAN)
908 1347
909 config ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANG !! 1348 config ARC_MEMORY
910 bool 1349 bool
911 !! 1350 depends on MACH_JAZZ || SNI_RM || SGI_IP32
912 config ARM64_ERRATUM_2253138 <<
913 bool "Neoverse-N2: 2253138: workaround <<
914 depends on CORESIGHT_TRBE <<
915 default y 1351 default y
916 select ARM64_WORKAROUND_TRBE_WRITE_OUT <<
917 help <<
918 This option adds the workaround for <<
919 1352
920 Affected Neoverse-N2 cores might wri !! 1353 config ARC_PROMLIB
921 for TRBE. Under some conditions, the !! 1354 bool
922 virtually addressed page following t !! 1355 depends on MACH_JAZZ || SNI_RM || SGI_IP22 || SGI_IP28 || SGI_IP32
923 (i.e., the TRBLIMITR_EL1.LIMIT), ins <<
924 <<
925 Work around this in the driver by al <<
926 page beyond the TRBLIMITR_EL1.LIMIT, <<
927 <<
928 If unsure, say Y. <<
929 <<
930 config ARM64_ERRATUM_2224489 <<
931 bool "Cortex-A710/X2: 2224489: workaro <<
932 depends on CORESIGHT_TRBE <<
933 default y 1356 default y
934 select ARM64_WORKAROUND_TRBE_WRITE_OUT <<
935 help <<
936 This option adds the workaround for <<
937 1357
938 Affected Cortex-A710/X2 cores might !! 1358 config FW_ARC64
939 for TRBE. Under some conditions, the !! 1359 bool
940 virtually addressed page following t <<
941 (i.e., the TRBLIMITR_EL1.LIMIT), ins <<
942 <<
943 Work around this in the driver by al <<
944 page beyond the TRBLIMITR_EL1.LIMIT, <<
945 <<
946 If unsure, say Y. <<
947 1360
948 config ARM64_ERRATUM_2441009 !! 1361 config BOOT_ELF64
949 bool "Cortex-A510: Completion of affec !! 1362 bool
950 select ARM64_WORKAROUND_REPEAT_TLBI <<
951 help <<
952 This option adds a workaround for AR <<
953 <<
954 Under very rare circumstances, affec <<
955 may not handle a race between a brea <<
956 CPU, and another CPU accessing the s <<
957 store to a page that has been unmapp <<
958 1363
959 Work around this by adding the affec !! 1364 menu "CPU selection"
960 TLB sequences to be done twice. <<
961 1365
962 If unsure, say N. !! 1366 choice
>> 1367 prompt "CPU type"
>> 1368 default CPU_R4X00
963 1369
964 config ARM64_ERRATUM_2064142 !! 1370 config CPU_LOONGSON3
965 bool "Cortex-A510: 2064142: workaround !! 1371 bool "Loongson 3 CPU"
966 depends on CORESIGHT_TRBE !! 1372 depends on SYS_HAS_CPU_LOONGSON3
967 default y !! 1373 select ARCH_HAS_PHYS_TO_DMA
>> 1374 select CPU_SUPPORTS_64BIT_KERNEL
>> 1375 select CPU_SUPPORTS_HIGHMEM
>> 1376 select CPU_SUPPORTS_HUGEPAGES
>> 1377 select CPU_HAS_LOAD_STORE_LR
>> 1378 select WEAK_ORDERING
>> 1379 select WEAK_REORDERING_BEYOND_LLSC
>> 1380 select MIPS_PGD_C0_CONTEXT
>> 1381 select MIPS_L1_CACHE_SHIFT_6
>> 1382 select GPIOLIB
>> 1383 select SWIOTLB
968 help 1384 help
969 This option adds the workaround for !! 1385 The Loongson 3 processor implements the MIPS64R2 instruction
>> 1386 set with many extensions.
970 1387
971 Affected Cortex-A510 core might fail !! 1388 config LOONGSON3_ENHANCEMENT
972 TRBE has been disabled. Under some c !! 1389 bool "New Loongson 3 CPU Enhancements"
973 writes into TRBE registers TRBLIMITR !! 1390 default n
974 and TRBTRG_EL1 will be ignored and w !! 1391 select CPU_MIPSR2
975 !! 1392 select CPU_HAS_PREFETCH
976 Work around this in the driver by ex !! 1393 depends on CPU_LOONGSON3
977 is stopped and before performing a s !! 1394 help
978 registers. !! 1395 New Loongson 3 CPU (since Loongson-3A R2, as opposed to Loongson-3A
>> 1396 R1, Loongson-3B R1 and Loongson-3B R2) has many enhancements, such as
>> 1397 FTLB, L1-VCache, EI/DI/Wait/Prefetch instruction, DSP/DSPv2 ASE, User
>> 1398 Local register, Read-Inhibit/Execute-Inhibit, SFB (Store Fill Buffer),
>> 1399 Fast TLB refill support, etc.
>> 1400
>> 1401 This option enable those enhancements which are not probed at run
>> 1402 time. If you want a generic kernel to run on all Loongson 3 machines,
>> 1403 please say 'N' here. If you want a high-performance kernel to run on
>> 1404 new Loongson 3 machines only, please say 'Y' here.
>> 1405
>> 1406 config CPU_LOONGSON3_WORKAROUNDS
>> 1407 bool "Old Loongson 3 LLSC Workarounds"
>> 1408 default y if SMP
>> 1409 depends on CPU_LOONGSON3
>> 1410 help
>> 1411 Loongson 3 processors have the llsc issues which require workarounds.
>> 1412 Without workarounds the system may hang unexpectedly.
>> 1413
>> 1414 Newer Loongson 3 will fix these issues and no workarounds are needed.
>> 1415 The workarounds have no significant side effect on them but may
>> 1416 decrease the performance of the system so this option should be
>> 1417 disabled unless the kernel is intended to be run on old systems.
>> 1418
>> 1419 If unsure, please say Y.
>> 1420
>> 1421 config CPU_LOONGSON2E
>> 1422 bool "Loongson 2E"
>> 1423 depends on SYS_HAS_CPU_LOONGSON2E
>> 1424 select CPU_LOONGSON2
>> 1425 help
>> 1426 The Loongson 2E processor implements the MIPS III instruction set
>> 1427 with many extensions.
>> 1428
>> 1429 It has an internal FPGA northbridge, which is compatible to
>> 1430 bonito64.
>> 1431
>> 1432 config CPU_LOONGSON2F
>> 1433 bool "Loongson 2F"
>> 1434 depends on SYS_HAS_CPU_LOONGSON2F
>> 1435 select CPU_LOONGSON2
>> 1436 select GPIOLIB
>> 1437 help
>> 1438 The Loongson 2F processor implements the MIPS III instruction set
>> 1439 with many extensions.
>> 1440
>> 1441 Loongson2F have built-in DDR2 and PCIX controller. The PCIX controller
>> 1442 have a similar programming interface with FPGA northbridge used in
>> 1443 Loongson2E.
>> 1444
>> 1445 config CPU_LOONGSON1B
>> 1446 bool "Loongson 1B"
>> 1447 depends on SYS_HAS_CPU_LOONGSON1B
>> 1448 select CPU_LOONGSON1
>> 1449 select LEDS_GPIO_REGISTER
>> 1450 help
>> 1451 The Loongson 1B is a 32-bit SoC, which implements the MIPS32
>> 1452 Release 1 instruction set and part of the MIPS32 Release 2
>> 1453 instruction set.
>> 1454
>> 1455 config CPU_LOONGSON1C
>> 1456 bool "Loongson 1C"
>> 1457 depends on SYS_HAS_CPU_LOONGSON1C
>> 1458 select CPU_LOONGSON1
>> 1459 select LEDS_GPIO_REGISTER
>> 1460 help
>> 1461 The Loongson 1C is a 32-bit SoC, which implements the MIPS32
>> 1462 Release 1 instruction set and part of the MIPS32 Release 2
>> 1463 instruction set.
>> 1464
>> 1465 config CPU_MIPS32_R1
>> 1466 bool "MIPS32 Release 1"
>> 1467 depends on SYS_HAS_CPU_MIPS32_R1
>> 1468 select CPU_HAS_PREFETCH
>> 1469 select CPU_HAS_LOAD_STORE_LR
>> 1470 select CPU_SUPPORTS_32BIT_KERNEL
>> 1471 select CPU_SUPPORTS_HIGHMEM
>> 1472 help
>> 1473 Choose this option to build a kernel for release 1 or later of the
>> 1474 MIPS32 architecture. Most modern embedded systems with a 32-bit
>> 1475 MIPS processor are based on a MIPS32 processor. If you know the
>> 1476 specific type of processor in your system, choose those that one
>> 1477 otherwise CPU_MIPS32_R1 is a safe bet for any MIPS32 system.
>> 1478 Release 2 of the MIPS32 architecture is available since several
>> 1479 years so chances are you even have a MIPS32 Release 2 processor
>> 1480 in which case you should choose CPU_MIPS32_R2 instead for better
>> 1481 performance.
>> 1482
>> 1483 config CPU_MIPS32_R2
>> 1484 bool "MIPS32 Release 2"
>> 1485 depends on SYS_HAS_CPU_MIPS32_R2
>> 1486 select CPU_HAS_PREFETCH
>> 1487 select CPU_HAS_LOAD_STORE_LR
>> 1488 select CPU_SUPPORTS_32BIT_KERNEL
>> 1489 select CPU_SUPPORTS_HIGHMEM
>> 1490 select CPU_SUPPORTS_MSA
>> 1491 select HAVE_KVM
>> 1492 help
>> 1493 Choose this option to build a kernel for release 2 or later of the
>> 1494 MIPS32 architecture. Most modern embedded systems with a 32-bit
>> 1495 MIPS processor are based on a MIPS32 processor. If you know the
>> 1496 specific type of processor in your system, choose those that one
>> 1497 otherwise CPU_MIPS32_R1 is a safe bet for any MIPS32 system.
>> 1498
>> 1499 config CPU_MIPS32_R6
>> 1500 bool "MIPS32 Release 6"
>> 1501 depends on SYS_HAS_CPU_MIPS32_R6
>> 1502 select CPU_HAS_PREFETCH
>> 1503 select CPU_SUPPORTS_32BIT_KERNEL
>> 1504 select CPU_SUPPORTS_HIGHMEM
>> 1505 select CPU_SUPPORTS_MSA
>> 1506 select HAVE_KVM
>> 1507 select MIPS_O32_FP64_SUPPORT
>> 1508 help
>> 1509 Choose this option to build a kernel for release 6 or later of the
>> 1510 MIPS32 architecture. New MIPS processors, starting with the Warrior
>> 1511 family, are based on a MIPS32r6 processor. If you own an older
>> 1512 processor, you probably need to select MIPS32r1 or MIPS32r2 instead.
>> 1513
>> 1514 config CPU_MIPS64_R1
>> 1515 bool "MIPS64 Release 1"
>> 1516 depends on SYS_HAS_CPU_MIPS64_R1
>> 1517 select CPU_HAS_PREFETCH
>> 1518 select CPU_HAS_LOAD_STORE_LR
>> 1519 select CPU_SUPPORTS_32BIT_KERNEL
>> 1520 select CPU_SUPPORTS_64BIT_KERNEL
>> 1521 select CPU_SUPPORTS_HIGHMEM
>> 1522 select CPU_SUPPORTS_HUGEPAGES
>> 1523 help
>> 1524 Choose this option to build a kernel for release 1 or later of the
>> 1525 MIPS64 architecture. Many modern embedded systems with a 64-bit
>> 1526 MIPS processor are based on a MIPS64 processor. If you know the
>> 1527 specific type of processor in your system, choose those that one
>> 1528 otherwise CPU_MIPS64_R1 is a safe bet for any MIPS64 system.
>> 1529 Release 2 of the MIPS64 architecture is available since several
>> 1530 years so chances are you even have a MIPS64 Release 2 processor
>> 1531 in which case you should choose CPU_MIPS64_R2 instead for better
>> 1532 performance.
>> 1533
>> 1534 config CPU_MIPS64_R2
>> 1535 bool "MIPS64 Release 2"
>> 1536 depends on SYS_HAS_CPU_MIPS64_R2
>> 1537 select CPU_HAS_PREFETCH
>> 1538 select CPU_HAS_LOAD_STORE_LR
>> 1539 select CPU_SUPPORTS_32BIT_KERNEL
>> 1540 select CPU_SUPPORTS_64BIT_KERNEL
>> 1541 select CPU_SUPPORTS_HIGHMEM
>> 1542 select CPU_SUPPORTS_HUGEPAGES
>> 1543 select CPU_SUPPORTS_MSA
>> 1544 select HAVE_KVM
>> 1545 help
>> 1546 Choose this option to build a kernel for release 2 or later of the
>> 1547 MIPS64 architecture. Many modern embedded systems with a 64-bit
>> 1548 MIPS processor are based on a MIPS64 processor. If you know the
>> 1549 specific type of processor in your system, choose those that one
>> 1550 otherwise CPU_MIPS64_R1 is a safe bet for any MIPS64 system.
>> 1551
>> 1552 config CPU_MIPS64_R6
>> 1553 bool "MIPS64 Release 6"
>> 1554 depends on SYS_HAS_CPU_MIPS64_R6
>> 1555 select CPU_HAS_PREFETCH
>> 1556 select CPU_SUPPORTS_32BIT_KERNEL
>> 1557 select CPU_SUPPORTS_64BIT_KERNEL
>> 1558 select CPU_SUPPORTS_HIGHMEM
>> 1559 select CPU_SUPPORTS_HUGEPAGES
>> 1560 select CPU_SUPPORTS_MSA
>> 1561 select MIPS_O32_FP64_SUPPORT if 32BIT || MIPS32_O32
>> 1562 select HAVE_KVM
>> 1563 help
>> 1564 Choose this option to build a kernel for release 6 or later of the
>> 1565 MIPS64 architecture. New MIPS processors, starting with the Warrior
>> 1566 family, are based on a MIPS64r6 processor. If you own an older
>> 1567 processor, you probably need to select MIPS64r1 or MIPS64r2 instead.
>> 1568
>> 1569 config CPU_R3000
>> 1570 bool "R3000"
>> 1571 depends on SYS_HAS_CPU_R3000
>> 1572 select CPU_HAS_WB
>> 1573 select CPU_HAS_LOAD_STORE_LR
>> 1574 select CPU_SUPPORTS_32BIT_KERNEL
>> 1575 select CPU_SUPPORTS_HIGHMEM
>> 1576 help
>> 1577 Please make sure to pick the right CPU type. Linux/MIPS is not
>> 1578 designed to be generic, i.e. Kernels compiled for R3000 CPUs will
>> 1579 *not* work on R4000 machines and vice versa. However, since most
>> 1580 of the supported machines have an R4000 (or similar) CPU, R4x00
>> 1581 might be a safe bet. If the resulting kernel does not work,
>> 1582 try to recompile with R3000.
>> 1583
>> 1584 config CPU_TX39XX
>> 1585 bool "R39XX"
>> 1586 depends on SYS_HAS_CPU_TX39XX
>> 1587 select CPU_SUPPORTS_32BIT_KERNEL
>> 1588 select CPU_HAS_LOAD_STORE_LR
>> 1589
>> 1590 config CPU_VR41XX
>> 1591 bool "R41xx"
>> 1592 depends on SYS_HAS_CPU_VR41XX
>> 1593 select CPU_SUPPORTS_32BIT_KERNEL
>> 1594 select CPU_SUPPORTS_64BIT_KERNEL
>> 1595 select CPU_HAS_LOAD_STORE_LR
>> 1596 help
>> 1597 The options selects support for the NEC VR4100 series of processors.
>> 1598 Only choose this option if you have one of these processors as a
>> 1599 kernel built with this option will not run on any other type of
>> 1600 processor or vice versa.
>> 1601
>> 1602 config CPU_R4300
>> 1603 bool "R4300"
>> 1604 depends on SYS_HAS_CPU_R4300
>> 1605 select CPU_SUPPORTS_32BIT_KERNEL
>> 1606 select CPU_SUPPORTS_64BIT_KERNEL
>> 1607 select CPU_HAS_LOAD_STORE_LR
>> 1608 help
>> 1609 MIPS Technologies R4300-series processors.
>> 1610
>> 1611 config CPU_R4X00
>> 1612 bool "R4x00"
>> 1613 depends on SYS_HAS_CPU_R4X00
>> 1614 select CPU_SUPPORTS_32BIT_KERNEL
>> 1615 select CPU_SUPPORTS_64BIT_KERNEL
>> 1616 select CPU_SUPPORTS_HUGEPAGES
>> 1617 select CPU_HAS_LOAD_STORE_LR
>> 1618 help
>> 1619 MIPS Technologies R4000-series processors other than 4300, including
>> 1620 the R4000, R4400, R4600, and 4700.
>> 1621
>> 1622 config CPU_TX49XX
>> 1623 bool "R49XX"
>> 1624 depends on SYS_HAS_CPU_TX49XX
>> 1625 select CPU_HAS_PREFETCH
>> 1626 select CPU_HAS_LOAD_STORE_LR
>> 1627 select CPU_SUPPORTS_32BIT_KERNEL
>> 1628 select CPU_SUPPORTS_64BIT_KERNEL
>> 1629 select CPU_SUPPORTS_HUGEPAGES
>> 1630
>> 1631 config CPU_R5000
>> 1632 bool "R5000"
>> 1633 depends on SYS_HAS_CPU_R5000
>> 1634 select CPU_SUPPORTS_32BIT_KERNEL
>> 1635 select CPU_SUPPORTS_64BIT_KERNEL
>> 1636 select CPU_SUPPORTS_HUGEPAGES
>> 1637 select CPU_HAS_LOAD_STORE_LR
>> 1638 help
>> 1639 MIPS Technologies R5000-series processors other than the Nevada.
>> 1640
>> 1641 config CPU_R5432
>> 1642 bool "R5432"
>> 1643 depends on SYS_HAS_CPU_R5432
>> 1644 select CPU_SUPPORTS_32BIT_KERNEL
>> 1645 select CPU_SUPPORTS_64BIT_KERNEL
>> 1646 select CPU_SUPPORTS_HUGEPAGES
>> 1647 select CPU_HAS_LOAD_STORE_LR
>> 1648
>> 1649 config CPU_R5500
>> 1650 bool "R5500"
>> 1651 depends on SYS_HAS_CPU_R5500
>> 1652 select CPU_SUPPORTS_32BIT_KERNEL
>> 1653 select CPU_SUPPORTS_64BIT_KERNEL
>> 1654 select CPU_SUPPORTS_HUGEPAGES
>> 1655 select CPU_HAS_LOAD_STORE_LR
>> 1656 help
>> 1657 NEC VR5500 and VR5500A series processors implement 64-bit MIPS IV
>> 1658 instruction set.
>> 1659
>> 1660 config CPU_NEVADA
>> 1661 bool "RM52xx"
>> 1662 depends on SYS_HAS_CPU_NEVADA
>> 1663 select CPU_SUPPORTS_32BIT_KERNEL
>> 1664 select CPU_SUPPORTS_64BIT_KERNEL
>> 1665 select CPU_SUPPORTS_HUGEPAGES
>> 1666 select CPU_HAS_LOAD_STORE_LR
>> 1667 help
>> 1668 QED / PMC-Sierra RM52xx-series ("Nevada") processors.
>> 1669
>> 1670 config CPU_R8000
>> 1671 bool "R8000"
>> 1672 depends on SYS_HAS_CPU_R8000
>> 1673 select CPU_HAS_PREFETCH
>> 1674 select CPU_HAS_LOAD_STORE_LR
>> 1675 select CPU_SUPPORTS_64BIT_KERNEL
>> 1676 help
>> 1677 MIPS Technologies R8000 processors. Note these processors are
>> 1678 uncommon and the support for them is incomplete.
>> 1679
>> 1680 config CPU_R10000
>> 1681 bool "R10000"
>> 1682 depends on SYS_HAS_CPU_R10000
>> 1683 select CPU_HAS_PREFETCH
>> 1684 select CPU_HAS_LOAD_STORE_LR
>> 1685 select CPU_SUPPORTS_32BIT_KERNEL
>> 1686 select CPU_SUPPORTS_64BIT_KERNEL
>> 1687 select CPU_SUPPORTS_HIGHMEM
>> 1688 select CPU_SUPPORTS_HUGEPAGES
>> 1689 help
>> 1690 MIPS Technologies R10000-series processors.
>> 1691
>> 1692 config CPU_RM7000
>> 1693 bool "RM7000"
>> 1694 depends on SYS_HAS_CPU_RM7000
>> 1695 select CPU_HAS_PREFETCH
>> 1696 select CPU_HAS_LOAD_STORE_LR
>> 1697 select CPU_SUPPORTS_32BIT_KERNEL
>> 1698 select CPU_SUPPORTS_64BIT_KERNEL
>> 1699 select CPU_SUPPORTS_HIGHMEM
>> 1700 select CPU_SUPPORTS_HUGEPAGES
>> 1701
>> 1702 config CPU_SB1
>> 1703 bool "SB1"
>> 1704 depends on SYS_HAS_CPU_SB1
>> 1705 select CPU_HAS_LOAD_STORE_LR
>> 1706 select CPU_SUPPORTS_32BIT_KERNEL
>> 1707 select CPU_SUPPORTS_64BIT_KERNEL
>> 1708 select CPU_SUPPORTS_HIGHMEM
>> 1709 select CPU_SUPPORTS_HUGEPAGES
>> 1710 select WEAK_ORDERING
>> 1711
>> 1712 config CPU_CAVIUM_OCTEON
>> 1713 bool "Cavium Octeon processor"
>> 1714 depends on SYS_HAS_CPU_CAVIUM_OCTEON
>> 1715 select CPU_HAS_PREFETCH
>> 1716 select CPU_HAS_LOAD_STORE_LR
>> 1717 select CPU_SUPPORTS_64BIT_KERNEL
>> 1718 select WEAK_ORDERING
>> 1719 select CPU_SUPPORTS_HIGHMEM
>> 1720 select CPU_SUPPORTS_HUGEPAGES
>> 1721 select USB_EHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 1722 select USB_OHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 1723 select MIPS_L1_CACHE_SHIFT_7
>> 1724 select HAVE_KVM
>> 1725 help
>> 1726 The Cavium Octeon processor is a highly integrated chip containing
>> 1727 many ethernet hardware widgets for networking tasks. The processor
>> 1728 can have up to 16 Mips64v2 cores and 8 integrated gigabit ethernets.
>> 1729 Full details can be found at http://www.caviumnetworks.com.
>> 1730
>> 1731 config CPU_BMIPS
>> 1732 bool "Broadcom BMIPS"
>> 1733 depends on SYS_HAS_CPU_BMIPS
>> 1734 select CPU_MIPS32
>> 1735 select CPU_BMIPS32_3300 if SYS_HAS_CPU_BMIPS32_3300
>> 1736 select CPU_BMIPS4350 if SYS_HAS_CPU_BMIPS4350
>> 1737 select CPU_BMIPS4380 if SYS_HAS_CPU_BMIPS4380
>> 1738 select CPU_BMIPS5000 if SYS_HAS_CPU_BMIPS5000
>> 1739 select CPU_SUPPORTS_32BIT_KERNEL
>> 1740 select DMA_NONCOHERENT
>> 1741 select IRQ_MIPS_CPU
>> 1742 select SWAP_IO_SPACE
>> 1743 select WEAK_ORDERING
>> 1744 select CPU_SUPPORTS_HIGHMEM
>> 1745 select CPU_HAS_PREFETCH
>> 1746 select CPU_HAS_LOAD_STORE_LR
>> 1747 select CPU_SUPPORTS_CPUFREQ
>> 1748 select MIPS_EXTERNAL_TIMER
>> 1749 help
>> 1750 Support for BMIPS32/3300/4350/4380 and BMIPS5000 processors.
>> 1751
>> 1752 config CPU_XLR
>> 1753 bool "Netlogic XLR SoC"
>> 1754 depends on SYS_HAS_CPU_XLR
>> 1755 select CPU_HAS_LOAD_STORE_LR
>> 1756 select CPU_SUPPORTS_32BIT_KERNEL
>> 1757 select CPU_SUPPORTS_64BIT_KERNEL
>> 1758 select CPU_SUPPORTS_HIGHMEM
>> 1759 select CPU_SUPPORTS_HUGEPAGES
>> 1760 select WEAK_ORDERING
>> 1761 select WEAK_REORDERING_BEYOND_LLSC
>> 1762 help
>> 1763 Netlogic Microsystems XLR/XLS processors.
>> 1764
>> 1765 config CPU_XLP
>> 1766 bool "Netlogic XLP SoC"
>> 1767 depends on SYS_HAS_CPU_XLP
>> 1768 select CPU_SUPPORTS_32BIT_KERNEL
>> 1769 select CPU_SUPPORTS_64BIT_KERNEL
>> 1770 select CPU_SUPPORTS_HIGHMEM
>> 1771 select WEAK_ORDERING
>> 1772 select WEAK_REORDERING_BEYOND_LLSC
>> 1773 select CPU_HAS_PREFETCH
>> 1774 select CPU_HAS_LOAD_STORE_LR
>> 1775 select CPU_MIPSR2
>> 1776 select CPU_SUPPORTS_HUGEPAGES
>> 1777 select MIPS_ASID_BITS_VARIABLE
>> 1778 help
>> 1779 Netlogic Microsystems XLP processors.
>> 1780 endchoice
979 1781
980 If unsure, say Y. !! 1782 config CPU_MIPS32_3_5_FEATURES
>> 1783 bool "MIPS32 Release 3.5 Features"
>> 1784 depends on SYS_HAS_CPU_MIPS32_R3_5
>> 1785 depends on CPU_MIPS32_R2 || CPU_MIPS32_R6
>> 1786 help
>> 1787 Choose this option to build a kernel for release 2 or later of the
>> 1788 MIPS32 architecture including features from the 3.5 release such as
>> 1789 support for Enhanced Virtual Addressing (EVA).
>> 1790
>> 1791 config CPU_MIPS32_3_5_EVA
>> 1792 bool "Enhanced Virtual Addressing (EVA)"
>> 1793 depends on CPU_MIPS32_3_5_FEATURES
>> 1794 select EVA
>> 1795 default y
>> 1796 help
>> 1797 Choose this option if you want to enable the Enhanced Virtual
>> 1798 Addressing (EVA) on your MIPS32 core (such as proAptiv).
>> 1799 One of its primary benefits is an increase in the maximum size
>> 1800 of lowmem (up to 3GB). If unsure, say 'N' here.
>> 1801
>> 1802 config CPU_MIPS32_R5_FEATURES
>> 1803 bool "MIPS32 Release 5 Features"
>> 1804 depends on SYS_HAS_CPU_MIPS32_R5
>> 1805 depends on CPU_MIPS32_R2
>> 1806 help
>> 1807 Choose this option to build a kernel for release 2 or later of the
>> 1808 MIPS32 architecture including features from release 5 such as
>> 1809 support for Extended Physical Addressing (XPA).
>> 1810
>> 1811 config CPU_MIPS32_R5_XPA
>> 1812 bool "Extended Physical Addressing (XPA)"
>> 1813 depends on CPU_MIPS32_R5_FEATURES
>> 1814 depends on !EVA
>> 1815 depends on !PAGE_SIZE_4KB
>> 1816 depends on SYS_SUPPORTS_HIGHMEM
>> 1817 select XPA
>> 1818 select HIGHMEM
>> 1819 select PHYS_ADDR_T_64BIT
>> 1820 default n
>> 1821 help
>> 1822 Choose this option if you want to enable the Extended Physical
>> 1823 Addressing (XPA) on your MIPS32 core (such as P5600 series). The
>> 1824 benefit is to increase physical addressing equal to or greater
>> 1825 than 40 bits. Note that this has the side effect of turning on
>> 1826 64-bit addressing which in turn makes the PTEs 64-bit in size.
>> 1827 If unsure, say 'N' here.
981 1828
982 config ARM64_ERRATUM_2038923 !! 1829 if CPU_LOONGSON2F
983 bool "Cortex-A510: 2038923: workaround !! 1830 config CPU_NOP_WORKAROUNDS
984 depends on CORESIGHT_TRBE !! 1831 bool
985 default y <<
986 help <<
987 This option adds the workaround for <<
988 <<
989 Affected Cortex-A510 core might caus <<
990 prohibited within the CPU. As a resu <<
991 might be corrupted. This happens aft <<
992 TRBLIMITR_EL1.E, followed by just a <<
993 execution changes from a context, in <<
994 isn't, or vice versa. In these menti <<
995 is prohibited is inconsistent betwee <<
996 the trace buffer state might be corr <<
997 <<
998 Work around this in the driver by pr <<
999 trace is prohibited or not based on <<
1000 change to TRBLIMITR_EL1.E with at l <<
1001 two ISB instructions if no ERET is <<
1002 1832
1003 If unsure, say Y. !! 1833 config CPU_JUMP_WORKAROUNDS
>> 1834 bool
1004 1835
1005 config ARM64_ERRATUM_1902691 !! 1836 config CPU_LOONGSON2F_WORKAROUNDS
1006 bool "Cortex-A510: 1902691: workaroun !! 1837 bool "Loongson 2F Workarounds"
1007 depends on CORESIGHT_TRBE <<
1008 default y 1838 default y
>> 1839 select CPU_NOP_WORKAROUNDS
>> 1840 select CPU_JUMP_WORKAROUNDS
1009 help 1841 help
1010 This option adds the workaround for !! 1842 Loongson 2F01 / 2F02 processors have the NOP & JUMP issues which
1011 !! 1843 require workarounds. Without workarounds the system may hang
1012 Affected Cortex-A510 core might cau !! 1844 unexpectedly. For more information please refer to the gas
1013 into the memory. Effectively TRBE i !! 1845 -mfix-loongson2f-nop and -mfix-loongson2f-jump options.
1014 trace data. !! 1846
>> 1847 Loongson 2F03 and later have fixed these issues and no workarounds
>> 1848 are needed. The workarounds have no significant side effect on them
>> 1849 but may decrease the performance of the system so this option should
>> 1850 be disabled unless the kernel is intended to be run on 2F01 or 2F02
>> 1851 systems.
1015 1852
1016 Work around this problem in the dri !! 1853 If unsure, please say Y.
1017 affected cpus. The firmware must ha !! 1854 endif # CPU_LOONGSON2F
1018 on such implementations. This will <<
1019 do this already. <<
1020 1855
1021 If unsure, say Y. !! 1856 config SYS_SUPPORTS_ZBOOT
>> 1857 bool
>> 1858 select HAVE_KERNEL_GZIP
>> 1859 select HAVE_KERNEL_BZIP2
>> 1860 select HAVE_KERNEL_LZ4
>> 1861 select HAVE_KERNEL_LZMA
>> 1862 select HAVE_KERNEL_LZO
>> 1863 select HAVE_KERNEL_XZ
1022 1864
1023 config ARM64_ERRATUM_2457168 !! 1865 config SYS_SUPPORTS_ZBOOT_UART16550
1024 bool "Cortex-A510: 2457168: workaroun !! 1866 bool
1025 depends on ARM64_AMU_EXTN !! 1867 select SYS_SUPPORTS_ZBOOT
1026 default y <<
1027 help <<
1028 This option adds the workaround for <<
1029 1868
1030 The AMU counter AMEVCNTR01 (constan !! 1869 config SYS_SUPPORTS_ZBOOT_UART_PROM
1031 as the system counter. On affected !! 1870 bool
1032 incorrectly giving a significantly !! 1871 select SYS_SUPPORTS_ZBOOT
1033 1872
1034 Work around this problem by returni !! 1873 config CPU_LOONGSON2
1035 key locations that results in disab !! 1874 bool
1036 is the same to firmware disabling a !! 1875 select CPU_SUPPORTS_32BIT_KERNEL
>> 1876 select CPU_SUPPORTS_64BIT_KERNEL
>> 1877 select CPU_SUPPORTS_HIGHMEM
>> 1878 select CPU_SUPPORTS_HUGEPAGES
>> 1879 select ARCH_HAS_PHYS_TO_DMA
>> 1880 select CPU_HAS_LOAD_STORE_LR
1037 1881
1038 If unsure, say Y. !! 1882 config CPU_LOONGSON1
>> 1883 bool
>> 1884 select CPU_MIPS32
>> 1885 select CPU_MIPSR2
>> 1886 select CPU_HAS_PREFETCH
>> 1887 select CPU_HAS_LOAD_STORE_LR
>> 1888 select CPU_SUPPORTS_32BIT_KERNEL
>> 1889 select CPU_SUPPORTS_HIGHMEM
>> 1890 select CPU_SUPPORTS_CPUFREQ
1039 1891
1040 config ARM64_ERRATUM_2645198 !! 1892 config CPU_BMIPS32_3300
1041 bool "Cortex-A715: 2645198: Workaroun !! 1893 select SMP_UP if SMP
1042 default y !! 1894 bool
1043 help <<
1044 This option adds the workaround for <<
1045 1895
1046 If a Cortex-A715 cpu sees a page ma !! 1896 config CPU_BMIPS4350
1047 to non-executable, it may corrupt t !! 1897 bool
1048 next instruction abort caused by pe !! 1898 select SYS_SUPPORTS_SMP
>> 1899 select SYS_SUPPORTS_HOTPLUG_CPU
1049 1900
1050 Only user-space does executable to !! 1901 config CPU_BMIPS4380
1051 mprotect() system call. Workaround !! 1902 bool
1052 TLB invalidation, for all changes t !! 1903 select MIPS_L1_CACHE_SHIFT_6
>> 1904 select SYS_SUPPORTS_SMP
>> 1905 select SYS_SUPPORTS_HOTPLUG_CPU
>> 1906 select CPU_HAS_RIXI
1053 1907
1054 If unsure, say Y. !! 1908 config CPU_BMIPS5000
>> 1909 bool
>> 1910 select MIPS_CPU_SCACHE
>> 1911 select MIPS_L1_CACHE_SHIFT_7
>> 1912 select SYS_SUPPORTS_SMP
>> 1913 select SYS_SUPPORTS_HOTPLUG_CPU
>> 1914 select CPU_HAS_RIXI
1055 1915
1056 config ARM64_WORKAROUND_SPECULATIVE_UNPRIV_LO !! 1916 config SYS_HAS_CPU_LOONGSON3
1057 bool 1917 bool
>> 1918 select CPU_SUPPORTS_CPUFREQ
>> 1919 select CPU_HAS_RIXI
1058 1920
1059 config ARM64_ERRATUM_2966298 !! 1921 config SYS_HAS_CPU_LOONGSON2E
1060 bool "Cortex-A520: 2966298: workaroun !! 1922 bool
1061 select ARM64_WORKAROUND_SPECULATIVE_U <<
1062 default y <<
1063 help <<
1064 This option adds the workaround for <<
1065 1923
1066 On an affected Cortex-A520 core, a !! 1924 config SYS_HAS_CPU_LOONGSON2F
1067 load might leak data from a privile !! 1925 bool
>> 1926 select CPU_SUPPORTS_CPUFREQ
>> 1927 select CPU_SUPPORTS_ADDRWINCFG if 64BIT
>> 1928 select CPU_SUPPORTS_UNCACHED_ACCELERATED
1068 1929
1069 Work around this problem by executi !! 1930 config SYS_HAS_CPU_LOONGSON1B
>> 1931 bool
1070 1932
1071 If unsure, say Y. !! 1933 config SYS_HAS_CPU_LOONGSON1C
>> 1934 bool
1072 1935
1073 config ARM64_ERRATUM_3117295 !! 1936 config SYS_HAS_CPU_MIPS32_R1
1074 bool "Cortex-A510: 3117295: workaroun !! 1937 bool
1075 select ARM64_WORKAROUND_SPECULATIVE_U <<
1076 default y <<
1077 help <<
1078 This option adds the workaround for <<
1079 1938
1080 On an affected Cortex-A510 core, a !! 1939 config SYS_HAS_CPU_MIPS32_R2
1081 load might leak data from a privile !! 1940 bool
1082 1941
1083 Work around this problem by executi !! 1942 config SYS_HAS_CPU_MIPS32_R3_5
>> 1943 bool
1084 1944
1085 If unsure, say Y. !! 1945 config SYS_HAS_CPU_MIPS32_R5
>> 1946 bool
>> 1947 select ARCH_HAS_SYNC_DMA_FOR_CPU if DMA_NONCOHERENT
1086 1948
1087 config ARM64_ERRATUM_3194386 !! 1949 config SYS_HAS_CPU_MIPS32_R6
1088 bool "Cortex-*/Neoverse-*: workaround !! 1950 bool
1089 default y !! 1951 select ARCH_HAS_SYNC_DMA_FOR_CPU if DMA_NONCOHERENT
1090 help <<
1091 This option adds the workaround for <<
1092 1952
1093 * ARM Cortex-A76 erratum 3324349 !! 1953 config SYS_HAS_CPU_MIPS64_R1
1094 * ARM Cortex-A77 erratum 3324348 !! 1954 bool
1095 * ARM Cortex-A78 erratum 3324344 <<
1096 * ARM Cortex-A78C erratum 3324346 <<
1097 * ARM Cortex-A78C erratum 3324347 <<
1098 * ARM Cortex-A710 erratam 3324338 <<
1099 * ARM Cortex-A715 errartum 3456084 <<
1100 * ARM Cortex-A720 erratum 3456091 <<
1101 * ARM Cortex-A725 erratum 3456106 <<
1102 * ARM Cortex-X1 erratum 3324344 <<
1103 * ARM Cortex-X1C erratum 3324346 <<
1104 * ARM Cortex-X2 erratum 3324338 <<
1105 * ARM Cortex-X3 erratum 3324335 <<
1106 * ARM Cortex-X4 erratum 3194386 <<
1107 * ARM Cortex-X925 erratum 3324334 <<
1108 * ARM Neoverse-N1 erratum 3324349 <<
1109 * ARM Neoverse N2 erratum 3324339 <<
1110 * ARM Neoverse-N3 erratum 3456111 <<
1111 * ARM Neoverse-V1 erratum 3324341 <<
1112 * ARM Neoverse V2 erratum 3324336 <<
1113 * ARM Neoverse-V3 erratum 3312417 <<
1114 <<
1115 On affected cores "MSR SSBS, #0" in <<
1116 subsequent speculative instructions <<
1117 speculative store bypassing. <<
1118 <<
1119 Work around this problem by placing <<
1120 Instruction Synchronization Barrier <<
1121 SSBS. The presence of the SSBS spec <<
1122 from hwcaps and EL0 reads of ID_AA6 <<
1123 will use the PR_SPEC_STORE_BYPASS p <<
1124 1955
1125 If unsure, say Y. !! 1956 config SYS_HAS_CPU_MIPS64_R2
>> 1957 bool
1126 1958
1127 config CAVIUM_ERRATUM_22375 !! 1959 config SYS_HAS_CPU_MIPS64_R6
1128 bool "Cavium erratum 22375, 24313" !! 1960 bool
1129 default y !! 1961 select ARCH_HAS_SYNC_DMA_FOR_CPU if DMA_NONCOHERENT
1130 help <<
1131 Enable workaround for errata 22375 <<
1132 1962
1133 This implements two gicv3-its errat !! 1963 config SYS_HAS_CPU_R3000
1134 with a small impact affecting only !! 1964 bool
1135 1965
1136 erratum 22375: only alloc 8MB tab !! 1966 config SYS_HAS_CPU_TX39XX
1137 erratum 24313: ignore memory acce !! 1967 bool
1138 1968
1139 The fixes are in ITS initialization !! 1969 config SYS_HAS_CPU_VR41XX
1140 type and table size provided by the !! 1970 bool
1141 1971
1142 If unsure, say Y. !! 1972 config SYS_HAS_CPU_R4300
>> 1973 bool
1143 1974
1144 config CAVIUM_ERRATUM_23144 !! 1975 config SYS_HAS_CPU_R4X00
1145 bool "Cavium erratum 23144: ITS SYNC !! 1976 bool
1146 depends on NUMA <<
1147 default y <<
1148 help <<
1149 ITS SYNC command hang for cross nod <<
1150 1977
1151 If unsure, say Y. !! 1978 config SYS_HAS_CPU_TX49XX
>> 1979 bool
1152 1980
1153 config CAVIUM_ERRATUM_23154 !! 1981 config SYS_HAS_CPU_R5000
1154 bool "Cavium errata 23154 and 38545: !! 1982 bool
1155 default y <<
1156 help <<
1157 The ThunderX GICv3 implementation r <<
1158 reading the IAR status to ensure da <<
1159 (access to icc_iar1_el1 is not sync <<
1160 1983
1161 It also suffers from erratum 38545 !! 1984 config SYS_HAS_CPU_R5432
1162 OcteonTX and OcteonTX2), resulting !! 1985 bool
1163 spuriously presented to the CPU int <<
1164 1986
1165 If unsure, say Y. !! 1987 config SYS_HAS_CPU_R5500
>> 1988 bool
1166 1989
1167 config CAVIUM_ERRATUM_27456 !! 1990 config SYS_HAS_CPU_NEVADA
1168 bool "Cavium erratum 27456: Broadcast !! 1991 bool
1169 default y <<
1170 help <<
1171 On ThunderX T88 pass 1.x through 2. <<
1172 instructions may cause the icache t <<
1173 contains data for a non-current ASI <<
1174 invalidate the icache when changing <<
1175 1992
1176 If unsure, say Y. !! 1993 config SYS_HAS_CPU_R8000
>> 1994 bool
1177 1995
1178 config CAVIUM_ERRATUM_30115 !! 1996 config SYS_HAS_CPU_R10000
1179 bool "Cavium erratum 30115: Guest may !! 1997 bool
1180 default y !! 1998 select ARCH_HAS_SYNC_DMA_FOR_CPU if DMA_NONCOHERENT
1181 help <<
1182 On ThunderX T88 pass 1.x through 2. <<
1183 1.2, and T83 Pass 1.0, KVM guest ex <<
1184 interrupts in host. Trapping both G <<
1185 accesses sidesteps the issue. <<
1186 1999
1187 If unsure, say Y. !! 2000 config SYS_HAS_CPU_RM7000
>> 2001 bool
1188 2002
1189 config CAVIUM_TX2_ERRATUM_219 !! 2003 config SYS_HAS_CPU_SB1
1190 bool "Cavium ThunderX2 erratum 219: P !! 2004 bool
1191 default y <<
1192 help <<
1193 On Cavium ThunderX2, a load, store <<
1194 TTBR update and the corresponding c <<
1195 cause a spurious Data Abort to be d <<
1196 the CPU core. <<
1197 <<
1198 Work around the issue by avoiding t <<
1199 trapping KVM guest TTBRx_EL1 writes <<
1200 trap handler performs the correspon <<
1201 instruction and ensures context syn <<
1202 exception return. <<
1203 2005
1204 If unsure, say Y. !! 2006 config SYS_HAS_CPU_CAVIUM_OCTEON
>> 2007 bool
1205 2008
1206 config FUJITSU_ERRATUM_010001 !! 2009 config SYS_HAS_CPU_BMIPS
1207 bool "Fujitsu-A64FX erratum E#010001: !! 2010 bool
1208 default y <<
1209 help <<
1210 This option adds a workaround for F <<
1211 On some variants of the Fujitsu-A64 <<
1212 accesses may cause undefined fault <<
1213 This fault occurs under a specific <<
1214 load/store instruction performs an <<
1215 case-1 TTBR0_EL1 with TCR_EL1.NFD0 <<
1216 case-2 TTBR0_EL2 with TCR_EL2.NFD0 <<
1217 case-3 TTBR1_EL1 with TCR_EL1.NFD1 <<
1218 case-4 TTBR1_EL2 with TCR_EL2.NFD1 <<
1219 2011
1220 The workaround is to ensure these b !! 2012 config SYS_HAS_CPU_BMIPS32_3300
1221 The workaround only affects the Fuj !! 2013 bool
>> 2014 select SYS_HAS_CPU_BMIPS
1222 2015
1223 If unsure, say Y. !! 2016 config SYS_HAS_CPU_BMIPS4350
>> 2017 bool
>> 2018 select SYS_HAS_CPU_BMIPS
1224 2019
1225 config HISILICON_ERRATUM_161600802 !! 2020 config SYS_HAS_CPU_BMIPS4380
1226 bool "Hip07 161600802: Erroneous redi !! 2021 bool
1227 default y !! 2022 select SYS_HAS_CPU_BMIPS
1228 help <<
1229 The HiSilicon Hip07 SoC uses the wr <<
1230 when issued ITS commands such as VM <<
1231 a 128kB offset to be applied to the <<
1232 2023
1233 If unsure, say Y. !! 2024 config SYS_HAS_CPU_BMIPS5000
>> 2025 bool
>> 2026 select SYS_HAS_CPU_BMIPS
>> 2027 select ARCH_HAS_SYNC_DMA_FOR_CPU
1234 2028
1235 config QCOM_FALKOR_ERRATUM_1003 !! 2029 config SYS_HAS_CPU_XLR
1236 bool "Falkor E1003: Incorrect transla !! 2030 bool
1237 default y <<
1238 help <<
1239 On Falkor v1, an incorrect ASID may <<
1240 and BADDR are changed together in T <<
1241 in TTBR1_EL1, this situation only o <<
1242 then only for entries in the walk c <<
1243 is unchanged. Work around the errat <<
1244 entries for the trampoline before e <<
1245 2031
1246 config QCOM_FALKOR_ERRATUM_1009 !! 2032 config SYS_HAS_CPU_XLP
1247 bool "Falkor E1009: Prematurely compl !! 2033 bool
1248 default y <<
1249 select ARM64_WORKAROUND_REPEAT_TLBI <<
1250 help <<
1251 On Falkor v1, the CPU may premature <<
1252 TLBI xxIS invalidate maintenance op <<
1253 one more time to fix the issue. <<
1254 2034
1255 If unsure, say Y. !! 2035 #
>> 2036 # CPU may reorder R->R, R->W, W->R, W->W
>> 2037 # Reordering beyond LL and SC is handled in WEAK_REORDERING_BEYOND_LLSC
>> 2038 #
>> 2039 config WEAK_ORDERING
>> 2040 bool
1256 2041
1257 config QCOM_QDF2400_ERRATUM_0065 !! 2042 #
1258 bool "QDF2400 E0065: Incorrect GITS_T !! 2043 # CPU may reorder reads and writes beyond LL/SC
1259 default y !! 2044 # CPU may reorder R->LL, R->LL, W->LL, W->LL, R->SC, R->SC, W->SC, W->SC
1260 help !! 2045 #
1261 On Qualcomm Datacenter Technologies !! 2046 config WEAK_REORDERING_BEYOND_LLSC
1262 ITE size incorrectly. The GITS_TYPE !! 2047 bool
1263 been indicated as 16Bytes (0xf), no !! 2048 endmenu
1264 2049
1265 If unsure, say Y. !! 2050 #
>> 2051 # These two indicate any level of the MIPS32 and MIPS64 architecture
>> 2052 #
>> 2053 config CPU_MIPS32
>> 2054 bool
>> 2055 default y if CPU_MIPS32_R1 || CPU_MIPS32_R2 || CPU_MIPS32_R6
1266 2056
1267 config QCOM_FALKOR_ERRATUM_E1041 !! 2057 config CPU_MIPS64
1268 bool "Falkor E1041: Speculative instr !! 2058 bool
1269 default y !! 2059 default y if CPU_MIPS64_R1 || CPU_MIPS64_R2 || CPU_MIPS64_R6
1270 help <<
1271 Falkor CPU may speculatively fetch <<
1272 memory location when MMU translatio <<
1273 to SCTLR_ELn[M]=0. Prefix an ISB in <<
1274 2060
1275 If unsure, say Y. !! 2061 #
>> 2062 # These indicate the revision of the architecture
>> 2063 #
>> 2064 config CPU_MIPSR1
>> 2065 bool
>> 2066 default y if CPU_MIPS32_R1 || CPU_MIPS64_R1
1276 2067
1277 config NVIDIA_CARMEL_CNP_ERRATUM !! 2068 config CPU_MIPSR2
1278 bool "NVIDIA Carmel CNP: CNP on Carme !! 2069 bool
1279 default y !! 2070 default y if CPU_MIPS32_R2 || CPU_MIPS64_R2 || CPU_CAVIUM_OCTEON
1280 help !! 2071 select CPU_HAS_RIXI
1281 If CNP is enabled on Carmel cores, !! 2072 select MIPS_SPRAM
1282 invalidate shared TLB entries insta <<
1283 on standard ARM cores. <<
1284 2073
1285 If unsure, say Y. !! 2074 config CPU_MIPSR6
>> 2075 bool
>> 2076 default y if CPU_MIPS32_R6 || CPU_MIPS64_R6
>> 2077 select CPU_HAS_RIXI
>> 2078 select HAVE_ARCH_BITREVERSE
>> 2079 select MIPS_ASID_BITS_VARIABLE
>> 2080 select MIPS_CRC_SUPPORT
>> 2081 select MIPS_SPRAM
1286 2082
1287 config ROCKCHIP_ERRATUM_3588001 !! 2083 config TARGET_ISA_REV
1288 bool "Rockchip 3588001: GIC600 can no !! 2084 int
1289 default y !! 2085 default 1 if CPU_MIPSR1
>> 2086 default 2 if CPU_MIPSR2
>> 2087 default 6 if CPU_MIPSR6
>> 2088 default 0
1290 help 2089 help
1291 The Rockchip RK3588 GIC600 SoC inte !! 2090 Reflects the ISA revision being targeted by the kernel build. This
1292 This means, that its sharability fe !! 2091 is effectively the Kconfig equivalent of MIPS_ISA_REV.
1293 is supported by the IP itself. <<
1294 <<
1295 If unsure, say Y. <<
1296 2092
1297 config SOCIONEXT_SYNQUACER_PREITS !! 2093 config EVA
1298 bool "Socionext Synquacer: Workaround !! 2094 bool
1299 default y <<
1300 help <<
1301 Socionext Synquacer SoCs implement <<
1302 MSI doorbell writes with non-zero v <<
1303 2095
1304 If unsure, say Y. !! 2096 config XPA
>> 2097 bool
1305 2098
1306 endmenu # "ARM errata workarounds via the alt !! 2099 config SYS_SUPPORTS_32BIT_KERNEL
>> 2100 bool
>> 2101 config SYS_SUPPORTS_64BIT_KERNEL
>> 2102 bool
>> 2103 config CPU_SUPPORTS_32BIT_KERNEL
>> 2104 bool
>> 2105 config CPU_SUPPORTS_64BIT_KERNEL
>> 2106 bool
>> 2107 config CPU_SUPPORTS_CPUFREQ
>> 2108 bool
>> 2109 config CPU_SUPPORTS_ADDRWINCFG
>> 2110 bool
>> 2111 config CPU_SUPPORTS_HUGEPAGES
>> 2112 bool
>> 2113 config CPU_SUPPORTS_UNCACHED_ACCELERATED
>> 2114 bool
>> 2115 config MIPS_PGD_C0_CONTEXT
>> 2116 bool
>> 2117 default y if 64BIT && (CPU_MIPSR2 || CPU_MIPSR6) && !CPU_XLP
1307 2118
1308 choice !! 2119 #
1309 prompt "Page size" !! 2120 # Set to y for ptrace access to watch registers.
1310 default ARM64_4K_PAGES !! 2121 #
1311 help !! 2122 config HARDWARE_WATCHPOINTS
1312 Page size (translation granule) con !! 2123 bool
>> 2124 default y if CPU_MIPSR1 || CPU_MIPSR2 || CPU_MIPSR6
1313 2125
1314 config ARM64_4K_PAGES !! 2126 menu "Kernel type"
1315 bool "4KB" <<
1316 select HAVE_PAGE_SIZE_4KB <<
1317 help <<
1318 This feature enables 4KB pages supp <<
1319 2127
1320 config ARM64_16K_PAGES !! 2128 choice
1321 bool "16KB" !! 2129 prompt "Kernel code model"
1322 select HAVE_PAGE_SIZE_16KB <<
1323 help 2130 help
1324 The system will use 16KB pages supp !! 2131 You should only select this option if you have a workload that
1325 requires applications compiled with !! 2132 actually benefits from 64-bit processing or if your machine has
1326 aligned segments. !! 2133 large memory. You will only be presented a single option in this
1327 !! 2134 menu if your system does not support both 32-bit and 64-bit kernels.
1328 config ARM64_64K_PAGES !! 2135
1329 bool "64KB" !! 2136 config 32BIT
1330 select HAVE_PAGE_SIZE_64KB !! 2137 bool "32-bit kernel"
>> 2138 depends on CPU_SUPPORTS_32BIT_KERNEL && SYS_SUPPORTS_32BIT_KERNEL
>> 2139 select TRAD_SIGNALS
1331 help 2140 help
1332 This feature enables 64KB pages sup !! 2141 Select this option if you want to build a 32-bit kernel.
1333 allowing only two levels of page ta <<
1334 look-up. AArch32 emulation requires <<
1335 with 64K aligned segments. <<
1336 <<
1337 endchoice <<
1338 2142
1339 choice !! 2143 config 64BIT
1340 prompt "Virtual address space size" !! 2144 bool "64-bit kernel"
1341 default ARM64_VA_BITS_52 !! 2145 depends on CPU_SUPPORTS_64BIT_KERNEL && SYS_SUPPORTS_64BIT_KERNEL
1342 help 2146 help
1343 Allows choosing one of multiple pos !! 2147 Select this option if you want to build a 64-bit kernel.
1344 space sizes. The level of translati <<
1345 a combination of page size and virt <<
1346 <<
1347 config ARM64_VA_BITS_36 <<
1348 bool "36-bit" if EXPERT <<
1349 depends on PAGE_SIZE_16KB <<
1350 <<
1351 config ARM64_VA_BITS_39 <<
1352 bool "39-bit" <<
1353 depends on PAGE_SIZE_4KB <<
1354 <<
1355 config ARM64_VA_BITS_42 <<
1356 bool "42-bit" <<
1357 depends on PAGE_SIZE_64KB <<
1358 <<
1359 config ARM64_VA_BITS_47 <<
1360 bool "47-bit" <<
1361 depends on PAGE_SIZE_16KB <<
1362 <<
1363 config ARM64_VA_BITS_48 <<
1364 bool "48-bit" <<
1365 <<
1366 config ARM64_VA_BITS_52 <<
1367 bool "52-bit" <<
1368 depends on ARM64_PAN || !ARM64_SW_TTB <<
1369 help <<
1370 Enable 52-bit virtual addressing fo <<
1371 requested via a hint to mmap(). The <<
1372 virtual addresses for its own mappi <<
1373 this feature is available, otherwis <<
1374 <<
1375 NOTE: Enabling 52-bit virtual addre <<
1376 ARMv8.3 Pointer Authentication will <<
1377 reduced from 7 bits to 3 bits, whic <<
1378 impact on its susceptibility to bru <<
1379 <<
1380 If unsure, select 48-bit virtual ad <<
1381 2148
1382 endchoice 2149 endchoice
1383 2150
1384 config ARM64_FORCE_52BIT !! 2151 config KVM_GUEST
1385 bool "Force 52-bit virtual addresses !! 2152 bool "KVM Guest Kernel"
1386 depends on ARM64_VA_BITS_52 && EXPERT !! 2153 depends on BROKEN_ON_SMP
1387 help !! 2154 help
1388 For systems with 52-bit userspace V !! 2155 Select this option if building a guest kernel for KVM (Trap & Emulate)
1389 to maintain compatibility with olde !! 2156 mode.
1390 unless a hint is supplied to mmap. !! 2157
1391 !! 2158 config KVM_GUEST_TIMER_FREQ
1392 This configuration option disables !! 2159 int "Count/Compare Timer Frequency (MHz)"
1393 forces all userspace addresses to b !! 2160 depends on KVM_GUEST
1394 should only enable this configurati !! 2161 default 100
1395 memory management code. If unsure s !! 2162 help
>> 2163 Set this to non-zero if building a guest kernel for KVM to skip RTC
>> 2164 emulation when determining guest CPU Frequency. Instead, the guest's
>> 2165 timer frequency is specified directly.
>> 2166
>> 2167 config MIPS_VA_BITS_48
>> 2168 bool "48 bits virtual memory"
>> 2169 depends on 64BIT
>> 2170 help
>> 2171 Support a maximum at least 48 bits of application virtual
>> 2172 memory. Default is 40 bits or less, depending on the CPU.
>> 2173 For page sizes 16k and above, this option results in a small
>> 2174 memory overhead for page tables. For 4k page size, a fourth
>> 2175 level of page tables is added which imposes both a memory
>> 2176 overhead as well as slower TLB fault handling.
1396 2177
1397 config ARM64_VA_BITS !! 2178 If unsure, say N.
1398 int <<
1399 default 36 if ARM64_VA_BITS_36 <<
1400 default 39 if ARM64_VA_BITS_39 <<
1401 default 42 if ARM64_VA_BITS_42 <<
1402 default 47 if ARM64_VA_BITS_47 <<
1403 default 48 if ARM64_VA_BITS_48 <<
1404 default 52 if ARM64_VA_BITS_52 <<
1405 2179
1406 choice 2180 choice
1407 prompt "Physical address space size" !! 2181 prompt "Kernel page size"
1408 default ARM64_PA_BITS_48 !! 2182 default PAGE_SIZE_4KB
1409 help <<
1410 Choose the maximum physical address <<
1411 support. <<
1412 2183
1413 config ARM64_PA_BITS_48 !! 2184 config PAGE_SIZE_4KB
1414 bool "48-bit" !! 2185 bool "4kB"
1415 depends on ARM64_64K_PAGES || !ARM64_ !! 2186 depends on !CPU_LOONGSON2 && !CPU_LOONGSON3
1416 !! 2187 help
1417 config ARM64_PA_BITS_52 !! 2188 This option select the standard 4kB Linux page size. On some
1418 bool "52-bit" !! 2189 R3000-family processors this is the only available page size. Using
1419 depends on ARM64_64K_PAGES || ARM64_V !! 2190 4kB page size will minimize memory consumption and is therefore
1420 depends on ARM64_PAN || !ARM64_SW_TTB !! 2191 recommended for low memory systems.
1421 help !! 2192
1422 Enable support for a 52-bit physica !! 2193 config PAGE_SIZE_8KB
1423 part of the ARMv8.2-LPA extension. !! 2194 bool "8kB"
1424 !! 2195 depends on CPU_R8000 || CPU_CAVIUM_OCTEON
1425 With this enabled, the kernel will !! 2196 depends on !MIPS_VA_BITS_48
1426 do not support ARMv8.2-LPA, but wit !! 2197 help
1427 minor performance overhead). !! 2198 Using 8kB page size will result in higher performance kernel at
>> 2199 the price of higher memory consumption. This option is available
>> 2200 only on R8000 and cnMIPS processors. Note that you will need a
>> 2201 suitable Linux distribution to support this.
>> 2202
>> 2203 config PAGE_SIZE_16KB
>> 2204 bool "16kB"
>> 2205 depends on !CPU_R3000 && !CPU_TX39XX
>> 2206 help
>> 2207 Using 16kB page size will result in higher performance kernel at
>> 2208 the price of higher memory consumption. This option is available on
>> 2209 all non-R3000 family processors. Note that you will need a suitable
>> 2210 Linux distribution to support this.
>> 2211
>> 2212 config PAGE_SIZE_32KB
>> 2213 bool "32kB"
>> 2214 depends on CPU_CAVIUM_OCTEON
>> 2215 depends on !MIPS_VA_BITS_48
>> 2216 help
>> 2217 Using 32kB page size will result in higher performance kernel at
>> 2218 the price of higher memory consumption. This option is available
>> 2219 only on cnMIPS cores. Note that you will need a suitable Linux
>> 2220 distribution to support this.
>> 2221
>> 2222 config PAGE_SIZE_64KB
>> 2223 bool "64kB"
>> 2224 depends on !CPU_R3000 && !CPU_TX39XX
>> 2225 help
>> 2226 Using 64kB page size will result in higher performance kernel at
>> 2227 the price of higher memory consumption. This option is available on
>> 2228 all non-R3000 family processor. Not that at the time of this
>> 2229 writing this option is still high experimental.
1428 2230
1429 endchoice 2231 endchoice
1430 2232
1431 config ARM64_PA_BITS !! 2233 config FORCE_MAX_ZONEORDER
1432 int !! 2234 int "Maximum zone order"
1433 default 48 if ARM64_PA_BITS_48 !! 2235 range 14 64 if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_64KB
1434 default 52 if ARM64_PA_BITS_52 !! 2236 default "14" if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_64KB
>> 2237 range 13 64 if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_32KB
>> 2238 default "13" if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_32KB
>> 2239 range 12 64 if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_16KB
>> 2240 default "12" if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_16KB
>> 2241 range 11 64
>> 2242 default "11"
>> 2243 help
>> 2244 The kernel memory allocator divides physically contiguous memory
>> 2245 blocks into "zones", where each zone is a power of two number of
>> 2246 pages. This option selects the largest power of two that the kernel
>> 2247 keeps in the memory allocator. If you need to allocate very large
>> 2248 blocks of physically contiguous memory, then you may need to
>> 2249 increase this value.
1435 2250
1436 config ARM64_LPA2 !! 2251 This config option is actually maximum order plus one. For example,
1437 def_bool y !! 2252 a value of 11 means that the largest free memory block is 2^10 pages.
1438 depends on ARM64_PA_BITS_52 && !ARM64 <<
1439 2253
1440 choice !! 2254 The page size is not necessarily 4KB. Keep this in mind
1441 prompt "Endianness" !! 2255 when choosing a value for this option.
1442 default CPU_LITTLE_ENDIAN <<
1443 help <<
1444 Select the endianness of data acces <<
1445 applications will need to be compil <<
1446 that is selected here. <<
1447 2256
1448 config CPU_BIG_ENDIAN !! 2257 config BOARD_SCACHE
1449 bool "Build big-endian kernel" !! 2258 bool
1450 # https://github.com/llvm/llvm-projec <<
1451 depends on AS_IS_GNU || AS_VERSION >= <<
1452 help <<
1453 Say Y if you plan on running a kern <<
1454 2259
1455 config CPU_LITTLE_ENDIAN !! 2260 config IP22_CPU_SCACHE
1456 bool "Build little-endian kernel" !! 2261 bool
1457 help !! 2262 select BOARD_SCACHE
1458 Say Y if you plan on running a kern <<
1459 This is usually the case for distri <<
1460 2263
1461 endchoice !! 2264 #
>> 2265 # Support for a MIPS32 / MIPS64 style S-caches
>> 2266 #
>> 2267 config MIPS_CPU_SCACHE
>> 2268 bool
>> 2269 select BOARD_SCACHE
1462 2270
1463 config SCHED_MC !! 2271 config R5000_CPU_SCACHE
1464 bool "Multi-core scheduler support" !! 2272 bool
1465 help !! 2273 select BOARD_SCACHE
1466 Multi-core scheduler support improv <<
1467 making when dealing with multi-core <<
1468 increased overhead in some places. <<
1469 2274
1470 config SCHED_CLUSTER !! 2275 config RM7000_CPU_SCACHE
1471 bool "Cluster scheduler support" !! 2276 bool
1472 help !! 2277 select BOARD_SCACHE
1473 Cluster scheduler support improves <<
1474 making when dealing with machines t <<
1475 Cluster usually means a couple of C <<
1476 by sharing mid-level caches, last-l <<
1477 busses. <<
1478 2278
1479 config SCHED_SMT !! 2279 config SIBYTE_DMA_PAGEOPS
1480 bool "SMT scheduler support" !! 2280 bool "Use DMA to clear/copy pages"
>> 2281 depends on CPU_SB1
1481 help 2282 help
1482 Improves the CPU scheduler's decisi !! 2283 Instead of using the CPU to zero and copy pages, use a Data Mover
1483 MultiThreading at a cost of slightl !! 2284 channel. These DMA channels are otherwise unused by the standard
1484 places. If unsure say N here. !! 2285 SiByte Linux port. Seems to give a small performance benefit.
1485 2286
1486 config NR_CPUS !! 2287 config CPU_HAS_PREFETCH
1487 int "Maximum number of CPUs (2-4096)" !! 2288 bool
1488 range 2 4096 <<
1489 default "512" <<
1490 2289
1491 config HOTPLUG_CPU !! 2290 config CPU_GENERIC_DUMP_TLB
1492 bool "Support for hot-pluggable CPUs" !! 2291 bool
1493 select GENERIC_IRQ_MIGRATION !! 2292 default y if !(CPU_R3000 || CPU_R8000 || CPU_TX39XX)
>> 2293
>> 2294 config MIPS_FP_SUPPORT
>> 2295 bool "Floating Point support" if EXPERT
>> 2296 default y
1494 help 2297 help
1495 Say Y here to experiment with turni !! 2298 Select y to include support for floating point in the kernel
1496 can be controlled through /sys/devi !! 2299 including initialization of FPU hardware, FP context save & restore
>> 2300 and emulation of an FPU where necessary. Without this support any
>> 2301 userland program attempting to use floating point instructions will
>> 2302 receive a SIGILL.
1497 2303
1498 # Common NUMA Features !! 2304 If you know that your userland will not attempt to use floating point
1499 config NUMA !! 2305 instructions then you can say n here to shrink the kernel a little.
1500 bool "NUMA Memory Allocation and Sche <<
1501 select GENERIC_ARCH_NUMA <<
1502 select OF_NUMA <<
1503 select HAVE_SETUP_PER_CPU_AREA <<
1504 select NEED_PER_CPU_EMBED_FIRST_CHUNK <<
1505 select NEED_PER_CPU_PAGE_FIRST_CHUNK <<
1506 select USE_PERCPU_NUMA_NODE_ID <<
1507 help <<
1508 Enable NUMA (Non-Uniform Memory Acc <<
1509 <<
1510 The kernel will try to allocate mem <<
1511 local memory of the CPU and add som <<
1512 NUMA awareness to the kernel. <<
1513 2306
1514 config NODES_SHIFT !! 2307 If unsure, say y.
1515 int "Maximum NUMA Nodes (as a power o <<
1516 range 1 10 <<
1517 default "4" <<
1518 depends on NUMA <<
1519 help <<
1520 Specify the maximum number of NUMA <<
1521 system. Increases memory reserved <<
1522 2308
1523 source "kernel/Kconfig.hz" !! 2309 config CPU_R2300_FPU
>> 2310 bool
>> 2311 depends on MIPS_FP_SUPPORT
>> 2312 default y if CPU_R3000 || CPU_TX39XX
1524 2313
1525 config ARCH_SPARSEMEM_ENABLE !! 2314 config CPU_R4K_FPU
1526 def_bool y !! 2315 bool
1527 select SPARSEMEM_VMEMMAP_ENABLE !! 2316 depends on MIPS_FP_SUPPORT
1528 select SPARSEMEM_VMEMMAP !! 2317 default y if !CPU_R2300_FPU
1529 2318
1530 config HW_PERF_EVENTS !! 2319 config CPU_R4K_CACHE_TLB
1531 def_bool y !! 2320 bool
1532 depends on ARM_PMU !! 2321 default y if !(CPU_R3000 || CPU_R8000 || CPU_SB1 || CPU_TX39XX || CPU_CAVIUM_OCTEON)
1533 2322
1534 # Supported by clang >= 7.0 or GCC >= 12.0.0 !! 2323 config MIPS_MT_SMP
1535 config CC_HAVE_SHADOW_CALL_STACK !! 2324 bool "MIPS MT SMP support (1 TC on each available VPE)"
1536 def_bool $(cc-option, -fsanitize=shad !! 2325 default y
>> 2326 depends on SYS_SUPPORTS_MULTITHREADING && !CPU_MIPSR6 && !CPU_MICROMIPS
>> 2327 select CPU_MIPSR2_IRQ_VI
>> 2328 select CPU_MIPSR2_IRQ_EI
>> 2329 select SYNC_R4K
>> 2330 select MIPS_MT
>> 2331 select SMP
>> 2332 select SMP_UP
>> 2333 select SYS_SUPPORTS_SMP
>> 2334 select SYS_SUPPORTS_SCHED_SMT
>> 2335 select MIPS_PERF_SHARED_TC_COUNTERS
>> 2336 help
>> 2337 This is a kernel model which is known as SMVP. This is supported
>> 2338 on cores with the MT ASE and uses the available VPEs to implement
>> 2339 virtual processors which supports SMP. This is equivalent to the
>> 2340 Intel Hyperthreading feature. For further information go to
>> 2341 <http://www.imgtec.com/mips/mips-multithreading.asp>.
1537 2342
1538 config PARAVIRT !! 2343 config MIPS_MT
1539 bool "Enable paravirtualization code" !! 2344 bool
1540 help <<
1541 This changes the kernel so it can m <<
1542 under a hypervisor, potentially imp <<
1543 over full virtualization. <<
1544 2345
1545 config PARAVIRT_TIME_ACCOUNTING !! 2346 config SCHED_SMT
1546 bool "Paravirtual steal time accounti !! 2347 bool "SMT (multithreading) scheduler support"
1547 select PARAVIRT !! 2348 depends on SYS_SUPPORTS_SCHED_SMT
>> 2349 default n
1548 help 2350 help
1549 Select this option to enable fine g !! 2351 SMT scheduler support improves the CPU scheduler's decision making
1550 accounting. Time spent executing ot !! 2352 when dealing with MIPS MT enabled cores at a cost of slightly
1551 the current vCPU is discounted from !! 2353 increased overhead in some places. If unsure say N here.
1552 that, there can be a small performa <<
1553 2354
1554 If in doubt, say N here. !! 2355 config SYS_SUPPORTS_SCHED_SMT
>> 2356 bool
1555 2357
1556 config ARCH_SUPPORTS_KEXEC !! 2358 config SYS_SUPPORTS_MULTITHREADING
1557 def_bool PM_SLEEP_SMP !! 2359 bool
1558 2360
1559 config ARCH_SUPPORTS_KEXEC_FILE !! 2361 config MIPS_MT_FPAFF
1560 def_bool y !! 2362 bool "Dynamic FPU affinity for FP-intensive threads"
>> 2363 default y
>> 2364 depends on MIPS_MT_SMP
1561 2365
1562 config ARCH_SELECTS_KEXEC_FILE !! 2366 config MIPSR2_TO_R6_EMULATOR
1563 def_bool y !! 2367 bool "MIPS R2-to-R6 emulator"
1564 depends on KEXEC_FILE !! 2368 depends on CPU_MIPSR6
1565 select HAVE_IMA_KEXEC if IMA !! 2369 depends on MIPS_FP_SUPPORT
>> 2370 default y
>> 2371 help
>> 2372 Choose this option if you want to run non-R6 MIPS userland code.
>> 2373 Even if you say 'Y' here, the emulator will still be disabled by
>> 2374 default. You can enable it using the 'mipsr2emu' kernel option.
>> 2375 The only reason this is a build-time option is to save ~14K from the
>> 2376 final kernel image.
1566 2377
1567 config ARCH_SUPPORTS_KEXEC_SIG !! 2378 config SYS_SUPPORTS_VPE_LOADER
1568 def_bool y !! 2379 bool
>> 2380 depends on SYS_SUPPORTS_MULTITHREADING
>> 2381 help
>> 2382 Indicates that the platform supports the VPE loader, and provides
>> 2383 physical_memsize.
1569 2384
1570 config ARCH_SUPPORTS_KEXEC_IMAGE_VERIFY_SIG !! 2385 config MIPS_VPE_LOADER
1571 def_bool y !! 2386 bool "VPE loader support."
>> 2387 depends on SYS_SUPPORTS_VPE_LOADER && MODULES
>> 2388 select CPU_MIPSR2_IRQ_VI
>> 2389 select CPU_MIPSR2_IRQ_EI
>> 2390 select MIPS_MT
>> 2391 help
>> 2392 Includes a loader for loading an elf relocatable object
>> 2393 onto another VPE and running it.
1572 2394
1573 config ARCH_DEFAULT_KEXEC_IMAGE_VERIFY_SIG !! 2395 config MIPS_VPE_LOADER_CMP
1574 def_bool y !! 2396 bool
>> 2397 default "y"
>> 2398 depends on MIPS_VPE_LOADER && MIPS_CMP
1575 2399
1576 config ARCH_SUPPORTS_CRASH_DUMP !! 2400 config MIPS_VPE_LOADER_MT
1577 def_bool y !! 2401 bool
>> 2402 default "y"
>> 2403 depends on MIPS_VPE_LOADER && !MIPS_CMP
1578 2404
1579 config ARCH_HAS_GENERIC_CRASHKERNEL_RESERVATI !! 2405 config MIPS_VPE_LOADER_TOM
1580 def_bool CRASH_RESERVE !! 2406 bool "Load VPE program into memory hidden from linux"
>> 2407 depends on MIPS_VPE_LOADER
>> 2408 default y
>> 2409 help
>> 2410 The loader can use memory that is present but has been hidden from
>> 2411 Linux using the kernel command line option "mem=xxMB". It's up to
>> 2412 you to ensure the amount you put in the option and the space your
>> 2413 program requires is less or equal to the amount physically present.
1581 2414
1582 config TRANS_TABLE !! 2415 config MIPS_VPE_APSP_API
1583 def_bool y !! 2416 bool "Enable support for AP/SP API (RTLX)"
1584 depends on HIBERNATION || KEXEC_CORE !! 2417 depends on MIPS_VPE_LOADER
1585 2418
1586 config XEN_DOM0 !! 2419 config MIPS_VPE_APSP_API_CMP
1587 def_bool y !! 2420 bool
1588 depends on XEN !! 2421 default "y"
>> 2422 depends on MIPS_VPE_APSP_API && MIPS_CMP
1589 2423
1590 config XEN !! 2424 config MIPS_VPE_APSP_API_MT
1591 bool "Xen guest support on ARM64" !! 2425 bool
1592 depends on ARM64 && OF !! 2426 default "y"
1593 select SWIOTLB_XEN !! 2427 depends on MIPS_VPE_APSP_API && !MIPS_CMP
1594 select PARAVIRT <<
1595 help <<
1596 Say Y if you want to run Linux in a <<
1597 2428
1598 # include/linux/mmzone.h requires the followi !! 2429 config MIPS_CMP
1599 # !! 2430 bool "MIPS CMP framework support (DEPRECATED)"
1600 # MAX_PAGE_ORDER + PAGE_SHIFT <= SECTION_SI !! 2431 depends on SYS_SUPPORTS_MIPS_CMP && !CPU_MIPSR6
1601 # !! 2432 select SMP
1602 # so the maximum value of MAX_PAGE_ORDER is S !! 2433 select SYNC_R4K
1603 # !! 2434 select SYS_SUPPORTS_SMP
1604 # | SECTION_SIZE_BITS | PAGE_SHIFT | m !! 2435 select WEAK_ORDERING
1605 # ----+-------------------+--------------+--- !! 2436 default n
1606 # 4K | 27 | 12 | <<
1607 # 16K | 27 | 14 | <<
1608 # 64K | 29 | 16 | <<
1609 config ARCH_FORCE_MAX_ORDER <<
1610 int <<
1611 default "13" if ARM64_64K_PAGES <<
1612 default "11" if ARM64_16K_PAGES <<
1613 default "10" <<
1614 help 2437 help
1615 The kernel page allocator limits th !! 2438 Select this if you are using a bootloader which implements the "CMP
1616 contiguous allocations. The limit i !! 2439 framework" protocol (ie. YAMON) and want your kernel to make use of
1617 defines the maximal power of two of !! 2440 its ability to start secondary CPUs.
1618 allocated as a single contiguous bl !! 2441
1619 overriding the default setting when !! 2442 Unless you have a specific need, you should use CONFIG_MIPS_CPS
1620 large blocks of physically contiguo !! 2443 instead of this.
1621 !! 2444
1622 The maximal size of allocation cann !! 2445 config MIPS_CPS
1623 section, so the value of MAX_PAGE_O !! 2446 bool "MIPS Coherent Processing System support"
1624 !! 2447 depends on SYS_SUPPORTS_MIPS_CPS
1625 MAX_PAGE_ORDER + PAGE_SHIFT <= SE !! 2448 select MIPS_CM
>> 2449 select MIPS_CPS_PM if HOTPLUG_CPU
>> 2450 select SMP
>> 2451 select SYNC_R4K if (CEVT_R4K || CSRC_R4K)
>> 2452 select SYS_SUPPORTS_HOTPLUG_CPU
>> 2453 select SYS_SUPPORTS_SCHED_SMT if CPU_MIPSR6
>> 2454 select SYS_SUPPORTS_SMP
>> 2455 select WEAK_ORDERING
>> 2456 help
>> 2457 Select this if you wish to run an SMP kernel across multiple cores
>> 2458 within a MIPS Coherent Processing System. When this option is
>> 2459 enabled the kernel will probe for other cores and boot them with
>> 2460 no external assistance. It is safe to enable this when hardware
>> 2461 support is unavailable.
1626 2462
1627 Don't change if unsure. !! 2463 config MIPS_CPS_PM
>> 2464 depends on MIPS_CPS
>> 2465 bool
1628 2466
1629 config UNMAP_KERNEL_AT_EL0 !! 2467 config MIPS_CM
1630 bool "Unmap kernel when running in us !! 2468 bool
1631 default y !! 2469 select MIPS_CPC
1632 help <<
1633 Speculation attacks against some hi <<
1634 be used to bypass MMU permission ch <<
1635 userspace. This can be defended aga <<
1636 when running in userspace, mapping <<
1637 via a trampoline page in the vector <<
1638 2470
1639 If unsure, say Y. !! 2471 config MIPS_CPC
>> 2472 bool
1640 2473
1641 config MITIGATE_SPECTRE_BRANCH_HISTORY !! 2474 config SB1_PASS_2_WORKAROUNDS
1642 bool "Mitigate Spectre style attacks !! 2475 bool
>> 2476 depends on CPU_SB1 && (CPU_SB1_PASS_2_2 || CPU_SB1_PASS_2)
1643 default y 2477 default y
1644 help <<
1645 Speculation attacks against some hi <<
1646 make use of branch history to influ <<
1647 When taking an exception from user- <<
1648 or a firmware call overwrites the b <<
1649 2478
1650 config RODATA_FULL_DEFAULT_ENABLED !! 2479 config SB1_PASS_2_1_WORKAROUNDS
1651 bool "Apply r/o permissions of VM are !! 2480 bool
>> 2481 depends on CPU_SB1 && CPU_SB1_PASS_2
1652 default y 2482 default y
1653 help <<
1654 Apply read-only attributes of VM ar <<
1655 the backing pages as well. This pre <<
1656 from being modified (inadvertently <<
1657 mapping of the same memory page. Th <<
1658 be turned off at runtime by passing <<
1659 with rodata=full if this option is <<
1660 2483
1661 This requires the linear region to <<
1662 which may adversely affect performa <<
1663 2484
1664 config ARM64_SW_TTBR0_PAN !! 2485 choice
1665 bool "Emulate Privileged Access Never !! 2486 prompt "SmartMIPS or microMIPS ASE support"
1666 depends on !KCSAN <<
1667 help <<
1668 Enabling this option prevents the k <<
1669 user-space memory directly by point <<
1670 zeroed area and reserved ASID. The <<
1671 restore the valid TTBR0_EL1 tempora <<
1672 2487
1673 config ARM64_TAGGED_ADDR_ABI !! 2488 config CPU_NEEDS_NO_SMARTMIPS_OR_MICROMIPS
1674 bool "Enable the tagged user addresse !! 2489 bool "None"
1675 default y <<
1676 help 2490 help
1677 When this option is enabled, user a !! 2491 Select this if you want neither microMIPS nor SmartMIPS support
1678 relaxed ABI via prctl() allowing ta <<
1679 to system calls as pointer argument <<
1680 Documentation/arch/arm64/tagged-add <<
1681 2492
1682 menuconfig COMPAT !! 2493 config CPU_HAS_SMARTMIPS
1683 bool "Kernel support for 32-bit EL0" !! 2494 depends on SYS_SUPPORTS_SMARTMIPS
1684 depends on ARM64_4K_PAGES || EXPERT !! 2495 bool "SmartMIPS"
1685 select HAVE_UID16 !! 2496 help
1686 select OLD_SIGSUSPEND3 !! 2497 SmartMIPS is a extension of the MIPS32 architecture aimed at
1687 select COMPAT_OLD_SIGACTION !! 2498 increased security at both hardware and software level for
>> 2499 smartcards. Enabling this option will allow proper use of the
>> 2500 SmartMIPS instructions by Linux applications. However a kernel with
>> 2501 this option will not work on a MIPS core without SmartMIPS core. If
>> 2502 you don't know you probably don't have SmartMIPS and should say N
>> 2503 here.
>> 2504
>> 2505 config CPU_MICROMIPS
>> 2506 depends on 32BIT && SYS_SUPPORTS_MICROMIPS && !CPU_MIPSR6
>> 2507 bool "microMIPS"
1688 help 2508 help
1689 This option enables support for a 3 !! 2509 When this option is enabled the kernel will be built using the
1690 kernel at EL1. AArch32-specific com !! 2510 microMIPS ISA
1691 the user helper functions, VFP supp <<
1692 handled appropriately by the kernel <<
1693 <<
1694 If you use a page size other than 4 <<
1695 that you will only be able to execu <<
1696 with page size aligned segments. <<
1697 <<
1698 If you want to execute 32-bit users <<
1699 <<
1700 if COMPAT <<
1701 2511
1702 config KUSER_HELPERS !! 2512 endchoice
1703 bool "Enable kuser helpers page for 3 <<
1704 default y <<
1705 help <<
1706 Warning: disabling this option may <<
1707 2513
1708 Provide kuser helpers to compat tas !! 2514 config CPU_HAS_MSA
1709 helper code to userspace in read on !! 2515 bool "Support for the MIPS SIMD Architecture"
1710 to allow userspace to be independen !! 2516 depends on CPU_SUPPORTS_MSA
1711 the system. This permits binaries t !! 2517 depends on MIPS_FP_SUPPORT
1712 to ARMv8 without modification. !! 2518 depends on 64BIT || MIPS_O32_FP64_SUPPORT
>> 2519 help
>> 2520 MIPS SIMD Architecture (MSA) introduces 128 bit wide vector registers
>> 2521 and a set of SIMD instructions to operate on them. When this option
>> 2522 is enabled the kernel will support allocating & switching MSA
>> 2523 vector register contexts. If you know that your kernel will only be
>> 2524 running on CPUs which do not support MSA or that your userland will
>> 2525 not be making use of it then you may wish to say N here to reduce
>> 2526 the size & complexity of your kernel.
1713 2527
1714 See Documentation/arch/arm/kernel_u !! 2528 If unsure, say Y.
1715 2529
1716 However, the fixed address nature o !! 2530 config CPU_HAS_WB
1717 by ROP (return orientated programmi !! 2531 bool
1718 exploits. <<
1719 2532
1720 If all of the binaries and librarie !! 2533 config XKS01
1721 are built specifically for your pla !! 2534 bool
1722 these helpers, then you can turn th <<
1723 such exploits. However, in that cas <<
1724 relying on those helpers is run, it <<
1725 2535
1726 Say N here only if you are absolute !! 2536 config CPU_HAS_RIXI
1727 need these helpers; otherwise, the !! 2537 bool
1728 2538
1729 config COMPAT_VDSO !! 2539 config CPU_HAS_LOAD_STORE_LR
1730 bool "Enable vDSO for 32-bit applicat !! 2540 bool
1731 depends on !CPU_BIG_ENDIAN <<
1732 depends on (CC_IS_CLANG && LD_IS_LLD) <<
1733 select GENERIC_COMPAT_VDSO <<
1734 default y <<
1735 help 2541 help
1736 Place in the process address space !! 2542 CPU has support for unaligned load and store instructions:
1737 ELF shared object providing fast im !! 2543 LWL, LWR, SWL, SWR (Load/store word left/right).
1738 and clock_gettime. !! 2544 LDL, LDR, SDL, SDR (Load/store doubleword left/right, for 64bit systems).
>> 2545
>> 2546 #
>> 2547 # Vectored interrupt mode is an R2 feature
>> 2548 #
>> 2549 config CPU_MIPSR2_IRQ_VI
>> 2550 bool
1739 2551
1740 You must have a 32-bit build of gli !! 2552 #
1741 to seamlessly take advantage of thi !! 2553 # Extended interrupt mode is an R2 feature
>> 2554 #
>> 2555 config CPU_MIPSR2_IRQ_EI
>> 2556 bool
1742 2557
1743 config THUMB2_COMPAT_VDSO !! 2558 config CPU_HAS_SYNC
1744 bool "Compile the 32-bit vDSO for Thu !! 2559 bool
1745 depends on COMPAT_VDSO !! 2560 depends on !CPU_R3000
1746 default y 2561 default y
1747 help <<
1748 Compile the compat vDSO with '-mthu <<
1749 otherwise with '-marm'. <<
1750 2562
1751 config COMPAT_ALIGNMENT_FIXUPS !! 2563 #
1752 bool "Fix up misaligned multi-word lo !! 2564 # CPU non-features
>> 2565 #
>> 2566 config CPU_DADDI_WORKAROUNDS
>> 2567 bool
1753 2568
1754 menuconfig ARMV8_DEPRECATED !! 2569 config CPU_R4000_WORKAROUNDS
1755 bool "Emulate deprecated/obsolete ARM !! 2570 bool
1756 depends on SYSCTL !! 2571 select CPU_R4400_WORKAROUNDS
1757 help <<
1758 Legacy software support may require <<
1759 that have been deprecated or obsole <<
1760 2572
1761 Enable this config to enable select !! 2573 config CPU_R4400_WORKAROUNDS
1762 features. !! 2574 bool
1763 2575
1764 If unsure, say Y !! 2576 config MIPS_ASID_SHIFT
>> 2577 int
>> 2578 default 6 if CPU_R3000 || CPU_TX39XX
>> 2579 default 4 if CPU_R8000
>> 2580 default 0
1765 2581
1766 if ARMV8_DEPRECATED !! 2582 config MIPS_ASID_BITS
>> 2583 int
>> 2584 default 0 if MIPS_ASID_BITS_VARIABLE
>> 2585 default 6 if CPU_R3000 || CPU_TX39XX
>> 2586 default 8
1767 2587
1768 config SWP_EMULATION !! 2588 config MIPS_ASID_BITS_VARIABLE
1769 bool "Emulate SWP/SWPB instructions" !! 2589 bool
1770 help <<
1771 ARMv8 obsoletes the use of A32 SWP/ <<
1772 they are always undefined. Say Y he <<
1773 emulation of these instructions for <<
1774 This feature can be controlled at r <<
1775 sysctl which is disabled by default <<
1776 2590
1777 In some older versions of glibc [<= !! 2591 config MIPS_CRC_SUPPORT
1778 trylock() operations with the assum !! 2592 bool
1779 be preempted. This invalid assumpti <<
1780 with SWP emulation enabled, leading <<
1781 application. <<
1782 2593
1783 NOTE: when accessing uncached share !! 2594 #
1784 on an external transaction monitori !! 2595 # - Highmem only makes sense for the 32-bit kernel.
1785 monitor to maintain update atomicit !! 2596 # - The current highmem code will only work properly on physically indexed
1786 implement a global monitor, this op !! 2597 # caches such as R3000, SB1, R7000 or those that look like they're virtually
1787 perform SWP operations to uncached !! 2598 # indexed such as R4000/R4400 SC and MC versions or R10000. So for the
>> 2599 # moment we protect the user and offer the highmem option only on machines
>> 2600 # where it's known to be safe. This will not offer highmem on a few systems
>> 2601 # such as MIPS32 and MIPS64 CPUs which may have virtual and physically
>> 2602 # indexed CPUs but we're playing safe.
>> 2603 # - We use SYS_SUPPORTS_HIGHMEM to offer highmem only for systems where we
>> 2604 # know they might have memory configurations that could make use of highmem
>> 2605 # support.
>> 2606 #
>> 2607 config HIGHMEM
>> 2608 bool "High Memory Support"
>> 2609 depends on 32BIT && CPU_SUPPORTS_HIGHMEM && SYS_SUPPORTS_HIGHMEM && !CPU_MIPS32_3_5_EVA
1788 2610
1789 If unsure, say Y !! 2611 config CPU_SUPPORTS_HIGHMEM
>> 2612 bool
1790 2613
1791 config CP15_BARRIER_EMULATION !! 2614 config SYS_SUPPORTS_HIGHMEM
1792 bool "Emulate CP15 Barrier instructio !! 2615 bool
1793 help <<
1794 The CP15 barrier instructions - CP1 <<
1795 CP15DMB - are deprecated in ARMv8 ( <<
1796 strongly recommended to use the ISB <<
1797 instructions instead. <<
1798 2616
1799 Say Y here to enable software emula !! 2617 config SYS_SUPPORTS_SMARTMIPS
1800 instructions for AArch32 userspace !! 2618 bool
1801 enabled, CP15 barrier usage is trac <<
1802 identify software that needs updati <<
1803 controlled at runtime with the abi. <<
1804 2619
1805 If unsure, say Y !! 2620 config SYS_SUPPORTS_MICROMIPS
>> 2621 bool
1806 2622
1807 config SETEND_EMULATION !! 2623 config SYS_SUPPORTS_MIPS16
1808 bool "Emulate SETEND instruction" !! 2624 bool
1809 help 2625 help
1810 The SETEND instruction alters the d !! 2626 This option must be set if a kernel might be executed on a MIPS16-
1811 AArch32 EL0, and is deprecated in A !! 2627 enabled CPU even if MIPS16 is not actually being used. In other
1812 !! 2628 words, it makes the kernel MIPS16-tolerant.
1813 Say Y here to enable software emula <<
1814 for AArch32 userspace code. This fe <<
1815 at runtime with the abi.setend sysc <<
1816 <<
1817 Note: All the cpus on the system mu <<
1818 for this feature to be enabled. If <<
1819 endian - is hotplugged in after thi <<
1820 be unexpected results in the applic <<
1821 <<
1822 If unsure, say Y <<
1823 endif # ARMV8_DEPRECATED <<
1824 2629
1825 endif # COMPAT !! 2630 config CPU_SUPPORTS_MSA
>> 2631 bool
1826 2632
1827 menu "ARMv8.1 architectural features" !! 2633 config ARCH_FLATMEM_ENABLE
>> 2634 def_bool y
>> 2635 depends on !NUMA && !CPU_LOONGSON2
1828 2636
1829 config ARM64_HW_AFDBM !! 2637 config ARCH_DISCONTIGMEM_ENABLE
1830 bool "Support for hardware updates of !! 2638 bool
1831 default y !! 2639 default y if SGI_IP27
1832 help 2640 help
1833 The ARMv8.1 architecture extensions !! 2641 Say Y to support efficient handling of discontiguous physical memory,
1834 hardware updates of the access and !! 2642 for architectures which are either NUMA (Non-Uniform Memory Access)
1835 table entries. When enabled in TCR_ !! 2643 or have huge holes in the physical address space for other reasons.
1836 capable processors, accesses to pag !! 2644 See <file:Documentation/vm/numa.rst> for more.
1837 set this bit instead of raising an <<
1838 Similarly, writes to read-only page <<
1839 clear the read-only bit (AP[2]) ins <<
1840 permission fault. <<
1841 2645
1842 Kernels built with this configurati !! 2646 config ARCH_SPARSEMEM_ENABLE
1843 to work on pre-ARMv8.1 hardware and !! 2647 bool
1844 minimal. If unsure, say Y. !! 2648 select SPARSEMEM_STATIC
1845 2649
1846 config ARM64_PAN !! 2650 config NUMA
1847 bool "Enable support for Privileged A !! 2651 bool "NUMA Support"
1848 default y !! 2652 depends on SYS_SUPPORTS_NUMA
1849 help 2653 help
1850 Privileged Access Never (PAN; part !! 2654 Say Y to compile the kernel to support NUMA (Non-Uniform Memory
1851 prevents the kernel or hypervisor f !! 2655 Access). This option improves performance on systems with more
1852 memory directly. !! 2656 than two nodes; on two node systems it is generally better to
1853 !! 2657 leave it disabled; on single node systems disable this option
1854 Choosing this option will cause any !! 2658 disabled.
1855 copy_to_user et al) memory access t <<
1856 2659
1857 The feature is detected at runtime, !! 2660 config SYS_SUPPORTS_NUMA
1858 instruction if the cpu does not imp <<
1859 <<
1860 config AS_HAS_LSE_ATOMICS <<
1861 def_bool $(as-instr,.arch_extension l <<
1862 <<
1863 config ARM64_LSE_ATOMICS <<
1864 bool 2661 bool
1865 default ARM64_USE_LSE_ATOMICS <<
1866 depends on AS_HAS_LSE_ATOMICS <<
1867 2662
1868 config ARM64_USE_LSE_ATOMICS !! 2663 config RELOCATABLE
1869 bool "Atomic instructions" !! 2664 bool "Relocatable kernel"
1870 default y !! 2665 depends on SYS_SUPPORTS_RELOCATABLE && (CPU_MIPS32_R2 || CPU_MIPS64_R2 || CPU_MIPS32_R6 || CPU_MIPS64_R6 || CAVIUM_OCTEON_SOC)
1871 help 2666 help
1872 As part of the Large System Extensi !! 2667 This builds a kernel image that retains relocation information
1873 atomic instructions that are design !! 2668 so it can be loaded someplace besides the default 1MB.
1874 very large systems. !! 2669 The relocations make the kernel binary about 15% larger,
>> 2670 but are discarded at runtime
>> 2671
>> 2672 config RELOCATION_TABLE_SIZE
>> 2673 hex "Relocation table size"
>> 2674 depends on RELOCATABLE
>> 2675 range 0x0 0x01000000
>> 2676 default "0x00100000"
>> 2677 ---help---
>> 2678 A table of relocation data will be appended to the kernel binary
>> 2679 and parsed at boot to fix up the relocated kernel.
1875 2680
1876 Say Y here to make use of these ins !! 2681 This option allows the amount of space reserved for the table to be
1877 atomic routines. This incurs a smal !! 2682 adjusted, although the default of 1Mb should be ok in most cases.
1878 not support these instructions and <<
1879 built with binutils >= 2.25 in orde <<
1880 to be used. <<
1881 2683
1882 endmenu # "ARMv8.1 architectural features" !! 2684 The build will fail and a valid size suggested if this is too small.
1883 2685
1884 menu "ARMv8.2 architectural features" !! 2686 If unsure, leave at the default value.
1885 2687
1886 config AS_HAS_ARMV8_2 !! 2688 config RANDOMIZE_BASE
1887 def_bool $(cc-option,-Wa$(comma)-marc !! 2689 bool "Randomize the address of the kernel image"
>> 2690 depends on RELOCATABLE
>> 2691 ---help---
>> 2692 Randomizes the physical and virtual address at which the
>> 2693 kernel image is loaded, as a security feature that
>> 2694 deters exploit attempts relying on knowledge of the location
>> 2695 of kernel internals.
1888 2696
1889 config AS_HAS_SHA3 !! 2697 Entropy is generated using any coprocessor 0 registers available.
1890 def_bool $(as-instr,.arch armv8.2-a+s <<
1891 2698
1892 config ARM64_PMEM !! 2699 The kernel will be offset by up to RANDOMIZE_BASE_MAX_OFFSET.
1893 bool "Enable support for persistent m <<
1894 select ARCH_HAS_PMEM_API <<
1895 select ARCH_HAS_UACCESS_FLUSHCACHE <<
1896 help <<
1897 Say Y to enable support for the per <<
1898 ARMv8.2 DCPoP feature. <<
1899 2700
1900 The feature is detected at runtime, !! 2701 If unsure, say N.
1901 operations if DC CVAP is not suppor <<
1902 DC CVAP itself if the system does n <<
1903 2702
1904 config ARM64_RAS_EXTN !! 2703 config RANDOMIZE_BASE_MAX_OFFSET
1905 bool "Enable support for RAS CPU Exte !! 2704 hex "Maximum kASLR offset" if EXPERT
1906 default y !! 2705 depends on RANDOMIZE_BASE
1907 help !! 2706 range 0x0 0x40000000 if EVA || 64BIT
1908 CPUs that support the Reliability, !! 2707 range 0x0 0x08000000
1909 (RAS) Extensions, part of ARMv8.2 a !! 2708 default "0x01000000"
1910 errors, classify them and report th !! 2709 ---help---
>> 2710 When kASLR is active, this provides the maximum offset that will
>> 2711 be applied to the kernel image. It should be set according to the
>> 2712 amount of physical RAM available in the target system minus
>> 2713 PHYSICAL_START and must be a power of 2.
1911 2714
1912 On CPUs with these extensions syste !! 2715 This is limited by the size of KSEG0, 256Mb on 32-bit or 1Gb with
1913 barriers to determine if faults are !! 2716 EVA or 64-bit. The default is 16Mb.
1914 classification from a new set of re <<
1915 2717
1916 Selecting this feature will allow t !! 2718 config NODES_SHIFT
1917 and access the new registers if the !! 2719 int
1918 Platform RAS features may additiona !! 2720 default "6"
>> 2721 depends on NEED_MULTIPLE_NODES
1919 2722
1920 config ARM64_CNP !! 2723 config HW_PERF_EVENTS
1921 bool "Enable support for Common Not P !! 2724 bool "Enable hardware performance counter support for perf events"
>> 2725 depends on PERF_EVENTS && !OPROFILE && (CPU_MIPS32 || CPU_MIPS64 || CPU_R10000 || CPU_SB1 || CPU_CAVIUM_OCTEON || CPU_XLP || CPU_LOONGSON3)
1922 default y 2726 default y
1923 depends on ARM64_PAN || !ARM64_SW_TTB <<
1924 help 2727 help
1925 Common Not Private (CNP) allows tra !! 2728 Enable hardware performance counter support for perf events. If
1926 be shared between different PEs in !! 2729 disabled, perf events will use software events only.
1927 domain, so the hardware can use thi <<
1928 caching of such entries in the TLB. <<
1929 <<
1930 Selecting this option allows the CN <<
1931 at runtime, and does not affect PEs <<
1932 this feature. <<
1933 2730
1934 endmenu # "ARMv8.2 architectural features" !! 2731 config SMP
1935 !! 2732 bool "Multi-Processing support"
1936 menu "ARMv8.3 architectural features" !! 2733 depends on SYS_SUPPORTS_SMP
1937 <<
1938 config ARM64_PTR_AUTH <<
1939 bool "Enable support for pointer auth <<
1940 default y <<
1941 help 2734 help
1942 Pointer authentication (part of the !! 2735 This enables support for systems with more than one CPU. If you have
1943 instructions for signing and authen !! 2736 a system with only one CPU, say N. If you have a system with more
1944 keys, which can be used to mitigate !! 2737 than one CPU, say Y.
1945 and other attacks. !! 2738
>> 2739 If you say N here, the kernel will run on uni- and multiprocessor
>> 2740 machines, but will use only one CPU of a multiprocessor machine. If
>> 2741 you say Y here, the kernel will run on many, but not all,
>> 2742 uniprocessor machines. On a uniprocessor machine, the kernel
>> 2743 will run faster if you say N here.
1946 2744
1947 This option enables these instructi !! 2745 People using multiprocessor machines who say Y here should also say
1948 Choosing this option will cause the !! 2746 Y to "Enhanced Real Time Clock Support", below.
1949 for each process at exec() time, wi <<
1950 context-switched along with the pro <<
1951 2747
1952 The feature is detected at runtime. !! 2748 See also the SMP-HOWTO available at
1953 hardware it will not be advertised !! 2749 <http://www.tldp.org/docs.html#howto>.
1954 be enabled. <<
1955 2750
1956 If the feature is present on the bo !! 2751 If you don't know what to do here, say N.
1957 the late CPU will be parked. Also, <<
1958 address auth and the late CPU has t <<
1959 but with the feature disabled. On s <<
1960 not be selected. <<
1961 2752
1962 config ARM64_PTR_AUTH_KERNEL !! 2753 config HOTPLUG_CPU
1963 bool "Use pointer authentication for !! 2754 bool "Support for hot-pluggable CPUs"
1964 default y !! 2755 depends on SMP && SYS_SUPPORTS_HOTPLUG_CPU
1965 depends on ARM64_PTR_AUTH <<
1966 depends on (CC_HAS_SIGN_RETURN_ADDRES <<
1967 # Modern compilers insert a .note.gnu <<
1968 # which is only understood by binutil <<
1969 depends on LD_IS_LLD || LD_VERSION >= <<
1970 depends on !CC_IS_CLANG || AS_HAS_CFI <<
1971 depends on (!FUNCTION_GRAPH_TRACER || <<
1972 help 2756 help
1973 If the compiler supports the -mbran !! 2757 Say Y here to allow turning CPUs off and on. CPUs can be
1974 -msign-return-address flag (e.g. GC !! 2758 controlled through /sys/devices/system/cpu.
1975 will cause the kernel itself to be !! 2759 (Note: power management support will enable this option
1976 protection. In this case, and if th !! 2760 automatically on SMP systems. )
1977 support pointer authentication, the !! 2761 Say N if you want to disable CPU hotplug.
1978 disabled with minimal loss of prote <<
1979 2762
1980 This feature works with FUNCTION_GR !! 2763 config SMP_UP
1981 DYNAMIC_FTRACE_WITH_ARGS is enabled !! 2764 bool
1982 2765
1983 config CC_HAS_BRANCH_PROT_PAC_RET !! 2766 config SYS_SUPPORTS_MIPS_CMP
1984 # GCC 9 or later, clang 8 or later !! 2767 bool
1985 def_bool $(cc-option,-mbranch-protect <<
1986 2768
1987 config CC_HAS_SIGN_RETURN_ADDRESS !! 2769 config SYS_SUPPORTS_MIPS_CPS
1988 # GCC 7, 8 !! 2770 bool
1989 def_bool $(cc-option,-msign-return-ad <<
1990 2771
1991 config AS_HAS_ARMV8_3 !! 2772 config SYS_SUPPORTS_SMP
1992 def_bool $(cc-option,-Wa$(comma)-marc !! 2773 bool
1993 2774
1994 config AS_HAS_CFI_NEGATE_RA_STATE !! 2775 config NR_CPUS_DEFAULT_4
1995 def_bool $(as-instr,.cfi_startproc\n. !! 2776 bool
1996 2777
1997 config AS_HAS_LDAPR !! 2778 config NR_CPUS_DEFAULT_8
1998 def_bool $(as-instr,.arch_extension r !! 2779 bool
1999 2780
2000 endmenu # "ARMv8.3 architectural features" !! 2781 config NR_CPUS_DEFAULT_16
>> 2782 bool
2001 2783
2002 menu "ARMv8.4 architectural features" !! 2784 config NR_CPUS_DEFAULT_32
>> 2785 bool
2003 2786
2004 config ARM64_AMU_EXTN !! 2787 config NR_CPUS_DEFAULT_64
2005 bool "Enable support for the Activity !! 2788 bool
2006 default y <<
2007 help <<
2008 The activity monitors extension is <<
2009 by the ARMv8.4 CPU architecture. Th <<
2010 of the activity monitors architectu <<
2011 2789
2012 To enable the use of this extension !! 2790 config NR_CPUS
>> 2791 int "Maximum number of CPUs (2-256)"
>> 2792 range 2 256
>> 2793 depends on SMP
>> 2794 default "4" if NR_CPUS_DEFAULT_4
>> 2795 default "8" if NR_CPUS_DEFAULT_8
>> 2796 default "16" if NR_CPUS_DEFAULT_16
>> 2797 default "32" if NR_CPUS_DEFAULT_32
>> 2798 default "64" if NR_CPUS_DEFAULT_64
>> 2799 help
>> 2800 This allows you to specify the maximum number of CPUs which this
>> 2801 kernel will support. The maximum supported value is 32 for 32-bit
>> 2802 kernel and 64 for 64-bit kernels; the minimum value which makes
>> 2803 sense is 1 for Qemu (useful only for kernel debugging purposes)
>> 2804 and 2 for all others.
>> 2805
>> 2806 This is purely to save memory - each supported CPU adds
>> 2807 approximately eight kilobytes to the kernel image. For best
>> 2808 performance should round up your number of processors to the next
>> 2809 power of two.
2013 2810
2014 Note that for architectural reasons !! 2811 config MIPS_PERF_SHARED_TC_COUNTERS
2015 support when running on CPUs that p !! 2812 bool
2016 extension. The required support is <<
2017 * Version 1.5 and later of the AR <<
2018 2813
2019 For kernels that have this configur !! 2814 config MIPS_NR_CPU_NR_MAP_1024
2020 firmware, you may need to say N her !! 2815 bool
2021 Otherwise you may experience firmwa <<
2022 accessing the counter registers. Ev <<
2023 symptoms, the values returned by th <<
2024 correctly reflect reality. Most com <<
2025 indicating that the counter is not <<
2026 2816
2027 config AS_HAS_ARMV8_4 !! 2817 config MIPS_NR_CPU_NR_MAP
2028 def_bool $(cc-option,-Wa$(comma)-marc !! 2818 int
>> 2819 depends on SMP
>> 2820 default 1024 if MIPS_NR_CPU_NR_MAP_1024
>> 2821 default NR_CPUS if !MIPS_NR_CPU_NR_MAP_1024
2029 2822
2030 config ARM64_TLB_RANGE !! 2823 #
2031 bool "Enable support for tlbi range f !! 2824 # Timer Interrupt Frequency Configuration
2032 default y !! 2825 #
2033 depends on AS_HAS_ARMV8_4 !! 2826
>> 2827 choice
>> 2828 prompt "Timer frequency"
>> 2829 default HZ_250
2034 help 2830 help
2035 ARMv8.4-TLBI provides TLBI invalida !! 2831 Allows the configuration of the timer frequency.
2036 range of input addresses. <<
2037 2832
2038 The feature introduces new assembly !! 2833 config HZ_24
2039 support when binutils >= 2.30. !! 2834 bool "24 HZ" if SYS_SUPPORTS_24HZ || SYS_SUPPORTS_ARBIT_HZ
2040 2835
2041 endmenu # "ARMv8.4 architectural features" !! 2836 config HZ_48
>> 2837 bool "48 HZ" if SYS_SUPPORTS_48HZ || SYS_SUPPORTS_ARBIT_HZ
2042 2838
2043 menu "ARMv8.5 architectural features" !! 2839 config HZ_100
>> 2840 bool "100 HZ" if SYS_SUPPORTS_100HZ || SYS_SUPPORTS_ARBIT_HZ
2044 2841
2045 config AS_HAS_ARMV8_5 !! 2842 config HZ_128
2046 def_bool $(cc-option,-Wa$(comma)-marc !! 2843 bool "128 HZ" if SYS_SUPPORTS_128HZ || SYS_SUPPORTS_ARBIT_HZ
2047 2844
2048 config ARM64_BTI !! 2845 config HZ_250
2049 bool "Branch Target Identification su !! 2846 bool "250 HZ" if SYS_SUPPORTS_250HZ || SYS_SUPPORTS_ARBIT_HZ
2050 default y <<
2051 help <<
2052 Branch Target Identification (part <<
2053 provides a mechanism to limit the s <<
2054 branch instructions such as BR or B <<
2055 2847
2056 To make use of BTI on CPUs that sup !! 2848 config HZ_256
>> 2849 bool "256 HZ" if SYS_SUPPORTS_256HZ || SYS_SUPPORTS_ARBIT_HZ
2057 2850
2058 BTI is intended to provide compleme !! 2851 config HZ_1000
2059 flow integrity protection mechanism !! 2852 bool "1000 HZ" if SYS_SUPPORTS_1000HZ || SYS_SUPPORTS_ARBIT_HZ
2060 authentication mechanism provided a <<
2061 For this reason, it does not make s <<
2062 also enabling support for pointer a <<
2063 enabling this option you should als <<
2064 2853
2065 Userspace binaries must also be spe !! 2854 config HZ_1024
2066 this mechanism. If you say N here !! 2855 bool "1024 HZ" if SYS_SUPPORTS_1024HZ || SYS_SUPPORTS_ARBIT_HZ
2067 BTI, such binaries can still run, b <<
2068 enforcement of branch destinations. <<
2069 2856
2070 config ARM64_BTI_KERNEL !! 2857 endchoice
2071 bool "Use Branch Target Identificatio <<
2072 default y <<
2073 depends on ARM64_BTI <<
2074 depends on ARM64_PTR_AUTH_KERNEL <<
2075 depends on CC_HAS_BRANCH_PROT_PAC_RET <<
2076 # https://gcc.gnu.org/bugzilla/show_b <<
2077 depends on !CC_IS_GCC || GCC_VERSION <<
2078 # https://gcc.gnu.org/bugzilla/show_b <<
2079 depends on !CC_IS_GCC <<
2080 depends on (!FUNCTION_GRAPH_TRACER || <<
2081 help <<
2082 Build the kernel with Branch Target <<
2083 and enable enforcement of this for <<
2084 is enabled and the system supports <<
2085 modular code must have BTI enabled. <<
2086 <<
2087 config CC_HAS_BRANCH_PROT_PAC_RET_BTI <<
2088 # GCC 9 or later, clang 8 or later <<
2089 def_bool $(cc-option,-mbranch-protect <<
2090 2858
2091 config ARM64_E0PD !! 2859 config SYS_SUPPORTS_24HZ
2092 bool "Enable support for E0PD" !! 2860 bool
2093 default y <<
2094 help <<
2095 E0PD (part of the ARMv8.5 extension <<
2096 that EL0 accesses made via TTBR1 al <<
2097 providing similar benefits to KASLR <<
2098 with lower overhead and without dis <<
2099 kernel memory such as SPE. <<
2100 2861
2101 This option enables E0PD for TTBR1 !! 2862 config SYS_SUPPORTS_48HZ
>> 2863 bool
2102 2864
2103 config ARM64_AS_HAS_MTE !! 2865 config SYS_SUPPORTS_100HZ
2104 # Initial support for MTE went in bin !! 2866 bool
2105 # ".arch armv8.5-a+memtag" below. How <<
2106 # as a late addition to the final arc <<
2107 # is only supported in the newer 2.32 <<
2108 # versions, hence the extra "stgm" in <<
2109 def_bool $(as-instr,.arch armv8.5-a+m <<
2110 2867
2111 config ARM64_MTE !! 2868 config SYS_SUPPORTS_128HZ
2112 bool "Memory Tagging Extension suppor !! 2869 bool
2113 default y <<
2114 depends on ARM64_AS_HAS_MTE && ARM64_ <<
2115 depends on AS_HAS_ARMV8_5 <<
2116 depends on AS_HAS_LSE_ATOMICS <<
2117 # Required for tag checking in the ua <<
2118 depends on ARM64_PAN <<
2119 select ARCH_HAS_SUBPAGE_FAULTS <<
2120 select ARCH_USES_HIGH_VMA_FLAGS <<
2121 select ARCH_USES_PG_ARCH_2 <<
2122 select ARCH_USES_PG_ARCH_3 <<
2123 help <<
2124 Memory Tagging (part of the ARMv8.5 <<
2125 architectural support for run-time, <<
2126 various classes of memory error to <<
2127 to eliminate vulnerabilities arisin <<
2128 languages. <<
2129 2870
2130 This option enables the support for !! 2871 config SYS_SUPPORTS_250HZ
2131 Extension at EL0 (i.e. for userspac !! 2872 bool
2132 2873
2133 Selecting this option allows the fe !! 2874 config SYS_SUPPORTS_256HZ
2134 runtime. Any secondary CPU not impl !! 2875 bool
2135 not be allowed a late bring-up. <<
2136 2876
2137 Userspace binaries that want to use !! 2877 config SYS_SUPPORTS_1000HZ
2138 explicitly opt in. The mechanism fo !! 2878 bool
2139 described in: <<
2140 2879
2141 Documentation/arch/arm64/memory-tag !! 2880 config SYS_SUPPORTS_1024HZ
>> 2881 bool
2142 2882
2143 endmenu # "ARMv8.5 architectural features" !! 2883 config SYS_SUPPORTS_ARBIT_HZ
>> 2884 bool
>> 2885 default y if !SYS_SUPPORTS_24HZ && \
>> 2886 !SYS_SUPPORTS_48HZ && \
>> 2887 !SYS_SUPPORTS_100HZ && \
>> 2888 !SYS_SUPPORTS_128HZ && \
>> 2889 !SYS_SUPPORTS_250HZ && \
>> 2890 !SYS_SUPPORTS_256HZ && \
>> 2891 !SYS_SUPPORTS_1000HZ && \
>> 2892 !SYS_SUPPORTS_1024HZ
2144 2893
2145 menu "ARMv8.7 architectural features" !! 2894 config HZ
>> 2895 int
>> 2896 default 24 if HZ_24
>> 2897 default 48 if HZ_48
>> 2898 default 100 if HZ_100
>> 2899 default 128 if HZ_128
>> 2900 default 250 if HZ_250
>> 2901 default 256 if HZ_256
>> 2902 default 1000 if HZ_1000
>> 2903 default 1024 if HZ_1024
>> 2904
>> 2905 config SCHED_HRTICK
>> 2906 def_bool HIGH_RES_TIMERS
>> 2907
>> 2908 config KEXEC
>> 2909 bool "Kexec system call"
>> 2910 select KEXEC_CORE
>> 2911 help
>> 2912 kexec is a system call that implements the ability to shutdown your
>> 2913 current kernel, and to start another kernel. It is like a reboot
>> 2914 but it is independent of the system firmware. And like a reboot
>> 2915 you can start any kernel with it, not just Linux.
>> 2916
>> 2917 The name comes from the similarity to the exec system call.
>> 2918
>> 2919 It is an ongoing process to be certain the hardware in a machine
>> 2920 is properly shutdown, so do not be surprised if this code does not
>> 2921 initially work for you. As of this writing the exact hardware
>> 2922 interface is strongly in flux, so no good recommendation can be
>> 2923 made.
>> 2924
>> 2925 config CRASH_DUMP
>> 2926 bool "Kernel crash dumps"
>> 2927 help
>> 2928 Generate crash dump after being started by kexec.
>> 2929 This should be normally only set in special crash dump kernels
>> 2930 which are loaded in the main kernel with kexec-tools into
>> 2931 a specially reserved region and then later executed after
>> 2932 a crash by kdump/kexec. The crash dump kernel must be compiled
>> 2933 to a memory address not used by the main kernel or firmware using
>> 2934 PHYSICAL_START.
>> 2935
>> 2936 config PHYSICAL_START
>> 2937 hex "Physical address where the kernel is loaded"
>> 2938 default "0xffffffff84000000"
>> 2939 depends on CRASH_DUMP
>> 2940 help
>> 2941 This gives the CKSEG0 or KSEG0 address where the kernel is loaded.
>> 2942 If you plan to use kernel for capturing the crash dump change
>> 2943 this value to start of the reserved region (the "X" value as
>> 2944 specified in the "crashkernel=YM@XM" command line boot parameter
>> 2945 passed to the panic-ed kernel).
>> 2946
>> 2947 config SECCOMP
>> 2948 bool "Enable seccomp to safely compute untrusted bytecode"
>> 2949 depends on PROC_FS
>> 2950 default y
>> 2951 help
>> 2952 This kernel feature is useful for number crunching applications
>> 2953 that may need to compute untrusted bytecode during their
>> 2954 execution. By using pipes or other transports made available to
>> 2955 the process as file descriptors supporting the read/write
>> 2956 syscalls, it's possible to isolate those applications in
>> 2957 their own address space using seccomp. Once seccomp is
>> 2958 enabled via /proc/<pid>/seccomp, it cannot be disabled
>> 2959 and the task is only allowed to execute a few safe syscalls
>> 2960 defined by each seccomp mode.
>> 2961
>> 2962 If unsure, say Y. Only embedded should say N here.
>> 2963
>> 2964 config MIPS_O32_FP64_SUPPORT
>> 2965 bool "Support for O32 binaries using 64-bit FP" if !CPU_MIPSR6
>> 2966 depends on 32BIT || MIPS32_O32
>> 2967 help
>> 2968 When this is enabled, the kernel will support use of 64-bit floating
>> 2969 point registers with binaries using the O32 ABI along with the
>> 2970 EF_MIPS_FP64 ELF header flag (typically built with -mfp64). On
>> 2971 32-bit MIPS systems this support is at the cost of increasing the
>> 2972 size and complexity of the compiled FPU emulator. Thus if you are
>> 2973 running a MIPS32 system and know that none of your userland binaries
>> 2974 will require 64-bit floating point, you may wish to reduce the size
>> 2975 of your kernel & potentially improve FP emulation performance by
>> 2976 saying N here.
>> 2977
>> 2978 Although binutils currently supports use of this flag the details
>> 2979 concerning its effect upon the O32 ABI in userland are still being
>> 2980 worked on. In order to avoid userland becoming dependant upon current
>> 2981 behaviour before the details have been finalised, this option should
>> 2982 be considered experimental and only enabled by those working upon
>> 2983 said details.
2146 2984
2147 config ARM64_EPAN !! 2985 If unsure, say N.
2148 bool "Enable support for Enhanced Pri <<
2149 default y <<
2150 depends on ARM64_PAN <<
2151 help <<
2152 Enhanced Privileged Access Never (E <<
2153 Access Never to be used with Execut <<
2154 2986
2155 The feature is detected at runtime, !! 2987 config USE_OF
2156 if the cpu does not implement the f !! 2988 bool
2157 endmenu # "ARMv8.7 architectural features" !! 2989 select OF
>> 2990 select OF_EARLY_FLATTREE
>> 2991 select IRQ_DOMAIN
2158 2992
2159 menu "ARMv8.9 architectural features" !! 2993 config UHI_BOOT
>> 2994 bool
2160 2995
2161 config ARM64_POE !! 2996 config BUILTIN_DTB
2162 prompt "Permission Overlay Extension" !! 2997 bool
2163 def_bool y <<
2164 select ARCH_USES_HIGH_VMA_FLAGS <<
2165 select ARCH_HAS_PKEYS <<
2166 help <<
2167 The Permission Overlay Extension is <<
2168 Protection Keys. Memory Protection <<
2169 enforcing page-based protections, b <<
2170 of the page tables when an applicat <<
2171 2998
2172 For details, see Documentation/core !! 2999 choice
>> 3000 prompt "Kernel appended dtb support" if USE_OF
>> 3001 default MIPS_NO_APPENDED_DTB
2173 3002
2174 If unsure, say y. !! 3003 config MIPS_NO_APPENDED_DTB
>> 3004 bool "None"
>> 3005 help
>> 3006 Do not enable appended dtb support.
>> 3007
>> 3008 config MIPS_ELF_APPENDED_DTB
>> 3009 bool "vmlinux"
>> 3010 help
>> 3011 With this option, the boot code will look for a device tree binary
>> 3012 DTB) included in the vmlinux ELF section .appended_dtb. By default
>> 3013 it is empty and the DTB can be appended using binutils command
>> 3014 objcopy:
>> 3015
>> 3016 objcopy --update-section .appended_dtb=<filename>.dtb vmlinux
>> 3017
>> 3018 This is meant as a backward compatiblity convenience for those
>> 3019 systems with a bootloader that can't be upgraded to accommodate
>> 3020 the documented boot protocol using a device tree.
>> 3021
>> 3022 config MIPS_RAW_APPENDED_DTB
>> 3023 bool "vmlinux.bin or vmlinuz.bin"
>> 3024 help
>> 3025 With this option, the boot code will look for a device tree binary
>> 3026 DTB) appended to raw vmlinux.bin or vmlinuz.bin.
>> 3027 (e.g. cat vmlinux.bin <filename>.dtb > vmlinux_w_dtb).
>> 3028
>> 3029 This is meant as a backward compatibility convenience for those
>> 3030 systems with a bootloader that can't be upgraded to accommodate
>> 3031 the documented boot protocol using a device tree.
>> 3032
>> 3033 Beware that there is very little in terms of protection against
>> 3034 this option being confused by leftover garbage in memory that might
>> 3035 look like a DTB header after a reboot if no actual DTB is appended
>> 3036 to vmlinux.bin. Do not leave this option active in a production kernel
>> 3037 if you don't intend to always append a DTB.
>> 3038 endchoice
2175 3039
2176 config ARCH_PKEY_BITS !! 3040 choice
2177 int !! 3041 prompt "Kernel command line type" if !CMDLINE_OVERRIDE
2178 default 3 !! 3042 default MIPS_CMDLINE_FROM_DTB if USE_OF && !ATH79 && !MACH_INGENIC && \
>> 3043 !MIPS_MALTA && \
>> 3044 !CAVIUM_OCTEON_SOC
>> 3045 default MIPS_CMDLINE_FROM_BOOTLOADER
>> 3046
>> 3047 config MIPS_CMDLINE_FROM_DTB
>> 3048 depends on USE_OF
>> 3049 bool "Dtb kernel arguments if available"
>> 3050
>> 3051 config MIPS_CMDLINE_DTB_EXTEND
>> 3052 depends on USE_OF
>> 3053 bool "Extend dtb kernel arguments with bootloader arguments"
>> 3054
>> 3055 config MIPS_CMDLINE_FROM_BOOTLOADER
>> 3056 bool "Bootloader kernel arguments if available"
>> 3057
>> 3058 config MIPS_CMDLINE_BUILTIN_EXTEND
>> 3059 depends on CMDLINE_BOOL
>> 3060 bool "Extend builtin kernel arguments with bootloader arguments"
>> 3061 endchoice
2179 3062
2180 endmenu # "ARMv8.9 architectural features" !! 3063 endmenu
2181 3064
2182 config ARM64_SVE !! 3065 config LOCKDEP_SUPPORT
2183 bool "ARM Scalable Vector Extension s !! 3066 bool
2184 default y 3067 default y
2185 help <<
2186 The Scalable Vector Extension (SVE) <<
2187 execution state which complements a <<
2188 of the base architecture to support <<
2189 additional vectorisation opportunit <<
2190 <<
2191 To enable use of this extension on <<
2192 3068
2193 On CPUs that support the SVE2 exten !! 3069 config STACKTRACE_SUPPORT
2194 those too. !! 3070 bool
>> 3071 default y
2195 3072
2196 Note that for architectural reasons !! 3073 config HAVE_LATENCYTOP_SUPPORT
2197 support when running on SVE capable !! 3074 bool
2198 is present in: !! 3075 default y
2199 3076
2200 * version 1.5 and later of the AR !! 3077 config PGTABLE_LEVELS
2201 * the AArch64 boot wrapper since !! 3078 int
2202 ("bootwrapper: SVE: Enable SVE !! 3079 default 4 if PAGE_SIZE_4KB && MIPS_VA_BITS_48
>> 3080 default 3 if 64BIT && !PAGE_SIZE_64KB
>> 3081 default 2
2203 3082
2204 For other firmware implementations, !! 3083 config MIPS_AUTO_PFN_OFFSET
2205 or vendor. !! 3084 bool
2206 3085
2207 If you need the kernel to boot on S !! 3086 menu "Bus options (PCI, PCMCIA, EISA, ISA, TC)"
2208 firmware, you may need to say N her <<
2209 fixed. Otherwise, you may experien <<
2210 booting the kernel. If unsure and <<
2211 symptoms, you should assume that it <<
2212 3087
2213 config ARM64_SME !! 3088 config PCI_DRIVERS_GENERIC
2214 bool "ARM Scalable Matrix Extension s !! 3089 select PCI_DOMAINS_GENERIC if PCI
2215 default y !! 3090 bool
2216 depends on ARM64_SVE <<
2217 depends on BROKEN <<
2218 help <<
2219 The Scalable Matrix Extension (SME) <<
2220 execution state which utilises a su <<
2221 instruction set, together with the <<
2222 register state capable of holding t <<
2223 enable various matrix operations. <<
2224 3091
2225 config ARM64_PSEUDO_NMI !! 3092 config PCI_DRIVERS_LEGACY
2226 bool "Support for NMI-like interrupts !! 3093 def_bool !PCI_DRIVERS_GENERIC
2227 select ARM_GIC_V3 !! 3094 select NO_GENERIC_PCI_IOPORT_MAP
2228 help !! 3095 select PCI_DOMAINS if PCI
2229 Adds support for mimicking Non-Mask <<
2230 GIC interrupt priority. This suppor <<
2231 ARM GIC. <<
2232 3096
2233 This high priority configuration fo !! 3097 #
2234 explicitly enabled by setting the k !! 3098 # ISA support is now enabled via select. Too many systems still have the one
2235 "irqchip.gicv3_pseudo_nmi" to 1. !! 3099 # or other ISA chip on the board that users don't know about so don't expect
>> 3100 # users to choose the right thing ...
>> 3101 #
>> 3102 config ISA
>> 3103 bool
2236 3104
2237 If unsure, say N !! 3105 config TC
>> 3106 bool "TURBOchannel support"
>> 3107 depends on MACH_DECSTATION
>> 3108 help
>> 3109 TURBOchannel is a DEC (now Compaq (now HP)) bus for Alpha and MIPS
>> 3110 processors. TURBOchannel programming specifications are available
>> 3111 at:
>> 3112 <ftp://ftp.hp.com/pub/alphaserver/archive/triadd/>
>> 3113 and:
>> 3114 <http://www.computer-refuge.org/classiccmp/ftp.digital.com/pub/DEC/TriAdd/>
>> 3115 Linux driver support status is documented at:
>> 3116 <http://www.linux-mips.org/wiki/DECstation>
2238 3117
2239 if ARM64_PSEUDO_NMI !! 3118 config MMU
2240 config ARM64_DEBUG_PRIORITY_MASKING !! 3119 bool
2241 bool "Debug interrupt priority maskin !! 3120 default y
2242 help <<
2243 This adds runtime checks to functio <<
2244 interrupts when using priority mask <<
2245 the validity of ICC_PMR_EL1 when ca <<
2246 3121
2247 If unsure, say N !! 3122 config ARCH_MMAP_RND_BITS_MIN
2248 endif # ARM64_PSEUDO_NMI !! 3123 default 12 if 64BIT
>> 3124 default 8
2249 3125
2250 config RELOCATABLE !! 3126 config ARCH_MMAP_RND_BITS_MAX
2251 bool "Build a relocatable kernel imag !! 3127 default 18 if 64BIT
2252 select ARCH_HAS_RELR !! 3128 default 15
2253 default y <<
2254 help <<
2255 This builds the kernel as a Positio <<
2256 which retains all relocation metada <<
2257 kernel binary at runtime to a diffe <<
2258 address it was linked at. <<
2259 Since AArch64 uses the RELA relocat <<
2260 relocation pass at runtime even if <<
2261 same address it was linked at. <<
2262 3129
2263 config RANDOMIZE_BASE !! 3130 config ARCH_MMAP_RND_COMPAT_BITS_MIN
2264 bool "Randomize the address of the ke !! 3131 default 8
2265 select RELOCATABLE <<
2266 help <<
2267 Randomizes the virtual address at w <<
2268 loaded, as a security feature that <<
2269 relying on knowledge of the locatio <<
2270 <<
2271 It is the bootloader's job to provi <<
2272 random u64 value in /chosen/kaslr-s <<
2273 <<
2274 When booting via the UEFI stub, it <<
2275 EFI_RNG_PROTOCOL implementation (if <<
2276 to the kernel proper. In addition, <<
2277 location of the kernel Image as wel <<
2278 3132
2279 If unsure, say N. !! 3133 config ARCH_MMAP_RND_COMPAT_BITS_MAX
>> 3134 default 15
2280 3135
2281 config RANDOMIZE_MODULE_REGION_FULL !! 3136 config I8253
2282 bool "Randomize the module region ove !! 3137 bool
2283 depends on RANDOMIZE_BASE !! 3138 select CLKSRC_I8253
2284 default y !! 3139 select CLKEVT_I8253
2285 help !! 3140 select MIPS_EXTERNAL_TIMER
2286 Randomizes the location of the modu <<
2287 covering the core kernel. This way, <<
2288 to leak information about the locat <<
2289 but it does imply that function cal <<
2290 kernel will need to be resolved via <<
2291 <<
2292 When this option is not set, the mo <<
2293 a limited range that contains the [ <<
2294 core kernel, so branch relocations <<
2295 the region is exhausted. In this pa <<
2296 exhaustion, modules might be able t <<
2297 3141
2298 config CC_HAVE_STACKPROTECTOR_SYSREG !! 3142 config ZONE_DMA
2299 def_bool $(cc-option,-mstack-protecto !! 3143 bool
2300 3144
2301 config STACKPROTECTOR_PER_TASK !! 3145 config ZONE_DMA32
2302 def_bool y !! 3146 bool
2303 depends on STACKPROTECTOR && CC_HAVE_ <<
2304 3147
2305 config UNWIND_PATCH_PAC_INTO_SCS !! 3148 endmenu
2306 bool "Enable shadow call stack dynami <<
2307 # needs Clang with https://github.com <<
2308 depends on CC_IS_CLANG && CLANG_VERSI <<
2309 depends on ARM64_PTR_AUTH_KERNEL && C <<
2310 depends on SHADOW_CALL_STACK <<
2311 select UNWIND_TABLES <<
2312 select DYNAMIC_SCS <<
2313 <<
2314 config ARM64_CONTPTE <<
2315 bool "Contiguous PTE mappings for use <<
2316 depends on TRANSPARENT_HUGEPAGE <<
2317 default y <<
2318 help <<
2319 When enabled, user mappings are con <<
2320 bit, for any mappings that meet the <<
2321 This reduces TLB pressure and impro <<
2322 <<
2323 endmenu # "Kernel Features" <<
2324 <<
2325 menu "Boot options" <<
2326 <<
2327 config ARM64_ACPI_PARKING_PROTOCOL <<
2328 bool "Enable support for the ARM64 AC <<
2329 depends on ACPI <<
2330 help <<
2331 Enable support for the ARM64 ACPI p <<
2332 the kernel will not allow booting t <<
2333 protocol even if the corresponding <<
2334 MADT table. <<
2335 <<
2336 config CMDLINE <<
2337 string "Default kernel command string <<
2338 default "" <<
2339 help <<
2340 Provide a set of default command-li <<
2341 entering them here. As a minimum, y <<
2342 root device (e.g. root=/dev/nfs). <<
2343 3149
2344 choice !! 3150 config TRAD_SIGNALS
2345 prompt "Kernel command line type" !! 3151 bool
2346 depends on CMDLINE != "" <<
2347 default CMDLINE_FROM_BOOTLOADER <<
2348 help <<
2349 Choose how the kernel will handle t <<
2350 command line string. <<
2351 <<
2352 config CMDLINE_FROM_BOOTLOADER <<
2353 bool "Use bootloader kernel arguments <<
2354 help <<
2355 Uses the command-line options passe <<
2356 the boot loader doesn't provide any <<
2357 string provided in CMDLINE will be <<
2358 <<
2359 config CMDLINE_FORCE <<
2360 bool "Always use the default kernel c <<
2361 help <<
2362 Always use the default kernel comma <<
2363 loader passes other arguments to th <<
2364 This is useful if you cannot or don <<
2365 command-line options your boot load <<
2366 3152
2367 endchoice !! 3153 config MIPS32_COMPAT
>> 3154 bool
2368 3155
2369 config EFI_STUB !! 3156 config COMPAT
2370 bool 3157 bool
2371 3158
2372 config EFI !! 3159 config SYSVIPC_COMPAT
2373 bool "UEFI runtime support" !! 3160 bool
2374 depends on OF && !CPU_BIG_ENDIAN <<
2375 depends on KERNEL_MODE_NEON <<
2376 select ARCH_SUPPORTS_ACPI <<
2377 select LIBFDT <<
2378 select UCS2_STRING <<
2379 select EFI_PARAMS_FROM_FDT <<
2380 select EFI_RUNTIME_WRAPPERS <<
2381 select EFI_STUB <<
2382 select EFI_GENERIC_STUB <<
2383 imply IMA_SECURE_AND_OR_TRUSTED_BOOT <<
2384 default y <<
2385 help <<
2386 This option provides support for ru <<
2387 by UEFI firmware (such as non-volat <<
2388 clock, and platform reset). A UEFI <<
2389 allow the kernel to be booted as an <<
2390 is only useful on systems that have <<
2391 3161
2392 config COMPRESSED_INSTALL !! 3162 config MIPS32_O32
2393 bool "Install compressed image by def !! 3163 bool "Kernel support for o32 binaries"
2394 help !! 3164 depends on 64BIT
2395 This makes the regular "make instal !! 3165 select ARCH_WANT_OLD_COMPAT_IPC
2396 image we built, not the legacy unco !! 3166 select COMPAT
>> 3167 select MIPS32_COMPAT
>> 3168 select SYSVIPC_COMPAT if SYSVIPC
>> 3169 help
>> 3170 Select this option if you want to run o32 binaries. These are pure
>> 3171 32-bit binaries as used by the 32-bit Linux/MIPS port. Most of
>> 3172 existing binaries are in this format.
2397 3173
2398 You can check that a compressed ima !! 3174 If unsure, say Y.
2399 "make zinstall" first, and verifyin <<
2400 in your environment before making " <<
2401 you. <<
2402 3175
2403 config DMI !! 3176 config MIPS32_N32
2404 bool "Enable support for SMBIOS (DMI) !! 3177 bool "Kernel support for n32 binaries"
2405 depends on EFI !! 3178 depends on 64BIT
2406 default y !! 3179 select ARCH_WANT_COMPAT_IPC_PARSE_VERSION
2407 help !! 3180 select COMPAT
2408 This enables SMBIOS/DMI feature for !! 3181 select MIPS32_COMPAT
>> 3182 select SYSVIPC_COMPAT if SYSVIPC
>> 3183 help
>> 3184 Select this option if you want to run n32 binaries. These are
>> 3185 64-bit binaries using 32-bit quantities for addressing and certain
>> 3186 data that would normally be 64-bit. They are used in special
>> 3187 cases.
2409 3188
2410 This option is only useful on syste !! 3189 If unsure, say N.
2411 However, even with this option, the <<
2412 continue to boot on existing non-UE <<
2413 3190
2414 endmenu # "Boot options" !! 3191 config BINFMT_ELF32
>> 3192 bool
>> 3193 default y if MIPS32_O32 || MIPS32_N32
>> 3194 select ELFCORE
2415 3195
2416 menu "Power management options" 3196 menu "Power management options"
2417 3197
2418 source "kernel/power/Kconfig" <<
2419 <<
2420 config ARCH_HIBERNATION_POSSIBLE 3198 config ARCH_HIBERNATION_POSSIBLE
2421 def_bool y 3199 def_bool y
2422 depends on CPU_PM !! 3200 depends on SYS_SUPPORTS_HOTPLUG_CPU || !SMP
2423 <<
2424 config ARCH_HIBERNATION_HEADER <<
2425 def_bool y <<
2426 depends on HIBERNATION <<
2427 3201
2428 config ARCH_SUSPEND_POSSIBLE 3202 config ARCH_SUSPEND_POSSIBLE
2429 def_bool y 3203 def_bool y
>> 3204 depends on SYS_SUPPORTS_HOTPLUG_CPU || !SMP
2430 3205
2431 endmenu # "Power management options" !! 3206 source "kernel/power/Kconfig"
2432 3207
2433 menu "CPU Power Management" !! 3208 endmenu
2434 3209
2435 source "drivers/cpuidle/Kconfig" !! 3210 config MIPS_EXTERNAL_TIMER
>> 3211 bool
2436 3212
>> 3213 menu "CPU Power Management"
>> 3214
>> 3215 if CPU_SUPPORTS_CPUFREQ && MIPS_EXTERNAL_TIMER
2437 source "drivers/cpufreq/Kconfig" 3216 source "drivers/cpufreq/Kconfig"
>> 3217 endif
2438 3218
2439 endmenu # "CPU Power Management" !! 3219 source "drivers/cpuidle/Kconfig"
2440 3220
2441 source "drivers/acpi/Kconfig" !! 3221 endmenu
2442 3222
2443 source "arch/arm64/kvm/Kconfig" !! 3223 source "drivers/firmware/Kconfig"
2444 3224
>> 3225 source "arch/mips/kvm/Kconfig"
Linux® is a registered trademark of Linus Torvalds in the United States and other countries.
TOMOYO® is a registered trademark of NTT DATA CORPORATION.