1 # SPDX-License-Identifier: GPL-2.0-only !! 1 # SPDX-License-Identifier: GPL-2.0
2 config ARM64 !! 2 config MIPS
3 def_bool y !! 3 bool
4 select ACPI_APMT if ACPI !! 4 default y
5 select ACPI_CCA_REQUIRED if ACPI !! 5 select ARCH_32BIT_OFF_T if !64BIT
6 select ACPI_GENERIC_GSI if ACPI !! 6 select ARCH_BINFMT_ELF_STATE if MIPS_FP_SUPPORT
7 select ACPI_GTDT if ACPI !! 7 select ARCH_HAS_CPU_FINALIZE_INIT
8 select ACPI_HOTPLUG_CPU if ACPI_PROCES <<
9 select ACPI_IORT if ACPI <<
10 select ACPI_REDUCED_HARDWARE_ONLY if A <<
11 select ACPI_MCFG if (ACPI && PCI) <<
12 select ACPI_SPCR_TABLE if ACPI <<
13 select ACPI_PPTT if ACPI <<
14 select ARCH_HAS_DEBUG_WX <<
15 select ARCH_BINFMT_ELF_EXTRA_PHDRS <<
16 select ARCH_BINFMT_ELF_STATE <<
17 select ARCH_CORRECT_STACKTRACE_ON_KRET <<
18 select ARCH_ENABLE_HUGEPAGE_MIGRATION <<
19 select ARCH_ENABLE_MEMORY_HOTPLUG <<
20 select ARCH_ENABLE_MEMORY_HOTREMOVE <<
21 select ARCH_ENABLE_SPLIT_PMD_PTLOCK if <<
22 select ARCH_ENABLE_THP_MIGRATION if TR <<
23 select ARCH_HAS_CACHE_LINE_SIZE <<
24 select ARCH_HAS_CURRENT_STACK_POINTER <<
25 select ARCH_HAS_DEBUG_VIRTUAL <<
26 select ARCH_HAS_DEBUG_VM_PGTABLE <<
27 select ARCH_HAS_DMA_OPS if XEN <<
28 select ARCH_HAS_DMA_PREP_COHERENT <<
29 select ARCH_HAS_ACPI_TABLE_UPGRADE if <<
30 select ARCH_HAS_FAST_MULTIPLIER <<
31 select ARCH_HAS_FORTIFY_SOURCE 8 select ARCH_HAS_FORTIFY_SOURCE
32 select ARCH_HAS_GCOV_PROFILE_ALL <<
33 select ARCH_HAS_GIGANTIC_PAGE <<
34 select ARCH_HAS_KCOV 9 select ARCH_HAS_KCOV
35 select ARCH_HAS_KERNEL_FPU_SUPPORT if !! 10 select ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE if !EVA
36 select ARCH_HAS_KEEPINITRD !! 11 select ARCH_HAS_PTE_SPECIAL if !(32BIT && CPU_HAS_RIXI)
37 select ARCH_HAS_MEMBARRIER_SYNC_CORE <<
38 select ARCH_HAS_MEM_ENCRYPT <<
39 select ARCH_HAS_NMI_SAFE_THIS_CPU_OPS <<
40 select ARCH_HAS_NON_OVERLAPPING_ADDRES <<
41 select ARCH_HAS_PTE_DEVMAP <<
42 select ARCH_HAS_PTE_SPECIAL <<
43 select ARCH_HAS_HW_PTE_YOUNG <<
44 select ARCH_HAS_SETUP_DMA_OPS <<
45 select ARCH_HAS_SET_DIRECT_MAP <<
46 select ARCH_HAS_SET_MEMORY <<
47 select ARCH_STACKWALK <<
48 select ARCH_HAS_STRICT_KERNEL_RWX <<
49 select ARCH_HAS_STRICT_MODULE_RWX <<
50 select ARCH_HAS_SYNC_DMA_FOR_DEVICE <<
51 select ARCH_HAS_SYNC_DMA_FOR_CPU <<
52 select ARCH_HAS_SYSCALL_WRAPPER <<
53 select ARCH_HAS_TICK_BROADCAST if GENE 12 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
54 select ARCH_HAS_ZONE_DMA_SET if EXPERT !! 13 select ARCH_HAS_UBSAN_SANITIZE_ALL
55 select ARCH_HAVE_ELF_PROT !! 14 select ARCH_SUPPORTS_UPROBES
56 select ARCH_HAVE_NMI_SAFE_CMPXCHG !! 15 select ARCH_USE_BUILTIN_BSWAP
57 select ARCH_HAVE_TRACE_MMIO_ACCESS !! 16 select ARCH_USE_CMPXCHG_LOCKREF if 64BIT
58 select ARCH_INLINE_READ_LOCK if !PREEM <<
59 select ARCH_INLINE_READ_LOCK_BH if !PR <<
60 select ARCH_INLINE_READ_LOCK_IRQ if !P <<
61 select ARCH_INLINE_READ_LOCK_IRQSAVE i <<
62 select ARCH_INLINE_READ_UNLOCK if !PRE <<
63 select ARCH_INLINE_READ_UNLOCK_BH if ! <<
64 select ARCH_INLINE_READ_UNLOCK_IRQ if <<
65 select ARCH_INLINE_READ_UNLOCK_IRQREST <<
66 select ARCH_INLINE_WRITE_LOCK if !PREE <<
67 select ARCH_INLINE_WRITE_LOCK_BH if !P <<
68 select ARCH_INLINE_WRITE_LOCK_IRQ if ! <<
69 select ARCH_INLINE_WRITE_LOCK_IRQSAVE <<
70 select ARCH_INLINE_WRITE_UNLOCK if !PR <<
71 select ARCH_INLINE_WRITE_UNLOCK_BH if <<
72 select ARCH_INLINE_WRITE_UNLOCK_IRQ if <<
73 select ARCH_INLINE_WRITE_UNLOCK_IRQRES <<
74 select ARCH_INLINE_SPIN_TRYLOCK if !PR <<
75 select ARCH_INLINE_SPIN_TRYLOCK_BH if <<
76 select ARCH_INLINE_SPIN_LOCK if !PREEM <<
77 select ARCH_INLINE_SPIN_LOCK_BH if !PR <<
78 select ARCH_INLINE_SPIN_LOCK_IRQ if !P <<
79 select ARCH_INLINE_SPIN_LOCK_IRQSAVE i <<
80 select ARCH_INLINE_SPIN_UNLOCK if !PRE <<
81 select ARCH_INLINE_SPIN_UNLOCK_BH if ! <<
82 select ARCH_INLINE_SPIN_UNLOCK_IRQ if <<
83 select ARCH_INLINE_SPIN_UNLOCK_IRQREST <<
84 select ARCH_KEEP_MEMBLOCK <<
85 select ARCH_MHP_MEMMAP_ON_MEMORY_ENABL <<
86 select ARCH_USE_CMPXCHG_LOCKREF <<
87 select ARCH_USE_GNU_PROPERTY <<
88 select ARCH_USE_MEMTEST <<
89 select ARCH_USE_QUEUED_RWLOCKS 17 select ARCH_USE_QUEUED_RWLOCKS
90 select ARCH_USE_QUEUED_SPINLOCKS 18 select ARCH_USE_QUEUED_SPINLOCKS
91 select ARCH_USE_SYM_ANNOTATIONS !! 19 select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT if MMU
92 select ARCH_SUPPORTS_DEBUG_PAGEALLOC !! 20 select ARCH_WANT_IPC_PARSE_VERSION
93 select ARCH_SUPPORTS_HUGETLBFS <<
94 select ARCH_SUPPORTS_MEMORY_FAILURE <<
95 select ARCH_SUPPORTS_SHADOW_CALL_STACK <<
96 select ARCH_SUPPORTS_LTO_CLANG if CPU_ <<
97 select ARCH_SUPPORTS_LTO_CLANG_THIN <<
98 select ARCH_SUPPORTS_CFI_CLANG <<
99 select ARCH_SUPPORTS_ATOMIC_RMW <<
100 select ARCH_SUPPORTS_INT128 if CC_HAS_ <<
101 select ARCH_SUPPORTS_NUMA_BALANCING <<
102 select ARCH_SUPPORTS_PAGE_TABLE_CHECK <<
103 select ARCH_SUPPORTS_PER_VMA_LOCK <<
104 select ARCH_SUPPORTS_HUGE_PFNMAP if TR <<
105 select ARCH_SUPPORTS_RT <<
106 select ARCH_WANT_BATCHED_UNMAP_TLB_FLU <<
107 select ARCH_WANT_COMPAT_IPC_PARSE_VERS <<
108 select ARCH_WANT_DEFAULT_BPF_JIT <<
109 select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_ <<
110 select ARCH_WANT_FRAME_POINTERS <<
111 select ARCH_WANT_HUGE_PMD_SHARE if ARM <<
112 select ARCH_WANT_LD_ORPHAN_WARN <<
113 select ARCH_WANTS_EXECMEM_LATE if EXEC <<
114 select ARCH_WANTS_NO_INSTR <<
115 select ARCH_WANTS_THP_SWAP if ARM64_4K <<
116 select ARCH_HAS_UBSAN <<
117 select ARM_AMBA <<
118 select ARM_ARCH_TIMER <<
119 select ARM_GIC <<
120 select AUDIT_ARCH_COMPAT_GENERIC <<
121 select ARM_GIC_V2M if PCI <<
122 select ARM_GIC_V3 <<
123 select ARM_GIC_V3_ITS if PCI <<
124 select ARM_PSCI_FW <<
125 select BUILDTIME_TABLE_SORT 21 select BUILDTIME_TABLE_SORT
126 select CLONE_BACKWARDS 22 select CLONE_BACKWARDS
127 select COMMON_CLK !! 23 select CPU_NO_EFFICIENT_FFS if (TARGET_ISA_REV < 1)
128 select CPU_PM if (SUSPEND || CPU_IDLE) !! 24 select CPU_PM if CPU_IDLE
129 select CPUMASK_OFFSTACK if NR_CPUS > 2 !! 25 select GENERIC_ATOMIC64 if !64BIT
130 select CRC32 !! 26 select GENERIC_CLOCKEVENTS
131 select DCACHE_WORD_ACCESS !! 27 select GENERIC_CMOS_UPDATE
132 select DYNAMIC_FTRACE if FUNCTION_TRAC <<
133 select DMA_BOUNCE_UNALIGNED_KMALLOC <<
134 select DMA_DIRECT_REMAP <<
135 select EDAC_SUPPORT <<
136 select FRAME_POINTER <<
137 select FUNCTION_ALIGNMENT_4B <<
138 select FUNCTION_ALIGNMENT_8B if DYNAMI <<
139 select GENERIC_ALLOCATOR <<
140 select GENERIC_ARCH_TOPOLOGY <<
141 select GENERIC_CLOCKEVENTS_BROADCAST <<
142 select GENERIC_CPU_AUTOPROBE 28 select GENERIC_CPU_AUTOPROBE
143 select GENERIC_CPU_DEVICES !! 29 select GENERIC_GETTIMEOFDAY
144 select GENERIC_CPU_VULNERABILITIES !! 30 select GENERIC_IOMAP
145 select GENERIC_EARLY_IOREMAP <<
146 select GENERIC_IDLE_POLL_SETUP <<
147 select GENERIC_IOREMAP <<
148 select GENERIC_IRQ_IPI <<
149 select GENERIC_IRQ_PROBE 31 select GENERIC_IRQ_PROBE
150 select GENERIC_IRQ_SHOW 32 select GENERIC_IRQ_SHOW
151 select GENERIC_IRQ_SHOW_LEVEL !! 33 select GENERIC_ISA_DMA if EISA
152 select GENERIC_LIB_DEVMEM_IS_ALLOWED !! 34 select GENERIC_LIB_ASHLDI3
153 select GENERIC_PCI_IOMAP !! 35 select GENERIC_LIB_ASHRDI3
154 select GENERIC_PTDUMP !! 36 select GENERIC_LIB_CMPDI2
155 select GENERIC_SCHED_CLOCK !! 37 select GENERIC_LIB_LSHRDI3
>> 38 select GENERIC_LIB_UCMPDI2
>> 39 select GENERIC_SCHED_CLOCK if !CAVIUM_OCTEON_SOC
156 select GENERIC_SMP_IDLE_THREAD 40 select GENERIC_SMP_IDLE_THREAD
157 select GENERIC_TIME_VSYSCALL 41 select GENERIC_TIME_VSYSCALL
158 select GENERIC_GETTIMEOFDAY !! 42 select GUP_GET_PTE_LOW_HIGH if CPU_MIPS32 && PHYS_ADDR_T_64BIT
159 select GENERIC_VDSO_TIME_NS !! 43 select HANDLE_DOMAIN_IRQ
160 select HARDIRQS_SW_RESEND <<
161 select HAS_IOPORT <<
162 select HAVE_MOVE_PMD <<
163 select HAVE_MOVE_PUD <<
164 select HAVE_PCI <<
165 select HAVE_ACPI_APEI if (ACPI && EFI) <<
166 select HAVE_ALIGNED_STRUCT_PAGE <<
167 select HAVE_ARCH_AUDITSYSCALL <<
168 select HAVE_ARCH_BITREVERSE <<
169 select HAVE_ARCH_COMPILER_H 44 select HAVE_ARCH_COMPILER_H
170 select HAVE_ARCH_HUGE_VMALLOC <<
171 select HAVE_ARCH_HUGE_VMAP <<
172 select HAVE_ARCH_JUMP_LABEL 45 select HAVE_ARCH_JUMP_LABEL
173 select HAVE_ARCH_JUMP_LABEL_RELATIVE <<
174 select HAVE_ARCH_KASAN <<
175 select HAVE_ARCH_KASAN_VMALLOC <<
176 select HAVE_ARCH_KASAN_SW_TAGS <<
177 select HAVE_ARCH_KASAN_HW_TAGS if ARM6 <<
178 # Some instrumentation may be unsound, <<
179 select HAVE_ARCH_KCSAN if EXPERT <<
180 select HAVE_ARCH_KFENCE <<
181 select HAVE_ARCH_KGDB 46 select HAVE_ARCH_KGDB
182 select HAVE_ARCH_MMAP_RND_BITS !! 47 select HAVE_ARCH_MMAP_RND_BITS if MMU
183 select HAVE_ARCH_MMAP_RND_COMPAT_BITS !! 48 select HAVE_ARCH_MMAP_RND_COMPAT_BITS if MMU && COMPAT
184 select HAVE_ARCH_PREL32_RELOCATIONS <<
185 select HAVE_ARCH_RANDOMIZE_KSTACK_OFFS <<
186 select HAVE_ARCH_SECCOMP_FILTER 49 select HAVE_ARCH_SECCOMP_FILTER
187 select HAVE_ARCH_STACKLEAK <<
188 select HAVE_ARCH_THREAD_STRUCT_WHITELI <<
189 select HAVE_ARCH_TRACEHOOK 50 select HAVE_ARCH_TRACEHOOK
190 select HAVE_ARCH_TRANSPARENT_HUGEPAGE !! 51 select HAVE_ARCH_TRANSPARENT_HUGEPAGE if CPU_SUPPORTS_HUGEPAGES
191 select HAVE_ARCH_VMAP_STACK <<
192 select HAVE_ARM_SMCCC <<
193 select HAVE_ASM_MODVERSIONS 52 select HAVE_ASM_MODVERSIONS
194 select HAVE_EBPF_JIT !! 53 select HAVE_CBPF_JIT if !64BIT && !CPU_MICROMIPS
>> 54 select HAVE_CONTEXT_TRACKING
>> 55 select HAVE_TIF_NOHZ
195 select HAVE_C_RECORDMCOUNT 56 select HAVE_C_RECORDMCOUNT
196 select HAVE_CMPXCHG_DOUBLE <<
197 select HAVE_CMPXCHG_LOCAL <<
198 select HAVE_CONTEXT_TRACKING_USER <<
199 select HAVE_DEBUG_KMEMLEAK 57 select HAVE_DEBUG_KMEMLEAK
>> 58 select HAVE_DEBUG_STACKOVERFLOW
200 select HAVE_DMA_CONTIGUOUS 59 select HAVE_DMA_CONTIGUOUS
201 select HAVE_DYNAMIC_FTRACE 60 select HAVE_DYNAMIC_FTRACE
202 select HAVE_DYNAMIC_FTRACE_WITH_ARGS \ !! 61 select HAVE_EBPF_JIT if 64BIT && !CPU_MICROMIPS && TARGET_ISA_REV >= 2
203 if (GCC_SUPPORTS_DYNAMIC_FTRAC !! 62 select HAVE_EXIT_THREAD
204 CLANG_SUPPORTS_DYNAMIC_FTR !! 63 select HAVE_FAST_GUP
205 select HAVE_DYNAMIC_FTRACE_WITH_DIRECT <<
206 if DYNAMIC_FTRACE_WITH_ARGS && <<
207 select HAVE_DYNAMIC_FTRACE_WITH_CALL_O <<
208 if (DYNAMIC_FTRACE_WITH_ARGS & <<
209 (CC_IS_CLANG || !CC_OPTIMI <<
210 select FTRACE_MCOUNT_USE_PATCHABLE_FUN <<
211 if DYNAMIC_FTRACE_WITH_ARGS <<
212 select HAVE_SAMPLE_FTRACE_DIRECT <<
213 select HAVE_SAMPLE_FTRACE_DIRECT_MULTI <<
214 select HAVE_EFFICIENT_UNALIGNED_ACCESS <<
215 select HAVE_GUP_FAST <<
216 select HAVE_FTRACE_MCOUNT_RECORD 64 select HAVE_FTRACE_MCOUNT_RECORD
217 select HAVE_FUNCTION_TRACER <<
218 select HAVE_FUNCTION_ERROR_INJECTION <<
219 select HAVE_FUNCTION_GRAPH_TRACER 65 select HAVE_FUNCTION_GRAPH_TRACER
220 select HAVE_FUNCTION_GRAPH_RETVAL !! 66 select HAVE_FUNCTION_TRACER
221 select HAVE_GCC_PLUGINS 67 select HAVE_GCC_PLUGINS
222 select HAVE_HARDLOCKUP_DETECTOR_PERF i !! 68 select HAVE_GENERIC_VDSO
223 HW_PERF_EVENTS && HAVE_PERF_EV !! 69 select HAVE_IDE
224 select HAVE_HW_BREAKPOINT if PERF_EVEN <<
225 select HAVE_IOREMAP_PROT 70 select HAVE_IOREMAP_PROT
>> 71 select HAVE_IRQ_EXIT_ON_IRQ_STACK
226 select HAVE_IRQ_TIME_ACCOUNTING 72 select HAVE_IRQ_TIME_ACCOUNTING
>> 73 select HAVE_KPROBES
>> 74 select HAVE_KRETPROBES
>> 75 select HAVE_LD_DEAD_CODE_DATA_ELIMINATION
227 select HAVE_MOD_ARCH_SPECIFIC 76 select HAVE_MOD_ARCH_SPECIFIC
228 select HAVE_NMI 77 select HAVE_NMI
>> 78 select HAVE_OPROFILE
229 select HAVE_PERF_EVENTS 79 select HAVE_PERF_EVENTS
230 select HAVE_PERF_EVENTS_NMI if ARM64_P <<
231 select HAVE_PERF_REGS <<
232 select HAVE_PERF_USER_STACK_DUMP <<
233 select HAVE_PREEMPT_DYNAMIC_KEY <<
234 select HAVE_REGS_AND_STACK_ACCESS_API 80 select HAVE_REGS_AND_STACK_ACCESS_API
235 select HAVE_POSIX_CPU_TIMERS_TASK_WORK <<
236 select HAVE_FUNCTION_ARG_ACCESS_API <<
237 select MMU_GATHER_RCU_TABLE_FREE <<
238 select HAVE_RSEQ 81 select HAVE_RSEQ
239 select HAVE_RUST if RUSTC_SUPPORTS_ARM !! 82 select HAVE_SPARSE_SYSCALL_NR
240 select HAVE_STACKPROTECTOR 83 select HAVE_STACKPROTECTOR
241 select HAVE_SYSCALL_TRACEPOINTS 84 select HAVE_SYSCALL_TRACEPOINTS
242 select HAVE_KPROBES !! 85 select HAVE_VIRT_CPU_ACCOUNTING_GEN if 64BIT || !SMP
243 select HAVE_KRETPROBES <<
244 select HAVE_GENERIC_VDSO <<
245 select HOTPLUG_CORE_SYNC_DEAD if HOTPL <<
246 select IRQ_DOMAIN <<
247 select IRQ_FORCED_THREADING 86 select IRQ_FORCED_THREADING
248 select KASAN_VMALLOC if KASAN !! 87 select ISA if EISA
249 select LOCK_MM_AND_FIND_VMA !! 88 select MODULES_USE_ELF_REL if MODULES
250 select MODULES_USE_ELF_RELA !! 89 select MODULES_USE_ELF_RELA if MODULES && 64BIT
251 select NEED_DMA_MAP_STATE !! 90 select PERF_USE_VMALLOC
252 select NEED_SG_DMA_LENGTH !! 91 select PCI_MSI_ARCH_FALLBACKS if PCI_MSI
253 select OF !! 92 select RTC_LIB
254 select OF_EARLY_FLATTREE !! 93 select SET_FS
255 select PCI_DOMAINS_GENERIC if PCI <<
256 select PCI_ECAM if (ACPI && PCI) <<
257 select PCI_SYSCALL if PCI <<
258 select POWER_RESET <<
259 select POWER_SUPPLY <<
260 select SPARSE_IRQ <<
261 select SWIOTLB <<
262 select SYSCTL_EXCEPTION_TRACE 94 select SYSCTL_EXCEPTION_TRACE
263 select THREAD_INFO_IN_TASK !! 95 select VIRT_TO_BUS
264 select HAVE_ARCH_USERFAULTFD_MINOR if <<
265 select HAVE_ARCH_USERFAULTFD_WP if USE <<
266 select TRACE_IRQFLAGS_SUPPORT <<
267 select TRACE_IRQFLAGS_NMI_SUPPORT <<
268 select HAVE_SOFTIRQ_ON_OWN_STACK <<
269 select USER_STACKTRACE_SUPPORT <<
270 select VDSO_GETRANDOM <<
271 help <<
272 ARM 64-bit (AArch64) Linux support. <<
273 <<
274 config RUSTC_SUPPORTS_ARM64 <<
275 def_bool y <<
276 depends on CPU_LITTLE_ENDIAN <<
277 # Shadow call stack is only supported <<
278 # <<
279 # When using the UNWIND_PATCH_PAC_INTO <<
280 # required due to use of the -Zfixed-x <<
281 # <<
282 # Otherwise, rustc version 1.82+ is re <<
283 # -Zsanitizer=shadow-call-stack flag. <<
284 depends on !SHADOW_CALL_STACK || RUSTC <<
285 <<
286 config CLANG_SUPPORTS_DYNAMIC_FTRACE_WITH_ARGS <<
287 def_bool CC_IS_CLANG <<
288 # https://github.com/ClangBuiltLinux/l <<
289 depends on AS_IS_GNU || (AS_IS_LLVM && <<
290 <<
291 config GCC_SUPPORTS_DYNAMIC_FTRACE_WITH_ARGS <<
292 def_bool CC_IS_GCC <<
293 depends on $(cc-option,-fpatchable-fun <<
294 96
295 config 64BIT !! 97 config MIPS_FIXUP_BIGPHYS_ADDR
296 def_bool y !! 98 bool
297 99
298 config MMU !! 100 config MIPS_GENERIC
299 def_bool y !! 101 bool
300 102
301 config ARM64_CONT_PTE_SHIFT !! 103 config MACH_INGENIC
302 int !! 104 bool
303 default 5 if PAGE_SIZE_64KB !! 105 select SYS_SUPPORTS_32BIT_KERNEL
304 default 7 if PAGE_SIZE_16KB !! 106 select SYS_SUPPORTS_LITTLE_ENDIAN
305 default 4 !! 107 select SYS_SUPPORTS_ZBOOT
>> 108 select DMA_NONCOHERENT
>> 109 select IRQ_MIPS_CPU
>> 110 select PINCTRL
>> 111 select GPIOLIB
>> 112 select COMMON_CLK
>> 113 select GENERIC_IRQ_CHIP
>> 114 select BUILTIN_DTB if MIPS_NO_APPENDED_DTB
>> 115 select USE_OF
>> 116 select CPU_SUPPORTS_CPUFREQ
>> 117 select MIPS_EXTERNAL_TIMER
306 118
307 config ARM64_CONT_PMD_SHIFT !! 119 menu "Machine selection"
308 int <<
309 default 5 if PAGE_SIZE_64KB <<
310 default 5 if PAGE_SIZE_16KB <<
311 default 4 <<
312 120
313 config ARCH_MMAP_RND_BITS_MIN !! 121 choice
314 default 14 if PAGE_SIZE_64KB !! 122 prompt "System type"
315 default 16 if PAGE_SIZE_16KB !! 123 default MIPS_GENERIC_KERNEL
316 default 18 <<
317 124
318 # max bits determined by the following formula !! 125 config MIPS_GENERIC_KERNEL
319 # VA_BITS - PAGE_SHIFT - 3 !! 126 bool "Generic board-agnostic MIPS kernel"
320 config ARCH_MMAP_RND_BITS_MAX !! 127 select MIPS_GENERIC
321 default 19 if ARM64_VA_BITS=36 !! 128 select BOOT_RAW
322 default 24 if ARM64_VA_BITS=39 !! 129 select BUILTIN_DTB
323 default 27 if ARM64_VA_BITS=42 !! 130 select CEVT_R4K
324 default 30 if ARM64_VA_BITS=47 !! 131 select CLKSRC_MIPS_GIC
325 default 29 if ARM64_VA_BITS=48 && ARM6 !! 132 select COMMON_CLK
326 default 31 if ARM64_VA_BITS=48 && ARM6 !! 133 select CPU_MIPSR2_IRQ_EI
327 default 33 if ARM64_VA_BITS=48 !! 134 select CPU_MIPSR2_IRQ_VI
328 default 14 if ARM64_64K_PAGES !! 135 select CSRC_R4K
329 default 16 if ARM64_16K_PAGES !! 136 select DMA_PERDEV_COHERENT
330 default 18 !! 137 select HAVE_PCI
>> 138 select IRQ_MIPS_CPU
>> 139 select MIPS_AUTO_PFN_OFFSET
>> 140 select MIPS_CPU_SCACHE
>> 141 select MIPS_GIC
>> 142 select MIPS_L1_CACHE_SHIFT_7
>> 143 select NO_EXCEPT_FILL
>> 144 select PCI_DRIVERS_GENERIC
>> 145 select SMP_UP if SMP
>> 146 select SWAP_IO_SPACE
>> 147 select SYS_HAS_CPU_MIPS32_R1
>> 148 select SYS_HAS_CPU_MIPS32_R2
>> 149 select SYS_HAS_CPU_MIPS32_R6
>> 150 select SYS_HAS_CPU_MIPS64_R1
>> 151 select SYS_HAS_CPU_MIPS64_R2
>> 152 select SYS_HAS_CPU_MIPS64_R6
>> 153 select SYS_SUPPORTS_32BIT_KERNEL
>> 154 select SYS_SUPPORTS_64BIT_KERNEL
>> 155 select SYS_SUPPORTS_BIG_ENDIAN
>> 156 select SYS_SUPPORTS_HIGHMEM
>> 157 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 158 select SYS_SUPPORTS_MICROMIPS
>> 159 select SYS_SUPPORTS_MIPS16
>> 160 select SYS_SUPPORTS_MIPS_CPS
>> 161 select SYS_SUPPORTS_MULTITHREADING
>> 162 select SYS_SUPPORTS_RELOCATABLE
>> 163 select SYS_SUPPORTS_SMARTMIPS
>> 164 select SYS_SUPPORTS_ZBOOT
>> 165 select UHI_BOOT
>> 166 select USB_EHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
>> 167 select USB_EHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 168 select USB_OHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
>> 169 select USB_OHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 170 select USB_UHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
>> 171 select USB_UHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 172 select USE_OF
>> 173 help
>> 174 Select this to build a kernel which aims to support multiple boards,
>> 175 generally using a flattened device tree passed from the bootloader
>> 176 using the boot protocol defined in the UHI (Unified Hosting
>> 177 Interface) specification.
>> 178
>> 179 config MIPS_ALCHEMY
>> 180 bool "Alchemy processor based machines"
>> 181 select PHYS_ADDR_T_64BIT
>> 182 select CEVT_R4K
>> 183 select CSRC_R4K
>> 184 select IRQ_MIPS_CPU
>> 185 select DMA_MAYBE_COHERENT # Au1000,1500,1100 aren't, rest is
>> 186 select MIPS_FIXUP_BIGPHYS_ADDR if PCI
>> 187 select SYS_HAS_CPU_MIPS32_R1
>> 188 select SYS_SUPPORTS_32BIT_KERNEL
>> 189 select SYS_SUPPORTS_APM_EMULATION
>> 190 select GPIOLIB
>> 191 select SYS_SUPPORTS_ZBOOT
>> 192 select COMMON_CLK
331 193
332 config ARCH_MMAP_RND_COMPAT_BITS_MIN !! 194 config AR7
333 default 7 if ARM64_64K_PAGES !! 195 bool "Texas Instruments AR7"
334 default 9 if ARM64_16K_PAGES !! 196 select BOOT_ELF32
335 default 11 !! 197 select DMA_NONCOHERENT
>> 198 select CEVT_R4K
>> 199 select CSRC_R4K
>> 200 select IRQ_MIPS_CPU
>> 201 select NO_EXCEPT_FILL
>> 202 select SWAP_IO_SPACE
>> 203 select SYS_HAS_CPU_MIPS32_R1
>> 204 select SYS_HAS_EARLY_PRINTK
>> 205 select SYS_SUPPORTS_32BIT_KERNEL
>> 206 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 207 select SYS_SUPPORTS_MIPS16
>> 208 select SYS_SUPPORTS_ZBOOT_UART16550
>> 209 select GPIOLIB
>> 210 select VLYNQ
>> 211 select HAVE_LEGACY_CLK
>> 212 help
>> 213 Support for the Texas Instruments AR7 System-on-a-Chip
>> 214 family: TNETD7100, 7200 and 7300.
>> 215
>> 216 config ATH25
>> 217 bool "Atheros AR231x/AR531x SoC support"
>> 218 select CEVT_R4K
>> 219 select CSRC_R4K
>> 220 select DMA_NONCOHERENT
>> 221 select IRQ_MIPS_CPU
>> 222 select IRQ_DOMAIN
>> 223 select SYS_HAS_CPU_MIPS32_R1
>> 224 select SYS_SUPPORTS_BIG_ENDIAN
>> 225 select SYS_SUPPORTS_32BIT_KERNEL
>> 226 select SYS_HAS_EARLY_PRINTK
>> 227 help
>> 228 Support for Atheros AR231x and Atheros AR531x based boards
>> 229
>> 230 config ATH79
>> 231 bool "Atheros AR71XX/AR724X/AR913X based boards"
>> 232 select ARCH_HAS_RESET_CONTROLLER
>> 233 select BOOT_RAW
>> 234 select CEVT_R4K
>> 235 select CSRC_R4K
>> 236 select DMA_NONCOHERENT
>> 237 select GPIOLIB
>> 238 select PINCTRL
>> 239 select COMMON_CLK
>> 240 select IRQ_MIPS_CPU
>> 241 select SYS_HAS_CPU_MIPS32_R2
>> 242 select SYS_HAS_EARLY_PRINTK
>> 243 select SYS_SUPPORTS_32BIT_KERNEL
>> 244 select SYS_SUPPORTS_BIG_ENDIAN
>> 245 select SYS_SUPPORTS_MIPS16
>> 246 select SYS_SUPPORTS_ZBOOT_UART_PROM
>> 247 select USE_OF
>> 248 select USB_EHCI_ROOT_HUB_TT if USB_EHCI_HCD_PLATFORM
>> 249 help
>> 250 Support for the Atheros AR71XX/AR724X/AR913X SoCs.
>> 251
>> 252 config BMIPS_GENERIC
>> 253 bool "Broadcom Generic BMIPS kernel"
>> 254 select ARCH_HAS_SYNC_DMA_FOR_CPU_ALL
>> 255 select ARCH_HAS_PHYS_TO_DMA
>> 256 select BOOT_RAW
>> 257 select NO_EXCEPT_FILL
>> 258 select USE_OF
>> 259 select CEVT_R4K
>> 260 select CSRC_R4K
>> 261 select SYNC_R4K
>> 262 select COMMON_CLK
>> 263 select BCM6345_L1_IRQ
>> 264 select BCM7038_L1_IRQ
>> 265 select BCM7120_L2_IRQ
>> 266 select BRCMSTB_L2_IRQ
>> 267 select IRQ_MIPS_CPU
>> 268 select DMA_NONCOHERENT
>> 269 select SYS_SUPPORTS_32BIT_KERNEL
>> 270 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 271 select SYS_SUPPORTS_BIG_ENDIAN
>> 272 select SYS_SUPPORTS_HIGHMEM
>> 273 select SYS_HAS_CPU_BMIPS32_3300
>> 274 select SYS_HAS_CPU_BMIPS4350
>> 275 select SYS_HAS_CPU_BMIPS4380
>> 276 select SYS_HAS_CPU_BMIPS5000
>> 277 select SWAP_IO_SPACE
>> 278 select USB_EHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
>> 279 select USB_EHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 280 select USB_OHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
>> 281 select USB_OHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 282 select HARDIRQS_SW_RESEND
>> 283 help
>> 284 Build a generic DT-based kernel image that boots on select
>> 285 BCM33xx cable modem chips, BCM63xx DSL chips, and BCM7xxx set-top
>> 286 box chips. Note that CONFIG_CPU_BIG_ENDIAN/CONFIG_CPU_LITTLE_ENDIAN
>> 287 must be set appropriately for your board.
>> 288
>> 289 config BCM47XX
>> 290 bool "Broadcom BCM47XX based boards"
>> 291 select BOOT_RAW
>> 292 select CEVT_R4K
>> 293 select CSRC_R4K
>> 294 select DMA_NONCOHERENT
>> 295 select HAVE_PCI
>> 296 select IRQ_MIPS_CPU
>> 297 select SYS_HAS_CPU_MIPS32_R1
>> 298 select NO_EXCEPT_FILL
>> 299 select SYS_SUPPORTS_32BIT_KERNEL
>> 300 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 301 select SYS_SUPPORTS_MIPS16
>> 302 select SYS_SUPPORTS_ZBOOT
>> 303 select SYS_HAS_EARLY_PRINTK
>> 304 select USE_GENERIC_EARLY_PRINTK_8250
>> 305 select GPIOLIB
>> 306 select LEDS_GPIO_REGISTER
>> 307 select BCM47XX_NVRAM
>> 308 select BCM47XX_SPROM
>> 309 select BCM47XX_SSB if !BCM47XX_BCMA
>> 310 help
>> 311 Support for BCM47XX based boards
>> 312
>> 313 config BCM63XX
>> 314 bool "Broadcom BCM63XX based boards"
>> 315 select BOOT_RAW
>> 316 select CEVT_R4K
>> 317 select CSRC_R4K
>> 318 select SYNC_R4K
>> 319 select DMA_NONCOHERENT
>> 320 select IRQ_MIPS_CPU
>> 321 select SYS_SUPPORTS_32BIT_KERNEL
>> 322 select SYS_SUPPORTS_BIG_ENDIAN
>> 323 select SYS_HAS_EARLY_PRINTK
>> 324 select SYS_HAS_CPU_BMIPS32_3300
>> 325 select SYS_HAS_CPU_BMIPS4350
>> 326 select SYS_HAS_CPU_BMIPS4380
>> 327 select SWAP_IO_SPACE
>> 328 select GPIOLIB
>> 329 select MIPS_L1_CACHE_SHIFT_4
>> 330 select CLKDEV_LOOKUP
>> 331 select HAVE_LEGACY_CLK
>> 332 help
>> 333 Support for BCM63XX based boards
>> 334
>> 335 config MIPS_COBALT
>> 336 bool "Cobalt Server"
>> 337 select CEVT_R4K
>> 338 select CSRC_R4K
>> 339 select CEVT_GT641XX
>> 340 select DMA_NONCOHERENT
>> 341 select FORCE_PCI
>> 342 select I8253
>> 343 select I8259
>> 344 select IRQ_MIPS_CPU
>> 345 select IRQ_GT641XX
>> 346 select PCI_GT64XXX_PCI0
>> 347 select SYS_HAS_CPU_NEVADA
>> 348 select SYS_HAS_EARLY_PRINTK
>> 349 select SYS_SUPPORTS_32BIT_KERNEL
>> 350 select SYS_SUPPORTS_64BIT_KERNEL
>> 351 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 352 select USE_GENERIC_EARLY_PRINTK_8250
>> 353
>> 354 config MACH_DECSTATION
>> 355 bool "DECstations"
>> 356 select BOOT_ELF32
>> 357 select CEVT_DS1287
>> 358 select CEVT_R4K if CPU_R4X00
>> 359 select CSRC_IOASIC
>> 360 select CSRC_R4K if CPU_R4X00
>> 361 select CPU_DADDI_WORKAROUNDS if 64BIT
>> 362 select CPU_R4000_WORKAROUNDS if 64BIT
>> 363 select CPU_R4400_WORKAROUNDS if 64BIT
>> 364 select DMA_NONCOHERENT
>> 365 select NO_IOPORT_MAP
>> 366 select IRQ_MIPS_CPU
>> 367 select SYS_HAS_CPU_R3000
>> 368 select SYS_HAS_CPU_R4X00
>> 369 select SYS_SUPPORTS_32BIT_KERNEL
>> 370 select SYS_SUPPORTS_64BIT_KERNEL
>> 371 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 372 select SYS_SUPPORTS_128HZ
>> 373 select SYS_SUPPORTS_256HZ
>> 374 select SYS_SUPPORTS_1024HZ
>> 375 select MIPS_L1_CACHE_SHIFT_4
>> 376 help
>> 377 This enables support for DEC's MIPS based workstations. For details
>> 378 see the Linux/MIPS FAQ on <http://www.linux-mips.org/> and the
>> 379 DECstation porting pages on <http://decstation.unix-ag.org/>.
>> 380
>> 381 If you have one of the following DECstation Models you definitely
>> 382 want to choose R4xx0 for the CPU Type:
>> 383
>> 384 DECstation 5000/50
>> 385 DECstation 5000/150
>> 386 DECstation 5000/260
>> 387 DECsystem 5900/260
>> 388
>> 389 otherwise choose R3000.
>> 390
>> 391 config MACH_JAZZ
>> 392 bool "Jazz family of machines"
>> 393 select ARC_MEMORY
>> 394 select ARC_PROMLIB
>> 395 select ARCH_MIGHT_HAVE_PC_PARPORT
>> 396 select ARCH_MIGHT_HAVE_PC_SERIO
>> 397 select DMA_OPS
>> 398 select FW_ARC
>> 399 select FW_ARC32
>> 400 select ARCH_MAY_HAVE_PC_FDC
>> 401 select CEVT_R4K
>> 402 select CSRC_R4K
>> 403 select DEFAULT_SGI_PARTITION if CPU_BIG_ENDIAN
>> 404 select GENERIC_ISA_DMA
>> 405 select HAVE_PCSPKR_PLATFORM
>> 406 select IRQ_MIPS_CPU
>> 407 select I8253
>> 408 select I8259
>> 409 select ISA
>> 410 select SYS_HAS_CPU_R4X00
>> 411 select SYS_SUPPORTS_32BIT_KERNEL
>> 412 select SYS_SUPPORTS_64BIT_KERNEL
>> 413 select SYS_SUPPORTS_100HZ
>> 414 help
>> 415 This a family of machines based on the MIPS R4030 chipset which was
>> 416 used by several vendors to build RISC/os and Windows NT workstations.
>> 417 Members include the Acer PICA, MIPS Magnum 4000, MIPS Millennium and
>> 418 Olivetti M700-10 workstations.
>> 419
>> 420 config MACH_INGENIC_SOC
>> 421 bool "Ingenic SoC based machines"
>> 422 select MIPS_GENERIC
>> 423 select MACH_INGENIC
>> 424 select SYS_SUPPORTS_ZBOOT_UART16550
>> 425 select CPU_SUPPORTS_CPUFREQ
>> 426 select MIPS_EXTERNAL_TIMER
>> 427
>> 428 config LANTIQ
>> 429 bool "Lantiq based platforms"
>> 430 select DMA_NONCOHERENT
>> 431 select IRQ_MIPS_CPU
>> 432 select CEVT_R4K
>> 433 select CSRC_R4K
>> 434 select SYS_HAS_CPU_MIPS32_R1
>> 435 select SYS_HAS_CPU_MIPS32_R2
>> 436 select SYS_SUPPORTS_BIG_ENDIAN
>> 437 select SYS_SUPPORTS_32BIT_KERNEL
>> 438 select SYS_SUPPORTS_MIPS16
>> 439 select SYS_SUPPORTS_MULTITHREADING
>> 440 select SYS_SUPPORTS_VPE_LOADER
>> 441 select SYS_HAS_EARLY_PRINTK
>> 442 select GPIOLIB
>> 443 select SWAP_IO_SPACE
>> 444 select BOOT_RAW
>> 445 select CLKDEV_LOOKUP
>> 446 select HAVE_LEGACY_CLK
>> 447 select USE_OF
>> 448 select PINCTRL
>> 449 select PINCTRL_LANTIQ
>> 450 select ARCH_HAS_RESET_CONTROLLER
>> 451 select RESET_CONTROLLER
>> 452
>> 453 config MACH_LOONGSON32
>> 454 bool "Loongson 32-bit family of machines"
>> 455 select SYS_SUPPORTS_ZBOOT
>> 456 help
>> 457 This enables support for the Loongson-1 family of machines.
>> 458
>> 459 Loongson-1 is a family of 32-bit MIPS-compatible SoCs developed by
>> 460 the Institute of Computing Technology (ICT), Chinese Academy of
>> 461 Sciences (CAS).
>> 462
>> 463 config MACH_LOONGSON2EF
>> 464 bool "Loongson-2E/F family of machines"
>> 465 select SYS_SUPPORTS_ZBOOT
>> 466 help
>> 467 This enables the support of early Loongson-2E/F family of machines.
>> 468
>> 469 config MACH_LOONGSON64
>> 470 bool "Loongson 64-bit family of machines"
>> 471 select ARCH_SPARSEMEM_ENABLE
>> 472 select ARCH_MIGHT_HAVE_PC_PARPORT
>> 473 select ARCH_MIGHT_HAVE_PC_SERIO
>> 474 select GENERIC_ISA_DMA_SUPPORT_BROKEN
>> 475 select BOOT_ELF32
>> 476 select BOARD_SCACHE
>> 477 select CSRC_R4K
>> 478 select CEVT_R4K
>> 479 select CPU_HAS_WB
>> 480 select FORCE_PCI
>> 481 select ISA
>> 482 select I8259
>> 483 select IRQ_MIPS_CPU
>> 484 select NO_EXCEPT_FILL
>> 485 select NR_CPUS_DEFAULT_64
>> 486 select USE_GENERIC_EARLY_PRINTK_8250
>> 487 select PCI_DRIVERS_GENERIC
>> 488 select SYS_HAS_CPU_LOONGSON64
>> 489 select SYS_HAS_EARLY_PRINTK
>> 490 select SYS_SUPPORTS_SMP
>> 491 select SYS_SUPPORTS_HOTPLUG_CPU
>> 492 select SYS_SUPPORTS_NUMA
>> 493 select SYS_SUPPORTS_64BIT_KERNEL
>> 494 select SYS_SUPPORTS_HIGHMEM
>> 495 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 496 select SYS_SUPPORTS_ZBOOT
>> 497 select ZONE_DMA32
>> 498 select NUMA
>> 499 select SMP
>> 500 select COMMON_CLK
>> 501 select USE_OF
>> 502 select BUILTIN_DTB
>> 503 select PCI_HOST_GENERIC
>> 504 help
>> 505 This enables the support of Loongson-2/3 family of machines.
>> 506
>> 507 Loongson-2 and Loongson-3 are 64-bit general-purpose processors with
>> 508 GS264/GS464/GS464E/GS464V microarchitecture (except old Loongson-2E
>> 509 and Loongson-2F which will be removed), developed by the Institute
>> 510 of Computing Technology (ICT), Chinese Academy of Sciences (CAS).
>> 511
>> 512 config MACH_PISTACHIO
>> 513 bool "IMG Pistachio SoC based boards"
>> 514 select BOOT_ELF32
>> 515 select BOOT_RAW
>> 516 select CEVT_R4K
>> 517 select CLKSRC_MIPS_GIC
>> 518 select COMMON_CLK
>> 519 select CSRC_R4K
>> 520 select DMA_NONCOHERENT
>> 521 select GPIOLIB
>> 522 select IRQ_MIPS_CPU
>> 523 select MFD_SYSCON
>> 524 select MIPS_CPU_SCACHE
>> 525 select MIPS_GIC
>> 526 select PINCTRL
>> 527 select REGULATOR
>> 528 select SYS_HAS_CPU_MIPS32_R2
>> 529 select SYS_SUPPORTS_32BIT_KERNEL
>> 530 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 531 select SYS_SUPPORTS_MIPS_CPS
>> 532 select SYS_SUPPORTS_MULTITHREADING
>> 533 select SYS_SUPPORTS_RELOCATABLE
>> 534 select SYS_SUPPORTS_ZBOOT
>> 535 select SYS_HAS_EARLY_PRINTK
>> 536 select USE_GENERIC_EARLY_PRINTK_8250
>> 537 select USE_OF
>> 538 help
>> 539 This enables support for the IMG Pistachio SoC platform.
>> 540
>> 541 config MIPS_MALTA
>> 542 bool "MIPS Malta board"
>> 543 select ARCH_MAY_HAVE_PC_FDC
>> 544 select ARCH_MIGHT_HAVE_PC_PARPORT
>> 545 select ARCH_MIGHT_HAVE_PC_SERIO
>> 546 select BOOT_ELF32
>> 547 select BOOT_RAW
>> 548 select BUILTIN_DTB
>> 549 select CEVT_R4K
>> 550 select CLKSRC_MIPS_GIC
>> 551 select COMMON_CLK
>> 552 select CSRC_R4K
>> 553 select DMA_MAYBE_COHERENT
>> 554 select GENERIC_ISA_DMA
>> 555 select HAVE_PCSPKR_PLATFORM
>> 556 select HAVE_PCI
>> 557 select I8253
>> 558 select I8259
>> 559 select IRQ_MIPS_CPU
>> 560 select MIPS_BONITO64
>> 561 select MIPS_CPU_SCACHE
>> 562 select MIPS_GIC
>> 563 select MIPS_L1_CACHE_SHIFT_6
>> 564 select MIPS_MSC
>> 565 select PCI_GT64XXX_PCI0
>> 566 select SMP_UP if SMP
>> 567 select SWAP_IO_SPACE
>> 568 select SYS_HAS_CPU_MIPS32_R1
>> 569 select SYS_HAS_CPU_MIPS32_R2
>> 570 select SYS_HAS_CPU_MIPS32_R3_5
>> 571 select SYS_HAS_CPU_MIPS32_R5
>> 572 select SYS_HAS_CPU_MIPS32_R6
>> 573 select SYS_HAS_CPU_MIPS64_R1
>> 574 select SYS_HAS_CPU_MIPS64_R2
>> 575 select SYS_HAS_CPU_MIPS64_R6
>> 576 select SYS_HAS_CPU_NEVADA
>> 577 select SYS_HAS_CPU_RM7000
>> 578 select SYS_SUPPORTS_32BIT_KERNEL
>> 579 select SYS_SUPPORTS_64BIT_KERNEL
>> 580 select SYS_SUPPORTS_BIG_ENDIAN
>> 581 select SYS_SUPPORTS_HIGHMEM
>> 582 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 583 select SYS_SUPPORTS_MICROMIPS
>> 584 select SYS_SUPPORTS_MIPS16
>> 585 select SYS_SUPPORTS_MIPS_CMP
>> 586 select SYS_SUPPORTS_MIPS_CPS
>> 587 select SYS_SUPPORTS_MULTITHREADING
>> 588 select SYS_SUPPORTS_RELOCATABLE
>> 589 select SYS_SUPPORTS_SMARTMIPS
>> 590 select SYS_SUPPORTS_VPE_LOADER
>> 591 select SYS_SUPPORTS_ZBOOT
>> 592 select USE_OF
>> 593 select WAR_ICACHE_REFILLS
>> 594 select ZONE_DMA32 if 64BIT
>> 595 help
>> 596 This enables support for the MIPS Technologies Malta evaluation
>> 597 board.
>> 598
>> 599 config MACH_PIC32
>> 600 bool "Microchip PIC32 Family"
>> 601 help
>> 602 This enables support for the Microchip PIC32 family of platforms.
>> 603
>> 604 Microchip PIC32 is a family of general-purpose 32 bit MIPS core
>> 605 microcontrollers.
>> 606
>> 607 config MACH_VR41XX
>> 608 bool "NEC VR4100 series based machines"
>> 609 select CEVT_R4K
>> 610 select CSRC_R4K
>> 611 select SYS_HAS_CPU_VR41XX
>> 612 select SYS_SUPPORTS_MIPS16
>> 613 select GPIOLIB
>> 614
>> 615 config RALINK
>> 616 bool "Ralink based machines"
>> 617 select CEVT_R4K
>> 618 select CSRC_R4K
>> 619 select BOOT_RAW
>> 620 select DMA_NONCOHERENT
>> 621 select IRQ_MIPS_CPU
>> 622 select USE_OF
>> 623 select SYS_HAS_CPU_MIPS32_R1
>> 624 select SYS_HAS_CPU_MIPS32_R2
>> 625 select SYS_SUPPORTS_32BIT_KERNEL
>> 626 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 627 select SYS_SUPPORTS_MIPS16
>> 628 select SYS_SUPPORTS_ZBOOT
>> 629 select SYS_HAS_EARLY_PRINTK
>> 630 select CLKDEV_LOOKUP
>> 631 select ARCH_HAS_RESET_CONTROLLER
>> 632 select RESET_CONTROLLER
>> 633
>> 634 config SGI_IP22
>> 635 bool "SGI IP22 (Indy/Indigo2)"
>> 636 select ARC_MEMORY
>> 637 select ARC_PROMLIB
>> 638 select FW_ARC
>> 639 select FW_ARC32
>> 640 select ARCH_MIGHT_HAVE_PC_SERIO
>> 641 select BOOT_ELF32
>> 642 select CEVT_R4K
>> 643 select CSRC_R4K
>> 644 select DEFAULT_SGI_PARTITION
>> 645 select DMA_NONCOHERENT
>> 646 select HAVE_EISA
>> 647 select I8253
>> 648 select I8259
>> 649 select IP22_CPU_SCACHE
>> 650 select IRQ_MIPS_CPU
>> 651 select GENERIC_ISA_DMA_SUPPORT_BROKEN
>> 652 select SGI_HAS_I8042
>> 653 select SGI_HAS_INDYDOG
>> 654 select SGI_HAS_HAL2
>> 655 select SGI_HAS_SEEQ
>> 656 select SGI_HAS_WD93
>> 657 select SGI_HAS_ZILOG
>> 658 select SWAP_IO_SPACE
>> 659 select SYS_HAS_CPU_R4X00
>> 660 select SYS_HAS_CPU_R5000
>> 661 select SYS_HAS_EARLY_PRINTK
>> 662 select SYS_SUPPORTS_32BIT_KERNEL
>> 663 select SYS_SUPPORTS_64BIT_KERNEL
>> 664 select SYS_SUPPORTS_BIG_ENDIAN
>> 665 select WAR_R4600_V1_INDEX_ICACHEOP
>> 666 select WAR_R4600_V1_HIT_CACHEOP
>> 667 select WAR_R4600_V2_HIT_CACHEOP
>> 668 select MIPS_L1_CACHE_SHIFT_7
>> 669 help
>> 670 This are the SGI Indy, Challenge S and Indigo2, as well as certain
>> 671 OEM variants like the Tandem CMN B006S. To compile a Linux kernel
>> 672 that runs on these, say Y here.
>> 673
>> 674 config SGI_IP27
>> 675 bool "SGI IP27 (Origin200/2000)"
>> 676 select ARCH_HAS_PHYS_TO_DMA
>> 677 select ARCH_SPARSEMEM_ENABLE
>> 678 select FW_ARC
>> 679 select FW_ARC64
>> 680 select ARC_CMDLINE_ONLY
>> 681 select BOOT_ELF64
>> 682 select DEFAULT_SGI_PARTITION
>> 683 select SYS_HAS_EARLY_PRINTK
>> 684 select HAVE_PCI
>> 685 select IRQ_MIPS_CPU
>> 686 select IRQ_DOMAIN_HIERARCHY
>> 687 select NR_CPUS_DEFAULT_64
>> 688 select PCI_DRIVERS_GENERIC
>> 689 select PCI_XTALK_BRIDGE
>> 690 select SYS_HAS_CPU_R10000
>> 691 select SYS_SUPPORTS_64BIT_KERNEL
>> 692 select SYS_SUPPORTS_BIG_ENDIAN
>> 693 select SYS_SUPPORTS_NUMA
>> 694 select SYS_SUPPORTS_SMP
>> 695 select WAR_R10000_LLSC
>> 696 select MIPS_L1_CACHE_SHIFT_7
>> 697 select NUMA
>> 698 help
>> 699 This are the SGI Origin 200, Origin 2000 and Onyx 2 Graphics
>> 700 workstations. To compile a Linux kernel that runs on these, say Y
>> 701 here.
>> 702
>> 703 config SGI_IP28
>> 704 bool "SGI IP28 (Indigo2 R10k)"
>> 705 select ARC_MEMORY
>> 706 select ARC_PROMLIB
>> 707 select FW_ARC
>> 708 select FW_ARC64
>> 709 select ARCH_MIGHT_HAVE_PC_SERIO
>> 710 select BOOT_ELF64
>> 711 select CEVT_R4K
>> 712 select CSRC_R4K
>> 713 select DEFAULT_SGI_PARTITION
>> 714 select DMA_NONCOHERENT
>> 715 select GENERIC_ISA_DMA_SUPPORT_BROKEN
>> 716 select IRQ_MIPS_CPU
>> 717 select HAVE_EISA
>> 718 select I8253
>> 719 select I8259
>> 720 select SGI_HAS_I8042
>> 721 select SGI_HAS_INDYDOG
>> 722 select SGI_HAS_HAL2
>> 723 select SGI_HAS_SEEQ
>> 724 select SGI_HAS_WD93
>> 725 select SGI_HAS_ZILOG
>> 726 select SWAP_IO_SPACE
>> 727 select SYS_HAS_CPU_R10000
>> 728 select SYS_HAS_EARLY_PRINTK
>> 729 select SYS_SUPPORTS_64BIT_KERNEL
>> 730 select SYS_SUPPORTS_BIG_ENDIAN
>> 731 select WAR_R10000_LLSC
>> 732 select MIPS_L1_CACHE_SHIFT_7
>> 733 help
>> 734 This is the SGI Indigo2 with R10000 processor. To compile a Linux
>> 735 kernel that runs on these, say Y here.
>> 736
>> 737 config SGI_IP30
>> 738 bool "SGI IP30 (Octane/Octane2)"
>> 739 select ARCH_HAS_PHYS_TO_DMA
>> 740 select FW_ARC
>> 741 select FW_ARC64
>> 742 select BOOT_ELF64
>> 743 select CEVT_R4K
>> 744 select CSRC_R4K
>> 745 select SYNC_R4K if SMP
>> 746 select ZONE_DMA32
>> 747 select HAVE_PCI
>> 748 select IRQ_MIPS_CPU
>> 749 select IRQ_DOMAIN_HIERARCHY
>> 750 select NR_CPUS_DEFAULT_2
>> 751 select PCI_DRIVERS_GENERIC
>> 752 select PCI_XTALK_BRIDGE
>> 753 select SYS_HAS_EARLY_PRINTK
>> 754 select SYS_HAS_CPU_R10000
>> 755 select SYS_SUPPORTS_64BIT_KERNEL
>> 756 select SYS_SUPPORTS_BIG_ENDIAN
>> 757 select SYS_SUPPORTS_SMP
>> 758 select WAR_R10000_LLSC
>> 759 select MIPS_L1_CACHE_SHIFT_7
>> 760 select ARC_MEMORY
>> 761 help
>> 762 These are the SGI Octane and Octane2 graphics workstations. To
>> 763 compile a Linux kernel that runs on these, say Y here.
>> 764
>> 765 config SGI_IP32
>> 766 bool "SGI IP32 (O2)"
>> 767 select ARC_MEMORY
>> 768 select ARC_PROMLIB
>> 769 select ARCH_HAS_PHYS_TO_DMA
>> 770 select FW_ARC
>> 771 select FW_ARC32
>> 772 select BOOT_ELF32
>> 773 select CEVT_R4K
>> 774 select CSRC_R4K
>> 775 select DMA_NONCOHERENT
>> 776 select HAVE_PCI
>> 777 select IRQ_MIPS_CPU
>> 778 select R5000_CPU_SCACHE
>> 779 select RM7000_CPU_SCACHE
>> 780 select SYS_HAS_CPU_R5000
>> 781 select SYS_HAS_CPU_R10000 if BROKEN
>> 782 select SYS_HAS_CPU_RM7000
>> 783 select SYS_HAS_CPU_NEVADA
>> 784 select SYS_SUPPORTS_64BIT_KERNEL
>> 785 select SYS_SUPPORTS_BIG_ENDIAN
>> 786 select WAR_ICACHE_REFILLS
>> 787 help
>> 788 If you want this kernel to run on SGI O2 workstation, say Y here.
>> 789
>> 790 config SIBYTE_CRHINE
>> 791 bool "Sibyte BCM91120C-CRhine"
>> 792 select BOOT_ELF32
>> 793 select SIBYTE_BCM1120
>> 794 select SWAP_IO_SPACE
>> 795 select SYS_HAS_CPU_SB1
>> 796 select SYS_SUPPORTS_BIG_ENDIAN
>> 797 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 798
>> 799 config SIBYTE_CARMEL
>> 800 bool "Sibyte BCM91120x-Carmel"
>> 801 select BOOT_ELF32
>> 802 select SIBYTE_BCM1120
>> 803 select SWAP_IO_SPACE
>> 804 select SYS_HAS_CPU_SB1
>> 805 select SYS_SUPPORTS_BIG_ENDIAN
>> 806 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 807
>> 808 config SIBYTE_CRHONE
>> 809 bool "Sibyte BCM91125C-CRhone"
>> 810 select BOOT_ELF32
>> 811 select SIBYTE_BCM1125
>> 812 select SWAP_IO_SPACE
>> 813 select SYS_HAS_CPU_SB1
>> 814 select SYS_SUPPORTS_BIG_ENDIAN
>> 815 select SYS_SUPPORTS_HIGHMEM
>> 816 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 817
>> 818 config SIBYTE_RHONE
>> 819 bool "Sibyte BCM91125E-Rhone"
>> 820 select BOOT_ELF32
>> 821 select SIBYTE_BCM1125H
>> 822 select SWAP_IO_SPACE
>> 823 select SYS_HAS_CPU_SB1
>> 824 select SYS_SUPPORTS_BIG_ENDIAN
>> 825 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 826
>> 827 config SIBYTE_SWARM
>> 828 bool "Sibyte BCM91250A-SWARM"
>> 829 select BOOT_ELF32
>> 830 select HAVE_PATA_PLATFORM
>> 831 select SIBYTE_SB1250
>> 832 select SWAP_IO_SPACE
>> 833 select SYS_HAS_CPU_SB1
>> 834 select SYS_SUPPORTS_BIG_ENDIAN
>> 835 select SYS_SUPPORTS_HIGHMEM
>> 836 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 837 select ZONE_DMA32 if 64BIT
>> 838 select SWIOTLB if ARCH_DMA_ADDR_T_64BIT && PCI
>> 839
>> 840 config SIBYTE_LITTLESUR
>> 841 bool "Sibyte BCM91250C2-LittleSur"
>> 842 select BOOT_ELF32
>> 843 select HAVE_PATA_PLATFORM
>> 844 select SIBYTE_SB1250
>> 845 select SWAP_IO_SPACE
>> 846 select SYS_HAS_CPU_SB1
>> 847 select SYS_SUPPORTS_BIG_ENDIAN
>> 848 select SYS_SUPPORTS_HIGHMEM
>> 849 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 850 select ZONE_DMA32 if 64BIT
>> 851
>> 852 config SIBYTE_SENTOSA
>> 853 bool "Sibyte BCM91250E-Sentosa"
>> 854 select BOOT_ELF32
>> 855 select SIBYTE_SB1250
>> 856 select SWAP_IO_SPACE
>> 857 select SYS_HAS_CPU_SB1
>> 858 select SYS_SUPPORTS_BIG_ENDIAN
>> 859 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 860 select SWIOTLB if ARCH_DMA_ADDR_T_64BIT && PCI
>> 861
>> 862 config SIBYTE_BIGSUR
>> 863 bool "Sibyte BCM91480B-BigSur"
>> 864 select BOOT_ELF32
>> 865 select NR_CPUS_DEFAULT_4
>> 866 select SIBYTE_BCM1x80
>> 867 select SWAP_IO_SPACE
>> 868 select SYS_HAS_CPU_SB1
>> 869 select SYS_SUPPORTS_BIG_ENDIAN
>> 870 select SYS_SUPPORTS_HIGHMEM
>> 871 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 872 select ZONE_DMA32 if 64BIT
>> 873 select SWIOTLB if ARCH_DMA_ADDR_T_64BIT && PCI
>> 874
>> 875 config SNI_RM
>> 876 bool "SNI RM200/300/400"
>> 877 select ARC_MEMORY
>> 878 select ARC_PROMLIB
>> 879 select FW_ARC if CPU_LITTLE_ENDIAN
>> 880 select FW_ARC32 if CPU_LITTLE_ENDIAN
>> 881 select FW_SNIPROM if CPU_BIG_ENDIAN
>> 882 select ARCH_MAY_HAVE_PC_FDC
>> 883 select ARCH_MIGHT_HAVE_PC_PARPORT
>> 884 select ARCH_MIGHT_HAVE_PC_SERIO
>> 885 select BOOT_ELF32
>> 886 select CEVT_R4K
>> 887 select CSRC_R4K
>> 888 select DEFAULT_SGI_PARTITION if CPU_BIG_ENDIAN
>> 889 select DMA_NONCOHERENT
>> 890 select GENERIC_ISA_DMA
>> 891 select HAVE_EISA
>> 892 select HAVE_PCSPKR_PLATFORM
>> 893 select HAVE_PCI
>> 894 select IRQ_MIPS_CPU
>> 895 select I8253
>> 896 select I8259
>> 897 select ISA
>> 898 select MIPS_L1_CACHE_SHIFT_6
>> 899 select SWAP_IO_SPACE if CPU_BIG_ENDIAN
>> 900 select SYS_HAS_CPU_R4X00
>> 901 select SYS_HAS_CPU_R5000
>> 902 select SYS_HAS_CPU_R10000
>> 903 select R5000_CPU_SCACHE
>> 904 select SYS_HAS_EARLY_PRINTK
>> 905 select SYS_SUPPORTS_32BIT_KERNEL
>> 906 select SYS_SUPPORTS_64BIT_KERNEL
>> 907 select SYS_SUPPORTS_BIG_ENDIAN
>> 908 select SYS_SUPPORTS_HIGHMEM
>> 909 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 910 select WAR_R4600_V2_HIT_CACHEOP
>> 911 help
>> 912 The SNI RM200/300/400 are MIPS-based machines manufactured by
>> 913 Siemens Nixdorf Informationssysteme (SNI), parent company of Pyramid
>> 914 Technology and now in turn merged with Fujitsu. Say Y here to
>> 915 support this machine type.
>> 916
>> 917 config MACH_TX39XX
>> 918 bool "Toshiba TX39 series based machines"
>> 919
>> 920 config MACH_TX49XX
>> 921 bool "Toshiba TX49 series based machines"
>> 922 select WAR_TX49XX_ICACHE_INDEX_INV
>> 923
>> 924 config MIKROTIK_RB532
>> 925 bool "Mikrotik RB532 boards"
>> 926 select CEVT_R4K
>> 927 select CSRC_R4K
>> 928 select DMA_NONCOHERENT
>> 929 select HAVE_PCI
>> 930 select IRQ_MIPS_CPU
>> 931 select SYS_HAS_CPU_MIPS32_R1
>> 932 select SYS_SUPPORTS_32BIT_KERNEL
>> 933 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 934 select SWAP_IO_SPACE
>> 935 select BOOT_RAW
>> 936 select GPIOLIB
>> 937 select MIPS_L1_CACHE_SHIFT_4
>> 938 help
>> 939 Support the Mikrotik(tm) RouterBoard 532 series,
>> 940 based on the IDT RC32434 SoC.
>> 941
>> 942 config CAVIUM_OCTEON_SOC
>> 943 bool "Cavium Networks Octeon SoC based boards"
>> 944 select CEVT_R4K
>> 945 select ARCH_HAS_PHYS_TO_DMA
>> 946 select HAVE_RAPIDIO
>> 947 select PHYS_ADDR_T_64BIT
>> 948 select SYS_SUPPORTS_64BIT_KERNEL
>> 949 select SYS_SUPPORTS_BIG_ENDIAN
>> 950 select EDAC_SUPPORT
>> 951 select EDAC_ATOMIC_SCRUB
>> 952 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 953 select SYS_SUPPORTS_HOTPLUG_CPU if CPU_BIG_ENDIAN
>> 954 select SYS_HAS_EARLY_PRINTK
>> 955 select SYS_HAS_CPU_CAVIUM_OCTEON
>> 956 select HAVE_PCI
>> 957 select HAVE_PLAT_DELAY
>> 958 select HAVE_PLAT_FW_INIT_CMDLINE
>> 959 select HAVE_PLAT_MEMCPY
>> 960 select ZONE_DMA32
>> 961 select HOLES_IN_ZONE
>> 962 select GPIOLIB
>> 963 select USE_OF
>> 964 select ARCH_SPARSEMEM_ENABLE
>> 965 select SYS_SUPPORTS_SMP
>> 966 select NR_CPUS_DEFAULT_64
>> 967 select MIPS_NR_CPU_NR_MAP_1024
>> 968 select BUILTIN_DTB
>> 969 select MTD_COMPLEX_MAPPINGS
>> 970 select SWIOTLB
>> 971 select SYS_SUPPORTS_RELOCATABLE
>> 972 help
>> 973 This option supports all of the Octeon reference boards from Cavium
>> 974 Networks. It builds a kernel that dynamically determines the Octeon
>> 975 CPU type and supports all known board reference implementations.
>> 976 Some of the supported boards are:
>> 977 EBT3000
>> 978 EBH3000
>> 979 EBH3100
>> 980 Thunder
>> 981 Kodama
>> 982 Hikari
>> 983 Say Y here for most Octeon reference boards.
>> 984
>> 985 config NLM_XLR_BOARD
>> 986 bool "Netlogic XLR/XLS based systems"
>> 987 select BOOT_ELF32
>> 988 select NLM_COMMON
>> 989 select SYS_HAS_CPU_XLR
>> 990 select SYS_SUPPORTS_SMP
>> 991 select HAVE_PCI
>> 992 select SWAP_IO_SPACE
>> 993 select SYS_SUPPORTS_32BIT_KERNEL
>> 994 select SYS_SUPPORTS_64BIT_KERNEL
>> 995 select PHYS_ADDR_T_64BIT
>> 996 select SYS_SUPPORTS_BIG_ENDIAN
>> 997 select SYS_SUPPORTS_HIGHMEM
>> 998 select NR_CPUS_DEFAULT_32
>> 999 select CEVT_R4K
>> 1000 select CSRC_R4K
>> 1001 select IRQ_MIPS_CPU
>> 1002 select ZONE_DMA32 if 64BIT
>> 1003 select SYNC_R4K
>> 1004 select SYS_HAS_EARLY_PRINTK
>> 1005 select SYS_SUPPORTS_ZBOOT
>> 1006 select SYS_SUPPORTS_ZBOOT_UART16550
>> 1007 help
>> 1008 Support for systems based on Netlogic XLR and XLS processors.
>> 1009 Say Y here if you have a XLR or XLS based board.
>> 1010
>> 1011 config NLM_XLP_BOARD
>> 1012 bool "Netlogic XLP based systems"
>> 1013 select BOOT_ELF32
>> 1014 select NLM_COMMON
>> 1015 select SYS_HAS_CPU_XLP
>> 1016 select SYS_SUPPORTS_SMP
>> 1017 select HAVE_PCI
>> 1018 select SYS_SUPPORTS_32BIT_KERNEL
>> 1019 select SYS_SUPPORTS_64BIT_KERNEL
>> 1020 select PHYS_ADDR_T_64BIT
>> 1021 select GPIOLIB
>> 1022 select SYS_SUPPORTS_BIG_ENDIAN
>> 1023 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 1024 select SYS_SUPPORTS_HIGHMEM
>> 1025 select NR_CPUS_DEFAULT_32
>> 1026 select CEVT_R4K
>> 1027 select CSRC_R4K
>> 1028 select IRQ_MIPS_CPU
>> 1029 select ZONE_DMA32 if 64BIT
>> 1030 select SYNC_R4K
>> 1031 select SYS_HAS_EARLY_PRINTK
>> 1032 select USE_OF
>> 1033 select SYS_SUPPORTS_ZBOOT
>> 1034 select SYS_SUPPORTS_ZBOOT_UART16550
>> 1035 help
>> 1036 This board is based on Netlogic XLP Processor.
>> 1037 Say Y here if you have a XLP based board.
336 1038
337 config ARCH_MMAP_RND_COMPAT_BITS_MAX !! 1039 endchoice
338 default 16 <<
339 1040
340 config NO_IOPORT_MAP !! 1041 source "arch/mips/alchemy/Kconfig"
341 def_bool y if !PCI !! 1042 source "arch/mips/ath25/Kconfig"
>> 1043 source "arch/mips/ath79/Kconfig"
>> 1044 source "arch/mips/bcm47xx/Kconfig"
>> 1045 source "arch/mips/bcm63xx/Kconfig"
>> 1046 source "arch/mips/bmips/Kconfig"
>> 1047 source "arch/mips/generic/Kconfig"
>> 1048 source "arch/mips/ingenic/Kconfig"
>> 1049 source "arch/mips/jazz/Kconfig"
>> 1050 source "arch/mips/lantiq/Kconfig"
>> 1051 source "arch/mips/pic32/Kconfig"
>> 1052 source "arch/mips/pistachio/Kconfig"
>> 1053 source "arch/mips/ralink/Kconfig"
>> 1054 source "arch/mips/sgi-ip27/Kconfig"
>> 1055 source "arch/mips/sibyte/Kconfig"
>> 1056 source "arch/mips/txx9/Kconfig"
>> 1057 source "arch/mips/vr41xx/Kconfig"
>> 1058 source "arch/mips/cavium-octeon/Kconfig"
>> 1059 source "arch/mips/loongson2ef/Kconfig"
>> 1060 source "arch/mips/loongson32/Kconfig"
>> 1061 source "arch/mips/loongson64/Kconfig"
>> 1062 source "arch/mips/netlogic/Kconfig"
342 1063
343 config STACKTRACE_SUPPORT !! 1064 endmenu
344 def_bool y <<
345 1065
346 config ILLEGAL_POINTER_VALUE !! 1066 config GENERIC_HWEIGHT
347 hex !! 1067 bool
348 default 0xdead000000000000 !! 1068 default y
349 1069
350 config LOCKDEP_SUPPORT !! 1070 config GENERIC_CALIBRATE_DELAY
351 def_bool y !! 1071 bool
>> 1072 default y
352 1073
353 config GENERIC_BUG !! 1074 config SCHED_OMIT_FRAME_POINTER
354 def_bool y !! 1075 bool
355 depends on BUG !! 1076 default y
356 1077
357 config GENERIC_BUG_RELATIVE_POINTERS !! 1078 #
358 def_bool y !! 1079 # Select some configuration options automatically based on user selections.
359 depends on GENERIC_BUG !! 1080 #
>> 1081 config FW_ARC
>> 1082 bool
360 1083
361 config GENERIC_HWEIGHT !! 1084 config ARCH_MAY_HAVE_PC_FDC
362 def_bool y !! 1085 bool
363 1086
364 config GENERIC_CSUM !! 1087 config BOOT_RAW
365 def_bool y !! 1088 bool
366 1089
367 config GENERIC_CALIBRATE_DELAY !! 1090 config CEVT_BCM1480
368 def_bool y !! 1091 bool
369 1092
370 config SMP !! 1093 config CEVT_DS1287
371 def_bool y !! 1094 bool
372 1095
373 config KERNEL_MODE_NEON !! 1096 config CEVT_GT641XX
374 def_bool y !! 1097 bool
375 1098
376 config FIX_EARLYCON_MEM !! 1099 config CEVT_R4K
377 def_bool y !! 1100 bool
378 1101
379 config PGTABLE_LEVELS !! 1102 config CEVT_SB1250
380 int !! 1103 bool
381 default 2 if ARM64_16K_PAGES && ARM64_ <<
382 default 2 if ARM64_64K_PAGES && ARM64_ <<
383 default 3 if ARM64_64K_PAGES && (ARM64 <<
384 default 3 if ARM64_4K_PAGES && ARM64_V <<
385 default 3 if ARM64_16K_PAGES && ARM64_ <<
386 default 4 if ARM64_16K_PAGES && (ARM64 <<
387 default 4 if !ARM64_64K_PAGES && ARM64 <<
388 default 5 if ARM64_4K_PAGES && ARM64_V <<
389 1104
390 config ARCH_SUPPORTS_UPROBES !! 1105 config CEVT_TXX9
391 def_bool y !! 1106 bool
392 1107
393 config ARCH_PROC_KCORE_TEXT !! 1108 config CSRC_BCM1480
394 def_bool y !! 1109 bool
395 1110
396 config BROKEN_GAS_INST !! 1111 config CSRC_IOASIC
397 def_bool !$(as-instr,1:\n.inst 0\n.rep !! 1112 bool
398 1113
399 config BUILTIN_RETURN_ADDRESS_STRIPS_PAC !! 1114 config CSRC_R4K
>> 1115 select CLOCKSOURCE_WATCHDOG if CPU_FREQ
400 bool 1116 bool
401 # Clang's __builtin_return_address() s <<
402 # https://github.com/llvm/llvm-project <<
403 default y if CC_IS_CLANG <<
404 # GCC's __builtin_return_address() str <<
405 # and this was backported to 10.2.0, 9 <<
406 # https://gcc.gnu.org/bugzilla/show_bu <<
407 default y if CC_IS_GCC && (GCC_VERSION <<
408 default y if CC_IS_GCC && (GCC_VERSION <<
409 default y if CC_IS_GCC && (GCC_VERSION <<
410 default y if CC_IS_GCC && (GCC_VERSION <<
411 default n <<
412 1117
413 config KASAN_SHADOW_OFFSET !! 1118 config CSRC_SB1250
414 hex !! 1119 bool
415 depends on KASAN_GENERIC || KASAN_SW_T <<
416 default 0xdfff800000000000 if (ARM64_V <<
417 default 0xdfffc00000000000 if (ARM64_V <<
418 default 0xdffffe0000000000 if ARM64_VA <<
419 default 0xdfffffc000000000 if ARM64_VA <<
420 default 0xdffffff800000000 if ARM64_VA <<
421 default 0xefff800000000000 if (ARM64_V <<
422 default 0xefffc00000000000 if (ARM64_V <<
423 default 0xeffffe0000000000 if ARM64_VA <<
424 default 0xefffffc000000000 if ARM64_VA <<
425 default 0xeffffff800000000 if ARM64_VA <<
426 default 0xffffffffffffffff <<
427 <<
428 config UNWIND_TABLES <<
429 bool <<
430 <<
431 source "arch/arm64/Kconfig.platforms" <<
432 <<
433 menu "Kernel Features" <<
434 <<
435 menu "ARM errata workarounds via the alternati <<
436 <<
437 config AMPERE_ERRATUM_AC03_CPU_38 <<
438 bool "AmpereOne: AC03_CPU_38: Certain <<
439 default y <<
440 help <<
441 This option adds an alternative code <<
442 errata AC03_CPU_38 and AC04_CPU_10 o <<
443 <<
444 The affected design reports FEAT_HAF <<
445 ID_AA64MMFR1_EL1.HAFDBS, but (V)TCR_ <<
446 as required by the architecture. The <<
447 implementation suffers from an addit <<
448 A/D updates can occur after a PTE ha <<
449 <<
450 The workaround forces KVM to explici <<
451 which avoids enabling unadvertised h <<
452 at stage-2. <<
453 1120
454 If unsure, say Y. !! 1121 config MIPS_CLOCK_VSYSCALL
>> 1122 def_bool CSRC_R4K || CLKSRC_MIPS_GIC
455 1123
456 config ARM64_WORKAROUND_CLEAN_CACHE !! 1124 config GPIO_TXX9
>> 1125 select GPIOLIB
457 bool 1126 bool
458 1127
459 config ARM64_ERRATUM_826319 !! 1128 config FW_CFE
460 bool "Cortex-A53: 826319: System might !! 1129 bool
461 default y <<
462 select ARM64_WORKAROUND_CLEAN_CACHE <<
463 help <<
464 This option adds an alternative code <<
465 erratum 826319 on Cortex-A53 parts u <<
466 AXI master interface and an L2 cache <<
467 <<
468 If a Cortex-A53 uses an AMBA AXI4 AC <<
469 and is unable to accept a certain wr <<
470 not progress on read data presented <<
471 system can deadlock. <<
472 1130
473 The workaround promotes data cache c !! 1131 config ARCH_SUPPORTS_UPROBES
474 data cache clean-and-invalidate. !! 1132 bool
475 Please note that this does not neces <<
476 as it depends on the alternative fra <<
477 the kernel if an affected CPU is det <<
478 1133
479 If unsure, say Y. !! 1134 config DMA_MAYBE_COHERENT
>> 1135 select ARCH_HAS_DMA_COHERENCE_H
>> 1136 select DMA_NONCOHERENT
>> 1137 bool
480 1138
481 config ARM64_ERRATUM_827319 !! 1139 config DMA_PERDEV_COHERENT
482 bool "Cortex-A53: 827319: Data cache c !! 1140 bool
483 default y !! 1141 select ARCH_HAS_SETUP_DMA_OPS
484 select ARM64_WORKAROUND_CLEAN_CACHE !! 1142 select DMA_NONCOHERENT
485 help <<
486 This option adds an alternative code <<
487 erratum 827319 on Cortex-A53 parts u <<
488 master interface and an L2 cache. <<
489 <<
490 Under certain conditions this erratu <<
491 to occur at the same time as another <<
492 on the AMBA 5 CHI interface, which c <<
493 interconnect reorders the two transa <<
494 <<
495 The workaround promotes data cache c <<
496 data cache clean-and-invalidate. <<
497 Please note that this does not neces <<
498 as it depends on the alternative fra <<
499 the kernel if an affected CPU is det <<
500 1143
501 If unsure, say Y. !! 1144 config DMA_NONCOHERENT
>> 1145 bool
>> 1146 #
>> 1147 # MIPS allows mixing "slightly different" Cacheability and Coherency
>> 1148 # Attribute bits. It is believed that the uncached access through
>> 1149 # KSEG1 and the implementation specific "uncached accelerated" used
>> 1150 # by pgprot_writcombine can be mixed, and the latter sometimes provides
>> 1151 # significant advantages.
>> 1152 #
>> 1153 select ARCH_HAS_DMA_WRITE_COMBINE
>> 1154 select ARCH_HAS_DMA_PREP_COHERENT
>> 1155 select ARCH_HAS_SYNC_DMA_FOR_DEVICE
>> 1156 select ARCH_HAS_DMA_SET_UNCACHED
>> 1157 select DMA_NONCOHERENT_MMAP
>> 1158 select NEED_DMA_MAP_STATE
502 1159
503 config ARM64_ERRATUM_824069 !! 1160 config SYS_HAS_EARLY_PRINTK
504 bool "Cortex-A53: 824069: Cache line m !! 1161 bool
505 default y <<
506 select ARM64_WORKAROUND_CLEAN_CACHE <<
507 help <<
508 This option adds an alternative code <<
509 erratum 824069 on Cortex-A53 parts u <<
510 to a coherent interconnect. <<
511 <<
512 If a Cortex-A53 processor is executi <<
513 write instruction at the same time a <<
514 cluster is executing a cache mainten <<
515 address, then this erratum might cau <<
516 incorrectly marked as dirty. <<
517 <<
518 The workaround promotes data cache c <<
519 data cache clean-and-invalidate. <<
520 Please note that this option does no <<
521 workaround, as it depends on the alt <<
522 only patch the kernel if an affected <<
523 1162
524 If unsure, say Y. !! 1163 config SYS_SUPPORTS_HOTPLUG_CPU
>> 1164 bool
525 1165
526 config ARM64_ERRATUM_819472 !! 1166 config MIPS_BONITO64
527 bool "Cortex-A53: 819472: Store exclus !! 1167 bool
528 default y <<
529 select ARM64_WORKAROUND_CLEAN_CACHE <<
530 help <<
531 This option adds an alternative code <<
532 erratum 819472 on Cortex-A53 parts u <<
533 present when it is connected to a co <<
534 <<
535 If the processor is executing a load <<
536 the same time as a processor in anot <<
537 maintenance operation to the same ad <<
538 cause data corruption. <<
539 <<
540 The workaround promotes data cache c <<
541 data cache clean-and-invalidate. <<
542 Please note that this does not neces <<
543 as it depends on the alternative fra <<
544 the kernel if an affected CPU is det <<
545 1168
546 If unsure, say Y. !! 1169 config MIPS_MSC
>> 1170 bool
547 1171
548 config ARM64_ERRATUM_832075 !! 1172 config SYNC_R4K
549 bool "Cortex-A57: 832075: possible dea !! 1173 bool
550 default y <<
551 help <<
552 This option adds an alternative code <<
553 erratum 832075 on Cortex-A57 parts u <<
554 1174
555 Affected Cortex-A57 parts might dead !! 1175 config NO_IOPORT_MAP
556 instructions to Write-Back memory ar !! 1176 def_bool n
557 1177
558 The workaround is to promote device !! 1178 config GENERIC_CSUM
559 semantics. !! 1179 def_bool CPU_NO_LOAD_STORE_LR
560 Please note that this does not neces <<
561 as it depends on the alternative fra <<
562 the kernel if an affected CPU is det <<
563 1180
564 If unsure, say Y. !! 1181 config GENERIC_ISA_DMA
>> 1182 bool
>> 1183 select ZONE_DMA if GENERIC_ISA_DMA_SUPPORT_BROKEN=n
>> 1184 select ISA_DMA_API
565 1185
566 config ARM64_ERRATUM_834220 !! 1186 config GENERIC_ISA_DMA_SUPPORT_BROKEN
567 bool "Cortex-A57: 834220: Stage 2 tran !! 1187 bool
568 depends on KVM !! 1188 select GENERIC_ISA_DMA
569 help <<
570 This option adds an alternative code <<
571 erratum 834220 on Cortex-A57 parts u <<
572 <<
573 Affected Cortex-A57 parts might repo <<
574 fault as the result of a Stage 1 fau <<
575 page boundary when there is a permis <<
576 alignment fault at Stage 1 and a tra <<
577 <<
578 The workaround is to verify that the <<
579 doesn't generate a fault before hand <<
580 Please note that this does not neces <<
581 as it depends on the alternative fra <<
582 the kernel if an affected CPU is det <<
583 1189
584 If unsure, say N. !! 1190 config HAVE_PLAT_DELAY
>> 1191 bool
585 1192
586 config ARM64_ERRATUM_1742098 !! 1193 config HAVE_PLAT_FW_INIT_CMDLINE
587 bool "Cortex-A57/A72: 1742098: ELR rec !! 1194 bool
588 depends on COMPAT <<
589 default y <<
590 help <<
591 This option removes the AES hwcap fo <<
592 workaround erratum 1742098 on Cortex <<
593 <<
594 Affected parts may corrupt the AES s <<
595 taken between a pair of AES instruct <<
596 are only present if the cryptography <<
597 All software should have a fallback <<
598 that don't implement the cryptograph <<
599 1195
600 If unsure, say Y. !! 1196 config HAVE_PLAT_MEMCPY
>> 1197 bool
601 1198
602 config ARM64_ERRATUM_845719 !! 1199 config ISA_DMA_API
603 bool "Cortex-A53: 845719: a load might !! 1200 bool
604 depends on COMPAT <<
605 default y <<
606 help <<
607 This option adds an alternative code <<
608 erratum 845719 on Cortex-A53 parts u <<
609 <<
610 When running a compat (AArch32) user <<
611 part, a load at EL0 from a virtual a <<
612 bits of the virtual address used by <<
613 might return incorrect data. <<
614 <<
615 The workaround is to write the conte <<
616 return to a 32-bit task. <<
617 Please note that this does not neces <<
618 as it depends on the alternative fra <<
619 the kernel if an affected CPU is det <<
620 1201
621 If unsure, say Y. !! 1202 config HOLES_IN_ZONE
>> 1203 bool
622 1204
623 config ARM64_ERRATUM_843419 !! 1205 config SYS_SUPPORTS_RELOCATABLE
624 bool "Cortex-A53: 843419: A load or st !! 1206 bool
625 default y <<
626 help 1207 help
627 This option links the kernel with '- !! 1208 Selected if the platform supports relocating the kernel.
628 enables PLT support to replace certa !! 1209 The platform must provide plat_get_fdt() if it selects CONFIG_USE_OF
629 cause subsequent memory accesses to !! 1210 to allow access to command line and entropy sources.
630 Cortex-A53 parts up to r0p4. <<
631 1211
632 If unsure, say Y. !! 1212 config MIPS_CBPF_JIT
>> 1213 def_bool y
>> 1214 depends on BPF_JIT && HAVE_CBPF_JIT
633 1215
634 config ARM64_LD_HAS_FIX_ERRATUM_843419 !! 1216 config MIPS_EBPF_JIT
635 def_bool $(ld-option,--fix-cortex-a53- !! 1217 def_bool y
>> 1218 depends on BPF_JIT && HAVE_EBPF_JIT
636 1219
637 config ARM64_ERRATUM_1024718 !! 1220
638 bool "Cortex-A55: 1024718: Update of D !! 1221 #
639 default y !! 1222 # Endianness selection. Sufficiently obscure so many users don't know what to
>> 1223 # answer,so we try hard to limit the available choices. Also the use of a
>> 1224 # choice statement should be more obvious to the user.
>> 1225 #
>> 1226 choice
>> 1227 prompt "Endianness selection"
640 help 1228 help
641 This option adds a workaround for AR !! 1229 Some MIPS machines can be configured for either little or big endian
>> 1230 byte order. These modes require different kernels and a different
>> 1231 Linux distribution. In general there is one preferred byteorder for a
>> 1232 particular system but some systems are just as commonly used in the
>> 1233 one or the other endianness.
642 1234
643 Affected Cortex-A55 cores (all revis !! 1235 config CPU_BIG_ENDIAN
644 update of the hardware dirty bit whe !! 1236 bool "Big endian"
645 without a break-before-make. The wor !! 1237 depends on SYS_SUPPORTS_BIG_ENDIAN
646 of hardware DBM locally on the affec <<
647 this erratum will continue to use th <<
648 1238
649 If unsure, say Y. !! 1239 config CPU_LITTLE_ENDIAN
>> 1240 bool "Little endian"
>> 1241 depends on SYS_SUPPORTS_LITTLE_ENDIAN
650 1242
651 config ARM64_ERRATUM_1418040 !! 1243 endchoice
652 bool "Cortex-A76/Neoverse-N1: MRC read <<
653 default y <<
654 depends on COMPAT <<
655 help <<
656 This option adds a workaround for AR <<
657 errata 1188873 and 1418040. <<
658 1244
659 Affected Cortex-A76/Neoverse-N1 core !! 1245 config EXPORT_UASM
660 cause register corruption when acces !! 1246 bool
661 from AArch32 userspace. <<
662 1247
663 If unsure, say Y. !! 1248 config SYS_SUPPORTS_APM_EMULATION
>> 1249 bool
>> 1250
>> 1251 config SYS_SUPPORTS_BIG_ENDIAN
>> 1252 bool
664 1253
665 config ARM64_WORKAROUND_SPECULATIVE_AT !! 1254 config SYS_SUPPORTS_LITTLE_ENDIAN
666 bool 1255 bool
667 1256
668 config ARM64_ERRATUM_1165522 !! 1257 config SYS_SUPPORTS_HUGETLBFS
669 bool "Cortex-A76: 1165522: Speculative !! 1258 bool
>> 1259 depends on CPU_SUPPORTS_HUGEPAGES
670 default y 1260 default y
671 select ARM64_WORKAROUND_SPECULATIVE_AT <<
672 help <<
673 This option adds a workaround for AR <<
674 1261
675 Affected Cortex-A76 cores (r0p0, r1p !! 1262 config MIPS_HUGE_TLB_SUPPORT
676 corrupted TLBs by speculating an AT !! 1263 def_bool HUGETLB_PAGE || TRANSPARENT_HUGEPAGE
677 context switch. <<
678 1264
679 If unsure, say Y. !! 1265 config IRQ_CPU_RM7K
>> 1266 bool
680 1267
681 config ARM64_ERRATUM_1319367 !! 1268 config IRQ_MSP_SLP
682 bool "Cortex-A57/A72: 1319537: Specula !! 1269 bool
683 default y <<
684 select ARM64_WORKAROUND_SPECULATIVE_AT <<
685 help <<
686 This option adds work arounds for AR <<
687 and A72 erratum 1319367 <<
688 1270
689 Cortex-A57 and A72 cores could end-u !! 1271 config IRQ_MSP_CIC
690 speculating an AT instruction during !! 1272 bool
691 1273
692 If unsure, say Y. !! 1274 config IRQ_TXX9
>> 1275 bool
693 1276
694 config ARM64_ERRATUM_1530923 !! 1277 config IRQ_GT641XX
695 bool "Cortex-A55: 1530923: Speculative !! 1278 bool
696 default y <<
697 select ARM64_WORKAROUND_SPECULATIVE_AT <<
698 help <<
699 This option adds a workaround for AR <<
700 1279
701 Affected Cortex-A55 cores (r0p0, r0p !! 1280 config PCI_GT64XXX_PCI0
702 corrupted TLBs by speculating an AT !! 1281 bool
703 context switch. <<
704 1282
705 If unsure, say Y. !! 1283 config PCI_XTALK_BRIDGE
>> 1284 bool
706 1285
707 config ARM64_WORKAROUND_REPEAT_TLBI !! 1286 config NO_EXCEPT_FILL
708 bool 1287 bool
709 1288
710 config ARM64_ERRATUM_2441007 !! 1289 config MIPS_SPRAM
711 bool "Cortex-A55: Completion of affect !! 1290 bool
712 select ARM64_WORKAROUND_REPEAT_TLBI <<
713 help <<
714 This option adds a workaround for AR <<
715 1291
716 Under very rare circumstances, affec !! 1292 config SWAP_IO_SPACE
717 may not handle a race between a brea !! 1293 bool
718 CPU, and another CPU accessing the s <<
719 store to a page that has been unmapp <<
720 1294
721 Work around this by adding the affec !! 1295 config SGI_HAS_INDYDOG
722 TLB sequences to be done twice. !! 1296 bool
723 1297
724 If unsure, say N. !! 1298 config SGI_HAS_HAL2
>> 1299 bool
725 1300
726 config ARM64_ERRATUM_1286807 !! 1301 config SGI_HAS_SEEQ
727 bool "Cortex-A76: Modification of the !! 1302 bool
728 select ARM64_WORKAROUND_REPEAT_TLBI <<
729 help <<
730 This option adds a workaround for AR <<
731 <<
732 On the affected Cortex-A76 cores (r0 <<
733 address for a cacheable mapping of a <<
734 accessed by a core while another cor <<
735 address to a new physical page using <<
736 break-before-make sequence, then und <<
737 TLBI+DSB completes before a read usi <<
738 invalidated has been observed by oth <<
739 workaround repeats the TLBI+DSB oper <<
740 1303
741 If unsure, say N. !! 1304 config SGI_HAS_WD93
>> 1305 bool
742 1306
743 config ARM64_ERRATUM_1463225 !! 1307 config SGI_HAS_ZILOG
744 bool "Cortex-A76: Software Step might !! 1308 bool
745 default y <<
746 help <<
747 This option adds a workaround for Ar <<
748 1309
749 On the affected Cortex-A76 cores (r0 !! 1310 config SGI_HAS_I8042
750 of a system call instruction (SVC) c !! 1311 bool
751 subsequent interrupts when software <<
752 exception handler of the system call <<
753 is enabled or VHE is in use. <<
754 1312
755 Work around the erratum by triggerin !! 1313 config DEFAULT_SGI_PARTITION
756 when handling a system call from a t !! 1314 bool
757 in a VHE configuration of the kernel <<
758 1315
759 If unsure, say Y. !! 1316 config FW_ARC32
>> 1317 bool
760 1318
761 config ARM64_ERRATUM_1542419 !! 1319 config FW_SNIPROM
762 bool "Neoverse-N1: workaround mis-orde !! 1320 bool
763 help <<
764 This option adds a workaround for AR <<
765 1542419. <<
766 1321
767 Affected Neoverse-N1 cores could exe !! 1322 config BOOT_ELF32
768 modified by another CPU. The workaro !! 1323 bool
769 counterpart. <<
770 1324
771 Workaround the issue by hiding the D !! 1325 config MIPS_L1_CACHE_SHIFT_4
772 forces user-space to perform cache m !! 1326 bool
773 1327
774 If unsure, say N. !! 1328 config MIPS_L1_CACHE_SHIFT_5
>> 1329 bool
775 1330
776 config ARM64_ERRATUM_1508412 !! 1331 config MIPS_L1_CACHE_SHIFT_6
777 bool "Cortex-A77: 1508412: workaround !! 1332 bool
778 default y <<
779 help <<
780 This option adds a workaround for Ar <<
781 1333
782 Affected Cortex-A77 cores (r0p0, r1p !! 1334 config MIPS_L1_CACHE_SHIFT_7
783 of a store-exclusive or read of PAR_ !! 1335 bool
784 non-cacheable memory attributes. The <<
785 counterpart. <<
786 1336
787 KVM guests must also have the workar !! 1337 config MIPS_L1_CACHE_SHIFT
788 deadlock the system. !! 1338 int
>> 1339 default "7" if MIPS_L1_CACHE_SHIFT_7
>> 1340 default "6" if MIPS_L1_CACHE_SHIFT_6
>> 1341 default "5" if MIPS_L1_CACHE_SHIFT_5
>> 1342 default "4" if MIPS_L1_CACHE_SHIFT_4
>> 1343 default "5"
789 1344
790 Work around the issue by inserting D !! 1345 config ARC_CMDLINE_ONLY
791 register reads and warning KVM users !! 1346 bool
792 to prevent a speculative PAR_EL1 rea <<
793 1347
794 If unsure, say Y. !! 1348 config ARC_CONSOLE
>> 1349 bool "ARC console support"
>> 1350 depends on SGI_IP22 || SGI_IP28 || (SNI_RM && CPU_LITTLE_ENDIAN)
795 1351
796 config ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MO !! 1352 config ARC_MEMORY
797 bool 1353 bool
798 1354
799 config ARM64_ERRATUM_2051678 !! 1355 config ARC_PROMLIB
800 bool "Cortex-A510: 2051678: disable Ha !! 1356 bool
801 default y <<
802 help <<
803 This options adds the workaround for <<
804 Affected Cortex-A510 might not respe <<
805 hardware update of the page table's <<
806 is to not enable the feature on affe <<
807 <<
808 If unsure, say Y. <<
809 1357
810 config ARM64_ERRATUM_2077057 !! 1358 config FW_ARC64
811 bool "Cortex-A510: 2077057: workaround !! 1359 bool
812 default y <<
813 help <<
814 This option adds the workaround for <<
815 Affected Cortex-A510 may corrupt SPS <<
816 expected, but a Pointer Authenticati <<
817 erratum causes SPSR_EL1 to be copied <<
818 EL1 to cause a return to EL2 with a <<
819 1360
820 This can only happen when EL2 is ste !! 1361 config BOOT_ELF64
>> 1362 bool
821 1363
822 When these conditions occur, the SPS !! 1364 menu "CPU selection"
823 previous guest entry, and can be res <<
824 1365
825 If unsure, say Y. !! 1366 choice
>> 1367 prompt "CPU type"
>> 1368 default CPU_R4X00
826 1369
827 config ARM64_ERRATUM_2658417 !! 1370 config CPU_LOONGSON64
828 bool "Cortex-A510: 2658417: remove BF1 !! 1371 bool "Loongson 64-bit CPU"
829 default y !! 1372 depends on SYS_HAS_CPU_LOONGSON64
>> 1373 select ARCH_HAS_PHYS_TO_DMA
>> 1374 select CPU_MIPSR2
>> 1375 select CPU_HAS_PREFETCH
>> 1376 select CPU_SUPPORTS_64BIT_KERNEL
>> 1377 select CPU_SUPPORTS_HIGHMEM
>> 1378 select CPU_SUPPORTS_HUGEPAGES
>> 1379 select CPU_SUPPORTS_MSA
>> 1380 select CPU_DIEI_BROKEN if !LOONGSON3_ENHANCEMENT
>> 1381 select CPU_MIPSR2_IRQ_VI
>> 1382 select WEAK_ORDERING
>> 1383 select WEAK_REORDERING_BEYOND_LLSC
>> 1384 select MIPS_ASID_BITS_VARIABLE
>> 1385 select MIPS_PGD_C0_CONTEXT
>> 1386 select MIPS_L1_CACHE_SHIFT_6
>> 1387 select MIPS_FP_SUPPORT
>> 1388 select GPIOLIB
>> 1389 select SWIOTLB
>> 1390 select HAVE_KVM
830 help 1391 help
831 This option adds the workaround for !! 1392 The Loongson GSx64(GS264/GS464/GS464E/GS464V) series of processor
832 Affected Cortex-A510 (r0p0 to r1p1) !! 1393 cores implements the MIPS64R2 instruction set with many extensions,
833 BFMMLA or VMMLA instructions in rare !! 1394 including most 64-bit Loongson-2 (2H, 2K) and Loongson-3 (3A1000,
834 A510 CPUs are using shared neon hard !! 1395 3B1000, 3B1500, 3A2000, 3A3000 and 3A4000) processors. However, old
835 discoverable by the kernel, hide the !! 1396 Loongson-2E/2F is not covered here and will be removed in future.
836 user-space should not be using these <<
837 <<
838 If unsure, say Y. <<
839 1397
840 config ARM64_ERRATUM_2119858 !! 1398 config LOONGSON3_ENHANCEMENT
841 bool "Cortex-A710/X2: 2119858: workaro !! 1399 bool "New Loongson-3 CPU Enhancements"
842 default y !! 1400 default n
843 depends on CORESIGHT_TRBE !! 1401 depends on CPU_LOONGSON64
844 select ARM64_WORKAROUND_TRBE_OVERWRITE <<
845 help 1402 help
846 This option adds the workaround for !! 1403 New Loongson-3 cores (since Loongson-3A R2, as opposed to Loongson-3A
847 !! 1404 R1, Loongson-3B R1 and Loongson-3B R2) has many enhancements, such as
848 Affected Cortex-A710/X2 cores could !! 1405 FTLB, L1-VCache, EI/DI/Wait/Prefetch instruction, DSP/DSPr2 ASE, User
849 data at the base of the buffer (poin !! 1406 Local register, Read-Inhibit/Execute-Inhibit, SFB (Store Fill Buffer),
850 the event of a WRAP event. !! 1407 Fast TLB refill support, etc.
851 !! 1408
852 Work around the issue by always maki !! 1409 This option enable those enhancements which are not probed at run
853 256 bytes before enabling the buffer !! 1410 time. If you want a generic kernel to run on all Loongson 3 machines,
854 the buffer with ETM ignore packets u !! 1411 please say 'N' here. If you want a high-performance kernel to run on
855 !! 1412 new Loongson-3 machines only, please say 'Y' here.
856 If unsure, say Y. !! 1413
857 !! 1414 config CPU_LOONGSON3_WORKAROUNDS
858 config ARM64_ERRATUM_2139208 !! 1415 bool "Old Loongson-3 LLSC Workarounds"
859 bool "Neoverse-N2: 2139208: workaround !! 1416 default y if SMP
860 default y !! 1417 depends on CPU_LOONGSON64
861 depends on CORESIGHT_TRBE !! 1418 help
862 select ARM64_WORKAROUND_TRBE_OVERWRITE !! 1419 Loongson-3 processors have the llsc issues which require workarounds.
>> 1420 Without workarounds the system may hang unexpectedly.
>> 1421
>> 1422 Newer Loongson-3 will fix these issues and no workarounds are needed.
>> 1423 The workarounds have no significant side effect on them but may
>> 1424 decrease the performance of the system so this option should be
>> 1425 disabled unless the kernel is intended to be run on old systems.
>> 1426
>> 1427 If unsure, please say Y.
>> 1428
>> 1429 config CPU_LOONGSON3_CPUCFG_EMULATION
>> 1430 bool "Emulate the CPUCFG instruction on older Loongson cores"
>> 1431 default y
>> 1432 depends on CPU_LOONGSON64
>> 1433 help
>> 1434 Loongson-3A R4 and newer have the CPUCFG instruction available for
>> 1435 userland to query CPU capabilities, much like CPUID on x86. This
>> 1436 option provides emulation of the instruction on older Loongson
>> 1437 cores, back to Loongson-3A1000.
>> 1438
>> 1439 If unsure, please say Y.
>> 1440
>> 1441 config CPU_LOONGSON2E
>> 1442 bool "Loongson 2E"
>> 1443 depends on SYS_HAS_CPU_LOONGSON2E
>> 1444 select CPU_LOONGSON2EF
>> 1445 help
>> 1446 The Loongson 2E processor implements the MIPS III instruction set
>> 1447 with many extensions.
>> 1448
>> 1449 It has an internal FPGA northbridge, which is compatible to
>> 1450 bonito64.
>> 1451
>> 1452 config CPU_LOONGSON2F
>> 1453 bool "Loongson 2F"
>> 1454 depends on SYS_HAS_CPU_LOONGSON2F
>> 1455 select CPU_LOONGSON2EF
>> 1456 select GPIOLIB
>> 1457 help
>> 1458 The Loongson 2F processor implements the MIPS III instruction set
>> 1459 with many extensions.
>> 1460
>> 1461 Loongson2F have built-in DDR2 and PCIX controller. The PCIX controller
>> 1462 have a similar programming interface with FPGA northbridge used in
>> 1463 Loongson2E.
>> 1464
>> 1465 config CPU_LOONGSON1B
>> 1466 bool "Loongson 1B"
>> 1467 depends on SYS_HAS_CPU_LOONGSON1B
>> 1468 select CPU_LOONGSON32
>> 1469 select LEDS_GPIO_REGISTER
>> 1470 help
>> 1471 The Loongson 1B is a 32-bit SoC, which implements the MIPS32
>> 1472 Release 1 instruction set and part of the MIPS32 Release 2
>> 1473 instruction set.
>> 1474
>> 1475 config CPU_LOONGSON1C
>> 1476 bool "Loongson 1C"
>> 1477 depends on SYS_HAS_CPU_LOONGSON1C
>> 1478 select CPU_LOONGSON32
>> 1479 select LEDS_GPIO_REGISTER
>> 1480 help
>> 1481 The Loongson 1C is a 32-bit SoC, which implements the MIPS32
>> 1482 Release 1 instruction set and part of the MIPS32 Release 2
>> 1483 instruction set.
>> 1484
>> 1485 config CPU_MIPS32_R1
>> 1486 bool "MIPS32 Release 1"
>> 1487 depends on SYS_HAS_CPU_MIPS32_R1
>> 1488 select CPU_HAS_PREFETCH
>> 1489 select CPU_SUPPORTS_32BIT_KERNEL
>> 1490 select CPU_SUPPORTS_HIGHMEM
>> 1491 help
>> 1492 Choose this option to build a kernel for release 1 or later of the
>> 1493 MIPS32 architecture. Most modern embedded systems with a 32-bit
>> 1494 MIPS processor are based on a MIPS32 processor. If you know the
>> 1495 specific type of processor in your system, choose those that one
>> 1496 otherwise CPU_MIPS32_R1 is a safe bet for any MIPS32 system.
>> 1497 Release 2 of the MIPS32 architecture is available since several
>> 1498 years so chances are you even have a MIPS32 Release 2 processor
>> 1499 in which case you should choose CPU_MIPS32_R2 instead for better
>> 1500 performance.
>> 1501
>> 1502 config CPU_MIPS32_R2
>> 1503 bool "MIPS32 Release 2"
>> 1504 depends on SYS_HAS_CPU_MIPS32_R2
>> 1505 select CPU_HAS_PREFETCH
>> 1506 select CPU_SUPPORTS_32BIT_KERNEL
>> 1507 select CPU_SUPPORTS_HIGHMEM
>> 1508 select CPU_SUPPORTS_MSA
>> 1509 select HAVE_KVM
>> 1510 help
>> 1511 Choose this option to build a kernel for release 2 or later of the
>> 1512 MIPS32 architecture. Most modern embedded systems with a 32-bit
>> 1513 MIPS processor are based on a MIPS32 processor. If you know the
>> 1514 specific type of processor in your system, choose those that one
>> 1515 otherwise CPU_MIPS32_R1 is a safe bet for any MIPS32 system.
>> 1516
>> 1517 config CPU_MIPS32_R5
>> 1518 bool "MIPS32 Release 5"
>> 1519 depends on SYS_HAS_CPU_MIPS32_R5
>> 1520 select CPU_HAS_PREFETCH
>> 1521 select CPU_SUPPORTS_32BIT_KERNEL
>> 1522 select CPU_SUPPORTS_HIGHMEM
>> 1523 select CPU_SUPPORTS_MSA
>> 1524 select HAVE_KVM
>> 1525 select MIPS_O32_FP64_SUPPORT
>> 1526 help
>> 1527 Choose this option to build a kernel for release 5 or later of the
>> 1528 MIPS32 architecture. New MIPS processors, starting with the Warrior
>> 1529 family, are based on a MIPS32r5 processor. If you own an older
>> 1530 processor, you probably need to select MIPS32r1 or MIPS32r2 instead.
>> 1531
>> 1532 config CPU_MIPS32_R6
>> 1533 bool "MIPS32 Release 6"
>> 1534 depends on SYS_HAS_CPU_MIPS32_R6
>> 1535 select CPU_HAS_PREFETCH
>> 1536 select CPU_NO_LOAD_STORE_LR
>> 1537 select CPU_SUPPORTS_32BIT_KERNEL
>> 1538 select CPU_SUPPORTS_HIGHMEM
>> 1539 select CPU_SUPPORTS_MSA
>> 1540 select HAVE_KVM
>> 1541 select MIPS_O32_FP64_SUPPORT
>> 1542 help
>> 1543 Choose this option to build a kernel for release 6 or later of the
>> 1544 MIPS32 architecture. New MIPS processors, starting with the Warrior
>> 1545 family, are based on a MIPS32r6 processor. If you own an older
>> 1546 processor, you probably need to select MIPS32r1 or MIPS32r2 instead.
>> 1547
>> 1548 config CPU_MIPS64_R1
>> 1549 bool "MIPS64 Release 1"
>> 1550 depends on SYS_HAS_CPU_MIPS64_R1
>> 1551 select CPU_HAS_PREFETCH
>> 1552 select CPU_SUPPORTS_32BIT_KERNEL
>> 1553 select CPU_SUPPORTS_64BIT_KERNEL
>> 1554 select CPU_SUPPORTS_HIGHMEM
>> 1555 select CPU_SUPPORTS_HUGEPAGES
>> 1556 help
>> 1557 Choose this option to build a kernel for release 1 or later of the
>> 1558 MIPS64 architecture. Many modern embedded systems with a 64-bit
>> 1559 MIPS processor are based on a MIPS64 processor. If you know the
>> 1560 specific type of processor in your system, choose those that one
>> 1561 otherwise CPU_MIPS64_R1 is a safe bet for any MIPS64 system.
>> 1562 Release 2 of the MIPS64 architecture is available since several
>> 1563 years so chances are you even have a MIPS64 Release 2 processor
>> 1564 in which case you should choose CPU_MIPS64_R2 instead for better
>> 1565 performance.
>> 1566
>> 1567 config CPU_MIPS64_R2
>> 1568 bool "MIPS64 Release 2"
>> 1569 depends on SYS_HAS_CPU_MIPS64_R2
>> 1570 select CPU_HAS_PREFETCH
>> 1571 select CPU_SUPPORTS_32BIT_KERNEL
>> 1572 select CPU_SUPPORTS_64BIT_KERNEL
>> 1573 select CPU_SUPPORTS_HIGHMEM
>> 1574 select CPU_SUPPORTS_HUGEPAGES
>> 1575 select CPU_SUPPORTS_MSA
>> 1576 select HAVE_KVM
>> 1577 help
>> 1578 Choose this option to build a kernel for release 2 or later of the
>> 1579 MIPS64 architecture. Many modern embedded systems with a 64-bit
>> 1580 MIPS processor are based on a MIPS64 processor. If you know the
>> 1581 specific type of processor in your system, choose those that one
>> 1582 otherwise CPU_MIPS64_R1 is a safe bet for any MIPS64 system.
>> 1583
>> 1584 config CPU_MIPS64_R5
>> 1585 bool "MIPS64 Release 5"
>> 1586 depends on SYS_HAS_CPU_MIPS64_R5
>> 1587 select CPU_HAS_PREFETCH
>> 1588 select CPU_SUPPORTS_32BIT_KERNEL
>> 1589 select CPU_SUPPORTS_64BIT_KERNEL
>> 1590 select CPU_SUPPORTS_HIGHMEM
>> 1591 select CPU_SUPPORTS_HUGEPAGES
>> 1592 select CPU_SUPPORTS_MSA
>> 1593 select MIPS_O32_FP64_SUPPORT if 32BIT || MIPS32_O32
>> 1594 select HAVE_KVM
>> 1595 help
>> 1596 Choose this option to build a kernel for release 5 or later of the
>> 1597 MIPS64 architecture. This is a intermediate MIPS architecture
>> 1598 release partly implementing release 6 features. Though there is no
>> 1599 any hardware known to be based on this release.
>> 1600
>> 1601 config CPU_MIPS64_R6
>> 1602 bool "MIPS64 Release 6"
>> 1603 depends on SYS_HAS_CPU_MIPS64_R6
>> 1604 select CPU_HAS_PREFETCH
>> 1605 select CPU_NO_LOAD_STORE_LR
>> 1606 select CPU_SUPPORTS_32BIT_KERNEL
>> 1607 select CPU_SUPPORTS_64BIT_KERNEL
>> 1608 select CPU_SUPPORTS_HIGHMEM
>> 1609 select CPU_SUPPORTS_HUGEPAGES
>> 1610 select CPU_SUPPORTS_MSA
>> 1611 select MIPS_O32_FP64_SUPPORT if 32BIT || MIPS32_O32
>> 1612 select HAVE_KVM
>> 1613 help
>> 1614 Choose this option to build a kernel for release 6 or later of the
>> 1615 MIPS64 architecture. New MIPS processors, starting with the Warrior
>> 1616 family, are based on a MIPS64r6 processor. If you own an older
>> 1617 processor, you probably need to select MIPS64r1 or MIPS64r2 instead.
>> 1618
>> 1619 config CPU_P5600
>> 1620 bool "MIPS Warrior P5600"
>> 1621 depends on SYS_HAS_CPU_P5600
>> 1622 select CPU_HAS_PREFETCH
>> 1623 select CPU_SUPPORTS_32BIT_KERNEL
>> 1624 select CPU_SUPPORTS_HIGHMEM
>> 1625 select CPU_SUPPORTS_MSA
>> 1626 select CPU_SUPPORTS_CPUFREQ
>> 1627 select CPU_MIPSR2_IRQ_VI
>> 1628 select CPU_MIPSR2_IRQ_EI
>> 1629 select HAVE_KVM
>> 1630 select MIPS_O32_FP64_SUPPORT
>> 1631 help
>> 1632 Choose this option to build a kernel for MIPS Warrior P5600 CPU.
>> 1633 It's based on MIPS32r5 ISA with XPA, EVA, dual/quad issue exec pipes,
>> 1634 MMU with two-levels TLB, UCA, MSA, MDU core level features and system
>> 1635 level features like up to six P5600 calculation cores, CM2 with L2
>> 1636 cache, IOCU/IOMMU (though might be unused depending on the system-
>> 1637 specific IP core configuration), GIC, CPC, virtualisation module,
>> 1638 eJTAG and PDtrace.
>> 1639
>> 1640 config CPU_R3000
>> 1641 bool "R3000"
>> 1642 depends on SYS_HAS_CPU_R3000
>> 1643 select CPU_HAS_WB
>> 1644 select CPU_R3K_TLB
>> 1645 select CPU_SUPPORTS_32BIT_KERNEL
>> 1646 select CPU_SUPPORTS_HIGHMEM
>> 1647 help
>> 1648 Please make sure to pick the right CPU type. Linux/MIPS is not
>> 1649 designed to be generic, i.e. Kernels compiled for R3000 CPUs will
>> 1650 *not* work on R4000 machines and vice versa. However, since most
>> 1651 of the supported machines have an R4000 (or similar) CPU, R4x00
>> 1652 might be a safe bet. If the resulting kernel does not work,
>> 1653 try to recompile with R3000.
>> 1654
>> 1655 config CPU_TX39XX
>> 1656 bool "R39XX"
>> 1657 depends on SYS_HAS_CPU_TX39XX
>> 1658 select CPU_SUPPORTS_32BIT_KERNEL
>> 1659 select CPU_R3K_TLB
>> 1660
>> 1661 config CPU_VR41XX
>> 1662 bool "R41xx"
>> 1663 depends on SYS_HAS_CPU_VR41XX
>> 1664 select CPU_SUPPORTS_32BIT_KERNEL
>> 1665 select CPU_SUPPORTS_64BIT_KERNEL
>> 1666 help
>> 1667 The options selects support for the NEC VR4100 series of processors.
>> 1668 Only choose this option if you have one of these processors as a
>> 1669 kernel built with this option will not run on any other type of
>> 1670 processor or vice versa.
>> 1671
>> 1672 config CPU_R4X00
>> 1673 bool "R4x00"
>> 1674 depends on SYS_HAS_CPU_R4X00
>> 1675 select CPU_SUPPORTS_32BIT_KERNEL
>> 1676 select CPU_SUPPORTS_64BIT_KERNEL
>> 1677 select CPU_SUPPORTS_HUGEPAGES
>> 1678 help
>> 1679 MIPS Technologies R4000-series processors other than 4300, including
>> 1680 the R4000, R4400, R4600, and 4700.
>> 1681
>> 1682 config CPU_TX49XX
>> 1683 bool "R49XX"
>> 1684 depends on SYS_HAS_CPU_TX49XX
>> 1685 select CPU_HAS_PREFETCH
>> 1686 select CPU_SUPPORTS_32BIT_KERNEL
>> 1687 select CPU_SUPPORTS_64BIT_KERNEL
>> 1688 select CPU_SUPPORTS_HUGEPAGES
>> 1689
>> 1690 config CPU_R5000
>> 1691 bool "R5000"
>> 1692 depends on SYS_HAS_CPU_R5000
>> 1693 select CPU_SUPPORTS_32BIT_KERNEL
>> 1694 select CPU_SUPPORTS_64BIT_KERNEL
>> 1695 select CPU_SUPPORTS_HUGEPAGES
>> 1696 help
>> 1697 MIPS Technologies R5000-series processors other than the Nevada.
>> 1698
>> 1699 config CPU_R5500
>> 1700 bool "R5500"
>> 1701 depends on SYS_HAS_CPU_R5500
>> 1702 select CPU_SUPPORTS_32BIT_KERNEL
>> 1703 select CPU_SUPPORTS_64BIT_KERNEL
>> 1704 select CPU_SUPPORTS_HUGEPAGES
>> 1705 help
>> 1706 NEC VR5500 and VR5500A series processors implement 64-bit MIPS IV
>> 1707 instruction set.
>> 1708
>> 1709 config CPU_NEVADA
>> 1710 bool "RM52xx"
>> 1711 depends on SYS_HAS_CPU_NEVADA
>> 1712 select CPU_SUPPORTS_32BIT_KERNEL
>> 1713 select CPU_SUPPORTS_64BIT_KERNEL
>> 1714 select CPU_SUPPORTS_HUGEPAGES
>> 1715 help
>> 1716 QED / PMC-Sierra RM52xx-series ("Nevada") processors.
>> 1717
>> 1718 config CPU_R10000
>> 1719 bool "R10000"
>> 1720 depends on SYS_HAS_CPU_R10000
>> 1721 select CPU_HAS_PREFETCH
>> 1722 select CPU_SUPPORTS_32BIT_KERNEL
>> 1723 select CPU_SUPPORTS_64BIT_KERNEL
>> 1724 select CPU_SUPPORTS_HIGHMEM
>> 1725 select CPU_SUPPORTS_HUGEPAGES
>> 1726 help
>> 1727 MIPS Technologies R10000-series processors.
>> 1728
>> 1729 config CPU_RM7000
>> 1730 bool "RM7000"
>> 1731 depends on SYS_HAS_CPU_RM7000
>> 1732 select CPU_HAS_PREFETCH
>> 1733 select CPU_SUPPORTS_32BIT_KERNEL
>> 1734 select CPU_SUPPORTS_64BIT_KERNEL
>> 1735 select CPU_SUPPORTS_HIGHMEM
>> 1736 select CPU_SUPPORTS_HUGEPAGES
>> 1737
>> 1738 config CPU_SB1
>> 1739 bool "SB1"
>> 1740 depends on SYS_HAS_CPU_SB1
>> 1741 select CPU_SUPPORTS_32BIT_KERNEL
>> 1742 select CPU_SUPPORTS_64BIT_KERNEL
>> 1743 select CPU_SUPPORTS_HIGHMEM
>> 1744 select CPU_SUPPORTS_HUGEPAGES
>> 1745 select WEAK_ORDERING
>> 1746
>> 1747 config CPU_CAVIUM_OCTEON
>> 1748 bool "Cavium Octeon processor"
>> 1749 depends on SYS_HAS_CPU_CAVIUM_OCTEON
>> 1750 select CPU_HAS_PREFETCH
>> 1751 select CPU_SUPPORTS_64BIT_KERNEL
>> 1752 select WEAK_ORDERING
>> 1753 select CPU_SUPPORTS_HIGHMEM
>> 1754 select CPU_SUPPORTS_HUGEPAGES
>> 1755 select USB_EHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 1756 select USB_OHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 1757 select MIPS_L1_CACHE_SHIFT_7
>> 1758 select HAVE_KVM
>> 1759 help
>> 1760 The Cavium Octeon processor is a highly integrated chip containing
>> 1761 many ethernet hardware widgets for networking tasks. The processor
>> 1762 can have up to 16 Mips64v2 cores and 8 integrated gigabit ethernets.
>> 1763 Full details can be found at http://www.caviumnetworks.com.
>> 1764
>> 1765 config CPU_BMIPS
>> 1766 bool "Broadcom BMIPS"
>> 1767 depends on SYS_HAS_CPU_BMIPS
>> 1768 select CPU_MIPS32
>> 1769 select CPU_BMIPS32_3300 if SYS_HAS_CPU_BMIPS32_3300
>> 1770 select CPU_BMIPS4350 if SYS_HAS_CPU_BMIPS4350
>> 1771 select CPU_BMIPS4380 if SYS_HAS_CPU_BMIPS4380
>> 1772 select CPU_BMIPS5000 if SYS_HAS_CPU_BMIPS5000
>> 1773 select CPU_SUPPORTS_32BIT_KERNEL
>> 1774 select DMA_NONCOHERENT
>> 1775 select IRQ_MIPS_CPU
>> 1776 select SWAP_IO_SPACE
>> 1777 select WEAK_ORDERING
>> 1778 select CPU_SUPPORTS_HIGHMEM
>> 1779 select CPU_HAS_PREFETCH
>> 1780 select CPU_SUPPORTS_CPUFREQ
>> 1781 select MIPS_EXTERNAL_TIMER
>> 1782 help
>> 1783 Support for BMIPS32/3300/4350/4380 and BMIPS5000 processors.
>> 1784
>> 1785 config CPU_XLR
>> 1786 bool "Netlogic XLR SoC"
>> 1787 depends on SYS_HAS_CPU_XLR
>> 1788 select CPU_SUPPORTS_32BIT_KERNEL
>> 1789 select CPU_SUPPORTS_64BIT_KERNEL
>> 1790 select CPU_SUPPORTS_HIGHMEM
>> 1791 select CPU_SUPPORTS_HUGEPAGES
>> 1792 select WEAK_ORDERING
>> 1793 select WEAK_REORDERING_BEYOND_LLSC
>> 1794 help
>> 1795 Netlogic Microsystems XLR/XLS processors.
>> 1796
>> 1797 config CPU_XLP
>> 1798 bool "Netlogic XLP SoC"
>> 1799 depends on SYS_HAS_CPU_XLP
>> 1800 select CPU_SUPPORTS_32BIT_KERNEL
>> 1801 select CPU_SUPPORTS_64BIT_KERNEL
>> 1802 select CPU_SUPPORTS_HIGHMEM
>> 1803 select WEAK_ORDERING
>> 1804 select WEAK_REORDERING_BEYOND_LLSC
>> 1805 select CPU_HAS_PREFETCH
>> 1806 select CPU_MIPSR2
>> 1807 select CPU_SUPPORTS_HUGEPAGES
>> 1808 select MIPS_ASID_BITS_VARIABLE
863 help 1809 help
864 This option adds the workaround for !! 1810 Netlogic Microsystems XLP processors.
865 !! 1811 endchoice
866 Affected Neoverse-N2 cores could ove <<
867 data at the base of the buffer (poin <<
868 the event of a WRAP event. <<
869 1812
870 Work around the issue by always maki !! 1813 config CPU_MIPS32_3_5_FEATURES
871 256 bytes before enabling the buffer !! 1814 bool "MIPS32 Release 3.5 Features"
872 the buffer with ETM ignore packets u !! 1815 depends on SYS_HAS_CPU_MIPS32_R3_5
>> 1816 depends on CPU_MIPS32_R2 || CPU_MIPS32_R5 || CPU_MIPS32_R6 || \
>> 1817 CPU_P5600
>> 1818 help
>> 1819 Choose this option to build a kernel for release 2 or later of the
>> 1820 MIPS32 architecture including features from the 3.5 release such as
>> 1821 support for Enhanced Virtual Addressing (EVA).
>> 1822
>> 1823 config CPU_MIPS32_3_5_EVA
>> 1824 bool "Enhanced Virtual Addressing (EVA)"
>> 1825 depends on CPU_MIPS32_3_5_FEATURES
>> 1826 select EVA
>> 1827 default y
>> 1828 help
>> 1829 Choose this option if you want to enable the Enhanced Virtual
>> 1830 Addressing (EVA) on your MIPS32 core (such as proAptiv).
>> 1831 One of its primary benefits is an increase in the maximum size
>> 1832 of lowmem (up to 3GB). If unsure, say 'N' here.
>> 1833
>> 1834 config CPU_MIPS32_R5_FEATURES
>> 1835 bool "MIPS32 Release 5 Features"
>> 1836 depends on SYS_HAS_CPU_MIPS32_R5
>> 1837 depends on CPU_MIPS32_R2 || CPU_MIPS32_R5 || CPU_P5600
>> 1838 help
>> 1839 Choose this option to build a kernel for release 2 or later of the
>> 1840 MIPS32 architecture including features from release 5 such as
>> 1841 support for Extended Physical Addressing (XPA).
>> 1842
>> 1843 config CPU_MIPS32_R5_XPA
>> 1844 bool "Extended Physical Addressing (XPA)"
>> 1845 depends on CPU_MIPS32_R5_FEATURES
>> 1846 depends on !EVA
>> 1847 depends on !PAGE_SIZE_4KB
>> 1848 depends on SYS_SUPPORTS_HIGHMEM
>> 1849 select XPA
>> 1850 select HIGHMEM
>> 1851 select PHYS_ADDR_T_64BIT
>> 1852 default n
>> 1853 help
>> 1854 Choose this option if you want to enable the Extended Physical
>> 1855 Addressing (XPA) on your MIPS32 core (such as P5600 series). The
>> 1856 benefit is to increase physical addressing equal to or greater
>> 1857 than 40 bits. Note that this has the side effect of turning on
>> 1858 64-bit addressing which in turn makes the PTEs 64-bit in size.
>> 1859 If unsure, say 'N' here.
873 1860
874 If unsure, say Y. !! 1861 if CPU_LOONGSON2F
>> 1862 config CPU_NOP_WORKAROUNDS
>> 1863 bool
875 1864
876 config ARM64_WORKAROUND_TSB_FLUSH_FAILURE !! 1865 config CPU_JUMP_WORKAROUNDS
877 bool 1866 bool
878 1867
879 config ARM64_ERRATUM_2054223 !! 1868 config CPU_LOONGSON2F_WORKAROUNDS
880 bool "Cortex-A710: 2054223: workaround !! 1869 bool "Loongson 2F Workarounds"
881 default y 1870 default y
882 select ARM64_WORKAROUND_TSB_FLUSH_FAIL !! 1871 select CPU_NOP_WORKAROUNDS
>> 1872 select CPU_JUMP_WORKAROUNDS
883 help 1873 help
884 Enable workaround for ARM Cortex-A71 !! 1874 Loongson 2F01 / 2F02 processors have the NOP & JUMP issues which
885 !! 1875 require workarounds. Without workarounds the system may hang
886 Affected cores may fail to flush the !! 1876 unexpectedly. For more information please refer to the gas
887 the PE is in trace prohibited state. !! 1877 -mfix-loongson2f-nop and -mfix-loongson2f-jump options.
888 of the trace cached. !! 1878
889 !! 1879 Loongson 2F03 and later have fixed these issues and no workarounds
890 Workaround is to issue two TSB conse !! 1880 are needed. The workarounds have no significant side effect on them
>> 1881 but may decrease the performance of the system so this option should
>> 1882 be disabled unless the kernel is intended to be run on 2F01 or 2F02
>> 1883 systems.
891 1884
892 If unsure, say Y. !! 1885 If unsure, please say Y.
>> 1886 endif # CPU_LOONGSON2F
893 1887
894 config ARM64_ERRATUM_2067961 !! 1888 config SYS_SUPPORTS_ZBOOT
895 bool "Neoverse-N2: 2067961: workaround !! 1889 bool
896 default y !! 1890 select HAVE_KERNEL_GZIP
897 select ARM64_WORKAROUND_TSB_FLUSH_FAIL !! 1891 select HAVE_KERNEL_BZIP2
898 help !! 1892 select HAVE_KERNEL_LZ4
899 Enable workaround for ARM Neoverse-N !! 1893 select HAVE_KERNEL_LZMA
>> 1894 select HAVE_KERNEL_LZO
>> 1895 select HAVE_KERNEL_XZ
>> 1896 select HAVE_KERNEL_ZSTD
900 1897
901 Affected cores may fail to flush the !! 1898 config SYS_SUPPORTS_ZBOOT_UART16550
902 the PE is in trace prohibited state. !! 1899 bool
903 of the trace cached. !! 1900 select SYS_SUPPORTS_ZBOOT
904 1901
905 Workaround is to issue two TSB conse !! 1902 config SYS_SUPPORTS_ZBOOT_UART_PROM
>> 1903 bool
>> 1904 select SYS_SUPPORTS_ZBOOT
906 1905
907 If unsure, say Y. !! 1906 config CPU_LOONGSON2EF
>> 1907 bool
>> 1908 select CPU_SUPPORTS_32BIT_KERNEL
>> 1909 select CPU_SUPPORTS_64BIT_KERNEL
>> 1910 select CPU_SUPPORTS_HIGHMEM
>> 1911 select CPU_SUPPORTS_HUGEPAGES
>> 1912 select ARCH_HAS_PHYS_TO_DMA
908 1913
909 config ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANG !! 1914 config CPU_LOONGSON32
910 bool 1915 bool
>> 1916 select CPU_MIPS32
>> 1917 select CPU_MIPSR2
>> 1918 select CPU_HAS_PREFETCH
>> 1919 select CPU_SUPPORTS_32BIT_KERNEL
>> 1920 select CPU_SUPPORTS_HIGHMEM
>> 1921 select CPU_SUPPORTS_CPUFREQ
911 1922
912 config ARM64_ERRATUM_2253138 !! 1923 config CPU_BMIPS32_3300
913 bool "Neoverse-N2: 2253138: workaround !! 1924 select SMP_UP if SMP
914 depends on CORESIGHT_TRBE !! 1925 bool
915 default y <<
916 select ARM64_WORKAROUND_TRBE_WRITE_OUT <<
917 help <<
918 This option adds the workaround for <<
919 1926
920 Affected Neoverse-N2 cores might wri !! 1927 config CPU_BMIPS4350
921 for TRBE. Under some conditions, the !! 1928 bool
922 virtually addressed page following t !! 1929 select SYS_SUPPORTS_SMP
923 (i.e., the TRBLIMITR_EL1.LIMIT), ins !! 1930 select SYS_SUPPORTS_HOTPLUG_CPU
924 1931
925 Work around this in the driver by al !! 1932 config CPU_BMIPS4380
926 page beyond the TRBLIMITR_EL1.LIMIT, !! 1933 bool
>> 1934 select MIPS_L1_CACHE_SHIFT_6
>> 1935 select SYS_SUPPORTS_SMP
>> 1936 select SYS_SUPPORTS_HOTPLUG_CPU
>> 1937 select CPU_HAS_RIXI
927 1938
928 If unsure, say Y. !! 1939 config CPU_BMIPS5000
>> 1940 bool
>> 1941 select MIPS_CPU_SCACHE
>> 1942 select MIPS_L1_CACHE_SHIFT_7
>> 1943 select SYS_SUPPORTS_SMP
>> 1944 select SYS_SUPPORTS_HOTPLUG_CPU
>> 1945 select CPU_HAS_RIXI
929 1946
930 config ARM64_ERRATUM_2224489 !! 1947 config SYS_HAS_CPU_LOONGSON64
931 bool "Cortex-A710/X2: 2224489: workaro !! 1948 bool
932 depends on CORESIGHT_TRBE !! 1949 select CPU_SUPPORTS_CPUFREQ
933 default y !! 1950 select CPU_HAS_RIXI
934 select ARM64_WORKAROUND_TRBE_WRITE_OUT <<
935 help <<
936 This option adds the workaround for <<
937 1951
938 Affected Cortex-A710/X2 cores might !! 1952 config SYS_HAS_CPU_LOONGSON2E
939 for TRBE. Under some conditions, the !! 1953 bool
940 virtually addressed page following t <<
941 (i.e., the TRBLIMITR_EL1.LIMIT), ins <<
942 1954
943 Work around this in the driver by al !! 1955 config SYS_HAS_CPU_LOONGSON2F
944 page beyond the TRBLIMITR_EL1.LIMIT, !! 1956 bool
>> 1957 select CPU_SUPPORTS_CPUFREQ
>> 1958 select CPU_SUPPORTS_ADDRWINCFG if 64BIT
945 1959
946 If unsure, say Y. !! 1960 config SYS_HAS_CPU_LOONGSON1B
>> 1961 bool
947 1962
948 config ARM64_ERRATUM_2441009 !! 1963 config SYS_HAS_CPU_LOONGSON1C
949 bool "Cortex-A510: Completion of affec !! 1964 bool
950 select ARM64_WORKAROUND_REPEAT_TLBI <<
951 help <<
952 This option adds a workaround for AR <<
953 <<
954 Under very rare circumstances, affec <<
955 may not handle a race between a brea <<
956 CPU, and another CPU accessing the s <<
957 store to a page that has been unmapp <<
958 1965
959 Work around this by adding the affec !! 1966 config SYS_HAS_CPU_MIPS32_R1
960 TLB sequences to be done twice. !! 1967 bool
961 1968
962 If unsure, say N. !! 1969 config SYS_HAS_CPU_MIPS32_R2
>> 1970 bool
963 1971
964 config ARM64_ERRATUM_2064142 !! 1972 config SYS_HAS_CPU_MIPS32_R3_5
965 bool "Cortex-A510: 2064142: workaround !! 1973 bool
966 depends on CORESIGHT_TRBE <<
967 default y <<
968 help <<
969 This option adds the workaround for <<
970 1974
971 Affected Cortex-A510 core might fail !! 1975 config SYS_HAS_CPU_MIPS32_R5
972 TRBE has been disabled. Under some c !! 1976 bool
973 writes into TRBE registers TRBLIMITR !! 1977 select ARCH_HAS_SYNC_DMA_FOR_CPU if DMA_NONCOHERENT
974 and TRBTRG_EL1 will be ignored and w <<
975 1978
976 Work around this in the driver by ex !! 1979 config SYS_HAS_CPU_MIPS32_R6
977 is stopped and before performing a s !! 1980 bool
978 registers. !! 1981 select ARCH_HAS_SYNC_DMA_FOR_CPU if DMA_NONCOHERENT
979 1982
980 If unsure, say Y. !! 1983 config SYS_HAS_CPU_MIPS64_R1
>> 1984 bool
981 1985
982 config ARM64_ERRATUM_2038923 !! 1986 config SYS_HAS_CPU_MIPS64_R2
983 bool "Cortex-A510: 2038923: workaround !! 1987 bool
984 depends on CORESIGHT_TRBE <<
985 default y <<
986 help <<
987 This option adds the workaround for <<
988 <<
989 Affected Cortex-A510 core might caus <<
990 prohibited within the CPU. As a resu <<
991 might be corrupted. This happens aft <<
992 TRBLIMITR_EL1.E, followed by just a <<
993 execution changes from a context, in <<
994 isn't, or vice versa. In these menti <<
995 is prohibited is inconsistent betwee <<
996 the trace buffer state might be corr <<
997 <<
998 Work around this in the driver by pr <<
999 trace is prohibited or not based on <<
1000 change to TRBLIMITR_EL1.E with at l <<
1001 two ISB instructions if no ERET is <<
1002 1988
1003 If unsure, say Y. !! 1989 config SYS_HAS_CPU_MIPS64_R5
>> 1990 bool
>> 1991 select ARCH_HAS_SYNC_DMA_FOR_CPU if DMA_NONCOHERENT
1004 1992
1005 config ARM64_ERRATUM_1902691 !! 1993 config SYS_HAS_CPU_MIPS64_R6
1006 bool "Cortex-A510: 1902691: workaroun !! 1994 bool
1007 depends on CORESIGHT_TRBE !! 1995 select ARCH_HAS_SYNC_DMA_FOR_CPU if DMA_NONCOHERENT
1008 default y <<
1009 help <<
1010 This option adds the workaround for <<
1011 1996
1012 Affected Cortex-A510 core might cau !! 1997 config SYS_HAS_CPU_P5600
1013 into the memory. Effectively TRBE i !! 1998 bool
1014 trace data. !! 1999 select ARCH_HAS_SYNC_DMA_FOR_CPU if DMA_NONCOHERENT
1015 2000
1016 Work around this problem in the dri !! 2001 config SYS_HAS_CPU_R3000
1017 affected cpus. The firmware must ha !! 2002 bool
1018 on such implementations. This will <<
1019 do this already. <<
1020 2003
1021 If unsure, say Y. !! 2004 config SYS_HAS_CPU_TX39XX
>> 2005 bool
1022 2006
1023 config ARM64_ERRATUM_2457168 !! 2007 config SYS_HAS_CPU_VR41XX
1024 bool "Cortex-A510: 2457168: workaroun !! 2008 bool
1025 depends on ARM64_AMU_EXTN <<
1026 default y <<
1027 help <<
1028 This option adds the workaround for <<
1029 2009
1030 The AMU counter AMEVCNTR01 (constan !! 2010 config SYS_HAS_CPU_R4X00
1031 as the system counter. On affected !! 2011 bool
1032 incorrectly giving a significantly <<
1033 2012
1034 Work around this problem by returni !! 2013 config SYS_HAS_CPU_TX49XX
1035 key locations that results in disab !! 2014 bool
1036 is the same to firmware disabling a <<
1037 2015
1038 If unsure, say Y. !! 2016 config SYS_HAS_CPU_R5000
>> 2017 bool
1039 2018
1040 config ARM64_ERRATUM_2645198 !! 2019 config SYS_HAS_CPU_R5500
1041 bool "Cortex-A715: 2645198: Workaroun !! 2020 bool
1042 default y <<
1043 help <<
1044 This option adds the workaround for <<
1045 2021
1046 If a Cortex-A715 cpu sees a page ma !! 2022 config SYS_HAS_CPU_NEVADA
1047 to non-executable, it may corrupt t !! 2023 bool
1048 next instruction abort caused by pe <<
1049 2024
1050 Only user-space does executable to !! 2025 config SYS_HAS_CPU_R10000
1051 mprotect() system call. Workaround !! 2026 bool
1052 TLB invalidation, for all changes t !! 2027 select ARCH_HAS_SYNC_DMA_FOR_CPU if DMA_NONCOHERENT
1053 2028
1054 If unsure, say Y. !! 2029 config SYS_HAS_CPU_RM7000
>> 2030 bool
1055 2031
1056 config ARM64_WORKAROUND_SPECULATIVE_UNPRIV_LO !! 2032 config SYS_HAS_CPU_SB1
1057 bool 2033 bool
1058 2034
1059 config ARM64_ERRATUM_2966298 !! 2035 config SYS_HAS_CPU_CAVIUM_OCTEON
1060 bool "Cortex-A520: 2966298: workaroun !! 2036 bool
1061 select ARM64_WORKAROUND_SPECULATIVE_U <<
1062 default y <<
1063 help <<
1064 This option adds the workaround for <<
1065 2037
1066 On an affected Cortex-A520 core, a !! 2038 config SYS_HAS_CPU_BMIPS
1067 load might leak data from a privile !! 2039 bool
1068 2040
1069 Work around this problem by executi !! 2041 config SYS_HAS_CPU_BMIPS32_3300
>> 2042 bool
>> 2043 select SYS_HAS_CPU_BMIPS
1070 2044
1071 If unsure, say Y. !! 2045 config SYS_HAS_CPU_BMIPS4350
>> 2046 bool
>> 2047 select SYS_HAS_CPU_BMIPS
1072 2048
1073 config ARM64_ERRATUM_3117295 !! 2049 config SYS_HAS_CPU_BMIPS4380
1074 bool "Cortex-A510: 3117295: workaroun !! 2050 bool
1075 select ARM64_WORKAROUND_SPECULATIVE_U !! 2051 select SYS_HAS_CPU_BMIPS
1076 default y <<
1077 help <<
1078 This option adds the workaround for <<
1079 2052
1080 On an affected Cortex-A510 core, a !! 2053 config SYS_HAS_CPU_BMIPS5000
1081 load might leak data from a privile !! 2054 bool
>> 2055 select SYS_HAS_CPU_BMIPS
>> 2056 select ARCH_HAS_SYNC_DMA_FOR_CPU
1082 2057
1083 Work around this problem by executi !! 2058 config SYS_HAS_CPU_XLR
>> 2059 bool
1084 2060
1085 If unsure, say Y. !! 2061 config SYS_HAS_CPU_XLP
>> 2062 bool
1086 2063
1087 config ARM64_ERRATUM_3194386 !! 2064 #
1088 bool "Cortex-*/Neoverse-*: workaround !! 2065 # CPU may reorder R->R, R->W, W->R, W->W
1089 default y !! 2066 # Reordering beyond LL and SC is handled in WEAK_REORDERING_BEYOND_LLSC
1090 help !! 2067 #
1091 This option adds the workaround for !! 2068 config WEAK_ORDERING
>> 2069 bool
1092 2070
1093 * ARM Cortex-A76 erratum 3324349 !! 2071 #
1094 * ARM Cortex-A77 erratum 3324348 !! 2072 # CPU may reorder reads and writes beyond LL/SC
1095 * ARM Cortex-A78 erratum 3324344 !! 2073 # CPU may reorder R->LL, R->LL, W->LL, W->LL, R->SC, R->SC, W->SC, W->SC
1096 * ARM Cortex-A78C erratum 3324346 !! 2074 #
1097 * ARM Cortex-A78C erratum 3324347 !! 2075 config WEAK_REORDERING_BEYOND_LLSC
1098 * ARM Cortex-A710 erratam 3324338 !! 2076 bool
1099 * ARM Cortex-A715 errartum 3456084 !! 2077 endmenu
1100 * ARM Cortex-A720 erratum 3456091 <<
1101 * ARM Cortex-A725 erratum 3456106 <<
1102 * ARM Cortex-X1 erratum 3324344 <<
1103 * ARM Cortex-X1C erratum 3324346 <<
1104 * ARM Cortex-X2 erratum 3324338 <<
1105 * ARM Cortex-X3 erratum 3324335 <<
1106 * ARM Cortex-X4 erratum 3194386 <<
1107 * ARM Cortex-X925 erratum 3324334 <<
1108 * ARM Neoverse-N1 erratum 3324349 <<
1109 * ARM Neoverse N2 erratum 3324339 <<
1110 * ARM Neoverse-N3 erratum 3456111 <<
1111 * ARM Neoverse-V1 erratum 3324341 <<
1112 * ARM Neoverse V2 erratum 3324336 <<
1113 * ARM Neoverse-V3 erratum 3312417 <<
1114 <<
1115 On affected cores "MSR SSBS, #0" in <<
1116 subsequent speculative instructions <<
1117 speculative store bypassing. <<
1118 <<
1119 Work around this problem by placing <<
1120 Instruction Synchronization Barrier <<
1121 SSBS. The presence of the SSBS spec <<
1122 from hwcaps and EL0 reads of ID_AA6 <<
1123 will use the PR_SPEC_STORE_BYPASS p <<
1124 2078
1125 If unsure, say Y. !! 2079 #
>> 2080 # These two indicate any level of the MIPS32 and MIPS64 architecture
>> 2081 #
>> 2082 config CPU_MIPS32
>> 2083 bool
>> 2084 default y if CPU_MIPS32_R1 || CPU_MIPS32_R2 || CPU_MIPS32_R5 || \
>> 2085 CPU_MIPS32_R6 || CPU_P5600
1126 2086
1127 config CAVIUM_ERRATUM_22375 !! 2087 config CPU_MIPS64
1128 bool "Cavium erratum 22375, 24313" !! 2088 bool
1129 default y !! 2089 default y if CPU_MIPS64_R1 || CPU_MIPS64_R2 || CPU_MIPS64_R5 || \
1130 help !! 2090 CPU_MIPS64_R6
1131 Enable workaround for errata 22375 <<
1132 2091
1133 This implements two gicv3-its errat !! 2092 #
1134 with a small impact affecting only !! 2093 # These indicate the revision of the architecture
>> 2094 #
>> 2095 config CPU_MIPSR1
>> 2096 bool
>> 2097 default y if CPU_MIPS32_R1 || CPU_MIPS64_R1
1135 2098
1136 erratum 22375: only alloc 8MB tab !! 2099 config CPU_MIPSR2
1137 erratum 24313: ignore memory acce !! 2100 bool
>> 2101 default y if CPU_MIPS32_R2 || CPU_MIPS64_R2 || CPU_CAVIUM_OCTEON
>> 2102 select CPU_HAS_RIXI
>> 2103 select CPU_HAS_DIEI if !CPU_DIEI_BROKEN
>> 2104 select MIPS_SPRAM
1138 2105
1139 The fixes are in ITS initialization !! 2106 config CPU_MIPSR5
1140 type and table size provided by the !! 2107 bool
>> 2108 default y if CPU_MIPS32_R5 || CPU_MIPS64_R5 || CPU_P5600
>> 2109 select CPU_HAS_RIXI
>> 2110 select CPU_HAS_DIEI if !CPU_DIEI_BROKEN
>> 2111 select MIPS_SPRAM
1141 2112
1142 If unsure, say Y. !! 2113 config CPU_MIPSR6
>> 2114 bool
>> 2115 default y if CPU_MIPS32_R6 || CPU_MIPS64_R6
>> 2116 select CPU_HAS_RIXI
>> 2117 select CPU_HAS_DIEI if !CPU_DIEI_BROKEN
>> 2118 select HAVE_ARCH_BITREVERSE
>> 2119 select MIPS_ASID_BITS_VARIABLE
>> 2120 select MIPS_CRC_SUPPORT
>> 2121 select MIPS_SPRAM
1143 2122
1144 config CAVIUM_ERRATUM_23144 !! 2123 config TARGET_ISA_REV
1145 bool "Cavium erratum 23144: ITS SYNC !! 2124 int
1146 depends on NUMA !! 2125 default 1 if CPU_MIPSR1
1147 default y !! 2126 default 2 if CPU_MIPSR2
>> 2127 default 5 if CPU_MIPSR5
>> 2128 default 6 if CPU_MIPSR6
>> 2129 default 0
1148 help 2130 help
1149 ITS SYNC command hang for cross nod !! 2131 Reflects the ISA revision being targeted by the kernel build. This
>> 2132 is effectively the Kconfig equivalent of MIPS_ISA_REV.
1150 2133
1151 If unsure, say Y. !! 2134 config EVA
1152 !! 2135 bool
1153 config CAVIUM_ERRATUM_23154 <<
1154 bool "Cavium errata 23154 and 38545: <<
1155 default y <<
1156 help <<
1157 The ThunderX GICv3 implementation r <<
1158 reading the IAR status to ensure da <<
1159 (access to icc_iar1_el1 is not sync <<
1160 2136
1161 It also suffers from erratum 38545 !! 2137 config XPA
1162 OcteonTX and OcteonTX2), resulting !! 2138 bool
1163 spuriously presented to the CPU int <<
1164 2139
1165 If unsure, say Y. !! 2140 config SYS_SUPPORTS_32BIT_KERNEL
>> 2141 bool
>> 2142 config SYS_SUPPORTS_64BIT_KERNEL
>> 2143 bool
>> 2144 config CPU_SUPPORTS_32BIT_KERNEL
>> 2145 bool
>> 2146 config CPU_SUPPORTS_64BIT_KERNEL
>> 2147 bool
>> 2148 config CPU_SUPPORTS_CPUFREQ
>> 2149 bool
>> 2150 config CPU_SUPPORTS_ADDRWINCFG
>> 2151 bool
>> 2152 config CPU_SUPPORTS_HUGEPAGES
>> 2153 bool
>> 2154 depends on !(32BIT && (PHYS_ADDR_T_64BIT || EVA))
>> 2155 config MIPS_PGD_C0_CONTEXT
>> 2156 bool
>> 2157 default y if 64BIT && (CPU_MIPSR2 || CPU_MIPSR6) && !CPU_XLP
1166 2158
1167 config CAVIUM_ERRATUM_27456 !! 2159 #
1168 bool "Cavium erratum 27456: Broadcast !! 2160 # Set to y for ptrace access to watch registers.
1169 default y !! 2161 #
1170 help !! 2162 config HARDWARE_WATCHPOINTS
1171 On ThunderX T88 pass 1.x through 2. !! 2163 bool
1172 instructions may cause the icache t !! 2164 default y if CPU_MIPSR1 || CPU_MIPSR2 || CPU_MIPSR6
1173 contains data for a non-current ASI <<
1174 invalidate the icache when changing <<
1175 2165
1176 If unsure, say Y. !! 2166 menu "Kernel type"
1177 2167
1178 config CAVIUM_ERRATUM_30115 !! 2168 choice
1179 bool "Cavium erratum 30115: Guest may !! 2169 prompt "Kernel code model"
1180 default y <<
1181 help 2170 help
1182 On ThunderX T88 pass 1.x through 2. !! 2171 You should only select this option if you have a workload that
1183 1.2, and T83 Pass 1.0, KVM guest ex !! 2172 actually benefits from 64-bit processing or if your machine has
1184 interrupts in host. Trapping both G !! 2173 large memory. You will only be presented a single option in this
1185 accesses sidesteps the issue. !! 2174 menu if your system does not support both 32-bit and 64-bit kernels.
1186 !! 2175
1187 If unsure, say Y. !! 2176 config 32BIT
1188 !! 2177 bool "32-bit kernel"
1189 config CAVIUM_TX2_ERRATUM_219 !! 2178 depends on CPU_SUPPORTS_32BIT_KERNEL && SYS_SUPPORTS_32BIT_KERNEL
1190 bool "Cavium ThunderX2 erratum 219: P !! 2179 select TRAD_SIGNALS
1191 default y <<
1192 help 2180 help
1193 On Cavium ThunderX2, a load, store !! 2181 Select this option if you want to build a 32-bit kernel.
1194 TTBR update and the corresponding c <<
1195 cause a spurious Data Abort to be d <<
1196 the CPU core. <<
1197 <<
1198 Work around the issue by avoiding t <<
1199 trapping KVM guest TTBRx_EL1 writes <<
1200 trap handler performs the correspon <<
1201 instruction and ensures context syn <<
1202 exception return. <<
1203 <<
1204 If unsure, say Y. <<
1205 2182
1206 config FUJITSU_ERRATUM_010001 !! 2183 config 64BIT
1207 bool "Fujitsu-A64FX erratum E#010001: !! 2184 bool "64-bit kernel"
1208 default y !! 2185 depends on CPU_SUPPORTS_64BIT_KERNEL && SYS_SUPPORTS_64BIT_KERNEL
1209 help 2186 help
1210 This option adds a workaround for F !! 2187 Select this option if you want to build a 64-bit kernel.
1211 On some variants of the Fujitsu-A64 <<
1212 accesses may cause undefined fault <<
1213 This fault occurs under a specific <<
1214 load/store instruction performs an <<
1215 case-1 TTBR0_EL1 with TCR_EL1.NFD0 <<
1216 case-2 TTBR0_EL2 with TCR_EL2.NFD0 <<
1217 case-3 TTBR1_EL1 with TCR_EL1.NFD1 <<
1218 case-4 TTBR1_EL2 with TCR_EL2.NFD1 <<
1219 <<
1220 The workaround is to ensure these b <<
1221 The workaround only affects the Fuj <<
1222 2188
1223 If unsure, say Y. !! 2189 endchoice
1224 2190
1225 config HISILICON_ERRATUM_161600802 !! 2191 config KVM_GUEST
1226 bool "Hip07 161600802: Erroneous redi !! 2192 bool "KVM Guest Kernel"
1227 default y !! 2193 depends on CPU_MIPS32_R2
1228 help !! 2194 depends on BROKEN_ON_SMP
1229 The HiSilicon Hip07 SoC uses the wr !! 2195 help
1230 when issued ITS commands such as VM !! 2196 Select this option if building a guest kernel for KVM (Trap & Emulate)
1231 a 128kB offset to be applied to the !! 2197 mode.
>> 2198
>> 2199 config KVM_GUEST_TIMER_FREQ
>> 2200 int "Count/Compare Timer Frequency (MHz)"
>> 2201 depends on KVM_GUEST
>> 2202 default 100
>> 2203 help
>> 2204 Set this to non-zero if building a guest kernel for KVM to skip RTC
>> 2205 emulation when determining guest CPU Frequency. Instead, the guest's
>> 2206 timer frequency is specified directly.
>> 2207
>> 2208 config MIPS_VA_BITS_48
>> 2209 bool "48 bits virtual memory"
>> 2210 depends on 64BIT
>> 2211 help
>> 2212 Support a maximum at least 48 bits of application virtual
>> 2213 memory. Default is 40 bits or less, depending on the CPU.
>> 2214 For page sizes 16k and above, this option results in a small
>> 2215 memory overhead for page tables. For 4k page size, a fourth
>> 2216 level of page tables is added which imposes both a memory
>> 2217 overhead as well as slower TLB fault handling.
1232 2218
1233 If unsure, say Y. !! 2219 If unsure, say N.
1234 2220
1235 config QCOM_FALKOR_ERRATUM_1003 !! 2221 choice
1236 bool "Falkor E1003: Incorrect transla !! 2222 prompt "Kernel page size"
1237 default y !! 2223 default PAGE_SIZE_4KB
1238 help <<
1239 On Falkor v1, an incorrect ASID may <<
1240 and BADDR are changed together in T <<
1241 in TTBR1_EL1, this situation only o <<
1242 then only for entries in the walk c <<
1243 is unchanged. Work around the errat <<
1244 entries for the trampoline before e <<
1245 2224
1246 config QCOM_FALKOR_ERRATUM_1009 !! 2225 config PAGE_SIZE_4KB
1247 bool "Falkor E1009: Prematurely compl !! 2226 bool "4kB"
1248 default y !! 2227 depends on !CPU_LOONGSON2EF && !CPU_LOONGSON64
1249 select ARM64_WORKAROUND_REPEAT_TLBI !! 2228 help
1250 help !! 2229 This option select the standard 4kB Linux page size. On some
1251 On Falkor v1, the CPU may premature !! 2230 R3000-family processors this is the only available page size. Using
1252 TLBI xxIS invalidate maintenance op !! 2231 4kB page size will minimize memory consumption and is therefore
1253 one more time to fix the issue. !! 2232 recommended for low memory systems.
>> 2233
>> 2234 config PAGE_SIZE_8KB
>> 2235 bool "8kB"
>> 2236 depends on CPU_CAVIUM_OCTEON
>> 2237 depends on !MIPS_VA_BITS_48
>> 2238 help
>> 2239 Using 8kB page size will result in higher performance kernel at
>> 2240 the price of higher memory consumption. This option is available
>> 2241 only on cnMIPS processors. Note that you will need a suitable Linux
>> 2242 distribution to support this.
>> 2243
>> 2244 config PAGE_SIZE_16KB
>> 2245 bool "16kB"
>> 2246 depends on !CPU_R3000 && !CPU_TX39XX
>> 2247 help
>> 2248 Using 16kB page size will result in higher performance kernel at
>> 2249 the price of higher memory consumption. This option is available on
>> 2250 all non-R3000 family processors. Note that you will need a suitable
>> 2251 Linux distribution to support this.
>> 2252
>> 2253 config PAGE_SIZE_32KB
>> 2254 bool "32kB"
>> 2255 depends on CPU_CAVIUM_OCTEON
>> 2256 depends on !MIPS_VA_BITS_48
>> 2257 help
>> 2258 Using 32kB page size will result in higher performance kernel at
>> 2259 the price of higher memory consumption. This option is available
>> 2260 only on cnMIPS cores. Note that you will need a suitable Linux
>> 2261 distribution to support this.
>> 2262
>> 2263 config PAGE_SIZE_64KB
>> 2264 bool "64kB"
>> 2265 depends on !CPU_R3000 && !CPU_TX39XX
>> 2266 help
>> 2267 Using 64kB page size will result in higher performance kernel at
>> 2268 the price of higher memory consumption. This option is available on
>> 2269 all non-R3000 family processor. Not that at the time of this
>> 2270 writing this option is still high experimental.
1254 2271
1255 If unsure, say Y. !! 2272 endchoice
1256 2273
1257 config QCOM_QDF2400_ERRATUM_0065 !! 2274 config FORCE_MAX_ZONEORDER
1258 bool "QDF2400 E0065: Incorrect GITS_T !! 2275 int "Maximum zone order"
1259 default y !! 2276 range 14 64 if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_64KB
1260 help !! 2277 default "14" if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_64KB
1261 On Qualcomm Datacenter Technologies !! 2278 range 13 64 if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_32KB
1262 ITE size incorrectly. The GITS_TYPE !! 2279 default "13" if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_32KB
1263 been indicated as 16Bytes (0xf), no !! 2280 range 12 64 if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_16KB
>> 2281 default "12" if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_16KB
>> 2282 range 0 64
>> 2283 default "11"
>> 2284 help
>> 2285 The kernel memory allocator divides physically contiguous memory
>> 2286 blocks into "zones", where each zone is a power of two number of
>> 2287 pages. This option selects the largest power of two that the kernel
>> 2288 keeps in the memory allocator. If you need to allocate very large
>> 2289 blocks of physically contiguous memory, then you may need to
>> 2290 increase this value.
1264 2291
1265 If unsure, say Y. !! 2292 This config option is actually maximum order plus one. For example,
>> 2293 a value of 11 means that the largest free memory block is 2^10 pages.
1266 2294
1267 config QCOM_FALKOR_ERRATUM_E1041 !! 2295 The page size is not necessarily 4KB. Keep this in mind
1268 bool "Falkor E1041: Speculative instr !! 2296 when choosing a value for this option.
1269 default y <<
1270 help <<
1271 Falkor CPU may speculatively fetch <<
1272 memory location when MMU translatio <<
1273 to SCTLR_ELn[M]=0. Prefix an ISB in <<
1274 2297
1275 If unsure, say Y. !! 2298 config BOARD_SCACHE
>> 2299 bool
1276 2300
1277 config NVIDIA_CARMEL_CNP_ERRATUM !! 2301 config IP22_CPU_SCACHE
1278 bool "NVIDIA Carmel CNP: CNP on Carme !! 2302 bool
1279 default y !! 2303 select BOARD_SCACHE
1280 help <<
1281 If CNP is enabled on Carmel cores, <<
1282 invalidate shared TLB entries insta <<
1283 on standard ARM cores. <<
1284 2304
1285 If unsure, say Y. !! 2305 #
>> 2306 # Support for a MIPS32 / MIPS64 style S-caches
>> 2307 #
>> 2308 config MIPS_CPU_SCACHE
>> 2309 bool
>> 2310 select BOARD_SCACHE
1286 2311
1287 config ROCKCHIP_ERRATUM_3588001 !! 2312 config R5000_CPU_SCACHE
1288 bool "Rockchip 3588001: GIC600 can no !! 2313 bool
1289 default y !! 2314 select BOARD_SCACHE
1290 help <<
1291 The Rockchip RK3588 GIC600 SoC inte <<
1292 This means, that its sharability fe <<
1293 is supported by the IP itself. <<
1294 2315
1295 If unsure, say Y. !! 2316 config RM7000_CPU_SCACHE
>> 2317 bool
>> 2318 select BOARD_SCACHE
1296 2319
1297 config SOCIONEXT_SYNQUACER_PREITS !! 2320 config SIBYTE_DMA_PAGEOPS
1298 bool "Socionext Synquacer: Workaround !! 2321 bool "Use DMA to clear/copy pages"
1299 default y !! 2322 depends on CPU_SB1
1300 help 2323 help
1301 Socionext Synquacer SoCs implement !! 2324 Instead of using the CPU to zero and copy pages, use a Data Mover
1302 MSI doorbell writes with non-zero v !! 2325 channel. These DMA channels are otherwise unused by the standard
1303 !! 2326 SiByte Linux port. Seems to give a small performance benefit.
1304 If unsure, say Y. <<
1305 2327
1306 endmenu # "ARM errata workarounds via the alt !! 2328 config CPU_HAS_PREFETCH
>> 2329 bool
1307 2330
1308 choice !! 2331 config CPU_GENERIC_DUMP_TLB
1309 prompt "Page size" !! 2332 bool
1310 default ARM64_4K_PAGES !! 2333 default y if !(CPU_R3000 || CPU_TX39XX)
1311 help <<
1312 Page size (translation granule) con <<
1313 2334
1314 config ARM64_4K_PAGES !! 2335 config MIPS_FP_SUPPORT
1315 bool "4KB" !! 2336 bool "Floating Point support" if EXPERT
1316 select HAVE_PAGE_SIZE_4KB !! 2337 default y
1317 help 2338 help
1318 This feature enables 4KB pages supp !! 2339 Select y to include support for floating point in the kernel
>> 2340 including initialization of FPU hardware, FP context save & restore
>> 2341 and emulation of an FPU where necessary. Without this support any
>> 2342 userland program attempting to use floating point instructions will
>> 2343 receive a SIGILL.
1319 2344
1320 config ARM64_16K_PAGES !! 2345 If you know that your userland will not attempt to use floating point
1321 bool "16KB" !! 2346 instructions then you can say n here to shrink the kernel a little.
1322 select HAVE_PAGE_SIZE_16KB <<
1323 help <<
1324 The system will use 16KB pages supp <<
1325 requires applications compiled with <<
1326 aligned segments. <<
1327 2347
1328 config ARM64_64K_PAGES !! 2348 If unsure, say y.
1329 bool "64KB" <<
1330 select HAVE_PAGE_SIZE_64KB <<
1331 help <<
1332 This feature enables 64KB pages sup <<
1333 allowing only two levels of page ta <<
1334 look-up. AArch32 emulation requires <<
1335 with 64K aligned segments. <<
1336 2349
1337 endchoice !! 2350 config CPU_R2300_FPU
>> 2351 bool
>> 2352 depends on MIPS_FP_SUPPORT
>> 2353 default y if CPU_R3000 || CPU_TX39XX
1338 2354
1339 choice !! 2355 config CPU_R3K_TLB
1340 prompt "Virtual address space size" !! 2356 bool
1341 default ARM64_VA_BITS_52 <<
1342 help <<
1343 Allows choosing one of multiple pos <<
1344 space sizes. The level of translati <<
1345 a combination of page size and virt <<
1346 <<
1347 config ARM64_VA_BITS_36 <<
1348 bool "36-bit" if EXPERT <<
1349 depends on PAGE_SIZE_16KB <<
1350 <<
1351 config ARM64_VA_BITS_39 <<
1352 bool "39-bit" <<
1353 depends on PAGE_SIZE_4KB <<
1354 <<
1355 config ARM64_VA_BITS_42 <<
1356 bool "42-bit" <<
1357 depends on PAGE_SIZE_64KB <<
1358 <<
1359 config ARM64_VA_BITS_47 <<
1360 bool "47-bit" <<
1361 depends on PAGE_SIZE_16KB <<
1362 <<
1363 config ARM64_VA_BITS_48 <<
1364 bool "48-bit" <<
1365 <<
1366 config ARM64_VA_BITS_52 <<
1367 bool "52-bit" <<
1368 depends on ARM64_PAN || !ARM64_SW_TTB <<
1369 help <<
1370 Enable 52-bit virtual addressing fo <<
1371 requested via a hint to mmap(). The <<
1372 virtual addresses for its own mappi <<
1373 this feature is available, otherwis <<
1374 <<
1375 NOTE: Enabling 52-bit virtual addre <<
1376 ARMv8.3 Pointer Authentication will <<
1377 reduced from 7 bits to 3 bits, whic <<
1378 impact on its susceptibility to bru <<
1379 2357
1380 If unsure, select 48-bit virtual ad !! 2358 config CPU_R4K_FPU
>> 2359 bool
>> 2360 depends on MIPS_FP_SUPPORT
>> 2361 default y if !CPU_R2300_FPU
1381 2362
1382 endchoice !! 2363 config CPU_R4K_CACHE_TLB
>> 2364 bool
>> 2365 default y if !(CPU_R3K_TLB || CPU_SB1 || CPU_CAVIUM_OCTEON)
1383 2366
1384 config ARM64_FORCE_52BIT !! 2367 config MIPS_MT_SMP
1385 bool "Force 52-bit virtual addresses !! 2368 bool "MIPS MT SMP support (1 TC on each available VPE)"
1386 depends on ARM64_VA_BITS_52 && EXPERT !! 2369 default y
1387 help !! 2370 depends on SYS_SUPPORTS_MULTITHREADING && !CPU_MIPSR6 && !CPU_MICROMIPS
1388 For systems with 52-bit userspace V !! 2371 select CPU_MIPSR2_IRQ_VI
1389 to maintain compatibility with olde !! 2372 select CPU_MIPSR2_IRQ_EI
1390 unless a hint is supplied to mmap. !! 2373 select SYNC_R4K
1391 !! 2374 select MIPS_MT
1392 This configuration option disables !! 2375 select SMP
1393 forces all userspace addresses to b !! 2376 select SMP_UP
1394 should only enable this configurati !! 2377 select SYS_SUPPORTS_SMP
1395 memory management code. If unsure s !! 2378 select SYS_SUPPORTS_SCHED_SMT
>> 2379 select MIPS_PERF_SHARED_TC_COUNTERS
>> 2380 help
>> 2381 This is a kernel model which is known as SMVP. This is supported
>> 2382 on cores with the MT ASE and uses the available VPEs to implement
>> 2383 virtual processors which supports SMP. This is equivalent to the
>> 2384 Intel Hyperthreading feature. For further information go to
>> 2385 <http://www.imgtec.com/mips/mips-multithreading.asp>.
1396 2386
1397 config ARM64_VA_BITS !! 2387 config MIPS_MT
1398 int !! 2388 bool
1399 default 36 if ARM64_VA_BITS_36 <<
1400 default 39 if ARM64_VA_BITS_39 <<
1401 default 42 if ARM64_VA_BITS_42 <<
1402 default 47 if ARM64_VA_BITS_47 <<
1403 default 48 if ARM64_VA_BITS_48 <<
1404 default 52 if ARM64_VA_BITS_52 <<
1405 2389
1406 choice !! 2390 config SCHED_SMT
1407 prompt "Physical address space size" !! 2391 bool "SMT (multithreading) scheduler support"
1408 default ARM64_PA_BITS_48 !! 2392 depends on SYS_SUPPORTS_SCHED_SMT
>> 2393 default n
1409 help 2394 help
1410 Choose the maximum physical address !! 2395 SMT scheduler support improves the CPU scheduler's decision making
1411 support. !! 2396 when dealing with MIPS MT enabled cores at a cost of slightly
1412 !! 2397 increased overhead in some places. If unsure say N here.
1413 config ARM64_PA_BITS_48 <<
1414 bool "48-bit" <<
1415 depends on ARM64_64K_PAGES || !ARM64_ <<
1416 <<
1417 config ARM64_PA_BITS_52 <<
1418 bool "52-bit" <<
1419 depends on ARM64_64K_PAGES || ARM64_V <<
1420 depends on ARM64_PAN || !ARM64_SW_TTB <<
1421 help <<
1422 Enable support for a 52-bit physica <<
1423 part of the ARMv8.2-LPA extension. <<
1424 <<
1425 With this enabled, the kernel will <<
1426 do not support ARMv8.2-LPA, but wit <<
1427 minor performance overhead). <<
1428 2398
1429 endchoice !! 2399 config SYS_SUPPORTS_SCHED_SMT
>> 2400 bool
1430 2401
1431 config ARM64_PA_BITS !! 2402 config SYS_SUPPORTS_MULTITHREADING
1432 int !! 2403 bool
1433 default 48 if ARM64_PA_BITS_48 <<
1434 default 52 if ARM64_PA_BITS_52 <<
1435 2404
1436 config ARM64_LPA2 !! 2405 config MIPS_MT_FPAFF
1437 def_bool y !! 2406 bool "Dynamic FPU affinity for FP-intensive threads"
1438 depends on ARM64_PA_BITS_52 && !ARM64 !! 2407 default y
>> 2408 depends on MIPS_MT_SMP
1439 2409
1440 choice !! 2410 config MIPSR2_TO_R6_EMULATOR
1441 prompt "Endianness" !! 2411 bool "MIPS R2-to-R6 emulator"
1442 default CPU_LITTLE_ENDIAN !! 2412 depends on CPU_MIPSR6
>> 2413 depends on MIPS_FP_SUPPORT
>> 2414 default y
1443 help 2415 help
1444 Select the endianness of data acces !! 2416 Choose this option if you want to run non-R6 MIPS userland code.
1445 applications will need to be compil !! 2417 Even if you say 'Y' here, the emulator will still be disabled by
1446 that is selected here. !! 2418 default. You can enable it using the 'mipsr2emu' kernel option.
>> 2419 The only reason this is a build-time option is to save ~14K from the
>> 2420 final kernel image.
1447 2421
1448 config CPU_BIG_ENDIAN !! 2422 config SYS_SUPPORTS_VPE_LOADER
1449 bool "Build big-endian kernel" !! 2423 bool
1450 # https://github.com/llvm/llvm-projec !! 2424 depends on SYS_SUPPORTS_MULTITHREADING
1451 depends on AS_IS_GNU || AS_VERSION >= <<
1452 help 2425 help
1453 Say Y if you plan on running a kern !! 2426 Indicates that the platform supports the VPE loader, and provides
>> 2427 physical_memsize.
1454 2428
1455 config CPU_LITTLE_ENDIAN !! 2429 config MIPS_VPE_LOADER
1456 bool "Build little-endian kernel" !! 2430 bool "VPE loader support."
>> 2431 depends on SYS_SUPPORTS_VPE_LOADER && MODULES
>> 2432 select CPU_MIPSR2_IRQ_VI
>> 2433 select CPU_MIPSR2_IRQ_EI
>> 2434 select MIPS_MT
1457 help 2435 help
1458 Say Y if you plan on running a kern !! 2436 Includes a loader for loading an elf relocatable object
1459 This is usually the case for distri !! 2437 onto another VPE and running it.
1460 2438
1461 endchoice !! 2439 config MIPS_VPE_LOADER_CMP
>> 2440 bool
>> 2441 default "y"
>> 2442 depends on MIPS_VPE_LOADER && MIPS_CMP
1462 2443
1463 config SCHED_MC !! 2444 config MIPS_VPE_LOADER_MT
1464 bool "Multi-core scheduler support" !! 2445 bool
1465 help !! 2446 default "y"
1466 Multi-core scheduler support improv !! 2447 depends on MIPS_VPE_LOADER && !MIPS_CMP
1467 making when dealing with multi-core <<
1468 increased overhead in some places. <<
1469 2448
1470 config SCHED_CLUSTER !! 2449 config MIPS_VPE_LOADER_TOM
1471 bool "Cluster scheduler support" !! 2450 bool "Load VPE program into memory hidden from linux"
>> 2451 depends on MIPS_VPE_LOADER
>> 2452 default y
1472 help 2453 help
1473 Cluster scheduler support improves !! 2454 The loader can use memory that is present but has been hidden from
1474 making when dealing with machines t !! 2455 Linux using the kernel command line option "mem=xxMB". It's up to
1475 Cluster usually means a couple of C !! 2456 you to ensure the amount you put in the option and the space your
1476 by sharing mid-level caches, last-l !! 2457 program requires is less or equal to the amount physically present.
1477 busses. <<
1478 2458
1479 config SCHED_SMT !! 2459 config MIPS_VPE_APSP_API
1480 bool "SMT scheduler support" !! 2460 bool "Enable support for AP/SP API (RTLX)"
1481 help !! 2461 depends on MIPS_VPE_LOADER
1482 Improves the CPU scheduler's decisi <<
1483 MultiThreading at a cost of slightl <<
1484 places. If unsure say N here. <<
1485 2462
1486 config NR_CPUS !! 2463 config MIPS_VPE_APSP_API_CMP
1487 int "Maximum number of CPUs (2-4096)" !! 2464 bool
1488 range 2 4096 !! 2465 default "y"
1489 default "512" !! 2466 depends on MIPS_VPE_APSP_API && MIPS_CMP
1490 2467
1491 config HOTPLUG_CPU !! 2468 config MIPS_VPE_APSP_API_MT
1492 bool "Support for hot-pluggable CPUs" !! 2469 bool
1493 select GENERIC_IRQ_MIGRATION !! 2470 default "y"
>> 2471 depends on MIPS_VPE_APSP_API && !MIPS_CMP
>> 2472
>> 2473 config MIPS_CMP
>> 2474 bool "MIPS CMP framework support (DEPRECATED)"
>> 2475 depends on SYS_SUPPORTS_MIPS_CMP && !CPU_MIPSR6
>> 2476 select SMP
>> 2477 select SYNC_R4K
>> 2478 select SYS_SUPPORTS_SMP
>> 2479 select WEAK_ORDERING
>> 2480 default n
1494 help 2481 help
1495 Say Y here to experiment with turni !! 2482 Select this if you are using a bootloader which implements the "CMP
1496 can be controlled through /sys/devi !! 2483 framework" protocol (ie. YAMON) and want your kernel to make use of
>> 2484 its ability to start secondary CPUs.
>> 2485
>> 2486 Unless you have a specific need, you should use CONFIG_MIPS_CPS
>> 2487 instead of this.
>> 2488
>> 2489 config MIPS_CPS
>> 2490 bool "MIPS Coherent Processing System support"
>> 2491 depends on SYS_SUPPORTS_MIPS_CPS
>> 2492 select MIPS_CM
>> 2493 select MIPS_CPS_PM if HOTPLUG_CPU
>> 2494 select SMP
>> 2495 select SYNC_R4K if (CEVT_R4K || CSRC_R4K)
>> 2496 select SYS_SUPPORTS_HOTPLUG_CPU
>> 2497 select SYS_SUPPORTS_SCHED_SMT if CPU_MIPSR6
>> 2498 select SYS_SUPPORTS_SMP
>> 2499 select WEAK_ORDERING
>> 2500 help
>> 2501 Select this if you wish to run an SMP kernel across multiple cores
>> 2502 within a MIPS Coherent Processing System. When this option is
>> 2503 enabled the kernel will probe for other cores and boot them with
>> 2504 no external assistance. It is safe to enable this when hardware
>> 2505 support is unavailable.
1497 2506
1498 # Common NUMA Features !! 2507 config MIPS_CPS_PM
1499 config NUMA !! 2508 depends on MIPS_CPS
1500 bool "NUMA Memory Allocation and Sche !! 2509 bool
1501 select GENERIC_ARCH_NUMA <<
1502 select OF_NUMA <<
1503 select HAVE_SETUP_PER_CPU_AREA <<
1504 select NEED_PER_CPU_EMBED_FIRST_CHUNK <<
1505 select NEED_PER_CPU_PAGE_FIRST_CHUNK <<
1506 select USE_PERCPU_NUMA_NODE_ID <<
1507 help <<
1508 Enable NUMA (Non-Uniform Memory Acc <<
1509 <<
1510 The kernel will try to allocate mem <<
1511 local memory of the CPU and add som <<
1512 NUMA awareness to the kernel. <<
1513 2510
1514 config NODES_SHIFT !! 2511 config MIPS_CM
1515 int "Maximum NUMA Nodes (as a power o !! 2512 bool
1516 range 1 10 !! 2513 select MIPS_CPC
1517 default "4" <<
1518 depends on NUMA <<
1519 help <<
1520 Specify the maximum number of NUMA <<
1521 system. Increases memory reserved <<
1522 2514
1523 source "kernel/Kconfig.hz" !! 2515 config MIPS_CPC
>> 2516 bool
1524 2517
1525 config ARCH_SPARSEMEM_ENABLE !! 2518 config SB1_PASS_2_WORKAROUNDS
1526 def_bool y !! 2519 bool
1527 select SPARSEMEM_VMEMMAP_ENABLE !! 2520 depends on CPU_SB1 && (CPU_SB1_PASS_2_2 || CPU_SB1_PASS_2)
1528 select SPARSEMEM_VMEMMAP !! 2521 default y
1529 2522
1530 config HW_PERF_EVENTS !! 2523 config SB1_PASS_2_1_WORKAROUNDS
1531 def_bool y !! 2524 bool
1532 depends on ARM_PMU !! 2525 depends on CPU_SB1 && CPU_SB1_PASS_2
>> 2526 default y
1533 2527
1534 # Supported by clang >= 7.0 or GCC >= 12.0.0 !! 2528 choice
1535 config CC_HAVE_SHADOW_CALL_STACK !! 2529 prompt "SmartMIPS or microMIPS ASE support"
1536 def_bool $(cc-option, -fsanitize=shad <<
1537 2530
1538 config PARAVIRT !! 2531 config CPU_NEEDS_NO_SMARTMIPS_OR_MICROMIPS
1539 bool "Enable paravirtualization code" !! 2532 bool "None"
1540 help 2533 help
1541 This changes the kernel so it can m !! 2534 Select this if you want neither microMIPS nor SmartMIPS support
1542 under a hypervisor, potentially imp <<
1543 over full virtualization. <<
1544 2535
1545 config PARAVIRT_TIME_ACCOUNTING !! 2536 config CPU_HAS_SMARTMIPS
1546 bool "Paravirtual steal time accounti !! 2537 depends on SYS_SUPPORTS_SMARTMIPS
1547 select PARAVIRT !! 2538 bool "SmartMIPS"
>> 2539 help
>> 2540 SmartMIPS is a extension of the MIPS32 architecture aimed at
>> 2541 increased security at both hardware and software level for
>> 2542 smartcards. Enabling this option will allow proper use of the
>> 2543 SmartMIPS instructions by Linux applications. However a kernel with
>> 2544 this option will not work on a MIPS core without SmartMIPS core. If
>> 2545 you don't know you probably don't have SmartMIPS and should say N
>> 2546 here.
>> 2547
>> 2548 config CPU_MICROMIPS
>> 2549 depends on 32BIT && SYS_SUPPORTS_MICROMIPS && !CPU_MIPSR6
>> 2550 bool "microMIPS"
1548 help 2551 help
1549 Select this option to enable fine g !! 2552 When this option is enabled the kernel will be built using the
1550 accounting. Time spent executing ot !! 2553 microMIPS ISA
1551 the current vCPU is discounted from <<
1552 that, there can be a small performa <<
1553 2554
1554 If in doubt, say N here. !! 2555 endchoice
1555 <<
1556 config ARCH_SUPPORTS_KEXEC <<
1557 def_bool PM_SLEEP_SMP <<
1558 <<
1559 config ARCH_SUPPORTS_KEXEC_FILE <<
1560 def_bool y <<
1561 <<
1562 config ARCH_SELECTS_KEXEC_FILE <<
1563 def_bool y <<
1564 depends on KEXEC_FILE <<
1565 select HAVE_IMA_KEXEC if IMA <<
1566 2556
1567 config ARCH_SUPPORTS_KEXEC_SIG !! 2557 config CPU_HAS_MSA
1568 def_bool y !! 2558 bool "Support for the MIPS SIMD Architecture"
>> 2559 depends on CPU_SUPPORTS_MSA
>> 2560 depends on MIPS_FP_SUPPORT
>> 2561 depends on 64BIT || MIPS_O32_FP64_SUPPORT
>> 2562 help
>> 2563 MIPS SIMD Architecture (MSA) introduces 128 bit wide vector registers
>> 2564 and a set of SIMD instructions to operate on them. When this option
>> 2565 is enabled the kernel will support allocating & switching MSA
>> 2566 vector register contexts. If you know that your kernel will only be
>> 2567 running on CPUs which do not support MSA or that your userland will
>> 2568 not be making use of it then you may wish to say N here to reduce
>> 2569 the size & complexity of your kernel.
1569 2570
1570 config ARCH_SUPPORTS_KEXEC_IMAGE_VERIFY_SIG !! 2571 If unsure, say Y.
1571 def_bool y <<
1572 2572
1573 config ARCH_DEFAULT_KEXEC_IMAGE_VERIFY_SIG !! 2573 config CPU_HAS_WB
1574 def_bool y !! 2574 bool
1575 2575
1576 config ARCH_SUPPORTS_CRASH_DUMP !! 2576 config XKS01
1577 def_bool y !! 2577 bool
1578 2578
1579 config ARCH_HAS_GENERIC_CRASHKERNEL_RESERVATI !! 2579 config CPU_HAS_DIEI
1580 def_bool CRASH_RESERVE !! 2580 depends on !CPU_DIEI_BROKEN
>> 2581 bool
1581 2582
1582 config TRANS_TABLE !! 2583 config CPU_DIEI_BROKEN
1583 def_bool y !! 2584 bool
1584 depends on HIBERNATION || KEXEC_CORE <<
1585 2585
1586 config XEN_DOM0 !! 2586 config CPU_HAS_RIXI
1587 def_bool y !! 2587 bool
1588 depends on XEN <<
1589 2588
1590 config XEN !! 2589 config CPU_NO_LOAD_STORE_LR
1591 bool "Xen guest support on ARM64" !! 2590 bool
1592 depends on ARM64 && OF <<
1593 select SWIOTLB_XEN <<
1594 select PARAVIRT <<
1595 help 2591 help
1596 Say Y if you want to run Linux in a !! 2592 CPU lacks support for unaligned load and store instructions:
>> 2593 LWL, LWR, SWL, SWR (Load/store word left/right).
>> 2594 LDL, LDR, SDL, SDR (Load/store doubleword left/right, for 64bit
>> 2595 systems).
1597 2596
1598 # include/linux/mmzone.h requires the followi <<
1599 # <<
1600 # MAX_PAGE_ORDER + PAGE_SHIFT <= SECTION_SI <<
1601 # 2597 #
1602 # so the maximum value of MAX_PAGE_ORDER is S !! 2598 # Vectored interrupt mode is an R2 feature
1603 # 2599 #
1604 # | SECTION_SIZE_BITS | PAGE_SHIFT | m !! 2600 config CPU_MIPSR2_IRQ_VI
1605 # ----+-------------------+--------------+--- !! 2601 bool
1606 # 4K | 27 | 12 | <<
1607 # 16K | 27 | 14 | <<
1608 # 64K | 29 | 16 | <<
1609 config ARCH_FORCE_MAX_ORDER <<
1610 int <<
1611 default "13" if ARM64_64K_PAGES <<
1612 default "11" if ARM64_16K_PAGES <<
1613 default "10" <<
1614 help <<
1615 The kernel page allocator limits th <<
1616 contiguous allocations. The limit i <<
1617 defines the maximal power of two of <<
1618 allocated as a single contiguous bl <<
1619 overriding the default setting when <<
1620 large blocks of physically contiguo <<
1621 <<
1622 The maximal size of allocation cann <<
1623 section, so the value of MAX_PAGE_O <<
1624 <<
1625 MAX_PAGE_ORDER + PAGE_SHIFT <= SE <<
1626 <<
1627 Don't change if unsure. <<
1628 <<
1629 config UNMAP_KERNEL_AT_EL0 <<
1630 bool "Unmap kernel when running in us <<
1631 default y <<
1632 help <<
1633 Speculation attacks against some hi <<
1634 be used to bypass MMU permission ch <<
1635 userspace. This can be defended aga <<
1636 when running in userspace, mapping <<
1637 via a trampoline page in the vector <<
1638 <<
1639 If unsure, say Y. <<
1640 2602
1641 config MITIGATE_SPECTRE_BRANCH_HISTORY !! 2603 #
1642 bool "Mitigate Spectre style attacks !! 2604 # Extended interrupt mode is an R2 feature
1643 default y !! 2605 #
1644 help !! 2606 config CPU_MIPSR2_IRQ_EI
1645 Speculation attacks against some hi !! 2607 bool
1646 make use of branch history to influ <<
1647 When taking an exception from user- <<
1648 or a firmware call overwrites the b <<
1649 2608
1650 config RODATA_FULL_DEFAULT_ENABLED !! 2609 config CPU_HAS_SYNC
1651 bool "Apply r/o permissions of VM are !! 2610 bool
>> 2611 depends on !CPU_R3000
1652 default y 2612 default y
1653 help <<
1654 Apply read-only attributes of VM ar <<
1655 the backing pages as well. This pre <<
1656 from being modified (inadvertently <<
1657 mapping of the same memory page. Th <<
1658 be turned off at runtime by passing <<
1659 with rodata=full if this option is <<
1660 <<
1661 This requires the linear region to <<
1662 which may adversely affect performa <<
1663 2613
1664 config ARM64_SW_TTBR0_PAN !! 2614 #
1665 bool "Emulate Privileged Access Never !! 2615 # CPU non-features
1666 depends on !KCSAN !! 2616 #
1667 help !! 2617 config CPU_DADDI_WORKAROUNDS
1668 Enabling this option prevents the k !! 2618 bool
1669 user-space memory directly by point <<
1670 zeroed area and reserved ASID. The <<
1671 restore the valid TTBR0_EL1 tempora <<
1672 2619
1673 config ARM64_TAGGED_ADDR_ABI !! 2620 config CPU_R4000_WORKAROUNDS
1674 bool "Enable the tagged user addresse !! 2621 bool
1675 default y !! 2622 select CPU_R4400_WORKAROUNDS
1676 help <<
1677 When this option is enabled, user a <<
1678 relaxed ABI via prctl() allowing ta <<
1679 to system calls as pointer argument <<
1680 Documentation/arch/arm64/tagged-add <<
1681 2623
1682 menuconfig COMPAT !! 2624 config CPU_R4400_WORKAROUNDS
1683 bool "Kernel support for 32-bit EL0" !! 2625 bool
1684 depends on ARM64_4K_PAGES || EXPERT <<
1685 select HAVE_UID16 <<
1686 select OLD_SIGSUSPEND3 <<
1687 select COMPAT_OLD_SIGACTION <<
1688 help <<
1689 This option enables support for a 3 <<
1690 kernel at EL1. AArch32-specific com <<
1691 the user helper functions, VFP supp <<
1692 handled appropriately by the kernel <<
1693 2626
1694 If you use a page size other than 4 !! 2627 config CPU_R4X00_BUGS64
1695 that you will only be able to execu !! 2628 bool
1696 with page size aligned segments. !! 2629 default y if SYS_HAS_CPU_R4X00 && 64BIT && (TARGET_ISA_REV < 1)
1697 2630
1698 If you want to execute 32-bit users !! 2631 config MIPS_ASID_SHIFT
>> 2632 int
>> 2633 default 6 if CPU_R3000 || CPU_TX39XX
>> 2634 default 0
1699 2635
1700 if COMPAT !! 2636 config MIPS_ASID_BITS
>> 2637 int
>> 2638 default 0 if MIPS_ASID_BITS_VARIABLE
>> 2639 default 6 if CPU_R3000 || CPU_TX39XX
>> 2640 default 8
1701 2641
1702 config KUSER_HELPERS !! 2642 config MIPS_ASID_BITS_VARIABLE
1703 bool "Enable kuser helpers page for 3 !! 2643 bool
1704 default y <<
1705 help <<
1706 Warning: disabling this option may <<
1707 2644
1708 Provide kuser helpers to compat tas !! 2645 config MIPS_CRC_SUPPORT
1709 helper code to userspace in read on !! 2646 bool
1710 to allow userspace to be independen <<
1711 the system. This permits binaries t <<
1712 to ARMv8 without modification. <<
1713 2647
1714 See Documentation/arch/arm/kernel_u !! 2648 # R4600 erratum. Due to the lack of errata information the exact
>> 2649 # technical details aren't known. I've experimentally found that disabling
>> 2650 # interrupts during indexed I-cache flushes seems to be sufficient to deal
>> 2651 # with the issue.
>> 2652 config WAR_R4600_V1_INDEX_ICACHEOP
>> 2653 bool
1715 2654
1716 However, the fixed address nature o !! 2655 # Pleasures of the R4600 V1.x. Cite from the IDT R4600 V1.7 errata:
1717 by ROP (return orientated programmi !! 2656 #
1718 exploits. !! 2657 # 18. The CACHE instructions Hit_Writeback_Invalidate_D, Hit_Writeback_D,
>> 2658 # Hit_Invalidate_D and Create_Dirty_Excl_D should only be
>> 2659 # executed if there is no other dcache activity. If the dcache is
>> 2660 # accessed for another instruction immeidately preceding when these
>> 2661 # cache instructions are executing, it is possible that the dcache
>> 2662 # tag match outputs used by these cache instructions will be
>> 2663 # incorrect. These cache instructions should be preceded by at least
>> 2664 # four instructions that are not any kind of load or store
>> 2665 # instruction.
>> 2666 #
>> 2667 # This is not allowed: lw
>> 2668 # nop
>> 2669 # nop
>> 2670 # nop
>> 2671 # cache Hit_Writeback_Invalidate_D
>> 2672 #
>> 2673 # This is allowed: lw
>> 2674 # nop
>> 2675 # nop
>> 2676 # nop
>> 2677 # nop
>> 2678 # cache Hit_Writeback_Invalidate_D
>> 2679 config WAR_R4600_V1_HIT_CACHEOP
>> 2680 bool
1719 2681
1720 If all of the binaries and librarie !! 2682 # Writeback and invalidate the primary cache dcache before DMA.
1721 are built specifically for your pla !! 2683 #
1722 these helpers, then you can turn th !! 2684 # R4600 v2.0 bug: "The CACHE instructions Hit_Writeback_Inv_D,
1723 such exploits. However, in that cas !! 2685 # Hit_Writeback_D, Hit_Invalidate_D and Create_Dirty_Exclusive_D will only
1724 relying on those helpers is run, it !! 2686 # operate correctly if the internal data cache refill buffer is empty. These
>> 2687 # CACHE instructions should be separated from any potential data cache miss
>> 2688 # by a load instruction to an uncached address to empty the response buffer."
>> 2689 # (Revision 2.0 device errata from IDT available on https://www.idt.com/
>> 2690 # in .pdf format.)
>> 2691 config WAR_R4600_V2_HIT_CACHEOP
>> 2692 bool
1725 2693
1726 Say N here only if you are absolute !! 2694 # From TX49/H2 manual: "If the instruction (i.e. CACHE) is issued for
1727 need these helpers; otherwise, the !! 2695 # the line which this instruction itself exists, the following
>> 2696 # operation is not guaranteed."
>> 2697 #
>> 2698 # Workaround: do two phase flushing for Index_Invalidate_I
>> 2699 config WAR_TX49XX_ICACHE_INDEX_INV
>> 2700 bool
1728 2701
1729 config COMPAT_VDSO !! 2702 # The RM7000 processors and the E9000 cores have a bug (though PMC-Sierra
1730 bool "Enable vDSO for 32-bit applicat !! 2703 # opposes it being called that) where invalid instructions in the same
1731 depends on !CPU_BIG_ENDIAN !! 2704 # I-cache line worth of instructions being fetched may case spurious
1732 depends on (CC_IS_CLANG && LD_IS_LLD) !! 2705 # exceptions.
1733 select GENERIC_COMPAT_VDSO !! 2706 config WAR_ICACHE_REFILLS
1734 default y !! 2707 bool
1735 help <<
1736 Place in the process address space <<
1737 ELF shared object providing fast im <<
1738 and clock_gettime. <<
1739 2708
1740 You must have a 32-bit build of gli !! 2709 # On the R10000 up to version 2.6 (not sure about 2.7) there is a bug that
1741 to seamlessly take advantage of thi !! 2710 # may cause ll / sc and lld / scd sequences to execute non-atomically.
>> 2711 config WAR_R10000_LLSC
>> 2712 bool
1742 2713
1743 config THUMB2_COMPAT_VDSO !! 2714 # 34K core erratum: "Problems Executing the TLBR Instruction"
1744 bool "Compile the 32-bit vDSO for Thu !! 2715 config WAR_MIPS34K_MISSED_ITLB
1745 depends on COMPAT_VDSO !! 2716 bool
1746 default y <<
1747 help <<
1748 Compile the compat vDSO with '-mthu <<
1749 otherwise with '-marm'. <<
1750 2717
1751 config COMPAT_ALIGNMENT_FIXUPS !! 2718 #
1752 bool "Fix up misaligned multi-word lo !! 2719 # - Highmem only makes sense for the 32-bit kernel.
>> 2720 # - The current highmem code will only work properly on physically indexed
>> 2721 # caches such as R3000, SB1, R7000 or those that look like they're virtually
>> 2722 # indexed such as R4000/R4400 SC and MC versions or R10000. So for the
>> 2723 # moment we protect the user and offer the highmem option only on machines
>> 2724 # where it's known to be safe. This will not offer highmem on a few systems
>> 2725 # such as MIPS32 and MIPS64 CPUs which may have virtual and physically
>> 2726 # indexed CPUs but we're playing safe.
>> 2727 # - We use SYS_SUPPORTS_HIGHMEM to offer highmem only for systems where we
>> 2728 # know they might have memory configurations that could make use of highmem
>> 2729 # support.
>> 2730 #
>> 2731 config HIGHMEM
>> 2732 bool "High Memory Support"
>> 2733 depends on 32BIT && CPU_SUPPORTS_HIGHMEM && SYS_SUPPORTS_HIGHMEM && !CPU_MIPS32_3_5_EVA
1753 2734
1754 menuconfig ARMV8_DEPRECATED !! 2735 config CPU_SUPPORTS_HIGHMEM
1755 bool "Emulate deprecated/obsolete ARM !! 2736 bool
1756 depends on SYSCTL <<
1757 help <<
1758 Legacy software support may require <<
1759 that have been deprecated or obsole <<
1760 2737
1761 Enable this config to enable select !! 2738 config SYS_SUPPORTS_HIGHMEM
1762 features. !! 2739 bool
1763 2740
1764 If unsure, say Y !! 2741 config SYS_SUPPORTS_SMARTMIPS
>> 2742 bool
1765 2743
1766 if ARMV8_DEPRECATED !! 2744 config SYS_SUPPORTS_MICROMIPS
>> 2745 bool
1767 2746
1768 config SWP_EMULATION !! 2747 config SYS_SUPPORTS_MIPS16
1769 bool "Emulate SWP/SWPB instructions" !! 2748 bool
1770 help 2749 help
1771 ARMv8 obsoletes the use of A32 SWP/ !! 2750 This option must be set if a kernel might be executed on a MIPS16-
1772 they are always undefined. Say Y he !! 2751 enabled CPU even if MIPS16 is not actually being used. In other
1773 emulation of these instructions for !! 2752 words, it makes the kernel MIPS16-tolerant.
1774 This feature can be controlled at r <<
1775 sysctl which is disabled by default <<
1776 2753
1777 In some older versions of glibc [<= !! 2754 config CPU_SUPPORTS_MSA
1778 trylock() operations with the assum !! 2755 bool
1779 be preempted. This invalid assumpti <<
1780 with SWP emulation enabled, leading <<
1781 application. <<
1782 2756
1783 NOTE: when accessing uncached share !! 2757 config ARCH_FLATMEM_ENABLE
1784 on an external transaction monitori !! 2758 def_bool y
1785 monitor to maintain update atomicit !! 2759 depends on !NUMA && !CPU_LOONGSON2EF
1786 implement a global monitor, this op <<
1787 perform SWP operations to uncached <<
1788 2760
1789 If unsure, say Y !! 2761 config ARCH_SPARSEMEM_ENABLE
>> 2762 bool
>> 2763 select SPARSEMEM_STATIC if !SGI_IP27
1790 2764
1791 config CP15_BARRIER_EMULATION !! 2765 config NUMA
1792 bool "Emulate CP15 Barrier instructio !! 2766 bool "NUMA Support"
>> 2767 depends on SYS_SUPPORTS_NUMA
1793 help 2768 help
1794 The CP15 barrier instructions - CP1 !! 2769 Say Y to compile the kernel to support NUMA (Non-Uniform Memory
1795 CP15DMB - are deprecated in ARMv8 ( !! 2770 Access). This option improves performance on systems with more
1796 strongly recommended to use the ISB !! 2771 than two nodes; on two node systems it is generally better to
1797 instructions instead. !! 2772 leave it disabled; on single node systems leave this option
1798 !! 2773 disabled.
1799 Say Y here to enable software emula <<
1800 instructions for AArch32 userspace <<
1801 enabled, CP15 barrier usage is trac <<
1802 identify software that needs updati <<
1803 controlled at runtime with the abi. <<
1804 2774
1805 If unsure, say Y !! 2775 config SYS_SUPPORTS_NUMA
>> 2776 bool
1806 2777
1807 config SETEND_EMULATION !! 2778 config HAVE_SETUP_PER_CPU_AREA
1808 bool "Emulate SETEND instruction" !! 2779 def_bool y
1809 help !! 2780 depends on NUMA
1810 The SETEND instruction alters the d <<
1811 AArch32 EL0, and is deprecated in A <<
1812 2781
1813 Say Y here to enable software emula !! 2782 config NEED_PER_CPU_EMBED_FIRST_CHUNK
1814 for AArch32 userspace code. This fe !! 2783 def_bool y
1815 at runtime with the abi.setend sysc !! 2784 depends on NUMA
1816 2785
1817 Note: All the cpus on the system mu !! 2786 config RELOCATABLE
1818 for this feature to be enabled. If !! 2787 bool "Relocatable kernel"
1819 endian - is hotplugged in after thi !! 2788 depends on SYS_SUPPORTS_RELOCATABLE
1820 be unexpected results in the applic !! 2789 depends on CPU_MIPS32_R2 || CPU_MIPS64_R2 || \
>> 2790 CPU_MIPS32_R5 || CPU_MIPS64_R5 || \
>> 2791 CPU_MIPS32_R6 || CPU_MIPS64_R6 || \
>> 2792 CPU_P5600 || CAVIUM_OCTEON_SOC
>> 2793 help
>> 2794 This builds a kernel image that retains relocation information
>> 2795 so it can be loaded someplace besides the default 1MB.
>> 2796 The relocations make the kernel binary about 15% larger,
>> 2797 but are discarded at runtime
>> 2798
>> 2799 config RELOCATION_TABLE_SIZE
>> 2800 hex "Relocation table size"
>> 2801 depends on RELOCATABLE
>> 2802 range 0x0 0x01000000
>> 2803 default "0x00100000"
>> 2804 help
>> 2805 A table of relocation data will be appended to the kernel binary
>> 2806 and parsed at boot to fix up the relocated kernel.
1821 2807
1822 If unsure, say Y !! 2808 This option allows the amount of space reserved for the table to be
1823 endif # ARMV8_DEPRECATED !! 2809 adjusted, although the default of 1Mb should be ok in most cases.
1824 2810
1825 endif # COMPAT !! 2811 The build will fail and a valid size suggested if this is too small.
1826 2812
1827 menu "ARMv8.1 architectural features" !! 2813 If unsure, leave at the default value.
1828 2814
1829 config ARM64_HW_AFDBM !! 2815 config RANDOMIZE_BASE
1830 bool "Support for hardware updates of !! 2816 bool "Randomize the address of the kernel image"
1831 default y !! 2817 depends on RELOCATABLE
1832 help 2818 help
1833 The ARMv8.1 architecture extensions !! 2819 Randomizes the physical and virtual address at which the
1834 hardware updates of the access and !! 2820 kernel image is loaded, as a security feature that
1835 table entries. When enabled in TCR_ !! 2821 deters exploit attempts relying on knowledge of the location
1836 capable processors, accesses to pag !! 2822 of kernel internals.
1837 set this bit instead of raising an <<
1838 Similarly, writes to read-only page <<
1839 clear the read-only bit (AP[2]) ins <<
1840 permission fault. <<
1841 2823
1842 Kernels built with this configurati !! 2824 Entropy is generated using any coprocessor 0 registers available.
1843 to work on pre-ARMv8.1 hardware and <<
1844 minimal. If unsure, say Y. <<
1845 2825
1846 config ARM64_PAN !! 2826 The kernel will be offset by up to RANDOMIZE_BASE_MAX_OFFSET.
1847 bool "Enable support for Privileged A <<
1848 default y <<
1849 help <<
1850 Privileged Access Never (PAN; part <<
1851 prevents the kernel or hypervisor f <<
1852 memory directly. <<
1853 2827
1854 Choosing this option will cause any !! 2828 If unsure, say N.
1855 copy_to_user et al) memory access t <<
1856 2829
1857 The feature is detected at runtime, !! 2830 config RANDOMIZE_BASE_MAX_OFFSET
1858 instruction if the cpu does not imp !! 2831 hex "Maximum kASLR offset" if EXPERT
>> 2832 depends on RANDOMIZE_BASE
>> 2833 range 0x0 0x40000000 if EVA || 64BIT
>> 2834 range 0x0 0x08000000
>> 2835 default "0x01000000"
>> 2836 help
>> 2837 When kASLR is active, this provides the maximum offset that will
>> 2838 be applied to the kernel image. It should be set according to the
>> 2839 amount of physical RAM available in the target system minus
>> 2840 PHYSICAL_START and must be a power of 2.
1859 2841
1860 config AS_HAS_LSE_ATOMICS !! 2842 This is limited by the size of KSEG0, 256Mb on 32-bit or 1Gb with
1861 def_bool $(as-instr,.arch_extension l !! 2843 EVA or 64-bit. The default is 16Mb.
1862 2844
1863 config ARM64_LSE_ATOMICS !! 2845 config NODES_SHIFT
1864 bool !! 2846 int
1865 default ARM64_USE_LSE_ATOMICS !! 2847 default "6"
1866 depends on AS_HAS_LSE_ATOMICS !! 2848 depends on NEED_MULTIPLE_NODES
1867 2849
1868 config ARM64_USE_LSE_ATOMICS !! 2850 config HW_PERF_EVENTS
1869 bool "Atomic instructions" !! 2851 bool "Enable hardware performance counter support for perf events"
>> 2852 depends on PERF_EVENTS && !OPROFILE && (CPU_MIPS32 || CPU_MIPS64 || CPU_R10000 || CPU_SB1 || CPU_CAVIUM_OCTEON || CPU_XLP || CPU_LOONGSON64)
1870 default y 2853 default y
1871 help 2854 help
1872 As part of the Large System Extensi !! 2855 Enable hardware performance counter support for perf events. If
1873 atomic instructions that are design !! 2856 disabled, perf events will use software events only.
1874 very large systems. <<
1875 <<
1876 Say Y here to make use of these ins <<
1877 atomic routines. This incurs a smal <<
1878 not support these instructions and <<
1879 built with binutils >= 2.25 in orde <<
1880 to be used. <<
1881 <<
1882 endmenu # "ARMv8.1 architectural features" <<
1883 <<
1884 menu "ARMv8.2 architectural features" <<
1885 <<
1886 config AS_HAS_ARMV8_2 <<
1887 def_bool $(cc-option,-Wa$(comma)-marc <<
1888 <<
1889 config AS_HAS_SHA3 <<
1890 def_bool $(as-instr,.arch armv8.2-a+s <<
1891 <<
1892 config ARM64_PMEM <<
1893 bool "Enable support for persistent m <<
1894 select ARCH_HAS_PMEM_API <<
1895 select ARCH_HAS_UACCESS_FLUSHCACHE <<
1896 help <<
1897 Say Y to enable support for the per <<
1898 ARMv8.2 DCPoP feature. <<
1899 <<
1900 The feature is detected at runtime, <<
1901 operations if DC CVAP is not suppor <<
1902 DC CVAP itself if the system does n <<
1903 2857
1904 config ARM64_RAS_EXTN !! 2858 config DMI
1905 bool "Enable support for RAS CPU Exte !! 2859 bool "Enable DMI scanning"
>> 2860 depends on MACH_LOONGSON64
>> 2861 select DMI_SCAN_MACHINE_NON_EFI_FALLBACK
1906 default y 2862 default y
1907 help 2863 help
1908 CPUs that support the Reliability, !! 2864 Enabled scanning of DMI to identify machine quirks. Say Y
1909 (RAS) Extensions, part of ARMv8.2 a !! 2865 here unless you have verified that your setup is not
1910 errors, classify them and report th !! 2866 affected by entries in the DMI blacklist. Required by PNP
>> 2867 BIOS code.
1911 2868
1912 On CPUs with these extensions syste !! 2869 config SMP
1913 barriers to determine if faults are !! 2870 bool "Multi-Processing support"
1914 classification from a new set of re !! 2871 depends on SYS_SUPPORTS_SMP
1915 <<
1916 Selecting this feature will allow t <<
1917 and access the new registers if the <<
1918 Platform RAS features may additiona <<
1919 <<
1920 config ARM64_CNP <<
1921 bool "Enable support for Common Not P <<
1922 default y <<
1923 depends on ARM64_PAN || !ARM64_SW_TTB <<
1924 help 2872 help
1925 Common Not Private (CNP) allows tra !! 2873 This enables support for systems with more than one CPU. If you have
1926 be shared between different PEs in !! 2874 a system with only one CPU, say N. If you have a system with more
1927 domain, so the hardware can use thi !! 2875 than one CPU, say Y.
1928 caching of such entries in the TLB. !! 2876
>> 2877 If you say N here, the kernel will run on uni- and multiprocessor
>> 2878 machines, but will use only one CPU of a multiprocessor machine. If
>> 2879 you say Y here, the kernel will run on many, but not all,
>> 2880 uniprocessor machines. On a uniprocessor machine, the kernel
>> 2881 will run faster if you say N here.
1929 2882
1930 Selecting this option allows the CN !! 2883 People using multiprocessor machines who say Y here should also say
1931 at runtime, and does not affect PEs !! 2884 Y to "Enhanced Real Time Clock Support", below.
1932 this feature. <<
1933 2885
1934 endmenu # "ARMv8.2 architectural features" !! 2886 See also the SMP-HOWTO available at
>> 2887 <https://www.tldp.org/docs.html#howto>.
1935 2888
1936 menu "ARMv8.3 architectural features" !! 2889 If you don't know what to do here, say N.
1937 2890
1938 config ARM64_PTR_AUTH !! 2891 config HOTPLUG_CPU
1939 bool "Enable support for pointer auth !! 2892 bool "Support for hot-pluggable CPUs"
1940 default y !! 2893 depends on SMP && SYS_SUPPORTS_HOTPLUG_CPU
1941 help 2894 help
1942 Pointer authentication (part of the !! 2895 Say Y here to allow turning CPUs off and on. CPUs can be
1943 instructions for signing and authen !! 2896 controlled through /sys/devices/system/cpu.
1944 keys, which can be used to mitigate !! 2897 (Note: power management support will enable this option
1945 and other attacks. !! 2898 automatically on SMP systems. )
1946 !! 2899 Say N if you want to disable CPU hotplug.
1947 This option enables these instructi <<
1948 Choosing this option will cause the <<
1949 for each process at exec() time, wi <<
1950 context-switched along with the pro <<
1951 <<
1952 The feature is detected at runtime. <<
1953 hardware it will not be advertised <<
1954 be enabled. <<
1955 2900
1956 If the feature is present on the bo !! 2901 config SMP_UP
1957 the late CPU will be parked. Also, !! 2902 bool
1958 address auth and the late CPU has t <<
1959 but with the feature disabled. On s <<
1960 not be selected. <<
1961 <<
1962 config ARM64_PTR_AUTH_KERNEL <<
1963 bool "Use pointer authentication for <<
1964 default y <<
1965 depends on ARM64_PTR_AUTH <<
1966 depends on (CC_HAS_SIGN_RETURN_ADDRES <<
1967 # Modern compilers insert a .note.gnu <<
1968 # which is only understood by binutil <<
1969 depends on LD_IS_LLD || LD_VERSION >= <<
1970 depends on !CC_IS_CLANG || AS_HAS_CFI <<
1971 depends on (!FUNCTION_GRAPH_TRACER || <<
1972 help <<
1973 If the compiler supports the -mbran <<
1974 -msign-return-address flag (e.g. GC <<
1975 will cause the kernel itself to be <<
1976 protection. In this case, and if th <<
1977 support pointer authentication, the <<
1978 disabled with minimal loss of prote <<
1979 2903
1980 This feature works with FUNCTION_GR !! 2904 config SYS_SUPPORTS_MIPS_CMP
1981 DYNAMIC_FTRACE_WITH_ARGS is enabled !! 2905 bool
1982 2906
1983 config CC_HAS_BRANCH_PROT_PAC_RET !! 2907 config SYS_SUPPORTS_MIPS_CPS
1984 # GCC 9 or later, clang 8 or later !! 2908 bool
1985 def_bool $(cc-option,-mbranch-protect <<
1986 2909
1987 config CC_HAS_SIGN_RETURN_ADDRESS !! 2910 config SYS_SUPPORTS_SMP
1988 # GCC 7, 8 !! 2911 bool
1989 def_bool $(cc-option,-msign-return-ad <<
1990 2912
1991 config AS_HAS_ARMV8_3 !! 2913 config NR_CPUS_DEFAULT_4
1992 def_bool $(cc-option,-Wa$(comma)-marc !! 2914 bool
1993 2915
1994 config AS_HAS_CFI_NEGATE_RA_STATE !! 2916 config NR_CPUS_DEFAULT_8
1995 def_bool $(as-instr,.cfi_startproc\n. !! 2917 bool
1996 2918
1997 config AS_HAS_LDAPR !! 2919 config NR_CPUS_DEFAULT_16
1998 def_bool $(as-instr,.arch_extension r !! 2920 bool
1999 2921
2000 endmenu # "ARMv8.3 architectural features" !! 2922 config NR_CPUS_DEFAULT_32
>> 2923 bool
2001 2924
2002 menu "ARMv8.4 architectural features" !! 2925 config NR_CPUS_DEFAULT_64
>> 2926 bool
2003 2927
2004 config ARM64_AMU_EXTN !! 2928 config NR_CPUS
2005 bool "Enable support for the Activity !! 2929 int "Maximum number of CPUs (2-256)"
2006 default y !! 2930 range 2 256
2007 help !! 2931 depends on SMP
2008 The activity monitors extension is !! 2932 default "4" if NR_CPUS_DEFAULT_4
2009 by the ARMv8.4 CPU architecture. Th !! 2933 default "8" if NR_CPUS_DEFAULT_8
2010 of the activity monitors architectu !! 2934 default "16" if NR_CPUS_DEFAULT_16
>> 2935 default "32" if NR_CPUS_DEFAULT_32
>> 2936 default "64" if NR_CPUS_DEFAULT_64
>> 2937 help
>> 2938 This allows you to specify the maximum number of CPUs which this
>> 2939 kernel will support. The maximum supported value is 32 for 32-bit
>> 2940 kernel and 64 for 64-bit kernels; the minimum value which makes
>> 2941 sense is 1 for Qemu (useful only for kernel debugging purposes)
>> 2942 and 2 for all others.
>> 2943
>> 2944 This is purely to save memory - each supported CPU adds
>> 2945 approximately eight kilobytes to the kernel image. For best
>> 2946 performance should round up your number of processors to the next
>> 2947 power of two.
2011 2948
2012 To enable the use of this extension !! 2949 config MIPS_PERF_SHARED_TC_COUNTERS
>> 2950 bool
2013 2951
2014 Note that for architectural reasons !! 2952 config MIPS_NR_CPU_NR_MAP_1024
2015 support when running on CPUs that p !! 2953 bool
2016 extension. The required support is <<
2017 * Version 1.5 and later of the AR <<
2018 2954
2019 For kernels that have this configur !! 2955 config MIPS_NR_CPU_NR_MAP
2020 firmware, you may need to say N her !! 2956 int
2021 Otherwise you may experience firmwa !! 2957 depends on SMP
2022 accessing the counter registers. Ev !! 2958 default 1024 if MIPS_NR_CPU_NR_MAP_1024
2023 symptoms, the values returned by th !! 2959 default NR_CPUS if !MIPS_NR_CPU_NR_MAP_1024
2024 correctly reflect reality. Most com <<
2025 indicating that the counter is not <<
2026 2960
2027 config AS_HAS_ARMV8_4 !! 2961 #
2028 def_bool $(cc-option,-Wa$(comma)-marc !! 2962 # Timer Interrupt Frequency Configuration
>> 2963 #
2029 2964
2030 config ARM64_TLB_RANGE !! 2965 choice
2031 bool "Enable support for tlbi range f !! 2966 prompt "Timer frequency"
2032 default y !! 2967 default HZ_250
2033 depends on AS_HAS_ARMV8_4 <<
2034 help 2968 help
2035 ARMv8.4-TLBI provides TLBI invalida !! 2969 Allows the configuration of the timer frequency.
2036 range of input addresses. <<
2037 2970
2038 The feature introduces new assembly !! 2971 config HZ_24
2039 support when binutils >= 2.30. !! 2972 bool "24 HZ" if SYS_SUPPORTS_24HZ || SYS_SUPPORTS_ARBIT_HZ
2040 2973
2041 endmenu # "ARMv8.4 architectural features" !! 2974 config HZ_48
>> 2975 bool "48 HZ" if SYS_SUPPORTS_48HZ || SYS_SUPPORTS_ARBIT_HZ
2042 2976
2043 menu "ARMv8.5 architectural features" !! 2977 config HZ_100
>> 2978 bool "100 HZ" if SYS_SUPPORTS_100HZ || SYS_SUPPORTS_ARBIT_HZ
2044 2979
2045 config AS_HAS_ARMV8_5 !! 2980 config HZ_128
2046 def_bool $(cc-option,-Wa$(comma)-marc !! 2981 bool "128 HZ" if SYS_SUPPORTS_128HZ || SYS_SUPPORTS_ARBIT_HZ
2047 2982
2048 config ARM64_BTI !! 2983 config HZ_250
2049 bool "Branch Target Identification su !! 2984 bool "250 HZ" if SYS_SUPPORTS_250HZ || SYS_SUPPORTS_ARBIT_HZ
2050 default y <<
2051 help <<
2052 Branch Target Identification (part <<
2053 provides a mechanism to limit the s <<
2054 branch instructions such as BR or B <<
2055 2985
2056 To make use of BTI on CPUs that sup !! 2986 config HZ_256
>> 2987 bool "256 HZ" if SYS_SUPPORTS_256HZ || SYS_SUPPORTS_ARBIT_HZ
2057 2988
2058 BTI is intended to provide compleme !! 2989 config HZ_1000
2059 flow integrity protection mechanism !! 2990 bool "1000 HZ" if SYS_SUPPORTS_1000HZ || SYS_SUPPORTS_ARBIT_HZ
2060 authentication mechanism provided a <<
2061 For this reason, it does not make s <<
2062 also enabling support for pointer a <<
2063 enabling this option you should als <<
2064 2991
2065 Userspace binaries must also be spe !! 2992 config HZ_1024
2066 this mechanism. If you say N here !! 2993 bool "1024 HZ" if SYS_SUPPORTS_1024HZ || SYS_SUPPORTS_ARBIT_HZ
2067 BTI, such binaries can still run, b <<
2068 enforcement of branch destinations. <<
2069 2994
2070 config ARM64_BTI_KERNEL !! 2995 endchoice
2071 bool "Use Branch Target Identificatio <<
2072 default y <<
2073 depends on ARM64_BTI <<
2074 depends on ARM64_PTR_AUTH_KERNEL <<
2075 depends on CC_HAS_BRANCH_PROT_PAC_RET <<
2076 # https://gcc.gnu.org/bugzilla/show_b <<
2077 depends on !CC_IS_GCC || GCC_VERSION <<
2078 # https://gcc.gnu.org/bugzilla/show_b <<
2079 depends on !CC_IS_GCC <<
2080 depends on (!FUNCTION_GRAPH_TRACER || <<
2081 help <<
2082 Build the kernel with Branch Target <<
2083 and enable enforcement of this for <<
2084 is enabled and the system supports <<
2085 modular code must have BTI enabled. <<
2086 <<
2087 config CC_HAS_BRANCH_PROT_PAC_RET_BTI <<
2088 # GCC 9 or later, clang 8 or later <<
2089 def_bool $(cc-option,-mbranch-protect <<
2090 2996
2091 config ARM64_E0PD !! 2997 config SYS_SUPPORTS_24HZ
2092 bool "Enable support for E0PD" !! 2998 bool
2093 default y <<
2094 help <<
2095 E0PD (part of the ARMv8.5 extension <<
2096 that EL0 accesses made via TTBR1 al <<
2097 providing similar benefits to KASLR <<
2098 with lower overhead and without dis <<
2099 kernel memory such as SPE. <<
2100 2999
2101 This option enables E0PD for TTBR1 !! 3000 config SYS_SUPPORTS_48HZ
>> 3001 bool
2102 3002
2103 config ARM64_AS_HAS_MTE !! 3003 config SYS_SUPPORTS_100HZ
2104 # Initial support for MTE went in bin !! 3004 bool
2105 # ".arch armv8.5-a+memtag" below. How <<
2106 # as a late addition to the final arc <<
2107 # is only supported in the newer 2.32 <<
2108 # versions, hence the extra "stgm" in <<
2109 def_bool $(as-instr,.arch armv8.5-a+m <<
2110 3005
2111 config ARM64_MTE !! 3006 config SYS_SUPPORTS_128HZ
2112 bool "Memory Tagging Extension suppor !! 3007 bool
2113 default y <<
2114 depends on ARM64_AS_HAS_MTE && ARM64_ <<
2115 depends on AS_HAS_ARMV8_5 <<
2116 depends on AS_HAS_LSE_ATOMICS <<
2117 # Required for tag checking in the ua <<
2118 depends on ARM64_PAN <<
2119 select ARCH_HAS_SUBPAGE_FAULTS <<
2120 select ARCH_USES_HIGH_VMA_FLAGS <<
2121 select ARCH_USES_PG_ARCH_2 <<
2122 select ARCH_USES_PG_ARCH_3 <<
2123 help <<
2124 Memory Tagging (part of the ARMv8.5 <<
2125 architectural support for run-time, <<
2126 various classes of memory error to <<
2127 to eliminate vulnerabilities arisin <<
2128 languages. <<
2129 3008
2130 This option enables the support for !! 3009 config SYS_SUPPORTS_250HZ
2131 Extension at EL0 (i.e. for userspac !! 3010 bool
2132 3011
2133 Selecting this option allows the fe !! 3012 config SYS_SUPPORTS_256HZ
2134 runtime. Any secondary CPU not impl !! 3013 bool
2135 not be allowed a late bring-up. <<
2136 3014
2137 Userspace binaries that want to use !! 3015 config SYS_SUPPORTS_1000HZ
2138 explicitly opt in. The mechanism fo !! 3016 bool
2139 described in: <<
2140 3017
2141 Documentation/arch/arm64/memory-tag !! 3018 config SYS_SUPPORTS_1024HZ
>> 3019 bool
2142 3020
2143 endmenu # "ARMv8.5 architectural features" !! 3021 config SYS_SUPPORTS_ARBIT_HZ
>> 3022 bool
>> 3023 default y if !SYS_SUPPORTS_24HZ && \
>> 3024 !SYS_SUPPORTS_48HZ && \
>> 3025 !SYS_SUPPORTS_100HZ && \
>> 3026 !SYS_SUPPORTS_128HZ && \
>> 3027 !SYS_SUPPORTS_250HZ && \
>> 3028 !SYS_SUPPORTS_256HZ && \
>> 3029 !SYS_SUPPORTS_1000HZ && \
>> 3030 !SYS_SUPPORTS_1024HZ
2144 3031
2145 menu "ARMv8.7 architectural features" !! 3032 config HZ
>> 3033 int
>> 3034 default 24 if HZ_24
>> 3035 default 48 if HZ_48
>> 3036 default 100 if HZ_100
>> 3037 default 128 if HZ_128
>> 3038 default 250 if HZ_250
>> 3039 default 256 if HZ_256
>> 3040 default 1000 if HZ_1000
>> 3041 default 1024 if HZ_1024
>> 3042
>> 3043 config SCHED_HRTICK
>> 3044 def_bool HIGH_RES_TIMERS
>> 3045
>> 3046 config KEXEC
>> 3047 bool "Kexec system call"
>> 3048 select KEXEC_CORE
>> 3049 help
>> 3050 kexec is a system call that implements the ability to shutdown your
>> 3051 current kernel, and to start another kernel. It is like a reboot
>> 3052 but it is independent of the system firmware. And like a reboot
>> 3053 you can start any kernel with it, not just Linux.
>> 3054
>> 3055 The name comes from the similarity to the exec system call.
>> 3056
>> 3057 It is an ongoing process to be certain the hardware in a machine
>> 3058 is properly shutdown, so do not be surprised if this code does not
>> 3059 initially work for you. As of this writing the exact hardware
>> 3060 interface is strongly in flux, so no good recommendation can be
>> 3061 made.
>> 3062
>> 3063 config CRASH_DUMP
>> 3064 bool "Kernel crash dumps"
>> 3065 help
>> 3066 Generate crash dump after being started by kexec.
>> 3067 This should be normally only set in special crash dump kernels
>> 3068 which are loaded in the main kernel with kexec-tools into
>> 3069 a specially reserved region and then later executed after
>> 3070 a crash by kdump/kexec. The crash dump kernel must be compiled
>> 3071 to a memory address not used by the main kernel or firmware using
>> 3072 PHYSICAL_START.
>> 3073
>> 3074 config PHYSICAL_START
>> 3075 hex "Physical address where the kernel is loaded"
>> 3076 default "0xffffffff84000000"
>> 3077 depends on CRASH_DUMP
>> 3078 help
>> 3079 This gives the CKSEG0 or KSEG0 address where the kernel is loaded.
>> 3080 If you plan to use kernel for capturing the crash dump change
>> 3081 this value to start of the reserved region (the "X" value as
>> 3082 specified in the "crashkernel=YM@XM" command line boot parameter
>> 3083 passed to the panic-ed kernel).
>> 3084
>> 3085 config MIPS_O32_FP64_SUPPORT
>> 3086 bool "Support for O32 binaries using 64-bit FP" if !CPU_MIPSR6
>> 3087 depends on 32BIT || MIPS32_O32
>> 3088 help
>> 3089 When this is enabled, the kernel will support use of 64-bit floating
>> 3090 point registers with binaries using the O32 ABI along with the
>> 3091 EF_MIPS_FP64 ELF header flag (typically built with -mfp64). On
>> 3092 32-bit MIPS systems this support is at the cost of increasing the
>> 3093 size and complexity of the compiled FPU emulator. Thus if you are
>> 3094 running a MIPS32 system and know that none of your userland binaries
>> 3095 will require 64-bit floating point, you may wish to reduce the size
>> 3096 of your kernel & potentially improve FP emulation performance by
>> 3097 saying N here.
>> 3098
>> 3099 Although binutils currently supports use of this flag the details
>> 3100 concerning its effect upon the O32 ABI in userland are still being
>> 3101 worked on. In order to avoid userland becoming dependant upon current
>> 3102 behaviour before the details have been finalised, this option should
>> 3103 be considered experimental and only enabled by those working upon
>> 3104 said details.
2146 3105
2147 config ARM64_EPAN !! 3106 If unsure, say N.
2148 bool "Enable support for Enhanced Pri <<
2149 default y <<
2150 depends on ARM64_PAN <<
2151 help <<
2152 Enhanced Privileged Access Never (E <<
2153 Access Never to be used with Execut <<
2154 3107
2155 The feature is detected at runtime, !! 3108 config USE_OF
2156 if the cpu does not implement the f !! 3109 bool
2157 endmenu # "ARMv8.7 architectural features" !! 3110 select OF
>> 3111 select OF_EARLY_FLATTREE
>> 3112 select IRQ_DOMAIN
2158 3113
2159 menu "ARMv8.9 architectural features" !! 3114 config UHI_BOOT
>> 3115 bool
2160 3116
2161 config ARM64_POE !! 3117 config BUILTIN_DTB
2162 prompt "Permission Overlay Extension" !! 3118 bool
2163 def_bool y <<
2164 select ARCH_USES_HIGH_VMA_FLAGS <<
2165 select ARCH_HAS_PKEYS <<
2166 help <<
2167 The Permission Overlay Extension is <<
2168 Protection Keys. Memory Protection <<
2169 enforcing page-based protections, b <<
2170 of the page tables when an applicat <<
2171 3119
2172 For details, see Documentation/core !! 3120 choice
>> 3121 prompt "Kernel appended dtb support" if USE_OF
>> 3122 default MIPS_NO_APPENDED_DTB
2173 3123
2174 If unsure, say y. !! 3124 config MIPS_NO_APPENDED_DTB
>> 3125 bool "None"
>> 3126 help
>> 3127 Do not enable appended dtb support.
>> 3128
>> 3129 config MIPS_ELF_APPENDED_DTB
>> 3130 bool "vmlinux"
>> 3131 help
>> 3132 With this option, the boot code will look for a device tree binary
>> 3133 DTB) included in the vmlinux ELF section .appended_dtb. By default
>> 3134 it is empty and the DTB can be appended using binutils command
>> 3135 objcopy:
>> 3136
>> 3137 objcopy --update-section .appended_dtb=<filename>.dtb vmlinux
>> 3138
>> 3139 This is meant as a backward compatiblity convenience for those
>> 3140 systems with a bootloader that can't be upgraded to accommodate
>> 3141 the documented boot protocol using a device tree.
>> 3142
>> 3143 config MIPS_RAW_APPENDED_DTB
>> 3144 bool "vmlinux.bin or vmlinuz.bin"
>> 3145 help
>> 3146 With this option, the boot code will look for a device tree binary
>> 3147 DTB) appended to raw vmlinux.bin or vmlinuz.bin.
>> 3148 (e.g. cat vmlinux.bin <filename>.dtb > vmlinux_w_dtb).
>> 3149
>> 3150 This is meant as a backward compatibility convenience for those
>> 3151 systems with a bootloader that can't be upgraded to accommodate
>> 3152 the documented boot protocol using a device tree.
>> 3153
>> 3154 Beware that there is very little in terms of protection against
>> 3155 this option being confused by leftover garbage in memory that might
>> 3156 look like a DTB header after a reboot if no actual DTB is appended
>> 3157 to vmlinux.bin. Do not leave this option active in a production kernel
>> 3158 if you don't intend to always append a DTB.
>> 3159 endchoice
2175 3160
2176 config ARCH_PKEY_BITS !! 3161 choice
2177 int !! 3162 prompt "Kernel command line type" if !CMDLINE_OVERRIDE
2178 default 3 !! 3163 default MIPS_CMDLINE_FROM_DTB if USE_OF && !ATH79 && !MACH_INGENIC && \
>> 3164 !MACH_LOONGSON64 && !MIPS_MALTA && \
>> 3165 !CAVIUM_OCTEON_SOC
>> 3166 default MIPS_CMDLINE_FROM_BOOTLOADER
>> 3167
>> 3168 config MIPS_CMDLINE_FROM_DTB
>> 3169 depends on USE_OF
>> 3170 bool "Dtb kernel arguments if available"
>> 3171
>> 3172 config MIPS_CMDLINE_DTB_EXTEND
>> 3173 depends on USE_OF
>> 3174 bool "Extend dtb kernel arguments with bootloader arguments"
>> 3175
>> 3176 config MIPS_CMDLINE_FROM_BOOTLOADER
>> 3177 bool "Bootloader kernel arguments if available"
>> 3178
>> 3179 config MIPS_CMDLINE_BUILTIN_EXTEND
>> 3180 depends on CMDLINE_BOOL
>> 3181 bool "Extend builtin kernel arguments with bootloader arguments"
>> 3182 endchoice
2179 3183
2180 endmenu # "ARMv8.9 architectural features" !! 3184 endmenu
2181 3185
2182 config ARM64_SVE !! 3186 config LOCKDEP_SUPPORT
2183 bool "ARM Scalable Vector Extension s !! 3187 bool
2184 default y 3188 default y
2185 help <<
2186 The Scalable Vector Extension (SVE) <<
2187 execution state which complements a <<
2188 of the base architecture to support <<
2189 additional vectorisation opportunit <<
2190 <<
2191 To enable use of this extension on <<
2192 3189
2193 On CPUs that support the SVE2 exten !! 3190 config STACKTRACE_SUPPORT
2194 those too. !! 3191 bool
>> 3192 default y
2195 3193
2196 Note that for architectural reasons !! 3194 config PGTABLE_LEVELS
2197 support when running on SVE capable !! 3195 int
2198 is present in: !! 3196 default 4 if PAGE_SIZE_4KB && MIPS_VA_BITS_48
>> 3197 default 3 if 64BIT && (!PAGE_SIZE_64KB || MIPS_VA_BITS_48)
>> 3198 default 2
2199 3199
2200 * version 1.5 and later of the AR !! 3200 config MIPS_AUTO_PFN_OFFSET
2201 * the AArch64 boot wrapper since !! 3201 bool
2202 ("bootwrapper: SVE: Enable SVE <<
2203 3202
2204 For other firmware implementations, !! 3203 menu "Bus options (PCI, PCMCIA, EISA, ISA, TC)"
2205 or vendor. <<
2206 3204
2207 If you need the kernel to boot on S !! 3205 config PCI_DRIVERS_GENERIC
2208 firmware, you may need to say N her !! 3206 select PCI_DOMAINS_GENERIC if PCI
2209 fixed. Otherwise, you may experien !! 3207 bool
2210 booting the kernel. If unsure and <<
2211 symptoms, you should assume that it <<
2212 3208
2213 config ARM64_SME !! 3209 config PCI_DRIVERS_LEGACY
2214 bool "ARM Scalable Matrix Extension s !! 3210 def_bool !PCI_DRIVERS_GENERIC
2215 default y !! 3211 select NO_GENERIC_PCI_IOPORT_MAP
2216 depends on ARM64_SVE !! 3212 select PCI_DOMAINS if PCI
2217 depends on BROKEN <<
2218 help <<
2219 The Scalable Matrix Extension (SME) <<
2220 execution state which utilises a su <<
2221 instruction set, together with the <<
2222 register state capable of holding t <<
2223 enable various matrix operations. <<
2224 3213
2225 config ARM64_PSEUDO_NMI !! 3214 #
2226 bool "Support for NMI-like interrupts !! 3215 # ISA support is now enabled via select. Too many systems still have the one
2227 select ARM_GIC_V3 !! 3216 # or other ISA chip on the board that users don't know about so don't expect
2228 help !! 3217 # users to choose the right thing ...
2229 Adds support for mimicking Non-Mask !! 3218 #
2230 GIC interrupt priority. This suppor !! 3219 config ISA
2231 ARM GIC. !! 3220 bool
2232 3221
2233 This high priority configuration fo !! 3222 config TC
2234 explicitly enabled by setting the k !! 3223 bool "TURBOchannel support"
2235 "irqchip.gicv3_pseudo_nmi" to 1. !! 3224 depends on MACH_DECSTATION
>> 3225 help
>> 3226 TURBOchannel is a DEC (now Compaq (now HP)) bus for Alpha and MIPS
>> 3227 processors. TURBOchannel programming specifications are available
>> 3228 at:
>> 3229 <ftp://ftp.hp.com/pub/alphaserver/archive/triadd/>
>> 3230 and:
>> 3231 <http://www.computer-refuge.org/classiccmp/ftp.digital.com/pub/DEC/TriAdd/>
>> 3232 Linux driver support status is documented at:
>> 3233 <http://www.linux-mips.org/wiki/DECstation>
2236 3234
2237 If unsure, say N !! 3235 config MMU
>> 3236 bool
>> 3237 default y
2238 3238
2239 if ARM64_PSEUDO_NMI !! 3239 config ARCH_MMAP_RND_BITS_MIN
2240 config ARM64_DEBUG_PRIORITY_MASKING !! 3240 default 12 if 64BIT
2241 bool "Debug interrupt priority maskin !! 3241 default 8
2242 help <<
2243 This adds runtime checks to functio <<
2244 interrupts when using priority mask <<
2245 the validity of ICC_PMR_EL1 when ca <<
2246 3242
2247 If unsure, say N !! 3243 config ARCH_MMAP_RND_BITS_MAX
2248 endif # ARM64_PSEUDO_NMI !! 3244 default 18 if 64BIT
>> 3245 default 15
2249 3246
2250 config RELOCATABLE !! 3247 config ARCH_MMAP_RND_COMPAT_BITS_MIN
2251 bool "Build a relocatable kernel imag !! 3248 default 8
2252 select ARCH_HAS_RELR <<
2253 default y <<
2254 help <<
2255 This builds the kernel as a Positio <<
2256 which retains all relocation metada <<
2257 kernel binary at runtime to a diffe <<
2258 address it was linked at. <<
2259 Since AArch64 uses the RELA relocat <<
2260 relocation pass at runtime even if <<
2261 same address it was linked at. <<
2262 3249
2263 config RANDOMIZE_BASE !! 3250 config ARCH_MMAP_RND_COMPAT_BITS_MAX
2264 bool "Randomize the address of the ke !! 3251 default 15
2265 select RELOCATABLE <<
2266 help <<
2267 Randomizes the virtual address at w <<
2268 loaded, as a security feature that <<
2269 relying on knowledge of the locatio <<
2270 <<
2271 It is the bootloader's job to provi <<
2272 random u64 value in /chosen/kaslr-s <<
2273 <<
2274 When booting via the UEFI stub, it <<
2275 EFI_RNG_PROTOCOL implementation (if <<
2276 to the kernel proper. In addition, <<
2277 location of the kernel Image as wel <<
2278 3252
2279 If unsure, say N. !! 3253 config I8253
>> 3254 bool
>> 3255 select CLKSRC_I8253
>> 3256 select CLKEVT_I8253
>> 3257 select MIPS_EXTERNAL_TIMER
2280 3258
2281 config RANDOMIZE_MODULE_REGION_FULL !! 3259 config ZONE_DMA
2282 bool "Randomize the module region ove !! 3260 bool
2283 depends on RANDOMIZE_BASE <<
2284 default y <<
2285 help <<
2286 Randomizes the location of the modu <<
2287 covering the core kernel. This way, <<
2288 to leak information about the locat <<
2289 but it does imply that function cal <<
2290 kernel will need to be resolved via <<
2291 <<
2292 When this option is not set, the mo <<
2293 a limited range that contains the [ <<
2294 core kernel, so branch relocations <<
2295 the region is exhausted. In this pa <<
2296 exhaustion, modules might be able t <<
2297 3261
2298 config CC_HAVE_STACKPROTECTOR_SYSREG !! 3262 config ZONE_DMA32
2299 def_bool $(cc-option,-mstack-protecto !! 3263 bool
2300 3264
2301 config STACKPROTECTOR_PER_TASK !! 3265 endmenu
2302 def_bool y <<
2303 depends on STACKPROTECTOR && CC_HAVE_ <<
2304 3266
2305 config UNWIND_PATCH_PAC_INTO_SCS !! 3267 config TRAD_SIGNALS
2306 bool "Enable shadow call stack dynami !! 3268 bool
2307 # needs Clang with https://github.com <<
2308 depends on CC_IS_CLANG && CLANG_VERSI <<
2309 depends on ARM64_PTR_AUTH_KERNEL && C <<
2310 depends on SHADOW_CALL_STACK <<
2311 select UNWIND_TABLES <<
2312 select DYNAMIC_SCS <<
2313 <<
2314 config ARM64_CONTPTE <<
2315 bool "Contiguous PTE mappings for use <<
2316 depends on TRANSPARENT_HUGEPAGE <<
2317 default y <<
2318 help <<
2319 When enabled, user mappings are con <<
2320 bit, for any mappings that meet the <<
2321 This reduces TLB pressure and impro <<
2322 <<
2323 endmenu # "Kernel Features" <<
2324 <<
2325 menu "Boot options" <<
2326 <<
2327 config ARM64_ACPI_PARKING_PROTOCOL <<
2328 bool "Enable support for the ARM64 AC <<
2329 depends on ACPI <<
2330 help <<
2331 Enable support for the ARM64 ACPI p <<
2332 the kernel will not allow booting t <<
2333 protocol even if the corresponding <<
2334 MADT table. <<
2335 <<
2336 config CMDLINE <<
2337 string "Default kernel command string <<
2338 default "" <<
2339 help <<
2340 Provide a set of default command-li <<
2341 entering them here. As a minimum, y <<
2342 root device (e.g. root=/dev/nfs). <<
2343 3269
2344 choice !! 3270 config MIPS32_COMPAT
2345 prompt "Kernel command line type" !! 3271 bool
2346 depends on CMDLINE != "" <<
2347 default CMDLINE_FROM_BOOTLOADER <<
2348 help <<
2349 Choose how the kernel will handle t <<
2350 command line string. <<
2351 <<
2352 config CMDLINE_FROM_BOOTLOADER <<
2353 bool "Use bootloader kernel arguments <<
2354 help <<
2355 Uses the command-line options passe <<
2356 the boot loader doesn't provide any <<
2357 string provided in CMDLINE will be <<
2358 <<
2359 config CMDLINE_FORCE <<
2360 bool "Always use the default kernel c <<
2361 help <<
2362 Always use the default kernel comma <<
2363 loader passes other arguments to th <<
2364 This is useful if you cannot or don <<
2365 command-line options your boot load <<
2366 3272
2367 endchoice !! 3273 config COMPAT
>> 3274 bool
2368 3275
2369 config EFI_STUB !! 3276 config SYSVIPC_COMPAT
2370 bool 3277 bool
2371 3278
2372 config EFI !! 3279 config MIPS32_O32
2373 bool "UEFI runtime support" !! 3280 bool "Kernel support for o32 binaries"
2374 depends on OF && !CPU_BIG_ENDIAN !! 3281 depends on 64BIT
2375 depends on KERNEL_MODE_NEON !! 3282 select ARCH_WANT_OLD_COMPAT_IPC
2376 select ARCH_SUPPORTS_ACPI !! 3283 select COMPAT
2377 select LIBFDT !! 3284 select MIPS32_COMPAT
2378 select UCS2_STRING !! 3285 select SYSVIPC_COMPAT if SYSVIPC
2379 select EFI_PARAMS_FROM_FDT !! 3286 help
2380 select EFI_RUNTIME_WRAPPERS !! 3287 Select this option if you want to run o32 binaries. These are pure
2381 select EFI_STUB !! 3288 32-bit binaries as used by the 32-bit Linux/MIPS port. Most of
2382 select EFI_GENERIC_STUB !! 3289 existing binaries are in this format.
2383 imply IMA_SECURE_AND_OR_TRUSTED_BOOT <<
2384 default y <<
2385 help <<
2386 This option provides support for ru <<
2387 by UEFI firmware (such as non-volat <<
2388 clock, and platform reset). A UEFI <<
2389 allow the kernel to be booted as an <<
2390 is only useful on systems that have <<
2391 <<
2392 config COMPRESSED_INSTALL <<
2393 bool "Install compressed image by def <<
2394 help <<
2395 This makes the regular "make instal <<
2396 image we built, not the legacy unco <<
2397 <<
2398 You can check that a compressed ima <<
2399 "make zinstall" first, and verifyin <<
2400 in your environment before making " <<
2401 you. <<
2402 3290
2403 config DMI !! 3291 If unsure, say Y.
2404 bool "Enable support for SMBIOS (DMI) <<
2405 depends on EFI <<
2406 default y <<
2407 help <<
2408 This enables SMBIOS/DMI feature for <<
2409 3292
2410 This option is only useful on syste !! 3293 config MIPS32_N32
2411 However, even with this option, the !! 3294 bool "Kernel support for n32 binaries"
2412 continue to boot on existing non-UE !! 3295 depends on 64BIT
>> 3296 select ARCH_WANT_COMPAT_IPC_PARSE_VERSION
>> 3297 select COMPAT
>> 3298 select MIPS32_COMPAT
>> 3299 select SYSVIPC_COMPAT if SYSVIPC
>> 3300 help
>> 3301 Select this option if you want to run n32 binaries. These are
>> 3302 64-bit binaries using 32-bit quantities for addressing and certain
>> 3303 data that would normally be 64-bit. They are used in special
>> 3304 cases.
2413 3305
2414 endmenu # "Boot options" !! 3306 If unsure, say N.
2415 3307
2416 menu "Power management options" !! 3308 config BINFMT_ELF32
>> 3309 bool
>> 3310 default y if MIPS32_O32 || MIPS32_N32
>> 3311 select ELFCORE
2417 3312
2418 source "kernel/power/Kconfig" !! 3313 menu "Power management options"
2419 3314
2420 config ARCH_HIBERNATION_POSSIBLE 3315 config ARCH_HIBERNATION_POSSIBLE
2421 def_bool y 3316 def_bool y
2422 depends on CPU_PM !! 3317 depends on SYS_SUPPORTS_HOTPLUG_CPU || !SMP
2423 <<
2424 config ARCH_HIBERNATION_HEADER <<
2425 def_bool y <<
2426 depends on HIBERNATION <<
2427 3318
2428 config ARCH_SUSPEND_POSSIBLE 3319 config ARCH_SUSPEND_POSSIBLE
2429 def_bool y 3320 def_bool y
>> 3321 depends on SYS_SUPPORTS_HOTPLUG_CPU || !SMP
2430 3322
2431 endmenu # "Power management options" !! 3323 source "kernel/power/Kconfig"
2432 3324
2433 menu "CPU Power Management" !! 3325 endmenu
2434 3326
2435 source "drivers/cpuidle/Kconfig" !! 3327 config MIPS_EXTERNAL_TIMER
>> 3328 bool
>> 3329
>> 3330 menu "CPU Power Management"
2436 3331
>> 3332 if CPU_SUPPORTS_CPUFREQ && MIPS_EXTERNAL_TIMER
2437 source "drivers/cpufreq/Kconfig" 3333 source "drivers/cpufreq/Kconfig"
>> 3334 endif
>> 3335
>> 3336 source "drivers/cpuidle/Kconfig"
2438 3337
2439 endmenu # "CPU Power Management" !! 3338 endmenu
2440 3339
2441 source "drivers/acpi/Kconfig" !! 3340 source "drivers/firmware/Kconfig"
2442 3341
2443 source "arch/arm64/kvm/Kconfig" !! 3342 source "arch/mips/kvm/Kconfig"
2444 3343
>> 3344 source "arch/mips/vdso/Kconfig"
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