1 # SPDX-License-Identifier: GPL-2.0-only !! 1 # SPDX-License-Identifier: GPL-2.0
2 config ARM64 !! 2 config MIPS
3 def_bool y !! 3 bool
4 select ACPI_APMT if ACPI !! 4 default y
5 select ACPI_CCA_REQUIRED if ACPI !! 5 select ARCH_32BIT_OFF_T if !64BIT
6 select ACPI_GENERIC_GSI if ACPI !! 6 select ARCH_BINFMT_ELF_STATE if MIPS_FP_SUPPORT
7 select ACPI_GTDT if ACPI <<
8 select ACPI_HOTPLUG_CPU if ACPI_PROCES <<
9 select ACPI_IORT if ACPI <<
10 select ACPI_REDUCED_HARDWARE_ONLY if A <<
11 select ACPI_MCFG if (ACPI && PCI) <<
12 select ACPI_SPCR_TABLE if ACPI <<
13 select ACPI_PPTT if ACPI <<
14 select ARCH_HAS_DEBUG_WX <<
15 select ARCH_BINFMT_ELF_EXTRA_PHDRS <<
16 select ARCH_BINFMT_ELF_STATE <<
17 select ARCH_CORRECT_STACKTRACE_ON_KRET <<
18 select ARCH_ENABLE_HUGEPAGE_MIGRATION <<
19 select ARCH_ENABLE_MEMORY_HOTPLUG <<
20 select ARCH_ENABLE_MEMORY_HOTREMOVE <<
21 select ARCH_ENABLE_SPLIT_PMD_PTLOCK if <<
22 select ARCH_ENABLE_THP_MIGRATION if TR <<
23 select ARCH_HAS_CACHE_LINE_SIZE <<
24 select ARCH_HAS_CURRENT_STACK_POINTER <<
25 select ARCH_HAS_DEBUG_VIRTUAL <<
26 select ARCH_HAS_DEBUG_VM_PGTABLE <<
27 select ARCH_HAS_DMA_OPS if XEN <<
28 select ARCH_HAS_DMA_PREP_COHERENT <<
29 select ARCH_HAS_ACPI_TABLE_UPGRADE if <<
30 select ARCH_HAS_FAST_MULTIPLIER <<
31 select ARCH_HAS_FORTIFY_SOURCE 7 select ARCH_HAS_FORTIFY_SOURCE
32 select ARCH_HAS_GCOV_PROFILE_ALL <<
33 select ARCH_HAS_GIGANTIC_PAGE <<
34 select ARCH_HAS_KCOV 8 select ARCH_HAS_KCOV
35 select ARCH_HAS_KERNEL_FPU_SUPPORT if !! 9 select ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE if !EVA
36 select ARCH_HAS_KEEPINITRD !! 10 select ARCH_HAS_PTE_SPECIAL if !(32BIT && CPU_HAS_RIXI)
37 select ARCH_HAS_MEMBARRIER_SYNC_CORE <<
38 select ARCH_HAS_MEM_ENCRYPT <<
39 select ARCH_HAS_NMI_SAFE_THIS_CPU_OPS <<
40 select ARCH_HAS_NON_OVERLAPPING_ADDRES <<
41 select ARCH_HAS_PTE_DEVMAP <<
42 select ARCH_HAS_PTE_SPECIAL <<
43 select ARCH_HAS_HW_PTE_YOUNG <<
44 select ARCH_HAS_SETUP_DMA_OPS <<
45 select ARCH_HAS_SET_DIRECT_MAP <<
46 select ARCH_HAS_SET_MEMORY <<
47 select ARCH_STACKWALK <<
48 select ARCH_HAS_STRICT_KERNEL_RWX <<
49 select ARCH_HAS_STRICT_MODULE_RWX <<
50 select ARCH_HAS_SYNC_DMA_FOR_DEVICE <<
51 select ARCH_HAS_SYNC_DMA_FOR_CPU <<
52 select ARCH_HAS_SYSCALL_WRAPPER <<
53 select ARCH_HAS_TICK_BROADCAST if GENE 11 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
54 select ARCH_HAS_ZONE_DMA_SET if EXPERT !! 12 select ARCH_HAS_UBSAN_SANITIZE_ALL
55 select ARCH_HAVE_ELF_PROT !! 13 select ARCH_HAS_GCOV_PROFILE_ALL
56 select ARCH_HAVE_NMI_SAFE_CMPXCHG !! 14 select ARCH_KEEP_MEMBLOCK if DEBUG_KERNEL
57 select ARCH_HAVE_TRACE_MMIO_ACCESS !! 15 select ARCH_SUPPORTS_UPROBES
58 select ARCH_INLINE_READ_LOCK if !PREEM !! 16 select ARCH_USE_BUILTIN_BSWAP
59 select ARCH_INLINE_READ_LOCK_BH if !PR !! 17 select ARCH_USE_CMPXCHG_LOCKREF if 64BIT
60 select ARCH_INLINE_READ_LOCK_IRQ if !P <<
61 select ARCH_INLINE_READ_LOCK_IRQSAVE i <<
62 select ARCH_INLINE_READ_UNLOCK if !PRE <<
63 select ARCH_INLINE_READ_UNLOCK_BH if ! <<
64 select ARCH_INLINE_READ_UNLOCK_IRQ if <<
65 select ARCH_INLINE_READ_UNLOCK_IRQREST <<
66 select ARCH_INLINE_WRITE_LOCK if !PREE <<
67 select ARCH_INLINE_WRITE_LOCK_BH if !P <<
68 select ARCH_INLINE_WRITE_LOCK_IRQ if ! <<
69 select ARCH_INLINE_WRITE_LOCK_IRQSAVE <<
70 select ARCH_INLINE_WRITE_UNLOCK if !PR <<
71 select ARCH_INLINE_WRITE_UNLOCK_BH if <<
72 select ARCH_INLINE_WRITE_UNLOCK_IRQ if <<
73 select ARCH_INLINE_WRITE_UNLOCK_IRQRES <<
74 select ARCH_INLINE_SPIN_TRYLOCK if !PR <<
75 select ARCH_INLINE_SPIN_TRYLOCK_BH if <<
76 select ARCH_INLINE_SPIN_LOCK if !PREEM <<
77 select ARCH_INLINE_SPIN_LOCK_BH if !PR <<
78 select ARCH_INLINE_SPIN_LOCK_IRQ if !P <<
79 select ARCH_INLINE_SPIN_LOCK_IRQSAVE i <<
80 select ARCH_INLINE_SPIN_UNLOCK if !PRE <<
81 select ARCH_INLINE_SPIN_UNLOCK_BH if ! <<
82 select ARCH_INLINE_SPIN_UNLOCK_IRQ if <<
83 select ARCH_INLINE_SPIN_UNLOCK_IRQREST <<
84 select ARCH_KEEP_MEMBLOCK <<
85 select ARCH_MHP_MEMMAP_ON_MEMORY_ENABL <<
86 select ARCH_USE_CMPXCHG_LOCKREF <<
87 select ARCH_USE_GNU_PROPERTY <<
88 select ARCH_USE_MEMTEST <<
89 select ARCH_USE_QUEUED_RWLOCKS 18 select ARCH_USE_QUEUED_RWLOCKS
90 select ARCH_USE_QUEUED_SPINLOCKS 19 select ARCH_USE_QUEUED_SPINLOCKS
91 select ARCH_USE_SYM_ANNOTATIONS !! 20 select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT if MMU
92 select ARCH_SUPPORTS_DEBUG_PAGEALLOC !! 21 select ARCH_WANT_IPC_PARSE_VERSION
93 select ARCH_SUPPORTS_HUGETLBFS <<
94 select ARCH_SUPPORTS_MEMORY_FAILURE <<
95 select ARCH_SUPPORTS_SHADOW_CALL_STACK <<
96 select ARCH_SUPPORTS_LTO_CLANG if CPU_ <<
97 select ARCH_SUPPORTS_LTO_CLANG_THIN <<
98 select ARCH_SUPPORTS_CFI_CLANG <<
99 select ARCH_SUPPORTS_ATOMIC_RMW <<
100 select ARCH_SUPPORTS_INT128 if CC_HAS_ <<
101 select ARCH_SUPPORTS_NUMA_BALANCING <<
102 select ARCH_SUPPORTS_PAGE_TABLE_CHECK <<
103 select ARCH_SUPPORTS_PER_VMA_LOCK <<
104 select ARCH_SUPPORTS_HUGE_PFNMAP if TR <<
105 select ARCH_SUPPORTS_RT <<
106 select ARCH_WANT_BATCHED_UNMAP_TLB_FLU <<
107 select ARCH_WANT_COMPAT_IPC_PARSE_VERS <<
108 select ARCH_WANT_DEFAULT_BPF_JIT <<
109 select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_ <<
110 select ARCH_WANT_FRAME_POINTERS <<
111 select ARCH_WANT_HUGE_PMD_SHARE if ARM <<
112 select ARCH_WANT_LD_ORPHAN_WARN <<
113 select ARCH_WANTS_EXECMEM_LATE if EXEC <<
114 select ARCH_WANTS_NO_INSTR <<
115 select ARCH_WANTS_THP_SWAP if ARM64_4K <<
116 select ARCH_HAS_UBSAN <<
117 select ARM_AMBA <<
118 select ARM_ARCH_TIMER <<
119 select ARM_GIC <<
120 select AUDIT_ARCH_COMPAT_GENERIC <<
121 select ARM_GIC_V2M if PCI <<
122 select ARM_GIC_V3 <<
123 select ARM_GIC_V3_ITS if PCI <<
124 select ARM_PSCI_FW <<
125 select BUILDTIME_TABLE_SORT 22 select BUILDTIME_TABLE_SORT
126 select CLONE_BACKWARDS 23 select CLONE_BACKWARDS
127 select COMMON_CLK !! 24 select CPU_NO_EFFICIENT_FFS if (TARGET_ISA_REV < 1)
128 select CPU_PM if (SUSPEND || CPU_IDLE) !! 25 select CPU_PM if CPU_IDLE
129 select CPUMASK_OFFSTACK if NR_CPUS > 2 !! 26 select GENERIC_ATOMIC64 if !64BIT
130 select CRC32 !! 27 select GENERIC_CMOS_UPDATE
131 select DCACHE_WORD_ACCESS <<
132 select DYNAMIC_FTRACE if FUNCTION_TRAC <<
133 select DMA_BOUNCE_UNALIGNED_KMALLOC <<
134 select DMA_DIRECT_REMAP <<
135 select EDAC_SUPPORT <<
136 select FRAME_POINTER <<
137 select FUNCTION_ALIGNMENT_4B <<
138 select FUNCTION_ALIGNMENT_8B if DYNAMI <<
139 select GENERIC_ALLOCATOR <<
140 select GENERIC_ARCH_TOPOLOGY <<
141 select GENERIC_CLOCKEVENTS_BROADCAST <<
142 select GENERIC_CPU_AUTOPROBE 28 select GENERIC_CPU_AUTOPROBE
143 select GENERIC_CPU_DEVICES !! 29 select GENERIC_GETTIMEOFDAY
144 select GENERIC_CPU_VULNERABILITIES !! 30 select GENERIC_IOMAP
145 select GENERIC_EARLY_IOREMAP <<
146 select GENERIC_IDLE_POLL_SETUP <<
147 select GENERIC_IOREMAP <<
148 select GENERIC_IRQ_IPI <<
149 select GENERIC_IRQ_PROBE 31 select GENERIC_IRQ_PROBE
150 select GENERIC_IRQ_SHOW 32 select GENERIC_IRQ_SHOW
151 select GENERIC_IRQ_SHOW_LEVEL !! 33 select GENERIC_ISA_DMA if EISA
152 select GENERIC_LIB_DEVMEM_IS_ALLOWED !! 34 select GENERIC_LIB_ASHLDI3
153 select GENERIC_PCI_IOMAP !! 35 select GENERIC_LIB_ASHRDI3
154 select GENERIC_PTDUMP !! 36 select GENERIC_LIB_CMPDI2
155 select GENERIC_SCHED_CLOCK !! 37 select GENERIC_LIB_LSHRDI3
>> 38 select GENERIC_LIB_UCMPDI2
>> 39 select GENERIC_SCHED_CLOCK if !CAVIUM_OCTEON_SOC
156 select GENERIC_SMP_IDLE_THREAD 40 select GENERIC_SMP_IDLE_THREAD
157 select GENERIC_TIME_VSYSCALL 41 select GENERIC_TIME_VSYSCALL
158 select GENERIC_GETTIMEOFDAY !! 42 select GUP_GET_PTE_LOW_HIGH if CPU_MIPS32 && PHYS_ADDR_T_64BIT
159 select GENERIC_VDSO_TIME_NS !! 43 select HANDLE_DOMAIN_IRQ
160 select HARDIRQS_SW_RESEND <<
161 select HAS_IOPORT <<
162 select HAVE_MOVE_PMD <<
163 select HAVE_MOVE_PUD <<
164 select HAVE_PCI <<
165 select HAVE_ACPI_APEI if (ACPI && EFI) <<
166 select HAVE_ALIGNED_STRUCT_PAGE <<
167 select HAVE_ARCH_AUDITSYSCALL <<
168 select HAVE_ARCH_BITREVERSE <<
169 select HAVE_ARCH_COMPILER_H 44 select HAVE_ARCH_COMPILER_H
170 select HAVE_ARCH_HUGE_VMALLOC <<
171 select HAVE_ARCH_HUGE_VMAP <<
172 select HAVE_ARCH_JUMP_LABEL 45 select HAVE_ARCH_JUMP_LABEL
173 select HAVE_ARCH_JUMP_LABEL_RELATIVE <<
174 select HAVE_ARCH_KASAN <<
175 select HAVE_ARCH_KASAN_VMALLOC <<
176 select HAVE_ARCH_KASAN_SW_TAGS <<
177 select HAVE_ARCH_KASAN_HW_TAGS if ARM6 <<
178 # Some instrumentation may be unsound, <<
179 select HAVE_ARCH_KCSAN if EXPERT <<
180 select HAVE_ARCH_KFENCE <<
181 select HAVE_ARCH_KGDB 46 select HAVE_ARCH_KGDB
182 select HAVE_ARCH_MMAP_RND_BITS !! 47 select HAVE_ARCH_MMAP_RND_BITS if MMU
183 select HAVE_ARCH_MMAP_RND_COMPAT_BITS !! 48 select HAVE_ARCH_MMAP_RND_COMPAT_BITS if MMU && COMPAT
184 select HAVE_ARCH_PREL32_RELOCATIONS <<
185 select HAVE_ARCH_RANDOMIZE_KSTACK_OFFS <<
186 select HAVE_ARCH_SECCOMP_FILTER 49 select HAVE_ARCH_SECCOMP_FILTER
187 select HAVE_ARCH_STACKLEAK <<
188 select HAVE_ARCH_THREAD_STRUCT_WHITELI <<
189 select HAVE_ARCH_TRACEHOOK 50 select HAVE_ARCH_TRACEHOOK
190 select HAVE_ARCH_TRANSPARENT_HUGEPAGE !! 51 select HAVE_ARCH_TRANSPARENT_HUGEPAGE if CPU_SUPPORTS_HUGEPAGES
191 select HAVE_ARCH_VMAP_STACK <<
192 select HAVE_ARM_SMCCC <<
193 select HAVE_ASM_MODVERSIONS 52 select HAVE_ASM_MODVERSIONS
194 select HAVE_EBPF_JIT !! 53 select HAVE_CBPF_JIT if !64BIT && !CPU_MICROMIPS
>> 54 select HAVE_CONTEXT_TRACKING
>> 55 select HAVE_TIF_NOHZ
195 select HAVE_C_RECORDMCOUNT 56 select HAVE_C_RECORDMCOUNT
196 select HAVE_CMPXCHG_DOUBLE <<
197 select HAVE_CMPXCHG_LOCAL <<
198 select HAVE_CONTEXT_TRACKING_USER <<
199 select HAVE_DEBUG_KMEMLEAK 57 select HAVE_DEBUG_KMEMLEAK
>> 58 select HAVE_DEBUG_STACKOVERFLOW
200 select HAVE_DMA_CONTIGUOUS 59 select HAVE_DMA_CONTIGUOUS
201 select HAVE_DYNAMIC_FTRACE 60 select HAVE_DYNAMIC_FTRACE
202 select HAVE_DYNAMIC_FTRACE_WITH_ARGS \ !! 61 select HAVE_EBPF_JIT if 64BIT && !CPU_MICROMIPS && TARGET_ISA_REV >= 2
203 if (GCC_SUPPORTS_DYNAMIC_FTRAC !! 62 select HAVE_EXIT_THREAD
204 CLANG_SUPPORTS_DYNAMIC_FTR !! 63 select HAVE_FAST_GUP
205 select HAVE_DYNAMIC_FTRACE_WITH_DIRECT <<
206 if DYNAMIC_FTRACE_WITH_ARGS && <<
207 select HAVE_DYNAMIC_FTRACE_WITH_CALL_O <<
208 if (DYNAMIC_FTRACE_WITH_ARGS & <<
209 (CC_IS_CLANG || !CC_OPTIMI <<
210 select FTRACE_MCOUNT_USE_PATCHABLE_FUN <<
211 if DYNAMIC_FTRACE_WITH_ARGS <<
212 select HAVE_SAMPLE_FTRACE_DIRECT <<
213 select HAVE_SAMPLE_FTRACE_DIRECT_MULTI <<
214 select HAVE_EFFICIENT_UNALIGNED_ACCESS <<
215 select HAVE_GUP_FAST <<
216 select HAVE_FTRACE_MCOUNT_RECORD 64 select HAVE_FTRACE_MCOUNT_RECORD
217 select HAVE_FUNCTION_TRACER <<
218 select HAVE_FUNCTION_ERROR_INJECTION <<
219 select HAVE_FUNCTION_GRAPH_TRACER 65 select HAVE_FUNCTION_GRAPH_TRACER
220 select HAVE_FUNCTION_GRAPH_RETVAL !! 66 select HAVE_FUNCTION_TRACER
221 select HAVE_GCC_PLUGINS 67 select HAVE_GCC_PLUGINS
222 select HAVE_HARDLOCKUP_DETECTOR_PERF i !! 68 select HAVE_GENERIC_VDSO
223 HW_PERF_EVENTS && HAVE_PERF_EV !! 69 select HAVE_IDE
224 select HAVE_HW_BREAKPOINT if PERF_EVEN <<
225 select HAVE_IOREMAP_PROT 70 select HAVE_IOREMAP_PROT
>> 71 select HAVE_IRQ_EXIT_ON_IRQ_STACK
226 select HAVE_IRQ_TIME_ACCOUNTING 72 select HAVE_IRQ_TIME_ACCOUNTING
>> 73 select HAVE_KPROBES
>> 74 select HAVE_KRETPROBES
>> 75 select HAVE_LD_DEAD_CODE_DATA_ELIMINATION
227 select HAVE_MOD_ARCH_SPECIFIC 76 select HAVE_MOD_ARCH_SPECIFIC
228 select HAVE_NMI 77 select HAVE_NMI
>> 78 select HAVE_OPROFILE
229 select HAVE_PERF_EVENTS 79 select HAVE_PERF_EVENTS
230 select HAVE_PERF_EVENTS_NMI if ARM64_P <<
231 select HAVE_PERF_REGS <<
232 select HAVE_PERF_USER_STACK_DUMP <<
233 select HAVE_PREEMPT_DYNAMIC_KEY <<
234 select HAVE_REGS_AND_STACK_ACCESS_API 80 select HAVE_REGS_AND_STACK_ACCESS_API
235 select HAVE_POSIX_CPU_TIMERS_TASK_WORK <<
236 select HAVE_FUNCTION_ARG_ACCESS_API <<
237 select MMU_GATHER_RCU_TABLE_FREE <<
238 select HAVE_RSEQ 81 select HAVE_RSEQ
239 select HAVE_RUST if RUSTC_SUPPORTS_ARM !! 82 select HAVE_SPARSE_SYSCALL_NR
240 select HAVE_STACKPROTECTOR 83 select HAVE_STACKPROTECTOR
241 select HAVE_SYSCALL_TRACEPOINTS 84 select HAVE_SYSCALL_TRACEPOINTS
242 select HAVE_KPROBES !! 85 select HAVE_VIRT_CPU_ACCOUNTING_GEN if 64BIT || !SMP
243 select HAVE_KRETPROBES <<
244 select HAVE_GENERIC_VDSO <<
245 select HOTPLUG_CORE_SYNC_DEAD if HOTPL <<
246 select IRQ_DOMAIN <<
247 select IRQ_FORCED_THREADING 86 select IRQ_FORCED_THREADING
248 select KASAN_VMALLOC if KASAN !! 87 select ISA if EISA
249 select LOCK_MM_AND_FIND_VMA !! 88 select MODULES_USE_ELF_REL if MODULES
250 select MODULES_USE_ELF_RELA !! 89 select MODULES_USE_ELF_RELA if MODULES && 64BIT
251 select NEED_DMA_MAP_STATE !! 90 select PERF_USE_VMALLOC
252 select NEED_SG_DMA_LENGTH !! 91 select PCI_MSI_ARCH_FALLBACKS if PCI_MSI
253 select OF !! 92 select RTC_LIB
254 select OF_EARLY_FLATTREE !! 93 select SET_FS
255 select PCI_DOMAINS_GENERIC if PCI <<
256 select PCI_ECAM if (ACPI && PCI) <<
257 select PCI_SYSCALL if PCI <<
258 select POWER_RESET <<
259 select POWER_SUPPLY <<
260 select SPARSE_IRQ <<
261 select SWIOTLB <<
262 select SYSCTL_EXCEPTION_TRACE 94 select SYSCTL_EXCEPTION_TRACE
263 select THREAD_INFO_IN_TASK !! 95 select VIRT_TO_BUS
264 select HAVE_ARCH_USERFAULTFD_MINOR if <<
265 select HAVE_ARCH_USERFAULTFD_WP if USE <<
266 select TRACE_IRQFLAGS_SUPPORT <<
267 select TRACE_IRQFLAGS_NMI_SUPPORT <<
268 select HAVE_SOFTIRQ_ON_OWN_STACK <<
269 select USER_STACKTRACE_SUPPORT <<
270 select VDSO_GETRANDOM <<
271 help <<
272 ARM 64-bit (AArch64) Linux support. <<
273 <<
274 config RUSTC_SUPPORTS_ARM64 <<
275 def_bool y <<
276 depends on CPU_LITTLE_ENDIAN <<
277 # Shadow call stack is only supported <<
278 # <<
279 # When using the UNWIND_PATCH_PAC_INTO <<
280 # required due to use of the -Zfixed-x <<
281 # <<
282 # Otherwise, rustc version 1.82+ is re <<
283 # -Zsanitizer=shadow-call-stack flag. <<
284 depends on !SHADOW_CALL_STACK || RUSTC <<
285 <<
286 config CLANG_SUPPORTS_DYNAMIC_FTRACE_WITH_ARGS <<
287 def_bool CC_IS_CLANG <<
288 # https://github.com/ClangBuiltLinux/l <<
289 depends on AS_IS_GNU || (AS_IS_LLVM && <<
290 <<
291 config GCC_SUPPORTS_DYNAMIC_FTRACE_WITH_ARGS <<
292 def_bool CC_IS_GCC <<
293 depends on $(cc-option,-fpatchable-fun <<
294 96
295 config 64BIT !! 97 config MIPS_FIXUP_BIGPHYS_ADDR
296 def_bool y !! 98 bool
297 99
298 config MMU !! 100 config MIPS_GENERIC
299 def_bool y !! 101 bool
300 102
301 config ARM64_CONT_PTE_SHIFT !! 103 config MACH_INGENIC
302 int !! 104 bool
303 default 5 if PAGE_SIZE_64KB !! 105 select SYS_SUPPORTS_32BIT_KERNEL
304 default 7 if PAGE_SIZE_16KB !! 106 select SYS_SUPPORTS_LITTLE_ENDIAN
305 default 4 !! 107 select SYS_SUPPORTS_ZBOOT
>> 108 select DMA_NONCOHERENT
>> 109 select IRQ_MIPS_CPU
>> 110 select PINCTRL
>> 111 select GPIOLIB
>> 112 select COMMON_CLK
>> 113 select GENERIC_IRQ_CHIP
>> 114 select BUILTIN_DTB if MIPS_NO_APPENDED_DTB
>> 115 select USE_OF
>> 116 select CPU_SUPPORTS_CPUFREQ
>> 117 select MIPS_EXTERNAL_TIMER
306 118
307 config ARM64_CONT_PMD_SHIFT !! 119 menu "Machine selection"
308 int <<
309 default 5 if PAGE_SIZE_64KB <<
310 default 5 if PAGE_SIZE_16KB <<
311 default 4 <<
312 120
313 config ARCH_MMAP_RND_BITS_MIN !! 121 choice
314 default 14 if PAGE_SIZE_64KB !! 122 prompt "System type"
315 default 16 if PAGE_SIZE_16KB !! 123 default MIPS_GENERIC_KERNEL
316 default 18 <<
317 124
318 # max bits determined by the following formula !! 125 config MIPS_GENERIC_KERNEL
319 # VA_BITS - PAGE_SHIFT - 3 !! 126 bool "Generic board-agnostic MIPS kernel"
320 config ARCH_MMAP_RND_BITS_MAX !! 127 select MIPS_GENERIC
321 default 19 if ARM64_VA_BITS=36 !! 128 select BOOT_RAW
322 default 24 if ARM64_VA_BITS=39 !! 129 select BUILTIN_DTB
323 default 27 if ARM64_VA_BITS=42 !! 130 select CEVT_R4K
324 default 30 if ARM64_VA_BITS=47 !! 131 select CLKSRC_MIPS_GIC
325 default 29 if ARM64_VA_BITS=48 && ARM6 !! 132 select COMMON_CLK
326 default 31 if ARM64_VA_BITS=48 && ARM6 !! 133 select CPU_MIPSR2_IRQ_EI
327 default 33 if ARM64_VA_BITS=48 !! 134 select CPU_MIPSR2_IRQ_VI
328 default 14 if ARM64_64K_PAGES !! 135 select CSRC_R4K
329 default 16 if ARM64_16K_PAGES !! 136 select DMA_PERDEV_COHERENT
330 default 18 !! 137 select HAVE_PCI
>> 138 select IRQ_MIPS_CPU
>> 139 select MIPS_AUTO_PFN_OFFSET
>> 140 select MIPS_CPU_SCACHE
>> 141 select MIPS_GIC
>> 142 select MIPS_L1_CACHE_SHIFT_7
>> 143 select NO_EXCEPT_FILL
>> 144 select PCI_DRIVERS_GENERIC
>> 145 select SMP_UP if SMP
>> 146 select SWAP_IO_SPACE
>> 147 select SYS_HAS_CPU_MIPS32_R1
>> 148 select SYS_HAS_CPU_MIPS32_R2
>> 149 select SYS_HAS_CPU_MIPS32_R6
>> 150 select SYS_HAS_CPU_MIPS64_R1
>> 151 select SYS_HAS_CPU_MIPS64_R2
>> 152 select SYS_HAS_CPU_MIPS64_R6
>> 153 select SYS_SUPPORTS_32BIT_KERNEL
>> 154 select SYS_SUPPORTS_64BIT_KERNEL
>> 155 select SYS_SUPPORTS_BIG_ENDIAN
>> 156 select SYS_SUPPORTS_HIGHMEM
>> 157 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 158 select SYS_SUPPORTS_MICROMIPS
>> 159 select SYS_SUPPORTS_MIPS16
>> 160 select SYS_SUPPORTS_MIPS_CPS
>> 161 select SYS_SUPPORTS_MULTITHREADING
>> 162 select SYS_SUPPORTS_RELOCATABLE
>> 163 select SYS_SUPPORTS_SMARTMIPS
>> 164 select SYS_SUPPORTS_ZBOOT
>> 165 select UHI_BOOT
>> 166 select USB_EHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
>> 167 select USB_EHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 168 select USB_OHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
>> 169 select USB_OHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 170 select USB_UHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
>> 171 select USB_UHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 172 select USE_OF
>> 173 help
>> 174 Select this to build a kernel which aims to support multiple boards,
>> 175 generally using a flattened device tree passed from the bootloader
>> 176 using the boot protocol defined in the UHI (Unified Hosting
>> 177 Interface) specification.
>> 178
>> 179 config MIPS_ALCHEMY
>> 180 bool "Alchemy processor based machines"
>> 181 select PHYS_ADDR_T_64BIT
>> 182 select CEVT_R4K
>> 183 select CSRC_R4K
>> 184 select IRQ_MIPS_CPU
>> 185 select DMA_MAYBE_COHERENT # Au1000,1500,1100 aren't, rest is
>> 186 select MIPS_FIXUP_BIGPHYS_ADDR if PCI
>> 187 select SYS_HAS_CPU_MIPS32_R1
>> 188 select SYS_SUPPORTS_32BIT_KERNEL
>> 189 select SYS_SUPPORTS_APM_EMULATION
>> 190 select GPIOLIB
>> 191 select SYS_SUPPORTS_ZBOOT
>> 192 select COMMON_CLK
331 193
332 config ARCH_MMAP_RND_COMPAT_BITS_MIN !! 194 config AR7
333 default 7 if ARM64_64K_PAGES !! 195 bool "Texas Instruments AR7"
334 default 9 if ARM64_16K_PAGES !! 196 select BOOT_ELF32
335 default 11 !! 197 select DMA_NONCOHERENT
>> 198 select CEVT_R4K
>> 199 select CSRC_R4K
>> 200 select IRQ_MIPS_CPU
>> 201 select NO_EXCEPT_FILL
>> 202 select SWAP_IO_SPACE
>> 203 select SYS_HAS_CPU_MIPS32_R1
>> 204 select SYS_HAS_EARLY_PRINTK
>> 205 select SYS_SUPPORTS_32BIT_KERNEL
>> 206 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 207 select SYS_SUPPORTS_MIPS16
>> 208 select SYS_SUPPORTS_ZBOOT_UART16550
>> 209 select GPIOLIB
>> 210 select VLYNQ
>> 211 select HAVE_LEGACY_CLK
>> 212 help
>> 213 Support for the Texas Instruments AR7 System-on-a-Chip
>> 214 family: TNETD7100, 7200 and 7300.
>> 215
>> 216 config ATH25
>> 217 bool "Atheros AR231x/AR531x SoC support"
>> 218 select CEVT_R4K
>> 219 select CSRC_R4K
>> 220 select DMA_NONCOHERENT
>> 221 select IRQ_MIPS_CPU
>> 222 select IRQ_DOMAIN
>> 223 select SYS_HAS_CPU_MIPS32_R1
>> 224 select SYS_SUPPORTS_BIG_ENDIAN
>> 225 select SYS_SUPPORTS_32BIT_KERNEL
>> 226 select SYS_HAS_EARLY_PRINTK
>> 227 help
>> 228 Support for Atheros AR231x and Atheros AR531x based boards
>> 229
>> 230 config ATH79
>> 231 bool "Atheros AR71XX/AR724X/AR913X based boards"
>> 232 select ARCH_HAS_RESET_CONTROLLER
>> 233 select BOOT_RAW
>> 234 select CEVT_R4K
>> 235 select CSRC_R4K
>> 236 select DMA_NONCOHERENT
>> 237 select GPIOLIB
>> 238 select PINCTRL
>> 239 select COMMON_CLK
>> 240 select IRQ_MIPS_CPU
>> 241 select SYS_HAS_CPU_MIPS32_R2
>> 242 select SYS_HAS_EARLY_PRINTK
>> 243 select SYS_SUPPORTS_32BIT_KERNEL
>> 244 select SYS_SUPPORTS_BIG_ENDIAN
>> 245 select SYS_SUPPORTS_MIPS16
>> 246 select SYS_SUPPORTS_ZBOOT_UART_PROM
>> 247 select USE_OF
>> 248 select USB_EHCI_ROOT_HUB_TT if USB_EHCI_HCD_PLATFORM
>> 249 help
>> 250 Support for the Atheros AR71XX/AR724X/AR913X SoCs.
>> 251
>> 252 config BMIPS_GENERIC
>> 253 bool "Broadcom Generic BMIPS kernel"
>> 254 select ARCH_HAS_RESET_CONTROLLER
>> 255 select ARCH_HAS_SYNC_DMA_FOR_CPU_ALL
>> 256 select ARCH_HAS_PHYS_TO_DMA
>> 257 select BOOT_RAW
>> 258 select NO_EXCEPT_FILL
>> 259 select USE_OF
>> 260 select CEVT_R4K
>> 261 select CSRC_R4K
>> 262 select SYNC_R4K
>> 263 select COMMON_CLK
>> 264 select BCM6345_L1_IRQ
>> 265 select BCM7038_L1_IRQ
>> 266 select BCM7120_L2_IRQ
>> 267 select BRCMSTB_L2_IRQ
>> 268 select IRQ_MIPS_CPU
>> 269 select DMA_NONCOHERENT
>> 270 select SYS_SUPPORTS_32BIT_KERNEL
>> 271 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 272 select SYS_SUPPORTS_BIG_ENDIAN
>> 273 select SYS_SUPPORTS_HIGHMEM
>> 274 select SYS_HAS_CPU_BMIPS32_3300
>> 275 select SYS_HAS_CPU_BMIPS4350
>> 276 select SYS_HAS_CPU_BMIPS4380
>> 277 select SYS_HAS_CPU_BMIPS5000
>> 278 select SWAP_IO_SPACE
>> 279 select USB_EHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
>> 280 select USB_EHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 281 select USB_OHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
>> 282 select USB_OHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 283 select HARDIRQS_SW_RESEND
>> 284 help
>> 285 Build a generic DT-based kernel image that boots on select
>> 286 BCM33xx cable modem chips, BCM63xx DSL chips, and BCM7xxx set-top
>> 287 box chips. Note that CONFIG_CPU_BIG_ENDIAN/CONFIG_CPU_LITTLE_ENDIAN
>> 288 must be set appropriately for your board.
>> 289
>> 290 config BCM47XX
>> 291 bool "Broadcom BCM47XX based boards"
>> 292 select BOOT_RAW
>> 293 select CEVT_R4K
>> 294 select CSRC_R4K
>> 295 select DMA_NONCOHERENT
>> 296 select HAVE_PCI
>> 297 select IRQ_MIPS_CPU
>> 298 select SYS_HAS_CPU_MIPS32_R1
>> 299 select NO_EXCEPT_FILL
>> 300 select SYS_SUPPORTS_32BIT_KERNEL
>> 301 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 302 select SYS_SUPPORTS_MIPS16
>> 303 select SYS_SUPPORTS_ZBOOT
>> 304 select SYS_HAS_EARLY_PRINTK
>> 305 select USE_GENERIC_EARLY_PRINTK_8250
>> 306 select GPIOLIB
>> 307 select LEDS_GPIO_REGISTER
>> 308 select BCM47XX_NVRAM
>> 309 select BCM47XX_SPROM
>> 310 select BCM47XX_SSB if !BCM47XX_BCMA
>> 311 help
>> 312 Support for BCM47XX based boards
>> 313
>> 314 config BCM63XX
>> 315 bool "Broadcom BCM63XX based boards"
>> 316 select BOOT_RAW
>> 317 select CEVT_R4K
>> 318 select CSRC_R4K
>> 319 select SYNC_R4K
>> 320 select DMA_NONCOHERENT
>> 321 select IRQ_MIPS_CPU
>> 322 select SYS_SUPPORTS_32BIT_KERNEL
>> 323 select SYS_SUPPORTS_BIG_ENDIAN
>> 324 select SYS_HAS_EARLY_PRINTK
>> 325 select SWAP_IO_SPACE
>> 326 select GPIOLIB
>> 327 select MIPS_L1_CACHE_SHIFT_4
>> 328 select CLKDEV_LOOKUP
>> 329 select HAVE_LEGACY_CLK
>> 330 help
>> 331 Support for BCM63XX based boards
>> 332
>> 333 config MIPS_COBALT
>> 334 bool "Cobalt Server"
>> 335 select CEVT_R4K
>> 336 select CSRC_R4K
>> 337 select CEVT_GT641XX
>> 338 select DMA_NONCOHERENT
>> 339 select FORCE_PCI
>> 340 select I8253
>> 341 select I8259
>> 342 select IRQ_MIPS_CPU
>> 343 select IRQ_GT641XX
>> 344 select PCI_GT64XXX_PCI0
>> 345 select SYS_HAS_CPU_NEVADA
>> 346 select SYS_HAS_EARLY_PRINTK
>> 347 select SYS_SUPPORTS_32BIT_KERNEL
>> 348 select SYS_SUPPORTS_64BIT_KERNEL
>> 349 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 350 select USE_GENERIC_EARLY_PRINTK_8250
>> 351
>> 352 config MACH_DECSTATION
>> 353 bool "DECstations"
>> 354 select BOOT_ELF32
>> 355 select CEVT_DS1287
>> 356 select CEVT_R4K if CPU_R4X00
>> 357 select CSRC_IOASIC
>> 358 select CSRC_R4K if CPU_R4X00
>> 359 select CPU_DADDI_WORKAROUNDS if 64BIT
>> 360 select CPU_R4000_WORKAROUNDS if 64BIT
>> 361 select CPU_R4400_WORKAROUNDS if 64BIT
>> 362 select DMA_NONCOHERENT
>> 363 select NO_IOPORT_MAP
>> 364 select IRQ_MIPS_CPU
>> 365 select SYS_HAS_CPU_R3000
>> 366 select SYS_HAS_CPU_R4X00
>> 367 select SYS_SUPPORTS_32BIT_KERNEL
>> 368 select SYS_SUPPORTS_64BIT_KERNEL
>> 369 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 370 select SYS_SUPPORTS_128HZ
>> 371 select SYS_SUPPORTS_256HZ
>> 372 select SYS_SUPPORTS_1024HZ
>> 373 select MIPS_L1_CACHE_SHIFT_4
>> 374 help
>> 375 This enables support for DEC's MIPS based workstations. For details
>> 376 see the Linux/MIPS FAQ on <http://www.linux-mips.org/> and the
>> 377 DECstation porting pages on <http://decstation.unix-ag.org/>.
>> 378
>> 379 If you have one of the following DECstation Models you definitely
>> 380 want to choose R4xx0 for the CPU Type:
>> 381
>> 382 DECstation 5000/50
>> 383 DECstation 5000/150
>> 384 DECstation 5000/260
>> 385 DECsystem 5900/260
>> 386
>> 387 otherwise choose R3000.
>> 388
>> 389 config MACH_JAZZ
>> 390 bool "Jazz family of machines"
>> 391 select ARC_MEMORY
>> 392 select ARC_PROMLIB
>> 393 select ARCH_MIGHT_HAVE_PC_PARPORT
>> 394 select ARCH_MIGHT_HAVE_PC_SERIO
>> 395 select DMA_OPS
>> 396 select FW_ARC
>> 397 select FW_ARC32
>> 398 select ARCH_MAY_HAVE_PC_FDC
>> 399 select CEVT_R4K
>> 400 select CSRC_R4K
>> 401 select DEFAULT_SGI_PARTITION if CPU_BIG_ENDIAN
>> 402 select GENERIC_ISA_DMA
>> 403 select HAVE_PCSPKR_PLATFORM
>> 404 select IRQ_MIPS_CPU
>> 405 select I8253
>> 406 select I8259
>> 407 select ISA
>> 408 select SYS_HAS_CPU_R4X00
>> 409 select SYS_SUPPORTS_32BIT_KERNEL
>> 410 select SYS_SUPPORTS_64BIT_KERNEL
>> 411 select SYS_SUPPORTS_100HZ
>> 412 help
>> 413 This a family of machines based on the MIPS R4030 chipset which was
>> 414 used by several vendors to build RISC/os and Windows NT workstations.
>> 415 Members include the Acer PICA, MIPS Magnum 4000, MIPS Millennium and
>> 416 Olivetti M700-10 workstations.
>> 417
>> 418 config MACH_INGENIC_SOC
>> 419 bool "Ingenic SoC based machines"
>> 420 select MIPS_GENERIC
>> 421 select MACH_INGENIC
>> 422 select SYS_SUPPORTS_ZBOOT_UART16550
>> 423
>> 424 config LANTIQ
>> 425 bool "Lantiq based platforms"
>> 426 select DMA_NONCOHERENT
>> 427 select IRQ_MIPS_CPU
>> 428 select CEVT_R4K
>> 429 select CSRC_R4K
>> 430 select SYS_HAS_CPU_MIPS32_R1
>> 431 select SYS_HAS_CPU_MIPS32_R2
>> 432 select SYS_SUPPORTS_BIG_ENDIAN
>> 433 select SYS_SUPPORTS_32BIT_KERNEL
>> 434 select SYS_SUPPORTS_MIPS16
>> 435 select SYS_SUPPORTS_MULTITHREADING
>> 436 select SYS_SUPPORTS_VPE_LOADER
>> 437 select SYS_HAS_EARLY_PRINTK
>> 438 select GPIOLIB
>> 439 select SWAP_IO_SPACE
>> 440 select BOOT_RAW
>> 441 select CLKDEV_LOOKUP
>> 442 select HAVE_LEGACY_CLK
>> 443 select USE_OF
>> 444 select PINCTRL
>> 445 select PINCTRL_LANTIQ
>> 446 select ARCH_HAS_RESET_CONTROLLER
>> 447 select RESET_CONTROLLER
>> 448
>> 449 config MACH_LOONGSON32
>> 450 bool "Loongson 32-bit family of machines"
>> 451 select SYS_SUPPORTS_ZBOOT
>> 452 help
>> 453 This enables support for the Loongson-1 family of machines.
>> 454
>> 455 Loongson-1 is a family of 32-bit MIPS-compatible SoCs developed by
>> 456 the Institute of Computing Technology (ICT), Chinese Academy of
>> 457 Sciences (CAS).
>> 458
>> 459 config MACH_LOONGSON2EF
>> 460 bool "Loongson-2E/F family of machines"
>> 461 select SYS_SUPPORTS_ZBOOT
>> 462 help
>> 463 This enables the support of early Loongson-2E/F family of machines.
>> 464
>> 465 config MACH_LOONGSON64
>> 466 bool "Loongson 64-bit family of machines"
>> 467 select ARCH_SPARSEMEM_ENABLE
>> 468 select ARCH_MIGHT_HAVE_PC_PARPORT
>> 469 select ARCH_MIGHT_HAVE_PC_SERIO
>> 470 select GENERIC_ISA_DMA_SUPPORT_BROKEN
>> 471 select BOOT_ELF32
>> 472 select BOARD_SCACHE
>> 473 select CSRC_R4K
>> 474 select CEVT_R4K
>> 475 select CPU_HAS_WB
>> 476 select FORCE_PCI
>> 477 select ISA
>> 478 select I8259
>> 479 select IRQ_MIPS_CPU
>> 480 select NO_EXCEPT_FILL
>> 481 select NR_CPUS_DEFAULT_64
>> 482 select USE_GENERIC_EARLY_PRINTK_8250
>> 483 select PCI_DRIVERS_GENERIC
>> 484 select SYS_HAS_CPU_LOONGSON64
>> 485 select SYS_HAS_EARLY_PRINTK
>> 486 select SYS_SUPPORTS_SMP
>> 487 select SYS_SUPPORTS_HOTPLUG_CPU
>> 488 select SYS_SUPPORTS_NUMA
>> 489 select SYS_SUPPORTS_64BIT_KERNEL
>> 490 select SYS_SUPPORTS_HIGHMEM
>> 491 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 492 select SYS_SUPPORTS_ZBOOT
>> 493 select SYS_SUPPORTS_RELOCATABLE
>> 494 select ZONE_DMA32
>> 495 select NUMA
>> 496 select SMP
>> 497 select COMMON_CLK
>> 498 select USE_OF
>> 499 select BUILTIN_DTB
>> 500 select PCI_HOST_GENERIC
>> 501 help
>> 502 This enables the support of Loongson-2/3 family of machines.
>> 503
>> 504 Loongson-2 and Loongson-3 are 64-bit general-purpose processors with
>> 505 GS264/GS464/GS464E/GS464V microarchitecture (except old Loongson-2E
>> 506 and Loongson-2F which will be removed), developed by the Institute
>> 507 of Computing Technology (ICT), Chinese Academy of Sciences (CAS).
>> 508
>> 509 config MACH_PISTACHIO
>> 510 bool "IMG Pistachio SoC based boards"
>> 511 select BOOT_ELF32
>> 512 select BOOT_RAW
>> 513 select CEVT_R4K
>> 514 select CLKSRC_MIPS_GIC
>> 515 select COMMON_CLK
>> 516 select CSRC_R4K
>> 517 select DMA_NONCOHERENT
>> 518 select GPIOLIB
>> 519 select IRQ_MIPS_CPU
>> 520 select MFD_SYSCON
>> 521 select MIPS_CPU_SCACHE
>> 522 select MIPS_GIC
>> 523 select PINCTRL
>> 524 select REGULATOR
>> 525 select SYS_HAS_CPU_MIPS32_R2
>> 526 select SYS_SUPPORTS_32BIT_KERNEL
>> 527 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 528 select SYS_SUPPORTS_MIPS_CPS
>> 529 select SYS_SUPPORTS_MULTITHREADING
>> 530 select SYS_SUPPORTS_RELOCATABLE
>> 531 select SYS_SUPPORTS_ZBOOT
>> 532 select SYS_HAS_EARLY_PRINTK
>> 533 select USE_GENERIC_EARLY_PRINTK_8250
>> 534 select USE_OF
>> 535 help
>> 536 This enables support for the IMG Pistachio SoC platform.
>> 537
>> 538 config MIPS_MALTA
>> 539 bool "MIPS Malta board"
>> 540 select ARCH_MAY_HAVE_PC_FDC
>> 541 select ARCH_MIGHT_HAVE_PC_PARPORT
>> 542 select ARCH_MIGHT_HAVE_PC_SERIO
>> 543 select BOOT_ELF32
>> 544 select BOOT_RAW
>> 545 select BUILTIN_DTB
>> 546 select CEVT_R4K
>> 547 select CLKSRC_MIPS_GIC
>> 548 select COMMON_CLK
>> 549 select CSRC_R4K
>> 550 select DMA_MAYBE_COHERENT
>> 551 select GENERIC_ISA_DMA
>> 552 select HAVE_PCSPKR_PLATFORM
>> 553 select HAVE_PCI
>> 554 select I8253
>> 555 select I8259
>> 556 select IRQ_MIPS_CPU
>> 557 select MIPS_BONITO64
>> 558 select MIPS_CPU_SCACHE
>> 559 select MIPS_GIC
>> 560 select MIPS_L1_CACHE_SHIFT_6
>> 561 select MIPS_MSC
>> 562 select PCI_GT64XXX_PCI0
>> 563 select SMP_UP if SMP
>> 564 select SWAP_IO_SPACE
>> 565 select SYS_HAS_CPU_MIPS32_R1
>> 566 select SYS_HAS_CPU_MIPS32_R2
>> 567 select SYS_HAS_CPU_MIPS32_R3_5
>> 568 select SYS_HAS_CPU_MIPS32_R5
>> 569 select SYS_HAS_CPU_MIPS32_R6
>> 570 select SYS_HAS_CPU_MIPS64_R1
>> 571 select SYS_HAS_CPU_MIPS64_R2
>> 572 select SYS_HAS_CPU_MIPS64_R6
>> 573 select SYS_HAS_CPU_NEVADA
>> 574 select SYS_HAS_CPU_RM7000
>> 575 select SYS_SUPPORTS_32BIT_KERNEL
>> 576 select SYS_SUPPORTS_64BIT_KERNEL
>> 577 select SYS_SUPPORTS_BIG_ENDIAN
>> 578 select SYS_SUPPORTS_HIGHMEM
>> 579 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 580 select SYS_SUPPORTS_MICROMIPS
>> 581 select SYS_SUPPORTS_MIPS16
>> 582 select SYS_SUPPORTS_MIPS_CMP
>> 583 select SYS_SUPPORTS_MIPS_CPS
>> 584 select SYS_SUPPORTS_MULTITHREADING
>> 585 select SYS_SUPPORTS_RELOCATABLE
>> 586 select SYS_SUPPORTS_SMARTMIPS
>> 587 select SYS_SUPPORTS_VPE_LOADER
>> 588 select SYS_SUPPORTS_ZBOOT
>> 589 select USE_OF
>> 590 select WAR_ICACHE_REFILLS
>> 591 select ZONE_DMA32 if 64BIT
>> 592 help
>> 593 This enables support for the MIPS Technologies Malta evaluation
>> 594 board.
>> 595
>> 596 config MACH_PIC32
>> 597 bool "Microchip PIC32 Family"
>> 598 help
>> 599 This enables support for the Microchip PIC32 family of platforms.
>> 600
>> 601 Microchip PIC32 is a family of general-purpose 32 bit MIPS core
>> 602 microcontrollers.
>> 603
>> 604 config MACH_VR41XX
>> 605 bool "NEC VR4100 series based machines"
>> 606 select CEVT_R4K
>> 607 select CSRC_R4K
>> 608 select SYS_HAS_CPU_VR41XX
>> 609 select SYS_SUPPORTS_MIPS16
>> 610 select GPIOLIB
>> 611
>> 612 config RALINK
>> 613 bool "Ralink based machines"
>> 614 select CEVT_R4K
>> 615 select CSRC_R4K
>> 616 select BOOT_RAW
>> 617 select DMA_NONCOHERENT
>> 618 select IRQ_MIPS_CPU
>> 619 select USE_OF
>> 620 select SYS_HAS_CPU_MIPS32_R1
>> 621 select SYS_HAS_CPU_MIPS32_R2
>> 622 select SYS_SUPPORTS_32BIT_KERNEL
>> 623 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 624 select SYS_SUPPORTS_MIPS16
>> 625 select SYS_SUPPORTS_ZBOOT
>> 626 select SYS_HAS_EARLY_PRINTK
>> 627 select CLKDEV_LOOKUP
>> 628 select ARCH_HAS_RESET_CONTROLLER
>> 629 select RESET_CONTROLLER
>> 630
>> 631 config SGI_IP22
>> 632 bool "SGI IP22 (Indy/Indigo2)"
>> 633 select ARC_MEMORY
>> 634 select ARC_PROMLIB
>> 635 select FW_ARC
>> 636 select FW_ARC32
>> 637 select ARCH_MIGHT_HAVE_PC_SERIO
>> 638 select BOOT_ELF32
>> 639 select CEVT_R4K
>> 640 select CSRC_R4K
>> 641 select DEFAULT_SGI_PARTITION
>> 642 select DMA_NONCOHERENT
>> 643 select HAVE_EISA
>> 644 select I8253
>> 645 select I8259
>> 646 select IP22_CPU_SCACHE
>> 647 select IRQ_MIPS_CPU
>> 648 select GENERIC_ISA_DMA_SUPPORT_BROKEN
>> 649 select SGI_HAS_I8042
>> 650 select SGI_HAS_INDYDOG
>> 651 select SGI_HAS_HAL2
>> 652 select SGI_HAS_SEEQ
>> 653 select SGI_HAS_WD93
>> 654 select SGI_HAS_ZILOG
>> 655 select SWAP_IO_SPACE
>> 656 select SYS_HAS_CPU_R4X00
>> 657 select SYS_HAS_CPU_R5000
>> 658 select SYS_HAS_EARLY_PRINTK
>> 659 select SYS_SUPPORTS_32BIT_KERNEL
>> 660 select SYS_SUPPORTS_64BIT_KERNEL
>> 661 select SYS_SUPPORTS_BIG_ENDIAN
>> 662 select WAR_R4600_V1_INDEX_ICACHEOP
>> 663 select WAR_R4600_V1_HIT_CACHEOP
>> 664 select WAR_R4600_V2_HIT_CACHEOP
>> 665 select MIPS_L1_CACHE_SHIFT_7
>> 666 help
>> 667 This are the SGI Indy, Challenge S and Indigo2, as well as certain
>> 668 OEM variants like the Tandem CMN B006S. To compile a Linux kernel
>> 669 that runs on these, say Y here.
>> 670
>> 671 config SGI_IP27
>> 672 bool "SGI IP27 (Origin200/2000)"
>> 673 select ARCH_HAS_PHYS_TO_DMA
>> 674 select ARCH_SPARSEMEM_ENABLE
>> 675 select FW_ARC
>> 676 select FW_ARC64
>> 677 select ARC_CMDLINE_ONLY
>> 678 select BOOT_ELF64
>> 679 select DEFAULT_SGI_PARTITION
>> 680 select SYS_HAS_EARLY_PRINTK
>> 681 select HAVE_PCI
>> 682 select IRQ_MIPS_CPU
>> 683 select IRQ_DOMAIN_HIERARCHY
>> 684 select NR_CPUS_DEFAULT_64
>> 685 select PCI_DRIVERS_GENERIC
>> 686 select PCI_XTALK_BRIDGE
>> 687 select SYS_HAS_CPU_R10000
>> 688 select SYS_SUPPORTS_64BIT_KERNEL
>> 689 select SYS_SUPPORTS_BIG_ENDIAN
>> 690 select SYS_SUPPORTS_NUMA
>> 691 select SYS_SUPPORTS_SMP
>> 692 select WAR_R10000_LLSC
>> 693 select MIPS_L1_CACHE_SHIFT_7
>> 694 select NUMA
>> 695 help
>> 696 This are the SGI Origin 200, Origin 2000 and Onyx 2 Graphics
>> 697 workstations. To compile a Linux kernel that runs on these, say Y
>> 698 here.
>> 699
>> 700 config SGI_IP28
>> 701 bool "SGI IP28 (Indigo2 R10k)"
>> 702 select ARC_MEMORY
>> 703 select ARC_PROMLIB
>> 704 select FW_ARC
>> 705 select FW_ARC64
>> 706 select ARCH_MIGHT_HAVE_PC_SERIO
>> 707 select BOOT_ELF64
>> 708 select CEVT_R4K
>> 709 select CSRC_R4K
>> 710 select DEFAULT_SGI_PARTITION
>> 711 select DMA_NONCOHERENT
>> 712 select GENERIC_ISA_DMA_SUPPORT_BROKEN
>> 713 select IRQ_MIPS_CPU
>> 714 select HAVE_EISA
>> 715 select I8253
>> 716 select I8259
>> 717 select SGI_HAS_I8042
>> 718 select SGI_HAS_INDYDOG
>> 719 select SGI_HAS_HAL2
>> 720 select SGI_HAS_SEEQ
>> 721 select SGI_HAS_WD93
>> 722 select SGI_HAS_ZILOG
>> 723 select SWAP_IO_SPACE
>> 724 select SYS_HAS_CPU_R10000
>> 725 select SYS_HAS_EARLY_PRINTK
>> 726 select SYS_SUPPORTS_64BIT_KERNEL
>> 727 select SYS_SUPPORTS_BIG_ENDIAN
>> 728 select WAR_R10000_LLSC
>> 729 select MIPS_L1_CACHE_SHIFT_7
>> 730 help
>> 731 This is the SGI Indigo2 with R10000 processor. To compile a Linux
>> 732 kernel that runs on these, say Y here.
>> 733
>> 734 config SGI_IP30
>> 735 bool "SGI IP30 (Octane/Octane2)"
>> 736 select ARCH_HAS_PHYS_TO_DMA
>> 737 select FW_ARC
>> 738 select FW_ARC64
>> 739 select BOOT_ELF64
>> 740 select CEVT_R4K
>> 741 select CSRC_R4K
>> 742 select SYNC_R4K if SMP
>> 743 select ZONE_DMA32
>> 744 select HAVE_PCI
>> 745 select IRQ_MIPS_CPU
>> 746 select IRQ_DOMAIN_HIERARCHY
>> 747 select NR_CPUS_DEFAULT_2
>> 748 select PCI_DRIVERS_GENERIC
>> 749 select PCI_XTALK_BRIDGE
>> 750 select SYS_HAS_EARLY_PRINTK
>> 751 select SYS_HAS_CPU_R10000
>> 752 select SYS_SUPPORTS_64BIT_KERNEL
>> 753 select SYS_SUPPORTS_BIG_ENDIAN
>> 754 select SYS_SUPPORTS_SMP
>> 755 select WAR_R10000_LLSC
>> 756 select MIPS_L1_CACHE_SHIFT_7
>> 757 select ARC_MEMORY
>> 758 help
>> 759 These are the SGI Octane and Octane2 graphics workstations. To
>> 760 compile a Linux kernel that runs on these, say Y here.
>> 761
>> 762 config SGI_IP32
>> 763 bool "SGI IP32 (O2)"
>> 764 select ARC_MEMORY
>> 765 select ARC_PROMLIB
>> 766 select ARCH_HAS_PHYS_TO_DMA
>> 767 select FW_ARC
>> 768 select FW_ARC32
>> 769 select BOOT_ELF32
>> 770 select CEVT_R4K
>> 771 select CSRC_R4K
>> 772 select DMA_NONCOHERENT
>> 773 select HAVE_PCI
>> 774 select IRQ_MIPS_CPU
>> 775 select R5000_CPU_SCACHE
>> 776 select RM7000_CPU_SCACHE
>> 777 select SYS_HAS_CPU_R5000
>> 778 select SYS_HAS_CPU_R10000 if BROKEN
>> 779 select SYS_HAS_CPU_RM7000
>> 780 select SYS_HAS_CPU_NEVADA
>> 781 select SYS_SUPPORTS_64BIT_KERNEL
>> 782 select SYS_SUPPORTS_BIG_ENDIAN
>> 783 select WAR_ICACHE_REFILLS
>> 784 help
>> 785 If you want this kernel to run on SGI O2 workstation, say Y here.
>> 786
>> 787 config SIBYTE_CRHINE
>> 788 bool "Sibyte BCM91120C-CRhine"
>> 789 select BOOT_ELF32
>> 790 select SIBYTE_BCM1120
>> 791 select SWAP_IO_SPACE
>> 792 select SYS_HAS_CPU_SB1
>> 793 select SYS_SUPPORTS_BIG_ENDIAN
>> 794 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 795
>> 796 config SIBYTE_CARMEL
>> 797 bool "Sibyte BCM91120x-Carmel"
>> 798 select BOOT_ELF32
>> 799 select SIBYTE_BCM1120
>> 800 select SWAP_IO_SPACE
>> 801 select SYS_HAS_CPU_SB1
>> 802 select SYS_SUPPORTS_BIG_ENDIAN
>> 803 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 804
>> 805 config SIBYTE_CRHONE
>> 806 bool "Sibyte BCM91125C-CRhone"
>> 807 select BOOT_ELF32
>> 808 select SIBYTE_BCM1125
>> 809 select SWAP_IO_SPACE
>> 810 select SYS_HAS_CPU_SB1
>> 811 select SYS_SUPPORTS_BIG_ENDIAN
>> 812 select SYS_SUPPORTS_HIGHMEM
>> 813 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 814
>> 815 config SIBYTE_RHONE
>> 816 bool "Sibyte BCM91125E-Rhone"
>> 817 select BOOT_ELF32
>> 818 select SIBYTE_BCM1125H
>> 819 select SWAP_IO_SPACE
>> 820 select SYS_HAS_CPU_SB1
>> 821 select SYS_SUPPORTS_BIG_ENDIAN
>> 822 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 823
>> 824 config SIBYTE_SWARM
>> 825 bool "Sibyte BCM91250A-SWARM"
>> 826 select BOOT_ELF32
>> 827 select HAVE_PATA_PLATFORM
>> 828 select SIBYTE_SB1250
>> 829 select SWAP_IO_SPACE
>> 830 select SYS_HAS_CPU_SB1
>> 831 select SYS_SUPPORTS_BIG_ENDIAN
>> 832 select SYS_SUPPORTS_HIGHMEM
>> 833 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 834 select ZONE_DMA32 if 64BIT
>> 835 select SWIOTLB if ARCH_DMA_ADDR_T_64BIT && PCI
>> 836
>> 837 config SIBYTE_LITTLESUR
>> 838 bool "Sibyte BCM91250C2-LittleSur"
>> 839 select BOOT_ELF32
>> 840 select HAVE_PATA_PLATFORM
>> 841 select SIBYTE_SB1250
>> 842 select SWAP_IO_SPACE
>> 843 select SYS_HAS_CPU_SB1
>> 844 select SYS_SUPPORTS_BIG_ENDIAN
>> 845 select SYS_SUPPORTS_HIGHMEM
>> 846 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 847 select ZONE_DMA32 if 64BIT
>> 848
>> 849 config SIBYTE_SENTOSA
>> 850 bool "Sibyte BCM91250E-Sentosa"
>> 851 select BOOT_ELF32
>> 852 select SIBYTE_SB1250
>> 853 select SWAP_IO_SPACE
>> 854 select SYS_HAS_CPU_SB1
>> 855 select SYS_SUPPORTS_BIG_ENDIAN
>> 856 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 857 select SWIOTLB if ARCH_DMA_ADDR_T_64BIT && PCI
>> 858
>> 859 config SIBYTE_BIGSUR
>> 860 bool "Sibyte BCM91480B-BigSur"
>> 861 select BOOT_ELF32
>> 862 select NR_CPUS_DEFAULT_4
>> 863 select SIBYTE_BCM1x80
>> 864 select SWAP_IO_SPACE
>> 865 select SYS_HAS_CPU_SB1
>> 866 select SYS_SUPPORTS_BIG_ENDIAN
>> 867 select SYS_SUPPORTS_HIGHMEM
>> 868 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 869 select ZONE_DMA32 if 64BIT
>> 870 select SWIOTLB if ARCH_DMA_ADDR_T_64BIT && PCI
>> 871
>> 872 config SNI_RM
>> 873 bool "SNI RM200/300/400"
>> 874 select ARC_MEMORY
>> 875 select ARC_PROMLIB
>> 876 select FW_ARC if CPU_LITTLE_ENDIAN
>> 877 select FW_ARC32 if CPU_LITTLE_ENDIAN
>> 878 select FW_SNIPROM if CPU_BIG_ENDIAN
>> 879 select ARCH_MAY_HAVE_PC_FDC
>> 880 select ARCH_MIGHT_HAVE_PC_PARPORT
>> 881 select ARCH_MIGHT_HAVE_PC_SERIO
>> 882 select BOOT_ELF32
>> 883 select CEVT_R4K
>> 884 select CSRC_R4K
>> 885 select DEFAULT_SGI_PARTITION if CPU_BIG_ENDIAN
>> 886 select DMA_NONCOHERENT
>> 887 select GENERIC_ISA_DMA
>> 888 select HAVE_EISA
>> 889 select HAVE_PCSPKR_PLATFORM
>> 890 select HAVE_PCI
>> 891 select IRQ_MIPS_CPU
>> 892 select I8253
>> 893 select I8259
>> 894 select ISA
>> 895 select MIPS_L1_CACHE_SHIFT_6
>> 896 select SWAP_IO_SPACE if CPU_BIG_ENDIAN
>> 897 select SYS_HAS_CPU_R4X00
>> 898 select SYS_HAS_CPU_R5000
>> 899 select SYS_HAS_CPU_R10000
>> 900 select R5000_CPU_SCACHE
>> 901 select SYS_HAS_EARLY_PRINTK
>> 902 select SYS_SUPPORTS_32BIT_KERNEL
>> 903 select SYS_SUPPORTS_64BIT_KERNEL
>> 904 select SYS_SUPPORTS_BIG_ENDIAN
>> 905 select SYS_SUPPORTS_HIGHMEM
>> 906 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 907 select WAR_R4600_V2_HIT_CACHEOP
>> 908 help
>> 909 The SNI RM200/300/400 are MIPS-based machines manufactured by
>> 910 Siemens Nixdorf Informationssysteme (SNI), parent company of Pyramid
>> 911 Technology and now in turn merged with Fujitsu. Say Y here to
>> 912 support this machine type.
>> 913
>> 914 config MACH_TX39XX
>> 915 bool "Toshiba TX39 series based machines"
>> 916
>> 917 config MACH_TX49XX
>> 918 bool "Toshiba TX49 series based machines"
>> 919 select WAR_TX49XX_ICACHE_INDEX_INV
>> 920
>> 921 config MIKROTIK_RB532
>> 922 bool "Mikrotik RB532 boards"
>> 923 select CEVT_R4K
>> 924 select CSRC_R4K
>> 925 select DMA_NONCOHERENT
>> 926 select HAVE_PCI
>> 927 select IRQ_MIPS_CPU
>> 928 select SYS_HAS_CPU_MIPS32_R1
>> 929 select SYS_SUPPORTS_32BIT_KERNEL
>> 930 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 931 select SWAP_IO_SPACE
>> 932 select BOOT_RAW
>> 933 select GPIOLIB
>> 934 select MIPS_L1_CACHE_SHIFT_4
>> 935 help
>> 936 Support the Mikrotik(tm) RouterBoard 532 series,
>> 937 based on the IDT RC32434 SoC.
>> 938
>> 939 config CAVIUM_OCTEON_SOC
>> 940 bool "Cavium Networks Octeon SoC based boards"
>> 941 select CEVT_R4K
>> 942 select ARCH_HAS_PHYS_TO_DMA
>> 943 select HAVE_RAPIDIO
>> 944 select PHYS_ADDR_T_64BIT
>> 945 select SYS_SUPPORTS_64BIT_KERNEL
>> 946 select SYS_SUPPORTS_BIG_ENDIAN
>> 947 select EDAC_SUPPORT
>> 948 select EDAC_ATOMIC_SCRUB
>> 949 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 950 select SYS_SUPPORTS_HOTPLUG_CPU if CPU_BIG_ENDIAN
>> 951 select SYS_HAS_EARLY_PRINTK
>> 952 select SYS_HAS_CPU_CAVIUM_OCTEON
>> 953 select HAVE_PCI
>> 954 select HAVE_PLAT_DELAY
>> 955 select HAVE_PLAT_FW_INIT_CMDLINE
>> 956 select HAVE_PLAT_MEMCPY
>> 957 select ZONE_DMA32
>> 958 select HOLES_IN_ZONE
>> 959 select GPIOLIB
>> 960 select USE_OF
>> 961 select ARCH_SPARSEMEM_ENABLE
>> 962 select SYS_SUPPORTS_SMP
>> 963 select NR_CPUS_DEFAULT_64
>> 964 select MIPS_NR_CPU_NR_MAP_1024
>> 965 select BUILTIN_DTB
>> 966 select MTD_COMPLEX_MAPPINGS
>> 967 select SWIOTLB
>> 968 select SYS_SUPPORTS_RELOCATABLE
>> 969 help
>> 970 This option supports all of the Octeon reference boards from Cavium
>> 971 Networks. It builds a kernel that dynamically determines the Octeon
>> 972 CPU type and supports all known board reference implementations.
>> 973 Some of the supported boards are:
>> 974 EBT3000
>> 975 EBH3000
>> 976 EBH3100
>> 977 Thunder
>> 978 Kodama
>> 979 Hikari
>> 980 Say Y here for most Octeon reference boards.
>> 981
>> 982 config NLM_XLR_BOARD
>> 983 bool "Netlogic XLR/XLS based systems"
>> 984 select BOOT_ELF32
>> 985 select NLM_COMMON
>> 986 select SYS_HAS_CPU_XLR
>> 987 select SYS_SUPPORTS_SMP
>> 988 select HAVE_PCI
>> 989 select SWAP_IO_SPACE
>> 990 select SYS_SUPPORTS_32BIT_KERNEL
>> 991 select SYS_SUPPORTS_64BIT_KERNEL
>> 992 select PHYS_ADDR_T_64BIT
>> 993 select SYS_SUPPORTS_BIG_ENDIAN
>> 994 select SYS_SUPPORTS_HIGHMEM
>> 995 select NR_CPUS_DEFAULT_32
>> 996 select CEVT_R4K
>> 997 select CSRC_R4K
>> 998 select IRQ_MIPS_CPU
>> 999 select ZONE_DMA32 if 64BIT
>> 1000 select SYNC_R4K
>> 1001 select SYS_HAS_EARLY_PRINTK
>> 1002 select SYS_SUPPORTS_ZBOOT
>> 1003 select SYS_SUPPORTS_ZBOOT_UART16550
>> 1004 help
>> 1005 Support for systems based on Netlogic XLR and XLS processors.
>> 1006 Say Y here if you have a XLR or XLS based board.
>> 1007
>> 1008 config NLM_XLP_BOARD
>> 1009 bool "Netlogic XLP based systems"
>> 1010 select BOOT_ELF32
>> 1011 select NLM_COMMON
>> 1012 select SYS_HAS_CPU_XLP
>> 1013 select SYS_SUPPORTS_SMP
>> 1014 select HAVE_PCI
>> 1015 select SYS_SUPPORTS_32BIT_KERNEL
>> 1016 select SYS_SUPPORTS_64BIT_KERNEL
>> 1017 select PHYS_ADDR_T_64BIT
>> 1018 select GPIOLIB
>> 1019 select SYS_SUPPORTS_BIG_ENDIAN
>> 1020 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 1021 select SYS_SUPPORTS_HIGHMEM
>> 1022 select NR_CPUS_DEFAULT_32
>> 1023 select CEVT_R4K
>> 1024 select CSRC_R4K
>> 1025 select IRQ_MIPS_CPU
>> 1026 select ZONE_DMA32 if 64BIT
>> 1027 select SYNC_R4K
>> 1028 select SYS_HAS_EARLY_PRINTK
>> 1029 select USE_OF
>> 1030 select SYS_SUPPORTS_ZBOOT
>> 1031 select SYS_SUPPORTS_ZBOOT_UART16550
>> 1032 help
>> 1033 This board is based on Netlogic XLP Processor.
>> 1034 Say Y here if you have a XLP based board.
336 1035
337 config ARCH_MMAP_RND_COMPAT_BITS_MAX !! 1036 endchoice
338 default 16 <<
339 1037
340 config NO_IOPORT_MAP !! 1038 source "arch/mips/alchemy/Kconfig"
341 def_bool y if !PCI !! 1039 source "arch/mips/ath25/Kconfig"
>> 1040 source "arch/mips/ath79/Kconfig"
>> 1041 source "arch/mips/bcm47xx/Kconfig"
>> 1042 source "arch/mips/bcm63xx/Kconfig"
>> 1043 source "arch/mips/bmips/Kconfig"
>> 1044 source "arch/mips/generic/Kconfig"
>> 1045 source "arch/mips/ingenic/Kconfig"
>> 1046 source "arch/mips/jazz/Kconfig"
>> 1047 source "arch/mips/lantiq/Kconfig"
>> 1048 source "arch/mips/pic32/Kconfig"
>> 1049 source "arch/mips/pistachio/Kconfig"
>> 1050 source "arch/mips/ralink/Kconfig"
>> 1051 source "arch/mips/sgi-ip27/Kconfig"
>> 1052 source "arch/mips/sibyte/Kconfig"
>> 1053 source "arch/mips/txx9/Kconfig"
>> 1054 source "arch/mips/vr41xx/Kconfig"
>> 1055 source "arch/mips/cavium-octeon/Kconfig"
>> 1056 source "arch/mips/loongson2ef/Kconfig"
>> 1057 source "arch/mips/loongson32/Kconfig"
>> 1058 source "arch/mips/loongson64/Kconfig"
>> 1059 source "arch/mips/netlogic/Kconfig"
342 1060
343 config STACKTRACE_SUPPORT !! 1061 endmenu
344 def_bool y <<
345 1062
346 config ILLEGAL_POINTER_VALUE !! 1063 config GENERIC_HWEIGHT
347 hex !! 1064 bool
348 default 0xdead000000000000 !! 1065 default y
349 1066
350 config LOCKDEP_SUPPORT !! 1067 config GENERIC_CALIBRATE_DELAY
351 def_bool y !! 1068 bool
>> 1069 default y
352 1070
353 config GENERIC_BUG !! 1071 config SCHED_OMIT_FRAME_POINTER
354 def_bool y !! 1072 bool
355 depends on BUG !! 1073 default y
356 1074
357 config GENERIC_BUG_RELATIVE_POINTERS !! 1075 #
358 def_bool y !! 1076 # Select some configuration options automatically based on user selections.
359 depends on GENERIC_BUG !! 1077 #
>> 1078 config FW_ARC
>> 1079 bool
360 1080
361 config GENERIC_HWEIGHT !! 1081 config ARCH_MAY_HAVE_PC_FDC
362 def_bool y !! 1082 bool
363 1083
364 config GENERIC_CSUM !! 1084 config BOOT_RAW
365 def_bool y !! 1085 bool
366 1086
367 config GENERIC_CALIBRATE_DELAY !! 1087 config CEVT_BCM1480
368 def_bool y !! 1088 bool
369 1089
370 config SMP !! 1090 config CEVT_DS1287
371 def_bool y !! 1091 bool
372 1092
373 config KERNEL_MODE_NEON !! 1093 config CEVT_GT641XX
374 def_bool y !! 1094 bool
375 1095
376 config FIX_EARLYCON_MEM !! 1096 config CEVT_R4K
377 def_bool y !! 1097 bool
378 1098
379 config PGTABLE_LEVELS !! 1099 config CEVT_SB1250
380 int !! 1100 bool
381 default 2 if ARM64_16K_PAGES && ARM64_ <<
382 default 2 if ARM64_64K_PAGES && ARM64_ <<
383 default 3 if ARM64_64K_PAGES && (ARM64 <<
384 default 3 if ARM64_4K_PAGES && ARM64_V <<
385 default 3 if ARM64_16K_PAGES && ARM64_ <<
386 default 4 if ARM64_16K_PAGES && (ARM64 <<
387 default 4 if !ARM64_64K_PAGES && ARM64 <<
388 default 5 if ARM64_4K_PAGES && ARM64_V <<
389 1101
390 config ARCH_SUPPORTS_UPROBES !! 1102 config CEVT_TXX9
391 def_bool y !! 1103 bool
392 1104
393 config ARCH_PROC_KCORE_TEXT !! 1105 config CSRC_BCM1480
394 def_bool y !! 1106 bool
395 1107
396 config BROKEN_GAS_INST !! 1108 config CSRC_IOASIC
397 def_bool !$(as-instr,1:\n.inst 0\n.rep !! 1109 bool
398 1110
399 config BUILTIN_RETURN_ADDRESS_STRIPS_PAC !! 1111 config CSRC_R4K
>> 1112 select CLOCKSOURCE_WATCHDOG if CPU_FREQ
400 bool 1113 bool
401 # Clang's __builtin_return_address() s <<
402 # https://github.com/llvm/llvm-project <<
403 default y if CC_IS_CLANG <<
404 # GCC's __builtin_return_address() str <<
405 # and this was backported to 10.2.0, 9 <<
406 # https://gcc.gnu.org/bugzilla/show_bu <<
407 default y if CC_IS_GCC && (GCC_VERSION <<
408 default y if CC_IS_GCC && (GCC_VERSION <<
409 default y if CC_IS_GCC && (GCC_VERSION <<
410 default y if CC_IS_GCC && (GCC_VERSION <<
411 default n <<
412 1114
413 config KASAN_SHADOW_OFFSET !! 1115 config CSRC_SB1250
414 hex !! 1116 bool
415 depends on KASAN_GENERIC || KASAN_SW_T <<
416 default 0xdfff800000000000 if (ARM64_V <<
417 default 0xdfffc00000000000 if (ARM64_V <<
418 default 0xdffffe0000000000 if ARM64_VA <<
419 default 0xdfffffc000000000 if ARM64_VA <<
420 default 0xdffffff800000000 if ARM64_VA <<
421 default 0xefff800000000000 if (ARM64_V <<
422 default 0xefffc00000000000 if (ARM64_V <<
423 default 0xeffffe0000000000 if ARM64_VA <<
424 default 0xefffffc000000000 if ARM64_VA <<
425 default 0xeffffff800000000 if ARM64_VA <<
426 default 0xffffffffffffffff <<
427 <<
428 config UNWIND_TABLES <<
429 bool <<
430 <<
431 source "arch/arm64/Kconfig.platforms" <<
432 <<
433 menu "Kernel Features" <<
434 <<
435 menu "ARM errata workarounds via the alternati <<
436 <<
437 config AMPERE_ERRATUM_AC03_CPU_38 <<
438 bool "AmpereOne: AC03_CPU_38: Certain <<
439 default y <<
440 help <<
441 This option adds an alternative code <<
442 errata AC03_CPU_38 and AC04_CPU_10 o <<
443 <<
444 The affected design reports FEAT_HAF <<
445 ID_AA64MMFR1_EL1.HAFDBS, but (V)TCR_ <<
446 as required by the architecture. The <<
447 implementation suffers from an addit <<
448 A/D updates can occur after a PTE ha <<
449 <<
450 The workaround forces KVM to explici <<
451 which avoids enabling unadvertised h <<
452 at stage-2. <<
453 1117
454 If unsure, say Y. !! 1118 config MIPS_CLOCK_VSYSCALL
>> 1119 def_bool CSRC_R4K || CLKSRC_MIPS_GIC
455 1120
456 config ARM64_WORKAROUND_CLEAN_CACHE !! 1121 config GPIO_TXX9
>> 1122 select GPIOLIB
457 bool 1123 bool
458 1124
459 config ARM64_ERRATUM_826319 !! 1125 config FW_CFE
460 bool "Cortex-A53: 826319: System might !! 1126 bool
461 default y <<
462 select ARM64_WORKAROUND_CLEAN_CACHE <<
463 help <<
464 This option adds an alternative code <<
465 erratum 826319 on Cortex-A53 parts u <<
466 AXI master interface and an L2 cache <<
467 <<
468 If a Cortex-A53 uses an AMBA AXI4 AC <<
469 and is unable to accept a certain wr <<
470 not progress on read data presented <<
471 system can deadlock. <<
472 1127
473 The workaround promotes data cache c !! 1128 config ARCH_SUPPORTS_UPROBES
474 data cache clean-and-invalidate. !! 1129 bool
475 Please note that this does not neces <<
476 as it depends on the alternative fra <<
477 the kernel if an affected CPU is det <<
478 1130
479 If unsure, say Y. !! 1131 config DMA_MAYBE_COHERENT
>> 1132 select ARCH_HAS_DMA_COHERENCE_H
>> 1133 select DMA_NONCOHERENT
>> 1134 bool
480 1135
481 config ARM64_ERRATUM_827319 !! 1136 config DMA_PERDEV_COHERENT
482 bool "Cortex-A53: 827319: Data cache c !! 1137 bool
483 default y !! 1138 select ARCH_HAS_SETUP_DMA_OPS
484 select ARM64_WORKAROUND_CLEAN_CACHE !! 1139 select DMA_NONCOHERENT
485 help <<
486 This option adds an alternative code <<
487 erratum 827319 on Cortex-A53 parts u <<
488 master interface and an L2 cache. <<
489 <<
490 Under certain conditions this erratu <<
491 to occur at the same time as another <<
492 on the AMBA 5 CHI interface, which c <<
493 interconnect reorders the two transa <<
494 <<
495 The workaround promotes data cache c <<
496 data cache clean-and-invalidate. <<
497 Please note that this does not neces <<
498 as it depends on the alternative fra <<
499 the kernel if an affected CPU is det <<
500 1140
501 If unsure, say Y. !! 1141 config DMA_NONCOHERENT
>> 1142 bool
>> 1143 #
>> 1144 # MIPS allows mixing "slightly different" Cacheability and Coherency
>> 1145 # Attribute bits. It is believed that the uncached access through
>> 1146 # KSEG1 and the implementation specific "uncached accelerated" used
>> 1147 # by pgprot_writcombine can be mixed, and the latter sometimes provides
>> 1148 # significant advantages.
>> 1149 #
>> 1150 select ARCH_HAS_DMA_WRITE_COMBINE
>> 1151 select ARCH_HAS_DMA_PREP_COHERENT
>> 1152 select ARCH_HAS_SYNC_DMA_FOR_DEVICE
>> 1153 select ARCH_HAS_DMA_SET_UNCACHED
>> 1154 select DMA_NONCOHERENT_MMAP
>> 1155 select NEED_DMA_MAP_STATE
502 1156
503 config ARM64_ERRATUM_824069 !! 1157 config SYS_HAS_EARLY_PRINTK
504 bool "Cortex-A53: 824069: Cache line m !! 1158 bool
505 default y <<
506 select ARM64_WORKAROUND_CLEAN_CACHE <<
507 help <<
508 This option adds an alternative code <<
509 erratum 824069 on Cortex-A53 parts u <<
510 to a coherent interconnect. <<
511 <<
512 If a Cortex-A53 processor is executi <<
513 write instruction at the same time a <<
514 cluster is executing a cache mainten <<
515 address, then this erratum might cau <<
516 incorrectly marked as dirty. <<
517 <<
518 The workaround promotes data cache c <<
519 data cache clean-and-invalidate. <<
520 Please note that this option does no <<
521 workaround, as it depends on the alt <<
522 only patch the kernel if an affected <<
523 1159
524 If unsure, say Y. !! 1160 config SYS_SUPPORTS_HOTPLUG_CPU
>> 1161 bool
525 1162
526 config ARM64_ERRATUM_819472 !! 1163 config MIPS_BONITO64
527 bool "Cortex-A53: 819472: Store exclus !! 1164 bool
528 default y <<
529 select ARM64_WORKAROUND_CLEAN_CACHE <<
530 help <<
531 This option adds an alternative code <<
532 erratum 819472 on Cortex-A53 parts u <<
533 present when it is connected to a co <<
534 <<
535 If the processor is executing a load <<
536 the same time as a processor in anot <<
537 maintenance operation to the same ad <<
538 cause data corruption. <<
539 <<
540 The workaround promotes data cache c <<
541 data cache clean-and-invalidate. <<
542 Please note that this does not neces <<
543 as it depends on the alternative fra <<
544 the kernel if an affected CPU is det <<
545 1165
546 If unsure, say Y. !! 1166 config MIPS_MSC
>> 1167 bool
547 1168
548 config ARM64_ERRATUM_832075 !! 1169 config SYNC_R4K
549 bool "Cortex-A57: 832075: possible dea !! 1170 bool
550 default y <<
551 help <<
552 This option adds an alternative code <<
553 erratum 832075 on Cortex-A57 parts u <<
554 1171
555 Affected Cortex-A57 parts might dead !! 1172 config NO_IOPORT_MAP
556 instructions to Write-Back memory ar !! 1173 def_bool n
557 1174
558 The workaround is to promote device !! 1175 config GENERIC_CSUM
559 semantics. !! 1176 def_bool CPU_NO_LOAD_STORE_LR
560 Please note that this does not neces <<
561 as it depends on the alternative fra <<
562 the kernel if an affected CPU is det <<
563 1177
564 If unsure, say Y. !! 1178 config GENERIC_ISA_DMA
>> 1179 bool
>> 1180 select ZONE_DMA if GENERIC_ISA_DMA_SUPPORT_BROKEN=n
>> 1181 select ISA_DMA_API
565 1182
566 config ARM64_ERRATUM_834220 !! 1183 config GENERIC_ISA_DMA_SUPPORT_BROKEN
567 bool "Cortex-A57: 834220: Stage 2 tran !! 1184 bool
568 depends on KVM !! 1185 select GENERIC_ISA_DMA
569 help <<
570 This option adds an alternative code <<
571 erratum 834220 on Cortex-A57 parts u <<
572 <<
573 Affected Cortex-A57 parts might repo <<
574 fault as the result of a Stage 1 fau <<
575 page boundary when there is a permis <<
576 alignment fault at Stage 1 and a tra <<
577 <<
578 The workaround is to verify that the <<
579 doesn't generate a fault before hand <<
580 Please note that this does not neces <<
581 as it depends on the alternative fra <<
582 the kernel if an affected CPU is det <<
583 1186
584 If unsure, say N. !! 1187 config HAVE_PLAT_DELAY
>> 1188 bool
585 1189
586 config ARM64_ERRATUM_1742098 !! 1190 config HAVE_PLAT_FW_INIT_CMDLINE
587 bool "Cortex-A57/A72: 1742098: ELR rec !! 1191 bool
588 depends on COMPAT <<
589 default y <<
590 help <<
591 This option removes the AES hwcap fo <<
592 workaround erratum 1742098 on Cortex <<
593 <<
594 Affected parts may corrupt the AES s <<
595 taken between a pair of AES instruct <<
596 are only present if the cryptography <<
597 All software should have a fallback <<
598 that don't implement the cryptograph <<
599 1192
600 If unsure, say Y. !! 1193 config HAVE_PLAT_MEMCPY
>> 1194 bool
601 1195
602 config ARM64_ERRATUM_845719 !! 1196 config ISA_DMA_API
603 bool "Cortex-A53: 845719: a load might !! 1197 bool
604 depends on COMPAT <<
605 default y <<
606 help <<
607 This option adds an alternative code <<
608 erratum 845719 on Cortex-A53 parts u <<
609 <<
610 When running a compat (AArch32) user <<
611 part, a load at EL0 from a virtual a <<
612 bits of the virtual address used by <<
613 might return incorrect data. <<
614 <<
615 The workaround is to write the conte <<
616 return to a 32-bit task. <<
617 Please note that this does not neces <<
618 as it depends on the alternative fra <<
619 the kernel if an affected CPU is det <<
620 1198
621 If unsure, say Y. !! 1199 config HOLES_IN_ZONE
>> 1200 bool
622 1201
623 config ARM64_ERRATUM_843419 !! 1202 config SYS_SUPPORTS_RELOCATABLE
624 bool "Cortex-A53: 843419: A load or st !! 1203 bool
625 default y <<
626 help 1204 help
627 This option links the kernel with '- !! 1205 Selected if the platform supports relocating the kernel.
628 enables PLT support to replace certa !! 1206 The platform must provide plat_get_fdt() if it selects CONFIG_USE_OF
629 cause subsequent memory accesses to !! 1207 to allow access to command line and entropy sources.
630 Cortex-A53 parts up to r0p4. <<
631 1208
632 If unsure, say Y. !! 1209 config MIPS_CBPF_JIT
>> 1210 def_bool y
>> 1211 depends on BPF_JIT && HAVE_CBPF_JIT
633 1212
634 config ARM64_LD_HAS_FIX_ERRATUM_843419 !! 1213 config MIPS_EBPF_JIT
635 def_bool $(ld-option,--fix-cortex-a53- !! 1214 def_bool y
>> 1215 depends on BPF_JIT && HAVE_EBPF_JIT
636 1216
637 config ARM64_ERRATUM_1024718 !! 1217
638 bool "Cortex-A55: 1024718: Update of D !! 1218 #
639 default y !! 1219 # Endianness selection. Sufficiently obscure so many users don't know what to
>> 1220 # answer,so we try hard to limit the available choices. Also the use of a
>> 1221 # choice statement should be more obvious to the user.
>> 1222 #
>> 1223 choice
>> 1224 prompt "Endianness selection"
640 help 1225 help
641 This option adds a workaround for AR !! 1226 Some MIPS machines can be configured for either little or big endian
>> 1227 byte order. These modes require different kernels and a different
>> 1228 Linux distribution. In general there is one preferred byteorder for a
>> 1229 particular system but some systems are just as commonly used in the
>> 1230 one or the other endianness.
642 1231
643 Affected Cortex-A55 cores (all revis !! 1232 config CPU_BIG_ENDIAN
644 update of the hardware dirty bit whe !! 1233 bool "Big endian"
645 without a break-before-make. The wor !! 1234 depends on SYS_SUPPORTS_BIG_ENDIAN
646 of hardware DBM locally on the affec <<
647 this erratum will continue to use th <<
648 1235
649 If unsure, say Y. !! 1236 config CPU_LITTLE_ENDIAN
>> 1237 bool "Little endian"
>> 1238 depends on SYS_SUPPORTS_LITTLE_ENDIAN
650 1239
651 config ARM64_ERRATUM_1418040 !! 1240 endchoice
652 bool "Cortex-A76/Neoverse-N1: MRC read <<
653 default y <<
654 depends on COMPAT <<
655 help <<
656 This option adds a workaround for AR <<
657 errata 1188873 and 1418040. <<
658 1241
659 Affected Cortex-A76/Neoverse-N1 core !! 1242 config EXPORT_UASM
660 cause register corruption when acces !! 1243 bool
661 from AArch32 userspace. <<
662 1244
663 If unsure, say Y. !! 1245 config SYS_SUPPORTS_APM_EMULATION
>> 1246 bool
664 1247
665 config ARM64_WORKAROUND_SPECULATIVE_AT !! 1248 config SYS_SUPPORTS_BIG_ENDIAN
666 bool 1249 bool
667 1250
668 config ARM64_ERRATUM_1165522 !! 1251 config SYS_SUPPORTS_LITTLE_ENDIAN
669 bool "Cortex-A76: 1165522: Speculative !! 1252 bool
>> 1253
>> 1254 config SYS_SUPPORTS_HUGETLBFS
>> 1255 bool
>> 1256 depends on CPU_SUPPORTS_HUGEPAGES
670 default y 1257 default y
671 select ARM64_WORKAROUND_SPECULATIVE_AT <<
672 help <<
673 This option adds a workaround for AR <<
674 1258
675 Affected Cortex-A76 cores (r0p0, r1p !! 1259 config MIPS_HUGE_TLB_SUPPORT
676 corrupted TLBs by speculating an AT !! 1260 def_bool HUGETLB_PAGE || TRANSPARENT_HUGEPAGE
677 context switch. <<
678 1261
679 If unsure, say Y. !! 1262 config IRQ_CPU_RM7K
>> 1263 bool
680 1264
681 config ARM64_ERRATUM_1319367 !! 1265 config IRQ_MSP_SLP
682 bool "Cortex-A57/A72: 1319537: Specula !! 1266 bool
683 default y <<
684 select ARM64_WORKAROUND_SPECULATIVE_AT <<
685 help <<
686 This option adds work arounds for AR <<
687 and A72 erratum 1319367 <<
688 1267
689 Cortex-A57 and A72 cores could end-u !! 1268 config IRQ_MSP_CIC
690 speculating an AT instruction during !! 1269 bool
691 1270
692 If unsure, say Y. !! 1271 config IRQ_TXX9
>> 1272 bool
693 1273
694 config ARM64_ERRATUM_1530923 !! 1274 config IRQ_GT641XX
695 bool "Cortex-A55: 1530923: Speculative !! 1275 bool
696 default y <<
697 select ARM64_WORKAROUND_SPECULATIVE_AT <<
698 help <<
699 This option adds a workaround for AR <<
700 1276
701 Affected Cortex-A55 cores (r0p0, r0p !! 1277 config PCI_GT64XXX_PCI0
702 corrupted TLBs by speculating an AT !! 1278 bool
703 context switch. <<
704 1279
705 If unsure, say Y. !! 1280 config PCI_XTALK_BRIDGE
>> 1281 bool
706 1282
707 config ARM64_WORKAROUND_REPEAT_TLBI !! 1283 config NO_EXCEPT_FILL
708 bool 1284 bool
709 1285
710 config ARM64_ERRATUM_2441007 !! 1286 config MIPS_SPRAM
711 bool "Cortex-A55: Completion of affect !! 1287 bool
712 select ARM64_WORKAROUND_REPEAT_TLBI <<
713 help <<
714 This option adds a workaround for AR <<
715 1288
716 Under very rare circumstances, affec !! 1289 config SWAP_IO_SPACE
717 may not handle a race between a brea !! 1290 bool
718 CPU, and another CPU accessing the s <<
719 store to a page that has been unmapp <<
720 1291
721 Work around this by adding the affec !! 1292 config SGI_HAS_INDYDOG
722 TLB sequences to be done twice. !! 1293 bool
723 1294
724 If unsure, say N. !! 1295 config SGI_HAS_HAL2
>> 1296 bool
725 1297
726 config ARM64_ERRATUM_1286807 !! 1298 config SGI_HAS_SEEQ
727 bool "Cortex-A76: Modification of the !! 1299 bool
728 select ARM64_WORKAROUND_REPEAT_TLBI <<
729 help <<
730 This option adds a workaround for AR <<
731 <<
732 On the affected Cortex-A76 cores (r0 <<
733 address for a cacheable mapping of a <<
734 accessed by a core while another cor <<
735 address to a new physical page using <<
736 break-before-make sequence, then und <<
737 TLBI+DSB completes before a read usi <<
738 invalidated has been observed by oth <<
739 workaround repeats the TLBI+DSB oper <<
740 1300
741 If unsure, say N. !! 1301 config SGI_HAS_WD93
>> 1302 bool
742 1303
743 config ARM64_ERRATUM_1463225 !! 1304 config SGI_HAS_ZILOG
744 bool "Cortex-A76: Software Step might !! 1305 bool
745 default y <<
746 help <<
747 This option adds a workaround for Ar <<
748 1306
749 On the affected Cortex-A76 cores (r0 !! 1307 config SGI_HAS_I8042
750 of a system call instruction (SVC) c !! 1308 bool
751 subsequent interrupts when software <<
752 exception handler of the system call <<
753 is enabled or VHE is in use. <<
754 1309
755 Work around the erratum by triggerin !! 1310 config DEFAULT_SGI_PARTITION
756 when handling a system call from a t !! 1311 bool
757 in a VHE configuration of the kernel <<
758 1312
759 If unsure, say Y. !! 1313 config FW_ARC32
>> 1314 bool
760 1315
761 config ARM64_ERRATUM_1542419 !! 1316 config FW_SNIPROM
762 bool "Neoverse-N1: workaround mis-orde !! 1317 bool
763 help <<
764 This option adds a workaround for AR <<
765 1542419. <<
766 1318
767 Affected Neoverse-N1 cores could exe !! 1319 config BOOT_ELF32
768 modified by another CPU. The workaro !! 1320 bool
769 counterpart. <<
770 1321
771 Workaround the issue by hiding the D !! 1322 config MIPS_L1_CACHE_SHIFT_4
772 forces user-space to perform cache m !! 1323 bool
773 1324
774 If unsure, say N. !! 1325 config MIPS_L1_CACHE_SHIFT_5
>> 1326 bool
775 1327
776 config ARM64_ERRATUM_1508412 !! 1328 config MIPS_L1_CACHE_SHIFT_6
777 bool "Cortex-A77: 1508412: workaround !! 1329 bool
778 default y <<
779 help <<
780 This option adds a workaround for Ar <<
781 1330
782 Affected Cortex-A77 cores (r0p0, r1p !! 1331 config MIPS_L1_CACHE_SHIFT_7
783 of a store-exclusive or read of PAR_ !! 1332 bool
784 non-cacheable memory attributes. The <<
785 counterpart. <<
786 1333
787 KVM guests must also have the workar !! 1334 config MIPS_L1_CACHE_SHIFT
788 deadlock the system. !! 1335 int
>> 1336 default "7" if MIPS_L1_CACHE_SHIFT_7
>> 1337 default "6" if MIPS_L1_CACHE_SHIFT_6
>> 1338 default "5" if MIPS_L1_CACHE_SHIFT_5
>> 1339 default "4" if MIPS_L1_CACHE_SHIFT_4
>> 1340 default "5"
789 1341
790 Work around the issue by inserting D !! 1342 config ARC_CMDLINE_ONLY
791 register reads and warning KVM users !! 1343 bool
792 to prevent a speculative PAR_EL1 rea <<
793 1344
794 If unsure, say Y. !! 1345 config ARC_CONSOLE
>> 1346 bool "ARC console support"
>> 1347 depends on SGI_IP22 || SGI_IP28 || (SNI_RM && CPU_LITTLE_ENDIAN)
795 1348
796 config ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MO !! 1349 config ARC_MEMORY
797 bool 1350 bool
798 1351
799 config ARM64_ERRATUM_2051678 !! 1352 config ARC_PROMLIB
800 bool "Cortex-A510: 2051678: disable Ha !! 1353 bool
801 default y <<
802 help <<
803 This options adds the workaround for <<
804 Affected Cortex-A510 might not respe <<
805 hardware update of the page table's <<
806 is to not enable the feature on affe <<
807 <<
808 If unsure, say Y. <<
809 1354
810 config ARM64_ERRATUM_2077057 !! 1355 config FW_ARC64
811 bool "Cortex-A510: 2077057: workaround !! 1356 bool
812 default y <<
813 help <<
814 This option adds the workaround for <<
815 Affected Cortex-A510 may corrupt SPS <<
816 expected, but a Pointer Authenticati <<
817 erratum causes SPSR_EL1 to be copied <<
818 EL1 to cause a return to EL2 with a <<
819 1357
820 This can only happen when EL2 is ste !! 1358 config BOOT_ELF64
>> 1359 bool
821 1360
822 When these conditions occur, the SPS !! 1361 menu "CPU selection"
823 previous guest entry, and can be res <<
824 1362
825 If unsure, say Y. !! 1363 choice
>> 1364 prompt "CPU type"
>> 1365 default CPU_R4X00
826 1366
827 config ARM64_ERRATUM_2658417 !! 1367 config CPU_LOONGSON64
828 bool "Cortex-A510: 2658417: remove BF1 !! 1368 bool "Loongson 64-bit CPU"
829 default y !! 1369 depends on SYS_HAS_CPU_LOONGSON64
>> 1370 select ARCH_HAS_PHYS_TO_DMA
>> 1371 select CPU_MIPSR2
>> 1372 select CPU_HAS_PREFETCH
>> 1373 select CPU_SUPPORTS_64BIT_KERNEL
>> 1374 select CPU_SUPPORTS_HIGHMEM
>> 1375 select CPU_SUPPORTS_HUGEPAGES
>> 1376 select CPU_SUPPORTS_MSA
>> 1377 select CPU_DIEI_BROKEN if !LOONGSON3_ENHANCEMENT
>> 1378 select CPU_MIPSR2_IRQ_VI
>> 1379 select WEAK_ORDERING
>> 1380 select WEAK_REORDERING_BEYOND_LLSC
>> 1381 select MIPS_ASID_BITS_VARIABLE
>> 1382 select MIPS_PGD_C0_CONTEXT
>> 1383 select MIPS_L1_CACHE_SHIFT_6
>> 1384 select GPIOLIB
>> 1385 select SWIOTLB
>> 1386 select HAVE_KVM
830 help 1387 help
831 This option adds the workaround for !! 1388 The Loongson GSx64(GS264/GS464/GS464E/GS464V) series of processor
832 Affected Cortex-A510 (r0p0 to r1p1) !! 1389 cores implements the MIPS64R2 instruction set with many extensions,
833 BFMMLA or VMMLA instructions in rare !! 1390 including most 64-bit Loongson-2 (2H, 2K) and Loongson-3 (3A1000,
834 A510 CPUs are using shared neon hard !! 1391 3B1000, 3B1500, 3A2000, 3A3000 and 3A4000) processors. However, old
835 discoverable by the kernel, hide the !! 1392 Loongson-2E/2F is not covered here and will be removed in future.
836 user-space should not be using these <<
837 <<
838 If unsure, say Y. <<
839 1393
840 config ARM64_ERRATUM_2119858 !! 1394 config LOONGSON3_ENHANCEMENT
841 bool "Cortex-A710/X2: 2119858: workaro !! 1395 bool "New Loongson-3 CPU Enhancements"
842 default y !! 1396 default n
843 depends on CORESIGHT_TRBE !! 1397 depends on CPU_LOONGSON64
844 select ARM64_WORKAROUND_TRBE_OVERWRITE !! 1398 help
>> 1399 New Loongson-3 cores (since Loongson-3A R2, as opposed to Loongson-3A
>> 1400 R1, Loongson-3B R1 and Loongson-3B R2) has many enhancements, such as
>> 1401 FTLB, L1-VCache, EI/DI/Wait/Prefetch instruction, DSP/DSPr2 ASE, User
>> 1402 Local register, Read-Inhibit/Execute-Inhibit, SFB (Store Fill Buffer),
>> 1403 Fast TLB refill support, etc.
>> 1404
>> 1405 This option enable those enhancements which are not probed at run
>> 1406 time. If you want a generic kernel to run on all Loongson 3 machines,
>> 1407 please say 'N' here. If you want a high-performance kernel to run on
>> 1408 new Loongson-3 machines only, please say 'Y' here.
>> 1409
>> 1410 config CPU_LOONGSON3_WORKAROUNDS
>> 1411 bool "Old Loongson-3 LLSC Workarounds"
>> 1412 default y if SMP
>> 1413 depends on CPU_LOONGSON64
>> 1414 help
>> 1415 Loongson-3 processors have the llsc issues which require workarounds.
>> 1416 Without workarounds the system may hang unexpectedly.
>> 1417
>> 1418 Newer Loongson-3 will fix these issues and no workarounds are needed.
>> 1419 The workarounds have no significant side effect on them but may
>> 1420 decrease the performance of the system so this option should be
>> 1421 disabled unless the kernel is intended to be run on old systems.
>> 1422
>> 1423 If unsure, please say Y.
>> 1424
>> 1425 config CPU_LOONGSON3_CPUCFG_EMULATION
>> 1426 bool "Emulate the CPUCFG instruction on older Loongson cores"
>> 1427 default y
>> 1428 depends on CPU_LOONGSON64
>> 1429 help
>> 1430 Loongson-3A R4 and newer have the CPUCFG instruction available for
>> 1431 userland to query CPU capabilities, much like CPUID on x86. This
>> 1432 option provides emulation of the instruction on older Loongson
>> 1433 cores, back to Loongson-3A1000.
>> 1434
>> 1435 If unsure, please say Y.
>> 1436
>> 1437 config CPU_LOONGSON2E
>> 1438 bool "Loongson 2E"
>> 1439 depends on SYS_HAS_CPU_LOONGSON2E
>> 1440 select CPU_LOONGSON2EF
>> 1441 help
>> 1442 The Loongson 2E processor implements the MIPS III instruction set
>> 1443 with many extensions.
>> 1444
>> 1445 It has an internal FPGA northbridge, which is compatible to
>> 1446 bonito64.
>> 1447
>> 1448 config CPU_LOONGSON2F
>> 1449 bool "Loongson 2F"
>> 1450 depends on SYS_HAS_CPU_LOONGSON2F
>> 1451 select CPU_LOONGSON2EF
>> 1452 select GPIOLIB
>> 1453 help
>> 1454 The Loongson 2F processor implements the MIPS III instruction set
>> 1455 with many extensions.
>> 1456
>> 1457 Loongson2F have built-in DDR2 and PCIX controller. The PCIX controller
>> 1458 have a similar programming interface with FPGA northbridge used in
>> 1459 Loongson2E.
>> 1460
>> 1461 config CPU_LOONGSON1B
>> 1462 bool "Loongson 1B"
>> 1463 depends on SYS_HAS_CPU_LOONGSON1B
>> 1464 select CPU_LOONGSON32
>> 1465 select LEDS_GPIO_REGISTER
>> 1466 help
>> 1467 The Loongson 1B is a 32-bit SoC, which implements the MIPS32
>> 1468 Release 1 instruction set and part of the MIPS32 Release 2
>> 1469 instruction set.
>> 1470
>> 1471 config CPU_LOONGSON1C
>> 1472 bool "Loongson 1C"
>> 1473 depends on SYS_HAS_CPU_LOONGSON1C
>> 1474 select CPU_LOONGSON32
>> 1475 select LEDS_GPIO_REGISTER
>> 1476 help
>> 1477 The Loongson 1C is a 32-bit SoC, which implements the MIPS32
>> 1478 Release 1 instruction set and part of the MIPS32 Release 2
>> 1479 instruction set.
>> 1480
>> 1481 config CPU_MIPS32_R1
>> 1482 bool "MIPS32 Release 1"
>> 1483 depends on SYS_HAS_CPU_MIPS32_R1
>> 1484 select CPU_HAS_PREFETCH
>> 1485 select CPU_SUPPORTS_32BIT_KERNEL
>> 1486 select CPU_SUPPORTS_HIGHMEM
>> 1487 help
>> 1488 Choose this option to build a kernel for release 1 or later of the
>> 1489 MIPS32 architecture. Most modern embedded systems with a 32-bit
>> 1490 MIPS processor are based on a MIPS32 processor. If you know the
>> 1491 specific type of processor in your system, choose those that one
>> 1492 otherwise CPU_MIPS32_R1 is a safe bet for any MIPS32 system.
>> 1493 Release 2 of the MIPS32 architecture is available since several
>> 1494 years so chances are you even have a MIPS32 Release 2 processor
>> 1495 in which case you should choose CPU_MIPS32_R2 instead for better
>> 1496 performance.
>> 1497
>> 1498 config CPU_MIPS32_R2
>> 1499 bool "MIPS32 Release 2"
>> 1500 depends on SYS_HAS_CPU_MIPS32_R2
>> 1501 select CPU_HAS_PREFETCH
>> 1502 select CPU_SUPPORTS_32BIT_KERNEL
>> 1503 select CPU_SUPPORTS_HIGHMEM
>> 1504 select CPU_SUPPORTS_MSA
>> 1505 select HAVE_KVM
>> 1506 help
>> 1507 Choose this option to build a kernel for release 2 or later of the
>> 1508 MIPS32 architecture. Most modern embedded systems with a 32-bit
>> 1509 MIPS processor are based on a MIPS32 processor. If you know the
>> 1510 specific type of processor in your system, choose those that one
>> 1511 otherwise CPU_MIPS32_R1 is a safe bet for any MIPS32 system.
>> 1512
>> 1513 config CPU_MIPS32_R5
>> 1514 bool "MIPS32 Release 5"
>> 1515 depends on SYS_HAS_CPU_MIPS32_R5
>> 1516 select CPU_HAS_PREFETCH
>> 1517 select CPU_SUPPORTS_32BIT_KERNEL
>> 1518 select CPU_SUPPORTS_HIGHMEM
>> 1519 select CPU_SUPPORTS_MSA
>> 1520 select HAVE_KVM
>> 1521 select MIPS_O32_FP64_SUPPORT
>> 1522 help
>> 1523 Choose this option to build a kernel for release 5 or later of the
>> 1524 MIPS32 architecture. New MIPS processors, starting with the Warrior
>> 1525 family, are based on a MIPS32r5 processor. If you own an older
>> 1526 processor, you probably need to select MIPS32r1 or MIPS32r2 instead.
>> 1527
>> 1528 config CPU_MIPS32_R6
>> 1529 bool "MIPS32 Release 6"
>> 1530 depends on SYS_HAS_CPU_MIPS32_R6
>> 1531 select CPU_HAS_PREFETCH
>> 1532 select CPU_NO_LOAD_STORE_LR
>> 1533 select CPU_SUPPORTS_32BIT_KERNEL
>> 1534 select CPU_SUPPORTS_HIGHMEM
>> 1535 select CPU_SUPPORTS_MSA
>> 1536 select HAVE_KVM
>> 1537 select MIPS_O32_FP64_SUPPORT
>> 1538 help
>> 1539 Choose this option to build a kernel for release 6 or later of the
>> 1540 MIPS32 architecture. New MIPS processors, starting with the Warrior
>> 1541 family, are based on a MIPS32r6 processor. If you own an older
>> 1542 processor, you probably need to select MIPS32r1 or MIPS32r2 instead.
>> 1543
>> 1544 config CPU_MIPS64_R1
>> 1545 bool "MIPS64 Release 1"
>> 1546 depends on SYS_HAS_CPU_MIPS64_R1
>> 1547 select CPU_HAS_PREFETCH
>> 1548 select CPU_SUPPORTS_32BIT_KERNEL
>> 1549 select CPU_SUPPORTS_64BIT_KERNEL
>> 1550 select CPU_SUPPORTS_HIGHMEM
>> 1551 select CPU_SUPPORTS_HUGEPAGES
>> 1552 help
>> 1553 Choose this option to build a kernel for release 1 or later of the
>> 1554 MIPS64 architecture. Many modern embedded systems with a 64-bit
>> 1555 MIPS processor are based on a MIPS64 processor. If you know the
>> 1556 specific type of processor in your system, choose those that one
>> 1557 otherwise CPU_MIPS64_R1 is a safe bet for any MIPS64 system.
>> 1558 Release 2 of the MIPS64 architecture is available since several
>> 1559 years so chances are you even have a MIPS64 Release 2 processor
>> 1560 in which case you should choose CPU_MIPS64_R2 instead for better
>> 1561 performance.
>> 1562
>> 1563 config CPU_MIPS64_R2
>> 1564 bool "MIPS64 Release 2"
>> 1565 depends on SYS_HAS_CPU_MIPS64_R2
>> 1566 select CPU_HAS_PREFETCH
>> 1567 select CPU_SUPPORTS_32BIT_KERNEL
>> 1568 select CPU_SUPPORTS_64BIT_KERNEL
>> 1569 select CPU_SUPPORTS_HIGHMEM
>> 1570 select CPU_SUPPORTS_HUGEPAGES
>> 1571 select CPU_SUPPORTS_MSA
>> 1572 select HAVE_KVM
>> 1573 help
>> 1574 Choose this option to build a kernel for release 2 or later of the
>> 1575 MIPS64 architecture. Many modern embedded systems with a 64-bit
>> 1576 MIPS processor are based on a MIPS64 processor. If you know the
>> 1577 specific type of processor in your system, choose those that one
>> 1578 otherwise CPU_MIPS64_R1 is a safe bet for any MIPS64 system.
>> 1579
>> 1580 config CPU_MIPS64_R5
>> 1581 bool "MIPS64 Release 5"
>> 1582 depends on SYS_HAS_CPU_MIPS64_R5
>> 1583 select CPU_HAS_PREFETCH
>> 1584 select CPU_SUPPORTS_32BIT_KERNEL
>> 1585 select CPU_SUPPORTS_64BIT_KERNEL
>> 1586 select CPU_SUPPORTS_HIGHMEM
>> 1587 select CPU_SUPPORTS_HUGEPAGES
>> 1588 select CPU_SUPPORTS_MSA
>> 1589 select MIPS_O32_FP64_SUPPORT if 32BIT || MIPS32_O32
>> 1590 select HAVE_KVM
>> 1591 help
>> 1592 Choose this option to build a kernel for release 5 or later of the
>> 1593 MIPS64 architecture. This is a intermediate MIPS architecture
>> 1594 release partly implementing release 6 features. Though there is no
>> 1595 any hardware known to be based on this release.
>> 1596
>> 1597 config CPU_MIPS64_R6
>> 1598 bool "MIPS64 Release 6"
>> 1599 depends on SYS_HAS_CPU_MIPS64_R6
>> 1600 select CPU_HAS_PREFETCH
>> 1601 select CPU_NO_LOAD_STORE_LR
>> 1602 select CPU_SUPPORTS_32BIT_KERNEL
>> 1603 select CPU_SUPPORTS_64BIT_KERNEL
>> 1604 select CPU_SUPPORTS_HIGHMEM
>> 1605 select CPU_SUPPORTS_HUGEPAGES
>> 1606 select CPU_SUPPORTS_MSA
>> 1607 select MIPS_O32_FP64_SUPPORT if 32BIT || MIPS32_O32
>> 1608 select HAVE_KVM
>> 1609 help
>> 1610 Choose this option to build a kernel for release 6 or later of the
>> 1611 MIPS64 architecture. New MIPS processors, starting with the Warrior
>> 1612 family, are based on a MIPS64r6 processor. If you own an older
>> 1613 processor, you probably need to select MIPS64r1 or MIPS64r2 instead.
>> 1614
>> 1615 config CPU_P5600
>> 1616 bool "MIPS Warrior P5600"
>> 1617 depends on SYS_HAS_CPU_P5600
>> 1618 select CPU_HAS_PREFETCH
>> 1619 select CPU_SUPPORTS_32BIT_KERNEL
>> 1620 select CPU_SUPPORTS_HIGHMEM
>> 1621 select CPU_SUPPORTS_MSA
>> 1622 select CPU_SUPPORTS_CPUFREQ
>> 1623 select CPU_MIPSR2_IRQ_VI
>> 1624 select CPU_MIPSR2_IRQ_EI
>> 1625 select HAVE_KVM
>> 1626 select MIPS_O32_FP64_SUPPORT
>> 1627 help
>> 1628 Choose this option to build a kernel for MIPS Warrior P5600 CPU.
>> 1629 It's based on MIPS32r5 ISA with XPA, EVA, dual/quad issue exec pipes,
>> 1630 MMU with two-levels TLB, UCA, MSA, MDU core level features and system
>> 1631 level features like up to six P5600 calculation cores, CM2 with L2
>> 1632 cache, IOCU/IOMMU (though might be unused depending on the system-
>> 1633 specific IP core configuration), GIC, CPC, virtualisation module,
>> 1634 eJTAG and PDtrace.
>> 1635
>> 1636 config CPU_R3000
>> 1637 bool "R3000"
>> 1638 depends on SYS_HAS_CPU_R3000
>> 1639 select CPU_HAS_WB
>> 1640 select CPU_R3K_TLB
>> 1641 select CPU_SUPPORTS_32BIT_KERNEL
>> 1642 select CPU_SUPPORTS_HIGHMEM
>> 1643 help
>> 1644 Please make sure to pick the right CPU type. Linux/MIPS is not
>> 1645 designed to be generic, i.e. Kernels compiled for R3000 CPUs will
>> 1646 *not* work on R4000 machines and vice versa. However, since most
>> 1647 of the supported machines have an R4000 (or similar) CPU, R4x00
>> 1648 might be a safe bet. If the resulting kernel does not work,
>> 1649 try to recompile with R3000.
>> 1650
>> 1651 config CPU_TX39XX
>> 1652 bool "R39XX"
>> 1653 depends on SYS_HAS_CPU_TX39XX
>> 1654 select CPU_SUPPORTS_32BIT_KERNEL
>> 1655 select CPU_R3K_TLB
>> 1656
>> 1657 config CPU_VR41XX
>> 1658 bool "R41xx"
>> 1659 depends on SYS_HAS_CPU_VR41XX
>> 1660 select CPU_SUPPORTS_32BIT_KERNEL
>> 1661 select CPU_SUPPORTS_64BIT_KERNEL
>> 1662 help
>> 1663 The options selects support for the NEC VR4100 series of processors.
>> 1664 Only choose this option if you have one of these processors as a
>> 1665 kernel built with this option will not run on any other type of
>> 1666 processor or vice versa.
>> 1667
>> 1668 config CPU_R4X00
>> 1669 bool "R4x00"
>> 1670 depends on SYS_HAS_CPU_R4X00
>> 1671 select CPU_SUPPORTS_32BIT_KERNEL
>> 1672 select CPU_SUPPORTS_64BIT_KERNEL
>> 1673 select CPU_SUPPORTS_HUGEPAGES
>> 1674 help
>> 1675 MIPS Technologies R4000-series processors other than 4300, including
>> 1676 the R4000, R4400, R4600, and 4700.
>> 1677
>> 1678 config CPU_TX49XX
>> 1679 bool "R49XX"
>> 1680 depends on SYS_HAS_CPU_TX49XX
>> 1681 select CPU_HAS_PREFETCH
>> 1682 select CPU_SUPPORTS_32BIT_KERNEL
>> 1683 select CPU_SUPPORTS_64BIT_KERNEL
>> 1684 select CPU_SUPPORTS_HUGEPAGES
>> 1685
>> 1686 config CPU_R5000
>> 1687 bool "R5000"
>> 1688 depends on SYS_HAS_CPU_R5000
>> 1689 select CPU_SUPPORTS_32BIT_KERNEL
>> 1690 select CPU_SUPPORTS_64BIT_KERNEL
>> 1691 select CPU_SUPPORTS_HUGEPAGES
>> 1692 help
>> 1693 MIPS Technologies R5000-series processors other than the Nevada.
>> 1694
>> 1695 config CPU_R5500
>> 1696 bool "R5500"
>> 1697 depends on SYS_HAS_CPU_R5500
>> 1698 select CPU_SUPPORTS_32BIT_KERNEL
>> 1699 select CPU_SUPPORTS_64BIT_KERNEL
>> 1700 select CPU_SUPPORTS_HUGEPAGES
>> 1701 help
>> 1702 NEC VR5500 and VR5500A series processors implement 64-bit MIPS IV
>> 1703 instruction set.
>> 1704
>> 1705 config CPU_NEVADA
>> 1706 bool "RM52xx"
>> 1707 depends on SYS_HAS_CPU_NEVADA
>> 1708 select CPU_SUPPORTS_32BIT_KERNEL
>> 1709 select CPU_SUPPORTS_64BIT_KERNEL
>> 1710 select CPU_SUPPORTS_HUGEPAGES
>> 1711 help
>> 1712 QED / PMC-Sierra RM52xx-series ("Nevada") processors.
>> 1713
>> 1714 config CPU_R10000
>> 1715 bool "R10000"
>> 1716 depends on SYS_HAS_CPU_R10000
>> 1717 select CPU_HAS_PREFETCH
>> 1718 select CPU_SUPPORTS_32BIT_KERNEL
>> 1719 select CPU_SUPPORTS_64BIT_KERNEL
>> 1720 select CPU_SUPPORTS_HIGHMEM
>> 1721 select CPU_SUPPORTS_HUGEPAGES
>> 1722 help
>> 1723 MIPS Technologies R10000-series processors.
>> 1724
>> 1725 config CPU_RM7000
>> 1726 bool "RM7000"
>> 1727 depends on SYS_HAS_CPU_RM7000
>> 1728 select CPU_HAS_PREFETCH
>> 1729 select CPU_SUPPORTS_32BIT_KERNEL
>> 1730 select CPU_SUPPORTS_64BIT_KERNEL
>> 1731 select CPU_SUPPORTS_HIGHMEM
>> 1732 select CPU_SUPPORTS_HUGEPAGES
>> 1733
>> 1734 config CPU_SB1
>> 1735 bool "SB1"
>> 1736 depends on SYS_HAS_CPU_SB1
>> 1737 select CPU_SUPPORTS_32BIT_KERNEL
>> 1738 select CPU_SUPPORTS_64BIT_KERNEL
>> 1739 select CPU_SUPPORTS_HIGHMEM
>> 1740 select CPU_SUPPORTS_HUGEPAGES
>> 1741 select WEAK_ORDERING
>> 1742
>> 1743 config CPU_CAVIUM_OCTEON
>> 1744 bool "Cavium Octeon processor"
>> 1745 depends on SYS_HAS_CPU_CAVIUM_OCTEON
>> 1746 select CPU_HAS_PREFETCH
>> 1747 select CPU_SUPPORTS_64BIT_KERNEL
>> 1748 select WEAK_ORDERING
>> 1749 select CPU_SUPPORTS_HIGHMEM
>> 1750 select CPU_SUPPORTS_HUGEPAGES
>> 1751 select USB_EHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 1752 select USB_OHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 1753 select MIPS_L1_CACHE_SHIFT_7
>> 1754 select HAVE_KVM
>> 1755 help
>> 1756 The Cavium Octeon processor is a highly integrated chip containing
>> 1757 many ethernet hardware widgets for networking tasks. The processor
>> 1758 can have up to 16 Mips64v2 cores and 8 integrated gigabit ethernets.
>> 1759 Full details can be found at http://www.caviumnetworks.com.
>> 1760
>> 1761 config CPU_BMIPS
>> 1762 bool "Broadcom BMIPS"
>> 1763 depends on SYS_HAS_CPU_BMIPS
>> 1764 select CPU_MIPS32
>> 1765 select CPU_BMIPS32_3300 if SYS_HAS_CPU_BMIPS32_3300
>> 1766 select CPU_BMIPS4350 if SYS_HAS_CPU_BMIPS4350
>> 1767 select CPU_BMIPS4380 if SYS_HAS_CPU_BMIPS4380
>> 1768 select CPU_BMIPS5000 if SYS_HAS_CPU_BMIPS5000
>> 1769 select CPU_SUPPORTS_32BIT_KERNEL
>> 1770 select DMA_NONCOHERENT
>> 1771 select IRQ_MIPS_CPU
>> 1772 select SWAP_IO_SPACE
>> 1773 select WEAK_ORDERING
>> 1774 select CPU_SUPPORTS_HIGHMEM
>> 1775 select CPU_HAS_PREFETCH
>> 1776 select CPU_SUPPORTS_CPUFREQ
>> 1777 select MIPS_EXTERNAL_TIMER
>> 1778 help
>> 1779 Support for BMIPS32/3300/4350/4380 and BMIPS5000 processors.
>> 1780
>> 1781 config CPU_XLR
>> 1782 bool "Netlogic XLR SoC"
>> 1783 depends on SYS_HAS_CPU_XLR
>> 1784 select CPU_SUPPORTS_32BIT_KERNEL
>> 1785 select CPU_SUPPORTS_64BIT_KERNEL
>> 1786 select CPU_SUPPORTS_HIGHMEM
>> 1787 select CPU_SUPPORTS_HUGEPAGES
>> 1788 select WEAK_ORDERING
>> 1789 select WEAK_REORDERING_BEYOND_LLSC
>> 1790 help
>> 1791 Netlogic Microsystems XLR/XLS processors.
>> 1792
>> 1793 config CPU_XLP
>> 1794 bool "Netlogic XLP SoC"
>> 1795 depends on SYS_HAS_CPU_XLP
>> 1796 select CPU_SUPPORTS_32BIT_KERNEL
>> 1797 select CPU_SUPPORTS_64BIT_KERNEL
>> 1798 select CPU_SUPPORTS_HIGHMEM
>> 1799 select WEAK_ORDERING
>> 1800 select WEAK_REORDERING_BEYOND_LLSC
>> 1801 select CPU_HAS_PREFETCH
>> 1802 select CPU_MIPSR2
>> 1803 select CPU_SUPPORTS_HUGEPAGES
>> 1804 select MIPS_ASID_BITS_VARIABLE
845 help 1805 help
846 This option adds the workaround for !! 1806 Netlogic Microsystems XLP processors.
>> 1807 endchoice
847 1808
848 Affected Cortex-A710/X2 cores could !! 1809 config CPU_MIPS32_3_5_FEATURES
849 data at the base of the buffer (poin !! 1810 bool "MIPS32 Release 3.5 Features"
850 the event of a WRAP event. !! 1811 depends on SYS_HAS_CPU_MIPS32_R3_5
>> 1812 depends on CPU_MIPS32_R2 || CPU_MIPS32_R5 || CPU_MIPS32_R6 || \
>> 1813 CPU_P5600
>> 1814 help
>> 1815 Choose this option to build a kernel for release 2 or later of the
>> 1816 MIPS32 architecture including features from the 3.5 release such as
>> 1817 support for Enhanced Virtual Addressing (EVA).
>> 1818
>> 1819 config CPU_MIPS32_3_5_EVA
>> 1820 bool "Enhanced Virtual Addressing (EVA)"
>> 1821 depends on CPU_MIPS32_3_5_FEATURES
>> 1822 select EVA
>> 1823 default y
>> 1824 help
>> 1825 Choose this option if you want to enable the Enhanced Virtual
>> 1826 Addressing (EVA) on your MIPS32 core (such as proAptiv).
>> 1827 One of its primary benefits is an increase in the maximum size
>> 1828 of lowmem (up to 3GB). If unsure, say 'N' here.
>> 1829
>> 1830 config CPU_MIPS32_R5_FEATURES
>> 1831 bool "MIPS32 Release 5 Features"
>> 1832 depends on SYS_HAS_CPU_MIPS32_R5
>> 1833 depends on CPU_MIPS32_R2 || CPU_MIPS32_R5 || CPU_P5600
>> 1834 help
>> 1835 Choose this option to build a kernel for release 2 or later of the
>> 1836 MIPS32 architecture including features from release 5 such as
>> 1837 support for Extended Physical Addressing (XPA).
>> 1838
>> 1839 config CPU_MIPS32_R5_XPA
>> 1840 bool "Extended Physical Addressing (XPA)"
>> 1841 depends on CPU_MIPS32_R5_FEATURES
>> 1842 depends on !EVA
>> 1843 depends on !PAGE_SIZE_4KB
>> 1844 depends on SYS_SUPPORTS_HIGHMEM
>> 1845 select XPA
>> 1846 select HIGHMEM
>> 1847 select PHYS_ADDR_T_64BIT
>> 1848 default n
>> 1849 help
>> 1850 Choose this option if you want to enable the Extended Physical
>> 1851 Addressing (XPA) on your MIPS32 core (such as P5600 series). The
>> 1852 benefit is to increase physical addressing equal to or greater
>> 1853 than 40 bits. Note that this has the side effect of turning on
>> 1854 64-bit addressing which in turn makes the PTEs 64-bit in size.
>> 1855 If unsure, say 'N' here.
851 1856
852 Work around the issue by always maki !! 1857 if CPU_LOONGSON2F
853 256 bytes before enabling the buffer !! 1858 config CPU_NOP_WORKAROUNDS
854 the buffer with ETM ignore packets u !! 1859 bool
855 1860
856 If unsure, say Y. !! 1861 config CPU_JUMP_WORKAROUNDS
>> 1862 bool
857 1863
858 config ARM64_ERRATUM_2139208 !! 1864 config CPU_LOONGSON2F_WORKAROUNDS
859 bool "Neoverse-N2: 2139208: workaround !! 1865 bool "Loongson 2F Workarounds"
860 default y 1866 default y
861 depends on CORESIGHT_TRBE !! 1867 select CPU_NOP_WORKAROUNDS
862 select ARM64_WORKAROUND_TRBE_OVERWRITE !! 1868 select CPU_JUMP_WORKAROUNDS
863 help 1869 help
864 This option adds the workaround for !! 1870 Loongson 2F01 / 2F02 processors have the NOP & JUMP issues which
>> 1871 require workarounds. Without workarounds the system may hang
>> 1872 unexpectedly. For more information please refer to the gas
>> 1873 -mfix-loongson2f-nop and -mfix-loongson2f-jump options.
>> 1874
>> 1875 Loongson 2F03 and later have fixed these issues and no workarounds
>> 1876 are needed. The workarounds have no significant side effect on them
>> 1877 but may decrease the performance of the system so this option should
>> 1878 be disabled unless the kernel is intended to be run on 2F01 or 2F02
>> 1879 systems.
865 1880
866 Affected Neoverse-N2 cores could ove !! 1881 If unsure, please say Y.
867 data at the base of the buffer (poin !! 1882 endif # CPU_LOONGSON2F
868 the event of a WRAP event. <<
869 1883
870 Work around the issue by always maki !! 1884 config SYS_SUPPORTS_ZBOOT
871 256 bytes before enabling the buffer !! 1885 bool
872 the buffer with ETM ignore packets u !! 1886 select HAVE_KERNEL_GZIP
>> 1887 select HAVE_KERNEL_BZIP2
>> 1888 select HAVE_KERNEL_LZ4
>> 1889 select HAVE_KERNEL_LZMA
>> 1890 select HAVE_KERNEL_LZO
>> 1891 select HAVE_KERNEL_XZ
>> 1892 select HAVE_KERNEL_ZSTD
873 1893
874 If unsure, say Y. !! 1894 config SYS_SUPPORTS_ZBOOT_UART16550
>> 1895 bool
>> 1896 select SYS_SUPPORTS_ZBOOT
875 1897
876 config ARM64_WORKAROUND_TSB_FLUSH_FAILURE !! 1898 config SYS_SUPPORTS_ZBOOT_UART_PROM
877 bool 1899 bool
>> 1900 select SYS_SUPPORTS_ZBOOT
878 1901
879 config ARM64_ERRATUM_2054223 !! 1902 config CPU_LOONGSON2EF
880 bool "Cortex-A710: 2054223: workaround !! 1903 bool
881 default y !! 1904 select CPU_SUPPORTS_32BIT_KERNEL
882 select ARM64_WORKAROUND_TSB_FLUSH_FAIL !! 1905 select CPU_SUPPORTS_64BIT_KERNEL
883 help !! 1906 select CPU_SUPPORTS_HIGHMEM
884 Enable workaround for ARM Cortex-A71 !! 1907 select CPU_SUPPORTS_HUGEPAGES
>> 1908 select ARCH_HAS_PHYS_TO_DMA
885 1909
886 Affected cores may fail to flush the !! 1910 config CPU_LOONGSON32
887 the PE is in trace prohibited state. !! 1911 bool
888 of the trace cached. !! 1912 select CPU_MIPS32
>> 1913 select CPU_MIPSR2
>> 1914 select CPU_HAS_PREFETCH
>> 1915 select CPU_SUPPORTS_32BIT_KERNEL
>> 1916 select CPU_SUPPORTS_HIGHMEM
>> 1917 select CPU_SUPPORTS_CPUFREQ
889 1918
890 Workaround is to issue two TSB conse !! 1919 config CPU_BMIPS32_3300
>> 1920 select SMP_UP if SMP
>> 1921 bool
891 1922
892 If unsure, say Y. !! 1923 config CPU_BMIPS4350
>> 1924 bool
>> 1925 select SYS_SUPPORTS_SMP
>> 1926 select SYS_SUPPORTS_HOTPLUG_CPU
893 1927
894 config ARM64_ERRATUM_2067961 !! 1928 config CPU_BMIPS4380
895 bool "Neoverse-N2: 2067961: workaround !! 1929 bool
896 default y !! 1930 select MIPS_L1_CACHE_SHIFT_6
897 select ARM64_WORKAROUND_TSB_FLUSH_FAIL !! 1931 select SYS_SUPPORTS_SMP
898 help !! 1932 select SYS_SUPPORTS_HOTPLUG_CPU
899 Enable workaround for ARM Neoverse-N !! 1933 select CPU_HAS_RIXI
900 1934
901 Affected cores may fail to flush the !! 1935 config CPU_BMIPS5000
902 the PE is in trace prohibited state. !! 1936 bool
903 of the trace cached. !! 1937 select MIPS_CPU_SCACHE
>> 1938 select MIPS_L1_CACHE_SHIFT_7
>> 1939 select SYS_SUPPORTS_SMP
>> 1940 select SYS_SUPPORTS_HOTPLUG_CPU
>> 1941 select CPU_HAS_RIXI
904 1942
905 Workaround is to issue two TSB conse !! 1943 config SYS_HAS_CPU_LOONGSON64
>> 1944 bool
>> 1945 select CPU_SUPPORTS_CPUFREQ
>> 1946 select CPU_HAS_RIXI
906 1947
907 If unsure, say Y. !! 1948 config SYS_HAS_CPU_LOONGSON2E
>> 1949 bool
908 1950
909 config ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANG !! 1951 config SYS_HAS_CPU_LOONGSON2F
910 bool 1952 bool
>> 1953 select CPU_SUPPORTS_CPUFREQ
>> 1954 select CPU_SUPPORTS_ADDRWINCFG if 64BIT
911 1955
912 config ARM64_ERRATUM_2253138 !! 1956 config SYS_HAS_CPU_LOONGSON1B
913 bool "Neoverse-N2: 2253138: workaround !! 1957 bool
914 depends on CORESIGHT_TRBE <<
915 default y <<
916 select ARM64_WORKAROUND_TRBE_WRITE_OUT <<
917 help <<
918 This option adds the workaround for <<
919 1958
920 Affected Neoverse-N2 cores might wri !! 1959 config SYS_HAS_CPU_LOONGSON1C
921 for TRBE. Under some conditions, the !! 1960 bool
922 virtually addressed page following t <<
923 (i.e., the TRBLIMITR_EL1.LIMIT), ins <<
924 1961
925 Work around this in the driver by al !! 1962 config SYS_HAS_CPU_MIPS32_R1
926 page beyond the TRBLIMITR_EL1.LIMIT, !! 1963 bool
927 1964
928 If unsure, say Y. !! 1965 config SYS_HAS_CPU_MIPS32_R2
>> 1966 bool
929 1967
930 config ARM64_ERRATUM_2224489 !! 1968 config SYS_HAS_CPU_MIPS32_R3_5
931 bool "Cortex-A710/X2: 2224489: workaro !! 1969 bool
932 depends on CORESIGHT_TRBE <<
933 default y <<
934 select ARM64_WORKAROUND_TRBE_WRITE_OUT <<
935 help <<
936 This option adds the workaround for <<
937 1970
938 Affected Cortex-A710/X2 cores might !! 1971 config SYS_HAS_CPU_MIPS32_R5
939 for TRBE. Under some conditions, the !! 1972 bool
940 virtually addressed page following t !! 1973 select ARCH_HAS_SYNC_DMA_FOR_CPU if DMA_NONCOHERENT
941 (i.e., the TRBLIMITR_EL1.LIMIT), ins <<
942 1974
943 Work around this in the driver by al !! 1975 config SYS_HAS_CPU_MIPS32_R6
944 page beyond the TRBLIMITR_EL1.LIMIT, !! 1976 bool
>> 1977 select ARCH_HAS_SYNC_DMA_FOR_CPU if DMA_NONCOHERENT
945 1978
946 If unsure, say Y. !! 1979 config SYS_HAS_CPU_MIPS64_R1
>> 1980 bool
947 1981
948 config ARM64_ERRATUM_2441009 !! 1982 config SYS_HAS_CPU_MIPS64_R2
949 bool "Cortex-A510: Completion of affec !! 1983 bool
950 select ARM64_WORKAROUND_REPEAT_TLBI <<
951 help <<
952 This option adds a workaround for AR <<
953 <<
954 Under very rare circumstances, affec <<
955 may not handle a race between a brea <<
956 CPU, and another CPU accessing the s <<
957 store to a page that has been unmapp <<
958 1984
959 Work around this by adding the affec !! 1985 config SYS_HAS_CPU_MIPS64_R6
960 TLB sequences to be done twice. !! 1986 bool
>> 1987 select ARCH_HAS_SYNC_DMA_FOR_CPU if DMA_NONCOHERENT
961 1988
962 If unsure, say N. !! 1989 config SYS_HAS_CPU_P5600
>> 1990 bool
>> 1991 select ARCH_HAS_SYNC_DMA_FOR_CPU if DMA_NONCOHERENT
963 1992
964 config ARM64_ERRATUM_2064142 !! 1993 config SYS_HAS_CPU_R3000
965 bool "Cortex-A510: 2064142: workaround !! 1994 bool
966 depends on CORESIGHT_TRBE <<
967 default y <<
968 help <<
969 This option adds the workaround for <<
970 1995
971 Affected Cortex-A510 core might fail !! 1996 config SYS_HAS_CPU_TX39XX
972 TRBE has been disabled. Under some c !! 1997 bool
973 writes into TRBE registers TRBLIMITR <<
974 and TRBTRG_EL1 will be ignored and w <<
975 1998
976 Work around this in the driver by ex !! 1999 config SYS_HAS_CPU_VR41XX
977 is stopped and before performing a s !! 2000 bool
978 registers. <<
979 2001
980 If unsure, say Y. !! 2002 config SYS_HAS_CPU_R4X00
>> 2003 bool
981 2004
982 config ARM64_ERRATUM_2038923 !! 2005 config SYS_HAS_CPU_TX49XX
983 bool "Cortex-A510: 2038923: workaround !! 2006 bool
984 depends on CORESIGHT_TRBE <<
985 default y <<
986 help <<
987 This option adds the workaround for <<
988 <<
989 Affected Cortex-A510 core might caus <<
990 prohibited within the CPU. As a resu <<
991 might be corrupted. This happens aft <<
992 TRBLIMITR_EL1.E, followed by just a <<
993 execution changes from a context, in <<
994 isn't, or vice versa. In these menti <<
995 is prohibited is inconsistent betwee <<
996 the trace buffer state might be corr <<
997 <<
998 Work around this in the driver by pr <<
999 trace is prohibited or not based on <<
1000 change to TRBLIMITR_EL1.E with at l <<
1001 two ISB instructions if no ERET is <<
1002 2007
1003 If unsure, say Y. !! 2008 config SYS_HAS_CPU_R5000
>> 2009 bool
1004 2010
1005 config ARM64_ERRATUM_1902691 !! 2011 config SYS_HAS_CPU_R5500
1006 bool "Cortex-A510: 1902691: workaroun !! 2012 bool
1007 depends on CORESIGHT_TRBE <<
1008 default y <<
1009 help <<
1010 This option adds the workaround for <<
1011 2013
1012 Affected Cortex-A510 core might cau !! 2014 config SYS_HAS_CPU_NEVADA
1013 into the memory. Effectively TRBE i !! 2015 bool
1014 trace data. <<
1015 2016
1016 Work around this problem in the dri !! 2017 config SYS_HAS_CPU_R10000
1017 affected cpus. The firmware must ha !! 2018 bool
1018 on such implementations. This will !! 2019 select ARCH_HAS_SYNC_DMA_FOR_CPU if DMA_NONCOHERENT
1019 do this already. <<
1020 2020
1021 If unsure, say Y. !! 2021 config SYS_HAS_CPU_RM7000
>> 2022 bool
1022 2023
1023 config ARM64_ERRATUM_2457168 !! 2024 config SYS_HAS_CPU_SB1
1024 bool "Cortex-A510: 2457168: workaroun !! 2025 bool
1025 depends on ARM64_AMU_EXTN <<
1026 default y <<
1027 help <<
1028 This option adds the workaround for <<
1029 2026
1030 The AMU counter AMEVCNTR01 (constan !! 2027 config SYS_HAS_CPU_CAVIUM_OCTEON
1031 as the system counter. On affected !! 2028 bool
1032 incorrectly giving a significantly <<
1033 2029
1034 Work around this problem by returni !! 2030 config SYS_HAS_CPU_BMIPS
1035 key locations that results in disab !! 2031 bool
1036 is the same to firmware disabling a <<
1037 2032
1038 If unsure, say Y. !! 2033 config SYS_HAS_CPU_BMIPS32_3300
>> 2034 bool
>> 2035 select SYS_HAS_CPU_BMIPS
1039 2036
1040 config ARM64_ERRATUM_2645198 !! 2037 config SYS_HAS_CPU_BMIPS4350
1041 bool "Cortex-A715: 2645198: Workaroun !! 2038 bool
1042 default y !! 2039 select SYS_HAS_CPU_BMIPS
1043 help <<
1044 This option adds the workaround for <<
1045 2040
1046 If a Cortex-A715 cpu sees a page ma !! 2041 config SYS_HAS_CPU_BMIPS4380
1047 to non-executable, it may corrupt t !! 2042 bool
1048 next instruction abort caused by pe !! 2043 select SYS_HAS_CPU_BMIPS
1049 2044
1050 Only user-space does executable to !! 2045 config SYS_HAS_CPU_BMIPS5000
1051 mprotect() system call. Workaround !! 2046 bool
1052 TLB invalidation, for all changes t !! 2047 select SYS_HAS_CPU_BMIPS
>> 2048 select ARCH_HAS_SYNC_DMA_FOR_CPU
1053 2049
1054 If unsure, say Y. !! 2050 config SYS_HAS_CPU_XLR
>> 2051 bool
1055 2052
1056 config ARM64_WORKAROUND_SPECULATIVE_UNPRIV_LO !! 2053 config SYS_HAS_CPU_XLP
1057 bool 2054 bool
1058 2055
1059 config ARM64_ERRATUM_2966298 !! 2056 #
1060 bool "Cortex-A520: 2966298: workaroun !! 2057 # CPU may reorder R->R, R->W, W->R, W->W
1061 select ARM64_WORKAROUND_SPECULATIVE_U !! 2058 # Reordering beyond LL and SC is handled in WEAK_REORDERING_BEYOND_LLSC
1062 default y !! 2059 #
1063 help !! 2060 config WEAK_ORDERING
1064 This option adds the workaround for !! 2061 bool
1065 2062
1066 On an affected Cortex-A520 core, a !! 2063 #
1067 load might leak data from a privile !! 2064 # CPU may reorder reads and writes beyond LL/SC
>> 2065 # CPU may reorder R->LL, R->LL, W->LL, W->LL, R->SC, R->SC, W->SC, W->SC
>> 2066 #
>> 2067 config WEAK_REORDERING_BEYOND_LLSC
>> 2068 bool
>> 2069 endmenu
1068 2070
1069 Work around this problem by executi !! 2071 #
>> 2072 # These two indicate any level of the MIPS32 and MIPS64 architecture
>> 2073 #
>> 2074 config CPU_MIPS32
>> 2075 bool
>> 2076 default y if CPU_MIPS32_R1 || CPU_MIPS32_R2 || CPU_MIPS32_R5 || \
>> 2077 CPU_MIPS32_R6 || CPU_P5600
1070 2078
1071 If unsure, say Y. !! 2079 config CPU_MIPS64
>> 2080 bool
>> 2081 default y if CPU_MIPS64_R1 || CPU_MIPS64_R2 || CPU_MIPS64_R5 || \
>> 2082 CPU_MIPS64_R6
1072 2083
1073 config ARM64_ERRATUM_3117295 !! 2084 #
1074 bool "Cortex-A510: 3117295: workaroun !! 2085 # These indicate the revision of the architecture
1075 select ARM64_WORKAROUND_SPECULATIVE_U !! 2086 #
1076 default y !! 2087 config CPU_MIPSR1
1077 help !! 2088 bool
1078 This option adds the workaround for !! 2089 default y if CPU_MIPS32_R1 || CPU_MIPS64_R1
1079 2090
1080 On an affected Cortex-A510 core, a !! 2091 config CPU_MIPSR2
1081 load might leak data from a privile !! 2092 bool
>> 2093 default y if CPU_MIPS32_R2 || CPU_MIPS64_R2 || CPU_CAVIUM_OCTEON
>> 2094 select CPU_HAS_RIXI
>> 2095 select CPU_HAS_DIEI if !CPU_DIEI_BROKEN
>> 2096 select MIPS_SPRAM
1082 2097
1083 Work around this problem by executi !! 2098 config CPU_MIPSR5
>> 2099 bool
>> 2100 default y if CPU_MIPS32_R5 || CPU_MIPS64_R5 || CPU_P5600
>> 2101 select CPU_HAS_RIXI
>> 2102 select CPU_HAS_DIEI if !CPU_DIEI_BROKEN
>> 2103 select MIPS_SPRAM
1084 2104
1085 If unsure, say Y. !! 2105 config CPU_MIPSR6
>> 2106 bool
>> 2107 default y if CPU_MIPS32_R6 || CPU_MIPS64_R6
>> 2108 select CPU_HAS_RIXI
>> 2109 select CPU_HAS_DIEI if !CPU_DIEI_BROKEN
>> 2110 select HAVE_ARCH_BITREVERSE
>> 2111 select MIPS_ASID_BITS_VARIABLE
>> 2112 select MIPS_CRC_SUPPORT
>> 2113 select MIPS_SPRAM
1086 2114
1087 config ARM64_ERRATUM_3194386 !! 2115 config TARGET_ISA_REV
1088 bool "Cortex-*/Neoverse-*: workaround !! 2116 int
1089 default y !! 2117 default 1 if CPU_MIPSR1
>> 2118 default 2 if CPU_MIPSR2
>> 2119 default 5 if CPU_MIPSR5
>> 2120 default 6 if CPU_MIPSR6
>> 2121 default 0
1090 help 2122 help
1091 This option adds the workaround for !! 2123 Reflects the ISA revision being targeted by the kernel build. This
1092 !! 2124 is effectively the Kconfig equivalent of MIPS_ISA_REV.
1093 * ARM Cortex-A76 erratum 3324349 <<
1094 * ARM Cortex-A77 erratum 3324348 <<
1095 * ARM Cortex-A78 erratum 3324344 <<
1096 * ARM Cortex-A78C erratum 3324346 <<
1097 * ARM Cortex-A78C erratum 3324347 <<
1098 * ARM Cortex-A710 erratam 3324338 <<
1099 * ARM Cortex-A715 errartum 3456084 <<
1100 * ARM Cortex-A720 erratum 3456091 <<
1101 * ARM Cortex-A725 erratum 3456106 <<
1102 * ARM Cortex-X1 erratum 3324344 <<
1103 * ARM Cortex-X1C erratum 3324346 <<
1104 * ARM Cortex-X2 erratum 3324338 <<
1105 * ARM Cortex-X3 erratum 3324335 <<
1106 * ARM Cortex-X4 erratum 3194386 <<
1107 * ARM Cortex-X925 erratum 3324334 <<
1108 * ARM Neoverse-N1 erratum 3324349 <<
1109 * ARM Neoverse N2 erratum 3324339 <<
1110 * ARM Neoverse-N3 erratum 3456111 <<
1111 * ARM Neoverse-V1 erratum 3324341 <<
1112 * ARM Neoverse V2 erratum 3324336 <<
1113 * ARM Neoverse-V3 erratum 3312417 <<
1114 <<
1115 On affected cores "MSR SSBS, #0" in <<
1116 subsequent speculative instructions <<
1117 speculative store bypassing. <<
1118 <<
1119 Work around this problem by placing <<
1120 Instruction Synchronization Barrier <<
1121 SSBS. The presence of the SSBS spec <<
1122 from hwcaps and EL0 reads of ID_AA6 <<
1123 will use the PR_SPEC_STORE_BYPASS p <<
1124 <<
1125 If unsure, say Y. <<
1126 2125
1127 config CAVIUM_ERRATUM_22375 !! 2126 config EVA
1128 bool "Cavium erratum 22375, 24313" !! 2127 bool
1129 default y <<
1130 help <<
1131 Enable workaround for errata 22375 <<
1132 2128
1133 This implements two gicv3-its errat !! 2129 config XPA
1134 with a small impact affecting only !! 2130 bool
1135 2131
1136 erratum 22375: only alloc 8MB tab !! 2132 config SYS_SUPPORTS_32BIT_KERNEL
1137 erratum 24313: ignore memory acce !! 2133 bool
>> 2134 config SYS_SUPPORTS_64BIT_KERNEL
>> 2135 bool
>> 2136 config CPU_SUPPORTS_32BIT_KERNEL
>> 2137 bool
>> 2138 config CPU_SUPPORTS_64BIT_KERNEL
>> 2139 bool
>> 2140 config CPU_SUPPORTS_CPUFREQ
>> 2141 bool
>> 2142 config CPU_SUPPORTS_ADDRWINCFG
>> 2143 bool
>> 2144 config CPU_SUPPORTS_HUGEPAGES
>> 2145 bool
>> 2146 depends on !(32BIT && (ARCH_PHYS_ADDR_T_64BIT || EVA))
>> 2147 config MIPS_PGD_C0_CONTEXT
>> 2148 bool
>> 2149 default y if 64BIT && (CPU_MIPSR2 || CPU_MIPSR6) && !CPU_XLP
1138 2150
1139 The fixes are in ITS initialization !! 2151 #
1140 type and table size provided by the !! 2152 # Set to y for ptrace access to watch registers.
>> 2153 #
>> 2154 config HARDWARE_WATCHPOINTS
>> 2155 bool
>> 2156 default y if CPU_MIPSR1 || CPU_MIPSR2 || CPU_MIPSR6
1141 2157
1142 If unsure, say Y. !! 2158 menu "Kernel type"
1143 2159
1144 config CAVIUM_ERRATUM_23144 !! 2160 choice
1145 bool "Cavium erratum 23144: ITS SYNC !! 2161 prompt "Kernel code model"
1146 depends on NUMA <<
1147 default y <<
1148 help 2162 help
1149 ITS SYNC command hang for cross nod !! 2163 You should only select this option if you have a workload that
1150 !! 2164 actually benefits from 64-bit processing or if your machine has
1151 If unsure, say Y. !! 2165 large memory. You will only be presented a single option in this
1152 !! 2166 menu if your system does not support both 32-bit and 64-bit kernels.
1153 config CAVIUM_ERRATUM_23154 !! 2167
1154 bool "Cavium errata 23154 and 38545: !! 2168 config 32BIT
1155 default y !! 2169 bool "32-bit kernel"
>> 2170 depends on CPU_SUPPORTS_32BIT_KERNEL && SYS_SUPPORTS_32BIT_KERNEL
>> 2171 select TRAD_SIGNALS
1156 help 2172 help
1157 The ThunderX GICv3 implementation r !! 2173 Select this option if you want to build a 32-bit kernel.
1158 reading the IAR status to ensure da <<
1159 (access to icc_iar1_el1 is not sync <<
1160 <<
1161 It also suffers from erratum 38545 <<
1162 OcteonTX and OcteonTX2), resulting <<
1163 spuriously presented to the CPU int <<
1164 <<
1165 If unsure, say Y. <<
1166 2174
1167 config CAVIUM_ERRATUM_27456 !! 2175 config 64BIT
1168 bool "Cavium erratum 27456: Broadcast !! 2176 bool "64-bit kernel"
1169 default y !! 2177 depends on CPU_SUPPORTS_64BIT_KERNEL && SYS_SUPPORTS_64BIT_KERNEL
1170 help 2178 help
1171 On ThunderX T88 pass 1.x through 2. !! 2179 Select this option if you want to build a 64-bit kernel.
1172 instructions may cause the icache t <<
1173 contains data for a non-current ASI <<
1174 invalidate the icache when changing <<
1175 2180
1176 If unsure, say Y. !! 2181 endchoice
1177 2182
1178 config CAVIUM_ERRATUM_30115 !! 2183 config KVM_GUEST
1179 bool "Cavium erratum 30115: Guest may !! 2184 bool "KVM Guest Kernel"
1180 default y !! 2185 depends on CPU_MIPS32_R2
1181 help !! 2186 depends on BROKEN_ON_SMP
1182 On ThunderX T88 pass 1.x through 2. !! 2187 help
1183 1.2, and T83 Pass 1.0, KVM guest ex !! 2188 Select this option if building a guest kernel for KVM (Trap & Emulate)
1184 interrupts in host. Trapping both G !! 2189 mode.
1185 accesses sidesteps the issue. !! 2190
>> 2191 config KVM_GUEST_TIMER_FREQ
>> 2192 int "Count/Compare Timer Frequency (MHz)"
>> 2193 depends on KVM_GUEST
>> 2194 default 100
>> 2195 help
>> 2196 Set this to non-zero if building a guest kernel for KVM to skip RTC
>> 2197 emulation when determining guest CPU Frequency. Instead, the guest's
>> 2198 timer frequency is specified directly.
>> 2199
>> 2200 config MIPS_VA_BITS_48
>> 2201 bool "48 bits virtual memory"
>> 2202 depends on 64BIT
>> 2203 help
>> 2204 Support a maximum at least 48 bits of application virtual
>> 2205 memory. Default is 40 bits or less, depending on the CPU.
>> 2206 For page sizes 16k and above, this option results in a small
>> 2207 memory overhead for page tables. For 4k page size, a fourth
>> 2208 level of page tables is added which imposes both a memory
>> 2209 overhead as well as slower TLB fault handling.
1186 2210
1187 If unsure, say Y. !! 2211 If unsure, say N.
1188 2212
1189 config CAVIUM_TX2_ERRATUM_219 !! 2213 choice
1190 bool "Cavium ThunderX2 erratum 219: P !! 2214 prompt "Kernel page size"
1191 default y !! 2215 default PAGE_SIZE_4KB
1192 help <<
1193 On Cavium ThunderX2, a load, store <<
1194 TTBR update and the corresponding c <<
1195 cause a spurious Data Abort to be d <<
1196 the CPU core. <<
1197 <<
1198 Work around the issue by avoiding t <<
1199 trapping KVM guest TTBRx_EL1 writes <<
1200 trap handler performs the correspon <<
1201 instruction and ensures context syn <<
1202 exception return. <<
1203 2216
1204 If unsure, say Y. !! 2217 config PAGE_SIZE_4KB
>> 2218 bool "4kB"
>> 2219 depends on !CPU_LOONGSON2EF && !CPU_LOONGSON64
>> 2220 help
>> 2221 This option select the standard 4kB Linux page size. On some
>> 2222 R3000-family processors this is the only available page size. Using
>> 2223 4kB page size will minimize memory consumption and is therefore
>> 2224 recommended for low memory systems.
>> 2225
>> 2226 config PAGE_SIZE_8KB
>> 2227 bool "8kB"
>> 2228 depends on CPU_CAVIUM_OCTEON
>> 2229 depends on !MIPS_VA_BITS_48
>> 2230 help
>> 2231 Using 8kB page size will result in higher performance kernel at
>> 2232 the price of higher memory consumption. This option is available
>> 2233 only on cnMIPS processors. Note that you will need a suitable Linux
>> 2234 distribution to support this.
>> 2235
>> 2236 config PAGE_SIZE_16KB
>> 2237 bool "16kB"
>> 2238 depends on !CPU_R3000 && !CPU_TX39XX
>> 2239 help
>> 2240 Using 16kB page size will result in higher performance kernel at
>> 2241 the price of higher memory consumption. This option is available on
>> 2242 all non-R3000 family processors. Note that you will need a suitable
>> 2243 Linux distribution to support this.
>> 2244
>> 2245 config PAGE_SIZE_32KB
>> 2246 bool "32kB"
>> 2247 depends on CPU_CAVIUM_OCTEON
>> 2248 depends on !MIPS_VA_BITS_48
>> 2249 help
>> 2250 Using 32kB page size will result in higher performance kernel at
>> 2251 the price of higher memory consumption. This option is available
>> 2252 only on cnMIPS cores. Note that you will need a suitable Linux
>> 2253 distribution to support this.
>> 2254
>> 2255 config PAGE_SIZE_64KB
>> 2256 bool "64kB"
>> 2257 depends on !CPU_R3000 && !CPU_TX39XX
>> 2258 help
>> 2259 Using 64kB page size will result in higher performance kernel at
>> 2260 the price of higher memory consumption. This option is available on
>> 2261 all non-R3000 family processor. Not that at the time of this
>> 2262 writing this option is still high experimental.
1205 2263
1206 config FUJITSU_ERRATUM_010001 !! 2264 endchoice
1207 bool "Fujitsu-A64FX erratum E#010001: <<
1208 default y <<
1209 help <<
1210 This option adds a workaround for F <<
1211 On some variants of the Fujitsu-A64 <<
1212 accesses may cause undefined fault <<
1213 This fault occurs under a specific <<
1214 load/store instruction performs an <<
1215 case-1 TTBR0_EL1 with TCR_EL1.NFD0 <<
1216 case-2 TTBR0_EL2 with TCR_EL2.NFD0 <<
1217 case-3 TTBR1_EL1 with TCR_EL1.NFD1 <<
1218 case-4 TTBR1_EL2 with TCR_EL2.NFD1 <<
1219 <<
1220 The workaround is to ensure these b <<
1221 The workaround only affects the Fuj <<
1222 2265
1223 If unsure, say Y. !! 2266 config FORCE_MAX_ZONEORDER
>> 2267 int "Maximum zone order"
>> 2268 range 14 64 if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_64KB
>> 2269 default "14" if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_64KB
>> 2270 range 13 64 if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_32KB
>> 2271 default "13" if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_32KB
>> 2272 range 12 64 if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_16KB
>> 2273 default "12" if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_16KB
>> 2274 range 0 64
>> 2275 default "11"
>> 2276 help
>> 2277 The kernel memory allocator divides physically contiguous memory
>> 2278 blocks into "zones", where each zone is a power of two number of
>> 2279 pages. This option selects the largest power of two that the kernel
>> 2280 keeps in the memory allocator. If you need to allocate very large
>> 2281 blocks of physically contiguous memory, then you may need to
>> 2282 increase this value.
1224 2283
1225 config HISILICON_ERRATUM_161600802 !! 2284 This config option is actually maximum order plus one. For example,
1226 bool "Hip07 161600802: Erroneous redi !! 2285 a value of 11 means that the largest free memory block is 2^10 pages.
1227 default y <<
1228 help <<
1229 The HiSilicon Hip07 SoC uses the wr <<
1230 when issued ITS commands such as VM <<
1231 a 128kB offset to be applied to the <<
1232 2286
1233 If unsure, say Y. !! 2287 The page size is not necessarily 4KB. Keep this in mind
>> 2288 when choosing a value for this option.
1234 2289
1235 config QCOM_FALKOR_ERRATUM_1003 !! 2290 config BOARD_SCACHE
1236 bool "Falkor E1003: Incorrect transla !! 2291 bool
1237 default y <<
1238 help <<
1239 On Falkor v1, an incorrect ASID may <<
1240 and BADDR are changed together in T <<
1241 in TTBR1_EL1, this situation only o <<
1242 then only for entries in the walk c <<
1243 is unchanged. Work around the errat <<
1244 entries for the trampoline before e <<
1245 2292
1246 config QCOM_FALKOR_ERRATUM_1009 !! 2293 config IP22_CPU_SCACHE
1247 bool "Falkor E1009: Prematurely compl !! 2294 bool
1248 default y !! 2295 select BOARD_SCACHE
1249 select ARM64_WORKAROUND_REPEAT_TLBI <<
1250 help <<
1251 On Falkor v1, the CPU may premature <<
1252 TLBI xxIS invalidate maintenance op <<
1253 one more time to fix the issue. <<
1254 2296
1255 If unsure, say Y. !! 2297 #
>> 2298 # Support for a MIPS32 / MIPS64 style S-caches
>> 2299 #
>> 2300 config MIPS_CPU_SCACHE
>> 2301 bool
>> 2302 select BOARD_SCACHE
1256 2303
1257 config QCOM_QDF2400_ERRATUM_0065 !! 2304 config R5000_CPU_SCACHE
1258 bool "QDF2400 E0065: Incorrect GITS_T !! 2305 bool
1259 default y !! 2306 select BOARD_SCACHE
1260 help <<
1261 On Qualcomm Datacenter Technologies <<
1262 ITE size incorrectly. The GITS_TYPE <<
1263 been indicated as 16Bytes (0xf), no <<
1264 2307
1265 If unsure, say Y. !! 2308 config RM7000_CPU_SCACHE
>> 2309 bool
>> 2310 select BOARD_SCACHE
1266 2311
1267 config QCOM_FALKOR_ERRATUM_E1041 !! 2312 config SIBYTE_DMA_PAGEOPS
1268 bool "Falkor E1041: Speculative instr !! 2313 bool "Use DMA to clear/copy pages"
1269 default y !! 2314 depends on CPU_SB1
1270 help 2315 help
1271 Falkor CPU may speculatively fetch !! 2316 Instead of using the CPU to zero and copy pages, use a Data Mover
1272 memory location when MMU translatio !! 2317 channel. These DMA channels are otherwise unused by the standard
1273 to SCTLR_ELn[M]=0. Prefix an ISB in !! 2318 SiByte Linux port. Seems to give a small performance benefit.
1274 2319
1275 If unsure, say Y. !! 2320 config CPU_HAS_PREFETCH
1276 !! 2321 bool
1277 config NVIDIA_CARMEL_CNP_ERRATUM <<
1278 bool "NVIDIA Carmel CNP: CNP on Carme <<
1279 default y <<
1280 help <<
1281 If CNP is enabled on Carmel cores, <<
1282 invalidate shared TLB entries insta <<
1283 on standard ARM cores. <<
1284 2322
1285 If unsure, say Y. !! 2323 config CPU_GENERIC_DUMP_TLB
>> 2324 bool
>> 2325 default y if !(CPU_R3000 || CPU_TX39XX)
1286 2326
1287 config ROCKCHIP_ERRATUM_3588001 !! 2327 config MIPS_FP_SUPPORT
1288 bool "Rockchip 3588001: GIC600 can no !! 2328 bool "Floating Point support" if EXPERT
1289 default y 2329 default y
1290 help 2330 help
1291 The Rockchip RK3588 GIC600 SoC inte !! 2331 Select y to include support for floating point in the kernel
1292 This means, that its sharability fe !! 2332 including initialization of FPU hardware, FP context save & restore
1293 is supported by the IP itself. !! 2333 and emulation of an FPU where necessary. Without this support any
>> 2334 userland program attempting to use floating point instructions will
>> 2335 receive a SIGILL.
1294 2336
1295 If unsure, say Y. !! 2337 If you know that your userland will not attempt to use floating point
1296 !! 2338 instructions then you can say n here to shrink the kernel a little.
1297 config SOCIONEXT_SYNQUACER_PREITS <<
1298 bool "Socionext Synquacer: Workaround <<
1299 default y <<
1300 help <<
1301 Socionext Synquacer SoCs implement <<
1302 MSI doorbell writes with non-zero v <<
1303 2339
1304 If unsure, say Y. !! 2340 If unsure, say y.
1305 2341
1306 endmenu # "ARM errata workarounds via the alt !! 2342 config CPU_R2300_FPU
>> 2343 bool
>> 2344 depends on MIPS_FP_SUPPORT
>> 2345 default y if CPU_R3000 || CPU_TX39XX
1307 2346
1308 choice !! 2347 config CPU_R3K_TLB
1309 prompt "Page size" !! 2348 bool
1310 default ARM64_4K_PAGES <<
1311 help <<
1312 Page size (translation granule) con <<
1313 2349
1314 config ARM64_4K_PAGES !! 2350 config CPU_R4K_FPU
1315 bool "4KB" !! 2351 bool
1316 select HAVE_PAGE_SIZE_4KB !! 2352 depends on MIPS_FP_SUPPORT
1317 help !! 2353 default y if !CPU_R2300_FPU
1318 This feature enables 4KB pages supp <<
1319 2354
1320 config ARM64_16K_PAGES !! 2355 config CPU_R4K_CACHE_TLB
1321 bool "16KB" !! 2356 bool
1322 select HAVE_PAGE_SIZE_16KB !! 2357 default y if !(CPU_R3K_TLB || CPU_SB1 || CPU_CAVIUM_OCTEON)
1323 help <<
1324 The system will use 16KB pages supp <<
1325 requires applications compiled with <<
1326 aligned segments. <<
1327 2358
1328 config ARM64_64K_PAGES !! 2359 config MIPS_MT_SMP
1329 bool "64KB" !! 2360 bool "MIPS MT SMP support (1 TC on each available VPE)"
1330 select HAVE_PAGE_SIZE_64KB !! 2361 default y
1331 help !! 2362 depends on SYS_SUPPORTS_MULTITHREADING && !CPU_MIPSR6 && !CPU_MICROMIPS
1332 This feature enables 64KB pages sup !! 2363 select CPU_MIPSR2_IRQ_VI
1333 allowing only two levels of page ta !! 2364 select CPU_MIPSR2_IRQ_EI
1334 look-up. AArch32 emulation requires !! 2365 select SYNC_R4K
1335 with 64K aligned segments. !! 2366 select MIPS_MT
>> 2367 select SMP
>> 2368 select SMP_UP
>> 2369 select SYS_SUPPORTS_SMP
>> 2370 select SYS_SUPPORTS_SCHED_SMT
>> 2371 select MIPS_PERF_SHARED_TC_COUNTERS
>> 2372 help
>> 2373 This is a kernel model which is known as SMVP. This is supported
>> 2374 on cores with the MT ASE and uses the available VPEs to implement
>> 2375 virtual processors which supports SMP. This is equivalent to the
>> 2376 Intel Hyperthreading feature. For further information go to
>> 2377 <http://www.imgtec.com/mips/mips-multithreading.asp>.
1336 2378
1337 endchoice !! 2379 config MIPS_MT
>> 2380 bool
1338 2381
1339 choice !! 2382 config SCHED_SMT
1340 prompt "Virtual address space size" !! 2383 bool "SMT (multithreading) scheduler support"
1341 default ARM64_VA_BITS_52 !! 2384 depends on SYS_SUPPORTS_SCHED_SMT
>> 2385 default n
1342 help 2386 help
1343 Allows choosing one of multiple pos !! 2387 SMT scheduler support improves the CPU scheduler's decision making
1344 space sizes. The level of translati !! 2388 when dealing with MIPS MT enabled cores at a cost of slightly
1345 a combination of page size and virt !! 2389 increased overhead in some places. If unsure say N here.
1346 <<
1347 config ARM64_VA_BITS_36 <<
1348 bool "36-bit" if EXPERT <<
1349 depends on PAGE_SIZE_16KB <<
1350 <<
1351 config ARM64_VA_BITS_39 <<
1352 bool "39-bit" <<
1353 depends on PAGE_SIZE_4KB <<
1354 <<
1355 config ARM64_VA_BITS_42 <<
1356 bool "42-bit" <<
1357 depends on PAGE_SIZE_64KB <<
1358 <<
1359 config ARM64_VA_BITS_47 <<
1360 bool "47-bit" <<
1361 depends on PAGE_SIZE_16KB <<
1362 <<
1363 config ARM64_VA_BITS_48 <<
1364 bool "48-bit" <<
1365 <<
1366 config ARM64_VA_BITS_52 <<
1367 bool "52-bit" <<
1368 depends on ARM64_PAN || !ARM64_SW_TTB <<
1369 help <<
1370 Enable 52-bit virtual addressing fo <<
1371 requested via a hint to mmap(). The <<
1372 virtual addresses for its own mappi <<
1373 this feature is available, otherwis <<
1374 <<
1375 NOTE: Enabling 52-bit virtual addre <<
1376 ARMv8.3 Pointer Authentication will <<
1377 reduced from 7 bits to 3 bits, whic <<
1378 impact on its susceptibility to bru <<
1379 <<
1380 If unsure, select 48-bit virtual ad <<
1381 2390
1382 endchoice !! 2391 config SYS_SUPPORTS_SCHED_SMT
>> 2392 bool
1383 2393
1384 config ARM64_FORCE_52BIT !! 2394 config SYS_SUPPORTS_MULTITHREADING
1385 bool "Force 52-bit virtual addresses !! 2395 bool
1386 depends on ARM64_VA_BITS_52 && EXPERT <<
1387 help <<
1388 For systems with 52-bit userspace V <<
1389 to maintain compatibility with olde <<
1390 unless a hint is supplied to mmap. <<
1391 <<
1392 This configuration option disables <<
1393 forces all userspace addresses to b <<
1394 should only enable this configurati <<
1395 memory management code. If unsure s <<
1396 2396
1397 config ARM64_VA_BITS !! 2397 config MIPS_MT_FPAFF
1398 int !! 2398 bool "Dynamic FPU affinity for FP-intensive threads"
1399 default 36 if ARM64_VA_BITS_36 !! 2399 default y
1400 default 39 if ARM64_VA_BITS_39 !! 2400 depends on MIPS_MT_SMP
1401 default 42 if ARM64_VA_BITS_42 <<
1402 default 47 if ARM64_VA_BITS_47 <<
1403 default 48 if ARM64_VA_BITS_48 <<
1404 default 52 if ARM64_VA_BITS_52 <<
1405 2401
1406 choice !! 2402 config MIPSR2_TO_R6_EMULATOR
1407 prompt "Physical address space size" !! 2403 bool "MIPS R2-to-R6 emulator"
1408 default ARM64_PA_BITS_48 !! 2404 depends on CPU_MIPSR6
>> 2405 depends on MIPS_FP_SUPPORT
>> 2406 default y
1409 help 2407 help
1410 Choose the maximum physical address !! 2408 Choose this option if you want to run non-R6 MIPS userland code.
1411 support. !! 2409 Even if you say 'Y' here, the emulator will still be disabled by
1412 !! 2410 default. You can enable it using the 'mipsr2emu' kernel option.
1413 config ARM64_PA_BITS_48 !! 2411 The only reason this is a build-time option is to save ~14K from the
1414 bool "48-bit" !! 2412 final kernel image.
1415 depends on ARM64_64K_PAGES || !ARM64_ <<
1416 <<
1417 config ARM64_PA_BITS_52 <<
1418 bool "52-bit" <<
1419 depends on ARM64_64K_PAGES || ARM64_V <<
1420 depends on ARM64_PAN || !ARM64_SW_TTB <<
1421 help <<
1422 Enable support for a 52-bit physica <<
1423 part of the ARMv8.2-LPA extension. <<
1424 <<
1425 With this enabled, the kernel will <<
1426 do not support ARMv8.2-LPA, but wit <<
1427 minor performance overhead). <<
1428 <<
1429 endchoice <<
1430 <<
1431 config ARM64_PA_BITS <<
1432 int <<
1433 default 48 if ARM64_PA_BITS_48 <<
1434 default 52 if ARM64_PA_BITS_52 <<
1435 2413
1436 config ARM64_LPA2 !! 2414 config SYS_SUPPORTS_VPE_LOADER
1437 def_bool y !! 2415 bool
1438 depends on ARM64_PA_BITS_52 && !ARM64 !! 2416 depends on SYS_SUPPORTS_MULTITHREADING
1439 <<
1440 choice <<
1441 prompt "Endianness" <<
1442 default CPU_LITTLE_ENDIAN <<
1443 help 2417 help
1444 Select the endianness of data acces !! 2418 Indicates that the platform supports the VPE loader, and provides
1445 applications will need to be compil !! 2419 physical_memsize.
1446 that is selected here. <<
1447 2420
1448 config CPU_BIG_ENDIAN !! 2421 config MIPS_VPE_LOADER
1449 bool "Build big-endian kernel" !! 2422 bool "VPE loader support."
1450 # https://github.com/llvm/llvm-projec !! 2423 depends on SYS_SUPPORTS_VPE_LOADER && MODULES
1451 depends on AS_IS_GNU || AS_VERSION >= !! 2424 select CPU_MIPSR2_IRQ_VI
>> 2425 select CPU_MIPSR2_IRQ_EI
>> 2426 select MIPS_MT
1452 help 2427 help
1453 Say Y if you plan on running a kern !! 2428 Includes a loader for loading an elf relocatable object
>> 2429 onto another VPE and running it.
1454 2430
1455 config CPU_LITTLE_ENDIAN !! 2431 config MIPS_VPE_LOADER_CMP
1456 bool "Build little-endian kernel" !! 2432 bool
1457 help !! 2433 default "y"
1458 Say Y if you plan on running a kern !! 2434 depends on MIPS_VPE_LOADER && MIPS_CMP
1459 This is usually the case for distri <<
1460 2435
1461 endchoice !! 2436 config MIPS_VPE_LOADER_MT
>> 2437 bool
>> 2438 default "y"
>> 2439 depends on MIPS_VPE_LOADER && !MIPS_CMP
1462 2440
1463 config SCHED_MC !! 2441 config MIPS_VPE_LOADER_TOM
1464 bool "Multi-core scheduler support" !! 2442 bool "Load VPE program into memory hidden from linux"
>> 2443 depends on MIPS_VPE_LOADER
>> 2444 default y
1465 help 2445 help
1466 Multi-core scheduler support improv !! 2446 The loader can use memory that is present but has been hidden from
1467 making when dealing with multi-core !! 2447 Linux using the kernel command line option "mem=xxMB". It's up to
1468 increased overhead in some places. !! 2448 you to ensure the amount you put in the option and the space your
>> 2449 program requires is less or equal to the amount physically present.
1469 2450
1470 config SCHED_CLUSTER !! 2451 config MIPS_VPE_APSP_API
1471 bool "Cluster scheduler support" !! 2452 bool "Enable support for AP/SP API (RTLX)"
1472 help !! 2453 depends on MIPS_VPE_LOADER
1473 Cluster scheduler support improves <<
1474 making when dealing with machines t <<
1475 Cluster usually means a couple of C <<
1476 by sharing mid-level caches, last-l <<
1477 busses. <<
1478 2454
1479 config SCHED_SMT !! 2455 config MIPS_VPE_APSP_API_CMP
1480 bool "SMT scheduler support" !! 2456 bool
1481 help !! 2457 default "y"
1482 Improves the CPU scheduler's decisi !! 2458 depends on MIPS_VPE_APSP_API && MIPS_CMP
1483 MultiThreading at a cost of slightl <<
1484 places. If unsure say N here. <<
1485 2459
1486 config NR_CPUS !! 2460 config MIPS_VPE_APSP_API_MT
1487 int "Maximum number of CPUs (2-4096)" !! 2461 bool
1488 range 2 4096 !! 2462 default "y"
1489 default "512" !! 2463 depends on MIPS_VPE_APSP_API && !MIPS_CMP
1490 2464
1491 config HOTPLUG_CPU !! 2465 config MIPS_CMP
1492 bool "Support for hot-pluggable CPUs" !! 2466 bool "MIPS CMP framework support (DEPRECATED)"
1493 select GENERIC_IRQ_MIGRATION !! 2467 depends on SYS_SUPPORTS_MIPS_CMP && !CPU_MIPSR6
>> 2468 select SMP
>> 2469 select SYNC_R4K
>> 2470 select SYS_SUPPORTS_SMP
>> 2471 select WEAK_ORDERING
>> 2472 default n
1494 help 2473 help
1495 Say Y here to experiment with turni !! 2474 Select this if you are using a bootloader which implements the "CMP
1496 can be controlled through /sys/devi !! 2475 framework" protocol (ie. YAMON) and want your kernel to make use of
>> 2476 its ability to start secondary CPUs.
>> 2477
>> 2478 Unless you have a specific need, you should use CONFIG_MIPS_CPS
>> 2479 instead of this.
>> 2480
>> 2481 config MIPS_CPS
>> 2482 bool "MIPS Coherent Processing System support"
>> 2483 depends on SYS_SUPPORTS_MIPS_CPS
>> 2484 select MIPS_CM
>> 2485 select MIPS_CPS_PM if HOTPLUG_CPU
>> 2486 select SMP
>> 2487 select SYNC_R4K if (CEVT_R4K || CSRC_R4K)
>> 2488 select SYS_SUPPORTS_HOTPLUG_CPU
>> 2489 select SYS_SUPPORTS_SCHED_SMT if CPU_MIPSR6
>> 2490 select SYS_SUPPORTS_SMP
>> 2491 select WEAK_ORDERING
>> 2492 select GENERIC_IRQ_MIGRATION if HOTPLUG_CPU
>> 2493 help
>> 2494 Select this if you wish to run an SMP kernel across multiple cores
>> 2495 within a MIPS Coherent Processing System. When this option is
>> 2496 enabled the kernel will probe for other cores and boot them with
>> 2497 no external assistance. It is safe to enable this when hardware
>> 2498 support is unavailable.
1497 2499
1498 # Common NUMA Features !! 2500 config MIPS_CPS_PM
1499 config NUMA !! 2501 depends on MIPS_CPS
1500 bool "NUMA Memory Allocation and Sche !! 2502 bool
1501 select GENERIC_ARCH_NUMA <<
1502 select OF_NUMA <<
1503 select HAVE_SETUP_PER_CPU_AREA <<
1504 select NEED_PER_CPU_EMBED_FIRST_CHUNK <<
1505 select NEED_PER_CPU_PAGE_FIRST_CHUNK <<
1506 select USE_PERCPU_NUMA_NODE_ID <<
1507 help <<
1508 Enable NUMA (Non-Uniform Memory Acc <<
1509 <<
1510 The kernel will try to allocate mem <<
1511 local memory of the CPU and add som <<
1512 NUMA awareness to the kernel. <<
1513 2503
1514 config NODES_SHIFT !! 2504 config MIPS_CM
1515 int "Maximum NUMA Nodes (as a power o !! 2505 bool
1516 range 1 10 !! 2506 select MIPS_CPC
1517 default "4" <<
1518 depends on NUMA <<
1519 help <<
1520 Specify the maximum number of NUMA <<
1521 system. Increases memory reserved <<
1522 2507
1523 source "kernel/Kconfig.hz" !! 2508 config MIPS_CPC
>> 2509 bool
1524 2510
1525 config ARCH_SPARSEMEM_ENABLE !! 2511 config SB1_PASS_2_WORKAROUNDS
1526 def_bool y !! 2512 bool
1527 select SPARSEMEM_VMEMMAP_ENABLE !! 2513 depends on CPU_SB1 && (CPU_SB1_PASS_2_2 || CPU_SB1_PASS_2)
1528 select SPARSEMEM_VMEMMAP !! 2514 default y
1529 2515
1530 config HW_PERF_EVENTS !! 2516 config SB1_PASS_2_1_WORKAROUNDS
1531 def_bool y !! 2517 bool
1532 depends on ARM_PMU !! 2518 depends on CPU_SB1 && CPU_SB1_PASS_2
>> 2519 default y
1533 2520
1534 # Supported by clang >= 7.0 or GCC >= 12.0.0 !! 2521 choice
1535 config CC_HAVE_SHADOW_CALL_STACK !! 2522 prompt "SmartMIPS or microMIPS ASE support"
1536 def_bool $(cc-option, -fsanitize=shad <<
1537 2523
1538 config PARAVIRT !! 2524 config CPU_NEEDS_NO_SMARTMIPS_OR_MICROMIPS
1539 bool "Enable paravirtualization code" !! 2525 bool "None"
1540 help 2526 help
1541 This changes the kernel so it can m !! 2527 Select this if you want neither microMIPS nor SmartMIPS support
1542 under a hypervisor, potentially imp <<
1543 over full virtualization. <<
1544 2528
1545 config PARAVIRT_TIME_ACCOUNTING !! 2529 config CPU_HAS_SMARTMIPS
1546 bool "Paravirtual steal time accounti !! 2530 depends on SYS_SUPPORTS_SMARTMIPS
1547 select PARAVIRT !! 2531 bool "SmartMIPS"
>> 2532 help
>> 2533 SmartMIPS is a extension of the MIPS32 architecture aimed at
>> 2534 increased security at both hardware and software level for
>> 2535 smartcards. Enabling this option will allow proper use of the
>> 2536 SmartMIPS instructions by Linux applications. However a kernel with
>> 2537 this option will not work on a MIPS core without SmartMIPS core. If
>> 2538 you don't know you probably don't have SmartMIPS and should say N
>> 2539 here.
>> 2540
>> 2541 config CPU_MICROMIPS
>> 2542 depends on 32BIT && SYS_SUPPORTS_MICROMIPS && !CPU_MIPSR6
>> 2543 bool "microMIPS"
1548 help 2544 help
1549 Select this option to enable fine g !! 2545 When this option is enabled the kernel will be built using the
1550 accounting. Time spent executing ot !! 2546 microMIPS ISA
1551 the current vCPU is discounted from <<
1552 that, there can be a small performa <<
1553 2547
1554 If in doubt, say N here. !! 2548 endchoice
1555 <<
1556 config ARCH_SUPPORTS_KEXEC <<
1557 def_bool PM_SLEEP_SMP <<
1558 <<
1559 config ARCH_SUPPORTS_KEXEC_FILE <<
1560 def_bool y <<
1561 <<
1562 config ARCH_SELECTS_KEXEC_FILE <<
1563 def_bool y <<
1564 depends on KEXEC_FILE <<
1565 select HAVE_IMA_KEXEC if IMA <<
1566 2549
1567 config ARCH_SUPPORTS_KEXEC_SIG !! 2550 config CPU_HAS_MSA
1568 def_bool y !! 2551 bool "Support for the MIPS SIMD Architecture"
>> 2552 depends on CPU_SUPPORTS_MSA
>> 2553 depends on MIPS_FP_SUPPORT
>> 2554 depends on 64BIT || MIPS_O32_FP64_SUPPORT
>> 2555 help
>> 2556 MIPS SIMD Architecture (MSA) introduces 128 bit wide vector registers
>> 2557 and a set of SIMD instructions to operate on them. When this option
>> 2558 is enabled the kernel will support allocating & switching MSA
>> 2559 vector register contexts. If you know that your kernel will only be
>> 2560 running on CPUs which do not support MSA or that your userland will
>> 2561 not be making use of it then you may wish to say N here to reduce
>> 2562 the size & complexity of your kernel.
1569 2563
1570 config ARCH_SUPPORTS_KEXEC_IMAGE_VERIFY_SIG !! 2564 If unsure, say Y.
1571 def_bool y <<
1572 2565
1573 config ARCH_DEFAULT_KEXEC_IMAGE_VERIFY_SIG !! 2566 config CPU_HAS_WB
1574 def_bool y !! 2567 bool
1575 2568
1576 config ARCH_SUPPORTS_CRASH_DUMP !! 2569 config XKS01
1577 def_bool y !! 2570 bool
1578 2571
1579 config ARCH_HAS_GENERIC_CRASHKERNEL_RESERVATI !! 2572 config CPU_HAS_DIEI
1580 def_bool CRASH_RESERVE !! 2573 depends on !CPU_DIEI_BROKEN
>> 2574 bool
1581 2575
1582 config TRANS_TABLE !! 2576 config CPU_DIEI_BROKEN
1583 def_bool y !! 2577 bool
1584 depends on HIBERNATION || KEXEC_CORE <<
1585 2578
1586 config XEN_DOM0 !! 2579 config CPU_HAS_RIXI
1587 def_bool y !! 2580 bool
1588 depends on XEN <<
1589 2581
1590 config XEN !! 2582 config CPU_NO_LOAD_STORE_LR
1591 bool "Xen guest support on ARM64" !! 2583 bool
1592 depends on ARM64 && OF <<
1593 select SWIOTLB_XEN <<
1594 select PARAVIRT <<
1595 help 2584 help
1596 Say Y if you want to run Linux in a !! 2585 CPU lacks support for unaligned load and store instructions:
>> 2586 LWL, LWR, SWL, SWR (Load/store word left/right).
>> 2587 LDL, LDR, SDL, SDR (Load/store doubleword left/right, for 64bit
>> 2588 systems).
1597 2589
1598 # include/linux/mmzone.h requires the followi <<
1599 # <<
1600 # MAX_PAGE_ORDER + PAGE_SHIFT <= SECTION_SI <<
1601 # 2590 #
1602 # so the maximum value of MAX_PAGE_ORDER is S !! 2591 # Vectored interrupt mode is an R2 feature
1603 # 2592 #
1604 # | SECTION_SIZE_BITS | PAGE_SHIFT | m !! 2593 config CPU_MIPSR2_IRQ_VI
1605 # ----+-------------------+--------------+--- !! 2594 bool
1606 # 4K | 27 | 12 | <<
1607 # 16K | 27 | 14 | <<
1608 # 64K | 29 | 16 | <<
1609 config ARCH_FORCE_MAX_ORDER <<
1610 int <<
1611 default "13" if ARM64_64K_PAGES <<
1612 default "11" if ARM64_16K_PAGES <<
1613 default "10" <<
1614 help <<
1615 The kernel page allocator limits th <<
1616 contiguous allocations. The limit i <<
1617 defines the maximal power of two of <<
1618 allocated as a single contiguous bl <<
1619 overriding the default setting when <<
1620 large blocks of physically contiguo <<
1621 <<
1622 The maximal size of allocation cann <<
1623 section, so the value of MAX_PAGE_O <<
1624 <<
1625 MAX_PAGE_ORDER + PAGE_SHIFT <= SE <<
1626 <<
1627 Don't change if unsure. <<
1628 <<
1629 config UNMAP_KERNEL_AT_EL0 <<
1630 bool "Unmap kernel when running in us <<
1631 default y <<
1632 help <<
1633 Speculation attacks against some hi <<
1634 be used to bypass MMU permission ch <<
1635 userspace. This can be defended aga <<
1636 when running in userspace, mapping <<
1637 via a trampoline page in the vector <<
1638 <<
1639 If unsure, say Y. <<
1640 2595
1641 config MITIGATE_SPECTRE_BRANCH_HISTORY !! 2596 #
1642 bool "Mitigate Spectre style attacks !! 2597 # Extended interrupt mode is an R2 feature
1643 default y !! 2598 #
1644 help !! 2599 config CPU_MIPSR2_IRQ_EI
1645 Speculation attacks against some hi !! 2600 bool
1646 make use of branch history to influ <<
1647 When taking an exception from user- <<
1648 or a firmware call overwrites the b <<
1649 2601
1650 config RODATA_FULL_DEFAULT_ENABLED !! 2602 config CPU_HAS_SYNC
1651 bool "Apply r/o permissions of VM are !! 2603 bool
>> 2604 depends on !CPU_R3000
1652 default y 2605 default y
1653 help <<
1654 Apply read-only attributes of VM ar <<
1655 the backing pages as well. This pre <<
1656 from being modified (inadvertently <<
1657 mapping of the same memory page. Th <<
1658 be turned off at runtime by passing <<
1659 with rodata=full if this option is <<
1660 <<
1661 This requires the linear region to <<
1662 which may adversely affect performa <<
1663 2606
1664 config ARM64_SW_TTBR0_PAN !! 2607 #
1665 bool "Emulate Privileged Access Never !! 2608 # CPU non-features
1666 depends on !KCSAN !! 2609 #
1667 help !! 2610 config CPU_DADDI_WORKAROUNDS
1668 Enabling this option prevents the k !! 2611 bool
1669 user-space memory directly by point <<
1670 zeroed area and reserved ASID. The <<
1671 restore the valid TTBR0_EL1 tempora <<
1672 2612
1673 config ARM64_TAGGED_ADDR_ABI !! 2613 config CPU_R4000_WORKAROUNDS
1674 bool "Enable the tagged user addresse !! 2614 bool
1675 default y !! 2615 select CPU_R4400_WORKAROUNDS
1676 help <<
1677 When this option is enabled, user a <<
1678 relaxed ABI via prctl() allowing ta <<
1679 to system calls as pointer argument <<
1680 Documentation/arch/arm64/tagged-add <<
1681 2616
1682 menuconfig COMPAT !! 2617 config CPU_R4400_WORKAROUNDS
1683 bool "Kernel support for 32-bit EL0" !! 2618 bool
1684 depends on ARM64_4K_PAGES || EXPERT <<
1685 select HAVE_UID16 <<
1686 select OLD_SIGSUSPEND3 <<
1687 select COMPAT_OLD_SIGACTION <<
1688 help <<
1689 This option enables support for a 3 <<
1690 kernel at EL1. AArch32-specific com <<
1691 the user helper functions, VFP supp <<
1692 handled appropriately by the kernel <<
1693 2619
1694 If you use a page size other than 4 !! 2620 config CPU_R4X00_BUGS64
1695 that you will only be able to execu !! 2621 bool
1696 with page size aligned segments. !! 2622 default y if SYS_HAS_CPU_R4X00 && 64BIT && (TARGET_ISA_REV < 1)
1697 2623
1698 If you want to execute 32-bit users !! 2624 config MIPS_ASID_SHIFT
>> 2625 int
>> 2626 default 6 if CPU_R3000 || CPU_TX39XX
>> 2627 default 0
1699 2628
1700 if COMPAT !! 2629 config MIPS_ASID_BITS
>> 2630 int
>> 2631 default 0 if MIPS_ASID_BITS_VARIABLE
>> 2632 default 6 if CPU_R3000 || CPU_TX39XX
>> 2633 default 8
1701 2634
1702 config KUSER_HELPERS !! 2635 config MIPS_ASID_BITS_VARIABLE
1703 bool "Enable kuser helpers page for 3 !! 2636 bool
1704 default y <<
1705 help <<
1706 Warning: disabling this option may <<
1707 2637
1708 Provide kuser helpers to compat tas !! 2638 config MIPS_CRC_SUPPORT
1709 helper code to userspace in read on !! 2639 bool
1710 to allow userspace to be independen <<
1711 the system. This permits binaries t <<
1712 to ARMv8 without modification. <<
1713 2640
1714 See Documentation/arch/arm/kernel_u !! 2641 # R4600 erratum. Due to the lack of errata information the exact
>> 2642 # technical details aren't known. I've experimentally found that disabling
>> 2643 # interrupts during indexed I-cache flushes seems to be sufficient to deal
>> 2644 # with the issue.
>> 2645 config WAR_R4600_V1_INDEX_ICACHEOP
>> 2646 bool
1715 2647
1716 However, the fixed address nature o !! 2648 # Pleasures of the R4600 V1.x. Cite from the IDT R4600 V1.7 errata:
1717 by ROP (return orientated programmi !! 2649 #
1718 exploits. !! 2650 # 18. The CACHE instructions Hit_Writeback_Invalidate_D, Hit_Writeback_D,
>> 2651 # Hit_Invalidate_D and Create_Dirty_Excl_D should only be
>> 2652 # executed if there is no other dcache activity. If the dcache is
>> 2653 # accessed for another instruction immediately preceding when these
>> 2654 # cache instructions are executing, it is possible that the dcache
>> 2655 # tag match outputs used by these cache instructions will be
>> 2656 # incorrect. These cache instructions should be preceded by at least
>> 2657 # four instructions that are not any kind of load or store
>> 2658 # instruction.
>> 2659 #
>> 2660 # This is not allowed: lw
>> 2661 # nop
>> 2662 # nop
>> 2663 # nop
>> 2664 # cache Hit_Writeback_Invalidate_D
>> 2665 #
>> 2666 # This is allowed: lw
>> 2667 # nop
>> 2668 # nop
>> 2669 # nop
>> 2670 # nop
>> 2671 # cache Hit_Writeback_Invalidate_D
>> 2672 config WAR_R4600_V1_HIT_CACHEOP
>> 2673 bool
1719 2674
1720 If all of the binaries and librarie !! 2675 # Writeback and invalidate the primary cache dcache before DMA.
1721 are built specifically for your pla !! 2676 #
1722 these helpers, then you can turn th !! 2677 # R4600 v2.0 bug: "The CACHE instructions Hit_Writeback_Inv_D,
1723 such exploits. However, in that cas !! 2678 # Hit_Writeback_D, Hit_Invalidate_D and Create_Dirty_Exclusive_D will only
1724 relying on those helpers is run, it !! 2679 # operate correctly if the internal data cache refill buffer is empty. These
>> 2680 # CACHE instructions should be separated from any potential data cache miss
>> 2681 # by a load instruction to an uncached address to empty the response buffer."
>> 2682 # (Revision 2.0 device errata from IDT available on https://www.idt.com/
>> 2683 # in .pdf format.)
>> 2684 config WAR_R4600_V2_HIT_CACHEOP
>> 2685 bool
1725 2686
1726 Say N here only if you are absolute !! 2687 # From TX49/H2 manual: "If the instruction (i.e. CACHE) is issued for
1727 need these helpers; otherwise, the !! 2688 # the line which this instruction itself exists, the following
>> 2689 # operation is not guaranteed."
>> 2690 #
>> 2691 # Workaround: do two phase flushing for Index_Invalidate_I
>> 2692 config WAR_TX49XX_ICACHE_INDEX_INV
>> 2693 bool
1728 2694
1729 config COMPAT_VDSO !! 2695 # The RM7000 processors and the E9000 cores have a bug (though PMC-Sierra
1730 bool "Enable vDSO for 32-bit applicat !! 2696 # opposes it being called that) where invalid instructions in the same
1731 depends on !CPU_BIG_ENDIAN !! 2697 # I-cache line worth of instructions being fetched may case spurious
1732 depends on (CC_IS_CLANG && LD_IS_LLD) !! 2698 # exceptions.
1733 select GENERIC_COMPAT_VDSO !! 2699 config WAR_ICACHE_REFILLS
1734 default y !! 2700 bool
1735 help <<
1736 Place in the process address space <<
1737 ELF shared object providing fast im <<
1738 and clock_gettime. <<
1739 2701
1740 You must have a 32-bit build of gli !! 2702 # On the R10000 up to version 2.6 (not sure about 2.7) there is a bug that
1741 to seamlessly take advantage of thi !! 2703 # may cause ll / sc and lld / scd sequences to execute non-atomically.
>> 2704 config WAR_R10000_LLSC
>> 2705 bool
1742 2706
1743 config THUMB2_COMPAT_VDSO !! 2707 # 34K core erratum: "Problems Executing the TLBR Instruction"
1744 bool "Compile the 32-bit vDSO for Thu !! 2708 config WAR_MIPS34K_MISSED_ITLB
1745 depends on COMPAT_VDSO !! 2709 bool
1746 default y <<
1747 help <<
1748 Compile the compat vDSO with '-mthu <<
1749 otherwise with '-marm'. <<
1750 2710
1751 config COMPAT_ALIGNMENT_FIXUPS !! 2711 #
1752 bool "Fix up misaligned multi-word lo !! 2712 # - Highmem only makes sense for the 32-bit kernel.
>> 2713 # - The current highmem code will only work properly on physically indexed
>> 2714 # caches such as R3000, SB1, R7000 or those that look like they're virtually
>> 2715 # indexed such as R4000/R4400 SC and MC versions or R10000. So for the
>> 2716 # moment we protect the user and offer the highmem option only on machines
>> 2717 # where it's known to be safe. This will not offer highmem on a few systems
>> 2718 # such as MIPS32 and MIPS64 CPUs which may have virtual and physically
>> 2719 # indexed CPUs but we're playing safe.
>> 2720 # - We use SYS_SUPPORTS_HIGHMEM to offer highmem only for systems where we
>> 2721 # know they might have memory configurations that could make use of highmem
>> 2722 # support.
>> 2723 #
>> 2724 config HIGHMEM
>> 2725 bool "High Memory Support"
>> 2726 depends on 32BIT && CPU_SUPPORTS_HIGHMEM && SYS_SUPPORTS_HIGHMEM && !CPU_MIPS32_3_5_EVA
>> 2727 select KMAP_LOCAL
1753 2728
1754 menuconfig ARMV8_DEPRECATED !! 2729 config CPU_SUPPORTS_HIGHMEM
1755 bool "Emulate deprecated/obsolete ARM !! 2730 bool
1756 depends on SYSCTL <<
1757 help <<
1758 Legacy software support may require <<
1759 that have been deprecated or obsole <<
1760 2731
1761 Enable this config to enable select !! 2732 config SYS_SUPPORTS_HIGHMEM
1762 features. !! 2733 bool
1763 2734
1764 If unsure, say Y !! 2735 config SYS_SUPPORTS_SMARTMIPS
>> 2736 bool
1765 2737
1766 if ARMV8_DEPRECATED !! 2738 config SYS_SUPPORTS_MICROMIPS
>> 2739 bool
1767 2740
1768 config SWP_EMULATION !! 2741 config SYS_SUPPORTS_MIPS16
1769 bool "Emulate SWP/SWPB instructions" !! 2742 bool
1770 help 2743 help
1771 ARMv8 obsoletes the use of A32 SWP/ !! 2744 This option must be set if a kernel might be executed on a MIPS16-
1772 they are always undefined. Say Y he !! 2745 enabled CPU even if MIPS16 is not actually being used. In other
1773 emulation of these instructions for !! 2746 words, it makes the kernel MIPS16-tolerant.
1774 This feature can be controlled at r <<
1775 sysctl which is disabled by default <<
1776 2747
1777 In some older versions of glibc [<= !! 2748 config CPU_SUPPORTS_MSA
1778 trylock() operations with the assum !! 2749 bool
1779 be preempted. This invalid assumpti <<
1780 with SWP emulation enabled, leading <<
1781 application. <<
1782 2750
1783 NOTE: when accessing uncached share !! 2751 config ARCH_FLATMEM_ENABLE
1784 on an external transaction monitori !! 2752 def_bool y
1785 monitor to maintain update atomicit !! 2753 depends on !NUMA && !CPU_LOONGSON2EF
1786 implement a global monitor, this op <<
1787 perform SWP operations to uncached <<
1788 2754
1789 If unsure, say Y !! 2755 config ARCH_SPARSEMEM_ENABLE
>> 2756 bool
>> 2757 select SPARSEMEM_STATIC if !SGI_IP27
1790 2758
1791 config CP15_BARRIER_EMULATION !! 2759 config NUMA
1792 bool "Emulate CP15 Barrier instructio !! 2760 bool "NUMA Support"
>> 2761 depends on SYS_SUPPORTS_NUMA
1793 help 2762 help
1794 The CP15 barrier instructions - CP1 !! 2763 Say Y to compile the kernel to support NUMA (Non-Uniform Memory
1795 CP15DMB - are deprecated in ARMv8 ( !! 2764 Access). This option improves performance on systems with more
1796 strongly recommended to use the ISB !! 2765 than two nodes; on two node systems it is generally better to
1797 instructions instead. !! 2766 leave it disabled; on single node systems leave this option
1798 !! 2767 disabled.
1799 Say Y here to enable software emula <<
1800 instructions for AArch32 userspace <<
1801 enabled, CP15 barrier usage is trac <<
1802 identify software that needs updati <<
1803 controlled at runtime with the abi. <<
1804 2768
1805 If unsure, say Y !! 2769 config SYS_SUPPORTS_NUMA
>> 2770 bool
1806 2771
1807 config SETEND_EMULATION !! 2772 config HAVE_SETUP_PER_CPU_AREA
1808 bool "Emulate SETEND instruction" !! 2773 def_bool y
1809 help !! 2774 depends on NUMA
1810 The SETEND instruction alters the d <<
1811 AArch32 EL0, and is deprecated in A <<
1812 2775
1813 Say Y here to enable software emula !! 2776 config NEED_PER_CPU_EMBED_FIRST_CHUNK
1814 for AArch32 userspace code. This fe !! 2777 def_bool y
1815 at runtime with the abi.setend sysc !! 2778 depends on NUMA
1816 2779
1817 Note: All the cpus on the system mu !! 2780 config RELOCATABLE
1818 for this feature to be enabled. If !! 2781 bool "Relocatable kernel"
1819 endian - is hotplugged in after thi !! 2782 depends on SYS_SUPPORTS_RELOCATABLE
1820 be unexpected results in the applic !! 2783 depends on CPU_MIPS32_R2 || CPU_MIPS64_R2 || \
>> 2784 CPU_MIPS32_R5 || CPU_MIPS64_R5 || \
>> 2785 CPU_MIPS32_R6 || CPU_MIPS64_R6 || \
>> 2786 CPU_P5600 || CAVIUM_OCTEON_SOC || \
>> 2787 CPU_LOONGSON64
>> 2788 help
>> 2789 This builds a kernel image that retains relocation information
>> 2790 so it can be loaded someplace besides the default 1MB.
>> 2791 The relocations make the kernel binary about 15% larger,
>> 2792 but are discarded at runtime
>> 2793
>> 2794 config RELOCATION_TABLE_SIZE
>> 2795 hex "Relocation table size"
>> 2796 depends on RELOCATABLE
>> 2797 range 0x0 0x01000000
>> 2798 default "0x00200000" if CPU_LOONGSON64
>> 2799 default "0x00100000"
>> 2800 help
>> 2801 A table of relocation data will be appended to the kernel binary
>> 2802 and parsed at boot to fix up the relocated kernel.
1821 2803
1822 If unsure, say Y !! 2804 This option allows the amount of space reserved for the table to be
1823 endif # ARMV8_DEPRECATED !! 2805 adjusted, although the default of 1Mb should be ok in most cases.
1824 2806
1825 endif # COMPAT !! 2807 The build will fail and a valid size suggested if this is too small.
1826 2808
1827 menu "ARMv8.1 architectural features" !! 2809 If unsure, leave at the default value.
1828 2810
1829 config ARM64_HW_AFDBM !! 2811 config RANDOMIZE_BASE
1830 bool "Support for hardware updates of !! 2812 bool "Randomize the address of the kernel image"
1831 default y !! 2813 depends on RELOCATABLE
1832 help 2814 help
1833 The ARMv8.1 architecture extensions !! 2815 Randomizes the physical and virtual address at which the
1834 hardware updates of the access and !! 2816 kernel image is loaded, as a security feature that
1835 table entries. When enabled in TCR_ !! 2817 deters exploit attempts relying on knowledge of the location
1836 capable processors, accesses to pag !! 2818 of kernel internals.
1837 set this bit instead of raising an <<
1838 Similarly, writes to read-only page <<
1839 clear the read-only bit (AP[2]) ins <<
1840 permission fault. <<
1841 2819
1842 Kernels built with this configurati !! 2820 Entropy is generated using any coprocessor 0 registers available.
1843 to work on pre-ARMv8.1 hardware and <<
1844 minimal. If unsure, say Y. <<
1845 2821
1846 config ARM64_PAN !! 2822 The kernel will be offset by up to RANDOMIZE_BASE_MAX_OFFSET.
1847 bool "Enable support for Privileged A <<
1848 default y <<
1849 help <<
1850 Privileged Access Never (PAN; part <<
1851 prevents the kernel or hypervisor f <<
1852 memory directly. <<
1853 2823
1854 Choosing this option will cause any !! 2824 If unsure, say N.
1855 copy_to_user et al) memory access t <<
1856 2825
1857 The feature is detected at runtime, !! 2826 config RANDOMIZE_BASE_MAX_OFFSET
1858 instruction if the cpu does not imp !! 2827 hex "Maximum kASLR offset" if EXPERT
>> 2828 depends on RANDOMIZE_BASE
>> 2829 range 0x0 0x40000000 if EVA || 64BIT
>> 2830 range 0x0 0x08000000
>> 2831 default "0x01000000"
>> 2832 help
>> 2833 When kASLR is active, this provides the maximum offset that will
>> 2834 be applied to the kernel image. It should be set according to the
>> 2835 amount of physical RAM available in the target system minus
>> 2836 PHYSICAL_START and must be a power of 2.
1859 2837
1860 config AS_HAS_LSE_ATOMICS !! 2838 This is limited by the size of KSEG0, 256Mb on 32-bit or 1Gb with
1861 def_bool $(as-instr,.arch_extension l !! 2839 EVA or 64-bit. The default is 16Mb.
1862 2840
1863 config ARM64_LSE_ATOMICS !! 2841 config NODES_SHIFT
1864 bool !! 2842 int
1865 default ARM64_USE_LSE_ATOMICS !! 2843 default "6"
1866 depends on AS_HAS_LSE_ATOMICS !! 2844 depends on NEED_MULTIPLE_NODES
1867 2845
1868 config ARM64_USE_LSE_ATOMICS !! 2846 config HW_PERF_EVENTS
1869 bool "Atomic instructions" !! 2847 bool "Enable hardware performance counter support for perf events"
>> 2848 depends on PERF_EVENTS && !OPROFILE && (CPU_MIPS32 || CPU_MIPS64 || CPU_R10000 || CPU_SB1 || CPU_CAVIUM_OCTEON || CPU_XLP || CPU_LOONGSON64)
1870 default y 2849 default y
1871 help 2850 help
1872 As part of the Large System Extensi !! 2851 Enable hardware performance counter support for perf events. If
1873 atomic instructions that are design !! 2852 disabled, perf events will use software events only.
1874 very large systems. <<
1875 <<
1876 Say Y here to make use of these ins <<
1877 atomic routines. This incurs a smal <<
1878 not support these instructions and <<
1879 built with binutils >= 2.25 in orde <<
1880 to be used. <<
1881 <<
1882 endmenu # "ARMv8.1 architectural features" <<
1883 <<
1884 menu "ARMv8.2 architectural features" <<
1885 <<
1886 config AS_HAS_ARMV8_2 <<
1887 def_bool $(cc-option,-Wa$(comma)-marc <<
1888 <<
1889 config AS_HAS_SHA3 <<
1890 def_bool $(as-instr,.arch armv8.2-a+s <<
1891 <<
1892 config ARM64_PMEM <<
1893 bool "Enable support for persistent m <<
1894 select ARCH_HAS_PMEM_API <<
1895 select ARCH_HAS_UACCESS_FLUSHCACHE <<
1896 help <<
1897 Say Y to enable support for the per <<
1898 ARMv8.2 DCPoP feature. <<
1899 <<
1900 The feature is detected at runtime, <<
1901 operations if DC CVAP is not suppor <<
1902 DC CVAP itself if the system does n <<
1903 2853
1904 config ARM64_RAS_EXTN !! 2854 config DMI
1905 bool "Enable support for RAS CPU Exte !! 2855 bool "Enable DMI scanning"
>> 2856 depends on MACH_LOONGSON64
>> 2857 select DMI_SCAN_MACHINE_NON_EFI_FALLBACK
1906 default y 2858 default y
1907 help 2859 help
1908 CPUs that support the Reliability, !! 2860 Enabled scanning of DMI to identify machine quirks. Say Y
1909 (RAS) Extensions, part of ARMv8.2 a !! 2861 here unless you have verified that your setup is not
1910 errors, classify them and report th !! 2862 affected by entries in the DMI blacklist. Required by PNP
>> 2863 BIOS code.
1911 2864
1912 On CPUs with these extensions syste !! 2865 config SMP
1913 barriers to determine if faults are !! 2866 bool "Multi-Processing support"
1914 classification from a new set of re !! 2867 depends on SYS_SUPPORTS_SMP
1915 <<
1916 Selecting this feature will allow t <<
1917 and access the new registers if the <<
1918 Platform RAS features may additiona <<
1919 <<
1920 config ARM64_CNP <<
1921 bool "Enable support for Common Not P <<
1922 default y <<
1923 depends on ARM64_PAN || !ARM64_SW_TTB <<
1924 help 2868 help
1925 Common Not Private (CNP) allows tra !! 2869 This enables support for systems with more than one CPU. If you have
1926 be shared between different PEs in !! 2870 a system with only one CPU, say N. If you have a system with more
1927 domain, so the hardware can use thi !! 2871 than one CPU, say Y.
1928 caching of such entries in the TLB. !! 2872
>> 2873 If you say N here, the kernel will run on uni- and multiprocessor
>> 2874 machines, but will use only one CPU of a multiprocessor machine. If
>> 2875 you say Y here, the kernel will run on many, but not all,
>> 2876 uniprocessor machines. On a uniprocessor machine, the kernel
>> 2877 will run faster if you say N here.
1929 2878
1930 Selecting this option allows the CN !! 2879 People using multiprocessor machines who say Y here should also say
1931 at runtime, and does not affect PEs !! 2880 Y to "Enhanced Real Time Clock Support", below.
1932 this feature. <<
1933 2881
1934 endmenu # "ARMv8.2 architectural features" !! 2882 See also the SMP-HOWTO available at
>> 2883 <https://www.tldp.org/docs.html#howto>.
1935 2884
1936 menu "ARMv8.3 architectural features" !! 2885 If you don't know what to do here, say N.
1937 2886
1938 config ARM64_PTR_AUTH !! 2887 config HOTPLUG_CPU
1939 bool "Enable support for pointer auth !! 2888 bool "Support for hot-pluggable CPUs"
1940 default y !! 2889 depends on SMP && SYS_SUPPORTS_HOTPLUG_CPU
1941 help 2890 help
1942 Pointer authentication (part of the !! 2891 Say Y here to allow turning CPUs off and on. CPUs can be
1943 instructions for signing and authen !! 2892 controlled through /sys/devices/system/cpu.
1944 keys, which can be used to mitigate !! 2893 (Note: power management support will enable this option
1945 and other attacks. !! 2894 automatically on SMP systems. )
1946 !! 2895 Say N if you want to disable CPU hotplug.
1947 This option enables these instructi <<
1948 Choosing this option will cause the <<
1949 for each process at exec() time, wi <<
1950 context-switched along with the pro <<
1951 <<
1952 The feature is detected at runtime. <<
1953 hardware it will not be advertised <<
1954 be enabled. <<
1955 2896
1956 If the feature is present on the bo !! 2897 config SMP_UP
1957 the late CPU will be parked. Also, !! 2898 bool
1958 address auth and the late CPU has t <<
1959 but with the feature disabled. On s <<
1960 not be selected. <<
1961 <<
1962 config ARM64_PTR_AUTH_KERNEL <<
1963 bool "Use pointer authentication for <<
1964 default y <<
1965 depends on ARM64_PTR_AUTH <<
1966 depends on (CC_HAS_SIGN_RETURN_ADDRES <<
1967 # Modern compilers insert a .note.gnu <<
1968 # which is only understood by binutil <<
1969 depends on LD_IS_LLD || LD_VERSION >= <<
1970 depends on !CC_IS_CLANG || AS_HAS_CFI <<
1971 depends on (!FUNCTION_GRAPH_TRACER || <<
1972 help <<
1973 If the compiler supports the -mbran <<
1974 -msign-return-address flag (e.g. GC <<
1975 will cause the kernel itself to be <<
1976 protection. In this case, and if th <<
1977 support pointer authentication, the <<
1978 disabled with minimal loss of prote <<
1979 2899
1980 This feature works with FUNCTION_GR !! 2900 config SYS_SUPPORTS_MIPS_CMP
1981 DYNAMIC_FTRACE_WITH_ARGS is enabled !! 2901 bool
1982 2902
1983 config CC_HAS_BRANCH_PROT_PAC_RET !! 2903 config SYS_SUPPORTS_MIPS_CPS
1984 # GCC 9 or later, clang 8 or later !! 2904 bool
1985 def_bool $(cc-option,-mbranch-protect <<
1986 2905
1987 config CC_HAS_SIGN_RETURN_ADDRESS !! 2906 config SYS_SUPPORTS_SMP
1988 # GCC 7, 8 !! 2907 bool
1989 def_bool $(cc-option,-msign-return-ad <<
1990 2908
1991 config AS_HAS_ARMV8_3 !! 2909 config NR_CPUS_DEFAULT_4
1992 def_bool $(cc-option,-Wa$(comma)-marc !! 2910 bool
1993 2911
1994 config AS_HAS_CFI_NEGATE_RA_STATE !! 2912 config NR_CPUS_DEFAULT_8
1995 def_bool $(as-instr,.cfi_startproc\n. !! 2913 bool
1996 2914
1997 config AS_HAS_LDAPR !! 2915 config NR_CPUS_DEFAULT_16
1998 def_bool $(as-instr,.arch_extension r !! 2916 bool
1999 2917
2000 endmenu # "ARMv8.3 architectural features" !! 2918 config NR_CPUS_DEFAULT_32
>> 2919 bool
2001 2920
2002 menu "ARMv8.4 architectural features" !! 2921 config NR_CPUS_DEFAULT_64
>> 2922 bool
2003 2923
2004 config ARM64_AMU_EXTN !! 2924 config NR_CPUS
2005 bool "Enable support for the Activity !! 2925 int "Maximum number of CPUs (2-256)"
2006 default y !! 2926 range 2 256
2007 help !! 2927 depends on SMP
2008 The activity monitors extension is !! 2928 default "4" if NR_CPUS_DEFAULT_4
2009 by the ARMv8.4 CPU architecture. Th !! 2929 default "8" if NR_CPUS_DEFAULT_8
2010 of the activity monitors architectu !! 2930 default "16" if NR_CPUS_DEFAULT_16
>> 2931 default "32" if NR_CPUS_DEFAULT_32
>> 2932 default "64" if NR_CPUS_DEFAULT_64
>> 2933 help
>> 2934 This allows you to specify the maximum number of CPUs which this
>> 2935 kernel will support. The maximum supported value is 32 for 32-bit
>> 2936 kernel and 64 for 64-bit kernels; the minimum value which makes
>> 2937 sense is 1 for Qemu (useful only for kernel debugging purposes)
>> 2938 and 2 for all others.
>> 2939
>> 2940 This is purely to save memory - each supported CPU adds
>> 2941 approximately eight kilobytes to the kernel image. For best
>> 2942 performance should round up your number of processors to the next
>> 2943 power of two.
2011 2944
2012 To enable the use of this extension !! 2945 config MIPS_PERF_SHARED_TC_COUNTERS
>> 2946 bool
2013 2947
2014 Note that for architectural reasons !! 2948 config MIPS_NR_CPU_NR_MAP_1024
2015 support when running on CPUs that p !! 2949 bool
2016 extension. The required support is <<
2017 * Version 1.5 and later of the AR <<
2018 2950
2019 For kernels that have this configur !! 2951 config MIPS_NR_CPU_NR_MAP
2020 firmware, you may need to say N her !! 2952 int
2021 Otherwise you may experience firmwa !! 2953 depends on SMP
2022 accessing the counter registers. Ev !! 2954 default 1024 if MIPS_NR_CPU_NR_MAP_1024
2023 symptoms, the values returned by th !! 2955 default NR_CPUS if !MIPS_NR_CPU_NR_MAP_1024
2024 correctly reflect reality. Most com <<
2025 indicating that the counter is not <<
2026 2956
2027 config AS_HAS_ARMV8_4 !! 2957 #
2028 def_bool $(cc-option,-Wa$(comma)-marc !! 2958 # Timer Interrupt Frequency Configuration
>> 2959 #
2029 2960
2030 config ARM64_TLB_RANGE !! 2961 choice
2031 bool "Enable support for tlbi range f !! 2962 prompt "Timer frequency"
2032 default y !! 2963 default HZ_250
2033 depends on AS_HAS_ARMV8_4 <<
2034 help 2964 help
2035 ARMv8.4-TLBI provides TLBI invalida !! 2965 Allows the configuration of the timer frequency.
2036 range of input addresses. <<
2037 2966
2038 The feature introduces new assembly !! 2967 config HZ_24
2039 support when binutils >= 2.30. !! 2968 bool "24 HZ" if SYS_SUPPORTS_24HZ || SYS_SUPPORTS_ARBIT_HZ
2040 2969
2041 endmenu # "ARMv8.4 architectural features" !! 2970 config HZ_48
>> 2971 bool "48 HZ" if SYS_SUPPORTS_48HZ || SYS_SUPPORTS_ARBIT_HZ
2042 2972
2043 menu "ARMv8.5 architectural features" !! 2973 config HZ_100
>> 2974 bool "100 HZ" if SYS_SUPPORTS_100HZ || SYS_SUPPORTS_ARBIT_HZ
2044 2975
2045 config AS_HAS_ARMV8_5 !! 2976 config HZ_128
2046 def_bool $(cc-option,-Wa$(comma)-marc !! 2977 bool "128 HZ" if SYS_SUPPORTS_128HZ || SYS_SUPPORTS_ARBIT_HZ
2047 2978
2048 config ARM64_BTI !! 2979 config HZ_250
2049 bool "Branch Target Identification su !! 2980 bool "250 HZ" if SYS_SUPPORTS_250HZ || SYS_SUPPORTS_ARBIT_HZ
2050 default y <<
2051 help <<
2052 Branch Target Identification (part <<
2053 provides a mechanism to limit the s <<
2054 branch instructions such as BR or B <<
2055 2981
2056 To make use of BTI on CPUs that sup !! 2982 config HZ_256
>> 2983 bool "256 HZ" if SYS_SUPPORTS_256HZ || SYS_SUPPORTS_ARBIT_HZ
2057 2984
2058 BTI is intended to provide compleme !! 2985 config HZ_1000
2059 flow integrity protection mechanism !! 2986 bool "1000 HZ" if SYS_SUPPORTS_1000HZ || SYS_SUPPORTS_ARBIT_HZ
2060 authentication mechanism provided a <<
2061 For this reason, it does not make s <<
2062 also enabling support for pointer a <<
2063 enabling this option you should als <<
2064 2987
2065 Userspace binaries must also be spe !! 2988 config HZ_1024
2066 this mechanism. If you say N here !! 2989 bool "1024 HZ" if SYS_SUPPORTS_1024HZ || SYS_SUPPORTS_ARBIT_HZ
2067 BTI, such binaries can still run, b <<
2068 enforcement of branch destinations. <<
2069 2990
2070 config ARM64_BTI_KERNEL !! 2991 endchoice
2071 bool "Use Branch Target Identificatio <<
2072 default y <<
2073 depends on ARM64_BTI <<
2074 depends on ARM64_PTR_AUTH_KERNEL <<
2075 depends on CC_HAS_BRANCH_PROT_PAC_RET <<
2076 # https://gcc.gnu.org/bugzilla/show_b <<
2077 depends on !CC_IS_GCC || GCC_VERSION <<
2078 # https://gcc.gnu.org/bugzilla/show_b <<
2079 depends on !CC_IS_GCC <<
2080 depends on (!FUNCTION_GRAPH_TRACER || <<
2081 help <<
2082 Build the kernel with Branch Target <<
2083 and enable enforcement of this for <<
2084 is enabled and the system supports <<
2085 modular code must have BTI enabled. <<
2086 <<
2087 config CC_HAS_BRANCH_PROT_PAC_RET_BTI <<
2088 # GCC 9 or later, clang 8 or later <<
2089 def_bool $(cc-option,-mbranch-protect <<
2090 2992
2091 config ARM64_E0PD !! 2993 config SYS_SUPPORTS_24HZ
2092 bool "Enable support for E0PD" !! 2994 bool
2093 default y <<
2094 help <<
2095 E0PD (part of the ARMv8.5 extension <<
2096 that EL0 accesses made via TTBR1 al <<
2097 providing similar benefits to KASLR <<
2098 with lower overhead and without dis <<
2099 kernel memory such as SPE. <<
2100 2995
2101 This option enables E0PD for TTBR1 !! 2996 config SYS_SUPPORTS_48HZ
>> 2997 bool
2102 2998
2103 config ARM64_AS_HAS_MTE !! 2999 config SYS_SUPPORTS_100HZ
2104 # Initial support for MTE went in bin !! 3000 bool
2105 # ".arch armv8.5-a+memtag" below. How <<
2106 # as a late addition to the final arc <<
2107 # is only supported in the newer 2.32 <<
2108 # versions, hence the extra "stgm" in <<
2109 def_bool $(as-instr,.arch armv8.5-a+m <<
2110 3001
2111 config ARM64_MTE !! 3002 config SYS_SUPPORTS_128HZ
2112 bool "Memory Tagging Extension suppor !! 3003 bool
2113 default y <<
2114 depends on ARM64_AS_HAS_MTE && ARM64_ <<
2115 depends on AS_HAS_ARMV8_5 <<
2116 depends on AS_HAS_LSE_ATOMICS <<
2117 # Required for tag checking in the ua <<
2118 depends on ARM64_PAN <<
2119 select ARCH_HAS_SUBPAGE_FAULTS <<
2120 select ARCH_USES_HIGH_VMA_FLAGS <<
2121 select ARCH_USES_PG_ARCH_2 <<
2122 select ARCH_USES_PG_ARCH_3 <<
2123 help <<
2124 Memory Tagging (part of the ARMv8.5 <<
2125 architectural support for run-time, <<
2126 various classes of memory error to <<
2127 to eliminate vulnerabilities arisin <<
2128 languages. <<
2129 3004
2130 This option enables the support for !! 3005 config SYS_SUPPORTS_250HZ
2131 Extension at EL0 (i.e. for userspac !! 3006 bool
2132 3007
2133 Selecting this option allows the fe !! 3008 config SYS_SUPPORTS_256HZ
2134 runtime. Any secondary CPU not impl !! 3009 bool
2135 not be allowed a late bring-up. <<
2136 3010
2137 Userspace binaries that want to use !! 3011 config SYS_SUPPORTS_1000HZ
2138 explicitly opt in. The mechanism fo !! 3012 bool
2139 described in: <<
2140 3013
2141 Documentation/arch/arm64/memory-tag !! 3014 config SYS_SUPPORTS_1024HZ
>> 3015 bool
2142 3016
2143 endmenu # "ARMv8.5 architectural features" !! 3017 config SYS_SUPPORTS_ARBIT_HZ
>> 3018 bool
>> 3019 default y if !SYS_SUPPORTS_24HZ && \
>> 3020 !SYS_SUPPORTS_48HZ && \
>> 3021 !SYS_SUPPORTS_100HZ && \
>> 3022 !SYS_SUPPORTS_128HZ && \
>> 3023 !SYS_SUPPORTS_250HZ && \
>> 3024 !SYS_SUPPORTS_256HZ && \
>> 3025 !SYS_SUPPORTS_1000HZ && \
>> 3026 !SYS_SUPPORTS_1024HZ
2144 3027
2145 menu "ARMv8.7 architectural features" !! 3028 config HZ
>> 3029 int
>> 3030 default 24 if HZ_24
>> 3031 default 48 if HZ_48
>> 3032 default 100 if HZ_100
>> 3033 default 128 if HZ_128
>> 3034 default 250 if HZ_250
>> 3035 default 256 if HZ_256
>> 3036 default 1000 if HZ_1000
>> 3037 default 1024 if HZ_1024
>> 3038
>> 3039 config SCHED_HRTICK
>> 3040 def_bool HIGH_RES_TIMERS
>> 3041
>> 3042 config KEXEC
>> 3043 bool "Kexec system call"
>> 3044 select KEXEC_CORE
>> 3045 help
>> 3046 kexec is a system call that implements the ability to shutdown your
>> 3047 current kernel, and to start another kernel. It is like a reboot
>> 3048 but it is independent of the system firmware. And like a reboot
>> 3049 you can start any kernel with it, not just Linux.
>> 3050
>> 3051 The name comes from the similarity to the exec system call.
>> 3052
>> 3053 It is an ongoing process to be certain the hardware in a machine
>> 3054 is properly shutdown, so do not be surprised if this code does not
>> 3055 initially work for you. As of this writing the exact hardware
>> 3056 interface is strongly in flux, so no good recommendation can be
>> 3057 made.
>> 3058
>> 3059 config CRASH_DUMP
>> 3060 bool "Kernel crash dumps"
>> 3061 help
>> 3062 Generate crash dump after being started by kexec.
>> 3063 This should be normally only set in special crash dump kernels
>> 3064 which are loaded in the main kernel with kexec-tools into
>> 3065 a specially reserved region and then later executed after
>> 3066 a crash by kdump/kexec. The crash dump kernel must be compiled
>> 3067 to a memory address not used by the main kernel or firmware using
>> 3068 PHYSICAL_START.
>> 3069
>> 3070 config PHYSICAL_START
>> 3071 hex "Physical address where the kernel is loaded"
>> 3072 default "0xffffffff84000000"
>> 3073 depends on CRASH_DUMP
>> 3074 help
>> 3075 This gives the CKSEG0 or KSEG0 address where the kernel is loaded.
>> 3076 If you plan to use kernel for capturing the crash dump change
>> 3077 this value to start of the reserved region (the "X" value as
>> 3078 specified in the "crashkernel=YM@XM" command line boot parameter
>> 3079 passed to the panic-ed kernel).
>> 3080
>> 3081 config MIPS_O32_FP64_SUPPORT
>> 3082 bool "Support for O32 binaries using 64-bit FP" if !CPU_MIPSR6
>> 3083 depends on 32BIT || MIPS32_O32
>> 3084 help
>> 3085 When this is enabled, the kernel will support use of 64-bit floating
>> 3086 point registers with binaries using the O32 ABI along with the
>> 3087 EF_MIPS_FP64 ELF header flag (typically built with -mfp64). On
>> 3088 32-bit MIPS systems this support is at the cost of increasing the
>> 3089 size and complexity of the compiled FPU emulator. Thus if you are
>> 3090 running a MIPS32 system and know that none of your userland binaries
>> 3091 will require 64-bit floating point, you may wish to reduce the size
>> 3092 of your kernel & potentially improve FP emulation performance by
>> 3093 saying N here.
>> 3094
>> 3095 Although binutils currently supports use of this flag the details
>> 3096 concerning its effect upon the O32 ABI in userland are still being
>> 3097 worked on. In order to avoid userland becoming dependent upon current
>> 3098 behaviour before the details have been finalised, this option should
>> 3099 be considered experimental and only enabled by those working upon
>> 3100 said details.
2146 3101
2147 config ARM64_EPAN !! 3102 If unsure, say N.
2148 bool "Enable support for Enhanced Pri <<
2149 default y <<
2150 depends on ARM64_PAN <<
2151 help <<
2152 Enhanced Privileged Access Never (E <<
2153 Access Never to be used with Execut <<
2154 3103
2155 The feature is detected at runtime, !! 3104 config USE_OF
2156 if the cpu does not implement the f !! 3105 bool
2157 endmenu # "ARMv8.7 architectural features" !! 3106 select OF
>> 3107 select OF_EARLY_FLATTREE
>> 3108 select IRQ_DOMAIN
2158 3109
2159 menu "ARMv8.9 architectural features" !! 3110 config UHI_BOOT
>> 3111 bool
2160 3112
2161 config ARM64_POE !! 3113 config BUILTIN_DTB
2162 prompt "Permission Overlay Extension" !! 3114 bool
2163 def_bool y <<
2164 select ARCH_USES_HIGH_VMA_FLAGS <<
2165 select ARCH_HAS_PKEYS <<
2166 help <<
2167 The Permission Overlay Extension is <<
2168 Protection Keys. Memory Protection <<
2169 enforcing page-based protections, b <<
2170 of the page tables when an applicat <<
2171 3115
2172 For details, see Documentation/core !! 3116 choice
>> 3117 prompt "Kernel appended dtb support" if USE_OF
>> 3118 default MIPS_NO_APPENDED_DTB
2173 3119
2174 If unsure, say y. !! 3120 config MIPS_NO_APPENDED_DTB
>> 3121 bool "None"
>> 3122 help
>> 3123 Do not enable appended dtb support.
>> 3124
>> 3125 config MIPS_ELF_APPENDED_DTB
>> 3126 bool "vmlinux"
>> 3127 help
>> 3128 With this option, the boot code will look for a device tree binary
>> 3129 DTB) included in the vmlinux ELF section .appended_dtb. By default
>> 3130 it is empty and the DTB can be appended using binutils command
>> 3131 objcopy:
>> 3132
>> 3133 objcopy --update-section .appended_dtb=<filename>.dtb vmlinux
>> 3134
>> 3135 This is meant as a backward compatibility convenience for those
>> 3136 systems with a bootloader that can't be upgraded to accommodate
>> 3137 the documented boot protocol using a device tree.
>> 3138
>> 3139 config MIPS_RAW_APPENDED_DTB
>> 3140 bool "vmlinux.bin or vmlinuz.bin"
>> 3141 help
>> 3142 With this option, the boot code will look for a device tree binary
>> 3143 DTB) appended to raw vmlinux.bin or vmlinuz.bin.
>> 3144 (e.g. cat vmlinux.bin <filename>.dtb > vmlinux_w_dtb).
>> 3145
>> 3146 This is meant as a backward compatibility convenience for those
>> 3147 systems with a bootloader that can't be upgraded to accommodate
>> 3148 the documented boot protocol using a device tree.
>> 3149
>> 3150 Beware that there is very little in terms of protection against
>> 3151 this option being confused by leftover garbage in memory that might
>> 3152 look like a DTB header after a reboot if no actual DTB is appended
>> 3153 to vmlinux.bin. Do not leave this option active in a production kernel
>> 3154 if you don't intend to always append a DTB.
>> 3155 endchoice
2175 3156
2176 config ARCH_PKEY_BITS !! 3157 choice
2177 int !! 3158 prompt "Kernel command line type" if !CMDLINE_OVERRIDE
2178 default 3 !! 3159 default MIPS_CMDLINE_FROM_DTB if USE_OF && !ATH79 && !MACH_INGENIC && \
>> 3160 !MACH_LOONGSON64 && !MIPS_MALTA && \
>> 3161 !CAVIUM_OCTEON_SOC
>> 3162 default MIPS_CMDLINE_FROM_BOOTLOADER
>> 3163
>> 3164 config MIPS_CMDLINE_FROM_DTB
>> 3165 depends on USE_OF
>> 3166 bool "Dtb kernel arguments if available"
>> 3167
>> 3168 config MIPS_CMDLINE_DTB_EXTEND
>> 3169 depends on USE_OF
>> 3170 bool "Extend dtb kernel arguments with bootloader arguments"
>> 3171
>> 3172 config MIPS_CMDLINE_FROM_BOOTLOADER
>> 3173 bool "Bootloader kernel arguments if available"
>> 3174
>> 3175 config MIPS_CMDLINE_BUILTIN_EXTEND
>> 3176 depends on CMDLINE_BOOL
>> 3177 bool "Extend builtin kernel arguments with bootloader arguments"
>> 3178 endchoice
2179 3179
2180 endmenu # "ARMv8.9 architectural features" !! 3180 endmenu
2181 3181
2182 config ARM64_SVE !! 3182 config LOCKDEP_SUPPORT
2183 bool "ARM Scalable Vector Extension s !! 3183 bool
2184 default y 3184 default y
2185 help <<
2186 The Scalable Vector Extension (SVE) <<
2187 execution state which complements a <<
2188 of the base architecture to support <<
2189 additional vectorisation opportunit <<
2190 <<
2191 To enable use of this extension on <<
2192 3185
2193 On CPUs that support the SVE2 exten !! 3186 config STACKTRACE_SUPPORT
2194 those too. !! 3187 bool
>> 3188 default y
2195 3189
2196 Note that for architectural reasons !! 3190 config PGTABLE_LEVELS
2197 support when running on SVE capable !! 3191 int
2198 is present in: !! 3192 default 4 if PAGE_SIZE_4KB && MIPS_VA_BITS_48
>> 3193 default 3 if 64BIT && !PAGE_SIZE_64KB
>> 3194 default 2
2199 3195
2200 * version 1.5 and later of the AR !! 3196 config MIPS_AUTO_PFN_OFFSET
2201 * the AArch64 boot wrapper since !! 3197 bool
2202 ("bootwrapper: SVE: Enable SVE <<
2203 3198
2204 For other firmware implementations, !! 3199 menu "Bus options (PCI, PCMCIA, EISA, ISA, TC)"
2205 or vendor. <<
2206 3200
2207 If you need the kernel to boot on S !! 3201 config PCI_DRIVERS_GENERIC
2208 firmware, you may need to say N her !! 3202 select PCI_DOMAINS_GENERIC if PCI
2209 fixed. Otherwise, you may experien !! 3203 bool
2210 booting the kernel. If unsure and <<
2211 symptoms, you should assume that it <<
2212 3204
2213 config ARM64_SME !! 3205 config PCI_DRIVERS_LEGACY
2214 bool "ARM Scalable Matrix Extension s !! 3206 def_bool !PCI_DRIVERS_GENERIC
2215 default y !! 3207 select NO_GENERIC_PCI_IOPORT_MAP
2216 depends on ARM64_SVE !! 3208 select PCI_DOMAINS if PCI
2217 depends on BROKEN <<
2218 help <<
2219 The Scalable Matrix Extension (SME) <<
2220 execution state which utilises a su <<
2221 instruction set, together with the <<
2222 register state capable of holding t <<
2223 enable various matrix operations. <<
2224 3209
2225 config ARM64_PSEUDO_NMI !! 3210 #
2226 bool "Support for NMI-like interrupts !! 3211 # ISA support is now enabled via select. Too many systems still have the one
2227 select ARM_GIC_V3 !! 3212 # or other ISA chip on the board that users don't know about so don't expect
2228 help !! 3213 # users to choose the right thing ...
2229 Adds support for mimicking Non-Mask !! 3214 #
2230 GIC interrupt priority. This suppor !! 3215 config ISA
2231 ARM GIC. !! 3216 bool
2232 3217
2233 This high priority configuration fo !! 3218 config TC
2234 explicitly enabled by setting the k !! 3219 bool "TURBOchannel support"
2235 "irqchip.gicv3_pseudo_nmi" to 1. !! 3220 depends on MACH_DECSTATION
>> 3221 help
>> 3222 TURBOchannel is a DEC (now Compaq (now HP)) bus for Alpha and MIPS
>> 3223 processors. TURBOchannel programming specifications are available
>> 3224 at:
>> 3225 <ftp://ftp.hp.com/pub/alphaserver/archive/triadd/>
>> 3226 and:
>> 3227 <http://www.computer-refuge.org/classiccmp/ftp.digital.com/pub/DEC/TriAdd/>
>> 3228 Linux driver support status is documented at:
>> 3229 <http://www.linux-mips.org/wiki/DECstation>
2236 3230
2237 If unsure, say N !! 3231 config MMU
>> 3232 bool
>> 3233 default y
2238 3234
2239 if ARM64_PSEUDO_NMI !! 3235 config ARCH_MMAP_RND_BITS_MIN
2240 config ARM64_DEBUG_PRIORITY_MASKING !! 3236 default 12 if 64BIT
2241 bool "Debug interrupt priority maskin !! 3237 default 8
2242 help <<
2243 This adds runtime checks to functio <<
2244 interrupts when using priority mask <<
2245 the validity of ICC_PMR_EL1 when ca <<
2246 3238
2247 If unsure, say N !! 3239 config ARCH_MMAP_RND_BITS_MAX
2248 endif # ARM64_PSEUDO_NMI !! 3240 default 18 if 64BIT
>> 3241 default 15
2249 3242
2250 config RELOCATABLE !! 3243 config ARCH_MMAP_RND_COMPAT_BITS_MIN
2251 bool "Build a relocatable kernel imag !! 3244 default 8
2252 select ARCH_HAS_RELR <<
2253 default y <<
2254 help <<
2255 This builds the kernel as a Positio <<
2256 which retains all relocation metada <<
2257 kernel binary at runtime to a diffe <<
2258 address it was linked at. <<
2259 Since AArch64 uses the RELA relocat <<
2260 relocation pass at runtime even if <<
2261 same address it was linked at. <<
2262 3245
2263 config RANDOMIZE_BASE !! 3246 config ARCH_MMAP_RND_COMPAT_BITS_MAX
2264 bool "Randomize the address of the ke !! 3247 default 15
2265 select RELOCATABLE <<
2266 help <<
2267 Randomizes the virtual address at w <<
2268 loaded, as a security feature that <<
2269 relying on knowledge of the locatio <<
2270 <<
2271 It is the bootloader's job to provi <<
2272 random u64 value in /chosen/kaslr-s <<
2273 <<
2274 When booting via the UEFI stub, it <<
2275 EFI_RNG_PROTOCOL implementation (if <<
2276 to the kernel proper. In addition, <<
2277 location of the kernel Image as wel <<
2278 3248
2279 If unsure, say N. !! 3249 config I8253
>> 3250 bool
>> 3251 select CLKSRC_I8253
>> 3252 select CLKEVT_I8253
>> 3253 select MIPS_EXTERNAL_TIMER
2280 3254
2281 config RANDOMIZE_MODULE_REGION_FULL !! 3255 config ZONE_DMA
2282 bool "Randomize the module region ove !! 3256 bool
2283 depends on RANDOMIZE_BASE <<
2284 default y <<
2285 help <<
2286 Randomizes the location of the modu <<
2287 covering the core kernel. This way, <<
2288 to leak information about the locat <<
2289 but it does imply that function cal <<
2290 kernel will need to be resolved via <<
2291 <<
2292 When this option is not set, the mo <<
2293 a limited range that contains the [ <<
2294 core kernel, so branch relocations <<
2295 the region is exhausted. In this pa <<
2296 exhaustion, modules might be able t <<
2297 3257
2298 config CC_HAVE_STACKPROTECTOR_SYSREG !! 3258 config ZONE_DMA32
2299 def_bool $(cc-option,-mstack-protecto !! 3259 bool
2300 3260
2301 config STACKPROTECTOR_PER_TASK !! 3261 endmenu
2302 def_bool y <<
2303 depends on STACKPROTECTOR && CC_HAVE_ <<
2304 3262
2305 config UNWIND_PATCH_PAC_INTO_SCS !! 3263 config TRAD_SIGNALS
2306 bool "Enable shadow call stack dynami !! 3264 bool
2307 # needs Clang with https://github.com <<
2308 depends on CC_IS_CLANG && CLANG_VERSI <<
2309 depends on ARM64_PTR_AUTH_KERNEL && C <<
2310 depends on SHADOW_CALL_STACK <<
2311 select UNWIND_TABLES <<
2312 select DYNAMIC_SCS <<
2313 <<
2314 config ARM64_CONTPTE <<
2315 bool "Contiguous PTE mappings for use <<
2316 depends on TRANSPARENT_HUGEPAGE <<
2317 default y <<
2318 help <<
2319 When enabled, user mappings are con <<
2320 bit, for any mappings that meet the <<
2321 This reduces TLB pressure and impro <<
2322 <<
2323 endmenu # "Kernel Features" <<
2324 <<
2325 menu "Boot options" <<
2326 <<
2327 config ARM64_ACPI_PARKING_PROTOCOL <<
2328 bool "Enable support for the ARM64 AC <<
2329 depends on ACPI <<
2330 help <<
2331 Enable support for the ARM64 ACPI p <<
2332 the kernel will not allow booting t <<
2333 protocol even if the corresponding <<
2334 MADT table. <<
2335 <<
2336 config CMDLINE <<
2337 string "Default kernel command string <<
2338 default "" <<
2339 help <<
2340 Provide a set of default command-li <<
2341 entering them here. As a minimum, y <<
2342 root device (e.g. root=/dev/nfs). <<
2343 3265
2344 choice !! 3266 config MIPS32_COMPAT
2345 prompt "Kernel command line type" !! 3267 bool
2346 depends on CMDLINE != "" <<
2347 default CMDLINE_FROM_BOOTLOADER <<
2348 help <<
2349 Choose how the kernel will handle t <<
2350 command line string. <<
2351 <<
2352 config CMDLINE_FROM_BOOTLOADER <<
2353 bool "Use bootloader kernel arguments <<
2354 help <<
2355 Uses the command-line options passe <<
2356 the boot loader doesn't provide any <<
2357 string provided in CMDLINE will be <<
2358 <<
2359 config CMDLINE_FORCE <<
2360 bool "Always use the default kernel c <<
2361 help <<
2362 Always use the default kernel comma <<
2363 loader passes other arguments to th <<
2364 This is useful if you cannot or don <<
2365 command-line options your boot load <<
2366 3268
2367 endchoice !! 3269 config COMPAT
>> 3270 bool
2368 3271
2369 config EFI_STUB !! 3272 config SYSVIPC_COMPAT
2370 bool 3273 bool
2371 3274
2372 config EFI !! 3275 config MIPS32_O32
2373 bool "UEFI runtime support" !! 3276 bool "Kernel support for o32 binaries"
2374 depends on OF && !CPU_BIG_ENDIAN !! 3277 depends on 64BIT
2375 depends on KERNEL_MODE_NEON !! 3278 select ARCH_WANT_OLD_COMPAT_IPC
2376 select ARCH_SUPPORTS_ACPI !! 3279 select COMPAT
2377 select LIBFDT !! 3280 select MIPS32_COMPAT
2378 select UCS2_STRING !! 3281 select SYSVIPC_COMPAT if SYSVIPC
2379 select EFI_PARAMS_FROM_FDT !! 3282 help
2380 select EFI_RUNTIME_WRAPPERS !! 3283 Select this option if you want to run o32 binaries. These are pure
2381 select EFI_STUB !! 3284 32-bit binaries as used by the 32-bit Linux/MIPS port. Most of
2382 select EFI_GENERIC_STUB !! 3285 existing binaries are in this format.
2383 imply IMA_SECURE_AND_OR_TRUSTED_BOOT <<
2384 default y <<
2385 help <<
2386 This option provides support for ru <<
2387 by UEFI firmware (such as non-volat <<
2388 clock, and platform reset). A UEFI <<
2389 allow the kernel to be booted as an <<
2390 is only useful on systems that have <<
2391 <<
2392 config COMPRESSED_INSTALL <<
2393 bool "Install compressed image by def <<
2394 help <<
2395 This makes the regular "make instal <<
2396 image we built, not the legacy unco <<
2397 <<
2398 You can check that a compressed ima <<
2399 "make zinstall" first, and verifyin <<
2400 in your environment before making " <<
2401 you. <<
2402 3286
2403 config DMI !! 3287 If unsure, say Y.
2404 bool "Enable support for SMBIOS (DMI) <<
2405 depends on EFI <<
2406 default y <<
2407 help <<
2408 This enables SMBIOS/DMI feature for <<
2409 3288
2410 This option is only useful on syste !! 3289 config MIPS32_N32
2411 However, even with this option, the !! 3290 bool "Kernel support for n32 binaries"
2412 continue to boot on existing non-UE !! 3291 depends on 64BIT
>> 3292 select ARCH_WANT_COMPAT_IPC_PARSE_VERSION
>> 3293 select COMPAT
>> 3294 select MIPS32_COMPAT
>> 3295 select SYSVIPC_COMPAT if SYSVIPC
>> 3296 help
>> 3297 Select this option if you want to run n32 binaries. These are
>> 3298 64-bit binaries using 32-bit quantities for addressing and certain
>> 3299 data that would normally be 64-bit. They are used in special
>> 3300 cases.
2413 3301
2414 endmenu # "Boot options" !! 3302 If unsure, say N.
2415 3303
2416 menu "Power management options" !! 3304 config BINFMT_ELF32
>> 3305 bool
>> 3306 default y if MIPS32_O32 || MIPS32_N32
>> 3307 select ELFCORE
2417 3308
2418 source "kernel/power/Kconfig" !! 3309 menu "Power management options"
2419 3310
2420 config ARCH_HIBERNATION_POSSIBLE 3311 config ARCH_HIBERNATION_POSSIBLE
2421 def_bool y 3312 def_bool y
2422 depends on CPU_PM !! 3313 depends on SYS_SUPPORTS_HOTPLUG_CPU || !SMP
2423 <<
2424 config ARCH_HIBERNATION_HEADER <<
2425 def_bool y <<
2426 depends on HIBERNATION <<
2427 3314
2428 config ARCH_SUSPEND_POSSIBLE 3315 config ARCH_SUSPEND_POSSIBLE
2429 def_bool y 3316 def_bool y
>> 3317 depends on SYS_SUPPORTS_HOTPLUG_CPU || !SMP
2430 3318
2431 endmenu # "Power management options" !! 3319 source "kernel/power/Kconfig"
2432 3320
2433 menu "CPU Power Management" !! 3321 endmenu
2434 3322
2435 source "drivers/cpuidle/Kconfig" !! 3323 config MIPS_EXTERNAL_TIMER
>> 3324 bool
>> 3325
>> 3326 menu "CPU Power Management"
2436 3327
>> 3328 if CPU_SUPPORTS_CPUFREQ && MIPS_EXTERNAL_TIMER
2437 source "drivers/cpufreq/Kconfig" 3329 source "drivers/cpufreq/Kconfig"
>> 3330 endif
>> 3331
>> 3332 source "drivers/cpuidle/Kconfig"
2438 3333
2439 endmenu # "CPU Power Management" !! 3334 endmenu
2440 3335
2441 source "drivers/acpi/Kconfig" !! 3336 source "drivers/firmware/Kconfig"
2442 3337
2443 source "arch/arm64/kvm/Kconfig" !! 3338 source "arch/mips/kvm/Kconfig"
2444 3339
>> 3340 source "arch/mips/vdso/Kconfig"
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