1 # SPDX-License-Identifier: GPL-2.0-only !! 1 # SPDX-License-Identifier: GPL-2.0
2 config ARM64 !! 2 config MIPS
3 def_bool y !! 3 bool
4 select ACPI_APMT if ACPI !! 4 default y
5 select ACPI_CCA_REQUIRED if ACPI !! 5 select ARCH_32BIT_OFF_T if !64BIT
6 select ACPI_GENERIC_GSI if ACPI !! 6 select ARCH_BINFMT_ELF_STATE if MIPS_FP_SUPPORT
7 select ACPI_GTDT if ACPI <<
8 select ACPI_HOTPLUG_CPU if ACPI_PROCES <<
9 select ACPI_IORT if ACPI <<
10 select ACPI_REDUCED_HARDWARE_ONLY if A <<
11 select ACPI_MCFG if (ACPI && PCI) <<
12 select ACPI_SPCR_TABLE if ACPI <<
13 select ACPI_PPTT if ACPI <<
14 select ARCH_HAS_DEBUG_WX <<
15 select ARCH_BINFMT_ELF_EXTRA_PHDRS <<
16 select ARCH_BINFMT_ELF_STATE <<
17 select ARCH_CORRECT_STACKTRACE_ON_KRET <<
18 select ARCH_ENABLE_HUGEPAGE_MIGRATION <<
19 select ARCH_ENABLE_MEMORY_HOTPLUG <<
20 select ARCH_ENABLE_MEMORY_HOTREMOVE <<
21 select ARCH_ENABLE_SPLIT_PMD_PTLOCK if <<
22 select ARCH_ENABLE_THP_MIGRATION if TR <<
23 select ARCH_HAS_CACHE_LINE_SIZE <<
24 select ARCH_HAS_CURRENT_STACK_POINTER <<
25 select ARCH_HAS_DEBUG_VIRTUAL <<
26 select ARCH_HAS_DEBUG_VM_PGTABLE <<
27 select ARCH_HAS_DMA_OPS if XEN <<
28 select ARCH_HAS_DMA_PREP_COHERENT <<
29 select ARCH_HAS_ACPI_TABLE_UPGRADE if <<
30 select ARCH_HAS_FAST_MULTIPLIER <<
31 select ARCH_HAS_FORTIFY_SOURCE 7 select ARCH_HAS_FORTIFY_SOURCE
32 select ARCH_HAS_GCOV_PROFILE_ALL <<
33 select ARCH_HAS_GIGANTIC_PAGE <<
34 select ARCH_HAS_KCOV 8 select ARCH_HAS_KCOV
35 select ARCH_HAS_KERNEL_FPU_SUPPORT if !! 9 select ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE if !EVA
36 select ARCH_HAS_KEEPINITRD !! 10 select ARCH_HAS_PTE_SPECIAL if !(32BIT && CPU_HAS_RIXI)
37 select ARCH_HAS_MEMBARRIER_SYNC_CORE <<
38 select ARCH_HAS_MEM_ENCRYPT <<
39 select ARCH_HAS_NMI_SAFE_THIS_CPU_OPS <<
40 select ARCH_HAS_NON_OVERLAPPING_ADDRES <<
41 select ARCH_HAS_PTE_DEVMAP <<
42 select ARCH_HAS_PTE_SPECIAL <<
43 select ARCH_HAS_HW_PTE_YOUNG <<
44 select ARCH_HAS_SETUP_DMA_OPS <<
45 select ARCH_HAS_SET_DIRECT_MAP <<
46 select ARCH_HAS_SET_MEMORY <<
47 select ARCH_STACKWALK <<
48 select ARCH_HAS_STRICT_KERNEL_RWX <<
49 select ARCH_HAS_STRICT_MODULE_RWX <<
50 select ARCH_HAS_SYNC_DMA_FOR_DEVICE <<
51 select ARCH_HAS_SYNC_DMA_FOR_CPU <<
52 select ARCH_HAS_SYSCALL_WRAPPER <<
53 select ARCH_HAS_TICK_BROADCAST if GENE 11 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
54 select ARCH_HAS_ZONE_DMA_SET if EXPERT !! 12 select ARCH_HAS_UBSAN_SANITIZE_ALL
55 select ARCH_HAVE_ELF_PROT !! 13 select ARCH_HAS_GCOV_PROFILE_ALL
56 select ARCH_HAVE_NMI_SAFE_CMPXCHG !! 14 select ARCH_KEEP_MEMBLOCK if DEBUG_KERNEL
57 select ARCH_HAVE_TRACE_MMIO_ACCESS !! 15 select ARCH_SUPPORTS_UPROBES
58 select ARCH_INLINE_READ_LOCK if !PREEM !! 16 select ARCH_USE_BUILTIN_BSWAP
59 select ARCH_INLINE_READ_LOCK_BH if !PR !! 17 select ARCH_USE_CMPXCHG_LOCKREF if 64BIT
60 select ARCH_INLINE_READ_LOCK_IRQ if !P <<
61 select ARCH_INLINE_READ_LOCK_IRQSAVE i <<
62 select ARCH_INLINE_READ_UNLOCK if !PRE <<
63 select ARCH_INLINE_READ_UNLOCK_BH if ! <<
64 select ARCH_INLINE_READ_UNLOCK_IRQ if <<
65 select ARCH_INLINE_READ_UNLOCK_IRQREST <<
66 select ARCH_INLINE_WRITE_LOCK if !PREE <<
67 select ARCH_INLINE_WRITE_LOCK_BH if !P <<
68 select ARCH_INLINE_WRITE_LOCK_IRQ if ! <<
69 select ARCH_INLINE_WRITE_LOCK_IRQSAVE <<
70 select ARCH_INLINE_WRITE_UNLOCK if !PR <<
71 select ARCH_INLINE_WRITE_UNLOCK_BH if <<
72 select ARCH_INLINE_WRITE_UNLOCK_IRQ if <<
73 select ARCH_INLINE_WRITE_UNLOCK_IRQRES <<
74 select ARCH_INLINE_SPIN_TRYLOCK if !PR <<
75 select ARCH_INLINE_SPIN_TRYLOCK_BH if <<
76 select ARCH_INLINE_SPIN_LOCK if !PREEM <<
77 select ARCH_INLINE_SPIN_LOCK_BH if !PR <<
78 select ARCH_INLINE_SPIN_LOCK_IRQ if !P <<
79 select ARCH_INLINE_SPIN_LOCK_IRQSAVE i <<
80 select ARCH_INLINE_SPIN_UNLOCK if !PRE <<
81 select ARCH_INLINE_SPIN_UNLOCK_BH if ! <<
82 select ARCH_INLINE_SPIN_UNLOCK_IRQ if <<
83 select ARCH_INLINE_SPIN_UNLOCK_IRQREST <<
84 select ARCH_KEEP_MEMBLOCK <<
85 select ARCH_MHP_MEMMAP_ON_MEMORY_ENABL <<
86 select ARCH_USE_CMPXCHG_LOCKREF <<
87 select ARCH_USE_GNU_PROPERTY <<
88 select ARCH_USE_MEMTEST <<
89 select ARCH_USE_QUEUED_RWLOCKS 18 select ARCH_USE_QUEUED_RWLOCKS
90 select ARCH_USE_QUEUED_SPINLOCKS 19 select ARCH_USE_QUEUED_SPINLOCKS
91 select ARCH_USE_SYM_ANNOTATIONS !! 20 select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT if MMU
92 select ARCH_SUPPORTS_DEBUG_PAGEALLOC !! 21 select ARCH_WANT_IPC_PARSE_VERSION
93 select ARCH_SUPPORTS_HUGETLBFS <<
94 select ARCH_SUPPORTS_MEMORY_FAILURE <<
95 select ARCH_SUPPORTS_SHADOW_CALL_STACK <<
96 select ARCH_SUPPORTS_LTO_CLANG if CPU_ <<
97 select ARCH_SUPPORTS_LTO_CLANG_THIN <<
98 select ARCH_SUPPORTS_CFI_CLANG <<
99 select ARCH_SUPPORTS_ATOMIC_RMW <<
100 select ARCH_SUPPORTS_INT128 if CC_HAS_ <<
101 select ARCH_SUPPORTS_NUMA_BALANCING <<
102 select ARCH_SUPPORTS_PAGE_TABLE_CHECK <<
103 select ARCH_SUPPORTS_PER_VMA_LOCK <<
104 select ARCH_SUPPORTS_HUGE_PFNMAP if TR <<
105 select ARCH_SUPPORTS_RT <<
106 select ARCH_WANT_BATCHED_UNMAP_TLB_FLU <<
107 select ARCH_WANT_COMPAT_IPC_PARSE_VERS <<
108 select ARCH_WANT_DEFAULT_BPF_JIT <<
109 select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_ <<
110 select ARCH_WANT_FRAME_POINTERS <<
111 select ARCH_WANT_HUGE_PMD_SHARE if ARM <<
112 select ARCH_WANT_LD_ORPHAN_WARN 22 select ARCH_WANT_LD_ORPHAN_WARN
113 select ARCH_WANTS_EXECMEM_LATE if EXEC <<
114 select ARCH_WANTS_NO_INSTR <<
115 select ARCH_WANTS_THP_SWAP if ARM64_4K <<
116 select ARCH_HAS_UBSAN <<
117 select ARM_AMBA <<
118 select ARM_ARCH_TIMER <<
119 select ARM_GIC <<
120 select AUDIT_ARCH_COMPAT_GENERIC <<
121 select ARM_GIC_V2M if PCI <<
122 select ARM_GIC_V3 <<
123 select ARM_GIC_V3_ITS if PCI <<
124 select ARM_PSCI_FW <<
125 select BUILDTIME_TABLE_SORT 23 select BUILDTIME_TABLE_SORT
126 select CLONE_BACKWARDS 24 select CLONE_BACKWARDS
127 select COMMON_CLK !! 25 select CPU_NO_EFFICIENT_FFS if (TARGET_ISA_REV < 1)
128 select CPU_PM if (SUSPEND || CPU_IDLE) !! 26 select CPU_PM if CPU_IDLE
129 select CPUMASK_OFFSTACK if NR_CPUS > 2 !! 27 select GENERIC_ATOMIC64 if !64BIT
130 select CRC32 !! 28 select GENERIC_CMOS_UPDATE
131 select DCACHE_WORD_ACCESS <<
132 select DYNAMIC_FTRACE if FUNCTION_TRAC <<
133 select DMA_BOUNCE_UNALIGNED_KMALLOC <<
134 select DMA_DIRECT_REMAP <<
135 select EDAC_SUPPORT <<
136 select FRAME_POINTER <<
137 select FUNCTION_ALIGNMENT_4B <<
138 select FUNCTION_ALIGNMENT_8B if DYNAMI <<
139 select GENERIC_ALLOCATOR <<
140 select GENERIC_ARCH_TOPOLOGY <<
141 select GENERIC_CLOCKEVENTS_BROADCAST <<
142 select GENERIC_CPU_AUTOPROBE 29 select GENERIC_CPU_AUTOPROBE
143 select GENERIC_CPU_DEVICES !! 30 select GENERIC_GETTIMEOFDAY
144 select GENERIC_CPU_VULNERABILITIES !! 31 select GENERIC_IOMAP
145 select GENERIC_EARLY_IOREMAP <<
146 select GENERIC_IDLE_POLL_SETUP <<
147 select GENERIC_IOREMAP <<
148 select GENERIC_IRQ_IPI <<
149 select GENERIC_IRQ_PROBE 32 select GENERIC_IRQ_PROBE
150 select GENERIC_IRQ_SHOW 33 select GENERIC_IRQ_SHOW
151 select GENERIC_IRQ_SHOW_LEVEL !! 34 select GENERIC_ISA_DMA if EISA
152 select GENERIC_LIB_DEVMEM_IS_ALLOWED !! 35 select GENERIC_LIB_ASHLDI3
153 select GENERIC_PCI_IOMAP !! 36 select GENERIC_LIB_ASHRDI3
154 select GENERIC_PTDUMP !! 37 select GENERIC_LIB_CMPDI2
155 select GENERIC_SCHED_CLOCK !! 38 select GENERIC_LIB_LSHRDI3
>> 39 select GENERIC_LIB_UCMPDI2
>> 40 select GENERIC_SCHED_CLOCK if !CAVIUM_OCTEON_SOC
156 select GENERIC_SMP_IDLE_THREAD 41 select GENERIC_SMP_IDLE_THREAD
157 select GENERIC_TIME_VSYSCALL 42 select GENERIC_TIME_VSYSCALL
158 select GENERIC_GETTIMEOFDAY !! 43 select GUP_GET_PTE_LOW_HIGH if CPU_MIPS32 && PHYS_ADDR_T_64BIT
159 select GENERIC_VDSO_TIME_NS !! 44 select HANDLE_DOMAIN_IRQ
160 select HARDIRQS_SW_RESEND <<
161 select HAS_IOPORT <<
162 select HAVE_MOVE_PMD <<
163 select HAVE_MOVE_PUD <<
164 select HAVE_PCI <<
165 select HAVE_ACPI_APEI if (ACPI && EFI) <<
166 select HAVE_ALIGNED_STRUCT_PAGE <<
167 select HAVE_ARCH_AUDITSYSCALL <<
168 select HAVE_ARCH_BITREVERSE <<
169 select HAVE_ARCH_COMPILER_H 45 select HAVE_ARCH_COMPILER_H
170 select HAVE_ARCH_HUGE_VMALLOC <<
171 select HAVE_ARCH_HUGE_VMAP <<
172 select HAVE_ARCH_JUMP_LABEL 46 select HAVE_ARCH_JUMP_LABEL
173 select HAVE_ARCH_JUMP_LABEL_RELATIVE !! 47 select HAVE_ARCH_KGDB if MIPS_FP_SUPPORT
174 select HAVE_ARCH_KASAN !! 48 select HAVE_ARCH_MMAP_RND_BITS if MMU
175 select HAVE_ARCH_KASAN_VMALLOC !! 49 select HAVE_ARCH_MMAP_RND_COMPAT_BITS if MMU && COMPAT
176 select HAVE_ARCH_KASAN_SW_TAGS <<
177 select HAVE_ARCH_KASAN_HW_TAGS if ARM6 <<
178 # Some instrumentation may be unsound, <<
179 select HAVE_ARCH_KCSAN if EXPERT <<
180 select HAVE_ARCH_KFENCE <<
181 select HAVE_ARCH_KGDB <<
182 select HAVE_ARCH_MMAP_RND_BITS <<
183 select HAVE_ARCH_MMAP_RND_COMPAT_BITS <<
184 select HAVE_ARCH_PREL32_RELOCATIONS <<
185 select HAVE_ARCH_RANDOMIZE_KSTACK_OFFS <<
186 select HAVE_ARCH_SECCOMP_FILTER 50 select HAVE_ARCH_SECCOMP_FILTER
187 select HAVE_ARCH_STACKLEAK <<
188 select HAVE_ARCH_THREAD_STRUCT_WHITELI <<
189 select HAVE_ARCH_TRACEHOOK 51 select HAVE_ARCH_TRACEHOOK
190 select HAVE_ARCH_TRANSPARENT_HUGEPAGE !! 52 select HAVE_ARCH_TRANSPARENT_HUGEPAGE if CPU_SUPPORTS_HUGEPAGES
191 select HAVE_ARCH_VMAP_STACK <<
192 select HAVE_ARM_SMCCC <<
193 select HAVE_ASM_MODVERSIONS 53 select HAVE_ASM_MODVERSIONS
194 select HAVE_EBPF_JIT !! 54 select HAVE_CBPF_JIT if !64BIT && !CPU_MICROMIPS
>> 55 select HAVE_CONTEXT_TRACKING
>> 56 select HAVE_TIF_NOHZ
195 select HAVE_C_RECORDMCOUNT 57 select HAVE_C_RECORDMCOUNT
196 select HAVE_CMPXCHG_DOUBLE <<
197 select HAVE_CMPXCHG_LOCAL <<
198 select HAVE_CONTEXT_TRACKING_USER <<
199 select HAVE_DEBUG_KMEMLEAK 58 select HAVE_DEBUG_KMEMLEAK
>> 59 select HAVE_DEBUG_STACKOVERFLOW
200 select HAVE_DMA_CONTIGUOUS 60 select HAVE_DMA_CONTIGUOUS
201 select HAVE_DYNAMIC_FTRACE 61 select HAVE_DYNAMIC_FTRACE
202 select HAVE_DYNAMIC_FTRACE_WITH_ARGS \ !! 62 select HAVE_EBPF_JIT if 64BIT && !CPU_MICROMIPS && TARGET_ISA_REV >= 2
203 if (GCC_SUPPORTS_DYNAMIC_FTRAC !! 63 select HAVE_EXIT_THREAD
204 CLANG_SUPPORTS_DYNAMIC_FTR !! 64 select HAVE_FAST_GUP
205 select HAVE_DYNAMIC_FTRACE_WITH_DIRECT <<
206 if DYNAMIC_FTRACE_WITH_ARGS && <<
207 select HAVE_DYNAMIC_FTRACE_WITH_CALL_O <<
208 if (DYNAMIC_FTRACE_WITH_ARGS & <<
209 (CC_IS_CLANG || !CC_OPTIMI <<
210 select FTRACE_MCOUNT_USE_PATCHABLE_FUN <<
211 if DYNAMIC_FTRACE_WITH_ARGS <<
212 select HAVE_SAMPLE_FTRACE_DIRECT <<
213 select HAVE_SAMPLE_FTRACE_DIRECT_MULTI <<
214 select HAVE_EFFICIENT_UNALIGNED_ACCESS <<
215 select HAVE_GUP_FAST <<
216 select HAVE_FTRACE_MCOUNT_RECORD 65 select HAVE_FTRACE_MCOUNT_RECORD
217 select HAVE_FUNCTION_TRACER <<
218 select HAVE_FUNCTION_ERROR_INJECTION <<
219 select HAVE_FUNCTION_GRAPH_TRACER 66 select HAVE_FUNCTION_GRAPH_TRACER
220 select HAVE_FUNCTION_GRAPH_RETVAL !! 67 select HAVE_FUNCTION_TRACER
221 select HAVE_GCC_PLUGINS 68 select HAVE_GCC_PLUGINS
222 select HAVE_HARDLOCKUP_DETECTOR_PERF i !! 69 select HAVE_GENERIC_VDSO
223 HW_PERF_EVENTS && HAVE_PERF_EV !! 70 select HAVE_IDE
224 select HAVE_HW_BREAKPOINT if PERF_EVEN <<
225 select HAVE_IOREMAP_PROT 71 select HAVE_IOREMAP_PROT
>> 72 select HAVE_IRQ_EXIT_ON_IRQ_STACK
226 select HAVE_IRQ_TIME_ACCOUNTING 73 select HAVE_IRQ_TIME_ACCOUNTING
>> 74 select HAVE_KPROBES
>> 75 select HAVE_KRETPROBES
>> 76 select HAVE_LD_DEAD_CODE_DATA_ELIMINATION
227 select HAVE_MOD_ARCH_SPECIFIC 77 select HAVE_MOD_ARCH_SPECIFIC
228 select HAVE_NMI 78 select HAVE_NMI
229 select HAVE_PERF_EVENTS 79 select HAVE_PERF_EVENTS
230 select HAVE_PERF_EVENTS_NMI if ARM64_P <<
231 select HAVE_PERF_REGS 80 select HAVE_PERF_REGS
232 select HAVE_PERF_USER_STACK_DUMP 81 select HAVE_PERF_USER_STACK_DUMP
233 select HAVE_PREEMPT_DYNAMIC_KEY <<
234 select HAVE_REGS_AND_STACK_ACCESS_API 82 select HAVE_REGS_AND_STACK_ACCESS_API
235 select HAVE_POSIX_CPU_TIMERS_TASK_WORK <<
236 select HAVE_FUNCTION_ARG_ACCESS_API <<
237 select MMU_GATHER_RCU_TABLE_FREE <<
238 select HAVE_RSEQ 83 select HAVE_RSEQ
239 select HAVE_RUST if RUSTC_SUPPORTS_ARM !! 84 select HAVE_SPARSE_SYSCALL_NR
240 select HAVE_STACKPROTECTOR 85 select HAVE_STACKPROTECTOR
241 select HAVE_SYSCALL_TRACEPOINTS 86 select HAVE_SYSCALL_TRACEPOINTS
242 select HAVE_KPROBES !! 87 select HAVE_VIRT_CPU_ACCOUNTING_GEN if 64BIT || !SMP
243 select HAVE_KRETPROBES <<
244 select HAVE_GENERIC_VDSO <<
245 select HOTPLUG_CORE_SYNC_DEAD if HOTPL <<
246 select IRQ_DOMAIN <<
247 select IRQ_FORCED_THREADING 88 select IRQ_FORCED_THREADING
248 select KASAN_VMALLOC if KASAN !! 89 select ISA if EISA
249 select LOCK_MM_AND_FIND_VMA !! 90 select MODULES_USE_ELF_REL if MODULES
250 select MODULES_USE_ELF_RELA !! 91 select MODULES_USE_ELF_RELA if MODULES && 64BIT
251 select NEED_DMA_MAP_STATE !! 92 select PERF_USE_VMALLOC
252 select NEED_SG_DMA_LENGTH !! 93 select PCI_MSI_ARCH_FALLBACKS if PCI_MSI
253 select OF !! 94 select RTC_LIB
254 select OF_EARLY_FLATTREE !! 95 select SET_FS
255 select PCI_DOMAINS_GENERIC if PCI <<
256 select PCI_ECAM if (ACPI && PCI) <<
257 select PCI_SYSCALL if PCI <<
258 select POWER_RESET <<
259 select POWER_SUPPLY <<
260 select SPARSE_IRQ <<
261 select SWIOTLB <<
262 select SYSCTL_EXCEPTION_TRACE 96 select SYSCTL_EXCEPTION_TRACE
263 select THREAD_INFO_IN_TASK !! 97 select VIRT_TO_BUS
264 select HAVE_ARCH_USERFAULTFD_MINOR if !! 98 select ARCH_HAS_ELFCORE_COMPAT
265 select HAVE_ARCH_USERFAULTFD_WP if USE <<
266 select TRACE_IRQFLAGS_SUPPORT <<
267 select TRACE_IRQFLAGS_NMI_SUPPORT <<
268 select HAVE_SOFTIRQ_ON_OWN_STACK <<
269 select USER_STACKTRACE_SUPPORT <<
270 select VDSO_GETRANDOM <<
271 help <<
272 ARM 64-bit (AArch64) Linux support. <<
273 99
274 config RUSTC_SUPPORTS_ARM64 !! 100 config MIPS_FIXUP_BIGPHYS_ADDR
275 def_bool y !! 101 bool
276 depends on CPU_LITTLE_ENDIAN <<
277 # Shadow call stack is only supported <<
278 # <<
279 # When using the UNWIND_PATCH_PAC_INTO <<
280 # required due to use of the -Zfixed-x <<
281 # <<
282 # Otherwise, rustc version 1.82+ is re <<
283 # -Zsanitizer=shadow-call-stack flag. <<
284 depends on !SHADOW_CALL_STACK || RUSTC <<
285 <<
286 config CLANG_SUPPORTS_DYNAMIC_FTRACE_WITH_ARGS <<
287 def_bool CC_IS_CLANG <<
288 # https://github.com/ClangBuiltLinux/l <<
289 depends on AS_IS_GNU || (AS_IS_LLVM && <<
290 <<
291 config GCC_SUPPORTS_DYNAMIC_FTRACE_WITH_ARGS <<
292 def_bool CC_IS_GCC <<
293 depends on $(cc-option,-fpatchable-fun <<
294 102
295 config 64BIT !! 103 config MIPS_GENERIC
296 def_bool y !! 104 bool
297 105
298 config MMU !! 106 config MACH_INGENIC
299 def_bool y !! 107 bool
>> 108 select SYS_SUPPORTS_32BIT_KERNEL
>> 109 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 110 select SYS_SUPPORTS_ZBOOT
>> 111 select DMA_NONCOHERENT
>> 112 select IRQ_MIPS_CPU
>> 113 select PINCTRL
>> 114 select GPIOLIB
>> 115 select COMMON_CLK
>> 116 select GENERIC_IRQ_CHIP
>> 117 select BUILTIN_DTB if MIPS_NO_APPENDED_DTB
>> 118 select USE_OF
>> 119 select CPU_SUPPORTS_CPUFREQ
>> 120 select MIPS_EXTERNAL_TIMER
300 121
301 config ARM64_CONT_PTE_SHIFT !! 122 menu "Machine selection"
302 int <<
303 default 5 if PAGE_SIZE_64KB <<
304 default 7 if PAGE_SIZE_16KB <<
305 default 4 <<
306 123
307 config ARM64_CONT_PMD_SHIFT !! 124 choice
308 int !! 125 prompt "System type"
309 default 5 if PAGE_SIZE_64KB !! 126 default MIPS_GENERIC_KERNEL
310 default 5 if PAGE_SIZE_16KB <<
311 default 4 <<
312 127
313 config ARCH_MMAP_RND_BITS_MIN !! 128 config MIPS_GENERIC_KERNEL
314 default 14 if PAGE_SIZE_64KB !! 129 bool "Generic board-agnostic MIPS kernel"
315 default 16 if PAGE_SIZE_16KB !! 130 select ARCH_HAS_SETUP_DMA_OPS
316 default 18 !! 131 select MIPS_GENERIC
>> 132 select BOOT_RAW
>> 133 select BUILTIN_DTB
>> 134 select CEVT_R4K
>> 135 select CLKSRC_MIPS_GIC
>> 136 select COMMON_CLK
>> 137 select CPU_MIPSR2_IRQ_EI
>> 138 select CPU_MIPSR2_IRQ_VI
>> 139 select CSRC_R4K
>> 140 select DMA_NONCOHERENT
>> 141 select HAVE_PCI
>> 142 select IRQ_MIPS_CPU
>> 143 select MIPS_AUTO_PFN_OFFSET
>> 144 select MIPS_CPU_SCACHE
>> 145 select MIPS_GIC
>> 146 select MIPS_L1_CACHE_SHIFT_7
>> 147 select NO_EXCEPT_FILL
>> 148 select PCI_DRIVERS_GENERIC
>> 149 select SMP_UP if SMP
>> 150 select SWAP_IO_SPACE
>> 151 select SYS_HAS_CPU_MIPS32_R1
>> 152 select SYS_HAS_CPU_MIPS32_R2
>> 153 select SYS_HAS_CPU_MIPS32_R6
>> 154 select SYS_HAS_CPU_MIPS64_R1
>> 155 select SYS_HAS_CPU_MIPS64_R2
>> 156 select SYS_HAS_CPU_MIPS64_R6
>> 157 select SYS_SUPPORTS_32BIT_KERNEL
>> 158 select SYS_SUPPORTS_64BIT_KERNEL
>> 159 select SYS_SUPPORTS_BIG_ENDIAN
>> 160 select SYS_SUPPORTS_HIGHMEM
>> 161 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 162 select SYS_SUPPORTS_MICROMIPS
>> 163 select SYS_SUPPORTS_MIPS16
>> 164 select SYS_SUPPORTS_MIPS_CPS
>> 165 select SYS_SUPPORTS_MULTITHREADING
>> 166 select SYS_SUPPORTS_RELOCATABLE
>> 167 select SYS_SUPPORTS_SMARTMIPS
>> 168 select SYS_SUPPORTS_ZBOOT
>> 169 select UHI_BOOT
>> 170 select USB_EHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
>> 171 select USB_EHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 172 select USB_OHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
>> 173 select USB_OHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 174 select USB_UHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
>> 175 select USB_UHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 176 select USE_OF
>> 177 help
>> 178 Select this to build a kernel which aims to support multiple boards,
>> 179 generally using a flattened device tree passed from the bootloader
>> 180 using the boot protocol defined in the UHI (Unified Hosting
>> 181 Interface) specification.
>> 182
>> 183 config MIPS_ALCHEMY
>> 184 bool "Alchemy processor based machines"
>> 185 select PHYS_ADDR_T_64BIT
>> 186 select CEVT_R4K
>> 187 select CSRC_R4K
>> 188 select IRQ_MIPS_CPU
>> 189 select DMA_NONCOHERENT # Au1000,1500,1100 aren't, rest is
>> 190 select MIPS_FIXUP_BIGPHYS_ADDR if PCI
>> 191 select SYS_HAS_CPU_MIPS32_R1
>> 192 select SYS_SUPPORTS_32BIT_KERNEL
>> 193 select SYS_SUPPORTS_APM_EMULATION
>> 194 select GPIOLIB
>> 195 select SYS_SUPPORTS_ZBOOT
>> 196 select COMMON_CLK
317 197
318 # max bits determined by the following formula !! 198 config AR7
319 # VA_BITS - PAGE_SHIFT - 3 !! 199 bool "Texas Instruments AR7"
320 config ARCH_MMAP_RND_BITS_MAX !! 200 select BOOT_ELF32
321 default 19 if ARM64_VA_BITS=36 !! 201 select DMA_NONCOHERENT
322 default 24 if ARM64_VA_BITS=39 !! 202 select CEVT_R4K
323 default 27 if ARM64_VA_BITS=42 !! 203 select CSRC_R4K
324 default 30 if ARM64_VA_BITS=47 !! 204 select IRQ_MIPS_CPU
325 default 29 if ARM64_VA_BITS=48 && ARM6 !! 205 select NO_EXCEPT_FILL
326 default 31 if ARM64_VA_BITS=48 && ARM6 !! 206 select SWAP_IO_SPACE
327 default 33 if ARM64_VA_BITS=48 !! 207 select SYS_HAS_CPU_MIPS32_R1
328 default 14 if ARM64_64K_PAGES !! 208 select SYS_HAS_EARLY_PRINTK
329 default 16 if ARM64_16K_PAGES !! 209 select SYS_SUPPORTS_32BIT_KERNEL
330 default 18 !! 210 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 211 select SYS_SUPPORTS_MIPS16
>> 212 select SYS_SUPPORTS_ZBOOT_UART16550
>> 213 select GPIOLIB
>> 214 select VLYNQ
>> 215 select HAVE_LEGACY_CLK
>> 216 help
>> 217 Support for the Texas Instruments AR7 System-on-a-Chip
>> 218 family: TNETD7100, 7200 and 7300.
>> 219
>> 220 config ATH25
>> 221 bool "Atheros AR231x/AR531x SoC support"
>> 222 select CEVT_R4K
>> 223 select CSRC_R4K
>> 224 select DMA_NONCOHERENT
>> 225 select IRQ_MIPS_CPU
>> 226 select IRQ_DOMAIN
>> 227 select SYS_HAS_CPU_MIPS32_R1
>> 228 select SYS_SUPPORTS_BIG_ENDIAN
>> 229 select SYS_SUPPORTS_32BIT_KERNEL
>> 230 select SYS_HAS_EARLY_PRINTK
>> 231 help
>> 232 Support for Atheros AR231x and Atheros AR531x based boards
>> 233
>> 234 config ATH79
>> 235 bool "Atheros AR71XX/AR724X/AR913X based boards"
>> 236 select ARCH_HAS_RESET_CONTROLLER
>> 237 select BOOT_RAW
>> 238 select CEVT_R4K
>> 239 select CSRC_R4K
>> 240 select DMA_NONCOHERENT
>> 241 select GPIOLIB
>> 242 select PINCTRL
>> 243 select COMMON_CLK
>> 244 select IRQ_MIPS_CPU
>> 245 select SYS_HAS_CPU_MIPS32_R2
>> 246 select SYS_HAS_EARLY_PRINTK
>> 247 select SYS_SUPPORTS_32BIT_KERNEL
>> 248 select SYS_SUPPORTS_BIG_ENDIAN
>> 249 select SYS_SUPPORTS_MIPS16
>> 250 select SYS_SUPPORTS_ZBOOT_UART_PROM
>> 251 select USE_OF
>> 252 select USB_EHCI_ROOT_HUB_TT if USB_EHCI_HCD_PLATFORM
>> 253 help
>> 254 Support for the Atheros AR71XX/AR724X/AR913X SoCs.
>> 255
>> 256 config BMIPS_GENERIC
>> 257 bool "Broadcom Generic BMIPS kernel"
>> 258 select ARCH_HAS_RESET_CONTROLLER
>> 259 select ARCH_HAS_SYNC_DMA_FOR_CPU_ALL
>> 260 select ARCH_HAS_PHYS_TO_DMA
>> 261 select BOOT_RAW
>> 262 select NO_EXCEPT_FILL
>> 263 select USE_OF
>> 264 select CEVT_R4K
>> 265 select CSRC_R4K
>> 266 select SYNC_R4K
>> 267 select COMMON_CLK
>> 268 select BCM6345_L1_IRQ
>> 269 select BCM7038_L1_IRQ
>> 270 select BCM7120_L2_IRQ
>> 271 select BRCMSTB_L2_IRQ
>> 272 select IRQ_MIPS_CPU
>> 273 select DMA_NONCOHERENT
>> 274 select SYS_SUPPORTS_32BIT_KERNEL
>> 275 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 276 select SYS_SUPPORTS_BIG_ENDIAN
>> 277 select SYS_SUPPORTS_HIGHMEM
>> 278 select SYS_HAS_CPU_BMIPS32_3300
>> 279 select SYS_HAS_CPU_BMIPS4350
>> 280 select SYS_HAS_CPU_BMIPS4380
>> 281 select SYS_HAS_CPU_BMIPS5000
>> 282 select SWAP_IO_SPACE
>> 283 select USB_EHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
>> 284 select USB_EHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 285 select USB_OHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
>> 286 select USB_OHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 287 select HARDIRQS_SW_RESEND
>> 288 help
>> 289 Build a generic DT-based kernel image that boots on select
>> 290 BCM33xx cable modem chips, BCM63xx DSL chips, and BCM7xxx set-top
>> 291 box chips. Note that CONFIG_CPU_BIG_ENDIAN/CONFIG_CPU_LITTLE_ENDIAN
>> 292 must be set appropriately for your board.
>> 293
>> 294 config BCM47XX
>> 295 bool "Broadcom BCM47XX based boards"
>> 296 select BOOT_RAW
>> 297 select CEVT_R4K
>> 298 select CSRC_R4K
>> 299 select DMA_NONCOHERENT
>> 300 select HAVE_PCI
>> 301 select IRQ_MIPS_CPU
>> 302 select SYS_HAS_CPU_MIPS32_R1
>> 303 select NO_EXCEPT_FILL
>> 304 select SYS_SUPPORTS_32BIT_KERNEL
>> 305 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 306 select SYS_SUPPORTS_MIPS16
>> 307 select SYS_SUPPORTS_ZBOOT
>> 308 select SYS_HAS_EARLY_PRINTK
>> 309 select USE_GENERIC_EARLY_PRINTK_8250
>> 310 select GPIOLIB
>> 311 select LEDS_GPIO_REGISTER
>> 312 select BCM47XX_NVRAM
>> 313 select BCM47XX_SPROM
>> 314 select BCM47XX_SSB if !BCM47XX_BCMA
>> 315 help
>> 316 Support for BCM47XX based boards
>> 317
>> 318 config BCM63XX
>> 319 bool "Broadcom BCM63XX based boards"
>> 320 select BOOT_RAW
>> 321 select CEVT_R4K
>> 322 select CSRC_R4K
>> 323 select SYNC_R4K
>> 324 select DMA_NONCOHERENT
>> 325 select IRQ_MIPS_CPU
>> 326 select SYS_SUPPORTS_32BIT_KERNEL
>> 327 select SYS_SUPPORTS_BIG_ENDIAN
>> 328 select SYS_HAS_EARLY_PRINTK
>> 329 select SWAP_IO_SPACE
>> 330 select GPIOLIB
>> 331 select MIPS_L1_CACHE_SHIFT_4
>> 332 select CLKDEV_LOOKUP
>> 333 select HAVE_LEGACY_CLK
>> 334 help
>> 335 Support for BCM63XX based boards
>> 336
>> 337 config MIPS_COBALT
>> 338 bool "Cobalt Server"
>> 339 select CEVT_R4K
>> 340 select CSRC_R4K
>> 341 select CEVT_GT641XX
>> 342 select DMA_NONCOHERENT
>> 343 select FORCE_PCI
>> 344 select I8253
>> 345 select I8259
>> 346 select IRQ_MIPS_CPU
>> 347 select IRQ_GT641XX
>> 348 select PCI_GT64XXX_PCI0
>> 349 select SYS_HAS_CPU_NEVADA
>> 350 select SYS_HAS_EARLY_PRINTK
>> 351 select SYS_SUPPORTS_32BIT_KERNEL
>> 352 select SYS_SUPPORTS_64BIT_KERNEL
>> 353 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 354 select USE_GENERIC_EARLY_PRINTK_8250
>> 355
>> 356 config MACH_DECSTATION
>> 357 bool "DECstations"
>> 358 select BOOT_ELF32
>> 359 select CEVT_DS1287
>> 360 select CEVT_R4K if CPU_R4X00
>> 361 select CSRC_IOASIC
>> 362 select CSRC_R4K if CPU_R4X00
>> 363 select CPU_DADDI_WORKAROUNDS if 64BIT
>> 364 select CPU_R4000_WORKAROUNDS if 64BIT
>> 365 select CPU_R4400_WORKAROUNDS if 64BIT
>> 366 select DMA_NONCOHERENT
>> 367 select NO_IOPORT_MAP
>> 368 select IRQ_MIPS_CPU
>> 369 select SYS_HAS_CPU_R3000
>> 370 select SYS_HAS_CPU_R4X00
>> 371 select SYS_SUPPORTS_32BIT_KERNEL
>> 372 select SYS_SUPPORTS_64BIT_KERNEL
>> 373 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 374 select SYS_SUPPORTS_128HZ
>> 375 select SYS_SUPPORTS_256HZ
>> 376 select SYS_SUPPORTS_1024HZ
>> 377 select MIPS_L1_CACHE_SHIFT_4
>> 378 help
>> 379 This enables support for DEC's MIPS based workstations. For details
>> 380 see the Linux/MIPS FAQ on <http://www.linux-mips.org/> and the
>> 381 DECstation porting pages on <http://decstation.unix-ag.org/>.
>> 382
>> 383 If you have one of the following DECstation Models you definitely
>> 384 want to choose R4xx0 for the CPU Type:
>> 385
>> 386 DECstation 5000/50
>> 387 DECstation 5000/150
>> 388 DECstation 5000/260
>> 389 DECsystem 5900/260
>> 390
>> 391 otherwise choose R3000.
>> 392
>> 393 config MACH_JAZZ
>> 394 bool "Jazz family of machines"
>> 395 select ARC_MEMORY
>> 396 select ARC_PROMLIB
>> 397 select ARCH_MIGHT_HAVE_PC_PARPORT
>> 398 select ARCH_MIGHT_HAVE_PC_SERIO
>> 399 select DMA_OPS
>> 400 select FW_ARC
>> 401 select FW_ARC32
>> 402 select ARCH_MAY_HAVE_PC_FDC
>> 403 select CEVT_R4K
>> 404 select CSRC_R4K
>> 405 select DEFAULT_SGI_PARTITION if CPU_BIG_ENDIAN
>> 406 select GENERIC_ISA_DMA
>> 407 select HAVE_PCSPKR_PLATFORM
>> 408 select IRQ_MIPS_CPU
>> 409 select I8253
>> 410 select I8259
>> 411 select ISA
>> 412 select SYS_HAS_CPU_R4X00
>> 413 select SYS_SUPPORTS_32BIT_KERNEL
>> 414 select SYS_SUPPORTS_64BIT_KERNEL
>> 415 select SYS_SUPPORTS_100HZ
>> 416 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 417 help
>> 418 This a family of machines based on the MIPS R4030 chipset which was
>> 419 used by several vendors to build RISC/os and Windows NT workstations.
>> 420 Members include the Acer PICA, MIPS Magnum 4000, MIPS Millennium and
>> 421 Olivetti M700-10 workstations.
>> 422
>> 423 config MACH_INGENIC_SOC
>> 424 bool "Ingenic SoC based machines"
>> 425 select MIPS_GENERIC
>> 426 select MACH_INGENIC
>> 427 select SYS_SUPPORTS_ZBOOT_UART16550
>> 428 select CPU_SUPPORTS_CPUFREQ
>> 429 select MIPS_EXTERNAL_TIMER
>> 430
>> 431 config LANTIQ
>> 432 bool "Lantiq based platforms"
>> 433 select DMA_NONCOHERENT
>> 434 select IRQ_MIPS_CPU
>> 435 select CEVT_R4K
>> 436 select CSRC_R4K
>> 437 select SYS_HAS_CPU_MIPS32_R1
>> 438 select SYS_HAS_CPU_MIPS32_R2
>> 439 select SYS_SUPPORTS_BIG_ENDIAN
>> 440 select SYS_SUPPORTS_32BIT_KERNEL
>> 441 select SYS_SUPPORTS_MIPS16
>> 442 select SYS_SUPPORTS_MULTITHREADING
>> 443 select SYS_SUPPORTS_VPE_LOADER
>> 444 select SYS_HAS_EARLY_PRINTK
>> 445 select GPIOLIB
>> 446 select SWAP_IO_SPACE
>> 447 select BOOT_RAW
>> 448 select CLKDEV_LOOKUP
>> 449 select HAVE_LEGACY_CLK
>> 450 select USE_OF
>> 451 select PINCTRL
>> 452 select PINCTRL_LANTIQ
>> 453 select ARCH_HAS_RESET_CONTROLLER
>> 454 select RESET_CONTROLLER
>> 455
>> 456 config MACH_LOONGSON32
>> 457 bool "Loongson 32-bit family of machines"
>> 458 select SYS_SUPPORTS_ZBOOT
>> 459 help
>> 460 This enables support for the Loongson-1 family of machines.
>> 461
>> 462 Loongson-1 is a family of 32-bit MIPS-compatible SoCs developed by
>> 463 the Institute of Computing Technology (ICT), Chinese Academy of
>> 464 Sciences (CAS).
>> 465
>> 466 config MACH_LOONGSON2EF
>> 467 bool "Loongson-2E/F family of machines"
>> 468 select SYS_SUPPORTS_ZBOOT
>> 469 help
>> 470 This enables the support of early Loongson-2E/F family of machines.
>> 471
>> 472 config MACH_LOONGSON64
>> 473 bool "Loongson 64-bit family of machines"
>> 474 select ARCH_SPARSEMEM_ENABLE
>> 475 select ARCH_MIGHT_HAVE_PC_PARPORT
>> 476 select ARCH_MIGHT_HAVE_PC_SERIO
>> 477 select GENERIC_ISA_DMA_SUPPORT_BROKEN
>> 478 select BOOT_ELF32
>> 479 select BOARD_SCACHE
>> 480 select CSRC_R4K
>> 481 select CEVT_R4K
>> 482 select CPU_HAS_WB
>> 483 select FORCE_PCI
>> 484 select ISA
>> 485 select I8259
>> 486 select IRQ_MIPS_CPU
>> 487 select NO_EXCEPT_FILL
>> 488 select NR_CPUS_DEFAULT_64
>> 489 select USE_GENERIC_EARLY_PRINTK_8250
>> 490 select PCI_DRIVERS_GENERIC
>> 491 select SYS_HAS_CPU_LOONGSON64
>> 492 select SYS_HAS_EARLY_PRINTK
>> 493 select SYS_SUPPORTS_SMP
>> 494 select SYS_SUPPORTS_HOTPLUG_CPU
>> 495 select SYS_SUPPORTS_NUMA
>> 496 select SYS_SUPPORTS_64BIT_KERNEL
>> 497 select SYS_SUPPORTS_HIGHMEM
>> 498 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 499 select SYS_SUPPORTS_ZBOOT
>> 500 select SYS_SUPPORTS_RELOCATABLE
>> 501 select ZONE_DMA32
>> 502 select COMMON_CLK
>> 503 select USE_OF
>> 504 select BUILTIN_DTB
>> 505 select PCI_HOST_GENERIC
>> 506 help
>> 507 This enables the support of Loongson-2/3 family of machines.
>> 508
>> 509 Loongson-2 and Loongson-3 are 64-bit general-purpose processors with
>> 510 GS264/GS464/GS464E/GS464V microarchitecture (except old Loongson-2E
>> 511 and Loongson-2F which will be removed), developed by the Institute
>> 512 of Computing Technology (ICT), Chinese Academy of Sciences (CAS).
>> 513
>> 514 config MACH_PISTACHIO
>> 515 bool "IMG Pistachio SoC based boards"
>> 516 select BOOT_ELF32
>> 517 select BOOT_RAW
>> 518 select CEVT_R4K
>> 519 select CLKSRC_MIPS_GIC
>> 520 select COMMON_CLK
>> 521 select CSRC_R4K
>> 522 select DMA_NONCOHERENT
>> 523 select GPIOLIB
>> 524 select IRQ_MIPS_CPU
>> 525 select MFD_SYSCON
>> 526 select MIPS_CPU_SCACHE
>> 527 select MIPS_GIC
>> 528 select PINCTRL
>> 529 select REGULATOR
>> 530 select SYS_HAS_CPU_MIPS32_R2
>> 531 select SYS_SUPPORTS_32BIT_KERNEL
>> 532 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 533 select SYS_SUPPORTS_MIPS_CPS
>> 534 select SYS_SUPPORTS_MULTITHREADING
>> 535 select SYS_SUPPORTS_RELOCATABLE
>> 536 select SYS_SUPPORTS_ZBOOT
>> 537 select SYS_HAS_EARLY_PRINTK
>> 538 select USE_GENERIC_EARLY_PRINTK_8250
>> 539 select USE_OF
>> 540 help
>> 541 This enables support for the IMG Pistachio SoC platform.
>> 542
>> 543 config MIPS_MALTA
>> 544 bool "MIPS Malta board"
>> 545 select ARCH_MAY_HAVE_PC_FDC
>> 546 select ARCH_MIGHT_HAVE_PC_PARPORT
>> 547 select ARCH_MIGHT_HAVE_PC_SERIO
>> 548 select BOOT_ELF32
>> 549 select BOOT_RAW
>> 550 select BUILTIN_DTB
>> 551 select CEVT_R4K
>> 552 select CLKSRC_MIPS_GIC
>> 553 select COMMON_CLK
>> 554 select CSRC_R4K
>> 555 select DMA_NONCOHERENT
>> 556 select GENERIC_ISA_DMA
>> 557 select HAVE_PCSPKR_PLATFORM
>> 558 select HAVE_PCI
>> 559 select I8253
>> 560 select I8259
>> 561 select IRQ_MIPS_CPU
>> 562 select MIPS_BONITO64
>> 563 select MIPS_CPU_SCACHE
>> 564 select MIPS_GIC
>> 565 select MIPS_L1_CACHE_SHIFT_6
>> 566 select MIPS_MSC
>> 567 select PCI_GT64XXX_PCI0
>> 568 select SMP_UP if SMP
>> 569 select SWAP_IO_SPACE
>> 570 select SYS_HAS_CPU_MIPS32_R1
>> 571 select SYS_HAS_CPU_MIPS32_R2
>> 572 select SYS_HAS_CPU_MIPS32_R3_5
>> 573 select SYS_HAS_CPU_MIPS32_R5
>> 574 select SYS_HAS_CPU_MIPS32_R6
>> 575 select SYS_HAS_CPU_MIPS64_R1
>> 576 select SYS_HAS_CPU_MIPS64_R2
>> 577 select SYS_HAS_CPU_MIPS64_R6
>> 578 select SYS_HAS_CPU_NEVADA
>> 579 select SYS_HAS_CPU_RM7000
>> 580 select SYS_SUPPORTS_32BIT_KERNEL
>> 581 select SYS_SUPPORTS_64BIT_KERNEL
>> 582 select SYS_SUPPORTS_BIG_ENDIAN
>> 583 select SYS_SUPPORTS_HIGHMEM
>> 584 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 585 select SYS_SUPPORTS_MICROMIPS
>> 586 select SYS_SUPPORTS_MIPS16
>> 587 select SYS_SUPPORTS_MIPS_CMP
>> 588 select SYS_SUPPORTS_MIPS_CPS
>> 589 select SYS_SUPPORTS_MULTITHREADING
>> 590 select SYS_SUPPORTS_RELOCATABLE
>> 591 select SYS_SUPPORTS_SMARTMIPS
>> 592 select SYS_SUPPORTS_VPE_LOADER
>> 593 select SYS_SUPPORTS_ZBOOT
>> 594 select USE_OF
>> 595 select WAR_ICACHE_REFILLS
>> 596 select ZONE_DMA32 if 64BIT
>> 597 help
>> 598 This enables support for the MIPS Technologies Malta evaluation
>> 599 board.
>> 600
>> 601 config MACH_PIC32
>> 602 bool "Microchip PIC32 Family"
>> 603 help
>> 604 This enables support for the Microchip PIC32 family of platforms.
>> 605
>> 606 Microchip PIC32 is a family of general-purpose 32 bit MIPS core
>> 607 microcontrollers.
>> 608
>> 609 config MACH_VR41XX
>> 610 bool "NEC VR4100 series based machines"
>> 611 select CEVT_R4K
>> 612 select CSRC_R4K
>> 613 select SYS_HAS_CPU_VR41XX
>> 614 select SYS_SUPPORTS_MIPS16
>> 615 select GPIOLIB
>> 616
>> 617 config MACH_NINTENDO64
>> 618 bool "Nintendo 64 console"
>> 619 select CEVT_R4K
>> 620 select CSRC_R4K
>> 621 select SYS_HAS_CPU_R4300
>> 622 select SYS_SUPPORTS_BIG_ENDIAN
>> 623 select SYS_SUPPORTS_ZBOOT
>> 624 select SYS_SUPPORTS_32BIT_KERNEL
>> 625 select SYS_SUPPORTS_64BIT_KERNEL
>> 626 select DMA_NONCOHERENT
>> 627 select IRQ_MIPS_CPU
>> 628
>> 629 config RALINK
>> 630 bool "Ralink based machines"
>> 631 select CEVT_R4K
>> 632 select CSRC_R4K
>> 633 select BOOT_RAW
>> 634 select DMA_NONCOHERENT
>> 635 select IRQ_MIPS_CPU
>> 636 select USE_OF
>> 637 select SYS_HAS_CPU_MIPS32_R1
>> 638 select SYS_HAS_CPU_MIPS32_R2
>> 639 select SYS_SUPPORTS_32BIT_KERNEL
>> 640 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 641 select SYS_SUPPORTS_MIPS16
>> 642 select SYS_SUPPORTS_ZBOOT
>> 643 select SYS_HAS_EARLY_PRINTK
>> 644 select CLKDEV_LOOKUP
>> 645 select ARCH_HAS_RESET_CONTROLLER
>> 646 select RESET_CONTROLLER
>> 647
>> 648 config MACH_REALTEK_RTL
>> 649 bool "Realtek RTL838x/RTL839x based machines"
>> 650 select MIPS_GENERIC
>> 651 select DMA_NONCOHERENT
>> 652 select IRQ_MIPS_CPU
>> 653 select CSRC_R4K
>> 654 select CEVT_R4K
>> 655 select SYS_HAS_CPU_MIPS32_R1
>> 656 select SYS_HAS_CPU_MIPS32_R2
>> 657 select SYS_SUPPORTS_BIG_ENDIAN
>> 658 select SYS_SUPPORTS_32BIT_KERNEL
>> 659 select SYS_SUPPORTS_MIPS16
>> 660 select SYS_SUPPORTS_MULTITHREADING
>> 661 select SYS_SUPPORTS_VPE_LOADER
>> 662 select SYS_HAS_EARLY_PRINTK
>> 663 select SYS_HAS_EARLY_PRINTK_8250
>> 664 select USE_GENERIC_EARLY_PRINTK_8250
>> 665 select BOOT_RAW
>> 666 select PINCTRL
>> 667 select USE_OF
>> 668
>> 669 config SGI_IP22
>> 670 bool "SGI IP22 (Indy/Indigo2)"
>> 671 select ARC_MEMORY
>> 672 select ARC_PROMLIB
>> 673 select FW_ARC
>> 674 select FW_ARC32
>> 675 select ARCH_MIGHT_HAVE_PC_SERIO
>> 676 select BOOT_ELF32
>> 677 select CEVT_R4K
>> 678 select CSRC_R4K
>> 679 select DEFAULT_SGI_PARTITION
>> 680 select DMA_NONCOHERENT
>> 681 select HAVE_EISA
>> 682 select I8253
>> 683 select I8259
>> 684 select IP22_CPU_SCACHE
>> 685 select IRQ_MIPS_CPU
>> 686 select GENERIC_ISA_DMA_SUPPORT_BROKEN
>> 687 select SGI_HAS_I8042
>> 688 select SGI_HAS_INDYDOG
>> 689 select SGI_HAS_HAL2
>> 690 select SGI_HAS_SEEQ
>> 691 select SGI_HAS_WD93
>> 692 select SGI_HAS_ZILOG
>> 693 select SWAP_IO_SPACE
>> 694 select SYS_HAS_CPU_R4X00
>> 695 select SYS_HAS_CPU_R5000
>> 696 select SYS_HAS_EARLY_PRINTK
>> 697 select SYS_SUPPORTS_32BIT_KERNEL
>> 698 select SYS_SUPPORTS_64BIT_KERNEL
>> 699 select SYS_SUPPORTS_BIG_ENDIAN
>> 700 select WAR_R4600_V1_INDEX_ICACHEOP
>> 701 select WAR_R4600_V1_HIT_CACHEOP
>> 702 select WAR_R4600_V2_HIT_CACHEOP
>> 703 select MIPS_L1_CACHE_SHIFT_7
>> 704 help
>> 705 This are the SGI Indy, Challenge S and Indigo2, as well as certain
>> 706 OEM variants like the Tandem CMN B006S. To compile a Linux kernel
>> 707 that runs on these, say Y here.
>> 708
>> 709 config SGI_IP27
>> 710 bool "SGI IP27 (Origin200/2000)"
>> 711 select ARCH_HAS_PHYS_TO_DMA
>> 712 select ARCH_SPARSEMEM_ENABLE
>> 713 select FW_ARC
>> 714 select FW_ARC64
>> 715 select ARC_CMDLINE_ONLY
>> 716 select BOOT_ELF64
>> 717 select DEFAULT_SGI_PARTITION
>> 718 select SYS_HAS_EARLY_PRINTK
>> 719 select HAVE_PCI
>> 720 select IRQ_MIPS_CPU
>> 721 select IRQ_DOMAIN_HIERARCHY
>> 722 select NR_CPUS_DEFAULT_64
>> 723 select PCI_DRIVERS_GENERIC
>> 724 select PCI_XTALK_BRIDGE
>> 725 select SYS_HAS_CPU_R10000
>> 726 select SYS_SUPPORTS_64BIT_KERNEL
>> 727 select SYS_SUPPORTS_BIG_ENDIAN
>> 728 select SYS_SUPPORTS_NUMA
>> 729 select SYS_SUPPORTS_SMP
>> 730 select WAR_R10000_LLSC
>> 731 select MIPS_L1_CACHE_SHIFT_7
>> 732 select NUMA
>> 733 help
>> 734 This are the SGI Origin 200, Origin 2000 and Onyx 2 Graphics
>> 735 workstations. To compile a Linux kernel that runs on these, say Y
>> 736 here.
>> 737
>> 738 config SGI_IP28
>> 739 bool "SGI IP28 (Indigo2 R10k)"
>> 740 select ARC_MEMORY
>> 741 select ARC_PROMLIB
>> 742 select FW_ARC
>> 743 select FW_ARC64
>> 744 select ARCH_MIGHT_HAVE_PC_SERIO
>> 745 select BOOT_ELF64
>> 746 select CEVT_R4K
>> 747 select CSRC_R4K
>> 748 select DEFAULT_SGI_PARTITION
>> 749 select DMA_NONCOHERENT
>> 750 select GENERIC_ISA_DMA_SUPPORT_BROKEN
>> 751 select IRQ_MIPS_CPU
>> 752 select HAVE_EISA
>> 753 select I8253
>> 754 select I8259
>> 755 select SGI_HAS_I8042
>> 756 select SGI_HAS_INDYDOG
>> 757 select SGI_HAS_HAL2
>> 758 select SGI_HAS_SEEQ
>> 759 select SGI_HAS_WD93
>> 760 select SGI_HAS_ZILOG
>> 761 select SWAP_IO_SPACE
>> 762 select SYS_HAS_CPU_R10000
>> 763 select SYS_HAS_EARLY_PRINTK
>> 764 select SYS_SUPPORTS_64BIT_KERNEL
>> 765 select SYS_SUPPORTS_BIG_ENDIAN
>> 766 select WAR_R10000_LLSC
>> 767 select MIPS_L1_CACHE_SHIFT_7
>> 768 help
>> 769 This is the SGI Indigo2 with R10000 processor. To compile a Linux
>> 770 kernel that runs on these, say Y here.
>> 771
>> 772 config SGI_IP30
>> 773 bool "SGI IP30 (Octane/Octane2)"
>> 774 select ARCH_HAS_PHYS_TO_DMA
>> 775 select FW_ARC
>> 776 select FW_ARC64
>> 777 select BOOT_ELF64
>> 778 select CEVT_R4K
>> 779 select CSRC_R4K
>> 780 select SYNC_R4K if SMP
>> 781 select ZONE_DMA32
>> 782 select HAVE_PCI
>> 783 select IRQ_MIPS_CPU
>> 784 select IRQ_DOMAIN_HIERARCHY
>> 785 select NR_CPUS_DEFAULT_2
>> 786 select PCI_DRIVERS_GENERIC
>> 787 select PCI_XTALK_BRIDGE
>> 788 select SYS_HAS_EARLY_PRINTK
>> 789 select SYS_HAS_CPU_R10000
>> 790 select SYS_SUPPORTS_64BIT_KERNEL
>> 791 select SYS_SUPPORTS_BIG_ENDIAN
>> 792 select SYS_SUPPORTS_SMP
>> 793 select WAR_R10000_LLSC
>> 794 select MIPS_L1_CACHE_SHIFT_7
>> 795 select ARC_MEMORY
>> 796 help
>> 797 These are the SGI Octane and Octane2 graphics workstations. To
>> 798 compile a Linux kernel that runs on these, say Y here.
>> 799
>> 800 config SGI_IP32
>> 801 bool "SGI IP32 (O2)"
>> 802 select ARC_MEMORY
>> 803 select ARC_PROMLIB
>> 804 select ARCH_HAS_PHYS_TO_DMA
>> 805 select FW_ARC
>> 806 select FW_ARC32
>> 807 select BOOT_ELF32
>> 808 select CEVT_R4K
>> 809 select CSRC_R4K
>> 810 select DMA_NONCOHERENT
>> 811 select HAVE_PCI
>> 812 select IRQ_MIPS_CPU
>> 813 select R5000_CPU_SCACHE
>> 814 select RM7000_CPU_SCACHE
>> 815 select SYS_HAS_CPU_R5000
>> 816 select SYS_HAS_CPU_R10000 if BROKEN
>> 817 select SYS_HAS_CPU_RM7000
>> 818 select SYS_HAS_CPU_NEVADA
>> 819 select SYS_SUPPORTS_64BIT_KERNEL
>> 820 select SYS_SUPPORTS_BIG_ENDIAN
>> 821 select WAR_ICACHE_REFILLS
>> 822 help
>> 823 If you want this kernel to run on SGI O2 workstation, say Y here.
>> 824
>> 825 config SIBYTE_CRHINE
>> 826 bool "Sibyte BCM91120C-CRhine"
>> 827 select BOOT_ELF32
>> 828 select SIBYTE_BCM1120
>> 829 select SWAP_IO_SPACE
>> 830 select SYS_HAS_CPU_SB1
>> 831 select SYS_SUPPORTS_BIG_ENDIAN
>> 832 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 833
>> 834 config SIBYTE_CARMEL
>> 835 bool "Sibyte BCM91120x-Carmel"
>> 836 select BOOT_ELF32
>> 837 select SIBYTE_BCM1120
>> 838 select SWAP_IO_SPACE
>> 839 select SYS_HAS_CPU_SB1
>> 840 select SYS_SUPPORTS_BIG_ENDIAN
>> 841 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 842
>> 843 config SIBYTE_CRHONE
>> 844 bool "Sibyte BCM91125C-CRhone"
>> 845 select BOOT_ELF32
>> 846 select SIBYTE_BCM1125
>> 847 select SWAP_IO_SPACE
>> 848 select SYS_HAS_CPU_SB1
>> 849 select SYS_SUPPORTS_BIG_ENDIAN
>> 850 select SYS_SUPPORTS_HIGHMEM
>> 851 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 852
>> 853 config SIBYTE_RHONE
>> 854 bool "Sibyte BCM91125E-Rhone"
>> 855 select BOOT_ELF32
>> 856 select SIBYTE_BCM1125H
>> 857 select SWAP_IO_SPACE
>> 858 select SYS_HAS_CPU_SB1
>> 859 select SYS_SUPPORTS_BIG_ENDIAN
>> 860 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 861
>> 862 config SIBYTE_SWARM
>> 863 bool "Sibyte BCM91250A-SWARM"
>> 864 select BOOT_ELF32
>> 865 select HAVE_PATA_PLATFORM
>> 866 select SIBYTE_SB1250
>> 867 select SWAP_IO_SPACE
>> 868 select SYS_HAS_CPU_SB1
>> 869 select SYS_SUPPORTS_BIG_ENDIAN
>> 870 select SYS_SUPPORTS_HIGHMEM
>> 871 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 872 select ZONE_DMA32 if 64BIT
>> 873 select SWIOTLB if ARCH_DMA_ADDR_T_64BIT && PCI
>> 874
>> 875 config SIBYTE_LITTLESUR
>> 876 bool "Sibyte BCM91250C2-LittleSur"
>> 877 select BOOT_ELF32
>> 878 select HAVE_PATA_PLATFORM
>> 879 select SIBYTE_SB1250
>> 880 select SWAP_IO_SPACE
>> 881 select SYS_HAS_CPU_SB1
>> 882 select SYS_SUPPORTS_BIG_ENDIAN
>> 883 select SYS_SUPPORTS_HIGHMEM
>> 884 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 885 select ZONE_DMA32 if 64BIT
>> 886
>> 887 config SIBYTE_SENTOSA
>> 888 bool "Sibyte BCM91250E-Sentosa"
>> 889 select BOOT_ELF32
>> 890 select SIBYTE_SB1250
>> 891 select SWAP_IO_SPACE
>> 892 select SYS_HAS_CPU_SB1
>> 893 select SYS_SUPPORTS_BIG_ENDIAN
>> 894 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 895 select SWIOTLB if ARCH_DMA_ADDR_T_64BIT && PCI
>> 896
>> 897 config SIBYTE_BIGSUR
>> 898 bool "Sibyte BCM91480B-BigSur"
>> 899 select BOOT_ELF32
>> 900 select NR_CPUS_DEFAULT_4
>> 901 select SIBYTE_BCM1x80
>> 902 select SWAP_IO_SPACE
>> 903 select SYS_HAS_CPU_SB1
>> 904 select SYS_SUPPORTS_BIG_ENDIAN
>> 905 select SYS_SUPPORTS_HIGHMEM
>> 906 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 907 select ZONE_DMA32 if 64BIT
>> 908 select SWIOTLB if ARCH_DMA_ADDR_T_64BIT && PCI
>> 909
>> 910 config SNI_RM
>> 911 bool "SNI RM200/300/400"
>> 912 select ARC_MEMORY
>> 913 select ARC_PROMLIB
>> 914 select FW_ARC if CPU_LITTLE_ENDIAN
>> 915 select FW_ARC32 if CPU_LITTLE_ENDIAN
>> 916 select FW_SNIPROM if CPU_BIG_ENDIAN
>> 917 select ARCH_MAY_HAVE_PC_FDC
>> 918 select ARCH_MIGHT_HAVE_PC_PARPORT
>> 919 select ARCH_MIGHT_HAVE_PC_SERIO
>> 920 select BOOT_ELF32
>> 921 select CEVT_R4K
>> 922 select CSRC_R4K
>> 923 select DEFAULT_SGI_PARTITION if CPU_BIG_ENDIAN
>> 924 select DMA_NONCOHERENT
>> 925 select GENERIC_ISA_DMA
>> 926 select HAVE_EISA
>> 927 select HAVE_PCSPKR_PLATFORM
>> 928 select HAVE_PCI
>> 929 select IRQ_MIPS_CPU
>> 930 select I8253
>> 931 select I8259
>> 932 select ISA
>> 933 select MIPS_L1_CACHE_SHIFT_6
>> 934 select SWAP_IO_SPACE if CPU_BIG_ENDIAN
>> 935 select SYS_HAS_CPU_R4X00
>> 936 select SYS_HAS_CPU_R5000
>> 937 select SYS_HAS_CPU_R10000
>> 938 select R5000_CPU_SCACHE
>> 939 select SYS_HAS_EARLY_PRINTK
>> 940 select SYS_SUPPORTS_32BIT_KERNEL
>> 941 select SYS_SUPPORTS_64BIT_KERNEL
>> 942 select SYS_SUPPORTS_BIG_ENDIAN
>> 943 select SYS_SUPPORTS_HIGHMEM
>> 944 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 945 select WAR_R4600_V2_HIT_CACHEOP
>> 946 help
>> 947 The SNI RM200/300/400 are MIPS-based machines manufactured by
>> 948 Siemens Nixdorf Informationssysteme (SNI), parent company of Pyramid
>> 949 Technology and now in turn merged with Fujitsu. Say Y here to
>> 950 support this machine type.
>> 951
>> 952 config MACH_TX39XX
>> 953 bool "Toshiba TX39 series based machines"
>> 954
>> 955 config MACH_TX49XX
>> 956 bool "Toshiba TX49 series based machines"
>> 957 select WAR_TX49XX_ICACHE_INDEX_INV
>> 958
>> 959 config MIKROTIK_RB532
>> 960 bool "Mikrotik RB532 boards"
>> 961 select CEVT_R4K
>> 962 select CSRC_R4K
>> 963 select DMA_NONCOHERENT
>> 964 select HAVE_PCI
>> 965 select IRQ_MIPS_CPU
>> 966 select SYS_HAS_CPU_MIPS32_R1
>> 967 select SYS_SUPPORTS_32BIT_KERNEL
>> 968 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 969 select SWAP_IO_SPACE
>> 970 select BOOT_RAW
>> 971 select GPIOLIB
>> 972 select MIPS_L1_CACHE_SHIFT_4
>> 973 help
>> 974 Support the Mikrotik(tm) RouterBoard 532 series,
>> 975 based on the IDT RC32434 SoC.
>> 976
>> 977 config CAVIUM_OCTEON_SOC
>> 978 bool "Cavium Networks Octeon SoC based boards"
>> 979 select CEVT_R4K
>> 980 select ARCH_HAS_PHYS_TO_DMA
>> 981 select HAVE_RAPIDIO
>> 982 select PHYS_ADDR_T_64BIT
>> 983 select SYS_SUPPORTS_64BIT_KERNEL
>> 984 select SYS_SUPPORTS_BIG_ENDIAN
>> 985 select EDAC_SUPPORT
>> 986 select EDAC_ATOMIC_SCRUB
>> 987 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 988 select SYS_SUPPORTS_HOTPLUG_CPU if CPU_BIG_ENDIAN
>> 989 select SYS_HAS_EARLY_PRINTK
>> 990 select SYS_HAS_CPU_CAVIUM_OCTEON
>> 991 select HAVE_PCI
>> 992 select HAVE_PLAT_DELAY
>> 993 select HAVE_PLAT_FW_INIT_CMDLINE
>> 994 select HAVE_PLAT_MEMCPY
>> 995 select ZONE_DMA32
>> 996 select HOLES_IN_ZONE
>> 997 select GPIOLIB
>> 998 select USE_OF
>> 999 select ARCH_SPARSEMEM_ENABLE
>> 1000 select SYS_SUPPORTS_SMP
>> 1001 select NR_CPUS_DEFAULT_64
>> 1002 select MIPS_NR_CPU_NR_MAP_1024
>> 1003 select BUILTIN_DTB
>> 1004 select MTD_COMPLEX_MAPPINGS
>> 1005 select SWIOTLB
>> 1006 select SYS_SUPPORTS_RELOCATABLE
>> 1007 help
>> 1008 This option supports all of the Octeon reference boards from Cavium
>> 1009 Networks. It builds a kernel that dynamically determines the Octeon
>> 1010 CPU type and supports all known board reference implementations.
>> 1011 Some of the supported boards are:
>> 1012 EBT3000
>> 1013 EBH3000
>> 1014 EBH3100
>> 1015 Thunder
>> 1016 Kodama
>> 1017 Hikari
>> 1018 Say Y here for most Octeon reference boards.
>> 1019
>> 1020 config NLM_XLR_BOARD
>> 1021 bool "Netlogic XLR/XLS based systems"
>> 1022 select BOOT_ELF32
>> 1023 select NLM_COMMON
>> 1024 select SYS_HAS_CPU_XLR
>> 1025 select SYS_SUPPORTS_SMP
>> 1026 select HAVE_PCI
>> 1027 select SWAP_IO_SPACE
>> 1028 select SYS_SUPPORTS_32BIT_KERNEL
>> 1029 select SYS_SUPPORTS_64BIT_KERNEL
>> 1030 select PHYS_ADDR_T_64BIT
>> 1031 select SYS_SUPPORTS_BIG_ENDIAN
>> 1032 select SYS_SUPPORTS_HIGHMEM
>> 1033 select NR_CPUS_DEFAULT_32
>> 1034 select CEVT_R4K
>> 1035 select CSRC_R4K
>> 1036 select IRQ_MIPS_CPU
>> 1037 select ZONE_DMA32 if 64BIT
>> 1038 select SYNC_R4K
>> 1039 select SYS_HAS_EARLY_PRINTK
>> 1040 select SYS_SUPPORTS_ZBOOT
>> 1041 select SYS_SUPPORTS_ZBOOT_UART16550
>> 1042 help
>> 1043 Support for systems based on Netlogic XLR and XLS processors.
>> 1044 Say Y here if you have a XLR or XLS based board.
>> 1045
>> 1046 config NLM_XLP_BOARD
>> 1047 bool "Netlogic XLP based systems"
>> 1048 select BOOT_ELF32
>> 1049 select NLM_COMMON
>> 1050 select SYS_HAS_CPU_XLP
>> 1051 select SYS_SUPPORTS_SMP
>> 1052 select HAVE_PCI
>> 1053 select SYS_SUPPORTS_32BIT_KERNEL
>> 1054 select SYS_SUPPORTS_64BIT_KERNEL
>> 1055 select PHYS_ADDR_T_64BIT
>> 1056 select GPIOLIB
>> 1057 select SYS_SUPPORTS_BIG_ENDIAN
>> 1058 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 1059 select SYS_SUPPORTS_HIGHMEM
>> 1060 select NR_CPUS_DEFAULT_32
>> 1061 select CEVT_R4K
>> 1062 select CSRC_R4K
>> 1063 select IRQ_MIPS_CPU
>> 1064 select ZONE_DMA32 if 64BIT
>> 1065 select SYNC_R4K
>> 1066 select SYS_HAS_EARLY_PRINTK
>> 1067 select USE_OF
>> 1068 select SYS_SUPPORTS_ZBOOT
>> 1069 select SYS_SUPPORTS_ZBOOT_UART16550
>> 1070 help
>> 1071 This board is based on Netlogic XLP Processor.
>> 1072 Say Y here if you have a XLP based board.
331 1073
332 config ARCH_MMAP_RND_COMPAT_BITS_MIN !! 1074 endchoice
333 default 7 if ARM64_64K_PAGES <<
334 default 9 if ARM64_16K_PAGES <<
335 default 11 <<
336 1075
337 config ARCH_MMAP_RND_COMPAT_BITS_MAX !! 1076 source "arch/mips/alchemy/Kconfig"
338 default 16 !! 1077 source "arch/mips/ath25/Kconfig"
>> 1078 source "arch/mips/ath79/Kconfig"
>> 1079 source "arch/mips/bcm47xx/Kconfig"
>> 1080 source "arch/mips/bcm63xx/Kconfig"
>> 1081 source "arch/mips/bmips/Kconfig"
>> 1082 source "arch/mips/generic/Kconfig"
>> 1083 source "arch/mips/ingenic/Kconfig"
>> 1084 source "arch/mips/jazz/Kconfig"
>> 1085 source "arch/mips/lantiq/Kconfig"
>> 1086 source "arch/mips/pic32/Kconfig"
>> 1087 source "arch/mips/pistachio/Kconfig"
>> 1088 source "arch/mips/ralink/Kconfig"
>> 1089 source "arch/mips/sgi-ip27/Kconfig"
>> 1090 source "arch/mips/sibyte/Kconfig"
>> 1091 source "arch/mips/txx9/Kconfig"
>> 1092 source "arch/mips/vr41xx/Kconfig"
>> 1093 source "arch/mips/cavium-octeon/Kconfig"
>> 1094 source "arch/mips/loongson2ef/Kconfig"
>> 1095 source "arch/mips/loongson32/Kconfig"
>> 1096 source "arch/mips/loongson64/Kconfig"
>> 1097 source "arch/mips/netlogic/Kconfig"
339 1098
340 config NO_IOPORT_MAP !! 1099 endmenu
341 def_bool y if !PCI <<
342 1100
343 config STACKTRACE_SUPPORT !! 1101 config GENERIC_HWEIGHT
344 def_bool y !! 1102 bool
>> 1103 default y
345 1104
346 config ILLEGAL_POINTER_VALUE !! 1105 config GENERIC_CALIBRATE_DELAY
347 hex !! 1106 bool
348 default 0xdead000000000000 !! 1107 default y
349 1108
350 config LOCKDEP_SUPPORT !! 1109 config SCHED_OMIT_FRAME_POINTER
351 def_bool y !! 1110 bool
>> 1111 default y
352 1112
353 config GENERIC_BUG !! 1113 #
354 def_bool y !! 1114 # Select some configuration options automatically based on user selections.
355 depends on BUG !! 1115 #
>> 1116 config FW_ARC
>> 1117 bool
356 1118
357 config GENERIC_BUG_RELATIVE_POINTERS !! 1119 config ARCH_MAY_HAVE_PC_FDC
358 def_bool y !! 1120 bool
359 depends on GENERIC_BUG <<
360 1121
361 config GENERIC_HWEIGHT !! 1122 config BOOT_RAW
362 def_bool y !! 1123 bool
363 1124
364 config GENERIC_CSUM !! 1125 config CEVT_BCM1480
365 def_bool y !! 1126 bool
366 1127
367 config GENERIC_CALIBRATE_DELAY !! 1128 config CEVT_DS1287
368 def_bool y !! 1129 bool
369 1130
370 config SMP !! 1131 config CEVT_GT641XX
371 def_bool y !! 1132 bool
372 1133
373 config KERNEL_MODE_NEON !! 1134 config CEVT_R4K
374 def_bool y !! 1135 bool
375 1136
376 config FIX_EARLYCON_MEM !! 1137 config CEVT_SB1250
377 def_bool y !! 1138 bool
378 1139
379 config PGTABLE_LEVELS !! 1140 config CEVT_TXX9
380 int !! 1141 bool
381 default 2 if ARM64_16K_PAGES && ARM64_ <<
382 default 2 if ARM64_64K_PAGES && ARM64_ <<
383 default 3 if ARM64_64K_PAGES && (ARM64 <<
384 default 3 if ARM64_4K_PAGES && ARM64_V <<
385 default 3 if ARM64_16K_PAGES && ARM64_ <<
386 default 4 if ARM64_16K_PAGES && (ARM64 <<
387 default 4 if !ARM64_64K_PAGES && ARM64 <<
388 default 5 if ARM64_4K_PAGES && ARM64_V <<
389 1142
390 config ARCH_SUPPORTS_UPROBES !! 1143 config CSRC_BCM1480
391 def_bool y !! 1144 bool
392 1145
393 config ARCH_PROC_KCORE_TEXT !! 1146 config CSRC_IOASIC
394 def_bool y !! 1147 bool
395 1148
396 config BROKEN_GAS_INST !! 1149 config CSRC_R4K
397 def_bool !$(as-instr,1:\n.inst 0\n.rep !! 1150 select CLOCKSOURCE_WATCHDOG if CPU_FREQ
>> 1151 bool
398 1152
399 config BUILTIN_RETURN_ADDRESS_STRIPS_PAC !! 1153 config CSRC_SB1250
400 bool 1154 bool
401 # Clang's __builtin_return_address() s <<
402 # https://github.com/llvm/llvm-project <<
403 default y if CC_IS_CLANG <<
404 # GCC's __builtin_return_address() str <<
405 # and this was backported to 10.2.0, 9 <<
406 # https://gcc.gnu.org/bugzilla/show_bu <<
407 default y if CC_IS_GCC && (GCC_VERSION <<
408 default y if CC_IS_GCC && (GCC_VERSION <<
409 default y if CC_IS_GCC && (GCC_VERSION <<
410 default y if CC_IS_GCC && (GCC_VERSION <<
411 default n <<
412 1155
413 config KASAN_SHADOW_OFFSET !! 1156 config MIPS_CLOCK_VSYSCALL
414 hex !! 1157 def_bool CSRC_R4K || CLKSRC_MIPS_GIC
415 depends on KASAN_GENERIC || KASAN_SW_T <<
416 default 0xdfff800000000000 if (ARM64_V <<
417 default 0xdfffc00000000000 if (ARM64_V <<
418 default 0xdffffe0000000000 if ARM64_VA <<
419 default 0xdfffffc000000000 if ARM64_VA <<
420 default 0xdffffff800000000 if ARM64_VA <<
421 default 0xefff800000000000 if (ARM64_V <<
422 default 0xefffc00000000000 if (ARM64_V <<
423 default 0xeffffe0000000000 if ARM64_VA <<
424 default 0xefffffc000000000 if ARM64_VA <<
425 default 0xeffffff800000000 if ARM64_VA <<
426 default 0xffffffffffffffff <<
427 <<
428 config UNWIND_TABLES <<
429 bool <<
430 <<
431 source "arch/arm64/Kconfig.platforms" <<
432 <<
433 menu "Kernel Features" <<
434 <<
435 menu "ARM errata workarounds via the alternati <<
436 <<
437 config AMPERE_ERRATUM_AC03_CPU_38 <<
438 bool "AmpereOne: AC03_CPU_38: Certain <<
439 default y <<
440 help <<
441 This option adds an alternative code <<
442 errata AC03_CPU_38 and AC04_CPU_10 o <<
443 <<
444 The affected design reports FEAT_HAF <<
445 ID_AA64MMFR1_EL1.HAFDBS, but (V)TCR_ <<
446 as required by the architecture. The <<
447 implementation suffers from an addit <<
448 A/D updates can occur after a PTE ha <<
449 <<
450 The workaround forces KVM to explici <<
451 which avoids enabling unadvertised h <<
452 at stage-2. <<
453 1158
454 If unsure, say Y. !! 1159 config GPIO_TXX9
>> 1160 select GPIOLIB
>> 1161 bool
455 1162
456 config ARM64_WORKAROUND_CLEAN_CACHE !! 1163 config FW_CFE
457 bool 1164 bool
458 1165
459 config ARM64_ERRATUM_826319 !! 1166 config ARCH_SUPPORTS_UPROBES
460 bool "Cortex-A53: 826319: System might !! 1167 bool
461 default y <<
462 select ARM64_WORKAROUND_CLEAN_CACHE <<
463 help <<
464 This option adds an alternative code <<
465 erratum 826319 on Cortex-A53 parts u <<
466 AXI master interface and an L2 cache <<
467 1168
468 If a Cortex-A53 uses an AMBA AXI4 AC !! 1169 config DMA_PERDEV_COHERENT
469 and is unable to accept a certain wr !! 1170 bool
470 not progress on read data presented !! 1171 select ARCH_HAS_SETUP_DMA_OPS
471 system can deadlock. !! 1172 select DMA_NONCOHERENT
472 1173
473 The workaround promotes data cache c !! 1174 config DMA_NONCOHERENT
474 data cache clean-and-invalidate. !! 1175 bool
475 Please note that this does not neces !! 1176 #
476 as it depends on the alternative fra !! 1177 # MIPS allows mixing "slightly different" Cacheability and Coherency
477 the kernel if an affected CPU is det !! 1178 # Attribute bits. It is believed that the uncached access through
>> 1179 # KSEG1 and the implementation specific "uncached accelerated" used
>> 1180 # by pgprot_writcombine can be mixed, and the latter sometimes provides
>> 1181 # significant advantages.
>> 1182 #
>> 1183 select ARCH_HAS_DMA_WRITE_COMBINE
>> 1184 select ARCH_HAS_DMA_PREP_COHERENT
>> 1185 select ARCH_HAS_SYNC_DMA_FOR_DEVICE
>> 1186 select ARCH_HAS_DMA_SET_UNCACHED
>> 1187 select DMA_NONCOHERENT_MMAP
>> 1188 select NEED_DMA_MAP_STATE
478 1189
479 If unsure, say Y. !! 1190 config SYS_HAS_EARLY_PRINTK
>> 1191 bool
480 1192
481 config ARM64_ERRATUM_827319 !! 1193 config SYS_SUPPORTS_HOTPLUG_CPU
482 bool "Cortex-A53: 827319: Data cache c !! 1194 bool
483 default y <<
484 select ARM64_WORKAROUND_CLEAN_CACHE <<
485 help <<
486 This option adds an alternative code <<
487 erratum 827319 on Cortex-A53 parts u <<
488 master interface and an L2 cache. <<
489 <<
490 Under certain conditions this erratu <<
491 to occur at the same time as another <<
492 on the AMBA 5 CHI interface, which c <<
493 interconnect reorders the two transa <<
494 <<
495 The workaround promotes data cache c <<
496 data cache clean-and-invalidate. <<
497 Please note that this does not neces <<
498 as it depends on the alternative fra <<
499 the kernel if an affected CPU is det <<
500 1195
501 If unsure, say Y. !! 1196 config MIPS_BONITO64
>> 1197 bool
502 1198
503 config ARM64_ERRATUM_824069 !! 1199 config MIPS_MSC
504 bool "Cortex-A53: 824069: Cache line m !! 1200 bool
505 default y <<
506 select ARM64_WORKAROUND_CLEAN_CACHE <<
507 help <<
508 This option adds an alternative code <<
509 erratum 824069 on Cortex-A53 parts u <<
510 to a coherent interconnect. <<
511 <<
512 If a Cortex-A53 processor is executi <<
513 write instruction at the same time a <<
514 cluster is executing a cache mainten <<
515 address, then this erratum might cau <<
516 incorrectly marked as dirty. <<
517 <<
518 The workaround promotes data cache c <<
519 data cache clean-and-invalidate. <<
520 Please note that this option does no <<
521 workaround, as it depends on the alt <<
522 only patch the kernel if an affected <<
523 1201
524 If unsure, say Y. !! 1202 config SYNC_R4K
>> 1203 bool
525 1204
526 config ARM64_ERRATUM_819472 !! 1205 config NO_IOPORT_MAP
527 bool "Cortex-A53: 819472: Store exclus !! 1206 def_bool n
528 default y <<
529 select ARM64_WORKAROUND_CLEAN_CACHE <<
530 help <<
531 This option adds an alternative code <<
532 erratum 819472 on Cortex-A53 parts u <<
533 present when it is connected to a co <<
534 <<
535 If the processor is executing a load <<
536 the same time as a processor in anot <<
537 maintenance operation to the same ad <<
538 cause data corruption. <<
539 <<
540 The workaround promotes data cache c <<
541 data cache clean-and-invalidate. <<
542 Please note that this does not neces <<
543 as it depends on the alternative fra <<
544 the kernel if an affected CPU is det <<
545 1207
546 If unsure, say Y. !! 1208 config GENERIC_CSUM
>> 1209 def_bool CPU_NO_LOAD_STORE_LR
547 1210
548 config ARM64_ERRATUM_832075 !! 1211 config GENERIC_ISA_DMA
549 bool "Cortex-A57: 832075: possible dea !! 1212 bool
550 default y !! 1213 select ZONE_DMA if GENERIC_ISA_DMA_SUPPORT_BROKEN=n
551 help !! 1214 select ISA_DMA_API
552 This option adds an alternative code <<
553 erratum 832075 on Cortex-A57 parts u <<
554 1215
555 Affected Cortex-A57 parts might dead !! 1216 config GENERIC_ISA_DMA_SUPPORT_BROKEN
556 instructions to Write-Back memory ar !! 1217 bool
>> 1218 select GENERIC_ISA_DMA
557 1219
558 The workaround is to promote device !! 1220 config HAVE_PLAT_DELAY
559 semantics. !! 1221 bool
560 Please note that this does not neces <<
561 as it depends on the alternative fra <<
562 the kernel if an affected CPU is det <<
563 1222
564 If unsure, say Y. !! 1223 config HAVE_PLAT_FW_INIT_CMDLINE
>> 1224 bool
565 1225
566 config ARM64_ERRATUM_834220 !! 1226 config HAVE_PLAT_MEMCPY
567 bool "Cortex-A57: 834220: Stage 2 tran !! 1227 bool
568 depends on KVM <<
569 help <<
570 This option adds an alternative code <<
571 erratum 834220 on Cortex-A57 parts u <<
572 <<
573 Affected Cortex-A57 parts might repo <<
574 fault as the result of a Stage 1 fau <<
575 page boundary when there is a permis <<
576 alignment fault at Stage 1 and a tra <<
577 <<
578 The workaround is to verify that the <<
579 doesn't generate a fault before hand <<
580 Please note that this does not neces <<
581 as it depends on the alternative fra <<
582 the kernel if an affected CPU is det <<
583 1228
584 If unsure, say N. !! 1229 config ISA_DMA_API
>> 1230 bool
585 1231
586 config ARM64_ERRATUM_1742098 !! 1232 config HOLES_IN_ZONE
587 bool "Cortex-A57/A72: 1742098: ELR rec !! 1233 bool
588 depends on COMPAT !! 1234
589 default y !! 1235 config SYS_SUPPORTS_RELOCATABLE
>> 1236 bool
590 help 1237 help
591 This option removes the AES hwcap fo !! 1238 Selected if the platform supports relocating the kernel.
592 workaround erratum 1742098 on Cortex !! 1239 The platform must provide plat_get_fdt() if it selects CONFIG_USE_OF
593 !! 1240 to allow access to command line and entropy sources.
594 Affected parts may corrupt the AES s <<
595 taken between a pair of AES instruct <<
596 are only present if the cryptography <<
597 All software should have a fallback <<
598 that don't implement the cryptograph <<
599 1241
600 If unsure, say Y. !! 1242 config MIPS_CBPF_JIT
>> 1243 def_bool y
>> 1244 depends on BPF_JIT && HAVE_CBPF_JIT
601 1245
602 config ARM64_ERRATUM_845719 !! 1246 config MIPS_EBPF_JIT
603 bool "Cortex-A53: 845719: a load might !! 1247 def_bool y
604 depends on COMPAT !! 1248 depends on BPF_JIT && HAVE_EBPF_JIT
605 default y <<
606 help <<
607 This option adds an alternative code <<
608 erratum 845719 on Cortex-A53 parts u <<
609 <<
610 When running a compat (AArch32) user <<
611 part, a load at EL0 from a virtual a <<
612 bits of the virtual address used by <<
613 might return incorrect data. <<
614 <<
615 The workaround is to write the conte <<
616 return to a 32-bit task. <<
617 Please note that this does not neces <<
618 as it depends on the alternative fra <<
619 the kernel if an affected CPU is det <<
620 1249
621 If unsure, say Y. <<
622 1250
623 config ARM64_ERRATUM_843419 !! 1251 #
624 bool "Cortex-A53: 843419: A load or st !! 1252 # Endianness selection. Sufficiently obscure so many users don't know what to
625 default y !! 1253 # answer,so we try hard to limit the available choices. Also the use of a
>> 1254 # choice statement should be more obvious to the user.
>> 1255 #
>> 1256 choice
>> 1257 prompt "Endianness selection"
626 help 1258 help
627 This option links the kernel with '- !! 1259 Some MIPS machines can be configured for either little or big endian
628 enables PLT support to replace certa !! 1260 byte order. These modes require different kernels and a different
629 cause subsequent memory accesses to !! 1261 Linux distribution. In general there is one preferred byteorder for a
630 Cortex-A53 parts up to r0p4. !! 1262 particular system but some systems are just as commonly used in the
>> 1263 one or the other endianness.
631 1264
632 If unsure, say Y. !! 1265 config CPU_BIG_ENDIAN
633 !! 1266 bool "Big endian"
634 config ARM64_LD_HAS_FIX_ERRATUM_843419 !! 1267 depends on SYS_SUPPORTS_BIG_ENDIAN
635 def_bool $(ld-option,--fix-cortex-a53- <<
636 <<
637 config ARM64_ERRATUM_1024718 <<
638 bool "Cortex-A55: 1024718: Update of D <<
639 default y <<
640 help <<
641 This option adds a workaround for AR <<
642 1268
643 Affected Cortex-A55 cores (all revis !! 1269 config CPU_LITTLE_ENDIAN
644 update of the hardware dirty bit whe !! 1270 bool "Little endian"
645 without a break-before-make. The wor !! 1271 depends on SYS_SUPPORTS_LITTLE_ENDIAN
646 of hardware DBM locally on the affec <<
647 this erratum will continue to use th <<
648 1272
649 If unsure, say Y. !! 1273 endchoice
650 1274
651 config ARM64_ERRATUM_1418040 !! 1275 config EXPORT_UASM
652 bool "Cortex-A76/Neoverse-N1: MRC read !! 1276 bool
653 default y <<
654 depends on COMPAT <<
655 help <<
656 This option adds a workaround for AR <<
657 errata 1188873 and 1418040. <<
658 1277
659 Affected Cortex-A76/Neoverse-N1 core !! 1278 config SYS_SUPPORTS_APM_EMULATION
660 cause register corruption when acces !! 1279 bool
661 from AArch32 userspace. <<
662 1280
663 If unsure, say Y. !! 1281 config SYS_SUPPORTS_BIG_ENDIAN
>> 1282 bool
664 1283
665 config ARM64_WORKAROUND_SPECULATIVE_AT !! 1284 config SYS_SUPPORTS_LITTLE_ENDIAN
666 bool 1285 bool
667 1286
668 config ARM64_ERRATUM_1165522 !! 1287 config SYS_SUPPORTS_HUGETLBFS
669 bool "Cortex-A76: 1165522: Speculative !! 1288 bool
>> 1289 depends on CPU_SUPPORTS_HUGEPAGES
670 default y 1290 default y
671 select ARM64_WORKAROUND_SPECULATIVE_AT <<
672 help <<
673 This option adds a workaround for AR <<
674 1291
675 Affected Cortex-A76 cores (r0p0, r1p !! 1292 config MIPS_HUGE_TLB_SUPPORT
676 corrupted TLBs by speculating an AT !! 1293 def_bool HUGETLB_PAGE || TRANSPARENT_HUGEPAGE
677 context switch. <<
678 1294
679 If unsure, say Y. !! 1295 config IRQ_MSP_SLP
>> 1296 bool
680 1297
681 config ARM64_ERRATUM_1319367 !! 1298 config IRQ_MSP_CIC
682 bool "Cortex-A57/A72: 1319537: Specula !! 1299 bool
683 default y <<
684 select ARM64_WORKAROUND_SPECULATIVE_AT <<
685 help <<
686 This option adds work arounds for AR <<
687 and A72 erratum 1319367 <<
688 1300
689 Cortex-A57 and A72 cores could end-u !! 1301 config IRQ_TXX9
690 speculating an AT instruction during !! 1302 bool
691 1303
692 If unsure, say Y. !! 1304 config IRQ_GT641XX
>> 1305 bool
693 1306
694 config ARM64_ERRATUM_1530923 !! 1307 config PCI_GT64XXX_PCI0
695 bool "Cortex-A55: 1530923: Speculative !! 1308 bool
696 default y <<
697 select ARM64_WORKAROUND_SPECULATIVE_AT <<
698 help <<
699 This option adds a workaround for AR <<
700 1309
701 Affected Cortex-A55 cores (r0p0, r0p !! 1310 config PCI_XTALK_BRIDGE
702 corrupted TLBs by speculating an AT !! 1311 bool
703 context switch. <<
704 1312
705 If unsure, say Y. !! 1313 config NO_EXCEPT_FILL
>> 1314 bool
706 1315
707 config ARM64_WORKAROUND_REPEAT_TLBI !! 1316 config MIPS_SPRAM
708 bool 1317 bool
709 1318
710 config ARM64_ERRATUM_2441007 !! 1319 config SWAP_IO_SPACE
711 bool "Cortex-A55: Completion of affect !! 1320 bool
712 select ARM64_WORKAROUND_REPEAT_TLBI <<
713 help <<
714 This option adds a workaround for AR <<
715 1321
716 Under very rare circumstances, affec !! 1322 config SGI_HAS_INDYDOG
717 may not handle a race between a brea !! 1323 bool
718 CPU, and another CPU accessing the s <<
719 store to a page that has been unmapp <<
720 1324
721 Work around this by adding the affec !! 1325 config SGI_HAS_HAL2
722 TLB sequences to be done twice. !! 1326 bool
723 1327
724 If unsure, say N. !! 1328 config SGI_HAS_SEEQ
>> 1329 bool
725 1330
726 config ARM64_ERRATUM_1286807 !! 1331 config SGI_HAS_WD93
727 bool "Cortex-A76: Modification of the !! 1332 bool
728 select ARM64_WORKAROUND_REPEAT_TLBI <<
729 help <<
730 This option adds a workaround for AR <<
731 <<
732 On the affected Cortex-A76 cores (r0 <<
733 address for a cacheable mapping of a <<
734 accessed by a core while another cor <<
735 address to a new physical page using <<
736 break-before-make sequence, then und <<
737 TLBI+DSB completes before a read usi <<
738 invalidated has been observed by oth <<
739 workaround repeats the TLBI+DSB oper <<
740 1333
741 If unsure, say N. !! 1334 config SGI_HAS_ZILOG
>> 1335 bool
742 1336
743 config ARM64_ERRATUM_1463225 !! 1337 config SGI_HAS_I8042
744 bool "Cortex-A76: Software Step might !! 1338 bool
745 default y <<
746 help <<
747 This option adds a workaround for Ar <<
748 1339
749 On the affected Cortex-A76 cores (r0 !! 1340 config DEFAULT_SGI_PARTITION
750 of a system call instruction (SVC) c !! 1341 bool
751 subsequent interrupts when software <<
752 exception handler of the system call <<
753 is enabled or VHE is in use. <<
754 1342
755 Work around the erratum by triggerin !! 1343 config FW_ARC32
756 when handling a system call from a t !! 1344 bool
757 in a VHE configuration of the kernel <<
758 1345
759 If unsure, say Y. !! 1346 config FW_SNIPROM
>> 1347 bool
760 1348
761 config ARM64_ERRATUM_1542419 !! 1349 config BOOT_ELF32
762 bool "Neoverse-N1: workaround mis-orde !! 1350 bool
763 help <<
764 This option adds a workaround for AR <<
765 1542419. <<
766 1351
767 Affected Neoverse-N1 cores could exe !! 1352 config MIPS_L1_CACHE_SHIFT_4
768 modified by another CPU. The workaro !! 1353 bool
769 counterpart. <<
770 1354
771 Workaround the issue by hiding the D !! 1355 config MIPS_L1_CACHE_SHIFT_5
772 forces user-space to perform cache m !! 1356 bool
773 1357
774 If unsure, say N. !! 1358 config MIPS_L1_CACHE_SHIFT_6
>> 1359 bool
775 1360
776 config ARM64_ERRATUM_1508412 !! 1361 config MIPS_L1_CACHE_SHIFT_7
777 bool "Cortex-A77: 1508412: workaround !! 1362 bool
778 default y <<
779 help <<
780 This option adds a workaround for Ar <<
781 1363
782 Affected Cortex-A77 cores (r0p0, r1p !! 1364 config MIPS_L1_CACHE_SHIFT
783 of a store-exclusive or read of PAR_ !! 1365 int
784 non-cacheable memory attributes. The !! 1366 default "7" if MIPS_L1_CACHE_SHIFT_7
785 counterpart. !! 1367 default "6" if MIPS_L1_CACHE_SHIFT_6
>> 1368 default "5" if MIPS_L1_CACHE_SHIFT_5
>> 1369 default "4" if MIPS_L1_CACHE_SHIFT_4
>> 1370 default "5"
786 1371
787 KVM guests must also have the workar !! 1372 config ARC_CMDLINE_ONLY
788 deadlock the system. !! 1373 bool
789 1374
790 Work around the issue by inserting D !! 1375 config ARC_CONSOLE
791 register reads and warning KVM users !! 1376 bool "ARC console support"
792 to prevent a speculative PAR_EL1 rea !! 1377 depends on SGI_IP22 || SGI_IP28 || (SNI_RM && CPU_LITTLE_ENDIAN)
793 1378
794 If unsure, say Y. !! 1379 config ARC_MEMORY
>> 1380 bool
795 1381
796 config ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MO !! 1382 config ARC_PROMLIB
797 bool 1383 bool
798 1384
799 config ARM64_ERRATUM_2051678 !! 1385 config FW_ARC64
800 bool "Cortex-A510: 2051678: disable Ha !! 1386 bool
801 default y <<
802 help <<
803 This options adds the workaround for <<
804 Affected Cortex-A510 might not respe <<
805 hardware update of the page table's <<
806 is to not enable the feature on affe <<
807 1387
808 If unsure, say Y. !! 1388 config BOOT_ELF64
>> 1389 bool
809 1390
810 config ARM64_ERRATUM_2077057 !! 1391 menu "CPU selection"
811 bool "Cortex-A510: 2077057: workaround <<
812 default y <<
813 help <<
814 This option adds the workaround for <<
815 Affected Cortex-A510 may corrupt SPS <<
816 expected, but a Pointer Authenticati <<
817 erratum causes SPSR_EL1 to be copied <<
818 EL1 to cause a return to EL2 with a <<
819 1392
820 This can only happen when EL2 is ste !! 1393 choice
>> 1394 prompt "CPU type"
>> 1395 default CPU_R4X00
821 1396
822 When these conditions occur, the SPS !! 1397 config CPU_LOONGSON64
823 previous guest entry, and can be res !! 1398 bool "Loongson 64-bit CPU"
>> 1399 depends on SYS_HAS_CPU_LOONGSON64
>> 1400 select ARCH_HAS_PHYS_TO_DMA
>> 1401 select CPU_MIPSR2
>> 1402 select CPU_HAS_PREFETCH
>> 1403 select CPU_SUPPORTS_64BIT_KERNEL
>> 1404 select CPU_SUPPORTS_HIGHMEM
>> 1405 select CPU_SUPPORTS_HUGEPAGES
>> 1406 select CPU_SUPPORTS_MSA
>> 1407 select CPU_DIEI_BROKEN if !LOONGSON3_ENHANCEMENT
>> 1408 select CPU_MIPSR2_IRQ_VI
>> 1409 select WEAK_ORDERING
>> 1410 select WEAK_REORDERING_BEYOND_LLSC
>> 1411 select MIPS_ASID_BITS_VARIABLE
>> 1412 select MIPS_PGD_C0_CONTEXT
>> 1413 select MIPS_L1_CACHE_SHIFT_6
>> 1414 select GPIOLIB
>> 1415 select SWIOTLB
>> 1416 select HAVE_KVM
>> 1417 help
>> 1418 The Loongson GSx64(GS264/GS464/GS464E/GS464V) series of processor
>> 1419 cores implements the MIPS64R2 instruction set with many extensions,
>> 1420 including most 64-bit Loongson-2 (2H, 2K) and Loongson-3 (3A1000,
>> 1421 3B1000, 3B1500, 3A2000, 3A3000 and 3A4000) processors. However, old
>> 1422 Loongson-2E/2F is not covered here and will be removed in future.
824 1423
825 If unsure, say Y. !! 1424 config LOONGSON3_ENHANCEMENT
>> 1425 bool "New Loongson-3 CPU Enhancements"
>> 1426 default n
>> 1427 depends on CPU_LOONGSON64
>> 1428 help
>> 1429 New Loongson-3 cores (since Loongson-3A R2, as opposed to Loongson-3A
>> 1430 R1, Loongson-3B R1 and Loongson-3B R2) has many enhancements, such as
>> 1431 FTLB, L1-VCache, EI/DI/Wait/Prefetch instruction, DSP/DSPr2 ASE, User
>> 1432 Local register, Read-Inhibit/Execute-Inhibit, SFB (Store Fill Buffer),
>> 1433 Fast TLB refill support, etc.
>> 1434
>> 1435 This option enable those enhancements which are not probed at run
>> 1436 time. If you want a generic kernel to run on all Loongson 3 machines,
>> 1437 please say 'N' here. If you want a high-performance kernel to run on
>> 1438 new Loongson-3 machines only, please say 'Y' here.
>> 1439
>> 1440 config CPU_LOONGSON3_WORKAROUNDS
>> 1441 bool "Old Loongson-3 LLSC Workarounds"
>> 1442 default y if SMP
>> 1443 depends on CPU_LOONGSON64
>> 1444 help
>> 1445 Loongson-3 processors have the llsc issues which require workarounds.
>> 1446 Without workarounds the system may hang unexpectedly.
>> 1447
>> 1448 Newer Loongson-3 will fix these issues and no workarounds are needed.
>> 1449 The workarounds have no significant side effect on them but may
>> 1450 decrease the performance of the system so this option should be
>> 1451 disabled unless the kernel is intended to be run on old systems.
>> 1452
>> 1453 If unsure, please say Y.
>> 1454
>> 1455 config CPU_LOONGSON3_CPUCFG_EMULATION
>> 1456 bool "Emulate the CPUCFG instruction on older Loongson cores"
>> 1457 default y
>> 1458 depends on CPU_LOONGSON64
>> 1459 help
>> 1460 Loongson-3A R4 and newer have the CPUCFG instruction available for
>> 1461 userland to query CPU capabilities, much like CPUID on x86. This
>> 1462 option provides emulation of the instruction on older Loongson
>> 1463 cores, back to Loongson-3A1000.
>> 1464
>> 1465 If unsure, please say Y.
>> 1466
>> 1467 config CPU_LOONGSON2E
>> 1468 bool "Loongson 2E"
>> 1469 depends on SYS_HAS_CPU_LOONGSON2E
>> 1470 select CPU_LOONGSON2EF
>> 1471 help
>> 1472 The Loongson 2E processor implements the MIPS III instruction set
>> 1473 with many extensions.
>> 1474
>> 1475 It has an internal FPGA northbridge, which is compatible to
>> 1476 bonito64.
>> 1477
>> 1478 config CPU_LOONGSON2F
>> 1479 bool "Loongson 2F"
>> 1480 depends on SYS_HAS_CPU_LOONGSON2F
>> 1481 select CPU_LOONGSON2EF
>> 1482 select GPIOLIB
>> 1483 help
>> 1484 The Loongson 2F processor implements the MIPS III instruction set
>> 1485 with many extensions.
>> 1486
>> 1487 Loongson2F have built-in DDR2 and PCIX controller. The PCIX controller
>> 1488 have a similar programming interface with FPGA northbridge used in
>> 1489 Loongson2E.
>> 1490
>> 1491 config CPU_LOONGSON1B
>> 1492 bool "Loongson 1B"
>> 1493 depends on SYS_HAS_CPU_LOONGSON1B
>> 1494 select CPU_LOONGSON32
>> 1495 select LEDS_GPIO_REGISTER
>> 1496 help
>> 1497 The Loongson 1B is a 32-bit SoC, which implements the MIPS32
>> 1498 Release 1 instruction set and part of the MIPS32 Release 2
>> 1499 instruction set.
>> 1500
>> 1501 config CPU_LOONGSON1C
>> 1502 bool "Loongson 1C"
>> 1503 depends on SYS_HAS_CPU_LOONGSON1C
>> 1504 select CPU_LOONGSON32
>> 1505 select LEDS_GPIO_REGISTER
>> 1506 help
>> 1507 The Loongson 1C is a 32-bit SoC, which implements the MIPS32
>> 1508 Release 1 instruction set and part of the MIPS32 Release 2
>> 1509 instruction set.
>> 1510
>> 1511 config CPU_MIPS32_R1
>> 1512 bool "MIPS32 Release 1"
>> 1513 depends on SYS_HAS_CPU_MIPS32_R1
>> 1514 select CPU_HAS_PREFETCH
>> 1515 select CPU_SUPPORTS_32BIT_KERNEL
>> 1516 select CPU_SUPPORTS_HIGHMEM
>> 1517 help
>> 1518 Choose this option to build a kernel for release 1 or later of the
>> 1519 MIPS32 architecture. Most modern embedded systems with a 32-bit
>> 1520 MIPS processor are based on a MIPS32 processor. If you know the
>> 1521 specific type of processor in your system, choose those that one
>> 1522 otherwise CPU_MIPS32_R1 is a safe bet for any MIPS32 system.
>> 1523 Release 2 of the MIPS32 architecture is available since several
>> 1524 years so chances are you even have a MIPS32 Release 2 processor
>> 1525 in which case you should choose CPU_MIPS32_R2 instead for better
>> 1526 performance.
>> 1527
>> 1528 config CPU_MIPS32_R2
>> 1529 bool "MIPS32 Release 2"
>> 1530 depends on SYS_HAS_CPU_MIPS32_R2
>> 1531 select CPU_HAS_PREFETCH
>> 1532 select CPU_SUPPORTS_32BIT_KERNEL
>> 1533 select CPU_SUPPORTS_HIGHMEM
>> 1534 select CPU_SUPPORTS_MSA
>> 1535 select HAVE_KVM
>> 1536 help
>> 1537 Choose this option to build a kernel for release 2 or later of the
>> 1538 MIPS32 architecture. Most modern embedded systems with a 32-bit
>> 1539 MIPS processor are based on a MIPS32 processor. If you know the
>> 1540 specific type of processor in your system, choose those that one
>> 1541 otherwise CPU_MIPS32_R1 is a safe bet for any MIPS32 system.
>> 1542
>> 1543 config CPU_MIPS32_R5
>> 1544 bool "MIPS32 Release 5"
>> 1545 depends on SYS_HAS_CPU_MIPS32_R5
>> 1546 select CPU_HAS_PREFETCH
>> 1547 select CPU_SUPPORTS_32BIT_KERNEL
>> 1548 select CPU_SUPPORTS_HIGHMEM
>> 1549 select CPU_SUPPORTS_MSA
>> 1550 select HAVE_KVM
>> 1551 select MIPS_O32_FP64_SUPPORT
>> 1552 help
>> 1553 Choose this option to build a kernel for release 5 or later of the
>> 1554 MIPS32 architecture. New MIPS processors, starting with the Warrior
>> 1555 family, are based on a MIPS32r5 processor. If you own an older
>> 1556 processor, you probably need to select MIPS32r1 or MIPS32r2 instead.
>> 1557
>> 1558 config CPU_MIPS32_R6
>> 1559 bool "MIPS32 Release 6"
>> 1560 depends on SYS_HAS_CPU_MIPS32_R6
>> 1561 select CPU_HAS_PREFETCH
>> 1562 select CPU_NO_LOAD_STORE_LR
>> 1563 select CPU_SUPPORTS_32BIT_KERNEL
>> 1564 select CPU_SUPPORTS_HIGHMEM
>> 1565 select CPU_SUPPORTS_MSA
>> 1566 select HAVE_KVM
>> 1567 select MIPS_O32_FP64_SUPPORT
>> 1568 help
>> 1569 Choose this option to build a kernel for release 6 or later of the
>> 1570 MIPS32 architecture. New MIPS processors, starting with the Warrior
>> 1571 family, are based on a MIPS32r6 processor. If you own an older
>> 1572 processor, you probably need to select MIPS32r1 or MIPS32r2 instead.
>> 1573
>> 1574 config CPU_MIPS64_R1
>> 1575 bool "MIPS64 Release 1"
>> 1576 depends on SYS_HAS_CPU_MIPS64_R1
>> 1577 select CPU_HAS_PREFETCH
>> 1578 select CPU_SUPPORTS_32BIT_KERNEL
>> 1579 select CPU_SUPPORTS_64BIT_KERNEL
>> 1580 select CPU_SUPPORTS_HIGHMEM
>> 1581 select CPU_SUPPORTS_HUGEPAGES
>> 1582 help
>> 1583 Choose this option to build a kernel for release 1 or later of the
>> 1584 MIPS64 architecture. Many modern embedded systems with a 64-bit
>> 1585 MIPS processor are based on a MIPS64 processor. If you know the
>> 1586 specific type of processor in your system, choose those that one
>> 1587 otherwise CPU_MIPS64_R1 is a safe bet for any MIPS64 system.
>> 1588 Release 2 of the MIPS64 architecture is available since several
>> 1589 years so chances are you even have a MIPS64 Release 2 processor
>> 1590 in which case you should choose CPU_MIPS64_R2 instead for better
>> 1591 performance.
>> 1592
>> 1593 config CPU_MIPS64_R2
>> 1594 bool "MIPS64 Release 2"
>> 1595 depends on SYS_HAS_CPU_MIPS64_R2
>> 1596 select CPU_HAS_PREFETCH
>> 1597 select CPU_SUPPORTS_32BIT_KERNEL
>> 1598 select CPU_SUPPORTS_64BIT_KERNEL
>> 1599 select CPU_SUPPORTS_HIGHMEM
>> 1600 select CPU_SUPPORTS_HUGEPAGES
>> 1601 select CPU_SUPPORTS_MSA
>> 1602 select HAVE_KVM
>> 1603 help
>> 1604 Choose this option to build a kernel for release 2 or later of the
>> 1605 MIPS64 architecture. Many modern embedded systems with a 64-bit
>> 1606 MIPS processor are based on a MIPS64 processor. If you know the
>> 1607 specific type of processor in your system, choose those that one
>> 1608 otherwise CPU_MIPS64_R1 is a safe bet for any MIPS64 system.
>> 1609
>> 1610 config CPU_MIPS64_R5
>> 1611 bool "MIPS64 Release 5"
>> 1612 depends on SYS_HAS_CPU_MIPS64_R5
>> 1613 select CPU_HAS_PREFETCH
>> 1614 select CPU_SUPPORTS_32BIT_KERNEL
>> 1615 select CPU_SUPPORTS_64BIT_KERNEL
>> 1616 select CPU_SUPPORTS_HIGHMEM
>> 1617 select CPU_SUPPORTS_HUGEPAGES
>> 1618 select CPU_SUPPORTS_MSA
>> 1619 select MIPS_O32_FP64_SUPPORT if 32BIT || MIPS32_O32
>> 1620 select HAVE_KVM
>> 1621 help
>> 1622 Choose this option to build a kernel for release 5 or later of the
>> 1623 MIPS64 architecture. This is a intermediate MIPS architecture
>> 1624 release partly implementing release 6 features. Though there is no
>> 1625 any hardware known to be based on this release.
>> 1626
>> 1627 config CPU_MIPS64_R6
>> 1628 bool "MIPS64 Release 6"
>> 1629 depends on SYS_HAS_CPU_MIPS64_R6
>> 1630 select CPU_HAS_PREFETCH
>> 1631 select CPU_NO_LOAD_STORE_LR
>> 1632 select CPU_SUPPORTS_32BIT_KERNEL
>> 1633 select CPU_SUPPORTS_64BIT_KERNEL
>> 1634 select CPU_SUPPORTS_HIGHMEM
>> 1635 select CPU_SUPPORTS_HUGEPAGES
>> 1636 select CPU_SUPPORTS_MSA
>> 1637 select MIPS_O32_FP64_SUPPORT if 32BIT || MIPS32_O32
>> 1638 select HAVE_KVM
>> 1639 help
>> 1640 Choose this option to build a kernel for release 6 or later of the
>> 1641 MIPS64 architecture. New MIPS processors, starting with the Warrior
>> 1642 family, are based on a MIPS64r6 processor. If you own an older
>> 1643 processor, you probably need to select MIPS64r1 or MIPS64r2 instead.
>> 1644
>> 1645 config CPU_P5600
>> 1646 bool "MIPS Warrior P5600"
>> 1647 depends on SYS_HAS_CPU_P5600
>> 1648 select CPU_HAS_PREFETCH
>> 1649 select CPU_SUPPORTS_32BIT_KERNEL
>> 1650 select CPU_SUPPORTS_HIGHMEM
>> 1651 select CPU_SUPPORTS_MSA
>> 1652 select CPU_SUPPORTS_CPUFREQ
>> 1653 select CPU_MIPSR2_IRQ_VI
>> 1654 select CPU_MIPSR2_IRQ_EI
>> 1655 select HAVE_KVM
>> 1656 select MIPS_O32_FP64_SUPPORT
>> 1657 help
>> 1658 Choose this option to build a kernel for MIPS Warrior P5600 CPU.
>> 1659 It's based on MIPS32r5 ISA with XPA, EVA, dual/quad issue exec pipes,
>> 1660 MMU with two-levels TLB, UCA, MSA, MDU core level features and system
>> 1661 level features like up to six P5600 calculation cores, CM2 with L2
>> 1662 cache, IOCU/IOMMU (though might be unused depending on the system-
>> 1663 specific IP core configuration), GIC, CPC, virtualisation module,
>> 1664 eJTAG and PDtrace.
>> 1665
>> 1666 config CPU_R3000
>> 1667 bool "R3000"
>> 1668 depends on SYS_HAS_CPU_R3000
>> 1669 select CPU_HAS_WB
>> 1670 select CPU_R3K_TLB
>> 1671 select CPU_SUPPORTS_32BIT_KERNEL
>> 1672 select CPU_SUPPORTS_HIGHMEM
>> 1673 help
>> 1674 Please make sure to pick the right CPU type. Linux/MIPS is not
>> 1675 designed to be generic, i.e. Kernels compiled for R3000 CPUs will
>> 1676 *not* work on R4000 machines and vice versa. However, since most
>> 1677 of the supported machines have an R4000 (or similar) CPU, R4x00
>> 1678 might be a safe bet. If the resulting kernel does not work,
>> 1679 try to recompile with R3000.
>> 1680
>> 1681 config CPU_TX39XX
>> 1682 bool "R39XX"
>> 1683 depends on SYS_HAS_CPU_TX39XX
>> 1684 select CPU_SUPPORTS_32BIT_KERNEL
>> 1685 select CPU_R3K_TLB
>> 1686
>> 1687 config CPU_VR41XX
>> 1688 bool "R41xx"
>> 1689 depends on SYS_HAS_CPU_VR41XX
>> 1690 select CPU_SUPPORTS_32BIT_KERNEL
>> 1691 select CPU_SUPPORTS_64BIT_KERNEL
>> 1692 help
>> 1693 The options selects support for the NEC VR4100 series of processors.
>> 1694 Only choose this option if you have one of these processors as a
>> 1695 kernel built with this option will not run on any other type of
>> 1696 processor or vice versa.
>> 1697
>> 1698 config CPU_R4300
>> 1699 bool "R4300"
>> 1700 depends on SYS_HAS_CPU_R4300
>> 1701 select CPU_SUPPORTS_32BIT_KERNEL
>> 1702 select CPU_SUPPORTS_64BIT_KERNEL
>> 1703 select CPU_HAS_LOAD_STORE_LR
>> 1704 help
>> 1705 MIPS Technologies R4300-series processors.
>> 1706
>> 1707 config CPU_R4X00
>> 1708 bool "R4x00"
>> 1709 depends on SYS_HAS_CPU_R4X00
>> 1710 select CPU_SUPPORTS_32BIT_KERNEL
>> 1711 select CPU_SUPPORTS_64BIT_KERNEL
>> 1712 select CPU_SUPPORTS_HUGEPAGES
>> 1713 help
>> 1714 MIPS Technologies R4000-series processors other than 4300, including
>> 1715 the R4000, R4400, R4600, and 4700.
>> 1716
>> 1717 config CPU_TX49XX
>> 1718 bool "R49XX"
>> 1719 depends on SYS_HAS_CPU_TX49XX
>> 1720 select CPU_HAS_PREFETCH
>> 1721 select CPU_SUPPORTS_32BIT_KERNEL
>> 1722 select CPU_SUPPORTS_64BIT_KERNEL
>> 1723 select CPU_SUPPORTS_HUGEPAGES
>> 1724
>> 1725 config CPU_R5000
>> 1726 bool "R5000"
>> 1727 depends on SYS_HAS_CPU_R5000
>> 1728 select CPU_SUPPORTS_32BIT_KERNEL
>> 1729 select CPU_SUPPORTS_64BIT_KERNEL
>> 1730 select CPU_SUPPORTS_HUGEPAGES
>> 1731 help
>> 1732 MIPS Technologies R5000-series processors other than the Nevada.
>> 1733
>> 1734 config CPU_R5500
>> 1735 bool "R5500"
>> 1736 depends on SYS_HAS_CPU_R5500
>> 1737 select CPU_SUPPORTS_32BIT_KERNEL
>> 1738 select CPU_SUPPORTS_64BIT_KERNEL
>> 1739 select CPU_SUPPORTS_HUGEPAGES
>> 1740 help
>> 1741 NEC VR5500 and VR5500A series processors implement 64-bit MIPS IV
>> 1742 instruction set.
>> 1743
>> 1744 config CPU_NEVADA
>> 1745 bool "RM52xx"
>> 1746 depends on SYS_HAS_CPU_NEVADA
>> 1747 select CPU_SUPPORTS_32BIT_KERNEL
>> 1748 select CPU_SUPPORTS_64BIT_KERNEL
>> 1749 select CPU_SUPPORTS_HUGEPAGES
>> 1750 help
>> 1751 QED / PMC-Sierra RM52xx-series ("Nevada") processors.
>> 1752
>> 1753 config CPU_R10000
>> 1754 bool "R10000"
>> 1755 depends on SYS_HAS_CPU_R10000
>> 1756 select CPU_HAS_PREFETCH
>> 1757 select CPU_SUPPORTS_32BIT_KERNEL
>> 1758 select CPU_SUPPORTS_64BIT_KERNEL
>> 1759 select CPU_SUPPORTS_HIGHMEM
>> 1760 select CPU_SUPPORTS_HUGEPAGES
>> 1761 help
>> 1762 MIPS Technologies R10000-series processors.
>> 1763
>> 1764 config CPU_RM7000
>> 1765 bool "RM7000"
>> 1766 depends on SYS_HAS_CPU_RM7000
>> 1767 select CPU_HAS_PREFETCH
>> 1768 select CPU_SUPPORTS_32BIT_KERNEL
>> 1769 select CPU_SUPPORTS_64BIT_KERNEL
>> 1770 select CPU_SUPPORTS_HIGHMEM
>> 1771 select CPU_SUPPORTS_HUGEPAGES
>> 1772
>> 1773 config CPU_SB1
>> 1774 bool "SB1"
>> 1775 depends on SYS_HAS_CPU_SB1
>> 1776 select CPU_SUPPORTS_32BIT_KERNEL
>> 1777 select CPU_SUPPORTS_64BIT_KERNEL
>> 1778 select CPU_SUPPORTS_HIGHMEM
>> 1779 select CPU_SUPPORTS_HUGEPAGES
>> 1780 select WEAK_ORDERING
>> 1781
>> 1782 config CPU_CAVIUM_OCTEON
>> 1783 bool "Cavium Octeon processor"
>> 1784 depends on SYS_HAS_CPU_CAVIUM_OCTEON
>> 1785 select CPU_HAS_PREFETCH
>> 1786 select CPU_SUPPORTS_64BIT_KERNEL
>> 1787 select WEAK_ORDERING
>> 1788 select CPU_SUPPORTS_HIGHMEM
>> 1789 select CPU_SUPPORTS_HUGEPAGES
>> 1790 select USB_EHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 1791 select USB_OHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 1792 select MIPS_L1_CACHE_SHIFT_7
>> 1793 select HAVE_KVM
>> 1794 help
>> 1795 The Cavium Octeon processor is a highly integrated chip containing
>> 1796 many ethernet hardware widgets for networking tasks. The processor
>> 1797 can have up to 16 Mips64v2 cores and 8 integrated gigabit ethernets.
>> 1798 Full details can be found at http://www.caviumnetworks.com.
>> 1799
>> 1800 config CPU_BMIPS
>> 1801 bool "Broadcom BMIPS"
>> 1802 depends on SYS_HAS_CPU_BMIPS
>> 1803 select CPU_MIPS32
>> 1804 select CPU_BMIPS32_3300 if SYS_HAS_CPU_BMIPS32_3300
>> 1805 select CPU_BMIPS4350 if SYS_HAS_CPU_BMIPS4350
>> 1806 select CPU_BMIPS4380 if SYS_HAS_CPU_BMIPS4380
>> 1807 select CPU_BMIPS5000 if SYS_HAS_CPU_BMIPS5000
>> 1808 select CPU_SUPPORTS_32BIT_KERNEL
>> 1809 select DMA_NONCOHERENT
>> 1810 select IRQ_MIPS_CPU
>> 1811 select SWAP_IO_SPACE
>> 1812 select WEAK_ORDERING
>> 1813 select CPU_SUPPORTS_HIGHMEM
>> 1814 select CPU_HAS_PREFETCH
>> 1815 select CPU_SUPPORTS_CPUFREQ
>> 1816 select MIPS_EXTERNAL_TIMER
>> 1817 help
>> 1818 Support for BMIPS32/3300/4350/4380 and BMIPS5000 processors.
>> 1819
>> 1820 config CPU_XLR
>> 1821 bool "Netlogic XLR SoC"
>> 1822 depends on SYS_HAS_CPU_XLR
>> 1823 select CPU_SUPPORTS_32BIT_KERNEL
>> 1824 select CPU_SUPPORTS_64BIT_KERNEL
>> 1825 select CPU_SUPPORTS_HIGHMEM
>> 1826 select CPU_SUPPORTS_HUGEPAGES
>> 1827 select WEAK_ORDERING
>> 1828 select WEAK_REORDERING_BEYOND_LLSC
>> 1829 help
>> 1830 Netlogic Microsystems XLR/XLS processors.
>> 1831
>> 1832 config CPU_XLP
>> 1833 bool "Netlogic XLP SoC"
>> 1834 depends on SYS_HAS_CPU_XLP
>> 1835 select CPU_SUPPORTS_32BIT_KERNEL
>> 1836 select CPU_SUPPORTS_64BIT_KERNEL
>> 1837 select CPU_SUPPORTS_HIGHMEM
>> 1838 select WEAK_ORDERING
>> 1839 select WEAK_REORDERING_BEYOND_LLSC
>> 1840 select CPU_HAS_PREFETCH
>> 1841 select CPU_MIPSR2
>> 1842 select CPU_SUPPORTS_HUGEPAGES
>> 1843 select MIPS_ASID_BITS_VARIABLE
>> 1844 help
>> 1845 Netlogic Microsystems XLP processors.
>> 1846 endchoice
826 1847
827 config ARM64_ERRATUM_2658417 !! 1848 config CPU_MIPS32_3_5_FEATURES
828 bool "Cortex-A510: 2658417: remove BF1 !! 1849 bool "MIPS32 Release 3.5 Features"
829 default y !! 1850 depends on SYS_HAS_CPU_MIPS32_R3_5
>> 1851 depends on CPU_MIPS32_R2 || CPU_MIPS32_R5 || CPU_MIPS32_R6 || \
>> 1852 CPU_P5600
>> 1853 help
>> 1854 Choose this option to build a kernel for release 2 or later of the
>> 1855 MIPS32 architecture including features from the 3.5 release such as
>> 1856 support for Enhanced Virtual Addressing (EVA).
>> 1857
>> 1858 config CPU_MIPS32_3_5_EVA
>> 1859 bool "Enhanced Virtual Addressing (EVA)"
>> 1860 depends on CPU_MIPS32_3_5_FEATURES
>> 1861 select EVA
>> 1862 default y
>> 1863 help
>> 1864 Choose this option if you want to enable the Enhanced Virtual
>> 1865 Addressing (EVA) on your MIPS32 core (such as proAptiv).
>> 1866 One of its primary benefits is an increase in the maximum size
>> 1867 of lowmem (up to 3GB). If unsure, say 'N' here.
>> 1868
>> 1869 config CPU_MIPS32_R5_FEATURES
>> 1870 bool "MIPS32 Release 5 Features"
>> 1871 depends on SYS_HAS_CPU_MIPS32_R5
>> 1872 depends on CPU_MIPS32_R2 || CPU_MIPS32_R5 || CPU_P5600
>> 1873 help
>> 1874 Choose this option to build a kernel for release 2 or later of the
>> 1875 MIPS32 architecture including features from release 5 such as
>> 1876 support for Extended Physical Addressing (XPA).
>> 1877
>> 1878 config CPU_MIPS32_R5_XPA
>> 1879 bool "Extended Physical Addressing (XPA)"
>> 1880 depends on CPU_MIPS32_R5_FEATURES
>> 1881 depends on !EVA
>> 1882 depends on !PAGE_SIZE_4KB
>> 1883 depends on SYS_SUPPORTS_HIGHMEM
>> 1884 select XPA
>> 1885 select HIGHMEM
>> 1886 select PHYS_ADDR_T_64BIT
>> 1887 default n
830 help 1888 help
831 This option adds the workaround for !! 1889 Choose this option if you want to enable the Extended Physical
832 Affected Cortex-A510 (r0p0 to r1p1) !! 1890 Addressing (XPA) on your MIPS32 core (such as P5600 series). The
833 BFMMLA or VMMLA instructions in rare !! 1891 benefit is to increase physical addressing equal to or greater
834 A510 CPUs are using shared neon hard !! 1892 than 40 bits. Note that this has the side effect of turning on
835 discoverable by the kernel, hide the !! 1893 64-bit addressing which in turn makes the PTEs 64-bit in size.
836 user-space should not be using these !! 1894 If unsure, say 'N' here.
837 1895
838 If unsure, say Y. !! 1896 if CPU_LOONGSON2F
>> 1897 config CPU_NOP_WORKAROUNDS
>> 1898 bool
>> 1899
>> 1900 config CPU_JUMP_WORKAROUNDS
>> 1901 bool
839 1902
840 config ARM64_ERRATUM_2119858 !! 1903 config CPU_LOONGSON2F_WORKAROUNDS
841 bool "Cortex-A710/X2: 2119858: workaro !! 1904 bool "Loongson 2F Workarounds"
842 default y 1905 default y
843 depends on CORESIGHT_TRBE !! 1906 select CPU_NOP_WORKAROUNDS
844 select ARM64_WORKAROUND_TRBE_OVERWRITE !! 1907 select CPU_JUMP_WORKAROUNDS
845 help 1908 help
846 This option adds the workaround for !! 1909 Loongson 2F01 / 2F02 processors have the NOP & JUMP issues which
>> 1910 require workarounds. Without workarounds the system may hang
>> 1911 unexpectedly. For more information please refer to the gas
>> 1912 -mfix-loongson2f-nop and -mfix-loongson2f-jump options.
>> 1913
>> 1914 Loongson 2F03 and later have fixed these issues and no workarounds
>> 1915 are needed. The workarounds have no significant side effect on them
>> 1916 but may decrease the performance of the system so this option should
>> 1917 be disabled unless the kernel is intended to be run on 2F01 or 2F02
>> 1918 systems.
847 1919
848 Affected Cortex-A710/X2 cores could !! 1920 If unsure, please say Y.
849 data at the base of the buffer (poin !! 1921 endif # CPU_LOONGSON2F
850 the event of a WRAP event. <<
851 1922
852 Work around the issue by always maki !! 1923 config SYS_SUPPORTS_ZBOOT
853 256 bytes before enabling the buffer !! 1924 bool
854 the buffer with ETM ignore packets u !! 1925 select HAVE_KERNEL_GZIP
>> 1926 select HAVE_KERNEL_BZIP2
>> 1927 select HAVE_KERNEL_LZ4
>> 1928 select HAVE_KERNEL_LZMA
>> 1929 select HAVE_KERNEL_LZO
>> 1930 select HAVE_KERNEL_XZ
>> 1931 select HAVE_KERNEL_ZSTD
855 1932
856 If unsure, say Y. !! 1933 config SYS_SUPPORTS_ZBOOT_UART16550
>> 1934 bool
>> 1935 select SYS_SUPPORTS_ZBOOT
857 1936
858 config ARM64_ERRATUM_2139208 !! 1937 config SYS_SUPPORTS_ZBOOT_UART_PROM
859 bool "Neoverse-N2: 2139208: workaround !! 1938 bool
860 default y !! 1939 select SYS_SUPPORTS_ZBOOT
861 depends on CORESIGHT_TRBE <<
862 select ARM64_WORKAROUND_TRBE_OVERWRITE <<
863 help <<
864 This option adds the workaround for <<
865 1940
866 Affected Neoverse-N2 cores could ove !! 1941 config CPU_LOONGSON2EF
867 data at the base of the buffer (poin !! 1942 bool
868 the event of a WRAP event. !! 1943 select CPU_SUPPORTS_32BIT_KERNEL
>> 1944 select CPU_SUPPORTS_64BIT_KERNEL
>> 1945 select CPU_SUPPORTS_HIGHMEM
>> 1946 select CPU_SUPPORTS_HUGEPAGES
>> 1947 select ARCH_HAS_PHYS_TO_DMA
869 1948
870 Work around the issue by always maki !! 1949 config CPU_LOONGSON32
871 256 bytes before enabling the buffer !! 1950 bool
872 the buffer with ETM ignore packets u !! 1951 select CPU_MIPS32
>> 1952 select CPU_MIPSR2
>> 1953 select CPU_HAS_PREFETCH
>> 1954 select CPU_SUPPORTS_32BIT_KERNEL
>> 1955 select CPU_SUPPORTS_HIGHMEM
>> 1956 select CPU_SUPPORTS_CPUFREQ
873 1957
874 If unsure, say Y. !! 1958 config CPU_BMIPS32_3300
>> 1959 select SMP_UP if SMP
>> 1960 bool
875 1961
876 config ARM64_WORKAROUND_TSB_FLUSH_FAILURE !! 1962 config CPU_BMIPS4350
877 bool 1963 bool
>> 1964 select SYS_SUPPORTS_SMP
>> 1965 select SYS_SUPPORTS_HOTPLUG_CPU
878 1966
879 config ARM64_ERRATUM_2054223 !! 1967 config CPU_BMIPS4380
880 bool "Cortex-A710: 2054223: workaround !! 1968 bool
881 default y !! 1969 select MIPS_L1_CACHE_SHIFT_6
882 select ARM64_WORKAROUND_TSB_FLUSH_FAIL !! 1970 select SYS_SUPPORTS_SMP
883 help !! 1971 select SYS_SUPPORTS_HOTPLUG_CPU
884 Enable workaround for ARM Cortex-A71 !! 1972 select CPU_HAS_RIXI
885 1973
886 Affected cores may fail to flush the !! 1974 config CPU_BMIPS5000
887 the PE is in trace prohibited state. !! 1975 bool
888 of the trace cached. !! 1976 select MIPS_CPU_SCACHE
>> 1977 select MIPS_L1_CACHE_SHIFT_7
>> 1978 select SYS_SUPPORTS_SMP
>> 1979 select SYS_SUPPORTS_HOTPLUG_CPU
>> 1980 select CPU_HAS_RIXI
889 1981
890 Workaround is to issue two TSB conse !! 1982 config SYS_HAS_CPU_LOONGSON64
>> 1983 bool
>> 1984 select CPU_SUPPORTS_CPUFREQ
>> 1985 select CPU_HAS_RIXI
891 1986
892 If unsure, say Y. !! 1987 config SYS_HAS_CPU_LOONGSON2E
>> 1988 bool
893 1989
894 config ARM64_ERRATUM_2067961 !! 1990 config SYS_HAS_CPU_LOONGSON2F
895 bool "Neoverse-N2: 2067961: workaround !! 1991 bool
896 default y !! 1992 select CPU_SUPPORTS_CPUFREQ
897 select ARM64_WORKAROUND_TSB_FLUSH_FAIL !! 1993 select CPU_SUPPORTS_ADDRWINCFG if 64BIT
898 help !! 1994
899 Enable workaround for ARM Neoverse-N !! 1995 config SYS_HAS_CPU_LOONGSON1B
>> 1996 bool
900 1997
901 Affected cores may fail to flush the !! 1998 config SYS_HAS_CPU_LOONGSON1C
902 the PE is in trace prohibited state. !! 1999 bool
903 of the trace cached. <<
904 2000
905 Workaround is to issue two TSB conse !! 2001 config SYS_HAS_CPU_MIPS32_R1
>> 2002 bool
906 2003
907 If unsure, say Y. !! 2004 config SYS_HAS_CPU_MIPS32_R2
>> 2005 bool
908 2006
909 config ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANG !! 2007 config SYS_HAS_CPU_MIPS32_R3_5
910 bool 2008 bool
911 2009
912 config ARM64_ERRATUM_2253138 !! 2010 config SYS_HAS_CPU_MIPS32_R5
913 bool "Neoverse-N2: 2253138: workaround !! 2011 bool
914 depends on CORESIGHT_TRBE !! 2012 select ARCH_HAS_SYNC_DMA_FOR_CPU if DMA_NONCOHERENT
915 default y <<
916 select ARM64_WORKAROUND_TRBE_WRITE_OUT <<
917 help <<
918 This option adds the workaround for <<
919 2013
920 Affected Neoverse-N2 cores might wri !! 2014 config SYS_HAS_CPU_MIPS32_R6
921 for TRBE. Under some conditions, the !! 2015 bool
922 virtually addressed page following t !! 2016 select ARCH_HAS_SYNC_DMA_FOR_CPU if DMA_NONCOHERENT
923 (i.e., the TRBLIMITR_EL1.LIMIT), ins <<
924 2017
925 Work around this in the driver by al !! 2018 config SYS_HAS_CPU_MIPS64_R1
926 page beyond the TRBLIMITR_EL1.LIMIT, !! 2019 bool
927 2020
928 If unsure, say Y. !! 2021 config SYS_HAS_CPU_MIPS64_R2
>> 2022 bool
929 2023
930 config ARM64_ERRATUM_2224489 !! 2024 config SYS_HAS_CPU_MIPS64_R6
931 bool "Cortex-A710/X2: 2224489: workaro !! 2025 bool
932 depends on CORESIGHT_TRBE !! 2026 select ARCH_HAS_SYNC_DMA_FOR_CPU if DMA_NONCOHERENT
933 default y <<
934 select ARM64_WORKAROUND_TRBE_WRITE_OUT <<
935 help <<
936 This option adds the workaround for <<
937 2027
938 Affected Cortex-A710/X2 cores might !! 2028 config SYS_HAS_CPU_P5600
939 for TRBE. Under some conditions, the !! 2029 bool
940 virtually addressed page following t !! 2030 select ARCH_HAS_SYNC_DMA_FOR_CPU if DMA_NONCOHERENT
941 (i.e., the TRBLIMITR_EL1.LIMIT), ins <<
942 2031
943 Work around this in the driver by al !! 2032 config SYS_HAS_CPU_R3000
944 page beyond the TRBLIMITR_EL1.LIMIT, !! 2033 bool
945 2034
946 If unsure, say Y. !! 2035 config SYS_HAS_CPU_TX39XX
>> 2036 bool
947 2037
948 config ARM64_ERRATUM_2441009 !! 2038 config SYS_HAS_CPU_VR41XX
949 bool "Cortex-A510: Completion of affec !! 2039 bool
950 select ARM64_WORKAROUND_REPEAT_TLBI <<
951 help <<
952 This option adds a workaround for AR <<
953 <<
954 Under very rare circumstances, affec <<
955 may not handle a race between a brea <<
956 CPU, and another CPU accessing the s <<
957 store to a page that has been unmapp <<
958 2040
959 Work around this by adding the affec !! 2041 config SYS_HAS_CPU_R4300
960 TLB sequences to be done twice. !! 2042 bool
961 2043
962 If unsure, say N. !! 2044 config SYS_HAS_CPU_R4X00
>> 2045 bool
963 2046
964 config ARM64_ERRATUM_2064142 !! 2047 config SYS_HAS_CPU_TX49XX
965 bool "Cortex-A510: 2064142: workaround !! 2048 bool
966 depends on CORESIGHT_TRBE <<
967 default y <<
968 help <<
969 This option adds the workaround for <<
970 2049
971 Affected Cortex-A510 core might fail !! 2050 config SYS_HAS_CPU_R5000
972 TRBE has been disabled. Under some c !! 2051 bool
973 writes into TRBE registers TRBLIMITR <<
974 and TRBTRG_EL1 will be ignored and w <<
975 2052
976 Work around this in the driver by ex !! 2053 config SYS_HAS_CPU_R5500
977 is stopped and before performing a s !! 2054 bool
978 registers. <<
979 2055
980 If unsure, say Y. !! 2056 config SYS_HAS_CPU_NEVADA
>> 2057 bool
981 2058
982 config ARM64_ERRATUM_2038923 !! 2059 config SYS_HAS_CPU_R10000
983 bool "Cortex-A510: 2038923: workaround !! 2060 bool
984 depends on CORESIGHT_TRBE !! 2061 select ARCH_HAS_SYNC_DMA_FOR_CPU if DMA_NONCOHERENT
985 default y <<
986 help <<
987 This option adds the workaround for <<
988 <<
989 Affected Cortex-A510 core might caus <<
990 prohibited within the CPU. As a resu <<
991 might be corrupted. This happens aft <<
992 TRBLIMITR_EL1.E, followed by just a <<
993 execution changes from a context, in <<
994 isn't, or vice versa. In these menti <<
995 is prohibited is inconsistent betwee <<
996 the trace buffer state might be corr <<
997 <<
998 Work around this in the driver by pr <<
999 trace is prohibited or not based on <<
1000 change to TRBLIMITR_EL1.E with at l <<
1001 two ISB instructions if no ERET is <<
1002 2062
1003 If unsure, say Y. !! 2063 config SYS_HAS_CPU_RM7000
>> 2064 bool
1004 2065
1005 config ARM64_ERRATUM_1902691 !! 2066 config SYS_HAS_CPU_SB1
1006 bool "Cortex-A510: 1902691: workaroun !! 2067 bool
1007 depends on CORESIGHT_TRBE <<
1008 default y <<
1009 help <<
1010 This option adds the workaround for <<
1011 2068
1012 Affected Cortex-A510 core might cau !! 2069 config SYS_HAS_CPU_CAVIUM_OCTEON
1013 into the memory. Effectively TRBE i !! 2070 bool
1014 trace data. <<
1015 2071
1016 Work around this problem in the dri !! 2072 config SYS_HAS_CPU_BMIPS
1017 affected cpus. The firmware must ha !! 2073 bool
1018 on such implementations. This will <<
1019 do this already. <<
1020 2074
1021 If unsure, say Y. !! 2075 config SYS_HAS_CPU_BMIPS32_3300
>> 2076 bool
>> 2077 select SYS_HAS_CPU_BMIPS
1022 2078
1023 config ARM64_ERRATUM_2457168 !! 2079 config SYS_HAS_CPU_BMIPS4350
1024 bool "Cortex-A510: 2457168: workaroun !! 2080 bool
1025 depends on ARM64_AMU_EXTN !! 2081 select SYS_HAS_CPU_BMIPS
1026 default y <<
1027 help <<
1028 This option adds the workaround for <<
1029 2082
1030 The AMU counter AMEVCNTR01 (constan !! 2083 config SYS_HAS_CPU_BMIPS4380
1031 as the system counter. On affected !! 2084 bool
1032 incorrectly giving a significantly !! 2085 select SYS_HAS_CPU_BMIPS
1033 2086
1034 Work around this problem by returni !! 2087 config SYS_HAS_CPU_BMIPS5000
1035 key locations that results in disab !! 2088 bool
1036 is the same to firmware disabling a !! 2089 select SYS_HAS_CPU_BMIPS
>> 2090 select ARCH_HAS_SYNC_DMA_FOR_CPU
1037 2091
1038 If unsure, say Y. !! 2092 config SYS_HAS_CPU_XLR
>> 2093 bool
1039 2094
1040 config ARM64_ERRATUM_2645198 !! 2095 config SYS_HAS_CPU_XLP
1041 bool "Cortex-A715: 2645198: Workaroun !! 2096 bool
1042 default y <<
1043 help <<
1044 This option adds the workaround for <<
1045 2097
1046 If a Cortex-A715 cpu sees a page ma !! 2098 #
1047 to non-executable, it may corrupt t !! 2099 # CPU may reorder R->R, R->W, W->R, W->W
1048 next instruction abort caused by pe !! 2100 # Reordering beyond LL and SC is handled in WEAK_REORDERING_BEYOND_LLSC
>> 2101 #
>> 2102 config WEAK_ORDERING
>> 2103 bool
1049 2104
1050 Only user-space does executable to !! 2105 #
1051 mprotect() system call. Workaround !! 2106 # CPU may reorder reads and writes beyond LL/SC
1052 TLB invalidation, for all changes t !! 2107 # CPU may reorder R->LL, R->LL, W->LL, W->LL, R->SC, R->SC, W->SC, W->SC
>> 2108 #
>> 2109 config WEAK_REORDERING_BEYOND_LLSC
>> 2110 bool
>> 2111 endmenu
1053 2112
1054 If unsure, say Y. !! 2113 #
>> 2114 # These two indicate any level of the MIPS32 and MIPS64 architecture
>> 2115 #
>> 2116 config CPU_MIPS32
>> 2117 bool
>> 2118 default y if CPU_MIPS32_R1 || CPU_MIPS32_R2 || CPU_MIPS32_R5 || \
>> 2119 CPU_MIPS32_R6 || CPU_P5600
1055 2120
1056 config ARM64_WORKAROUND_SPECULATIVE_UNPRIV_LO !! 2121 config CPU_MIPS64
1057 bool 2122 bool
>> 2123 default y if CPU_MIPS64_R1 || CPU_MIPS64_R2 || CPU_MIPS64_R5 || \
>> 2124 CPU_MIPS64_R6
1058 2125
1059 config ARM64_ERRATUM_2966298 !! 2126 #
1060 bool "Cortex-A520: 2966298: workaroun !! 2127 # These indicate the revision of the architecture
1061 select ARM64_WORKAROUND_SPECULATIVE_U !! 2128 #
1062 default y !! 2129 config CPU_MIPSR1
1063 help !! 2130 bool
1064 This option adds the workaround for !! 2131 default y if CPU_MIPS32_R1 || CPU_MIPS64_R1
1065 2132
1066 On an affected Cortex-A520 core, a !! 2133 config CPU_MIPSR2
1067 load might leak data from a privile !! 2134 bool
>> 2135 default y if CPU_MIPS32_R2 || CPU_MIPS64_R2 || CPU_CAVIUM_OCTEON
>> 2136 select CPU_HAS_RIXI
>> 2137 select CPU_HAS_DIEI if !CPU_DIEI_BROKEN
>> 2138 select MIPS_SPRAM
1068 2139
1069 Work around this problem by executi !! 2140 config CPU_MIPSR5
>> 2141 bool
>> 2142 default y if CPU_MIPS32_R5 || CPU_MIPS64_R5 || CPU_P5600
>> 2143 select CPU_HAS_RIXI
>> 2144 select CPU_HAS_DIEI if !CPU_DIEI_BROKEN
>> 2145 select MIPS_SPRAM
1070 2146
1071 If unsure, say Y. !! 2147 config CPU_MIPSR6
>> 2148 bool
>> 2149 default y if CPU_MIPS32_R6 || CPU_MIPS64_R6
>> 2150 select CPU_HAS_RIXI
>> 2151 select CPU_HAS_DIEI if !CPU_DIEI_BROKEN
>> 2152 select HAVE_ARCH_BITREVERSE
>> 2153 select MIPS_ASID_BITS_VARIABLE
>> 2154 select MIPS_CRC_SUPPORT
>> 2155 select MIPS_SPRAM
1072 2156
1073 config ARM64_ERRATUM_3117295 !! 2157 config TARGET_ISA_REV
1074 bool "Cortex-A510: 3117295: workaroun !! 2158 int
1075 select ARM64_WORKAROUND_SPECULATIVE_U !! 2159 default 1 if CPU_MIPSR1
1076 default y !! 2160 default 2 if CPU_MIPSR2
>> 2161 default 5 if CPU_MIPSR5
>> 2162 default 6 if CPU_MIPSR6
>> 2163 default 0
1077 help 2164 help
1078 This option adds the workaround for !! 2165 Reflects the ISA revision being targeted by the kernel build. This
>> 2166 is effectively the Kconfig equivalent of MIPS_ISA_REV.
1079 2167
1080 On an affected Cortex-A510 core, a !! 2168 config EVA
1081 load might leak data from a privile !! 2169 bool
1082 <<
1083 Work around this problem by executi <<
1084 2170
1085 If unsure, say Y. !! 2171 config XPA
>> 2172 bool
1086 2173
1087 config ARM64_ERRATUM_3194386 !! 2174 config SYS_SUPPORTS_32BIT_KERNEL
1088 bool "Cortex-*/Neoverse-*: workaround !! 2175 bool
1089 default y !! 2176 config SYS_SUPPORTS_64BIT_KERNEL
1090 help !! 2177 bool
1091 This option adds the workaround for !! 2178 config CPU_SUPPORTS_32BIT_KERNEL
>> 2179 bool
>> 2180 config CPU_SUPPORTS_64BIT_KERNEL
>> 2181 bool
>> 2182 config CPU_SUPPORTS_CPUFREQ
>> 2183 bool
>> 2184 config CPU_SUPPORTS_ADDRWINCFG
>> 2185 bool
>> 2186 config CPU_SUPPORTS_HUGEPAGES
>> 2187 bool
>> 2188 depends on !(32BIT && (ARCH_PHYS_ADDR_T_64BIT || EVA))
>> 2189 config MIPS_PGD_C0_CONTEXT
>> 2190 bool
>> 2191 default y if 64BIT && (CPU_MIPSR2 || CPU_MIPSR6) && !CPU_XLP
1092 2192
1093 * ARM Cortex-A76 erratum 3324349 !! 2193 #
1094 * ARM Cortex-A77 erratum 3324348 !! 2194 # Set to y for ptrace access to watch registers.
1095 * ARM Cortex-A78 erratum 3324344 !! 2195 #
1096 * ARM Cortex-A78C erratum 3324346 !! 2196 config HARDWARE_WATCHPOINTS
1097 * ARM Cortex-A78C erratum 3324347 !! 2197 bool
1098 * ARM Cortex-A710 erratam 3324338 !! 2198 default y if CPU_MIPSR1 || CPU_MIPSR2 || CPU_MIPSR6
1099 * ARM Cortex-A715 errartum 3456084 <<
1100 * ARM Cortex-A720 erratum 3456091 <<
1101 * ARM Cortex-A725 erratum 3456106 <<
1102 * ARM Cortex-X1 erratum 3324344 <<
1103 * ARM Cortex-X1C erratum 3324346 <<
1104 * ARM Cortex-X2 erratum 3324338 <<
1105 * ARM Cortex-X3 erratum 3324335 <<
1106 * ARM Cortex-X4 erratum 3194386 <<
1107 * ARM Cortex-X925 erratum 3324334 <<
1108 * ARM Neoverse-N1 erratum 3324349 <<
1109 * ARM Neoverse N2 erratum 3324339 <<
1110 * ARM Neoverse-N3 erratum 3456111 <<
1111 * ARM Neoverse-V1 erratum 3324341 <<
1112 * ARM Neoverse V2 erratum 3324336 <<
1113 * ARM Neoverse-V3 erratum 3312417 <<
1114 <<
1115 On affected cores "MSR SSBS, #0" in <<
1116 subsequent speculative instructions <<
1117 speculative store bypassing. <<
1118 <<
1119 Work around this problem by placing <<
1120 Instruction Synchronization Barrier <<
1121 SSBS. The presence of the SSBS spec <<
1122 from hwcaps and EL0 reads of ID_AA6 <<
1123 will use the PR_SPEC_STORE_BYPASS p <<
1124 2199
1125 If unsure, say Y. !! 2200 menu "Kernel type"
1126 2201
1127 config CAVIUM_ERRATUM_22375 !! 2202 choice
1128 bool "Cavium erratum 22375, 24313" !! 2203 prompt "Kernel code model"
1129 default y <<
1130 help 2204 help
1131 Enable workaround for errata 22375 !! 2205 You should only select this option if you have a workload that
>> 2206 actually benefits from 64-bit processing or if your machine has
>> 2207 large memory. You will only be presented a single option in this
>> 2208 menu if your system does not support both 32-bit and 64-bit kernels.
>> 2209
>> 2210 config 32BIT
>> 2211 bool "32-bit kernel"
>> 2212 depends on CPU_SUPPORTS_32BIT_KERNEL && SYS_SUPPORTS_32BIT_KERNEL
>> 2213 select TRAD_SIGNALS
>> 2214 help
>> 2215 Select this option if you want to build a 32-bit kernel.
1132 2216
1133 This implements two gicv3-its errat !! 2217 config 64BIT
1134 with a small impact affecting only !! 2218 bool "64-bit kernel"
>> 2219 depends on CPU_SUPPORTS_64BIT_KERNEL && SYS_SUPPORTS_64BIT_KERNEL
>> 2220 help
>> 2221 Select this option if you want to build a 64-bit kernel.
1135 2222
1136 erratum 22375: only alloc 8MB tab !! 2223 endchoice
1137 erratum 24313: ignore memory acce <<
1138 2224
1139 The fixes are in ITS initialization !! 2225 config KVM_GUEST
1140 type and table size provided by the !! 2226 bool "KVM Guest Kernel"
>> 2227 depends on CPU_MIPS32_R2
>> 2228 depends on !64BIT && BROKEN_ON_SMP
>> 2229 help
>> 2230 Select this option if building a guest kernel for KVM (Trap & Emulate)
>> 2231 mode.
>> 2232
>> 2233 config KVM_GUEST_TIMER_FREQ
>> 2234 int "Count/Compare Timer Frequency (MHz)"
>> 2235 depends on KVM_GUEST
>> 2236 default 100
>> 2237 help
>> 2238 Set this to non-zero if building a guest kernel for KVM to skip RTC
>> 2239 emulation when determining guest CPU Frequency. Instead, the guest's
>> 2240 timer frequency is specified directly.
>> 2241
>> 2242 config MIPS_VA_BITS_48
>> 2243 bool "48 bits virtual memory"
>> 2244 depends on 64BIT
>> 2245 help
>> 2246 Support a maximum at least 48 bits of application virtual
>> 2247 memory. Default is 40 bits or less, depending on the CPU.
>> 2248 For page sizes 16k and above, this option results in a small
>> 2249 memory overhead for page tables. For 4k page size, a fourth
>> 2250 level of page tables is added which imposes both a memory
>> 2251 overhead as well as slower TLB fault handling.
1141 2252
1142 If unsure, say Y. !! 2253 If unsure, say N.
1143 2254
1144 config CAVIUM_ERRATUM_23144 !! 2255 choice
1145 bool "Cavium erratum 23144: ITS SYNC !! 2256 prompt "Kernel page size"
1146 depends on NUMA !! 2257 default PAGE_SIZE_4KB
1147 default y <<
1148 help <<
1149 ITS SYNC command hang for cross nod <<
1150 2258
1151 If unsure, say Y. !! 2259 config PAGE_SIZE_4KB
>> 2260 bool "4kB"
>> 2261 depends on !CPU_LOONGSON2EF && !CPU_LOONGSON64
>> 2262 help
>> 2263 This option select the standard 4kB Linux page size. On some
>> 2264 R3000-family processors this is the only available page size. Using
>> 2265 4kB page size will minimize memory consumption and is therefore
>> 2266 recommended for low memory systems.
>> 2267
>> 2268 config PAGE_SIZE_8KB
>> 2269 bool "8kB"
>> 2270 depends on CPU_CAVIUM_OCTEON
>> 2271 depends on !MIPS_VA_BITS_48
>> 2272 help
>> 2273 Using 8kB page size will result in higher performance kernel at
>> 2274 the price of higher memory consumption. This option is available
>> 2275 only on cnMIPS processors. Note that you will need a suitable Linux
>> 2276 distribution to support this.
>> 2277
>> 2278 config PAGE_SIZE_16KB
>> 2279 bool "16kB"
>> 2280 depends on !CPU_R3000 && !CPU_TX39XX
>> 2281 help
>> 2282 Using 16kB page size will result in higher performance kernel at
>> 2283 the price of higher memory consumption. This option is available on
>> 2284 all non-R3000 family processors. Note that you will need a suitable
>> 2285 Linux distribution to support this.
>> 2286
>> 2287 config PAGE_SIZE_32KB
>> 2288 bool "32kB"
>> 2289 depends on CPU_CAVIUM_OCTEON
>> 2290 depends on !MIPS_VA_BITS_48
>> 2291 help
>> 2292 Using 32kB page size will result in higher performance kernel at
>> 2293 the price of higher memory consumption. This option is available
>> 2294 only on cnMIPS cores. Note that you will need a suitable Linux
>> 2295 distribution to support this.
>> 2296
>> 2297 config PAGE_SIZE_64KB
>> 2298 bool "64kB"
>> 2299 depends on !CPU_R3000 && !CPU_TX39XX
>> 2300 help
>> 2301 Using 64kB page size will result in higher performance kernel at
>> 2302 the price of higher memory consumption. This option is available on
>> 2303 all non-R3000 family processor. Not that at the time of this
>> 2304 writing this option is still high experimental.
1152 2305
1153 config CAVIUM_ERRATUM_23154 !! 2306 endchoice
1154 bool "Cavium errata 23154 and 38545: <<
1155 default y <<
1156 help <<
1157 The ThunderX GICv3 implementation r <<
1158 reading the IAR status to ensure da <<
1159 (access to icc_iar1_el1 is not sync <<
1160 2307
1161 It also suffers from erratum 38545 !! 2308 config FORCE_MAX_ZONEORDER
1162 OcteonTX and OcteonTX2), resulting !! 2309 int "Maximum zone order"
1163 spuriously presented to the CPU int !! 2310 range 14 64 if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_64KB
>> 2311 default "14" if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_64KB
>> 2312 range 13 64 if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_32KB
>> 2313 default "13" if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_32KB
>> 2314 range 12 64 if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_16KB
>> 2315 default "12" if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_16KB
>> 2316 range 0 64
>> 2317 default "11"
>> 2318 help
>> 2319 The kernel memory allocator divides physically contiguous memory
>> 2320 blocks into "zones", where each zone is a power of two number of
>> 2321 pages. This option selects the largest power of two that the kernel
>> 2322 keeps in the memory allocator. If you need to allocate very large
>> 2323 blocks of physically contiguous memory, then you may need to
>> 2324 increase this value.
1164 2325
1165 If unsure, say Y. !! 2326 This config option is actually maximum order plus one. For example,
>> 2327 a value of 11 means that the largest free memory block is 2^10 pages.
1166 2328
1167 config CAVIUM_ERRATUM_27456 !! 2329 The page size is not necessarily 4KB. Keep this in mind
1168 bool "Cavium erratum 27456: Broadcast !! 2330 when choosing a value for this option.
1169 default y <<
1170 help <<
1171 On ThunderX T88 pass 1.x through 2. <<
1172 instructions may cause the icache t <<
1173 contains data for a non-current ASI <<
1174 invalidate the icache when changing <<
1175 2331
1176 If unsure, say Y. !! 2332 config BOARD_SCACHE
>> 2333 bool
1177 2334
1178 config CAVIUM_ERRATUM_30115 !! 2335 config IP22_CPU_SCACHE
1179 bool "Cavium erratum 30115: Guest may !! 2336 bool
1180 default y !! 2337 select BOARD_SCACHE
1181 help <<
1182 On ThunderX T88 pass 1.x through 2. <<
1183 1.2, and T83 Pass 1.0, KVM guest ex <<
1184 interrupts in host. Trapping both G <<
1185 accesses sidesteps the issue. <<
1186 2338
1187 If unsure, say Y. !! 2339 #
>> 2340 # Support for a MIPS32 / MIPS64 style S-caches
>> 2341 #
>> 2342 config MIPS_CPU_SCACHE
>> 2343 bool
>> 2344 select BOARD_SCACHE
1188 2345
1189 config CAVIUM_TX2_ERRATUM_219 !! 2346 config R5000_CPU_SCACHE
1190 bool "Cavium ThunderX2 erratum 219: P !! 2347 bool
1191 default y !! 2348 select BOARD_SCACHE
1192 help <<
1193 On Cavium ThunderX2, a load, store <<
1194 TTBR update and the corresponding c <<
1195 cause a spurious Data Abort to be d <<
1196 the CPU core. <<
1197 <<
1198 Work around the issue by avoiding t <<
1199 trapping KVM guest TTBRx_EL1 writes <<
1200 trap handler performs the correspon <<
1201 instruction and ensures context syn <<
1202 exception return. <<
1203 2349
1204 If unsure, say Y. !! 2350 config RM7000_CPU_SCACHE
>> 2351 bool
>> 2352 select BOARD_SCACHE
1205 2353
1206 config FUJITSU_ERRATUM_010001 !! 2354 config SIBYTE_DMA_PAGEOPS
1207 bool "Fujitsu-A64FX erratum E#010001: !! 2355 bool "Use DMA to clear/copy pages"
1208 default y !! 2356 depends on CPU_SB1
1209 help 2357 help
1210 This option adds a workaround for F !! 2358 Instead of using the CPU to zero and copy pages, use a Data Mover
1211 On some variants of the Fujitsu-A64 !! 2359 channel. These DMA channels are otherwise unused by the standard
1212 accesses may cause undefined fault !! 2360 SiByte Linux port. Seems to give a small performance benefit.
1213 This fault occurs under a specific <<
1214 load/store instruction performs an <<
1215 case-1 TTBR0_EL1 with TCR_EL1.NFD0 <<
1216 case-2 TTBR0_EL2 with TCR_EL2.NFD0 <<
1217 case-3 TTBR1_EL1 with TCR_EL1.NFD1 <<
1218 case-4 TTBR1_EL2 with TCR_EL2.NFD1 <<
1219 2361
1220 The workaround is to ensure these b !! 2362 config CPU_HAS_PREFETCH
1221 The workaround only affects the Fuj !! 2363 bool
1222 2364
1223 If unsure, say Y. !! 2365 config CPU_GENERIC_DUMP_TLB
>> 2366 bool
>> 2367 default y if !(CPU_R3000 || CPU_TX39XX)
1224 2368
1225 config HISILICON_ERRATUM_161600802 !! 2369 config MIPS_FP_SUPPORT
1226 bool "Hip07 161600802: Erroneous redi !! 2370 bool "Floating Point support" if EXPERT
1227 default y 2371 default y
1228 help 2372 help
1229 The HiSilicon Hip07 SoC uses the wr !! 2373 Select y to include support for floating point in the kernel
1230 when issued ITS commands such as VM !! 2374 including initialization of FPU hardware, FP context save & restore
1231 a 128kB offset to be applied to the !! 2375 and emulation of an FPU where necessary. Without this support any
>> 2376 userland program attempting to use floating point instructions will
>> 2377 receive a SIGILL.
1232 2378
1233 If unsure, say Y. !! 2379 If you know that your userland will not attempt to use floating point
>> 2380 instructions then you can say n here to shrink the kernel a little.
1234 2381
1235 config QCOM_FALKOR_ERRATUM_1003 !! 2382 If unsure, say y.
1236 bool "Falkor E1003: Incorrect transla <<
1237 default y <<
1238 help <<
1239 On Falkor v1, an incorrect ASID may <<
1240 and BADDR are changed together in T <<
1241 in TTBR1_EL1, this situation only o <<
1242 then only for entries in the walk c <<
1243 is unchanged. Work around the errat <<
1244 entries for the trampoline before e <<
1245 2383
1246 config QCOM_FALKOR_ERRATUM_1009 !! 2384 config CPU_R2300_FPU
1247 bool "Falkor E1009: Prematurely compl !! 2385 bool
1248 default y !! 2386 depends on MIPS_FP_SUPPORT
1249 select ARM64_WORKAROUND_REPEAT_TLBI !! 2387 default y if CPU_R3000 || CPU_TX39XX
1250 help <<
1251 On Falkor v1, the CPU may premature <<
1252 TLBI xxIS invalidate maintenance op <<
1253 one more time to fix the issue. <<
1254 2388
1255 If unsure, say Y. !! 2389 config CPU_R3K_TLB
>> 2390 bool
1256 2391
1257 config QCOM_QDF2400_ERRATUM_0065 !! 2392 config CPU_R4K_FPU
1258 bool "QDF2400 E0065: Incorrect GITS_T !! 2393 bool
1259 default y !! 2394 depends on MIPS_FP_SUPPORT
1260 help !! 2395 default y if !CPU_R2300_FPU
1261 On Qualcomm Datacenter Technologies <<
1262 ITE size incorrectly. The GITS_TYPE <<
1263 been indicated as 16Bytes (0xf), no <<
1264 2396
1265 If unsure, say Y. !! 2397 config CPU_R4K_CACHE_TLB
>> 2398 bool
>> 2399 default y if !(CPU_R3K_TLB || CPU_SB1 || CPU_CAVIUM_OCTEON)
1266 2400
1267 config QCOM_FALKOR_ERRATUM_E1041 !! 2401 config MIPS_MT_SMP
1268 bool "Falkor E1041: Speculative instr !! 2402 bool "MIPS MT SMP support (1 TC on each available VPE)"
1269 default y 2403 default y
1270 help !! 2404 depends on SYS_SUPPORTS_MULTITHREADING && !CPU_MIPSR6 && !CPU_MICROMIPS
1271 Falkor CPU may speculatively fetch !! 2405 select CPU_MIPSR2_IRQ_VI
1272 memory location when MMU translatio !! 2406 select CPU_MIPSR2_IRQ_EI
1273 to SCTLR_ELn[M]=0. Prefix an ISB in !! 2407 select SYNC_R4K
>> 2408 select MIPS_MT
>> 2409 select SMP
>> 2410 select SMP_UP
>> 2411 select SYS_SUPPORTS_SMP
>> 2412 select SYS_SUPPORTS_SCHED_SMT
>> 2413 select MIPS_PERF_SHARED_TC_COUNTERS
>> 2414 help
>> 2415 This is a kernel model which is known as SMVP. This is supported
>> 2416 on cores with the MT ASE and uses the available VPEs to implement
>> 2417 virtual processors which supports SMP. This is equivalent to the
>> 2418 Intel Hyperthreading feature. For further information go to
>> 2419 <http://www.imgtec.com/mips/mips-multithreading.asp>.
1274 2420
1275 If unsure, say Y. !! 2421 config MIPS_MT
>> 2422 bool
1276 2423
1277 config NVIDIA_CARMEL_CNP_ERRATUM !! 2424 config SCHED_SMT
1278 bool "NVIDIA Carmel CNP: CNP on Carme !! 2425 bool "SMT (multithreading) scheduler support"
1279 default y !! 2426 depends on SYS_SUPPORTS_SCHED_SMT
>> 2427 default n
1280 help 2428 help
1281 If CNP is enabled on Carmel cores, !! 2429 SMT scheduler support improves the CPU scheduler's decision making
1282 invalidate shared TLB entries insta !! 2430 when dealing with MIPS MT enabled cores at a cost of slightly
1283 on standard ARM cores. !! 2431 increased overhead in some places. If unsure say N here.
1284 <<
1285 If unsure, say Y. <<
1286 2432
1287 config ROCKCHIP_ERRATUM_3588001 !! 2433 config SYS_SUPPORTS_SCHED_SMT
1288 bool "Rockchip 3588001: GIC600 can no !! 2434 bool
1289 default y <<
1290 help <<
1291 The Rockchip RK3588 GIC600 SoC inte <<
1292 This means, that its sharability fe <<
1293 is supported by the IP itself. <<
1294 2435
1295 If unsure, say Y. !! 2436 config SYS_SUPPORTS_MULTITHREADING
>> 2437 bool
1296 2438
1297 config SOCIONEXT_SYNQUACER_PREITS !! 2439 config MIPS_MT_FPAFF
1298 bool "Socionext Synquacer: Workaround !! 2440 bool "Dynamic FPU affinity for FP-intensive threads"
1299 default y 2441 default y
1300 help !! 2442 depends on MIPS_MT_SMP
1301 Socionext Synquacer SoCs implement <<
1302 MSI doorbell writes with non-zero v <<
1303 2443
1304 If unsure, say Y. !! 2444 config MIPSR2_TO_R6_EMULATOR
1305 !! 2445 bool "MIPS R2-to-R6 emulator"
1306 endmenu # "ARM errata workarounds via the alt !! 2446 depends on CPU_MIPSR6
1307 !! 2447 depends on MIPS_FP_SUPPORT
1308 choice !! 2448 default y
1309 prompt "Page size" <<
1310 default ARM64_4K_PAGES <<
1311 help 2449 help
1312 Page size (translation granule) con !! 2450 Choose this option if you want to run non-R6 MIPS userland code.
>> 2451 Even if you say 'Y' here, the emulator will still be disabled by
>> 2452 default. You can enable it using the 'mipsr2emu' kernel option.
>> 2453 The only reason this is a build-time option is to save ~14K from the
>> 2454 final kernel image.
1313 2455
1314 config ARM64_4K_PAGES !! 2456 config SYS_SUPPORTS_VPE_LOADER
1315 bool "4KB" !! 2457 bool
1316 select HAVE_PAGE_SIZE_4KB !! 2458 depends on SYS_SUPPORTS_MULTITHREADING
1317 help 2459 help
1318 This feature enables 4KB pages supp !! 2460 Indicates that the platform supports the VPE loader, and provides
>> 2461 physical_memsize.
1319 2462
1320 config ARM64_16K_PAGES !! 2463 config MIPS_VPE_LOADER
1321 bool "16KB" !! 2464 bool "VPE loader support."
1322 select HAVE_PAGE_SIZE_16KB !! 2465 depends on SYS_SUPPORTS_VPE_LOADER && MODULES
>> 2466 select CPU_MIPSR2_IRQ_VI
>> 2467 select CPU_MIPSR2_IRQ_EI
>> 2468 select MIPS_MT
1323 help 2469 help
1324 The system will use 16KB pages supp !! 2470 Includes a loader for loading an elf relocatable object
1325 requires applications compiled with !! 2471 onto another VPE and running it.
1326 aligned segments. <<
1327 2472
1328 config ARM64_64K_PAGES !! 2473 config MIPS_VPE_LOADER_CMP
1329 bool "64KB" !! 2474 bool
1330 select HAVE_PAGE_SIZE_64KB !! 2475 default "y"
1331 help !! 2476 depends on MIPS_VPE_LOADER && MIPS_CMP
1332 This feature enables 64KB pages sup <<
1333 allowing only two levels of page ta <<
1334 look-up. AArch32 emulation requires <<
1335 with 64K aligned segments. <<
1336 2477
1337 endchoice !! 2478 config MIPS_VPE_LOADER_MT
>> 2479 bool
>> 2480 default "y"
>> 2481 depends on MIPS_VPE_LOADER && !MIPS_CMP
1338 2482
1339 choice !! 2483 config MIPS_VPE_LOADER_TOM
1340 prompt "Virtual address space size" !! 2484 bool "Load VPE program into memory hidden from linux"
1341 default ARM64_VA_BITS_52 !! 2485 depends on MIPS_VPE_LOADER
>> 2486 default y
1342 help 2487 help
1343 Allows choosing one of multiple pos !! 2488 The loader can use memory that is present but has been hidden from
1344 space sizes. The level of translati !! 2489 Linux using the kernel command line option "mem=xxMB". It's up to
1345 a combination of page size and virt !! 2490 you to ensure the amount you put in the option and the space your
1346 !! 2491 program requires is less or equal to the amount physically present.
1347 config ARM64_VA_BITS_36 <<
1348 bool "36-bit" if EXPERT <<
1349 depends on PAGE_SIZE_16KB <<
1350 <<
1351 config ARM64_VA_BITS_39 <<
1352 bool "39-bit" <<
1353 depends on PAGE_SIZE_4KB <<
1354 <<
1355 config ARM64_VA_BITS_42 <<
1356 bool "42-bit" <<
1357 depends on PAGE_SIZE_64KB <<
1358 <<
1359 config ARM64_VA_BITS_47 <<
1360 bool "47-bit" <<
1361 depends on PAGE_SIZE_16KB <<
1362 <<
1363 config ARM64_VA_BITS_48 <<
1364 bool "48-bit" <<
1365 <<
1366 config ARM64_VA_BITS_52 <<
1367 bool "52-bit" <<
1368 depends on ARM64_PAN || !ARM64_SW_TTB <<
1369 help <<
1370 Enable 52-bit virtual addressing fo <<
1371 requested via a hint to mmap(). The <<
1372 virtual addresses for its own mappi <<
1373 this feature is available, otherwis <<
1374 <<
1375 NOTE: Enabling 52-bit virtual addre <<
1376 ARMv8.3 Pointer Authentication will <<
1377 reduced from 7 bits to 3 bits, whic <<
1378 impact on its susceptibility to bru <<
1379 <<
1380 If unsure, select 48-bit virtual ad <<
1381 2492
1382 endchoice !! 2493 config MIPS_VPE_APSP_API
>> 2494 bool "Enable support for AP/SP API (RTLX)"
>> 2495 depends on MIPS_VPE_LOADER
1383 2496
1384 config ARM64_FORCE_52BIT !! 2497 config MIPS_VPE_APSP_API_CMP
1385 bool "Force 52-bit virtual addresses !! 2498 bool
1386 depends on ARM64_VA_BITS_52 && EXPERT !! 2499 default "y"
1387 help !! 2500 depends on MIPS_VPE_APSP_API && MIPS_CMP
1388 For systems with 52-bit userspace V <<
1389 to maintain compatibility with olde <<
1390 unless a hint is supplied to mmap. <<
1391 <<
1392 This configuration option disables <<
1393 forces all userspace addresses to b <<
1394 should only enable this configurati <<
1395 memory management code. If unsure s <<
1396 2501
1397 config ARM64_VA_BITS !! 2502 config MIPS_VPE_APSP_API_MT
1398 int !! 2503 bool
1399 default 36 if ARM64_VA_BITS_36 !! 2504 default "y"
1400 default 39 if ARM64_VA_BITS_39 !! 2505 depends on MIPS_VPE_APSP_API && !MIPS_CMP
1401 default 42 if ARM64_VA_BITS_42 <<
1402 default 47 if ARM64_VA_BITS_47 <<
1403 default 48 if ARM64_VA_BITS_48 <<
1404 default 52 if ARM64_VA_BITS_52 <<
1405 2506
1406 choice !! 2507 config MIPS_CMP
1407 prompt "Physical address space size" !! 2508 bool "MIPS CMP framework support (DEPRECATED)"
1408 default ARM64_PA_BITS_48 !! 2509 depends on SYS_SUPPORTS_MIPS_CMP && !CPU_MIPSR6
>> 2510 select SMP
>> 2511 select SYNC_R4K
>> 2512 select SYS_SUPPORTS_SMP
>> 2513 select WEAK_ORDERING
>> 2514 default n
1409 help 2515 help
1410 Choose the maximum physical address !! 2516 Select this if you are using a bootloader which implements the "CMP
1411 support. !! 2517 framework" protocol (ie. YAMON) and want your kernel to make use of
>> 2518 its ability to start secondary CPUs.
>> 2519
>> 2520 Unless you have a specific need, you should use CONFIG_MIPS_CPS
>> 2521 instead of this.
>> 2522
>> 2523 config MIPS_CPS
>> 2524 bool "MIPS Coherent Processing System support"
>> 2525 depends on SYS_SUPPORTS_MIPS_CPS
>> 2526 select MIPS_CM
>> 2527 select MIPS_CPS_PM if HOTPLUG_CPU
>> 2528 select SMP
>> 2529 select SYNC_R4K if (CEVT_R4K || CSRC_R4K)
>> 2530 select SYS_SUPPORTS_HOTPLUG_CPU
>> 2531 select SYS_SUPPORTS_SCHED_SMT if CPU_MIPSR6
>> 2532 select SYS_SUPPORTS_SMP
>> 2533 select WEAK_ORDERING
>> 2534 select GENERIC_IRQ_MIGRATION if HOTPLUG_CPU
>> 2535 help
>> 2536 Select this if you wish to run an SMP kernel across multiple cores
>> 2537 within a MIPS Coherent Processing System. When this option is
>> 2538 enabled the kernel will probe for other cores and boot them with
>> 2539 no external assistance. It is safe to enable this when hardware
>> 2540 support is unavailable.
1412 2541
1413 config ARM64_PA_BITS_48 !! 2542 config MIPS_CPS_PM
1414 bool "48-bit" !! 2543 depends on MIPS_CPS
1415 depends on ARM64_64K_PAGES || !ARM64_ !! 2544 bool
1416 <<
1417 config ARM64_PA_BITS_52 <<
1418 bool "52-bit" <<
1419 depends on ARM64_64K_PAGES || ARM64_V <<
1420 depends on ARM64_PAN || !ARM64_SW_TTB <<
1421 help <<
1422 Enable support for a 52-bit physica <<
1423 part of the ARMv8.2-LPA extension. <<
1424 <<
1425 With this enabled, the kernel will <<
1426 do not support ARMv8.2-LPA, but wit <<
1427 minor performance overhead). <<
1428 2545
1429 endchoice !! 2546 config MIPS_CM
>> 2547 bool
>> 2548 select MIPS_CPC
1430 2549
1431 config ARM64_PA_BITS !! 2550 config MIPS_CPC
1432 int !! 2551 bool
1433 default 48 if ARM64_PA_BITS_48 <<
1434 default 52 if ARM64_PA_BITS_52 <<
1435 2552
1436 config ARM64_LPA2 !! 2553 config SB1_PASS_2_WORKAROUNDS
1437 def_bool y !! 2554 bool
1438 depends on ARM64_PA_BITS_52 && !ARM64 !! 2555 depends on CPU_SB1 && (CPU_SB1_PASS_2_2 || CPU_SB1_PASS_2)
>> 2556 default y
>> 2557
>> 2558 config SB1_PASS_2_1_WORKAROUNDS
>> 2559 bool
>> 2560 depends on CPU_SB1 && CPU_SB1_PASS_2
>> 2561 default y
1439 2562
1440 choice 2563 choice
1441 prompt "Endianness" !! 2564 prompt "SmartMIPS or microMIPS ASE support"
1442 default CPU_LITTLE_ENDIAN <<
1443 help <<
1444 Select the endianness of data acces <<
1445 applications will need to be compil <<
1446 that is selected here. <<
1447 2565
1448 config CPU_BIG_ENDIAN !! 2566 config CPU_NEEDS_NO_SMARTMIPS_OR_MICROMIPS
1449 bool "Build big-endian kernel" !! 2567 bool "None"
1450 # https://github.com/llvm/llvm-projec <<
1451 depends on AS_IS_GNU || AS_VERSION >= <<
1452 help 2568 help
1453 Say Y if you plan on running a kern !! 2569 Select this if you want neither microMIPS nor SmartMIPS support
1454 2570
1455 config CPU_LITTLE_ENDIAN !! 2571 config CPU_HAS_SMARTMIPS
1456 bool "Build little-endian kernel" !! 2572 depends on SYS_SUPPORTS_SMARTMIPS
>> 2573 bool "SmartMIPS"
>> 2574 help
>> 2575 SmartMIPS is a extension of the MIPS32 architecture aimed at
>> 2576 increased security at both hardware and software level for
>> 2577 smartcards. Enabling this option will allow proper use of the
>> 2578 SmartMIPS instructions by Linux applications. However a kernel with
>> 2579 this option will not work on a MIPS core without SmartMIPS core. If
>> 2580 you don't know you probably don't have SmartMIPS and should say N
>> 2581 here.
>> 2582
>> 2583 config CPU_MICROMIPS
>> 2584 depends on 32BIT && SYS_SUPPORTS_MICROMIPS && !CPU_MIPSR6
>> 2585 bool "microMIPS"
1457 help 2586 help
1458 Say Y if you plan on running a kern !! 2587 When this option is enabled the kernel will be built using the
1459 This is usually the case for distri !! 2588 microMIPS ISA
1460 2589
1461 endchoice 2590 endchoice
1462 2591
1463 config SCHED_MC !! 2592 config CPU_HAS_MSA
1464 bool "Multi-core scheduler support" !! 2593 bool "Support for the MIPS SIMD Architecture"
1465 help !! 2594 depends on CPU_SUPPORTS_MSA
1466 Multi-core scheduler support improv !! 2595 depends on MIPS_FP_SUPPORT
1467 making when dealing with multi-core !! 2596 depends on 64BIT || MIPS_O32_FP64_SUPPORT
1468 increased overhead in some places. !! 2597 help
1469 !! 2598 MIPS SIMD Architecture (MSA) introduces 128 bit wide vector registers
1470 config SCHED_CLUSTER !! 2599 and a set of SIMD instructions to operate on them. When this option
1471 bool "Cluster scheduler support" !! 2600 is enabled the kernel will support allocating & switching MSA
1472 help !! 2601 vector register contexts. If you know that your kernel will only be
1473 Cluster scheduler support improves !! 2602 running on CPUs which do not support MSA or that your userland will
1474 making when dealing with machines t !! 2603 not be making use of it then you may wish to say N here to reduce
1475 Cluster usually means a couple of C !! 2604 the size & complexity of your kernel.
1476 by sharing mid-level caches, last-l <<
1477 busses. <<
1478 <<
1479 config SCHED_SMT <<
1480 bool "SMT scheduler support" <<
1481 help <<
1482 Improves the CPU scheduler's decisi <<
1483 MultiThreading at a cost of slightl <<
1484 places. If unsure say N here. <<
1485 2605
1486 config NR_CPUS !! 2606 If unsure, say Y.
1487 int "Maximum number of CPUs (2-4096)" <<
1488 range 2 4096 <<
1489 default "512" <<
1490 <<
1491 config HOTPLUG_CPU <<
1492 bool "Support for hot-pluggable CPUs" <<
1493 select GENERIC_IRQ_MIGRATION <<
1494 help <<
1495 Say Y here to experiment with turni <<
1496 can be controlled through /sys/devi <<
1497 <<
1498 # Common NUMA Features <<
1499 config NUMA <<
1500 bool "NUMA Memory Allocation and Sche <<
1501 select GENERIC_ARCH_NUMA <<
1502 select OF_NUMA <<
1503 select HAVE_SETUP_PER_CPU_AREA <<
1504 select NEED_PER_CPU_EMBED_FIRST_CHUNK <<
1505 select NEED_PER_CPU_PAGE_FIRST_CHUNK <<
1506 select USE_PERCPU_NUMA_NODE_ID <<
1507 help <<
1508 Enable NUMA (Non-Uniform Memory Acc <<
1509 <<
1510 The kernel will try to allocate mem <<
1511 local memory of the CPU and add som <<
1512 NUMA awareness to the kernel. <<
1513 <<
1514 config NODES_SHIFT <<
1515 int "Maximum NUMA Nodes (as a power o <<
1516 range 1 10 <<
1517 default "4" <<
1518 depends on NUMA <<
1519 help <<
1520 Specify the maximum number of NUMA <<
1521 system. Increases memory reserved <<
1522 2607
1523 source "kernel/Kconfig.hz" !! 2608 config CPU_HAS_WB
>> 2609 bool
1524 2610
1525 config ARCH_SPARSEMEM_ENABLE !! 2611 config XKS01
1526 def_bool y !! 2612 bool
1527 select SPARSEMEM_VMEMMAP_ENABLE <<
1528 select SPARSEMEM_VMEMMAP <<
1529 2613
1530 config HW_PERF_EVENTS !! 2614 config CPU_HAS_DIEI
1531 def_bool y !! 2615 depends on !CPU_DIEI_BROKEN
1532 depends on ARM_PMU !! 2616 bool
1533 2617
1534 # Supported by clang >= 7.0 or GCC >= 12.0.0 !! 2618 config CPU_DIEI_BROKEN
1535 config CC_HAVE_SHADOW_CALL_STACK !! 2619 bool
1536 def_bool $(cc-option, -fsanitize=shad <<
1537 2620
1538 config PARAVIRT !! 2621 config CPU_HAS_RIXI
1539 bool "Enable paravirtualization code" !! 2622 bool
1540 help <<
1541 This changes the kernel so it can m <<
1542 under a hypervisor, potentially imp <<
1543 over full virtualization. <<
1544 2623
1545 config PARAVIRT_TIME_ACCOUNTING !! 2624 config CPU_NO_LOAD_STORE_LR
1546 bool "Paravirtual steal time accounti !! 2625 bool
1547 select PARAVIRT <<
1548 help 2626 help
1549 Select this option to enable fine g !! 2627 CPU lacks support for unaligned load and store instructions:
1550 accounting. Time spent executing ot !! 2628 LWL, LWR, SWL, SWR (Load/store word left/right).
1551 the current vCPU is discounted from !! 2629 LDL, LDR, SDL, SDR (Load/store doubleword left/right, for 64bit
1552 that, there can be a small performa !! 2630 systems).
1553 2631
1554 If in doubt, say N here. !! 2632 #
>> 2633 # Vectored interrupt mode is an R2 feature
>> 2634 #
>> 2635 config CPU_MIPSR2_IRQ_VI
>> 2636 bool
1555 2637
1556 config ARCH_SUPPORTS_KEXEC !! 2638 #
1557 def_bool PM_SLEEP_SMP !! 2639 # Extended interrupt mode is an R2 feature
>> 2640 #
>> 2641 config CPU_MIPSR2_IRQ_EI
>> 2642 bool
1558 2643
1559 config ARCH_SUPPORTS_KEXEC_FILE !! 2644 config CPU_HAS_SYNC
1560 def_bool y !! 2645 bool
>> 2646 depends on !CPU_R3000
>> 2647 default y
1561 2648
1562 config ARCH_SELECTS_KEXEC_FILE !! 2649 #
1563 def_bool y !! 2650 # CPU non-features
1564 depends on KEXEC_FILE !! 2651 #
1565 select HAVE_IMA_KEXEC if IMA !! 2652 config CPU_DADDI_WORKAROUNDS
>> 2653 bool
1566 2654
1567 config ARCH_SUPPORTS_KEXEC_SIG !! 2655 config CPU_R4000_WORKAROUNDS
1568 def_bool y !! 2656 bool
>> 2657 select CPU_R4400_WORKAROUNDS
1569 2658
1570 config ARCH_SUPPORTS_KEXEC_IMAGE_VERIFY_SIG !! 2659 config CPU_R4400_WORKAROUNDS
1571 def_bool y !! 2660 bool
1572 2661
1573 config ARCH_DEFAULT_KEXEC_IMAGE_VERIFY_SIG !! 2662 config CPU_R4X00_BUGS64
1574 def_bool y !! 2663 bool
>> 2664 default y if SYS_HAS_CPU_R4X00 && 64BIT && (TARGET_ISA_REV < 1)
1575 2665
1576 config ARCH_SUPPORTS_CRASH_DUMP !! 2666 config MIPS_ASID_SHIFT
1577 def_bool y !! 2667 int
>> 2668 default 6 if CPU_R3000 || CPU_TX39XX
>> 2669 default 0
1578 2670
1579 config ARCH_HAS_GENERIC_CRASHKERNEL_RESERVATI !! 2671 config MIPS_ASID_BITS
1580 def_bool CRASH_RESERVE !! 2672 int
>> 2673 default 0 if MIPS_ASID_BITS_VARIABLE
>> 2674 default 6 if CPU_R3000 || CPU_TX39XX
>> 2675 default 8
1581 2676
1582 config TRANS_TABLE !! 2677 config MIPS_ASID_BITS_VARIABLE
1583 def_bool y !! 2678 bool
1584 depends on HIBERNATION || KEXEC_CORE <<
1585 2679
1586 config XEN_DOM0 !! 2680 config MIPS_CRC_SUPPORT
1587 def_bool y !! 2681 bool
1588 depends on XEN <<
1589 2682
1590 config XEN !! 2683 # R4600 erratum. Due to the lack of errata information the exact
1591 bool "Xen guest support on ARM64" !! 2684 # technical details aren't known. I've experimentally found that disabling
1592 depends on ARM64 && OF !! 2685 # interrupts during indexed I-cache flushes seems to be sufficient to deal
1593 select SWIOTLB_XEN !! 2686 # with the issue.
1594 select PARAVIRT !! 2687 config WAR_R4600_V1_INDEX_ICACHEOP
1595 help !! 2688 bool
1596 Say Y if you want to run Linux in a <<
1597 2689
1598 # include/linux/mmzone.h requires the followi !! 2690 # Pleasures of the R4600 V1.x. Cite from the IDT R4600 V1.7 errata:
1599 # 2691 #
1600 # MAX_PAGE_ORDER + PAGE_SHIFT <= SECTION_SI !! 2692 # 18. The CACHE instructions Hit_Writeback_Invalidate_D, Hit_Writeback_D,
>> 2693 # Hit_Invalidate_D and Create_Dirty_Excl_D should only be
>> 2694 # executed if there is no other dcache activity. If the dcache is
>> 2695 # accessed for another instruction immediately preceding when these
>> 2696 # cache instructions are executing, it is possible that the dcache
>> 2697 # tag match outputs used by these cache instructions will be
>> 2698 # incorrect. These cache instructions should be preceded by at least
>> 2699 # four instructions that are not any kind of load or store
>> 2700 # instruction.
1601 # 2701 #
1602 # so the maximum value of MAX_PAGE_ORDER is S !! 2702 # This is not allowed: lw
>> 2703 # nop
>> 2704 # nop
>> 2705 # nop
>> 2706 # cache Hit_Writeback_Invalidate_D
1603 # 2707 #
1604 # | SECTION_SIZE_BITS | PAGE_SHIFT | m !! 2708 # This is allowed: lw
1605 # ----+-------------------+--------------+--- !! 2709 # nop
1606 # 4K | 27 | 12 | !! 2710 # nop
1607 # 16K | 27 | 14 | !! 2711 # nop
1608 # 64K | 29 | 16 | !! 2712 # nop
1609 config ARCH_FORCE_MAX_ORDER !! 2713 # cache Hit_Writeback_Invalidate_D
1610 int !! 2714 config WAR_R4600_V1_HIT_CACHEOP
1611 default "13" if ARM64_64K_PAGES !! 2715 bool
1612 default "11" if ARM64_16K_PAGES <<
1613 default "10" <<
1614 help <<
1615 The kernel page allocator limits th <<
1616 contiguous allocations. The limit i <<
1617 defines the maximal power of two of <<
1618 allocated as a single contiguous bl <<
1619 overriding the default setting when <<
1620 large blocks of physically contiguo <<
1621 <<
1622 The maximal size of allocation cann <<
1623 section, so the value of MAX_PAGE_O <<
1624 <<
1625 MAX_PAGE_ORDER + PAGE_SHIFT <= SE <<
1626 <<
1627 Don't change if unsure. <<
1628 <<
1629 config UNMAP_KERNEL_AT_EL0 <<
1630 bool "Unmap kernel when running in us <<
1631 default y <<
1632 help <<
1633 Speculation attacks against some hi <<
1634 be used to bypass MMU permission ch <<
1635 userspace. This can be defended aga <<
1636 when running in userspace, mapping <<
1637 via a trampoline page in the vector <<
1638 <<
1639 If unsure, say Y. <<
1640 <<
1641 config MITIGATE_SPECTRE_BRANCH_HISTORY <<
1642 bool "Mitigate Spectre style attacks <<
1643 default y <<
1644 help <<
1645 Speculation attacks against some hi <<
1646 make use of branch history to influ <<
1647 When taking an exception from user- <<
1648 or a firmware call overwrites the b <<
1649 <<
1650 config RODATA_FULL_DEFAULT_ENABLED <<
1651 bool "Apply r/o permissions of VM are <<
1652 default y <<
1653 help <<
1654 Apply read-only attributes of VM ar <<
1655 the backing pages as well. This pre <<
1656 from being modified (inadvertently <<
1657 mapping of the same memory page. Th <<
1658 be turned off at runtime by passing <<
1659 with rodata=full if this option is <<
1660 <<
1661 This requires the linear region to <<
1662 which may adversely affect performa <<
1663 <<
1664 config ARM64_SW_TTBR0_PAN <<
1665 bool "Emulate Privileged Access Never <<
1666 depends on !KCSAN <<
1667 help <<
1668 Enabling this option prevents the k <<
1669 user-space memory directly by point <<
1670 zeroed area and reserved ASID. The <<
1671 restore the valid TTBR0_EL1 tempora <<
1672 <<
1673 config ARM64_TAGGED_ADDR_ABI <<
1674 bool "Enable the tagged user addresse <<
1675 default y <<
1676 help <<
1677 When this option is enabled, user a <<
1678 relaxed ABI via prctl() allowing ta <<
1679 to system calls as pointer argument <<
1680 Documentation/arch/arm64/tagged-add <<
1681 2716
1682 menuconfig COMPAT !! 2717 # Writeback and invalidate the primary cache dcache before DMA.
1683 bool "Kernel support for 32-bit EL0" !! 2718 #
1684 depends on ARM64_4K_PAGES || EXPERT !! 2719 # R4600 v2.0 bug: "The CACHE instructions Hit_Writeback_Inv_D,
1685 select HAVE_UID16 !! 2720 # Hit_Writeback_D, Hit_Invalidate_D and Create_Dirty_Exclusive_D will only
1686 select OLD_SIGSUSPEND3 !! 2721 # operate correctly if the internal data cache refill buffer is empty. These
1687 select COMPAT_OLD_SIGACTION !! 2722 # CACHE instructions should be separated from any potential data cache miss
1688 help !! 2723 # by a load instruction to an uncached address to empty the response buffer."
1689 This option enables support for a 3 !! 2724 # (Revision 2.0 device errata from IDT available on https://www.idt.com/
1690 kernel at EL1. AArch32-specific com !! 2725 # in .pdf format.)
1691 the user helper functions, VFP supp !! 2726 config WAR_R4600_V2_HIT_CACHEOP
1692 handled appropriately by the kernel !! 2727 bool
1693 2728
1694 If you use a page size other than 4 !! 2729 # From TX49/H2 manual: "If the instruction (i.e. CACHE) is issued for
1695 that you will only be able to execu !! 2730 # the line which this instruction itself exists, the following
1696 with page size aligned segments. !! 2731 # operation is not guaranteed."
>> 2732 #
>> 2733 # Workaround: do two phase flushing for Index_Invalidate_I
>> 2734 config WAR_TX49XX_ICACHE_INDEX_INV
>> 2735 bool
1697 2736
1698 If you want to execute 32-bit users !! 2737 # The RM7000 processors and the E9000 cores have a bug (though PMC-Sierra
>> 2738 # opposes it being called that) where invalid instructions in the same
>> 2739 # I-cache line worth of instructions being fetched may case spurious
>> 2740 # exceptions.
>> 2741 config WAR_ICACHE_REFILLS
>> 2742 bool
1699 2743
1700 if COMPAT !! 2744 # On the R10000 up to version 2.6 (not sure about 2.7) there is a bug that
>> 2745 # may cause ll / sc and lld / scd sequences to execute non-atomically.
>> 2746 config WAR_R10000_LLSC
>> 2747 bool
1701 2748
1702 config KUSER_HELPERS !! 2749 # 34K core erratum: "Problems Executing the TLBR Instruction"
1703 bool "Enable kuser helpers page for 3 !! 2750 config WAR_MIPS34K_MISSED_ITLB
1704 default y !! 2751 bool
1705 help <<
1706 Warning: disabling this option may <<
1707 2752
1708 Provide kuser helpers to compat tas !! 2753 #
1709 helper code to userspace in read on !! 2754 # - Highmem only makes sense for the 32-bit kernel.
1710 to allow userspace to be independen !! 2755 # - The current highmem code will only work properly on physically indexed
1711 the system. This permits binaries t !! 2756 # caches such as R3000, SB1, R7000 or those that look like they're virtually
1712 to ARMv8 without modification. !! 2757 # indexed such as R4000/R4400 SC and MC versions or R10000. So for the
>> 2758 # moment we protect the user and offer the highmem option only on machines
>> 2759 # where it's known to be safe. This will not offer highmem on a few systems
>> 2760 # such as MIPS32 and MIPS64 CPUs which may have virtual and physically
>> 2761 # indexed CPUs but we're playing safe.
>> 2762 # - We use SYS_SUPPORTS_HIGHMEM to offer highmem only for systems where we
>> 2763 # know they might have memory configurations that could make use of highmem
>> 2764 # support.
>> 2765 #
>> 2766 config HIGHMEM
>> 2767 bool "High Memory Support"
>> 2768 depends on 32BIT && CPU_SUPPORTS_HIGHMEM && SYS_SUPPORTS_HIGHMEM && !CPU_MIPS32_3_5_EVA
>> 2769 select KMAP_LOCAL
1713 2770
1714 See Documentation/arch/arm/kernel_u !! 2771 config CPU_SUPPORTS_HIGHMEM
>> 2772 bool
1715 2773
1716 However, the fixed address nature o !! 2774 config SYS_SUPPORTS_HIGHMEM
1717 by ROP (return orientated programmi !! 2775 bool
1718 exploits. <<
1719 2776
1720 If all of the binaries and librarie !! 2777 config SYS_SUPPORTS_SMARTMIPS
1721 are built specifically for your pla !! 2778 bool
1722 these helpers, then you can turn th <<
1723 such exploits. However, in that cas <<
1724 relying on those helpers is run, it <<
1725 2779
1726 Say N here only if you are absolute !! 2780 config SYS_SUPPORTS_MICROMIPS
1727 need these helpers; otherwise, the !! 2781 bool
1728 2782
1729 config COMPAT_VDSO !! 2783 config SYS_SUPPORTS_MIPS16
1730 bool "Enable vDSO for 32-bit applicat !! 2784 bool
1731 depends on !CPU_BIG_ENDIAN <<
1732 depends on (CC_IS_CLANG && LD_IS_LLD) <<
1733 select GENERIC_COMPAT_VDSO <<
1734 default y <<
1735 help 2785 help
1736 Place in the process address space !! 2786 This option must be set if a kernel might be executed on a MIPS16-
1737 ELF shared object providing fast im !! 2787 enabled CPU even if MIPS16 is not actually being used. In other
1738 and clock_gettime. !! 2788 words, it makes the kernel MIPS16-tolerant.
1739 2789
1740 You must have a 32-bit build of gli !! 2790 config CPU_SUPPORTS_MSA
1741 to seamlessly take advantage of thi !! 2791 bool
1742 2792
1743 config THUMB2_COMPAT_VDSO !! 2793 config ARCH_FLATMEM_ENABLE
1744 bool "Compile the 32-bit vDSO for Thu !! 2794 def_bool y
1745 depends on COMPAT_VDSO !! 2795 depends on !NUMA && !CPU_LOONGSON2EF
1746 default y <<
1747 help <<
1748 Compile the compat vDSO with '-mthu <<
1749 otherwise with '-marm'. <<
1750 2796
1751 config COMPAT_ALIGNMENT_FIXUPS !! 2797 config ARCH_SPARSEMEM_ENABLE
1752 bool "Fix up misaligned multi-word lo !! 2798 bool
>> 2799 select SPARSEMEM_STATIC if !SGI_IP27
1753 2800
1754 menuconfig ARMV8_DEPRECATED !! 2801 config NUMA
1755 bool "Emulate deprecated/obsolete ARM !! 2802 bool "NUMA Support"
1756 depends on SYSCTL !! 2803 depends on SYS_SUPPORTS_NUMA
1757 help !! 2804 select SMP
1758 Legacy software support may require !! 2805 help
1759 that have been deprecated or obsole !! 2806 Say Y to compile the kernel to support NUMA (Non-Uniform Memory
>> 2807 Access). This option improves performance on systems with more
>> 2808 than two nodes; on two node systems it is generally better to
>> 2809 leave it disabled; on single node systems leave this option
>> 2810 disabled.
1760 2811
1761 Enable this config to enable select !! 2812 config SYS_SUPPORTS_NUMA
1762 features. !! 2813 bool
1763 2814
1764 If unsure, say Y !! 2815 config HAVE_SETUP_PER_CPU_AREA
>> 2816 def_bool y
>> 2817 depends on NUMA
1765 2818
1766 if ARMV8_DEPRECATED !! 2819 config NEED_PER_CPU_EMBED_FIRST_CHUNK
>> 2820 def_bool y
>> 2821 depends on NUMA
1767 2822
1768 config SWP_EMULATION !! 2823 config RELOCATABLE
1769 bool "Emulate SWP/SWPB instructions" !! 2824 bool "Relocatable kernel"
1770 help !! 2825 depends on SYS_SUPPORTS_RELOCATABLE
1771 ARMv8 obsoletes the use of A32 SWP/ !! 2826 depends on CPU_MIPS32_R2 || CPU_MIPS64_R2 || \
1772 they are always undefined. Say Y he !! 2827 CPU_MIPS32_R5 || CPU_MIPS64_R5 || \
1773 emulation of these instructions for !! 2828 CPU_MIPS32_R6 || CPU_MIPS64_R6 || \
1774 This feature can be controlled at r !! 2829 CPU_P5600 || CAVIUM_OCTEON_SOC || \
1775 sysctl which is disabled by default !! 2830 CPU_LOONGSON64
>> 2831 help
>> 2832 This builds a kernel image that retains relocation information
>> 2833 so it can be loaded someplace besides the default 1MB.
>> 2834 The relocations make the kernel binary about 15% larger,
>> 2835 but are discarded at runtime
>> 2836
>> 2837 config RELOCATION_TABLE_SIZE
>> 2838 hex "Relocation table size"
>> 2839 depends on RELOCATABLE
>> 2840 range 0x0 0x01000000
>> 2841 default "0x00200000" if CPU_LOONGSON64
>> 2842 default "0x00100000"
>> 2843 help
>> 2844 A table of relocation data will be appended to the kernel binary
>> 2845 and parsed at boot to fix up the relocated kernel.
1776 2846
1777 In some older versions of glibc [<= !! 2847 This option allows the amount of space reserved for the table to be
1778 trylock() operations with the assum !! 2848 adjusted, although the default of 1Mb should be ok in most cases.
1779 be preempted. This invalid assumpti <<
1780 with SWP emulation enabled, leading <<
1781 application. <<
1782 2849
1783 NOTE: when accessing uncached share !! 2850 The build will fail and a valid size suggested if this is too small.
1784 on an external transaction monitori <<
1785 monitor to maintain update atomicit <<
1786 implement a global monitor, this op <<
1787 perform SWP operations to uncached <<
1788 2851
1789 If unsure, say Y !! 2852 If unsure, leave at the default value.
1790 2853
1791 config CP15_BARRIER_EMULATION !! 2854 config RANDOMIZE_BASE
1792 bool "Emulate CP15 Barrier instructio !! 2855 bool "Randomize the address of the kernel image"
>> 2856 depends on RELOCATABLE
1793 help 2857 help
1794 The CP15 barrier instructions - CP1 !! 2858 Randomizes the physical and virtual address at which the
1795 CP15DMB - are deprecated in ARMv8 ( !! 2859 kernel image is loaded, as a security feature that
1796 strongly recommended to use the ISB !! 2860 deters exploit attempts relying on knowledge of the location
1797 instructions instead. !! 2861 of kernel internals.
1798 2862
1799 Say Y here to enable software emula !! 2863 Entropy is generated using any coprocessor 0 registers available.
1800 instructions for AArch32 userspace <<
1801 enabled, CP15 barrier usage is trac <<
1802 identify software that needs updati <<
1803 controlled at runtime with the abi. <<
1804 2864
1805 If unsure, say Y !! 2865 The kernel will be offset by up to RANDOMIZE_BASE_MAX_OFFSET.
1806 2866
1807 config SETEND_EMULATION !! 2867 If unsure, say N.
1808 bool "Emulate SETEND instruction" <<
1809 help <<
1810 The SETEND instruction alters the d <<
1811 AArch32 EL0, and is deprecated in A <<
1812 <<
1813 Say Y here to enable software emula <<
1814 for AArch32 userspace code. This fe <<
1815 at runtime with the abi.setend sysc <<
1816 <<
1817 Note: All the cpus on the system mu <<
1818 for this feature to be enabled. If <<
1819 endian - is hotplugged in after thi <<
1820 be unexpected results in the applic <<
1821 2868
1822 If unsure, say Y !! 2869 config RANDOMIZE_BASE_MAX_OFFSET
1823 endif # ARMV8_DEPRECATED !! 2870 hex "Maximum kASLR offset" if EXPERT
>> 2871 depends on RANDOMIZE_BASE
>> 2872 range 0x0 0x40000000 if EVA || 64BIT
>> 2873 range 0x0 0x08000000
>> 2874 default "0x01000000"
>> 2875 help
>> 2876 When kASLR is active, this provides the maximum offset that will
>> 2877 be applied to the kernel image. It should be set according to the
>> 2878 amount of physical RAM available in the target system minus
>> 2879 PHYSICAL_START and must be a power of 2.
1824 2880
1825 endif # COMPAT !! 2881 This is limited by the size of KSEG0, 256Mb on 32-bit or 1Gb with
>> 2882 EVA or 64-bit. The default is 16Mb.
1826 2883
1827 menu "ARMv8.1 architectural features" !! 2884 config NODES_SHIFT
>> 2885 int
>> 2886 default "6"
>> 2887 depends on NEED_MULTIPLE_NODES
1828 2888
1829 config ARM64_HW_AFDBM !! 2889 config HW_PERF_EVENTS
1830 bool "Support for hardware updates of !! 2890 bool "Enable hardware performance counter support for perf events"
>> 2891 depends on PERF_EVENTS && (CPU_MIPS32 || CPU_MIPS64 || CPU_R10000 || CPU_SB1 || CPU_CAVIUM_OCTEON || CPU_XLP || CPU_LOONGSON64)
1831 default y 2892 default y
1832 help 2893 help
1833 The ARMv8.1 architecture extensions !! 2894 Enable hardware performance counter support for perf events. If
1834 hardware updates of the access and !! 2895 disabled, perf events will use software events only.
1835 table entries. When enabled in TCR_ <<
1836 capable processors, accesses to pag <<
1837 set this bit instead of raising an <<
1838 Similarly, writes to read-only page <<
1839 clear the read-only bit (AP[2]) ins <<
1840 permission fault. <<
1841 <<
1842 Kernels built with this configurati <<
1843 to work on pre-ARMv8.1 hardware and <<
1844 minimal. If unsure, say Y. <<
1845 2896
1846 config ARM64_PAN !! 2897 config DMI
1847 bool "Enable support for Privileged A !! 2898 bool "Enable DMI scanning"
>> 2899 depends on MACH_LOONGSON64
>> 2900 select DMI_SCAN_MACHINE_NON_EFI_FALLBACK
1848 default y 2901 default y
1849 help 2902 help
1850 Privileged Access Never (PAN; part !! 2903 Enabled scanning of DMI to identify machine quirks. Say Y
1851 prevents the kernel or hypervisor f !! 2904 here unless you have verified that your setup is not
1852 memory directly. !! 2905 affected by entries in the DMI blacklist. Required by PNP
1853 !! 2906 BIOS code.
1854 Choosing this option will cause any <<
1855 copy_to_user et al) memory access t <<
1856 <<
1857 The feature is detected at runtime, <<
1858 instruction if the cpu does not imp <<
1859 2907
1860 config AS_HAS_LSE_ATOMICS !! 2908 config SMP
1861 def_bool $(as-instr,.arch_extension l !! 2909 bool "Multi-Processing support"
1862 !! 2910 depends on SYS_SUPPORTS_SMP
1863 config ARM64_LSE_ATOMICS <<
1864 bool <<
1865 default ARM64_USE_LSE_ATOMICS <<
1866 depends on AS_HAS_LSE_ATOMICS <<
1867 <<
1868 config ARM64_USE_LSE_ATOMICS <<
1869 bool "Atomic instructions" <<
1870 default y <<
1871 help 2911 help
1872 As part of the Large System Extensi !! 2912 This enables support for systems with more than one CPU. If you have
1873 atomic instructions that are design !! 2913 a system with only one CPU, say N. If you have a system with more
1874 very large systems. !! 2914 than one CPU, say Y.
>> 2915
>> 2916 If you say N here, the kernel will run on uni- and multiprocessor
>> 2917 machines, but will use only one CPU of a multiprocessor machine. If
>> 2918 you say Y here, the kernel will run on many, but not all,
>> 2919 uniprocessor machines. On a uniprocessor machine, the kernel
>> 2920 will run faster if you say N here.
1875 2921
1876 Say Y here to make use of these ins !! 2922 People using multiprocessor machines who say Y here should also say
1877 atomic routines. This incurs a smal !! 2923 Y to "Enhanced Real Time Clock Support", below.
1878 not support these instructions and <<
1879 built with binutils >= 2.25 in orde <<
1880 to be used. <<
1881 2924
1882 endmenu # "ARMv8.1 architectural features" !! 2925 See also the SMP-HOWTO available at
>> 2926 <https://www.tldp.org/docs.html#howto>.
1883 2927
1884 menu "ARMv8.2 architectural features" !! 2928 If you don't know what to do here, say N.
1885 2929
1886 config AS_HAS_ARMV8_2 !! 2930 config HOTPLUG_CPU
1887 def_bool $(cc-option,-Wa$(comma)-marc !! 2931 bool "Support for hot-pluggable CPUs"
>> 2932 depends on SMP && SYS_SUPPORTS_HOTPLUG_CPU
>> 2933 help
>> 2934 Say Y here to allow turning CPUs off and on. CPUs can be
>> 2935 controlled through /sys/devices/system/cpu.
>> 2936 (Note: power management support will enable this option
>> 2937 automatically on SMP systems. )
>> 2938 Say N if you want to disable CPU hotplug.
1888 2939
1889 config AS_HAS_SHA3 !! 2940 config SMP_UP
1890 def_bool $(as-instr,.arch armv8.2-a+s !! 2941 bool
1891 2942
1892 config ARM64_PMEM !! 2943 config SYS_SUPPORTS_MIPS_CMP
1893 bool "Enable support for persistent m !! 2944 bool
1894 select ARCH_HAS_PMEM_API <<
1895 select ARCH_HAS_UACCESS_FLUSHCACHE <<
1896 help <<
1897 Say Y to enable support for the per <<
1898 ARMv8.2 DCPoP feature. <<
1899 2945
1900 The feature is detected at runtime, !! 2946 config SYS_SUPPORTS_MIPS_CPS
1901 operations if DC CVAP is not suppor !! 2947 bool
1902 DC CVAP itself if the system does n <<
1903 2948
1904 config ARM64_RAS_EXTN !! 2949 config SYS_SUPPORTS_SMP
1905 bool "Enable support for RAS CPU Exte !! 2950 bool
1906 default y <<
1907 help <<
1908 CPUs that support the Reliability, <<
1909 (RAS) Extensions, part of ARMv8.2 a <<
1910 errors, classify them and report th <<
1911 2951
1912 On CPUs with these extensions syste !! 2952 config NR_CPUS_DEFAULT_4
1913 barriers to determine if faults are !! 2953 bool
1914 classification from a new set of re <<
1915 2954
1916 Selecting this feature will allow t !! 2955 config NR_CPUS_DEFAULT_8
1917 and access the new registers if the !! 2956 bool
1918 Platform RAS features may additiona <<
1919 2957
1920 config ARM64_CNP !! 2958 config NR_CPUS_DEFAULT_16
1921 bool "Enable support for Common Not P !! 2959 bool
1922 default y <<
1923 depends on ARM64_PAN || !ARM64_SW_TTB <<
1924 help <<
1925 Common Not Private (CNP) allows tra <<
1926 be shared between different PEs in <<
1927 domain, so the hardware can use thi <<
1928 caching of such entries in the TLB. <<
1929 2960
1930 Selecting this option allows the CN !! 2961 config NR_CPUS_DEFAULT_32
1931 at runtime, and does not affect PEs !! 2962 bool
1932 this feature. <<
1933 2963
1934 endmenu # "ARMv8.2 architectural features" !! 2964 config NR_CPUS_DEFAULT_64
>> 2965 bool
1935 2966
1936 menu "ARMv8.3 architectural features" !! 2967 config NR_CPUS
>> 2968 int "Maximum number of CPUs (2-256)"
>> 2969 range 2 256
>> 2970 depends on SMP
>> 2971 default "4" if NR_CPUS_DEFAULT_4
>> 2972 default "8" if NR_CPUS_DEFAULT_8
>> 2973 default "16" if NR_CPUS_DEFAULT_16
>> 2974 default "32" if NR_CPUS_DEFAULT_32
>> 2975 default "64" if NR_CPUS_DEFAULT_64
>> 2976 help
>> 2977 This allows you to specify the maximum number of CPUs which this
>> 2978 kernel will support. The maximum supported value is 32 for 32-bit
>> 2979 kernel and 64 for 64-bit kernels; the minimum value which makes
>> 2980 sense is 1 for Qemu (useful only for kernel debugging purposes)
>> 2981 and 2 for all others.
>> 2982
>> 2983 This is purely to save memory - each supported CPU adds
>> 2984 approximately eight kilobytes to the kernel image. For best
>> 2985 performance should round up your number of processors to the next
>> 2986 power of two.
1937 2987
1938 config ARM64_PTR_AUTH !! 2988 config MIPS_PERF_SHARED_TC_COUNTERS
1939 bool "Enable support for pointer auth !! 2989 bool
1940 default y <<
1941 help <<
1942 Pointer authentication (part of the <<
1943 instructions for signing and authen <<
1944 keys, which can be used to mitigate <<
1945 and other attacks. <<
1946 2990
1947 This option enables these instructi !! 2991 config MIPS_NR_CPU_NR_MAP_1024
1948 Choosing this option will cause the !! 2992 bool
1949 for each process at exec() time, wi <<
1950 context-switched along with the pro <<
1951 2993
1952 The feature is detected at runtime. !! 2994 config MIPS_NR_CPU_NR_MAP
1953 hardware it will not be advertised !! 2995 int
1954 be enabled. !! 2996 depends on SMP
>> 2997 default 1024 if MIPS_NR_CPU_NR_MAP_1024
>> 2998 default NR_CPUS if !MIPS_NR_CPU_NR_MAP_1024
1955 2999
1956 If the feature is present on the bo !! 3000 #
1957 the late CPU will be parked. Also, !! 3001 # Timer Interrupt Frequency Configuration
1958 address auth and the late CPU has t !! 3002 #
1959 but with the feature disabled. On s <<
1960 not be selected. <<
1961 3003
1962 config ARM64_PTR_AUTH_KERNEL !! 3004 choice
1963 bool "Use pointer authentication for !! 3005 prompt "Timer frequency"
1964 default y !! 3006 default HZ_250
1965 depends on ARM64_PTR_AUTH <<
1966 depends on (CC_HAS_SIGN_RETURN_ADDRES <<
1967 # Modern compilers insert a .note.gnu <<
1968 # which is only understood by binutil <<
1969 depends on LD_IS_LLD || LD_VERSION >= <<
1970 depends on !CC_IS_CLANG || AS_HAS_CFI <<
1971 depends on (!FUNCTION_GRAPH_TRACER || <<
1972 help 3007 help
1973 If the compiler supports the -mbran !! 3008 Allows the configuration of the timer frequency.
1974 -msign-return-address flag (e.g. GC <<
1975 will cause the kernel itself to be <<
1976 protection. In this case, and if th <<
1977 support pointer authentication, the <<
1978 disabled with minimal loss of prote <<
1979 3009
1980 This feature works with FUNCTION_GR !! 3010 config HZ_24
1981 DYNAMIC_FTRACE_WITH_ARGS is enabled !! 3011 bool "24 HZ" if SYS_SUPPORTS_24HZ || SYS_SUPPORTS_ARBIT_HZ
1982 3012
1983 config CC_HAS_BRANCH_PROT_PAC_RET !! 3013 config HZ_48
1984 # GCC 9 or later, clang 8 or later !! 3014 bool "48 HZ" if SYS_SUPPORTS_48HZ || SYS_SUPPORTS_ARBIT_HZ
1985 def_bool $(cc-option,-mbranch-protect <<
1986 3015
1987 config CC_HAS_SIGN_RETURN_ADDRESS !! 3016 config HZ_100
1988 # GCC 7, 8 !! 3017 bool "100 HZ" if SYS_SUPPORTS_100HZ || SYS_SUPPORTS_ARBIT_HZ
1989 def_bool $(cc-option,-msign-return-ad <<
1990 3018
1991 config AS_HAS_ARMV8_3 !! 3019 config HZ_128
1992 def_bool $(cc-option,-Wa$(comma)-marc !! 3020 bool "128 HZ" if SYS_SUPPORTS_128HZ || SYS_SUPPORTS_ARBIT_HZ
1993 3021
1994 config AS_HAS_CFI_NEGATE_RA_STATE !! 3022 config HZ_250
1995 def_bool $(as-instr,.cfi_startproc\n. !! 3023 bool "250 HZ" if SYS_SUPPORTS_250HZ || SYS_SUPPORTS_ARBIT_HZ
1996 3024
1997 config AS_HAS_LDAPR !! 3025 config HZ_256
1998 def_bool $(as-instr,.arch_extension r !! 3026 bool "256 HZ" if SYS_SUPPORTS_256HZ || SYS_SUPPORTS_ARBIT_HZ
1999 3027
2000 endmenu # "ARMv8.3 architectural features" !! 3028 config HZ_1000
>> 3029 bool "1000 HZ" if SYS_SUPPORTS_1000HZ || SYS_SUPPORTS_ARBIT_HZ
2001 3030
2002 menu "ARMv8.4 architectural features" !! 3031 config HZ_1024
>> 3032 bool "1024 HZ" if SYS_SUPPORTS_1024HZ || SYS_SUPPORTS_ARBIT_HZ
2003 3033
2004 config ARM64_AMU_EXTN !! 3034 endchoice
2005 bool "Enable support for the Activity <<
2006 default y <<
2007 help <<
2008 The activity monitors extension is <<
2009 by the ARMv8.4 CPU architecture. Th <<
2010 of the activity monitors architectu <<
2011 3035
2012 To enable the use of this extension !! 3036 config SYS_SUPPORTS_24HZ
>> 3037 bool
2013 3038
2014 Note that for architectural reasons !! 3039 config SYS_SUPPORTS_48HZ
2015 support when running on CPUs that p !! 3040 bool
2016 extension. The required support is <<
2017 * Version 1.5 and later of the AR <<
2018 3041
2019 For kernels that have this configur !! 3042 config SYS_SUPPORTS_100HZ
2020 firmware, you may need to say N her !! 3043 bool
2021 Otherwise you may experience firmwa <<
2022 accessing the counter registers. Ev <<
2023 symptoms, the values returned by th <<
2024 correctly reflect reality. Most com <<
2025 indicating that the counter is not <<
2026 3044
2027 config AS_HAS_ARMV8_4 !! 3045 config SYS_SUPPORTS_128HZ
2028 def_bool $(cc-option,-Wa$(comma)-marc !! 3046 bool
2029 3047
2030 config ARM64_TLB_RANGE !! 3048 config SYS_SUPPORTS_250HZ
2031 bool "Enable support for tlbi range f !! 3049 bool
2032 default y <<
2033 depends on AS_HAS_ARMV8_4 <<
2034 help <<
2035 ARMv8.4-TLBI provides TLBI invalida <<
2036 range of input addresses. <<
2037 3050
2038 The feature introduces new assembly !! 3051 config SYS_SUPPORTS_256HZ
2039 support when binutils >= 2.30. !! 3052 bool
2040 3053
2041 endmenu # "ARMv8.4 architectural features" !! 3054 config SYS_SUPPORTS_1000HZ
>> 3055 bool
2042 3056
2043 menu "ARMv8.5 architectural features" !! 3057 config SYS_SUPPORTS_1024HZ
>> 3058 bool
2044 3059
2045 config AS_HAS_ARMV8_5 !! 3060 config SYS_SUPPORTS_ARBIT_HZ
2046 def_bool $(cc-option,-Wa$(comma)-marc !! 3061 bool
>> 3062 default y if !SYS_SUPPORTS_24HZ && \
>> 3063 !SYS_SUPPORTS_48HZ && \
>> 3064 !SYS_SUPPORTS_100HZ && \
>> 3065 !SYS_SUPPORTS_128HZ && \
>> 3066 !SYS_SUPPORTS_250HZ && \
>> 3067 !SYS_SUPPORTS_256HZ && \
>> 3068 !SYS_SUPPORTS_1000HZ && \
>> 3069 !SYS_SUPPORTS_1024HZ
2047 3070
2048 config ARM64_BTI !! 3071 config HZ
2049 bool "Branch Target Identification su !! 3072 int
2050 default y !! 3073 default 24 if HZ_24
2051 help !! 3074 default 48 if HZ_48
2052 Branch Target Identification (part !! 3075 default 100 if HZ_100
2053 provides a mechanism to limit the s !! 3076 default 128 if HZ_128
2054 branch instructions such as BR or B !! 3077 default 250 if HZ_250
>> 3078 default 256 if HZ_256
>> 3079 default 1000 if HZ_1000
>> 3080 default 1024 if HZ_1024
>> 3081
>> 3082 config SCHED_HRTICK
>> 3083 def_bool HIGH_RES_TIMERS
>> 3084
>> 3085 config KEXEC
>> 3086 bool "Kexec system call"
>> 3087 select KEXEC_CORE
>> 3088 help
>> 3089 kexec is a system call that implements the ability to shutdown your
>> 3090 current kernel, and to start another kernel. It is like a reboot
>> 3091 but it is independent of the system firmware. And like a reboot
>> 3092 you can start any kernel with it, not just Linux.
>> 3093
>> 3094 The name comes from the similarity to the exec system call.
>> 3095
>> 3096 It is an ongoing process to be certain the hardware in a machine
>> 3097 is properly shutdown, so do not be surprised if this code does not
>> 3098 initially work for you. As of this writing the exact hardware
>> 3099 interface is strongly in flux, so no good recommendation can be
>> 3100 made.
>> 3101
>> 3102 config CRASH_DUMP
>> 3103 bool "Kernel crash dumps"
>> 3104 help
>> 3105 Generate crash dump after being started by kexec.
>> 3106 This should be normally only set in special crash dump kernels
>> 3107 which are loaded in the main kernel with kexec-tools into
>> 3108 a specially reserved region and then later executed after
>> 3109 a crash by kdump/kexec. The crash dump kernel must be compiled
>> 3110 to a memory address not used by the main kernel or firmware using
>> 3111 PHYSICAL_START.
>> 3112
>> 3113 config PHYSICAL_START
>> 3114 hex "Physical address where the kernel is loaded"
>> 3115 default "0xffffffff84000000"
>> 3116 depends on CRASH_DUMP
>> 3117 help
>> 3118 This gives the CKSEG0 or KSEG0 address where the kernel is loaded.
>> 3119 If you plan to use kernel for capturing the crash dump change
>> 3120 this value to start of the reserved region (the "X" value as
>> 3121 specified in the "crashkernel=YM@XM" command line boot parameter
>> 3122 passed to the panic-ed kernel).
>> 3123
>> 3124 config MIPS_O32_FP64_SUPPORT
>> 3125 bool "Support for O32 binaries using 64-bit FP" if !CPU_MIPSR6
>> 3126 depends on 32BIT || MIPS32_O32
>> 3127 help
>> 3128 When this is enabled, the kernel will support use of 64-bit floating
>> 3129 point registers with binaries using the O32 ABI along with the
>> 3130 EF_MIPS_FP64 ELF header flag (typically built with -mfp64). On
>> 3131 32-bit MIPS systems this support is at the cost of increasing the
>> 3132 size and complexity of the compiled FPU emulator. Thus if you are
>> 3133 running a MIPS32 system and know that none of your userland binaries
>> 3134 will require 64-bit floating point, you may wish to reduce the size
>> 3135 of your kernel & potentially improve FP emulation performance by
>> 3136 saying N here.
>> 3137
>> 3138 Although binutils currently supports use of this flag the details
>> 3139 concerning its effect upon the O32 ABI in userland are still being
>> 3140 worked on. In order to avoid userland becoming dependent upon current
>> 3141 behaviour before the details have been finalised, this option should
>> 3142 be considered experimental and only enabled by those working upon
>> 3143 said details.
2055 3144
2056 To make use of BTI on CPUs that sup !! 3145 If unsure, say N.
2057 3146
2058 BTI is intended to provide compleme !! 3147 config USE_OF
2059 flow integrity protection mechanism !! 3148 bool
2060 authentication mechanism provided a !! 3149 select OF
2061 For this reason, it does not make s !! 3150 select OF_EARLY_FLATTREE
2062 also enabling support for pointer a !! 3151 select IRQ_DOMAIN
2063 enabling this option you should als <<
2064 3152
2065 Userspace binaries must also be spe !! 3153 config UHI_BOOT
2066 this mechanism. If you say N here !! 3154 bool
2067 BTI, such binaries can still run, b <<
2068 enforcement of branch destinations. <<
2069 3155
2070 config ARM64_BTI_KERNEL !! 3156 config BUILTIN_DTB
2071 bool "Use Branch Target Identificatio !! 3157 bool
2072 default y <<
2073 depends on ARM64_BTI <<
2074 depends on ARM64_PTR_AUTH_KERNEL <<
2075 depends on CC_HAS_BRANCH_PROT_PAC_RET <<
2076 # https://gcc.gnu.org/bugzilla/show_b <<
2077 depends on !CC_IS_GCC || GCC_VERSION <<
2078 # https://gcc.gnu.org/bugzilla/show_b <<
2079 depends on !CC_IS_GCC <<
2080 depends on (!FUNCTION_GRAPH_TRACER || <<
2081 help <<
2082 Build the kernel with Branch Target <<
2083 and enable enforcement of this for <<
2084 is enabled and the system supports <<
2085 modular code must have BTI enabled. <<
2086 3158
2087 config CC_HAS_BRANCH_PROT_PAC_RET_BTI !! 3159 choice
2088 # GCC 9 or later, clang 8 or later !! 3160 prompt "Kernel appended dtb support" if USE_OF
2089 def_bool $(cc-option,-mbranch-protect !! 3161 default MIPS_NO_APPENDED_DTB
2090 3162
2091 config ARM64_E0PD !! 3163 config MIPS_NO_APPENDED_DTB
2092 bool "Enable support for E0PD" !! 3164 bool "None"
2093 default y !! 3165 help
2094 help !! 3166 Do not enable appended dtb support.
2095 E0PD (part of the ARMv8.5 extension !! 3167
2096 that EL0 accesses made via TTBR1 al !! 3168 config MIPS_ELF_APPENDED_DTB
2097 providing similar benefits to KASLR !! 3169 bool "vmlinux"
2098 with lower overhead and without dis !! 3170 help
2099 kernel memory such as SPE. !! 3171 With this option, the boot code will look for a device tree binary
>> 3172 DTB) included in the vmlinux ELF section .appended_dtb. By default
>> 3173 it is empty and the DTB can be appended using binutils command
>> 3174 objcopy:
>> 3175
>> 3176 objcopy --update-section .appended_dtb=<filename>.dtb vmlinux
>> 3177
>> 3178 This is meant as a backward compatibility convenience for those
>> 3179 systems with a bootloader that can't be upgraded to accommodate
>> 3180 the documented boot protocol using a device tree.
>> 3181
>> 3182 config MIPS_RAW_APPENDED_DTB
>> 3183 bool "vmlinux.bin or vmlinuz.bin"
>> 3184 help
>> 3185 With this option, the boot code will look for a device tree binary
>> 3186 DTB) appended to raw vmlinux.bin or vmlinuz.bin.
>> 3187 (e.g. cat vmlinux.bin <filename>.dtb > vmlinux_w_dtb).
>> 3188
>> 3189 This is meant as a backward compatibility convenience for those
>> 3190 systems with a bootloader that can't be upgraded to accommodate
>> 3191 the documented boot protocol using a device tree.
>> 3192
>> 3193 Beware that there is very little in terms of protection against
>> 3194 this option being confused by leftover garbage in memory that might
>> 3195 look like a DTB header after a reboot if no actual DTB is appended
>> 3196 to vmlinux.bin. Do not leave this option active in a production kernel
>> 3197 if you don't intend to always append a DTB.
>> 3198 endchoice
2100 3199
2101 This option enables E0PD for TTBR1 !! 3200 choice
>> 3201 prompt "Kernel command line type" if !CMDLINE_OVERRIDE
>> 3202 default MIPS_CMDLINE_FROM_DTB if USE_OF && !ATH79 && !MACH_INGENIC && \
>> 3203 !MACH_LOONGSON64 && !MIPS_MALTA && \
>> 3204 !CAVIUM_OCTEON_SOC
>> 3205 default MIPS_CMDLINE_FROM_BOOTLOADER
>> 3206
>> 3207 config MIPS_CMDLINE_FROM_DTB
>> 3208 depends on USE_OF
>> 3209 bool "Dtb kernel arguments if available"
>> 3210
>> 3211 config MIPS_CMDLINE_DTB_EXTEND
>> 3212 depends on USE_OF
>> 3213 bool "Extend dtb kernel arguments with bootloader arguments"
>> 3214
>> 3215 config MIPS_CMDLINE_FROM_BOOTLOADER
>> 3216 bool "Bootloader kernel arguments if available"
>> 3217
>> 3218 config MIPS_CMDLINE_BUILTIN_EXTEND
>> 3219 depends on CMDLINE_BOOL
>> 3220 bool "Extend builtin kernel arguments with bootloader arguments"
>> 3221 endchoice
2102 3222
2103 config ARM64_AS_HAS_MTE !! 3223 endmenu
2104 # Initial support for MTE went in bin <<
2105 # ".arch armv8.5-a+memtag" below. How <<
2106 # as a late addition to the final arc <<
2107 # is only supported in the newer 2.32 <<
2108 # versions, hence the extra "stgm" in <<
2109 def_bool $(as-instr,.arch armv8.5-a+m <<
2110 3224
2111 config ARM64_MTE !! 3225 config LOCKDEP_SUPPORT
2112 bool "Memory Tagging Extension suppor !! 3226 bool
2113 default y 3227 default y
2114 depends on ARM64_AS_HAS_MTE && ARM64_ <<
2115 depends on AS_HAS_ARMV8_5 <<
2116 depends on AS_HAS_LSE_ATOMICS <<
2117 # Required for tag checking in the ua <<
2118 depends on ARM64_PAN <<
2119 select ARCH_HAS_SUBPAGE_FAULTS <<
2120 select ARCH_USES_HIGH_VMA_FLAGS <<
2121 select ARCH_USES_PG_ARCH_2 <<
2122 select ARCH_USES_PG_ARCH_3 <<
2123 help <<
2124 Memory Tagging (part of the ARMv8.5 <<
2125 architectural support for run-time, <<
2126 various classes of memory error to <<
2127 to eliminate vulnerabilities arisin <<
2128 languages. <<
2129 <<
2130 This option enables the support for <<
2131 Extension at EL0 (i.e. for userspac <<
2132 <<
2133 Selecting this option allows the fe <<
2134 runtime. Any secondary CPU not impl <<
2135 not be allowed a late bring-up. <<
2136 3228
2137 Userspace binaries that want to use !! 3229 config STACKTRACE_SUPPORT
2138 explicitly opt in. The mechanism fo !! 3230 bool
2139 described in: <<
2140 <<
2141 Documentation/arch/arm64/memory-tag <<
2142 <<
2143 endmenu # "ARMv8.5 architectural features" <<
2144 <<
2145 menu "ARMv8.7 architectural features" <<
2146 <<
2147 config ARM64_EPAN <<
2148 bool "Enable support for Enhanced Pri <<
2149 default y 3231 default y
2150 depends on ARM64_PAN <<
2151 help <<
2152 Enhanced Privileged Access Never (E <<
2153 Access Never to be used with Execut <<
2154 <<
2155 The feature is detected at runtime, <<
2156 if the cpu does not implement the f <<
2157 endmenu # "ARMv8.7 architectural features" <<
2158 <<
2159 menu "ARMv8.9 architectural features" <<
2160 <<
2161 config ARM64_POE <<
2162 prompt "Permission Overlay Extension" <<
2163 def_bool y <<
2164 select ARCH_USES_HIGH_VMA_FLAGS <<
2165 select ARCH_HAS_PKEYS <<
2166 help <<
2167 The Permission Overlay Extension is <<
2168 Protection Keys. Memory Protection <<
2169 enforcing page-based protections, b <<
2170 of the page tables when an applicat <<
2171 <<
2172 For details, see Documentation/core <<
2173 <<
2174 If unsure, say y. <<
2175 3232
2176 config ARCH_PKEY_BITS !! 3233 config PGTABLE_LEVELS
2177 int 3234 int
2178 default 3 !! 3235 default 4 if PAGE_SIZE_4KB && MIPS_VA_BITS_48
2179 !! 3236 default 3 if 64BIT && !PAGE_SIZE_64KB
2180 endmenu # "ARMv8.9 architectural features" !! 3237 default 2
2181 3238
2182 config ARM64_SVE !! 3239 config MIPS_AUTO_PFN_OFFSET
2183 bool "ARM Scalable Vector Extension s !! 3240 bool
2184 default y <<
2185 help <<
2186 The Scalable Vector Extension (SVE) <<
2187 execution state which complements a <<
2188 of the base architecture to support <<
2189 additional vectorisation opportunit <<
2190 <<
2191 To enable use of this extension on <<
2192 3241
2193 On CPUs that support the SVE2 exten !! 3242 menu "Bus options (PCI, PCMCIA, EISA, ISA, TC)"
2194 those too. <<
2195 3243
2196 Note that for architectural reasons !! 3244 config PCI_DRIVERS_GENERIC
2197 support when running on SVE capable !! 3245 select PCI_DOMAINS_GENERIC if PCI
2198 is present in: !! 3246 bool
2199 3247
2200 * version 1.5 and later of the AR !! 3248 config PCI_DRIVERS_LEGACY
2201 * the AArch64 boot wrapper since !! 3249 def_bool !PCI_DRIVERS_GENERIC
2202 ("bootwrapper: SVE: Enable SVE !! 3250 select NO_GENERIC_PCI_IOPORT_MAP
>> 3251 select PCI_DOMAINS if PCI
2203 3252
2204 For other firmware implementations, !! 3253 #
2205 or vendor. !! 3254 # ISA support is now enabled via select. Too many systems still have the one
>> 3255 # or other ISA chip on the board that users don't know about so don't expect
>> 3256 # users to choose the right thing ...
>> 3257 #
>> 3258 config ISA
>> 3259 bool
2206 3260
2207 If you need the kernel to boot on S !! 3261 config TC
2208 firmware, you may need to say N her !! 3262 bool "TURBOchannel support"
2209 fixed. Otherwise, you may experien !! 3263 depends on MACH_DECSTATION
2210 booting the kernel. If unsure and !! 3264 help
2211 symptoms, you should assume that it !! 3265 TURBOchannel is a DEC (now Compaq (now HP)) bus for Alpha and MIPS
>> 3266 processors. TURBOchannel programming specifications are available
>> 3267 at:
>> 3268 <ftp://ftp.hp.com/pub/alphaserver/archive/triadd/>
>> 3269 and:
>> 3270 <http://www.computer-refuge.org/classiccmp/ftp.digital.com/pub/DEC/TriAdd/>
>> 3271 Linux driver support status is documented at:
>> 3272 <http://www.linux-mips.org/wiki/DECstation>
2212 3273
2213 config ARM64_SME !! 3274 config MMU
2214 bool "ARM Scalable Matrix Extension s !! 3275 bool
2215 default y 3276 default y
2216 depends on ARM64_SVE <<
2217 depends on BROKEN <<
2218 help <<
2219 The Scalable Matrix Extension (SME) <<
2220 execution state which utilises a su <<
2221 instruction set, together with the <<
2222 register state capable of holding t <<
2223 enable various matrix operations. <<
2224 <<
2225 config ARM64_PSEUDO_NMI <<
2226 bool "Support for NMI-like interrupts <<
2227 select ARM_GIC_V3 <<
2228 help <<
2229 Adds support for mimicking Non-Mask <<
2230 GIC interrupt priority. This suppor <<
2231 ARM GIC. <<
2232 3277
2233 This high priority configuration fo !! 3278 config ARCH_MMAP_RND_BITS_MIN
2234 explicitly enabled by setting the k !! 3279 default 12 if 64BIT
2235 "irqchip.gicv3_pseudo_nmi" to 1. !! 3280 default 8
2236 <<
2237 If unsure, say N <<
2238 <<
2239 if ARM64_PSEUDO_NMI <<
2240 config ARM64_DEBUG_PRIORITY_MASKING <<
2241 bool "Debug interrupt priority maskin <<
2242 help <<
2243 This adds runtime checks to functio <<
2244 interrupts when using priority mask <<
2245 the validity of ICC_PMR_EL1 when ca <<
2246 3281
2247 If unsure, say N !! 3282 config ARCH_MMAP_RND_BITS_MAX
2248 endif # ARM64_PSEUDO_NMI !! 3283 default 18 if 64BIT
>> 3284 default 15
2249 3285
2250 config RELOCATABLE !! 3286 config ARCH_MMAP_RND_COMPAT_BITS_MIN
2251 bool "Build a relocatable kernel imag !! 3287 default 8
2252 select ARCH_HAS_RELR <<
2253 default y <<
2254 help <<
2255 This builds the kernel as a Positio <<
2256 which retains all relocation metada <<
2257 kernel binary at runtime to a diffe <<
2258 address it was linked at. <<
2259 Since AArch64 uses the RELA relocat <<
2260 relocation pass at runtime even if <<
2261 same address it was linked at. <<
2262 3288
2263 config RANDOMIZE_BASE !! 3289 config ARCH_MMAP_RND_COMPAT_BITS_MAX
2264 bool "Randomize the address of the ke !! 3290 default 15
2265 select RELOCATABLE <<
2266 help <<
2267 Randomizes the virtual address at w <<
2268 loaded, as a security feature that <<
2269 relying on knowledge of the locatio <<
2270 <<
2271 It is the bootloader's job to provi <<
2272 random u64 value in /chosen/kaslr-s <<
2273 <<
2274 When booting via the UEFI stub, it <<
2275 EFI_RNG_PROTOCOL implementation (if <<
2276 to the kernel proper. In addition, <<
2277 location of the kernel Image as wel <<
2278 3291
2279 If unsure, say N. !! 3292 config I8253
>> 3293 bool
>> 3294 select CLKSRC_I8253
>> 3295 select CLKEVT_I8253
>> 3296 select MIPS_EXTERNAL_TIMER
2280 3297
2281 config RANDOMIZE_MODULE_REGION_FULL !! 3298 config ZONE_DMA
2282 bool "Randomize the module region ove !! 3299 bool
2283 depends on RANDOMIZE_BASE <<
2284 default y <<
2285 help <<
2286 Randomizes the location of the modu <<
2287 covering the core kernel. This way, <<
2288 to leak information about the locat <<
2289 but it does imply that function cal <<
2290 kernel will need to be resolved via <<
2291 <<
2292 When this option is not set, the mo <<
2293 a limited range that contains the [ <<
2294 core kernel, so branch relocations <<
2295 the region is exhausted. In this pa <<
2296 exhaustion, modules might be able t <<
2297 3300
2298 config CC_HAVE_STACKPROTECTOR_SYSREG !! 3301 config ZONE_DMA32
2299 def_bool $(cc-option,-mstack-protecto !! 3302 bool
2300 3303
2301 config STACKPROTECTOR_PER_TASK !! 3304 endmenu
2302 def_bool y <<
2303 depends on STACKPROTECTOR && CC_HAVE_ <<
2304 3305
2305 config UNWIND_PATCH_PAC_INTO_SCS !! 3306 config TRAD_SIGNALS
2306 bool "Enable shadow call stack dynami !! 3307 bool
2307 # needs Clang with https://github.com <<
2308 depends on CC_IS_CLANG && CLANG_VERSI <<
2309 depends on ARM64_PTR_AUTH_KERNEL && C <<
2310 depends on SHADOW_CALL_STACK <<
2311 select UNWIND_TABLES <<
2312 select DYNAMIC_SCS <<
2313 <<
2314 config ARM64_CONTPTE <<
2315 bool "Contiguous PTE mappings for use <<
2316 depends on TRANSPARENT_HUGEPAGE <<
2317 default y <<
2318 help <<
2319 When enabled, user mappings are con <<
2320 bit, for any mappings that meet the <<
2321 This reduces TLB pressure and impro <<
2322 <<
2323 endmenu # "Kernel Features" <<
2324 <<
2325 menu "Boot options" <<
2326 <<
2327 config ARM64_ACPI_PARKING_PROTOCOL <<
2328 bool "Enable support for the ARM64 AC <<
2329 depends on ACPI <<
2330 help <<
2331 Enable support for the ARM64 ACPI p <<
2332 the kernel will not allow booting t <<
2333 protocol even if the corresponding <<
2334 MADT table. <<
2335 <<
2336 config CMDLINE <<
2337 string "Default kernel command string <<
2338 default "" <<
2339 help <<
2340 Provide a set of default command-li <<
2341 entering them here. As a minimum, y <<
2342 root device (e.g. root=/dev/nfs). <<
2343 3308
2344 choice !! 3309 config MIPS32_COMPAT
2345 prompt "Kernel command line type" !! 3310 bool
2346 depends on CMDLINE != "" <<
2347 default CMDLINE_FROM_BOOTLOADER <<
2348 help <<
2349 Choose how the kernel will handle t <<
2350 command line string. <<
2351 <<
2352 config CMDLINE_FROM_BOOTLOADER <<
2353 bool "Use bootloader kernel arguments <<
2354 help <<
2355 Uses the command-line options passe <<
2356 the boot loader doesn't provide any <<
2357 string provided in CMDLINE will be <<
2358 <<
2359 config CMDLINE_FORCE <<
2360 bool "Always use the default kernel c <<
2361 help <<
2362 Always use the default kernel comma <<
2363 loader passes other arguments to th <<
2364 This is useful if you cannot or don <<
2365 command-line options your boot load <<
2366 3311
2367 endchoice !! 3312 config COMPAT
>> 3313 bool
2368 3314
2369 config EFI_STUB !! 3315 config SYSVIPC_COMPAT
2370 bool 3316 bool
2371 3317
2372 config EFI !! 3318 config MIPS32_O32
2373 bool "UEFI runtime support" !! 3319 bool "Kernel support for o32 binaries"
2374 depends on OF && !CPU_BIG_ENDIAN !! 3320 depends on 64BIT
2375 depends on KERNEL_MODE_NEON !! 3321 select ARCH_WANT_OLD_COMPAT_IPC
2376 select ARCH_SUPPORTS_ACPI !! 3322 select COMPAT
2377 select LIBFDT !! 3323 select MIPS32_COMPAT
2378 select UCS2_STRING !! 3324 select SYSVIPC_COMPAT if SYSVIPC
2379 select EFI_PARAMS_FROM_FDT !! 3325 help
2380 select EFI_RUNTIME_WRAPPERS !! 3326 Select this option if you want to run o32 binaries. These are pure
2381 select EFI_STUB !! 3327 32-bit binaries as used by the 32-bit Linux/MIPS port. Most of
2382 select EFI_GENERIC_STUB !! 3328 existing binaries are in this format.
2383 imply IMA_SECURE_AND_OR_TRUSTED_BOOT <<
2384 default y <<
2385 help <<
2386 This option provides support for ru <<
2387 by UEFI firmware (such as non-volat <<
2388 clock, and platform reset). A UEFI <<
2389 allow the kernel to be booted as an <<
2390 is only useful on systems that have <<
2391 <<
2392 config COMPRESSED_INSTALL <<
2393 bool "Install compressed image by def <<
2394 help <<
2395 This makes the regular "make instal <<
2396 image we built, not the legacy unco <<
2397 <<
2398 You can check that a compressed ima <<
2399 "make zinstall" first, and verifyin <<
2400 in your environment before making " <<
2401 you. <<
2402 3329
2403 config DMI !! 3330 If unsure, say Y.
2404 bool "Enable support for SMBIOS (DMI) <<
2405 depends on EFI <<
2406 default y <<
2407 help <<
2408 This enables SMBIOS/DMI feature for <<
2409 3331
2410 This option is only useful on syste !! 3332 config MIPS32_N32
2411 However, even with this option, the !! 3333 bool "Kernel support for n32 binaries"
2412 continue to boot on existing non-UE !! 3334 depends on 64BIT
>> 3335 select ARCH_WANT_COMPAT_IPC_PARSE_VERSION
>> 3336 select COMPAT
>> 3337 select MIPS32_COMPAT
>> 3338 select SYSVIPC_COMPAT if SYSVIPC
>> 3339 help
>> 3340 Select this option if you want to run n32 binaries. These are
>> 3341 64-bit binaries using 32-bit quantities for addressing and certain
>> 3342 data that would normally be 64-bit. They are used in special
>> 3343 cases.
2413 3344
2414 endmenu # "Boot options" !! 3345 If unsure, say N.
2415 3346
2416 menu "Power management options" 3347 menu "Power management options"
2417 3348
2418 source "kernel/power/Kconfig" <<
2419 <<
2420 config ARCH_HIBERNATION_POSSIBLE 3349 config ARCH_HIBERNATION_POSSIBLE
2421 def_bool y 3350 def_bool y
2422 depends on CPU_PM !! 3351 depends on SYS_SUPPORTS_HOTPLUG_CPU || !SMP
2423 <<
2424 config ARCH_HIBERNATION_HEADER <<
2425 def_bool y <<
2426 depends on HIBERNATION <<
2427 3352
2428 config ARCH_SUSPEND_POSSIBLE 3353 config ARCH_SUSPEND_POSSIBLE
2429 def_bool y 3354 def_bool y
>> 3355 depends on SYS_SUPPORTS_HOTPLUG_CPU || !SMP
2430 3356
2431 endmenu # "Power management options" !! 3357 source "kernel/power/Kconfig"
2432 3358
2433 menu "CPU Power Management" !! 3359 endmenu
2434 3360
2435 source "drivers/cpuidle/Kconfig" !! 3361 config MIPS_EXTERNAL_TIMER
>> 3362 bool
>> 3363
>> 3364 menu "CPU Power Management"
2436 3365
>> 3366 if CPU_SUPPORTS_CPUFREQ && MIPS_EXTERNAL_TIMER
2437 source "drivers/cpufreq/Kconfig" 3367 source "drivers/cpufreq/Kconfig"
>> 3368 endif
>> 3369
>> 3370 source "drivers/cpuidle/Kconfig"
2438 3371
2439 endmenu # "CPU Power Management" !! 3372 endmenu
2440 3373
2441 source "drivers/acpi/Kconfig" !! 3374 source "drivers/firmware/Kconfig"
2442 3375
2443 source "arch/arm64/kvm/Kconfig" !! 3376 source "arch/mips/kvm/Kconfig"
2444 3377
>> 3378 source "arch/mips/vdso/Kconfig"
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