1 # SPDX-License-Identifier: GPL-2.0-only !! 1 # SPDX-License-Identifier: GPL-2.0
2 config ARM64 !! 2 config MIPS
3 def_bool y !! 3 bool
4 select ACPI_APMT if ACPI !! 4 default y
5 select ACPI_CCA_REQUIRED if ACPI !! 5 select ARCH_32BIT_OFF_T if !64BIT
6 select ACPI_GENERIC_GSI if ACPI !! 6 select ARCH_BINFMT_ELF_STATE if MIPS_FP_SUPPORT
7 select ACPI_GTDT if ACPI !! 7 select ARCH_HAS_DEBUG_VIRTUAL if !64BIT
8 select ACPI_HOTPLUG_CPU if ACPI_PROCES <<
9 select ACPI_IORT if ACPI <<
10 select ACPI_REDUCED_HARDWARE_ONLY if A <<
11 select ACPI_MCFG if (ACPI && PCI) <<
12 select ACPI_SPCR_TABLE if ACPI <<
13 select ACPI_PPTT if ACPI <<
14 select ARCH_HAS_DEBUG_WX <<
15 select ARCH_BINFMT_ELF_EXTRA_PHDRS <<
16 select ARCH_BINFMT_ELF_STATE <<
17 select ARCH_CORRECT_STACKTRACE_ON_KRET <<
18 select ARCH_ENABLE_HUGEPAGE_MIGRATION <<
19 select ARCH_ENABLE_MEMORY_HOTPLUG <<
20 select ARCH_ENABLE_MEMORY_HOTREMOVE <<
21 select ARCH_ENABLE_SPLIT_PMD_PTLOCK if <<
22 select ARCH_ENABLE_THP_MIGRATION if TR <<
23 select ARCH_HAS_CACHE_LINE_SIZE <<
24 select ARCH_HAS_CURRENT_STACK_POINTER <<
25 select ARCH_HAS_DEBUG_VIRTUAL <<
26 select ARCH_HAS_DEBUG_VM_PGTABLE <<
27 select ARCH_HAS_DMA_OPS if XEN <<
28 select ARCH_HAS_DMA_PREP_COHERENT <<
29 select ARCH_HAS_ACPI_TABLE_UPGRADE if <<
30 select ARCH_HAS_FAST_MULTIPLIER <<
31 select ARCH_HAS_FORTIFY_SOURCE 8 select ARCH_HAS_FORTIFY_SOURCE
32 select ARCH_HAS_GCOV_PROFILE_ALL <<
33 select ARCH_HAS_GIGANTIC_PAGE <<
34 select ARCH_HAS_KCOV 9 select ARCH_HAS_KCOV
35 select ARCH_HAS_KERNEL_FPU_SUPPORT if !! 10 select ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE if !EVA
36 select ARCH_HAS_KEEPINITRD !! 11 select ARCH_HAS_PTE_SPECIAL if !(32BIT && CPU_HAS_RIXI)
37 select ARCH_HAS_MEMBARRIER_SYNC_CORE <<
38 select ARCH_HAS_MEM_ENCRYPT <<
39 select ARCH_HAS_NMI_SAFE_THIS_CPU_OPS <<
40 select ARCH_HAS_NON_OVERLAPPING_ADDRES <<
41 select ARCH_HAS_PTE_DEVMAP <<
42 select ARCH_HAS_PTE_SPECIAL <<
43 select ARCH_HAS_HW_PTE_YOUNG <<
44 select ARCH_HAS_SETUP_DMA_OPS <<
45 select ARCH_HAS_SET_DIRECT_MAP <<
46 select ARCH_HAS_SET_MEMORY <<
47 select ARCH_STACKWALK <<
48 select ARCH_HAS_STRICT_KERNEL_RWX <<
49 select ARCH_HAS_STRICT_MODULE_RWX <<
50 select ARCH_HAS_SYNC_DMA_FOR_DEVICE <<
51 select ARCH_HAS_SYNC_DMA_FOR_CPU <<
52 select ARCH_HAS_SYSCALL_WRAPPER <<
53 select ARCH_HAS_TICK_BROADCAST if GENE 12 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
54 select ARCH_HAS_ZONE_DMA_SET if EXPERT !! 13 select ARCH_HAS_UBSAN_SANITIZE_ALL
55 select ARCH_HAVE_ELF_PROT !! 14 select ARCH_HAS_GCOV_PROFILE_ALL
56 select ARCH_HAVE_NMI_SAFE_CMPXCHG <<
57 select ARCH_HAVE_TRACE_MMIO_ACCESS <<
58 select ARCH_INLINE_READ_LOCK if !PREEM <<
59 select ARCH_INLINE_READ_LOCK_BH if !PR <<
60 select ARCH_INLINE_READ_LOCK_IRQ if !P <<
61 select ARCH_INLINE_READ_LOCK_IRQSAVE i <<
62 select ARCH_INLINE_READ_UNLOCK if !PRE <<
63 select ARCH_INLINE_READ_UNLOCK_BH if ! <<
64 select ARCH_INLINE_READ_UNLOCK_IRQ if <<
65 select ARCH_INLINE_READ_UNLOCK_IRQREST <<
66 select ARCH_INLINE_WRITE_LOCK if !PREE <<
67 select ARCH_INLINE_WRITE_LOCK_BH if !P <<
68 select ARCH_INLINE_WRITE_LOCK_IRQ if ! <<
69 select ARCH_INLINE_WRITE_LOCK_IRQSAVE <<
70 select ARCH_INLINE_WRITE_UNLOCK if !PR <<
71 select ARCH_INLINE_WRITE_UNLOCK_BH if <<
72 select ARCH_INLINE_WRITE_UNLOCK_IRQ if <<
73 select ARCH_INLINE_WRITE_UNLOCK_IRQRES <<
74 select ARCH_INLINE_SPIN_TRYLOCK if !PR <<
75 select ARCH_INLINE_SPIN_TRYLOCK_BH if <<
76 select ARCH_INLINE_SPIN_LOCK if !PREEM <<
77 select ARCH_INLINE_SPIN_LOCK_BH if !PR <<
78 select ARCH_INLINE_SPIN_LOCK_IRQ if !P <<
79 select ARCH_INLINE_SPIN_LOCK_IRQSAVE i <<
80 select ARCH_INLINE_SPIN_UNLOCK if !PRE <<
81 select ARCH_INLINE_SPIN_UNLOCK_BH if ! <<
82 select ARCH_INLINE_SPIN_UNLOCK_IRQ if <<
83 select ARCH_INLINE_SPIN_UNLOCK_IRQREST <<
84 select ARCH_KEEP_MEMBLOCK 15 select ARCH_KEEP_MEMBLOCK
85 select ARCH_MHP_MEMMAP_ON_MEMORY_ENABL !! 16 select ARCH_SUPPORTS_UPROBES
86 select ARCH_USE_CMPXCHG_LOCKREF !! 17 select ARCH_USE_BUILTIN_BSWAP
87 select ARCH_USE_GNU_PROPERTY !! 18 select ARCH_USE_CMPXCHG_LOCKREF if 64BIT
88 select ARCH_USE_MEMTEST 19 select ARCH_USE_MEMTEST
89 select ARCH_USE_QUEUED_RWLOCKS 20 select ARCH_USE_QUEUED_RWLOCKS
90 select ARCH_USE_QUEUED_SPINLOCKS 21 select ARCH_USE_QUEUED_SPINLOCKS
91 select ARCH_USE_SYM_ANNOTATIONS !! 22 select ARCH_SUPPORTS_HUGETLBFS if CPU_SUPPORTS_HUGEPAGES
92 select ARCH_SUPPORTS_DEBUG_PAGEALLOC !! 23 select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT if MMU
93 select ARCH_SUPPORTS_HUGETLBFS !! 24 select ARCH_WANT_IPC_PARSE_VERSION
94 select ARCH_SUPPORTS_MEMORY_FAILURE <<
95 select ARCH_SUPPORTS_SHADOW_CALL_STACK <<
96 select ARCH_SUPPORTS_LTO_CLANG if CPU_ <<
97 select ARCH_SUPPORTS_LTO_CLANG_THIN <<
98 select ARCH_SUPPORTS_CFI_CLANG <<
99 select ARCH_SUPPORTS_ATOMIC_RMW <<
100 select ARCH_SUPPORTS_INT128 if CC_HAS_ <<
101 select ARCH_SUPPORTS_NUMA_BALANCING <<
102 select ARCH_SUPPORTS_PAGE_TABLE_CHECK <<
103 select ARCH_SUPPORTS_PER_VMA_LOCK <<
104 select ARCH_SUPPORTS_HUGE_PFNMAP if TR <<
105 select ARCH_SUPPORTS_RT <<
106 select ARCH_WANT_BATCHED_UNMAP_TLB_FLU <<
107 select ARCH_WANT_COMPAT_IPC_PARSE_VERS <<
108 select ARCH_WANT_DEFAULT_BPF_JIT <<
109 select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_ <<
110 select ARCH_WANT_FRAME_POINTERS <<
111 select ARCH_WANT_HUGE_PMD_SHARE if ARM <<
112 select ARCH_WANT_LD_ORPHAN_WARN 25 select ARCH_WANT_LD_ORPHAN_WARN
113 select ARCH_WANTS_EXECMEM_LATE if EXEC <<
114 select ARCH_WANTS_NO_INSTR <<
115 select ARCH_WANTS_THP_SWAP if ARM64_4K <<
116 select ARCH_HAS_UBSAN <<
117 select ARM_AMBA <<
118 select ARM_ARCH_TIMER <<
119 select ARM_GIC <<
120 select AUDIT_ARCH_COMPAT_GENERIC <<
121 select ARM_GIC_V2M if PCI <<
122 select ARM_GIC_V3 <<
123 select ARM_GIC_V3_ITS if PCI <<
124 select ARM_PSCI_FW <<
125 select BUILDTIME_TABLE_SORT 26 select BUILDTIME_TABLE_SORT
126 select CLONE_BACKWARDS 27 select CLONE_BACKWARDS
127 select COMMON_CLK !! 28 select CPU_NO_EFFICIENT_FFS if (TARGET_ISA_REV < 1)
128 select CPU_PM if (SUSPEND || CPU_IDLE) !! 29 select CPU_PM if CPU_IDLE
129 select CPUMASK_OFFSTACK if NR_CPUS > 2 !! 30 select GENERIC_ATOMIC64 if !64BIT
130 select CRC32 !! 31 select GENERIC_CMOS_UPDATE
131 select DCACHE_WORD_ACCESS <<
132 select DYNAMIC_FTRACE if FUNCTION_TRAC <<
133 select DMA_BOUNCE_UNALIGNED_KMALLOC <<
134 select DMA_DIRECT_REMAP <<
135 select EDAC_SUPPORT <<
136 select FRAME_POINTER <<
137 select FUNCTION_ALIGNMENT_4B <<
138 select FUNCTION_ALIGNMENT_8B if DYNAMI <<
139 select GENERIC_ALLOCATOR <<
140 select GENERIC_ARCH_TOPOLOGY <<
141 select GENERIC_CLOCKEVENTS_BROADCAST <<
142 select GENERIC_CPU_AUTOPROBE 32 select GENERIC_CPU_AUTOPROBE
143 select GENERIC_CPU_DEVICES !! 33 select GENERIC_FIND_FIRST_BIT
144 select GENERIC_CPU_VULNERABILITIES !! 34 select GENERIC_GETTIMEOFDAY
145 select GENERIC_EARLY_IOREMAP !! 35 select GENERIC_IOMAP
146 select GENERIC_IDLE_POLL_SETUP <<
147 select GENERIC_IOREMAP <<
148 select GENERIC_IRQ_IPI <<
149 select GENERIC_IRQ_PROBE 36 select GENERIC_IRQ_PROBE
150 select GENERIC_IRQ_SHOW 37 select GENERIC_IRQ_SHOW
151 select GENERIC_IRQ_SHOW_LEVEL !! 38 select GENERIC_ISA_DMA if EISA
152 select GENERIC_LIB_DEVMEM_IS_ALLOWED !! 39 select GENERIC_LIB_ASHLDI3
153 select GENERIC_PCI_IOMAP !! 40 select GENERIC_LIB_ASHRDI3
154 select GENERIC_PTDUMP !! 41 select GENERIC_LIB_CMPDI2
155 select GENERIC_SCHED_CLOCK !! 42 select GENERIC_LIB_LSHRDI3
>> 43 select GENERIC_LIB_UCMPDI2
>> 44 select GENERIC_SCHED_CLOCK if !CAVIUM_OCTEON_SOC
156 select GENERIC_SMP_IDLE_THREAD 45 select GENERIC_SMP_IDLE_THREAD
157 select GENERIC_TIME_VSYSCALL 46 select GENERIC_TIME_VSYSCALL
158 select GENERIC_GETTIMEOFDAY !! 47 select GUP_GET_PTE_LOW_HIGH if CPU_MIPS32 && PHYS_ADDR_T_64BIT
159 select GENERIC_VDSO_TIME_NS !! 48 select HANDLE_DOMAIN_IRQ
160 select HARDIRQS_SW_RESEND <<
161 select HAS_IOPORT <<
162 select HAVE_MOVE_PMD <<
163 select HAVE_MOVE_PUD <<
164 select HAVE_PCI <<
165 select HAVE_ACPI_APEI if (ACPI && EFI) <<
166 select HAVE_ALIGNED_STRUCT_PAGE <<
167 select HAVE_ARCH_AUDITSYSCALL <<
168 select HAVE_ARCH_BITREVERSE <<
169 select HAVE_ARCH_COMPILER_H 49 select HAVE_ARCH_COMPILER_H
170 select HAVE_ARCH_HUGE_VMALLOC <<
171 select HAVE_ARCH_HUGE_VMAP <<
172 select HAVE_ARCH_JUMP_LABEL 50 select HAVE_ARCH_JUMP_LABEL
173 select HAVE_ARCH_JUMP_LABEL_RELATIVE !! 51 select HAVE_ARCH_KGDB if MIPS_FP_SUPPORT
174 select HAVE_ARCH_KASAN !! 52 select HAVE_ARCH_MMAP_RND_BITS if MMU
175 select HAVE_ARCH_KASAN_VMALLOC !! 53 select HAVE_ARCH_MMAP_RND_COMPAT_BITS if MMU && COMPAT
176 select HAVE_ARCH_KASAN_SW_TAGS <<
177 select HAVE_ARCH_KASAN_HW_TAGS if ARM6 <<
178 # Some instrumentation may be unsound, <<
179 select HAVE_ARCH_KCSAN if EXPERT <<
180 select HAVE_ARCH_KFENCE <<
181 select HAVE_ARCH_KGDB <<
182 select HAVE_ARCH_MMAP_RND_BITS <<
183 select HAVE_ARCH_MMAP_RND_COMPAT_BITS <<
184 select HAVE_ARCH_PREL32_RELOCATIONS <<
185 select HAVE_ARCH_RANDOMIZE_KSTACK_OFFS <<
186 select HAVE_ARCH_SECCOMP_FILTER 54 select HAVE_ARCH_SECCOMP_FILTER
187 select HAVE_ARCH_STACKLEAK <<
188 select HAVE_ARCH_THREAD_STRUCT_WHITELI <<
189 select HAVE_ARCH_TRACEHOOK 55 select HAVE_ARCH_TRACEHOOK
190 select HAVE_ARCH_TRANSPARENT_HUGEPAGE !! 56 select HAVE_ARCH_TRANSPARENT_HUGEPAGE if CPU_SUPPORTS_HUGEPAGES
191 select HAVE_ARCH_VMAP_STACK <<
192 select HAVE_ARM_SMCCC <<
193 select HAVE_ASM_MODVERSIONS 57 select HAVE_ASM_MODVERSIONS
194 select HAVE_EBPF_JIT !! 58 select HAVE_CBPF_JIT if !64BIT && !CPU_MICROMIPS
>> 59 select HAVE_CONTEXT_TRACKING
>> 60 select HAVE_TIF_NOHZ
195 select HAVE_C_RECORDMCOUNT 61 select HAVE_C_RECORDMCOUNT
196 select HAVE_CMPXCHG_DOUBLE <<
197 select HAVE_CMPXCHG_LOCAL <<
198 select HAVE_CONTEXT_TRACKING_USER <<
199 select HAVE_DEBUG_KMEMLEAK 62 select HAVE_DEBUG_KMEMLEAK
>> 63 select HAVE_DEBUG_STACKOVERFLOW
200 select HAVE_DMA_CONTIGUOUS 64 select HAVE_DMA_CONTIGUOUS
201 select HAVE_DYNAMIC_FTRACE 65 select HAVE_DYNAMIC_FTRACE
202 select HAVE_DYNAMIC_FTRACE_WITH_ARGS \ !! 66 select HAVE_EBPF_JIT if 64BIT && !CPU_MICROMIPS && TARGET_ISA_REV >= 2
203 if (GCC_SUPPORTS_DYNAMIC_FTRAC !! 67 select HAVE_EXIT_THREAD
204 CLANG_SUPPORTS_DYNAMIC_FTR !! 68 select HAVE_FAST_GUP
205 select HAVE_DYNAMIC_FTRACE_WITH_DIRECT <<
206 if DYNAMIC_FTRACE_WITH_ARGS && <<
207 select HAVE_DYNAMIC_FTRACE_WITH_CALL_O <<
208 if (DYNAMIC_FTRACE_WITH_ARGS & <<
209 (CC_IS_CLANG || !CC_OPTIMI <<
210 select FTRACE_MCOUNT_USE_PATCHABLE_FUN <<
211 if DYNAMIC_FTRACE_WITH_ARGS <<
212 select HAVE_SAMPLE_FTRACE_DIRECT <<
213 select HAVE_SAMPLE_FTRACE_DIRECT_MULTI <<
214 select HAVE_EFFICIENT_UNALIGNED_ACCESS <<
215 select HAVE_GUP_FAST <<
216 select HAVE_FTRACE_MCOUNT_RECORD 69 select HAVE_FTRACE_MCOUNT_RECORD
217 select HAVE_FUNCTION_TRACER <<
218 select HAVE_FUNCTION_ERROR_INJECTION <<
219 select HAVE_FUNCTION_GRAPH_TRACER 70 select HAVE_FUNCTION_GRAPH_TRACER
220 select HAVE_FUNCTION_GRAPH_RETVAL !! 71 select HAVE_FUNCTION_TRACER
221 select HAVE_GCC_PLUGINS 72 select HAVE_GCC_PLUGINS
222 select HAVE_HARDLOCKUP_DETECTOR_PERF i !! 73 select HAVE_GENERIC_VDSO
223 HW_PERF_EVENTS && HAVE_PERF_EV <<
224 select HAVE_HW_BREAKPOINT if PERF_EVEN <<
225 select HAVE_IOREMAP_PROT 74 select HAVE_IOREMAP_PROT
>> 75 select HAVE_IRQ_EXIT_ON_IRQ_STACK
226 select HAVE_IRQ_TIME_ACCOUNTING 76 select HAVE_IRQ_TIME_ACCOUNTING
>> 77 select HAVE_KPROBES
>> 78 select HAVE_KRETPROBES
>> 79 select HAVE_LD_DEAD_CODE_DATA_ELIMINATION
227 select HAVE_MOD_ARCH_SPECIFIC 80 select HAVE_MOD_ARCH_SPECIFIC
228 select HAVE_NMI 81 select HAVE_NMI
229 select HAVE_PERF_EVENTS 82 select HAVE_PERF_EVENTS
230 select HAVE_PERF_EVENTS_NMI if ARM64_P <<
231 select HAVE_PERF_REGS 83 select HAVE_PERF_REGS
232 select HAVE_PERF_USER_STACK_DUMP 84 select HAVE_PERF_USER_STACK_DUMP
233 select HAVE_PREEMPT_DYNAMIC_KEY <<
234 select HAVE_REGS_AND_STACK_ACCESS_API 85 select HAVE_REGS_AND_STACK_ACCESS_API
235 select HAVE_POSIX_CPU_TIMERS_TASK_WORK <<
236 select HAVE_FUNCTION_ARG_ACCESS_API <<
237 select MMU_GATHER_RCU_TABLE_FREE <<
238 select HAVE_RSEQ 86 select HAVE_RSEQ
239 select HAVE_RUST if RUSTC_SUPPORTS_ARM !! 87 select HAVE_SPARSE_SYSCALL_NR
240 select HAVE_STACKPROTECTOR 88 select HAVE_STACKPROTECTOR
241 select HAVE_SYSCALL_TRACEPOINTS 89 select HAVE_SYSCALL_TRACEPOINTS
242 select HAVE_KPROBES !! 90 select HAVE_VIRT_CPU_ACCOUNTING_GEN if 64BIT || !SMP
243 select HAVE_KRETPROBES <<
244 select HAVE_GENERIC_VDSO <<
245 select HOTPLUG_CORE_SYNC_DEAD if HOTPL <<
246 select IRQ_DOMAIN <<
247 select IRQ_FORCED_THREADING 91 select IRQ_FORCED_THREADING
248 select KASAN_VMALLOC if KASAN !! 92 select ISA if EISA
249 select LOCK_MM_AND_FIND_VMA !! 93 select MODULES_USE_ELF_REL if MODULES
250 select MODULES_USE_ELF_RELA !! 94 select MODULES_USE_ELF_RELA if MODULES && 64BIT
251 select NEED_DMA_MAP_STATE !! 95 select PERF_USE_VMALLOC
252 select NEED_SG_DMA_LENGTH !! 96 select PCI_MSI_ARCH_FALLBACKS if PCI_MSI
253 select OF !! 97 select RTC_LIB
254 select OF_EARLY_FLATTREE <<
255 select PCI_DOMAINS_GENERIC if PCI <<
256 select PCI_ECAM if (ACPI && PCI) <<
257 select PCI_SYSCALL if PCI <<
258 select POWER_RESET <<
259 select POWER_SUPPLY <<
260 select SPARSE_IRQ <<
261 select SWIOTLB <<
262 select SYSCTL_EXCEPTION_TRACE 98 select SYSCTL_EXCEPTION_TRACE
263 select THREAD_INFO_IN_TASK !! 99 select VIRT_TO_BUS
264 select HAVE_ARCH_USERFAULTFD_MINOR if !! 100 select ARCH_HAS_ELFCORE_COMPAT
265 select HAVE_ARCH_USERFAULTFD_WP if USE <<
266 select TRACE_IRQFLAGS_SUPPORT <<
267 select TRACE_IRQFLAGS_NMI_SUPPORT <<
268 select HAVE_SOFTIRQ_ON_OWN_STACK <<
269 select USER_STACKTRACE_SUPPORT <<
270 select VDSO_GETRANDOM <<
271 help <<
272 ARM 64-bit (AArch64) Linux support. <<
273 101
274 config RUSTC_SUPPORTS_ARM64 !! 102 config MIPS_FIXUP_BIGPHYS_ADDR
275 def_bool y !! 103 bool
276 depends on CPU_LITTLE_ENDIAN <<
277 # Shadow call stack is only supported <<
278 # <<
279 # When using the UNWIND_PATCH_PAC_INTO <<
280 # required due to use of the -Zfixed-x <<
281 # <<
282 # Otherwise, rustc version 1.82+ is re <<
283 # -Zsanitizer=shadow-call-stack flag. <<
284 depends on !SHADOW_CALL_STACK || RUSTC <<
285 <<
286 config CLANG_SUPPORTS_DYNAMIC_FTRACE_WITH_ARGS <<
287 def_bool CC_IS_CLANG <<
288 # https://github.com/ClangBuiltLinux/l <<
289 depends on AS_IS_GNU || (AS_IS_LLVM && <<
290 <<
291 config GCC_SUPPORTS_DYNAMIC_FTRACE_WITH_ARGS <<
292 def_bool CC_IS_GCC <<
293 depends on $(cc-option,-fpatchable-fun <<
294 104
295 config 64BIT !! 105 config MIPS_GENERIC
296 def_bool y !! 106 bool
297 107
298 config MMU !! 108 config MACH_INGENIC
299 def_bool y !! 109 bool
>> 110 select SYS_SUPPORTS_32BIT_KERNEL
>> 111 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 112 select SYS_SUPPORTS_ZBOOT
>> 113 select DMA_NONCOHERENT
>> 114 select ARCH_HAS_SYNC_DMA_FOR_CPU
>> 115 select IRQ_MIPS_CPU
>> 116 select PINCTRL
>> 117 select GPIOLIB
>> 118 select COMMON_CLK
>> 119 select GENERIC_IRQ_CHIP
>> 120 select BUILTIN_DTB if MIPS_NO_APPENDED_DTB
>> 121 select USE_OF
>> 122 select CPU_SUPPORTS_CPUFREQ
>> 123 select MIPS_EXTERNAL_TIMER
300 124
301 config ARM64_CONT_PTE_SHIFT !! 125 menu "Machine selection"
302 int <<
303 default 5 if PAGE_SIZE_64KB <<
304 default 7 if PAGE_SIZE_16KB <<
305 default 4 <<
306 126
307 config ARM64_CONT_PMD_SHIFT !! 127 choice
308 int !! 128 prompt "System type"
309 default 5 if PAGE_SIZE_64KB !! 129 default MIPS_GENERIC_KERNEL
310 default 5 if PAGE_SIZE_16KB <<
311 default 4 <<
312 130
313 config ARCH_MMAP_RND_BITS_MIN !! 131 config MIPS_GENERIC_KERNEL
314 default 14 if PAGE_SIZE_64KB !! 132 bool "Generic board-agnostic MIPS kernel"
315 default 16 if PAGE_SIZE_16KB !! 133 select ARCH_HAS_SETUP_DMA_OPS
316 default 18 !! 134 select MIPS_GENERIC
>> 135 select BOOT_RAW
>> 136 select BUILTIN_DTB
>> 137 select CEVT_R4K
>> 138 select CLKSRC_MIPS_GIC
>> 139 select COMMON_CLK
>> 140 select CPU_MIPSR2_IRQ_EI
>> 141 select CPU_MIPSR2_IRQ_VI
>> 142 select CSRC_R4K
>> 143 select DMA_NONCOHERENT
>> 144 select HAVE_PCI
>> 145 select IRQ_MIPS_CPU
>> 146 select MIPS_AUTO_PFN_OFFSET
>> 147 select MIPS_CPU_SCACHE
>> 148 select MIPS_GIC
>> 149 select MIPS_L1_CACHE_SHIFT_7
>> 150 select NO_EXCEPT_FILL
>> 151 select PCI_DRIVERS_GENERIC
>> 152 select SMP_UP if SMP
>> 153 select SWAP_IO_SPACE
>> 154 select SYS_HAS_CPU_MIPS32_R1
>> 155 select SYS_HAS_CPU_MIPS32_R2
>> 156 select SYS_HAS_CPU_MIPS32_R6
>> 157 select SYS_HAS_CPU_MIPS64_R1
>> 158 select SYS_HAS_CPU_MIPS64_R2
>> 159 select SYS_HAS_CPU_MIPS64_R6
>> 160 select SYS_SUPPORTS_32BIT_KERNEL
>> 161 select SYS_SUPPORTS_64BIT_KERNEL
>> 162 select SYS_SUPPORTS_BIG_ENDIAN
>> 163 select SYS_SUPPORTS_HIGHMEM
>> 164 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 165 select SYS_SUPPORTS_MICROMIPS
>> 166 select SYS_SUPPORTS_MIPS16
>> 167 select SYS_SUPPORTS_MIPS_CPS
>> 168 select SYS_SUPPORTS_MULTITHREADING
>> 169 select SYS_SUPPORTS_RELOCATABLE
>> 170 select SYS_SUPPORTS_SMARTMIPS
>> 171 select SYS_SUPPORTS_ZBOOT
>> 172 select UHI_BOOT
>> 173 select USB_EHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
>> 174 select USB_EHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 175 select USB_OHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
>> 176 select USB_OHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 177 select USB_UHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
>> 178 select USB_UHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 179 select USE_OF
>> 180 help
>> 181 Select this to build a kernel which aims to support multiple boards,
>> 182 generally using a flattened device tree passed from the bootloader
>> 183 using the boot protocol defined in the UHI (Unified Hosting
>> 184 Interface) specification.
>> 185
>> 186 config MIPS_ALCHEMY
>> 187 bool "Alchemy processor based machines"
>> 188 select PHYS_ADDR_T_64BIT
>> 189 select CEVT_R4K
>> 190 select CSRC_R4K
>> 191 select IRQ_MIPS_CPU
>> 192 select DMA_NONCOHERENT # Au1000,1500,1100 aren't, rest is
>> 193 select MIPS_FIXUP_BIGPHYS_ADDR if PCI
>> 194 select SYS_HAS_CPU_MIPS32_R1
>> 195 select SYS_SUPPORTS_32BIT_KERNEL
>> 196 select SYS_SUPPORTS_APM_EMULATION
>> 197 select GPIOLIB
>> 198 select SYS_SUPPORTS_ZBOOT
>> 199 select COMMON_CLK
317 200
318 # max bits determined by the following formula !! 201 config AR7
319 # VA_BITS - PAGE_SHIFT - 3 !! 202 bool "Texas Instruments AR7"
320 config ARCH_MMAP_RND_BITS_MAX !! 203 select BOOT_ELF32
321 default 19 if ARM64_VA_BITS=36 !! 204 select COMMON_CLK
322 default 24 if ARM64_VA_BITS=39 !! 205 select DMA_NONCOHERENT
323 default 27 if ARM64_VA_BITS=42 !! 206 select CEVT_R4K
324 default 30 if ARM64_VA_BITS=47 !! 207 select CSRC_R4K
325 default 29 if ARM64_VA_BITS=48 && ARM6 !! 208 select IRQ_MIPS_CPU
326 default 31 if ARM64_VA_BITS=48 && ARM6 !! 209 select NO_EXCEPT_FILL
327 default 33 if ARM64_VA_BITS=48 !! 210 select SWAP_IO_SPACE
328 default 14 if ARM64_64K_PAGES !! 211 select SYS_HAS_CPU_MIPS32_R1
329 default 16 if ARM64_16K_PAGES !! 212 select SYS_HAS_EARLY_PRINTK
330 default 18 !! 213 select SYS_SUPPORTS_32BIT_KERNEL
>> 214 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 215 select SYS_SUPPORTS_MIPS16
>> 216 select SYS_SUPPORTS_ZBOOT_UART16550
>> 217 select GPIOLIB
>> 218 select VLYNQ
>> 219 help
>> 220 Support for the Texas Instruments AR7 System-on-a-Chip
>> 221 family: TNETD7100, 7200 and 7300.
>> 222
>> 223 config ATH25
>> 224 bool "Atheros AR231x/AR531x SoC support"
>> 225 select CEVT_R4K
>> 226 select CSRC_R4K
>> 227 select DMA_NONCOHERENT
>> 228 select IRQ_MIPS_CPU
>> 229 select IRQ_DOMAIN
>> 230 select SYS_HAS_CPU_MIPS32_R1
>> 231 select SYS_SUPPORTS_BIG_ENDIAN
>> 232 select SYS_SUPPORTS_32BIT_KERNEL
>> 233 select SYS_HAS_EARLY_PRINTK
>> 234 help
>> 235 Support for Atheros AR231x and Atheros AR531x based boards
>> 236
>> 237 config ATH79
>> 238 bool "Atheros AR71XX/AR724X/AR913X based boards"
>> 239 select ARCH_HAS_RESET_CONTROLLER
>> 240 select BOOT_RAW
>> 241 select CEVT_R4K
>> 242 select CSRC_R4K
>> 243 select DMA_NONCOHERENT
>> 244 select GPIOLIB
>> 245 select PINCTRL
>> 246 select COMMON_CLK
>> 247 select IRQ_MIPS_CPU
>> 248 select SYS_HAS_CPU_MIPS32_R2
>> 249 select SYS_HAS_EARLY_PRINTK
>> 250 select SYS_SUPPORTS_32BIT_KERNEL
>> 251 select SYS_SUPPORTS_BIG_ENDIAN
>> 252 select SYS_SUPPORTS_MIPS16
>> 253 select SYS_SUPPORTS_ZBOOT_UART_PROM
>> 254 select USE_OF
>> 255 select USB_EHCI_ROOT_HUB_TT if USB_EHCI_HCD_PLATFORM
>> 256 help
>> 257 Support for the Atheros AR71XX/AR724X/AR913X SoCs.
>> 258
>> 259 config BMIPS_GENERIC
>> 260 bool "Broadcom Generic BMIPS kernel"
>> 261 select ARCH_HAS_RESET_CONTROLLER
>> 262 select ARCH_HAS_SYNC_DMA_FOR_CPU_ALL
>> 263 select ARCH_HAS_PHYS_TO_DMA
>> 264 select BOOT_RAW
>> 265 select NO_EXCEPT_FILL
>> 266 select USE_OF
>> 267 select CEVT_R4K
>> 268 select CSRC_R4K
>> 269 select SYNC_R4K
>> 270 select COMMON_CLK
>> 271 select BCM6345_L1_IRQ
>> 272 select BCM7038_L1_IRQ
>> 273 select BCM7120_L2_IRQ
>> 274 select BRCMSTB_L2_IRQ
>> 275 select IRQ_MIPS_CPU
>> 276 select DMA_NONCOHERENT
>> 277 select SYS_SUPPORTS_32BIT_KERNEL
>> 278 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 279 select SYS_SUPPORTS_BIG_ENDIAN
>> 280 select SYS_SUPPORTS_HIGHMEM
>> 281 select SYS_HAS_CPU_BMIPS32_3300
>> 282 select SYS_HAS_CPU_BMIPS4350
>> 283 select SYS_HAS_CPU_BMIPS4380
>> 284 select SYS_HAS_CPU_BMIPS5000
>> 285 select SWAP_IO_SPACE
>> 286 select USB_EHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
>> 287 select USB_EHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 288 select USB_OHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
>> 289 select USB_OHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 290 select HARDIRQS_SW_RESEND
>> 291 help
>> 292 Build a generic DT-based kernel image that boots on select
>> 293 BCM33xx cable modem chips, BCM63xx DSL chips, and BCM7xxx set-top
>> 294 box chips. Note that CONFIG_CPU_BIG_ENDIAN/CONFIG_CPU_LITTLE_ENDIAN
>> 295 must be set appropriately for your board.
>> 296
>> 297 config BCM47XX
>> 298 bool "Broadcom BCM47XX based boards"
>> 299 select BOOT_RAW
>> 300 select CEVT_R4K
>> 301 select CSRC_R4K
>> 302 select DMA_NONCOHERENT
>> 303 select HAVE_PCI
>> 304 select IRQ_MIPS_CPU
>> 305 select SYS_HAS_CPU_MIPS32_R1
>> 306 select NO_EXCEPT_FILL
>> 307 select SYS_SUPPORTS_32BIT_KERNEL
>> 308 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 309 select SYS_SUPPORTS_MIPS16
>> 310 select SYS_SUPPORTS_ZBOOT
>> 311 select SYS_HAS_EARLY_PRINTK
>> 312 select USE_GENERIC_EARLY_PRINTK_8250
>> 313 select GPIOLIB
>> 314 select LEDS_GPIO_REGISTER
>> 315 select BCM47XX_NVRAM
>> 316 select BCM47XX_SPROM
>> 317 select BCM47XX_SSB if !BCM47XX_BCMA
>> 318 help
>> 319 Support for BCM47XX based boards
>> 320
>> 321 config BCM63XX
>> 322 bool "Broadcom BCM63XX based boards"
>> 323 select BOOT_RAW
>> 324 select CEVT_R4K
>> 325 select CSRC_R4K
>> 326 select SYNC_R4K
>> 327 select DMA_NONCOHERENT
>> 328 select IRQ_MIPS_CPU
>> 329 select SYS_SUPPORTS_32BIT_KERNEL
>> 330 select SYS_SUPPORTS_BIG_ENDIAN
>> 331 select SYS_HAS_EARLY_PRINTK
>> 332 select SWAP_IO_SPACE
>> 333 select GPIOLIB
>> 334 select MIPS_L1_CACHE_SHIFT_4
>> 335 select HAVE_LEGACY_CLK
>> 336 help
>> 337 Support for BCM63XX based boards
>> 338
>> 339 config MIPS_COBALT
>> 340 bool "Cobalt Server"
>> 341 select CEVT_R4K
>> 342 select CSRC_R4K
>> 343 select CEVT_GT641XX
>> 344 select DMA_NONCOHERENT
>> 345 select FORCE_PCI
>> 346 select I8253
>> 347 select I8259
>> 348 select IRQ_MIPS_CPU
>> 349 select IRQ_GT641XX
>> 350 select PCI_GT64XXX_PCI0
>> 351 select SYS_HAS_CPU_NEVADA
>> 352 select SYS_HAS_EARLY_PRINTK
>> 353 select SYS_SUPPORTS_32BIT_KERNEL
>> 354 select SYS_SUPPORTS_64BIT_KERNEL
>> 355 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 356 select USE_GENERIC_EARLY_PRINTK_8250
>> 357
>> 358 config MACH_DECSTATION
>> 359 bool "DECstations"
>> 360 select BOOT_ELF32
>> 361 select CEVT_DS1287
>> 362 select CEVT_R4K if CPU_R4X00
>> 363 select CSRC_IOASIC
>> 364 select CSRC_R4K if CPU_R4X00
>> 365 select CPU_DADDI_WORKAROUNDS if 64BIT
>> 366 select CPU_R4000_WORKAROUNDS if 64BIT
>> 367 select CPU_R4400_WORKAROUNDS if 64BIT
>> 368 select DMA_NONCOHERENT
>> 369 select NO_IOPORT_MAP
>> 370 select IRQ_MIPS_CPU
>> 371 select SYS_HAS_CPU_R3000
>> 372 select SYS_HAS_CPU_R4X00
>> 373 select SYS_SUPPORTS_32BIT_KERNEL
>> 374 select SYS_SUPPORTS_64BIT_KERNEL
>> 375 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 376 select SYS_SUPPORTS_128HZ
>> 377 select SYS_SUPPORTS_256HZ
>> 378 select SYS_SUPPORTS_1024HZ
>> 379 select MIPS_L1_CACHE_SHIFT_4
>> 380 help
>> 381 This enables support for DEC's MIPS based workstations. For details
>> 382 see the Linux/MIPS FAQ on <http://www.linux-mips.org/> and the
>> 383 DECstation porting pages on <http://decstation.unix-ag.org/>.
>> 384
>> 385 If you have one of the following DECstation Models you definitely
>> 386 want to choose R4xx0 for the CPU Type:
>> 387
>> 388 DECstation 5000/50
>> 389 DECstation 5000/150
>> 390 DECstation 5000/260
>> 391 DECsystem 5900/260
>> 392
>> 393 otherwise choose R3000.
>> 394
>> 395 config MACH_JAZZ
>> 396 bool "Jazz family of machines"
>> 397 select ARC_MEMORY
>> 398 select ARC_PROMLIB
>> 399 select ARCH_MIGHT_HAVE_PC_PARPORT
>> 400 select ARCH_MIGHT_HAVE_PC_SERIO
>> 401 select DMA_OPS
>> 402 select FW_ARC
>> 403 select FW_ARC32
>> 404 select ARCH_MAY_HAVE_PC_FDC
>> 405 select CEVT_R4K
>> 406 select CSRC_R4K
>> 407 select DEFAULT_SGI_PARTITION if CPU_BIG_ENDIAN
>> 408 select GENERIC_ISA_DMA
>> 409 select HAVE_PCSPKR_PLATFORM
>> 410 select IRQ_MIPS_CPU
>> 411 select I8253
>> 412 select I8259
>> 413 select ISA
>> 414 select SYS_HAS_CPU_R4X00
>> 415 select SYS_SUPPORTS_32BIT_KERNEL
>> 416 select SYS_SUPPORTS_64BIT_KERNEL
>> 417 select SYS_SUPPORTS_100HZ
>> 418 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 419 help
>> 420 This a family of machines based on the MIPS R4030 chipset which was
>> 421 used by several vendors to build RISC/os and Windows NT workstations.
>> 422 Members include the Acer PICA, MIPS Magnum 4000, MIPS Millennium and
>> 423 Olivetti M700-10 workstations.
>> 424
>> 425 config MACH_INGENIC_SOC
>> 426 bool "Ingenic SoC based machines"
>> 427 select MIPS_GENERIC
>> 428 select MACH_INGENIC
>> 429 select SYS_SUPPORTS_ZBOOT_UART16550
>> 430 select CPU_SUPPORTS_CPUFREQ
>> 431 select MIPS_EXTERNAL_TIMER
>> 432
>> 433 config LANTIQ
>> 434 bool "Lantiq based platforms"
>> 435 select DMA_NONCOHERENT
>> 436 select IRQ_MIPS_CPU
>> 437 select CEVT_R4K
>> 438 select CSRC_R4K
>> 439 select SYS_HAS_CPU_MIPS32_R1
>> 440 select SYS_HAS_CPU_MIPS32_R2
>> 441 select SYS_SUPPORTS_BIG_ENDIAN
>> 442 select SYS_SUPPORTS_32BIT_KERNEL
>> 443 select SYS_SUPPORTS_MIPS16
>> 444 select SYS_SUPPORTS_MULTITHREADING
>> 445 select SYS_SUPPORTS_VPE_LOADER
>> 446 select SYS_HAS_EARLY_PRINTK
>> 447 select GPIOLIB
>> 448 select SWAP_IO_SPACE
>> 449 select BOOT_RAW
>> 450 select HAVE_LEGACY_CLK
>> 451 select USE_OF
>> 452 select PINCTRL
>> 453 select PINCTRL_LANTIQ
>> 454 select ARCH_HAS_RESET_CONTROLLER
>> 455 select RESET_CONTROLLER
>> 456
>> 457 config MACH_LOONGSON32
>> 458 bool "Loongson 32-bit family of machines"
>> 459 select SYS_SUPPORTS_ZBOOT
>> 460 help
>> 461 This enables support for the Loongson-1 family of machines.
>> 462
>> 463 Loongson-1 is a family of 32-bit MIPS-compatible SoCs developed by
>> 464 the Institute of Computing Technology (ICT), Chinese Academy of
>> 465 Sciences (CAS).
>> 466
>> 467 config MACH_LOONGSON2EF
>> 468 bool "Loongson-2E/F family of machines"
>> 469 select SYS_SUPPORTS_ZBOOT
>> 470 help
>> 471 This enables the support of early Loongson-2E/F family of machines.
>> 472
>> 473 config MACH_LOONGSON64
>> 474 bool "Loongson 64-bit family of machines"
>> 475 select ARCH_SPARSEMEM_ENABLE
>> 476 select ARCH_MIGHT_HAVE_PC_PARPORT
>> 477 select ARCH_MIGHT_HAVE_PC_SERIO
>> 478 select GENERIC_ISA_DMA_SUPPORT_BROKEN
>> 479 select BOOT_ELF32
>> 480 select BOARD_SCACHE
>> 481 select CSRC_R4K
>> 482 select CEVT_R4K
>> 483 select CPU_HAS_WB
>> 484 select FORCE_PCI
>> 485 select ISA
>> 486 select I8259
>> 487 select IRQ_MIPS_CPU
>> 488 select NO_EXCEPT_FILL
>> 489 select NR_CPUS_DEFAULT_64
>> 490 select USE_GENERIC_EARLY_PRINTK_8250
>> 491 select PCI_DRIVERS_GENERIC
>> 492 select SYS_HAS_CPU_LOONGSON64
>> 493 select SYS_HAS_EARLY_PRINTK
>> 494 select SYS_SUPPORTS_SMP
>> 495 select SYS_SUPPORTS_HOTPLUG_CPU
>> 496 select SYS_SUPPORTS_NUMA
>> 497 select SYS_SUPPORTS_64BIT_KERNEL
>> 498 select SYS_SUPPORTS_HIGHMEM
>> 499 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 500 select SYS_SUPPORTS_ZBOOT
>> 501 select SYS_SUPPORTS_RELOCATABLE
>> 502 select ZONE_DMA32
>> 503 select COMMON_CLK
>> 504 select USE_OF
>> 505 select BUILTIN_DTB
>> 506 select PCI_HOST_GENERIC
>> 507 help
>> 508 This enables the support of Loongson-2/3 family of machines.
>> 509
>> 510 Loongson-2 and Loongson-3 are 64-bit general-purpose processors with
>> 511 GS264/GS464/GS464E/GS464V microarchitecture (except old Loongson-2E
>> 512 and Loongson-2F which will be removed), developed by the Institute
>> 513 of Computing Technology (ICT), Chinese Academy of Sciences (CAS).
>> 514
>> 515 config MACH_PISTACHIO
>> 516 bool "IMG Pistachio SoC based boards"
>> 517 select BOOT_ELF32
>> 518 select BOOT_RAW
>> 519 select CEVT_R4K
>> 520 select CLKSRC_MIPS_GIC
>> 521 select COMMON_CLK
>> 522 select CSRC_R4K
>> 523 select DMA_NONCOHERENT
>> 524 select GPIOLIB
>> 525 select IRQ_MIPS_CPU
>> 526 select MFD_SYSCON
>> 527 select MIPS_CPU_SCACHE
>> 528 select MIPS_GIC
>> 529 select PINCTRL
>> 530 select REGULATOR
>> 531 select SYS_HAS_CPU_MIPS32_R2
>> 532 select SYS_SUPPORTS_32BIT_KERNEL
>> 533 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 534 select SYS_SUPPORTS_MIPS_CPS
>> 535 select SYS_SUPPORTS_MULTITHREADING
>> 536 select SYS_SUPPORTS_RELOCATABLE
>> 537 select SYS_SUPPORTS_ZBOOT
>> 538 select SYS_HAS_EARLY_PRINTK
>> 539 select USE_GENERIC_EARLY_PRINTK_8250
>> 540 select USE_OF
>> 541 help
>> 542 This enables support for the IMG Pistachio SoC platform.
>> 543
>> 544 config MIPS_MALTA
>> 545 bool "MIPS Malta board"
>> 546 select ARCH_MAY_HAVE_PC_FDC
>> 547 select ARCH_MIGHT_HAVE_PC_PARPORT
>> 548 select ARCH_MIGHT_HAVE_PC_SERIO
>> 549 select BOOT_ELF32
>> 550 select BOOT_RAW
>> 551 select BUILTIN_DTB
>> 552 select CEVT_R4K
>> 553 select CLKSRC_MIPS_GIC
>> 554 select COMMON_CLK
>> 555 select CSRC_R4K
>> 556 select DMA_NONCOHERENT
>> 557 select GENERIC_ISA_DMA
>> 558 select HAVE_PCSPKR_PLATFORM
>> 559 select HAVE_PCI
>> 560 select I8253
>> 561 select I8259
>> 562 select IRQ_MIPS_CPU
>> 563 select MIPS_BONITO64
>> 564 select MIPS_CPU_SCACHE
>> 565 select MIPS_GIC
>> 566 select MIPS_L1_CACHE_SHIFT_6
>> 567 select MIPS_MSC
>> 568 select PCI_GT64XXX_PCI0
>> 569 select SMP_UP if SMP
>> 570 select SWAP_IO_SPACE
>> 571 select SYS_HAS_CPU_MIPS32_R1
>> 572 select SYS_HAS_CPU_MIPS32_R2
>> 573 select SYS_HAS_CPU_MIPS32_R3_5
>> 574 select SYS_HAS_CPU_MIPS32_R5
>> 575 select SYS_HAS_CPU_MIPS32_R6
>> 576 select SYS_HAS_CPU_MIPS64_R1
>> 577 select SYS_HAS_CPU_MIPS64_R2
>> 578 select SYS_HAS_CPU_MIPS64_R6
>> 579 select SYS_HAS_CPU_NEVADA
>> 580 select SYS_HAS_CPU_RM7000
>> 581 select SYS_SUPPORTS_32BIT_KERNEL
>> 582 select SYS_SUPPORTS_64BIT_KERNEL
>> 583 select SYS_SUPPORTS_BIG_ENDIAN
>> 584 select SYS_SUPPORTS_HIGHMEM
>> 585 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 586 select SYS_SUPPORTS_MICROMIPS
>> 587 select SYS_SUPPORTS_MIPS16
>> 588 select SYS_SUPPORTS_MIPS_CMP
>> 589 select SYS_SUPPORTS_MIPS_CPS
>> 590 select SYS_SUPPORTS_MULTITHREADING
>> 591 select SYS_SUPPORTS_RELOCATABLE
>> 592 select SYS_SUPPORTS_SMARTMIPS
>> 593 select SYS_SUPPORTS_VPE_LOADER
>> 594 select SYS_SUPPORTS_ZBOOT
>> 595 select USE_OF
>> 596 select WAR_ICACHE_REFILLS
>> 597 select ZONE_DMA32 if 64BIT
>> 598 help
>> 599 This enables support for the MIPS Technologies Malta evaluation
>> 600 board.
>> 601
>> 602 config MACH_PIC32
>> 603 bool "Microchip PIC32 Family"
>> 604 help
>> 605 This enables support for the Microchip PIC32 family of platforms.
>> 606
>> 607 Microchip PIC32 is a family of general-purpose 32 bit MIPS core
>> 608 microcontrollers.
>> 609
>> 610 config MACH_VR41XX
>> 611 bool "NEC VR4100 series based machines"
>> 612 select CEVT_R4K
>> 613 select CSRC_R4K
>> 614 select SYS_HAS_CPU_VR41XX
>> 615 select SYS_SUPPORTS_MIPS16
>> 616 select GPIOLIB
>> 617
>> 618 config MACH_NINTENDO64
>> 619 bool "Nintendo 64 console"
>> 620 select CEVT_R4K
>> 621 select CSRC_R4K
>> 622 select SYS_HAS_CPU_R4300
>> 623 select SYS_SUPPORTS_BIG_ENDIAN
>> 624 select SYS_SUPPORTS_ZBOOT
>> 625 select SYS_SUPPORTS_32BIT_KERNEL
>> 626 select SYS_SUPPORTS_64BIT_KERNEL
>> 627 select DMA_NONCOHERENT
>> 628 select IRQ_MIPS_CPU
>> 629
>> 630 config RALINK
>> 631 bool "Ralink based machines"
>> 632 select CEVT_R4K
>> 633 select COMMON_CLK
>> 634 select CSRC_R4K
>> 635 select BOOT_RAW
>> 636 select DMA_NONCOHERENT
>> 637 select IRQ_MIPS_CPU
>> 638 select USE_OF
>> 639 select SYS_HAS_CPU_MIPS32_R1
>> 640 select SYS_HAS_CPU_MIPS32_R2
>> 641 select SYS_SUPPORTS_32BIT_KERNEL
>> 642 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 643 select SYS_SUPPORTS_MIPS16
>> 644 select SYS_SUPPORTS_ZBOOT
>> 645 select SYS_HAS_EARLY_PRINTK
>> 646 select ARCH_HAS_RESET_CONTROLLER
>> 647 select RESET_CONTROLLER
>> 648
>> 649 config MACH_REALTEK_RTL
>> 650 bool "Realtek RTL838x/RTL839x based machines"
>> 651 select MIPS_GENERIC
>> 652 select DMA_NONCOHERENT
>> 653 select IRQ_MIPS_CPU
>> 654 select CSRC_R4K
>> 655 select CEVT_R4K
>> 656 select SYS_HAS_CPU_MIPS32_R1
>> 657 select SYS_HAS_CPU_MIPS32_R2
>> 658 select SYS_SUPPORTS_BIG_ENDIAN
>> 659 select SYS_SUPPORTS_32BIT_KERNEL
>> 660 select SYS_SUPPORTS_MIPS16
>> 661 select SYS_SUPPORTS_MULTITHREADING
>> 662 select SYS_SUPPORTS_VPE_LOADER
>> 663 select SYS_HAS_EARLY_PRINTK
>> 664 select SYS_HAS_EARLY_PRINTK_8250
>> 665 select USE_GENERIC_EARLY_PRINTK_8250
>> 666 select BOOT_RAW
>> 667 select PINCTRL
>> 668 select USE_OF
>> 669
>> 670 config SGI_IP22
>> 671 bool "SGI IP22 (Indy/Indigo2)"
>> 672 select ARC_MEMORY
>> 673 select ARC_PROMLIB
>> 674 select FW_ARC
>> 675 select FW_ARC32
>> 676 select ARCH_MIGHT_HAVE_PC_SERIO
>> 677 select BOOT_ELF32
>> 678 select CEVT_R4K
>> 679 select CSRC_R4K
>> 680 select DEFAULT_SGI_PARTITION
>> 681 select DMA_NONCOHERENT
>> 682 select HAVE_EISA
>> 683 select I8253
>> 684 select I8259
>> 685 select IP22_CPU_SCACHE
>> 686 select IRQ_MIPS_CPU
>> 687 select GENERIC_ISA_DMA_SUPPORT_BROKEN
>> 688 select SGI_HAS_I8042
>> 689 select SGI_HAS_INDYDOG
>> 690 select SGI_HAS_HAL2
>> 691 select SGI_HAS_SEEQ
>> 692 select SGI_HAS_WD93
>> 693 select SGI_HAS_ZILOG
>> 694 select SWAP_IO_SPACE
>> 695 select SYS_HAS_CPU_R4X00
>> 696 select SYS_HAS_CPU_R5000
>> 697 select SYS_HAS_EARLY_PRINTK
>> 698 select SYS_SUPPORTS_32BIT_KERNEL
>> 699 select SYS_SUPPORTS_64BIT_KERNEL
>> 700 select SYS_SUPPORTS_BIG_ENDIAN
>> 701 select WAR_R4600_V1_INDEX_ICACHEOP
>> 702 select WAR_R4600_V1_HIT_CACHEOP
>> 703 select WAR_R4600_V2_HIT_CACHEOP
>> 704 select MIPS_L1_CACHE_SHIFT_7
>> 705 help
>> 706 This are the SGI Indy, Challenge S and Indigo2, as well as certain
>> 707 OEM variants like the Tandem CMN B006S. To compile a Linux kernel
>> 708 that runs on these, say Y here.
>> 709
>> 710 config SGI_IP27
>> 711 bool "SGI IP27 (Origin200/2000)"
>> 712 select ARCH_HAS_PHYS_TO_DMA
>> 713 select ARCH_SPARSEMEM_ENABLE
>> 714 select FW_ARC
>> 715 select FW_ARC64
>> 716 select ARC_CMDLINE_ONLY
>> 717 select BOOT_ELF64
>> 718 select DEFAULT_SGI_PARTITION
>> 719 select FORCE_PCI
>> 720 select SYS_HAS_EARLY_PRINTK
>> 721 select HAVE_PCI
>> 722 select IRQ_MIPS_CPU
>> 723 select IRQ_DOMAIN_HIERARCHY
>> 724 select NR_CPUS_DEFAULT_64
>> 725 select PCI_DRIVERS_GENERIC
>> 726 select PCI_XTALK_BRIDGE
>> 727 select SYS_HAS_CPU_R10000
>> 728 select SYS_SUPPORTS_64BIT_KERNEL
>> 729 select SYS_SUPPORTS_BIG_ENDIAN
>> 730 select SYS_SUPPORTS_NUMA
>> 731 select SYS_SUPPORTS_SMP
>> 732 select WAR_R10000_LLSC
>> 733 select MIPS_L1_CACHE_SHIFT_7
>> 734 select NUMA
>> 735 help
>> 736 This are the SGI Origin 200, Origin 2000 and Onyx 2 Graphics
>> 737 workstations. To compile a Linux kernel that runs on these, say Y
>> 738 here.
>> 739
>> 740 config SGI_IP28
>> 741 bool "SGI IP28 (Indigo2 R10k)"
>> 742 select ARC_MEMORY
>> 743 select ARC_PROMLIB
>> 744 select FW_ARC
>> 745 select FW_ARC64
>> 746 select ARCH_MIGHT_HAVE_PC_SERIO
>> 747 select BOOT_ELF64
>> 748 select CEVT_R4K
>> 749 select CSRC_R4K
>> 750 select DEFAULT_SGI_PARTITION
>> 751 select DMA_NONCOHERENT
>> 752 select GENERIC_ISA_DMA_SUPPORT_BROKEN
>> 753 select IRQ_MIPS_CPU
>> 754 select HAVE_EISA
>> 755 select I8253
>> 756 select I8259
>> 757 select SGI_HAS_I8042
>> 758 select SGI_HAS_INDYDOG
>> 759 select SGI_HAS_HAL2
>> 760 select SGI_HAS_SEEQ
>> 761 select SGI_HAS_WD93
>> 762 select SGI_HAS_ZILOG
>> 763 select SWAP_IO_SPACE
>> 764 select SYS_HAS_CPU_R10000
>> 765 select SYS_HAS_EARLY_PRINTK
>> 766 select SYS_SUPPORTS_64BIT_KERNEL
>> 767 select SYS_SUPPORTS_BIG_ENDIAN
>> 768 select WAR_R10000_LLSC
>> 769 select MIPS_L1_CACHE_SHIFT_7
>> 770 help
>> 771 This is the SGI Indigo2 with R10000 processor. To compile a Linux
>> 772 kernel that runs on these, say Y here.
>> 773
>> 774 config SGI_IP30
>> 775 bool "SGI IP30 (Octane/Octane2)"
>> 776 select ARCH_HAS_PHYS_TO_DMA
>> 777 select FW_ARC
>> 778 select FW_ARC64
>> 779 select BOOT_ELF64
>> 780 select CEVT_R4K
>> 781 select CSRC_R4K
>> 782 select FORCE_PCI
>> 783 select SYNC_R4K if SMP
>> 784 select ZONE_DMA32
>> 785 select HAVE_PCI
>> 786 select IRQ_MIPS_CPU
>> 787 select IRQ_DOMAIN_HIERARCHY
>> 788 select NR_CPUS_DEFAULT_2
>> 789 select PCI_DRIVERS_GENERIC
>> 790 select PCI_XTALK_BRIDGE
>> 791 select SYS_HAS_EARLY_PRINTK
>> 792 select SYS_HAS_CPU_R10000
>> 793 select SYS_SUPPORTS_64BIT_KERNEL
>> 794 select SYS_SUPPORTS_BIG_ENDIAN
>> 795 select SYS_SUPPORTS_SMP
>> 796 select WAR_R10000_LLSC
>> 797 select MIPS_L1_CACHE_SHIFT_7
>> 798 select ARC_MEMORY
>> 799 help
>> 800 These are the SGI Octane and Octane2 graphics workstations. To
>> 801 compile a Linux kernel that runs on these, say Y here.
>> 802
>> 803 config SGI_IP32
>> 804 bool "SGI IP32 (O2)"
>> 805 select ARC_MEMORY
>> 806 select ARC_PROMLIB
>> 807 select ARCH_HAS_PHYS_TO_DMA
>> 808 select FW_ARC
>> 809 select FW_ARC32
>> 810 select BOOT_ELF32
>> 811 select CEVT_R4K
>> 812 select CSRC_R4K
>> 813 select DMA_NONCOHERENT
>> 814 select HAVE_PCI
>> 815 select IRQ_MIPS_CPU
>> 816 select R5000_CPU_SCACHE
>> 817 select RM7000_CPU_SCACHE
>> 818 select SYS_HAS_CPU_R5000
>> 819 select SYS_HAS_CPU_R10000 if BROKEN
>> 820 select SYS_HAS_CPU_RM7000
>> 821 select SYS_HAS_CPU_NEVADA
>> 822 select SYS_SUPPORTS_64BIT_KERNEL
>> 823 select SYS_SUPPORTS_BIG_ENDIAN
>> 824 select WAR_ICACHE_REFILLS
>> 825 help
>> 826 If you want this kernel to run on SGI O2 workstation, say Y here.
>> 827
>> 828 config SIBYTE_CRHINE
>> 829 bool "Sibyte BCM91120C-CRhine"
>> 830 select BOOT_ELF32
>> 831 select SIBYTE_BCM1120
>> 832 select SWAP_IO_SPACE
>> 833 select SYS_HAS_CPU_SB1
>> 834 select SYS_SUPPORTS_BIG_ENDIAN
>> 835 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 836
>> 837 config SIBYTE_CARMEL
>> 838 bool "Sibyte BCM91120x-Carmel"
>> 839 select BOOT_ELF32
>> 840 select SIBYTE_BCM1120
>> 841 select SWAP_IO_SPACE
>> 842 select SYS_HAS_CPU_SB1
>> 843 select SYS_SUPPORTS_BIG_ENDIAN
>> 844 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 845
>> 846 config SIBYTE_CRHONE
>> 847 bool "Sibyte BCM91125C-CRhone"
>> 848 select BOOT_ELF32
>> 849 select SIBYTE_BCM1125
>> 850 select SWAP_IO_SPACE
>> 851 select SYS_HAS_CPU_SB1
>> 852 select SYS_SUPPORTS_BIG_ENDIAN
>> 853 select SYS_SUPPORTS_HIGHMEM
>> 854 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 855
>> 856 config SIBYTE_RHONE
>> 857 bool "Sibyte BCM91125E-Rhone"
>> 858 select BOOT_ELF32
>> 859 select SIBYTE_BCM1125H
>> 860 select SWAP_IO_SPACE
>> 861 select SYS_HAS_CPU_SB1
>> 862 select SYS_SUPPORTS_BIG_ENDIAN
>> 863 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 864
>> 865 config SIBYTE_SWARM
>> 866 bool "Sibyte BCM91250A-SWARM"
>> 867 select BOOT_ELF32
>> 868 select HAVE_PATA_PLATFORM
>> 869 select SIBYTE_SB1250
>> 870 select SWAP_IO_SPACE
>> 871 select SYS_HAS_CPU_SB1
>> 872 select SYS_SUPPORTS_BIG_ENDIAN
>> 873 select SYS_SUPPORTS_HIGHMEM
>> 874 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 875 select ZONE_DMA32 if 64BIT
>> 876 select SWIOTLB if ARCH_DMA_ADDR_T_64BIT && PCI
>> 877
>> 878 config SIBYTE_LITTLESUR
>> 879 bool "Sibyte BCM91250C2-LittleSur"
>> 880 select BOOT_ELF32
>> 881 select HAVE_PATA_PLATFORM
>> 882 select SIBYTE_SB1250
>> 883 select SWAP_IO_SPACE
>> 884 select SYS_HAS_CPU_SB1
>> 885 select SYS_SUPPORTS_BIG_ENDIAN
>> 886 select SYS_SUPPORTS_HIGHMEM
>> 887 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 888 select ZONE_DMA32 if 64BIT
>> 889
>> 890 config SIBYTE_SENTOSA
>> 891 bool "Sibyte BCM91250E-Sentosa"
>> 892 select BOOT_ELF32
>> 893 select SIBYTE_SB1250
>> 894 select SWAP_IO_SPACE
>> 895 select SYS_HAS_CPU_SB1
>> 896 select SYS_SUPPORTS_BIG_ENDIAN
>> 897 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 898 select SWIOTLB if ARCH_DMA_ADDR_T_64BIT && PCI
>> 899
>> 900 config SIBYTE_BIGSUR
>> 901 bool "Sibyte BCM91480B-BigSur"
>> 902 select BOOT_ELF32
>> 903 select NR_CPUS_DEFAULT_4
>> 904 select SIBYTE_BCM1x80
>> 905 select SWAP_IO_SPACE
>> 906 select SYS_HAS_CPU_SB1
>> 907 select SYS_SUPPORTS_BIG_ENDIAN
>> 908 select SYS_SUPPORTS_HIGHMEM
>> 909 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 910 select ZONE_DMA32 if 64BIT
>> 911 select SWIOTLB if ARCH_DMA_ADDR_T_64BIT && PCI
>> 912
>> 913 config SNI_RM
>> 914 bool "SNI RM200/300/400"
>> 915 select ARC_MEMORY
>> 916 select ARC_PROMLIB
>> 917 select FW_ARC if CPU_LITTLE_ENDIAN
>> 918 select FW_ARC32 if CPU_LITTLE_ENDIAN
>> 919 select FW_SNIPROM if CPU_BIG_ENDIAN
>> 920 select ARCH_MAY_HAVE_PC_FDC
>> 921 select ARCH_MIGHT_HAVE_PC_PARPORT
>> 922 select ARCH_MIGHT_HAVE_PC_SERIO
>> 923 select BOOT_ELF32
>> 924 select CEVT_R4K
>> 925 select CSRC_R4K
>> 926 select DEFAULT_SGI_PARTITION if CPU_BIG_ENDIAN
>> 927 select DMA_NONCOHERENT
>> 928 select GENERIC_ISA_DMA
>> 929 select HAVE_EISA
>> 930 select HAVE_PCSPKR_PLATFORM
>> 931 select HAVE_PCI
>> 932 select IRQ_MIPS_CPU
>> 933 select I8253
>> 934 select I8259
>> 935 select ISA
>> 936 select MIPS_L1_CACHE_SHIFT_6
>> 937 select SWAP_IO_SPACE if CPU_BIG_ENDIAN
>> 938 select SYS_HAS_CPU_R4X00
>> 939 select SYS_HAS_CPU_R5000
>> 940 select SYS_HAS_CPU_R10000
>> 941 select R5000_CPU_SCACHE
>> 942 select SYS_HAS_EARLY_PRINTK
>> 943 select SYS_SUPPORTS_32BIT_KERNEL
>> 944 select SYS_SUPPORTS_64BIT_KERNEL
>> 945 select SYS_SUPPORTS_BIG_ENDIAN
>> 946 select SYS_SUPPORTS_HIGHMEM
>> 947 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 948 select WAR_R4600_V2_HIT_CACHEOP
>> 949 help
>> 950 The SNI RM200/300/400 are MIPS-based machines manufactured by
>> 951 Siemens Nixdorf Informationssysteme (SNI), parent company of Pyramid
>> 952 Technology and now in turn merged with Fujitsu. Say Y here to
>> 953 support this machine type.
>> 954
>> 955 config MACH_TX39XX
>> 956 bool "Toshiba TX39 series based machines"
>> 957
>> 958 config MACH_TX49XX
>> 959 bool "Toshiba TX49 series based machines"
>> 960 select WAR_TX49XX_ICACHE_INDEX_INV
>> 961
>> 962 config MIKROTIK_RB532
>> 963 bool "Mikrotik RB532 boards"
>> 964 select CEVT_R4K
>> 965 select CSRC_R4K
>> 966 select DMA_NONCOHERENT
>> 967 select HAVE_PCI
>> 968 select IRQ_MIPS_CPU
>> 969 select SYS_HAS_CPU_MIPS32_R1
>> 970 select SYS_SUPPORTS_32BIT_KERNEL
>> 971 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 972 select SWAP_IO_SPACE
>> 973 select BOOT_RAW
>> 974 select GPIOLIB
>> 975 select MIPS_L1_CACHE_SHIFT_4
>> 976 help
>> 977 Support the Mikrotik(tm) RouterBoard 532 series,
>> 978 based on the IDT RC32434 SoC.
>> 979
>> 980 config CAVIUM_OCTEON_SOC
>> 981 bool "Cavium Networks Octeon SoC based boards"
>> 982 select CEVT_R4K
>> 983 select ARCH_HAS_PHYS_TO_DMA
>> 984 select HAVE_RAPIDIO
>> 985 select PHYS_ADDR_T_64BIT
>> 986 select SYS_SUPPORTS_64BIT_KERNEL
>> 987 select SYS_SUPPORTS_BIG_ENDIAN
>> 988 select EDAC_SUPPORT
>> 989 select EDAC_ATOMIC_SCRUB
>> 990 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 991 select SYS_SUPPORTS_HOTPLUG_CPU if CPU_BIG_ENDIAN
>> 992 select SYS_HAS_EARLY_PRINTK
>> 993 select SYS_HAS_CPU_CAVIUM_OCTEON
>> 994 select HAVE_PCI
>> 995 select HAVE_PLAT_DELAY
>> 996 select HAVE_PLAT_FW_INIT_CMDLINE
>> 997 select HAVE_PLAT_MEMCPY
>> 998 select ZONE_DMA32
>> 999 select GPIOLIB
>> 1000 select USE_OF
>> 1001 select ARCH_SPARSEMEM_ENABLE
>> 1002 select SYS_SUPPORTS_SMP
>> 1003 select NR_CPUS_DEFAULT_64
>> 1004 select MIPS_NR_CPU_NR_MAP_1024
>> 1005 select BUILTIN_DTB
>> 1006 select MTD
>> 1007 select MTD_COMPLEX_MAPPINGS
>> 1008 select SWIOTLB
>> 1009 select SYS_SUPPORTS_RELOCATABLE
>> 1010 help
>> 1011 This option supports all of the Octeon reference boards from Cavium
>> 1012 Networks. It builds a kernel that dynamically determines the Octeon
>> 1013 CPU type and supports all known board reference implementations.
>> 1014 Some of the supported boards are:
>> 1015 EBT3000
>> 1016 EBH3000
>> 1017 EBH3100
>> 1018 Thunder
>> 1019 Kodama
>> 1020 Hikari
>> 1021 Say Y here for most Octeon reference boards.
>> 1022
>> 1023 config NLM_XLR_BOARD
>> 1024 bool "Netlogic XLR/XLS based systems"
>> 1025 select BOOT_ELF32
>> 1026 select NLM_COMMON
>> 1027 select SYS_HAS_CPU_XLR
>> 1028 select SYS_SUPPORTS_SMP
>> 1029 select HAVE_PCI
>> 1030 select SWAP_IO_SPACE
>> 1031 select SYS_SUPPORTS_32BIT_KERNEL
>> 1032 select SYS_SUPPORTS_64BIT_KERNEL
>> 1033 select PHYS_ADDR_T_64BIT
>> 1034 select SYS_SUPPORTS_BIG_ENDIAN
>> 1035 select SYS_SUPPORTS_HIGHMEM
>> 1036 select NR_CPUS_DEFAULT_32
>> 1037 select CEVT_R4K
>> 1038 select CSRC_R4K
>> 1039 select IRQ_MIPS_CPU
>> 1040 select ZONE_DMA32 if 64BIT
>> 1041 select SYNC_R4K
>> 1042 select SYS_HAS_EARLY_PRINTK
>> 1043 select SYS_SUPPORTS_ZBOOT
>> 1044 select SYS_SUPPORTS_ZBOOT_UART16550
>> 1045 help
>> 1046 Support for systems based on Netlogic XLR and XLS processors.
>> 1047 Say Y here if you have a XLR or XLS based board.
>> 1048
>> 1049 config NLM_XLP_BOARD
>> 1050 bool "Netlogic XLP based systems"
>> 1051 select BOOT_ELF32
>> 1052 select NLM_COMMON
>> 1053 select SYS_HAS_CPU_XLP
>> 1054 select SYS_SUPPORTS_SMP
>> 1055 select HAVE_PCI
>> 1056 select SYS_SUPPORTS_32BIT_KERNEL
>> 1057 select SYS_SUPPORTS_64BIT_KERNEL
>> 1058 select PHYS_ADDR_T_64BIT
>> 1059 select GPIOLIB
>> 1060 select SYS_SUPPORTS_BIG_ENDIAN
>> 1061 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 1062 select SYS_SUPPORTS_HIGHMEM
>> 1063 select NR_CPUS_DEFAULT_32
>> 1064 select CEVT_R4K
>> 1065 select CSRC_R4K
>> 1066 select IRQ_MIPS_CPU
>> 1067 select ZONE_DMA32 if 64BIT
>> 1068 select SYNC_R4K
>> 1069 select SYS_HAS_EARLY_PRINTK
>> 1070 select USE_OF
>> 1071 select SYS_SUPPORTS_ZBOOT
>> 1072 select SYS_SUPPORTS_ZBOOT_UART16550
>> 1073 help
>> 1074 This board is based on Netlogic XLP Processor.
>> 1075 Say Y here if you have a XLP based board.
331 1076
332 config ARCH_MMAP_RND_COMPAT_BITS_MIN !! 1077 endchoice
333 default 7 if ARM64_64K_PAGES <<
334 default 9 if ARM64_16K_PAGES <<
335 default 11 <<
336 1078
337 config ARCH_MMAP_RND_COMPAT_BITS_MAX !! 1079 source "arch/mips/alchemy/Kconfig"
338 default 16 !! 1080 source "arch/mips/ath25/Kconfig"
>> 1081 source "arch/mips/ath79/Kconfig"
>> 1082 source "arch/mips/bcm47xx/Kconfig"
>> 1083 source "arch/mips/bcm63xx/Kconfig"
>> 1084 source "arch/mips/bmips/Kconfig"
>> 1085 source "arch/mips/generic/Kconfig"
>> 1086 source "arch/mips/ingenic/Kconfig"
>> 1087 source "arch/mips/jazz/Kconfig"
>> 1088 source "arch/mips/lantiq/Kconfig"
>> 1089 source "arch/mips/pic32/Kconfig"
>> 1090 source "arch/mips/pistachio/Kconfig"
>> 1091 source "arch/mips/ralink/Kconfig"
>> 1092 source "arch/mips/sgi-ip27/Kconfig"
>> 1093 source "arch/mips/sibyte/Kconfig"
>> 1094 source "arch/mips/txx9/Kconfig"
>> 1095 source "arch/mips/vr41xx/Kconfig"
>> 1096 source "arch/mips/cavium-octeon/Kconfig"
>> 1097 source "arch/mips/loongson2ef/Kconfig"
>> 1098 source "arch/mips/loongson32/Kconfig"
>> 1099 source "arch/mips/loongson64/Kconfig"
>> 1100 source "arch/mips/netlogic/Kconfig"
339 1101
340 config NO_IOPORT_MAP !! 1102 endmenu
341 def_bool y if !PCI <<
342 1103
343 config STACKTRACE_SUPPORT !! 1104 config GENERIC_HWEIGHT
344 def_bool y !! 1105 bool
>> 1106 default y
345 1107
346 config ILLEGAL_POINTER_VALUE !! 1108 config GENERIC_CALIBRATE_DELAY
347 hex !! 1109 bool
348 default 0xdead000000000000 !! 1110 default y
349 1111
350 config LOCKDEP_SUPPORT !! 1112 config SCHED_OMIT_FRAME_POINTER
351 def_bool y !! 1113 bool
>> 1114 default y
352 1115
353 config GENERIC_BUG !! 1116 #
354 def_bool y !! 1117 # Select some configuration options automatically based on user selections.
355 depends on BUG !! 1118 #
>> 1119 config FW_ARC
>> 1120 bool
356 1121
357 config GENERIC_BUG_RELATIVE_POINTERS !! 1122 config ARCH_MAY_HAVE_PC_FDC
358 def_bool y !! 1123 bool
359 depends on GENERIC_BUG <<
360 1124
361 config GENERIC_HWEIGHT !! 1125 config BOOT_RAW
362 def_bool y !! 1126 bool
363 1127
364 config GENERIC_CSUM !! 1128 config CEVT_BCM1480
365 def_bool y !! 1129 bool
366 1130
367 config GENERIC_CALIBRATE_DELAY !! 1131 config CEVT_DS1287
368 def_bool y !! 1132 bool
369 1133
370 config SMP !! 1134 config CEVT_GT641XX
371 def_bool y !! 1135 bool
372 1136
373 config KERNEL_MODE_NEON !! 1137 config CEVT_R4K
374 def_bool y !! 1138 bool
375 1139
376 config FIX_EARLYCON_MEM !! 1140 config CEVT_SB1250
377 def_bool y !! 1141 bool
378 1142
379 config PGTABLE_LEVELS !! 1143 config CEVT_TXX9
380 int !! 1144 bool
381 default 2 if ARM64_16K_PAGES && ARM64_ <<
382 default 2 if ARM64_64K_PAGES && ARM64_ <<
383 default 3 if ARM64_64K_PAGES && (ARM64 <<
384 default 3 if ARM64_4K_PAGES && ARM64_V <<
385 default 3 if ARM64_16K_PAGES && ARM64_ <<
386 default 4 if ARM64_16K_PAGES && (ARM64 <<
387 default 4 if !ARM64_64K_PAGES && ARM64 <<
388 default 5 if ARM64_4K_PAGES && ARM64_V <<
389 1145
390 config ARCH_SUPPORTS_UPROBES !! 1146 config CSRC_BCM1480
391 def_bool y !! 1147 bool
392 1148
393 config ARCH_PROC_KCORE_TEXT !! 1149 config CSRC_IOASIC
394 def_bool y !! 1150 bool
395 1151
396 config BROKEN_GAS_INST !! 1152 config CSRC_R4K
397 def_bool !$(as-instr,1:\n.inst 0\n.rep !! 1153 select CLOCKSOURCE_WATCHDOG if CPU_FREQ
>> 1154 bool
398 1155
399 config BUILTIN_RETURN_ADDRESS_STRIPS_PAC !! 1156 config CSRC_SB1250
400 bool 1157 bool
401 # Clang's __builtin_return_address() s <<
402 # https://github.com/llvm/llvm-project <<
403 default y if CC_IS_CLANG <<
404 # GCC's __builtin_return_address() str <<
405 # and this was backported to 10.2.0, 9 <<
406 # https://gcc.gnu.org/bugzilla/show_bu <<
407 default y if CC_IS_GCC && (GCC_VERSION <<
408 default y if CC_IS_GCC && (GCC_VERSION <<
409 default y if CC_IS_GCC && (GCC_VERSION <<
410 default y if CC_IS_GCC && (GCC_VERSION <<
411 default n <<
412 1158
413 config KASAN_SHADOW_OFFSET !! 1159 config MIPS_CLOCK_VSYSCALL
414 hex !! 1160 def_bool CSRC_R4K || CLKSRC_MIPS_GIC
415 depends on KASAN_GENERIC || KASAN_SW_T !! 1161
416 default 0xdfff800000000000 if (ARM64_V !! 1162 config GPIO_TXX9
417 default 0xdfffc00000000000 if (ARM64_V !! 1163 select GPIOLIB
418 default 0xdffffe0000000000 if ARM64_VA <<
419 default 0xdfffffc000000000 if ARM64_VA <<
420 default 0xdffffff800000000 if ARM64_VA <<
421 default 0xefff800000000000 if (ARM64_V <<
422 default 0xefffc00000000000 if (ARM64_V <<
423 default 0xeffffe0000000000 if ARM64_VA <<
424 default 0xefffffc000000000 if ARM64_VA <<
425 default 0xeffffff800000000 if ARM64_VA <<
426 default 0xffffffffffffffff <<
427 <<
428 config UNWIND_TABLES <<
429 bool 1164 bool
430 1165
431 source "arch/arm64/Kconfig.platforms" !! 1166 config FW_CFE
>> 1167 bool
432 1168
433 menu "Kernel Features" !! 1169 config ARCH_SUPPORTS_UPROBES
>> 1170 bool
434 1171
435 menu "ARM errata workarounds via the alternati !! 1172 config DMA_PERDEV_COHERENT
>> 1173 bool
>> 1174 select ARCH_HAS_SETUP_DMA_OPS
>> 1175 select DMA_NONCOHERENT
436 1176
437 config AMPERE_ERRATUM_AC03_CPU_38 !! 1177 config DMA_NONCOHERENT
438 bool "AmpereOne: AC03_CPU_38: Certain !! 1178 bool
439 default y !! 1179 #
440 help !! 1180 # MIPS allows mixing "slightly different" Cacheability and Coherency
441 This option adds an alternative code !! 1181 # Attribute bits. It is believed that the uncached access through
442 errata AC03_CPU_38 and AC04_CPU_10 o !! 1182 # KSEG1 and the implementation specific "uncached accelerated" used
>> 1183 # by pgprot_writcombine can be mixed, and the latter sometimes provides
>> 1184 # significant advantages.
>> 1185 #
>> 1186 select ARCH_HAS_DMA_WRITE_COMBINE
>> 1187 select ARCH_HAS_DMA_PREP_COHERENT
>> 1188 select ARCH_HAS_SYNC_DMA_FOR_DEVICE
>> 1189 select ARCH_HAS_DMA_SET_UNCACHED
>> 1190 select DMA_NONCOHERENT_MMAP
>> 1191 select NEED_DMA_MAP_STATE
443 1192
444 The affected design reports FEAT_HAF !! 1193 config SYS_HAS_EARLY_PRINTK
445 ID_AA64MMFR1_EL1.HAFDBS, but (V)TCR_ !! 1194 bool
446 as required by the architecture. The <<
447 implementation suffers from an addit <<
448 A/D updates can occur after a PTE ha <<
449 <<
450 The workaround forces KVM to explici <<
451 which avoids enabling unadvertised h <<
452 at stage-2. <<
453 1195
454 If unsure, say Y. !! 1196 config SYS_SUPPORTS_HOTPLUG_CPU
>> 1197 bool
455 1198
456 config ARM64_WORKAROUND_CLEAN_CACHE !! 1199 config MIPS_BONITO64
457 bool 1200 bool
458 1201
459 config ARM64_ERRATUM_826319 !! 1202 config MIPS_MSC
460 bool "Cortex-A53: 826319: System might !! 1203 bool
461 default y <<
462 select ARM64_WORKAROUND_CLEAN_CACHE <<
463 help <<
464 This option adds an alternative code <<
465 erratum 826319 on Cortex-A53 parts u <<
466 AXI master interface and an L2 cache <<
467 <<
468 If a Cortex-A53 uses an AMBA AXI4 AC <<
469 and is unable to accept a certain wr <<
470 not progress on read data presented <<
471 system can deadlock. <<
472 <<
473 The workaround promotes data cache c <<
474 data cache clean-and-invalidate. <<
475 Please note that this does not neces <<
476 as it depends on the alternative fra <<
477 the kernel if an affected CPU is det <<
478 1204
479 If unsure, say Y. !! 1205 config SYNC_R4K
>> 1206 bool
480 1207
481 config ARM64_ERRATUM_827319 !! 1208 config NO_IOPORT_MAP
482 bool "Cortex-A53: 827319: Data cache c !! 1209 def_bool n
483 default y <<
484 select ARM64_WORKAROUND_CLEAN_CACHE <<
485 help <<
486 This option adds an alternative code <<
487 erratum 827319 on Cortex-A53 parts u <<
488 master interface and an L2 cache. <<
489 <<
490 Under certain conditions this erratu <<
491 to occur at the same time as another <<
492 on the AMBA 5 CHI interface, which c <<
493 interconnect reorders the two transa <<
494 <<
495 The workaround promotes data cache c <<
496 data cache clean-and-invalidate. <<
497 Please note that this does not neces <<
498 as it depends on the alternative fra <<
499 the kernel if an affected CPU is det <<
500 1210
501 If unsure, say Y. !! 1211 config GENERIC_CSUM
>> 1212 def_bool CPU_NO_LOAD_STORE_LR
502 1213
503 config ARM64_ERRATUM_824069 !! 1214 config GENERIC_ISA_DMA
504 bool "Cortex-A53: 824069: Cache line m !! 1215 bool
505 default y !! 1216 select ZONE_DMA if GENERIC_ISA_DMA_SUPPORT_BROKEN=n
506 select ARM64_WORKAROUND_CLEAN_CACHE !! 1217 select ISA_DMA_API
507 help <<
508 This option adds an alternative code <<
509 erratum 824069 on Cortex-A53 parts u <<
510 to a coherent interconnect. <<
511 <<
512 If a Cortex-A53 processor is executi <<
513 write instruction at the same time a <<
514 cluster is executing a cache mainten <<
515 address, then this erratum might cau <<
516 incorrectly marked as dirty. <<
517 <<
518 The workaround promotes data cache c <<
519 data cache clean-and-invalidate. <<
520 Please note that this option does no <<
521 workaround, as it depends on the alt <<
522 only patch the kernel if an affected <<
523 1218
524 If unsure, say Y. !! 1219 config GENERIC_ISA_DMA_SUPPORT_BROKEN
>> 1220 bool
>> 1221 select GENERIC_ISA_DMA
525 1222
526 config ARM64_ERRATUM_819472 !! 1223 config HAVE_PLAT_DELAY
527 bool "Cortex-A53: 819472: Store exclus !! 1224 bool
528 default y <<
529 select ARM64_WORKAROUND_CLEAN_CACHE <<
530 help <<
531 This option adds an alternative code <<
532 erratum 819472 on Cortex-A53 parts u <<
533 present when it is connected to a co <<
534 <<
535 If the processor is executing a load <<
536 the same time as a processor in anot <<
537 maintenance operation to the same ad <<
538 cause data corruption. <<
539 <<
540 The workaround promotes data cache c <<
541 data cache clean-and-invalidate. <<
542 Please note that this does not neces <<
543 as it depends on the alternative fra <<
544 the kernel if an affected CPU is det <<
545 1225
546 If unsure, say Y. !! 1226 config HAVE_PLAT_FW_INIT_CMDLINE
>> 1227 bool
547 1228
548 config ARM64_ERRATUM_832075 !! 1229 config HAVE_PLAT_MEMCPY
549 bool "Cortex-A57: 832075: possible dea !! 1230 bool
550 default y <<
551 help <<
552 This option adds an alternative code <<
553 erratum 832075 on Cortex-A57 parts u <<
554 1231
555 Affected Cortex-A57 parts might dead !! 1232 config ISA_DMA_API
556 instructions to Write-Back memory ar !! 1233 bool
557 1234
558 The workaround is to promote device !! 1235 config SYS_SUPPORTS_RELOCATABLE
559 semantics. !! 1236 bool
560 Please note that this does not neces !! 1237 help
561 as it depends on the alternative fra !! 1238 Selected if the platform supports relocating the kernel.
562 the kernel if an affected CPU is det !! 1239 The platform must provide plat_get_fdt() if it selects CONFIG_USE_OF
>> 1240 to allow access to command line and entropy sources.
563 1241
564 If unsure, say Y. !! 1242 config MIPS_CBPF_JIT
>> 1243 def_bool y
>> 1244 depends on BPF_JIT && HAVE_CBPF_JIT
565 1245
566 config ARM64_ERRATUM_834220 !! 1246 config MIPS_EBPF_JIT
567 bool "Cortex-A57: 834220: Stage 2 tran !! 1247 def_bool y
568 depends on KVM !! 1248 depends on BPF_JIT && HAVE_EBPF_JIT
569 help <<
570 This option adds an alternative code <<
571 erratum 834220 on Cortex-A57 parts u <<
572 <<
573 Affected Cortex-A57 parts might repo <<
574 fault as the result of a Stage 1 fau <<
575 page boundary when there is a permis <<
576 alignment fault at Stage 1 and a tra <<
577 <<
578 The workaround is to verify that the <<
579 doesn't generate a fault before hand <<
580 Please note that this does not neces <<
581 as it depends on the alternative fra <<
582 the kernel if an affected CPU is det <<
583 1249
584 If unsure, say N. <<
585 1250
586 config ARM64_ERRATUM_1742098 !! 1251 #
587 bool "Cortex-A57/A72: 1742098: ELR rec !! 1252 # Endianness selection. Sufficiently obscure so many users don't know what to
588 depends on COMPAT !! 1253 # answer,so we try hard to limit the available choices. Also the use of a
589 default y !! 1254 # choice statement should be more obvious to the user.
>> 1255 #
>> 1256 choice
>> 1257 prompt "Endianness selection"
590 help 1258 help
591 This option removes the AES hwcap fo !! 1259 Some MIPS machines can be configured for either little or big endian
592 workaround erratum 1742098 on Cortex !! 1260 byte order. These modes require different kernels and a different
>> 1261 Linux distribution. In general there is one preferred byteorder for a
>> 1262 particular system but some systems are just as commonly used in the
>> 1263 one or the other endianness.
593 1264
594 Affected parts may corrupt the AES s !! 1265 config CPU_BIG_ENDIAN
595 taken between a pair of AES instruct !! 1266 bool "Big endian"
596 are only present if the cryptography !! 1267 depends on SYS_SUPPORTS_BIG_ENDIAN
597 All software should have a fallback <<
598 that don't implement the cryptograph <<
599 1268
600 If unsure, say Y. !! 1269 config CPU_LITTLE_ENDIAN
>> 1270 bool "Little endian"
>> 1271 depends on SYS_SUPPORTS_LITTLE_ENDIAN
601 1272
602 config ARM64_ERRATUM_845719 !! 1273 endchoice
603 bool "Cortex-A53: 845719: a load might <<
604 depends on COMPAT <<
605 default y <<
606 help <<
607 This option adds an alternative code <<
608 erratum 845719 on Cortex-A53 parts u <<
609 1274
610 When running a compat (AArch32) user !! 1275 config EXPORT_UASM
611 part, a load at EL0 from a virtual a !! 1276 bool
612 bits of the virtual address used by <<
613 might return incorrect data. <<
614 <<
615 The workaround is to write the conte <<
616 return to a 32-bit task. <<
617 Please note that this does not neces <<
618 as it depends on the alternative fra <<
619 the kernel if an affected CPU is det <<
620 1277
621 If unsure, say Y. !! 1278 config SYS_SUPPORTS_APM_EMULATION
>> 1279 bool
622 1280
623 config ARM64_ERRATUM_843419 !! 1281 config SYS_SUPPORTS_BIG_ENDIAN
624 bool "Cortex-A53: 843419: A load or st !! 1282 bool
625 default y <<
626 help <<
627 This option links the kernel with '- <<
628 enables PLT support to replace certa <<
629 cause subsequent memory accesses to <<
630 Cortex-A53 parts up to r0p4. <<
631 1283
632 If unsure, say Y. !! 1284 config SYS_SUPPORTS_LITTLE_ENDIAN
>> 1285 bool
633 1286
634 config ARM64_LD_HAS_FIX_ERRATUM_843419 !! 1287 config MIPS_HUGE_TLB_SUPPORT
635 def_bool $(ld-option,--fix-cortex-a53- !! 1288 def_bool HUGETLB_PAGE || TRANSPARENT_HUGEPAGE
636 1289
637 config ARM64_ERRATUM_1024718 !! 1290 config IRQ_MSP_SLP
638 bool "Cortex-A55: 1024718: Update of D !! 1291 bool
639 default y <<
640 help <<
641 This option adds a workaround for AR <<
642 1292
643 Affected Cortex-A55 cores (all revis !! 1293 config IRQ_MSP_CIC
644 update of the hardware dirty bit whe !! 1294 bool
645 without a break-before-make. The wor <<
646 of hardware DBM locally on the affec <<
647 this erratum will continue to use th <<
648 1295
649 If unsure, say Y. !! 1296 config IRQ_TXX9
>> 1297 bool
650 1298
651 config ARM64_ERRATUM_1418040 !! 1299 config IRQ_GT641XX
652 bool "Cortex-A76/Neoverse-N1: MRC read !! 1300 bool
653 default y <<
654 depends on COMPAT <<
655 help <<
656 This option adds a workaround for AR <<
657 errata 1188873 and 1418040. <<
658 1301
659 Affected Cortex-A76/Neoverse-N1 core !! 1302 config PCI_GT64XXX_PCI0
660 cause register corruption when acces !! 1303 bool
661 from AArch32 userspace. <<
662 1304
663 If unsure, say Y. !! 1305 config PCI_XTALK_BRIDGE
>> 1306 bool
664 1307
665 config ARM64_WORKAROUND_SPECULATIVE_AT !! 1308 config NO_EXCEPT_FILL
666 bool 1309 bool
667 1310
668 config ARM64_ERRATUM_1165522 !! 1311 config MIPS_SPRAM
669 bool "Cortex-A76: 1165522: Speculative !! 1312 bool
670 default y <<
671 select ARM64_WORKAROUND_SPECULATIVE_AT <<
672 help <<
673 This option adds a workaround for AR <<
674 1313
675 Affected Cortex-A76 cores (r0p0, r1p !! 1314 config SWAP_IO_SPACE
676 corrupted TLBs by speculating an AT !! 1315 bool
677 context switch. <<
678 1316
679 If unsure, say Y. !! 1317 config SGI_HAS_INDYDOG
>> 1318 bool
680 1319
681 config ARM64_ERRATUM_1319367 !! 1320 config SGI_HAS_HAL2
682 bool "Cortex-A57/A72: 1319537: Specula !! 1321 bool
683 default y <<
684 select ARM64_WORKAROUND_SPECULATIVE_AT <<
685 help <<
686 This option adds work arounds for AR <<
687 and A72 erratum 1319367 <<
688 1322
689 Cortex-A57 and A72 cores could end-u !! 1323 config SGI_HAS_SEEQ
690 speculating an AT instruction during !! 1324 bool
691 1325
692 If unsure, say Y. !! 1326 config SGI_HAS_WD93
>> 1327 bool
693 1328
694 config ARM64_ERRATUM_1530923 !! 1329 config SGI_HAS_ZILOG
695 bool "Cortex-A55: 1530923: Speculative !! 1330 bool
696 default y <<
697 select ARM64_WORKAROUND_SPECULATIVE_AT <<
698 help <<
699 This option adds a workaround for AR <<
700 1331
701 Affected Cortex-A55 cores (r0p0, r0p !! 1332 config SGI_HAS_I8042
702 corrupted TLBs by speculating an AT !! 1333 bool
703 context switch. <<
704 1334
705 If unsure, say Y. !! 1335 config DEFAULT_SGI_PARTITION
>> 1336 bool
706 1337
707 config ARM64_WORKAROUND_REPEAT_TLBI !! 1338 config FW_ARC32
708 bool 1339 bool
709 1340
710 config ARM64_ERRATUM_2441007 !! 1341 config FW_SNIPROM
711 bool "Cortex-A55: Completion of affect !! 1342 bool
712 select ARM64_WORKAROUND_REPEAT_TLBI <<
713 help <<
714 This option adds a workaround for AR <<
715 1343
716 Under very rare circumstances, affec !! 1344 config BOOT_ELF32
717 may not handle a race between a brea !! 1345 bool
718 CPU, and another CPU accessing the s <<
719 store to a page that has been unmapp <<
720 1346
721 Work around this by adding the affec !! 1347 config MIPS_L1_CACHE_SHIFT_4
722 TLB sequences to be done twice. !! 1348 bool
723 1349
724 If unsure, say N. !! 1350 config MIPS_L1_CACHE_SHIFT_5
>> 1351 bool
725 1352
726 config ARM64_ERRATUM_1286807 !! 1353 config MIPS_L1_CACHE_SHIFT_6
727 bool "Cortex-A76: Modification of the !! 1354 bool
728 select ARM64_WORKAROUND_REPEAT_TLBI <<
729 help <<
730 This option adds a workaround for AR <<
731 <<
732 On the affected Cortex-A76 cores (r0 <<
733 address for a cacheable mapping of a <<
734 accessed by a core while another cor <<
735 address to a new physical page using <<
736 break-before-make sequence, then und <<
737 TLBI+DSB completes before a read usi <<
738 invalidated has been observed by oth <<
739 workaround repeats the TLBI+DSB oper <<
740 1355
741 If unsure, say N. !! 1356 config MIPS_L1_CACHE_SHIFT_7
>> 1357 bool
742 1358
743 config ARM64_ERRATUM_1463225 !! 1359 config MIPS_L1_CACHE_SHIFT
744 bool "Cortex-A76: Software Step might !! 1360 int
745 default y !! 1361 default "7" if MIPS_L1_CACHE_SHIFT_7
746 help !! 1362 default "6" if MIPS_L1_CACHE_SHIFT_6
747 This option adds a workaround for Ar !! 1363 default "5" if MIPS_L1_CACHE_SHIFT_5
>> 1364 default "4" if MIPS_L1_CACHE_SHIFT_4
>> 1365 default "5"
748 1366
749 On the affected Cortex-A76 cores (r0 !! 1367 config ARC_CMDLINE_ONLY
750 of a system call instruction (SVC) c !! 1368 bool
751 subsequent interrupts when software <<
752 exception handler of the system call <<
753 is enabled or VHE is in use. <<
754 <<
755 Work around the erratum by triggerin <<
756 when handling a system call from a t <<
757 in a VHE configuration of the kernel <<
758 1369
759 If unsure, say Y. !! 1370 config ARC_CONSOLE
>> 1371 bool "ARC console support"
>> 1372 depends on SGI_IP22 || SGI_IP28 || (SNI_RM && CPU_LITTLE_ENDIAN)
760 1373
761 config ARM64_ERRATUM_1542419 !! 1374 config ARC_MEMORY
762 bool "Neoverse-N1: workaround mis-orde !! 1375 bool
763 help <<
764 This option adds a workaround for AR <<
765 1542419. <<
766 1376
767 Affected Neoverse-N1 cores could exe !! 1377 config ARC_PROMLIB
768 modified by another CPU. The workaro !! 1378 bool
769 counterpart. <<
770 1379
771 Workaround the issue by hiding the D !! 1380 config FW_ARC64
772 forces user-space to perform cache m !! 1381 bool
773 1382
774 If unsure, say N. !! 1383 config BOOT_ELF64
>> 1384 bool
775 1385
776 config ARM64_ERRATUM_1508412 !! 1386 menu "CPU selection"
777 bool "Cortex-A77: 1508412: workaround <<
778 default y <<
779 help <<
780 This option adds a workaround for Ar <<
781 1387
782 Affected Cortex-A77 cores (r0p0, r1p !! 1388 choice
783 of a store-exclusive or read of PAR_ !! 1389 prompt "CPU type"
784 non-cacheable memory attributes. The !! 1390 default CPU_R4X00
785 counterpart. <<
786 <<
787 KVM guests must also have the workar <<
788 deadlock the system. <<
789 <<
790 Work around the issue by inserting D <<
791 register reads and warning KVM users <<
792 to prevent a speculative PAR_EL1 rea <<
793 1391
794 If unsure, say Y. !! 1392 config CPU_LOONGSON64
>> 1393 bool "Loongson 64-bit CPU"
>> 1394 depends on SYS_HAS_CPU_LOONGSON64
>> 1395 select ARCH_HAS_PHYS_TO_DMA
>> 1396 select CPU_MIPSR2
>> 1397 select CPU_HAS_PREFETCH
>> 1398 select CPU_SUPPORTS_64BIT_KERNEL
>> 1399 select CPU_SUPPORTS_HIGHMEM
>> 1400 select CPU_SUPPORTS_HUGEPAGES
>> 1401 select CPU_SUPPORTS_MSA
>> 1402 select CPU_DIEI_BROKEN if !LOONGSON3_ENHANCEMENT
>> 1403 select CPU_MIPSR2_IRQ_VI
>> 1404 select WEAK_ORDERING
>> 1405 select WEAK_REORDERING_BEYOND_LLSC
>> 1406 select MIPS_ASID_BITS_VARIABLE
>> 1407 select MIPS_PGD_C0_CONTEXT
>> 1408 select MIPS_L1_CACHE_SHIFT_6
>> 1409 select MIPS_FP_SUPPORT
>> 1410 select GPIOLIB
>> 1411 select SWIOTLB
>> 1412 select HAVE_KVM
>> 1413 help
>> 1414 The Loongson GSx64(GS264/GS464/GS464E/GS464V) series of processor
>> 1415 cores implements the MIPS64R2 instruction set with many extensions,
>> 1416 including most 64-bit Loongson-2 (2H, 2K) and Loongson-3 (3A1000,
>> 1417 3B1000, 3B1500, 3A2000, 3A3000 and 3A4000) processors. However, old
>> 1418 Loongson-2E/2F is not covered here and will be removed in future.
795 1419
796 config ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MO !! 1420 config LOONGSON3_ENHANCEMENT
797 bool !! 1421 bool "New Loongson-3 CPU Enhancements"
>> 1422 default n
>> 1423 depends on CPU_LOONGSON64
>> 1424 help
>> 1425 New Loongson-3 cores (since Loongson-3A R2, as opposed to Loongson-3A
>> 1426 R1, Loongson-3B R1 and Loongson-3B R2) has many enhancements, such as
>> 1427 FTLB, L1-VCache, EI/DI/Wait/Prefetch instruction, DSP/DSPr2 ASE, User
>> 1428 Local register, Read-Inhibit/Execute-Inhibit, SFB (Store Fill Buffer),
>> 1429 Fast TLB refill support, etc.
>> 1430
>> 1431 This option enable those enhancements which are not probed at run
>> 1432 time. If you want a generic kernel to run on all Loongson 3 machines,
>> 1433 please say 'N' here. If you want a high-performance kernel to run on
>> 1434 new Loongson-3 machines only, please say 'Y' here.
>> 1435
>> 1436 config CPU_LOONGSON3_WORKAROUNDS
>> 1437 bool "Old Loongson-3 LLSC Workarounds"
>> 1438 default y if SMP
>> 1439 depends on CPU_LOONGSON64
>> 1440 help
>> 1441 Loongson-3 processors have the llsc issues which require workarounds.
>> 1442 Without workarounds the system may hang unexpectedly.
>> 1443
>> 1444 Newer Loongson-3 will fix these issues and no workarounds are needed.
>> 1445 The workarounds have no significant side effect on them but may
>> 1446 decrease the performance of the system so this option should be
>> 1447 disabled unless the kernel is intended to be run on old systems.
>> 1448
>> 1449 If unsure, please say Y.
>> 1450
>> 1451 config CPU_LOONGSON3_CPUCFG_EMULATION
>> 1452 bool "Emulate the CPUCFG instruction on older Loongson cores"
>> 1453 default y
>> 1454 depends on CPU_LOONGSON64
>> 1455 help
>> 1456 Loongson-3A R4 and newer have the CPUCFG instruction available for
>> 1457 userland to query CPU capabilities, much like CPUID on x86. This
>> 1458 option provides emulation of the instruction on older Loongson
>> 1459 cores, back to Loongson-3A1000.
>> 1460
>> 1461 If unsure, please say Y.
>> 1462
>> 1463 config CPU_LOONGSON2E
>> 1464 bool "Loongson 2E"
>> 1465 depends on SYS_HAS_CPU_LOONGSON2E
>> 1466 select CPU_LOONGSON2EF
>> 1467 help
>> 1468 The Loongson 2E processor implements the MIPS III instruction set
>> 1469 with many extensions.
>> 1470
>> 1471 It has an internal FPGA northbridge, which is compatible to
>> 1472 bonito64.
>> 1473
>> 1474 config CPU_LOONGSON2F
>> 1475 bool "Loongson 2F"
>> 1476 depends on SYS_HAS_CPU_LOONGSON2F
>> 1477 select CPU_LOONGSON2EF
>> 1478 select GPIOLIB
>> 1479 help
>> 1480 The Loongson 2F processor implements the MIPS III instruction set
>> 1481 with many extensions.
>> 1482
>> 1483 Loongson2F have built-in DDR2 and PCIX controller. The PCIX controller
>> 1484 have a similar programming interface with FPGA northbridge used in
>> 1485 Loongson2E.
>> 1486
>> 1487 config CPU_LOONGSON1B
>> 1488 bool "Loongson 1B"
>> 1489 depends on SYS_HAS_CPU_LOONGSON1B
>> 1490 select CPU_LOONGSON32
>> 1491 select LEDS_GPIO_REGISTER
>> 1492 help
>> 1493 The Loongson 1B is a 32-bit SoC, which implements the MIPS32
>> 1494 Release 1 instruction set and part of the MIPS32 Release 2
>> 1495 instruction set.
>> 1496
>> 1497 config CPU_LOONGSON1C
>> 1498 bool "Loongson 1C"
>> 1499 depends on SYS_HAS_CPU_LOONGSON1C
>> 1500 select CPU_LOONGSON32
>> 1501 select LEDS_GPIO_REGISTER
>> 1502 help
>> 1503 The Loongson 1C is a 32-bit SoC, which implements the MIPS32
>> 1504 Release 1 instruction set and part of the MIPS32 Release 2
>> 1505 instruction set.
>> 1506
>> 1507 config CPU_MIPS32_R1
>> 1508 bool "MIPS32 Release 1"
>> 1509 depends on SYS_HAS_CPU_MIPS32_R1
>> 1510 select CPU_HAS_PREFETCH
>> 1511 select CPU_SUPPORTS_32BIT_KERNEL
>> 1512 select CPU_SUPPORTS_HIGHMEM
>> 1513 help
>> 1514 Choose this option to build a kernel for release 1 or later of the
>> 1515 MIPS32 architecture. Most modern embedded systems with a 32-bit
>> 1516 MIPS processor are based on a MIPS32 processor. If you know the
>> 1517 specific type of processor in your system, choose those that one
>> 1518 otherwise CPU_MIPS32_R1 is a safe bet for any MIPS32 system.
>> 1519 Release 2 of the MIPS32 architecture is available since several
>> 1520 years so chances are you even have a MIPS32 Release 2 processor
>> 1521 in which case you should choose CPU_MIPS32_R2 instead for better
>> 1522 performance.
>> 1523
>> 1524 config CPU_MIPS32_R2
>> 1525 bool "MIPS32 Release 2"
>> 1526 depends on SYS_HAS_CPU_MIPS32_R2
>> 1527 select CPU_HAS_PREFETCH
>> 1528 select CPU_SUPPORTS_32BIT_KERNEL
>> 1529 select CPU_SUPPORTS_HIGHMEM
>> 1530 select CPU_SUPPORTS_MSA
>> 1531 select HAVE_KVM
>> 1532 help
>> 1533 Choose this option to build a kernel for release 2 or later of the
>> 1534 MIPS32 architecture. Most modern embedded systems with a 32-bit
>> 1535 MIPS processor are based on a MIPS32 processor. If you know the
>> 1536 specific type of processor in your system, choose those that one
>> 1537 otherwise CPU_MIPS32_R1 is a safe bet for any MIPS32 system.
>> 1538
>> 1539 config CPU_MIPS32_R5
>> 1540 bool "MIPS32 Release 5"
>> 1541 depends on SYS_HAS_CPU_MIPS32_R5
>> 1542 select CPU_HAS_PREFETCH
>> 1543 select CPU_SUPPORTS_32BIT_KERNEL
>> 1544 select CPU_SUPPORTS_HIGHMEM
>> 1545 select CPU_SUPPORTS_MSA
>> 1546 select HAVE_KVM
>> 1547 select MIPS_O32_FP64_SUPPORT
>> 1548 help
>> 1549 Choose this option to build a kernel for release 5 or later of the
>> 1550 MIPS32 architecture. New MIPS processors, starting with the Warrior
>> 1551 family, are based on a MIPS32r5 processor. If you own an older
>> 1552 processor, you probably need to select MIPS32r1 or MIPS32r2 instead.
>> 1553
>> 1554 config CPU_MIPS32_R6
>> 1555 bool "MIPS32 Release 6"
>> 1556 depends on SYS_HAS_CPU_MIPS32_R6
>> 1557 select CPU_HAS_PREFETCH
>> 1558 select CPU_NO_LOAD_STORE_LR
>> 1559 select CPU_SUPPORTS_32BIT_KERNEL
>> 1560 select CPU_SUPPORTS_HIGHMEM
>> 1561 select CPU_SUPPORTS_MSA
>> 1562 select HAVE_KVM
>> 1563 select MIPS_O32_FP64_SUPPORT
>> 1564 help
>> 1565 Choose this option to build a kernel for release 6 or later of the
>> 1566 MIPS32 architecture. New MIPS processors, starting with the Warrior
>> 1567 family, are based on a MIPS32r6 processor. If you own an older
>> 1568 processor, you probably need to select MIPS32r1 or MIPS32r2 instead.
>> 1569
>> 1570 config CPU_MIPS64_R1
>> 1571 bool "MIPS64 Release 1"
>> 1572 depends on SYS_HAS_CPU_MIPS64_R1
>> 1573 select CPU_HAS_PREFETCH
>> 1574 select CPU_SUPPORTS_32BIT_KERNEL
>> 1575 select CPU_SUPPORTS_64BIT_KERNEL
>> 1576 select CPU_SUPPORTS_HIGHMEM
>> 1577 select CPU_SUPPORTS_HUGEPAGES
>> 1578 help
>> 1579 Choose this option to build a kernel for release 1 or later of the
>> 1580 MIPS64 architecture. Many modern embedded systems with a 64-bit
>> 1581 MIPS processor are based on a MIPS64 processor. If you know the
>> 1582 specific type of processor in your system, choose those that one
>> 1583 otherwise CPU_MIPS64_R1 is a safe bet for any MIPS64 system.
>> 1584 Release 2 of the MIPS64 architecture is available since several
>> 1585 years so chances are you even have a MIPS64 Release 2 processor
>> 1586 in which case you should choose CPU_MIPS64_R2 instead for better
>> 1587 performance.
>> 1588
>> 1589 config CPU_MIPS64_R2
>> 1590 bool "MIPS64 Release 2"
>> 1591 depends on SYS_HAS_CPU_MIPS64_R2
>> 1592 select CPU_HAS_PREFETCH
>> 1593 select CPU_SUPPORTS_32BIT_KERNEL
>> 1594 select CPU_SUPPORTS_64BIT_KERNEL
>> 1595 select CPU_SUPPORTS_HIGHMEM
>> 1596 select CPU_SUPPORTS_HUGEPAGES
>> 1597 select CPU_SUPPORTS_MSA
>> 1598 select HAVE_KVM
>> 1599 help
>> 1600 Choose this option to build a kernel for release 2 or later of the
>> 1601 MIPS64 architecture. Many modern embedded systems with a 64-bit
>> 1602 MIPS processor are based on a MIPS64 processor. If you know the
>> 1603 specific type of processor in your system, choose those that one
>> 1604 otherwise CPU_MIPS64_R1 is a safe bet for any MIPS64 system.
>> 1605
>> 1606 config CPU_MIPS64_R5
>> 1607 bool "MIPS64 Release 5"
>> 1608 depends on SYS_HAS_CPU_MIPS64_R5
>> 1609 select CPU_HAS_PREFETCH
>> 1610 select CPU_SUPPORTS_32BIT_KERNEL
>> 1611 select CPU_SUPPORTS_64BIT_KERNEL
>> 1612 select CPU_SUPPORTS_HIGHMEM
>> 1613 select CPU_SUPPORTS_HUGEPAGES
>> 1614 select CPU_SUPPORTS_MSA
>> 1615 select MIPS_O32_FP64_SUPPORT if 32BIT || MIPS32_O32
>> 1616 select HAVE_KVM
>> 1617 help
>> 1618 Choose this option to build a kernel for release 5 or later of the
>> 1619 MIPS64 architecture. This is a intermediate MIPS architecture
>> 1620 release partly implementing release 6 features. Though there is no
>> 1621 any hardware known to be based on this release.
>> 1622
>> 1623 config CPU_MIPS64_R6
>> 1624 bool "MIPS64 Release 6"
>> 1625 depends on SYS_HAS_CPU_MIPS64_R6
>> 1626 select CPU_HAS_PREFETCH
>> 1627 select CPU_NO_LOAD_STORE_LR
>> 1628 select CPU_SUPPORTS_32BIT_KERNEL
>> 1629 select CPU_SUPPORTS_64BIT_KERNEL
>> 1630 select CPU_SUPPORTS_HIGHMEM
>> 1631 select CPU_SUPPORTS_HUGEPAGES
>> 1632 select CPU_SUPPORTS_MSA
>> 1633 select MIPS_O32_FP64_SUPPORT if 32BIT || MIPS32_O32
>> 1634 select HAVE_KVM
>> 1635 help
>> 1636 Choose this option to build a kernel for release 6 or later of the
>> 1637 MIPS64 architecture. New MIPS processors, starting with the Warrior
>> 1638 family, are based on a MIPS64r6 processor. If you own an older
>> 1639 processor, you probably need to select MIPS64r1 or MIPS64r2 instead.
>> 1640
>> 1641 config CPU_P5600
>> 1642 bool "MIPS Warrior P5600"
>> 1643 depends on SYS_HAS_CPU_P5600
>> 1644 select CPU_HAS_PREFETCH
>> 1645 select CPU_SUPPORTS_32BIT_KERNEL
>> 1646 select CPU_SUPPORTS_HIGHMEM
>> 1647 select CPU_SUPPORTS_MSA
>> 1648 select CPU_SUPPORTS_CPUFREQ
>> 1649 select CPU_MIPSR2_IRQ_VI
>> 1650 select CPU_MIPSR2_IRQ_EI
>> 1651 select HAVE_KVM
>> 1652 select MIPS_O32_FP64_SUPPORT
>> 1653 help
>> 1654 Choose this option to build a kernel for MIPS Warrior P5600 CPU.
>> 1655 It's based on MIPS32r5 ISA with XPA, EVA, dual/quad issue exec pipes,
>> 1656 MMU with two-levels TLB, UCA, MSA, MDU core level features and system
>> 1657 level features like up to six P5600 calculation cores, CM2 with L2
>> 1658 cache, IOCU/IOMMU (though might be unused depending on the system-
>> 1659 specific IP core configuration), GIC, CPC, virtualisation module,
>> 1660 eJTAG and PDtrace.
>> 1661
>> 1662 config CPU_R3000
>> 1663 bool "R3000"
>> 1664 depends on SYS_HAS_CPU_R3000
>> 1665 select CPU_HAS_WB
>> 1666 select CPU_R3K_TLB
>> 1667 select CPU_SUPPORTS_32BIT_KERNEL
>> 1668 select CPU_SUPPORTS_HIGHMEM
>> 1669 help
>> 1670 Please make sure to pick the right CPU type. Linux/MIPS is not
>> 1671 designed to be generic, i.e. Kernels compiled for R3000 CPUs will
>> 1672 *not* work on R4000 machines and vice versa. However, since most
>> 1673 of the supported machines have an R4000 (or similar) CPU, R4x00
>> 1674 might be a safe bet. If the resulting kernel does not work,
>> 1675 try to recompile with R3000.
>> 1676
>> 1677 config CPU_TX39XX
>> 1678 bool "R39XX"
>> 1679 depends on SYS_HAS_CPU_TX39XX
>> 1680 select CPU_SUPPORTS_32BIT_KERNEL
>> 1681 select CPU_R3K_TLB
>> 1682
>> 1683 config CPU_VR41XX
>> 1684 bool "R41xx"
>> 1685 depends on SYS_HAS_CPU_VR41XX
>> 1686 select CPU_SUPPORTS_32BIT_KERNEL
>> 1687 select CPU_SUPPORTS_64BIT_KERNEL
>> 1688 help
>> 1689 The options selects support for the NEC VR4100 series of processors.
>> 1690 Only choose this option if you have one of these processors as a
>> 1691 kernel built with this option will not run on any other type of
>> 1692 processor or vice versa.
>> 1693
>> 1694 config CPU_R4300
>> 1695 bool "R4300"
>> 1696 depends on SYS_HAS_CPU_R4300
>> 1697 select CPU_SUPPORTS_32BIT_KERNEL
>> 1698 select CPU_SUPPORTS_64BIT_KERNEL
>> 1699 select CPU_HAS_LOAD_STORE_LR
>> 1700 help
>> 1701 MIPS Technologies R4300-series processors.
>> 1702
>> 1703 config CPU_R4X00
>> 1704 bool "R4x00"
>> 1705 depends on SYS_HAS_CPU_R4X00
>> 1706 select CPU_SUPPORTS_32BIT_KERNEL
>> 1707 select CPU_SUPPORTS_64BIT_KERNEL
>> 1708 select CPU_SUPPORTS_HUGEPAGES
>> 1709 help
>> 1710 MIPS Technologies R4000-series processors other than 4300, including
>> 1711 the R4000, R4400, R4600, and 4700.
>> 1712
>> 1713 config CPU_TX49XX
>> 1714 bool "R49XX"
>> 1715 depends on SYS_HAS_CPU_TX49XX
>> 1716 select CPU_HAS_PREFETCH
>> 1717 select CPU_SUPPORTS_32BIT_KERNEL
>> 1718 select CPU_SUPPORTS_64BIT_KERNEL
>> 1719 select CPU_SUPPORTS_HUGEPAGES
>> 1720
>> 1721 config CPU_R5000
>> 1722 bool "R5000"
>> 1723 depends on SYS_HAS_CPU_R5000
>> 1724 select CPU_SUPPORTS_32BIT_KERNEL
>> 1725 select CPU_SUPPORTS_64BIT_KERNEL
>> 1726 select CPU_SUPPORTS_HUGEPAGES
>> 1727 help
>> 1728 MIPS Technologies R5000-series processors other than the Nevada.
>> 1729
>> 1730 config CPU_R5500
>> 1731 bool "R5500"
>> 1732 depends on SYS_HAS_CPU_R5500
>> 1733 select CPU_SUPPORTS_32BIT_KERNEL
>> 1734 select CPU_SUPPORTS_64BIT_KERNEL
>> 1735 select CPU_SUPPORTS_HUGEPAGES
>> 1736 help
>> 1737 NEC VR5500 and VR5500A series processors implement 64-bit MIPS IV
>> 1738 instruction set.
>> 1739
>> 1740 config CPU_NEVADA
>> 1741 bool "RM52xx"
>> 1742 depends on SYS_HAS_CPU_NEVADA
>> 1743 select CPU_SUPPORTS_32BIT_KERNEL
>> 1744 select CPU_SUPPORTS_64BIT_KERNEL
>> 1745 select CPU_SUPPORTS_HUGEPAGES
>> 1746 help
>> 1747 QED / PMC-Sierra RM52xx-series ("Nevada") processors.
>> 1748
>> 1749 config CPU_R10000
>> 1750 bool "R10000"
>> 1751 depends on SYS_HAS_CPU_R10000
>> 1752 select CPU_HAS_PREFETCH
>> 1753 select CPU_SUPPORTS_32BIT_KERNEL
>> 1754 select CPU_SUPPORTS_64BIT_KERNEL
>> 1755 select CPU_SUPPORTS_HIGHMEM
>> 1756 select CPU_SUPPORTS_HUGEPAGES
>> 1757 help
>> 1758 MIPS Technologies R10000-series processors.
>> 1759
>> 1760 config CPU_RM7000
>> 1761 bool "RM7000"
>> 1762 depends on SYS_HAS_CPU_RM7000
>> 1763 select CPU_HAS_PREFETCH
>> 1764 select CPU_SUPPORTS_32BIT_KERNEL
>> 1765 select CPU_SUPPORTS_64BIT_KERNEL
>> 1766 select CPU_SUPPORTS_HIGHMEM
>> 1767 select CPU_SUPPORTS_HUGEPAGES
>> 1768
>> 1769 config CPU_SB1
>> 1770 bool "SB1"
>> 1771 depends on SYS_HAS_CPU_SB1
>> 1772 select CPU_SUPPORTS_32BIT_KERNEL
>> 1773 select CPU_SUPPORTS_64BIT_KERNEL
>> 1774 select CPU_SUPPORTS_HIGHMEM
>> 1775 select CPU_SUPPORTS_HUGEPAGES
>> 1776 select WEAK_ORDERING
>> 1777
>> 1778 config CPU_CAVIUM_OCTEON
>> 1779 bool "Cavium Octeon processor"
>> 1780 depends on SYS_HAS_CPU_CAVIUM_OCTEON
>> 1781 select CPU_HAS_PREFETCH
>> 1782 select CPU_SUPPORTS_64BIT_KERNEL
>> 1783 select WEAK_ORDERING
>> 1784 select CPU_SUPPORTS_HIGHMEM
>> 1785 select CPU_SUPPORTS_HUGEPAGES
>> 1786 select USB_EHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 1787 select USB_OHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 1788 select MIPS_L1_CACHE_SHIFT_7
>> 1789 select HAVE_KVM
>> 1790 help
>> 1791 The Cavium Octeon processor is a highly integrated chip containing
>> 1792 many ethernet hardware widgets for networking tasks. The processor
>> 1793 can have up to 16 Mips64v2 cores and 8 integrated gigabit ethernets.
>> 1794 Full details can be found at http://www.caviumnetworks.com.
>> 1795
>> 1796 config CPU_BMIPS
>> 1797 bool "Broadcom BMIPS"
>> 1798 depends on SYS_HAS_CPU_BMIPS
>> 1799 select CPU_MIPS32
>> 1800 select CPU_BMIPS32_3300 if SYS_HAS_CPU_BMIPS32_3300
>> 1801 select CPU_BMIPS4350 if SYS_HAS_CPU_BMIPS4350
>> 1802 select CPU_BMIPS4380 if SYS_HAS_CPU_BMIPS4380
>> 1803 select CPU_BMIPS5000 if SYS_HAS_CPU_BMIPS5000
>> 1804 select CPU_SUPPORTS_32BIT_KERNEL
>> 1805 select DMA_NONCOHERENT
>> 1806 select IRQ_MIPS_CPU
>> 1807 select SWAP_IO_SPACE
>> 1808 select WEAK_ORDERING
>> 1809 select CPU_SUPPORTS_HIGHMEM
>> 1810 select CPU_HAS_PREFETCH
>> 1811 select CPU_SUPPORTS_CPUFREQ
>> 1812 select MIPS_EXTERNAL_TIMER
>> 1813 help
>> 1814 Support for BMIPS32/3300/4350/4380 and BMIPS5000 processors.
>> 1815
>> 1816 config CPU_XLR
>> 1817 bool "Netlogic XLR SoC"
>> 1818 depends on SYS_HAS_CPU_XLR
>> 1819 select CPU_SUPPORTS_32BIT_KERNEL
>> 1820 select CPU_SUPPORTS_64BIT_KERNEL
>> 1821 select CPU_SUPPORTS_HIGHMEM
>> 1822 select CPU_SUPPORTS_HUGEPAGES
>> 1823 select WEAK_ORDERING
>> 1824 select WEAK_REORDERING_BEYOND_LLSC
>> 1825 help
>> 1826 Netlogic Microsystems XLR/XLS processors.
>> 1827
>> 1828 config CPU_XLP
>> 1829 bool "Netlogic XLP SoC"
>> 1830 depends on SYS_HAS_CPU_XLP
>> 1831 select CPU_SUPPORTS_32BIT_KERNEL
>> 1832 select CPU_SUPPORTS_64BIT_KERNEL
>> 1833 select CPU_SUPPORTS_HIGHMEM
>> 1834 select WEAK_ORDERING
>> 1835 select WEAK_REORDERING_BEYOND_LLSC
>> 1836 select CPU_HAS_PREFETCH
>> 1837 select CPU_MIPSR2
>> 1838 select CPU_SUPPORTS_HUGEPAGES
>> 1839 select MIPS_ASID_BITS_VARIABLE
>> 1840 help
>> 1841 Netlogic Microsystems XLP processors.
>> 1842 endchoice
798 1843
799 config ARM64_ERRATUM_2051678 !! 1844 config CPU_MIPS32_3_5_FEATURES
800 bool "Cortex-A510: 2051678: disable Ha !! 1845 bool "MIPS32 Release 3.5 Features"
801 default y !! 1846 depends on SYS_HAS_CPU_MIPS32_R3_5
>> 1847 depends on CPU_MIPS32_R2 || CPU_MIPS32_R5 || CPU_MIPS32_R6 || \
>> 1848 CPU_P5600
>> 1849 help
>> 1850 Choose this option to build a kernel for release 2 or later of the
>> 1851 MIPS32 architecture including features from the 3.5 release such as
>> 1852 support for Enhanced Virtual Addressing (EVA).
>> 1853
>> 1854 config CPU_MIPS32_3_5_EVA
>> 1855 bool "Enhanced Virtual Addressing (EVA)"
>> 1856 depends on CPU_MIPS32_3_5_FEATURES
>> 1857 select EVA
>> 1858 default y
>> 1859 help
>> 1860 Choose this option if you want to enable the Enhanced Virtual
>> 1861 Addressing (EVA) on your MIPS32 core (such as proAptiv).
>> 1862 One of its primary benefits is an increase in the maximum size
>> 1863 of lowmem (up to 3GB). If unsure, say 'N' here.
>> 1864
>> 1865 config CPU_MIPS32_R5_FEATURES
>> 1866 bool "MIPS32 Release 5 Features"
>> 1867 depends on SYS_HAS_CPU_MIPS32_R5
>> 1868 depends on CPU_MIPS32_R2 || CPU_MIPS32_R5 || CPU_P5600
>> 1869 help
>> 1870 Choose this option to build a kernel for release 2 or later of the
>> 1871 MIPS32 architecture including features from release 5 such as
>> 1872 support for Extended Physical Addressing (XPA).
>> 1873
>> 1874 config CPU_MIPS32_R5_XPA
>> 1875 bool "Extended Physical Addressing (XPA)"
>> 1876 depends on CPU_MIPS32_R5_FEATURES
>> 1877 depends on !EVA
>> 1878 depends on !PAGE_SIZE_4KB
>> 1879 depends on SYS_SUPPORTS_HIGHMEM
>> 1880 select XPA
>> 1881 select HIGHMEM
>> 1882 select PHYS_ADDR_T_64BIT
>> 1883 default n
802 help 1884 help
803 This options adds the workaround for !! 1885 Choose this option if you want to enable the Extended Physical
804 Affected Cortex-A510 might not respe !! 1886 Addressing (XPA) on your MIPS32 core (such as P5600 series). The
805 hardware update of the page table's !! 1887 benefit is to increase physical addressing equal to or greater
806 is to not enable the feature on affe !! 1888 than 40 bits. Note that this has the side effect of turning on
>> 1889 64-bit addressing which in turn makes the PTEs 64-bit in size.
>> 1890 If unsure, say 'N' here.
807 1891
808 If unsure, say Y. !! 1892 if CPU_LOONGSON2F
>> 1893 config CPU_NOP_WORKAROUNDS
>> 1894 bool
>> 1895
>> 1896 config CPU_JUMP_WORKAROUNDS
>> 1897 bool
809 1898
810 config ARM64_ERRATUM_2077057 !! 1899 config CPU_LOONGSON2F_WORKAROUNDS
811 bool "Cortex-A510: 2077057: workaround !! 1900 bool "Loongson 2F Workarounds"
812 default y 1901 default y
>> 1902 select CPU_NOP_WORKAROUNDS
>> 1903 select CPU_JUMP_WORKAROUNDS
813 help 1904 help
814 This option adds the workaround for !! 1905 Loongson 2F01 / 2F02 processors have the NOP & JUMP issues which
815 Affected Cortex-A510 may corrupt SPS !! 1906 require workarounds. Without workarounds the system may hang
816 expected, but a Pointer Authenticati !! 1907 unexpectedly. For more information please refer to the gas
817 erratum causes SPSR_EL1 to be copied !! 1908 -mfix-loongson2f-nop and -mfix-loongson2f-jump options.
818 EL1 to cause a return to EL2 with a !! 1909
>> 1910 Loongson 2F03 and later have fixed these issues and no workarounds
>> 1911 are needed. The workarounds have no significant side effect on them
>> 1912 but may decrease the performance of the system so this option should
>> 1913 be disabled unless the kernel is intended to be run on 2F01 or 2F02
>> 1914 systems.
819 1915
820 This can only happen when EL2 is ste !! 1916 If unsure, please say Y.
>> 1917 endif # CPU_LOONGSON2F
821 1918
822 When these conditions occur, the SPS !! 1919 config SYS_SUPPORTS_ZBOOT
823 previous guest entry, and can be res !! 1920 bool
>> 1921 select HAVE_KERNEL_GZIP
>> 1922 select HAVE_KERNEL_BZIP2
>> 1923 select HAVE_KERNEL_LZ4
>> 1924 select HAVE_KERNEL_LZMA
>> 1925 select HAVE_KERNEL_LZO
>> 1926 select HAVE_KERNEL_XZ
>> 1927 select HAVE_KERNEL_ZSTD
824 1928
825 If unsure, say Y. !! 1929 config SYS_SUPPORTS_ZBOOT_UART16550
>> 1930 bool
>> 1931 select SYS_SUPPORTS_ZBOOT
826 1932
827 config ARM64_ERRATUM_2658417 !! 1933 config SYS_SUPPORTS_ZBOOT_UART_PROM
828 bool "Cortex-A510: 2658417: remove BF1 !! 1934 bool
829 default y !! 1935 select SYS_SUPPORTS_ZBOOT
830 help <<
831 This option adds the workaround for <<
832 Affected Cortex-A510 (r0p0 to r1p1) <<
833 BFMMLA or VMMLA instructions in rare <<
834 A510 CPUs are using shared neon hard <<
835 discoverable by the kernel, hide the <<
836 user-space should not be using these <<
837 1936
838 If unsure, say Y. !! 1937 config CPU_LOONGSON2EF
>> 1938 bool
>> 1939 select CPU_SUPPORTS_32BIT_KERNEL
>> 1940 select CPU_SUPPORTS_64BIT_KERNEL
>> 1941 select CPU_SUPPORTS_HIGHMEM
>> 1942 select CPU_SUPPORTS_HUGEPAGES
>> 1943 select ARCH_HAS_PHYS_TO_DMA
839 1944
840 config ARM64_ERRATUM_2119858 !! 1945 config CPU_LOONGSON32
841 bool "Cortex-A710/X2: 2119858: workaro !! 1946 bool
842 default y !! 1947 select CPU_MIPS32
843 depends on CORESIGHT_TRBE !! 1948 select CPU_MIPSR2
844 select ARM64_WORKAROUND_TRBE_OVERWRITE !! 1949 select CPU_HAS_PREFETCH
845 help !! 1950 select CPU_SUPPORTS_32BIT_KERNEL
846 This option adds the workaround for !! 1951 select CPU_SUPPORTS_HIGHMEM
>> 1952 select CPU_SUPPORTS_CPUFREQ
847 1953
848 Affected Cortex-A710/X2 cores could !! 1954 config CPU_BMIPS32_3300
849 data at the base of the buffer (poin !! 1955 select SMP_UP if SMP
850 the event of a WRAP event. !! 1956 bool
851 <<
852 Work around the issue by always maki <<
853 256 bytes before enabling the buffer <<
854 the buffer with ETM ignore packets u <<
855 1957
856 If unsure, say Y. !! 1958 config CPU_BMIPS4350
>> 1959 bool
>> 1960 select SYS_SUPPORTS_SMP
>> 1961 select SYS_SUPPORTS_HOTPLUG_CPU
857 1962
858 config ARM64_ERRATUM_2139208 !! 1963 config CPU_BMIPS4380
859 bool "Neoverse-N2: 2139208: workaround !! 1964 bool
860 default y !! 1965 select MIPS_L1_CACHE_SHIFT_6
861 depends on CORESIGHT_TRBE !! 1966 select SYS_SUPPORTS_SMP
862 select ARM64_WORKAROUND_TRBE_OVERWRITE !! 1967 select SYS_SUPPORTS_HOTPLUG_CPU
863 help !! 1968 select CPU_HAS_RIXI
864 This option adds the workaround for <<
865 1969
866 Affected Neoverse-N2 cores could ove !! 1970 config CPU_BMIPS5000
867 data at the base of the buffer (poin !! 1971 bool
868 the event of a WRAP event. !! 1972 select MIPS_CPU_SCACHE
869 !! 1973 select MIPS_L1_CACHE_SHIFT_7
870 Work around the issue by always maki !! 1974 select SYS_SUPPORTS_SMP
871 256 bytes before enabling the buffer !! 1975 select SYS_SUPPORTS_HOTPLUG_CPU
872 the buffer with ETM ignore packets u !! 1976 select CPU_HAS_RIXI
873 1977
874 If unsure, say Y. !! 1978 config SYS_HAS_CPU_LOONGSON64
>> 1979 bool
>> 1980 select CPU_SUPPORTS_CPUFREQ
>> 1981 select CPU_HAS_RIXI
875 1982
876 config ARM64_WORKAROUND_TSB_FLUSH_FAILURE !! 1983 config SYS_HAS_CPU_LOONGSON2E
877 bool 1984 bool
878 1985
879 config ARM64_ERRATUM_2054223 !! 1986 config SYS_HAS_CPU_LOONGSON2F
880 bool "Cortex-A710: 2054223: workaround !! 1987 bool
881 default y !! 1988 select CPU_SUPPORTS_CPUFREQ
882 select ARM64_WORKAROUND_TSB_FLUSH_FAIL !! 1989 select CPU_SUPPORTS_ADDRWINCFG if 64BIT
883 help <<
884 Enable workaround for ARM Cortex-A71 <<
885 1990
886 Affected cores may fail to flush the !! 1991 config SYS_HAS_CPU_LOONGSON1B
887 the PE is in trace prohibited state. !! 1992 bool
888 of the trace cached. <<
889 1993
890 Workaround is to issue two TSB conse !! 1994 config SYS_HAS_CPU_LOONGSON1C
>> 1995 bool
891 1996
892 If unsure, say Y. !! 1997 config SYS_HAS_CPU_MIPS32_R1
>> 1998 bool
893 1999
894 config ARM64_ERRATUM_2067961 !! 2000 config SYS_HAS_CPU_MIPS32_R2
895 bool "Neoverse-N2: 2067961: workaround !! 2001 bool
896 default y <<
897 select ARM64_WORKAROUND_TSB_FLUSH_FAIL <<
898 help <<
899 Enable workaround for ARM Neoverse-N <<
900 2002
901 Affected cores may fail to flush the !! 2003 config SYS_HAS_CPU_MIPS32_R3_5
902 the PE is in trace prohibited state. !! 2004 bool
903 of the trace cached. <<
904 2005
905 Workaround is to issue two TSB conse !! 2006 config SYS_HAS_CPU_MIPS32_R5
>> 2007 bool
>> 2008 select ARCH_HAS_SYNC_DMA_FOR_CPU if DMA_NONCOHERENT
906 2009
907 If unsure, say Y. !! 2010 config SYS_HAS_CPU_MIPS32_R6
>> 2011 bool
>> 2012 select ARCH_HAS_SYNC_DMA_FOR_CPU if DMA_NONCOHERENT
908 2013
909 config ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANG !! 2014 config SYS_HAS_CPU_MIPS64_R1
910 bool 2015 bool
911 2016
912 config ARM64_ERRATUM_2253138 !! 2017 config SYS_HAS_CPU_MIPS64_R2
913 bool "Neoverse-N2: 2253138: workaround !! 2018 bool
914 depends on CORESIGHT_TRBE <<
915 default y <<
916 select ARM64_WORKAROUND_TRBE_WRITE_OUT <<
917 help <<
918 This option adds the workaround for <<
919 2019
920 Affected Neoverse-N2 cores might wri !! 2020 config SYS_HAS_CPU_MIPS64_R6
921 for TRBE. Under some conditions, the !! 2021 bool
922 virtually addressed page following t !! 2022 select ARCH_HAS_SYNC_DMA_FOR_CPU if DMA_NONCOHERENT
923 (i.e., the TRBLIMITR_EL1.LIMIT), ins <<
924 2023
925 Work around this in the driver by al !! 2024 config SYS_HAS_CPU_P5600
926 page beyond the TRBLIMITR_EL1.LIMIT, !! 2025 bool
>> 2026 select ARCH_HAS_SYNC_DMA_FOR_CPU if DMA_NONCOHERENT
927 2027
928 If unsure, say Y. !! 2028 config SYS_HAS_CPU_R3000
>> 2029 bool
929 2030
930 config ARM64_ERRATUM_2224489 !! 2031 config SYS_HAS_CPU_TX39XX
931 bool "Cortex-A710/X2: 2224489: workaro !! 2032 bool
932 depends on CORESIGHT_TRBE <<
933 default y <<
934 select ARM64_WORKAROUND_TRBE_WRITE_OUT <<
935 help <<
936 This option adds the workaround for <<
937 2033
938 Affected Cortex-A710/X2 cores might !! 2034 config SYS_HAS_CPU_VR41XX
939 for TRBE. Under some conditions, the !! 2035 bool
940 virtually addressed page following t <<
941 (i.e., the TRBLIMITR_EL1.LIMIT), ins <<
942 2036
943 Work around this in the driver by al !! 2037 config SYS_HAS_CPU_R4300
944 page beyond the TRBLIMITR_EL1.LIMIT, !! 2038 bool
945 2039
946 If unsure, say Y. !! 2040 config SYS_HAS_CPU_R4X00
>> 2041 bool
947 2042
948 config ARM64_ERRATUM_2441009 !! 2043 config SYS_HAS_CPU_TX49XX
949 bool "Cortex-A510: Completion of affec !! 2044 bool
950 select ARM64_WORKAROUND_REPEAT_TLBI <<
951 help <<
952 This option adds a workaround for AR <<
953 <<
954 Under very rare circumstances, affec <<
955 may not handle a race between a brea <<
956 CPU, and another CPU accessing the s <<
957 store to a page that has been unmapp <<
958 2045
959 Work around this by adding the affec !! 2046 config SYS_HAS_CPU_R5000
960 TLB sequences to be done twice. !! 2047 bool
961 2048
962 If unsure, say N. !! 2049 config SYS_HAS_CPU_R5500
>> 2050 bool
963 2051
964 config ARM64_ERRATUM_2064142 !! 2052 config SYS_HAS_CPU_NEVADA
965 bool "Cortex-A510: 2064142: workaround !! 2053 bool
966 depends on CORESIGHT_TRBE <<
967 default y <<
968 help <<
969 This option adds the workaround for <<
970 2054
971 Affected Cortex-A510 core might fail !! 2055 config SYS_HAS_CPU_R10000
972 TRBE has been disabled. Under some c !! 2056 bool
973 writes into TRBE registers TRBLIMITR !! 2057 select ARCH_HAS_SYNC_DMA_FOR_CPU if DMA_NONCOHERENT
974 and TRBTRG_EL1 will be ignored and w <<
975 <<
976 Work around this in the driver by ex <<
977 is stopped and before performing a s <<
978 registers. <<
979 2058
980 If unsure, say Y. !! 2059 config SYS_HAS_CPU_RM7000
>> 2060 bool
981 2061
982 config ARM64_ERRATUM_2038923 !! 2062 config SYS_HAS_CPU_SB1
983 bool "Cortex-A510: 2038923: workaround !! 2063 bool
984 depends on CORESIGHT_TRBE <<
985 default y <<
986 help <<
987 This option adds the workaround for <<
988 2064
989 Affected Cortex-A510 core might caus !! 2065 config SYS_HAS_CPU_CAVIUM_OCTEON
990 prohibited within the CPU. As a resu !! 2066 bool
991 might be corrupted. This happens aft <<
992 TRBLIMITR_EL1.E, followed by just a <<
993 execution changes from a context, in <<
994 isn't, or vice versa. In these menti <<
995 is prohibited is inconsistent betwee <<
996 the trace buffer state might be corr <<
997 <<
998 Work around this in the driver by pr <<
999 trace is prohibited or not based on <<
1000 change to TRBLIMITR_EL1.E with at l <<
1001 two ISB instructions if no ERET is <<
1002 2067
1003 If unsure, say Y. !! 2068 config SYS_HAS_CPU_BMIPS
>> 2069 bool
1004 2070
1005 config ARM64_ERRATUM_1902691 !! 2071 config SYS_HAS_CPU_BMIPS32_3300
1006 bool "Cortex-A510: 1902691: workaroun !! 2072 bool
1007 depends on CORESIGHT_TRBE !! 2073 select SYS_HAS_CPU_BMIPS
1008 default y <<
1009 help <<
1010 This option adds the workaround for <<
1011 2074
1012 Affected Cortex-A510 core might cau !! 2075 config SYS_HAS_CPU_BMIPS4350
1013 into the memory. Effectively TRBE i !! 2076 bool
1014 trace data. !! 2077 select SYS_HAS_CPU_BMIPS
1015 <<
1016 Work around this problem in the dri <<
1017 affected cpus. The firmware must ha <<
1018 on such implementations. This will <<
1019 do this already. <<
1020 2078
1021 If unsure, say Y. !! 2079 config SYS_HAS_CPU_BMIPS4380
>> 2080 bool
>> 2081 select SYS_HAS_CPU_BMIPS
1022 2082
1023 config ARM64_ERRATUM_2457168 !! 2083 config SYS_HAS_CPU_BMIPS5000
1024 bool "Cortex-A510: 2457168: workaroun !! 2084 bool
1025 depends on ARM64_AMU_EXTN !! 2085 select SYS_HAS_CPU_BMIPS
1026 default y !! 2086 select ARCH_HAS_SYNC_DMA_FOR_CPU
1027 help <<
1028 This option adds the workaround for <<
1029 2087
1030 The AMU counter AMEVCNTR01 (constan !! 2088 config SYS_HAS_CPU_XLR
1031 as the system counter. On affected !! 2089 bool
1032 incorrectly giving a significantly <<
1033 <<
1034 Work around this problem by returni <<
1035 key locations that results in disab <<
1036 is the same to firmware disabling a <<
1037 2090
1038 If unsure, say Y. !! 2091 config SYS_HAS_CPU_XLP
>> 2092 bool
1039 2093
1040 config ARM64_ERRATUM_2645198 !! 2094 #
1041 bool "Cortex-A715: 2645198: Workaroun !! 2095 # CPU may reorder R->R, R->W, W->R, W->W
1042 default y !! 2096 # Reordering beyond LL and SC is handled in WEAK_REORDERING_BEYOND_LLSC
1043 help !! 2097 #
1044 This option adds the workaround for !! 2098 config WEAK_ORDERING
>> 2099 bool
1045 2100
1046 If a Cortex-A715 cpu sees a page ma !! 2101 #
1047 to non-executable, it may corrupt t !! 2102 # CPU may reorder reads and writes beyond LL/SC
1048 next instruction abort caused by pe !! 2103 # CPU may reorder R->LL, R->LL, W->LL, W->LL, R->SC, R->SC, W->SC, W->SC
1049 !! 2104 #
1050 Only user-space does executable to !! 2105 config WEAK_REORDERING_BEYOND_LLSC
1051 mprotect() system call. Workaround !! 2106 bool
1052 TLB invalidation, for all changes t !! 2107 endmenu
1053 2108
1054 If unsure, say Y. !! 2109 #
>> 2110 # These two indicate any level of the MIPS32 and MIPS64 architecture
>> 2111 #
>> 2112 config CPU_MIPS32
>> 2113 bool
>> 2114 default y if CPU_MIPS32_R1 || CPU_MIPS32_R2 || CPU_MIPS32_R5 || \
>> 2115 CPU_MIPS32_R6 || CPU_P5600
1055 2116
1056 config ARM64_WORKAROUND_SPECULATIVE_UNPRIV_LO !! 2117 config CPU_MIPS64
1057 bool 2118 bool
>> 2119 default y if CPU_MIPS64_R1 || CPU_MIPS64_R2 || CPU_MIPS64_R5 || \
>> 2120 CPU_MIPS64_R6 || CPU_LOONGSON64 || CPU_CAVIUM_OCTEON
1058 2121
1059 config ARM64_ERRATUM_2966298 !! 2122 #
1060 bool "Cortex-A520: 2966298: workaroun !! 2123 # These indicate the revision of the architecture
1061 select ARM64_WORKAROUND_SPECULATIVE_U !! 2124 #
1062 default y !! 2125 config CPU_MIPSR1
1063 help !! 2126 bool
1064 This option adds the workaround for !! 2127 default y if CPU_MIPS32_R1 || CPU_MIPS64_R1
1065 2128
1066 On an affected Cortex-A520 core, a !! 2129 config CPU_MIPSR2
1067 load might leak data from a privile !! 2130 bool
>> 2131 default y if CPU_MIPS32_R2 || CPU_MIPS64_R2 || CPU_CAVIUM_OCTEON
>> 2132 select CPU_HAS_RIXI
>> 2133 select CPU_HAS_DIEI if !CPU_DIEI_BROKEN
>> 2134 select MIPS_SPRAM
1068 2135
1069 Work around this problem by executi !! 2136 config CPU_MIPSR5
>> 2137 bool
>> 2138 default y if CPU_MIPS32_R5 || CPU_MIPS64_R5 || CPU_P5600
>> 2139 select CPU_HAS_RIXI
>> 2140 select CPU_HAS_DIEI if !CPU_DIEI_BROKEN
>> 2141 select MIPS_SPRAM
1070 2142
1071 If unsure, say Y. !! 2143 config CPU_MIPSR6
>> 2144 bool
>> 2145 default y if CPU_MIPS32_R6 || CPU_MIPS64_R6
>> 2146 select CPU_HAS_RIXI
>> 2147 select CPU_HAS_DIEI if !CPU_DIEI_BROKEN
>> 2148 select HAVE_ARCH_BITREVERSE
>> 2149 select MIPS_ASID_BITS_VARIABLE
>> 2150 select MIPS_CRC_SUPPORT
>> 2151 select MIPS_SPRAM
1072 2152
1073 config ARM64_ERRATUM_3117295 !! 2153 config TARGET_ISA_REV
1074 bool "Cortex-A510: 3117295: workaroun !! 2154 int
1075 select ARM64_WORKAROUND_SPECULATIVE_U !! 2155 default 1 if CPU_MIPSR1
1076 default y !! 2156 default 2 if CPU_MIPSR2
>> 2157 default 5 if CPU_MIPSR5
>> 2158 default 6 if CPU_MIPSR6
>> 2159 default 0
1077 help 2160 help
1078 This option adds the workaround for !! 2161 Reflects the ISA revision being targeted by the kernel build. This
>> 2162 is effectively the Kconfig equivalent of MIPS_ISA_REV.
1079 2163
1080 On an affected Cortex-A510 core, a !! 2164 config EVA
1081 load might leak data from a privile !! 2165 bool
1082 2166
1083 Work around this problem by executi !! 2167 config XPA
>> 2168 bool
1084 2169
1085 If unsure, say Y. !! 2170 config SYS_SUPPORTS_32BIT_KERNEL
>> 2171 bool
>> 2172 config SYS_SUPPORTS_64BIT_KERNEL
>> 2173 bool
>> 2174 config CPU_SUPPORTS_32BIT_KERNEL
>> 2175 bool
>> 2176 config CPU_SUPPORTS_64BIT_KERNEL
>> 2177 bool
>> 2178 config CPU_SUPPORTS_CPUFREQ
>> 2179 bool
>> 2180 config CPU_SUPPORTS_ADDRWINCFG
>> 2181 bool
>> 2182 config CPU_SUPPORTS_HUGEPAGES
>> 2183 bool
>> 2184 depends on !(32BIT && (ARCH_PHYS_ADDR_T_64BIT || EVA))
>> 2185 config MIPS_PGD_C0_CONTEXT
>> 2186 bool
>> 2187 depends on 64BIT
>> 2188 default y if (CPU_MIPSR2 || CPU_MIPSR6) && !CPU_XLP
1086 2189
1087 config ARM64_ERRATUM_3194386 !! 2190 #
1088 bool "Cortex-*/Neoverse-*: workaround !! 2191 # Set to y for ptrace access to watch registers.
1089 default y !! 2192 #
1090 help !! 2193 config HARDWARE_WATCHPOINTS
1091 This option adds the workaround for !! 2194 bool
>> 2195 default y if CPU_MIPSR1 || CPU_MIPSR2 || CPU_MIPSR6
1092 2196
1093 * ARM Cortex-A76 erratum 3324349 !! 2197 menu "Kernel type"
1094 * ARM Cortex-A77 erratum 3324348 <<
1095 * ARM Cortex-A78 erratum 3324344 <<
1096 * ARM Cortex-A78C erratum 3324346 <<
1097 * ARM Cortex-A78C erratum 3324347 <<
1098 * ARM Cortex-A710 erratam 3324338 <<
1099 * ARM Cortex-A715 errartum 3456084 <<
1100 * ARM Cortex-A720 erratum 3456091 <<
1101 * ARM Cortex-A725 erratum 3456106 <<
1102 * ARM Cortex-X1 erratum 3324344 <<
1103 * ARM Cortex-X1C erratum 3324346 <<
1104 * ARM Cortex-X2 erratum 3324338 <<
1105 * ARM Cortex-X3 erratum 3324335 <<
1106 * ARM Cortex-X4 erratum 3194386 <<
1107 * ARM Cortex-X925 erratum 3324334 <<
1108 * ARM Neoverse-N1 erratum 3324349 <<
1109 * ARM Neoverse N2 erratum 3324339 <<
1110 * ARM Neoverse-N3 erratum 3456111 <<
1111 * ARM Neoverse-V1 erratum 3324341 <<
1112 * ARM Neoverse V2 erratum 3324336 <<
1113 * ARM Neoverse-V3 erratum 3312417 <<
1114 <<
1115 On affected cores "MSR SSBS, #0" in <<
1116 subsequent speculative instructions <<
1117 speculative store bypassing. <<
1118 <<
1119 Work around this problem by placing <<
1120 Instruction Synchronization Barrier <<
1121 SSBS. The presence of the SSBS spec <<
1122 from hwcaps and EL0 reads of ID_AA6 <<
1123 will use the PR_SPEC_STORE_BYPASS p <<
1124 2198
1125 If unsure, say Y. !! 2199 choice
>> 2200 prompt "Kernel code model"
>> 2201 help
>> 2202 You should only select this option if you have a workload that
>> 2203 actually benefits from 64-bit processing or if your machine has
>> 2204 large memory. You will only be presented a single option in this
>> 2205 menu if your system does not support both 32-bit and 64-bit kernels.
>> 2206
>> 2207 config 32BIT
>> 2208 bool "32-bit kernel"
>> 2209 depends on CPU_SUPPORTS_32BIT_KERNEL && SYS_SUPPORTS_32BIT_KERNEL
>> 2210 select TRAD_SIGNALS
>> 2211 help
>> 2212 Select this option if you want to build a 32-bit kernel.
1126 2213
1127 config CAVIUM_ERRATUM_22375 !! 2214 config 64BIT
1128 bool "Cavium erratum 22375, 24313" !! 2215 bool "64-bit kernel"
1129 default y !! 2216 depends on CPU_SUPPORTS_64BIT_KERNEL && SYS_SUPPORTS_64BIT_KERNEL
1130 help 2217 help
1131 Enable workaround for errata 22375 !! 2218 Select this option if you want to build a 64-bit kernel.
1132 2219
1133 This implements two gicv3-its errat !! 2220 endchoice
1134 with a small impact affecting only <<
1135 2221
1136 erratum 22375: only alloc 8MB tab !! 2222 config MIPS_VA_BITS_48
1137 erratum 24313: ignore memory acce !! 2223 bool "48 bits virtual memory"
>> 2224 depends on 64BIT
>> 2225 help
>> 2226 Support a maximum at least 48 bits of application virtual
>> 2227 memory. Default is 40 bits or less, depending on the CPU.
>> 2228 For page sizes 16k and above, this option results in a small
>> 2229 memory overhead for page tables. For 4k page size, a fourth
>> 2230 level of page tables is added which imposes both a memory
>> 2231 overhead as well as slower TLB fault handling.
1138 2232
1139 The fixes are in ITS initialization !! 2233 If unsure, say N.
1140 type and table size provided by the <<
1141 2234
1142 If unsure, say Y. !! 2235 choice
>> 2236 prompt "Kernel page size"
>> 2237 default PAGE_SIZE_4KB
1143 2238
1144 config CAVIUM_ERRATUM_23144 !! 2239 config PAGE_SIZE_4KB
1145 bool "Cavium erratum 23144: ITS SYNC !! 2240 bool "4kB"
1146 depends on NUMA !! 2241 depends on !CPU_LOONGSON2EF && !CPU_LOONGSON64
1147 default y !! 2242 help
1148 help !! 2243 This option select the standard 4kB Linux page size. On some
1149 ITS SYNC command hang for cross nod !! 2244 R3000-family processors this is the only available page size. Using
>> 2245 4kB page size will minimize memory consumption and is therefore
>> 2246 recommended for low memory systems.
>> 2247
>> 2248 config PAGE_SIZE_8KB
>> 2249 bool "8kB"
>> 2250 depends on CPU_CAVIUM_OCTEON
>> 2251 depends on !MIPS_VA_BITS_48
>> 2252 help
>> 2253 Using 8kB page size will result in higher performance kernel at
>> 2254 the price of higher memory consumption. This option is available
>> 2255 only on cnMIPS processors. Note that you will need a suitable Linux
>> 2256 distribution to support this.
>> 2257
>> 2258 config PAGE_SIZE_16KB
>> 2259 bool "16kB"
>> 2260 depends on !CPU_R3000 && !CPU_TX39XX
>> 2261 help
>> 2262 Using 16kB page size will result in higher performance kernel at
>> 2263 the price of higher memory consumption. This option is available on
>> 2264 all non-R3000 family processors. Note that you will need a suitable
>> 2265 Linux distribution to support this.
>> 2266
>> 2267 config PAGE_SIZE_32KB
>> 2268 bool "32kB"
>> 2269 depends on CPU_CAVIUM_OCTEON
>> 2270 depends on !MIPS_VA_BITS_48
>> 2271 help
>> 2272 Using 32kB page size will result in higher performance kernel at
>> 2273 the price of higher memory consumption. This option is available
>> 2274 only on cnMIPS cores. Note that you will need a suitable Linux
>> 2275 distribution to support this.
>> 2276
>> 2277 config PAGE_SIZE_64KB
>> 2278 bool "64kB"
>> 2279 depends on !CPU_R3000 && !CPU_TX39XX
>> 2280 help
>> 2281 Using 64kB page size will result in higher performance kernel at
>> 2282 the price of higher memory consumption. This option is available on
>> 2283 all non-R3000 family processor. Not that at the time of this
>> 2284 writing this option is still high experimental.
1150 2285
1151 If unsure, say Y. !! 2286 endchoice
1152 2287
1153 config CAVIUM_ERRATUM_23154 !! 2288 config FORCE_MAX_ZONEORDER
1154 bool "Cavium errata 23154 and 38545: !! 2289 int "Maximum zone order"
1155 default y !! 2290 range 14 64 if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_64KB
1156 help !! 2291 default "14" if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_64KB
1157 The ThunderX GICv3 implementation r !! 2292 range 13 64 if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_32KB
1158 reading the IAR status to ensure da !! 2293 default "13" if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_32KB
1159 (access to icc_iar1_el1 is not sync !! 2294 range 12 64 if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_16KB
1160 !! 2295 default "12" if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_16KB
1161 It also suffers from erratum 38545 !! 2296 range 0 64
1162 OcteonTX and OcteonTX2), resulting !! 2297 default "11"
1163 spuriously presented to the CPU int !! 2298 help
>> 2299 The kernel memory allocator divides physically contiguous memory
>> 2300 blocks into "zones", where each zone is a power of two number of
>> 2301 pages. This option selects the largest power of two that the kernel
>> 2302 keeps in the memory allocator. If you need to allocate very large
>> 2303 blocks of physically contiguous memory, then you may need to
>> 2304 increase this value.
1164 2305
1165 If unsure, say Y. !! 2306 This config option is actually maximum order plus one. For example,
>> 2307 a value of 11 means that the largest free memory block is 2^10 pages.
1166 2308
1167 config CAVIUM_ERRATUM_27456 !! 2309 The page size is not necessarily 4KB. Keep this in mind
1168 bool "Cavium erratum 27456: Broadcast !! 2310 when choosing a value for this option.
1169 default y <<
1170 help <<
1171 On ThunderX T88 pass 1.x through 2. <<
1172 instructions may cause the icache t <<
1173 contains data for a non-current ASI <<
1174 invalidate the icache when changing <<
1175 2311
1176 If unsure, say Y. !! 2312 config BOARD_SCACHE
>> 2313 bool
1177 2314
1178 config CAVIUM_ERRATUM_30115 !! 2315 config IP22_CPU_SCACHE
1179 bool "Cavium erratum 30115: Guest may !! 2316 bool
1180 default y !! 2317 select BOARD_SCACHE
1181 help <<
1182 On ThunderX T88 pass 1.x through 2. <<
1183 1.2, and T83 Pass 1.0, KVM guest ex <<
1184 interrupts in host. Trapping both G <<
1185 accesses sidesteps the issue. <<
1186 2318
1187 If unsure, say Y. !! 2319 #
>> 2320 # Support for a MIPS32 / MIPS64 style S-caches
>> 2321 #
>> 2322 config MIPS_CPU_SCACHE
>> 2323 bool
>> 2324 select BOARD_SCACHE
1188 2325
1189 config CAVIUM_TX2_ERRATUM_219 !! 2326 config R5000_CPU_SCACHE
1190 bool "Cavium ThunderX2 erratum 219: P !! 2327 bool
1191 default y !! 2328 select BOARD_SCACHE
1192 help <<
1193 On Cavium ThunderX2, a load, store <<
1194 TTBR update and the corresponding c <<
1195 cause a spurious Data Abort to be d <<
1196 the CPU core. <<
1197 <<
1198 Work around the issue by avoiding t <<
1199 trapping KVM guest TTBRx_EL1 writes <<
1200 trap handler performs the correspon <<
1201 instruction and ensures context syn <<
1202 exception return. <<
1203 2329
1204 If unsure, say Y. !! 2330 config RM7000_CPU_SCACHE
>> 2331 bool
>> 2332 select BOARD_SCACHE
1205 2333
1206 config FUJITSU_ERRATUM_010001 !! 2334 config SIBYTE_DMA_PAGEOPS
1207 bool "Fujitsu-A64FX erratum E#010001: !! 2335 bool "Use DMA to clear/copy pages"
1208 default y !! 2336 depends on CPU_SB1
1209 help 2337 help
1210 This option adds a workaround for F !! 2338 Instead of using the CPU to zero and copy pages, use a Data Mover
1211 On some variants of the Fujitsu-A64 !! 2339 channel. These DMA channels are otherwise unused by the standard
1212 accesses may cause undefined fault !! 2340 SiByte Linux port. Seems to give a small performance benefit.
1213 This fault occurs under a specific <<
1214 load/store instruction performs an <<
1215 case-1 TTBR0_EL1 with TCR_EL1.NFD0 <<
1216 case-2 TTBR0_EL2 with TCR_EL2.NFD0 <<
1217 case-3 TTBR1_EL1 with TCR_EL1.NFD1 <<
1218 case-4 TTBR1_EL2 with TCR_EL2.NFD1 <<
1219 2341
1220 The workaround is to ensure these b !! 2342 config CPU_HAS_PREFETCH
1221 The workaround only affects the Fuj !! 2343 bool
1222 2344
1223 If unsure, say Y. !! 2345 config CPU_GENERIC_DUMP_TLB
>> 2346 bool
>> 2347 default y if !(CPU_R3000 || CPU_TX39XX)
1224 2348
1225 config HISILICON_ERRATUM_161600802 !! 2349 config MIPS_FP_SUPPORT
1226 bool "Hip07 161600802: Erroneous redi !! 2350 bool "Floating Point support" if EXPERT
1227 default y 2351 default y
1228 help 2352 help
1229 The HiSilicon Hip07 SoC uses the wr !! 2353 Select y to include support for floating point in the kernel
1230 when issued ITS commands such as VM !! 2354 including initialization of FPU hardware, FP context save & restore
1231 a 128kB offset to be applied to the !! 2355 and emulation of an FPU where necessary. Without this support any
>> 2356 userland program attempting to use floating point instructions will
>> 2357 receive a SIGILL.
1232 2358
1233 If unsure, say Y. !! 2359 If you know that your userland will not attempt to use floating point
>> 2360 instructions then you can say n here to shrink the kernel a little.
1234 2361
1235 config QCOM_FALKOR_ERRATUM_1003 !! 2362 If unsure, say y.
1236 bool "Falkor E1003: Incorrect transla <<
1237 default y <<
1238 help <<
1239 On Falkor v1, an incorrect ASID may <<
1240 and BADDR are changed together in T <<
1241 in TTBR1_EL1, this situation only o <<
1242 then only for entries in the walk c <<
1243 is unchanged. Work around the errat <<
1244 entries for the trampoline before e <<
1245 2363
1246 config QCOM_FALKOR_ERRATUM_1009 !! 2364 config CPU_R2300_FPU
1247 bool "Falkor E1009: Prematurely compl !! 2365 bool
1248 default y !! 2366 depends on MIPS_FP_SUPPORT
1249 select ARM64_WORKAROUND_REPEAT_TLBI !! 2367 default y if CPU_R3000 || CPU_TX39XX
1250 help <<
1251 On Falkor v1, the CPU may premature <<
1252 TLBI xxIS invalidate maintenance op <<
1253 one more time to fix the issue. <<
1254 2368
1255 If unsure, say Y. !! 2369 config CPU_R3K_TLB
>> 2370 bool
1256 2371
1257 config QCOM_QDF2400_ERRATUM_0065 !! 2372 config CPU_R4K_FPU
1258 bool "QDF2400 E0065: Incorrect GITS_T !! 2373 bool
1259 default y !! 2374 depends on MIPS_FP_SUPPORT
1260 help !! 2375 default y if !CPU_R2300_FPU
1261 On Qualcomm Datacenter Technologies <<
1262 ITE size incorrectly. The GITS_TYPE <<
1263 been indicated as 16Bytes (0xf), no <<
1264 2376
1265 If unsure, say Y. !! 2377 config CPU_R4K_CACHE_TLB
>> 2378 bool
>> 2379 default y if !(CPU_R3K_TLB || CPU_SB1 || CPU_CAVIUM_OCTEON)
1266 2380
1267 config QCOM_FALKOR_ERRATUM_E1041 !! 2381 config MIPS_MT_SMP
1268 bool "Falkor E1041: Speculative instr !! 2382 bool "MIPS MT SMP support (1 TC on each available VPE)"
1269 default y 2383 default y
1270 help !! 2384 depends on SYS_SUPPORTS_MULTITHREADING && !CPU_MIPSR6 && !CPU_MICROMIPS
1271 Falkor CPU may speculatively fetch !! 2385 select CPU_MIPSR2_IRQ_VI
1272 memory location when MMU translatio !! 2386 select CPU_MIPSR2_IRQ_EI
1273 to SCTLR_ELn[M]=0. Prefix an ISB in !! 2387 select SYNC_R4K
>> 2388 select MIPS_MT
>> 2389 select SMP
>> 2390 select SMP_UP
>> 2391 select SYS_SUPPORTS_SMP
>> 2392 select SYS_SUPPORTS_SCHED_SMT
>> 2393 select MIPS_PERF_SHARED_TC_COUNTERS
>> 2394 help
>> 2395 This is a kernel model which is known as SMVP. This is supported
>> 2396 on cores with the MT ASE and uses the available VPEs to implement
>> 2397 virtual processors which supports SMP. This is equivalent to the
>> 2398 Intel Hyperthreading feature. For further information go to
>> 2399 <http://www.imgtec.com/mips/mips-multithreading.asp>.
1274 2400
1275 If unsure, say Y. !! 2401 config MIPS_MT
>> 2402 bool
1276 2403
1277 config NVIDIA_CARMEL_CNP_ERRATUM !! 2404 config SCHED_SMT
1278 bool "NVIDIA Carmel CNP: CNP on Carme !! 2405 bool "SMT (multithreading) scheduler support"
1279 default y !! 2406 depends on SYS_SUPPORTS_SCHED_SMT
>> 2407 default n
1280 help 2408 help
1281 If CNP is enabled on Carmel cores, !! 2409 SMT scheduler support improves the CPU scheduler's decision making
1282 invalidate shared TLB entries insta !! 2410 when dealing with MIPS MT enabled cores at a cost of slightly
1283 on standard ARM cores. !! 2411 increased overhead in some places. If unsure say N here.
1284 <<
1285 If unsure, say Y. <<
1286 2412
1287 config ROCKCHIP_ERRATUM_3588001 !! 2413 config SYS_SUPPORTS_SCHED_SMT
1288 bool "Rockchip 3588001: GIC600 can no !! 2414 bool
1289 default y <<
1290 help <<
1291 The Rockchip RK3588 GIC600 SoC inte <<
1292 This means, that its sharability fe <<
1293 is supported by the IP itself. <<
1294 2415
1295 If unsure, say Y. !! 2416 config SYS_SUPPORTS_MULTITHREADING
>> 2417 bool
1296 2418
1297 config SOCIONEXT_SYNQUACER_PREITS !! 2419 config MIPS_MT_FPAFF
1298 bool "Socionext Synquacer: Workaround !! 2420 bool "Dynamic FPU affinity for FP-intensive threads"
1299 default y 2421 default y
1300 help !! 2422 depends on MIPS_MT_SMP
1301 Socionext Synquacer SoCs implement <<
1302 MSI doorbell writes with non-zero v <<
1303 <<
1304 If unsure, say Y. <<
1305 <<
1306 endmenu # "ARM errata workarounds via the alt <<
1307 2423
1308 choice !! 2424 config MIPSR2_TO_R6_EMULATOR
1309 prompt "Page size" !! 2425 bool "MIPS R2-to-R6 emulator"
1310 default ARM64_4K_PAGES !! 2426 depends on CPU_MIPSR6
>> 2427 depends on MIPS_FP_SUPPORT
>> 2428 default y
1311 help 2429 help
1312 Page size (translation granule) con !! 2430 Choose this option if you want to run non-R6 MIPS userland code.
>> 2431 Even if you say 'Y' here, the emulator will still be disabled by
>> 2432 default. You can enable it using the 'mipsr2emu' kernel option.
>> 2433 The only reason this is a build-time option is to save ~14K from the
>> 2434 final kernel image.
1313 2435
1314 config ARM64_4K_PAGES !! 2436 config SYS_SUPPORTS_VPE_LOADER
1315 bool "4KB" !! 2437 bool
1316 select HAVE_PAGE_SIZE_4KB !! 2438 depends on SYS_SUPPORTS_MULTITHREADING
1317 help 2439 help
1318 This feature enables 4KB pages supp !! 2440 Indicates that the platform supports the VPE loader, and provides
>> 2441 physical_memsize.
1319 2442
1320 config ARM64_16K_PAGES !! 2443 config MIPS_VPE_LOADER
1321 bool "16KB" !! 2444 bool "VPE loader support."
1322 select HAVE_PAGE_SIZE_16KB !! 2445 depends on SYS_SUPPORTS_VPE_LOADER && MODULES
>> 2446 select CPU_MIPSR2_IRQ_VI
>> 2447 select CPU_MIPSR2_IRQ_EI
>> 2448 select MIPS_MT
1323 help 2449 help
1324 The system will use 16KB pages supp !! 2450 Includes a loader for loading an elf relocatable object
1325 requires applications compiled with !! 2451 onto another VPE and running it.
1326 aligned segments. <<
1327 2452
1328 config ARM64_64K_PAGES !! 2453 config MIPS_VPE_LOADER_CMP
1329 bool "64KB" !! 2454 bool
1330 select HAVE_PAGE_SIZE_64KB !! 2455 default "y"
1331 help !! 2456 depends on MIPS_VPE_LOADER && MIPS_CMP
1332 This feature enables 64KB pages sup <<
1333 allowing only two levels of page ta <<
1334 look-up. AArch32 emulation requires <<
1335 with 64K aligned segments. <<
1336 2457
1337 endchoice !! 2458 config MIPS_VPE_LOADER_MT
>> 2459 bool
>> 2460 default "y"
>> 2461 depends on MIPS_VPE_LOADER && !MIPS_CMP
1338 2462
1339 choice !! 2463 config MIPS_VPE_LOADER_TOM
1340 prompt "Virtual address space size" !! 2464 bool "Load VPE program into memory hidden from linux"
1341 default ARM64_VA_BITS_52 !! 2465 depends on MIPS_VPE_LOADER
>> 2466 default y
1342 help 2467 help
1343 Allows choosing one of multiple pos !! 2468 The loader can use memory that is present but has been hidden from
1344 space sizes. The level of translati !! 2469 Linux using the kernel command line option "mem=xxMB". It's up to
1345 a combination of page size and virt !! 2470 you to ensure the amount you put in the option and the space your
1346 !! 2471 program requires is less or equal to the amount physically present.
1347 config ARM64_VA_BITS_36 <<
1348 bool "36-bit" if EXPERT <<
1349 depends on PAGE_SIZE_16KB <<
1350 <<
1351 config ARM64_VA_BITS_39 <<
1352 bool "39-bit" <<
1353 depends on PAGE_SIZE_4KB <<
1354 <<
1355 config ARM64_VA_BITS_42 <<
1356 bool "42-bit" <<
1357 depends on PAGE_SIZE_64KB <<
1358 <<
1359 config ARM64_VA_BITS_47 <<
1360 bool "47-bit" <<
1361 depends on PAGE_SIZE_16KB <<
1362 <<
1363 config ARM64_VA_BITS_48 <<
1364 bool "48-bit" <<
1365 <<
1366 config ARM64_VA_BITS_52 <<
1367 bool "52-bit" <<
1368 depends on ARM64_PAN || !ARM64_SW_TTB <<
1369 help <<
1370 Enable 52-bit virtual addressing fo <<
1371 requested via a hint to mmap(). The <<
1372 virtual addresses for its own mappi <<
1373 this feature is available, otherwis <<
1374 <<
1375 NOTE: Enabling 52-bit virtual addre <<
1376 ARMv8.3 Pointer Authentication will <<
1377 reduced from 7 bits to 3 bits, whic <<
1378 impact on its susceptibility to bru <<
1379 <<
1380 If unsure, select 48-bit virtual ad <<
1381 2472
1382 endchoice !! 2473 config MIPS_VPE_APSP_API
>> 2474 bool "Enable support for AP/SP API (RTLX)"
>> 2475 depends on MIPS_VPE_LOADER
1383 2476
1384 config ARM64_FORCE_52BIT !! 2477 config MIPS_VPE_APSP_API_CMP
1385 bool "Force 52-bit virtual addresses !! 2478 bool
1386 depends on ARM64_VA_BITS_52 && EXPERT !! 2479 default "y"
1387 help !! 2480 depends on MIPS_VPE_APSP_API && MIPS_CMP
1388 For systems with 52-bit userspace V <<
1389 to maintain compatibility with olde <<
1390 unless a hint is supplied to mmap. <<
1391 <<
1392 This configuration option disables <<
1393 forces all userspace addresses to b <<
1394 should only enable this configurati <<
1395 memory management code. If unsure s <<
1396 2481
1397 config ARM64_VA_BITS !! 2482 config MIPS_VPE_APSP_API_MT
1398 int !! 2483 bool
1399 default 36 if ARM64_VA_BITS_36 !! 2484 default "y"
1400 default 39 if ARM64_VA_BITS_39 !! 2485 depends on MIPS_VPE_APSP_API && !MIPS_CMP
1401 default 42 if ARM64_VA_BITS_42 <<
1402 default 47 if ARM64_VA_BITS_47 <<
1403 default 48 if ARM64_VA_BITS_48 <<
1404 default 52 if ARM64_VA_BITS_52 <<
1405 2486
1406 choice !! 2487 config MIPS_CMP
1407 prompt "Physical address space size" !! 2488 bool "MIPS CMP framework support (DEPRECATED)"
1408 default ARM64_PA_BITS_48 !! 2489 depends on SYS_SUPPORTS_MIPS_CMP && !CPU_MIPSR6
>> 2490 select SMP
>> 2491 select SYNC_R4K
>> 2492 select SYS_SUPPORTS_SMP
>> 2493 select WEAK_ORDERING
>> 2494 default n
1409 help 2495 help
1410 Choose the maximum physical address !! 2496 Select this if you are using a bootloader which implements the "CMP
1411 support. !! 2497 framework" protocol (ie. YAMON) and want your kernel to make use of
>> 2498 its ability to start secondary CPUs.
>> 2499
>> 2500 Unless you have a specific need, you should use CONFIG_MIPS_CPS
>> 2501 instead of this.
>> 2502
>> 2503 config MIPS_CPS
>> 2504 bool "MIPS Coherent Processing System support"
>> 2505 depends on SYS_SUPPORTS_MIPS_CPS
>> 2506 select MIPS_CM
>> 2507 select MIPS_CPS_PM if HOTPLUG_CPU
>> 2508 select SMP
>> 2509 select SYNC_R4K if (CEVT_R4K || CSRC_R4K)
>> 2510 select SYS_SUPPORTS_HOTPLUG_CPU
>> 2511 select SYS_SUPPORTS_SCHED_SMT if CPU_MIPSR6
>> 2512 select SYS_SUPPORTS_SMP
>> 2513 select WEAK_ORDERING
>> 2514 select GENERIC_IRQ_MIGRATION if HOTPLUG_CPU
>> 2515 help
>> 2516 Select this if you wish to run an SMP kernel across multiple cores
>> 2517 within a MIPS Coherent Processing System. When this option is
>> 2518 enabled the kernel will probe for other cores and boot them with
>> 2519 no external assistance. It is safe to enable this when hardware
>> 2520 support is unavailable.
1412 2521
1413 config ARM64_PA_BITS_48 !! 2522 config MIPS_CPS_PM
1414 bool "48-bit" !! 2523 depends on MIPS_CPS
1415 depends on ARM64_64K_PAGES || !ARM64_ !! 2524 bool
1416 <<
1417 config ARM64_PA_BITS_52 <<
1418 bool "52-bit" <<
1419 depends on ARM64_64K_PAGES || ARM64_V <<
1420 depends on ARM64_PAN || !ARM64_SW_TTB <<
1421 help <<
1422 Enable support for a 52-bit physica <<
1423 part of the ARMv8.2-LPA extension. <<
1424 <<
1425 With this enabled, the kernel will <<
1426 do not support ARMv8.2-LPA, but wit <<
1427 minor performance overhead). <<
1428 2525
1429 endchoice !! 2526 config MIPS_CM
>> 2527 bool
>> 2528 select MIPS_CPC
1430 2529
1431 config ARM64_PA_BITS !! 2530 config MIPS_CPC
1432 int !! 2531 bool
1433 default 48 if ARM64_PA_BITS_48 <<
1434 default 52 if ARM64_PA_BITS_52 <<
1435 2532
1436 config ARM64_LPA2 !! 2533 config SB1_PASS_2_WORKAROUNDS
1437 def_bool y !! 2534 bool
1438 depends on ARM64_PA_BITS_52 && !ARM64 !! 2535 depends on CPU_SB1 && (CPU_SB1_PASS_2_2 || CPU_SB1_PASS_2)
>> 2536 default y
>> 2537
>> 2538 config SB1_PASS_2_1_WORKAROUNDS
>> 2539 bool
>> 2540 depends on CPU_SB1 && CPU_SB1_PASS_2
>> 2541 default y
1439 2542
1440 choice 2543 choice
1441 prompt "Endianness" !! 2544 prompt "SmartMIPS or microMIPS ASE support"
1442 default CPU_LITTLE_ENDIAN <<
1443 help <<
1444 Select the endianness of data acces <<
1445 applications will need to be compil <<
1446 that is selected here. <<
1447 2545
1448 config CPU_BIG_ENDIAN !! 2546 config CPU_NEEDS_NO_SMARTMIPS_OR_MICROMIPS
1449 bool "Build big-endian kernel" !! 2547 bool "None"
1450 # https://github.com/llvm/llvm-projec <<
1451 depends on AS_IS_GNU || AS_VERSION >= <<
1452 help 2548 help
1453 Say Y if you plan on running a kern !! 2549 Select this if you want neither microMIPS nor SmartMIPS support
1454 2550
1455 config CPU_LITTLE_ENDIAN !! 2551 config CPU_HAS_SMARTMIPS
1456 bool "Build little-endian kernel" !! 2552 depends on SYS_SUPPORTS_SMARTMIPS
>> 2553 bool "SmartMIPS"
>> 2554 help
>> 2555 SmartMIPS is a extension of the MIPS32 architecture aimed at
>> 2556 increased security at both hardware and software level for
>> 2557 smartcards. Enabling this option will allow proper use of the
>> 2558 SmartMIPS instructions by Linux applications. However a kernel with
>> 2559 this option will not work on a MIPS core without SmartMIPS core. If
>> 2560 you don't know you probably don't have SmartMIPS and should say N
>> 2561 here.
>> 2562
>> 2563 config CPU_MICROMIPS
>> 2564 depends on 32BIT && SYS_SUPPORTS_MICROMIPS && !CPU_MIPSR6
>> 2565 bool "microMIPS"
1457 help 2566 help
1458 Say Y if you plan on running a kern !! 2567 When this option is enabled the kernel will be built using the
1459 This is usually the case for distri !! 2568 microMIPS ISA
1460 2569
1461 endchoice 2570 endchoice
1462 2571
1463 config SCHED_MC !! 2572 config CPU_HAS_MSA
1464 bool "Multi-core scheduler support" !! 2573 bool "Support for the MIPS SIMD Architecture"
1465 help !! 2574 depends on CPU_SUPPORTS_MSA
1466 Multi-core scheduler support improv !! 2575 depends on MIPS_FP_SUPPORT
1467 making when dealing with multi-core !! 2576 depends on 64BIT || MIPS_O32_FP64_SUPPORT
1468 increased overhead in some places. !! 2577 help
>> 2578 MIPS SIMD Architecture (MSA) introduces 128 bit wide vector registers
>> 2579 and a set of SIMD instructions to operate on them. When this option
>> 2580 is enabled the kernel will support allocating & switching MSA
>> 2581 vector register contexts. If you know that your kernel will only be
>> 2582 running on CPUs which do not support MSA or that your userland will
>> 2583 not be making use of it then you may wish to say N here to reduce
>> 2584 the size & complexity of your kernel.
1469 2585
1470 config SCHED_CLUSTER !! 2586 If unsure, say Y.
1471 bool "Cluster scheduler support" <<
1472 help <<
1473 Cluster scheduler support improves <<
1474 making when dealing with machines t <<
1475 Cluster usually means a couple of C <<
1476 by sharing mid-level caches, last-l <<
1477 busses. <<
1478 2587
1479 config SCHED_SMT !! 2588 config CPU_HAS_WB
1480 bool "SMT scheduler support" !! 2589 bool
1481 help <<
1482 Improves the CPU scheduler's decisi <<
1483 MultiThreading at a cost of slightl <<
1484 places. If unsure say N here. <<
1485 2590
1486 config NR_CPUS !! 2591 config XKS01
1487 int "Maximum number of CPUs (2-4096)" !! 2592 bool
1488 range 2 4096 <<
1489 default "512" <<
1490 2593
1491 config HOTPLUG_CPU !! 2594 config CPU_HAS_DIEI
1492 bool "Support for hot-pluggable CPUs" !! 2595 depends on !CPU_DIEI_BROKEN
1493 select GENERIC_IRQ_MIGRATION !! 2596 bool
1494 help <<
1495 Say Y here to experiment with turni <<
1496 can be controlled through /sys/devi <<
1497 2597
1498 # Common NUMA Features !! 2598 config CPU_DIEI_BROKEN
1499 config NUMA !! 2599 bool
1500 bool "NUMA Memory Allocation and Sche <<
1501 select GENERIC_ARCH_NUMA <<
1502 select OF_NUMA <<
1503 select HAVE_SETUP_PER_CPU_AREA <<
1504 select NEED_PER_CPU_EMBED_FIRST_CHUNK <<
1505 select NEED_PER_CPU_PAGE_FIRST_CHUNK <<
1506 select USE_PERCPU_NUMA_NODE_ID <<
1507 help <<
1508 Enable NUMA (Non-Uniform Memory Acc <<
1509 <<
1510 The kernel will try to allocate mem <<
1511 local memory of the CPU and add som <<
1512 NUMA awareness to the kernel. <<
1513 2600
1514 config NODES_SHIFT !! 2601 config CPU_HAS_RIXI
1515 int "Maximum NUMA Nodes (as a power o !! 2602 bool
1516 range 1 10 !! 2603
1517 default "4" !! 2604 config CPU_NO_LOAD_STORE_LR
1518 depends on NUMA !! 2605 bool
1519 help 2606 help
1520 Specify the maximum number of NUMA !! 2607 CPU lacks support for unaligned load and store instructions:
1521 system. Increases memory reserved !! 2608 LWL, LWR, SWL, SWR (Load/store word left/right).
>> 2609 LDL, LDR, SDL, SDR (Load/store doubleword left/right, for 64bit
>> 2610 systems).
1522 2611
1523 source "kernel/Kconfig.hz" !! 2612 #
>> 2613 # Vectored interrupt mode is an R2 feature
>> 2614 #
>> 2615 config CPU_MIPSR2_IRQ_VI
>> 2616 bool
1524 2617
1525 config ARCH_SPARSEMEM_ENABLE !! 2618 #
1526 def_bool y !! 2619 # Extended interrupt mode is an R2 feature
1527 select SPARSEMEM_VMEMMAP_ENABLE !! 2620 #
1528 select SPARSEMEM_VMEMMAP !! 2621 config CPU_MIPSR2_IRQ_EI
>> 2622 bool
1529 2623
1530 config HW_PERF_EVENTS !! 2624 config CPU_HAS_SYNC
1531 def_bool y !! 2625 bool
1532 depends on ARM_PMU !! 2626 depends on !CPU_R3000
>> 2627 default y
1533 2628
1534 # Supported by clang >= 7.0 or GCC >= 12.0.0 !! 2629 #
1535 config CC_HAVE_SHADOW_CALL_STACK !! 2630 # CPU non-features
1536 def_bool $(cc-option, -fsanitize=shad !! 2631 #
>> 2632 config CPU_DADDI_WORKAROUNDS
>> 2633 bool
1537 2634
1538 config PARAVIRT !! 2635 config CPU_R4000_WORKAROUNDS
1539 bool "Enable paravirtualization code" !! 2636 bool
1540 help !! 2637 select CPU_R4400_WORKAROUNDS
1541 This changes the kernel so it can m <<
1542 under a hypervisor, potentially imp <<
1543 over full virtualization. <<
1544 2638
1545 config PARAVIRT_TIME_ACCOUNTING !! 2639 config CPU_R4400_WORKAROUNDS
1546 bool "Paravirtual steal time accounti !! 2640 bool
1547 select PARAVIRT <<
1548 help <<
1549 Select this option to enable fine g <<
1550 accounting. Time spent executing ot <<
1551 the current vCPU is discounted from <<
1552 that, there can be a small performa <<
1553 2641
1554 If in doubt, say N here. !! 2642 config CPU_R4X00_BUGS64
>> 2643 bool
>> 2644 default y if SYS_HAS_CPU_R4X00 && 64BIT && (TARGET_ISA_REV < 1)
1555 2645
1556 config ARCH_SUPPORTS_KEXEC !! 2646 config MIPS_ASID_SHIFT
1557 def_bool PM_SLEEP_SMP !! 2647 int
>> 2648 default 6 if CPU_R3000 || CPU_TX39XX
>> 2649 default 0
1558 2650
1559 config ARCH_SUPPORTS_KEXEC_FILE !! 2651 config MIPS_ASID_BITS
1560 def_bool y !! 2652 int
>> 2653 default 0 if MIPS_ASID_BITS_VARIABLE
>> 2654 default 6 if CPU_R3000 || CPU_TX39XX
>> 2655 default 8
1561 2656
1562 config ARCH_SELECTS_KEXEC_FILE !! 2657 config MIPS_ASID_BITS_VARIABLE
1563 def_bool y !! 2658 bool
1564 depends on KEXEC_FILE <<
1565 select HAVE_IMA_KEXEC if IMA <<
1566 2659
1567 config ARCH_SUPPORTS_KEXEC_SIG !! 2660 config MIPS_CRC_SUPPORT
1568 def_bool y !! 2661 bool
1569 2662
1570 config ARCH_SUPPORTS_KEXEC_IMAGE_VERIFY_SIG !! 2663 # R4600 erratum. Due to the lack of errata information the exact
1571 def_bool y !! 2664 # technical details aren't known. I've experimentally found that disabling
>> 2665 # interrupts during indexed I-cache flushes seems to be sufficient to deal
>> 2666 # with the issue.
>> 2667 config WAR_R4600_V1_INDEX_ICACHEOP
>> 2668 bool
1572 2669
1573 config ARCH_DEFAULT_KEXEC_IMAGE_VERIFY_SIG !! 2670 # Pleasures of the R4600 V1.x. Cite from the IDT R4600 V1.7 errata:
1574 def_bool y !! 2671 #
>> 2672 # 18. The CACHE instructions Hit_Writeback_Invalidate_D, Hit_Writeback_D,
>> 2673 # Hit_Invalidate_D and Create_Dirty_Excl_D should only be
>> 2674 # executed if there is no other dcache activity. If the dcache is
>> 2675 # accessed for another instruction immediately preceding when these
>> 2676 # cache instructions are executing, it is possible that the dcache
>> 2677 # tag match outputs used by these cache instructions will be
>> 2678 # incorrect. These cache instructions should be preceded by at least
>> 2679 # four instructions that are not any kind of load or store
>> 2680 # instruction.
>> 2681 #
>> 2682 # This is not allowed: lw
>> 2683 # nop
>> 2684 # nop
>> 2685 # nop
>> 2686 # cache Hit_Writeback_Invalidate_D
>> 2687 #
>> 2688 # This is allowed: lw
>> 2689 # nop
>> 2690 # nop
>> 2691 # nop
>> 2692 # nop
>> 2693 # cache Hit_Writeback_Invalidate_D
>> 2694 config WAR_R4600_V1_HIT_CACHEOP
>> 2695 bool
1575 2696
1576 config ARCH_SUPPORTS_CRASH_DUMP !! 2697 # Writeback and invalidate the primary cache dcache before DMA.
1577 def_bool y !! 2698 #
>> 2699 # R4600 v2.0 bug: "The CACHE instructions Hit_Writeback_Inv_D,
>> 2700 # Hit_Writeback_D, Hit_Invalidate_D and Create_Dirty_Exclusive_D will only
>> 2701 # operate correctly if the internal data cache refill buffer is empty. These
>> 2702 # CACHE instructions should be separated from any potential data cache miss
>> 2703 # by a load instruction to an uncached address to empty the response buffer."
>> 2704 # (Revision 2.0 device errata from IDT available on https://www.idt.com/
>> 2705 # in .pdf format.)
>> 2706 config WAR_R4600_V2_HIT_CACHEOP
>> 2707 bool
1578 2708
1579 config ARCH_HAS_GENERIC_CRASHKERNEL_RESERVATI !! 2709 # From TX49/H2 manual: "If the instruction (i.e. CACHE) is issued for
1580 def_bool CRASH_RESERVE !! 2710 # the line which this instruction itself exists, the following
>> 2711 # operation is not guaranteed."
>> 2712 #
>> 2713 # Workaround: do two phase flushing for Index_Invalidate_I
>> 2714 config WAR_TX49XX_ICACHE_INDEX_INV
>> 2715 bool
1581 2716
1582 config TRANS_TABLE !! 2717 # The RM7000 processors and the E9000 cores have a bug (though PMC-Sierra
1583 def_bool y !! 2718 # opposes it being called that) where invalid instructions in the same
1584 depends on HIBERNATION || KEXEC_CORE !! 2719 # I-cache line worth of instructions being fetched may case spurious
>> 2720 # exceptions.
>> 2721 config WAR_ICACHE_REFILLS
>> 2722 bool
1585 2723
1586 config XEN_DOM0 !! 2724 # On the R10000 up to version 2.6 (not sure about 2.7) there is a bug that
1587 def_bool y !! 2725 # may cause ll / sc and lld / scd sequences to execute non-atomically.
1588 depends on XEN !! 2726 config WAR_R10000_LLSC
>> 2727 bool
1589 2728
1590 config XEN !! 2729 # 34K core erratum: "Problems Executing the TLBR Instruction"
1591 bool "Xen guest support on ARM64" !! 2730 config WAR_MIPS34K_MISSED_ITLB
1592 depends on ARM64 && OF !! 2731 bool
1593 select SWIOTLB_XEN <<
1594 select PARAVIRT <<
1595 help <<
1596 Say Y if you want to run Linux in a <<
1597 2732
1598 # include/linux/mmzone.h requires the followi <<
1599 # <<
1600 # MAX_PAGE_ORDER + PAGE_SHIFT <= SECTION_SI <<
1601 # 2733 #
1602 # so the maximum value of MAX_PAGE_ORDER is S !! 2734 # - Highmem only makes sense for the 32-bit kernel.
>> 2735 # - The current highmem code will only work properly on physically indexed
>> 2736 # caches such as R3000, SB1, R7000 or those that look like they're virtually
>> 2737 # indexed such as R4000/R4400 SC and MC versions or R10000. So for the
>> 2738 # moment we protect the user and offer the highmem option only on machines
>> 2739 # where it's known to be safe. This will not offer highmem on a few systems
>> 2740 # such as MIPS32 and MIPS64 CPUs which may have virtual and physically
>> 2741 # indexed CPUs but we're playing safe.
>> 2742 # - We use SYS_SUPPORTS_HIGHMEM to offer highmem only for systems where we
>> 2743 # know they might have memory configurations that could make use of highmem
>> 2744 # support.
1603 # 2745 #
1604 # | SECTION_SIZE_BITS | PAGE_SHIFT | m !! 2746 config HIGHMEM
1605 # ----+-------------------+--------------+--- !! 2747 bool "High Memory Support"
1606 # 4K | 27 | 12 | !! 2748 depends on 32BIT && CPU_SUPPORTS_HIGHMEM && SYS_SUPPORTS_HIGHMEM && !CPU_MIPS32_3_5_EVA
1607 # 16K | 27 | 14 | !! 2749 select KMAP_LOCAL
1608 # 64K | 29 | 16 | <<
1609 config ARCH_FORCE_MAX_ORDER <<
1610 int <<
1611 default "13" if ARM64_64K_PAGES <<
1612 default "11" if ARM64_16K_PAGES <<
1613 default "10" <<
1614 help <<
1615 The kernel page allocator limits th <<
1616 contiguous allocations. The limit i <<
1617 defines the maximal power of two of <<
1618 allocated as a single contiguous bl <<
1619 overriding the default setting when <<
1620 large blocks of physically contiguo <<
1621 <<
1622 The maximal size of allocation cann <<
1623 section, so the value of MAX_PAGE_O <<
1624 2750
1625 MAX_PAGE_ORDER + PAGE_SHIFT <= SE !! 2751 config CPU_SUPPORTS_HIGHMEM
>> 2752 bool
1626 2753
1627 Don't change if unsure. !! 2754 config SYS_SUPPORTS_HIGHMEM
>> 2755 bool
1628 2756
1629 config UNMAP_KERNEL_AT_EL0 !! 2757 config SYS_SUPPORTS_SMARTMIPS
1630 bool "Unmap kernel when running in us !! 2758 bool
1631 default y <<
1632 help <<
1633 Speculation attacks against some hi <<
1634 be used to bypass MMU permission ch <<
1635 userspace. This can be defended aga <<
1636 when running in userspace, mapping <<
1637 via a trampoline page in the vector <<
1638 2759
1639 If unsure, say Y. !! 2760 config SYS_SUPPORTS_MICROMIPS
>> 2761 bool
1640 2762
1641 config MITIGATE_SPECTRE_BRANCH_HISTORY !! 2763 config SYS_SUPPORTS_MIPS16
1642 bool "Mitigate Spectre style attacks !! 2764 bool
1643 default y <<
1644 help 2765 help
1645 Speculation attacks against some hi !! 2766 This option must be set if a kernel might be executed on a MIPS16-
1646 make use of branch history to influ !! 2767 enabled CPU even if MIPS16 is not actually being used. In other
1647 When taking an exception from user- !! 2768 words, it makes the kernel MIPS16-tolerant.
1648 or a firmware call overwrites the b <<
1649 2769
1650 config RODATA_FULL_DEFAULT_ENABLED !! 2770 config CPU_SUPPORTS_MSA
1651 bool "Apply r/o permissions of VM are !! 2771 bool
1652 default y <<
1653 help <<
1654 Apply read-only attributes of VM ar <<
1655 the backing pages as well. This pre <<
1656 from being modified (inadvertently <<
1657 mapping of the same memory page. Th <<
1658 be turned off at runtime by passing <<
1659 with rodata=full if this option is <<
1660 <<
1661 This requires the linear region to <<
1662 which may adversely affect performa <<
1663 <<
1664 config ARM64_SW_TTBR0_PAN <<
1665 bool "Emulate Privileged Access Never <<
1666 depends on !KCSAN <<
1667 help <<
1668 Enabling this option prevents the k <<
1669 user-space memory directly by point <<
1670 zeroed area and reserved ASID. The <<
1671 restore the valid TTBR0_EL1 tempora <<
1672 2772
1673 config ARM64_TAGGED_ADDR_ABI !! 2773 config ARCH_FLATMEM_ENABLE
1674 bool "Enable the tagged user addresse !! 2774 def_bool y
1675 default y !! 2775 depends on !NUMA && !CPU_LOONGSON2EF
1676 help <<
1677 When this option is enabled, user a <<
1678 relaxed ABI via prctl() allowing ta <<
1679 to system calls as pointer argument <<
1680 Documentation/arch/arm64/tagged-add <<
1681 <<
1682 menuconfig COMPAT <<
1683 bool "Kernel support for 32-bit EL0" <<
1684 depends on ARM64_4K_PAGES || EXPERT <<
1685 select HAVE_UID16 <<
1686 select OLD_SIGSUSPEND3 <<
1687 select COMPAT_OLD_SIGACTION <<
1688 help <<
1689 This option enables support for a 3 <<
1690 kernel at EL1. AArch32-specific com <<
1691 the user helper functions, VFP supp <<
1692 handled appropriately by the kernel <<
1693 <<
1694 If you use a page size other than 4 <<
1695 that you will only be able to execu <<
1696 with page size aligned segments. <<
1697 2776
1698 If you want to execute 32-bit users !! 2777 config ARCH_SPARSEMEM_ENABLE
>> 2778 bool
>> 2779 select SPARSEMEM_STATIC if !SGI_IP27
1699 2780
1700 if COMPAT !! 2781 config NUMA
>> 2782 bool "NUMA Support"
>> 2783 depends on SYS_SUPPORTS_NUMA
>> 2784 select SMP
>> 2785 help
>> 2786 Say Y to compile the kernel to support NUMA (Non-Uniform Memory
>> 2787 Access). This option improves performance on systems with more
>> 2788 than two nodes; on two node systems it is generally better to
>> 2789 leave it disabled; on single node systems leave this option
>> 2790 disabled.
1701 2791
1702 config KUSER_HELPERS !! 2792 config SYS_SUPPORTS_NUMA
1703 bool "Enable kuser helpers page for 3 !! 2793 bool
1704 default y <<
1705 help <<
1706 Warning: disabling this option may <<
1707 2794
1708 Provide kuser helpers to compat tas !! 2795 config HAVE_SETUP_PER_CPU_AREA
1709 helper code to userspace in read on !! 2796 def_bool y
1710 to allow userspace to be independen !! 2797 depends on NUMA
1711 the system. This permits binaries t <<
1712 to ARMv8 without modification. <<
1713 <<
1714 See Documentation/arch/arm/kernel_u <<
1715 <<
1716 However, the fixed address nature o <<
1717 by ROP (return orientated programmi <<
1718 exploits. <<
1719 <<
1720 If all of the binaries and librarie <<
1721 are built specifically for your pla <<
1722 these helpers, then you can turn th <<
1723 such exploits. However, in that cas <<
1724 relying on those helpers is run, it <<
1725 <<
1726 Say N here only if you are absolute <<
1727 need these helpers; otherwise, the <<
1728 <<
1729 config COMPAT_VDSO <<
1730 bool "Enable vDSO for 32-bit applicat <<
1731 depends on !CPU_BIG_ENDIAN <<
1732 depends on (CC_IS_CLANG && LD_IS_LLD) <<
1733 select GENERIC_COMPAT_VDSO <<
1734 default y <<
1735 help <<
1736 Place in the process address space <<
1737 ELF shared object providing fast im <<
1738 and clock_gettime. <<
1739 <<
1740 You must have a 32-bit build of gli <<
1741 to seamlessly take advantage of thi <<
1742 <<
1743 config THUMB2_COMPAT_VDSO <<
1744 bool "Compile the 32-bit vDSO for Thu <<
1745 depends on COMPAT_VDSO <<
1746 default y <<
1747 help <<
1748 Compile the compat vDSO with '-mthu <<
1749 otherwise with '-marm'. <<
1750 2798
1751 config COMPAT_ALIGNMENT_FIXUPS !! 2799 config NEED_PER_CPU_EMBED_FIRST_CHUNK
1752 bool "Fix up misaligned multi-word lo !! 2800 def_bool y
>> 2801 depends on NUMA
1753 2802
1754 menuconfig ARMV8_DEPRECATED !! 2803 config RELOCATABLE
1755 bool "Emulate deprecated/obsolete ARM !! 2804 bool "Relocatable kernel"
1756 depends on SYSCTL !! 2805 depends on SYS_SUPPORTS_RELOCATABLE
1757 help !! 2806 depends on CPU_MIPS32_R2 || CPU_MIPS64_R2 || \
1758 Legacy software support may require !! 2807 CPU_MIPS32_R5 || CPU_MIPS64_R5 || \
1759 that have been deprecated or obsole !! 2808 CPU_MIPS32_R6 || CPU_MIPS64_R6 || \
>> 2809 CPU_P5600 || CAVIUM_OCTEON_SOC || \
>> 2810 CPU_LOONGSON64
>> 2811 help
>> 2812 This builds a kernel image that retains relocation information
>> 2813 so it can be loaded someplace besides the default 1MB.
>> 2814 The relocations make the kernel binary about 15% larger,
>> 2815 but are discarded at runtime
>> 2816
>> 2817 config RELOCATION_TABLE_SIZE
>> 2818 hex "Relocation table size"
>> 2819 depends on RELOCATABLE
>> 2820 range 0x0 0x01000000
>> 2821 default "0x00200000" if CPU_LOONGSON64
>> 2822 default "0x00100000"
>> 2823 help
>> 2824 A table of relocation data will be appended to the kernel binary
>> 2825 and parsed at boot to fix up the relocated kernel.
1760 2826
1761 Enable this config to enable select !! 2827 This option allows the amount of space reserved for the table to be
1762 features. !! 2828 adjusted, although the default of 1Mb should be ok in most cases.
1763 2829
1764 If unsure, say Y !! 2830 The build will fail and a valid size suggested if this is too small.
1765 2831
1766 if ARMV8_DEPRECATED !! 2832 If unsure, leave at the default value.
1767 2833
1768 config SWP_EMULATION !! 2834 config RANDOMIZE_BASE
1769 bool "Emulate SWP/SWPB instructions" !! 2835 bool "Randomize the address of the kernel image"
>> 2836 depends on RELOCATABLE
1770 help 2837 help
1771 ARMv8 obsoletes the use of A32 SWP/ !! 2838 Randomizes the physical and virtual address at which the
1772 they are always undefined. Say Y he !! 2839 kernel image is loaded, as a security feature that
1773 emulation of these instructions for !! 2840 deters exploit attempts relying on knowledge of the location
1774 This feature can be controlled at r !! 2841 of kernel internals.
1775 sysctl which is disabled by default <<
1776 2842
1777 In some older versions of glibc [<= !! 2843 Entropy is generated using any coprocessor 0 registers available.
1778 trylock() operations with the assum <<
1779 be preempted. This invalid assumpti <<
1780 with SWP emulation enabled, leading <<
1781 application. <<
1782 2844
1783 NOTE: when accessing uncached share !! 2845 The kernel will be offset by up to RANDOMIZE_BASE_MAX_OFFSET.
1784 on an external transaction monitori <<
1785 monitor to maintain update atomicit <<
1786 implement a global monitor, this op <<
1787 perform SWP operations to uncached <<
1788 2846
1789 If unsure, say Y !! 2847 If unsure, say N.
1790 2848
1791 config CP15_BARRIER_EMULATION !! 2849 config RANDOMIZE_BASE_MAX_OFFSET
1792 bool "Emulate CP15 Barrier instructio !! 2850 hex "Maximum kASLR offset" if EXPERT
1793 help !! 2851 depends on RANDOMIZE_BASE
1794 The CP15 barrier instructions - CP1 !! 2852 range 0x0 0x40000000 if EVA || 64BIT
1795 CP15DMB - are deprecated in ARMv8 ( !! 2853 range 0x0 0x08000000
1796 strongly recommended to use the ISB !! 2854 default "0x01000000"
1797 instructions instead. !! 2855 help
>> 2856 When kASLR is active, this provides the maximum offset that will
>> 2857 be applied to the kernel image. It should be set according to the
>> 2858 amount of physical RAM available in the target system minus
>> 2859 PHYSICAL_START and must be a power of 2.
1798 2860
1799 Say Y here to enable software emula !! 2861 This is limited by the size of KSEG0, 256Mb on 32-bit or 1Gb with
1800 instructions for AArch32 userspace !! 2862 EVA or 64-bit. The default is 16Mb.
1801 enabled, CP15 barrier usage is trac <<
1802 identify software that needs updati <<
1803 controlled at runtime with the abi. <<
1804 2863
1805 If unsure, say Y !! 2864 config NODES_SHIFT
>> 2865 int
>> 2866 default "6"
>> 2867 depends on NUMA
1806 2868
1807 config SETEND_EMULATION !! 2869 config HW_PERF_EVENTS
1808 bool "Emulate SETEND instruction" !! 2870 bool "Enable hardware performance counter support for perf events"
>> 2871 depends on PERF_EVENTS && (CPU_MIPS32 || CPU_MIPS64 || CPU_R10000 || CPU_SB1 || CPU_CAVIUM_OCTEON || CPU_XLP || CPU_LOONGSON64)
>> 2872 default y
1809 help 2873 help
1810 The SETEND instruction alters the d !! 2874 Enable hardware performance counter support for perf events. If
1811 AArch32 EL0, and is deprecated in A !! 2875 disabled, perf events will use software events only.
1812 2876
1813 Say Y here to enable software emula !! 2877 config DMI
1814 for AArch32 userspace code. This fe !! 2878 bool "Enable DMI scanning"
1815 at runtime with the abi.setend sysc !! 2879 depends on MACH_LOONGSON64
>> 2880 select DMI_SCAN_MACHINE_NON_EFI_FALLBACK
>> 2881 default y
>> 2882 help
>> 2883 Enabled scanning of DMI to identify machine quirks. Say Y
>> 2884 here unless you have verified that your setup is not
>> 2885 affected by entries in the DMI blacklist. Required by PNP
>> 2886 BIOS code.
1816 2887
1817 Note: All the cpus on the system mu !! 2888 config SMP
1818 for this feature to be enabled. If !! 2889 bool "Multi-Processing support"
1819 endian - is hotplugged in after thi !! 2890 depends on SYS_SUPPORTS_SMP
1820 be unexpected results in the applic !! 2891 help
>> 2892 This enables support for systems with more than one CPU. If you have
>> 2893 a system with only one CPU, say N. If you have a system with more
>> 2894 than one CPU, say Y.
>> 2895
>> 2896 If you say N here, the kernel will run on uni- and multiprocessor
>> 2897 machines, but will use only one CPU of a multiprocessor machine. If
>> 2898 you say Y here, the kernel will run on many, but not all,
>> 2899 uniprocessor machines. On a uniprocessor machine, the kernel
>> 2900 will run faster if you say N here.
1821 2901
1822 If unsure, say Y !! 2902 People using multiprocessor machines who say Y here should also say
1823 endif # ARMV8_DEPRECATED !! 2903 Y to "Enhanced Real Time Clock Support", below.
1824 2904
1825 endif # COMPAT !! 2905 See also the SMP-HOWTO available at
>> 2906 <https://www.tldp.org/docs.html#howto>.
1826 2907
1827 menu "ARMv8.1 architectural features" !! 2908 If you don't know what to do here, say N.
1828 2909
1829 config ARM64_HW_AFDBM !! 2910 config HOTPLUG_CPU
1830 bool "Support for hardware updates of !! 2911 bool "Support for hot-pluggable CPUs"
1831 default y !! 2912 depends on SMP && SYS_SUPPORTS_HOTPLUG_CPU
1832 help 2913 help
1833 The ARMv8.1 architecture extensions !! 2914 Say Y here to allow turning CPUs off and on. CPUs can be
1834 hardware updates of the access and !! 2915 controlled through /sys/devices/system/cpu.
1835 table entries. When enabled in TCR_ !! 2916 (Note: power management support will enable this option
1836 capable processors, accesses to pag !! 2917 automatically on SMP systems. )
1837 set this bit instead of raising an !! 2918 Say N if you want to disable CPU hotplug.
1838 Similarly, writes to read-only page <<
1839 clear the read-only bit (AP[2]) ins <<
1840 permission fault. <<
1841 <<
1842 Kernels built with this configurati <<
1843 to work on pre-ARMv8.1 hardware and <<
1844 minimal. If unsure, say Y. <<
1845 2919
1846 config ARM64_PAN !! 2920 config SMP_UP
1847 bool "Enable support for Privileged A !! 2921 bool
1848 default y <<
1849 help <<
1850 Privileged Access Never (PAN; part <<
1851 prevents the kernel or hypervisor f <<
1852 memory directly. <<
1853 2922
1854 Choosing this option will cause any !! 2923 config SYS_SUPPORTS_MIPS_CMP
1855 copy_to_user et al) memory access t !! 2924 bool
1856 2925
1857 The feature is detected at runtime, !! 2926 config SYS_SUPPORTS_MIPS_CPS
1858 instruction if the cpu does not imp !! 2927 bool
1859 2928
1860 config AS_HAS_LSE_ATOMICS !! 2929 config SYS_SUPPORTS_SMP
1861 def_bool $(as-instr,.arch_extension l !! 2930 bool
1862 2931
1863 config ARM64_LSE_ATOMICS !! 2932 config NR_CPUS_DEFAULT_4
1864 bool 2933 bool
1865 default ARM64_USE_LSE_ATOMICS <<
1866 depends on AS_HAS_LSE_ATOMICS <<
1867 2934
1868 config ARM64_USE_LSE_ATOMICS !! 2935 config NR_CPUS_DEFAULT_8
1869 bool "Atomic instructions" !! 2936 bool
1870 default y <<
1871 help <<
1872 As part of the Large System Extensi <<
1873 atomic instructions that are design <<
1874 very large systems. <<
1875 2937
1876 Say Y here to make use of these ins !! 2938 config NR_CPUS_DEFAULT_16
1877 atomic routines. This incurs a smal !! 2939 bool
1878 not support these instructions and <<
1879 built with binutils >= 2.25 in orde <<
1880 to be used. <<
1881 2940
1882 endmenu # "ARMv8.1 architectural features" !! 2941 config NR_CPUS_DEFAULT_32
>> 2942 bool
1883 2943
1884 menu "ARMv8.2 architectural features" !! 2944 config NR_CPUS_DEFAULT_64
>> 2945 bool
1885 2946
1886 config AS_HAS_ARMV8_2 !! 2947 config NR_CPUS
1887 def_bool $(cc-option,-Wa$(comma)-marc !! 2948 int "Maximum number of CPUs (2-256)"
>> 2949 range 2 256
>> 2950 depends on SMP
>> 2951 default "4" if NR_CPUS_DEFAULT_4
>> 2952 default "8" if NR_CPUS_DEFAULT_8
>> 2953 default "16" if NR_CPUS_DEFAULT_16
>> 2954 default "32" if NR_CPUS_DEFAULT_32
>> 2955 default "64" if NR_CPUS_DEFAULT_64
>> 2956 help
>> 2957 This allows you to specify the maximum number of CPUs which this
>> 2958 kernel will support. The maximum supported value is 32 for 32-bit
>> 2959 kernel and 64 for 64-bit kernels; the minimum value which makes
>> 2960 sense is 1 for Qemu (useful only for kernel debugging purposes)
>> 2961 and 2 for all others.
>> 2962
>> 2963 This is purely to save memory - each supported CPU adds
>> 2964 approximately eight kilobytes to the kernel image. For best
>> 2965 performance should round up your number of processors to the next
>> 2966 power of two.
1888 2967
1889 config AS_HAS_SHA3 !! 2968 config MIPS_PERF_SHARED_TC_COUNTERS
1890 def_bool $(as-instr,.arch armv8.2-a+s !! 2969 bool
1891 2970
1892 config ARM64_PMEM !! 2971 config MIPS_NR_CPU_NR_MAP_1024
1893 bool "Enable support for persistent m !! 2972 bool
1894 select ARCH_HAS_PMEM_API <<
1895 select ARCH_HAS_UACCESS_FLUSHCACHE <<
1896 help <<
1897 Say Y to enable support for the per <<
1898 ARMv8.2 DCPoP feature. <<
1899 2973
1900 The feature is detected at runtime, !! 2974 config MIPS_NR_CPU_NR_MAP
1901 operations if DC CVAP is not suppor !! 2975 int
1902 DC CVAP itself if the system does n !! 2976 depends on SMP
>> 2977 default 1024 if MIPS_NR_CPU_NR_MAP_1024
>> 2978 default NR_CPUS if !MIPS_NR_CPU_NR_MAP_1024
1903 2979
1904 config ARM64_RAS_EXTN !! 2980 #
1905 bool "Enable support for RAS CPU Exte !! 2981 # Timer Interrupt Frequency Configuration
1906 default y !! 2982 #
1907 help <<
1908 CPUs that support the Reliability, <<
1909 (RAS) Extensions, part of ARMv8.2 a <<
1910 errors, classify them and report th <<
1911 <<
1912 On CPUs with these extensions syste <<
1913 barriers to determine if faults are <<
1914 classification from a new set of re <<
1915 <<
1916 Selecting this feature will allow t <<
1917 and access the new registers if the <<
1918 Platform RAS features may additiona <<
1919 2983
1920 config ARM64_CNP !! 2984 choice
1921 bool "Enable support for Common Not P !! 2985 prompt "Timer frequency"
1922 default y !! 2986 default HZ_250
1923 depends on ARM64_PAN || !ARM64_SW_TTB <<
1924 help 2987 help
1925 Common Not Private (CNP) allows tra !! 2988 Allows the configuration of the timer frequency.
1926 be shared between different PEs in <<
1927 domain, so the hardware can use thi <<
1928 caching of such entries in the TLB. <<
1929 2989
1930 Selecting this option allows the CN !! 2990 config HZ_24
1931 at runtime, and does not affect PEs !! 2991 bool "24 HZ" if SYS_SUPPORTS_24HZ || SYS_SUPPORTS_ARBIT_HZ
1932 this feature. <<
1933 2992
1934 endmenu # "ARMv8.2 architectural features" !! 2993 config HZ_48
>> 2994 bool "48 HZ" if SYS_SUPPORTS_48HZ || SYS_SUPPORTS_ARBIT_HZ
1935 2995
1936 menu "ARMv8.3 architectural features" !! 2996 config HZ_100
>> 2997 bool "100 HZ" if SYS_SUPPORTS_100HZ || SYS_SUPPORTS_ARBIT_HZ
1937 2998
1938 config ARM64_PTR_AUTH !! 2999 config HZ_128
1939 bool "Enable support for pointer auth !! 3000 bool "128 HZ" if SYS_SUPPORTS_128HZ || SYS_SUPPORTS_ARBIT_HZ
1940 default y <<
1941 help <<
1942 Pointer authentication (part of the <<
1943 instructions for signing and authen <<
1944 keys, which can be used to mitigate <<
1945 and other attacks. <<
1946 <<
1947 This option enables these instructi <<
1948 Choosing this option will cause the <<
1949 for each process at exec() time, wi <<
1950 context-switched along with the pro <<
1951 <<
1952 The feature is detected at runtime. <<
1953 hardware it will not be advertised <<
1954 be enabled. <<
1955 <<
1956 If the feature is present on the bo <<
1957 the late CPU will be parked. Also, <<
1958 address auth and the late CPU has t <<
1959 but with the feature disabled. On s <<
1960 not be selected. <<
1961 3001
1962 config ARM64_PTR_AUTH_KERNEL !! 3002 config HZ_250
1963 bool "Use pointer authentication for !! 3003 bool "250 HZ" if SYS_SUPPORTS_250HZ || SYS_SUPPORTS_ARBIT_HZ
1964 default y <<
1965 depends on ARM64_PTR_AUTH <<
1966 depends on (CC_HAS_SIGN_RETURN_ADDRES <<
1967 # Modern compilers insert a .note.gnu <<
1968 # which is only understood by binutil <<
1969 depends on LD_IS_LLD || LD_VERSION >= <<
1970 depends on !CC_IS_CLANG || AS_HAS_CFI <<
1971 depends on (!FUNCTION_GRAPH_TRACER || <<
1972 help <<
1973 If the compiler supports the -mbran <<
1974 -msign-return-address flag (e.g. GC <<
1975 will cause the kernel itself to be <<
1976 protection. In this case, and if th <<
1977 support pointer authentication, the <<
1978 disabled with minimal loss of prote <<
1979 <<
1980 This feature works with FUNCTION_GR <<
1981 DYNAMIC_FTRACE_WITH_ARGS is enabled <<
1982 <<
1983 config CC_HAS_BRANCH_PROT_PAC_RET <<
1984 # GCC 9 or later, clang 8 or later <<
1985 def_bool $(cc-option,-mbranch-protect <<
1986 <<
1987 config CC_HAS_SIGN_RETURN_ADDRESS <<
1988 # GCC 7, 8 <<
1989 def_bool $(cc-option,-msign-return-ad <<
1990 <<
1991 config AS_HAS_ARMV8_3 <<
1992 def_bool $(cc-option,-Wa$(comma)-marc <<
1993 <<
1994 config AS_HAS_CFI_NEGATE_RA_STATE <<
1995 def_bool $(as-instr,.cfi_startproc\n. <<
1996 <<
1997 config AS_HAS_LDAPR <<
1998 def_bool $(as-instr,.arch_extension r <<
1999 3004
2000 endmenu # "ARMv8.3 architectural features" !! 3005 config HZ_256
>> 3006 bool "256 HZ" if SYS_SUPPORTS_256HZ || SYS_SUPPORTS_ARBIT_HZ
2001 3007
2002 menu "ARMv8.4 architectural features" !! 3008 config HZ_1000
>> 3009 bool "1000 HZ" if SYS_SUPPORTS_1000HZ || SYS_SUPPORTS_ARBIT_HZ
2003 3010
2004 config ARM64_AMU_EXTN !! 3011 config HZ_1024
2005 bool "Enable support for the Activity !! 3012 bool "1024 HZ" if SYS_SUPPORTS_1024HZ || SYS_SUPPORTS_ARBIT_HZ
2006 default y <<
2007 help <<
2008 The activity monitors extension is <<
2009 by the ARMv8.4 CPU architecture. Th <<
2010 of the activity monitors architectu <<
2011 <<
2012 To enable the use of this extension <<
2013 <<
2014 Note that for architectural reasons <<
2015 support when running on CPUs that p <<
2016 extension. The required support is <<
2017 * Version 1.5 and later of the AR <<
2018 <<
2019 For kernels that have this configur <<
2020 firmware, you may need to say N her <<
2021 Otherwise you may experience firmwa <<
2022 accessing the counter registers. Ev <<
2023 symptoms, the values returned by th <<
2024 correctly reflect reality. Most com <<
2025 indicating that the counter is not <<
2026 3013
2027 config AS_HAS_ARMV8_4 !! 3014 endchoice
2028 def_bool $(cc-option,-Wa$(comma)-marc <<
2029 3015
2030 config ARM64_TLB_RANGE !! 3016 config SYS_SUPPORTS_24HZ
2031 bool "Enable support for tlbi range f !! 3017 bool
2032 default y <<
2033 depends on AS_HAS_ARMV8_4 <<
2034 help <<
2035 ARMv8.4-TLBI provides TLBI invalida <<
2036 range of input addresses. <<
2037 3018
2038 The feature introduces new assembly !! 3019 config SYS_SUPPORTS_48HZ
2039 support when binutils >= 2.30. !! 3020 bool
2040 3021
2041 endmenu # "ARMv8.4 architectural features" !! 3022 config SYS_SUPPORTS_100HZ
>> 3023 bool
2042 3024
2043 menu "ARMv8.5 architectural features" !! 3025 config SYS_SUPPORTS_128HZ
>> 3026 bool
2044 3027
2045 config AS_HAS_ARMV8_5 !! 3028 config SYS_SUPPORTS_250HZ
2046 def_bool $(cc-option,-Wa$(comma)-marc !! 3029 bool
2047 3030
2048 config ARM64_BTI !! 3031 config SYS_SUPPORTS_256HZ
2049 bool "Branch Target Identification su !! 3032 bool
2050 default y <<
2051 help <<
2052 Branch Target Identification (part <<
2053 provides a mechanism to limit the s <<
2054 branch instructions such as BR or B <<
2055 <<
2056 To make use of BTI on CPUs that sup <<
2057 <<
2058 BTI is intended to provide compleme <<
2059 flow integrity protection mechanism <<
2060 authentication mechanism provided a <<
2061 For this reason, it does not make s <<
2062 also enabling support for pointer a <<
2063 enabling this option you should als <<
2064 <<
2065 Userspace binaries must also be spe <<
2066 this mechanism. If you say N here <<
2067 BTI, such binaries can still run, b <<
2068 enforcement of branch destinations. <<
2069 3033
2070 config ARM64_BTI_KERNEL !! 3034 config SYS_SUPPORTS_1000HZ
2071 bool "Use Branch Target Identificatio !! 3035 bool
2072 default y <<
2073 depends on ARM64_BTI <<
2074 depends on ARM64_PTR_AUTH_KERNEL <<
2075 depends on CC_HAS_BRANCH_PROT_PAC_RET <<
2076 # https://gcc.gnu.org/bugzilla/show_b <<
2077 depends on !CC_IS_GCC || GCC_VERSION <<
2078 # https://gcc.gnu.org/bugzilla/show_b <<
2079 depends on !CC_IS_GCC <<
2080 depends on (!FUNCTION_GRAPH_TRACER || <<
2081 help <<
2082 Build the kernel with Branch Target <<
2083 and enable enforcement of this for <<
2084 is enabled and the system supports <<
2085 modular code must have BTI enabled. <<
2086 <<
2087 config CC_HAS_BRANCH_PROT_PAC_RET_BTI <<
2088 # GCC 9 or later, clang 8 or later <<
2089 def_bool $(cc-option,-mbranch-protect <<
2090 3036
2091 config ARM64_E0PD !! 3037 config SYS_SUPPORTS_1024HZ
2092 bool "Enable support for E0PD" !! 3038 bool
2093 default y <<
2094 help <<
2095 E0PD (part of the ARMv8.5 extension <<
2096 that EL0 accesses made via TTBR1 al <<
2097 providing similar benefits to KASLR <<
2098 with lower overhead and without dis <<
2099 kernel memory such as SPE. <<
2100 <<
2101 This option enables E0PD for TTBR1 <<
2102 <<
2103 config ARM64_AS_HAS_MTE <<
2104 # Initial support for MTE went in bin <<
2105 # ".arch armv8.5-a+memtag" below. How <<
2106 # as a late addition to the final arc <<
2107 # is only supported in the newer 2.32 <<
2108 # versions, hence the extra "stgm" in <<
2109 def_bool $(as-instr,.arch armv8.5-a+m <<
2110 3039
2111 config ARM64_MTE !! 3040 config SYS_SUPPORTS_ARBIT_HZ
2112 bool "Memory Tagging Extension suppor !! 3041 bool
2113 default y !! 3042 default y if !SYS_SUPPORTS_24HZ && \
2114 depends on ARM64_AS_HAS_MTE && ARM64_ !! 3043 !SYS_SUPPORTS_48HZ && \
2115 depends on AS_HAS_ARMV8_5 !! 3044 !SYS_SUPPORTS_100HZ && \
2116 depends on AS_HAS_LSE_ATOMICS !! 3045 !SYS_SUPPORTS_128HZ && \
2117 # Required for tag checking in the ua !! 3046 !SYS_SUPPORTS_250HZ && \
2118 depends on ARM64_PAN !! 3047 !SYS_SUPPORTS_256HZ && \
2119 select ARCH_HAS_SUBPAGE_FAULTS !! 3048 !SYS_SUPPORTS_1000HZ && \
2120 select ARCH_USES_HIGH_VMA_FLAGS !! 3049 !SYS_SUPPORTS_1024HZ
2121 select ARCH_USES_PG_ARCH_2 <<
2122 select ARCH_USES_PG_ARCH_3 <<
2123 help <<
2124 Memory Tagging (part of the ARMv8.5 <<
2125 architectural support for run-time, <<
2126 various classes of memory error to <<
2127 to eliminate vulnerabilities arisin <<
2128 languages. <<
2129 <<
2130 This option enables the support for <<
2131 Extension at EL0 (i.e. for userspac <<
2132 <<
2133 Selecting this option allows the fe <<
2134 runtime. Any secondary CPU not impl <<
2135 not be allowed a late bring-up. <<
2136 <<
2137 Userspace binaries that want to use <<
2138 explicitly opt in. The mechanism fo <<
2139 described in: <<
2140 3050
2141 Documentation/arch/arm64/memory-tag !! 3051 config HZ
>> 3052 int
>> 3053 default 24 if HZ_24
>> 3054 default 48 if HZ_48
>> 3055 default 100 if HZ_100
>> 3056 default 128 if HZ_128
>> 3057 default 250 if HZ_250
>> 3058 default 256 if HZ_256
>> 3059 default 1000 if HZ_1000
>> 3060 default 1024 if HZ_1024
>> 3061
>> 3062 config SCHED_HRTICK
>> 3063 def_bool HIGH_RES_TIMERS
>> 3064
>> 3065 config KEXEC
>> 3066 bool "Kexec system call"
>> 3067 select KEXEC_CORE
>> 3068 help
>> 3069 kexec is a system call that implements the ability to shutdown your
>> 3070 current kernel, and to start another kernel. It is like a reboot
>> 3071 but it is independent of the system firmware. And like a reboot
>> 3072 you can start any kernel with it, not just Linux.
>> 3073
>> 3074 The name comes from the similarity to the exec system call.
>> 3075
>> 3076 It is an ongoing process to be certain the hardware in a machine
>> 3077 is properly shutdown, so do not be surprised if this code does not
>> 3078 initially work for you. As of this writing the exact hardware
>> 3079 interface is strongly in flux, so no good recommendation can be
>> 3080 made.
>> 3081
>> 3082 config CRASH_DUMP
>> 3083 bool "Kernel crash dumps"
>> 3084 help
>> 3085 Generate crash dump after being started by kexec.
>> 3086 This should be normally only set in special crash dump kernels
>> 3087 which are loaded in the main kernel with kexec-tools into
>> 3088 a specially reserved region and then later executed after
>> 3089 a crash by kdump/kexec. The crash dump kernel must be compiled
>> 3090 to a memory address not used by the main kernel or firmware using
>> 3091 PHYSICAL_START.
>> 3092
>> 3093 config PHYSICAL_START
>> 3094 hex "Physical address where the kernel is loaded"
>> 3095 default "0xffffffff84000000"
>> 3096 depends on CRASH_DUMP
>> 3097 help
>> 3098 This gives the CKSEG0 or KSEG0 address where the kernel is loaded.
>> 3099 If you plan to use kernel for capturing the crash dump change
>> 3100 this value to start of the reserved region (the "X" value as
>> 3101 specified in the "crashkernel=YM@XM" command line boot parameter
>> 3102 passed to the panic-ed kernel).
>> 3103
>> 3104 config MIPS_O32_FP64_SUPPORT
>> 3105 bool "Support for O32 binaries using 64-bit FP" if !CPU_MIPSR6
>> 3106 depends on 32BIT || MIPS32_O32
>> 3107 help
>> 3108 When this is enabled, the kernel will support use of 64-bit floating
>> 3109 point registers with binaries using the O32 ABI along with the
>> 3110 EF_MIPS_FP64 ELF header flag (typically built with -mfp64). On
>> 3111 32-bit MIPS systems this support is at the cost of increasing the
>> 3112 size and complexity of the compiled FPU emulator. Thus if you are
>> 3113 running a MIPS32 system and know that none of your userland binaries
>> 3114 will require 64-bit floating point, you may wish to reduce the size
>> 3115 of your kernel & potentially improve FP emulation performance by
>> 3116 saying N here.
>> 3117
>> 3118 Although binutils currently supports use of this flag the details
>> 3119 concerning its effect upon the O32 ABI in userland are still being
>> 3120 worked on. In order to avoid userland becoming dependent upon current
>> 3121 behaviour before the details have been finalised, this option should
>> 3122 be considered experimental and only enabled by those working upon
>> 3123 said details.
2142 3124
2143 endmenu # "ARMv8.5 architectural features" !! 3125 If unsure, say N.
2144 3126
2145 menu "ARMv8.7 architectural features" !! 3127 config USE_OF
>> 3128 bool
>> 3129 select OF
>> 3130 select OF_EARLY_FLATTREE
>> 3131 select IRQ_DOMAIN
2146 3132
2147 config ARM64_EPAN !! 3133 config UHI_BOOT
2148 bool "Enable support for Enhanced Pri !! 3134 bool
2149 default y <<
2150 depends on ARM64_PAN <<
2151 help <<
2152 Enhanced Privileged Access Never (E <<
2153 Access Never to be used with Execut <<
2154 3135
2155 The feature is detected at runtime, !! 3136 config BUILTIN_DTB
2156 if the cpu does not implement the f !! 3137 bool
2157 endmenu # "ARMv8.7 architectural features" <<
2158 3138
2159 menu "ARMv8.9 architectural features" !! 3139 choice
>> 3140 prompt "Kernel appended dtb support" if USE_OF
>> 3141 default MIPS_NO_APPENDED_DTB
2160 3142
2161 config ARM64_POE !! 3143 config MIPS_NO_APPENDED_DTB
2162 prompt "Permission Overlay Extension" !! 3144 bool "None"
2163 def_bool y !! 3145 help
2164 select ARCH_USES_HIGH_VMA_FLAGS !! 3146 Do not enable appended dtb support.
2165 select ARCH_HAS_PKEYS !! 3147
2166 help !! 3148 config MIPS_ELF_APPENDED_DTB
2167 The Permission Overlay Extension is !! 3149 bool "vmlinux"
2168 Protection Keys. Memory Protection !! 3150 help
2169 enforcing page-based protections, b !! 3151 With this option, the boot code will look for a device tree binary
2170 of the page tables when an applicat !! 3152 DTB) included in the vmlinux ELF section .appended_dtb. By default
>> 3153 it is empty and the DTB can be appended using binutils command
>> 3154 objcopy:
>> 3155
>> 3156 objcopy --update-section .appended_dtb=<filename>.dtb vmlinux
>> 3157
>> 3158 This is meant as a backward compatibility convenience for those
>> 3159 systems with a bootloader that can't be upgraded to accommodate
>> 3160 the documented boot protocol using a device tree.
>> 3161
>> 3162 config MIPS_RAW_APPENDED_DTB
>> 3163 bool "vmlinux.bin or vmlinuz.bin"
>> 3164 help
>> 3165 With this option, the boot code will look for a device tree binary
>> 3166 DTB) appended to raw vmlinux.bin or vmlinuz.bin.
>> 3167 (e.g. cat vmlinux.bin <filename>.dtb > vmlinux_w_dtb).
>> 3168
>> 3169 This is meant as a backward compatibility convenience for those
>> 3170 systems with a bootloader that can't be upgraded to accommodate
>> 3171 the documented boot protocol using a device tree.
>> 3172
>> 3173 Beware that there is very little in terms of protection against
>> 3174 this option being confused by leftover garbage in memory that might
>> 3175 look like a DTB header after a reboot if no actual DTB is appended
>> 3176 to vmlinux.bin. Do not leave this option active in a production kernel
>> 3177 if you don't intend to always append a DTB.
>> 3178 endchoice
2171 3179
2172 For details, see Documentation/core !! 3180 choice
>> 3181 prompt "Kernel command line type" if !CMDLINE_OVERRIDE
>> 3182 default MIPS_CMDLINE_FROM_DTB if USE_OF && !ATH79 && !MACH_INGENIC && \
>> 3183 !MACH_LOONGSON64 && !MIPS_MALTA && \
>> 3184 !CAVIUM_OCTEON_SOC
>> 3185 default MIPS_CMDLINE_FROM_BOOTLOADER
>> 3186
>> 3187 config MIPS_CMDLINE_FROM_DTB
>> 3188 depends on USE_OF
>> 3189 bool "Dtb kernel arguments if available"
>> 3190
>> 3191 config MIPS_CMDLINE_DTB_EXTEND
>> 3192 depends on USE_OF
>> 3193 bool "Extend dtb kernel arguments with bootloader arguments"
>> 3194
>> 3195 config MIPS_CMDLINE_FROM_BOOTLOADER
>> 3196 bool "Bootloader kernel arguments if available"
>> 3197
>> 3198 config MIPS_CMDLINE_BUILTIN_EXTEND
>> 3199 depends on CMDLINE_BOOL
>> 3200 bool "Extend builtin kernel arguments with bootloader arguments"
>> 3201 endchoice
2173 3202
2174 If unsure, say y. !! 3203 endmenu
>> 3204
>> 3205 config LOCKDEP_SUPPORT
>> 3206 bool
>> 3207 default y
2175 3208
2176 config ARCH_PKEY_BITS !! 3209 config STACKTRACE_SUPPORT
>> 3210 bool
>> 3211 default y
>> 3212
>> 3213 config PGTABLE_LEVELS
2177 int 3214 int
2178 default 3 !! 3215 default 4 if PAGE_SIZE_4KB && MIPS_VA_BITS_48
>> 3216 default 3 if 64BIT && !PAGE_SIZE_64KB
>> 3217 default 2
2179 3218
2180 endmenu # "ARMv8.9 architectural features" !! 3219 config MIPS_AUTO_PFN_OFFSET
>> 3220 bool
2181 3221
2182 config ARM64_SVE !! 3222 menu "Bus options (PCI, PCMCIA, EISA, ISA, TC)"
2183 bool "ARM Scalable Vector Extension s <<
2184 default y <<
2185 help <<
2186 The Scalable Vector Extension (SVE) <<
2187 execution state which complements a <<
2188 of the base architecture to support <<
2189 additional vectorisation opportunit <<
2190 <<
2191 To enable use of this extension on <<
2192 <<
2193 On CPUs that support the SVE2 exten <<
2194 those too. <<
2195 <<
2196 Note that for architectural reasons <<
2197 support when running on SVE capable <<
2198 is present in: <<
2199 <<
2200 * version 1.5 and later of the AR <<
2201 * the AArch64 boot wrapper since <<
2202 ("bootwrapper: SVE: Enable SVE <<
2203 <<
2204 For other firmware implementations, <<
2205 or vendor. <<
2206 <<
2207 If you need the kernel to boot on S <<
2208 firmware, you may need to say N her <<
2209 fixed. Otherwise, you may experien <<
2210 booting the kernel. If unsure and <<
2211 symptoms, you should assume that it <<
2212 3223
2213 config ARM64_SME !! 3224 config PCI_DRIVERS_GENERIC
2214 bool "ARM Scalable Matrix Extension s !! 3225 select PCI_DOMAINS_GENERIC if PCI
2215 default y !! 3226 bool
2216 depends on ARM64_SVE <<
2217 depends on BROKEN <<
2218 help <<
2219 The Scalable Matrix Extension (SME) <<
2220 execution state which utilises a su <<
2221 instruction set, together with the <<
2222 register state capable of holding t <<
2223 enable various matrix operations. <<
2224 <<
2225 config ARM64_PSEUDO_NMI <<
2226 bool "Support for NMI-like interrupts <<
2227 select ARM_GIC_V3 <<
2228 help <<
2229 Adds support for mimicking Non-Mask <<
2230 GIC interrupt priority. This suppor <<
2231 ARM GIC. <<
2232 <<
2233 This high priority configuration fo <<
2234 explicitly enabled by setting the k <<
2235 "irqchip.gicv3_pseudo_nmi" to 1. <<
2236 <<
2237 If unsure, say N <<
2238 <<
2239 if ARM64_PSEUDO_NMI <<
2240 config ARM64_DEBUG_PRIORITY_MASKING <<
2241 bool "Debug interrupt priority maskin <<
2242 help <<
2243 This adds runtime checks to functio <<
2244 interrupts when using priority mask <<
2245 the validity of ICC_PMR_EL1 when ca <<
2246 3227
2247 If unsure, say N !! 3228 config PCI_DRIVERS_LEGACY
2248 endif # ARM64_PSEUDO_NMI !! 3229 def_bool !PCI_DRIVERS_GENERIC
>> 3230 select NO_GENERIC_PCI_IOPORT_MAP
>> 3231 select PCI_DOMAINS if PCI
2249 3232
2250 config RELOCATABLE !! 3233 #
2251 bool "Build a relocatable kernel imag !! 3234 # ISA support is now enabled via select. Too many systems still have the one
2252 select ARCH_HAS_RELR !! 3235 # or other ISA chip on the board that users don't know about so don't expect
>> 3236 # users to choose the right thing ...
>> 3237 #
>> 3238 config ISA
>> 3239 bool
>> 3240
>> 3241 config TC
>> 3242 bool "TURBOchannel support"
>> 3243 depends on MACH_DECSTATION
>> 3244 help
>> 3245 TURBOchannel is a DEC (now Compaq (now HP)) bus for Alpha and MIPS
>> 3246 processors. TURBOchannel programming specifications are available
>> 3247 at:
>> 3248 <ftp://ftp.hp.com/pub/alphaserver/archive/triadd/>
>> 3249 and:
>> 3250 <http://www.computer-refuge.org/classiccmp/ftp.digital.com/pub/DEC/TriAdd/>
>> 3251 Linux driver support status is documented at:
>> 3252 <http://www.linux-mips.org/wiki/DECstation>
>> 3253
>> 3254 config MMU
>> 3255 bool
2253 default y 3256 default y
2254 help <<
2255 This builds the kernel as a Positio <<
2256 which retains all relocation metada <<
2257 kernel binary at runtime to a diffe <<
2258 address it was linked at. <<
2259 Since AArch64 uses the RELA relocat <<
2260 relocation pass at runtime even if <<
2261 same address it was linked at. <<
2262 3257
2263 config RANDOMIZE_BASE !! 3258 config ARCH_MMAP_RND_BITS_MIN
2264 bool "Randomize the address of the ke !! 3259 default 12 if 64BIT
2265 select RELOCATABLE !! 3260 default 8
2266 help <<
2267 Randomizes the virtual address at w <<
2268 loaded, as a security feature that <<
2269 relying on knowledge of the locatio <<
2270 <<
2271 It is the bootloader's job to provi <<
2272 random u64 value in /chosen/kaslr-s <<
2273 <<
2274 When booting via the UEFI stub, it <<
2275 EFI_RNG_PROTOCOL implementation (if <<
2276 to the kernel proper. In addition, <<
2277 location of the kernel Image as wel <<
2278 3261
2279 If unsure, say N. !! 3262 config ARCH_MMAP_RND_BITS_MAX
>> 3263 default 18 if 64BIT
>> 3264 default 15
2280 3265
2281 config RANDOMIZE_MODULE_REGION_FULL !! 3266 config ARCH_MMAP_RND_COMPAT_BITS_MIN
2282 bool "Randomize the module region ove !! 3267 default 8
2283 depends on RANDOMIZE_BASE <<
2284 default y <<
2285 help <<
2286 Randomizes the location of the modu <<
2287 covering the core kernel. This way, <<
2288 to leak information about the locat <<
2289 but it does imply that function cal <<
2290 kernel will need to be resolved via <<
2291 <<
2292 When this option is not set, the mo <<
2293 a limited range that contains the [ <<
2294 core kernel, so branch relocations <<
2295 the region is exhausted. In this pa <<
2296 exhaustion, modules might be able t <<
2297 3268
2298 config CC_HAVE_STACKPROTECTOR_SYSREG !! 3269 config ARCH_MMAP_RND_COMPAT_BITS_MAX
2299 def_bool $(cc-option,-mstack-protecto !! 3270 default 15
2300 3271
2301 config STACKPROTECTOR_PER_TASK !! 3272 config I8253
2302 def_bool y !! 3273 bool
2303 depends on STACKPROTECTOR && CC_HAVE_ !! 3274 select CLKSRC_I8253
>> 3275 select CLKEVT_I8253
>> 3276 select MIPS_EXTERNAL_TIMER
>> 3277 endmenu
2304 3278
2305 config UNWIND_PATCH_PAC_INTO_SCS !! 3279 config TRAD_SIGNALS
2306 bool "Enable shadow call stack dynami !! 3280 bool
2307 # needs Clang with https://github.com <<
2308 depends on CC_IS_CLANG && CLANG_VERSI <<
2309 depends on ARM64_PTR_AUTH_KERNEL && C <<
2310 depends on SHADOW_CALL_STACK <<
2311 select UNWIND_TABLES <<
2312 select DYNAMIC_SCS <<
2313 <<
2314 config ARM64_CONTPTE <<
2315 bool "Contiguous PTE mappings for use <<
2316 depends on TRANSPARENT_HUGEPAGE <<
2317 default y <<
2318 help <<
2319 When enabled, user mappings are con <<
2320 bit, for any mappings that meet the <<
2321 This reduces TLB pressure and impro <<
2322 <<
2323 endmenu # "Kernel Features" <<
2324 <<
2325 menu "Boot options" <<
2326 <<
2327 config ARM64_ACPI_PARKING_PROTOCOL <<
2328 bool "Enable support for the ARM64 AC <<
2329 depends on ACPI <<
2330 help <<
2331 Enable support for the ARM64 ACPI p <<
2332 the kernel will not allow booting t <<
2333 protocol even if the corresponding <<
2334 MADT table. <<
2335 <<
2336 config CMDLINE <<
2337 string "Default kernel command string <<
2338 default "" <<
2339 help <<
2340 Provide a set of default command-li <<
2341 entering them here. As a minimum, y <<
2342 root device (e.g. root=/dev/nfs). <<
2343 3281
2344 choice !! 3282 config MIPS32_COMPAT
2345 prompt "Kernel command line type" !! 3283 bool
2346 depends on CMDLINE != "" <<
2347 default CMDLINE_FROM_BOOTLOADER <<
2348 help <<
2349 Choose how the kernel will handle t <<
2350 command line string. <<
2351 <<
2352 config CMDLINE_FROM_BOOTLOADER <<
2353 bool "Use bootloader kernel arguments <<
2354 help <<
2355 Uses the command-line options passe <<
2356 the boot loader doesn't provide any <<
2357 string provided in CMDLINE will be <<
2358 <<
2359 config CMDLINE_FORCE <<
2360 bool "Always use the default kernel c <<
2361 help <<
2362 Always use the default kernel comma <<
2363 loader passes other arguments to th <<
2364 This is useful if you cannot or don <<
2365 command-line options your boot load <<
2366 3284
2367 endchoice !! 3285 config COMPAT
>> 3286 bool
2368 3287
2369 config EFI_STUB !! 3288 config SYSVIPC_COMPAT
2370 bool 3289 bool
2371 3290
2372 config EFI !! 3291 config MIPS32_O32
2373 bool "UEFI runtime support" !! 3292 bool "Kernel support for o32 binaries"
2374 depends on OF && !CPU_BIG_ENDIAN !! 3293 depends on 64BIT
2375 depends on KERNEL_MODE_NEON !! 3294 select ARCH_WANT_OLD_COMPAT_IPC
2376 select ARCH_SUPPORTS_ACPI !! 3295 select COMPAT
2377 select LIBFDT !! 3296 select MIPS32_COMPAT
2378 select UCS2_STRING !! 3297 select SYSVIPC_COMPAT if SYSVIPC
2379 select EFI_PARAMS_FROM_FDT !! 3298 help
2380 select EFI_RUNTIME_WRAPPERS !! 3299 Select this option if you want to run o32 binaries. These are pure
2381 select EFI_STUB !! 3300 32-bit binaries as used by the 32-bit Linux/MIPS port. Most of
2382 select EFI_GENERIC_STUB !! 3301 existing binaries are in this format.
2383 imply IMA_SECURE_AND_OR_TRUSTED_BOOT <<
2384 default y <<
2385 help <<
2386 This option provides support for ru <<
2387 by UEFI firmware (such as non-volat <<
2388 clock, and platform reset). A UEFI <<
2389 allow the kernel to be booted as an <<
2390 is only useful on systems that have <<
2391 <<
2392 config COMPRESSED_INSTALL <<
2393 bool "Install compressed image by def <<
2394 help <<
2395 This makes the regular "make instal <<
2396 image we built, not the legacy unco <<
2397 <<
2398 You can check that a compressed ima <<
2399 "make zinstall" first, and verifyin <<
2400 in your environment before making " <<
2401 you. <<
2402 3302
2403 config DMI !! 3303 If unsure, say Y.
2404 bool "Enable support for SMBIOS (DMI) <<
2405 depends on EFI <<
2406 default y <<
2407 help <<
2408 This enables SMBIOS/DMI feature for <<
2409 3304
2410 This option is only useful on syste !! 3305 config MIPS32_N32
2411 However, even with this option, the !! 3306 bool "Kernel support for n32 binaries"
2412 continue to boot on existing non-UE !! 3307 depends on 64BIT
>> 3308 select ARCH_WANT_COMPAT_IPC_PARSE_VERSION
>> 3309 select COMPAT
>> 3310 select MIPS32_COMPAT
>> 3311 select SYSVIPC_COMPAT if SYSVIPC
>> 3312 help
>> 3313 Select this option if you want to run n32 binaries. These are
>> 3314 64-bit binaries using 32-bit quantities for addressing and certain
>> 3315 data that would normally be 64-bit. They are used in special
>> 3316 cases.
2413 3317
2414 endmenu # "Boot options" !! 3318 If unsure, say N.
2415 3319
2416 menu "Power management options" 3320 menu "Power management options"
2417 3321
2418 source "kernel/power/Kconfig" <<
2419 <<
2420 config ARCH_HIBERNATION_POSSIBLE 3322 config ARCH_HIBERNATION_POSSIBLE
2421 def_bool y 3323 def_bool y
2422 depends on CPU_PM !! 3324 depends on SYS_SUPPORTS_HOTPLUG_CPU || !SMP
2423 <<
2424 config ARCH_HIBERNATION_HEADER <<
2425 def_bool y <<
2426 depends on HIBERNATION <<
2427 3325
2428 config ARCH_SUSPEND_POSSIBLE 3326 config ARCH_SUSPEND_POSSIBLE
2429 def_bool y 3327 def_bool y
>> 3328 depends on SYS_SUPPORTS_HOTPLUG_CPU || !SMP
2430 3329
2431 endmenu # "Power management options" !! 3330 source "kernel/power/Kconfig"
2432 3331
2433 menu "CPU Power Management" !! 3332 endmenu
2434 3333
2435 source "drivers/cpuidle/Kconfig" !! 3334 config MIPS_EXTERNAL_TIMER
>> 3335 bool
>> 3336
>> 3337 menu "CPU Power Management"
2436 3338
>> 3339 if CPU_SUPPORTS_CPUFREQ && MIPS_EXTERNAL_TIMER
2437 source "drivers/cpufreq/Kconfig" 3340 source "drivers/cpufreq/Kconfig"
>> 3341 endif
>> 3342
>> 3343 source "drivers/cpuidle/Kconfig"
2438 3344
2439 endmenu # "CPU Power Management" !! 3345 endmenu
2440 3346
2441 source "drivers/acpi/Kconfig" !! 3347 source "drivers/firmware/Kconfig"
2442 3348
2443 source "arch/arm64/kvm/Kconfig" !! 3349 source "arch/mips/kvm/Kconfig"
2444 3350
>> 3351 source "arch/mips/vdso/Kconfig"
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