1 # SPDX-License-Identifier: GPL-2.0-only !! 1 # SPDX-License-Identifier: GPL-2.0
2 config ARM64 !! 2 config MIPS
3 def_bool y !! 3 bool
4 select ACPI_APMT if ACPI !! 4 default y
5 select ACPI_CCA_REQUIRED if ACPI !! 5 select ARCH_32BIT_OFF_T if !64BIT
6 select ACPI_GENERIC_GSI if ACPI !! 6 select ARCH_BINFMT_ELF_STATE if MIPS_FP_SUPPORT
7 select ACPI_GTDT if ACPI !! 7 select ARCH_HAS_CPU_FINALIZE_INIT
8 select ACPI_HOTPLUG_CPU if ACPI_PROCES !! 8 select ARCH_HAS_DEBUG_VIRTUAL if !64BIT
9 select ACPI_IORT if ACPI <<
10 select ACPI_REDUCED_HARDWARE_ONLY if A <<
11 select ACPI_MCFG if (ACPI && PCI) <<
12 select ACPI_SPCR_TABLE if ACPI <<
13 select ACPI_PPTT if ACPI <<
14 select ARCH_HAS_DEBUG_WX <<
15 select ARCH_BINFMT_ELF_EXTRA_PHDRS <<
16 select ARCH_BINFMT_ELF_STATE <<
17 select ARCH_CORRECT_STACKTRACE_ON_KRET <<
18 select ARCH_ENABLE_HUGEPAGE_MIGRATION <<
19 select ARCH_ENABLE_MEMORY_HOTPLUG <<
20 select ARCH_ENABLE_MEMORY_HOTREMOVE <<
21 select ARCH_ENABLE_SPLIT_PMD_PTLOCK if <<
22 select ARCH_ENABLE_THP_MIGRATION if TR <<
23 select ARCH_HAS_CACHE_LINE_SIZE <<
24 select ARCH_HAS_CURRENT_STACK_POINTER <<
25 select ARCH_HAS_DEBUG_VIRTUAL <<
26 select ARCH_HAS_DEBUG_VM_PGTABLE <<
27 select ARCH_HAS_DMA_OPS if XEN <<
28 select ARCH_HAS_DMA_PREP_COHERENT <<
29 select ARCH_HAS_ACPI_TABLE_UPGRADE if <<
30 select ARCH_HAS_FAST_MULTIPLIER <<
31 select ARCH_HAS_FORTIFY_SOURCE 9 select ARCH_HAS_FORTIFY_SOURCE
32 select ARCH_HAS_GCOV_PROFILE_ALL <<
33 select ARCH_HAS_GIGANTIC_PAGE <<
34 select ARCH_HAS_KCOV 10 select ARCH_HAS_KCOV
35 select ARCH_HAS_KERNEL_FPU_SUPPORT if !! 11 select ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE if !EVA
36 select ARCH_HAS_KEEPINITRD !! 12 select ARCH_HAS_PTE_SPECIAL if !(32BIT && CPU_HAS_RIXI)
37 select ARCH_HAS_MEMBARRIER_SYNC_CORE !! 13 select ARCH_HAS_STRNCPY_FROM_USER
38 select ARCH_HAS_MEM_ENCRYPT !! 14 select ARCH_HAS_STRNLEN_USER
39 select ARCH_HAS_NMI_SAFE_THIS_CPU_OPS <<
40 select ARCH_HAS_NON_OVERLAPPING_ADDRES <<
41 select ARCH_HAS_PTE_DEVMAP <<
42 select ARCH_HAS_PTE_SPECIAL <<
43 select ARCH_HAS_HW_PTE_YOUNG <<
44 select ARCH_HAS_SETUP_DMA_OPS <<
45 select ARCH_HAS_SET_DIRECT_MAP <<
46 select ARCH_HAS_SET_MEMORY <<
47 select ARCH_STACKWALK <<
48 select ARCH_HAS_STRICT_KERNEL_RWX <<
49 select ARCH_HAS_STRICT_MODULE_RWX <<
50 select ARCH_HAS_SYNC_DMA_FOR_DEVICE <<
51 select ARCH_HAS_SYNC_DMA_FOR_CPU <<
52 select ARCH_HAS_SYSCALL_WRAPPER <<
53 select ARCH_HAS_TICK_BROADCAST if GENE 15 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
54 select ARCH_HAS_ZONE_DMA_SET if EXPERT !! 16 select ARCH_HAS_UBSAN_SANITIZE_ALL
55 select ARCH_HAVE_ELF_PROT !! 17 select ARCH_HAS_GCOV_PROFILE_ALL
56 select ARCH_HAVE_NMI_SAFE_CMPXCHG <<
57 select ARCH_HAVE_TRACE_MMIO_ACCESS <<
58 select ARCH_INLINE_READ_LOCK if !PREEM <<
59 select ARCH_INLINE_READ_LOCK_BH if !PR <<
60 select ARCH_INLINE_READ_LOCK_IRQ if !P <<
61 select ARCH_INLINE_READ_LOCK_IRQSAVE i <<
62 select ARCH_INLINE_READ_UNLOCK if !PRE <<
63 select ARCH_INLINE_READ_UNLOCK_BH if ! <<
64 select ARCH_INLINE_READ_UNLOCK_IRQ if <<
65 select ARCH_INLINE_READ_UNLOCK_IRQREST <<
66 select ARCH_INLINE_WRITE_LOCK if !PREE <<
67 select ARCH_INLINE_WRITE_LOCK_BH if !P <<
68 select ARCH_INLINE_WRITE_LOCK_IRQ if ! <<
69 select ARCH_INLINE_WRITE_LOCK_IRQSAVE <<
70 select ARCH_INLINE_WRITE_UNLOCK if !PR <<
71 select ARCH_INLINE_WRITE_UNLOCK_BH if <<
72 select ARCH_INLINE_WRITE_UNLOCK_IRQ if <<
73 select ARCH_INLINE_WRITE_UNLOCK_IRQRES <<
74 select ARCH_INLINE_SPIN_TRYLOCK if !PR <<
75 select ARCH_INLINE_SPIN_TRYLOCK_BH if <<
76 select ARCH_INLINE_SPIN_LOCK if !PREEM <<
77 select ARCH_INLINE_SPIN_LOCK_BH if !PR <<
78 select ARCH_INLINE_SPIN_LOCK_IRQ if !P <<
79 select ARCH_INLINE_SPIN_LOCK_IRQSAVE i <<
80 select ARCH_INLINE_SPIN_UNLOCK if !PRE <<
81 select ARCH_INLINE_SPIN_UNLOCK_BH if ! <<
82 select ARCH_INLINE_SPIN_UNLOCK_IRQ if <<
83 select ARCH_INLINE_SPIN_UNLOCK_IRQREST <<
84 select ARCH_KEEP_MEMBLOCK 18 select ARCH_KEEP_MEMBLOCK
85 select ARCH_MHP_MEMMAP_ON_MEMORY_ENABL !! 19 select ARCH_SUPPORTS_UPROBES
86 select ARCH_USE_CMPXCHG_LOCKREF !! 20 select ARCH_USE_BUILTIN_BSWAP
87 select ARCH_USE_GNU_PROPERTY !! 21 select ARCH_USE_CMPXCHG_LOCKREF if 64BIT
88 select ARCH_USE_MEMTEST 22 select ARCH_USE_MEMTEST
89 select ARCH_USE_QUEUED_RWLOCKS 23 select ARCH_USE_QUEUED_RWLOCKS
90 select ARCH_USE_QUEUED_SPINLOCKS 24 select ARCH_USE_QUEUED_SPINLOCKS
91 select ARCH_USE_SYM_ANNOTATIONS !! 25 select ARCH_SUPPORTS_HUGETLBFS if CPU_SUPPORTS_HUGEPAGES
92 select ARCH_SUPPORTS_DEBUG_PAGEALLOC !! 26 select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT if MMU
93 select ARCH_SUPPORTS_HUGETLBFS !! 27 select ARCH_WANT_IPC_PARSE_VERSION
94 select ARCH_SUPPORTS_MEMORY_FAILURE <<
95 select ARCH_SUPPORTS_SHADOW_CALL_STACK <<
96 select ARCH_SUPPORTS_LTO_CLANG if CPU_ <<
97 select ARCH_SUPPORTS_LTO_CLANG_THIN <<
98 select ARCH_SUPPORTS_CFI_CLANG <<
99 select ARCH_SUPPORTS_ATOMIC_RMW <<
100 select ARCH_SUPPORTS_INT128 if CC_HAS_ <<
101 select ARCH_SUPPORTS_NUMA_BALANCING <<
102 select ARCH_SUPPORTS_PAGE_TABLE_CHECK <<
103 select ARCH_SUPPORTS_PER_VMA_LOCK <<
104 select ARCH_SUPPORTS_HUGE_PFNMAP if TR <<
105 select ARCH_SUPPORTS_RT <<
106 select ARCH_WANT_BATCHED_UNMAP_TLB_FLU <<
107 select ARCH_WANT_COMPAT_IPC_PARSE_VERS <<
108 select ARCH_WANT_DEFAULT_BPF_JIT <<
109 select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_ <<
110 select ARCH_WANT_FRAME_POINTERS <<
111 select ARCH_WANT_HUGE_PMD_SHARE if ARM <<
112 select ARCH_WANT_LD_ORPHAN_WARN 28 select ARCH_WANT_LD_ORPHAN_WARN
113 select ARCH_WANTS_EXECMEM_LATE if EXEC <<
114 select ARCH_WANTS_NO_INSTR <<
115 select ARCH_WANTS_THP_SWAP if ARM64_4K <<
116 select ARCH_HAS_UBSAN <<
117 select ARM_AMBA <<
118 select ARM_ARCH_TIMER <<
119 select ARM_GIC <<
120 select AUDIT_ARCH_COMPAT_GENERIC <<
121 select ARM_GIC_V2M if PCI <<
122 select ARM_GIC_V3 <<
123 select ARM_GIC_V3_ITS if PCI <<
124 select ARM_PSCI_FW <<
125 select BUILDTIME_TABLE_SORT 29 select BUILDTIME_TABLE_SORT
126 select CLONE_BACKWARDS 30 select CLONE_BACKWARDS
127 select COMMON_CLK !! 31 select CPU_NO_EFFICIENT_FFS if (TARGET_ISA_REV < 1)
128 select CPU_PM if (SUSPEND || CPU_IDLE) !! 32 select CPU_PM if CPU_IDLE
129 select CPUMASK_OFFSTACK if NR_CPUS > 2 !! 33 select GENERIC_ATOMIC64 if !64BIT
130 select CRC32 !! 34 select GENERIC_CMOS_UPDATE
131 select DCACHE_WORD_ACCESS <<
132 select DYNAMIC_FTRACE if FUNCTION_TRAC <<
133 select DMA_BOUNCE_UNALIGNED_KMALLOC <<
134 select DMA_DIRECT_REMAP <<
135 select EDAC_SUPPORT <<
136 select FRAME_POINTER <<
137 select FUNCTION_ALIGNMENT_4B <<
138 select FUNCTION_ALIGNMENT_8B if DYNAMI <<
139 select GENERIC_ALLOCATOR <<
140 select GENERIC_ARCH_TOPOLOGY <<
141 select GENERIC_CLOCKEVENTS_BROADCAST <<
142 select GENERIC_CPU_AUTOPROBE 35 select GENERIC_CPU_AUTOPROBE
143 select GENERIC_CPU_DEVICES !! 36 select GENERIC_FIND_FIRST_BIT
144 select GENERIC_CPU_VULNERABILITIES !! 37 select GENERIC_GETTIMEOFDAY
145 select GENERIC_EARLY_IOREMAP !! 38 select GENERIC_IOMAP
146 select GENERIC_IDLE_POLL_SETUP <<
147 select GENERIC_IOREMAP <<
148 select GENERIC_IRQ_IPI <<
149 select GENERIC_IRQ_PROBE 39 select GENERIC_IRQ_PROBE
150 select GENERIC_IRQ_SHOW 40 select GENERIC_IRQ_SHOW
151 select GENERIC_IRQ_SHOW_LEVEL !! 41 select GENERIC_ISA_DMA if EISA
152 select GENERIC_LIB_DEVMEM_IS_ALLOWED !! 42 select GENERIC_LIB_ASHLDI3
153 select GENERIC_PCI_IOMAP !! 43 select GENERIC_LIB_ASHRDI3
154 select GENERIC_PTDUMP !! 44 select GENERIC_LIB_CMPDI2
155 select GENERIC_SCHED_CLOCK !! 45 select GENERIC_LIB_LSHRDI3
>> 46 select GENERIC_LIB_UCMPDI2
>> 47 select GENERIC_SCHED_CLOCK if !CAVIUM_OCTEON_SOC
156 select GENERIC_SMP_IDLE_THREAD 48 select GENERIC_SMP_IDLE_THREAD
157 select GENERIC_TIME_VSYSCALL 49 select GENERIC_TIME_VSYSCALL
158 select GENERIC_GETTIMEOFDAY !! 50 select GUP_GET_PTE_LOW_HIGH if CPU_MIPS32 && PHYS_ADDR_T_64BIT
159 select GENERIC_VDSO_TIME_NS !! 51 select HANDLE_DOMAIN_IRQ
160 select HARDIRQS_SW_RESEND <<
161 select HAS_IOPORT <<
162 select HAVE_MOVE_PMD <<
163 select HAVE_MOVE_PUD <<
164 select HAVE_PCI <<
165 select HAVE_ACPI_APEI if (ACPI && EFI) <<
166 select HAVE_ALIGNED_STRUCT_PAGE <<
167 select HAVE_ARCH_AUDITSYSCALL <<
168 select HAVE_ARCH_BITREVERSE <<
169 select HAVE_ARCH_COMPILER_H 52 select HAVE_ARCH_COMPILER_H
170 select HAVE_ARCH_HUGE_VMALLOC <<
171 select HAVE_ARCH_HUGE_VMAP <<
172 select HAVE_ARCH_JUMP_LABEL 53 select HAVE_ARCH_JUMP_LABEL
173 select HAVE_ARCH_JUMP_LABEL_RELATIVE !! 54 select HAVE_ARCH_KGDB if MIPS_FP_SUPPORT
174 select HAVE_ARCH_KASAN !! 55 select HAVE_ARCH_MMAP_RND_BITS if MMU
175 select HAVE_ARCH_KASAN_VMALLOC !! 56 select HAVE_ARCH_MMAP_RND_COMPAT_BITS if MMU && COMPAT
176 select HAVE_ARCH_KASAN_SW_TAGS <<
177 select HAVE_ARCH_KASAN_HW_TAGS if ARM6 <<
178 # Some instrumentation may be unsound, <<
179 select HAVE_ARCH_KCSAN if EXPERT <<
180 select HAVE_ARCH_KFENCE <<
181 select HAVE_ARCH_KGDB <<
182 select HAVE_ARCH_MMAP_RND_BITS <<
183 select HAVE_ARCH_MMAP_RND_COMPAT_BITS <<
184 select HAVE_ARCH_PREL32_RELOCATIONS <<
185 select HAVE_ARCH_RANDOMIZE_KSTACK_OFFS <<
186 select HAVE_ARCH_SECCOMP_FILTER 57 select HAVE_ARCH_SECCOMP_FILTER
187 select HAVE_ARCH_STACKLEAK <<
188 select HAVE_ARCH_THREAD_STRUCT_WHITELI <<
189 select HAVE_ARCH_TRACEHOOK 58 select HAVE_ARCH_TRACEHOOK
190 select HAVE_ARCH_TRANSPARENT_HUGEPAGE !! 59 select HAVE_ARCH_TRANSPARENT_HUGEPAGE if CPU_SUPPORTS_HUGEPAGES
191 select HAVE_ARCH_VMAP_STACK <<
192 select HAVE_ARM_SMCCC <<
193 select HAVE_ASM_MODVERSIONS 60 select HAVE_ASM_MODVERSIONS
194 select HAVE_EBPF_JIT !! 61 select HAVE_CBPF_JIT if !64BIT && !CPU_MICROMIPS
>> 62 select HAVE_CONTEXT_TRACKING
>> 63 select HAVE_TIF_NOHZ
195 select HAVE_C_RECORDMCOUNT 64 select HAVE_C_RECORDMCOUNT
196 select HAVE_CMPXCHG_DOUBLE <<
197 select HAVE_CMPXCHG_LOCAL <<
198 select HAVE_CONTEXT_TRACKING_USER <<
199 select HAVE_DEBUG_KMEMLEAK 65 select HAVE_DEBUG_KMEMLEAK
>> 66 select HAVE_DEBUG_STACKOVERFLOW
200 select HAVE_DMA_CONTIGUOUS 67 select HAVE_DMA_CONTIGUOUS
201 select HAVE_DYNAMIC_FTRACE 68 select HAVE_DYNAMIC_FTRACE
202 select HAVE_DYNAMIC_FTRACE_WITH_ARGS \ !! 69 select HAVE_EBPF_JIT if 64BIT && !CPU_MICROMIPS && TARGET_ISA_REV >= 2
203 if (GCC_SUPPORTS_DYNAMIC_FTRAC !! 70 select HAVE_EXIT_THREAD
204 CLANG_SUPPORTS_DYNAMIC_FTR !! 71 select HAVE_FAST_GUP
205 select HAVE_DYNAMIC_FTRACE_WITH_DIRECT <<
206 if DYNAMIC_FTRACE_WITH_ARGS && <<
207 select HAVE_DYNAMIC_FTRACE_WITH_CALL_O <<
208 if (DYNAMIC_FTRACE_WITH_ARGS & <<
209 (CC_IS_CLANG || !CC_OPTIMI <<
210 select FTRACE_MCOUNT_USE_PATCHABLE_FUN <<
211 if DYNAMIC_FTRACE_WITH_ARGS <<
212 select HAVE_SAMPLE_FTRACE_DIRECT <<
213 select HAVE_SAMPLE_FTRACE_DIRECT_MULTI <<
214 select HAVE_EFFICIENT_UNALIGNED_ACCESS <<
215 select HAVE_GUP_FAST <<
216 select HAVE_FTRACE_MCOUNT_RECORD 72 select HAVE_FTRACE_MCOUNT_RECORD
217 select HAVE_FUNCTION_TRACER <<
218 select HAVE_FUNCTION_ERROR_INJECTION <<
219 select HAVE_FUNCTION_GRAPH_TRACER 73 select HAVE_FUNCTION_GRAPH_TRACER
220 select HAVE_FUNCTION_GRAPH_RETVAL !! 74 select HAVE_FUNCTION_TRACER
221 select HAVE_GCC_PLUGINS 75 select HAVE_GCC_PLUGINS
222 select HAVE_HARDLOCKUP_DETECTOR_PERF i !! 76 select HAVE_GENERIC_VDSO
223 HW_PERF_EVENTS && HAVE_PERF_EV <<
224 select HAVE_HW_BREAKPOINT if PERF_EVEN <<
225 select HAVE_IOREMAP_PROT 77 select HAVE_IOREMAP_PROT
>> 78 select HAVE_IRQ_EXIT_ON_IRQ_STACK
226 select HAVE_IRQ_TIME_ACCOUNTING 79 select HAVE_IRQ_TIME_ACCOUNTING
>> 80 select HAVE_KPROBES
>> 81 select HAVE_KRETPROBES
>> 82 select HAVE_LD_DEAD_CODE_DATA_ELIMINATION
227 select HAVE_MOD_ARCH_SPECIFIC 83 select HAVE_MOD_ARCH_SPECIFIC
228 select HAVE_NMI 84 select HAVE_NMI
>> 85 select HAVE_PATA_PLATFORM
229 select HAVE_PERF_EVENTS 86 select HAVE_PERF_EVENTS
230 select HAVE_PERF_EVENTS_NMI if ARM64_P <<
231 select HAVE_PERF_REGS 87 select HAVE_PERF_REGS
232 select HAVE_PERF_USER_STACK_DUMP 88 select HAVE_PERF_USER_STACK_DUMP
233 select HAVE_PREEMPT_DYNAMIC_KEY <<
234 select HAVE_REGS_AND_STACK_ACCESS_API 89 select HAVE_REGS_AND_STACK_ACCESS_API
235 select HAVE_POSIX_CPU_TIMERS_TASK_WORK <<
236 select HAVE_FUNCTION_ARG_ACCESS_API <<
237 select MMU_GATHER_RCU_TABLE_FREE <<
238 select HAVE_RSEQ 90 select HAVE_RSEQ
239 select HAVE_RUST if RUSTC_SUPPORTS_ARM !! 91 select HAVE_SPARSE_SYSCALL_NR
240 select HAVE_STACKPROTECTOR 92 select HAVE_STACKPROTECTOR
241 select HAVE_SYSCALL_TRACEPOINTS 93 select HAVE_SYSCALL_TRACEPOINTS
242 select HAVE_KPROBES !! 94 select HAVE_VIRT_CPU_ACCOUNTING_GEN if 64BIT || !SMP
243 select HAVE_KRETPROBES <<
244 select HAVE_GENERIC_VDSO <<
245 select HOTPLUG_CORE_SYNC_DEAD if HOTPL <<
246 select IRQ_DOMAIN <<
247 select IRQ_FORCED_THREADING 95 select IRQ_FORCED_THREADING
248 select KASAN_VMALLOC if KASAN !! 96 select ISA if EISA
249 select LOCK_MM_AND_FIND_VMA !! 97 select MODULES_USE_ELF_REL if MODULES
250 select MODULES_USE_ELF_RELA !! 98 select MODULES_USE_ELF_RELA if MODULES && 64BIT
251 select NEED_DMA_MAP_STATE !! 99 select PERF_USE_VMALLOC
252 select NEED_SG_DMA_LENGTH !! 100 select PCI_MSI_ARCH_FALLBACKS if PCI_MSI
253 select OF !! 101 select RTC_LIB
254 select OF_EARLY_FLATTREE <<
255 select PCI_DOMAINS_GENERIC if PCI <<
256 select PCI_ECAM if (ACPI && PCI) <<
257 select PCI_SYSCALL if PCI <<
258 select POWER_RESET <<
259 select POWER_SUPPLY <<
260 select SPARSE_IRQ <<
261 select SWIOTLB <<
262 select SYSCTL_EXCEPTION_TRACE 102 select SYSCTL_EXCEPTION_TRACE
263 select THREAD_INFO_IN_TASK <<
264 select HAVE_ARCH_USERFAULTFD_MINOR if <<
265 select HAVE_ARCH_USERFAULTFD_WP if USE <<
266 select TRACE_IRQFLAGS_SUPPORT 103 select TRACE_IRQFLAGS_SUPPORT
267 select TRACE_IRQFLAGS_NMI_SUPPORT !! 104 select VIRT_TO_BUS
268 select HAVE_SOFTIRQ_ON_OWN_STACK !! 105 select ARCH_HAS_ELFCORE_COMPAT
269 select USER_STACKTRACE_SUPPORT !! 106
270 select VDSO_GETRANDOM !! 107 config MIPS_FIXUP_BIGPHYS_ADDR
>> 108 bool
>> 109
>> 110 config MIPS_GENERIC
>> 111 bool
>> 112
>> 113 config MACH_INGENIC
>> 114 bool
>> 115 select SYS_SUPPORTS_32BIT_KERNEL
>> 116 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 117 select SYS_SUPPORTS_ZBOOT
>> 118 select DMA_NONCOHERENT
>> 119 select ARCH_HAS_SYNC_DMA_FOR_CPU
>> 120 select IRQ_MIPS_CPU
>> 121 select PINCTRL
>> 122 select GPIOLIB
>> 123 select COMMON_CLK
>> 124 select GENERIC_IRQ_CHIP
>> 125 select BUILTIN_DTB if MIPS_NO_APPENDED_DTB
>> 126 select USE_OF
>> 127 select CPU_SUPPORTS_CPUFREQ
>> 128 select MIPS_EXTERNAL_TIMER
>> 129
>> 130 menu "Machine selection"
>> 131
>> 132 choice
>> 133 prompt "System type"
>> 134 default MIPS_GENERIC_KERNEL
>> 135
>> 136 config MIPS_GENERIC_KERNEL
>> 137 bool "Generic board-agnostic MIPS kernel"
>> 138 select ARCH_HAS_SETUP_DMA_OPS
>> 139 select MIPS_GENERIC
>> 140 select BOOT_RAW
>> 141 select BUILTIN_DTB
>> 142 select CEVT_R4K
>> 143 select CLKSRC_MIPS_GIC
>> 144 select COMMON_CLK
>> 145 select CPU_MIPSR2_IRQ_EI
>> 146 select CPU_MIPSR2_IRQ_VI
>> 147 select CSRC_R4K
>> 148 select DMA_NONCOHERENT
>> 149 select HAVE_PCI
>> 150 select IRQ_MIPS_CPU
>> 151 select MIPS_AUTO_PFN_OFFSET
>> 152 select MIPS_CPU_SCACHE
>> 153 select MIPS_GIC
>> 154 select MIPS_L1_CACHE_SHIFT_7
>> 155 select NO_EXCEPT_FILL
>> 156 select PCI_DRIVERS_GENERIC
>> 157 select SMP_UP if SMP
>> 158 select SWAP_IO_SPACE
>> 159 select SYS_HAS_CPU_MIPS32_R1
>> 160 select SYS_HAS_CPU_MIPS32_R2
>> 161 select SYS_HAS_CPU_MIPS32_R6
>> 162 select SYS_HAS_CPU_MIPS64_R1
>> 163 select SYS_HAS_CPU_MIPS64_R2
>> 164 select SYS_HAS_CPU_MIPS64_R6
>> 165 select SYS_SUPPORTS_32BIT_KERNEL
>> 166 select SYS_SUPPORTS_64BIT_KERNEL
>> 167 select SYS_SUPPORTS_BIG_ENDIAN
>> 168 select SYS_SUPPORTS_HIGHMEM
>> 169 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 170 select SYS_SUPPORTS_MICROMIPS
>> 171 select SYS_SUPPORTS_MIPS16
>> 172 select SYS_SUPPORTS_MIPS_CPS
>> 173 select SYS_SUPPORTS_MULTITHREADING
>> 174 select SYS_SUPPORTS_RELOCATABLE
>> 175 select SYS_SUPPORTS_SMARTMIPS
>> 176 select SYS_SUPPORTS_ZBOOT
>> 177 select UHI_BOOT
>> 178 select USB_EHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
>> 179 select USB_EHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 180 select USB_OHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
>> 181 select USB_OHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 182 select USB_UHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
>> 183 select USB_UHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 184 select USE_OF
>> 185 help
>> 186 Select this to build a kernel which aims to support multiple boards,
>> 187 generally using a flattened device tree passed from the bootloader
>> 188 using the boot protocol defined in the UHI (Unified Hosting
>> 189 Interface) specification.
>> 190
>> 191 config MIPS_ALCHEMY
>> 192 bool "Alchemy processor based machines"
>> 193 select PHYS_ADDR_T_64BIT
>> 194 select CEVT_R4K
>> 195 select CSRC_R4K
>> 196 select IRQ_MIPS_CPU
>> 197 select DMA_NONCOHERENT # Au1000,1500,1100 aren't, rest is
>> 198 select MIPS_FIXUP_BIGPHYS_ADDR if PCI
>> 199 select SYS_HAS_CPU_MIPS32_R1
>> 200 select SYS_SUPPORTS_32BIT_KERNEL
>> 201 select SYS_SUPPORTS_APM_EMULATION
>> 202 select GPIOLIB
>> 203 select SYS_SUPPORTS_ZBOOT
>> 204 select COMMON_CLK
>> 205
>> 206 config AR7
>> 207 bool "Texas Instruments AR7"
>> 208 select BOOT_ELF32
>> 209 select COMMON_CLK
>> 210 select DMA_NONCOHERENT
>> 211 select CEVT_R4K
>> 212 select CSRC_R4K
>> 213 select IRQ_MIPS_CPU
>> 214 select NO_EXCEPT_FILL
>> 215 select SWAP_IO_SPACE
>> 216 select SYS_HAS_CPU_MIPS32_R1
>> 217 select SYS_HAS_EARLY_PRINTK
>> 218 select SYS_SUPPORTS_32BIT_KERNEL
>> 219 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 220 select SYS_SUPPORTS_MIPS16
>> 221 select SYS_SUPPORTS_ZBOOT_UART16550
>> 222 select GPIOLIB
>> 223 select VLYNQ
>> 224 help
>> 225 Support for the Texas Instruments AR7 System-on-a-Chip
>> 226 family: TNETD7100, 7200 and 7300.
>> 227
>> 228 config ATH25
>> 229 bool "Atheros AR231x/AR531x SoC support"
>> 230 select CEVT_R4K
>> 231 select CSRC_R4K
>> 232 select DMA_NONCOHERENT
>> 233 select IRQ_MIPS_CPU
>> 234 select IRQ_DOMAIN
>> 235 select SYS_HAS_CPU_MIPS32_R1
>> 236 select SYS_SUPPORTS_BIG_ENDIAN
>> 237 select SYS_SUPPORTS_32BIT_KERNEL
>> 238 select SYS_HAS_EARLY_PRINTK
>> 239 help
>> 240 Support for Atheros AR231x and Atheros AR531x based boards
>> 241
>> 242 config ATH79
>> 243 bool "Atheros AR71XX/AR724X/AR913X based boards"
>> 244 select ARCH_HAS_RESET_CONTROLLER
>> 245 select BOOT_RAW
>> 246 select CEVT_R4K
>> 247 select CSRC_R4K
>> 248 select DMA_NONCOHERENT
>> 249 select GPIOLIB
>> 250 select PINCTRL
>> 251 select COMMON_CLK
>> 252 select IRQ_MIPS_CPU
>> 253 select SYS_HAS_CPU_MIPS32_R2
>> 254 select SYS_HAS_EARLY_PRINTK
>> 255 select SYS_SUPPORTS_32BIT_KERNEL
>> 256 select SYS_SUPPORTS_BIG_ENDIAN
>> 257 select SYS_SUPPORTS_MIPS16
>> 258 select SYS_SUPPORTS_ZBOOT_UART_PROM
>> 259 select USE_OF
>> 260 select USB_EHCI_ROOT_HUB_TT if USB_EHCI_HCD_PLATFORM
>> 261 help
>> 262 Support for the Atheros AR71XX/AR724X/AR913X SoCs.
>> 263
>> 264 config BMIPS_GENERIC
>> 265 bool "Broadcom Generic BMIPS kernel"
>> 266 select ARCH_HAS_RESET_CONTROLLER
>> 267 select ARCH_HAS_SYNC_DMA_FOR_CPU_ALL
>> 268 select ARCH_HAS_PHYS_TO_DMA
>> 269 select BOOT_RAW
>> 270 select NO_EXCEPT_FILL
>> 271 select USE_OF
>> 272 select CEVT_R4K
>> 273 select CSRC_R4K
>> 274 select SYNC_R4K
>> 275 select COMMON_CLK
>> 276 select BCM6345_L1_IRQ
>> 277 select BCM7038_L1_IRQ
>> 278 select BCM7120_L2_IRQ
>> 279 select BRCMSTB_L2_IRQ
>> 280 select IRQ_MIPS_CPU
>> 281 select DMA_NONCOHERENT
>> 282 select SYS_SUPPORTS_32BIT_KERNEL
>> 283 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 284 select SYS_SUPPORTS_BIG_ENDIAN
>> 285 select SYS_SUPPORTS_HIGHMEM
>> 286 select SYS_HAS_CPU_BMIPS32_3300
>> 287 select SYS_HAS_CPU_BMIPS4350
>> 288 select SYS_HAS_CPU_BMIPS4380
>> 289 select SYS_HAS_CPU_BMIPS5000
>> 290 select SWAP_IO_SPACE
>> 291 select USB_EHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
>> 292 select USB_EHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 293 select USB_OHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
>> 294 select USB_OHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 295 select HARDIRQS_SW_RESEND
271 help 296 help
272 ARM 64-bit (AArch64) Linux support. !! 297 Build a generic DT-based kernel image that boots on select
>> 298 BCM33xx cable modem chips, BCM63xx DSL chips, and BCM7xxx set-top
>> 299 box chips. Note that CONFIG_CPU_BIG_ENDIAN/CONFIG_CPU_LITTLE_ENDIAN
>> 300 must be set appropriately for your board.
>> 301
>> 302 config BCM47XX
>> 303 bool "Broadcom BCM47XX based boards"
>> 304 select BOOT_RAW
>> 305 select CEVT_R4K
>> 306 select CSRC_R4K
>> 307 select DMA_NONCOHERENT
>> 308 select HAVE_PCI
>> 309 select IRQ_MIPS_CPU
>> 310 select SYS_HAS_CPU_MIPS32_R1
>> 311 select NO_EXCEPT_FILL
>> 312 select SYS_SUPPORTS_32BIT_KERNEL
>> 313 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 314 select SYS_SUPPORTS_MIPS16
>> 315 select SYS_SUPPORTS_ZBOOT
>> 316 select SYS_HAS_EARLY_PRINTK
>> 317 select USE_GENERIC_EARLY_PRINTK_8250
>> 318 select GPIOLIB
>> 319 select LEDS_GPIO_REGISTER
>> 320 select BCM47XX_NVRAM
>> 321 select BCM47XX_SPROM
>> 322 select BCM47XX_SSB if !BCM47XX_BCMA
>> 323 help
>> 324 Support for BCM47XX based boards
>> 325
>> 326 config BCM63XX
>> 327 bool "Broadcom BCM63XX based boards"
>> 328 select BOOT_RAW
>> 329 select CEVT_R4K
>> 330 select CSRC_R4K
>> 331 select SYNC_R4K
>> 332 select DMA_NONCOHERENT
>> 333 select IRQ_MIPS_CPU
>> 334 select SYS_SUPPORTS_32BIT_KERNEL
>> 335 select SYS_SUPPORTS_BIG_ENDIAN
>> 336 select SYS_HAS_EARLY_PRINTK
>> 337 select SYS_HAS_CPU_BMIPS32_3300
>> 338 select SYS_HAS_CPU_BMIPS4350
>> 339 select SYS_HAS_CPU_BMIPS4380
>> 340 select SWAP_IO_SPACE
>> 341 select GPIOLIB
>> 342 select MIPS_L1_CACHE_SHIFT_4
>> 343 select HAVE_LEGACY_CLK
>> 344 help
>> 345 Support for BCM63XX based boards
>> 346
>> 347 config MIPS_COBALT
>> 348 bool "Cobalt Server"
>> 349 select CEVT_R4K
>> 350 select CSRC_R4K
>> 351 select CEVT_GT641XX
>> 352 select DMA_NONCOHERENT
>> 353 select FORCE_PCI
>> 354 select I8253
>> 355 select I8259
>> 356 select IRQ_MIPS_CPU
>> 357 select IRQ_GT641XX
>> 358 select PCI_GT64XXX_PCI0
>> 359 select SYS_HAS_CPU_NEVADA
>> 360 select SYS_HAS_EARLY_PRINTK
>> 361 select SYS_SUPPORTS_32BIT_KERNEL
>> 362 select SYS_SUPPORTS_64BIT_KERNEL
>> 363 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 364 select USE_GENERIC_EARLY_PRINTK_8250
>> 365
>> 366 config MACH_DECSTATION
>> 367 bool "DECstations"
>> 368 select BOOT_ELF32
>> 369 select CEVT_DS1287
>> 370 select CEVT_R4K if CPU_R4X00
>> 371 select CSRC_IOASIC
>> 372 select CSRC_R4K if CPU_R4X00
>> 373 select CPU_DADDI_WORKAROUNDS if 64BIT
>> 374 select CPU_R4000_WORKAROUNDS if 64BIT
>> 375 select CPU_R4400_WORKAROUNDS if 64BIT
>> 376 select DMA_NONCOHERENT
>> 377 select NO_IOPORT_MAP
>> 378 select IRQ_MIPS_CPU
>> 379 select SYS_HAS_CPU_R3000
>> 380 select SYS_HAS_CPU_R4X00
>> 381 select SYS_SUPPORTS_32BIT_KERNEL
>> 382 select SYS_SUPPORTS_64BIT_KERNEL
>> 383 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 384 select SYS_SUPPORTS_128HZ
>> 385 select SYS_SUPPORTS_256HZ
>> 386 select SYS_SUPPORTS_1024HZ
>> 387 select MIPS_L1_CACHE_SHIFT_4
>> 388 help
>> 389 This enables support for DEC's MIPS based workstations. For details
>> 390 see the Linux/MIPS FAQ on <http://www.linux-mips.org/> and the
>> 391 DECstation porting pages on <http://decstation.unix-ag.org/>.
>> 392
>> 393 If you have one of the following DECstation Models you definitely
>> 394 want to choose R4xx0 for the CPU Type:
>> 395
>> 396 DECstation 5000/50
>> 397 DECstation 5000/150
>> 398 DECstation 5000/260
>> 399 DECsystem 5900/260
>> 400
>> 401 otherwise choose R3000.
>> 402
>> 403 config MACH_JAZZ
>> 404 bool "Jazz family of machines"
>> 405 select ARC_MEMORY
>> 406 select ARC_PROMLIB
>> 407 select ARCH_MIGHT_HAVE_PC_PARPORT
>> 408 select ARCH_MIGHT_HAVE_PC_SERIO
>> 409 select DMA_OPS
>> 410 select FW_ARC
>> 411 select FW_ARC32
>> 412 select ARCH_MAY_HAVE_PC_FDC
>> 413 select CEVT_R4K
>> 414 select CSRC_R4K
>> 415 select DEFAULT_SGI_PARTITION if CPU_BIG_ENDIAN
>> 416 select GENERIC_ISA_DMA
>> 417 select HAVE_PCSPKR_PLATFORM
>> 418 select IRQ_MIPS_CPU
>> 419 select I8253
>> 420 select I8259
>> 421 select ISA
>> 422 select SYS_HAS_CPU_R4X00
>> 423 select SYS_SUPPORTS_32BIT_KERNEL
>> 424 select SYS_SUPPORTS_64BIT_KERNEL
>> 425 select SYS_SUPPORTS_100HZ
>> 426 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 427 help
>> 428 This a family of machines based on the MIPS R4030 chipset which was
>> 429 used by several vendors to build RISC/os and Windows NT workstations.
>> 430 Members include the Acer PICA, MIPS Magnum 4000, MIPS Millennium and
>> 431 Olivetti M700-10 workstations.
>> 432
>> 433 config MACH_INGENIC_SOC
>> 434 bool "Ingenic SoC based machines"
>> 435 select MIPS_GENERIC
>> 436 select MACH_INGENIC
>> 437 select SYS_SUPPORTS_ZBOOT_UART16550
>> 438 select CPU_SUPPORTS_CPUFREQ
>> 439 select MIPS_EXTERNAL_TIMER
>> 440
>> 441 config LANTIQ
>> 442 bool "Lantiq based platforms"
>> 443 select DMA_NONCOHERENT
>> 444 select IRQ_MIPS_CPU
>> 445 select CEVT_R4K
>> 446 select CSRC_R4K
>> 447 select SYS_HAS_CPU_MIPS32_R1
>> 448 select SYS_HAS_CPU_MIPS32_R2
>> 449 select SYS_SUPPORTS_BIG_ENDIAN
>> 450 select SYS_SUPPORTS_32BIT_KERNEL
>> 451 select SYS_SUPPORTS_MIPS16
>> 452 select SYS_SUPPORTS_MULTITHREADING
>> 453 select SYS_SUPPORTS_VPE_LOADER
>> 454 select SYS_HAS_EARLY_PRINTK
>> 455 select GPIOLIB
>> 456 select SWAP_IO_SPACE
>> 457 select BOOT_RAW
>> 458 select HAVE_LEGACY_CLK
>> 459 select USE_OF
>> 460 select PINCTRL
>> 461 select PINCTRL_LANTIQ
>> 462 select ARCH_HAS_RESET_CONTROLLER
>> 463 select RESET_CONTROLLER
>> 464
>> 465 config MACH_LOONGSON32
>> 466 bool "Loongson 32-bit family of machines"
>> 467 select SYS_SUPPORTS_ZBOOT
>> 468 help
>> 469 This enables support for the Loongson-1 family of machines.
>> 470
>> 471 Loongson-1 is a family of 32-bit MIPS-compatible SoCs developed by
>> 472 the Institute of Computing Technology (ICT), Chinese Academy of
>> 473 Sciences (CAS).
>> 474
>> 475 config MACH_LOONGSON2EF
>> 476 bool "Loongson-2E/F family of machines"
>> 477 select SYS_SUPPORTS_ZBOOT
>> 478 help
>> 479 This enables the support of early Loongson-2E/F family of machines.
>> 480
>> 481 config MACH_LOONGSON64
>> 482 bool "Loongson 64-bit family of machines"
>> 483 select ARCH_DMA_DEFAULT_COHERENT
>> 484 select ARCH_SPARSEMEM_ENABLE
>> 485 select ARCH_MIGHT_HAVE_PC_PARPORT
>> 486 select ARCH_MIGHT_HAVE_PC_SERIO
>> 487 select GENERIC_ISA_DMA_SUPPORT_BROKEN
>> 488 select BOOT_ELF32
>> 489 select BOARD_SCACHE
>> 490 select CSRC_R4K
>> 491 select CEVT_R4K
>> 492 select CPU_HAS_WB
>> 493 select FORCE_PCI
>> 494 select ISA
>> 495 select I8259
>> 496 select IRQ_MIPS_CPU
>> 497 select NO_EXCEPT_FILL
>> 498 select NR_CPUS_DEFAULT_64
>> 499 select USE_GENERIC_EARLY_PRINTK_8250
>> 500 select PCI_DRIVERS_GENERIC
>> 501 select SYS_HAS_CPU_LOONGSON64
>> 502 select SYS_HAS_EARLY_PRINTK
>> 503 select SYS_SUPPORTS_SMP
>> 504 select SYS_SUPPORTS_HOTPLUG_CPU
>> 505 select SYS_SUPPORTS_NUMA
>> 506 select SYS_SUPPORTS_64BIT_KERNEL
>> 507 select SYS_SUPPORTS_HIGHMEM
>> 508 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 509 select SYS_SUPPORTS_ZBOOT
>> 510 select SYS_SUPPORTS_RELOCATABLE
>> 511 select ZONE_DMA32
>> 512 select COMMON_CLK
>> 513 select USE_OF
>> 514 select BUILTIN_DTB
>> 515 select PCI_HOST_GENERIC
>> 516 help
>> 517 This enables the support of Loongson-2/3 family of machines.
>> 518
>> 519 Loongson-2 and Loongson-3 are 64-bit general-purpose processors with
>> 520 GS264/GS464/GS464E/GS464V microarchitecture (except old Loongson-2E
>> 521 and Loongson-2F which will be removed), developed by the Institute
>> 522 of Computing Technology (ICT), Chinese Academy of Sciences (CAS).
>> 523
>> 524 config MIPS_MALTA
>> 525 bool "MIPS Malta board"
>> 526 select ARCH_MAY_HAVE_PC_FDC
>> 527 select ARCH_MIGHT_HAVE_PC_PARPORT
>> 528 select ARCH_MIGHT_HAVE_PC_SERIO
>> 529 select BOOT_ELF32
>> 530 select BOOT_RAW
>> 531 select BUILTIN_DTB
>> 532 select CEVT_R4K
>> 533 select CLKSRC_MIPS_GIC
>> 534 select COMMON_CLK
>> 535 select CSRC_R4K
>> 536 select DMA_NONCOHERENT
>> 537 select GENERIC_ISA_DMA
>> 538 select HAVE_PCSPKR_PLATFORM
>> 539 select HAVE_PCI
>> 540 select I8253
>> 541 select I8259
>> 542 select IRQ_MIPS_CPU
>> 543 select MIPS_BONITO64
>> 544 select MIPS_CPU_SCACHE
>> 545 select MIPS_GIC
>> 546 select MIPS_L1_CACHE_SHIFT_6
>> 547 select MIPS_MSC
>> 548 select PCI_GT64XXX_PCI0
>> 549 select SMP_UP if SMP
>> 550 select SWAP_IO_SPACE
>> 551 select SYS_HAS_CPU_MIPS32_R1
>> 552 select SYS_HAS_CPU_MIPS32_R2
>> 553 select SYS_HAS_CPU_MIPS32_R3_5
>> 554 select SYS_HAS_CPU_MIPS32_R5
>> 555 select SYS_HAS_CPU_MIPS32_R6
>> 556 select SYS_HAS_CPU_MIPS64_R1
>> 557 select SYS_HAS_CPU_MIPS64_R2
>> 558 select SYS_HAS_CPU_MIPS64_R6
>> 559 select SYS_HAS_CPU_NEVADA
>> 560 select SYS_HAS_CPU_RM7000
>> 561 select SYS_SUPPORTS_32BIT_KERNEL
>> 562 select SYS_SUPPORTS_64BIT_KERNEL
>> 563 select SYS_SUPPORTS_BIG_ENDIAN
>> 564 select SYS_SUPPORTS_HIGHMEM
>> 565 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 566 select SYS_SUPPORTS_MICROMIPS
>> 567 select SYS_SUPPORTS_MIPS16
>> 568 select SYS_SUPPORTS_MIPS_CMP
>> 569 select SYS_SUPPORTS_MIPS_CPS
>> 570 select SYS_SUPPORTS_MULTITHREADING
>> 571 select SYS_SUPPORTS_RELOCATABLE
>> 572 select SYS_SUPPORTS_SMARTMIPS
>> 573 select SYS_SUPPORTS_VPE_LOADER
>> 574 select SYS_SUPPORTS_ZBOOT
>> 575 select USE_OF
>> 576 select WAR_ICACHE_REFILLS
>> 577 select ZONE_DMA32 if 64BIT
>> 578 help
>> 579 This enables support for the MIPS Technologies Malta evaluation
>> 580 board.
>> 581
>> 582 config MACH_PIC32
>> 583 bool "Microchip PIC32 Family"
>> 584 help
>> 585 This enables support for the Microchip PIC32 family of platforms.
>> 586
>> 587 Microchip PIC32 is a family of general-purpose 32 bit MIPS core
>> 588 microcontrollers.
>> 589
>> 590 config MACH_VR41XX
>> 591 bool "NEC VR4100 series based machines"
>> 592 select CEVT_R4K
>> 593 select CSRC_R4K
>> 594 select SYS_HAS_CPU_VR41XX
>> 595 select SYS_SUPPORTS_MIPS16
>> 596 select GPIOLIB
>> 597
>> 598 config MACH_NINTENDO64
>> 599 bool "Nintendo 64 console"
>> 600 select CEVT_R4K
>> 601 select CSRC_R4K
>> 602 select SYS_HAS_CPU_R4300
>> 603 select SYS_SUPPORTS_BIG_ENDIAN
>> 604 select SYS_SUPPORTS_ZBOOT
>> 605 select SYS_SUPPORTS_32BIT_KERNEL
>> 606 select SYS_SUPPORTS_64BIT_KERNEL
>> 607 select DMA_NONCOHERENT
>> 608 select IRQ_MIPS_CPU
>> 609
>> 610 config RALINK
>> 611 bool "Ralink based machines"
>> 612 select CEVT_R4K
>> 613 select COMMON_CLK
>> 614 select CSRC_R4K
>> 615 select BOOT_RAW
>> 616 select DMA_NONCOHERENT
>> 617 select IRQ_MIPS_CPU
>> 618 select USE_OF
>> 619 select SYS_HAS_CPU_MIPS32_R1
>> 620 select SYS_HAS_CPU_MIPS32_R2
>> 621 select SYS_SUPPORTS_32BIT_KERNEL
>> 622 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 623 select SYS_SUPPORTS_MIPS16
>> 624 select SYS_SUPPORTS_ZBOOT
>> 625 select SYS_HAS_EARLY_PRINTK
>> 626 select ARCH_HAS_RESET_CONTROLLER
>> 627 select RESET_CONTROLLER
>> 628
>> 629 config MACH_REALTEK_RTL
>> 630 bool "Realtek RTL838x/RTL839x based machines"
>> 631 select MIPS_GENERIC
>> 632 select DMA_NONCOHERENT
>> 633 select IRQ_MIPS_CPU
>> 634 select CSRC_R4K
>> 635 select CEVT_R4K
>> 636 select SYS_HAS_CPU_MIPS32_R1
>> 637 select SYS_HAS_CPU_MIPS32_R2
>> 638 select SYS_SUPPORTS_BIG_ENDIAN
>> 639 select SYS_SUPPORTS_32BIT_KERNEL
>> 640 select SYS_SUPPORTS_MIPS16
>> 641 select SYS_SUPPORTS_MULTITHREADING
>> 642 select SYS_SUPPORTS_VPE_LOADER
>> 643 select SYS_HAS_EARLY_PRINTK
>> 644 select SYS_HAS_EARLY_PRINTK_8250
>> 645 select USE_GENERIC_EARLY_PRINTK_8250
>> 646 select BOOT_RAW
>> 647 select PINCTRL
>> 648 select USE_OF
>> 649
>> 650 config SGI_IP22
>> 651 bool "SGI IP22 (Indy/Indigo2)"
>> 652 select ARC_MEMORY
>> 653 select ARC_PROMLIB
>> 654 select FW_ARC
>> 655 select FW_ARC32
>> 656 select ARCH_MIGHT_HAVE_PC_SERIO
>> 657 select BOOT_ELF32
>> 658 select CEVT_R4K
>> 659 select CSRC_R4K
>> 660 select DEFAULT_SGI_PARTITION
>> 661 select DMA_NONCOHERENT
>> 662 select HAVE_EISA
>> 663 select I8253
>> 664 select I8259
>> 665 select IP22_CPU_SCACHE
>> 666 select IRQ_MIPS_CPU
>> 667 select GENERIC_ISA_DMA_SUPPORT_BROKEN
>> 668 select SGI_HAS_I8042
>> 669 select SGI_HAS_INDYDOG
>> 670 select SGI_HAS_HAL2
>> 671 select SGI_HAS_SEEQ
>> 672 select SGI_HAS_WD93
>> 673 select SGI_HAS_ZILOG
>> 674 select SWAP_IO_SPACE
>> 675 select SYS_HAS_CPU_R4X00
>> 676 select SYS_HAS_CPU_R5000
>> 677 select SYS_HAS_EARLY_PRINTK
>> 678 select SYS_SUPPORTS_32BIT_KERNEL
>> 679 select SYS_SUPPORTS_64BIT_KERNEL
>> 680 select SYS_SUPPORTS_BIG_ENDIAN
>> 681 select WAR_R4600_V1_INDEX_ICACHEOP
>> 682 select WAR_R4600_V1_HIT_CACHEOP
>> 683 select WAR_R4600_V2_HIT_CACHEOP
>> 684 select MIPS_L1_CACHE_SHIFT_7
>> 685 help
>> 686 This are the SGI Indy, Challenge S and Indigo2, as well as certain
>> 687 OEM variants like the Tandem CMN B006S. To compile a Linux kernel
>> 688 that runs on these, say Y here.
>> 689
>> 690 config SGI_IP27
>> 691 bool "SGI IP27 (Origin200/2000)"
>> 692 select ARCH_HAS_PHYS_TO_DMA
>> 693 select ARCH_SPARSEMEM_ENABLE
>> 694 select FW_ARC
>> 695 select FW_ARC64
>> 696 select ARC_CMDLINE_ONLY
>> 697 select BOOT_ELF64
>> 698 select DEFAULT_SGI_PARTITION
>> 699 select FORCE_PCI
>> 700 select SYS_HAS_EARLY_PRINTK
>> 701 select HAVE_PCI
>> 702 select IRQ_MIPS_CPU
>> 703 select IRQ_DOMAIN_HIERARCHY
>> 704 select NR_CPUS_DEFAULT_64
>> 705 select PCI_DRIVERS_GENERIC
>> 706 select PCI_XTALK_BRIDGE
>> 707 select SYS_HAS_CPU_R10000
>> 708 select SYS_SUPPORTS_64BIT_KERNEL
>> 709 select SYS_SUPPORTS_BIG_ENDIAN
>> 710 select SYS_SUPPORTS_NUMA
>> 711 select SYS_SUPPORTS_SMP
>> 712 select WAR_R10000_LLSC
>> 713 select MIPS_L1_CACHE_SHIFT_7
>> 714 select NUMA
>> 715 help
>> 716 This are the SGI Origin 200, Origin 2000 and Onyx 2 Graphics
>> 717 workstations. To compile a Linux kernel that runs on these, say Y
>> 718 here.
>> 719
>> 720 config SGI_IP28
>> 721 bool "SGI IP28 (Indigo2 R10k)"
>> 722 select ARC_MEMORY
>> 723 select ARC_PROMLIB
>> 724 select FW_ARC
>> 725 select FW_ARC64
>> 726 select ARCH_MIGHT_HAVE_PC_SERIO
>> 727 select BOOT_ELF64
>> 728 select CEVT_R4K
>> 729 select CSRC_R4K
>> 730 select DEFAULT_SGI_PARTITION
>> 731 select DMA_NONCOHERENT
>> 732 select GENERIC_ISA_DMA_SUPPORT_BROKEN
>> 733 select IRQ_MIPS_CPU
>> 734 select HAVE_EISA
>> 735 select I8253
>> 736 select I8259
>> 737 select SGI_HAS_I8042
>> 738 select SGI_HAS_INDYDOG
>> 739 select SGI_HAS_HAL2
>> 740 select SGI_HAS_SEEQ
>> 741 select SGI_HAS_WD93
>> 742 select SGI_HAS_ZILOG
>> 743 select SWAP_IO_SPACE
>> 744 select SYS_HAS_CPU_R10000
>> 745 select SYS_HAS_EARLY_PRINTK
>> 746 select SYS_SUPPORTS_64BIT_KERNEL
>> 747 select SYS_SUPPORTS_BIG_ENDIAN
>> 748 select WAR_R10000_LLSC
>> 749 select MIPS_L1_CACHE_SHIFT_7
>> 750 help
>> 751 This is the SGI Indigo2 with R10000 processor. To compile a Linux
>> 752 kernel that runs on these, say Y here.
>> 753
>> 754 config SGI_IP30
>> 755 bool "SGI IP30 (Octane/Octane2)"
>> 756 select ARCH_HAS_PHYS_TO_DMA
>> 757 select FW_ARC
>> 758 select FW_ARC64
>> 759 select BOOT_ELF64
>> 760 select CEVT_R4K
>> 761 select CSRC_R4K
>> 762 select FORCE_PCI
>> 763 select SYNC_R4K if SMP
>> 764 select ZONE_DMA32
>> 765 select HAVE_PCI
>> 766 select IRQ_MIPS_CPU
>> 767 select IRQ_DOMAIN_HIERARCHY
>> 768 select NR_CPUS_DEFAULT_2
>> 769 select PCI_DRIVERS_GENERIC
>> 770 select PCI_XTALK_BRIDGE
>> 771 select SYS_HAS_EARLY_PRINTK
>> 772 select SYS_HAS_CPU_R10000
>> 773 select SYS_SUPPORTS_64BIT_KERNEL
>> 774 select SYS_SUPPORTS_BIG_ENDIAN
>> 775 select SYS_SUPPORTS_SMP
>> 776 select WAR_R10000_LLSC
>> 777 select MIPS_L1_CACHE_SHIFT_7
>> 778 select ARC_MEMORY
>> 779 help
>> 780 These are the SGI Octane and Octane2 graphics workstations. To
>> 781 compile a Linux kernel that runs on these, say Y here.
>> 782
>> 783 config SGI_IP32
>> 784 bool "SGI IP32 (O2)"
>> 785 select ARC_MEMORY
>> 786 select ARC_PROMLIB
>> 787 select ARCH_HAS_PHYS_TO_DMA
>> 788 select FW_ARC
>> 789 select FW_ARC32
>> 790 select BOOT_ELF32
>> 791 select CEVT_R4K
>> 792 select CSRC_R4K
>> 793 select DMA_NONCOHERENT
>> 794 select HAVE_PCI
>> 795 select IRQ_MIPS_CPU
>> 796 select R5000_CPU_SCACHE
>> 797 select RM7000_CPU_SCACHE
>> 798 select SYS_HAS_CPU_R5000
>> 799 select SYS_HAS_CPU_R10000 if BROKEN
>> 800 select SYS_HAS_CPU_RM7000
>> 801 select SYS_HAS_CPU_NEVADA
>> 802 select SYS_SUPPORTS_64BIT_KERNEL
>> 803 select SYS_SUPPORTS_BIG_ENDIAN
>> 804 select WAR_ICACHE_REFILLS
>> 805 help
>> 806 If you want this kernel to run on SGI O2 workstation, say Y here.
>> 807
>> 808 config SIBYTE_CRHINE
>> 809 bool "Sibyte BCM91120C-CRhine"
>> 810 select BOOT_ELF32
>> 811 select SIBYTE_BCM1120
>> 812 select SWAP_IO_SPACE
>> 813 select SYS_HAS_CPU_SB1
>> 814 select SYS_SUPPORTS_BIG_ENDIAN
>> 815 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 816
>> 817 config SIBYTE_CARMEL
>> 818 bool "Sibyte BCM91120x-Carmel"
>> 819 select BOOT_ELF32
>> 820 select SIBYTE_BCM1120
>> 821 select SWAP_IO_SPACE
>> 822 select SYS_HAS_CPU_SB1
>> 823 select SYS_SUPPORTS_BIG_ENDIAN
>> 824 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 825
>> 826 config SIBYTE_CRHONE
>> 827 bool "Sibyte BCM91125C-CRhone"
>> 828 select BOOT_ELF32
>> 829 select SIBYTE_BCM1125
>> 830 select SWAP_IO_SPACE
>> 831 select SYS_HAS_CPU_SB1
>> 832 select SYS_SUPPORTS_BIG_ENDIAN
>> 833 select SYS_SUPPORTS_HIGHMEM
>> 834 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 835
>> 836 config SIBYTE_RHONE
>> 837 bool "Sibyte BCM91125E-Rhone"
>> 838 select BOOT_ELF32
>> 839 select SIBYTE_BCM1125H
>> 840 select SWAP_IO_SPACE
>> 841 select SYS_HAS_CPU_SB1
>> 842 select SYS_SUPPORTS_BIG_ENDIAN
>> 843 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 844
>> 845 config SIBYTE_SWARM
>> 846 bool "Sibyte BCM91250A-SWARM"
>> 847 select BOOT_ELF32
>> 848 select HAVE_PATA_PLATFORM
>> 849 select SIBYTE_SB1250
>> 850 select SWAP_IO_SPACE
>> 851 select SYS_HAS_CPU_SB1
>> 852 select SYS_SUPPORTS_BIG_ENDIAN
>> 853 select SYS_SUPPORTS_HIGHMEM
>> 854 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 855 select ZONE_DMA32 if 64BIT
>> 856 select SWIOTLB if ARCH_DMA_ADDR_T_64BIT && PCI
>> 857
>> 858 config SIBYTE_LITTLESUR
>> 859 bool "Sibyte BCM91250C2-LittleSur"
>> 860 select BOOT_ELF32
>> 861 select HAVE_PATA_PLATFORM
>> 862 select SIBYTE_SB1250
>> 863 select SWAP_IO_SPACE
>> 864 select SYS_HAS_CPU_SB1
>> 865 select SYS_SUPPORTS_BIG_ENDIAN
>> 866 select SYS_SUPPORTS_HIGHMEM
>> 867 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 868 select ZONE_DMA32 if 64BIT
>> 869
>> 870 config SIBYTE_SENTOSA
>> 871 bool "Sibyte BCM91250E-Sentosa"
>> 872 select BOOT_ELF32
>> 873 select SIBYTE_SB1250
>> 874 select SWAP_IO_SPACE
>> 875 select SYS_HAS_CPU_SB1
>> 876 select SYS_SUPPORTS_BIG_ENDIAN
>> 877 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 878 select SWIOTLB if ARCH_DMA_ADDR_T_64BIT && PCI
>> 879
>> 880 config SIBYTE_BIGSUR
>> 881 bool "Sibyte BCM91480B-BigSur"
>> 882 select BOOT_ELF32
>> 883 select NR_CPUS_DEFAULT_4
>> 884 select SIBYTE_BCM1x80
>> 885 select SWAP_IO_SPACE
>> 886 select SYS_HAS_CPU_SB1
>> 887 select SYS_SUPPORTS_BIG_ENDIAN
>> 888 select SYS_SUPPORTS_HIGHMEM
>> 889 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 890 select ZONE_DMA32 if 64BIT
>> 891 select SWIOTLB if ARCH_DMA_ADDR_T_64BIT && PCI
>> 892
>> 893 config SNI_RM
>> 894 bool "SNI RM200/300/400"
>> 895 select ARC_MEMORY
>> 896 select ARC_PROMLIB
>> 897 select FW_ARC if CPU_LITTLE_ENDIAN
>> 898 select FW_ARC32 if CPU_LITTLE_ENDIAN
>> 899 select FW_SNIPROM if CPU_BIG_ENDIAN
>> 900 select ARCH_MAY_HAVE_PC_FDC
>> 901 select ARCH_MIGHT_HAVE_PC_PARPORT
>> 902 select ARCH_MIGHT_HAVE_PC_SERIO
>> 903 select BOOT_ELF32
>> 904 select CEVT_R4K
>> 905 select CSRC_R4K
>> 906 select DEFAULT_SGI_PARTITION if CPU_BIG_ENDIAN
>> 907 select DMA_NONCOHERENT
>> 908 select GENERIC_ISA_DMA
>> 909 select HAVE_EISA
>> 910 select HAVE_PCSPKR_PLATFORM
>> 911 select HAVE_PCI
>> 912 select IRQ_MIPS_CPU
>> 913 select I8253
>> 914 select I8259
>> 915 select ISA
>> 916 select MIPS_L1_CACHE_SHIFT_6
>> 917 select SWAP_IO_SPACE if CPU_BIG_ENDIAN
>> 918 select SYS_HAS_CPU_R4X00
>> 919 select SYS_HAS_CPU_R5000
>> 920 select SYS_HAS_CPU_R10000
>> 921 select R5000_CPU_SCACHE
>> 922 select SYS_HAS_EARLY_PRINTK
>> 923 select SYS_SUPPORTS_32BIT_KERNEL
>> 924 select SYS_SUPPORTS_64BIT_KERNEL
>> 925 select SYS_SUPPORTS_BIG_ENDIAN
>> 926 select SYS_SUPPORTS_HIGHMEM
>> 927 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 928 select WAR_R4600_V2_HIT_CACHEOP
>> 929 help
>> 930 The SNI RM200/300/400 are MIPS-based machines manufactured by
>> 931 Siemens Nixdorf Informationssysteme (SNI), parent company of Pyramid
>> 932 Technology and now in turn merged with Fujitsu. Say Y here to
>> 933 support this machine type.
>> 934
>> 935 config MACH_TX39XX
>> 936 bool "Toshiba TX39 series based machines"
>> 937
>> 938 config MACH_TX49XX
>> 939 bool "Toshiba TX49 series based machines"
>> 940 select WAR_TX49XX_ICACHE_INDEX_INV
>> 941
>> 942 config MIKROTIK_RB532
>> 943 bool "Mikrotik RB532 boards"
>> 944 select CEVT_R4K
>> 945 select CSRC_R4K
>> 946 select DMA_NONCOHERENT
>> 947 select HAVE_PCI
>> 948 select IRQ_MIPS_CPU
>> 949 select SYS_HAS_CPU_MIPS32_R1
>> 950 select SYS_SUPPORTS_32BIT_KERNEL
>> 951 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 952 select SWAP_IO_SPACE
>> 953 select BOOT_RAW
>> 954 select GPIOLIB
>> 955 select MIPS_L1_CACHE_SHIFT_4
>> 956 help
>> 957 Support the Mikrotik(tm) RouterBoard 532 series,
>> 958 based on the IDT RC32434 SoC.
>> 959
>> 960 config CAVIUM_OCTEON_SOC
>> 961 bool "Cavium Networks Octeon SoC based boards"
>> 962 select CEVT_R4K
>> 963 select ARCH_HAS_PHYS_TO_DMA
>> 964 select HAVE_RAPIDIO
>> 965 select PHYS_ADDR_T_64BIT
>> 966 select SYS_SUPPORTS_64BIT_KERNEL
>> 967 select SYS_SUPPORTS_BIG_ENDIAN
>> 968 select EDAC_SUPPORT
>> 969 select EDAC_ATOMIC_SCRUB
>> 970 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 971 select SYS_SUPPORTS_HOTPLUG_CPU if CPU_BIG_ENDIAN
>> 972 select SYS_HAS_EARLY_PRINTK
>> 973 select SYS_HAS_CPU_CAVIUM_OCTEON
>> 974 select HAVE_PCI
>> 975 select HAVE_PLAT_DELAY
>> 976 select HAVE_PLAT_FW_INIT_CMDLINE
>> 977 select HAVE_PLAT_MEMCPY
>> 978 select ZONE_DMA32
>> 979 select GPIOLIB
>> 980 select USE_OF
>> 981 select ARCH_SPARSEMEM_ENABLE
>> 982 select SYS_SUPPORTS_SMP
>> 983 select NR_CPUS_DEFAULT_64
>> 984 select MIPS_NR_CPU_NR_MAP_1024
>> 985 select BUILTIN_DTB
>> 986 select MTD
>> 987 select MTD_COMPLEX_MAPPINGS
>> 988 select SWIOTLB
>> 989 select SYS_SUPPORTS_RELOCATABLE
>> 990 help
>> 991 This option supports all of the Octeon reference boards from Cavium
>> 992 Networks. It builds a kernel that dynamically determines the Octeon
>> 993 CPU type and supports all known board reference implementations.
>> 994 Some of the supported boards are:
>> 995 EBT3000
>> 996 EBH3000
>> 997 EBH3100
>> 998 Thunder
>> 999 Kodama
>> 1000 Hikari
>> 1001 Say Y here for most Octeon reference boards.
>> 1002
>> 1003 config NLM_XLR_BOARD
>> 1004 bool "Netlogic XLR/XLS based systems"
>> 1005 select BOOT_ELF32
>> 1006 select NLM_COMMON
>> 1007 select SYS_HAS_CPU_XLR
>> 1008 select SYS_SUPPORTS_SMP
>> 1009 select HAVE_PCI
>> 1010 select SWAP_IO_SPACE
>> 1011 select SYS_SUPPORTS_32BIT_KERNEL
>> 1012 select SYS_SUPPORTS_64BIT_KERNEL
>> 1013 select PHYS_ADDR_T_64BIT
>> 1014 select SYS_SUPPORTS_BIG_ENDIAN
>> 1015 select SYS_SUPPORTS_HIGHMEM
>> 1016 select NR_CPUS_DEFAULT_32
>> 1017 select CEVT_R4K
>> 1018 select CSRC_R4K
>> 1019 select IRQ_MIPS_CPU
>> 1020 select ZONE_DMA32 if 64BIT
>> 1021 select SYNC_R4K
>> 1022 select SYS_HAS_EARLY_PRINTK
>> 1023 select SYS_SUPPORTS_ZBOOT
>> 1024 select SYS_SUPPORTS_ZBOOT_UART16550
>> 1025 help
>> 1026 Support for systems based on Netlogic XLR and XLS processors.
>> 1027 Say Y here if you have a XLR or XLS based board.
>> 1028
>> 1029 config NLM_XLP_BOARD
>> 1030 bool "Netlogic XLP based systems"
>> 1031 select BOOT_ELF32
>> 1032 select NLM_COMMON
>> 1033 select SYS_HAS_CPU_XLP
>> 1034 select SYS_SUPPORTS_SMP
>> 1035 select HAVE_PCI
>> 1036 select SYS_SUPPORTS_32BIT_KERNEL
>> 1037 select SYS_SUPPORTS_64BIT_KERNEL
>> 1038 select PHYS_ADDR_T_64BIT
>> 1039 select GPIOLIB
>> 1040 select SYS_SUPPORTS_BIG_ENDIAN
>> 1041 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 1042 select SYS_SUPPORTS_HIGHMEM
>> 1043 select NR_CPUS_DEFAULT_32
>> 1044 select CEVT_R4K
>> 1045 select CSRC_R4K
>> 1046 select IRQ_MIPS_CPU
>> 1047 select ZONE_DMA32 if 64BIT
>> 1048 select SYNC_R4K
>> 1049 select SYS_HAS_EARLY_PRINTK
>> 1050 select USE_OF
>> 1051 select SYS_SUPPORTS_ZBOOT
>> 1052 select SYS_SUPPORTS_ZBOOT_UART16550
>> 1053 help
>> 1054 This board is based on Netlogic XLP Processor.
>> 1055 Say Y here if you have a XLP based board.
273 1056
274 config RUSTC_SUPPORTS_ARM64 !! 1057 endchoice
275 def_bool y <<
276 depends on CPU_LITTLE_ENDIAN <<
277 # Shadow call stack is only supported <<
278 # <<
279 # When using the UNWIND_PATCH_PAC_INTO <<
280 # required due to use of the -Zfixed-x <<
281 # <<
282 # Otherwise, rustc version 1.82+ is re <<
283 # -Zsanitizer=shadow-call-stack flag. <<
284 depends on !SHADOW_CALL_STACK || RUSTC <<
285 <<
286 config CLANG_SUPPORTS_DYNAMIC_FTRACE_WITH_ARGS <<
287 def_bool CC_IS_CLANG <<
288 # https://github.com/ClangBuiltLinux/l <<
289 depends on AS_IS_GNU || (AS_IS_LLVM && <<
290 <<
291 config GCC_SUPPORTS_DYNAMIC_FTRACE_WITH_ARGS <<
292 def_bool CC_IS_GCC <<
293 depends on $(cc-option,-fpatchable-fun <<
294 1058
295 config 64BIT !! 1059 source "arch/mips/alchemy/Kconfig"
296 def_bool y !! 1060 source "arch/mips/ath25/Kconfig"
>> 1061 source "arch/mips/ath79/Kconfig"
>> 1062 source "arch/mips/bcm47xx/Kconfig"
>> 1063 source "arch/mips/bcm63xx/Kconfig"
>> 1064 source "arch/mips/bmips/Kconfig"
>> 1065 source "arch/mips/generic/Kconfig"
>> 1066 source "arch/mips/ingenic/Kconfig"
>> 1067 source "arch/mips/jazz/Kconfig"
>> 1068 source "arch/mips/lantiq/Kconfig"
>> 1069 source "arch/mips/pic32/Kconfig"
>> 1070 source "arch/mips/ralink/Kconfig"
>> 1071 source "arch/mips/sgi-ip27/Kconfig"
>> 1072 source "arch/mips/sibyte/Kconfig"
>> 1073 source "arch/mips/txx9/Kconfig"
>> 1074 source "arch/mips/vr41xx/Kconfig"
>> 1075 source "arch/mips/cavium-octeon/Kconfig"
>> 1076 source "arch/mips/loongson2ef/Kconfig"
>> 1077 source "arch/mips/loongson32/Kconfig"
>> 1078 source "arch/mips/loongson64/Kconfig"
>> 1079 source "arch/mips/netlogic/Kconfig"
297 1080
298 config MMU !! 1081 endmenu
299 def_bool y <<
300 1082
301 config ARM64_CONT_PTE_SHIFT !! 1083 config GENERIC_HWEIGHT
302 int !! 1084 bool
303 default 5 if PAGE_SIZE_64KB !! 1085 default y
304 default 7 if PAGE_SIZE_16KB <<
305 default 4 <<
306 1086
307 config ARM64_CONT_PMD_SHIFT !! 1087 config GENERIC_CALIBRATE_DELAY
308 int !! 1088 bool
309 default 5 if PAGE_SIZE_64KB !! 1089 default y
310 default 5 if PAGE_SIZE_16KB <<
311 default 4 <<
312 1090
313 config ARCH_MMAP_RND_BITS_MIN !! 1091 config SCHED_OMIT_FRAME_POINTER
314 default 14 if PAGE_SIZE_64KB !! 1092 bool
315 default 16 if PAGE_SIZE_16KB !! 1093 default y
316 default 18 <<
317 1094
318 # max bits determined by the following formula !! 1095 #
319 # VA_BITS - PAGE_SHIFT - 3 !! 1096 # Select some configuration options automatically based on user selections.
320 config ARCH_MMAP_RND_BITS_MAX !! 1097 #
321 default 19 if ARM64_VA_BITS=36 !! 1098 config FW_ARC
322 default 24 if ARM64_VA_BITS=39 !! 1099 bool
323 default 27 if ARM64_VA_BITS=42 <<
324 default 30 if ARM64_VA_BITS=47 <<
325 default 29 if ARM64_VA_BITS=48 && ARM6 <<
326 default 31 if ARM64_VA_BITS=48 && ARM6 <<
327 default 33 if ARM64_VA_BITS=48 <<
328 default 14 if ARM64_64K_PAGES <<
329 default 16 if ARM64_16K_PAGES <<
330 default 18 <<
331 1100
332 config ARCH_MMAP_RND_COMPAT_BITS_MIN !! 1101 config ARCH_MAY_HAVE_PC_FDC
333 default 7 if ARM64_64K_PAGES !! 1102 bool
334 default 9 if ARM64_16K_PAGES <<
335 default 11 <<
336 1103
337 config ARCH_MMAP_RND_COMPAT_BITS_MAX !! 1104 config BOOT_RAW
338 default 16 !! 1105 bool
339 1106
340 config NO_IOPORT_MAP !! 1107 config CEVT_BCM1480
341 def_bool y if !PCI !! 1108 bool
342 1109
343 config STACKTRACE_SUPPORT !! 1110 config CEVT_DS1287
344 def_bool y !! 1111 bool
345 1112
346 config ILLEGAL_POINTER_VALUE !! 1113 config CEVT_GT641XX
347 hex !! 1114 bool
348 default 0xdead000000000000 <<
349 1115
350 config LOCKDEP_SUPPORT !! 1116 config CEVT_R4K
351 def_bool y !! 1117 bool
352 1118
353 config GENERIC_BUG !! 1119 config CEVT_SB1250
354 def_bool y !! 1120 bool
355 depends on BUG <<
356 1121
357 config GENERIC_BUG_RELATIVE_POINTERS !! 1122 config CEVT_TXX9
358 def_bool y !! 1123 bool
359 depends on GENERIC_BUG <<
360 1124
361 config GENERIC_HWEIGHT !! 1125 config CSRC_BCM1480
362 def_bool y !! 1126 bool
363 1127
364 config GENERIC_CSUM !! 1128 config CSRC_IOASIC
365 def_bool y !! 1129 bool
366 1130
367 config GENERIC_CALIBRATE_DELAY !! 1131 config CSRC_R4K
368 def_bool y !! 1132 select CLOCKSOURCE_WATCHDOG if CPU_FREQ
>> 1133 bool
369 1134
370 config SMP !! 1135 config CSRC_SB1250
371 def_bool y !! 1136 bool
372 1137
373 config KERNEL_MODE_NEON !! 1138 config MIPS_CLOCK_VSYSCALL
374 def_bool y !! 1139 def_bool CSRC_R4K || CLKSRC_MIPS_GIC
375 1140
376 config FIX_EARLYCON_MEM !! 1141 config GPIO_TXX9
377 def_bool y !! 1142 select GPIOLIB
>> 1143 bool
378 1144
379 config PGTABLE_LEVELS !! 1145 config FW_CFE
380 int !! 1146 bool
381 default 2 if ARM64_16K_PAGES && ARM64_ <<
382 default 2 if ARM64_64K_PAGES && ARM64_ <<
383 default 3 if ARM64_64K_PAGES && (ARM64 <<
384 default 3 if ARM64_4K_PAGES && ARM64_V <<
385 default 3 if ARM64_16K_PAGES && ARM64_ <<
386 default 4 if ARM64_16K_PAGES && (ARM64 <<
387 default 4 if !ARM64_64K_PAGES && ARM64 <<
388 default 5 if ARM64_4K_PAGES && ARM64_V <<
389 1147
390 config ARCH_SUPPORTS_UPROBES 1148 config ARCH_SUPPORTS_UPROBES
391 def_bool y !! 1149 bool
392 1150
393 config ARCH_PROC_KCORE_TEXT !! 1151 config DMA_PERDEV_COHERENT
394 def_bool y !! 1152 bool
>> 1153 select ARCH_HAS_SETUP_DMA_OPS
>> 1154 select DMA_NONCOHERENT
395 1155
396 config BROKEN_GAS_INST !! 1156 config DMA_NONCOHERENT
397 def_bool !$(as-instr,1:\n.inst 0\n.rep !! 1157 bool
>> 1158 #
>> 1159 # MIPS allows mixing "slightly different" Cacheability and Coherency
>> 1160 # Attribute bits. It is believed that the uncached access through
>> 1161 # KSEG1 and the implementation specific "uncached accelerated" used
>> 1162 # by pgprot_writcombine can be mixed, and the latter sometimes provides
>> 1163 # significant advantages.
>> 1164 #
>> 1165 select ARCH_HAS_DMA_WRITE_COMBINE
>> 1166 select ARCH_HAS_DMA_PREP_COHERENT
>> 1167 select ARCH_HAS_SYNC_DMA_FOR_DEVICE
>> 1168 select ARCH_HAS_DMA_SET_UNCACHED
>> 1169 select DMA_NONCOHERENT_MMAP
>> 1170 select NEED_DMA_MAP_STATE
398 1171
399 config BUILTIN_RETURN_ADDRESS_STRIPS_PAC !! 1172 config SYS_HAS_EARLY_PRINTK
400 bool 1173 bool
401 # Clang's __builtin_return_address() s <<
402 # https://github.com/llvm/llvm-project <<
403 default y if CC_IS_CLANG <<
404 # GCC's __builtin_return_address() str <<
405 # and this was backported to 10.2.0, 9 <<
406 # https://gcc.gnu.org/bugzilla/show_bu <<
407 default y if CC_IS_GCC && (GCC_VERSION <<
408 default y if CC_IS_GCC && (GCC_VERSION <<
409 default y if CC_IS_GCC && (GCC_VERSION <<
410 default y if CC_IS_GCC && (GCC_VERSION <<
411 default n <<
412 1174
413 config KASAN_SHADOW_OFFSET !! 1175 config SYS_SUPPORTS_HOTPLUG_CPU
414 hex <<
415 depends on KASAN_GENERIC || KASAN_SW_T <<
416 default 0xdfff800000000000 if (ARM64_V <<
417 default 0xdfffc00000000000 if (ARM64_V <<
418 default 0xdffffe0000000000 if ARM64_VA <<
419 default 0xdfffffc000000000 if ARM64_VA <<
420 default 0xdffffff800000000 if ARM64_VA <<
421 default 0xefff800000000000 if (ARM64_V <<
422 default 0xefffc00000000000 if (ARM64_V <<
423 default 0xeffffe0000000000 if ARM64_VA <<
424 default 0xefffffc000000000 if ARM64_VA <<
425 default 0xeffffff800000000 if ARM64_VA <<
426 default 0xffffffffffffffff <<
427 <<
428 config UNWIND_TABLES <<
429 bool 1176 bool
430 1177
431 source "arch/arm64/Kconfig.platforms" !! 1178 config MIPS_BONITO64
>> 1179 bool
432 1180
433 menu "Kernel Features" !! 1181 config MIPS_MSC
>> 1182 bool
434 1183
435 menu "ARM errata workarounds via the alternati !! 1184 config SYNC_R4K
>> 1185 bool
436 1186
437 config AMPERE_ERRATUM_AC03_CPU_38 !! 1187 config NO_IOPORT_MAP
438 bool "AmpereOne: AC03_CPU_38: Certain !! 1188 def_bool n
439 default y <<
440 help <<
441 This option adds an alternative code <<
442 errata AC03_CPU_38 and AC04_CPU_10 o <<
443 1189
444 The affected design reports FEAT_HAF !! 1190 config GENERIC_CSUM
445 ID_AA64MMFR1_EL1.HAFDBS, but (V)TCR_ !! 1191 def_bool CPU_NO_LOAD_STORE_LR
446 as required by the architecture. The <<
447 implementation suffers from an addit <<
448 A/D updates can occur after a PTE ha <<
449 <<
450 The workaround forces KVM to explici <<
451 which avoids enabling unadvertised h <<
452 at stage-2. <<
453 1192
454 If unsure, say Y. !! 1193 config GENERIC_ISA_DMA
>> 1194 bool
>> 1195 select ZONE_DMA if GENERIC_ISA_DMA_SUPPORT_BROKEN=n
>> 1196 select ISA_DMA_API
455 1197
456 config ARM64_WORKAROUND_CLEAN_CACHE !! 1198 config GENERIC_ISA_DMA_SUPPORT_BROKEN
457 bool 1199 bool
>> 1200 select GENERIC_ISA_DMA
458 1201
459 config ARM64_ERRATUM_826319 !! 1202 config HAVE_PLAT_DELAY
460 bool "Cortex-A53: 826319: System might !! 1203 bool
461 default y <<
462 select ARM64_WORKAROUND_CLEAN_CACHE <<
463 help <<
464 This option adds an alternative code <<
465 erratum 826319 on Cortex-A53 parts u <<
466 AXI master interface and an L2 cache <<
467 <<
468 If a Cortex-A53 uses an AMBA AXI4 AC <<
469 and is unable to accept a certain wr <<
470 not progress on read data presented <<
471 system can deadlock. <<
472 <<
473 The workaround promotes data cache c <<
474 data cache clean-and-invalidate. <<
475 Please note that this does not neces <<
476 as it depends on the alternative fra <<
477 the kernel if an affected CPU is det <<
478 1204
479 If unsure, say Y. !! 1205 config HAVE_PLAT_FW_INIT_CMDLINE
>> 1206 bool
480 1207
481 config ARM64_ERRATUM_827319 !! 1208 config HAVE_PLAT_MEMCPY
482 bool "Cortex-A53: 827319: Data cache c !! 1209 bool
483 default y <<
484 select ARM64_WORKAROUND_CLEAN_CACHE <<
485 help <<
486 This option adds an alternative code <<
487 erratum 827319 on Cortex-A53 parts u <<
488 master interface and an L2 cache. <<
489 <<
490 Under certain conditions this erratu <<
491 to occur at the same time as another <<
492 on the AMBA 5 CHI interface, which c <<
493 interconnect reorders the two transa <<
494 <<
495 The workaround promotes data cache c <<
496 data cache clean-and-invalidate. <<
497 Please note that this does not neces <<
498 as it depends on the alternative fra <<
499 the kernel if an affected CPU is det <<
500 1210
501 If unsure, say Y. !! 1211 config ISA_DMA_API
>> 1212 bool
502 1213
503 config ARM64_ERRATUM_824069 !! 1214 config SYS_SUPPORTS_RELOCATABLE
504 bool "Cortex-A53: 824069: Cache line m !! 1215 bool
505 default y <<
506 select ARM64_WORKAROUND_CLEAN_CACHE <<
507 help 1216 help
508 This option adds an alternative code !! 1217 Selected if the platform supports relocating the kernel.
509 erratum 824069 on Cortex-A53 parts u !! 1218 The platform must provide plat_get_fdt() if it selects CONFIG_USE_OF
510 to a coherent interconnect. !! 1219 to allow access to command line and entropy sources.
511 <<
512 If a Cortex-A53 processor is executi <<
513 write instruction at the same time a <<
514 cluster is executing a cache mainten <<
515 address, then this erratum might cau <<
516 incorrectly marked as dirty. <<
517 <<
518 The workaround promotes data cache c <<
519 data cache clean-and-invalidate. <<
520 Please note that this option does no <<
521 workaround, as it depends on the alt <<
522 only patch the kernel if an affected <<
523 1220
524 If unsure, say Y. !! 1221 config MIPS_CBPF_JIT
>> 1222 def_bool y
>> 1223 depends on BPF_JIT && HAVE_CBPF_JIT
525 1224
526 config ARM64_ERRATUM_819472 !! 1225 config MIPS_EBPF_JIT
527 bool "Cortex-A53: 819472: Store exclus !! 1226 def_bool y
528 default y !! 1227 depends on BPF_JIT && HAVE_EBPF_JIT
529 select ARM64_WORKAROUND_CLEAN_CACHE <<
530 help <<
531 This option adds an alternative code <<
532 erratum 819472 on Cortex-A53 parts u <<
533 present when it is connected to a co <<
534 <<
535 If the processor is executing a load <<
536 the same time as a processor in anot <<
537 maintenance operation to the same ad <<
538 cause data corruption. <<
539 <<
540 The workaround promotes data cache c <<
541 data cache clean-and-invalidate. <<
542 Please note that this does not neces <<
543 as it depends on the alternative fra <<
544 the kernel if an affected CPU is det <<
545 1228
546 If unsure, say Y. <<
547 1229
548 config ARM64_ERRATUM_832075 !! 1230 #
549 bool "Cortex-A57: 832075: possible dea !! 1231 # Endianness selection. Sufficiently obscure so many users don't know what to
550 default y !! 1232 # answer,so we try hard to limit the available choices. Also the use of a
>> 1233 # choice statement should be more obvious to the user.
>> 1234 #
>> 1235 choice
>> 1236 prompt "Endianness selection"
551 help 1237 help
552 This option adds an alternative code !! 1238 Some MIPS machines can be configured for either little or big endian
553 erratum 832075 on Cortex-A57 parts u !! 1239 byte order. These modes require different kernels and a different
>> 1240 Linux distribution. In general there is one preferred byteorder for a
>> 1241 particular system but some systems are just as commonly used in the
>> 1242 one or the other endianness.
554 1243
555 Affected Cortex-A57 parts might dead !! 1244 config CPU_BIG_ENDIAN
556 instructions to Write-Back memory ar !! 1245 bool "Big endian"
>> 1246 depends on SYS_SUPPORTS_BIG_ENDIAN
557 1247
558 The workaround is to promote device !! 1248 config CPU_LITTLE_ENDIAN
559 semantics. !! 1249 bool "Little endian"
560 Please note that this does not neces !! 1250 depends on SYS_SUPPORTS_LITTLE_ENDIAN
561 as it depends on the alternative fra <<
562 the kernel if an affected CPU is det <<
563 1251
564 If unsure, say Y. !! 1252 endchoice
565 1253
566 config ARM64_ERRATUM_834220 !! 1254 config EXPORT_UASM
567 bool "Cortex-A57: 834220: Stage 2 tran !! 1255 bool
568 depends on KVM <<
569 help <<
570 This option adds an alternative code <<
571 erratum 834220 on Cortex-A57 parts u <<
572 <<
573 Affected Cortex-A57 parts might repo <<
574 fault as the result of a Stage 1 fau <<
575 page boundary when there is a permis <<
576 alignment fault at Stage 1 and a tra <<
577 <<
578 The workaround is to verify that the <<
579 doesn't generate a fault before hand <<
580 Please note that this does not neces <<
581 as it depends on the alternative fra <<
582 the kernel if an affected CPU is det <<
583 1256
584 If unsure, say N. !! 1257 config SYS_SUPPORTS_APM_EMULATION
>> 1258 bool
585 1259
586 config ARM64_ERRATUM_1742098 !! 1260 config SYS_SUPPORTS_BIG_ENDIAN
587 bool "Cortex-A57/A72: 1742098: ELR rec !! 1261 bool
588 depends on COMPAT <<
589 default y <<
590 help <<
591 This option removes the AES hwcap fo <<
592 workaround erratum 1742098 on Cortex <<
593 1262
594 Affected parts may corrupt the AES s !! 1263 config SYS_SUPPORTS_LITTLE_ENDIAN
595 taken between a pair of AES instruct !! 1264 bool
596 are only present if the cryptography <<
597 All software should have a fallback <<
598 that don't implement the cryptograph <<
599 1265
600 If unsure, say Y. !! 1266 config MIPS_HUGE_TLB_SUPPORT
>> 1267 def_bool HUGETLB_PAGE || TRANSPARENT_HUGEPAGE
601 1268
602 config ARM64_ERRATUM_845719 !! 1269 config IRQ_MSP_SLP
603 bool "Cortex-A53: 845719: a load might !! 1270 bool
604 depends on COMPAT <<
605 default y <<
606 help <<
607 This option adds an alternative code <<
608 erratum 845719 on Cortex-A53 parts u <<
609 1271
610 When running a compat (AArch32) user !! 1272 config IRQ_MSP_CIC
611 part, a load at EL0 from a virtual a !! 1273 bool
612 bits of the virtual address used by <<
613 might return incorrect data. <<
614 <<
615 The workaround is to write the conte <<
616 return to a 32-bit task. <<
617 Please note that this does not neces <<
618 as it depends on the alternative fra <<
619 the kernel if an affected CPU is det <<
620 1274
621 If unsure, say Y. !! 1275 config IRQ_TXX9
>> 1276 bool
622 1277
623 config ARM64_ERRATUM_843419 !! 1278 config IRQ_GT641XX
624 bool "Cortex-A53: 843419: A load or st !! 1279 bool
625 default y <<
626 help <<
627 This option links the kernel with '- <<
628 enables PLT support to replace certa <<
629 cause subsequent memory accesses to <<
630 Cortex-A53 parts up to r0p4. <<
631 1280
632 If unsure, say Y. !! 1281 config PCI_GT64XXX_PCI0
>> 1282 bool
633 1283
634 config ARM64_LD_HAS_FIX_ERRATUM_843419 !! 1284 config PCI_XTALK_BRIDGE
635 def_bool $(ld-option,--fix-cortex-a53- !! 1285 bool
636 1286
637 config ARM64_ERRATUM_1024718 !! 1287 config NO_EXCEPT_FILL
638 bool "Cortex-A55: 1024718: Update of D !! 1288 bool
639 default y <<
640 help <<
641 This option adds a workaround for AR <<
642 1289
643 Affected Cortex-A55 cores (all revis !! 1290 config MIPS_SPRAM
644 update of the hardware dirty bit whe !! 1291 bool
645 without a break-before-make. The wor <<
646 of hardware DBM locally on the affec <<
647 this erratum will continue to use th <<
648 1292
649 If unsure, say Y. !! 1293 config SWAP_IO_SPACE
>> 1294 bool
650 1295
651 config ARM64_ERRATUM_1418040 !! 1296 config SGI_HAS_INDYDOG
652 bool "Cortex-A76/Neoverse-N1: MRC read !! 1297 bool
653 default y <<
654 depends on COMPAT <<
655 help <<
656 This option adds a workaround for AR <<
657 errata 1188873 and 1418040. <<
658 1298
659 Affected Cortex-A76/Neoverse-N1 core !! 1299 config SGI_HAS_HAL2
660 cause register corruption when acces !! 1300 bool
661 from AArch32 userspace. <<
662 1301
663 If unsure, say Y. !! 1302 config SGI_HAS_SEEQ
>> 1303 bool
664 1304
665 config ARM64_WORKAROUND_SPECULATIVE_AT !! 1305 config SGI_HAS_WD93
666 bool 1306 bool
667 1307
668 config ARM64_ERRATUM_1165522 !! 1308 config SGI_HAS_ZILOG
669 bool "Cortex-A76: 1165522: Speculative !! 1309 bool
670 default y <<
671 select ARM64_WORKAROUND_SPECULATIVE_AT <<
672 help <<
673 This option adds a workaround for AR <<
674 1310
675 Affected Cortex-A76 cores (r0p0, r1p !! 1311 config SGI_HAS_I8042
676 corrupted TLBs by speculating an AT !! 1312 bool
677 context switch. <<
678 1313
679 If unsure, say Y. !! 1314 config DEFAULT_SGI_PARTITION
>> 1315 bool
680 1316
681 config ARM64_ERRATUM_1319367 !! 1317 config FW_ARC32
682 bool "Cortex-A57/A72: 1319537: Specula !! 1318 bool
683 default y <<
684 select ARM64_WORKAROUND_SPECULATIVE_AT <<
685 help <<
686 This option adds work arounds for AR <<
687 and A72 erratum 1319367 <<
688 1319
689 Cortex-A57 and A72 cores could end-u !! 1320 config FW_SNIPROM
690 speculating an AT instruction during !! 1321 bool
691 1322
692 If unsure, say Y. !! 1323 config BOOT_ELF32
>> 1324 bool
693 1325
694 config ARM64_ERRATUM_1530923 !! 1326 config MIPS_L1_CACHE_SHIFT_4
695 bool "Cortex-A55: 1530923: Speculative !! 1327 bool
696 default y <<
697 select ARM64_WORKAROUND_SPECULATIVE_AT <<
698 help <<
699 This option adds a workaround for AR <<
700 1328
701 Affected Cortex-A55 cores (r0p0, r0p !! 1329 config MIPS_L1_CACHE_SHIFT_5
702 corrupted TLBs by speculating an AT !! 1330 bool
703 context switch. <<
704 1331
705 If unsure, say Y. !! 1332 config MIPS_L1_CACHE_SHIFT_6
>> 1333 bool
706 1334
707 config ARM64_WORKAROUND_REPEAT_TLBI !! 1335 config MIPS_L1_CACHE_SHIFT_7
708 bool 1336 bool
709 1337
710 config ARM64_ERRATUM_2441007 !! 1338 config MIPS_L1_CACHE_SHIFT
711 bool "Cortex-A55: Completion of affect !! 1339 int
712 select ARM64_WORKAROUND_REPEAT_TLBI !! 1340 default "7" if MIPS_L1_CACHE_SHIFT_7
713 help !! 1341 default "6" if MIPS_L1_CACHE_SHIFT_6
714 This option adds a workaround for AR !! 1342 default "5" if MIPS_L1_CACHE_SHIFT_5
>> 1343 default "4" if MIPS_L1_CACHE_SHIFT_4
>> 1344 default "5"
715 1345
716 Under very rare circumstances, affec !! 1346 config ARC_CMDLINE_ONLY
717 may not handle a race between a brea !! 1347 bool
718 CPU, and another CPU accessing the s <<
719 store to a page that has been unmapp <<
720 1348
721 Work around this by adding the affec !! 1349 config ARC_CONSOLE
722 TLB sequences to be done twice. !! 1350 bool "ARC console support"
>> 1351 depends on SGI_IP22 || SGI_IP28 || (SNI_RM && CPU_LITTLE_ENDIAN)
723 1352
724 If unsure, say N. !! 1353 config ARC_MEMORY
>> 1354 bool
725 1355
726 config ARM64_ERRATUM_1286807 !! 1356 config ARC_PROMLIB
727 bool "Cortex-A76: Modification of the !! 1357 bool
728 select ARM64_WORKAROUND_REPEAT_TLBI <<
729 help <<
730 This option adds a workaround for AR <<
731 <<
732 On the affected Cortex-A76 cores (r0 <<
733 address for a cacheable mapping of a <<
734 accessed by a core while another cor <<
735 address to a new physical page using <<
736 break-before-make sequence, then und <<
737 TLBI+DSB completes before a read usi <<
738 invalidated has been observed by oth <<
739 workaround repeats the TLBI+DSB oper <<
740 1358
741 If unsure, say N. !! 1359 config FW_ARC64
>> 1360 bool
742 1361
743 config ARM64_ERRATUM_1463225 !! 1362 config BOOT_ELF64
744 bool "Cortex-A76: Software Step might !! 1363 bool
745 default y <<
746 help <<
747 This option adds a workaround for Ar <<
748 1364
749 On the affected Cortex-A76 cores (r0 !! 1365 menu "CPU selection"
750 of a system call instruction (SVC) c <<
751 subsequent interrupts when software <<
752 exception handler of the system call <<
753 is enabled or VHE is in use. <<
754 <<
755 Work around the erratum by triggerin <<
756 when handling a system call from a t <<
757 in a VHE configuration of the kernel <<
758 1366
759 If unsure, say Y. !! 1367 choice
>> 1368 prompt "CPU type"
>> 1369 default CPU_R4X00
760 1370
761 config ARM64_ERRATUM_1542419 !! 1371 config CPU_LOONGSON64
762 bool "Neoverse-N1: workaround mis-orde !! 1372 bool "Loongson 64-bit CPU"
>> 1373 depends on SYS_HAS_CPU_LOONGSON64
>> 1374 select ARCH_HAS_PHYS_TO_DMA
>> 1375 select CPU_MIPSR2
>> 1376 select CPU_HAS_PREFETCH
>> 1377 select CPU_SUPPORTS_64BIT_KERNEL
>> 1378 select CPU_SUPPORTS_HIGHMEM
>> 1379 select CPU_SUPPORTS_HUGEPAGES
>> 1380 select CPU_SUPPORTS_MSA
>> 1381 select CPU_DIEI_BROKEN if !LOONGSON3_ENHANCEMENT
>> 1382 select CPU_MIPSR2_IRQ_VI
>> 1383 select DMA_NONCOHERENT
>> 1384 select WEAK_ORDERING
>> 1385 select WEAK_REORDERING_BEYOND_LLSC
>> 1386 select MIPS_ASID_BITS_VARIABLE
>> 1387 select MIPS_PGD_C0_CONTEXT
>> 1388 select MIPS_L1_CACHE_SHIFT_6
>> 1389 select MIPS_FP_SUPPORT
>> 1390 select GPIOLIB
>> 1391 select SWIOTLB
>> 1392 select HAVE_KVM
763 help 1393 help
764 This option adds a workaround for AR !! 1394 The Loongson GSx64(GS264/GS464/GS464E/GS464V) series of processor
765 1542419. !! 1395 cores implements the MIPS64R2 instruction set with many extensions,
>> 1396 including most 64-bit Loongson-2 (2H, 2K) and Loongson-3 (3A1000,
>> 1397 3B1000, 3B1500, 3A2000, 3A3000 and 3A4000) processors. However, old
>> 1398 Loongson-2E/2F is not covered here and will be removed in future.
766 1399
767 Affected Neoverse-N1 cores could exe !! 1400 config LOONGSON3_ENHANCEMENT
768 modified by another CPU. The workaro !! 1401 bool "New Loongson-3 CPU Enhancements"
769 counterpart. !! 1402 default n
770 !! 1403 depends on CPU_LOONGSON64
771 Workaround the issue by hiding the D <<
772 forces user-space to perform cache m <<
773 <<
774 If unsure, say N. <<
775 <<
776 config ARM64_ERRATUM_1508412 <<
777 bool "Cortex-A77: 1508412: workaround <<
778 default y <<
779 help 1404 help
780 This option adds a workaround for Ar !! 1405 New Loongson-3 cores (since Loongson-3A R2, as opposed to Loongson-3A
>> 1406 R1, Loongson-3B R1 and Loongson-3B R2) has many enhancements, such as
>> 1407 FTLB, L1-VCache, EI/DI/Wait/Prefetch instruction, DSP/DSPr2 ASE, User
>> 1408 Local register, Read-Inhibit/Execute-Inhibit, SFB (Store Fill Buffer),
>> 1409 Fast TLB refill support, etc.
>> 1410
>> 1411 This option enable those enhancements which are not probed at run
>> 1412 time. If you want a generic kernel to run on all Loongson 3 machines,
>> 1413 please say 'N' here. If you want a high-performance kernel to run on
>> 1414 new Loongson-3 machines only, please say 'Y' here.
>> 1415
>> 1416 config CPU_LOONGSON3_WORKAROUNDS
>> 1417 bool "Old Loongson-3 LLSC Workarounds"
>> 1418 default y if SMP
>> 1419 depends on CPU_LOONGSON64
>> 1420 help
>> 1421 Loongson-3 processors have the llsc issues which require workarounds.
>> 1422 Without workarounds the system may hang unexpectedly.
>> 1423
>> 1424 Newer Loongson-3 will fix these issues and no workarounds are needed.
>> 1425 The workarounds have no significant side effect on them but may
>> 1426 decrease the performance of the system so this option should be
>> 1427 disabled unless the kernel is intended to be run on old systems.
>> 1428
>> 1429 If unsure, please say Y.
>> 1430
>> 1431 config CPU_LOONGSON3_CPUCFG_EMULATION
>> 1432 bool "Emulate the CPUCFG instruction on older Loongson cores"
>> 1433 default y
>> 1434 depends on CPU_LOONGSON64
>> 1435 help
>> 1436 Loongson-3A R4 and newer have the CPUCFG instruction available for
>> 1437 userland to query CPU capabilities, much like CPUID on x86. This
>> 1438 option provides emulation of the instruction on older Loongson
>> 1439 cores, back to Loongson-3A1000.
>> 1440
>> 1441 If unsure, please say Y.
>> 1442
>> 1443 config CPU_LOONGSON2E
>> 1444 bool "Loongson 2E"
>> 1445 depends on SYS_HAS_CPU_LOONGSON2E
>> 1446 select CPU_LOONGSON2EF
>> 1447 help
>> 1448 The Loongson 2E processor implements the MIPS III instruction set
>> 1449 with many extensions.
>> 1450
>> 1451 It has an internal FPGA northbridge, which is compatible to
>> 1452 bonito64.
>> 1453
>> 1454 config CPU_LOONGSON2F
>> 1455 bool "Loongson 2F"
>> 1456 depends on SYS_HAS_CPU_LOONGSON2F
>> 1457 select CPU_LOONGSON2EF
>> 1458 select GPIOLIB
>> 1459 help
>> 1460 The Loongson 2F processor implements the MIPS III instruction set
>> 1461 with many extensions.
>> 1462
>> 1463 Loongson2F have built-in DDR2 and PCIX controller. The PCIX controller
>> 1464 have a similar programming interface with FPGA northbridge used in
>> 1465 Loongson2E.
>> 1466
>> 1467 config CPU_LOONGSON1B
>> 1468 bool "Loongson 1B"
>> 1469 depends on SYS_HAS_CPU_LOONGSON1B
>> 1470 select CPU_LOONGSON32
>> 1471 select LEDS_GPIO_REGISTER
>> 1472 help
>> 1473 The Loongson 1B is a 32-bit SoC, which implements the MIPS32
>> 1474 Release 1 instruction set and part of the MIPS32 Release 2
>> 1475 instruction set.
>> 1476
>> 1477 config CPU_LOONGSON1C
>> 1478 bool "Loongson 1C"
>> 1479 depends on SYS_HAS_CPU_LOONGSON1C
>> 1480 select CPU_LOONGSON32
>> 1481 select LEDS_GPIO_REGISTER
>> 1482 help
>> 1483 The Loongson 1C is a 32-bit SoC, which implements the MIPS32
>> 1484 Release 1 instruction set and part of the MIPS32 Release 2
>> 1485 instruction set.
>> 1486
>> 1487 config CPU_MIPS32_R1
>> 1488 bool "MIPS32 Release 1"
>> 1489 depends on SYS_HAS_CPU_MIPS32_R1
>> 1490 select CPU_HAS_PREFETCH
>> 1491 select CPU_SUPPORTS_32BIT_KERNEL
>> 1492 select CPU_SUPPORTS_HIGHMEM
>> 1493 help
>> 1494 Choose this option to build a kernel for release 1 or later of the
>> 1495 MIPS32 architecture. Most modern embedded systems with a 32-bit
>> 1496 MIPS processor are based on a MIPS32 processor. If you know the
>> 1497 specific type of processor in your system, choose those that one
>> 1498 otherwise CPU_MIPS32_R1 is a safe bet for any MIPS32 system.
>> 1499 Release 2 of the MIPS32 architecture is available since several
>> 1500 years so chances are you even have a MIPS32 Release 2 processor
>> 1501 in which case you should choose CPU_MIPS32_R2 instead for better
>> 1502 performance.
>> 1503
>> 1504 config CPU_MIPS32_R2
>> 1505 bool "MIPS32 Release 2"
>> 1506 depends on SYS_HAS_CPU_MIPS32_R2
>> 1507 select CPU_HAS_PREFETCH
>> 1508 select CPU_SUPPORTS_32BIT_KERNEL
>> 1509 select CPU_SUPPORTS_HIGHMEM
>> 1510 select CPU_SUPPORTS_MSA
>> 1511 select HAVE_KVM
>> 1512 help
>> 1513 Choose this option to build a kernel for release 2 or later of the
>> 1514 MIPS32 architecture. Most modern embedded systems with a 32-bit
>> 1515 MIPS processor are based on a MIPS32 processor. If you know the
>> 1516 specific type of processor in your system, choose those that one
>> 1517 otherwise CPU_MIPS32_R1 is a safe bet for any MIPS32 system.
>> 1518
>> 1519 config CPU_MIPS32_R5
>> 1520 bool "MIPS32 Release 5"
>> 1521 depends on SYS_HAS_CPU_MIPS32_R5
>> 1522 select CPU_HAS_PREFETCH
>> 1523 select CPU_SUPPORTS_32BIT_KERNEL
>> 1524 select CPU_SUPPORTS_HIGHMEM
>> 1525 select CPU_SUPPORTS_MSA
>> 1526 select HAVE_KVM
>> 1527 select MIPS_O32_FP64_SUPPORT
>> 1528 help
>> 1529 Choose this option to build a kernel for release 5 or later of the
>> 1530 MIPS32 architecture. New MIPS processors, starting with the Warrior
>> 1531 family, are based on a MIPS32r5 processor. If you own an older
>> 1532 processor, you probably need to select MIPS32r1 or MIPS32r2 instead.
>> 1533
>> 1534 config CPU_MIPS32_R6
>> 1535 bool "MIPS32 Release 6"
>> 1536 depends on SYS_HAS_CPU_MIPS32_R6
>> 1537 select CPU_HAS_PREFETCH
>> 1538 select CPU_NO_LOAD_STORE_LR
>> 1539 select CPU_SUPPORTS_32BIT_KERNEL
>> 1540 select CPU_SUPPORTS_HIGHMEM
>> 1541 select CPU_SUPPORTS_MSA
>> 1542 select HAVE_KVM
>> 1543 select MIPS_O32_FP64_SUPPORT
>> 1544 help
>> 1545 Choose this option to build a kernel for release 6 or later of the
>> 1546 MIPS32 architecture. New MIPS processors, starting with the Warrior
>> 1547 family, are based on a MIPS32r6 processor. If you own an older
>> 1548 processor, you probably need to select MIPS32r1 or MIPS32r2 instead.
>> 1549
>> 1550 config CPU_MIPS64_R1
>> 1551 bool "MIPS64 Release 1"
>> 1552 depends on SYS_HAS_CPU_MIPS64_R1
>> 1553 select CPU_HAS_PREFETCH
>> 1554 select CPU_SUPPORTS_32BIT_KERNEL
>> 1555 select CPU_SUPPORTS_64BIT_KERNEL
>> 1556 select CPU_SUPPORTS_HIGHMEM
>> 1557 select CPU_SUPPORTS_HUGEPAGES
>> 1558 help
>> 1559 Choose this option to build a kernel for release 1 or later of the
>> 1560 MIPS64 architecture. Many modern embedded systems with a 64-bit
>> 1561 MIPS processor are based on a MIPS64 processor. If you know the
>> 1562 specific type of processor in your system, choose those that one
>> 1563 otherwise CPU_MIPS64_R1 is a safe bet for any MIPS64 system.
>> 1564 Release 2 of the MIPS64 architecture is available since several
>> 1565 years so chances are you even have a MIPS64 Release 2 processor
>> 1566 in which case you should choose CPU_MIPS64_R2 instead for better
>> 1567 performance.
>> 1568
>> 1569 config CPU_MIPS64_R2
>> 1570 bool "MIPS64 Release 2"
>> 1571 depends on SYS_HAS_CPU_MIPS64_R2
>> 1572 select CPU_HAS_PREFETCH
>> 1573 select CPU_SUPPORTS_32BIT_KERNEL
>> 1574 select CPU_SUPPORTS_64BIT_KERNEL
>> 1575 select CPU_SUPPORTS_HIGHMEM
>> 1576 select CPU_SUPPORTS_HUGEPAGES
>> 1577 select CPU_SUPPORTS_MSA
>> 1578 select HAVE_KVM
>> 1579 help
>> 1580 Choose this option to build a kernel for release 2 or later of the
>> 1581 MIPS64 architecture. Many modern embedded systems with a 64-bit
>> 1582 MIPS processor are based on a MIPS64 processor. If you know the
>> 1583 specific type of processor in your system, choose those that one
>> 1584 otherwise CPU_MIPS64_R1 is a safe bet for any MIPS64 system.
>> 1585
>> 1586 config CPU_MIPS64_R5
>> 1587 bool "MIPS64 Release 5"
>> 1588 depends on SYS_HAS_CPU_MIPS64_R5
>> 1589 select CPU_HAS_PREFETCH
>> 1590 select CPU_SUPPORTS_32BIT_KERNEL
>> 1591 select CPU_SUPPORTS_64BIT_KERNEL
>> 1592 select CPU_SUPPORTS_HIGHMEM
>> 1593 select CPU_SUPPORTS_HUGEPAGES
>> 1594 select CPU_SUPPORTS_MSA
>> 1595 select MIPS_O32_FP64_SUPPORT if 32BIT || MIPS32_O32
>> 1596 select HAVE_KVM
>> 1597 help
>> 1598 Choose this option to build a kernel for release 5 or later of the
>> 1599 MIPS64 architecture. This is a intermediate MIPS architecture
>> 1600 release partly implementing release 6 features. Though there is no
>> 1601 any hardware known to be based on this release.
>> 1602
>> 1603 config CPU_MIPS64_R6
>> 1604 bool "MIPS64 Release 6"
>> 1605 depends on SYS_HAS_CPU_MIPS64_R6
>> 1606 select CPU_HAS_PREFETCH
>> 1607 select CPU_NO_LOAD_STORE_LR
>> 1608 select CPU_SUPPORTS_32BIT_KERNEL
>> 1609 select CPU_SUPPORTS_64BIT_KERNEL
>> 1610 select CPU_SUPPORTS_HIGHMEM
>> 1611 select CPU_SUPPORTS_HUGEPAGES
>> 1612 select CPU_SUPPORTS_MSA
>> 1613 select MIPS_O32_FP64_SUPPORT if 32BIT || MIPS32_O32
>> 1614 select HAVE_KVM
>> 1615 help
>> 1616 Choose this option to build a kernel for release 6 or later of the
>> 1617 MIPS64 architecture. New MIPS processors, starting with the Warrior
>> 1618 family, are based on a MIPS64r6 processor. If you own an older
>> 1619 processor, you probably need to select MIPS64r1 or MIPS64r2 instead.
>> 1620
>> 1621 config CPU_P5600
>> 1622 bool "MIPS Warrior P5600"
>> 1623 depends on SYS_HAS_CPU_P5600
>> 1624 select CPU_HAS_PREFETCH
>> 1625 select CPU_SUPPORTS_32BIT_KERNEL
>> 1626 select CPU_SUPPORTS_HIGHMEM
>> 1627 select CPU_SUPPORTS_MSA
>> 1628 select CPU_SUPPORTS_CPUFREQ
>> 1629 select CPU_MIPSR2_IRQ_VI
>> 1630 select CPU_MIPSR2_IRQ_EI
>> 1631 select HAVE_KVM
>> 1632 select MIPS_O32_FP64_SUPPORT
>> 1633 help
>> 1634 Choose this option to build a kernel for MIPS Warrior P5600 CPU.
>> 1635 It's based on MIPS32r5 ISA with XPA, EVA, dual/quad issue exec pipes,
>> 1636 MMU with two-levels TLB, UCA, MSA, MDU core level features and system
>> 1637 level features like up to six P5600 calculation cores, CM2 with L2
>> 1638 cache, IOCU/IOMMU (though might be unused depending on the system-
>> 1639 specific IP core configuration), GIC, CPC, virtualisation module,
>> 1640 eJTAG and PDtrace.
>> 1641
>> 1642 config CPU_R3000
>> 1643 bool "R3000"
>> 1644 depends on SYS_HAS_CPU_R3000
>> 1645 select CPU_HAS_WB
>> 1646 select CPU_R3K_TLB
>> 1647 select CPU_SUPPORTS_32BIT_KERNEL
>> 1648 select CPU_SUPPORTS_HIGHMEM
>> 1649 help
>> 1650 Please make sure to pick the right CPU type. Linux/MIPS is not
>> 1651 designed to be generic, i.e. Kernels compiled for R3000 CPUs will
>> 1652 *not* work on R4000 machines and vice versa. However, since most
>> 1653 of the supported machines have an R4000 (or similar) CPU, R4x00
>> 1654 might be a safe bet. If the resulting kernel does not work,
>> 1655 try to recompile with R3000.
>> 1656
>> 1657 config CPU_TX39XX
>> 1658 bool "R39XX"
>> 1659 depends on SYS_HAS_CPU_TX39XX
>> 1660 select CPU_SUPPORTS_32BIT_KERNEL
>> 1661 select CPU_R3K_TLB
>> 1662
>> 1663 config CPU_VR41XX
>> 1664 bool "R41xx"
>> 1665 depends on SYS_HAS_CPU_VR41XX
>> 1666 select CPU_SUPPORTS_32BIT_KERNEL
>> 1667 select CPU_SUPPORTS_64BIT_KERNEL
>> 1668 help
>> 1669 The options selects support for the NEC VR4100 series of processors.
>> 1670 Only choose this option if you have one of these processors as a
>> 1671 kernel built with this option will not run on any other type of
>> 1672 processor or vice versa.
>> 1673
>> 1674 config CPU_R4300
>> 1675 bool "R4300"
>> 1676 depends on SYS_HAS_CPU_R4300
>> 1677 select CPU_SUPPORTS_32BIT_KERNEL
>> 1678 select CPU_SUPPORTS_64BIT_KERNEL
>> 1679 select CPU_HAS_LOAD_STORE_LR
>> 1680 help
>> 1681 MIPS Technologies R4300-series processors.
>> 1682
>> 1683 config CPU_R4X00
>> 1684 bool "R4x00"
>> 1685 depends on SYS_HAS_CPU_R4X00
>> 1686 select CPU_SUPPORTS_32BIT_KERNEL
>> 1687 select CPU_SUPPORTS_64BIT_KERNEL
>> 1688 select CPU_SUPPORTS_HUGEPAGES
>> 1689 help
>> 1690 MIPS Technologies R4000-series processors other than 4300, including
>> 1691 the R4000, R4400, R4600, and 4700.
>> 1692
>> 1693 config CPU_TX49XX
>> 1694 bool "R49XX"
>> 1695 depends on SYS_HAS_CPU_TX49XX
>> 1696 select CPU_HAS_PREFETCH
>> 1697 select CPU_SUPPORTS_32BIT_KERNEL
>> 1698 select CPU_SUPPORTS_64BIT_KERNEL
>> 1699 select CPU_SUPPORTS_HUGEPAGES
>> 1700
>> 1701 config CPU_R5000
>> 1702 bool "R5000"
>> 1703 depends on SYS_HAS_CPU_R5000
>> 1704 select CPU_SUPPORTS_32BIT_KERNEL
>> 1705 select CPU_SUPPORTS_64BIT_KERNEL
>> 1706 select CPU_SUPPORTS_HUGEPAGES
>> 1707 help
>> 1708 MIPS Technologies R5000-series processors other than the Nevada.
>> 1709
>> 1710 config CPU_R5500
>> 1711 bool "R5500"
>> 1712 depends on SYS_HAS_CPU_R5500
>> 1713 select CPU_SUPPORTS_32BIT_KERNEL
>> 1714 select CPU_SUPPORTS_64BIT_KERNEL
>> 1715 select CPU_SUPPORTS_HUGEPAGES
>> 1716 help
>> 1717 NEC VR5500 and VR5500A series processors implement 64-bit MIPS IV
>> 1718 instruction set.
>> 1719
>> 1720 config CPU_NEVADA
>> 1721 bool "RM52xx"
>> 1722 depends on SYS_HAS_CPU_NEVADA
>> 1723 select CPU_SUPPORTS_32BIT_KERNEL
>> 1724 select CPU_SUPPORTS_64BIT_KERNEL
>> 1725 select CPU_SUPPORTS_HUGEPAGES
>> 1726 help
>> 1727 QED / PMC-Sierra RM52xx-series ("Nevada") processors.
>> 1728
>> 1729 config CPU_R10000
>> 1730 bool "R10000"
>> 1731 depends on SYS_HAS_CPU_R10000
>> 1732 select CPU_HAS_PREFETCH
>> 1733 select CPU_SUPPORTS_32BIT_KERNEL
>> 1734 select CPU_SUPPORTS_64BIT_KERNEL
>> 1735 select CPU_SUPPORTS_HIGHMEM
>> 1736 select CPU_SUPPORTS_HUGEPAGES
>> 1737 help
>> 1738 MIPS Technologies R10000-series processors.
>> 1739
>> 1740 config CPU_RM7000
>> 1741 bool "RM7000"
>> 1742 depends on SYS_HAS_CPU_RM7000
>> 1743 select CPU_HAS_PREFETCH
>> 1744 select CPU_SUPPORTS_32BIT_KERNEL
>> 1745 select CPU_SUPPORTS_64BIT_KERNEL
>> 1746 select CPU_SUPPORTS_HIGHMEM
>> 1747 select CPU_SUPPORTS_HUGEPAGES
>> 1748
>> 1749 config CPU_SB1
>> 1750 bool "SB1"
>> 1751 depends on SYS_HAS_CPU_SB1
>> 1752 select CPU_SUPPORTS_32BIT_KERNEL
>> 1753 select CPU_SUPPORTS_64BIT_KERNEL
>> 1754 select CPU_SUPPORTS_HIGHMEM
>> 1755 select CPU_SUPPORTS_HUGEPAGES
>> 1756 select WEAK_ORDERING
>> 1757
>> 1758 config CPU_CAVIUM_OCTEON
>> 1759 bool "Cavium Octeon processor"
>> 1760 depends on SYS_HAS_CPU_CAVIUM_OCTEON
>> 1761 select CPU_HAS_PREFETCH
>> 1762 select CPU_SUPPORTS_64BIT_KERNEL
>> 1763 select WEAK_ORDERING
>> 1764 select CPU_SUPPORTS_HIGHMEM
>> 1765 select CPU_SUPPORTS_HUGEPAGES
>> 1766 select USB_EHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 1767 select USB_OHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 1768 select MIPS_L1_CACHE_SHIFT_7
>> 1769 select HAVE_KVM
>> 1770 help
>> 1771 The Cavium Octeon processor is a highly integrated chip containing
>> 1772 many ethernet hardware widgets for networking tasks. The processor
>> 1773 can have up to 16 Mips64v2 cores and 8 integrated gigabit ethernets.
>> 1774 Full details can be found at http://www.caviumnetworks.com.
>> 1775
>> 1776 config CPU_BMIPS
>> 1777 bool "Broadcom BMIPS"
>> 1778 depends on SYS_HAS_CPU_BMIPS
>> 1779 select CPU_MIPS32
>> 1780 select CPU_BMIPS32_3300 if SYS_HAS_CPU_BMIPS32_3300
>> 1781 select CPU_BMIPS4350 if SYS_HAS_CPU_BMIPS4350
>> 1782 select CPU_BMIPS4380 if SYS_HAS_CPU_BMIPS4380
>> 1783 select CPU_BMIPS5000 if SYS_HAS_CPU_BMIPS5000
>> 1784 select CPU_SUPPORTS_32BIT_KERNEL
>> 1785 select DMA_NONCOHERENT
>> 1786 select IRQ_MIPS_CPU
>> 1787 select SWAP_IO_SPACE
>> 1788 select WEAK_ORDERING
>> 1789 select CPU_SUPPORTS_HIGHMEM
>> 1790 select CPU_HAS_PREFETCH
>> 1791 select CPU_SUPPORTS_CPUFREQ
>> 1792 select MIPS_EXTERNAL_TIMER
>> 1793 help
>> 1794 Support for BMIPS32/3300/4350/4380 and BMIPS5000 processors.
>> 1795
>> 1796 config CPU_XLR
>> 1797 bool "Netlogic XLR SoC"
>> 1798 depends on SYS_HAS_CPU_XLR
>> 1799 select CPU_SUPPORTS_32BIT_KERNEL
>> 1800 select CPU_SUPPORTS_64BIT_KERNEL
>> 1801 select CPU_SUPPORTS_HIGHMEM
>> 1802 select CPU_SUPPORTS_HUGEPAGES
>> 1803 select WEAK_ORDERING
>> 1804 select WEAK_REORDERING_BEYOND_LLSC
>> 1805 help
>> 1806 Netlogic Microsystems XLR/XLS processors.
>> 1807
>> 1808 config CPU_XLP
>> 1809 bool "Netlogic XLP SoC"
>> 1810 depends on SYS_HAS_CPU_XLP
>> 1811 select CPU_SUPPORTS_32BIT_KERNEL
>> 1812 select CPU_SUPPORTS_64BIT_KERNEL
>> 1813 select CPU_SUPPORTS_HIGHMEM
>> 1814 select WEAK_ORDERING
>> 1815 select WEAK_REORDERING_BEYOND_LLSC
>> 1816 select CPU_HAS_PREFETCH
>> 1817 select CPU_MIPSR2
>> 1818 select CPU_SUPPORTS_HUGEPAGES
>> 1819 select MIPS_ASID_BITS_VARIABLE
>> 1820 help
>> 1821 Netlogic Microsystems XLP processors.
>> 1822 endchoice
781 1823
782 Affected Cortex-A77 cores (r0p0, r1p !! 1824 config CPU_MIPS32_3_5_FEATURES
783 of a store-exclusive or read of PAR_ !! 1825 bool "MIPS32 Release 3.5 Features"
784 non-cacheable memory attributes. The !! 1826 depends on SYS_HAS_CPU_MIPS32_R3_5
785 counterpart. !! 1827 depends on CPU_MIPS32_R2 || CPU_MIPS32_R5 || CPU_MIPS32_R6 || \
786 !! 1828 CPU_P5600
787 KVM guests must also have the workar !! 1829 help
788 deadlock the system. !! 1830 Choose this option to build a kernel for release 2 or later of the
789 !! 1831 MIPS32 architecture including features from the 3.5 release such as
790 Work around the issue by inserting D !! 1832 support for Enhanced Virtual Addressing (EVA).
791 register reads and warning KVM users !! 1833
792 to prevent a speculative PAR_EL1 rea !! 1834 config CPU_MIPS32_3_5_EVA
>> 1835 bool "Enhanced Virtual Addressing (EVA)"
>> 1836 depends on CPU_MIPS32_3_5_FEATURES
>> 1837 select EVA
>> 1838 default y
>> 1839 help
>> 1840 Choose this option if you want to enable the Enhanced Virtual
>> 1841 Addressing (EVA) on your MIPS32 core (such as proAptiv).
>> 1842 One of its primary benefits is an increase in the maximum size
>> 1843 of lowmem (up to 3GB). If unsure, say 'N' here.
>> 1844
>> 1845 config CPU_MIPS32_R5_FEATURES
>> 1846 bool "MIPS32 Release 5 Features"
>> 1847 depends on SYS_HAS_CPU_MIPS32_R5
>> 1848 depends on CPU_MIPS32_R2 || CPU_MIPS32_R5 || CPU_P5600
>> 1849 help
>> 1850 Choose this option to build a kernel for release 2 or later of the
>> 1851 MIPS32 architecture including features from release 5 such as
>> 1852 support for Extended Physical Addressing (XPA).
>> 1853
>> 1854 config CPU_MIPS32_R5_XPA
>> 1855 bool "Extended Physical Addressing (XPA)"
>> 1856 depends on CPU_MIPS32_R5_FEATURES
>> 1857 depends on !EVA
>> 1858 depends on !PAGE_SIZE_4KB
>> 1859 depends on SYS_SUPPORTS_HIGHMEM
>> 1860 select XPA
>> 1861 select HIGHMEM
>> 1862 select PHYS_ADDR_T_64BIT
>> 1863 default n
>> 1864 help
>> 1865 Choose this option if you want to enable the Extended Physical
>> 1866 Addressing (XPA) on your MIPS32 core (such as P5600 series). The
>> 1867 benefit is to increase physical addressing equal to or greater
>> 1868 than 40 bits. Note that this has the side effect of turning on
>> 1869 64-bit addressing which in turn makes the PTEs 64-bit in size.
>> 1870 If unsure, say 'N' here.
793 1871
794 If unsure, say Y. !! 1872 if CPU_LOONGSON2F
>> 1873 config CPU_NOP_WORKAROUNDS
>> 1874 bool
795 1875
796 config ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MO !! 1876 config CPU_JUMP_WORKAROUNDS
797 bool 1877 bool
798 1878
799 config ARM64_ERRATUM_2051678 !! 1879 config CPU_LOONGSON2F_WORKAROUNDS
800 bool "Cortex-A510: 2051678: disable Ha !! 1880 bool "Loongson 2F Workarounds"
801 default y 1881 default y
>> 1882 select CPU_NOP_WORKAROUNDS
>> 1883 select CPU_JUMP_WORKAROUNDS
802 help 1884 help
803 This options adds the workaround for !! 1885 Loongson 2F01 / 2F02 processors have the NOP & JUMP issues which
804 Affected Cortex-A510 might not respe !! 1886 require workarounds. Without workarounds the system may hang
805 hardware update of the page table's !! 1887 unexpectedly. For more information please refer to the gas
806 is to not enable the feature on affe !! 1888 -mfix-loongson2f-nop and -mfix-loongson2f-jump options.
>> 1889
>> 1890 Loongson 2F03 and later have fixed these issues and no workarounds
>> 1891 are needed. The workarounds have no significant side effect on them
>> 1892 but may decrease the performance of the system so this option should
>> 1893 be disabled unless the kernel is intended to be run on 2F01 or 2F02
>> 1894 systems.
807 1895
808 If unsure, say Y. !! 1896 If unsure, please say Y.
>> 1897 endif # CPU_LOONGSON2F
809 1898
810 config ARM64_ERRATUM_2077057 !! 1899 config SYS_SUPPORTS_ZBOOT
811 bool "Cortex-A510: 2077057: workaround !! 1900 bool
812 default y !! 1901 select HAVE_KERNEL_GZIP
813 help !! 1902 select HAVE_KERNEL_BZIP2
814 This option adds the workaround for !! 1903 select HAVE_KERNEL_LZ4
815 Affected Cortex-A510 may corrupt SPS !! 1904 select HAVE_KERNEL_LZMA
816 expected, but a Pointer Authenticati !! 1905 select HAVE_KERNEL_LZO
817 erratum causes SPSR_EL1 to be copied !! 1906 select HAVE_KERNEL_XZ
818 EL1 to cause a return to EL2 with a !! 1907 select HAVE_KERNEL_ZSTD
819 <<
820 This can only happen when EL2 is ste <<
821 1908
822 When these conditions occur, the SPS !! 1909 config SYS_SUPPORTS_ZBOOT_UART16550
823 previous guest entry, and can be res !! 1910 bool
>> 1911 select SYS_SUPPORTS_ZBOOT
824 1912
825 If unsure, say Y. !! 1913 config SYS_SUPPORTS_ZBOOT_UART_PROM
>> 1914 bool
>> 1915 select SYS_SUPPORTS_ZBOOT
826 1916
827 config ARM64_ERRATUM_2658417 !! 1917 config CPU_LOONGSON2EF
828 bool "Cortex-A510: 2658417: remove BF1 !! 1918 bool
829 default y !! 1919 select CPU_SUPPORTS_32BIT_KERNEL
830 help !! 1920 select CPU_SUPPORTS_64BIT_KERNEL
831 This option adds the workaround for !! 1921 select CPU_SUPPORTS_HIGHMEM
832 Affected Cortex-A510 (r0p0 to r1p1) !! 1922 select CPU_SUPPORTS_HUGEPAGES
833 BFMMLA or VMMLA instructions in rare !! 1923 select ARCH_HAS_PHYS_TO_DMA
834 A510 CPUs are using shared neon hard <<
835 discoverable by the kernel, hide the <<
836 user-space should not be using these <<
837 1924
838 If unsure, say Y. !! 1925 config CPU_LOONGSON32
>> 1926 bool
>> 1927 select CPU_MIPS32
>> 1928 select CPU_MIPSR2
>> 1929 select CPU_HAS_PREFETCH
>> 1930 select CPU_SUPPORTS_32BIT_KERNEL
>> 1931 select CPU_SUPPORTS_HIGHMEM
>> 1932 select CPU_SUPPORTS_CPUFREQ
839 1933
840 config ARM64_ERRATUM_2119858 !! 1934 config CPU_BMIPS32_3300
841 bool "Cortex-A710/X2: 2119858: workaro !! 1935 select SMP_UP if SMP
842 default y !! 1936 bool
843 depends on CORESIGHT_TRBE <<
844 select ARM64_WORKAROUND_TRBE_OVERWRITE <<
845 help <<
846 This option adds the workaround for <<
847 1937
848 Affected Cortex-A710/X2 cores could !! 1938 config CPU_BMIPS4350
849 data at the base of the buffer (poin !! 1939 bool
850 the event of a WRAP event. !! 1940 select SYS_SUPPORTS_SMP
851 !! 1941 select SYS_SUPPORTS_HOTPLUG_CPU
852 Work around the issue by always maki <<
853 256 bytes before enabling the buffer <<
854 the buffer with ETM ignore packets u <<
855 1942
856 If unsure, say Y. !! 1943 config CPU_BMIPS4380
>> 1944 bool
>> 1945 select MIPS_L1_CACHE_SHIFT_6
>> 1946 select SYS_SUPPORTS_SMP
>> 1947 select SYS_SUPPORTS_HOTPLUG_CPU
>> 1948 select CPU_HAS_RIXI
857 1949
858 config ARM64_ERRATUM_2139208 !! 1950 config CPU_BMIPS5000
859 bool "Neoverse-N2: 2139208: workaround !! 1951 bool
860 default y !! 1952 select MIPS_CPU_SCACHE
861 depends on CORESIGHT_TRBE !! 1953 select MIPS_L1_CACHE_SHIFT_7
862 select ARM64_WORKAROUND_TRBE_OVERWRITE !! 1954 select SYS_SUPPORTS_SMP
863 help !! 1955 select SYS_SUPPORTS_HOTPLUG_CPU
864 This option adds the workaround for !! 1956 select CPU_HAS_RIXI
865 1957
866 Affected Neoverse-N2 cores could ove !! 1958 config SYS_HAS_CPU_LOONGSON64
867 data at the base of the buffer (poin !! 1959 bool
868 the event of a WRAP event. !! 1960 select CPU_SUPPORTS_CPUFREQ
869 !! 1961 select CPU_HAS_RIXI
870 Work around the issue by always maki <<
871 256 bytes before enabling the buffer <<
872 the buffer with ETM ignore packets u <<
873 1962
874 If unsure, say Y. !! 1963 config SYS_HAS_CPU_LOONGSON2E
>> 1964 bool
875 1965
876 config ARM64_WORKAROUND_TSB_FLUSH_FAILURE !! 1966 config SYS_HAS_CPU_LOONGSON2F
877 bool 1967 bool
>> 1968 select CPU_SUPPORTS_CPUFREQ
>> 1969 select CPU_SUPPORTS_ADDRWINCFG if 64BIT
878 1970
879 config ARM64_ERRATUM_2054223 !! 1971 config SYS_HAS_CPU_LOONGSON1B
880 bool "Cortex-A710: 2054223: workaround !! 1972 bool
881 default y <<
882 select ARM64_WORKAROUND_TSB_FLUSH_FAIL <<
883 help <<
884 Enable workaround for ARM Cortex-A71 <<
885 1973
886 Affected cores may fail to flush the !! 1974 config SYS_HAS_CPU_LOONGSON1C
887 the PE is in trace prohibited state. !! 1975 bool
888 of the trace cached. <<
889 1976
890 Workaround is to issue two TSB conse !! 1977 config SYS_HAS_CPU_MIPS32_R1
>> 1978 bool
891 1979
892 If unsure, say Y. !! 1980 config SYS_HAS_CPU_MIPS32_R2
>> 1981 bool
893 1982
894 config ARM64_ERRATUM_2067961 !! 1983 config SYS_HAS_CPU_MIPS32_R3_5
895 bool "Neoverse-N2: 2067961: workaround !! 1984 bool
896 default y <<
897 select ARM64_WORKAROUND_TSB_FLUSH_FAIL <<
898 help <<
899 Enable workaround for ARM Neoverse-N <<
900 1985
901 Affected cores may fail to flush the !! 1986 config SYS_HAS_CPU_MIPS32_R5
902 the PE is in trace prohibited state. !! 1987 bool
903 of the trace cached. !! 1988 select ARCH_HAS_SYNC_DMA_FOR_CPU if DMA_NONCOHERENT
904 1989
905 Workaround is to issue two TSB conse !! 1990 config SYS_HAS_CPU_MIPS32_R6
>> 1991 bool
>> 1992 select ARCH_HAS_SYNC_DMA_FOR_CPU if DMA_NONCOHERENT
906 1993
907 If unsure, say Y. !! 1994 config SYS_HAS_CPU_MIPS64_R1
>> 1995 bool
908 1996
909 config ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANG !! 1997 config SYS_HAS_CPU_MIPS64_R2
910 bool 1998 bool
911 1999
912 config ARM64_ERRATUM_2253138 !! 2000 config SYS_HAS_CPU_MIPS64_R5
913 bool "Neoverse-N2: 2253138: workaround !! 2001 bool
914 depends on CORESIGHT_TRBE !! 2002 select ARCH_HAS_SYNC_DMA_FOR_CPU if DMA_NONCOHERENT
915 default y <<
916 select ARM64_WORKAROUND_TRBE_WRITE_OUT <<
917 help <<
918 This option adds the workaround for <<
919 2003
920 Affected Neoverse-N2 cores might wri !! 2004 config SYS_HAS_CPU_MIPS64_R6
921 for TRBE. Under some conditions, the !! 2005 bool
922 virtually addressed page following t !! 2006 select ARCH_HAS_SYNC_DMA_FOR_CPU if DMA_NONCOHERENT
923 (i.e., the TRBLIMITR_EL1.LIMIT), ins <<
924 2007
925 Work around this in the driver by al !! 2008 config SYS_HAS_CPU_P5600
926 page beyond the TRBLIMITR_EL1.LIMIT, !! 2009 bool
>> 2010 select ARCH_HAS_SYNC_DMA_FOR_CPU if DMA_NONCOHERENT
927 2011
928 If unsure, say Y. !! 2012 config SYS_HAS_CPU_R3000
>> 2013 bool
929 2014
930 config ARM64_ERRATUM_2224489 !! 2015 config SYS_HAS_CPU_TX39XX
931 bool "Cortex-A710/X2: 2224489: workaro !! 2016 bool
932 depends on CORESIGHT_TRBE <<
933 default y <<
934 select ARM64_WORKAROUND_TRBE_WRITE_OUT <<
935 help <<
936 This option adds the workaround for <<
937 2017
938 Affected Cortex-A710/X2 cores might !! 2018 config SYS_HAS_CPU_VR41XX
939 for TRBE. Under some conditions, the !! 2019 bool
940 virtually addressed page following t <<
941 (i.e., the TRBLIMITR_EL1.LIMIT), ins <<
942 2020
943 Work around this in the driver by al !! 2021 config SYS_HAS_CPU_R4300
944 page beyond the TRBLIMITR_EL1.LIMIT, !! 2022 bool
945 2023
946 If unsure, say Y. !! 2024 config SYS_HAS_CPU_R4X00
>> 2025 bool
947 2026
948 config ARM64_ERRATUM_2441009 !! 2027 config SYS_HAS_CPU_TX49XX
949 bool "Cortex-A510: Completion of affec !! 2028 bool
950 select ARM64_WORKAROUND_REPEAT_TLBI <<
951 help <<
952 This option adds a workaround for AR <<
953 <<
954 Under very rare circumstances, affec <<
955 may not handle a race between a brea <<
956 CPU, and another CPU accessing the s <<
957 store to a page that has been unmapp <<
958 2029
959 Work around this by adding the affec !! 2030 config SYS_HAS_CPU_R5000
960 TLB sequences to be done twice. !! 2031 bool
961 2032
962 If unsure, say N. !! 2033 config SYS_HAS_CPU_R5500
>> 2034 bool
963 2035
964 config ARM64_ERRATUM_2064142 !! 2036 config SYS_HAS_CPU_NEVADA
965 bool "Cortex-A510: 2064142: workaround !! 2037 bool
966 depends on CORESIGHT_TRBE <<
967 default y <<
968 help <<
969 This option adds the workaround for <<
970 2038
971 Affected Cortex-A510 core might fail !! 2039 config SYS_HAS_CPU_R10000
972 TRBE has been disabled. Under some c !! 2040 bool
973 writes into TRBE registers TRBLIMITR !! 2041 select ARCH_HAS_SYNC_DMA_FOR_CPU if DMA_NONCOHERENT
974 and TRBTRG_EL1 will be ignored and w <<
975 <<
976 Work around this in the driver by ex <<
977 is stopped and before performing a s <<
978 registers. <<
979 2042
980 If unsure, say Y. !! 2043 config SYS_HAS_CPU_RM7000
>> 2044 bool
981 2045
982 config ARM64_ERRATUM_2038923 !! 2046 config SYS_HAS_CPU_SB1
983 bool "Cortex-A510: 2038923: workaround !! 2047 bool
984 depends on CORESIGHT_TRBE <<
985 default y <<
986 help <<
987 This option adds the workaround for <<
988 2048
989 Affected Cortex-A510 core might caus !! 2049 config SYS_HAS_CPU_CAVIUM_OCTEON
990 prohibited within the CPU. As a resu !! 2050 bool
991 might be corrupted. This happens aft <<
992 TRBLIMITR_EL1.E, followed by just a <<
993 execution changes from a context, in <<
994 isn't, or vice versa. In these menti <<
995 is prohibited is inconsistent betwee <<
996 the trace buffer state might be corr <<
997 <<
998 Work around this in the driver by pr <<
999 trace is prohibited or not based on <<
1000 change to TRBLIMITR_EL1.E with at l <<
1001 two ISB instructions if no ERET is <<
1002 2051
1003 If unsure, say Y. !! 2052 config SYS_HAS_CPU_BMIPS
>> 2053 bool
1004 2054
1005 config ARM64_ERRATUM_1902691 !! 2055 config SYS_HAS_CPU_BMIPS32_3300
1006 bool "Cortex-A510: 1902691: workaroun !! 2056 bool
1007 depends on CORESIGHT_TRBE !! 2057 select SYS_HAS_CPU_BMIPS
1008 default y <<
1009 help <<
1010 This option adds the workaround for <<
1011 2058
1012 Affected Cortex-A510 core might cau !! 2059 config SYS_HAS_CPU_BMIPS4350
1013 into the memory. Effectively TRBE i !! 2060 bool
1014 trace data. !! 2061 select SYS_HAS_CPU_BMIPS
1015 <<
1016 Work around this problem in the dri <<
1017 affected cpus. The firmware must ha <<
1018 on such implementations. This will <<
1019 do this already. <<
1020 2062
1021 If unsure, say Y. !! 2063 config SYS_HAS_CPU_BMIPS4380
>> 2064 bool
>> 2065 select SYS_HAS_CPU_BMIPS
1022 2066
1023 config ARM64_ERRATUM_2457168 !! 2067 config SYS_HAS_CPU_BMIPS5000
1024 bool "Cortex-A510: 2457168: workaroun !! 2068 bool
1025 depends on ARM64_AMU_EXTN !! 2069 select SYS_HAS_CPU_BMIPS
1026 default y !! 2070 select ARCH_HAS_SYNC_DMA_FOR_CPU
1027 help <<
1028 This option adds the workaround for <<
1029 2071
1030 The AMU counter AMEVCNTR01 (constan !! 2072 config SYS_HAS_CPU_XLR
1031 as the system counter. On affected !! 2073 bool
1032 incorrectly giving a significantly <<
1033 <<
1034 Work around this problem by returni <<
1035 key locations that results in disab <<
1036 is the same to firmware disabling a <<
1037 2074
1038 If unsure, say Y. !! 2075 config SYS_HAS_CPU_XLP
>> 2076 bool
1039 2077
1040 config ARM64_ERRATUM_2645198 !! 2078 #
1041 bool "Cortex-A715: 2645198: Workaroun !! 2079 # CPU may reorder R->R, R->W, W->R, W->W
1042 default y !! 2080 # Reordering beyond LL and SC is handled in WEAK_REORDERING_BEYOND_LLSC
1043 help !! 2081 #
1044 This option adds the workaround for !! 2082 config WEAK_ORDERING
>> 2083 bool
1045 2084
1046 If a Cortex-A715 cpu sees a page ma !! 2085 #
1047 to non-executable, it may corrupt t !! 2086 # CPU may reorder reads and writes beyond LL/SC
1048 next instruction abort caused by pe !! 2087 # CPU may reorder R->LL, R->LL, W->LL, W->LL, R->SC, R->SC, W->SC, W->SC
1049 !! 2088 #
1050 Only user-space does executable to !! 2089 config WEAK_REORDERING_BEYOND_LLSC
1051 mprotect() system call. Workaround !! 2090 bool
1052 TLB invalidation, for all changes t !! 2091 endmenu
1053 2092
1054 If unsure, say Y. !! 2093 #
>> 2094 # These two indicate any level of the MIPS32 and MIPS64 architecture
>> 2095 #
>> 2096 config CPU_MIPS32
>> 2097 bool
>> 2098 default y if CPU_MIPS32_R1 || CPU_MIPS32_R2 || CPU_MIPS32_R5 || \
>> 2099 CPU_MIPS32_R6 || CPU_P5600
1055 2100
1056 config ARM64_WORKAROUND_SPECULATIVE_UNPRIV_LO !! 2101 config CPU_MIPS64
1057 bool 2102 bool
>> 2103 default y if CPU_MIPS64_R1 || CPU_MIPS64_R2 || CPU_MIPS64_R5 || \
>> 2104 CPU_MIPS64_R6 || CPU_LOONGSON64 || CPU_CAVIUM_OCTEON
1058 2105
1059 config ARM64_ERRATUM_2966298 !! 2106 #
1060 bool "Cortex-A520: 2966298: workaroun !! 2107 # These indicate the revision of the architecture
1061 select ARM64_WORKAROUND_SPECULATIVE_U !! 2108 #
1062 default y !! 2109 config CPU_MIPSR1
1063 help !! 2110 bool
1064 This option adds the workaround for !! 2111 default y if CPU_MIPS32_R1 || CPU_MIPS64_R1
1065 2112
1066 On an affected Cortex-A520 core, a !! 2113 config CPU_MIPSR2
1067 load might leak data from a privile !! 2114 bool
>> 2115 default y if CPU_MIPS32_R2 || CPU_MIPS64_R2 || CPU_CAVIUM_OCTEON
>> 2116 select CPU_HAS_RIXI
>> 2117 select CPU_HAS_DIEI if !CPU_DIEI_BROKEN
>> 2118 select MIPS_SPRAM
1068 2119
1069 Work around this problem by executi !! 2120 config CPU_MIPSR5
>> 2121 bool
>> 2122 default y if CPU_MIPS32_R5 || CPU_MIPS64_R5 || CPU_P5600
>> 2123 select CPU_HAS_RIXI
>> 2124 select CPU_HAS_DIEI if !CPU_DIEI_BROKEN
>> 2125 select MIPS_SPRAM
1070 2126
1071 If unsure, say Y. !! 2127 config CPU_MIPSR6
>> 2128 bool
>> 2129 default y if CPU_MIPS32_R6 || CPU_MIPS64_R6
>> 2130 select CPU_HAS_RIXI
>> 2131 select CPU_HAS_DIEI if !CPU_DIEI_BROKEN
>> 2132 select HAVE_ARCH_BITREVERSE
>> 2133 select MIPS_ASID_BITS_VARIABLE
>> 2134 select MIPS_CRC_SUPPORT
>> 2135 select MIPS_SPRAM
1072 2136
1073 config ARM64_ERRATUM_3117295 !! 2137 config TARGET_ISA_REV
1074 bool "Cortex-A510: 3117295: workaroun !! 2138 int
1075 select ARM64_WORKAROUND_SPECULATIVE_U !! 2139 default 1 if CPU_MIPSR1
1076 default y !! 2140 default 2 if CPU_MIPSR2
>> 2141 default 5 if CPU_MIPSR5
>> 2142 default 6 if CPU_MIPSR6
>> 2143 default 0
1077 help 2144 help
1078 This option adds the workaround for !! 2145 Reflects the ISA revision being targeted by the kernel build. This
>> 2146 is effectively the Kconfig equivalent of MIPS_ISA_REV.
1079 2147
1080 On an affected Cortex-A510 core, a !! 2148 config EVA
1081 load might leak data from a privile !! 2149 bool
1082 2150
1083 Work around this problem by executi !! 2151 config XPA
>> 2152 bool
1084 2153
1085 If unsure, say Y. !! 2154 config SYS_SUPPORTS_32BIT_KERNEL
>> 2155 bool
>> 2156 config SYS_SUPPORTS_64BIT_KERNEL
>> 2157 bool
>> 2158 config CPU_SUPPORTS_32BIT_KERNEL
>> 2159 bool
>> 2160 config CPU_SUPPORTS_64BIT_KERNEL
>> 2161 bool
>> 2162 config CPU_SUPPORTS_CPUFREQ
>> 2163 bool
>> 2164 config CPU_SUPPORTS_ADDRWINCFG
>> 2165 bool
>> 2166 config CPU_SUPPORTS_HUGEPAGES
>> 2167 bool
>> 2168 depends on !(32BIT && (PHYS_ADDR_T_64BIT || EVA))
>> 2169 config MIPS_PGD_C0_CONTEXT
>> 2170 bool
>> 2171 depends on 64BIT
>> 2172 default y if (CPU_MIPSR2 || CPU_MIPSR6) && !CPU_XLP
1086 2173
1087 config ARM64_ERRATUM_3194386 !! 2174 #
1088 bool "Cortex-*/Neoverse-*: workaround !! 2175 # Set to y for ptrace access to watch registers.
1089 default y !! 2176 #
1090 help !! 2177 config HARDWARE_WATCHPOINTS
1091 This option adds the workaround for !! 2178 bool
>> 2179 default y if CPU_MIPSR1 || CPU_MIPSR2 || CPU_MIPSR6
1092 2180
1093 * ARM Cortex-A76 erratum 3324349 !! 2181 menu "Kernel type"
1094 * ARM Cortex-A77 erratum 3324348 <<
1095 * ARM Cortex-A78 erratum 3324344 <<
1096 * ARM Cortex-A78C erratum 3324346 <<
1097 * ARM Cortex-A78C erratum 3324347 <<
1098 * ARM Cortex-A710 erratam 3324338 <<
1099 * ARM Cortex-A715 errartum 3456084 <<
1100 * ARM Cortex-A720 erratum 3456091 <<
1101 * ARM Cortex-A725 erratum 3456106 <<
1102 * ARM Cortex-X1 erratum 3324344 <<
1103 * ARM Cortex-X1C erratum 3324346 <<
1104 * ARM Cortex-X2 erratum 3324338 <<
1105 * ARM Cortex-X3 erratum 3324335 <<
1106 * ARM Cortex-X4 erratum 3194386 <<
1107 * ARM Cortex-X925 erratum 3324334 <<
1108 * ARM Neoverse-N1 erratum 3324349 <<
1109 * ARM Neoverse N2 erratum 3324339 <<
1110 * ARM Neoverse-N3 erratum 3456111 <<
1111 * ARM Neoverse-V1 erratum 3324341 <<
1112 * ARM Neoverse V2 erratum 3324336 <<
1113 * ARM Neoverse-V3 erratum 3312417 <<
1114 <<
1115 On affected cores "MSR SSBS, #0" in <<
1116 subsequent speculative instructions <<
1117 speculative store bypassing. <<
1118 <<
1119 Work around this problem by placing <<
1120 Instruction Synchronization Barrier <<
1121 SSBS. The presence of the SSBS spec <<
1122 from hwcaps and EL0 reads of ID_AA6 <<
1123 will use the PR_SPEC_STORE_BYPASS p <<
1124 2182
1125 If unsure, say Y. !! 2183 choice
>> 2184 prompt "Kernel code model"
>> 2185 help
>> 2186 You should only select this option if you have a workload that
>> 2187 actually benefits from 64-bit processing or if your machine has
>> 2188 large memory. You will only be presented a single option in this
>> 2189 menu if your system does not support both 32-bit and 64-bit kernels.
>> 2190
>> 2191 config 32BIT
>> 2192 bool "32-bit kernel"
>> 2193 depends on CPU_SUPPORTS_32BIT_KERNEL && SYS_SUPPORTS_32BIT_KERNEL
>> 2194 select TRAD_SIGNALS
>> 2195 help
>> 2196 Select this option if you want to build a 32-bit kernel.
1126 2197
1127 config CAVIUM_ERRATUM_22375 !! 2198 config 64BIT
1128 bool "Cavium erratum 22375, 24313" !! 2199 bool "64-bit kernel"
1129 default y !! 2200 depends on CPU_SUPPORTS_64BIT_KERNEL && SYS_SUPPORTS_64BIT_KERNEL
1130 help 2201 help
1131 Enable workaround for errata 22375 !! 2202 Select this option if you want to build a 64-bit kernel.
1132 2203
1133 This implements two gicv3-its errat !! 2204 endchoice
1134 with a small impact affecting only <<
1135 2205
1136 erratum 22375: only alloc 8MB tab !! 2206 config MIPS_VA_BITS_48
1137 erratum 24313: ignore memory acce !! 2207 bool "48 bits virtual memory"
>> 2208 depends on 64BIT
>> 2209 help
>> 2210 Support a maximum at least 48 bits of application virtual
>> 2211 memory. Default is 40 bits or less, depending on the CPU.
>> 2212 For page sizes 16k and above, this option results in a small
>> 2213 memory overhead for page tables. For 4k page size, a fourth
>> 2214 level of page tables is added which imposes both a memory
>> 2215 overhead as well as slower TLB fault handling.
1138 2216
1139 The fixes are in ITS initialization !! 2217 If unsure, say N.
1140 type and table size provided by the <<
1141 2218
1142 If unsure, say Y. !! 2219 choice
>> 2220 prompt "Kernel page size"
>> 2221 default PAGE_SIZE_4KB
1143 2222
1144 config CAVIUM_ERRATUM_23144 !! 2223 config PAGE_SIZE_4KB
1145 bool "Cavium erratum 23144: ITS SYNC !! 2224 bool "4kB"
1146 depends on NUMA !! 2225 depends on !CPU_LOONGSON2EF && !CPU_LOONGSON64
1147 default y !! 2226 help
1148 help !! 2227 This option select the standard 4kB Linux page size. On some
1149 ITS SYNC command hang for cross nod !! 2228 R3000-family processors this is the only available page size. Using
>> 2229 4kB page size will minimize memory consumption and is therefore
>> 2230 recommended for low memory systems.
>> 2231
>> 2232 config PAGE_SIZE_8KB
>> 2233 bool "8kB"
>> 2234 depends on CPU_CAVIUM_OCTEON
>> 2235 depends on !MIPS_VA_BITS_48
>> 2236 help
>> 2237 Using 8kB page size will result in higher performance kernel at
>> 2238 the price of higher memory consumption. This option is available
>> 2239 only on cnMIPS processors. Note that you will need a suitable Linux
>> 2240 distribution to support this.
>> 2241
>> 2242 config PAGE_SIZE_16KB
>> 2243 bool "16kB"
>> 2244 depends on !CPU_R3000 && !CPU_TX39XX
>> 2245 help
>> 2246 Using 16kB page size will result in higher performance kernel at
>> 2247 the price of higher memory consumption. This option is available on
>> 2248 all non-R3000 family processors. Note that you will need a suitable
>> 2249 Linux distribution to support this.
>> 2250
>> 2251 config PAGE_SIZE_32KB
>> 2252 bool "32kB"
>> 2253 depends on CPU_CAVIUM_OCTEON
>> 2254 depends on !MIPS_VA_BITS_48
>> 2255 help
>> 2256 Using 32kB page size will result in higher performance kernel at
>> 2257 the price of higher memory consumption. This option is available
>> 2258 only on cnMIPS cores. Note that you will need a suitable Linux
>> 2259 distribution to support this.
>> 2260
>> 2261 config PAGE_SIZE_64KB
>> 2262 bool "64kB"
>> 2263 depends on !CPU_R3000 && !CPU_TX39XX
>> 2264 help
>> 2265 Using 64kB page size will result in higher performance kernel at
>> 2266 the price of higher memory consumption. This option is available on
>> 2267 all non-R3000 family processor. Not that at the time of this
>> 2268 writing this option is still high experimental.
1150 2269
1151 If unsure, say Y. !! 2270 endchoice
1152 2271
1153 config CAVIUM_ERRATUM_23154 !! 2272 config FORCE_MAX_ZONEORDER
1154 bool "Cavium errata 23154 and 38545: !! 2273 int "Maximum zone order"
1155 default y !! 2274 range 14 64 if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_64KB
1156 help !! 2275 default "14" if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_64KB
1157 The ThunderX GICv3 implementation r !! 2276 range 13 64 if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_32KB
1158 reading the IAR status to ensure da !! 2277 default "13" if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_32KB
1159 (access to icc_iar1_el1 is not sync !! 2278 range 12 64 if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_16KB
1160 !! 2279 default "12" if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_16KB
1161 It also suffers from erratum 38545 !! 2280 range 0 64
1162 OcteonTX and OcteonTX2), resulting !! 2281 default "11"
1163 spuriously presented to the CPU int !! 2282 help
>> 2283 The kernel memory allocator divides physically contiguous memory
>> 2284 blocks into "zones", where each zone is a power of two number of
>> 2285 pages. This option selects the largest power of two that the kernel
>> 2286 keeps in the memory allocator. If you need to allocate very large
>> 2287 blocks of physically contiguous memory, then you may need to
>> 2288 increase this value.
1164 2289
1165 If unsure, say Y. !! 2290 This config option is actually maximum order plus one. For example,
>> 2291 a value of 11 means that the largest free memory block is 2^10 pages.
1166 2292
1167 config CAVIUM_ERRATUM_27456 !! 2293 The page size is not necessarily 4KB. Keep this in mind
1168 bool "Cavium erratum 27456: Broadcast !! 2294 when choosing a value for this option.
1169 default y <<
1170 help <<
1171 On ThunderX T88 pass 1.x through 2. <<
1172 instructions may cause the icache t <<
1173 contains data for a non-current ASI <<
1174 invalidate the icache when changing <<
1175 2295
1176 If unsure, say Y. !! 2296 config BOARD_SCACHE
>> 2297 bool
1177 2298
1178 config CAVIUM_ERRATUM_30115 !! 2299 config IP22_CPU_SCACHE
1179 bool "Cavium erratum 30115: Guest may !! 2300 bool
1180 default y !! 2301 select BOARD_SCACHE
1181 help <<
1182 On ThunderX T88 pass 1.x through 2. <<
1183 1.2, and T83 Pass 1.0, KVM guest ex <<
1184 interrupts in host. Trapping both G <<
1185 accesses sidesteps the issue. <<
1186 2302
1187 If unsure, say Y. !! 2303 #
>> 2304 # Support for a MIPS32 / MIPS64 style S-caches
>> 2305 #
>> 2306 config MIPS_CPU_SCACHE
>> 2307 bool
>> 2308 select BOARD_SCACHE
1188 2309
1189 config CAVIUM_TX2_ERRATUM_219 !! 2310 config R5000_CPU_SCACHE
1190 bool "Cavium ThunderX2 erratum 219: P !! 2311 bool
1191 default y !! 2312 select BOARD_SCACHE
1192 help <<
1193 On Cavium ThunderX2, a load, store <<
1194 TTBR update and the corresponding c <<
1195 cause a spurious Data Abort to be d <<
1196 the CPU core. <<
1197 <<
1198 Work around the issue by avoiding t <<
1199 trapping KVM guest TTBRx_EL1 writes <<
1200 trap handler performs the correspon <<
1201 instruction and ensures context syn <<
1202 exception return. <<
1203 2313
1204 If unsure, say Y. !! 2314 config RM7000_CPU_SCACHE
>> 2315 bool
>> 2316 select BOARD_SCACHE
1205 2317
1206 config FUJITSU_ERRATUM_010001 !! 2318 config SIBYTE_DMA_PAGEOPS
1207 bool "Fujitsu-A64FX erratum E#010001: !! 2319 bool "Use DMA to clear/copy pages"
1208 default y !! 2320 depends on CPU_SB1
1209 help 2321 help
1210 This option adds a workaround for F !! 2322 Instead of using the CPU to zero and copy pages, use a Data Mover
1211 On some variants of the Fujitsu-A64 !! 2323 channel. These DMA channels are otherwise unused by the standard
1212 accesses may cause undefined fault !! 2324 SiByte Linux port. Seems to give a small performance benefit.
1213 This fault occurs under a specific <<
1214 load/store instruction performs an <<
1215 case-1 TTBR0_EL1 with TCR_EL1.NFD0 <<
1216 case-2 TTBR0_EL2 with TCR_EL2.NFD0 <<
1217 case-3 TTBR1_EL1 with TCR_EL1.NFD1 <<
1218 case-4 TTBR1_EL2 with TCR_EL2.NFD1 <<
1219 2325
1220 The workaround is to ensure these b !! 2326 config CPU_HAS_PREFETCH
1221 The workaround only affects the Fuj !! 2327 bool
1222 2328
1223 If unsure, say Y. !! 2329 config CPU_GENERIC_DUMP_TLB
>> 2330 bool
>> 2331 default y if !(CPU_R3000 || CPU_TX39XX)
1224 2332
1225 config HISILICON_ERRATUM_161600802 !! 2333 config MIPS_FP_SUPPORT
1226 bool "Hip07 161600802: Erroneous redi !! 2334 bool "Floating Point support" if EXPERT
1227 default y 2335 default y
1228 help 2336 help
1229 The HiSilicon Hip07 SoC uses the wr !! 2337 Select y to include support for floating point in the kernel
1230 when issued ITS commands such as VM !! 2338 including initialization of FPU hardware, FP context save & restore
1231 a 128kB offset to be applied to the !! 2339 and emulation of an FPU where necessary. Without this support any
>> 2340 userland program attempting to use floating point instructions will
>> 2341 receive a SIGILL.
1232 2342
1233 If unsure, say Y. !! 2343 If you know that your userland will not attempt to use floating point
>> 2344 instructions then you can say n here to shrink the kernel a little.
1234 2345
1235 config QCOM_FALKOR_ERRATUM_1003 !! 2346 If unsure, say y.
1236 bool "Falkor E1003: Incorrect transla <<
1237 default y <<
1238 help <<
1239 On Falkor v1, an incorrect ASID may <<
1240 and BADDR are changed together in T <<
1241 in TTBR1_EL1, this situation only o <<
1242 then only for entries in the walk c <<
1243 is unchanged. Work around the errat <<
1244 entries for the trampoline before e <<
1245 2347
1246 config QCOM_FALKOR_ERRATUM_1009 !! 2348 config CPU_R2300_FPU
1247 bool "Falkor E1009: Prematurely compl !! 2349 bool
1248 default y !! 2350 depends on MIPS_FP_SUPPORT
1249 select ARM64_WORKAROUND_REPEAT_TLBI !! 2351 default y if CPU_R3000 || CPU_TX39XX
1250 help <<
1251 On Falkor v1, the CPU may premature <<
1252 TLBI xxIS invalidate maintenance op <<
1253 one more time to fix the issue. <<
1254 2352
1255 If unsure, say Y. !! 2353 config CPU_R3K_TLB
>> 2354 bool
1256 2355
1257 config QCOM_QDF2400_ERRATUM_0065 !! 2356 config CPU_R4K_FPU
1258 bool "QDF2400 E0065: Incorrect GITS_T !! 2357 bool
1259 default y !! 2358 depends on MIPS_FP_SUPPORT
1260 help !! 2359 default y if !CPU_R2300_FPU
1261 On Qualcomm Datacenter Technologies <<
1262 ITE size incorrectly. The GITS_TYPE <<
1263 been indicated as 16Bytes (0xf), no <<
1264 2360
1265 If unsure, say Y. !! 2361 config CPU_R4K_CACHE_TLB
>> 2362 bool
>> 2363 default y if !(CPU_R3K_TLB || CPU_SB1 || CPU_CAVIUM_OCTEON)
1266 2364
1267 config QCOM_FALKOR_ERRATUM_E1041 !! 2365 config MIPS_MT_SMP
1268 bool "Falkor E1041: Speculative instr !! 2366 bool "MIPS MT SMP support (1 TC on each available VPE)"
1269 default y 2367 default y
1270 help !! 2368 depends on SYS_SUPPORTS_MULTITHREADING && !CPU_MIPSR6 && !CPU_MICROMIPS
1271 Falkor CPU may speculatively fetch !! 2369 select CPU_MIPSR2_IRQ_VI
1272 memory location when MMU translatio !! 2370 select CPU_MIPSR2_IRQ_EI
1273 to SCTLR_ELn[M]=0. Prefix an ISB in !! 2371 select SYNC_R4K
>> 2372 select MIPS_MT
>> 2373 select SMP
>> 2374 select SMP_UP
>> 2375 select SYS_SUPPORTS_SMP
>> 2376 select SYS_SUPPORTS_SCHED_SMT
>> 2377 select MIPS_PERF_SHARED_TC_COUNTERS
>> 2378 help
>> 2379 This is a kernel model which is known as SMVP. This is supported
>> 2380 on cores with the MT ASE and uses the available VPEs to implement
>> 2381 virtual processors which supports SMP. This is equivalent to the
>> 2382 Intel Hyperthreading feature. For further information go to
>> 2383 <http://www.imgtec.com/mips/mips-multithreading.asp>.
1274 2384
1275 If unsure, say Y. !! 2385 config MIPS_MT
>> 2386 bool
1276 2387
1277 config NVIDIA_CARMEL_CNP_ERRATUM !! 2388 config SCHED_SMT
1278 bool "NVIDIA Carmel CNP: CNP on Carme !! 2389 bool "SMT (multithreading) scheduler support"
1279 default y !! 2390 depends on SYS_SUPPORTS_SCHED_SMT
>> 2391 default n
1280 help 2392 help
1281 If CNP is enabled on Carmel cores, !! 2393 SMT scheduler support improves the CPU scheduler's decision making
1282 invalidate shared TLB entries insta !! 2394 when dealing with MIPS MT enabled cores at a cost of slightly
1283 on standard ARM cores. !! 2395 increased overhead in some places. If unsure say N here.
1284 <<
1285 If unsure, say Y. <<
1286 2396
1287 config ROCKCHIP_ERRATUM_3588001 !! 2397 config SYS_SUPPORTS_SCHED_SMT
1288 bool "Rockchip 3588001: GIC600 can no !! 2398 bool
1289 default y <<
1290 help <<
1291 The Rockchip RK3588 GIC600 SoC inte <<
1292 This means, that its sharability fe <<
1293 is supported by the IP itself. <<
1294 2399
1295 If unsure, say Y. !! 2400 config SYS_SUPPORTS_MULTITHREADING
>> 2401 bool
1296 2402
1297 config SOCIONEXT_SYNQUACER_PREITS !! 2403 config MIPS_MT_FPAFF
1298 bool "Socionext Synquacer: Workaround !! 2404 bool "Dynamic FPU affinity for FP-intensive threads"
1299 default y 2405 default y
1300 help !! 2406 depends on MIPS_MT_SMP
1301 Socionext Synquacer SoCs implement <<
1302 MSI doorbell writes with non-zero v <<
1303 <<
1304 If unsure, say Y. <<
1305 <<
1306 endmenu # "ARM errata workarounds via the alt <<
1307 2407
1308 choice !! 2408 config MIPSR2_TO_R6_EMULATOR
1309 prompt "Page size" !! 2409 bool "MIPS R2-to-R6 emulator"
1310 default ARM64_4K_PAGES !! 2410 depends on CPU_MIPSR6
>> 2411 depends on MIPS_FP_SUPPORT
>> 2412 default y
1311 help 2413 help
1312 Page size (translation granule) con !! 2414 Choose this option if you want to run non-R6 MIPS userland code.
>> 2415 Even if you say 'Y' here, the emulator will still be disabled by
>> 2416 default. You can enable it using the 'mipsr2emu' kernel option.
>> 2417 The only reason this is a build-time option is to save ~14K from the
>> 2418 final kernel image.
1313 2419
1314 config ARM64_4K_PAGES !! 2420 config SYS_SUPPORTS_VPE_LOADER
1315 bool "4KB" !! 2421 bool
1316 select HAVE_PAGE_SIZE_4KB !! 2422 depends on SYS_SUPPORTS_MULTITHREADING
1317 help 2423 help
1318 This feature enables 4KB pages supp !! 2424 Indicates that the platform supports the VPE loader, and provides
>> 2425 physical_memsize.
1319 2426
1320 config ARM64_16K_PAGES !! 2427 config MIPS_VPE_LOADER
1321 bool "16KB" !! 2428 bool "VPE loader support."
1322 select HAVE_PAGE_SIZE_16KB !! 2429 depends on SYS_SUPPORTS_VPE_LOADER && MODULES
>> 2430 select CPU_MIPSR2_IRQ_VI
>> 2431 select CPU_MIPSR2_IRQ_EI
>> 2432 select MIPS_MT
1323 help 2433 help
1324 The system will use 16KB pages supp !! 2434 Includes a loader for loading an elf relocatable object
1325 requires applications compiled with !! 2435 onto another VPE and running it.
1326 aligned segments. <<
1327 2436
1328 config ARM64_64K_PAGES !! 2437 config MIPS_VPE_LOADER_CMP
1329 bool "64KB" !! 2438 bool
1330 select HAVE_PAGE_SIZE_64KB !! 2439 default "y"
1331 help !! 2440 depends on MIPS_VPE_LOADER && MIPS_CMP
1332 This feature enables 64KB pages sup <<
1333 allowing only two levels of page ta <<
1334 look-up. AArch32 emulation requires <<
1335 with 64K aligned segments. <<
1336 2441
1337 endchoice !! 2442 config MIPS_VPE_LOADER_MT
>> 2443 bool
>> 2444 default "y"
>> 2445 depends on MIPS_VPE_LOADER && !MIPS_CMP
1338 2446
1339 choice !! 2447 config MIPS_VPE_LOADER_TOM
1340 prompt "Virtual address space size" !! 2448 bool "Load VPE program into memory hidden from linux"
1341 default ARM64_VA_BITS_52 !! 2449 depends on MIPS_VPE_LOADER
>> 2450 default y
1342 help 2451 help
1343 Allows choosing one of multiple pos !! 2452 The loader can use memory that is present but has been hidden from
1344 space sizes. The level of translati !! 2453 Linux using the kernel command line option "mem=xxMB". It's up to
1345 a combination of page size and virt !! 2454 you to ensure the amount you put in the option and the space your
1346 !! 2455 program requires is less or equal to the amount physically present.
1347 config ARM64_VA_BITS_36 <<
1348 bool "36-bit" if EXPERT <<
1349 depends on PAGE_SIZE_16KB <<
1350 <<
1351 config ARM64_VA_BITS_39 <<
1352 bool "39-bit" <<
1353 depends on PAGE_SIZE_4KB <<
1354 <<
1355 config ARM64_VA_BITS_42 <<
1356 bool "42-bit" <<
1357 depends on PAGE_SIZE_64KB <<
1358 <<
1359 config ARM64_VA_BITS_47 <<
1360 bool "47-bit" <<
1361 depends on PAGE_SIZE_16KB <<
1362 <<
1363 config ARM64_VA_BITS_48 <<
1364 bool "48-bit" <<
1365 <<
1366 config ARM64_VA_BITS_52 <<
1367 bool "52-bit" <<
1368 depends on ARM64_PAN || !ARM64_SW_TTB <<
1369 help <<
1370 Enable 52-bit virtual addressing fo <<
1371 requested via a hint to mmap(). The <<
1372 virtual addresses for its own mappi <<
1373 this feature is available, otherwis <<
1374 <<
1375 NOTE: Enabling 52-bit virtual addre <<
1376 ARMv8.3 Pointer Authentication will <<
1377 reduced from 7 bits to 3 bits, whic <<
1378 impact on its susceptibility to bru <<
1379 <<
1380 If unsure, select 48-bit virtual ad <<
1381 2456
1382 endchoice !! 2457 config MIPS_VPE_APSP_API
>> 2458 bool "Enable support for AP/SP API (RTLX)"
>> 2459 depends on MIPS_VPE_LOADER
1383 2460
1384 config ARM64_FORCE_52BIT !! 2461 config MIPS_VPE_APSP_API_CMP
1385 bool "Force 52-bit virtual addresses !! 2462 bool
1386 depends on ARM64_VA_BITS_52 && EXPERT !! 2463 default "y"
1387 help !! 2464 depends on MIPS_VPE_APSP_API && MIPS_CMP
1388 For systems with 52-bit userspace V <<
1389 to maintain compatibility with olde <<
1390 unless a hint is supplied to mmap. <<
1391 <<
1392 This configuration option disables <<
1393 forces all userspace addresses to b <<
1394 should only enable this configurati <<
1395 memory management code. If unsure s <<
1396 2465
1397 config ARM64_VA_BITS !! 2466 config MIPS_VPE_APSP_API_MT
1398 int !! 2467 bool
1399 default 36 if ARM64_VA_BITS_36 !! 2468 default "y"
1400 default 39 if ARM64_VA_BITS_39 !! 2469 depends on MIPS_VPE_APSP_API && !MIPS_CMP
1401 default 42 if ARM64_VA_BITS_42 <<
1402 default 47 if ARM64_VA_BITS_47 <<
1403 default 48 if ARM64_VA_BITS_48 <<
1404 default 52 if ARM64_VA_BITS_52 <<
1405 2470
1406 choice !! 2471 config MIPS_CMP
1407 prompt "Physical address space size" !! 2472 bool "MIPS CMP framework support (DEPRECATED)"
1408 default ARM64_PA_BITS_48 !! 2473 depends on SYS_SUPPORTS_MIPS_CMP && !CPU_MIPSR6
>> 2474 select SMP
>> 2475 select SYNC_R4K
>> 2476 select SYS_SUPPORTS_SMP
>> 2477 select WEAK_ORDERING
>> 2478 default n
1409 help 2479 help
1410 Choose the maximum physical address !! 2480 Select this if you are using a bootloader which implements the "CMP
1411 support. !! 2481 framework" protocol (ie. YAMON) and want your kernel to make use of
>> 2482 its ability to start secondary CPUs.
>> 2483
>> 2484 Unless you have a specific need, you should use CONFIG_MIPS_CPS
>> 2485 instead of this.
>> 2486
>> 2487 config MIPS_CPS
>> 2488 bool "MIPS Coherent Processing System support"
>> 2489 depends on SYS_SUPPORTS_MIPS_CPS
>> 2490 select MIPS_CM
>> 2491 select MIPS_CPS_PM if HOTPLUG_CPU
>> 2492 select SMP
>> 2493 select SYNC_R4K if (CEVT_R4K || CSRC_R4K)
>> 2494 select SYS_SUPPORTS_HOTPLUG_CPU
>> 2495 select SYS_SUPPORTS_SCHED_SMT if CPU_MIPSR6
>> 2496 select SYS_SUPPORTS_SMP
>> 2497 select WEAK_ORDERING
>> 2498 select GENERIC_IRQ_MIGRATION if HOTPLUG_CPU
>> 2499 help
>> 2500 Select this if you wish to run an SMP kernel across multiple cores
>> 2501 within a MIPS Coherent Processing System. When this option is
>> 2502 enabled the kernel will probe for other cores and boot them with
>> 2503 no external assistance. It is safe to enable this when hardware
>> 2504 support is unavailable.
1412 2505
1413 config ARM64_PA_BITS_48 !! 2506 config MIPS_CPS_PM
1414 bool "48-bit" !! 2507 depends on MIPS_CPS
1415 depends on ARM64_64K_PAGES || !ARM64_ !! 2508 bool
1416 <<
1417 config ARM64_PA_BITS_52 <<
1418 bool "52-bit" <<
1419 depends on ARM64_64K_PAGES || ARM64_V <<
1420 depends on ARM64_PAN || !ARM64_SW_TTB <<
1421 help <<
1422 Enable support for a 52-bit physica <<
1423 part of the ARMv8.2-LPA extension. <<
1424 <<
1425 With this enabled, the kernel will <<
1426 do not support ARMv8.2-LPA, but wit <<
1427 minor performance overhead). <<
1428 2509
1429 endchoice !! 2510 config MIPS_CM
>> 2511 bool
>> 2512 select MIPS_CPC
1430 2513
1431 config ARM64_PA_BITS !! 2514 config MIPS_CPC
1432 int !! 2515 bool
1433 default 48 if ARM64_PA_BITS_48 <<
1434 default 52 if ARM64_PA_BITS_52 <<
1435 2516
1436 config ARM64_LPA2 !! 2517 config SB1_PASS_2_WORKAROUNDS
1437 def_bool y !! 2518 bool
1438 depends on ARM64_PA_BITS_52 && !ARM64 !! 2519 depends on CPU_SB1 && (CPU_SB1_PASS_2_2 || CPU_SB1_PASS_2)
>> 2520 default y
>> 2521
>> 2522 config SB1_PASS_2_1_WORKAROUNDS
>> 2523 bool
>> 2524 depends on CPU_SB1 && CPU_SB1_PASS_2
>> 2525 default y
1439 2526
1440 choice 2527 choice
1441 prompt "Endianness" !! 2528 prompt "SmartMIPS or microMIPS ASE support"
1442 default CPU_LITTLE_ENDIAN <<
1443 help <<
1444 Select the endianness of data acces <<
1445 applications will need to be compil <<
1446 that is selected here. <<
1447 2529
1448 config CPU_BIG_ENDIAN !! 2530 config CPU_NEEDS_NO_SMARTMIPS_OR_MICROMIPS
1449 bool "Build big-endian kernel" !! 2531 bool "None"
1450 # https://github.com/llvm/llvm-projec <<
1451 depends on AS_IS_GNU || AS_VERSION >= <<
1452 help 2532 help
1453 Say Y if you plan on running a kern !! 2533 Select this if you want neither microMIPS nor SmartMIPS support
1454 2534
1455 config CPU_LITTLE_ENDIAN !! 2535 config CPU_HAS_SMARTMIPS
1456 bool "Build little-endian kernel" !! 2536 depends on SYS_SUPPORTS_SMARTMIPS
>> 2537 bool "SmartMIPS"
>> 2538 help
>> 2539 SmartMIPS is a extension of the MIPS32 architecture aimed at
>> 2540 increased security at both hardware and software level for
>> 2541 smartcards. Enabling this option will allow proper use of the
>> 2542 SmartMIPS instructions by Linux applications. However a kernel with
>> 2543 this option will not work on a MIPS core without SmartMIPS core. If
>> 2544 you don't know you probably don't have SmartMIPS and should say N
>> 2545 here.
>> 2546
>> 2547 config CPU_MICROMIPS
>> 2548 depends on 32BIT && SYS_SUPPORTS_MICROMIPS && !CPU_MIPSR6
>> 2549 bool "microMIPS"
1457 help 2550 help
1458 Say Y if you plan on running a kern !! 2551 When this option is enabled the kernel will be built using the
1459 This is usually the case for distri !! 2552 microMIPS ISA
1460 2553
1461 endchoice 2554 endchoice
1462 2555
1463 config SCHED_MC !! 2556 config CPU_HAS_MSA
1464 bool "Multi-core scheduler support" !! 2557 bool "Support for the MIPS SIMD Architecture"
1465 help !! 2558 depends on CPU_SUPPORTS_MSA
1466 Multi-core scheduler support improv !! 2559 depends on MIPS_FP_SUPPORT
1467 making when dealing with multi-core !! 2560 depends on 64BIT || MIPS_O32_FP64_SUPPORT
1468 increased overhead in some places. !! 2561 help
>> 2562 MIPS SIMD Architecture (MSA) introduces 128 bit wide vector registers
>> 2563 and a set of SIMD instructions to operate on them. When this option
>> 2564 is enabled the kernel will support allocating & switching MSA
>> 2565 vector register contexts. If you know that your kernel will only be
>> 2566 running on CPUs which do not support MSA or that your userland will
>> 2567 not be making use of it then you may wish to say N here to reduce
>> 2568 the size & complexity of your kernel.
1469 2569
1470 config SCHED_CLUSTER !! 2570 If unsure, say Y.
1471 bool "Cluster scheduler support" <<
1472 help <<
1473 Cluster scheduler support improves <<
1474 making when dealing with machines t <<
1475 Cluster usually means a couple of C <<
1476 by sharing mid-level caches, last-l <<
1477 busses. <<
1478 2571
1479 config SCHED_SMT !! 2572 config CPU_HAS_WB
1480 bool "SMT scheduler support" !! 2573 bool
1481 help <<
1482 Improves the CPU scheduler's decisi <<
1483 MultiThreading at a cost of slightl <<
1484 places. If unsure say N here. <<
1485 2574
1486 config NR_CPUS !! 2575 config XKS01
1487 int "Maximum number of CPUs (2-4096)" !! 2576 bool
1488 range 2 4096 <<
1489 default "512" <<
1490 2577
1491 config HOTPLUG_CPU !! 2578 config CPU_HAS_DIEI
1492 bool "Support for hot-pluggable CPUs" !! 2579 depends on !CPU_DIEI_BROKEN
1493 select GENERIC_IRQ_MIGRATION !! 2580 bool
1494 help <<
1495 Say Y here to experiment with turni <<
1496 can be controlled through /sys/devi <<
1497 2581
1498 # Common NUMA Features !! 2582 config CPU_DIEI_BROKEN
1499 config NUMA !! 2583 bool
1500 bool "NUMA Memory Allocation and Sche <<
1501 select GENERIC_ARCH_NUMA <<
1502 select OF_NUMA <<
1503 select HAVE_SETUP_PER_CPU_AREA <<
1504 select NEED_PER_CPU_EMBED_FIRST_CHUNK <<
1505 select NEED_PER_CPU_PAGE_FIRST_CHUNK <<
1506 select USE_PERCPU_NUMA_NODE_ID <<
1507 help <<
1508 Enable NUMA (Non-Uniform Memory Acc <<
1509 <<
1510 The kernel will try to allocate mem <<
1511 local memory of the CPU and add som <<
1512 NUMA awareness to the kernel. <<
1513 2584
1514 config NODES_SHIFT !! 2585 config CPU_HAS_RIXI
1515 int "Maximum NUMA Nodes (as a power o !! 2586 bool
1516 range 1 10 !! 2587
1517 default "4" !! 2588 config CPU_NO_LOAD_STORE_LR
1518 depends on NUMA !! 2589 bool
1519 help 2590 help
1520 Specify the maximum number of NUMA !! 2591 CPU lacks support for unaligned load and store instructions:
1521 system. Increases memory reserved !! 2592 LWL, LWR, SWL, SWR (Load/store word left/right).
>> 2593 LDL, LDR, SDL, SDR (Load/store doubleword left/right, for 64bit
>> 2594 systems).
1522 2595
1523 source "kernel/Kconfig.hz" !! 2596 #
>> 2597 # Vectored interrupt mode is an R2 feature
>> 2598 #
>> 2599 config CPU_MIPSR2_IRQ_VI
>> 2600 bool
1524 2601
1525 config ARCH_SPARSEMEM_ENABLE !! 2602 #
1526 def_bool y !! 2603 # Extended interrupt mode is an R2 feature
1527 select SPARSEMEM_VMEMMAP_ENABLE !! 2604 #
1528 select SPARSEMEM_VMEMMAP !! 2605 config CPU_MIPSR2_IRQ_EI
>> 2606 bool
1529 2607
1530 config HW_PERF_EVENTS !! 2608 config CPU_HAS_SYNC
1531 def_bool y !! 2609 bool
1532 depends on ARM_PMU !! 2610 depends on !CPU_R3000
>> 2611 default y
1533 2612
1534 # Supported by clang >= 7.0 or GCC >= 12.0.0 !! 2613 #
1535 config CC_HAVE_SHADOW_CALL_STACK !! 2614 # CPU non-features
1536 def_bool $(cc-option, -fsanitize=shad !! 2615 #
>> 2616 config CPU_DADDI_WORKAROUNDS
>> 2617 bool
1537 2618
1538 config PARAVIRT !! 2619 config CPU_R4000_WORKAROUNDS
1539 bool "Enable paravirtualization code" !! 2620 bool
1540 help !! 2621 select CPU_R4400_WORKAROUNDS
1541 This changes the kernel so it can m <<
1542 under a hypervisor, potentially imp <<
1543 over full virtualization. <<
1544 2622
1545 config PARAVIRT_TIME_ACCOUNTING !! 2623 config CPU_R4400_WORKAROUNDS
1546 bool "Paravirtual steal time accounti !! 2624 bool
1547 select PARAVIRT <<
1548 help <<
1549 Select this option to enable fine g <<
1550 accounting. Time spent executing ot <<
1551 the current vCPU is discounted from <<
1552 that, there can be a small performa <<
1553 2625
1554 If in doubt, say N here. !! 2626 config CPU_R4X00_BUGS64
>> 2627 bool
>> 2628 default y if SYS_HAS_CPU_R4X00 && 64BIT && (TARGET_ISA_REV < 1)
1555 2629
1556 config ARCH_SUPPORTS_KEXEC !! 2630 config MIPS_ASID_SHIFT
1557 def_bool PM_SLEEP_SMP !! 2631 int
>> 2632 default 6 if CPU_R3000 || CPU_TX39XX
>> 2633 default 0
1558 2634
1559 config ARCH_SUPPORTS_KEXEC_FILE !! 2635 config MIPS_ASID_BITS
1560 def_bool y !! 2636 int
>> 2637 default 0 if MIPS_ASID_BITS_VARIABLE
>> 2638 default 6 if CPU_R3000 || CPU_TX39XX
>> 2639 default 8
1561 2640
1562 config ARCH_SELECTS_KEXEC_FILE !! 2641 config MIPS_ASID_BITS_VARIABLE
1563 def_bool y !! 2642 bool
1564 depends on KEXEC_FILE <<
1565 select HAVE_IMA_KEXEC if IMA <<
1566 2643
1567 config ARCH_SUPPORTS_KEXEC_SIG !! 2644 config MIPS_CRC_SUPPORT
1568 def_bool y !! 2645 bool
1569 2646
1570 config ARCH_SUPPORTS_KEXEC_IMAGE_VERIFY_SIG !! 2647 # R4600 erratum. Due to the lack of errata information the exact
1571 def_bool y !! 2648 # technical details aren't known. I've experimentally found that disabling
>> 2649 # interrupts during indexed I-cache flushes seems to be sufficient to deal
>> 2650 # with the issue.
>> 2651 config WAR_R4600_V1_INDEX_ICACHEOP
>> 2652 bool
1572 2653
1573 config ARCH_DEFAULT_KEXEC_IMAGE_VERIFY_SIG !! 2654 # Pleasures of the R4600 V1.x. Cite from the IDT R4600 V1.7 errata:
1574 def_bool y !! 2655 #
>> 2656 # 18. The CACHE instructions Hit_Writeback_Invalidate_D, Hit_Writeback_D,
>> 2657 # Hit_Invalidate_D and Create_Dirty_Excl_D should only be
>> 2658 # executed if there is no other dcache activity. If the dcache is
>> 2659 # accessed for another instruction immediately preceding when these
>> 2660 # cache instructions are executing, it is possible that the dcache
>> 2661 # tag match outputs used by these cache instructions will be
>> 2662 # incorrect. These cache instructions should be preceded by at least
>> 2663 # four instructions that are not any kind of load or store
>> 2664 # instruction.
>> 2665 #
>> 2666 # This is not allowed: lw
>> 2667 # nop
>> 2668 # nop
>> 2669 # nop
>> 2670 # cache Hit_Writeback_Invalidate_D
>> 2671 #
>> 2672 # This is allowed: lw
>> 2673 # nop
>> 2674 # nop
>> 2675 # nop
>> 2676 # nop
>> 2677 # cache Hit_Writeback_Invalidate_D
>> 2678 config WAR_R4600_V1_HIT_CACHEOP
>> 2679 bool
1575 2680
1576 config ARCH_SUPPORTS_CRASH_DUMP !! 2681 # Writeback and invalidate the primary cache dcache before DMA.
1577 def_bool y !! 2682 #
>> 2683 # R4600 v2.0 bug: "The CACHE instructions Hit_Writeback_Inv_D,
>> 2684 # Hit_Writeback_D, Hit_Invalidate_D and Create_Dirty_Exclusive_D will only
>> 2685 # operate correctly if the internal data cache refill buffer is empty. These
>> 2686 # CACHE instructions should be separated from any potential data cache miss
>> 2687 # by a load instruction to an uncached address to empty the response buffer."
>> 2688 # (Revision 2.0 device errata from IDT available on https://www.idt.com/
>> 2689 # in .pdf format.)
>> 2690 config WAR_R4600_V2_HIT_CACHEOP
>> 2691 bool
1578 2692
1579 config ARCH_HAS_GENERIC_CRASHKERNEL_RESERVATI !! 2693 # From TX49/H2 manual: "If the instruction (i.e. CACHE) is issued for
1580 def_bool CRASH_RESERVE !! 2694 # the line which this instruction itself exists, the following
>> 2695 # operation is not guaranteed."
>> 2696 #
>> 2697 # Workaround: do two phase flushing for Index_Invalidate_I
>> 2698 config WAR_TX49XX_ICACHE_INDEX_INV
>> 2699 bool
1581 2700
1582 config TRANS_TABLE !! 2701 # The RM7000 processors and the E9000 cores have a bug (though PMC-Sierra
1583 def_bool y !! 2702 # opposes it being called that) where invalid instructions in the same
1584 depends on HIBERNATION || KEXEC_CORE !! 2703 # I-cache line worth of instructions being fetched may case spurious
>> 2704 # exceptions.
>> 2705 config WAR_ICACHE_REFILLS
>> 2706 bool
1585 2707
1586 config XEN_DOM0 !! 2708 # On the R10000 up to version 2.6 (not sure about 2.7) there is a bug that
1587 def_bool y !! 2709 # may cause ll / sc and lld / scd sequences to execute non-atomically.
1588 depends on XEN !! 2710 config WAR_R10000_LLSC
>> 2711 bool
1589 2712
1590 config XEN !! 2713 # 34K core erratum: "Problems Executing the TLBR Instruction"
1591 bool "Xen guest support on ARM64" !! 2714 config WAR_MIPS34K_MISSED_ITLB
1592 depends on ARM64 && OF !! 2715 bool
1593 select SWIOTLB_XEN <<
1594 select PARAVIRT <<
1595 help <<
1596 Say Y if you want to run Linux in a <<
1597 2716
1598 # include/linux/mmzone.h requires the followi <<
1599 # <<
1600 # MAX_PAGE_ORDER + PAGE_SHIFT <= SECTION_SI <<
1601 # 2717 #
1602 # so the maximum value of MAX_PAGE_ORDER is S !! 2718 # - Highmem only makes sense for the 32-bit kernel.
>> 2719 # - The current highmem code will only work properly on physically indexed
>> 2720 # caches such as R3000, SB1, R7000 or those that look like they're virtually
>> 2721 # indexed such as R4000/R4400 SC and MC versions or R10000. So for the
>> 2722 # moment we protect the user and offer the highmem option only on machines
>> 2723 # where it's known to be safe. This will not offer highmem on a few systems
>> 2724 # such as MIPS32 and MIPS64 CPUs which may have virtual and physically
>> 2725 # indexed CPUs but we're playing safe.
>> 2726 # - We use SYS_SUPPORTS_HIGHMEM to offer highmem only for systems where we
>> 2727 # know they might have memory configurations that could make use of highmem
>> 2728 # support.
1603 # 2729 #
1604 # | SECTION_SIZE_BITS | PAGE_SHIFT | m !! 2730 config HIGHMEM
1605 # ----+-------------------+--------------+--- !! 2731 bool "High Memory Support"
1606 # 4K | 27 | 12 | !! 2732 depends on 32BIT && CPU_SUPPORTS_HIGHMEM && SYS_SUPPORTS_HIGHMEM && !CPU_MIPS32_3_5_EVA
1607 # 16K | 27 | 14 | !! 2733 select KMAP_LOCAL
1608 # 64K | 29 | 16 | <<
1609 config ARCH_FORCE_MAX_ORDER <<
1610 int <<
1611 default "13" if ARM64_64K_PAGES <<
1612 default "11" if ARM64_16K_PAGES <<
1613 default "10" <<
1614 help <<
1615 The kernel page allocator limits th <<
1616 contiguous allocations. The limit i <<
1617 defines the maximal power of two of <<
1618 allocated as a single contiguous bl <<
1619 overriding the default setting when <<
1620 large blocks of physically contiguo <<
1621 <<
1622 The maximal size of allocation cann <<
1623 section, so the value of MAX_PAGE_O <<
1624 2734
1625 MAX_PAGE_ORDER + PAGE_SHIFT <= SE !! 2735 config CPU_SUPPORTS_HIGHMEM
>> 2736 bool
1626 2737
1627 Don't change if unsure. !! 2738 config SYS_SUPPORTS_HIGHMEM
>> 2739 bool
1628 2740
1629 config UNMAP_KERNEL_AT_EL0 !! 2741 config SYS_SUPPORTS_SMARTMIPS
1630 bool "Unmap kernel when running in us !! 2742 bool
1631 default y <<
1632 help <<
1633 Speculation attacks against some hi <<
1634 be used to bypass MMU permission ch <<
1635 userspace. This can be defended aga <<
1636 when running in userspace, mapping <<
1637 via a trampoline page in the vector <<
1638 2743
1639 If unsure, say Y. !! 2744 config SYS_SUPPORTS_MICROMIPS
>> 2745 bool
1640 2746
1641 config MITIGATE_SPECTRE_BRANCH_HISTORY !! 2747 config SYS_SUPPORTS_MIPS16
1642 bool "Mitigate Spectre style attacks !! 2748 bool
1643 default y <<
1644 help 2749 help
1645 Speculation attacks against some hi !! 2750 This option must be set if a kernel might be executed on a MIPS16-
1646 make use of branch history to influ !! 2751 enabled CPU even if MIPS16 is not actually being used. In other
1647 When taking an exception from user- !! 2752 words, it makes the kernel MIPS16-tolerant.
1648 or a firmware call overwrites the b <<
1649 2753
1650 config RODATA_FULL_DEFAULT_ENABLED !! 2754 config CPU_SUPPORTS_MSA
1651 bool "Apply r/o permissions of VM are !! 2755 bool
1652 default y <<
1653 help <<
1654 Apply read-only attributes of VM ar <<
1655 the backing pages as well. This pre <<
1656 from being modified (inadvertently <<
1657 mapping of the same memory page. Th <<
1658 be turned off at runtime by passing <<
1659 with rodata=full if this option is <<
1660 <<
1661 This requires the linear region to <<
1662 which may adversely affect performa <<
1663 <<
1664 config ARM64_SW_TTBR0_PAN <<
1665 bool "Emulate Privileged Access Never <<
1666 depends on !KCSAN <<
1667 help <<
1668 Enabling this option prevents the k <<
1669 user-space memory directly by point <<
1670 zeroed area and reserved ASID. The <<
1671 restore the valid TTBR0_EL1 tempora <<
1672 2756
1673 config ARM64_TAGGED_ADDR_ABI !! 2757 config ARCH_FLATMEM_ENABLE
1674 bool "Enable the tagged user addresse !! 2758 def_bool y
1675 default y !! 2759 depends on !NUMA && !CPU_LOONGSON2EF
1676 help <<
1677 When this option is enabled, user a <<
1678 relaxed ABI via prctl() allowing ta <<
1679 to system calls as pointer argument <<
1680 Documentation/arch/arm64/tagged-add <<
1681 <<
1682 menuconfig COMPAT <<
1683 bool "Kernel support for 32-bit EL0" <<
1684 depends on ARM64_4K_PAGES || EXPERT <<
1685 select HAVE_UID16 <<
1686 select OLD_SIGSUSPEND3 <<
1687 select COMPAT_OLD_SIGACTION <<
1688 help <<
1689 This option enables support for a 3 <<
1690 kernel at EL1. AArch32-specific com <<
1691 the user helper functions, VFP supp <<
1692 handled appropriately by the kernel <<
1693 <<
1694 If you use a page size other than 4 <<
1695 that you will only be able to execu <<
1696 with page size aligned segments. <<
1697 2760
1698 If you want to execute 32-bit users !! 2761 config ARCH_SPARSEMEM_ENABLE
>> 2762 bool
>> 2763 select SPARSEMEM_STATIC if !SGI_IP27
1699 2764
1700 if COMPAT !! 2765 config NUMA
>> 2766 bool "NUMA Support"
>> 2767 depends on SYS_SUPPORTS_NUMA
>> 2768 select SMP
>> 2769 help
>> 2770 Say Y to compile the kernel to support NUMA (Non-Uniform Memory
>> 2771 Access). This option improves performance on systems with more
>> 2772 than two nodes; on two node systems it is generally better to
>> 2773 leave it disabled; on single node systems leave this option
>> 2774 disabled.
1701 2775
1702 config KUSER_HELPERS !! 2776 config SYS_SUPPORTS_NUMA
1703 bool "Enable kuser helpers page for 3 !! 2777 bool
1704 default y <<
1705 help <<
1706 Warning: disabling this option may <<
1707 2778
1708 Provide kuser helpers to compat tas !! 2779 config HAVE_SETUP_PER_CPU_AREA
1709 helper code to userspace in read on !! 2780 def_bool y
1710 to allow userspace to be independen !! 2781 depends on NUMA
1711 the system. This permits binaries t <<
1712 to ARMv8 without modification. <<
1713 <<
1714 See Documentation/arch/arm/kernel_u <<
1715 <<
1716 However, the fixed address nature o <<
1717 by ROP (return orientated programmi <<
1718 exploits. <<
1719 <<
1720 If all of the binaries and librarie <<
1721 are built specifically for your pla <<
1722 these helpers, then you can turn th <<
1723 such exploits. However, in that cas <<
1724 relying on those helpers is run, it <<
1725 <<
1726 Say N here only if you are absolute <<
1727 need these helpers; otherwise, the <<
1728 <<
1729 config COMPAT_VDSO <<
1730 bool "Enable vDSO for 32-bit applicat <<
1731 depends on !CPU_BIG_ENDIAN <<
1732 depends on (CC_IS_CLANG && LD_IS_LLD) <<
1733 select GENERIC_COMPAT_VDSO <<
1734 default y <<
1735 help <<
1736 Place in the process address space <<
1737 ELF shared object providing fast im <<
1738 and clock_gettime. <<
1739 <<
1740 You must have a 32-bit build of gli <<
1741 to seamlessly take advantage of thi <<
1742 <<
1743 config THUMB2_COMPAT_VDSO <<
1744 bool "Compile the 32-bit vDSO for Thu <<
1745 depends on COMPAT_VDSO <<
1746 default y <<
1747 help <<
1748 Compile the compat vDSO with '-mthu <<
1749 otherwise with '-marm'. <<
1750 2782
1751 config COMPAT_ALIGNMENT_FIXUPS !! 2783 config NEED_PER_CPU_EMBED_FIRST_CHUNK
1752 bool "Fix up misaligned multi-word lo !! 2784 def_bool y
>> 2785 depends on NUMA
1753 2786
1754 menuconfig ARMV8_DEPRECATED !! 2787 config RELOCATABLE
1755 bool "Emulate deprecated/obsolete ARM !! 2788 bool "Relocatable kernel"
1756 depends on SYSCTL !! 2789 depends on SYS_SUPPORTS_RELOCATABLE
1757 help !! 2790 depends on CPU_MIPS32_R2 || CPU_MIPS64_R2 || \
1758 Legacy software support may require !! 2791 CPU_MIPS32_R5 || CPU_MIPS64_R5 || \
1759 that have been deprecated or obsole !! 2792 CPU_MIPS32_R6 || CPU_MIPS64_R6 || \
>> 2793 CPU_P5600 || CAVIUM_OCTEON_SOC || \
>> 2794 CPU_LOONGSON64
>> 2795 help
>> 2796 This builds a kernel image that retains relocation information
>> 2797 so it can be loaded someplace besides the default 1MB.
>> 2798 The relocations make the kernel binary about 15% larger,
>> 2799 but are discarded at runtime
>> 2800
>> 2801 config RELOCATION_TABLE_SIZE
>> 2802 hex "Relocation table size"
>> 2803 depends on RELOCATABLE
>> 2804 range 0x0 0x01000000
>> 2805 default "0x00200000" if CPU_LOONGSON64
>> 2806 default "0x00100000"
>> 2807 help
>> 2808 A table of relocation data will be appended to the kernel binary
>> 2809 and parsed at boot to fix up the relocated kernel.
1760 2810
1761 Enable this config to enable select !! 2811 This option allows the amount of space reserved for the table to be
1762 features. !! 2812 adjusted, although the default of 1Mb should be ok in most cases.
1763 2813
1764 If unsure, say Y !! 2814 The build will fail and a valid size suggested if this is too small.
1765 2815
1766 if ARMV8_DEPRECATED !! 2816 If unsure, leave at the default value.
1767 2817
1768 config SWP_EMULATION !! 2818 config RANDOMIZE_BASE
1769 bool "Emulate SWP/SWPB instructions" !! 2819 bool "Randomize the address of the kernel image"
>> 2820 depends on RELOCATABLE
1770 help 2821 help
1771 ARMv8 obsoletes the use of A32 SWP/ !! 2822 Randomizes the physical and virtual address at which the
1772 they are always undefined. Say Y he !! 2823 kernel image is loaded, as a security feature that
1773 emulation of these instructions for !! 2824 deters exploit attempts relying on knowledge of the location
1774 This feature can be controlled at r !! 2825 of kernel internals.
1775 sysctl which is disabled by default <<
1776 2826
1777 In some older versions of glibc [<= !! 2827 Entropy is generated using any coprocessor 0 registers available.
1778 trylock() operations with the assum <<
1779 be preempted. This invalid assumpti <<
1780 with SWP emulation enabled, leading <<
1781 application. <<
1782 2828
1783 NOTE: when accessing uncached share !! 2829 The kernel will be offset by up to RANDOMIZE_BASE_MAX_OFFSET.
1784 on an external transaction monitori <<
1785 monitor to maintain update atomicit <<
1786 implement a global monitor, this op <<
1787 perform SWP operations to uncached <<
1788 2830
1789 If unsure, say Y !! 2831 If unsure, say N.
1790 2832
1791 config CP15_BARRIER_EMULATION !! 2833 config RANDOMIZE_BASE_MAX_OFFSET
1792 bool "Emulate CP15 Barrier instructio !! 2834 hex "Maximum kASLR offset" if EXPERT
1793 help !! 2835 depends on RANDOMIZE_BASE
1794 The CP15 barrier instructions - CP1 !! 2836 range 0x0 0x40000000 if EVA || 64BIT
1795 CP15DMB - are deprecated in ARMv8 ( !! 2837 range 0x0 0x08000000
1796 strongly recommended to use the ISB !! 2838 default "0x01000000"
1797 instructions instead. !! 2839 help
>> 2840 When kASLR is active, this provides the maximum offset that will
>> 2841 be applied to the kernel image. It should be set according to the
>> 2842 amount of physical RAM available in the target system minus
>> 2843 PHYSICAL_START and must be a power of 2.
1798 2844
1799 Say Y here to enable software emula !! 2845 This is limited by the size of KSEG0, 256Mb on 32-bit or 1Gb with
1800 instructions for AArch32 userspace !! 2846 EVA or 64-bit. The default is 16Mb.
1801 enabled, CP15 barrier usage is trac <<
1802 identify software that needs updati <<
1803 controlled at runtime with the abi. <<
1804 2847
1805 If unsure, say Y !! 2848 config NODES_SHIFT
>> 2849 int
>> 2850 default "6"
>> 2851 depends on NUMA
1806 2852
1807 config SETEND_EMULATION !! 2853 config HW_PERF_EVENTS
1808 bool "Emulate SETEND instruction" !! 2854 bool "Enable hardware performance counter support for perf events"
>> 2855 depends on PERF_EVENTS && (CPU_MIPS32 || CPU_MIPS64 || CPU_R10000 || CPU_SB1 || CPU_CAVIUM_OCTEON || CPU_XLP || CPU_LOONGSON64)
>> 2856 default y
1809 help 2857 help
1810 The SETEND instruction alters the d !! 2858 Enable hardware performance counter support for perf events. If
1811 AArch32 EL0, and is deprecated in A !! 2859 disabled, perf events will use software events only.
1812 2860
1813 Say Y here to enable software emula !! 2861 config DMI
1814 for AArch32 userspace code. This fe !! 2862 bool "Enable DMI scanning"
1815 at runtime with the abi.setend sysc !! 2863 depends on MACH_LOONGSON64
>> 2864 select DMI_SCAN_MACHINE_NON_EFI_FALLBACK
>> 2865 default y
>> 2866 help
>> 2867 Enabled scanning of DMI to identify machine quirks. Say Y
>> 2868 here unless you have verified that your setup is not
>> 2869 affected by entries in the DMI blacklist. Required by PNP
>> 2870 BIOS code.
1816 2871
1817 Note: All the cpus on the system mu !! 2872 config SMP
1818 for this feature to be enabled. If !! 2873 bool "Multi-Processing support"
1819 endian - is hotplugged in after thi !! 2874 depends on SYS_SUPPORTS_SMP
1820 be unexpected results in the applic !! 2875 help
>> 2876 This enables support for systems with more than one CPU. If you have
>> 2877 a system with only one CPU, say N. If you have a system with more
>> 2878 than one CPU, say Y.
>> 2879
>> 2880 If you say N here, the kernel will run on uni- and multiprocessor
>> 2881 machines, but will use only one CPU of a multiprocessor machine. If
>> 2882 you say Y here, the kernel will run on many, but not all,
>> 2883 uniprocessor machines. On a uniprocessor machine, the kernel
>> 2884 will run faster if you say N here.
1821 2885
1822 If unsure, say Y !! 2886 People using multiprocessor machines who say Y here should also say
1823 endif # ARMV8_DEPRECATED !! 2887 Y to "Enhanced Real Time Clock Support", below.
1824 2888
1825 endif # COMPAT !! 2889 See also the SMP-HOWTO available at
>> 2890 <https://www.tldp.org/docs.html#howto>.
1826 2891
1827 menu "ARMv8.1 architectural features" !! 2892 If you don't know what to do here, say N.
1828 2893
1829 config ARM64_HW_AFDBM !! 2894 config HOTPLUG_CPU
1830 bool "Support for hardware updates of !! 2895 bool "Support for hot-pluggable CPUs"
1831 default y !! 2896 depends on SMP && SYS_SUPPORTS_HOTPLUG_CPU
1832 help 2897 help
1833 The ARMv8.1 architecture extensions !! 2898 Say Y here to allow turning CPUs off and on. CPUs can be
1834 hardware updates of the access and !! 2899 controlled through /sys/devices/system/cpu.
1835 table entries. When enabled in TCR_ !! 2900 (Note: power management support will enable this option
1836 capable processors, accesses to pag !! 2901 automatically on SMP systems. )
1837 set this bit instead of raising an !! 2902 Say N if you want to disable CPU hotplug.
1838 Similarly, writes to read-only page <<
1839 clear the read-only bit (AP[2]) ins <<
1840 permission fault. <<
1841 <<
1842 Kernels built with this configurati <<
1843 to work on pre-ARMv8.1 hardware and <<
1844 minimal. If unsure, say Y. <<
1845 2903
1846 config ARM64_PAN !! 2904 config SMP_UP
1847 bool "Enable support for Privileged A !! 2905 bool
1848 default y <<
1849 help <<
1850 Privileged Access Never (PAN; part <<
1851 prevents the kernel or hypervisor f <<
1852 memory directly. <<
1853 2906
1854 Choosing this option will cause any !! 2907 config SYS_SUPPORTS_MIPS_CMP
1855 copy_to_user et al) memory access t !! 2908 bool
1856 2909
1857 The feature is detected at runtime, !! 2910 config SYS_SUPPORTS_MIPS_CPS
1858 instruction if the cpu does not imp !! 2911 bool
1859 2912
1860 config AS_HAS_LSE_ATOMICS !! 2913 config SYS_SUPPORTS_SMP
1861 def_bool $(as-instr,.arch_extension l !! 2914 bool
1862 2915
1863 config ARM64_LSE_ATOMICS !! 2916 config NR_CPUS_DEFAULT_4
1864 bool 2917 bool
1865 default ARM64_USE_LSE_ATOMICS <<
1866 depends on AS_HAS_LSE_ATOMICS <<
1867 2918
1868 config ARM64_USE_LSE_ATOMICS !! 2919 config NR_CPUS_DEFAULT_8
1869 bool "Atomic instructions" !! 2920 bool
1870 default y <<
1871 help <<
1872 As part of the Large System Extensi <<
1873 atomic instructions that are design <<
1874 very large systems. <<
1875 2921
1876 Say Y here to make use of these ins !! 2922 config NR_CPUS_DEFAULT_16
1877 atomic routines. This incurs a smal !! 2923 bool
1878 not support these instructions and <<
1879 built with binutils >= 2.25 in orde <<
1880 to be used. <<
1881 2924
1882 endmenu # "ARMv8.1 architectural features" !! 2925 config NR_CPUS_DEFAULT_32
>> 2926 bool
1883 2927
1884 menu "ARMv8.2 architectural features" !! 2928 config NR_CPUS_DEFAULT_64
>> 2929 bool
1885 2930
1886 config AS_HAS_ARMV8_2 !! 2931 config NR_CPUS
1887 def_bool $(cc-option,-Wa$(comma)-marc !! 2932 int "Maximum number of CPUs (2-256)"
>> 2933 range 2 256
>> 2934 depends on SMP
>> 2935 default "4" if NR_CPUS_DEFAULT_4
>> 2936 default "8" if NR_CPUS_DEFAULT_8
>> 2937 default "16" if NR_CPUS_DEFAULT_16
>> 2938 default "32" if NR_CPUS_DEFAULT_32
>> 2939 default "64" if NR_CPUS_DEFAULT_64
>> 2940 help
>> 2941 This allows you to specify the maximum number of CPUs which this
>> 2942 kernel will support. The maximum supported value is 32 for 32-bit
>> 2943 kernel and 64 for 64-bit kernels; the minimum value which makes
>> 2944 sense is 1 for Qemu (useful only for kernel debugging purposes)
>> 2945 and 2 for all others.
>> 2946
>> 2947 This is purely to save memory - each supported CPU adds
>> 2948 approximately eight kilobytes to the kernel image. For best
>> 2949 performance should round up your number of processors to the next
>> 2950 power of two.
1888 2951
1889 config AS_HAS_SHA3 !! 2952 config MIPS_PERF_SHARED_TC_COUNTERS
1890 def_bool $(as-instr,.arch armv8.2-a+s !! 2953 bool
1891 2954
1892 config ARM64_PMEM !! 2955 config MIPS_NR_CPU_NR_MAP_1024
1893 bool "Enable support for persistent m !! 2956 bool
1894 select ARCH_HAS_PMEM_API <<
1895 select ARCH_HAS_UACCESS_FLUSHCACHE <<
1896 help <<
1897 Say Y to enable support for the per <<
1898 ARMv8.2 DCPoP feature. <<
1899 2957
1900 The feature is detected at runtime, !! 2958 config MIPS_NR_CPU_NR_MAP
1901 operations if DC CVAP is not suppor !! 2959 int
1902 DC CVAP itself if the system does n !! 2960 depends on SMP
>> 2961 default 1024 if MIPS_NR_CPU_NR_MAP_1024
>> 2962 default NR_CPUS if !MIPS_NR_CPU_NR_MAP_1024
1903 2963
1904 config ARM64_RAS_EXTN !! 2964 #
1905 bool "Enable support for RAS CPU Exte !! 2965 # Timer Interrupt Frequency Configuration
1906 default y !! 2966 #
1907 help <<
1908 CPUs that support the Reliability, <<
1909 (RAS) Extensions, part of ARMv8.2 a <<
1910 errors, classify them and report th <<
1911 <<
1912 On CPUs with these extensions syste <<
1913 barriers to determine if faults are <<
1914 classification from a new set of re <<
1915 <<
1916 Selecting this feature will allow t <<
1917 and access the new registers if the <<
1918 Platform RAS features may additiona <<
1919 2967
1920 config ARM64_CNP !! 2968 choice
1921 bool "Enable support for Common Not P !! 2969 prompt "Timer frequency"
1922 default y !! 2970 default HZ_250
1923 depends on ARM64_PAN || !ARM64_SW_TTB <<
1924 help 2971 help
1925 Common Not Private (CNP) allows tra !! 2972 Allows the configuration of the timer frequency.
1926 be shared between different PEs in <<
1927 domain, so the hardware can use thi <<
1928 caching of such entries in the TLB. <<
1929 2973
1930 Selecting this option allows the CN !! 2974 config HZ_24
1931 at runtime, and does not affect PEs !! 2975 bool "24 HZ" if SYS_SUPPORTS_24HZ || SYS_SUPPORTS_ARBIT_HZ
1932 this feature. <<
1933 2976
1934 endmenu # "ARMv8.2 architectural features" !! 2977 config HZ_48
>> 2978 bool "48 HZ" if SYS_SUPPORTS_48HZ || SYS_SUPPORTS_ARBIT_HZ
1935 2979
1936 menu "ARMv8.3 architectural features" !! 2980 config HZ_100
>> 2981 bool "100 HZ" if SYS_SUPPORTS_100HZ || SYS_SUPPORTS_ARBIT_HZ
1937 2982
1938 config ARM64_PTR_AUTH !! 2983 config HZ_128
1939 bool "Enable support for pointer auth !! 2984 bool "128 HZ" if SYS_SUPPORTS_128HZ || SYS_SUPPORTS_ARBIT_HZ
1940 default y <<
1941 help <<
1942 Pointer authentication (part of the <<
1943 instructions for signing and authen <<
1944 keys, which can be used to mitigate <<
1945 and other attacks. <<
1946 <<
1947 This option enables these instructi <<
1948 Choosing this option will cause the <<
1949 for each process at exec() time, wi <<
1950 context-switched along with the pro <<
1951 <<
1952 The feature is detected at runtime. <<
1953 hardware it will not be advertised <<
1954 be enabled. <<
1955 <<
1956 If the feature is present on the bo <<
1957 the late CPU will be parked. Also, <<
1958 address auth and the late CPU has t <<
1959 but with the feature disabled. On s <<
1960 not be selected. <<
1961 2985
1962 config ARM64_PTR_AUTH_KERNEL !! 2986 config HZ_250
1963 bool "Use pointer authentication for !! 2987 bool "250 HZ" if SYS_SUPPORTS_250HZ || SYS_SUPPORTS_ARBIT_HZ
1964 default y <<
1965 depends on ARM64_PTR_AUTH <<
1966 depends on (CC_HAS_SIGN_RETURN_ADDRES <<
1967 # Modern compilers insert a .note.gnu <<
1968 # which is only understood by binutil <<
1969 depends on LD_IS_LLD || LD_VERSION >= <<
1970 depends on !CC_IS_CLANG || AS_HAS_CFI <<
1971 depends on (!FUNCTION_GRAPH_TRACER || <<
1972 help <<
1973 If the compiler supports the -mbran <<
1974 -msign-return-address flag (e.g. GC <<
1975 will cause the kernel itself to be <<
1976 protection. In this case, and if th <<
1977 support pointer authentication, the <<
1978 disabled with minimal loss of prote <<
1979 <<
1980 This feature works with FUNCTION_GR <<
1981 DYNAMIC_FTRACE_WITH_ARGS is enabled <<
1982 <<
1983 config CC_HAS_BRANCH_PROT_PAC_RET <<
1984 # GCC 9 or later, clang 8 or later <<
1985 def_bool $(cc-option,-mbranch-protect <<
1986 <<
1987 config CC_HAS_SIGN_RETURN_ADDRESS <<
1988 # GCC 7, 8 <<
1989 def_bool $(cc-option,-msign-return-ad <<
1990 <<
1991 config AS_HAS_ARMV8_3 <<
1992 def_bool $(cc-option,-Wa$(comma)-marc <<
1993 <<
1994 config AS_HAS_CFI_NEGATE_RA_STATE <<
1995 def_bool $(as-instr,.cfi_startproc\n. <<
1996 <<
1997 config AS_HAS_LDAPR <<
1998 def_bool $(as-instr,.arch_extension r <<
1999 2988
2000 endmenu # "ARMv8.3 architectural features" !! 2989 config HZ_256
>> 2990 bool "256 HZ" if SYS_SUPPORTS_256HZ || SYS_SUPPORTS_ARBIT_HZ
2001 2991
2002 menu "ARMv8.4 architectural features" !! 2992 config HZ_1000
>> 2993 bool "1000 HZ" if SYS_SUPPORTS_1000HZ || SYS_SUPPORTS_ARBIT_HZ
2003 2994
2004 config ARM64_AMU_EXTN !! 2995 config HZ_1024
2005 bool "Enable support for the Activity !! 2996 bool "1024 HZ" if SYS_SUPPORTS_1024HZ || SYS_SUPPORTS_ARBIT_HZ
2006 default y <<
2007 help <<
2008 The activity monitors extension is <<
2009 by the ARMv8.4 CPU architecture. Th <<
2010 of the activity monitors architectu <<
2011 <<
2012 To enable the use of this extension <<
2013 <<
2014 Note that for architectural reasons <<
2015 support when running on CPUs that p <<
2016 extension. The required support is <<
2017 * Version 1.5 and later of the AR <<
2018 <<
2019 For kernels that have this configur <<
2020 firmware, you may need to say N her <<
2021 Otherwise you may experience firmwa <<
2022 accessing the counter registers. Ev <<
2023 symptoms, the values returned by th <<
2024 correctly reflect reality. Most com <<
2025 indicating that the counter is not <<
2026 2997
2027 config AS_HAS_ARMV8_4 !! 2998 endchoice
2028 def_bool $(cc-option,-Wa$(comma)-marc <<
2029 2999
2030 config ARM64_TLB_RANGE !! 3000 config SYS_SUPPORTS_24HZ
2031 bool "Enable support for tlbi range f !! 3001 bool
2032 default y <<
2033 depends on AS_HAS_ARMV8_4 <<
2034 help <<
2035 ARMv8.4-TLBI provides TLBI invalida <<
2036 range of input addresses. <<
2037 3002
2038 The feature introduces new assembly !! 3003 config SYS_SUPPORTS_48HZ
2039 support when binutils >= 2.30. !! 3004 bool
2040 3005
2041 endmenu # "ARMv8.4 architectural features" !! 3006 config SYS_SUPPORTS_100HZ
>> 3007 bool
2042 3008
2043 menu "ARMv8.5 architectural features" !! 3009 config SYS_SUPPORTS_128HZ
>> 3010 bool
2044 3011
2045 config AS_HAS_ARMV8_5 !! 3012 config SYS_SUPPORTS_250HZ
2046 def_bool $(cc-option,-Wa$(comma)-marc !! 3013 bool
2047 3014
2048 config ARM64_BTI !! 3015 config SYS_SUPPORTS_256HZ
2049 bool "Branch Target Identification su !! 3016 bool
2050 default y <<
2051 help <<
2052 Branch Target Identification (part <<
2053 provides a mechanism to limit the s <<
2054 branch instructions such as BR or B <<
2055 <<
2056 To make use of BTI on CPUs that sup <<
2057 <<
2058 BTI is intended to provide compleme <<
2059 flow integrity protection mechanism <<
2060 authentication mechanism provided a <<
2061 For this reason, it does not make s <<
2062 also enabling support for pointer a <<
2063 enabling this option you should als <<
2064 <<
2065 Userspace binaries must also be spe <<
2066 this mechanism. If you say N here <<
2067 BTI, such binaries can still run, b <<
2068 enforcement of branch destinations. <<
2069 3017
2070 config ARM64_BTI_KERNEL !! 3018 config SYS_SUPPORTS_1000HZ
2071 bool "Use Branch Target Identificatio !! 3019 bool
2072 default y <<
2073 depends on ARM64_BTI <<
2074 depends on ARM64_PTR_AUTH_KERNEL <<
2075 depends on CC_HAS_BRANCH_PROT_PAC_RET <<
2076 # https://gcc.gnu.org/bugzilla/show_b <<
2077 depends on !CC_IS_GCC || GCC_VERSION <<
2078 # https://gcc.gnu.org/bugzilla/show_b <<
2079 depends on !CC_IS_GCC <<
2080 depends on (!FUNCTION_GRAPH_TRACER || <<
2081 help <<
2082 Build the kernel with Branch Target <<
2083 and enable enforcement of this for <<
2084 is enabled and the system supports <<
2085 modular code must have BTI enabled. <<
2086 <<
2087 config CC_HAS_BRANCH_PROT_PAC_RET_BTI <<
2088 # GCC 9 or later, clang 8 or later <<
2089 def_bool $(cc-option,-mbranch-protect <<
2090 3020
2091 config ARM64_E0PD !! 3021 config SYS_SUPPORTS_1024HZ
2092 bool "Enable support for E0PD" !! 3022 bool
2093 default y <<
2094 help <<
2095 E0PD (part of the ARMv8.5 extension <<
2096 that EL0 accesses made via TTBR1 al <<
2097 providing similar benefits to KASLR <<
2098 with lower overhead and without dis <<
2099 kernel memory such as SPE. <<
2100 <<
2101 This option enables E0PD for TTBR1 <<
2102 <<
2103 config ARM64_AS_HAS_MTE <<
2104 # Initial support for MTE went in bin <<
2105 # ".arch armv8.5-a+memtag" below. How <<
2106 # as a late addition to the final arc <<
2107 # is only supported in the newer 2.32 <<
2108 # versions, hence the extra "stgm" in <<
2109 def_bool $(as-instr,.arch armv8.5-a+m <<
2110 3023
2111 config ARM64_MTE !! 3024 config SYS_SUPPORTS_ARBIT_HZ
2112 bool "Memory Tagging Extension suppor !! 3025 bool
2113 default y !! 3026 default y if !SYS_SUPPORTS_24HZ && \
2114 depends on ARM64_AS_HAS_MTE && ARM64_ !! 3027 !SYS_SUPPORTS_48HZ && \
2115 depends on AS_HAS_ARMV8_5 !! 3028 !SYS_SUPPORTS_100HZ && \
2116 depends on AS_HAS_LSE_ATOMICS !! 3029 !SYS_SUPPORTS_128HZ && \
2117 # Required for tag checking in the ua !! 3030 !SYS_SUPPORTS_250HZ && \
2118 depends on ARM64_PAN !! 3031 !SYS_SUPPORTS_256HZ && \
2119 select ARCH_HAS_SUBPAGE_FAULTS !! 3032 !SYS_SUPPORTS_1000HZ && \
2120 select ARCH_USES_HIGH_VMA_FLAGS !! 3033 !SYS_SUPPORTS_1024HZ
2121 select ARCH_USES_PG_ARCH_2 <<
2122 select ARCH_USES_PG_ARCH_3 <<
2123 help <<
2124 Memory Tagging (part of the ARMv8.5 <<
2125 architectural support for run-time, <<
2126 various classes of memory error to <<
2127 to eliminate vulnerabilities arisin <<
2128 languages. <<
2129 <<
2130 This option enables the support for <<
2131 Extension at EL0 (i.e. for userspac <<
2132 <<
2133 Selecting this option allows the fe <<
2134 runtime. Any secondary CPU not impl <<
2135 not be allowed a late bring-up. <<
2136 <<
2137 Userspace binaries that want to use <<
2138 explicitly opt in. The mechanism fo <<
2139 described in: <<
2140 3034
2141 Documentation/arch/arm64/memory-tag !! 3035 config HZ
>> 3036 int
>> 3037 default 24 if HZ_24
>> 3038 default 48 if HZ_48
>> 3039 default 100 if HZ_100
>> 3040 default 128 if HZ_128
>> 3041 default 250 if HZ_250
>> 3042 default 256 if HZ_256
>> 3043 default 1000 if HZ_1000
>> 3044 default 1024 if HZ_1024
>> 3045
>> 3046 config SCHED_HRTICK
>> 3047 def_bool HIGH_RES_TIMERS
>> 3048
>> 3049 config KEXEC
>> 3050 bool "Kexec system call"
>> 3051 select KEXEC_CORE
>> 3052 help
>> 3053 kexec is a system call that implements the ability to shutdown your
>> 3054 current kernel, and to start another kernel. It is like a reboot
>> 3055 but it is independent of the system firmware. And like a reboot
>> 3056 you can start any kernel with it, not just Linux.
>> 3057
>> 3058 The name comes from the similarity to the exec system call.
>> 3059
>> 3060 It is an ongoing process to be certain the hardware in a machine
>> 3061 is properly shutdown, so do not be surprised if this code does not
>> 3062 initially work for you. As of this writing the exact hardware
>> 3063 interface is strongly in flux, so no good recommendation can be
>> 3064 made.
>> 3065
>> 3066 config CRASH_DUMP
>> 3067 bool "Kernel crash dumps"
>> 3068 help
>> 3069 Generate crash dump after being started by kexec.
>> 3070 This should be normally only set in special crash dump kernels
>> 3071 which are loaded in the main kernel with kexec-tools into
>> 3072 a specially reserved region and then later executed after
>> 3073 a crash by kdump/kexec. The crash dump kernel must be compiled
>> 3074 to a memory address not used by the main kernel or firmware using
>> 3075 PHYSICAL_START.
>> 3076
>> 3077 config PHYSICAL_START
>> 3078 hex "Physical address where the kernel is loaded"
>> 3079 default "0xffffffff84000000"
>> 3080 depends on CRASH_DUMP
>> 3081 help
>> 3082 This gives the CKSEG0 or KSEG0 address where the kernel is loaded.
>> 3083 If you plan to use kernel for capturing the crash dump change
>> 3084 this value to start of the reserved region (the "X" value as
>> 3085 specified in the "crashkernel=YM@XM" command line boot parameter
>> 3086 passed to the panic-ed kernel).
>> 3087
>> 3088 config MIPS_O32_FP64_SUPPORT
>> 3089 bool "Support for O32 binaries using 64-bit FP" if !CPU_MIPSR6
>> 3090 depends on 32BIT || MIPS32_O32
>> 3091 help
>> 3092 When this is enabled, the kernel will support use of 64-bit floating
>> 3093 point registers with binaries using the O32 ABI along with the
>> 3094 EF_MIPS_FP64 ELF header flag (typically built with -mfp64). On
>> 3095 32-bit MIPS systems this support is at the cost of increasing the
>> 3096 size and complexity of the compiled FPU emulator. Thus if you are
>> 3097 running a MIPS32 system and know that none of your userland binaries
>> 3098 will require 64-bit floating point, you may wish to reduce the size
>> 3099 of your kernel & potentially improve FP emulation performance by
>> 3100 saying N here.
>> 3101
>> 3102 Although binutils currently supports use of this flag the details
>> 3103 concerning its effect upon the O32 ABI in userland are still being
>> 3104 worked on. In order to avoid userland becoming dependent upon current
>> 3105 behaviour before the details have been finalised, this option should
>> 3106 be considered experimental and only enabled by those working upon
>> 3107 said details.
2142 3108
2143 endmenu # "ARMv8.5 architectural features" !! 3109 If unsure, say N.
2144 3110
2145 menu "ARMv8.7 architectural features" !! 3111 config USE_OF
>> 3112 bool
>> 3113 select OF
>> 3114 select OF_EARLY_FLATTREE
>> 3115 select IRQ_DOMAIN
2146 3116
2147 config ARM64_EPAN !! 3117 config UHI_BOOT
2148 bool "Enable support for Enhanced Pri !! 3118 bool
2149 default y <<
2150 depends on ARM64_PAN <<
2151 help <<
2152 Enhanced Privileged Access Never (E <<
2153 Access Never to be used with Execut <<
2154 3119
2155 The feature is detected at runtime, !! 3120 config BUILTIN_DTB
2156 if the cpu does not implement the f !! 3121 bool
2157 endmenu # "ARMv8.7 architectural features" <<
2158 3122
2159 menu "ARMv8.9 architectural features" !! 3123 choice
>> 3124 prompt "Kernel appended dtb support" if USE_OF
>> 3125 default MIPS_NO_APPENDED_DTB
2160 3126
2161 config ARM64_POE !! 3127 config MIPS_NO_APPENDED_DTB
2162 prompt "Permission Overlay Extension" !! 3128 bool "None"
2163 def_bool y !! 3129 help
2164 select ARCH_USES_HIGH_VMA_FLAGS !! 3130 Do not enable appended dtb support.
2165 select ARCH_HAS_PKEYS !! 3131
2166 help !! 3132 config MIPS_ELF_APPENDED_DTB
2167 The Permission Overlay Extension is !! 3133 bool "vmlinux"
2168 Protection Keys. Memory Protection !! 3134 help
2169 enforcing page-based protections, b !! 3135 With this option, the boot code will look for a device tree binary
2170 of the page tables when an applicat !! 3136 DTB) included in the vmlinux ELF section .appended_dtb. By default
>> 3137 it is empty and the DTB can be appended using binutils command
>> 3138 objcopy:
>> 3139
>> 3140 objcopy --update-section .appended_dtb=<filename>.dtb vmlinux
>> 3141
>> 3142 This is meant as a backward compatibility convenience for those
>> 3143 systems with a bootloader that can't be upgraded to accommodate
>> 3144 the documented boot protocol using a device tree.
>> 3145
>> 3146 config MIPS_RAW_APPENDED_DTB
>> 3147 bool "vmlinux.bin or vmlinuz.bin"
>> 3148 help
>> 3149 With this option, the boot code will look for a device tree binary
>> 3150 DTB) appended to raw vmlinux.bin or vmlinuz.bin.
>> 3151 (e.g. cat vmlinux.bin <filename>.dtb > vmlinux_w_dtb).
>> 3152
>> 3153 This is meant as a backward compatibility convenience for those
>> 3154 systems with a bootloader that can't be upgraded to accommodate
>> 3155 the documented boot protocol using a device tree.
>> 3156
>> 3157 Beware that there is very little in terms of protection against
>> 3158 this option being confused by leftover garbage in memory that might
>> 3159 look like a DTB header after a reboot if no actual DTB is appended
>> 3160 to vmlinux.bin. Do not leave this option active in a production kernel
>> 3161 if you don't intend to always append a DTB.
>> 3162 endchoice
2171 3163
2172 For details, see Documentation/core !! 3164 choice
>> 3165 prompt "Kernel command line type" if !CMDLINE_OVERRIDE
>> 3166 default MIPS_CMDLINE_FROM_DTB if USE_OF && !ATH79 && !MACH_INGENIC && \
>> 3167 !MACH_LOONGSON64 && !MIPS_MALTA && \
>> 3168 !CAVIUM_OCTEON_SOC
>> 3169 default MIPS_CMDLINE_FROM_BOOTLOADER
>> 3170
>> 3171 config MIPS_CMDLINE_FROM_DTB
>> 3172 depends on USE_OF
>> 3173 bool "Dtb kernel arguments if available"
>> 3174
>> 3175 config MIPS_CMDLINE_DTB_EXTEND
>> 3176 depends on USE_OF
>> 3177 bool "Extend dtb kernel arguments with bootloader arguments"
>> 3178
>> 3179 config MIPS_CMDLINE_FROM_BOOTLOADER
>> 3180 bool "Bootloader kernel arguments if available"
>> 3181
>> 3182 config MIPS_CMDLINE_BUILTIN_EXTEND
>> 3183 depends on CMDLINE_BOOL
>> 3184 bool "Extend builtin kernel arguments with bootloader arguments"
>> 3185 endchoice
2173 3186
2174 If unsure, say y. !! 3187 endmenu
>> 3188
>> 3189 config LOCKDEP_SUPPORT
>> 3190 bool
>> 3191 default y
>> 3192
>> 3193 config STACKTRACE_SUPPORT
>> 3194 bool
>> 3195 default y
2175 3196
2176 config ARCH_PKEY_BITS !! 3197 config PGTABLE_LEVELS
2177 int 3198 int
2178 default 3 !! 3199 default 4 if PAGE_SIZE_4KB && MIPS_VA_BITS_48
>> 3200 default 3 if 64BIT && (!PAGE_SIZE_64KB || MIPS_VA_BITS_48)
>> 3201 default 2
2179 3202
2180 endmenu # "ARMv8.9 architectural features" !! 3203 config MIPS_AUTO_PFN_OFFSET
>> 3204 bool
2181 3205
2182 config ARM64_SVE !! 3206 menu "Bus options (PCI, PCMCIA, EISA, ISA, TC)"
2183 bool "ARM Scalable Vector Extension s <<
2184 default y <<
2185 help <<
2186 The Scalable Vector Extension (SVE) <<
2187 execution state which complements a <<
2188 of the base architecture to support <<
2189 additional vectorisation opportunit <<
2190 <<
2191 To enable use of this extension on <<
2192 <<
2193 On CPUs that support the SVE2 exten <<
2194 those too. <<
2195 <<
2196 Note that for architectural reasons <<
2197 support when running on SVE capable <<
2198 is present in: <<
2199 <<
2200 * version 1.5 and later of the AR <<
2201 * the AArch64 boot wrapper since <<
2202 ("bootwrapper: SVE: Enable SVE <<
2203 <<
2204 For other firmware implementations, <<
2205 or vendor. <<
2206 <<
2207 If you need the kernel to boot on S <<
2208 firmware, you may need to say N her <<
2209 fixed. Otherwise, you may experien <<
2210 booting the kernel. If unsure and <<
2211 symptoms, you should assume that it <<
2212 3207
2213 config ARM64_SME !! 3208 config PCI_DRIVERS_GENERIC
2214 bool "ARM Scalable Matrix Extension s !! 3209 select PCI_DOMAINS_GENERIC if PCI
2215 default y !! 3210 bool
2216 depends on ARM64_SVE <<
2217 depends on BROKEN <<
2218 help <<
2219 The Scalable Matrix Extension (SME) <<
2220 execution state which utilises a su <<
2221 instruction set, together with the <<
2222 register state capable of holding t <<
2223 enable various matrix operations. <<
2224 <<
2225 config ARM64_PSEUDO_NMI <<
2226 bool "Support for NMI-like interrupts <<
2227 select ARM_GIC_V3 <<
2228 help <<
2229 Adds support for mimicking Non-Mask <<
2230 GIC interrupt priority. This suppor <<
2231 ARM GIC. <<
2232 <<
2233 This high priority configuration fo <<
2234 explicitly enabled by setting the k <<
2235 "irqchip.gicv3_pseudo_nmi" to 1. <<
2236 <<
2237 If unsure, say N <<
2238 <<
2239 if ARM64_PSEUDO_NMI <<
2240 config ARM64_DEBUG_PRIORITY_MASKING <<
2241 bool "Debug interrupt priority maskin <<
2242 help <<
2243 This adds runtime checks to functio <<
2244 interrupts when using priority mask <<
2245 the validity of ICC_PMR_EL1 when ca <<
2246 3211
2247 If unsure, say N !! 3212 config PCI_DRIVERS_LEGACY
2248 endif # ARM64_PSEUDO_NMI !! 3213 def_bool !PCI_DRIVERS_GENERIC
>> 3214 select NO_GENERIC_PCI_IOPORT_MAP
>> 3215 select PCI_DOMAINS if PCI
2249 3216
2250 config RELOCATABLE !! 3217 #
2251 bool "Build a relocatable kernel imag !! 3218 # ISA support is now enabled via select. Too many systems still have the one
2252 select ARCH_HAS_RELR !! 3219 # or other ISA chip on the board that users don't know about so don't expect
>> 3220 # users to choose the right thing ...
>> 3221 #
>> 3222 config ISA
>> 3223 bool
>> 3224
>> 3225 config TC
>> 3226 bool "TURBOchannel support"
>> 3227 depends on MACH_DECSTATION
>> 3228 help
>> 3229 TURBOchannel is a DEC (now Compaq (now HP)) bus for Alpha and MIPS
>> 3230 processors. TURBOchannel programming specifications are available
>> 3231 at:
>> 3232 <ftp://ftp.hp.com/pub/alphaserver/archive/triadd/>
>> 3233 and:
>> 3234 <http://www.computer-refuge.org/classiccmp/ftp.digital.com/pub/DEC/TriAdd/>
>> 3235 Linux driver support status is documented at:
>> 3236 <http://www.linux-mips.org/wiki/DECstation>
>> 3237
>> 3238 config MMU
>> 3239 bool
2253 default y 3240 default y
2254 help <<
2255 This builds the kernel as a Positio <<
2256 which retains all relocation metada <<
2257 kernel binary at runtime to a diffe <<
2258 address it was linked at. <<
2259 Since AArch64 uses the RELA relocat <<
2260 relocation pass at runtime even if <<
2261 same address it was linked at. <<
2262 3241
2263 config RANDOMIZE_BASE !! 3242 config ARCH_MMAP_RND_BITS_MIN
2264 bool "Randomize the address of the ke !! 3243 default 12 if 64BIT
2265 select RELOCATABLE !! 3244 default 8
2266 help <<
2267 Randomizes the virtual address at w <<
2268 loaded, as a security feature that <<
2269 relying on knowledge of the locatio <<
2270 <<
2271 It is the bootloader's job to provi <<
2272 random u64 value in /chosen/kaslr-s <<
2273 <<
2274 When booting via the UEFI stub, it <<
2275 EFI_RNG_PROTOCOL implementation (if <<
2276 to the kernel proper. In addition, <<
2277 location of the kernel Image as wel <<
2278 3245
2279 If unsure, say N. !! 3246 config ARCH_MMAP_RND_BITS_MAX
>> 3247 default 18 if 64BIT
>> 3248 default 15
2280 3249
2281 config RANDOMIZE_MODULE_REGION_FULL !! 3250 config ARCH_MMAP_RND_COMPAT_BITS_MIN
2282 bool "Randomize the module region ove !! 3251 default 8
2283 depends on RANDOMIZE_BASE <<
2284 default y <<
2285 help <<
2286 Randomizes the location of the modu <<
2287 covering the core kernel. This way, <<
2288 to leak information about the locat <<
2289 but it does imply that function cal <<
2290 kernel will need to be resolved via <<
2291 <<
2292 When this option is not set, the mo <<
2293 a limited range that contains the [ <<
2294 core kernel, so branch relocations <<
2295 the region is exhausted. In this pa <<
2296 exhaustion, modules might be able t <<
2297 3252
2298 config CC_HAVE_STACKPROTECTOR_SYSREG !! 3253 config ARCH_MMAP_RND_COMPAT_BITS_MAX
2299 def_bool $(cc-option,-mstack-protecto !! 3254 default 15
2300 3255
2301 config STACKPROTECTOR_PER_TASK !! 3256 config I8253
2302 def_bool y !! 3257 bool
2303 depends on STACKPROTECTOR && CC_HAVE_ !! 3258 select CLKSRC_I8253
>> 3259 select CLKEVT_I8253
>> 3260 select MIPS_EXTERNAL_TIMER
>> 3261 endmenu
2304 3262
2305 config UNWIND_PATCH_PAC_INTO_SCS !! 3263 config TRAD_SIGNALS
2306 bool "Enable shadow call stack dynami !! 3264 bool
2307 # needs Clang with https://github.com <<
2308 depends on CC_IS_CLANG && CLANG_VERSI <<
2309 depends on ARM64_PTR_AUTH_KERNEL && C <<
2310 depends on SHADOW_CALL_STACK <<
2311 select UNWIND_TABLES <<
2312 select DYNAMIC_SCS <<
2313 <<
2314 config ARM64_CONTPTE <<
2315 bool "Contiguous PTE mappings for use <<
2316 depends on TRANSPARENT_HUGEPAGE <<
2317 default y <<
2318 help <<
2319 When enabled, user mappings are con <<
2320 bit, for any mappings that meet the <<
2321 This reduces TLB pressure and impro <<
2322 <<
2323 endmenu # "Kernel Features" <<
2324 <<
2325 menu "Boot options" <<
2326 <<
2327 config ARM64_ACPI_PARKING_PROTOCOL <<
2328 bool "Enable support for the ARM64 AC <<
2329 depends on ACPI <<
2330 help <<
2331 Enable support for the ARM64 ACPI p <<
2332 the kernel will not allow booting t <<
2333 protocol even if the corresponding <<
2334 MADT table. <<
2335 <<
2336 config CMDLINE <<
2337 string "Default kernel command string <<
2338 default "" <<
2339 help <<
2340 Provide a set of default command-li <<
2341 entering them here. As a minimum, y <<
2342 root device (e.g. root=/dev/nfs). <<
2343 3265
2344 choice !! 3266 config MIPS32_COMPAT
2345 prompt "Kernel command line type" !! 3267 bool
2346 depends on CMDLINE != "" <<
2347 default CMDLINE_FROM_BOOTLOADER <<
2348 help <<
2349 Choose how the kernel will handle t <<
2350 command line string. <<
2351 <<
2352 config CMDLINE_FROM_BOOTLOADER <<
2353 bool "Use bootloader kernel arguments <<
2354 help <<
2355 Uses the command-line options passe <<
2356 the boot loader doesn't provide any <<
2357 string provided in CMDLINE will be <<
2358 <<
2359 config CMDLINE_FORCE <<
2360 bool "Always use the default kernel c <<
2361 help <<
2362 Always use the default kernel comma <<
2363 loader passes other arguments to th <<
2364 This is useful if you cannot or don <<
2365 command-line options your boot load <<
2366 3268
2367 endchoice !! 3269 config COMPAT
>> 3270 bool
2368 3271
2369 config EFI_STUB !! 3272 config SYSVIPC_COMPAT
2370 bool 3273 bool
2371 3274
2372 config EFI !! 3275 config MIPS32_O32
2373 bool "UEFI runtime support" !! 3276 bool "Kernel support for o32 binaries"
2374 depends on OF && !CPU_BIG_ENDIAN !! 3277 depends on 64BIT
2375 depends on KERNEL_MODE_NEON !! 3278 select ARCH_WANT_OLD_COMPAT_IPC
2376 select ARCH_SUPPORTS_ACPI !! 3279 select COMPAT
2377 select LIBFDT !! 3280 select MIPS32_COMPAT
2378 select UCS2_STRING !! 3281 select SYSVIPC_COMPAT if SYSVIPC
2379 select EFI_PARAMS_FROM_FDT !! 3282 help
2380 select EFI_RUNTIME_WRAPPERS !! 3283 Select this option if you want to run o32 binaries. These are pure
2381 select EFI_STUB !! 3284 32-bit binaries as used by the 32-bit Linux/MIPS port. Most of
2382 select EFI_GENERIC_STUB !! 3285 existing binaries are in this format.
2383 imply IMA_SECURE_AND_OR_TRUSTED_BOOT <<
2384 default y <<
2385 help <<
2386 This option provides support for ru <<
2387 by UEFI firmware (such as non-volat <<
2388 clock, and platform reset). A UEFI <<
2389 allow the kernel to be booted as an <<
2390 is only useful on systems that have <<
2391 <<
2392 config COMPRESSED_INSTALL <<
2393 bool "Install compressed image by def <<
2394 help <<
2395 This makes the regular "make instal <<
2396 image we built, not the legacy unco <<
2397 <<
2398 You can check that a compressed ima <<
2399 "make zinstall" first, and verifyin <<
2400 in your environment before making " <<
2401 you. <<
2402 3286
2403 config DMI !! 3287 If unsure, say Y.
2404 bool "Enable support for SMBIOS (DMI) <<
2405 depends on EFI <<
2406 default y <<
2407 help <<
2408 This enables SMBIOS/DMI feature for <<
2409 3288
2410 This option is only useful on syste !! 3289 config MIPS32_N32
2411 However, even with this option, the !! 3290 bool "Kernel support for n32 binaries"
2412 continue to boot on existing non-UE !! 3291 depends on 64BIT
>> 3292 select ARCH_WANT_COMPAT_IPC_PARSE_VERSION
>> 3293 select COMPAT
>> 3294 select MIPS32_COMPAT
>> 3295 select SYSVIPC_COMPAT if SYSVIPC
>> 3296 help
>> 3297 Select this option if you want to run n32 binaries. These are
>> 3298 64-bit binaries using 32-bit quantities for addressing and certain
>> 3299 data that would normally be 64-bit. They are used in special
>> 3300 cases.
2413 3301
2414 endmenu # "Boot options" !! 3302 If unsure, say N.
2415 3303
2416 menu "Power management options" 3304 menu "Power management options"
2417 3305
2418 source "kernel/power/Kconfig" <<
2419 <<
2420 config ARCH_HIBERNATION_POSSIBLE 3306 config ARCH_HIBERNATION_POSSIBLE
2421 def_bool y 3307 def_bool y
2422 depends on CPU_PM !! 3308 depends on SYS_SUPPORTS_HOTPLUG_CPU || !SMP
2423 <<
2424 config ARCH_HIBERNATION_HEADER <<
2425 def_bool y <<
2426 depends on HIBERNATION <<
2427 3309
2428 config ARCH_SUSPEND_POSSIBLE 3310 config ARCH_SUSPEND_POSSIBLE
2429 def_bool y 3311 def_bool y
>> 3312 depends on SYS_SUPPORTS_HOTPLUG_CPU || !SMP
2430 3313
2431 endmenu # "Power management options" !! 3314 source "kernel/power/Kconfig"
2432 3315
2433 menu "CPU Power Management" !! 3316 endmenu
2434 3317
2435 source "drivers/cpuidle/Kconfig" !! 3318 config MIPS_EXTERNAL_TIMER
>> 3319 bool
2436 3320
>> 3321 menu "CPU Power Management"
>> 3322
>> 3323 if CPU_SUPPORTS_CPUFREQ && MIPS_EXTERNAL_TIMER
2437 source "drivers/cpufreq/Kconfig" 3324 source "drivers/cpufreq/Kconfig"
>> 3325 endif
2438 3326
2439 endmenu # "CPU Power Management" !! 3327 source "drivers/cpuidle/Kconfig"
2440 3328
2441 source "drivers/acpi/Kconfig" !! 3329 endmenu
2442 3330
2443 source "arch/arm64/kvm/Kconfig" !! 3331 source "arch/mips/kvm/Kconfig"
2444 3332
>> 3333 source "arch/mips/vdso/Kconfig"
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