1 # SPDX-License-Identifier: GPL-2.0-only !! 1 # SPDX-License-Identifier: GPL-2.0
2 config ARM64 !! 2 config MIPS
3 def_bool y !! 3 bool
4 select ACPI_APMT if ACPI !! 4 default y
5 select ACPI_CCA_REQUIRED if ACPI !! 5 select ARCH_32BIT_OFF_T if !64BIT
6 select ACPI_GENERIC_GSI if ACPI !! 6 select ARCH_BINFMT_ELF_STATE if MIPS_FP_SUPPORT
7 select ACPI_GTDT if ACPI !! 7 select ARCH_HAS_CURRENT_STACK_POINTER if !CC_IS_CLANG || CLANG_VERSION >= 140000
8 select ACPI_HOTPLUG_CPU if ACPI_PROCES !! 8 select ARCH_HAS_DEBUG_VIRTUAL if !64BIT
9 select ACPI_IORT if ACPI <<
10 select ACPI_REDUCED_HARDWARE_ONLY if A <<
11 select ACPI_MCFG if (ACPI && PCI) <<
12 select ACPI_SPCR_TABLE if ACPI <<
13 select ACPI_PPTT if ACPI <<
14 select ARCH_HAS_DEBUG_WX <<
15 select ARCH_BINFMT_ELF_EXTRA_PHDRS <<
16 select ARCH_BINFMT_ELF_STATE <<
17 select ARCH_CORRECT_STACKTRACE_ON_KRET <<
18 select ARCH_ENABLE_HUGEPAGE_MIGRATION <<
19 select ARCH_ENABLE_MEMORY_HOTPLUG <<
20 select ARCH_ENABLE_MEMORY_HOTREMOVE <<
21 select ARCH_ENABLE_SPLIT_PMD_PTLOCK if <<
22 select ARCH_ENABLE_THP_MIGRATION if TR <<
23 select ARCH_HAS_CACHE_LINE_SIZE <<
24 select ARCH_HAS_CURRENT_STACK_POINTER <<
25 select ARCH_HAS_DEBUG_VIRTUAL <<
26 select ARCH_HAS_DEBUG_VM_PGTABLE <<
27 select ARCH_HAS_DMA_OPS if XEN <<
28 select ARCH_HAS_DMA_PREP_COHERENT <<
29 select ARCH_HAS_ACPI_TABLE_UPGRADE if <<
30 select ARCH_HAS_FAST_MULTIPLIER <<
31 select ARCH_HAS_FORTIFY_SOURCE 9 select ARCH_HAS_FORTIFY_SOURCE
32 select ARCH_HAS_GCOV_PROFILE_ALL <<
33 select ARCH_HAS_GIGANTIC_PAGE <<
34 select ARCH_HAS_KCOV 10 select ARCH_HAS_KCOV
35 select ARCH_HAS_KERNEL_FPU_SUPPORT if !! 11 select ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE if !EVA
36 select ARCH_HAS_KEEPINITRD !! 12 select ARCH_HAS_PTE_SPECIAL if !(32BIT && CPU_HAS_RIXI)
37 select ARCH_HAS_MEMBARRIER_SYNC_CORE !! 13 select ARCH_HAS_STRNCPY_FROM_USER
38 select ARCH_HAS_MEM_ENCRYPT !! 14 select ARCH_HAS_STRNLEN_USER
39 select ARCH_HAS_NMI_SAFE_THIS_CPU_OPS <<
40 select ARCH_HAS_NON_OVERLAPPING_ADDRES <<
41 select ARCH_HAS_PTE_DEVMAP <<
42 select ARCH_HAS_PTE_SPECIAL <<
43 select ARCH_HAS_HW_PTE_YOUNG <<
44 select ARCH_HAS_SETUP_DMA_OPS <<
45 select ARCH_HAS_SET_DIRECT_MAP <<
46 select ARCH_HAS_SET_MEMORY <<
47 select ARCH_STACKWALK <<
48 select ARCH_HAS_STRICT_KERNEL_RWX <<
49 select ARCH_HAS_STRICT_MODULE_RWX <<
50 select ARCH_HAS_SYNC_DMA_FOR_DEVICE <<
51 select ARCH_HAS_SYNC_DMA_FOR_CPU <<
52 select ARCH_HAS_SYSCALL_WRAPPER <<
53 select ARCH_HAS_TICK_BROADCAST if GENE 15 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
54 select ARCH_HAS_ZONE_DMA_SET if EXPERT !! 16 select ARCH_HAS_UBSAN_SANITIZE_ALL
55 select ARCH_HAVE_ELF_PROT !! 17 select ARCH_HAS_GCOV_PROFILE_ALL
56 select ARCH_HAVE_NMI_SAFE_CMPXCHG <<
57 select ARCH_HAVE_TRACE_MMIO_ACCESS <<
58 select ARCH_INLINE_READ_LOCK if !PREEM <<
59 select ARCH_INLINE_READ_LOCK_BH if !PR <<
60 select ARCH_INLINE_READ_LOCK_IRQ if !P <<
61 select ARCH_INLINE_READ_LOCK_IRQSAVE i <<
62 select ARCH_INLINE_READ_UNLOCK if !PRE <<
63 select ARCH_INLINE_READ_UNLOCK_BH if ! <<
64 select ARCH_INLINE_READ_UNLOCK_IRQ if <<
65 select ARCH_INLINE_READ_UNLOCK_IRQREST <<
66 select ARCH_INLINE_WRITE_LOCK if !PREE <<
67 select ARCH_INLINE_WRITE_LOCK_BH if !P <<
68 select ARCH_INLINE_WRITE_LOCK_IRQ if ! <<
69 select ARCH_INLINE_WRITE_LOCK_IRQSAVE <<
70 select ARCH_INLINE_WRITE_UNLOCK if !PR <<
71 select ARCH_INLINE_WRITE_UNLOCK_BH if <<
72 select ARCH_INLINE_WRITE_UNLOCK_IRQ if <<
73 select ARCH_INLINE_WRITE_UNLOCK_IRQRES <<
74 select ARCH_INLINE_SPIN_TRYLOCK if !PR <<
75 select ARCH_INLINE_SPIN_TRYLOCK_BH if <<
76 select ARCH_INLINE_SPIN_LOCK if !PREEM <<
77 select ARCH_INLINE_SPIN_LOCK_BH if !PR <<
78 select ARCH_INLINE_SPIN_LOCK_IRQ if !P <<
79 select ARCH_INLINE_SPIN_LOCK_IRQSAVE i <<
80 select ARCH_INLINE_SPIN_UNLOCK if !PRE <<
81 select ARCH_INLINE_SPIN_UNLOCK_BH if ! <<
82 select ARCH_INLINE_SPIN_UNLOCK_IRQ if <<
83 select ARCH_INLINE_SPIN_UNLOCK_IRQREST <<
84 select ARCH_KEEP_MEMBLOCK 18 select ARCH_KEEP_MEMBLOCK
85 select ARCH_MHP_MEMMAP_ON_MEMORY_ENABL !! 19 select ARCH_SUPPORTS_UPROBES
86 select ARCH_USE_CMPXCHG_LOCKREF !! 20 select ARCH_USE_BUILTIN_BSWAP
87 select ARCH_USE_GNU_PROPERTY !! 21 select ARCH_USE_CMPXCHG_LOCKREF if 64BIT
88 select ARCH_USE_MEMTEST 22 select ARCH_USE_MEMTEST
89 select ARCH_USE_QUEUED_RWLOCKS 23 select ARCH_USE_QUEUED_RWLOCKS
90 select ARCH_USE_QUEUED_SPINLOCKS 24 select ARCH_USE_QUEUED_SPINLOCKS
91 select ARCH_USE_SYM_ANNOTATIONS !! 25 select ARCH_SUPPORTS_HUGETLBFS if CPU_SUPPORTS_HUGEPAGES
92 select ARCH_SUPPORTS_DEBUG_PAGEALLOC !! 26 select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT if MMU
93 select ARCH_SUPPORTS_HUGETLBFS !! 27 select ARCH_WANT_IPC_PARSE_VERSION
94 select ARCH_SUPPORTS_MEMORY_FAILURE <<
95 select ARCH_SUPPORTS_SHADOW_CALL_STACK <<
96 select ARCH_SUPPORTS_LTO_CLANG if CPU_ <<
97 select ARCH_SUPPORTS_LTO_CLANG_THIN <<
98 select ARCH_SUPPORTS_CFI_CLANG <<
99 select ARCH_SUPPORTS_ATOMIC_RMW <<
100 select ARCH_SUPPORTS_INT128 if CC_HAS_ <<
101 select ARCH_SUPPORTS_NUMA_BALANCING <<
102 select ARCH_SUPPORTS_PAGE_TABLE_CHECK <<
103 select ARCH_SUPPORTS_PER_VMA_LOCK <<
104 select ARCH_SUPPORTS_HUGE_PFNMAP if TR <<
105 select ARCH_SUPPORTS_RT <<
106 select ARCH_WANT_BATCHED_UNMAP_TLB_FLU <<
107 select ARCH_WANT_COMPAT_IPC_PARSE_VERS <<
108 select ARCH_WANT_DEFAULT_BPF_JIT <<
109 select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_ <<
110 select ARCH_WANT_FRAME_POINTERS <<
111 select ARCH_WANT_HUGE_PMD_SHARE if ARM <<
112 select ARCH_WANT_LD_ORPHAN_WARN 28 select ARCH_WANT_LD_ORPHAN_WARN
113 select ARCH_WANTS_EXECMEM_LATE if EXEC <<
114 select ARCH_WANTS_NO_INSTR <<
115 select ARCH_WANTS_THP_SWAP if ARM64_4K <<
116 select ARCH_HAS_UBSAN <<
117 select ARM_AMBA <<
118 select ARM_ARCH_TIMER <<
119 select ARM_GIC <<
120 select AUDIT_ARCH_COMPAT_GENERIC <<
121 select ARM_GIC_V2M if PCI <<
122 select ARM_GIC_V3 <<
123 select ARM_GIC_V3_ITS if PCI <<
124 select ARM_PSCI_FW <<
125 select BUILDTIME_TABLE_SORT 29 select BUILDTIME_TABLE_SORT
126 select CLONE_BACKWARDS 30 select CLONE_BACKWARDS
127 select COMMON_CLK !! 31 select CPU_NO_EFFICIENT_FFS if (TARGET_ISA_REV < 1)
128 select CPU_PM if (SUSPEND || CPU_IDLE) !! 32 select CPU_PM if CPU_IDLE
129 select CPUMASK_OFFSTACK if NR_CPUS > 2 !! 33 select GENERIC_ATOMIC64 if !64BIT
130 select CRC32 !! 34 select GENERIC_CMOS_UPDATE
131 select DCACHE_WORD_ACCESS <<
132 select DYNAMIC_FTRACE if FUNCTION_TRAC <<
133 select DMA_BOUNCE_UNALIGNED_KMALLOC <<
134 select DMA_DIRECT_REMAP <<
135 select EDAC_SUPPORT <<
136 select FRAME_POINTER <<
137 select FUNCTION_ALIGNMENT_4B <<
138 select FUNCTION_ALIGNMENT_8B if DYNAMI <<
139 select GENERIC_ALLOCATOR <<
140 select GENERIC_ARCH_TOPOLOGY <<
141 select GENERIC_CLOCKEVENTS_BROADCAST <<
142 select GENERIC_CPU_AUTOPROBE 35 select GENERIC_CPU_AUTOPROBE
143 select GENERIC_CPU_DEVICES !! 36 select GENERIC_GETTIMEOFDAY
144 select GENERIC_CPU_VULNERABILITIES !! 37 select GENERIC_IOMAP
145 select GENERIC_EARLY_IOREMAP <<
146 select GENERIC_IDLE_POLL_SETUP <<
147 select GENERIC_IOREMAP <<
148 select GENERIC_IRQ_IPI <<
149 select GENERIC_IRQ_PROBE 38 select GENERIC_IRQ_PROBE
150 select GENERIC_IRQ_SHOW 39 select GENERIC_IRQ_SHOW
151 select GENERIC_IRQ_SHOW_LEVEL !! 40 select GENERIC_ISA_DMA if EISA
152 select GENERIC_LIB_DEVMEM_IS_ALLOWED !! 41 select GENERIC_LIB_ASHLDI3
153 select GENERIC_PCI_IOMAP !! 42 select GENERIC_LIB_ASHRDI3
154 select GENERIC_PTDUMP !! 43 select GENERIC_LIB_CMPDI2
155 select GENERIC_SCHED_CLOCK !! 44 select GENERIC_LIB_LSHRDI3
>> 45 select GENERIC_LIB_UCMPDI2
>> 46 select GENERIC_SCHED_CLOCK if !CAVIUM_OCTEON_SOC
156 select GENERIC_SMP_IDLE_THREAD 47 select GENERIC_SMP_IDLE_THREAD
157 select GENERIC_TIME_VSYSCALL 48 select GENERIC_TIME_VSYSCALL
158 select GENERIC_GETTIMEOFDAY !! 49 select GUP_GET_PTE_LOW_HIGH if CPU_MIPS32 && PHYS_ADDR_T_64BIT
159 select GENERIC_VDSO_TIME_NS <<
160 select HARDIRQS_SW_RESEND <<
161 select HAS_IOPORT <<
162 select HAVE_MOVE_PMD <<
163 select HAVE_MOVE_PUD <<
164 select HAVE_PCI <<
165 select HAVE_ACPI_APEI if (ACPI && EFI) <<
166 select HAVE_ALIGNED_STRUCT_PAGE <<
167 select HAVE_ARCH_AUDITSYSCALL <<
168 select HAVE_ARCH_BITREVERSE <<
169 select HAVE_ARCH_COMPILER_H 50 select HAVE_ARCH_COMPILER_H
170 select HAVE_ARCH_HUGE_VMALLOC <<
171 select HAVE_ARCH_HUGE_VMAP <<
172 select HAVE_ARCH_JUMP_LABEL 51 select HAVE_ARCH_JUMP_LABEL
173 select HAVE_ARCH_JUMP_LABEL_RELATIVE !! 52 select HAVE_ARCH_KGDB if MIPS_FP_SUPPORT
174 select HAVE_ARCH_KASAN !! 53 select HAVE_ARCH_MMAP_RND_BITS if MMU
175 select HAVE_ARCH_KASAN_VMALLOC !! 54 select HAVE_ARCH_MMAP_RND_COMPAT_BITS if MMU && COMPAT
176 select HAVE_ARCH_KASAN_SW_TAGS <<
177 select HAVE_ARCH_KASAN_HW_TAGS if ARM6 <<
178 # Some instrumentation may be unsound, <<
179 select HAVE_ARCH_KCSAN if EXPERT <<
180 select HAVE_ARCH_KFENCE <<
181 select HAVE_ARCH_KGDB <<
182 select HAVE_ARCH_MMAP_RND_BITS <<
183 select HAVE_ARCH_MMAP_RND_COMPAT_BITS <<
184 select HAVE_ARCH_PREL32_RELOCATIONS <<
185 select HAVE_ARCH_RANDOMIZE_KSTACK_OFFS <<
186 select HAVE_ARCH_SECCOMP_FILTER 55 select HAVE_ARCH_SECCOMP_FILTER
187 select HAVE_ARCH_STACKLEAK <<
188 select HAVE_ARCH_THREAD_STRUCT_WHITELI <<
189 select HAVE_ARCH_TRACEHOOK 56 select HAVE_ARCH_TRACEHOOK
190 select HAVE_ARCH_TRANSPARENT_HUGEPAGE !! 57 select HAVE_ARCH_TRANSPARENT_HUGEPAGE if CPU_SUPPORTS_HUGEPAGES
191 select HAVE_ARCH_VMAP_STACK <<
192 select HAVE_ARM_SMCCC <<
193 select HAVE_ASM_MODVERSIONS 58 select HAVE_ASM_MODVERSIONS
194 select HAVE_EBPF_JIT !! 59 select HAVE_CONTEXT_TRACKING
>> 60 select HAVE_TIF_NOHZ
195 select HAVE_C_RECORDMCOUNT 61 select HAVE_C_RECORDMCOUNT
196 select HAVE_CMPXCHG_DOUBLE <<
197 select HAVE_CMPXCHG_LOCAL <<
198 select HAVE_CONTEXT_TRACKING_USER <<
199 select HAVE_DEBUG_KMEMLEAK 62 select HAVE_DEBUG_KMEMLEAK
>> 63 select HAVE_DEBUG_STACKOVERFLOW
200 select HAVE_DMA_CONTIGUOUS 64 select HAVE_DMA_CONTIGUOUS
201 select HAVE_DYNAMIC_FTRACE 65 select HAVE_DYNAMIC_FTRACE
202 select HAVE_DYNAMIC_FTRACE_WITH_ARGS \ !! 66 select HAVE_EBPF_JIT if !CPU_MICROMIPS && \
203 if (GCC_SUPPORTS_DYNAMIC_FTRAC !! 67 !CPU_DADDI_WORKAROUNDS && \
204 CLANG_SUPPORTS_DYNAMIC_FTR !! 68 !CPU_R4000_WORKAROUNDS && \
205 select HAVE_DYNAMIC_FTRACE_WITH_DIRECT !! 69 !CPU_R4400_WORKAROUNDS
206 if DYNAMIC_FTRACE_WITH_ARGS && !! 70 select HAVE_EXIT_THREAD
207 select HAVE_DYNAMIC_FTRACE_WITH_CALL_O !! 71 select HAVE_FAST_GUP
208 if (DYNAMIC_FTRACE_WITH_ARGS & <<
209 (CC_IS_CLANG || !CC_OPTIMI <<
210 select FTRACE_MCOUNT_USE_PATCHABLE_FUN <<
211 if DYNAMIC_FTRACE_WITH_ARGS <<
212 select HAVE_SAMPLE_FTRACE_DIRECT <<
213 select HAVE_SAMPLE_FTRACE_DIRECT_MULTI <<
214 select HAVE_EFFICIENT_UNALIGNED_ACCESS <<
215 select HAVE_GUP_FAST <<
216 select HAVE_FTRACE_MCOUNT_RECORD 72 select HAVE_FTRACE_MCOUNT_RECORD
217 select HAVE_FUNCTION_TRACER <<
218 select HAVE_FUNCTION_ERROR_INJECTION <<
219 select HAVE_FUNCTION_GRAPH_TRACER 73 select HAVE_FUNCTION_GRAPH_TRACER
220 select HAVE_FUNCTION_GRAPH_RETVAL !! 74 select HAVE_FUNCTION_TRACER
221 select HAVE_GCC_PLUGINS 75 select HAVE_GCC_PLUGINS
222 select HAVE_HARDLOCKUP_DETECTOR_PERF i !! 76 select HAVE_GENERIC_VDSO
223 HW_PERF_EVENTS && HAVE_PERF_EV <<
224 select HAVE_HW_BREAKPOINT if PERF_EVEN <<
225 select HAVE_IOREMAP_PROT 77 select HAVE_IOREMAP_PROT
>> 78 select HAVE_IRQ_EXIT_ON_IRQ_STACK
226 select HAVE_IRQ_TIME_ACCOUNTING 79 select HAVE_IRQ_TIME_ACCOUNTING
>> 80 select HAVE_KPROBES
>> 81 select HAVE_KRETPROBES
>> 82 select HAVE_LD_DEAD_CODE_DATA_ELIMINATION
227 select HAVE_MOD_ARCH_SPECIFIC 83 select HAVE_MOD_ARCH_SPECIFIC
228 select HAVE_NMI 84 select HAVE_NMI
229 select HAVE_PERF_EVENTS 85 select HAVE_PERF_EVENTS
230 select HAVE_PERF_EVENTS_NMI if ARM64_P <<
231 select HAVE_PERF_REGS 86 select HAVE_PERF_REGS
232 select HAVE_PERF_USER_STACK_DUMP 87 select HAVE_PERF_USER_STACK_DUMP
233 select HAVE_PREEMPT_DYNAMIC_KEY <<
234 select HAVE_REGS_AND_STACK_ACCESS_API 88 select HAVE_REGS_AND_STACK_ACCESS_API
235 select HAVE_POSIX_CPU_TIMERS_TASK_WORK <<
236 select HAVE_FUNCTION_ARG_ACCESS_API <<
237 select MMU_GATHER_RCU_TABLE_FREE <<
238 select HAVE_RSEQ 89 select HAVE_RSEQ
239 select HAVE_RUST if RUSTC_SUPPORTS_ARM !! 90 select HAVE_SPARSE_SYSCALL_NR
240 select HAVE_STACKPROTECTOR 91 select HAVE_STACKPROTECTOR
241 select HAVE_SYSCALL_TRACEPOINTS 92 select HAVE_SYSCALL_TRACEPOINTS
242 select HAVE_KPROBES !! 93 select HAVE_VIRT_CPU_ACCOUNTING_GEN if 64BIT || !SMP
243 select HAVE_KRETPROBES <<
244 select HAVE_GENERIC_VDSO <<
245 select HOTPLUG_CORE_SYNC_DEAD if HOTPL <<
246 select IRQ_DOMAIN <<
247 select IRQ_FORCED_THREADING 94 select IRQ_FORCED_THREADING
248 select KASAN_VMALLOC if KASAN !! 95 select ISA if EISA
249 select LOCK_MM_AND_FIND_VMA !! 96 select MODULES_USE_ELF_REL if MODULES
250 select MODULES_USE_ELF_RELA !! 97 select MODULES_USE_ELF_RELA if MODULES && 64BIT
251 select NEED_DMA_MAP_STATE !! 98 select PERF_USE_VMALLOC
252 select NEED_SG_DMA_LENGTH !! 99 select PCI_MSI_ARCH_FALLBACKS if PCI_MSI
253 select OF !! 100 select RTC_LIB
254 select OF_EARLY_FLATTREE <<
255 select PCI_DOMAINS_GENERIC if PCI <<
256 select PCI_ECAM if (ACPI && PCI) <<
257 select PCI_SYSCALL if PCI <<
258 select POWER_RESET <<
259 select POWER_SUPPLY <<
260 select SPARSE_IRQ <<
261 select SWIOTLB <<
262 select SYSCTL_EXCEPTION_TRACE 101 select SYSCTL_EXCEPTION_TRACE
263 select THREAD_INFO_IN_TASK <<
264 select HAVE_ARCH_USERFAULTFD_MINOR if <<
265 select HAVE_ARCH_USERFAULTFD_WP if USE <<
266 select TRACE_IRQFLAGS_SUPPORT 102 select TRACE_IRQFLAGS_SUPPORT
267 select TRACE_IRQFLAGS_NMI_SUPPORT !! 103 select VIRT_TO_BUS
268 select HAVE_SOFTIRQ_ON_OWN_STACK !! 104 select ARCH_HAS_ELFCORE_COMPAT
269 select USER_STACKTRACE_SUPPORT !! 105 select HAVE_ARCH_KCSAN if 64BIT
270 select VDSO_GETRANDOM <<
271 help <<
272 ARM 64-bit (AArch64) Linux support. <<
273 <<
274 config RUSTC_SUPPORTS_ARM64 <<
275 def_bool y <<
276 depends on CPU_LITTLE_ENDIAN <<
277 # Shadow call stack is only supported <<
278 # <<
279 # When using the UNWIND_PATCH_PAC_INTO <<
280 # required due to use of the -Zfixed-x <<
281 # <<
282 # Otherwise, rustc version 1.82+ is re <<
283 # -Zsanitizer=shadow-call-stack flag. <<
284 depends on !SHADOW_CALL_STACK || RUSTC <<
285 <<
286 config CLANG_SUPPORTS_DYNAMIC_FTRACE_WITH_ARGS <<
287 def_bool CC_IS_CLANG <<
288 # https://github.com/ClangBuiltLinux/l <<
289 depends on AS_IS_GNU || (AS_IS_LLVM && <<
290 <<
291 config GCC_SUPPORTS_DYNAMIC_FTRACE_WITH_ARGS <<
292 def_bool CC_IS_GCC <<
293 depends on $(cc-option,-fpatchable-fun <<
294 <<
295 config 64BIT <<
296 def_bool y <<
297 <<
298 config MMU <<
299 def_bool y <<
300 <<
301 config ARM64_CONT_PTE_SHIFT <<
302 int <<
303 default 5 if PAGE_SIZE_64KB <<
304 default 7 if PAGE_SIZE_16KB <<
305 default 4 <<
306 <<
307 config ARM64_CONT_PMD_SHIFT <<
308 int <<
309 default 5 if PAGE_SIZE_64KB <<
310 default 5 if PAGE_SIZE_16KB <<
311 default 4 <<
312 106
313 config ARCH_MMAP_RND_BITS_MIN !! 107 config MIPS_FIXUP_BIGPHYS_ADDR
314 default 14 if PAGE_SIZE_64KB !! 108 bool
315 default 16 if PAGE_SIZE_16KB <<
316 default 18 <<
317 109
318 # max bits determined by the following formula !! 110 config MIPS_GENERIC
319 # VA_BITS - PAGE_SHIFT - 3 !! 111 bool
320 config ARCH_MMAP_RND_BITS_MAX <<
321 default 19 if ARM64_VA_BITS=36 <<
322 default 24 if ARM64_VA_BITS=39 <<
323 default 27 if ARM64_VA_BITS=42 <<
324 default 30 if ARM64_VA_BITS=47 <<
325 default 29 if ARM64_VA_BITS=48 && ARM6 <<
326 default 31 if ARM64_VA_BITS=48 && ARM6 <<
327 default 33 if ARM64_VA_BITS=48 <<
328 default 14 if ARM64_64K_PAGES <<
329 default 16 if ARM64_16K_PAGES <<
330 default 18 <<
331 112
332 config ARCH_MMAP_RND_COMPAT_BITS_MIN !! 113 config MACH_INGENIC
333 default 7 if ARM64_64K_PAGES !! 114 bool
334 default 9 if ARM64_16K_PAGES !! 115 select SYS_SUPPORTS_32BIT_KERNEL
335 default 11 !! 116 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 117 select SYS_SUPPORTS_ZBOOT
>> 118 select DMA_NONCOHERENT
>> 119 select ARCH_HAS_SYNC_DMA_FOR_CPU
>> 120 select IRQ_MIPS_CPU
>> 121 select PINCTRL
>> 122 select GPIOLIB
>> 123 select COMMON_CLK
>> 124 select GENERIC_IRQ_CHIP
>> 125 select BUILTIN_DTB if MIPS_NO_APPENDED_DTB
>> 126 select USE_OF
>> 127 select CPU_SUPPORTS_CPUFREQ
>> 128 select MIPS_EXTERNAL_TIMER
336 129
337 config ARCH_MMAP_RND_COMPAT_BITS_MAX !! 130 menu "Machine selection"
338 default 16 <<
339 131
340 config NO_IOPORT_MAP !! 132 choice
341 def_bool y if !PCI !! 133 prompt "System type"
>> 134 default MIPS_GENERIC_KERNEL
342 135
343 config STACKTRACE_SUPPORT !! 136 config MIPS_GENERIC_KERNEL
344 def_bool y !! 137 bool "Generic board-agnostic MIPS kernel"
>> 138 select ARCH_HAS_SETUP_DMA_OPS
>> 139 select MIPS_GENERIC
>> 140 select BOOT_RAW
>> 141 select BUILTIN_DTB
>> 142 select CEVT_R4K
>> 143 select CLKSRC_MIPS_GIC
>> 144 select COMMON_CLK
>> 145 select CPU_MIPSR2_IRQ_EI
>> 146 select CPU_MIPSR2_IRQ_VI
>> 147 select CSRC_R4K
>> 148 select DMA_NONCOHERENT
>> 149 select HAVE_PCI
>> 150 select IRQ_MIPS_CPU
>> 151 select MIPS_AUTO_PFN_OFFSET
>> 152 select MIPS_CPU_SCACHE
>> 153 select MIPS_GIC
>> 154 select MIPS_L1_CACHE_SHIFT_7
>> 155 select NO_EXCEPT_FILL
>> 156 select PCI_DRIVERS_GENERIC
>> 157 select SMP_UP if SMP
>> 158 select SWAP_IO_SPACE
>> 159 select SYS_HAS_CPU_MIPS32_R1
>> 160 select SYS_HAS_CPU_MIPS32_R2
>> 161 select SYS_HAS_CPU_MIPS32_R6
>> 162 select SYS_HAS_CPU_MIPS64_R1
>> 163 select SYS_HAS_CPU_MIPS64_R2
>> 164 select SYS_HAS_CPU_MIPS64_R6
>> 165 select SYS_SUPPORTS_32BIT_KERNEL
>> 166 select SYS_SUPPORTS_64BIT_KERNEL
>> 167 select SYS_SUPPORTS_BIG_ENDIAN
>> 168 select SYS_SUPPORTS_HIGHMEM
>> 169 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 170 select SYS_SUPPORTS_MICROMIPS
>> 171 select SYS_SUPPORTS_MIPS16
>> 172 select SYS_SUPPORTS_MIPS_CPS
>> 173 select SYS_SUPPORTS_MULTITHREADING
>> 174 select SYS_SUPPORTS_RELOCATABLE
>> 175 select SYS_SUPPORTS_SMARTMIPS
>> 176 select SYS_SUPPORTS_ZBOOT
>> 177 select UHI_BOOT
>> 178 select USB_EHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
>> 179 select USB_EHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 180 select USB_OHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
>> 181 select USB_OHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 182 select USB_UHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
>> 183 select USB_UHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 184 select USE_OF
>> 185 help
>> 186 Select this to build a kernel which aims to support multiple boards,
>> 187 generally using a flattened device tree passed from the bootloader
>> 188 using the boot protocol defined in the UHI (Unified Hosting
>> 189 Interface) specification.
>> 190
>> 191 config MIPS_ALCHEMY
>> 192 bool "Alchemy processor based machines"
>> 193 select PHYS_ADDR_T_64BIT
>> 194 select CEVT_R4K
>> 195 select CSRC_R4K
>> 196 select IRQ_MIPS_CPU
>> 197 select DMA_NONCOHERENT # Au1000,1500,1100 aren't, rest is
>> 198 select MIPS_FIXUP_BIGPHYS_ADDR if PCI
>> 199 select SYS_HAS_CPU_MIPS32_R1
>> 200 select SYS_SUPPORTS_32BIT_KERNEL
>> 201 select SYS_SUPPORTS_APM_EMULATION
>> 202 select GPIOLIB
>> 203 select SYS_SUPPORTS_ZBOOT
>> 204 select COMMON_CLK
345 205
346 config ILLEGAL_POINTER_VALUE !! 206 config AR7
347 hex !! 207 bool "Texas Instruments AR7"
348 default 0xdead000000000000 !! 208 select BOOT_ELF32
>> 209 select COMMON_CLK
>> 210 select DMA_NONCOHERENT
>> 211 select CEVT_R4K
>> 212 select CSRC_R4K
>> 213 select IRQ_MIPS_CPU
>> 214 select NO_EXCEPT_FILL
>> 215 select SWAP_IO_SPACE
>> 216 select SYS_HAS_CPU_MIPS32_R1
>> 217 select SYS_HAS_EARLY_PRINTK
>> 218 select SYS_SUPPORTS_32BIT_KERNEL
>> 219 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 220 select SYS_SUPPORTS_MIPS16
>> 221 select SYS_SUPPORTS_ZBOOT_UART16550
>> 222 select GPIOLIB
>> 223 select VLYNQ
>> 224 help
>> 225 Support for the Texas Instruments AR7 System-on-a-Chip
>> 226 family: TNETD7100, 7200 and 7300.
>> 227
>> 228 config ATH25
>> 229 bool "Atheros AR231x/AR531x SoC support"
>> 230 select CEVT_R4K
>> 231 select CSRC_R4K
>> 232 select DMA_NONCOHERENT
>> 233 select IRQ_MIPS_CPU
>> 234 select IRQ_DOMAIN
>> 235 select SYS_HAS_CPU_MIPS32_R1
>> 236 select SYS_SUPPORTS_BIG_ENDIAN
>> 237 select SYS_SUPPORTS_32BIT_KERNEL
>> 238 select SYS_HAS_EARLY_PRINTK
>> 239 help
>> 240 Support for Atheros AR231x and Atheros AR531x based boards
>> 241
>> 242 config ATH79
>> 243 bool "Atheros AR71XX/AR724X/AR913X based boards"
>> 244 select ARCH_HAS_RESET_CONTROLLER
>> 245 select BOOT_RAW
>> 246 select CEVT_R4K
>> 247 select CSRC_R4K
>> 248 select DMA_NONCOHERENT
>> 249 select GPIOLIB
>> 250 select PINCTRL
>> 251 select COMMON_CLK
>> 252 select IRQ_MIPS_CPU
>> 253 select SYS_HAS_CPU_MIPS32_R2
>> 254 select SYS_HAS_EARLY_PRINTK
>> 255 select SYS_SUPPORTS_32BIT_KERNEL
>> 256 select SYS_SUPPORTS_BIG_ENDIAN
>> 257 select SYS_SUPPORTS_MIPS16
>> 258 select SYS_SUPPORTS_ZBOOT_UART_PROM
>> 259 select USE_OF
>> 260 select USB_EHCI_ROOT_HUB_TT if USB_EHCI_HCD_PLATFORM
>> 261 help
>> 262 Support for the Atheros AR71XX/AR724X/AR913X SoCs.
>> 263
>> 264 config BMIPS_GENERIC
>> 265 bool "Broadcom Generic BMIPS kernel"
>> 266 select ARCH_HAS_RESET_CONTROLLER
>> 267 select ARCH_HAS_SYNC_DMA_FOR_CPU_ALL
>> 268 select BOOT_RAW
>> 269 select NO_EXCEPT_FILL
>> 270 select USE_OF
>> 271 select CEVT_R4K
>> 272 select CSRC_R4K
>> 273 select SYNC_R4K
>> 274 select COMMON_CLK
>> 275 select BCM6345_L1_IRQ
>> 276 select BCM7038_L1_IRQ
>> 277 select BCM7120_L2_IRQ
>> 278 select BRCMSTB_L2_IRQ
>> 279 select IRQ_MIPS_CPU
>> 280 select DMA_NONCOHERENT
>> 281 select SYS_SUPPORTS_32BIT_KERNEL
>> 282 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 283 select SYS_SUPPORTS_BIG_ENDIAN
>> 284 select SYS_SUPPORTS_HIGHMEM
>> 285 select SYS_HAS_CPU_BMIPS32_3300
>> 286 select SYS_HAS_CPU_BMIPS4350
>> 287 select SYS_HAS_CPU_BMIPS4380
>> 288 select SYS_HAS_CPU_BMIPS5000
>> 289 select SWAP_IO_SPACE
>> 290 select USB_EHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
>> 291 select USB_EHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 292 select USB_OHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
>> 293 select USB_OHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 294 select HARDIRQS_SW_RESEND
>> 295 select HAVE_PCI
>> 296 select PCI_DRIVERS_GENERIC
>> 297 help
>> 298 Build a generic DT-based kernel image that boots on select
>> 299 BCM33xx cable modem chips, BCM63xx DSL chips, and BCM7xxx set-top
>> 300 box chips. Note that CONFIG_CPU_BIG_ENDIAN/CONFIG_CPU_LITTLE_ENDIAN
>> 301 must be set appropriately for your board.
>> 302
>> 303 config BCM47XX
>> 304 bool "Broadcom BCM47XX based boards"
>> 305 select BOOT_RAW
>> 306 select CEVT_R4K
>> 307 select CSRC_R4K
>> 308 select DMA_NONCOHERENT
>> 309 select HAVE_PCI
>> 310 select IRQ_MIPS_CPU
>> 311 select SYS_HAS_CPU_MIPS32_R1
>> 312 select NO_EXCEPT_FILL
>> 313 select SYS_SUPPORTS_32BIT_KERNEL
>> 314 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 315 select SYS_SUPPORTS_MIPS16
>> 316 select SYS_SUPPORTS_ZBOOT
>> 317 select SYS_HAS_EARLY_PRINTK
>> 318 select USE_GENERIC_EARLY_PRINTK_8250
>> 319 select GPIOLIB
>> 320 select LEDS_GPIO_REGISTER
>> 321 select BCM47XX_NVRAM
>> 322 select BCM47XX_SPROM
>> 323 select BCM47XX_SSB if !BCM47XX_BCMA
>> 324 help
>> 325 Support for BCM47XX based boards
>> 326
>> 327 config BCM63XX
>> 328 bool "Broadcom BCM63XX based boards"
>> 329 select BOOT_RAW
>> 330 select CEVT_R4K
>> 331 select CSRC_R4K
>> 332 select SYNC_R4K
>> 333 select DMA_NONCOHERENT
>> 334 select IRQ_MIPS_CPU
>> 335 select SYS_SUPPORTS_32BIT_KERNEL
>> 336 select SYS_SUPPORTS_BIG_ENDIAN
>> 337 select SYS_HAS_EARLY_PRINTK
>> 338 select SYS_HAS_CPU_BMIPS32_3300
>> 339 select SYS_HAS_CPU_BMIPS4350
>> 340 select SYS_HAS_CPU_BMIPS4380
>> 341 select SWAP_IO_SPACE
>> 342 select GPIOLIB
>> 343 select MIPS_L1_CACHE_SHIFT_4
>> 344 select HAVE_LEGACY_CLK
>> 345 help
>> 346 Support for BCM63XX based boards
>> 347
>> 348 config MIPS_COBALT
>> 349 bool "Cobalt Server"
>> 350 select CEVT_R4K
>> 351 select CSRC_R4K
>> 352 select CEVT_GT641XX
>> 353 select DMA_NONCOHERENT
>> 354 select FORCE_PCI
>> 355 select I8253
>> 356 select I8259
>> 357 select IRQ_MIPS_CPU
>> 358 select IRQ_GT641XX
>> 359 select PCI_GT64XXX_PCI0
>> 360 select SYS_HAS_CPU_NEVADA
>> 361 select SYS_HAS_EARLY_PRINTK
>> 362 select SYS_SUPPORTS_32BIT_KERNEL
>> 363 select SYS_SUPPORTS_64BIT_KERNEL
>> 364 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 365 select USE_GENERIC_EARLY_PRINTK_8250
>> 366
>> 367 config MACH_DECSTATION
>> 368 bool "DECstations"
>> 369 select BOOT_ELF32
>> 370 select CEVT_DS1287
>> 371 select CEVT_R4K if CPU_R4X00
>> 372 select CSRC_IOASIC
>> 373 select CSRC_R4K if CPU_R4X00
>> 374 select CPU_DADDI_WORKAROUNDS if 64BIT
>> 375 select CPU_R4000_WORKAROUNDS if 64BIT
>> 376 select CPU_R4400_WORKAROUNDS if 64BIT
>> 377 select DMA_NONCOHERENT
>> 378 select NO_IOPORT_MAP
>> 379 select IRQ_MIPS_CPU
>> 380 select SYS_HAS_CPU_R3000
>> 381 select SYS_HAS_CPU_R4X00
>> 382 select SYS_SUPPORTS_32BIT_KERNEL
>> 383 select SYS_SUPPORTS_64BIT_KERNEL
>> 384 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 385 select SYS_SUPPORTS_128HZ
>> 386 select SYS_SUPPORTS_256HZ
>> 387 select SYS_SUPPORTS_1024HZ
>> 388 select MIPS_L1_CACHE_SHIFT_4
>> 389 help
>> 390 This enables support for DEC's MIPS based workstations. For details
>> 391 see the Linux/MIPS FAQ on <http://www.linux-mips.org/> and the
>> 392 DECstation porting pages on <http://decstation.unix-ag.org/>.
>> 393
>> 394 If you have one of the following DECstation Models you definitely
>> 395 want to choose R4xx0 for the CPU Type:
>> 396
>> 397 DECstation 5000/50
>> 398 DECstation 5000/150
>> 399 DECstation 5000/260
>> 400 DECsystem 5900/260
>> 401
>> 402 otherwise choose R3000.
>> 403
>> 404 config MACH_JAZZ
>> 405 bool "Jazz family of machines"
>> 406 select ARC_MEMORY
>> 407 select ARC_PROMLIB
>> 408 select ARCH_MIGHT_HAVE_PC_PARPORT
>> 409 select ARCH_MIGHT_HAVE_PC_SERIO
>> 410 select DMA_OPS
>> 411 select FW_ARC
>> 412 select FW_ARC32
>> 413 select ARCH_MAY_HAVE_PC_FDC
>> 414 select CEVT_R4K
>> 415 select CSRC_R4K
>> 416 select DEFAULT_SGI_PARTITION if CPU_BIG_ENDIAN
>> 417 select GENERIC_ISA_DMA
>> 418 select HAVE_PCSPKR_PLATFORM
>> 419 select IRQ_MIPS_CPU
>> 420 select I8253
>> 421 select I8259
>> 422 select ISA
>> 423 select SYS_HAS_CPU_R4X00
>> 424 select SYS_SUPPORTS_32BIT_KERNEL
>> 425 select SYS_SUPPORTS_64BIT_KERNEL
>> 426 select SYS_SUPPORTS_100HZ
>> 427 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 428 help
>> 429 This a family of machines based on the MIPS R4030 chipset which was
>> 430 used by several vendors to build RISC/os and Windows NT workstations.
>> 431 Members include the Acer PICA, MIPS Magnum 4000, MIPS Millennium and
>> 432 Olivetti M700-10 workstations.
>> 433
>> 434 config MACH_INGENIC_SOC
>> 435 bool "Ingenic SoC based machines"
>> 436 select MIPS_GENERIC
>> 437 select MACH_INGENIC
>> 438 select SYS_SUPPORTS_ZBOOT_UART16550
>> 439 select CPU_SUPPORTS_CPUFREQ
>> 440 select MIPS_EXTERNAL_TIMER
>> 441
>> 442 config LANTIQ
>> 443 bool "Lantiq based platforms"
>> 444 select DMA_NONCOHERENT
>> 445 select IRQ_MIPS_CPU
>> 446 select CEVT_R4K
>> 447 select CSRC_R4K
>> 448 select SYS_HAS_CPU_MIPS32_R1
>> 449 select SYS_HAS_CPU_MIPS32_R2
>> 450 select SYS_SUPPORTS_BIG_ENDIAN
>> 451 select SYS_SUPPORTS_32BIT_KERNEL
>> 452 select SYS_SUPPORTS_MIPS16
>> 453 select SYS_SUPPORTS_MULTITHREADING
>> 454 select SYS_SUPPORTS_VPE_LOADER
>> 455 select SYS_HAS_EARLY_PRINTK
>> 456 select GPIOLIB
>> 457 select SWAP_IO_SPACE
>> 458 select BOOT_RAW
>> 459 select HAVE_LEGACY_CLK
>> 460 select USE_OF
>> 461 select PINCTRL
>> 462 select PINCTRL_LANTIQ
>> 463 select ARCH_HAS_RESET_CONTROLLER
>> 464 select RESET_CONTROLLER
>> 465
>> 466 config MACH_LOONGSON32
>> 467 bool "Loongson 32-bit family of machines"
>> 468 select SYS_SUPPORTS_ZBOOT
>> 469 help
>> 470 This enables support for the Loongson-1 family of machines.
>> 471
>> 472 Loongson-1 is a family of 32-bit MIPS-compatible SoCs developed by
>> 473 the Institute of Computing Technology (ICT), Chinese Academy of
>> 474 Sciences (CAS).
>> 475
>> 476 config MACH_LOONGSON2EF
>> 477 bool "Loongson-2E/F family of machines"
>> 478 select SYS_SUPPORTS_ZBOOT
>> 479 help
>> 480 This enables the support of early Loongson-2E/F family of machines.
>> 481
>> 482 config MACH_LOONGSON64
>> 483 bool "Loongson 64-bit family of machines"
>> 484 select ARCH_SPARSEMEM_ENABLE
>> 485 select ARCH_MIGHT_HAVE_PC_PARPORT
>> 486 select ARCH_MIGHT_HAVE_PC_SERIO
>> 487 select GENERIC_ISA_DMA_SUPPORT_BROKEN
>> 488 select BOOT_ELF32
>> 489 select BOARD_SCACHE
>> 490 select CSRC_R4K
>> 491 select CEVT_R4K
>> 492 select CPU_HAS_WB
>> 493 select FORCE_PCI
>> 494 select ISA
>> 495 select I8259
>> 496 select IRQ_MIPS_CPU
>> 497 select NO_EXCEPT_FILL
>> 498 select NR_CPUS_DEFAULT_64
>> 499 select USE_GENERIC_EARLY_PRINTK_8250
>> 500 select PCI_DRIVERS_GENERIC
>> 501 select SYS_HAS_CPU_LOONGSON64
>> 502 select SYS_HAS_EARLY_PRINTK
>> 503 select SYS_SUPPORTS_SMP
>> 504 select SYS_SUPPORTS_HOTPLUG_CPU
>> 505 select SYS_SUPPORTS_NUMA
>> 506 select SYS_SUPPORTS_64BIT_KERNEL
>> 507 select SYS_SUPPORTS_HIGHMEM
>> 508 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 509 select SYS_SUPPORTS_ZBOOT
>> 510 select SYS_SUPPORTS_RELOCATABLE
>> 511 select ZONE_DMA32
>> 512 select COMMON_CLK
>> 513 select USE_OF
>> 514 select BUILTIN_DTB
>> 515 select PCI_HOST_GENERIC
>> 516 select HAVE_ARCH_NODEDATA_EXTENSION if NUMA
>> 517 help
>> 518 This enables the support of Loongson-2/3 family of machines.
>> 519
>> 520 Loongson-2 and Loongson-3 are 64-bit general-purpose processors with
>> 521 GS264/GS464/GS464E/GS464V microarchitecture (except old Loongson-2E
>> 522 and Loongson-2F which will be removed), developed by the Institute
>> 523 of Computing Technology (ICT), Chinese Academy of Sciences (CAS).
>> 524
>> 525 config MIPS_MALTA
>> 526 bool "MIPS Malta board"
>> 527 select ARCH_MAY_HAVE_PC_FDC
>> 528 select ARCH_MIGHT_HAVE_PC_PARPORT
>> 529 select ARCH_MIGHT_HAVE_PC_SERIO
>> 530 select BOOT_ELF32
>> 531 select BOOT_RAW
>> 532 select BUILTIN_DTB
>> 533 select CEVT_R4K
>> 534 select CLKSRC_MIPS_GIC
>> 535 select COMMON_CLK
>> 536 select CSRC_R4K
>> 537 select DMA_NONCOHERENT
>> 538 select GENERIC_ISA_DMA
>> 539 select HAVE_PCSPKR_PLATFORM
>> 540 select HAVE_PCI
>> 541 select I8253
>> 542 select I8259
>> 543 select IRQ_MIPS_CPU
>> 544 select MIPS_BONITO64
>> 545 select MIPS_CPU_SCACHE
>> 546 select MIPS_GIC
>> 547 select MIPS_L1_CACHE_SHIFT_6
>> 548 select MIPS_MSC
>> 549 select PCI_GT64XXX_PCI0
>> 550 select SMP_UP if SMP
>> 551 select SWAP_IO_SPACE
>> 552 select SYS_HAS_CPU_MIPS32_R1
>> 553 select SYS_HAS_CPU_MIPS32_R2
>> 554 select SYS_HAS_CPU_MIPS32_R3_5
>> 555 select SYS_HAS_CPU_MIPS32_R5
>> 556 select SYS_HAS_CPU_MIPS32_R6
>> 557 select SYS_HAS_CPU_MIPS64_R1
>> 558 select SYS_HAS_CPU_MIPS64_R2
>> 559 select SYS_HAS_CPU_MIPS64_R6
>> 560 select SYS_HAS_CPU_NEVADA
>> 561 select SYS_HAS_CPU_RM7000
>> 562 select SYS_SUPPORTS_32BIT_KERNEL
>> 563 select SYS_SUPPORTS_64BIT_KERNEL
>> 564 select SYS_SUPPORTS_BIG_ENDIAN
>> 565 select SYS_SUPPORTS_HIGHMEM
>> 566 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 567 select SYS_SUPPORTS_MICROMIPS
>> 568 select SYS_SUPPORTS_MIPS16
>> 569 select SYS_SUPPORTS_MIPS_CMP
>> 570 select SYS_SUPPORTS_MIPS_CPS
>> 571 select SYS_SUPPORTS_MULTITHREADING
>> 572 select SYS_SUPPORTS_RELOCATABLE
>> 573 select SYS_SUPPORTS_SMARTMIPS
>> 574 select SYS_SUPPORTS_VPE_LOADER
>> 575 select SYS_SUPPORTS_ZBOOT
>> 576 select USE_OF
>> 577 select WAR_ICACHE_REFILLS
>> 578 select ZONE_DMA32 if 64BIT
>> 579 help
>> 580 This enables support for the MIPS Technologies Malta evaluation
>> 581 board.
>> 582
>> 583 config MACH_PIC32
>> 584 bool "Microchip PIC32 Family"
>> 585 help
>> 586 This enables support for the Microchip PIC32 family of platforms.
>> 587
>> 588 Microchip PIC32 is a family of general-purpose 32 bit MIPS core
>> 589 microcontrollers.
>> 590
>> 591 config MACH_VR41XX
>> 592 bool "NEC VR4100 series based machines"
>> 593 select CEVT_R4K
>> 594 select CSRC_R4K
>> 595 select SYS_HAS_CPU_VR41XX
>> 596 select SYS_SUPPORTS_MIPS16
>> 597 select GPIOLIB
>> 598
>> 599 config MACH_NINTENDO64
>> 600 bool "Nintendo 64 console"
>> 601 select CEVT_R4K
>> 602 select CSRC_R4K
>> 603 select SYS_HAS_CPU_R4300
>> 604 select SYS_SUPPORTS_BIG_ENDIAN
>> 605 select SYS_SUPPORTS_ZBOOT
>> 606 select SYS_SUPPORTS_32BIT_KERNEL
>> 607 select SYS_SUPPORTS_64BIT_KERNEL
>> 608 select DMA_NONCOHERENT
>> 609 select IRQ_MIPS_CPU
>> 610
>> 611 config RALINK
>> 612 bool "Ralink based machines"
>> 613 select CEVT_R4K
>> 614 select COMMON_CLK
>> 615 select CSRC_R4K
>> 616 select BOOT_RAW
>> 617 select DMA_NONCOHERENT
>> 618 select IRQ_MIPS_CPU
>> 619 select USE_OF
>> 620 select SYS_HAS_CPU_MIPS32_R1
>> 621 select SYS_HAS_CPU_MIPS32_R2
>> 622 select SYS_SUPPORTS_32BIT_KERNEL
>> 623 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 624 select SYS_SUPPORTS_MIPS16
>> 625 select SYS_SUPPORTS_ZBOOT
>> 626 select SYS_HAS_EARLY_PRINTK
>> 627 select ARCH_HAS_RESET_CONTROLLER
>> 628 select RESET_CONTROLLER
>> 629
>> 630 config MACH_REALTEK_RTL
>> 631 bool "Realtek RTL838x/RTL839x based machines"
>> 632 select MIPS_GENERIC
>> 633 select DMA_NONCOHERENT
>> 634 select IRQ_MIPS_CPU
>> 635 select CSRC_R4K
>> 636 select CEVT_R4K
>> 637 select SYS_HAS_CPU_MIPS32_R1
>> 638 select SYS_HAS_CPU_MIPS32_R2
>> 639 select SYS_SUPPORTS_BIG_ENDIAN
>> 640 select SYS_SUPPORTS_32BIT_KERNEL
>> 641 select SYS_SUPPORTS_MIPS16
>> 642 select SYS_SUPPORTS_MULTITHREADING
>> 643 select SYS_SUPPORTS_VPE_LOADER
>> 644 select BOOT_RAW
>> 645 select PINCTRL
>> 646 select USE_OF
>> 647
>> 648 config SGI_IP22
>> 649 bool "SGI IP22 (Indy/Indigo2)"
>> 650 select ARC_MEMORY
>> 651 select ARC_PROMLIB
>> 652 select FW_ARC
>> 653 select FW_ARC32
>> 654 select ARCH_MIGHT_HAVE_PC_SERIO
>> 655 select BOOT_ELF32
>> 656 select CEVT_R4K
>> 657 select CSRC_R4K
>> 658 select DEFAULT_SGI_PARTITION
>> 659 select DMA_NONCOHERENT
>> 660 select HAVE_EISA
>> 661 select I8253
>> 662 select I8259
>> 663 select IP22_CPU_SCACHE
>> 664 select IRQ_MIPS_CPU
>> 665 select GENERIC_ISA_DMA_SUPPORT_BROKEN
>> 666 select SGI_HAS_I8042
>> 667 select SGI_HAS_INDYDOG
>> 668 select SGI_HAS_HAL2
>> 669 select SGI_HAS_SEEQ
>> 670 select SGI_HAS_WD93
>> 671 select SGI_HAS_ZILOG
>> 672 select SWAP_IO_SPACE
>> 673 select SYS_HAS_CPU_R4X00
>> 674 select SYS_HAS_CPU_R5000
>> 675 select SYS_HAS_EARLY_PRINTK
>> 676 select SYS_SUPPORTS_32BIT_KERNEL
>> 677 select SYS_SUPPORTS_64BIT_KERNEL
>> 678 select SYS_SUPPORTS_BIG_ENDIAN
>> 679 select WAR_R4600_V1_INDEX_ICACHEOP
>> 680 select WAR_R4600_V1_HIT_CACHEOP
>> 681 select WAR_R4600_V2_HIT_CACHEOP
>> 682 select MIPS_L1_CACHE_SHIFT_7
>> 683 help
>> 684 This are the SGI Indy, Challenge S and Indigo2, as well as certain
>> 685 OEM variants like the Tandem CMN B006S. To compile a Linux kernel
>> 686 that runs on these, say Y here.
>> 687
>> 688 config SGI_IP27
>> 689 bool "SGI IP27 (Origin200/2000)"
>> 690 select ARCH_HAS_PHYS_TO_DMA
>> 691 select ARCH_SPARSEMEM_ENABLE
>> 692 select FW_ARC
>> 693 select FW_ARC64
>> 694 select ARC_CMDLINE_ONLY
>> 695 select BOOT_ELF64
>> 696 select DEFAULT_SGI_PARTITION
>> 697 select FORCE_PCI
>> 698 select SYS_HAS_EARLY_PRINTK
>> 699 select HAVE_PCI
>> 700 select IRQ_MIPS_CPU
>> 701 select IRQ_DOMAIN_HIERARCHY
>> 702 select NR_CPUS_DEFAULT_64
>> 703 select PCI_DRIVERS_GENERIC
>> 704 select PCI_XTALK_BRIDGE
>> 705 select SYS_HAS_CPU_R10000
>> 706 select SYS_SUPPORTS_64BIT_KERNEL
>> 707 select SYS_SUPPORTS_BIG_ENDIAN
>> 708 select SYS_SUPPORTS_NUMA
>> 709 select SYS_SUPPORTS_SMP
>> 710 select WAR_R10000_LLSC
>> 711 select MIPS_L1_CACHE_SHIFT_7
>> 712 select NUMA
>> 713 select HAVE_ARCH_NODEDATA_EXTENSION
>> 714 help
>> 715 This are the SGI Origin 200, Origin 2000 and Onyx 2 Graphics
>> 716 workstations. To compile a Linux kernel that runs on these, say Y
>> 717 here.
>> 718
>> 719 config SGI_IP28
>> 720 bool "SGI IP28 (Indigo2 R10k)"
>> 721 select ARC_MEMORY
>> 722 select ARC_PROMLIB
>> 723 select FW_ARC
>> 724 select FW_ARC64
>> 725 select ARCH_MIGHT_HAVE_PC_SERIO
>> 726 select BOOT_ELF64
>> 727 select CEVT_R4K
>> 728 select CSRC_R4K
>> 729 select DEFAULT_SGI_PARTITION
>> 730 select DMA_NONCOHERENT
>> 731 select GENERIC_ISA_DMA_SUPPORT_BROKEN
>> 732 select IRQ_MIPS_CPU
>> 733 select HAVE_EISA
>> 734 select I8253
>> 735 select I8259
>> 736 select SGI_HAS_I8042
>> 737 select SGI_HAS_INDYDOG
>> 738 select SGI_HAS_HAL2
>> 739 select SGI_HAS_SEEQ
>> 740 select SGI_HAS_WD93
>> 741 select SGI_HAS_ZILOG
>> 742 select SWAP_IO_SPACE
>> 743 select SYS_HAS_CPU_R10000
>> 744 select SYS_HAS_EARLY_PRINTK
>> 745 select SYS_SUPPORTS_64BIT_KERNEL
>> 746 select SYS_SUPPORTS_BIG_ENDIAN
>> 747 select WAR_R10000_LLSC
>> 748 select MIPS_L1_CACHE_SHIFT_7
>> 749 help
>> 750 This is the SGI Indigo2 with R10000 processor. To compile a Linux
>> 751 kernel that runs on these, say Y here.
>> 752
>> 753 config SGI_IP30
>> 754 bool "SGI IP30 (Octane/Octane2)"
>> 755 select ARCH_HAS_PHYS_TO_DMA
>> 756 select FW_ARC
>> 757 select FW_ARC64
>> 758 select BOOT_ELF64
>> 759 select CEVT_R4K
>> 760 select CSRC_R4K
>> 761 select FORCE_PCI
>> 762 select SYNC_R4K if SMP
>> 763 select ZONE_DMA32
>> 764 select HAVE_PCI
>> 765 select IRQ_MIPS_CPU
>> 766 select IRQ_DOMAIN_HIERARCHY
>> 767 select PCI_DRIVERS_GENERIC
>> 768 select PCI_XTALK_BRIDGE
>> 769 select SYS_HAS_EARLY_PRINTK
>> 770 select SYS_HAS_CPU_R10000
>> 771 select SYS_SUPPORTS_64BIT_KERNEL
>> 772 select SYS_SUPPORTS_BIG_ENDIAN
>> 773 select SYS_SUPPORTS_SMP
>> 774 select WAR_R10000_LLSC
>> 775 select MIPS_L1_CACHE_SHIFT_7
>> 776 select ARC_MEMORY
>> 777 help
>> 778 These are the SGI Octane and Octane2 graphics workstations. To
>> 779 compile a Linux kernel that runs on these, say Y here.
>> 780
>> 781 config SGI_IP32
>> 782 bool "SGI IP32 (O2)"
>> 783 select ARC_MEMORY
>> 784 select ARC_PROMLIB
>> 785 select ARCH_HAS_PHYS_TO_DMA
>> 786 select FW_ARC
>> 787 select FW_ARC32
>> 788 select BOOT_ELF32
>> 789 select CEVT_R4K
>> 790 select CSRC_R4K
>> 791 select DMA_NONCOHERENT
>> 792 select HAVE_PCI
>> 793 select IRQ_MIPS_CPU
>> 794 select R5000_CPU_SCACHE
>> 795 select RM7000_CPU_SCACHE
>> 796 select SYS_HAS_CPU_R5000
>> 797 select SYS_HAS_CPU_R10000 if BROKEN
>> 798 select SYS_HAS_CPU_RM7000
>> 799 select SYS_HAS_CPU_NEVADA
>> 800 select SYS_SUPPORTS_64BIT_KERNEL
>> 801 select SYS_SUPPORTS_BIG_ENDIAN
>> 802 select WAR_ICACHE_REFILLS
>> 803 help
>> 804 If you want this kernel to run on SGI O2 workstation, say Y here.
>> 805
>> 806 config SIBYTE_CRHINE
>> 807 bool "Sibyte BCM91120C-CRhine"
>> 808 select BOOT_ELF32
>> 809 select SIBYTE_BCM1120
>> 810 select SWAP_IO_SPACE
>> 811 select SYS_HAS_CPU_SB1
>> 812 select SYS_SUPPORTS_BIG_ENDIAN
>> 813 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 814
>> 815 config SIBYTE_CARMEL
>> 816 bool "Sibyte BCM91120x-Carmel"
>> 817 select BOOT_ELF32
>> 818 select SIBYTE_BCM1120
>> 819 select SWAP_IO_SPACE
>> 820 select SYS_HAS_CPU_SB1
>> 821 select SYS_SUPPORTS_BIG_ENDIAN
>> 822 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 823
>> 824 config SIBYTE_CRHONE
>> 825 bool "Sibyte BCM91125C-CRhone"
>> 826 select BOOT_ELF32
>> 827 select SIBYTE_BCM1125
>> 828 select SWAP_IO_SPACE
>> 829 select SYS_HAS_CPU_SB1
>> 830 select SYS_SUPPORTS_BIG_ENDIAN
>> 831 select SYS_SUPPORTS_HIGHMEM
>> 832 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 833
>> 834 config SIBYTE_RHONE
>> 835 bool "Sibyte BCM91125E-Rhone"
>> 836 select BOOT_ELF32
>> 837 select SIBYTE_BCM1125H
>> 838 select SWAP_IO_SPACE
>> 839 select SYS_HAS_CPU_SB1
>> 840 select SYS_SUPPORTS_BIG_ENDIAN
>> 841 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 842
>> 843 config SIBYTE_SWARM
>> 844 bool "Sibyte BCM91250A-SWARM"
>> 845 select BOOT_ELF32
>> 846 select HAVE_PATA_PLATFORM
>> 847 select SIBYTE_SB1250
>> 848 select SWAP_IO_SPACE
>> 849 select SYS_HAS_CPU_SB1
>> 850 select SYS_SUPPORTS_BIG_ENDIAN
>> 851 select SYS_SUPPORTS_HIGHMEM
>> 852 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 853 select ZONE_DMA32 if 64BIT
>> 854 select SWIOTLB if ARCH_DMA_ADDR_T_64BIT && PCI
>> 855
>> 856 config SIBYTE_LITTLESUR
>> 857 bool "Sibyte BCM91250C2-LittleSur"
>> 858 select BOOT_ELF32
>> 859 select HAVE_PATA_PLATFORM
>> 860 select SIBYTE_SB1250
>> 861 select SWAP_IO_SPACE
>> 862 select SYS_HAS_CPU_SB1
>> 863 select SYS_SUPPORTS_BIG_ENDIAN
>> 864 select SYS_SUPPORTS_HIGHMEM
>> 865 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 866 select ZONE_DMA32 if 64BIT
>> 867
>> 868 config SIBYTE_SENTOSA
>> 869 bool "Sibyte BCM91250E-Sentosa"
>> 870 select BOOT_ELF32
>> 871 select SIBYTE_SB1250
>> 872 select SWAP_IO_SPACE
>> 873 select SYS_HAS_CPU_SB1
>> 874 select SYS_SUPPORTS_BIG_ENDIAN
>> 875 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 876 select SWIOTLB if ARCH_DMA_ADDR_T_64BIT && PCI
>> 877
>> 878 config SIBYTE_BIGSUR
>> 879 bool "Sibyte BCM91480B-BigSur"
>> 880 select BOOT_ELF32
>> 881 select NR_CPUS_DEFAULT_4
>> 882 select SIBYTE_BCM1x80
>> 883 select SWAP_IO_SPACE
>> 884 select SYS_HAS_CPU_SB1
>> 885 select SYS_SUPPORTS_BIG_ENDIAN
>> 886 select SYS_SUPPORTS_HIGHMEM
>> 887 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 888 select ZONE_DMA32 if 64BIT
>> 889 select SWIOTLB if ARCH_DMA_ADDR_T_64BIT && PCI
>> 890
>> 891 config SNI_RM
>> 892 bool "SNI RM200/300/400"
>> 893 select ARC_MEMORY
>> 894 select ARC_PROMLIB
>> 895 select FW_ARC if CPU_LITTLE_ENDIAN
>> 896 select FW_ARC32 if CPU_LITTLE_ENDIAN
>> 897 select FW_SNIPROM if CPU_BIG_ENDIAN
>> 898 select ARCH_MAY_HAVE_PC_FDC
>> 899 select ARCH_MIGHT_HAVE_PC_PARPORT
>> 900 select ARCH_MIGHT_HAVE_PC_SERIO
>> 901 select BOOT_ELF32
>> 902 select CEVT_R4K
>> 903 select CSRC_R4K
>> 904 select DEFAULT_SGI_PARTITION if CPU_BIG_ENDIAN
>> 905 select DMA_NONCOHERENT
>> 906 select GENERIC_ISA_DMA
>> 907 select HAVE_EISA
>> 908 select HAVE_PCSPKR_PLATFORM
>> 909 select HAVE_PCI
>> 910 select IRQ_MIPS_CPU
>> 911 select I8253
>> 912 select I8259
>> 913 select ISA
>> 914 select MIPS_L1_CACHE_SHIFT_6
>> 915 select SWAP_IO_SPACE if CPU_BIG_ENDIAN
>> 916 select SYS_HAS_CPU_R4X00
>> 917 select SYS_HAS_CPU_R5000
>> 918 select SYS_HAS_CPU_R10000
>> 919 select R5000_CPU_SCACHE
>> 920 select SYS_HAS_EARLY_PRINTK
>> 921 select SYS_SUPPORTS_32BIT_KERNEL
>> 922 select SYS_SUPPORTS_64BIT_KERNEL
>> 923 select SYS_SUPPORTS_BIG_ENDIAN
>> 924 select SYS_SUPPORTS_HIGHMEM
>> 925 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 926 select WAR_R4600_V2_HIT_CACHEOP
>> 927 help
>> 928 The SNI RM200/300/400 are MIPS-based machines manufactured by
>> 929 Siemens Nixdorf Informationssysteme (SNI), parent company of Pyramid
>> 930 Technology and now in turn merged with Fujitsu. Say Y here to
>> 931 support this machine type.
>> 932
>> 933 config MACH_TX49XX
>> 934 bool "Toshiba TX49 series based machines"
>> 935 select WAR_TX49XX_ICACHE_INDEX_INV
>> 936
>> 937 config MIKROTIK_RB532
>> 938 bool "Mikrotik RB532 boards"
>> 939 select CEVT_R4K
>> 940 select CSRC_R4K
>> 941 select DMA_NONCOHERENT
>> 942 select HAVE_PCI
>> 943 select IRQ_MIPS_CPU
>> 944 select SYS_HAS_CPU_MIPS32_R1
>> 945 select SYS_SUPPORTS_32BIT_KERNEL
>> 946 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 947 select SWAP_IO_SPACE
>> 948 select BOOT_RAW
>> 949 select GPIOLIB
>> 950 select MIPS_L1_CACHE_SHIFT_4
>> 951 help
>> 952 Support the Mikrotik(tm) RouterBoard 532 series,
>> 953 based on the IDT RC32434 SoC.
>> 954
>> 955 config CAVIUM_OCTEON_SOC
>> 956 bool "Cavium Networks Octeon SoC based boards"
>> 957 select CEVT_R4K
>> 958 select ARCH_HAS_PHYS_TO_DMA
>> 959 select HAVE_RAPIDIO
>> 960 select PHYS_ADDR_T_64BIT
>> 961 select SYS_SUPPORTS_64BIT_KERNEL
>> 962 select SYS_SUPPORTS_BIG_ENDIAN
>> 963 select EDAC_SUPPORT
>> 964 select EDAC_ATOMIC_SCRUB
>> 965 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 966 select SYS_SUPPORTS_HOTPLUG_CPU if CPU_BIG_ENDIAN
>> 967 select SYS_HAS_EARLY_PRINTK
>> 968 select SYS_HAS_CPU_CAVIUM_OCTEON
>> 969 select HAVE_PCI
>> 970 select HAVE_PLAT_DELAY
>> 971 select HAVE_PLAT_FW_INIT_CMDLINE
>> 972 select HAVE_PLAT_MEMCPY
>> 973 select ZONE_DMA32
>> 974 select GPIOLIB
>> 975 select USE_OF
>> 976 select ARCH_SPARSEMEM_ENABLE
>> 977 select SYS_SUPPORTS_SMP
>> 978 select NR_CPUS_DEFAULT_64
>> 979 select MIPS_NR_CPU_NR_MAP_1024
>> 980 select BUILTIN_DTB
>> 981 select MTD
>> 982 select MTD_COMPLEX_MAPPINGS
>> 983 select SWIOTLB
>> 984 select SYS_SUPPORTS_RELOCATABLE
>> 985 help
>> 986 This option supports all of the Octeon reference boards from Cavium
>> 987 Networks. It builds a kernel that dynamically determines the Octeon
>> 988 CPU type and supports all known board reference implementations.
>> 989 Some of the supported boards are:
>> 990 EBT3000
>> 991 EBH3000
>> 992 EBH3100
>> 993 Thunder
>> 994 Kodama
>> 995 Hikari
>> 996 Say Y here for most Octeon reference boards.
349 997
350 config LOCKDEP_SUPPORT !! 998 endchoice
351 def_bool y <<
352 999
353 config GENERIC_BUG !! 1000 source "arch/mips/alchemy/Kconfig"
354 def_bool y !! 1001 source "arch/mips/ath25/Kconfig"
355 depends on BUG !! 1002 source "arch/mips/ath79/Kconfig"
>> 1003 source "arch/mips/bcm47xx/Kconfig"
>> 1004 source "arch/mips/bcm63xx/Kconfig"
>> 1005 source "arch/mips/bmips/Kconfig"
>> 1006 source "arch/mips/generic/Kconfig"
>> 1007 source "arch/mips/ingenic/Kconfig"
>> 1008 source "arch/mips/jazz/Kconfig"
>> 1009 source "arch/mips/lantiq/Kconfig"
>> 1010 source "arch/mips/pic32/Kconfig"
>> 1011 source "arch/mips/ralink/Kconfig"
>> 1012 source "arch/mips/sgi-ip27/Kconfig"
>> 1013 source "arch/mips/sibyte/Kconfig"
>> 1014 source "arch/mips/txx9/Kconfig"
>> 1015 source "arch/mips/vr41xx/Kconfig"
>> 1016 source "arch/mips/cavium-octeon/Kconfig"
>> 1017 source "arch/mips/loongson2ef/Kconfig"
>> 1018 source "arch/mips/loongson32/Kconfig"
>> 1019 source "arch/mips/loongson64/Kconfig"
356 1020
357 config GENERIC_BUG_RELATIVE_POINTERS !! 1021 endmenu
358 def_bool y <<
359 depends on GENERIC_BUG <<
360 1022
361 config GENERIC_HWEIGHT 1023 config GENERIC_HWEIGHT
362 def_bool y !! 1024 bool
363 !! 1025 default y
364 config GENERIC_CSUM <<
365 def_bool y <<
366 1026
367 config GENERIC_CALIBRATE_DELAY 1027 config GENERIC_CALIBRATE_DELAY
368 def_bool y !! 1028 bool
>> 1029 default y
369 1030
370 config SMP !! 1031 config SCHED_OMIT_FRAME_POINTER
371 def_bool y !! 1032 bool
>> 1033 default y
372 1034
373 config KERNEL_MODE_NEON !! 1035 #
374 def_bool y !! 1036 # Select some configuration options automatically based on user selections.
>> 1037 #
>> 1038 config FW_ARC
>> 1039 bool
375 1040
376 config FIX_EARLYCON_MEM !! 1041 config ARCH_MAY_HAVE_PC_FDC
377 def_bool y !! 1042 bool
378 1043
379 config PGTABLE_LEVELS !! 1044 config BOOT_RAW
380 int !! 1045 bool
381 default 2 if ARM64_16K_PAGES && ARM64_ <<
382 default 2 if ARM64_64K_PAGES && ARM64_ <<
383 default 3 if ARM64_64K_PAGES && (ARM64 <<
384 default 3 if ARM64_4K_PAGES && ARM64_V <<
385 default 3 if ARM64_16K_PAGES && ARM64_ <<
386 default 4 if ARM64_16K_PAGES && (ARM64 <<
387 default 4 if !ARM64_64K_PAGES && ARM64 <<
388 default 5 if ARM64_4K_PAGES && ARM64_V <<
389 1046
390 config ARCH_SUPPORTS_UPROBES !! 1047 config CEVT_BCM1480
391 def_bool y !! 1048 bool
392 1049
393 config ARCH_PROC_KCORE_TEXT !! 1050 config CEVT_DS1287
394 def_bool y !! 1051 bool
395 1052
396 config BROKEN_GAS_INST !! 1053 config CEVT_GT641XX
397 def_bool !$(as-instr,1:\n.inst 0\n.rep !! 1054 bool
398 1055
399 config BUILTIN_RETURN_ADDRESS_STRIPS_PAC !! 1056 config CEVT_R4K
400 bool 1057 bool
401 # Clang's __builtin_return_address() s <<
402 # https://github.com/llvm/llvm-project <<
403 default y if CC_IS_CLANG <<
404 # GCC's __builtin_return_address() str <<
405 # and this was backported to 10.2.0, 9 <<
406 # https://gcc.gnu.org/bugzilla/show_bu <<
407 default y if CC_IS_GCC && (GCC_VERSION <<
408 default y if CC_IS_GCC && (GCC_VERSION <<
409 default y if CC_IS_GCC && (GCC_VERSION <<
410 default y if CC_IS_GCC && (GCC_VERSION <<
411 default n <<
412 1058
413 config KASAN_SHADOW_OFFSET !! 1059 config CEVT_SB1250
414 hex <<
415 depends on KASAN_GENERIC || KASAN_SW_T <<
416 default 0xdfff800000000000 if (ARM64_V <<
417 default 0xdfffc00000000000 if (ARM64_V <<
418 default 0xdffffe0000000000 if ARM64_VA <<
419 default 0xdfffffc000000000 if ARM64_VA <<
420 default 0xdffffff800000000 if ARM64_VA <<
421 default 0xefff800000000000 if (ARM64_V <<
422 default 0xefffc00000000000 if (ARM64_V <<
423 default 0xeffffe0000000000 if ARM64_VA <<
424 default 0xefffffc000000000 if ARM64_VA <<
425 default 0xeffffff800000000 if ARM64_VA <<
426 default 0xffffffffffffffff <<
427 <<
428 config UNWIND_TABLES <<
429 bool 1060 bool
430 1061
431 source "arch/arm64/Kconfig.platforms" !! 1062 config CEVT_TXX9
>> 1063 bool
432 1064
433 menu "Kernel Features" !! 1065 config CSRC_BCM1480
>> 1066 bool
434 1067
435 menu "ARM errata workarounds via the alternati !! 1068 config CSRC_IOASIC
>> 1069 bool
436 1070
437 config AMPERE_ERRATUM_AC03_CPU_38 !! 1071 config CSRC_R4K
438 bool "AmpereOne: AC03_CPU_38: Certain !! 1072 select CLOCKSOURCE_WATCHDOG if CPU_FREQ
439 default y !! 1073 bool
440 help <<
441 This option adds an alternative code <<
442 errata AC03_CPU_38 and AC04_CPU_10 o <<
443 1074
444 The affected design reports FEAT_HAF !! 1075 config CSRC_SB1250
445 ID_AA64MMFR1_EL1.HAFDBS, but (V)TCR_ !! 1076 bool
446 as required by the architecture. The <<
447 implementation suffers from an addit <<
448 A/D updates can occur after a PTE ha <<
449 <<
450 The workaround forces KVM to explici <<
451 which avoids enabling unadvertised h <<
452 at stage-2. <<
453 1077
454 If unsure, say Y. !! 1078 config MIPS_CLOCK_VSYSCALL
>> 1079 def_bool CSRC_R4K || CLKSRC_MIPS_GIC
455 1080
456 config ARM64_WORKAROUND_CLEAN_CACHE !! 1081 config GPIO_TXX9
>> 1082 select GPIOLIB
457 bool 1083 bool
458 1084
459 config ARM64_ERRATUM_826319 !! 1085 config FW_CFE
460 bool "Cortex-A53: 826319: System might !! 1086 bool
461 default y <<
462 select ARM64_WORKAROUND_CLEAN_CACHE <<
463 help <<
464 This option adds an alternative code <<
465 erratum 826319 on Cortex-A53 parts u <<
466 AXI master interface and an L2 cache <<
467 <<
468 If a Cortex-A53 uses an AMBA AXI4 AC <<
469 and is unable to accept a certain wr <<
470 not progress on read data presented <<
471 system can deadlock. <<
472 <<
473 The workaround promotes data cache c <<
474 data cache clean-and-invalidate. <<
475 Please note that this does not neces <<
476 as it depends on the alternative fra <<
477 the kernel if an affected CPU is det <<
478 1087
479 If unsure, say Y. !! 1088 config ARCH_SUPPORTS_UPROBES
>> 1089 bool
480 1090
481 config ARM64_ERRATUM_827319 !! 1091 config DMA_PERDEV_COHERENT
482 bool "Cortex-A53: 827319: Data cache c !! 1092 bool
483 default y !! 1093 select ARCH_HAS_SETUP_DMA_OPS
484 select ARM64_WORKAROUND_CLEAN_CACHE !! 1094 select DMA_NONCOHERENT
485 help <<
486 This option adds an alternative code <<
487 erratum 827319 on Cortex-A53 parts u <<
488 master interface and an L2 cache. <<
489 <<
490 Under certain conditions this erratu <<
491 to occur at the same time as another <<
492 on the AMBA 5 CHI interface, which c <<
493 interconnect reorders the two transa <<
494 <<
495 The workaround promotes data cache c <<
496 data cache clean-and-invalidate. <<
497 Please note that this does not neces <<
498 as it depends on the alternative fra <<
499 the kernel if an affected CPU is det <<
500 1095
501 If unsure, say Y. !! 1096 config DMA_NONCOHERENT
>> 1097 bool
>> 1098 #
>> 1099 # MIPS allows mixing "slightly different" Cacheability and Coherency
>> 1100 # Attribute bits. It is believed that the uncached access through
>> 1101 # KSEG1 and the implementation specific "uncached accelerated" used
>> 1102 # by pgprot_writcombine can be mixed, and the latter sometimes provides
>> 1103 # significant advantages.
>> 1104 #
>> 1105 select ARCH_HAS_DMA_WRITE_COMBINE
>> 1106 select ARCH_HAS_DMA_PREP_COHERENT
>> 1107 select ARCH_HAS_SYNC_DMA_FOR_DEVICE
>> 1108 select ARCH_HAS_DMA_SET_UNCACHED
>> 1109 select DMA_NONCOHERENT_MMAP
>> 1110 select NEED_DMA_MAP_STATE
502 1111
503 config ARM64_ERRATUM_824069 !! 1112 config SYS_HAS_EARLY_PRINTK
504 bool "Cortex-A53: 824069: Cache line m !! 1113 bool
505 default y <<
506 select ARM64_WORKAROUND_CLEAN_CACHE <<
507 help <<
508 This option adds an alternative code <<
509 erratum 824069 on Cortex-A53 parts u <<
510 to a coherent interconnect. <<
511 <<
512 If a Cortex-A53 processor is executi <<
513 write instruction at the same time a <<
514 cluster is executing a cache mainten <<
515 address, then this erratum might cau <<
516 incorrectly marked as dirty. <<
517 <<
518 The workaround promotes data cache c <<
519 data cache clean-and-invalidate. <<
520 Please note that this option does no <<
521 workaround, as it depends on the alt <<
522 only patch the kernel if an affected <<
523 1114
524 If unsure, say Y. !! 1115 config SYS_SUPPORTS_HOTPLUG_CPU
>> 1116 bool
525 1117
526 config ARM64_ERRATUM_819472 !! 1118 config MIPS_BONITO64
527 bool "Cortex-A53: 819472: Store exclus !! 1119 bool
528 default y <<
529 select ARM64_WORKAROUND_CLEAN_CACHE <<
530 help <<
531 This option adds an alternative code <<
532 erratum 819472 on Cortex-A53 parts u <<
533 present when it is connected to a co <<
534 <<
535 If the processor is executing a load <<
536 the same time as a processor in anot <<
537 maintenance operation to the same ad <<
538 cause data corruption. <<
539 <<
540 The workaround promotes data cache c <<
541 data cache clean-and-invalidate. <<
542 Please note that this does not neces <<
543 as it depends on the alternative fra <<
544 the kernel if an affected CPU is det <<
545 1120
546 If unsure, say Y. !! 1121 config MIPS_MSC
>> 1122 bool
547 1123
548 config ARM64_ERRATUM_832075 !! 1124 config SYNC_R4K
549 bool "Cortex-A57: 832075: possible dea !! 1125 bool
550 default y <<
551 help <<
552 This option adds an alternative code <<
553 erratum 832075 on Cortex-A57 parts u <<
554 1126
555 Affected Cortex-A57 parts might dead !! 1127 config NO_IOPORT_MAP
556 instructions to Write-Back memory ar !! 1128 def_bool n
557 1129
558 The workaround is to promote device !! 1130 config GENERIC_CSUM
559 semantics. !! 1131 def_bool CPU_NO_LOAD_STORE_LR
560 Please note that this does not neces <<
561 as it depends on the alternative fra <<
562 the kernel if an affected CPU is det <<
563 1132
564 If unsure, say Y. !! 1133 config GENERIC_ISA_DMA
>> 1134 bool
>> 1135 select ZONE_DMA if GENERIC_ISA_DMA_SUPPORT_BROKEN=n
>> 1136 select ISA_DMA_API
565 1137
566 config ARM64_ERRATUM_834220 !! 1138 config GENERIC_ISA_DMA_SUPPORT_BROKEN
567 bool "Cortex-A57: 834220: Stage 2 tran !! 1139 bool
568 depends on KVM !! 1140 select GENERIC_ISA_DMA
569 help <<
570 This option adds an alternative code <<
571 erratum 834220 on Cortex-A57 parts u <<
572 <<
573 Affected Cortex-A57 parts might repo <<
574 fault as the result of a Stage 1 fau <<
575 page boundary when there is a permis <<
576 alignment fault at Stage 1 and a tra <<
577 <<
578 The workaround is to verify that the <<
579 doesn't generate a fault before hand <<
580 Please note that this does not neces <<
581 as it depends on the alternative fra <<
582 the kernel if an affected CPU is det <<
583 1141
584 If unsure, say N. !! 1142 config HAVE_PLAT_DELAY
>> 1143 bool
585 1144
586 config ARM64_ERRATUM_1742098 !! 1145 config HAVE_PLAT_FW_INIT_CMDLINE
587 bool "Cortex-A57/A72: 1742098: ELR rec !! 1146 bool
588 depends on COMPAT <<
589 default y <<
590 help <<
591 This option removes the AES hwcap fo <<
592 workaround erratum 1742098 on Cortex <<
593 1147
594 Affected parts may corrupt the AES s !! 1148 config HAVE_PLAT_MEMCPY
595 taken between a pair of AES instruct !! 1149 bool
596 are only present if the cryptography <<
597 All software should have a fallback <<
598 that don't implement the cryptograph <<
599 1150
600 If unsure, say Y. !! 1151 config ISA_DMA_API
>> 1152 bool
601 1153
602 config ARM64_ERRATUM_845719 !! 1154 config SYS_SUPPORTS_RELOCATABLE
603 bool "Cortex-A53: 845719: a load might !! 1155 bool
604 depends on COMPAT <<
605 default y <<
606 help 1156 help
607 This option adds an alternative code !! 1157 Selected if the platform supports relocating the kernel.
608 erratum 845719 on Cortex-A53 parts u !! 1158 The platform must provide plat_get_fdt() if it selects CONFIG_USE_OF
609 !! 1159 to allow access to command line and entropy sources.
610 When running a compat (AArch32) user <<
611 part, a load at EL0 from a virtual a <<
612 bits of the virtual address used by <<
613 might return incorrect data. <<
614 <<
615 The workaround is to write the conte <<
616 return to a 32-bit task. <<
617 Please note that this does not neces <<
618 as it depends on the alternative fra <<
619 the kernel if an affected CPU is det <<
620 <<
621 If unsure, say Y. <<
622 1160
623 config ARM64_ERRATUM_843419 !! 1161 #
624 bool "Cortex-A53: 843419: A load or st !! 1162 # Endianness selection. Sufficiently obscure so many users don't know what to
625 default y !! 1163 # answer,so we try hard to limit the available choices. Also the use of a
>> 1164 # choice statement should be more obvious to the user.
>> 1165 #
>> 1166 choice
>> 1167 prompt "Endianness selection"
626 help 1168 help
627 This option links the kernel with '- !! 1169 Some MIPS machines can be configured for either little or big endian
628 enables PLT support to replace certa !! 1170 byte order. These modes require different kernels and a different
629 cause subsequent memory accesses to !! 1171 Linux distribution. In general there is one preferred byteorder for a
630 Cortex-A53 parts up to r0p4. !! 1172 particular system but some systems are just as commonly used in the
>> 1173 one or the other endianness.
631 1174
632 If unsure, say Y. !! 1175 config CPU_BIG_ENDIAN
>> 1176 bool "Big endian"
>> 1177 depends on SYS_SUPPORTS_BIG_ENDIAN
633 1178
634 config ARM64_LD_HAS_FIX_ERRATUM_843419 !! 1179 config CPU_LITTLE_ENDIAN
635 def_bool $(ld-option,--fix-cortex-a53- !! 1180 bool "Little endian"
>> 1181 depends on SYS_SUPPORTS_LITTLE_ENDIAN
636 1182
637 config ARM64_ERRATUM_1024718 !! 1183 endchoice
638 bool "Cortex-A55: 1024718: Update of D <<
639 default y <<
640 help <<
641 This option adds a workaround for AR <<
642 1184
643 Affected Cortex-A55 cores (all revis !! 1185 config EXPORT_UASM
644 update of the hardware dirty bit whe !! 1186 bool
645 without a break-before-make. The wor <<
646 of hardware DBM locally on the affec <<
647 this erratum will continue to use th <<
648 1187
649 If unsure, say Y. !! 1188 config SYS_SUPPORTS_APM_EMULATION
>> 1189 bool
650 1190
651 config ARM64_ERRATUM_1418040 !! 1191 config SYS_SUPPORTS_BIG_ENDIAN
652 bool "Cortex-A76/Neoverse-N1: MRC read !! 1192 bool
653 default y <<
654 depends on COMPAT <<
655 help <<
656 This option adds a workaround for AR <<
657 errata 1188873 and 1418040. <<
658 1193
659 Affected Cortex-A76/Neoverse-N1 core !! 1194 config SYS_SUPPORTS_LITTLE_ENDIAN
660 cause register corruption when acces !! 1195 bool
661 from AArch32 userspace. <<
662 1196
663 If unsure, say Y. !! 1197 config MIPS_HUGE_TLB_SUPPORT
>> 1198 def_bool HUGETLB_PAGE || TRANSPARENT_HUGEPAGE
664 1199
665 config ARM64_WORKAROUND_SPECULATIVE_AT !! 1200 config IRQ_MSP_SLP
666 bool 1201 bool
667 1202
668 config ARM64_ERRATUM_1165522 !! 1203 config IRQ_MSP_CIC
669 bool "Cortex-A76: 1165522: Speculative !! 1204 bool
670 default y <<
671 select ARM64_WORKAROUND_SPECULATIVE_AT <<
672 help <<
673 This option adds a workaround for AR <<
674 <<
675 Affected Cortex-A76 cores (r0p0, r1p <<
676 corrupted TLBs by speculating an AT <<
677 context switch. <<
678 1205
679 If unsure, say Y. !! 1206 config IRQ_TXX9
>> 1207 bool
680 1208
681 config ARM64_ERRATUM_1319367 !! 1209 config IRQ_GT641XX
682 bool "Cortex-A57/A72: 1319537: Specula !! 1210 bool
683 default y <<
684 select ARM64_WORKAROUND_SPECULATIVE_AT <<
685 help <<
686 This option adds work arounds for AR <<
687 and A72 erratum 1319367 <<
688 1211
689 Cortex-A57 and A72 cores could end-u !! 1212 config PCI_GT64XXX_PCI0
690 speculating an AT instruction during !! 1213 bool
691 1214
692 If unsure, say Y. !! 1215 config PCI_XTALK_BRIDGE
>> 1216 bool
693 1217
694 config ARM64_ERRATUM_1530923 !! 1218 config NO_EXCEPT_FILL
695 bool "Cortex-A55: 1530923: Speculative !! 1219 bool
696 default y <<
697 select ARM64_WORKAROUND_SPECULATIVE_AT <<
698 help <<
699 This option adds a workaround for AR <<
700 1220
701 Affected Cortex-A55 cores (r0p0, r0p !! 1221 config MIPS_SPRAM
702 corrupted TLBs by speculating an AT !! 1222 bool
703 context switch. <<
704 1223
705 If unsure, say Y. !! 1224 config SWAP_IO_SPACE
>> 1225 bool
706 1226
707 config ARM64_WORKAROUND_REPEAT_TLBI !! 1227 config SGI_HAS_INDYDOG
708 bool 1228 bool
709 1229
710 config ARM64_ERRATUM_2441007 !! 1230 config SGI_HAS_HAL2
711 bool "Cortex-A55: Completion of affect !! 1231 bool
712 select ARM64_WORKAROUND_REPEAT_TLBI <<
713 help <<
714 This option adds a workaround for AR <<
715 1232
716 Under very rare circumstances, affec !! 1233 config SGI_HAS_SEEQ
717 may not handle a race between a brea !! 1234 bool
718 CPU, and another CPU accessing the s <<
719 store to a page that has been unmapp <<
720 1235
721 Work around this by adding the affec !! 1236 config SGI_HAS_WD93
722 TLB sequences to be done twice. !! 1237 bool
723 1238
724 If unsure, say N. !! 1239 config SGI_HAS_ZILOG
>> 1240 bool
725 1241
726 config ARM64_ERRATUM_1286807 !! 1242 config SGI_HAS_I8042
727 bool "Cortex-A76: Modification of the !! 1243 bool
728 select ARM64_WORKAROUND_REPEAT_TLBI <<
729 help <<
730 This option adds a workaround for AR <<
731 <<
732 On the affected Cortex-A76 cores (r0 <<
733 address for a cacheable mapping of a <<
734 accessed by a core while another cor <<
735 address to a new physical page using <<
736 break-before-make sequence, then und <<
737 TLBI+DSB completes before a read usi <<
738 invalidated has been observed by oth <<
739 workaround repeats the TLBI+DSB oper <<
740 1244
741 If unsure, say N. !! 1245 config DEFAULT_SGI_PARTITION
>> 1246 bool
742 1247
743 config ARM64_ERRATUM_1463225 !! 1248 config FW_ARC32
744 bool "Cortex-A76: Software Step might !! 1249 bool
745 default y <<
746 help <<
747 This option adds a workaround for Ar <<
748 1250
749 On the affected Cortex-A76 cores (r0 !! 1251 config FW_SNIPROM
750 of a system call instruction (SVC) c !! 1252 bool
751 subsequent interrupts when software <<
752 exception handler of the system call <<
753 is enabled or VHE is in use. <<
754 <<
755 Work around the erratum by triggerin <<
756 when handling a system call from a t <<
757 in a VHE configuration of the kernel <<
758 1253
759 If unsure, say Y. !! 1254 config BOOT_ELF32
>> 1255 bool
760 1256
761 config ARM64_ERRATUM_1542419 !! 1257 config MIPS_L1_CACHE_SHIFT_4
762 bool "Neoverse-N1: workaround mis-orde !! 1258 bool
763 help <<
764 This option adds a workaround for AR <<
765 1542419. <<
766 1259
767 Affected Neoverse-N1 cores could exe !! 1260 config MIPS_L1_CACHE_SHIFT_5
768 modified by another CPU. The workaro !! 1261 bool
769 counterpart. <<
770 1262
771 Workaround the issue by hiding the D !! 1263 config MIPS_L1_CACHE_SHIFT_6
772 forces user-space to perform cache m !! 1264 bool
773 1265
774 If unsure, say N. !! 1266 config MIPS_L1_CACHE_SHIFT_7
>> 1267 bool
775 1268
776 config ARM64_ERRATUM_1508412 !! 1269 config MIPS_L1_CACHE_SHIFT
777 bool "Cortex-A77: 1508412: workaround !! 1270 int
778 default y !! 1271 default "7" if MIPS_L1_CACHE_SHIFT_7
779 help !! 1272 default "6" if MIPS_L1_CACHE_SHIFT_6
780 This option adds a workaround for Ar !! 1273 default "5" if MIPS_L1_CACHE_SHIFT_5
>> 1274 default "4" if MIPS_L1_CACHE_SHIFT_4
>> 1275 default "5"
781 1276
782 Affected Cortex-A77 cores (r0p0, r1p !! 1277 config ARC_CMDLINE_ONLY
783 of a store-exclusive or read of PAR_ !! 1278 bool
784 non-cacheable memory attributes. The <<
785 counterpart. <<
786 <<
787 KVM guests must also have the workar <<
788 deadlock the system. <<
789 <<
790 Work around the issue by inserting D <<
791 register reads and warning KVM users <<
792 to prevent a speculative PAR_EL1 rea <<
793 1279
794 If unsure, say Y. !! 1280 config ARC_CONSOLE
>> 1281 bool "ARC console support"
>> 1282 depends on SGI_IP22 || SGI_IP28 || (SNI_RM && CPU_LITTLE_ENDIAN)
795 1283
796 config ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MO !! 1284 config ARC_MEMORY
797 bool 1285 bool
798 1286
799 config ARM64_ERRATUM_2051678 !! 1287 config ARC_PROMLIB
800 bool "Cortex-A510: 2051678: disable Ha !! 1288 bool
801 default y <<
802 help <<
803 This options adds the workaround for <<
804 Affected Cortex-A510 might not respe <<
805 hardware update of the page table's <<
806 is to not enable the feature on affe <<
807 1289
808 If unsure, say Y. !! 1290 config FW_ARC64
>> 1291 bool
809 1292
810 config ARM64_ERRATUM_2077057 !! 1293 config BOOT_ELF64
811 bool "Cortex-A510: 2077057: workaround !! 1294 bool
812 default y <<
813 help <<
814 This option adds the workaround for <<
815 Affected Cortex-A510 may corrupt SPS <<
816 expected, but a Pointer Authenticati <<
817 erratum causes SPSR_EL1 to be copied <<
818 EL1 to cause a return to EL2 with a <<
819 1295
820 This can only happen when EL2 is ste !! 1296 menu "CPU selection"
821 1297
822 When these conditions occur, the SPS !! 1298 choice
823 previous guest entry, and can be res !! 1299 prompt "CPU type"
>> 1300 default CPU_R4X00
824 1301
825 If unsure, say Y. !! 1302 config CPU_LOONGSON64
>> 1303 bool "Loongson 64-bit CPU"
>> 1304 depends on SYS_HAS_CPU_LOONGSON64
>> 1305 select ARCH_HAS_PHYS_TO_DMA
>> 1306 select CPU_MIPSR2
>> 1307 select CPU_HAS_PREFETCH
>> 1308 select CPU_SUPPORTS_64BIT_KERNEL
>> 1309 select CPU_SUPPORTS_HIGHMEM
>> 1310 select CPU_SUPPORTS_HUGEPAGES
>> 1311 select CPU_SUPPORTS_MSA
>> 1312 select CPU_DIEI_BROKEN if !LOONGSON3_ENHANCEMENT
>> 1313 select CPU_MIPSR2_IRQ_VI
>> 1314 select WEAK_ORDERING
>> 1315 select WEAK_REORDERING_BEYOND_LLSC
>> 1316 select MIPS_ASID_BITS_VARIABLE
>> 1317 select MIPS_PGD_C0_CONTEXT
>> 1318 select MIPS_L1_CACHE_SHIFT_6
>> 1319 select MIPS_FP_SUPPORT
>> 1320 select GPIOLIB
>> 1321 select SWIOTLB
>> 1322 select HAVE_KVM
>> 1323 help
>> 1324 The Loongson GSx64(GS264/GS464/GS464E/GS464V) series of processor
>> 1325 cores implements the MIPS64R2 instruction set with many extensions,
>> 1326 including most 64-bit Loongson-2 (2H, 2K) and Loongson-3 (3A1000,
>> 1327 3B1000, 3B1500, 3A2000, 3A3000 and 3A4000) processors. However, old
>> 1328 Loongson-2E/2F is not covered here and will be removed in future.
826 1329
827 config ARM64_ERRATUM_2658417 !! 1330 config LOONGSON3_ENHANCEMENT
828 bool "Cortex-A510: 2658417: remove BF1 !! 1331 bool "New Loongson-3 CPU Enhancements"
829 default y !! 1332 default n
>> 1333 depends on CPU_LOONGSON64
>> 1334 help
>> 1335 New Loongson-3 cores (since Loongson-3A R2, as opposed to Loongson-3A
>> 1336 R1, Loongson-3B R1 and Loongson-3B R2) has many enhancements, such as
>> 1337 FTLB, L1-VCache, EI/DI/Wait/Prefetch instruction, DSP/DSPr2 ASE, User
>> 1338 Local register, Read-Inhibit/Execute-Inhibit, SFB (Store Fill Buffer),
>> 1339 Fast TLB refill support, etc.
>> 1340
>> 1341 This option enable those enhancements which are not probed at run
>> 1342 time. If you want a generic kernel to run on all Loongson 3 machines,
>> 1343 please say 'N' here. If you want a high-performance kernel to run on
>> 1344 new Loongson-3 machines only, please say 'Y' here.
>> 1345
>> 1346 config CPU_LOONGSON3_WORKAROUNDS
>> 1347 bool "Loongson-3 LLSC Workarounds"
>> 1348 default y if SMP
>> 1349 depends on CPU_LOONGSON64
>> 1350 help
>> 1351 Loongson-3 processors have the llsc issues which require workarounds.
>> 1352 Without workarounds the system may hang unexpectedly.
>> 1353
>> 1354 Say Y, unless you know what you are doing.
>> 1355
>> 1356 config CPU_LOONGSON3_CPUCFG_EMULATION
>> 1357 bool "Emulate the CPUCFG instruction on older Loongson cores"
>> 1358 default y
>> 1359 depends on CPU_LOONGSON64
>> 1360 help
>> 1361 Loongson-3A R4 and newer have the CPUCFG instruction available for
>> 1362 userland to query CPU capabilities, much like CPUID on x86. This
>> 1363 option provides emulation of the instruction on older Loongson
>> 1364 cores, back to Loongson-3A1000.
>> 1365
>> 1366 If unsure, please say Y.
>> 1367
>> 1368 config CPU_LOONGSON2E
>> 1369 bool "Loongson 2E"
>> 1370 depends on SYS_HAS_CPU_LOONGSON2E
>> 1371 select CPU_LOONGSON2EF
>> 1372 help
>> 1373 The Loongson 2E processor implements the MIPS III instruction set
>> 1374 with many extensions.
>> 1375
>> 1376 It has an internal FPGA northbridge, which is compatible to
>> 1377 bonito64.
>> 1378
>> 1379 config CPU_LOONGSON2F
>> 1380 bool "Loongson 2F"
>> 1381 depends on SYS_HAS_CPU_LOONGSON2F
>> 1382 select CPU_LOONGSON2EF
>> 1383 select GPIOLIB
>> 1384 help
>> 1385 The Loongson 2F processor implements the MIPS III instruction set
>> 1386 with many extensions.
>> 1387
>> 1388 Loongson2F have built-in DDR2 and PCIX controller. The PCIX controller
>> 1389 have a similar programming interface with FPGA northbridge used in
>> 1390 Loongson2E.
>> 1391
>> 1392 config CPU_LOONGSON1B
>> 1393 bool "Loongson 1B"
>> 1394 depends on SYS_HAS_CPU_LOONGSON1B
>> 1395 select CPU_LOONGSON32
>> 1396 select LEDS_GPIO_REGISTER
>> 1397 help
>> 1398 The Loongson 1B is a 32-bit SoC, which implements the MIPS32
>> 1399 Release 1 instruction set and part of the MIPS32 Release 2
>> 1400 instruction set.
>> 1401
>> 1402 config CPU_LOONGSON1C
>> 1403 bool "Loongson 1C"
>> 1404 depends on SYS_HAS_CPU_LOONGSON1C
>> 1405 select CPU_LOONGSON32
>> 1406 select LEDS_GPIO_REGISTER
>> 1407 help
>> 1408 The Loongson 1C is a 32-bit SoC, which implements the MIPS32
>> 1409 Release 1 instruction set and part of the MIPS32 Release 2
>> 1410 instruction set.
>> 1411
>> 1412 config CPU_MIPS32_R1
>> 1413 bool "MIPS32 Release 1"
>> 1414 depends on SYS_HAS_CPU_MIPS32_R1
>> 1415 select CPU_HAS_PREFETCH
>> 1416 select CPU_SUPPORTS_32BIT_KERNEL
>> 1417 select CPU_SUPPORTS_HIGHMEM
>> 1418 help
>> 1419 Choose this option to build a kernel for release 1 or later of the
>> 1420 MIPS32 architecture. Most modern embedded systems with a 32-bit
>> 1421 MIPS processor are based on a MIPS32 processor. If you know the
>> 1422 specific type of processor in your system, choose those that one
>> 1423 otherwise CPU_MIPS32_R1 is a safe bet for any MIPS32 system.
>> 1424 Release 2 of the MIPS32 architecture is available since several
>> 1425 years so chances are you even have a MIPS32 Release 2 processor
>> 1426 in which case you should choose CPU_MIPS32_R2 instead for better
>> 1427 performance.
>> 1428
>> 1429 config CPU_MIPS32_R2
>> 1430 bool "MIPS32 Release 2"
>> 1431 depends on SYS_HAS_CPU_MIPS32_R2
>> 1432 select CPU_HAS_PREFETCH
>> 1433 select CPU_SUPPORTS_32BIT_KERNEL
>> 1434 select CPU_SUPPORTS_HIGHMEM
>> 1435 select CPU_SUPPORTS_MSA
>> 1436 select HAVE_KVM
>> 1437 help
>> 1438 Choose this option to build a kernel for release 2 or later of the
>> 1439 MIPS32 architecture. Most modern embedded systems with a 32-bit
>> 1440 MIPS processor are based on a MIPS32 processor. If you know the
>> 1441 specific type of processor in your system, choose those that one
>> 1442 otherwise CPU_MIPS32_R1 is a safe bet for any MIPS32 system.
>> 1443
>> 1444 config CPU_MIPS32_R5
>> 1445 bool "MIPS32 Release 5"
>> 1446 depends on SYS_HAS_CPU_MIPS32_R5
>> 1447 select CPU_HAS_PREFETCH
>> 1448 select CPU_SUPPORTS_32BIT_KERNEL
>> 1449 select CPU_SUPPORTS_HIGHMEM
>> 1450 select CPU_SUPPORTS_MSA
>> 1451 select HAVE_KVM
>> 1452 select MIPS_O32_FP64_SUPPORT
>> 1453 help
>> 1454 Choose this option to build a kernel for release 5 or later of the
>> 1455 MIPS32 architecture. New MIPS processors, starting with the Warrior
>> 1456 family, are based on a MIPS32r5 processor. If you own an older
>> 1457 processor, you probably need to select MIPS32r1 or MIPS32r2 instead.
>> 1458
>> 1459 config CPU_MIPS32_R6
>> 1460 bool "MIPS32 Release 6"
>> 1461 depends on SYS_HAS_CPU_MIPS32_R6
>> 1462 select CPU_HAS_PREFETCH
>> 1463 select CPU_NO_LOAD_STORE_LR
>> 1464 select CPU_SUPPORTS_32BIT_KERNEL
>> 1465 select CPU_SUPPORTS_HIGHMEM
>> 1466 select CPU_SUPPORTS_MSA
>> 1467 select HAVE_KVM
>> 1468 select MIPS_O32_FP64_SUPPORT
>> 1469 help
>> 1470 Choose this option to build a kernel for release 6 or later of the
>> 1471 MIPS32 architecture. New MIPS processors, starting with the Warrior
>> 1472 family, are based on a MIPS32r6 processor. If you own an older
>> 1473 processor, you probably need to select MIPS32r1 or MIPS32r2 instead.
>> 1474
>> 1475 config CPU_MIPS64_R1
>> 1476 bool "MIPS64 Release 1"
>> 1477 depends on SYS_HAS_CPU_MIPS64_R1
>> 1478 select CPU_HAS_PREFETCH
>> 1479 select CPU_SUPPORTS_32BIT_KERNEL
>> 1480 select CPU_SUPPORTS_64BIT_KERNEL
>> 1481 select CPU_SUPPORTS_HIGHMEM
>> 1482 select CPU_SUPPORTS_HUGEPAGES
>> 1483 help
>> 1484 Choose this option to build a kernel for release 1 or later of the
>> 1485 MIPS64 architecture. Many modern embedded systems with a 64-bit
>> 1486 MIPS processor are based on a MIPS64 processor. If you know the
>> 1487 specific type of processor in your system, choose those that one
>> 1488 otherwise CPU_MIPS64_R1 is a safe bet for any MIPS64 system.
>> 1489 Release 2 of the MIPS64 architecture is available since several
>> 1490 years so chances are you even have a MIPS64 Release 2 processor
>> 1491 in which case you should choose CPU_MIPS64_R2 instead for better
>> 1492 performance.
>> 1493
>> 1494 config CPU_MIPS64_R2
>> 1495 bool "MIPS64 Release 2"
>> 1496 depends on SYS_HAS_CPU_MIPS64_R2
>> 1497 select CPU_HAS_PREFETCH
>> 1498 select CPU_SUPPORTS_32BIT_KERNEL
>> 1499 select CPU_SUPPORTS_64BIT_KERNEL
>> 1500 select CPU_SUPPORTS_HIGHMEM
>> 1501 select CPU_SUPPORTS_HUGEPAGES
>> 1502 select CPU_SUPPORTS_MSA
>> 1503 select HAVE_KVM
>> 1504 help
>> 1505 Choose this option to build a kernel for release 2 or later of the
>> 1506 MIPS64 architecture. Many modern embedded systems with a 64-bit
>> 1507 MIPS processor are based on a MIPS64 processor. If you know the
>> 1508 specific type of processor in your system, choose those that one
>> 1509 otherwise CPU_MIPS64_R1 is a safe bet for any MIPS64 system.
>> 1510
>> 1511 config CPU_MIPS64_R5
>> 1512 bool "MIPS64 Release 5"
>> 1513 depends on SYS_HAS_CPU_MIPS64_R5
>> 1514 select CPU_HAS_PREFETCH
>> 1515 select CPU_SUPPORTS_32BIT_KERNEL
>> 1516 select CPU_SUPPORTS_64BIT_KERNEL
>> 1517 select CPU_SUPPORTS_HIGHMEM
>> 1518 select CPU_SUPPORTS_HUGEPAGES
>> 1519 select CPU_SUPPORTS_MSA
>> 1520 select MIPS_O32_FP64_SUPPORT if 32BIT || MIPS32_O32
>> 1521 select HAVE_KVM
>> 1522 help
>> 1523 Choose this option to build a kernel for release 5 or later of the
>> 1524 MIPS64 architecture. This is a intermediate MIPS architecture
>> 1525 release partly implementing release 6 features. Though there is no
>> 1526 any hardware known to be based on this release.
>> 1527
>> 1528 config CPU_MIPS64_R6
>> 1529 bool "MIPS64 Release 6"
>> 1530 depends on SYS_HAS_CPU_MIPS64_R6
>> 1531 select CPU_HAS_PREFETCH
>> 1532 select CPU_NO_LOAD_STORE_LR
>> 1533 select CPU_SUPPORTS_32BIT_KERNEL
>> 1534 select CPU_SUPPORTS_64BIT_KERNEL
>> 1535 select CPU_SUPPORTS_HIGHMEM
>> 1536 select CPU_SUPPORTS_HUGEPAGES
>> 1537 select CPU_SUPPORTS_MSA
>> 1538 select MIPS_O32_FP64_SUPPORT if 32BIT || MIPS32_O32
>> 1539 select HAVE_KVM
>> 1540 help
>> 1541 Choose this option to build a kernel for release 6 or later of the
>> 1542 MIPS64 architecture. New MIPS processors, starting with the Warrior
>> 1543 family, are based on a MIPS64r6 processor. If you own an older
>> 1544 processor, you probably need to select MIPS64r1 or MIPS64r2 instead.
>> 1545
>> 1546 config CPU_P5600
>> 1547 bool "MIPS Warrior P5600"
>> 1548 depends on SYS_HAS_CPU_P5600
>> 1549 select CPU_HAS_PREFETCH
>> 1550 select CPU_SUPPORTS_32BIT_KERNEL
>> 1551 select CPU_SUPPORTS_HIGHMEM
>> 1552 select CPU_SUPPORTS_MSA
>> 1553 select CPU_SUPPORTS_CPUFREQ
>> 1554 select CPU_MIPSR2_IRQ_VI
>> 1555 select CPU_MIPSR2_IRQ_EI
>> 1556 select HAVE_KVM
>> 1557 select MIPS_O32_FP64_SUPPORT
>> 1558 help
>> 1559 Choose this option to build a kernel for MIPS Warrior P5600 CPU.
>> 1560 It's based on MIPS32r5 ISA with XPA, EVA, dual/quad issue exec pipes,
>> 1561 MMU with two-levels TLB, UCA, MSA, MDU core level features and system
>> 1562 level features like up to six P5600 calculation cores, CM2 with L2
>> 1563 cache, IOCU/IOMMU (though might be unused depending on the system-
>> 1564 specific IP core configuration), GIC, CPC, virtualisation module,
>> 1565 eJTAG and PDtrace.
>> 1566
>> 1567 config CPU_R3000
>> 1568 bool "R3000"
>> 1569 depends on SYS_HAS_CPU_R3000
>> 1570 select CPU_HAS_WB
>> 1571 select CPU_R3K_TLB
>> 1572 select CPU_SUPPORTS_32BIT_KERNEL
>> 1573 select CPU_SUPPORTS_HIGHMEM
>> 1574 help
>> 1575 Please make sure to pick the right CPU type. Linux/MIPS is not
>> 1576 designed to be generic, i.e. Kernels compiled for R3000 CPUs will
>> 1577 *not* work on R4000 machines and vice versa. However, since most
>> 1578 of the supported machines have an R4000 (or similar) CPU, R4x00
>> 1579 might be a safe bet. If the resulting kernel does not work,
>> 1580 try to recompile with R3000.
>> 1581
>> 1582 config CPU_VR41XX
>> 1583 bool "R41xx"
>> 1584 depends on SYS_HAS_CPU_VR41XX
>> 1585 select CPU_SUPPORTS_32BIT_KERNEL
>> 1586 select CPU_SUPPORTS_64BIT_KERNEL
>> 1587 help
>> 1588 The options selects support for the NEC VR4100 series of processors.
>> 1589 Only choose this option if you have one of these processors as a
>> 1590 kernel built with this option will not run on any other type of
>> 1591 processor or vice versa.
>> 1592
>> 1593 config CPU_R4300
>> 1594 bool "R4300"
>> 1595 depends on SYS_HAS_CPU_R4300
>> 1596 select CPU_SUPPORTS_32BIT_KERNEL
>> 1597 select CPU_SUPPORTS_64BIT_KERNEL
>> 1598 help
>> 1599 MIPS Technologies R4300-series processors.
>> 1600
>> 1601 config CPU_R4X00
>> 1602 bool "R4x00"
>> 1603 depends on SYS_HAS_CPU_R4X00
>> 1604 select CPU_SUPPORTS_32BIT_KERNEL
>> 1605 select CPU_SUPPORTS_64BIT_KERNEL
>> 1606 select CPU_SUPPORTS_HUGEPAGES
>> 1607 help
>> 1608 MIPS Technologies R4000-series processors other than 4300, including
>> 1609 the R4000, R4400, R4600, and 4700.
>> 1610
>> 1611 config CPU_TX49XX
>> 1612 bool "R49XX"
>> 1613 depends on SYS_HAS_CPU_TX49XX
>> 1614 select CPU_HAS_PREFETCH
>> 1615 select CPU_SUPPORTS_32BIT_KERNEL
>> 1616 select CPU_SUPPORTS_64BIT_KERNEL
>> 1617 select CPU_SUPPORTS_HUGEPAGES
>> 1618
>> 1619 config CPU_R5000
>> 1620 bool "R5000"
>> 1621 depends on SYS_HAS_CPU_R5000
>> 1622 select CPU_SUPPORTS_32BIT_KERNEL
>> 1623 select CPU_SUPPORTS_64BIT_KERNEL
>> 1624 select CPU_SUPPORTS_HUGEPAGES
>> 1625 help
>> 1626 MIPS Technologies R5000-series processors other than the Nevada.
>> 1627
>> 1628 config CPU_R5500
>> 1629 bool "R5500"
>> 1630 depends on SYS_HAS_CPU_R5500
>> 1631 select CPU_SUPPORTS_32BIT_KERNEL
>> 1632 select CPU_SUPPORTS_64BIT_KERNEL
>> 1633 select CPU_SUPPORTS_HUGEPAGES
>> 1634 help
>> 1635 NEC VR5500 and VR5500A series processors implement 64-bit MIPS IV
>> 1636 instruction set.
>> 1637
>> 1638 config CPU_NEVADA
>> 1639 bool "RM52xx"
>> 1640 depends on SYS_HAS_CPU_NEVADA
>> 1641 select CPU_SUPPORTS_32BIT_KERNEL
>> 1642 select CPU_SUPPORTS_64BIT_KERNEL
>> 1643 select CPU_SUPPORTS_HUGEPAGES
>> 1644 help
>> 1645 QED / PMC-Sierra RM52xx-series ("Nevada") processors.
>> 1646
>> 1647 config CPU_R10000
>> 1648 bool "R10000"
>> 1649 depends on SYS_HAS_CPU_R10000
>> 1650 select CPU_HAS_PREFETCH
>> 1651 select CPU_SUPPORTS_32BIT_KERNEL
>> 1652 select CPU_SUPPORTS_64BIT_KERNEL
>> 1653 select CPU_SUPPORTS_HIGHMEM
>> 1654 select CPU_SUPPORTS_HUGEPAGES
>> 1655 help
>> 1656 MIPS Technologies R10000-series processors.
>> 1657
>> 1658 config CPU_RM7000
>> 1659 bool "RM7000"
>> 1660 depends on SYS_HAS_CPU_RM7000
>> 1661 select CPU_HAS_PREFETCH
>> 1662 select CPU_SUPPORTS_32BIT_KERNEL
>> 1663 select CPU_SUPPORTS_64BIT_KERNEL
>> 1664 select CPU_SUPPORTS_HIGHMEM
>> 1665 select CPU_SUPPORTS_HUGEPAGES
>> 1666
>> 1667 config CPU_SB1
>> 1668 bool "SB1"
>> 1669 depends on SYS_HAS_CPU_SB1
>> 1670 select CPU_SUPPORTS_32BIT_KERNEL
>> 1671 select CPU_SUPPORTS_64BIT_KERNEL
>> 1672 select CPU_SUPPORTS_HIGHMEM
>> 1673 select CPU_SUPPORTS_HUGEPAGES
>> 1674 select WEAK_ORDERING
>> 1675
>> 1676 config CPU_CAVIUM_OCTEON
>> 1677 bool "Cavium Octeon processor"
>> 1678 depends on SYS_HAS_CPU_CAVIUM_OCTEON
>> 1679 select CPU_HAS_PREFETCH
>> 1680 select CPU_SUPPORTS_64BIT_KERNEL
>> 1681 select WEAK_ORDERING
>> 1682 select CPU_SUPPORTS_HIGHMEM
>> 1683 select CPU_SUPPORTS_HUGEPAGES
>> 1684 select USB_EHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 1685 select USB_OHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 1686 select MIPS_L1_CACHE_SHIFT_7
>> 1687 select HAVE_KVM
>> 1688 help
>> 1689 The Cavium Octeon processor is a highly integrated chip containing
>> 1690 many ethernet hardware widgets for networking tasks. The processor
>> 1691 can have up to 16 Mips64v2 cores and 8 integrated gigabit ethernets.
>> 1692 Full details can be found at http://www.caviumnetworks.com.
>> 1693
>> 1694 config CPU_BMIPS
>> 1695 bool "Broadcom BMIPS"
>> 1696 depends on SYS_HAS_CPU_BMIPS
>> 1697 select CPU_MIPS32
>> 1698 select CPU_BMIPS32_3300 if SYS_HAS_CPU_BMIPS32_3300
>> 1699 select CPU_BMIPS4350 if SYS_HAS_CPU_BMIPS4350
>> 1700 select CPU_BMIPS4380 if SYS_HAS_CPU_BMIPS4380
>> 1701 select CPU_BMIPS5000 if SYS_HAS_CPU_BMIPS5000
>> 1702 select CPU_SUPPORTS_32BIT_KERNEL
>> 1703 select DMA_NONCOHERENT
>> 1704 select IRQ_MIPS_CPU
>> 1705 select SWAP_IO_SPACE
>> 1706 select WEAK_ORDERING
>> 1707 select CPU_SUPPORTS_HIGHMEM
>> 1708 select CPU_HAS_PREFETCH
>> 1709 select CPU_SUPPORTS_CPUFREQ
>> 1710 select MIPS_EXTERNAL_TIMER
>> 1711 select GENERIC_IRQ_MIGRATION if HOTPLUG_CPU
830 help 1712 help
831 This option adds the workaround for !! 1713 Support for BMIPS32/3300/4350/4380 and BMIPS5000 processors.
832 Affected Cortex-A510 (r0p0 to r1p1) <<
833 BFMMLA or VMMLA instructions in rare <<
834 A510 CPUs are using shared neon hard <<
835 discoverable by the kernel, hide the <<
836 user-space should not be using these <<
837 1714
838 If unsure, say Y. !! 1715 endchoice
839 1716
840 config ARM64_ERRATUM_2119858 !! 1717 config CPU_MIPS32_3_5_FEATURES
841 bool "Cortex-A710/X2: 2119858: workaro !! 1718 bool "MIPS32 Release 3.5 Features"
842 default y !! 1719 depends on SYS_HAS_CPU_MIPS32_R3_5
843 depends on CORESIGHT_TRBE !! 1720 depends on CPU_MIPS32_R2 || CPU_MIPS32_R5 || CPU_MIPS32_R6 || \
844 select ARM64_WORKAROUND_TRBE_OVERWRITE !! 1721 CPU_P5600
>> 1722 help
>> 1723 Choose this option to build a kernel for release 2 or later of the
>> 1724 MIPS32 architecture including features from the 3.5 release such as
>> 1725 support for Enhanced Virtual Addressing (EVA).
>> 1726
>> 1727 config CPU_MIPS32_3_5_EVA
>> 1728 bool "Enhanced Virtual Addressing (EVA)"
>> 1729 depends on CPU_MIPS32_3_5_FEATURES
>> 1730 select EVA
>> 1731 default y
>> 1732 help
>> 1733 Choose this option if you want to enable the Enhanced Virtual
>> 1734 Addressing (EVA) on your MIPS32 core (such as proAptiv).
>> 1735 One of its primary benefits is an increase in the maximum size
>> 1736 of lowmem (up to 3GB). If unsure, say 'N' here.
>> 1737
>> 1738 config CPU_MIPS32_R5_FEATURES
>> 1739 bool "MIPS32 Release 5 Features"
>> 1740 depends on SYS_HAS_CPU_MIPS32_R5
>> 1741 depends on CPU_MIPS32_R2 || CPU_MIPS32_R5 || CPU_P5600
>> 1742 help
>> 1743 Choose this option to build a kernel for release 2 or later of the
>> 1744 MIPS32 architecture including features from release 5 such as
>> 1745 support for Extended Physical Addressing (XPA).
>> 1746
>> 1747 config CPU_MIPS32_R5_XPA
>> 1748 bool "Extended Physical Addressing (XPA)"
>> 1749 depends on CPU_MIPS32_R5_FEATURES
>> 1750 depends on !EVA
>> 1751 depends on !PAGE_SIZE_4KB
>> 1752 depends on SYS_SUPPORTS_HIGHMEM
>> 1753 select XPA
>> 1754 select HIGHMEM
>> 1755 select PHYS_ADDR_T_64BIT
>> 1756 default n
845 help 1757 help
846 This option adds the workaround for !! 1758 Choose this option if you want to enable the Extended Physical
>> 1759 Addressing (XPA) on your MIPS32 core (such as P5600 series). The
>> 1760 benefit is to increase physical addressing equal to or greater
>> 1761 than 40 bits. Note that this has the side effect of turning on
>> 1762 64-bit addressing which in turn makes the PTEs 64-bit in size.
>> 1763 If unsure, say 'N' here.
847 1764
848 Affected Cortex-A710/X2 cores could !! 1765 if CPU_LOONGSON2F
849 data at the base of the buffer (poin !! 1766 config CPU_NOP_WORKAROUNDS
850 the event of a WRAP event. !! 1767 bool
851 <<
852 Work around the issue by always maki <<
853 256 bytes before enabling the buffer <<
854 the buffer with ETM ignore packets u <<
855 1768
856 If unsure, say Y. !! 1769 config CPU_JUMP_WORKAROUNDS
>> 1770 bool
857 1771
858 config ARM64_ERRATUM_2139208 !! 1772 config CPU_LOONGSON2F_WORKAROUNDS
859 bool "Neoverse-N2: 2139208: workaround !! 1773 bool "Loongson 2F Workarounds"
860 default y 1774 default y
861 depends on CORESIGHT_TRBE !! 1775 select CPU_NOP_WORKAROUNDS
862 select ARM64_WORKAROUND_TRBE_OVERWRITE !! 1776 select CPU_JUMP_WORKAROUNDS
863 help 1777 help
864 This option adds the workaround for !! 1778 Loongson 2F01 / 2F02 processors have the NOP & JUMP issues which
>> 1779 require workarounds. Without workarounds the system may hang
>> 1780 unexpectedly. For more information please refer to the gas
>> 1781 -mfix-loongson2f-nop and -mfix-loongson2f-jump options.
>> 1782
>> 1783 Loongson 2F03 and later have fixed these issues and no workarounds
>> 1784 are needed. The workarounds have no significant side effect on them
>> 1785 but may decrease the performance of the system so this option should
>> 1786 be disabled unless the kernel is intended to be run on 2F01 or 2F02
>> 1787 systems.
865 1788
866 Affected Neoverse-N2 cores could ove !! 1789 If unsure, please say Y.
867 data at the base of the buffer (poin !! 1790 endif # CPU_LOONGSON2F
868 the event of a WRAP event. <<
869 <<
870 Work around the issue by always maki <<
871 256 bytes before enabling the buffer <<
872 the buffer with ETM ignore packets u <<
873 1791
874 If unsure, say Y. !! 1792 config SYS_SUPPORTS_ZBOOT
>> 1793 bool
>> 1794 select HAVE_KERNEL_GZIP
>> 1795 select HAVE_KERNEL_BZIP2
>> 1796 select HAVE_KERNEL_LZ4
>> 1797 select HAVE_KERNEL_LZMA
>> 1798 select HAVE_KERNEL_LZO
>> 1799 select HAVE_KERNEL_XZ
>> 1800 select HAVE_KERNEL_ZSTD
875 1801
876 config ARM64_WORKAROUND_TSB_FLUSH_FAILURE !! 1802 config SYS_SUPPORTS_ZBOOT_UART16550
877 bool 1803 bool
>> 1804 select SYS_SUPPORTS_ZBOOT
878 1805
879 config ARM64_ERRATUM_2054223 !! 1806 config SYS_SUPPORTS_ZBOOT_UART_PROM
880 bool "Cortex-A710: 2054223: workaround !! 1807 bool
881 default y !! 1808 select SYS_SUPPORTS_ZBOOT
882 select ARM64_WORKAROUND_TSB_FLUSH_FAIL <<
883 help <<
884 Enable workaround for ARM Cortex-A71 <<
885 1809
886 Affected cores may fail to flush the !! 1810 config CPU_LOONGSON2EF
887 the PE is in trace prohibited state. !! 1811 bool
888 of the trace cached. !! 1812 select CPU_SUPPORTS_32BIT_KERNEL
>> 1813 select CPU_SUPPORTS_64BIT_KERNEL
>> 1814 select CPU_SUPPORTS_HIGHMEM
>> 1815 select CPU_SUPPORTS_HUGEPAGES
>> 1816 select ARCH_HAS_PHYS_TO_DMA
889 1817
890 Workaround is to issue two TSB conse !! 1818 config CPU_LOONGSON32
>> 1819 bool
>> 1820 select CPU_MIPS32
>> 1821 select CPU_MIPSR2
>> 1822 select CPU_HAS_PREFETCH
>> 1823 select CPU_SUPPORTS_32BIT_KERNEL
>> 1824 select CPU_SUPPORTS_HIGHMEM
>> 1825 select CPU_SUPPORTS_CPUFREQ
891 1826
892 If unsure, say Y. !! 1827 config CPU_BMIPS32_3300
>> 1828 select SMP_UP if SMP
>> 1829 bool
893 1830
894 config ARM64_ERRATUM_2067961 !! 1831 config CPU_BMIPS4350
895 bool "Neoverse-N2: 2067961: workaround !! 1832 bool
896 default y !! 1833 select SYS_SUPPORTS_SMP
897 select ARM64_WORKAROUND_TSB_FLUSH_FAIL !! 1834 select SYS_SUPPORTS_HOTPLUG_CPU
898 help <<
899 Enable workaround for ARM Neoverse-N <<
900 1835
901 Affected cores may fail to flush the !! 1836 config CPU_BMIPS4380
902 the PE is in trace prohibited state. !! 1837 bool
903 of the trace cached. !! 1838 select MIPS_L1_CACHE_SHIFT_6
>> 1839 select SYS_SUPPORTS_SMP
>> 1840 select SYS_SUPPORTS_HOTPLUG_CPU
>> 1841 select CPU_HAS_RIXI
904 1842
905 Workaround is to issue two TSB conse !! 1843 config CPU_BMIPS5000
>> 1844 bool
>> 1845 select MIPS_CPU_SCACHE
>> 1846 select MIPS_L1_CACHE_SHIFT_7
>> 1847 select SYS_SUPPORTS_SMP
>> 1848 select SYS_SUPPORTS_HOTPLUG_CPU
>> 1849 select CPU_HAS_RIXI
906 1850
907 If unsure, say Y. !! 1851 config SYS_HAS_CPU_LOONGSON64
>> 1852 bool
>> 1853 select CPU_SUPPORTS_CPUFREQ
>> 1854 select CPU_HAS_RIXI
908 1855
909 config ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANG !! 1856 config SYS_HAS_CPU_LOONGSON2E
910 bool 1857 bool
911 1858
912 config ARM64_ERRATUM_2253138 !! 1859 config SYS_HAS_CPU_LOONGSON2F
913 bool "Neoverse-N2: 2253138: workaround !! 1860 bool
914 depends on CORESIGHT_TRBE !! 1861 select CPU_SUPPORTS_CPUFREQ
915 default y !! 1862 select CPU_SUPPORTS_ADDRWINCFG if 64BIT
916 select ARM64_WORKAROUND_TRBE_WRITE_OUT <<
917 help <<
918 This option adds the workaround for <<
919 1863
920 Affected Neoverse-N2 cores might wri !! 1864 config SYS_HAS_CPU_LOONGSON1B
921 for TRBE. Under some conditions, the !! 1865 bool
922 virtually addressed page following t <<
923 (i.e., the TRBLIMITR_EL1.LIMIT), ins <<
924 1866
925 Work around this in the driver by al !! 1867 config SYS_HAS_CPU_LOONGSON1C
926 page beyond the TRBLIMITR_EL1.LIMIT, !! 1868 bool
927 1869
928 If unsure, say Y. !! 1870 config SYS_HAS_CPU_MIPS32_R1
>> 1871 bool
929 1872
930 config ARM64_ERRATUM_2224489 !! 1873 config SYS_HAS_CPU_MIPS32_R2
931 bool "Cortex-A710/X2: 2224489: workaro !! 1874 bool
932 depends on CORESIGHT_TRBE <<
933 default y <<
934 select ARM64_WORKAROUND_TRBE_WRITE_OUT <<
935 help <<
936 This option adds the workaround for <<
937 1875
938 Affected Cortex-A710/X2 cores might !! 1876 config SYS_HAS_CPU_MIPS32_R3_5
939 for TRBE. Under some conditions, the !! 1877 bool
940 virtually addressed page following t <<
941 (i.e., the TRBLIMITR_EL1.LIMIT), ins <<
942 1878
943 Work around this in the driver by al !! 1879 config SYS_HAS_CPU_MIPS32_R5
944 page beyond the TRBLIMITR_EL1.LIMIT, !! 1880 bool
>> 1881 select ARCH_HAS_SYNC_DMA_FOR_CPU if DMA_NONCOHERENT
945 1882
946 If unsure, say Y. !! 1883 config SYS_HAS_CPU_MIPS32_R6
>> 1884 bool
>> 1885 select ARCH_HAS_SYNC_DMA_FOR_CPU if DMA_NONCOHERENT
947 1886
948 config ARM64_ERRATUM_2441009 !! 1887 config SYS_HAS_CPU_MIPS64_R1
949 bool "Cortex-A510: Completion of affec !! 1888 bool
950 select ARM64_WORKAROUND_REPEAT_TLBI <<
951 help <<
952 This option adds a workaround for AR <<
953 <<
954 Under very rare circumstances, affec <<
955 may not handle a race between a brea <<
956 CPU, and another CPU accessing the s <<
957 store to a page that has been unmapp <<
958 1889
959 Work around this by adding the affec !! 1890 config SYS_HAS_CPU_MIPS64_R2
960 TLB sequences to be done twice. !! 1891 bool
961 1892
962 If unsure, say N. !! 1893 config SYS_HAS_CPU_MIPS64_R5
>> 1894 bool
>> 1895 select ARCH_HAS_SYNC_DMA_FOR_CPU if DMA_NONCOHERENT
963 1896
964 config ARM64_ERRATUM_2064142 !! 1897 config SYS_HAS_CPU_MIPS64_R6
965 bool "Cortex-A510: 2064142: workaround !! 1898 bool
966 depends on CORESIGHT_TRBE !! 1899 select ARCH_HAS_SYNC_DMA_FOR_CPU if DMA_NONCOHERENT
967 default y <<
968 help <<
969 This option adds the workaround for <<
970 1900
971 Affected Cortex-A510 core might fail !! 1901 config SYS_HAS_CPU_P5600
972 TRBE has been disabled. Under some c !! 1902 bool
973 writes into TRBE registers TRBLIMITR !! 1903 select ARCH_HAS_SYNC_DMA_FOR_CPU if DMA_NONCOHERENT
974 and TRBTRG_EL1 will be ignored and w <<
975 <<
976 Work around this in the driver by ex <<
977 is stopped and before performing a s <<
978 registers. <<
979 1904
980 If unsure, say Y. !! 1905 config SYS_HAS_CPU_R3000
>> 1906 bool
981 1907
982 config ARM64_ERRATUM_2038923 !! 1908 config SYS_HAS_CPU_VR41XX
983 bool "Cortex-A510: 2038923: workaround !! 1909 bool
984 depends on CORESIGHT_TRBE <<
985 default y <<
986 help <<
987 This option adds the workaround for <<
988 1910
989 Affected Cortex-A510 core might caus !! 1911 config SYS_HAS_CPU_R4300
990 prohibited within the CPU. As a resu !! 1912 bool
991 might be corrupted. This happens aft <<
992 TRBLIMITR_EL1.E, followed by just a <<
993 execution changes from a context, in <<
994 isn't, or vice versa. In these menti <<
995 is prohibited is inconsistent betwee <<
996 the trace buffer state might be corr <<
997 <<
998 Work around this in the driver by pr <<
999 trace is prohibited or not based on <<
1000 change to TRBLIMITR_EL1.E with at l <<
1001 two ISB instructions if no ERET is <<
1002 1913
1003 If unsure, say Y. !! 1914 config SYS_HAS_CPU_R4X00
>> 1915 bool
1004 1916
1005 config ARM64_ERRATUM_1902691 !! 1917 config SYS_HAS_CPU_TX49XX
1006 bool "Cortex-A510: 1902691: workaroun !! 1918 bool
1007 depends on CORESIGHT_TRBE <<
1008 default y <<
1009 help <<
1010 This option adds the workaround for <<
1011 1919
1012 Affected Cortex-A510 core might cau !! 1920 config SYS_HAS_CPU_R5000
1013 into the memory. Effectively TRBE i !! 1921 bool
1014 trace data. <<
1015 <<
1016 Work around this problem in the dri <<
1017 affected cpus. The firmware must ha <<
1018 on such implementations. This will <<
1019 do this already. <<
1020 1922
1021 If unsure, say Y. !! 1923 config SYS_HAS_CPU_R5500
>> 1924 bool
1022 1925
1023 config ARM64_ERRATUM_2457168 !! 1926 config SYS_HAS_CPU_NEVADA
1024 bool "Cortex-A510: 2457168: workaroun !! 1927 bool
1025 depends on ARM64_AMU_EXTN <<
1026 default y <<
1027 help <<
1028 This option adds the workaround for <<
1029 1928
1030 The AMU counter AMEVCNTR01 (constan !! 1929 config SYS_HAS_CPU_R10000
1031 as the system counter. On affected !! 1930 bool
1032 incorrectly giving a significantly !! 1931 select ARCH_HAS_SYNC_DMA_FOR_CPU if DMA_NONCOHERENT
1033 <<
1034 Work around this problem by returni <<
1035 key locations that results in disab <<
1036 is the same to firmware disabling a <<
1037 1932
1038 If unsure, say Y. !! 1933 config SYS_HAS_CPU_RM7000
>> 1934 bool
1039 1935
1040 config ARM64_ERRATUM_2645198 !! 1936 config SYS_HAS_CPU_SB1
1041 bool "Cortex-A715: 2645198: Workaroun !! 1937 bool
1042 default y <<
1043 help <<
1044 This option adds the workaround for <<
1045 1938
1046 If a Cortex-A715 cpu sees a page ma !! 1939 config SYS_HAS_CPU_CAVIUM_OCTEON
1047 to non-executable, it may corrupt t !! 1940 bool
1048 next instruction abort caused by pe <<
1049 <<
1050 Only user-space does executable to <<
1051 mprotect() system call. Workaround <<
1052 TLB invalidation, for all changes t <<
1053 1941
1054 If unsure, say Y. !! 1942 config SYS_HAS_CPU_BMIPS
>> 1943 bool
1055 1944
1056 config ARM64_WORKAROUND_SPECULATIVE_UNPRIV_LO !! 1945 config SYS_HAS_CPU_BMIPS32_3300
1057 bool 1946 bool
>> 1947 select SYS_HAS_CPU_BMIPS
1058 1948
1059 config ARM64_ERRATUM_2966298 !! 1949 config SYS_HAS_CPU_BMIPS4350
1060 bool "Cortex-A520: 2966298: workaroun !! 1950 bool
1061 select ARM64_WORKAROUND_SPECULATIVE_U !! 1951 select SYS_HAS_CPU_BMIPS
1062 default y <<
1063 help <<
1064 This option adds the workaround for <<
1065 1952
1066 On an affected Cortex-A520 core, a !! 1953 config SYS_HAS_CPU_BMIPS4380
1067 load might leak data from a privile !! 1954 bool
>> 1955 select SYS_HAS_CPU_BMIPS
1068 1956
1069 Work around this problem by executi !! 1957 config SYS_HAS_CPU_BMIPS5000
>> 1958 bool
>> 1959 select SYS_HAS_CPU_BMIPS
>> 1960 select ARCH_HAS_SYNC_DMA_FOR_CPU
1070 1961
1071 If unsure, say Y. !! 1962 #
>> 1963 # CPU may reorder R->R, R->W, W->R, W->W
>> 1964 # Reordering beyond LL and SC is handled in WEAK_REORDERING_BEYOND_LLSC
>> 1965 #
>> 1966 config WEAK_ORDERING
>> 1967 bool
1072 1968
1073 config ARM64_ERRATUM_3117295 !! 1969 #
1074 bool "Cortex-A510: 3117295: workaroun !! 1970 # CPU may reorder reads and writes beyond LL/SC
1075 select ARM64_WORKAROUND_SPECULATIVE_U !! 1971 # CPU may reorder R->LL, R->LL, W->LL, W->LL, R->SC, R->SC, W->SC, W->SC
1076 default y !! 1972 #
1077 help !! 1973 config WEAK_REORDERING_BEYOND_LLSC
1078 This option adds the workaround for !! 1974 bool
>> 1975 endmenu
1079 1976
1080 On an affected Cortex-A510 core, a !! 1977 #
1081 load might leak data from a privile !! 1978 # These two indicate any level of the MIPS32 and MIPS64 architecture
>> 1979 #
>> 1980 config CPU_MIPS32
>> 1981 bool
>> 1982 default y if CPU_MIPS32_R1 || CPU_MIPS32_R2 || CPU_MIPS32_R5 || \
>> 1983 CPU_MIPS32_R6 || CPU_P5600
1082 1984
1083 Work around this problem by executi !! 1985 config CPU_MIPS64
>> 1986 bool
>> 1987 default y if CPU_MIPS64_R1 || CPU_MIPS64_R2 || CPU_MIPS64_R5 || \
>> 1988 CPU_MIPS64_R6 || CPU_LOONGSON64 || CPU_CAVIUM_OCTEON
1084 1989
1085 If unsure, say Y. !! 1990 #
>> 1991 # These indicate the revision of the architecture
>> 1992 #
>> 1993 config CPU_MIPSR1
>> 1994 bool
>> 1995 default y if CPU_MIPS32_R1 || CPU_MIPS64_R1
1086 1996
1087 config ARM64_ERRATUM_3194386 !! 1997 config CPU_MIPSR2
1088 bool "Cortex-*/Neoverse-*: workaround !! 1998 bool
1089 default y !! 1999 default y if CPU_MIPS32_R2 || CPU_MIPS64_R2 || CPU_CAVIUM_OCTEON
1090 help !! 2000 select CPU_HAS_RIXI
1091 This option adds the workaround for !! 2001 select CPU_HAS_DIEI if !CPU_DIEI_BROKEN
>> 2002 select MIPS_SPRAM
1092 2003
1093 * ARM Cortex-A76 erratum 3324349 !! 2004 config CPU_MIPSR5
1094 * ARM Cortex-A77 erratum 3324348 !! 2005 bool
1095 * ARM Cortex-A78 erratum 3324344 !! 2006 default y if CPU_MIPS32_R5 || CPU_MIPS64_R5 || CPU_P5600
1096 * ARM Cortex-A78C erratum 3324346 !! 2007 select CPU_HAS_RIXI
1097 * ARM Cortex-A78C erratum 3324347 !! 2008 select CPU_HAS_DIEI if !CPU_DIEI_BROKEN
1098 * ARM Cortex-A710 erratam 3324338 !! 2009 select MIPS_SPRAM
1099 * ARM Cortex-A715 errartum 3456084 <<
1100 * ARM Cortex-A720 erratum 3456091 <<
1101 * ARM Cortex-A725 erratum 3456106 <<
1102 * ARM Cortex-X1 erratum 3324344 <<
1103 * ARM Cortex-X1C erratum 3324346 <<
1104 * ARM Cortex-X2 erratum 3324338 <<
1105 * ARM Cortex-X3 erratum 3324335 <<
1106 * ARM Cortex-X4 erratum 3194386 <<
1107 * ARM Cortex-X925 erratum 3324334 <<
1108 * ARM Neoverse-N1 erratum 3324349 <<
1109 * ARM Neoverse N2 erratum 3324339 <<
1110 * ARM Neoverse-N3 erratum 3456111 <<
1111 * ARM Neoverse-V1 erratum 3324341 <<
1112 * ARM Neoverse V2 erratum 3324336 <<
1113 * ARM Neoverse-V3 erratum 3312417 <<
1114 <<
1115 On affected cores "MSR SSBS, #0" in <<
1116 subsequent speculative instructions <<
1117 speculative store bypassing. <<
1118 <<
1119 Work around this problem by placing <<
1120 Instruction Synchronization Barrier <<
1121 SSBS. The presence of the SSBS spec <<
1122 from hwcaps and EL0 reads of ID_AA6 <<
1123 will use the PR_SPEC_STORE_BYPASS p <<
1124 2010
1125 If unsure, say Y. !! 2011 config CPU_MIPSR6
>> 2012 bool
>> 2013 default y if CPU_MIPS32_R6 || CPU_MIPS64_R6
>> 2014 select CPU_HAS_RIXI
>> 2015 select CPU_HAS_DIEI if !CPU_DIEI_BROKEN
>> 2016 select HAVE_ARCH_BITREVERSE
>> 2017 select MIPS_ASID_BITS_VARIABLE
>> 2018 select MIPS_CRC_SUPPORT
>> 2019 select MIPS_SPRAM
1126 2020
1127 config CAVIUM_ERRATUM_22375 !! 2021 config TARGET_ISA_REV
1128 bool "Cavium erratum 22375, 24313" !! 2022 int
1129 default y !! 2023 default 1 if CPU_MIPSR1
>> 2024 default 2 if CPU_MIPSR2
>> 2025 default 5 if CPU_MIPSR5
>> 2026 default 6 if CPU_MIPSR6
>> 2027 default 0
1130 help 2028 help
1131 Enable workaround for errata 22375 !! 2029 Reflects the ISA revision being targeted by the kernel build. This
>> 2030 is effectively the Kconfig equivalent of MIPS_ISA_REV.
1132 2031
1133 This implements two gicv3-its errat !! 2032 config EVA
1134 with a small impact affecting only !! 2033 bool
1135 2034
1136 erratum 22375: only alloc 8MB tab !! 2035 config XPA
1137 erratum 24313: ignore memory acce !! 2036 bool
1138 2037
1139 The fixes are in ITS initialization !! 2038 config SYS_SUPPORTS_32BIT_KERNEL
1140 type and table size provided by the !! 2039 bool
>> 2040 config SYS_SUPPORTS_64BIT_KERNEL
>> 2041 bool
>> 2042 config CPU_SUPPORTS_32BIT_KERNEL
>> 2043 bool
>> 2044 config CPU_SUPPORTS_64BIT_KERNEL
>> 2045 bool
>> 2046 config CPU_SUPPORTS_CPUFREQ
>> 2047 bool
>> 2048 config CPU_SUPPORTS_ADDRWINCFG
>> 2049 bool
>> 2050 config CPU_SUPPORTS_HUGEPAGES
>> 2051 bool
>> 2052 depends on !(32BIT && (PHYS_ADDR_T_64BIT || EVA))
>> 2053 config MIPS_PGD_C0_CONTEXT
>> 2054 bool
>> 2055 depends on 64BIT
>> 2056 default y if (CPU_MIPSR2 || CPU_MIPSR6)
1141 2057
1142 If unsure, say Y. !! 2058 #
>> 2059 # Set to y for ptrace access to watch registers.
>> 2060 #
>> 2061 config HARDWARE_WATCHPOINTS
>> 2062 bool
>> 2063 default y if CPU_MIPSR1 || CPU_MIPSR2 || CPU_MIPSR6
1143 2064
1144 config CAVIUM_ERRATUM_23144 !! 2065 menu "Kernel type"
1145 bool "Cavium erratum 23144: ITS SYNC <<
1146 depends on NUMA <<
1147 default y <<
1148 help <<
1149 ITS SYNC command hang for cross nod <<
1150 2066
1151 If unsure, say Y. !! 2067 choice
>> 2068 prompt "Kernel code model"
>> 2069 help
>> 2070 You should only select this option if you have a workload that
>> 2071 actually benefits from 64-bit processing or if your machine has
>> 2072 large memory. You will only be presented a single option in this
>> 2073 menu if your system does not support both 32-bit and 64-bit kernels.
>> 2074
>> 2075 config 32BIT
>> 2076 bool "32-bit kernel"
>> 2077 depends on CPU_SUPPORTS_32BIT_KERNEL && SYS_SUPPORTS_32BIT_KERNEL
>> 2078 select TRAD_SIGNALS
>> 2079 help
>> 2080 Select this option if you want to build a 32-bit kernel.
1152 2081
1153 config CAVIUM_ERRATUM_23154 !! 2082 config 64BIT
1154 bool "Cavium errata 23154 and 38545: !! 2083 bool "64-bit kernel"
1155 default y !! 2084 depends on CPU_SUPPORTS_64BIT_KERNEL && SYS_SUPPORTS_64BIT_KERNEL
1156 help 2085 help
1157 The ThunderX GICv3 implementation r !! 2086 Select this option if you want to build a 64-bit kernel.
1158 reading the IAR status to ensure da <<
1159 (access to icc_iar1_el1 is not sync <<
1160 <<
1161 It also suffers from erratum 38545 <<
1162 OcteonTX and OcteonTX2), resulting <<
1163 spuriously presented to the CPU int <<
1164 2087
1165 If unsure, say Y. !! 2088 endchoice
1166 2089
1167 config CAVIUM_ERRATUM_27456 !! 2090 config MIPS_VA_BITS_48
1168 bool "Cavium erratum 27456: Broadcast !! 2091 bool "48 bits virtual memory"
1169 default y !! 2092 depends on 64BIT
1170 help !! 2093 help
1171 On ThunderX T88 pass 1.x through 2. !! 2094 Support a maximum at least 48 bits of application virtual
1172 instructions may cause the icache t !! 2095 memory. Default is 40 bits or less, depending on the CPU.
1173 contains data for a non-current ASI !! 2096 For page sizes 16k and above, this option results in a small
1174 invalidate the icache when changing !! 2097 memory overhead for page tables. For 4k page size, a fourth
>> 2098 level of page tables is added which imposes both a memory
>> 2099 overhead as well as slower TLB fault handling.
1175 2100
1176 If unsure, say Y. !! 2101 If unsure, say N.
1177 2102
1178 config CAVIUM_ERRATUM_30115 !! 2103 config ZBOOT_LOAD_ADDRESS
1179 bool "Cavium erratum 30115: Guest may !! 2104 hex "Compressed kernel load address"
1180 default y !! 2105 default 0xffffffff80400000 if BCM47XX
>> 2106 default 0x0
>> 2107 depends on SYS_SUPPORTS_ZBOOT
1181 help 2108 help
1182 On ThunderX T88 pass 1.x through 2. !! 2109 The address to load compressed kernel, aka vmlinuz.
1183 1.2, and T83 Pass 1.0, KVM guest ex <<
1184 interrupts in host. Trapping both G <<
1185 accesses sidesteps the issue. <<
1186 2110
1187 If unsure, say Y. !! 2111 This is only used if non-zero.
1188 2112
1189 config CAVIUM_TX2_ERRATUM_219 !! 2113 choice
1190 bool "Cavium ThunderX2 erratum 219: P !! 2114 prompt "Kernel page size"
1191 default y !! 2115 default PAGE_SIZE_4KB
1192 help <<
1193 On Cavium ThunderX2, a load, store <<
1194 TTBR update and the corresponding c <<
1195 cause a spurious Data Abort to be d <<
1196 the CPU core. <<
1197 <<
1198 Work around the issue by avoiding t <<
1199 trapping KVM guest TTBRx_EL1 writes <<
1200 trap handler performs the correspon <<
1201 instruction and ensures context syn <<
1202 exception return. <<
1203 2116
1204 If unsure, say Y. !! 2117 config PAGE_SIZE_4KB
>> 2118 bool "4kB"
>> 2119 depends on !CPU_LOONGSON2EF && !CPU_LOONGSON64
>> 2120 help
>> 2121 This option select the standard 4kB Linux page size. On some
>> 2122 R3000-family processors this is the only available page size. Using
>> 2123 4kB page size will minimize memory consumption and is therefore
>> 2124 recommended for low memory systems.
>> 2125
>> 2126 config PAGE_SIZE_8KB
>> 2127 bool "8kB"
>> 2128 depends on CPU_CAVIUM_OCTEON
>> 2129 depends on !MIPS_VA_BITS_48
>> 2130 help
>> 2131 Using 8kB page size will result in higher performance kernel at
>> 2132 the price of higher memory consumption. This option is available
>> 2133 only on cnMIPS processors. Note that you will need a suitable Linux
>> 2134 distribution to support this.
>> 2135
>> 2136 config PAGE_SIZE_16KB
>> 2137 bool "16kB"
>> 2138 depends on !CPU_R3000
>> 2139 help
>> 2140 Using 16kB page size will result in higher performance kernel at
>> 2141 the price of higher memory consumption. This option is available on
>> 2142 all non-R3000 family processors. Note that you will need a suitable
>> 2143 Linux distribution to support this.
>> 2144
>> 2145 config PAGE_SIZE_32KB
>> 2146 bool "32kB"
>> 2147 depends on CPU_CAVIUM_OCTEON
>> 2148 depends on !MIPS_VA_BITS_48
>> 2149 help
>> 2150 Using 32kB page size will result in higher performance kernel at
>> 2151 the price of higher memory consumption. This option is available
>> 2152 only on cnMIPS cores. Note that you will need a suitable Linux
>> 2153 distribution to support this.
>> 2154
>> 2155 config PAGE_SIZE_64KB
>> 2156 bool "64kB"
>> 2157 depends on !CPU_R3000
>> 2158 help
>> 2159 Using 64kB page size will result in higher performance kernel at
>> 2160 the price of higher memory consumption. This option is available on
>> 2161 all non-R3000 family processor. Not that at the time of this
>> 2162 writing this option is still high experimental.
1205 2163
1206 config FUJITSU_ERRATUM_010001 !! 2164 endchoice
1207 bool "Fujitsu-A64FX erratum E#010001: <<
1208 default y <<
1209 help <<
1210 This option adds a workaround for F <<
1211 On some variants of the Fujitsu-A64 <<
1212 accesses may cause undefined fault <<
1213 This fault occurs under a specific <<
1214 load/store instruction performs an <<
1215 case-1 TTBR0_EL1 with TCR_EL1.NFD0 <<
1216 case-2 TTBR0_EL2 with TCR_EL2.NFD0 <<
1217 case-3 TTBR1_EL1 with TCR_EL1.NFD1 <<
1218 case-4 TTBR1_EL2 with TCR_EL2.NFD1 <<
1219 2165
1220 The workaround is to ensure these b !! 2166 config FORCE_MAX_ZONEORDER
1221 The workaround only affects the Fuj !! 2167 int "Maximum zone order"
>> 2168 range 14 64 if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_64KB
>> 2169 default "14" if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_64KB
>> 2170 range 13 64 if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_32KB
>> 2171 default "13" if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_32KB
>> 2172 range 12 64 if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_16KB
>> 2173 default "12" if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_16KB
>> 2174 range 0 64
>> 2175 default "11"
>> 2176 help
>> 2177 The kernel memory allocator divides physically contiguous memory
>> 2178 blocks into "zones", where each zone is a power of two number of
>> 2179 pages. This option selects the largest power of two that the kernel
>> 2180 keeps in the memory allocator. If you need to allocate very large
>> 2181 blocks of physically contiguous memory, then you may need to
>> 2182 increase this value.
1222 2183
1223 If unsure, say Y. !! 2184 This config option is actually maximum order plus one. For example,
>> 2185 a value of 11 means that the largest free memory block is 2^10 pages.
1224 2186
1225 config HISILICON_ERRATUM_161600802 !! 2187 The page size is not necessarily 4KB. Keep this in mind
1226 bool "Hip07 161600802: Erroneous redi !! 2188 when choosing a value for this option.
1227 default y <<
1228 help <<
1229 The HiSilicon Hip07 SoC uses the wr <<
1230 when issued ITS commands such as VM <<
1231 a 128kB offset to be applied to the <<
1232 2189
1233 If unsure, say Y. !! 2190 config BOARD_SCACHE
>> 2191 bool
1234 2192
1235 config QCOM_FALKOR_ERRATUM_1003 !! 2193 config IP22_CPU_SCACHE
1236 bool "Falkor E1003: Incorrect transla !! 2194 bool
1237 default y !! 2195 select BOARD_SCACHE
1238 help <<
1239 On Falkor v1, an incorrect ASID may <<
1240 and BADDR are changed together in T <<
1241 in TTBR1_EL1, this situation only o <<
1242 then only for entries in the walk c <<
1243 is unchanged. Work around the errat <<
1244 entries for the trampoline before e <<
1245 2196
1246 config QCOM_FALKOR_ERRATUM_1009 !! 2197 #
1247 bool "Falkor E1009: Prematurely compl !! 2198 # Support for a MIPS32 / MIPS64 style S-caches
1248 default y !! 2199 #
1249 select ARM64_WORKAROUND_REPEAT_TLBI !! 2200 config MIPS_CPU_SCACHE
1250 help !! 2201 bool
1251 On Falkor v1, the CPU may premature !! 2202 select BOARD_SCACHE
1252 TLBI xxIS invalidate maintenance op <<
1253 one more time to fix the issue. <<
1254 2203
1255 If unsure, say Y. !! 2204 config R5000_CPU_SCACHE
>> 2205 bool
>> 2206 select BOARD_SCACHE
1256 2207
1257 config QCOM_QDF2400_ERRATUM_0065 !! 2208 config RM7000_CPU_SCACHE
1258 bool "QDF2400 E0065: Incorrect GITS_T !! 2209 bool
1259 default y !! 2210 select BOARD_SCACHE
>> 2211
>> 2212 config SIBYTE_DMA_PAGEOPS
>> 2213 bool "Use DMA to clear/copy pages"
>> 2214 depends on CPU_SB1
1260 help 2215 help
1261 On Qualcomm Datacenter Technologies !! 2216 Instead of using the CPU to zero and copy pages, use a Data Mover
1262 ITE size incorrectly. The GITS_TYPE !! 2217 channel. These DMA channels are otherwise unused by the standard
1263 been indicated as 16Bytes (0xf), no !! 2218 SiByte Linux port. Seems to give a small performance benefit.
1264 2219
1265 If unsure, say Y. !! 2220 config CPU_HAS_PREFETCH
>> 2221 bool
1266 2222
1267 config QCOM_FALKOR_ERRATUM_E1041 !! 2223 config CPU_GENERIC_DUMP_TLB
1268 bool "Falkor E1041: Speculative instr !! 2224 bool
>> 2225 default y if !CPU_R3000
>> 2226
>> 2227 config MIPS_FP_SUPPORT
>> 2228 bool "Floating Point support" if EXPERT
1269 default y 2229 default y
1270 help 2230 help
1271 Falkor CPU may speculatively fetch !! 2231 Select y to include support for floating point in the kernel
1272 memory location when MMU translatio !! 2232 including initialization of FPU hardware, FP context save & restore
1273 to SCTLR_ELn[M]=0. Prefix an ISB in !! 2233 and emulation of an FPU where necessary. Without this support any
>> 2234 userland program attempting to use floating point instructions will
>> 2235 receive a SIGILL.
1274 2236
1275 If unsure, say Y. !! 2237 If you know that your userland will not attempt to use floating point
>> 2238 instructions then you can say n here to shrink the kernel a little.
1276 2239
1277 config NVIDIA_CARMEL_CNP_ERRATUM !! 2240 If unsure, say y.
1278 bool "NVIDIA Carmel CNP: CNP on Carme <<
1279 default y <<
1280 help <<
1281 If CNP is enabled on Carmel cores, <<
1282 invalidate shared TLB entries insta <<
1283 on standard ARM cores. <<
1284 2241
1285 If unsure, say Y. !! 2242 config CPU_R2300_FPU
>> 2243 bool
>> 2244 depends on MIPS_FP_SUPPORT
>> 2245 default y if CPU_R3000
1286 2246
1287 config ROCKCHIP_ERRATUM_3588001 !! 2247 config CPU_R3K_TLB
1288 bool "Rockchip 3588001: GIC600 can no !! 2248 bool
1289 default y <<
1290 help <<
1291 The Rockchip RK3588 GIC600 SoC inte <<
1292 This means, that its sharability fe <<
1293 is supported by the IP itself. <<
1294 2249
1295 If unsure, say Y. !! 2250 config CPU_R4K_FPU
>> 2251 bool
>> 2252 depends on MIPS_FP_SUPPORT
>> 2253 default y if !CPU_R2300_FPU
>> 2254
>> 2255 config CPU_R4K_CACHE_TLB
>> 2256 bool
>> 2257 default y if !(CPU_R3K_TLB || CPU_SB1 || CPU_CAVIUM_OCTEON)
1296 2258
1297 config SOCIONEXT_SYNQUACER_PREITS !! 2259 config MIPS_MT_SMP
1298 bool "Socionext Synquacer: Workaround !! 2260 bool "MIPS MT SMP support (1 TC on each available VPE)"
1299 default y 2261 default y
>> 2262 depends on SYS_SUPPORTS_MULTITHREADING && !CPU_MIPSR6 && !CPU_MICROMIPS
>> 2263 select CPU_MIPSR2_IRQ_VI
>> 2264 select CPU_MIPSR2_IRQ_EI
>> 2265 select SYNC_R4K
>> 2266 select MIPS_MT
>> 2267 select SMP
>> 2268 select SMP_UP
>> 2269 select SYS_SUPPORTS_SMP
>> 2270 select SYS_SUPPORTS_SCHED_SMT
>> 2271 select MIPS_PERF_SHARED_TC_COUNTERS
>> 2272 help
>> 2273 This is a kernel model which is known as SMVP. This is supported
>> 2274 on cores with the MT ASE and uses the available VPEs to implement
>> 2275 virtual processors which supports SMP. This is equivalent to the
>> 2276 Intel Hyperthreading feature. For further information go to
>> 2277 <http://www.imgtec.com/mips/mips-multithreading.asp>.
>> 2278
>> 2279 config MIPS_MT
>> 2280 bool
>> 2281
>> 2282 config SCHED_SMT
>> 2283 bool "SMT (multithreading) scheduler support"
>> 2284 depends on SYS_SUPPORTS_SCHED_SMT
>> 2285 default n
1300 help 2286 help
1301 Socionext Synquacer SoCs implement !! 2287 SMT scheduler support improves the CPU scheduler's decision making
1302 MSI doorbell writes with non-zero v !! 2288 when dealing with MIPS MT enabled cores at a cost of slightly
>> 2289 increased overhead in some places. If unsure say N here.
1303 2290
1304 If unsure, say Y. !! 2291 config SYS_SUPPORTS_SCHED_SMT
>> 2292 bool
1305 2293
1306 endmenu # "ARM errata workarounds via the alt !! 2294 config SYS_SUPPORTS_MULTITHREADING
>> 2295 bool
1307 2296
1308 choice !! 2297 config MIPS_MT_FPAFF
1309 prompt "Page size" !! 2298 bool "Dynamic FPU affinity for FP-intensive threads"
1310 default ARM64_4K_PAGES !! 2299 default y
1311 help !! 2300 depends on MIPS_MT_SMP
1312 Page size (translation granule) con <<
1313 2301
1314 config ARM64_4K_PAGES !! 2302 config MIPSR2_TO_R6_EMULATOR
1315 bool "4KB" !! 2303 bool "MIPS R2-to-R6 emulator"
1316 select HAVE_PAGE_SIZE_4KB !! 2304 depends on CPU_MIPSR6
>> 2305 depends on MIPS_FP_SUPPORT
>> 2306 default y
1317 help 2307 help
1318 This feature enables 4KB pages supp !! 2308 Choose this option if you want to run non-R6 MIPS userland code.
>> 2309 Even if you say 'Y' here, the emulator will still be disabled by
>> 2310 default. You can enable it using the 'mipsr2emu' kernel option.
>> 2311 The only reason this is a build-time option is to save ~14K from the
>> 2312 final kernel image.
1319 2313
1320 config ARM64_16K_PAGES !! 2314 config SYS_SUPPORTS_VPE_LOADER
1321 bool "16KB" !! 2315 bool
1322 select HAVE_PAGE_SIZE_16KB !! 2316 depends on SYS_SUPPORTS_MULTITHREADING
1323 help 2317 help
1324 The system will use 16KB pages supp !! 2318 Indicates that the platform supports the VPE loader, and provides
1325 requires applications compiled with !! 2319 physical_memsize.
1326 aligned segments. <<
1327 2320
1328 config ARM64_64K_PAGES !! 2321 config MIPS_VPE_LOADER
1329 bool "64KB" !! 2322 bool "VPE loader support."
1330 select HAVE_PAGE_SIZE_64KB !! 2323 depends on SYS_SUPPORTS_VPE_LOADER && MODULES
>> 2324 select CPU_MIPSR2_IRQ_VI
>> 2325 select CPU_MIPSR2_IRQ_EI
>> 2326 select MIPS_MT
1331 help 2327 help
1332 This feature enables 64KB pages sup !! 2328 Includes a loader for loading an elf relocatable object
1333 allowing only two levels of page ta !! 2329 onto another VPE and running it.
1334 look-up. AArch32 emulation requires <<
1335 with 64K aligned segments. <<
1336 2330
1337 endchoice !! 2331 config MIPS_VPE_LOADER_CMP
>> 2332 bool
>> 2333 default "y"
>> 2334 depends on MIPS_VPE_LOADER && MIPS_CMP
1338 2335
1339 choice !! 2336 config MIPS_VPE_LOADER_MT
1340 prompt "Virtual address space size" !! 2337 bool
1341 default ARM64_VA_BITS_52 !! 2338 default "y"
1342 help !! 2339 depends on MIPS_VPE_LOADER && !MIPS_CMP
1343 Allows choosing one of multiple pos <<
1344 space sizes. The level of translati <<
1345 a combination of page size and virt <<
1346 <<
1347 config ARM64_VA_BITS_36 <<
1348 bool "36-bit" if EXPERT <<
1349 depends on PAGE_SIZE_16KB <<
1350 <<
1351 config ARM64_VA_BITS_39 <<
1352 bool "39-bit" <<
1353 depends on PAGE_SIZE_4KB <<
1354 <<
1355 config ARM64_VA_BITS_42 <<
1356 bool "42-bit" <<
1357 depends on PAGE_SIZE_64KB <<
1358 <<
1359 config ARM64_VA_BITS_47 <<
1360 bool "47-bit" <<
1361 depends on PAGE_SIZE_16KB <<
1362 <<
1363 config ARM64_VA_BITS_48 <<
1364 bool "48-bit" <<
1365 <<
1366 config ARM64_VA_BITS_52 <<
1367 bool "52-bit" <<
1368 depends on ARM64_PAN || !ARM64_SW_TTB <<
1369 help <<
1370 Enable 52-bit virtual addressing fo <<
1371 requested via a hint to mmap(). The <<
1372 virtual addresses for its own mappi <<
1373 this feature is available, otherwis <<
1374 <<
1375 NOTE: Enabling 52-bit virtual addre <<
1376 ARMv8.3 Pointer Authentication will <<
1377 reduced from 7 bits to 3 bits, whic <<
1378 impact on its susceptibility to bru <<
1379 2340
1380 If unsure, select 48-bit virtual ad !! 2341 config MIPS_VPE_LOADER_TOM
>> 2342 bool "Load VPE program into memory hidden from linux"
>> 2343 depends on MIPS_VPE_LOADER
>> 2344 default y
>> 2345 help
>> 2346 The loader can use memory that is present but has been hidden from
>> 2347 Linux using the kernel command line option "mem=xxMB". It's up to
>> 2348 you to ensure the amount you put in the option and the space your
>> 2349 program requires is less or equal to the amount physically present.
1381 2350
1382 endchoice !! 2351 config MIPS_VPE_APSP_API
>> 2352 bool "Enable support for AP/SP API (RTLX)"
>> 2353 depends on MIPS_VPE_LOADER
1383 2354
1384 config ARM64_FORCE_52BIT !! 2355 config MIPS_VPE_APSP_API_CMP
1385 bool "Force 52-bit virtual addresses !! 2356 bool
1386 depends on ARM64_VA_BITS_52 && EXPERT !! 2357 default "y"
1387 help !! 2358 depends on MIPS_VPE_APSP_API && MIPS_CMP
1388 For systems with 52-bit userspace V <<
1389 to maintain compatibility with olde <<
1390 unless a hint is supplied to mmap. <<
1391 <<
1392 This configuration option disables <<
1393 forces all userspace addresses to b <<
1394 should only enable this configurati <<
1395 memory management code. If unsure s <<
1396 2359
1397 config ARM64_VA_BITS !! 2360 config MIPS_VPE_APSP_API_MT
1398 int !! 2361 bool
1399 default 36 if ARM64_VA_BITS_36 !! 2362 default "y"
1400 default 39 if ARM64_VA_BITS_39 !! 2363 depends on MIPS_VPE_APSP_API && !MIPS_CMP
1401 default 42 if ARM64_VA_BITS_42 <<
1402 default 47 if ARM64_VA_BITS_47 <<
1403 default 48 if ARM64_VA_BITS_48 <<
1404 default 52 if ARM64_VA_BITS_52 <<
1405 2364
1406 choice !! 2365 config MIPS_CMP
1407 prompt "Physical address space size" !! 2366 bool "MIPS CMP framework support (DEPRECATED)"
1408 default ARM64_PA_BITS_48 !! 2367 depends on SYS_SUPPORTS_MIPS_CMP && !CPU_MIPSR6
>> 2368 select SMP
>> 2369 select SYNC_R4K
>> 2370 select SYS_SUPPORTS_SMP
>> 2371 select WEAK_ORDERING
>> 2372 default n
1409 help 2373 help
1410 Choose the maximum physical address !! 2374 Select this if you are using a bootloader which implements the "CMP
1411 support. !! 2375 framework" protocol (ie. YAMON) and want your kernel to make use of
>> 2376 its ability to start secondary CPUs.
>> 2377
>> 2378 Unless you have a specific need, you should use CONFIG_MIPS_CPS
>> 2379 instead of this.
>> 2380
>> 2381 config MIPS_CPS
>> 2382 bool "MIPS Coherent Processing System support"
>> 2383 depends on SYS_SUPPORTS_MIPS_CPS
>> 2384 select MIPS_CM
>> 2385 select MIPS_CPS_PM if HOTPLUG_CPU
>> 2386 select SMP
>> 2387 select SYNC_R4K if (CEVT_R4K || CSRC_R4K)
>> 2388 select SYS_SUPPORTS_HOTPLUG_CPU
>> 2389 select SYS_SUPPORTS_SCHED_SMT if CPU_MIPSR6
>> 2390 select SYS_SUPPORTS_SMP
>> 2391 select WEAK_ORDERING
>> 2392 select GENERIC_IRQ_MIGRATION if HOTPLUG_CPU
>> 2393 help
>> 2394 Select this if you wish to run an SMP kernel across multiple cores
>> 2395 within a MIPS Coherent Processing System. When this option is
>> 2396 enabled the kernel will probe for other cores and boot them with
>> 2397 no external assistance. It is safe to enable this when hardware
>> 2398 support is unavailable.
1412 2399
1413 config ARM64_PA_BITS_48 !! 2400 config MIPS_CPS_PM
1414 bool "48-bit" !! 2401 depends on MIPS_CPS
1415 depends on ARM64_64K_PAGES || !ARM64_ !! 2402 bool
1416 <<
1417 config ARM64_PA_BITS_52 <<
1418 bool "52-bit" <<
1419 depends on ARM64_64K_PAGES || ARM64_V <<
1420 depends on ARM64_PAN || !ARM64_SW_TTB <<
1421 help <<
1422 Enable support for a 52-bit physica <<
1423 part of the ARMv8.2-LPA extension. <<
1424 <<
1425 With this enabled, the kernel will <<
1426 do not support ARMv8.2-LPA, but wit <<
1427 minor performance overhead). <<
1428 2403
1429 endchoice !! 2404 config MIPS_CM
>> 2405 bool
>> 2406 select MIPS_CPC
1430 2407
1431 config ARM64_PA_BITS !! 2408 config MIPS_CPC
1432 int !! 2409 bool
1433 default 48 if ARM64_PA_BITS_48 <<
1434 default 52 if ARM64_PA_BITS_52 <<
1435 2410
1436 config ARM64_LPA2 !! 2411 config SB1_PASS_2_WORKAROUNDS
1437 def_bool y !! 2412 bool
1438 depends on ARM64_PA_BITS_52 && !ARM64 !! 2413 depends on CPU_SB1 && (CPU_SB1_PASS_2_2 || CPU_SB1_PASS_2)
>> 2414 default y
>> 2415
>> 2416 config SB1_PASS_2_1_WORKAROUNDS
>> 2417 bool
>> 2418 depends on CPU_SB1 && CPU_SB1_PASS_2
>> 2419 default y
1439 2420
1440 choice 2421 choice
1441 prompt "Endianness" !! 2422 prompt "SmartMIPS or microMIPS ASE support"
1442 default CPU_LITTLE_ENDIAN <<
1443 help <<
1444 Select the endianness of data acces <<
1445 applications will need to be compil <<
1446 that is selected here. <<
1447 2423
1448 config CPU_BIG_ENDIAN !! 2424 config CPU_NEEDS_NO_SMARTMIPS_OR_MICROMIPS
1449 bool "Build big-endian kernel" !! 2425 bool "None"
1450 # https://github.com/llvm/llvm-projec <<
1451 depends on AS_IS_GNU || AS_VERSION >= <<
1452 help 2426 help
1453 Say Y if you plan on running a kern !! 2427 Select this if you want neither microMIPS nor SmartMIPS support
1454 2428
1455 config CPU_LITTLE_ENDIAN !! 2429 config CPU_HAS_SMARTMIPS
1456 bool "Build little-endian kernel" !! 2430 depends on SYS_SUPPORTS_SMARTMIPS
>> 2431 bool "SmartMIPS"
>> 2432 help
>> 2433 SmartMIPS is a extension of the MIPS32 architecture aimed at
>> 2434 increased security at both hardware and software level for
>> 2435 smartcards. Enabling this option will allow proper use of the
>> 2436 SmartMIPS instructions by Linux applications. However a kernel with
>> 2437 this option will not work on a MIPS core without SmartMIPS core. If
>> 2438 you don't know you probably don't have SmartMIPS and should say N
>> 2439 here.
>> 2440
>> 2441 config CPU_MICROMIPS
>> 2442 depends on 32BIT && SYS_SUPPORTS_MICROMIPS && !CPU_MIPSR6
>> 2443 bool "microMIPS"
1457 help 2444 help
1458 Say Y if you plan on running a kern !! 2445 When this option is enabled the kernel will be built using the
1459 This is usually the case for distri !! 2446 microMIPS ISA
1460 2447
1461 endchoice 2448 endchoice
1462 2449
1463 config SCHED_MC !! 2450 config CPU_HAS_MSA
1464 bool "Multi-core scheduler support" !! 2451 bool "Support for the MIPS SIMD Architecture"
1465 help !! 2452 depends on CPU_SUPPORTS_MSA
1466 Multi-core scheduler support improv !! 2453 depends on MIPS_FP_SUPPORT
1467 making when dealing with multi-core !! 2454 depends on 64BIT || MIPS_O32_FP64_SUPPORT
1468 increased overhead in some places. !! 2455 help
>> 2456 MIPS SIMD Architecture (MSA) introduces 128 bit wide vector registers
>> 2457 and a set of SIMD instructions to operate on them. When this option
>> 2458 is enabled the kernel will support allocating & switching MSA
>> 2459 vector register contexts. If you know that your kernel will only be
>> 2460 running on CPUs which do not support MSA or that your userland will
>> 2461 not be making use of it then you may wish to say N here to reduce
>> 2462 the size & complexity of your kernel.
1469 2463
1470 config SCHED_CLUSTER !! 2464 If unsure, say Y.
1471 bool "Cluster scheduler support" <<
1472 help <<
1473 Cluster scheduler support improves <<
1474 making when dealing with machines t <<
1475 Cluster usually means a couple of C <<
1476 by sharing mid-level caches, last-l <<
1477 busses. <<
1478 2465
1479 config SCHED_SMT !! 2466 config CPU_HAS_WB
1480 bool "SMT scheduler support" !! 2467 bool
1481 help <<
1482 Improves the CPU scheduler's decisi <<
1483 MultiThreading at a cost of slightl <<
1484 places. If unsure say N here. <<
1485 2468
1486 config NR_CPUS !! 2469 config XKS01
1487 int "Maximum number of CPUs (2-4096)" !! 2470 bool
1488 range 2 4096 <<
1489 default "512" <<
1490 2471
1491 config HOTPLUG_CPU !! 2472 config CPU_HAS_DIEI
1492 bool "Support for hot-pluggable CPUs" !! 2473 depends on !CPU_DIEI_BROKEN
1493 select GENERIC_IRQ_MIGRATION !! 2474 bool
1494 help <<
1495 Say Y here to experiment with turni <<
1496 can be controlled through /sys/devi <<
1497 2475
1498 # Common NUMA Features !! 2476 config CPU_DIEI_BROKEN
1499 config NUMA !! 2477 bool
1500 bool "NUMA Memory Allocation and Sche <<
1501 select GENERIC_ARCH_NUMA <<
1502 select OF_NUMA <<
1503 select HAVE_SETUP_PER_CPU_AREA <<
1504 select NEED_PER_CPU_EMBED_FIRST_CHUNK <<
1505 select NEED_PER_CPU_PAGE_FIRST_CHUNK <<
1506 select USE_PERCPU_NUMA_NODE_ID <<
1507 help <<
1508 Enable NUMA (Non-Uniform Memory Acc <<
1509 2478
1510 The kernel will try to allocate mem !! 2479 config CPU_HAS_RIXI
1511 local memory of the CPU and add som !! 2480 bool
1512 NUMA awareness to the kernel. <<
1513 2481
1514 config NODES_SHIFT !! 2482 config CPU_NO_LOAD_STORE_LR
1515 int "Maximum NUMA Nodes (as a power o !! 2483 bool
1516 range 1 10 <<
1517 default "4" <<
1518 depends on NUMA <<
1519 help 2484 help
1520 Specify the maximum number of NUMA !! 2485 CPU lacks support for unaligned load and store instructions:
1521 system. Increases memory reserved !! 2486 LWL, LWR, SWL, SWR (Load/store word left/right).
>> 2487 LDL, LDR, SDL, SDR (Load/store doubleword left/right, for 64bit
>> 2488 systems).
1522 2489
1523 source "kernel/Kconfig.hz" !! 2490 #
>> 2491 # Vectored interrupt mode is an R2 feature
>> 2492 #
>> 2493 config CPU_MIPSR2_IRQ_VI
>> 2494 bool
1524 2495
1525 config ARCH_SPARSEMEM_ENABLE !! 2496 #
1526 def_bool y !! 2497 # Extended interrupt mode is an R2 feature
1527 select SPARSEMEM_VMEMMAP_ENABLE !! 2498 #
1528 select SPARSEMEM_VMEMMAP !! 2499 config CPU_MIPSR2_IRQ_EI
>> 2500 bool
1529 2501
1530 config HW_PERF_EVENTS !! 2502 config CPU_HAS_SYNC
1531 def_bool y !! 2503 bool
1532 depends on ARM_PMU !! 2504 depends on !CPU_R3000
>> 2505 default y
1533 2506
1534 # Supported by clang >= 7.0 or GCC >= 12.0.0 !! 2507 #
1535 config CC_HAVE_SHADOW_CALL_STACK !! 2508 # CPU non-features
1536 def_bool $(cc-option, -fsanitize=shad !! 2509 #
1537 2510
1538 config PARAVIRT !! 2511 # Work around the "daddi" and "daddiu" CPU errata:
1539 bool "Enable paravirtualization code" !! 2512 #
1540 help !! 2513 # - The `daddi' instruction fails to trap on overflow.
1541 This changes the kernel so it can m !! 2514 # "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0",
1542 under a hypervisor, potentially imp !! 2515 # erratum #23
1543 over full virtualization. !! 2516 #
>> 2517 # - The `daddiu' instruction can produce an incorrect result.
>> 2518 # "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0",
>> 2519 # erratum #41
>> 2520 # "MIPS R4000MC Errata, Processor Revision 2.2 and 3.0", erratum
>> 2521 # #15
>> 2522 # "MIPS R4400PC/SC Errata, Processor Revision 1.0", erratum #7
>> 2523 # "MIPS R4400MC Errata, Processor Revision 1.0", erratum #5
>> 2524 config CPU_DADDI_WORKAROUNDS
>> 2525 bool
1544 2526
1545 config PARAVIRT_TIME_ACCOUNTING !! 2527 # Work around certain R4000 CPU errata (as implemented by GCC):
1546 bool "Paravirtual steal time accounti !! 2528 #
1547 select PARAVIRT !! 2529 # - A double-word or a variable shift may give an incorrect result
1548 help !! 2530 # if executed immediately after starting an integer division:
1549 Select this option to enable fine g !! 2531 # "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0",
1550 accounting. Time spent executing ot !! 2532 # erratum #28
1551 the current vCPU is discounted from !! 2533 # "MIPS R4000MC Errata, Processor Revision 2.2 and 3.0", erratum
1552 that, there can be a small performa !! 2534 # #19
>> 2535 #
>> 2536 # - A double-word or a variable shift may give an incorrect result
>> 2537 # if executed while an integer multiplication is in progress:
>> 2538 # "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0",
>> 2539 # errata #16 & #28
>> 2540 #
>> 2541 # - An integer division may give an incorrect result if started in
>> 2542 # a delay slot of a taken branch or a jump:
>> 2543 # "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0",
>> 2544 # erratum #52
>> 2545 config CPU_R4000_WORKAROUNDS
>> 2546 bool
>> 2547 select CPU_R4400_WORKAROUNDS
1553 2548
1554 If in doubt, say N here. !! 2549 # Work around certain R4400 CPU errata (as implemented by GCC):
>> 2550 #
>> 2551 # - A double-word or a variable shift may give an incorrect result
>> 2552 # if executed immediately after starting an integer division:
>> 2553 # "MIPS R4400MC Errata, Processor Revision 1.0", erratum #10
>> 2554 # "MIPS R4400MC Errata, Processor Revision 2.0 & 3.0", erratum #4
>> 2555 config CPU_R4400_WORKAROUNDS
>> 2556 bool
1555 2557
1556 config ARCH_SUPPORTS_KEXEC !! 2558 config CPU_R4X00_BUGS64
1557 def_bool PM_SLEEP_SMP !! 2559 bool
>> 2560 default y if SYS_HAS_CPU_R4X00 && 64BIT && (TARGET_ISA_REV < 1)
1558 2561
1559 config ARCH_SUPPORTS_KEXEC_FILE !! 2562 config MIPS_ASID_SHIFT
1560 def_bool y !! 2563 int
>> 2564 default 6 if CPU_R3000
>> 2565 default 0
1561 2566
1562 config ARCH_SELECTS_KEXEC_FILE !! 2567 config MIPS_ASID_BITS
1563 def_bool y !! 2568 int
1564 depends on KEXEC_FILE !! 2569 default 0 if MIPS_ASID_BITS_VARIABLE
1565 select HAVE_IMA_KEXEC if IMA !! 2570 default 6 if CPU_R3000
>> 2571 default 8
1566 2572
1567 config ARCH_SUPPORTS_KEXEC_SIG !! 2573 config MIPS_ASID_BITS_VARIABLE
1568 def_bool y !! 2574 bool
1569 2575
1570 config ARCH_SUPPORTS_KEXEC_IMAGE_VERIFY_SIG !! 2576 config MIPS_CRC_SUPPORT
1571 def_bool y !! 2577 bool
1572 2578
1573 config ARCH_DEFAULT_KEXEC_IMAGE_VERIFY_SIG !! 2579 # R4600 erratum. Due to the lack of errata information the exact
1574 def_bool y !! 2580 # technical details aren't known. I've experimentally found that disabling
>> 2581 # interrupts during indexed I-cache flushes seems to be sufficient to deal
>> 2582 # with the issue.
>> 2583 config WAR_R4600_V1_INDEX_ICACHEOP
>> 2584 bool
1575 2585
1576 config ARCH_SUPPORTS_CRASH_DUMP !! 2586 # Pleasures of the R4600 V1.x. Cite from the IDT R4600 V1.7 errata:
1577 def_bool y !! 2587 #
>> 2588 # 18. The CACHE instructions Hit_Writeback_Invalidate_D, Hit_Writeback_D,
>> 2589 # Hit_Invalidate_D and Create_Dirty_Excl_D should only be
>> 2590 # executed if there is no other dcache activity. If the dcache is
>> 2591 # accessed for another instruction immediately preceding when these
>> 2592 # cache instructions are executing, it is possible that the dcache
>> 2593 # tag match outputs used by these cache instructions will be
>> 2594 # incorrect. These cache instructions should be preceded by at least
>> 2595 # four instructions that are not any kind of load or store
>> 2596 # instruction.
>> 2597 #
>> 2598 # This is not allowed: lw
>> 2599 # nop
>> 2600 # nop
>> 2601 # nop
>> 2602 # cache Hit_Writeback_Invalidate_D
>> 2603 #
>> 2604 # This is allowed: lw
>> 2605 # nop
>> 2606 # nop
>> 2607 # nop
>> 2608 # nop
>> 2609 # cache Hit_Writeback_Invalidate_D
>> 2610 config WAR_R4600_V1_HIT_CACHEOP
>> 2611 bool
1578 2612
1579 config ARCH_HAS_GENERIC_CRASHKERNEL_RESERVATI !! 2613 # Writeback and invalidate the primary cache dcache before DMA.
1580 def_bool CRASH_RESERVE !! 2614 #
>> 2615 # R4600 v2.0 bug: "The CACHE instructions Hit_Writeback_Inv_D,
>> 2616 # Hit_Writeback_D, Hit_Invalidate_D and Create_Dirty_Exclusive_D will only
>> 2617 # operate correctly if the internal data cache refill buffer is empty. These
>> 2618 # CACHE instructions should be separated from any potential data cache miss
>> 2619 # by a load instruction to an uncached address to empty the response buffer."
>> 2620 # (Revision 2.0 device errata from IDT available on https://www.idt.com/
>> 2621 # in .pdf format.)
>> 2622 config WAR_R4600_V2_HIT_CACHEOP
>> 2623 bool
1581 2624
1582 config TRANS_TABLE !! 2625 # From TX49/H2 manual: "If the instruction (i.e. CACHE) is issued for
1583 def_bool y !! 2626 # the line which this instruction itself exists, the following
1584 depends on HIBERNATION || KEXEC_CORE !! 2627 # operation is not guaranteed."
>> 2628 #
>> 2629 # Workaround: do two phase flushing for Index_Invalidate_I
>> 2630 config WAR_TX49XX_ICACHE_INDEX_INV
>> 2631 bool
1585 2632
1586 config XEN_DOM0 !! 2633 # The RM7000 processors and the E9000 cores have a bug (though PMC-Sierra
1587 def_bool y !! 2634 # opposes it being called that) where invalid instructions in the same
1588 depends on XEN !! 2635 # I-cache line worth of instructions being fetched may case spurious
>> 2636 # exceptions.
>> 2637 config WAR_ICACHE_REFILLS
>> 2638 bool
1589 2639
1590 config XEN !! 2640 # On the R10000 up to version 2.6 (not sure about 2.7) there is a bug that
1591 bool "Xen guest support on ARM64" !! 2641 # may cause ll / sc and lld / scd sequences to execute non-atomically.
1592 depends on ARM64 && OF !! 2642 config WAR_R10000_LLSC
1593 select SWIOTLB_XEN !! 2643 bool
1594 select PARAVIRT !! 2644
1595 help !! 2645 # 34K core erratum: "Problems Executing the TLBR Instruction"
1596 Say Y if you want to run Linux in a !! 2646 config WAR_MIPS34K_MISSED_ITLB
>> 2647 bool
1597 2648
1598 # include/linux/mmzone.h requires the followi <<
1599 # <<
1600 # MAX_PAGE_ORDER + PAGE_SHIFT <= SECTION_SI <<
1601 # 2649 #
1602 # so the maximum value of MAX_PAGE_ORDER is S !! 2650 # - Highmem only makes sense for the 32-bit kernel.
>> 2651 # - The current highmem code will only work properly on physically indexed
>> 2652 # caches such as R3000, SB1, R7000 or those that look like they're virtually
>> 2653 # indexed such as R4000/R4400 SC and MC versions or R10000. So for the
>> 2654 # moment we protect the user and offer the highmem option only on machines
>> 2655 # where it's known to be safe. This will not offer highmem on a few systems
>> 2656 # such as MIPS32 and MIPS64 CPUs which may have virtual and physically
>> 2657 # indexed CPUs but we're playing safe.
>> 2658 # - We use SYS_SUPPORTS_HIGHMEM to offer highmem only for systems where we
>> 2659 # know they might have memory configurations that could make use of highmem
>> 2660 # support.
1603 # 2661 #
1604 # | SECTION_SIZE_BITS | PAGE_SHIFT | m !! 2662 config HIGHMEM
1605 # ----+-------------------+--------------+--- !! 2663 bool "High Memory Support"
1606 # 4K | 27 | 12 | !! 2664 depends on 32BIT && CPU_SUPPORTS_HIGHMEM && SYS_SUPPORTS_HIGHMEM && !CPU_MIPS32_3_5_EVA
1607 # 16K | 27 | 14 | !! 2665 select KMAP_LOCAL
1608 # 64K | 29 | 16 | <<
1609 config ARCH_FORCE_MAX_ORDER <<
1610 int <<
1611 default "13" if ARM64_64K_PAGES <<
1612 default "11" if ARM64_16K_PAGES <<
1613 default "10" <<
1614 help <<
1615 The kernel page allocator limits th <<
1616 contiguous allocations. The limit i <<
1617 defines the maximal power of two of <<
1618 allocated as a single contiguous bl <<
1619 overriding the default setting when <<
1620 large blocks of physically contiguo <<
1621 <<
1622 The maximal size of allocation cann <<
1623 section, so the value of MAX_PAGE_O <<
1624 2666
1625 MAX_PAGE_ORDER + PAGE_SHIFT <= SE !! 2667 config CPU_SUPPORTS_HIGHMEM
1626 !! 2668 bool
1627 Don't change if unsure. <<
1628 2669
1629 config UNMAP_KERNEL_AT_EL0 !! 2670 config SYS_SUPPORTS_HIGHMEM
1630 bool "Unmap kernel when running in us !! 2671 bool
1631 default y <<
1632 help <<
1633 Speculation attacks against some hi <<
1634 be used to bypass MMU permission ch <<
1635 userspace. This can be defended aga <<
1636 when running in userspace, mapping <<
1637 via a trampoline page in the vector <<
1638 2672
1639 If unsure, say Y. !! 2673 config SYS_SUPPORTS_SMARTMIPS
>> 2674 bool
1640 2675
1641 config MITIGATE_SPECTRE_BRANCH_HISTORY !! 2676 config SYS_SUPPORTS_MICROMIPS
1642 bool "Mitigate Spectre style attacks !! 2677 bool
1643 default y <<
1644 help <<
1645 Speculation attacks against some hi <<
1646 make use of branch history to influ <<
1647 When taking an exception from user- <<
1648 or a firmware call overwrites the b <<
1649 2678
1650 config RODATA_FULL_DEFAULT_ENABLED !! 2679 config SYS_SUPPORTS_MIPS16
1651 bool "Apply r/o permissions of VM are !! 2680 bool
1652 default y <<
1653 help 2681 help
1654 Apply read-only attributes of VM ar !! 2682 This option must be set if a kernel might be executed on a MIPS16-
1655 the backing pages as well. This pre !! 2683 enabled CPU even if MIPS16 is not actually being used. In other
1656 from being modified (inadvertently !! 2684 words, it makes the kernel MIPS16-tolerant.
1657 mapping of the same memory page. Th <<
1658 be turned off at runtime by passing <<
1659 with rodata=full if this option is <<
1660 <<
1661 This requires the linear region to <<
1662 which may adversely affect performa <<
1663 <<
1664 config ARM64_SW_TTBR0_PAN <<
1665 bool "Emulate Privileged Access Never <<
1666 depends on !KCSAN <<
1667 help <<
1668 Enabling this option prevents the k <<
1669 user-space memory directly by point <<
1670 zeroed area and reserved ASID. The <<
1671 restore the valid TTBR0_EL1 tempora <<
1672 2685
1673 config ARM64_TAGGED_ADDR_ABI !! 2686 config CPU_SUPPORTS_MSA
1674 bool "Enable the tagged user addresse !! 2687 bool
1675 default y <<
1676 help <<
1677 When this option is enabled, user a <<
1678 relaxed ABI via prctl() allowing ta <<
1679 to system calls as pointer argument <<
1680 Documentation/arch/arm64/tagged-add <<
1681 <<
1682 menuconfig COMPAT <<
1683 bool "Kernel support for 32-bit EL0" <<
1684 depends on ARM64_4K_PAGES || EXPERT <<
1685 select HAVE_UID16 <<
1686 select OLD_SIGSUSPEND3 <<
1687 select COMPAT_OLD_SIGACTION <<
1688 help <<
1689 This option enables support for a 3 <<
1690 kernel at EL1. AArch32-specific com <<
1691 the user helper functions, VFP supp <<
1692 handled appropriately by the kernel <<
1693 <<
1694 If you use a page size other than 4 <<
1695 that you will only be able to execu <<
1696 with page size aligned segments. <<
1697 2688
1698 If you want to execute 32-bit users !! 2689 config ARCH_FLATMEM_ENABLE
>> 2690 def_bool y
>> 2691 depends on !NUMA && !CPU_LOONGSON2EF
1699 2692
1700 if COMPAT !! 2693 config ARCH_SPARSEMEM_ENABLE
>> 2694 bool
>> 2695 select SPARSEMEM_STATIC if !SGI_IP27
1701 2696
1702 config KUSER_HELPERS !! 2697 config NUMA
1703 bool "Enable kuser helpers page for 3 !! 2698 bool "NUMA Support"
1704 default y !! 2699 depends on SYS_SUPPORTS_NUMA
>> 2700 select SMP
>> 2701 select HAVE_SETUP_PER_CPU_AREA
>> 2702 select NEED_PER_CPU_EMBED_FIRST_CHUNK
1705 help 2703 help
1706 Warning: disabling this option may !! 2704 Say Y to compile the kernel to support NUMA (Non-Uniform Memory
>> 2705 Access). This option improves performance on systems with more
>> 2706 than two nodes; on two node systems it is generally better to
>> 2707 leave it disabled; on single node systems leave this option
>> 2708 disabled.
1707 2709
1708 Provide kuser helpers to compat tas !! 2710 config SYS_SUPPORTS_NUMA
1709 helper code to userspace in read on !! 2711 bool
1710 to allow userspace to be independen <<
1711 the system. This permits binaries t <<
1712 to ARMv8 without modification. <<
1713 <<
1714 See Documentation/arch/arm/kernel_u <<
1715 <<
1716 However, the fixed address nature o <<
1717 by ROP (return orientated programmi <<
1718 exploits. <<
1719 <<
1720 If all of the binaries and librarie <<
1721 are built specifically for your pla <<
1722 these helpers, then you can turn th <<
1723 such exploits. However, in that cas <<
1724 relying on those helpers is run, it <<
1725 <<
1726 Say N here only if you are absolute <<
1727 need these helpers; otherwise, the <<
1728 <<
1729 config COMPAT_VDSO <<
1730 bool "Enable vDSO for 32-bit applicat <<
1731 depends on !CPU_BIG_ENDIAN <<
1732 depends on (CC_IS_CLANG && LD_IS_LLD) <<
1733 select GENERIC_COMPAT_VDSO <<
1734 default y <<
1735 help <<
1736 Place in the process address space <<
1737 ELF shared object providing fast im <<
1738 and clock_gettime. <<
1739 <<
1740 You must have a 32-bit build of gli <<
1741 to seamlessly take advantage of thi <<
1742 <<
1743 config THUMB2_COMPAT_VDSO <<
1744 bool "Compile the 32-bit vDSO for Thu <<
1745 depends on COMPAT_VDSO <<
1746 default y <<
1747 help <<
1748 Compile the compat vDSO with '-mthu <<
1749 otherwise with '-marm'. <<
1750 2712
1751 config COMPAT_ALIGNMENT_FIXUPS !! 2713 config HAVE_ARCH_NODEDATA_EXTENSION
1752 bool "Fix up misaligned multi-word lo !! 2714 bool
1753 2715
1754 menuconfig ARMV8_DEPRECATED !! 2716 config RELOCATABLE
1755 bool "Emulate deprecated/obsolete ARM !! 2717 bool "Relocatable kernel"
1756 depends on SYSCTL !! 2718 depends on SYS_SUPPORTS_RELOCATABLE
1757 help !! 2719 depends on CPU_MIPS32_R2 || CPU_MIPS64_R2 || \
1758 Legacy software support may require !! 2720 CPU_MIPS32_R5 || CPU_MIPS64_R5 || \
1759 that have been deprecated or obsole !! 2721 CPU_MIPS32_R6 || CPU_MIPS64_R6 || \
>> 2722 CPU_P5600 || CAVIUM_OCTEON_SOC || \
>> 2723 CPU_LOONGSON64
>> 2724 help
>> 2725 This builds a kernel image that retains relocation information
>> 2726 so it can be loaded someplace besides the default 1MB.
>> 2727 The relocations make the kernel binary about 15% larger,
>> 2728 but are discarded at runtime
>> 2729
>> 2730 config RELOCATION_TABLE_SIZE
>> 2731 hex "Relocation table size"
>> 2732 depends on RELOCATABLE
>> 2733 range 0x0 0x01000000
>> 2734 default "0x00200000" if CPU_LOONGSON64
>> 2735 default "0x00100000"
>> 2736 help
>> 2737 A table of relocation data will be appended to the kernel binary
>> 2738 and parsed at boot to fix up the relocated kernel.
1760 2739
1761 Enable this config to enable select !! 2740 This option allows the amount of space reserved for the table to be
1762 features. !! 2741 adjusted, although the default of 1Mb should be ok in most cases.
1763 2742
1764 If unsure, say Y !! 2743 The build will fail and a valid size suggested if this is too small.
1765 2744
1766 if ARMV8_DEPRECATED !! 2745 If unsure, leave at the default value.
1767 2746
1768 config SWP_EMULATION !! 2747 config RANDOMIZE_BASE
1769 bool "Emulate SWP/SWPB instructions" !! 2748 bool "Randomize the address of the kernel image"
>> 2749 depends on RELOCATABLE
1770 help 2750 help
1771 ARMv8 obsoletes the use of A32 SWP/ !! 2751 Randomizes the physical and virtual address at which the
1772 they are always undefined. Say Y he !! 2752 kernel image is loaded, as a security feature that
1773 emulation of these instructions for !! 2753 deters exploit attempts relying on knowledge of the location
1774 This feature can be controlled at r !! 2754 of kernel internals.
1775 sysctl which is disabled by default <<
1776 2755
1777 In some older versions of glibc [<= !! 2756 Entropy is generated using any coprocessor 0 registers available.
1778 trylock() operations with the assum <<
1779 be preempted. This invalid assumpti <<
1780 with SWP emulation enabled, leading <<
1781 application. <<
1782 2757
1783 NOTE: when accessing uncached share !! 2758 The kernel will be offset by up to RANDOMIZE_BASE_MAX_OFFSET.
1784 on an external transaction monitori <<
1785 monitor to maintain update atomicit <<
1786 implement a global monitor, this op <<
1787 perform SWP operations to uncached <<
1788 2759
1789 If unsure, say Y !! 2760 If unsure, say N.
1790 2761
1791 config CP15_BARRIER_EMULATION !! 2762 config RANDOMIZE_BASE_MAX_OFFSET
1792 bool "Emulate CP15 Barrier instructio !! 2763 hex "Maximum kASLR offset" if EXPERT
1793 help !! 2764 depends on RANDOMIZE_BASE
1794 The CP15 barrier instructions - CP1 !! 2765 range 0x0 0x40000000 if EVA || 64BIT
1795 CP15DMB - are deprecated in ARMv8 ( !! 2766 range 0x0 0x08000000
1796 strongly recommended to use the ISB !! 2767 default "0x01000000"
1797 instructions instead. !! 2768 help
>> 2769 When kASLR is active, this provides the maximum offset that will
>> 2770 be applied to the kernel image. It should be set according to the
>> 2771 amount of physical RAM available in the target system minus
>> 2772 PHYSICAL_START and must be a power of 2.
1798 2773
1799 Say Y here to enable software emula !! 2774 This is limited by the size of KSEG0, 256Mb on 32-bit or 1Gb with
1800 instructions for AArch32 userspace !! 2775 EVA or 64-bit. The default is 16Mb.
1801 enabled, CP15 barrier usage is trac <<
1802 identify software that needs updati <<
1803 controlled at runtime with the abi. <<
1804 2776
1805 If unsure, say Y !! 2777 config NODES_SHIFT
>> 2778 int
>> 2779 default "6"
>> 2780 depends on NUMA
1806 2781
1807 config SETEND_EMULATION !! 2782 config HW_PERF_EVENTS
1808 bool "Emulate SETEND instruction" !! 2783 bool "Enable hardware performance counter support for perf events"
>> 2784 depends on PERF_EVENTS && (CPU_MIPS32 || CPU_MIPS64 || CPU_R10000 || CPU_SB1 || CPU_CAVIUM_OCTEON || CPU_LOONGSON64)
>> 2785 default y
1809 help 2786 help
1810 The SETEND instruction alters the d !! 2787 Enable hardware performance counter support for perf events. If
1811 AArch32 EL0, and is deprecated in A !! 2788 disabled, perf events will use software events only.
1812 2789
1813 Say Y here to enable software emula !! 2790 config DMI
1814 for AArch32 userspace code. This fe !! 2791 bool "Enable DMI scanning"
1815 at runtime with the abi.setend sysc !! 2792 depends on MACH_LOONGSON64
>> 2793 select DMI_SCAN_MACHINE_NON_EFI_FALLBACK
>> 2794 default y
>> 2795 help
>> 2796 Enabled scanning of DMI to identify machine quirks. Say Y
>> 2797 here unless you have verified that your setup is not
>> 2798 affected by entries in the DMI blacklist. Required by PNP
>> 2799 BIOS code.
1816 2800
1817 Note: All the cpus on the system mu !! 2801 config SMP
1818 for this feature to be enabled. If !! 2802 bool "Multi-Processing support"
1819 endian - is hotplugged in after thi !! 2803 depends on SYS_SUPPORTS_SMP
1820 be unexpected results in the applic !! 2804 help
>> 2805 This enables support for systems with more than one CPU. If you have
>> 2806 a system with only one CPU, say N. If you have a system with more
>> 2807 than one CPU, say Y.
>> 2808
>> 2809 If you say N here, the kernel will run on uni- and multiprocessor
>> 2810 machines, but will use only one CPU of a multiprocessor machine. If
>> 2811 you say Y here, the kernel will run on many, but not all,
>> 2812 uniprocessor machines. On a uniprocessor machine, the kernel
>> 2813 will run faster if you say N here.
1821 2814
1822 If unsure, say Y !! 2815 People using multiprocessor machines who say Y here should also say
1823 endif # ARMV8_DEPRECATED !! 2816 Y to "Enhanced Real Time Clock Support", below.
1824 2817
1825 endif # COMPAT !! 2818 See also the SMP-HOWTO available at
>> 2819 <https://www.tldp.org/docs.html#howto>.
1826 2820
1827 menu "ARMv8.1 architectural features" !! 2821 If you don't know what to do here, say N.
1828 2822
1829 config ARM64_HW_AFDBM !! 2823 config HOTPLUG_CPU
1830 bool "Support for hardware updates of !! 2824 bool "Support for hot-pluggable CPUs"
1831 default y !! 2825 depends on SMP && SYS_SUPPORTS_HOTPLUG_CPU
1832 help 2826 help
1833 The ARMv8.1 architecture extensions !! 2827 Say Y here to allow turning CPUs off and on. CPUs can be
1834 hardware updates of the access and !! 2828 controlled through /sys/devices/system/cpu.
1835 table entries. When enabled in TCR_ !! 2829 (Note: power management support will enable this option
1836 capable processors, accesses to pag !! 2830 automatically on SMP systems. )
1837 set this bit instead of raising an !! 2831 Say N if you want to disable CPU hotplug.
1838 Similarly, writes to read-only page <<
1839 clear the read-only bit (AP[2]) ins <<
1840 permission fault. <<
1841 <<
1842 Kernels built with this configurati <<
1843 to work on pre-ARMv8.1 hardware and <<
1844 minimal. If unsure, say Y. <<
1845 2832
1846 config ARM64_PAN !! 2833 config SMP_UP
1847 bool "Enable support for Privileged A !! 2834 bool
1848 default y <<
1849 help <<
1850 Privileged Access Never (PAN; part <<
1851 prevents the kernel or hypervisor f <<
1852 memory directly. <<
1853 2835
1854 Choosing this option will cause any !! 2836 config SYS_SUPPORTS_MIPS_CMP
1855 copy_to_user et al) memory access t !! 2837 bool
1856 2838
1857 The feature is detected at runtime, !! 2839 config SYS_SUPPORTS_MIPS_CPS
1858 instruction if the cpu does not imp !! 2840 bool
1859 2841
1860 config AS_HAS_LSE_ATOMICS !! 2842 config SYS_SUPPORTS_SMP
1861 def_bool $(as-instr,.arch_extension l !! 2843 bool
1862 2844
1863 config ARM64_LSE_ATOMICS !! 2845 config NR_CPUS_DEFAULT_4
1864 bool 2846 bool
1865 default ARM64_USE_LSE_ATOMICS <<
1866 depends on AS_HAS_LSE_ATOMICS <<
1867 2847
1868 config ARM64_USE_LSE_ATOMICS !! 2848 config NR_CPUS_DEFAULT_8
1869 bool "Atomic instructions" !! 2849 bool
1870 default y <<
1871 help <<
1872 As part of the Large System Extensi <<
1873 atomic instructions that are design <<
1874 very large systems. <<
1875 2850
1876 Say Y here to make use of these ins !! 2851 config NR_CPUS_DEFAULT_16
1877 atomic routines. This incurs a smal !! 2852 bool
1878 not support these instructions and <<
1879 built with binutils >= 2.25 in orde <<
1880 to be used. <<
1881 2853
1882 endmenu # "ARMv8.1 architectural features" !! 2854 config NR_CPUS_DEFAULT_32
>> 2855 bool
1883 2856
1884 menu "ARMv8.2 architectural features" !! 2857 config NR_CPUS_DEFAULT_64
>> 2858 bool
1885 2859
1886 config AS_HAS_ARMV8_2 !! 2860 config NR_CPUS
1887 def_bool $(cc-option,-Wa$(comma)-marc !! 2861 int "Maximum number of CPUs (2-256)"
>> 2862 range 2 256
>> 2863 depends on SMP
>> 2864 default "4" if NR_CPUS_DEFAULT_4
>> 2865 default "8" if NR_CPUS_DEFAULT_8
>> 2866 default "16" if NR_CPUS_DEFAULT_16
>> 2867 default "32" if NR_CPUS_DEFAULT_32
>> 2868 default "64" if NR_CPUS_DEFAULT_64
>> 2869 help
>> 2870 This allows you to specify the maximum number of CPUs which this
>> 2871 kernel will support. The maximum supported value is 32 for 32-bit
>> 2872 kernel and 64 for 64-bit kernels; the minimum value which makes
>> 2873 sense is 1 for Qemu (useful only for kernel debugging purposes)
>> 2874 and 2 for all others.
>> 2875
>> 2876 This is purely to save memory - each supported CPU adds
>> 2877 approximately eight kilobytes to the kernel image. For best
>> 2878 performance should round up your number of processors to the next
>> 2879 power of two.
1888 2880
1889 config AS_HAS_SHA3 !! 2881 config MIPS_PERF_SHARED_TC_COUNTERS
1890 def_bool $(as-instr,.arch armv8.2-a+s !! 2882 bool
1891 2883
1892 config ARM64_PMEM !! 2884 config MIPS_NR_CPU_NR_MAP_1024
1893 bool "Enable support for persistent m !! 2885 bool
1894 select ARCH_HAS_PMEM_API <<
1895 select ARCH_HAS_UACCESS_FLUSHCACHE <<
1896 help <<
1897 Say Y to enable support for the per <<
1898 ARMv8.2 DCPoP feature. <<
1899 2886
1900 The feature is detected at runtime, !! 2887 config MIPS_NR_CPU_NR_MAP
1901 operations if DC CVAP is not suppor !! 2888 int
1902 DC CVAP itself if the system does n !! 2889 depends on SMP
>> 2890 default 1024 if MIPS_NR_CPU_NR_MAP_1024
>> 2891 default NR_CPUS if !MIPS_NR_CPU_NR_MAP_1024
1903 2892
1904 config ARM64_RAS_EXTN !! 2893 #
1905 bool "Enable support for RAS CPU Exte !! 2894 # Timer Interrupt Frequency Configuration
1906 default y !! 2895 #
1907 help <<
1908 CPUs that support the Reliability, <<
1909 (RAS) Extensions, part of ARMv8.2 a <<
1910 errors, classify them and report th <<
1911 <<
1912 On CPUs with these extensions syste <<
1913 barriers to determine if faults are <<
1914 classification from a new set of re <<
1915 <<
1916 Selecting this feature will allow t <<
1917 and access the new registers if the <<
1918 Platform RAS features may additiona <<
1919 2896
1920 config ARM64_CNP !! 2897 choice
1921 bool "Enable support for Common Not P !! 2898 prompt "Timer frequency"
1922 default y !! 2899 default HZ_250
1923 depends on ARM64_PAN || !ARM64_SW_TTB <<
1924 help 2900 help
1925 Common Not Private (CNP) allows tra !! 2901 Allows the configuration of the timer frequency.
1926 be shared between different PEs in <<
1927 domain, so the hardware can use thi <<
1928 caching of such entries in the TLB. <<
1929 2902
1930 Selecting this option allows the CN !! 2903 config HZ_24
1931 at runtime, and does not affect PEs !! 2904 bool "24 HZ" if SYS_SUPPORTS_24HZ || SYS_SUPPORTS_ARBIT_HZ
1932 this feature. <<
1933 2905
1934 endmenu # "ARMv8.2 architectural features" !! 2906 config HZ_48
>> 2907 bool "48 HZ" if SYS_SUPPORTS_48HZ || SYS_SUPPORTS_ARBIT_HZ
1935 2908
1936 menu "ARMv8.3 architectural features" !! 2909 config HZ_100
1937 !! 2910 bool "100 HZ" if SYS_SUPPORTS_100HZ || SYS_SUPPORTS_ARBIT_HZ
1938 config ARM64_PTR_AUTH <<
1939 bool "Enable support for pointer auth <<
1940 default y <<
1941 help <<
1942 Pointer authentication (part of the <<
1943 instructions for signing and authen <<
1944 keys, which can be used to mitigate <<
1945 and other attacks. <<
1946 <<
1947 This option enables these instructi <<
1948 Choosing this option will cause the <<
1949 for each process at exec() time, wi <<
1950 context-switched along with the pro <<
1951 <<
1952 The feature is detected at runtime. <<
1953 hardware it will not be advertised <<
1954 be enabled. <<
1955 <<
1956 If the feature is present on the bo <<
1957 the late CPU will be parked. Also, <<
1958 address auth and the late CPU has t <<
1959 but with the feature disabled. On s <<
1960 not be selected. <<
1961 <<
1962 config ARM64_PTR_AUTH_KERNEL <<
1963 bool "Use pointer authentication for <<
1964 default y <<
1965 depends on ARM64_PTR_AUTH <<
1966 depends on (CC_HAS_SIGN_RETURN_ADDRES <<
1967 # Modern compilers insert a .note.gnu <<
1968 # which is only understood by binutil <<
1969 depends on LD_IS_LLD || LD_VERSION >= <<
1970 depends on !CC_IS_CLANG || AS_HAS_CFI <<
1971 depends on (!FUNCTION_GRAPH_TRACER || <<
1972 help <<
1973 If the compiler supports the -mbran <<
1974 -msign-return-address flag (e.g. GC <<
1975 will cause the kernel itself to be <<
1976 protection. In this case, and if th <<
1977 support pointer authentication, the <<
1978 disabled with minimal loss of prote <<
1979 <<
1980 This feature works with FUNCTION_GR <<
1981 DYNAMIC_FTRACE_WITH_ARGS is enabled <<
1982 <<
1983 config CC_HAS_BRANCH_PROT_PAC_RET <<
1984 # GCC 9 or later, clang 8 or later <<
1985 def_bool $(cc-option,-mbranch-protect <<
1986 <<
1987 config CC_HAS_SIGN_RETURN_ADDRESS <<
1988 # GCC 7, 8 <<
1989 def_bool $(cc-option,-msign-return-ad <<
1990 <<
1991 config AS_HAS_ARMV8_3 <<
1992 def_bool $(cc-option,-Wa$(comma)-marc <<
1993 <<
1994 config AS_HAS_CFI_NEGATE_RA_STATE <<
1995 def_bool $(as-instr,.cfi_startproc\n. <<
1996 <<
1997 config AS_HAS_LDAPR <<
1998 def_bool $(as-instr,.arch_extension r <<
1999 2911
2000 endmenu # "ARMv8.3 architectural features" !! 2912 config HZ_128
>> 2913 bool "128 HZ" if SYS_SUPPORTS_128HZ || SYS_SUPPORTS_ARBIT_HZ
2001 2914
2002 menu "ARMv8.4 architectural features" !! 2915 config HZ_250
>> 2916 bool "250 HZ" if SYS_SUPPORTS_250HZ || SYS_SUPPORTS_ARBIT_HZ
2003 2917
2004 config ARM64_AMU_EXTN !! 2918 config HZ_256
2005 bool "Enable support for the Activity !! 2919 bool "256 HZ" if SYS_SUPPORTS_256HZ || SYS_SUPPORTS_ARBIT_HZ
2006 default y <<
2007 help <<
2008 The activity monitors extension is <<
2009 by the ARMv8.4 CPU architecture. Th <<
2010 of the activity monitors architectu <<
2011 <<
2012 To enable the use of this extension <<
2013 <<
2014 Note that for architectural reasons <<
2015 support when running on CPUs that p <<
2016 extension. The required support is <<
2017 * Version 1.5 and later of the AR <<
2018 <<
2019 For kernels that have this configur <<
2020 firmware, you may need to say N her <<
2021 Otherwise you may experience firmwa <<
2022 accessing the counter registers. Ev <<
2023 symptoms, the values returned by th <<
2024 correctly reflect reality. Most com <<
2025 indicating that the counter is not <<
2026 2920
2027 config AS_HAS_ARMV8_4 !! 2921 config HZ_1000
2028 def_bool $(cc-option,-Wa$(comma)-marc !! 2922 bool "1000 HZ" if SYS_SUPPORTS_1000HZ || SYS_SUPPORTS_ARBIT_HZ
2029 2923
2030 config ARM64_TLB_RANGE !! 2924 config HZ_1024
2031 bool "Enable support for tlbi range f !! 2925 bool "1024 HZ" if SYS_SUPPORTS_1024HZ || SYS_SUPPORTS_ARBIT_HZ
2032 default y <<
2033 depends on AS_HAS_ARMV8_4 <<
2034 help <<
2035 ARMv8.4-TLBI provides TLBI invalida <<
2036 range of input addresses. <<
2037 2926
2038 The feature introduces new assembly !! 2927 endchoice
2039 support when binutils >= 2.30. <<
2040 2928
2041 endmenu # "ARMv8.4 architectural features" !! 2929 config SYS_SUPPORTS_24HZ
>> 2930 bool
2042 2931
2043 menu "ARMv8.5 architectural features" !! 2932 config SYS_SUPPORTS_48HZ
>> 2933 bool
2044 2934
2045 config AS_HAS_ARMV8_5 !! 2935 config SYS_SUPPORTS_100HZ
2046 def_bool $(cc-option,-Wa$(comma)-marc !! 2936 bool
2047 2937
2048 config ARM64_BTI !! 2938 config SYS_SUPPORTS_128HZ
2049 bool "Branch Target Identification su !! 2939 bool
2050 default y <<
2051 help <<
2052 Branch Target Identification (part <<
2053 provides a mechanism to limit the s <<
2054 branch instructions such as BR or B <<
2055 <<
2056 To make use of BTI on CPUs that sup <<
2057 <<
2058 BTI is intended to provide compleme <<
2059 flow integrity protection mechanism <<
2060 authentication mechanism provided a <<
2061 For this reason, it does not make s <<
2062 also enabling support for pointer a <<
2063 enabling this option you should als <<
2064 <<
2065 Userspace binaries must also be spe <<
2066 this mechanism. If you say N here <<
2067 BTI, such binaries can still run, b <<
2068 enforcement of branch destinations. <<
2069 2940
2070 config ARM64_BTI_KERNEL !! 2941 config SYS_SUPPORTS_250HZ
2071 bool "Use Branch Target Identificatio !! 2942 bool
2072 default y <<
2073 depends on ARM64_BTI <<
2074 depends on ARM64_PTR_AUTH_KERNEL <<
2075 depends on CC_HAS_BRANCH_PROT_PAC_RET <<
2076 # https://gcc.gnu.org/bugzilla/show_b <<
2077 depends on !CC_IS_GCC || GCC_VERSION <<
2078 # https://gcc.gnu.org/bugzilla/show_b <<
2079 depends on !CC_IS_GCC <<
2080 depends on (!FUNCTION_GRAPH_TRACER || <<
2081 help <<
2082 Build the kernel with Branch Target <<
2083 and enable enforcement of this for <<
2084 is enabled and the system supports <<
2085 modular code must have BTI enabled. <<
2086 <<
2087 config CC_HAS_BRANCH_PROT_PAC_RET_BTI <<
2088 # GCC 9 or later, clang 8 or later <<
2089 def_bool $(cc-option,-mbranch-protect <<
2090 2943
2091 config ARM64_E0PD !! 2944 config SYS_SUPPORTS_256HZ
2092 bool "Enable support for E0PD" !! 2945 bool
2093 default y <<
2094 help <<
2095 E0PD (part of the ARMv8.5 extension <<
2096 that EL0 accesses made via TTBR1 al <<
2097 providing similar benefits to KASLR <<
2098 with lower overhead and without dis <<
2099 kernel memory such as SPE. <<
2100 <<
2101 This option enables E0PD for TTBR1 <<
2102 <<
2103 config ARM64_AS_HAS_MTE <<
2104 # Initial support for MTE went in bin <<
2105 # ".arch armv8.5-a+memtag" below. How <<
2106 # as a late addition to the final arc <<
2107 # is only supported in the newer 2.32 <<
2108 # versions, hence the extra "stgm" in <<
2109 def_bool $(as-instr,.arch armv8.5-a+m <<
2110 2946
2111 config ARM64_MTE !! 2947 config SYS_SUPPORTS_1000HZ
2112 bool "Memory Tagging Extension suppor !! 2948 bool
2113 default y <<
2114 depends on ARM64_AS_HAS_MTE && ARM64_ <<
2115 depends on AS_HAS_ARMV8_5 <<
2116 depends on AS_HAS_LSE_ATOMICS <<
2117 # Required for tag checking in the ua <<
2118 depends on ARM64_PAN <<
2119 select ARCH_HAS_SUBPAGE_FAULTS <<
2120 select ARCH_USES_HIGH_VMA_FLAGS <<
2121 select ARCH_USES_PG_ARCH_2 <<
2122 select ARCH_USES_PG_ARCH_3 <<
2123 help <<
2124 Memory Tagging (part of the ARMv8.5 <<
2125 architectural support for run-time, <<
2126 various classes of memory error to <<
2127 to eliminate vulnerabilities arisin <<
2128 languages. <<
2129 <<
2130 This option enables the support for <<
2131 Extension at EL0 (i.e. for userspac <<
2132 <<
2133 Selecting this option allows the fe <<
2134 runtime. Any secondary CPU not impl <<
2135 not be allowed a late bring-up. <<
2136 <<
2137 Userspace binaries that want to use <<
2138 explicitly opt in. The mechanism fo <<
2139 described in: <<
2140 2949
2141 Documentation/arch/arm64/memory-tag !! 2950 config SYS_SUPPORTS_1024HZ
>> 2951 bool
2142 2952
2143 endmenu # "ARMv8.5 architectural features" !! 2953 config SYS_SUPPORTS_ARBIT_HZ
>> 2954 bool
>> 2955 default y if !SYS_SUPPORTS_24HZ && \
>> 2956 !SYS_SUPPORTS_48HZ && \
>> 2957 !SYS_SUPPORTS_100HZ && \
>> 2958 !SYS_SUPPORTS_128HZ && \
>> 2959 !SYS_SUPPORTS_250HZ && \
>> 2960 !SYS_SUPPORTS_256HZ && \
>> 2961 !SYS_SUPPORTS_1000HZ && \
>> 2962 !SYS_SUPPORTS_1024HZ
2144 2963
2145 menu "ARMv8.7 architectural features" !! 2964 config HZ
>> 2965 int
>> 2966 default 24 if HZ_24
>> 2967 default 48 if HZ_48
>> 2968 default 100 if HZ_100
>> 2969 default 128 if HZ_128
>> 2970 default 250 if HZ_250
>> 2971 default 256 if HZ_256
>> 2972 default 1000 if HZ_1000
>> 2973 default 1024 if HZ_1024
>> 2974
>> 2975 config SCHED_HRTICK
>> 2976 def_bool HIGH_RES_TIMERS
>> 2977
>> 2978 config KEXEC
>> 2979 bool "Kexec system call"
>> 2980 select KEXEC_CORE
>> 2981 help
>> 2982 kexec is a system call that implements the ability to shutdown your
>> 2983 current kernel, and to start another kernel. It is like a reboot
>> 2984 but it is independent of the system firmware. And like a reboot
>> 2985 you can start any kernel with it, not just Linux.
>> 2986
>> 2987 The name comes from the similarity to the exec system call.
>> 2988
>> 2989 It is an ongoing process to be certain the hardware in a machine
>> 2990 is properly shutdown, so do not be surprised if this code does not
>> 2991 initially work for you. As of this writing the exact hardware
>> 2992 interface is strongly in flux, so no good recommendation can be
>> 2993 made.
>> 2994
>> 2995 config CRASH_DUMP
>> 2996 bool "Kernel crash dumps"
>> 2997 help
>> 2998 Generate crash dump after being started by kexec.
>> 2999 This should be normally only set in special crash dump kernels
>> 3000 which are loaded in the main kernel with kexec-tools into
>> 3001 a specially reserved region and then later executed after
>> 3002 a crash by kdump/kexec. The crash dump kernel must be compiled
>> 3003 to a memory address not used by the main kernel or firmware using
>> 3004 PHYSICAL_START.
>> 3005
>> 3006 config PHYSICAL_START
>> 3007 hex "Physical address where the kernel is loaded"
>> 3008 default "0xffffffff84000000"
>> 3009 depends on CRASH_DUMP
>> 3010 help
>> 3011 This gives the CKSEG0 or KSEG0 address where the kernel is loaded.
>> 3012 If you plan to use kernel for capturing the crash dump change
>> 3013 this value to start of the reserved region (the "X" value as
>> 3014 specified in the "crashkernel=YM@XM" command line boot parameter
>> 3015 passed to the panic-ed kernel).
>> 3016
>> 3017 config MIPS_O32_FP64_SUPPORT
>> 3018 bool "Support for O32 binaries using 64-bit FP" if !CPU_MIPSR6
>> 3019 depends on 32BIT || MIPS32_O32
>> 3020 help
>> 3021 When this is enabled, the kernel will support use of 64-bit floating
>> 3022 point registers with binaries using the O32 ABI along with the
>> 3023 EF_MIPS_FP64 ELF header flag (typically built with -mfp64). On
>> 3024 32-bit MIPS systems this support is at the cost of increasing the
>> 3025 size and complexity of the compiled FPU emulator. Thus if you are
>> 3026 running a MIPS32 system and know that none of your userland binaries
>> 3027 will require 64-bit floating point, you may wish to reduce the size
>> 3028 of your kernel & potentially improve FP emulation performance by
>> 3029 saying N here.
>> 3030
>> 3031 Although binutils currently supports use of this flag the details
>> 3032 concerning its effect upon the O32 ABI in userland are still being
>> 3033 worked on. In order to avoid userland becoming dependent upon current
>> 3034 behaviour before the details have been finalised, this option should
>> 3035 be considered experimental and only enabled by those working upon
>> 3036 said details.
2146 3037
2147 config ARM64_EPAN !! 3038 If unsure, say N.
2148 bool "Enable support for Enhanced Pri <<
2149 default y <<
2150 depends on ARM64_PAN <<
2151 help <<
2152 Enhanced Privileged Access Never (E <<
2153 Access Never to be used with Execut <<
2154 3039
2155 The feature is detected at runtime, !! 3040 config USE_OF
2156 if the cpu does not implement the f !! 3041 bool
2157 endmenu # "ARMv8.7 architectural features" !! 3042 select OF
>> 3043 select OF_EARLY_FLATTREE
>> 3044 select IRQ_DOMAIN
2158 3045
2159 menu "ARMv8.9 architectural features" !! 3046 config UHI_BOOT
>> 3047 bool
2160 3048
2161 config ARM64_POE !! 3049 config BUILTIN_DTB
2162 prompt "Permission Overlay Extension" !! 3050 bool
2163 def_bool y <<
2164 select ARCH_USES_HIGH_VMA_FLAGS <<
2165 select ARCH_HAS_PKEYS <<
2166 help <<
2167 The Permission Overlay Extension is <<
2168 Protection Keys. Memory Protection <<
2169 enforcing page-based protections, b <<
2170 of the page tables when an applicat <<
2171 3051
2172 For details, see Documentation/core !! 3052 choice
>> 3053 prompt "Kernel appended dtb support" if USE_OF
>> 3054 default MIPS_NO_APPENDED_DTB
2173 3055
2174 If unsure, say y. !! 3056 config MIPS_NO_APPENDED_DTB
>> 3057 bool "None"
>> 3058 help
>> 3059 Do not enable appended dtb support.
>> 3060
>> 3061 config MIPS_ELF_APPENDED_DTB
>> 3062 bool "vmlinux"
>> 3063 help
>> 3064 With this option, the boot code will look for a device tree binary
>> 3065 DTB) included in the vmlinux ELF section .appended_dtb. By default
>> 3066 it is empty and the DTB can be appended using binutils command
>> 3067 objcopy:
>> 3068
>> 3069 objcopy --update-section .appended_dtb=<filename>.dtb vmlinux
>> 3070
>> 3071 This is meant as a backward compatibility convenience for those
>> 3072 systems with a bootloader that can't be upgraded to accommodate
>> 3073 the documented boot protocol using a device tree.
>> 3074
>> 3075 config MIPS_RAW_APPENDED_DTB
>> 3076 bool "vmlinux.bin or vmlinuz.bin"
>> 3077 help
>> 3078 With this option, the boot code will look for a device tree binary
>> 3079 DTB) appended to raw vmlinux.bin or vmlinuz.bin.
>> 3080 (e.g. cat vmlinux.bin <filename>.dtb > vmlinux_w_dtb).
>> 3081
>> 3082 This is meant as a backward compatibility convenience for those
>> 3083 systems with a bootloader that can't be upgraded to accommodate
>> 3084 the documented boot protocol using a device tree.
>> 3085
>> 3086 Beware that there is very little in terms of protection against
>> 3087 this option being confused by leftover garbage in memory that might
>> 3088 look like a DTB header after a reboot if no actual DTB is appended
>> 3089 to vmlinux.bin. Do not leave this option active in a production kernel
>> 3090 if you don't intend to always append a DTB.
>> 3091 endchoice
2175 3092
2176 config ARCH_PKEY_BITS !! 3093 choice
2177 int !! 3094 prompt "Kernel command line type" if !CMDLINE_OVERRIDE
2178 default 3 !! 3095 default MIPS_CMDLINE_FROM_DTB if USE_OF && !ATH79 && !MACH_INGENIC && \
>> 3096 !MACH_LOONGSON64 && !MIPS_MALTA && \
>> 3097 !CAVIUM_OCTEON_SOC
>> 3098 default MIPS_CMDLINE_FROM_BOOTLOADER
>> 3099
>> 3100 config MIPS_CMDLINE_FROM_DTB
>> 3101 depends on USE_OF
>> 3102 bool "Dtb kernel arguments if available"
>> 3103
>> 3104 config MIPS_CMDLINE_DTB_EXTEND
>> 3105 depends on USE_OF
>> 3106 bool "Extend dtb kernel arguments with bootloader arguments"
>> 3107
>> 3108 config MIPS_CMDLINE_FROM_BOOTLOADER
>> 3109 bool "Bootloader kernel arguments if available"
>> 3110
>> 3111 config MIPS_CMDLINE_BUILTIN_EXTEND
>> 3112 depends on CMDLINE_BOOL
>> 3113 bool "Extend builtin kernel arguments with bootloader arguments"
>> 3114 endchoice
2179 3115
2180 endmenu # "ARMv8.9 architectural features" !! 3116 endmenu
2181 3117
2182 config ARM64_SVE !! 3118 config LOCKDEP_SUPPORT
2183 bool "ARM Scalable Vector Extension s !! 3119 bool
2184 default y 3120 default y
2185 help <<
2186 The Scalable Vector Extension (SVE) <<
2187 execution state which complements a <<
2188 of the base architecture to support <<
2189 additional vectorisation opportunit <<
2190 <<
2191 To enable use of this extension on <<
2192 <<
2193 On CPUs that support the SVE2 exten <<
2194 those too. <<
2195 <<
2196 Note that for architectural reasons <<
2197 support when running on SVE capable <<
2198 is present in: <<
2199 <<
2200 * version 1.5 and later of the AR <<
2201 * the AArch64 boot wrapper since <<
2202 ("bootwrapper: SVE: Enable SVE <<
2203 <<
2204 For other firmware implementations, <<
2205 or vendor. <<
2206 <<
2207 If you need the kernel to boot on S <<
2208 firmware, you may need to say N her <<
2209 fixed. Otherwise, you may experien <<
2210 booting the kernel. If unsure and <<
2211 symptoms, you should assume that it <<
2212 3121
2213 config ARM64_SME !! 3122 config STACKTRACE_SUPPORT
2214 bool "ARM Scalable Matrix Extension s !! 3123 bool
2215 default y 3124 default y
2216 depends on ARM64_SVE <<
2217 depends on BROKEN <<
2218 help <<
2219 The Scalable Matrix Extension (SME) <<
2220 execution state which utilises a su <<
2221 instruction set, together with the <<
2222 register state capable of holding t <<
2223 enable various matrix operations. <<
2224 <<
2225 config ARM64_PSEUDO_NMI <<
2226 bool "Support for NMI-like interrupts <<
2227 select ARM_GIC_V3 <<
2228 help <<
2229 Adds support for mimicking Non-Mask <<
2230 GIC interrupt priority. This suppor <<
2231 ARM GIC. <<
2232 <<
2233 This high priority configuration fo <<
2234 explicitly enabled by setting the k <<
2235 "irqchip.gicv3_pseudo_nmi" to 1. <<
2236 <<
2237 If unsure, say N <<
2238 <<
2239 if ARM64_PSEUDO_NMI <<
2240 config ARM64_DEBUG_PRIORITY_MASKING <<
2241 bool "Debug interrupt priority maskin <<
2242 help <<
2243 This adds runtime checks to functio <<
2244 interrupts when using priority mask <<
2245 the validity of ICC_PMR_EL1 when ca <<
2246 3125
2247 If unsure, say N !! 3126 config PGTABLE_LEVELS
2248 endif # ARM64_PSEUDO_NMI !! 3127 int
>> 3128 default 4 if PAGE_SIZE_4KB && MIPS_VA_BITS_48
>> 3129 default 3 if 64BIT && (!PAGE_SIZE_64KB || MIPS_VA_BITS_48)
>> 3130 default 2
2249 3131
2250 config RELOCATABLE !! 3132 config MIPS_AUTO_PFN_OFFSET
2251 bool "Build a relocatable kernel imag !! 3133 bool
2252 select ARCH_HAS_RELR <<
2253 default y <<
2254 help <<
2255 This builds the kernel as a Positio <<
2256 which retains all relocation metada <<
2257 kernel binary at runtime to a diffe <<
2258 address it was linked at. <<
2259 Since AArch64 uses the RELA relocat <<
2260 relocation pass at runtime even if <<
2261 same address it was linked at. <<
2262 3134
2263 config RANDOMIZE_BASE !! 3135 menu "Bus options (PCI, PCMCIA, EISA, ISA, TC)"
2264 bool "Randomize the address of the ke <<
2265 select RELOCATABLE <<
2266 help <<
2267 Randomizes the virtual address at w <<
2268 loaded, as a security feature that <<
2269 relying on knowledge of the locatio <<
2270 <<
2271 It is the bootloader's job to provi <<
2272 random u64 value in /chosen/kaslr-s <<
2273 <<
2274 When booting via the UEFI stub, it <<
2275 EFI_RNG_PROTOCOL implementation (if <<
2276 to the kernel proper. In addition, <<
2277 location of the kernel Image as wel <<
2278 3136
2279 If unsure, say N. !! 3137 config PCI_DRIVERS_GENERIC
>> 3138 select PCI_DOMAINS_GENERIC if PCI
>> 3139 bool
2280 3140
2281 config RANDOMIZE_MODULE_REGION_FULL !! 3141 config PCI_DRIVERS_LEGACY
2282 bool "Randomize the module region ove !! 3142 def_bool !PCI_DRIVERS_GENERIC
2283 depends on RANDOMIZE_BASE !! 3143 select NO_GENERIC_PCI_IOPORT_MAP
2284 default y !! 3144 select PCI_DOMAINS if PCI
2285 help <<
2286 Randomizes the location of the modu <<
2287 covering the core kernel. This way, <<
2288 to leak information about the locat <<
2289 but it does imply that function cal <<
2290 kernel will need to be resolved via <<
2291 <<
2292 When this option is not set, the mo <<
2293 a limited range that contains the [ <<
2294 core kernel, so branch relocations <<
2295 the region is exhausted. In this pa <<
2296 exhaustion, modules might be able t <<
2297 3145
2298 config CC_HAVE_STACKPROTECTOR_SYSREG !! 3146 #
2299 def_bool $(cc-option,-mstack-protecto !! 3147 # ISA support is now enabled via select. Too many systems still have the one
>> 3148 # or other ISA chip on the board that users don't know about so don't expect
>> 3149 # users to choose the right thing ...
>> 3150 #
>> 3151 config ISA
>> 3152 bool
2300 3153
2301 config STACKPROTECTOR_PER_TASK !! 3154 config TC
2302 def_bool y !! 3155 bool "TURBOchannel support"
2303 depends on STACKPROTECTOR && CC_HAVE_ !! 3156 depends on MACH_DECSTATION
>> 3157 help
>> 3158 TURBOchannel is a DEC (now Compaq (now HP)) bus for Alpha and MIPS
>> 3159 processors. TURBOchannel programming specifications are available
>> 3160 at:
>> 3161 <ftp://ftp.hp.com/pub/alphaserver/archive/triadd/>
>> 3162 and:
>> 3163 <http://www.computer-refuge.org/classiccmp/ftp.digital.com/pub/DEC/TriAdd/>
>> 3164 Linux driver support status is documented at:
>> 3165 <http://www.linux-mips.org/wiki/DECstation>
2304 3166
2305 config UNWIND_PATCH_PAC_INTO_SCS !! 3167 config MMU
2306 bool "Enable shadow call stack dynami !! 3168 bool
2307 # needs Clang with https://github.com <<
2308 depends on CC_IS_CLANG && CLANG_VERSI <<
2309 depends on ARM64_PTR_AUTH_KERNEL && C <<
2310 depends on SHADOW_CALL_STACK <<
2311 select UNWIND_TABLES <<
2312 select DYNAMIC_SCS <<
2313 <<
2314 config ARM64_CONTPTE <<
2315 bool "Contiguous PTE mappings for use <<
2316 depends on TRANSPARENT_HUGEPAGE <<
2317 default y 3169 default y
2318 help <<
2319 When enabled, user mappings are con <<
2320 bit, for any mappings that meet the <<
2321 This reduces TLB pressure and impro <<
2322 <<
2323 endmenu # "Kernel Features" <<
2324 <<
2325 menu "Boot options" <<
2326 <<
2327 config ARM64_ACPI_PARKING_PROTOCOL <<
2328 bool "Enable support for the ARM64 AC <<
2329 depends on ACPI <<
2330 help <<
2331 Enable support for the ARM64 ACPI p <<
2332 the kernel will not allow booting t <<
2333 protocol even if the corresponding <<
2334 MADT table. <<
2335 <<
2336 config CMDLINE <<
2337 string "Default kernel command string <<
2338 default "" <<
2339 help <<
2340 Provide a set of default command-li <<
2341 entering them here. As a minimum, y <<
2342 root device (e.g. root=/dev/nfs). <<
2343 3170
2344 choice !! 3171 config ARCH_MMAP_RND_BITS_MIN
2345 prompt "Kernel command line type" !! 3172 default 12 if 64BIT
2346 depends on CMDLINE != "" !! 3173 default 8
2347 default CMDLINE_FROM_BOOTLOADER <<
2348 help <<
2349 Choose how the kernel will handle t <<
2350 command line string. <<
2351 <<
2352 config CMDLINE_FROM_BOOTLOADER <<
2353 bool "Use bootloader kernel arguments <<
2354 help <<
2355 Uses the command-line options passe <<
2356 the boot loader doesn't provide any <<
2357 string provided in CMDLINE will be <<
2358 <<
2359 config CMDLINE_FORCE <<
2360 bool "Always use the default kernel c <<
2361 help <<
2362 Always use the default kernel comma <<
2363 loader passes other arguments to th <<
2364 This is useful if you cannot or don <<
2365 command-line options your boot load <<
2366 3174
2367 endchoice !! 3175 config ARCH_MMAP_RND_BITS_MAX
>> 3176 default 18 if 64BIT
>> 3177 default 15
2368 3178
2369 config EFI_STUB !! 3179 config ARCH_MMAP_RND_COMPAT_BITS_MIN
>> 3180 default 8
>> 3181
>> 3182 config ARCH_MMAP_RND_COMPAT_BITS_MAX
>> 3183 default 15
>> 3184
>> 3185 config I8253
2370 bool 3186 bool
>> 3187 select CLKSRC_I8253
>> 3188 select CLKEVT_I8253
>> 3189 select MIPS_EXTERNAL_TIMER
>> 3190 endmenu
2371 3191
2372 config EFI !! 3192 config TRAD_SIGNALS
2373 bool "UEFI runtime support" !! 3193 bool
2374 depends on OF && !CPU_BIG_ENDIAN <<
2375 depends on KERNEL_MODE_NEON <<
2376 select ARCH_SUPPORTS_ACPI <<
2377 select LIBFDT <<
2378 select UCS2_STRING <<
2379 select EFI_PARAMS_FROM_FDT <<
2380 select EFI_RUNTIME_WRAPPERS <<
2381 select EFI_STUB <<
2382 select EFI_GENERIC_STUB <<
2383 imply IMA_SECURE_AND_OR_TRUSTED_BOOT <<
2384 default y <<
2385 help <<
2386 This option provides support for ru <<
2387 by UEFI firmware (such as non-volat <<
2388 clock, and platform reset). A UEFI <<
2389 allow the kernel to be booted as an <<
2390 is only useful on systems that have <<
2391 <<
2392 config COMPRESSED_INSTALL <<
2393 bool "Install compressed image by def <<
2394 help <<
2395 This makes the regular "make instal <<
2396 image we built, not the legacy unco <<
2397 <<
2398 You can check that a compressed ima <<
2399 "make zinstall" first, and verifyin <<
2400 in your environment before making " <<
2401 you. <<
2402 3194
2403 config DMI !! 3195 config MIPS32_COMPAT
2404 bool "Enable support for SMBIOS (DMI) !! 3196 bool
2405 depends on EFI <<
2406 default y <<
2407 help <<
2408 This enables SMBIOS/DMI feature for <<
2409 3197
2410 This option is only useful on syste !! 3198 config COMPAT
2411 However, even with this option, the !! 3199 bool
2412 continue to boot on existing non-UE <<
2413 3200
2414 endmenu # "Boot options" !! 3201 config SYSVIPC_COMPAT
>> 3202 bool
2415 3203
2416 menu "Power management options" !! 3204 config MIPS32_O32
>> 3205 bool "Kernel support for o32 binaries"
>> 3206 depends on 64BIT
>> 3207 select ARCH_WANT_OLD_COMPAT_IPC
>> 3208 select COMPAT
>> 3209 select MIPS32_COMPAT
>> 3210 select SYSVIPC_COMPAT if SYSVIPC
>> 3211 help
>> 3212 Select this option if you want to run o32 binaries. These are pure
>> 3213 32-bit binaries as used by the 32-bit Linux/MIPS port. Most of
>> 3214 existing binaries are in this format.
2417 3215
2418 source "kernel/power/Kconfig" !! 3216 If unsure, say Y.
2419 3217
2420 config ARCH_HIBERNATION_POSSIBLE !! 3218 config MIPS32_N32
>> 3219 bool "Kernel support for n32 binaries"
>> 3220 depends on 64BIT
>> 3221 select ARCH_WANT_COMPAT_IPC_PARSE_VERSION
>> 3222 select COMPAT
>> 3223 select MIPS32_COMPAT
>> 3224 select SYSVIPC_COMPAT if SYSVIPC
>> 3225 help
>> 3226 Select this option if you want to run n32 binaries. These are
>> 3227 64-bit binaries using 32-bit quantities for addressing and certain
>> 3228 data that would normally be 64-bit. They are used in special
>> 3229 cases.
>> 3230
>> 3231 If unsure, say N.
>> 3232
>> 3233 config CC_HAS_MNO_BRANCH_LIKELY
2421 def_bool y 3234 def_bool y
2422 depends on CPU_PM !! 3235 depends on $(cc-option,-mno-branch-likely)
>> 3236
>> 3237 menu "Power management options"
2423 3238
2424 config ARCH_HIBERNATION_HEADER !! 3239 config ARCH_HIBERNATION_POSSIBLE
2425 def_bool y 3240 def_bool y
2426 depends on HIBERNATION !! 3241 depends on SYS_SUPPORTS_HOTPLUG_CPU || !SMP
2427 3242
2428 config ARCH_SUSPEND_POSSIBLE 3243 config ARCH_SUSPEND_POSSIBLE
2429 def_bool y 3244 def_bool y
>> 3245 depends on SYS_SUPPORTS_HOTPLUG_CPU || !SMP
2430 3246
2431 endmenu # "Power management options" !! 3247 source "kernel/power/Kconfig"
2432 3248
2433 menu "CPU Power Management" !! 3249 endmenu
2434 3250
2435 source "drivers/cpuidle/Kconfig" !! 3251 config MIPS_EXTERNAL_TIMER
>> 3252 bool
2436 3253
>> 3254 menu "CPU Power Management"
>> 3255
>> 3256 if CPU_SUPPORTS_CPUFREQ && MIPS_EXTERNAL_TIMER
2437 source "drivers/cpufreq/Kconfig" 3257 source "drivers/cpufreq/Kconfig"
>> 3258 endif
2438 3259
2439 endmenu # "CPU Power Management" !! 3260 source "drivers/cpuidle/Kconfig"
2440 3261
2441 source "drivers/acpi/Kconfig" !! 3262 endmenu
2442 3263
2443 source "arch/arm64/kvm/Kconfig" !! 3264 source "arch/mips/kvm/Kconfig"
2444 3265
>> 3266 source "arch/mips/vdso/Kconfig"
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