1 # SPDX-License-Identifier: GPL-2.0-only !! 1 # SPDX-License-Identifier: GPL-2.0
2 config ARM64 !! 2 config MIPS
3 def_bool y !! 3 bool
4 select ACPI_APMT if ACPI !! 4 default y
5 select ACPI_CCA_REQUIRED if ACPI !! 5 select ARCH_32BIT_OFF_T if !64BIT
6 select ACPI_GENERIC_GSI if ACPI !! 6 select ARCH_BINFMT_ELF_STATE if MIPS_FP_SUPPORT
7 select ACPI_GTDT if ACPI !! 7 select ARCH_CLOCKSOURCE_DATA
8 select ACPI_HOTPLUG_CPU if ACPI_PROCES !! 8 select ARCH_HAS_ELF_RANDOMIZE
9 select ACPI_IORT if ACPI <<
10 select ACPI_REDUCED_HARDWARE_ONLY if A <<
11 select ACPI_MCFG if (ACPI && PCI) <<
12 select ACPI_SPCR_TABLE if ACPI <<
13 select ACPI_PPTT if ACPI <<
14 select ARCH_HAS_DEBUG_WX <<
15 select ARCH_BINFMT_ELF_EXTRA_PHDRS <<
16 select ARCH_BINFMT_ELF_STATE <<
17 select ARCH_CORRECT_STACKTRACE_ON_KRET <<
18 select ARCH_ENABLE_HUGEPAGE_MIGRATION <<
19 select ARCH_ENABLE_MEMORY_HOTPLUG <<
20 select ARCH_ENABLE_MEMORY_HOTREMOVE <<
21 select ARCH_ENABLE_SPLIT_PMD_PTLOCK if <<
22 select ARCH_ENABLE_THP_MIGRATION if TR <<
23 select ARCH_HAS_CACHE_LINE_SIZE <<
24 select ARCH_HAS_CURRENT_STACK_POINTER <<
25 select ARCH_HAS_DEBUG_VIRTUAL <<
26 select ARCH_HAS_DEBUG_VM_PGTABLE <<
27 select ARCH_HAS_DMA_OPS if XEN <<
28 select ARCH_HAS_DMA_PREP_COHERENT <<
29 select ARCH_HAS_ACPI_TABLE_UPGRADE if <<
30 select ARCH_HAS_FAST_MULTIPLIER <<
31 select ARCH_HAS_FORTIFY_SOURCE <<
32 select ARCH_HAS_GCOV_PROFILE_ALL <<
33 select ARCH_HAS_GIGANTIC_PAGE <<
34 select ARCH_HAS_KCOV <<
35 select ARCH_HAS_KERNEL_FPU_SUPPORT if <<
36 select ARCH_HAS_KEEPINITRD <<
37 select ARCH_HAS_MEMBARRIER_SYNC_CORE <<
38 select ARCH_HAS_MEM_ENCRYPT <<
39 select ARCH_HAS_NMI_SAFE_THIS_CPU_OPS <<
40 select ARCH_HAS_NON_OVERLAPPING_ADDRES <<
41 select ARCH_HAS_PTE_DEVMAP <<
42 select ARCH_HAS_PTE_SPECIAL <<
43 select ARCH_HAS_HW_PTE_YOUNG <<
44 select ARCH_HAS_SETUP_DMA_OPS <<
45 select ARCH_HAS_SET_DIRECT_MAP <<
46 select ARCH_HAS_SET_MEMORY <<
47 select ARCH_STACKWALK <<
48 select ARCH_HAS_STRICT_KERNEL_RWX <<
49 select ARCH_HAS_STRICT_MODULE_RWX <<
50 select ARCH_HAS_SYNC_DMA_FOR_DEVICE <<
51 select ARCH_HAS_SYNC_DMA_FOR_CPU <<
52 select ARCH_HAS_SYSCALL_WRAPPER <<
53 select ARCH_HAS_TICK_BROADCAST if GENE 9 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
54 select ARCH_HAS_ZONE_DMA_SET if EXPERT !! 10 select ARCH_HAS_UBSAN_SANITIZE_ALL
55 select ARCH_HAVE_ELF_PROT !! 11 select ARCH_SUPPORTS_UPROBES
56 select ARCH_HAVE_NMI_SAFE_CMPXCHG !! 12 select ARCH_USE_BUILTIN_BSWAP
57 select ARCH_HAVE_TRACE_MMIO_ACCESS !! 13 select ARCH_USE_CMPXCHG_LOCKREF if 64BIT
58 select ARCH_INLINE_READ_LOCK if !PREEM <<
59 select ARCH_INLINE_READ_LOCK_BH if !PR <<
60 select ARCH_INLINE_READ_LOCK_IRQ if !P <<
61 select ARCH_INLINE_READ_LOCK_IRQSAVE i <<
62 select ARCH_INLINE_READ_UNLOCK if !PRE <<
63 select ARCH_INLINE_READ_UNLOCK_BH if ! <<
64 select ARCH_INLINE_READ_UNLOCK_IRQ if <<
65 select ARCH_INLINE_READ_UNLOCK_IRQREST <<
66 select ARCH_INLINE_WRITE_LOCK if !PREE <<
67 select ARCH_INLINE_WRITE_LOCK_BH if !P <<
68 select ARCH_INLINE_WRITE_LOCK_IRQ if ! <<
69 select ARCH_INLINE_WRITE_LOCK_IRQSAVE <<
70 select ARCH_INLINE_WRITE_UNLOCK if !PR <<
71 select ARCH_INLINE_WRITE_UNLOCK_BH if <<
72 select ARCH_INLINE_WRITE_UNLOCK_IRQ if <<
73 select ARCH_INLINE_WRITE_UNLOCK_IRQRES <<
74 select ARCH_INLINE_SPIN_TRYLOCK if !PR <<
75 select ARCH_INLINE_SPIN_TRYLOCK_BH if <<
76 select ARCH_INLINE_SPIN_LOCK if !PREEM <<
77 select ARCH_INLINE_SPIN_LOCK_BH if !PR <<
78 select ARCH_INLINE_SPIN_LOCK_IRQ if !P <<
79 select ARCH_INLINE_SPIN_LOCK_IRQSAVE i <<
80 select ARCH_INLINE_SPIN_UNLOCK if !PRE <<
81 select ARCH_INLINE_SPIN_UNLOCK_BH if ! <<
82 select ARCH_INLINE_SPIN_UNLOCK_IRQ if <<
83 select ARCH_INLINE_SPIN_UNLOCK_IRQREST <<
84 select ARCH_KEEP_MEMBLOCK <<
85 select ARCH_MHP_MEMMAP_ON_MEMORY_ENABL <<
86 select ARCH_USE_CMPXCHG_LOCKREF <<
87 select ARCH_USE_GNU_PROPERTY <<
88 select ARCH_USE_MEMTEST <<
89 select ARCH_USE_QUEUED_RWLOCKS 14 select ARCH_USE_QUEUED_RWLOCKS
90 select ARCH_USE_QUEUED_SPINLOCKS 15 select ARCH_USE_QUEUED_SPINLOCKS
91 select ARCH_USE_SYM_ANNOTATIONS !! 16 select ARCH_WANT_IPC_PARSE_VERSION
92 select ARCH_SUPPORTS_DEBUG_PAGEALLOC !! 17 select BUILDTIME_EXTABLE_SORT
93 select ARCH_SUPPORTS_HUGETLBFS <<
94 select ARCH_SUPPORTS_MEMORY_FAILURE <<
95 select ARCH_SUPPORTS_SHADOW_CALL_STACK <<
96 select ARCH_SUPPORTS_LTO_CLANG if CPU_ <<
97 select ARCH_SUPPORTS_LTO_CLANG_THIN <<
98 select ARCH_SUPPORTS_CFI_CLANG <<
99 select ARCH_SUPPORTS_ATOMIC_RMW <<
100 select ARCH_SUPPORTS_INT128 if CC_HAS_ <<
101 select ARCH_SUPPORTS_NUMA_BALANCING <<
102 select ARCH_SUPPORTS_PAGE_TABLE_CHECK <<
103 select ARCH_SUPPORTS_PER_VMA_LOCK <<
104 select ARCH_SUPPORTS_HUGE_PFNMAP if TR <<
105 select ARCH_SUPPORTS_RT <<
106 select ARCH_WANT_BATCHED_UNMAP_TLB_FLU <<
107 select ARCH_WANT_COMPAT_IPC_PARSE_VERS <<
108 select ARCH_WANT_DEFAULT_BPF_JIT <<
109 select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_ <<
110 select ARCH_WANT_FRAME_POINTERS <<
111 select ARCH_WANT_HUGE_PMD_SHARE if ARM <<
112 select ARCH_WANT_LD_ORPHAN_WARN <<
113 select ARCH_WANTS_EXECMEM_LATE if EXEC <<
114 select ARCH_WANTS_NO_INSTR <<
115 select ARCH_WANTS_THP_SWAP if ARM64_4K <<
116 select ARCH_HAS_UBSAN <<
117 select ARM_AMBA <<
118 select ARM_ARCH_TIMER <<
119 select ARM_GIC <<
120 select AUDIT_ARCH_COMPAT_GENERIC <<
121 select ARM_GIC_V2M if PCI <<
122 select ARM_GIC_V3 <<
123 select ARM_GIC_V3_ITS if PCI <<
124 select ARM_PSCI_FW <<
125 select BUILDTIME_TABLE_SORT <<
126 select CLONE_BACKWARDS 18 select CLONE_BACKWARDS
127 select COMMON_CLK !! 19 select CPU_NO_EFFICIENT_FFS if (TARGET_ISA_REV < 1)
128 select CPU_PM if (SUSPEND || CPU_IDLE) !! 20 select CPU_PM if CPU_IDLE
129 select CPUMASK_OFFSTACK if NR_CPUS > 2 !! 21 select GENERIC_ATOMIC64 if !64BIT
130 select CRC32 !! 22 select GENERIC_CLOCKEVENTS
131 select DCACHE_WORD_ACCESS !! 23 select GENERIC_CMOS_UPDATE
132 select DYNAMIC_FTRACE if FUNCTION_TRAC <<
133 select DMA_BOUNCE_UNALIGNED_KMALLOC <<
134 select DMA_DIRECT_REMAP <<
135 select EDAC_SUPPORT <<
136 select FRAME_POINTER <<
137 select FUNCTION_ALIGNMENT_4B <<
138 select FUNCTION_ALIGNMENT_8B if DYNAMI <<
139 select GENERIC_ALLOCATOR <<
140 select GENERIC_ARCH_TOPOLOGY <<
141 select GENERIC_CLOCKEVENTS_BROADCAST <<
142 select GENERIC_CPU_AUTOPROBE 24 select GENERIC_CPU_AUTOPROBE
143 select GENERIC_CPU_DEVICES !! 25 select GENERIC_IOMAP
144 select GENERIC_CPU_VULNERABILITIES <<
145 select GENERIC_EARLY_IOREMAP <<
146 select GENERIC_IDLE_POLL_SETUP <<
147 select GENERIC_IOREMAP <<
148 select GENERIC_IRQ_IPI <<
149 select GENERIC_IRQ_PROBE 26 select GENERIC_IRQ_PROBE
150 select GENERIC_IRQ_SHOW 27 select GENERIC_IRQ_SHOW
151 select GENERIC_IRQ_SHOW_LEVEL !! 28 select GENERIC_ISA_DMA if EISA
152 select GENERIC_LIB_DEVMEM_IS_ALLOWED !! 29 select GENERIC_LIB_ASHLDI3
153 select GENERIC_PCI_IOMAP !! 30 select GENERIC_LIB_ASHRDI3
154 select GENERIC_PTDUMP !! 31 select GENERIC_LIB_CMPDI2
155 select GENERIC_SCHED_CLOCK !! 32 select GENERIC_LIB_LSHRDI3
>> 33 select GENERIC_LIB_UCMPDI2
>> 34 select GENERIC_SCHED_CLOCK if !CAVIUM_OCTEON_SOC
156 select GENERIC_SMP_IDLE_THREAD 35 select GENERIC_SMP_IDLE_THREAD
157 select GENERIC_TIME_VSYSCALL 36 select GENERIC_TIME_VSYSCALL
158 select GENERIC_GETTIMEOFDAY !! 37 select GUP_GET_PTE_LOW_HIGH if CPU_MIPS32 && PHYS_ADDR_T_64BIT
159 select GENERIC_VDSO_TIME_NS !! 38 select HANDLE_DOMAIN_IRQ
160 select HARDIRQS_SW_RESEND <<
161 select HAS_IOPORT <<
162 select HAVE_MOVE_PMD <<
163 select HAVE_MOVE_PUD <<
164 select HAVE_PCI <<
165 select HAVE_ACPI_APEI if (ACPI && EFI) <<
166 select HAVE_ALIGNED_STRUCT_PAGE <<
167 select HAVE_ARCH_AUDITSYSCALL <<
168 select HAVE_ARCH_BITREVERSE <<
169 select HAVE_ARCH_COMPILER_H 39 select HAVE_ARCH_COMPILER_H
170 select HAVE_ARCH_HUGE_VMALLOC <<
171 select HAVE_ARCH_HUGE_VMAP <<
172 select HAVE_ARCH_JUMP_LABEL 40 select HAVE_ARCH_JUMP_LABEL
173 select HAVE_ARCH_JUMP_LABEL_RELATIVE <<
174 select HAVE_ARCH_KASAN <<
175 select HAVE_ARCH_KASAN_VMALLOC <<
176 select HAVE_ARCH_KASAN_SW_TAGS <<
177 select HAVE_ARCH_KASAN_HW_TAGS if ARM6 <<
178 # Some instrumentation may be unsound, <<
179 select HAVE_ARCH_KCSAN if EXPERT <<
180 select HAVE_ARCH_KFENCE <<
181 select HAVE_ARCH_KGDB 41 select HAVE_ARCH_KGDB
182 select HAVE_ARCH_MMAP_RND_BITS !! 42 select HAVE_ARCH_MMAP_RND_BITS if MMU
183 select HAVE_ARCH_MMAP_RND_COMPAT_BITS !! 43 select HAVE_ARCH_MMAP_RND_COMPAT_BITS if MMU && COMPAT
184 select HAVE_ARCH_PREL32_RELOCATIONS <<
185 select HAVE_ARCH_RANDOMIZE_KSTACK_OFFS <<
186 select HAVE_ARCH_SECCOMP_FILTER 44 select HAVE_ARCH_SECCOMP_FILTER
187 select HAVE_ARCH_STACKLEAK <<
188 select HAVE_ARCH_THREAD_STRUCT_WHITELI <<
189 select HAVE_ARCH_TRACEHOOK 45 select HAVE_ARCH_TRACEHOOK
190 select HAVE_ARCH_TRANSPARENT_HUGEPAGE !! 46 select HAVE_ARCH_TRANSPARENT_HUGEPAGE if CPU_SUPPORTS_HUGEPAGES && 64BIT
191 select HAVE_ARCH_VMAP_STACK !! 47 select HAVE_EBPF_JIT if (!CPU_MICROMIPS)
192 select HAVE_ARM_SMCCC !! 48 select HAVE_CONTEXT_TRACKING
193 select HAVE_ASM_MODVERSIONS !! 49 select HAVE_COPY_THREAD_TLS
194 select HAVE_EBPF_JIT <<
195 select HAVE_C_RECORDMCOUNT 50 select HAVE_C_RECORDMCOUNT
196 select HAVE_CMPXCHG_DOUBLE <<
197 select HAVE_CMPXCHG_LOCAL <<
198 select HAVE_CONTEXT_TRACKING_USER <<
199 select HAVE_DEBUG_KMEMLEAK 51 select HAVE_DEBUG_KMEMLEAK
>> 52 select HAVE_DEBUG_STACKOVERFLOW
200 select HAVE_DMA_CONTIGUOUS 53 select HAVE_DMA_CONTIGUOUS
201 select HAVE_DYNAMIC_FTRACE 54 select HAVE_DYNAMIC_FTRACE
202 select HAVE_DYNAMIC_FTRACE_WITH_ARGS \ !! 55 select HAVE_EXIT_THREAD
203 if (GCC_SUPPORTS_DYNAMIC_FTRAC !! 56 select HAVE_FAST_GUP
204 CLANG_SUPPORTS_DYNAMIC_FTR <<
205 select HAVE_DYNAMIC_FTRACE_WITH_DIRECT <<
206 if DYNAMIC_FTRACE_WITH_ARGS && <<
207 select HAVE_DYNAMIC_FTRACE_WITH_CALL_O <<
208 if (DYNAMIC_FTRACE_WITH_ARGS & <<
209 (CC_IS_CLANG || !CC_OPTIMI <<
210 select FTRACE_MCOUNT_USE_PATCHABLE_FUN <<
211 if DYNAMIC_FTRACE_WITH_ARGS <<
212 select HAVE_SAMPLE_FTRACE_DIRECT <<
213 select HAVE_SAMPLE_FTRACE_DIRECT_MULTI <<
214 select HAVE_EFFICIENT_UNALIGNED_ACCESS <<
215 select HAVE_GUP_FAST <<
216 select HAVE_FTRACE_MCOUNT_RECORD 57 select HAVE_FTRACE_MCOUNT_RECORD
217 select HAVE_FUNCTION_TRACER <<
218 select HAVE_FUNCTION_ERROR_INJECTION <<
219 select HAVE_FUNCTION_GRAPH_TRACER 58 select HAVE_FUNCTION_GRAPH_TRACER
220 select HAVE_FUNCTION_GRAPH_RETVAL !! 59 select HAVE_FUNCTION_TRACER
221 select HAVE_GCC_PLUGINS !! 60 select HAVE_IDE
222 select HAVE_HARDLOCKUP_DETECTOR_PERF i <<
223 HW_PERF_EVENTS && HAVE_PERF_EV <<
224 select HAVE_HW_BREAKPOINT if PERF_EVEN <<
225 select HAVE_IOREMAP_PROT 61 select HAVE_IOREMAP_PROT
>> 62 select HAVE_IRQ_EXIT_ON_IRQ_STACK
226 select HAVE_IRQ_TIME_ACCOUNTING 63 select HAVE_IRQ_TIME_ACCOUNTING
>> 64 select HAVE_KPROBES
>> 65 select HAVE_KRETPROBES
>> 66 select HAVE_LD_DEAD_CODE_DATA_ELIMINATION
>> 67 select HAVE_MEMBLOCK_NODE_MAP
227 select HAVE_MOD_ARCH_SPECIFIC 68 select HAVE_MOD_ARCH_SPECIFIC
228 select HAVE_NMI 69 select HAVE_NMI
>> 70 select HAVE_OPROFILE
229 select HAVE_PERF_EVENTS 71 select HAVE_PERF_EVENTS
230 select HAVE_PERF_EVENTS_NMI if ARM64_P <<
231 select HAVE_PERF_REGS <<
232 select HAVE_PERF_USER_STACK_DUMP <<
233 select HAVE_PREEMPT_DYNAMIC_KEY <<
234 select HAVE_REGS_AND_STACK_ACCESS_API 72 select HAVE_REGS_AND_STACK_ACCESS_API
235 select HAVE_POSIX_CPU_TIMERS_TASK_WORK <<
236 select HAVE_FUNCTION_ARG_ACCESS_API <<
237 select MMU_GATHER_RCU_TABLE_FREE <<
238 select HAVE_RSEQ 73 select HAVE_RSEQ
239 select HAVE_RUST if RUSTC_SUPPORTS_ARM <<
240 select HAVE_STACKPROTECTOR 74 select HAVE_STACKPROTECTOR
241 select HAVE_SYSCALL_TRACEPOINTS 75 select HAVE_SYSCALL_TRACEPOINTS
242 select HAVE_KPROBES !! 76 select HAVE_VIRT_CPU_ACCOUNTING_GEN if 64BIT || !SMP
243 select HAVE_KRETPROBES <<
244 select HAVE_GENERIC_VDSO <<
245 select HOTPLUG_CORE_SYNC_DEAD if HOTPL <<
246 select IRQ_DOMAIN <<
247 select IRQ_FORCED_THREADING 77 select IRQ_FORCED_THREADING
248 select KASAN_VMALLOC if KASAN !! 78 select ISA if EISA
249 select LOCK_MM_AND_FIND_VMA !! 79 select MODULES_USE_ELF_RELA if MODULES && 64BIT
250 select MODULES_USE_ELF_RELA !! 80 select MODULES_USE_ELF_REL if MODULES
251 select NEED_DMA_MAP_STATE !! 81 select PERF_USE_VMALLOC
252 select NEED_SG_DMA_LENGTH !! 82 select RTC_LIB
253 select OF <<
254 select OF_EARLY_FLATTREE <<
255 select PCI_DOMAINS_GENERIC if PCI <<
256 select PCI_ECAM if (ACPI && PCI) <<
257 select PCI_SYSCALL if PCI <<
258 select POWER_RESET <<
259 select POWER_SUPPLY <<
260 select SPARSE_IRQ <<
261 select SWIOTLB <<
262 select SYSCTL_EXCEPTION_TRACE 83 select SYSCTL_EXCEPTION_TRACE
263 select THREAD_INFO_IN_TASK !! 84 select VIRT_TO_BUS
264 select HAVE_ARCH_USERFAULTFD_MINOR if !! 85
265 select HAVE_ARCH_USERFAULTFD_WP if USE !! 86 menu "Machine selection"
266 select TRACE_IRQFLAGS_SUPPORT !! 87
267 select TRACE_IRQFLAGS_NMI_SUPPORT !! 88 choice
268 select HAVE_SOFTIRQ_ON_OWN_STACK !! 89 prompt "System type"
269 select USER_STACKTRACE_SUPPORT !! 90 default MIPS_GENERIC
270 select VDSO_GETRANDOM !! 91
>> 92 config MIPS_GENERIC
>> 93 bool "Generic board-agnostic MIPS kernel"
>> 94 select BOOT_RAW
>> 95 select BUILTIN_DTB
>> 96 select CEVT_R4K
>> 97 select CLKSRC_MIPS_GIC
>> 98 select COMMON_CLK
>> 99 select CPU_MIPSR2_IRQ_VI
>> 100 select CPU_MIPSR2_IRQ_EI
>> 101 select CSRC_R4K
>> 102 select DMA_PERDEV_COHERENT
>> 103 select HAVE_PCI
>> 104 select IRQ_MIPS_CPU
>> 105 select LIBFDT
>> 106 select MIPS_AUTO_PFN_OFFSET
>> 107 select MIPS_CPU_SCACHE
>> 108 select MIPS_GIC
>> 109 select MIPS_L1_CACHE_SHIFT_7
>> 110 select NO_EXCEPT_FILL
>> 111 select PCI_DRIVERS_GENERIC
>> 112 select PINCTRL
>> 113 select SMP_UP if SMP
>> 114 select SWAP_IO_SPACE
>> 115 select SYS_HAS_CPU_MIPS32_R1
>> 116 select SYS_HAS_CPU_MIPS32_R2
>> 117 select SYS_HAS_CPU_MIPS32_R6
>> 118 select SYS_HAS_CPU_MIPS64_R1
>> 119 select SYS_HAS_CPU_MIPS64_R2
>> 120 select SYS_HAS_CPU_MIPS64_R6
>> 121 select SYS_SUPPORTS_32BIT_KERNEL
>> 122 select SYS_SUPPORTS_64BIT_KERNEL
>> 123 select SYS_SUPPORTS_BIG_ENDIAN
>> 124 select SYS_SUPPORTS_HIGHMEM
>> 125 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 126 select SYS_SUPPORTS_MICROMIPS
>> 127 select SYS_SUPPORTS_MIPS_CPS
>> 128 select SYS_SUPPORTS_MIPS16
>> 129 select SYS_SUPPORTS_MULTITHREADING
>> 130 select SYS_SUPPORTS_RELOCATABLE
>> 131 select SYS_SUPPORTS_SMARTMIPS
>> 132 select USB_EHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
>> 133 select USB_EHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 134 select USB_OHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
>> 135 select USB_OHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 136 select USB_UHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
>> 137 select USB_UHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 138 select USE_OF
>> 139 select UHI_BOOT
>> 140 help
>> 141 Select this to build a kernel which aims to support multiple boards,
>> 142 generally using a flattened device tree passed from the bootloader
>> 143 using the boot protocol defined in the UHI (Unified Hosting
>> 144 Interface) specification.
>> 145
>> 146 config MIPS_ALCHEMY
>> 147 bool "Alchemy processor based machines"
>> 148 select PHYS_ADDR_T_64BIT
>> 149 select CEVT_R4K
>> 150 select CSRC_R4K
>> 151 select IRQ_MIPS_CPU
>> 152 select DMA_MAYBE_COHERENT # Au1000,1500,1100 aren't, rest is
>> 153 select SYS_HAS_CPU_MIPS32_R1
>> 154 select SYS_SUPPORTS_32BIT_KERNEL
>> 155 select SYS_SUPPORTS_APM_EMULATION
>> 156 select GPIOLIB
>> 157 select SYS_SUPPORTS_ZBOOT
>> 158 select COMMON_CLK
>> 159
>> 160 config AR7
>> 161 bool "Texas Instruments AR7"
>> 162 select BOOT_ELF32
>> 163 select DMA_NONCOHERENT
>> 164 select CEVT_R4K
>> 165 select CSRC_R4K
>> 166 select IRQ_MIPS_CPU
>> 167 select NO_EXCEPT_FILL
>> 168 select SWAP_IO_SPACE
>> 169 select SYS_HAS_CPU_MIPS32_R1
>> 170 select SYS_HAS_EARLY_PRINTK
>> 171 select SYS_SUPPORTS_32BIT_KERNEL
>> 172 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 173 select SYS_SUPPORTS_MIPS16
>> 174 select SYS_SUPPORTS_ZBOOT_UART16550
>> 175 select GPIOLIB
>> 176 select VLYNQ
>> 177 select HAVE_CLK
>> 178 help
>> 179 Support for the Texas Instruments AR7 System-on-a-Chip
>> 180 family: TNETD7100, 7200 and 7300.
>> 181
>> 182 config ATH25
>> 183 bool "Atheros AR231x/AR531x SoC support"
>> 184 select CEVT_R4K
>> 185 select CSRC_R4K
>> 186 select DMA_NONCOHERENT
>> 187 select IRQ_MIPS_CPU
>> 188 select IRQ_DOMAIN
>> 189 select SYS_HAS_CPU_MIPS32_R1
>> 190 select SYS_SUPPORTS_BIG_ENDIAN
>> 191 select SYS_SUPPORTS_32BIT_KERNEL
>> 192 select SYS_HAS_EARLY_PRINTK
>> 193 help
>> 194 Support for Atheros AR231x and Atheros AR531x based boards
>> 195
>> 196 config ATH79
>> 197 bool "Atheros AR71XX/AR724X/AR913X based boards"
>> 198 select ARCH_HAS_RESET_CONTROLLER
>> 199 select BOOT_RAW
>> 200 select CEVT_R4K
>> 201 select CSRC_R4K
>> 202 select DMA_NONCOHERENT
>> 203 select GPIOLIB
>> 204 select PINCTRL
>> 205 select HAVE_CLK
>> 206 select COMMON_CLK
>> 207 select CLKDEV_LOOKUP
>> 208 select IRQ_MIPS_CPU
>> 209 select SYS_HAS_CPU_MIPS32_R2
>> 210 select SYS_HAS_EARLY_PRINTK
>> 211 select SYS_SUPPORTS_32BIT_KERNEL
>> 212 select SYS_SUPPORTS_BIG_ENDIAN
>> 213 select SYS_SUPPORTS_MIPS16
>> 214 select SYS_SUPPORTS_ZBOOT_UART_PROM
>> 215 select USE_OF
>> 216 select USB_EHCI_ROOT_HUB_TT if USB_EHCI_HCD_PLATFORM
>> 217 help
>> 218 Support for the Atheros AR71XX/AR724X/AR913X SoCs.
>> 219
>> 220 config BMIPS_GENERIC
>> 221 bool "Broadcom Generic BMIPS kernel"
>> 222 select ARCH_HAS_SYNC_DMA_FOR_CPU_ALL
>> 223 select ARCH_HAS_PHYS_TO_DMA
>> 224 select BOOT_RAW
>> 225 select NO_EXCEPT_FILL
>> 226 select USE_OF
>> 227 select CEVT_R4K
>> 228 select CSRC_R4K
>> 229 select SYNC_R4K
>> 230 select COMMON_CLK
>> 231 select BCM6345_L1_IRQ
>> 232 select BCM7038_L1_IRQ
>> 233 select BCM7120_L2_IRQ
>> 234 select BRCMSTB_L2_IRQ
>> 235 select IRQ_MIPS_CPU
>> 236 select DMA_NONCOHERENT
>> 237 select SYS_SUPPORTS_32BIT_KERNEL
>> 238 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 239 select SYS_SUPPORTS_BIG_ENDIAN
>> 240 select SYS_SUPPORTS_HIGHMEM
>> 241 select SYS_HAS_CPU_BMIPS32_3300
>> 242 select SYS_HAS_CPU_BMIPS4350
>> 243 select SYS_HAS_CPU_BMIPS4380
>> 244 select SYS_HAS_CPU_BMIPS5000
>> 245 select SWAP_IO_SPACE
>> 246 select USB_EHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
>> 247 select USB_EHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 248 select USB_OHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
>> 249 select USB_OHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 250 select HARDIRQS_SW_RESEND
271 help 251 help
272 ARM 64-bit (AArch64) Linux support. !! 252 Build a generic DT-based kernel image that boots on select
>> 253 BCM33xx cable modem chips, BCM63xx DSL chips, and BCM7xxx set-top
>> 254 box chips. Note that CONFIG_CPU_BIG_ENDIAN/CONFIG_CPU_LITTLE_ENDIAN
>> 255 must be set appropriately for your board.
>> 256
>> 257 config BCM47XX
>> 258 bool "Broadcom BCM47XX based boards"
>> 259 select BOOT_RAW
>> 260 select CEVT_R4K
>> 261 select CSRC_R4K
>> 262 select DMA_NONCOHERENT
>> 263 select HAVE_PCI
>> 264 select IRQ_MIPS_CPU
>> 265 select SYS_HAS_CPU_MIPS32_R1
>> 266 select NO_EXCEPT_FILL
>> 267 select SYS_SUPPORTS_32BIT_KERNEL
>> 268 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 269 select SYS_SUPPORTS_MIPS16
>> 270 select SYS_SUPPORTS_ZBOOT
>> 271 select SYS_HAS_EARLY_PRINTK
>> 272 select USE_GENERIC_EARLY_PRINTK_8250
>> 273 select GPIOLIB
>> 274 select LEDS_GPIO_REGISTER
>> 275 select BCM47XX_NVRAM
>> 276 select BCM47XX_SPROM
>> 277 select BCM47XX_SSB if !BCM47XX_BCMA
>> 278 help
>> 279 Support for BCM47XX based boards
>> 280
>> 281 config BCM63XX
>> 282 bool "Broadcom BCM63XX based boards"
>> 283 select BOOT_RAW
>> 284 select CEVT_R4K
>> 285 select CSRC_R4K
>> 286 select SYNC_R4K
>> 287 select DMA_NONCOHERENT
>> 288 select IRQ_MIPS_CPU
>> 289 select SYS_SUPPORTS_32BIT_KERNEL
>> 290 select SYS_SUPPORTS_BIG_ENDIAN
>> 291 select SYS_HAS_EARLY_PRINTK
>> 292 select SWAP_IO_SPACE
>> 293 select GPIOLIB
>> 294 select HAVE_CLK
>> 295 select MIPS_L1_CACHE_SHIFT_4
>> 296 select CLKDEV_LOOKUP
>> 297 help
>> 298 Support for BCM63XX based boards
>> 299
>> 300 config MIPS_COBALT
>> 301 bool "Cobalt Server"
>> 302 select CEVT_R4K
>> 303 select CSRC_R4K
>> 304 select CEVT_GT641XX
>> 305 select DMA_NONCOHERENT
>> 306 select FORCE_PCI
>> 307 select I8253
>> 308 select I8259
>> 309 select IRQ_MIPS_CPU
>> 310 select IRQ_GT641XX
>> 311 select PCI_GT64XXX_PCI0
>> 312 select SYS_HAS_CPU_NEVADA
>> 313 select SYS_HAS_EARLY_PRINTK
>> 314 select SYS_SUPPORTS_32BIT_KERNEL
>> 315 select SYS_SUPPORTS_64BIT_KERNEL
>> 316 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 317 select USE_GENERIC_EARLY_PRINTK_8250
>> 318
>> 319 config MACH_DECSTATION
>> 320 bool "DECstations"
>> 321 select BOOT_ELF32
>> 322 select CEVT_DS1287
>> 323 select CEVT_R4K if CPU_R4X00
>> 324 select CSRC_IOASIC
>> 325 select CSRC_R4K if CPU_R4X00
>> 326 select CPU_DADDI_WORKAROUNDS if 64BIT
>> 327 select CPU_R4000_WORKAROUNDS if 64BIT
>> 328 select CPU_R4400_WORKAROUNDS if 64BIT
>> 329 select DMA_NONCOHERENT
>> 330 select NO_IOPORT_MAP
>> 331 select IRQ_MIPS_CPU
>> 332 select SYS_HAS_CPU_R3000
>> 333 select SYS_HAS_CPU_R4X00
>> 334 select SYS_SUPPORTS_32BIT_KERNEL
>> 335 select SYS_SUPPORTS_64BIT_KERNEL
>> 336 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 337 select SYS_SUPPORTS_128HZ
>> 338 select SYS_SUPPORTS_256HZ
>> 339 select SYS_SUPPORTS_1024HZ
>> 340 select MIPS_L1_CACHE_SHIFT_4
>> 341 help
>> 342 This enables support for DEC's MIPS based workstations. For details
>> 343 see the Linux/MIPS FAQ on <http://www.linux-mips.org/> and the
>> 344 DECstation porting pages on <http://decstation.unix-ag.org/>.
>> 345
>> 346 If you have one of the following DECstation Models you definitely
>> 347 want to choose R4xx0 for the CPU Type:
>> 348
>> 349 DECstation 5000/50
>> 350 DECstation 5000/150
>> 351 DECstation 5000/260
>> 352 DECsystem 5900/260
>> 353
>> 354 otherwise choose R3000.
>> 355
>> 356 config MACH_JAZZ
>> 357 bool "Jazz family of machines"
>> 358 select ARCH_MIGHT_HAVE_PC_PARPORT
>> 359 select ARCH_MIGHT_HAVE_PC_SERIO
>> 360 select FW_ARC
>> 361 select FW_ARC32
>> 362 select ARCH_MAY_HAVE_PC_FDC
>> 363 select CEVT_R4K
>> 364 select CSRC_R4K
>> 365 select DEFAULT_SGI_PARTITION if CPU_BIG_ENDIAN
>> 366 select GENERIC_ISA_DMA
>> 367 select HAVE_PCSPKR_PLATFORM
>> 368 select IRQ_MIPS_CPU
>> 369 select I8253
>> 370 select I8259
>> 371 select ISA
>> 372 select SYS_HAS_CPU_R4X00
>> 373 select SYS_SUPPORTS_32BIT_KERNEL
>> 374 select SYS_SUPPORTS_64BIT_KERNEL
>> 375 select SYS_SUPPORTS_100HZ
>> 376 help
>> 377 This a family of machines based on the MIPS R4030 chipset which was
>> 378 used by several vendors to build RISC/os and Windows NT workstations.
>> 379 Members include the Acer PICA, MIPS Magnum 4000, MIPS Millennium and
>> 380 Olivetti M700-10 workstations.
>> 381
>> 382 config MACH_INGENIC
>> 383 bool "Ingenic SoC based machines"
>> 384 select SYS_SUPPORTS_32BIT_KERNEL
>> 385 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 386 select SYS_SUPPORTS_ZBOOT_UART16550
>> 387 select DMA_NONCOHERENT
>> 388 select IRQ_MIPS_CPU
>> 389 select PINCTRL
>> 390 select GPIOLIB
>> 391 select COMMON_CLK
>> 392 select GENERIC_IRQ_CHIP
>> 393 select BUILTIN_DTB if MIPS_NO_APPENDED_DTB
>> 394 select USE_OF
>> 395 select LIBFDT
273 396
274 config RUSTC_SUPPORTS_ARM64 !! 397 config LANTIQ
275 def_bool y !! 398 bool "Lantiq based platforms"
276 depends on CPU_LITTLE_ENDIAN !! 399 select DMA_NONCOHERENT
277 # Shadow call stack is only supported !! 400 select IRQ_MIPS_CPU
>> 401 select CEVT_R4K
>> 402 select CSRC_R4K
>> 403 select SYS_HAS_CPU_MIPS32_R1
>> 404 select SYS_HAS_CPU_MIPS32_R2
>> 405 select SYS_SUPPORTS_BIG_ENDIAN
>> 406 select SYS_SUPPORTS_32BIT_KERNEL
>> 407 select SYS_SUPPORTS_MIPS16
>> 408 select SYS_SUPPORTS_MULTITHREADING
>> 409 select SYS_SUPPORTS_VPE_LOADER
>> 410 select SYS_HAS_EARLY_PRINTK
>> 411 select GPIOLIB
>> 412 select SWAP_IO_SPACE
>> 413 select BOOT_RAW
>> 414 select CLKDEV_LOOKUP
>> 415 select USE_OF
>> 416 select PINCTRL
>> 417 select PINCTRL_LANTIQ
>> 418 select ARCH_HAS_RESET_CONTROLLER
>> 419 select RESET_CONTROLLER
>> 420
>> 421 config LASAT
>> 422 bool "LASAT Networks platforms"
>> 423 select CEVT_R4K
>> 424 select CRC32
>> 425 select CSRC_R4K
>> 426 select DMA_NONCOHERENT
>> 427 select SYS_HAS_EARLY_PRINTK
>> 428 select HAVE_PCI
>> 429 select IRQ_MIPS_CPU
>> 430 select PCI_GT64XXX_PCI0
>> 431 select MIPS_NILE4
>> 432 select R5000_CPU_SCACHE
>> 433 select SYS_HAS_CPU_R5000
>> 434 select SYS_SUPPORTS_32BIT_KERNEL
>> 435 select SYS_SUPPORTS_64BIT_KERNEL if BROKEN
>> 436 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 437
>> 438 config MACH_LOONGSON32
>> 439 bool "Loongson-1 family of machines"
>> 440 select SYS_SUPPORTS_ZBOOT
>> 441 help
>> 442 This enables support for the Loongson-1 family of machines.
>> 443
>> 444 Loongson-1 is a family of 32-bit MIPS-compatible SoCs developed by
>> 445 the Institute of Computing Technology (ICT), Chinese Academy of
>> 446 Sciences (CAS).
>> 447
>> 448 config MACH_LOONGSON64
>> 449 bool "Loongson-2/3 family of machines"
>> 450 select SYS_SUPPORTS_ZBOOT
>> 451 help
>> 452 This enables the support of Loongson-2/3 family of machines.
>> 453
>> 454 Loongson-2 is a family of single-core CPUs and Loongson-3 is a
>> 455 family of multi-core CPUs. They are both 64-bit general-purpose
>> 456 MIPS-compatible CPUs. Loongson-2/3 are developed by the Institute
>> 457 of Computing Technology (ICT), Chinese Academy of Sciences (CAS)
>> 458 in the People's Republic of China. The chief architect is Professor
>> 459 Weiwu Hu.
>> 460
>> 461 config MACH_PISTACHIO
>> 462 bool "IMG Pistachio SoC based boards"
>> 463 select BOOT_ELF32
>> 464 select BOOT_RAW
>> 465 select CEVT_R4K
>> 466 select CLKSRC_MIPS_GIC
>> 467 select COMMON_CLK
>> 468 select CSRC_R4K
>> 469 select DMA_NONCOHERENT
>> 470 select GPIOLIB
>> 471 select IRQ_MIPS_CPU
>> 472 select LIBFDT
>> 473 select MFD_SYSCON
>> 474 select MIPS_CPU_SCACHE
>> 475 select MIPS_GIC
>> 476 select PINCTRL
>> 477 select REGULATOR
>> 478 select SYS_HAS_CPU_MIPS32_R2
>> 479 select SYS_SUPPORTS_32BIT_KERNEL
>> 480 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 481 select SYS_SUPPORTS_MIPS_CPS
>> 482 select SYS_SUPPORTS_MULTITHREADING
>> 483 select SYS_SUPPORTS_RELOCATABLE
>> 484 select SYS_SUPPORTS_ZBOOT
>> 485 select SYS_HAS_EARLY_PRINTK
>> 486 select USE_GENERIC_EARLY_PRINTK_8250
>> 487 select USE_OF
>> 488 help
>> 489 This enables support for the IMG Pistachio SoC platform.
>> 490
>> 491 config MIPS_MALTA
>> 492 bool "MIPS Malta board"
>> 493 select ARCH_MAY_HAVE_PC_FDC
>> 494 select ARCH_MIGHT_HAVE_PC_PARPORT
>> 495 select ARCH_MIGHT_HAVE_PC_SERIO
>> 496 select BOOT_ELF32
>> 497 select BOOT_RAW
>> 498 select BUILTIN_DTB
>> 499 select CEVT_R4K
>> 500 select CLKSRC_MIPS_GIC
>> 501 select COMMON_CLK
>> 502 select CSRC_R4K
>> 503 select DMA_MAYBE_COHERENT
>> 504 select GENERIC_ISA_DMA
>> 505 select HAVE_PCSPKR_PLATFORM
>> 506 select HAVE_PCI
>> 507 select I8253
>> 508 select I8259
>> 509 select IRQ_MIPS_CPU
>> 510 select LIBFDT
>> 511 select MIPS_BONITO64
>> 512 select MIPS_CPU_SCACHE
>> 513 select MIPS_GIC
>> 514 select MIPS_L1_CACHE_SHIFT_6
>> 515 select MIPS_MSC
>> 516 select PCI_GT64XXX_PCI0
>> 517 select SMP_UP if SMP
>> 518 select SWAP_IO_SPACE
>> 519 select SYS_HAS_CPU_MIPS32_R1
>> 520 select SYS_HAS_CPU_MIPS32_R2
>> 521 select SYS_HAS_CPU_MIPS32_R3_5
>> 522 select SYS_HAS_CPU_MIPS32_R5
>> 523 select SYS_HAS_CPU_MIPS32_R6
>> 524 select SYS_HAS_CPU_MIPS64_R1
>> 525 select SYS_HAS_CPU_MIPS64_R2
>> 526 select SYS_HAS_CPU_MIPS64_R6
>> 527 select SYS_HAS_CPU_NEVADA
>> 528 select SYS_HAS_CPU_RM7000
>> 529 select SYS_SUPPORTS_32BIT_KERNEL
>> 530 select SYS_SUPPORTS_64BIT_KERNEL
>> 531 select SYS_SUPPORTS_BIG_ENDIAN
>> 532 select SYS_SUPPORTS_HIGHMEM
>> 533 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 534 select SYS_SUPPORTS_MICROMIPS
>> 535 select SYS_SUPPORTS_MIPS16
>> 536 select SYS_SUPPORTS_MIPS_CMP
>> 537 select SYS_SUPPORTS_MIPS_CPS
>> 538 select SYS_SUPPORTS_MULTITHREADING
>> 539 select SYS_SUPPORTS_RELOCATABLE
>> 540 select SYS_SUPPORTS_SMARTMIPS
>> 541 select SYS_SUPPORTS_VPE_LOADER
>> 542 select SYS_SUPPORTS_ZBOOT
>> 543 select USE_OF
>> 544 select ZONE_DMA32 if 64BIT
>> 545 help
>> 546 This enables support for the MIPS Technologies Malta evaluation
>> 547 board.
>> 548
>> 549 config MACH_PIC32
>> 550 bool "Microchip PIC32 Family"
>> 551 help
>> 552 This enables support for the Microchip PIC32 family of platforms.
>> 553
>> 554 Microchip PIC32 is a family of general-purpose 32 bit MIPS core
>> 555 microcontrollers.
>> 556
>> 557 config NEC_MARKEINS
>> 558 bool "NEC EMMA2RH Mark-eins board"
>> 559 select SOC_EMMA2RH
>> 560 select HAVE_PCI
>> 561 help
>> 562 This enables support for the NEC Electronics Mark-eins boards.
>> 563
>> 564 config MACH_VR41XX
>> 565 bool "NEC VR4100 series based machines"
>> 566 select CEVT_R4K
>> 567 select CSRC_R4K
>> 568 select SYS_HAS_CPU_VR41XX
>> 569 select SYS_SUPPORTS_MIPS16
>> 570 select GPIOLIB
>> 571
>> 572 config NXP_STB220
>> 573 bool "NXP STB220 board"
>> 574 select SOC_PNX833X
>> 575 help
>> 576 Support for NXP Semiconductors STB220 Development Board.
>> 577
>> 578 config NXP_STB225
>> 579 bool "NXP 225 board"
>> 580 select SOC_PNX833X
>> 581 select SOC_PNX8335
>> 582 help
>> 583 Support for NXP Semiconductors STB225 Development Board.
>> 584
>> 585 config PMC_MSP
>> 586 bool "PMC-Sierra MSP chipsets"
>> 587 select CEVT_R4K
>> 588 select CSRC_R4K
>> 589 select DMA_NONCOHERENT
>> 590 select SWAP_IO_SPACE
>> 591 select NO_EXCEPT_FILL
>> 592 select BOOT_RAW
>> 593 select SYS_HAS_CPU_MIPS32_R1
>> 594 select SYS_HAS_CPU_MIPS32_R2
>> 595 select SYS_SUPPORTS_32BIT_KERNEL
>> 596 select SYS_SUPPORTS_BIG_ENDIAN
>> 597 select SYS_SUPPORTS_MIPS16
>> 598 select IRQ_MIPS_CPU
>> 599 select SERIAL_8250
>> 600 select SERIAL_8250_CONSOLE
>> 601 select USB_EHCI_BIG_ENDIAN_MMIO
>> 602 select USB_EHCI_BIG_ENDIAN_DESC
>> 603 help
>> 604 This adds support for the PMC-Sierra family of Multi-Service
>> 605 Processor System-On-A-Chips. These parts include a number
>> 606 of integrated peripherals, interfaces and DSPs in addition to
>> 607 a variety of MIPS cores.
>> 608
>> 609 config RALINK
>> 610 bool "Ralink based machines"
>> 611 select CEVT_R4K
>> 612 select CSRC_R4K
>> 613 select BOOT_RAW
>> 614 select DMA_NONCOHERENT
>> 615 select IRQ_MIPS_CPU
>> 616 select USE_OF
>> 617 select SYS_HAS_CPU_MIPS32_R1
>> 618 select SYS_HAS_CPU_MIPS32_R2
>> 619 select SYS_SUPPORTS_32BIT_KERNEL
>> 620 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 621 select SYS_SUPPORTS_MIPS16
>> 622 select SYS_HAS_EARLY_PRINTK
>> 623 select CLKDEV_LOOKUP
>> 624 select ARCH_HAS_RESET_CONTROLLER
>> 625 select RESET_CONTROLLER
>> 626
>> 627 config SGI_IP22
>> 628 bool "SGI IP22 (Indy/Indigo2)"
>> 629 select FW_ARC
>> 630 select FW_ARC32
>> 631 select ARCH_MIGHT_HAVE_PC_SERIO
>> 632 select BOOT_ELF32
>> 633 select CEVT_R4K
>> 634 select CSRC_R4K
>> 635 select DEFAULT_SGI_PARTITION
>> 636 select DMA_NONCOHERENT
>> 637 select HAVE_EISA
>> 638 select I8253
>> 639 select I8259
>> 640 select IP22_CPU_SCACHE
>> 641 select IRQ_MIPS_CPU
>> 642 select GENERIC_ISA_DMA_SUPPORT_BROKEN
>> 643 select SGI_HAS_I8042
>> 644 select SGI_HAS_INDYDOG
>> 645 select SGI_HAS_HAL2
>> 646 select SGI_HAS_SEEQ
>> 647 select SGI_HAS_WD93
>> 648 select SGI_HAS_ZILOG
>> 649 select SWAP_IO_SPACE
>> 650 select SYS_HAS_CPU_R4X00
>> 651 select SYS_HAS_CPU_R5000
>> 652 #
>> 653 # Disable EARLY_PRINTK for now since it leads to overwritten prom
>> 654 # memory during early boot on some machines.
278 # 655 #
279 # When using the UNWIND_PATCH_PAC_INTO !! 656 # See http://www.linux-mips.org/cgi-bin/mesg.cgi?a=linux-mips&i=20091119164009.GA15038%40deprecation.cyrius.com
280 # required due to use of the -Zfixed-x !! 657 # for a more details discussion
281 # 658 #
282 # Otherwise, rustc version 1.82+ is re !! 659 # select SYS_HAS_EARLY_PRINTK
283 # -Zsanitizer=shadow-call-stack flag. !! 660 select SYS_SUPPORTS_32BIT_KERNEL
284 depends on !SHADOW_CALL_STACK || RUSTC !! 661 select SYS_SUPPORTS_64BIT_KERNEL
285 !! 662 select SYS_SUPPORTS_BIG_ENDIAN
286 config CLANG_SUPPORTS_DYNAMIC_FTRACE_WITH_ARGS !! 663 select MIPS_L1_CACHE_SHIFT_7
287 def_bool CC_IS_CLANG !! 664 help
288 # https://github.com/ClangBuiltLinux/l !! 665 This are the SGI Indy, Challenge S and Indigo2, as well as certain
289 depends on AS_IS_GNU || (AS_IS_LLVM && !! 666 OEM variants like the Tandem CMN B006S. To compile a Linux kernel
290 !! 667 that runs on these, say Y here.
291 config GCC_SUPPORTS_DYNAMIC_FTRACE_WITH_ARGS !! 668
292 def_bool CC_IS_GCC !! 669 config SGI_IP27
293 depends on $(cc-option,-fpatchable-fun !! 670 bool "SGI IP27 (Origin200/2000)"
>> 671 select ARCH_HAS_PHYS_TO_DMA
>> 672 select FW_ARC
>> 673 select FW_ARC64
>> 674 select BOOT_ELF64
>> 675 select DEFAULT_SGI_PARTITION
>> 676 select SYS_HAS_EARLY_PRINTK
>> 677 select HAVE_PCI
>> 678 select IRQ_MIPS_CPU
>> 679 select IRQ_DOMAIN_HIERARCHY
>> 680 select NR_CPUS_DEFAULT_64
>> 681 select PCI_DRIVERS_GENERIC
>> 682 select PCI_XTALK_BRIDGE
>> 683 select SYS_HAS_CPU_R10000
>> 684 select SYS_SUPPORTS_64BIT_KERNEL
>> 685 select SYS_SUPPORTS_BIG_ENDIAN
>> 686 select SYS_SUPPORTS_NUMA
>> 687 select SYS_SUPPORTS_SMP
>> 688 select MIPS_L1_CACHE_SHIFT_7
>> 689 help
>> 690 This are the SGI Origin 200, Origin 2000 and Onyx 2 Graphics
>> 691 workstations. To compile a Linux kernel that runs on these, say Y
>> 692 here.
>> 693
>> 694 config SGI_IP28
>> 695 bool "SGI IP28 (Indigo2 R10k)"
>> 696 select FW_ARC
>> 697 select FW_ARC64
>> 698 select ARCH_MIGHT_HAVE_PC_SERIO
>> 699 select BOOT_ELF64
>> 700 select CEVT_R4K
>> 701 select CSRC_R4K
>> 702 select DEFAULT_SGI_PARTITION
>> 703 select DMA_NONCOHERENT
>> 704 select GENERIC_ISA_DMA_SUPPORT_BROKEN
>> 705 select IRQ_MIPS_CPU
>> 706 select HAVE_EISA
>> 707 select I8253
>> 708 select I8259
>> 709 select SGI_HAS_I8042
>> 710 select SGI_HAS_INDYDOG
>> 711 select SGI_HAS_HAL2
>> 712 select SGI_HAS_SEEQ
>> 713 select SGI_HAS_WD93
>> 714 select SGI_HAS_ZILOG
>> 715 select SWAP_IO_SPACE
>> 716 select SYS_HAS_CPU_R10000
>> 717 #
>> 718 # Disable EARLY_PRINTK for now since it leads to overwritten prom
>> 719 # memory during early boot on some machines.
>> 720 #
>> 721 # See http://www.linux-mips.org/cgi-bin/mesg.cgi?a=linux-mips&i=20091119164009.GA15038%40deprecation.cyrius.com
>> 722 # for a more details discussion
>> 723 #
>> 724 # select SYS_HAS_EARLY_PRINTK
>> 725 select SYS_SUPPORTS_64BIT_KERNEL
>> 726 select SYS_SUPPORTS_BIG_ENDIAN
>> 727 select MIPS_L1_CACHE_SHIFT_7
>> 728 help
>> 729 This is the SGI Indigo2 with R10000 processor. To compile a Linux
>> 730 kernel that runs on these, say Y here.
>> 731
>> 732 config SGI_IP32
>> 733 bool "SGI IP32 (O2)"
>> 734 select ARCH_HAS_PHYS_TO_DMA
>> 735 select FW_ARC
>> 736 select FW_ARC32
>> 737 select BOOT_ELF32
>> 738 select CEVT_R4K
>> 739 select CSRC_R4K
>> 740 select DMA_NONCOHERENT
>> 741 select HAVE_PCI
>> 742 select IRQ_MIPS_CPU
>> 743 select R5000_CPU_SCACHE
>> 744 select RM7000_CPU_SCACHE
>> 745 select SYS_HAS_CPU_R5000
>> 746 select SYS_HAS_CPU_R10000 if BROKEN
>> 747 select SYS_HAS_CPU_RM7000
>> 748 select SYS_HAS_CPU_NEVADA
>> 749 select SYS_SUPPORTS_64BIT_KERNEL
>> 750 select SYS_SUPPORTS_BIG_ENDIAN
>> 751 help
>> 752 If you want this kernel to run on SGI O2 workstation, say Y here.
>> 753
>> 754 config SIBYTE_CRHINE
>> 755 bool "Sibyte BCM91120C-CRhine"
>> 756 select BOOT_ELF32
>> 757 select SIBYTE_BCM1120
>> 758 select SWAP_IO_SPACE
>> 759 select SYS_HAS_CPU_SB1
>> 760 select SYS_SUPPORTS_BIG_ENDIAN
>> 761 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 762
>> 763 config SIBYTE_CARMEL
>> 764 bool "Sibyte BCM91120x-Carmel"
>> 765 select BOOT_ELF32
>> 766 select SIBYTE_BCM1120
>> 767 select SWAP_IO_SPACE
>> 768 select SYS_HAS_CPU_SB1
>> 769 select SYS_SUPPORTS_BIG_ENDIAN
>> 770 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 771
>> 772 config SIBYTE_CRHONE
>> 773 bool "Sibyte BCM91125C-CRhone"
>> 774 select BOOT_ELF32
>> 775 select SIBYTE_BCM1125
>> 776 select SWAP_IO_SPACE
>> 777 select SYS_HAS_CPU_SB1
>> 778 select SYS_SUPPORTS_BIG_ENDIAN
>> 779 select SYS_SUPPORTS_HIGHMEM
>> 780 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 781
>> 782 config SIBYTE_RHONE
>> 783 bool "Sibyte BCM91125E-Rhone"
>> 784 select BOOT_ELF32
>> 785 select SIBYTE_BCM1125H
>> 786 select SWAP_IO_SPACE
>> 787 select SYS_HAS_CPU_SB1
>> 788 select SYS_SUPPORTS_BIG_ENDIAN
>> 789 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 790
>> 791 config SIBYTE_SWARM
>> 792 bool "Sibyte BCM91250A-SWARM"
>> 793 select BOOT_ELF32
>> 794 select HAVE_PATA_PLATFORM
>> 795 select SIBYTE_SB1250
>> 796 select SWAP_IO_SPACE
>> 797 select SYS_HAS_CPU_SB1
>> 798 select SYS_SUPPORTS_BIG_ENDIAN
>> 799 select SYS_SUPPORTS_HIGHMEM
>> 800 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 801 select ZONE_DMA32 if 64BIT
>> 802 select SWIOTLB if ARCH_DMA_ADDR_T_64BIT && PCI
>> 803
>> 804 config SIBYTE_LITTLESUR
>> 805 bool "Sibyte BCM91250C2-LittleSur"
>> 806 select BOOT_ELF32
>> 807 select HAVE_PATA_PLATFORM
>> 808 select SIBYTE_SB1250
>> 809 select SWAP_IO_SPACE
>> 810 select SYS_HAS_CPU_SB1
>> 811 select SYS_SUPPORTS_BIG_ENDIAN
>> 812 select SYS_SUPPORTS_HIGHMEM
>> 813 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 814 select ZONE_DMA32 if 64BIT
>> 815
>> 816 config SIBYTE_SENTOSA
>> 817 bool "Sibyte BCM91250E-Sentosa"
>> 818 select BOOT_ELF32
>> 819 select SIBYTE_SB1250
>> 820 select SWAP_IO_SPACE
>> 821 select SYS_HAS_CPU_SB1
>> 822 select SYS_SUPPORTS_BIG_ENDIAN
>> 823 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 824 select SWIOTLB if ARCH_DMA_ADDR_T_64BIT && PCI
>> 825
>> 826 config SIBYTE_BIGSUR
>> 827 bool "Sibyte BCM91480B-BigSur"
>> 828 select BOOT_ELF32
>> 829 select NR_CPUS_DEFAULT_4
>> 830 select SIBYTE_BCM1x80
>> 831 select SWAP_IO_SPACE
>> 832 select SYS_HAS_CPU_SB1
>> 833 select SYS_SUPPORTS_BIG_ENDIAN
>> 834 select SYS_SUPPORTS_HIGHMEM
>> 835 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 836 select ZONE_DMA32 if 64BIT
>> 837 select SWIOTLB if ARCH_DMA_ADDR_T_64BIT && PCI
>> 838
>> 839 config SNI_RM
>> 840 bool "SNI RM200/300/400"
>> 841 select FW_ARC if CPU_LITTLE_ENDIAN
>> 842 select FW_ARC32 if CPU_LITTLE_ENDIAN
>> 843 select FW_SNIPROM if CPU_BIG_ENDIAN
>> 844 select ARCH_MAY_HAVE_PC_FDC
>> 845 select ARCH_MIGHT_HAVE_PC_PARPORT
>> 846 select ARCH_MIGHT_HAVE_PC_SERIO
>> 847 select BOOT_ELF32
>> 848 select CEVT_R4K
>> 849 select CSRC_R4K
>> 850 select DEFAULT_SGI_PARTITION if CPU_BIG_ENDIAN
>> 851 select DMA_NONCOHERENT
>> 852 select GENERIC_ISA_DMA
>> 853 select HAVE_EISA
>> 854 select HAVE_PCSPKR_PLATFORM
>> 855 select HAVE_PCI
>> 856 select IRQ_MIPS_CPU
>> 857 select I8253
>> 858 select I8259
>> 859 select ISA
>> 860 select SWAP_IO_SPACE if CPU_BIG_ENDIAN
>> 861 select SYS_HAS_CPU_R4X00
>> 862 select SYS_HAS_CPU_R5000
>> 863 select SYS_HAS_CPU_R10000
>> 864 select R5000_CPU_SCACHE
>> 865 select SYS_HAS_EARLY_PRINTK
>> 866 select SYS_SUPPORTS_32BIT_KERNEL
>> 867 select SYS_SUPPORTS_64BIT_KERNEL
>> 868 select SYS_SUPPORTS_BIG_ENDIAN
>> 869 select SYS_SUPPORTS_HIGHMEM
>> 870 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 871 help
>> 872 The SNI RM200/300/400 are MIPS-based machines manufactured by
>> 873 Siemens Nixdorf Informationssysteme (SNI), parent company of Pyramid
>> 874 Technology and now in turn merged with Fujitsu. Say Y here to
>> 875 support this machine type.
>> 876
>> 877 config MACH_TX39XX
>> 878 bool "Toshiba TX39 series based machines"
>> 879
>> 880 config MACH_TX49XX
>> 881 bool "Toshiba TX49 series based machines"
>> 882
>> 883 config MIKROTIK_RB532
>> 884 bool "Mikrotik RB532 boards"
>> 885 select CEVT_R4K
>> 886 select CSRC_R4K
>> 887 select DMA_NONCOHERENT
>> 888 select HAVE_PCI
>> 889 select IRQ_MIPS_CPU
>> 890 select SYS_HAS_CPU_MIPS32_R1
>> 891 select SYS_SUPPORTS_32BIT_KERNEL
>> 892 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 893 select SWAP_IO_SPACE
>> 894 select BOOT_RAW
>> 895 select GPIOLIB
>> 896 select MIPS_L1_CACHE_SHIFT_4
>> 897 help
>> 898 Support the Mikrotik(tm) RouterBoard 532 series,
>> 899 based on the IDT RC32434 SoC.
>> 900
>> 901 config CAVIUM_OCTEON_SOC
>> 902 bool "Cavium Networks Octeon SoC based boards"
>> 903 select CEVT_R4K
>> 904 select ARCH_HAS_PHYS_TO_DMA
>> 905 select HAVE_RAPIDIO
>> 906 select PHYS_ADDR_T_64BIT
>> 907 select SYS_SUPPORTS_64BIT_KERNEL
>> 908 select SYS_SUPPORTS_BIG_ENDIAN
>> 909 select EDAC_SUPPORT
>> 910 select EDAC_ATOMIC_SCRUB
>> 911 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 912 select SYS_SUPPORTS_HOTPLUG_CPU if CPU_BIG_ENDIAN
>> 913 select SYS_HAS_EARLY_PRINTK
>> 914 select SYS_HAS_CPU_CAVIUM_OCTEON
>> 915 select HAVE_PCI
>> 916 select ZONE_DMA32
>> 917 select HOLES_IN_ZONE
>> 918 select GPIOLIB
>> 919 select LIBFDT
>> 920 select USE_OF
>> 921 select ARCH_SPARSEMEM_ENABLE
>> 922 select SYS_SUPPORTS_SMP
>> 923 select NR_CPUS_DEFAULT_64
>> 924 select MIPS_NR_CPU_NR_MAP_1024
>> 925 select BUILTIN_DTB
>> 926 select MTD_COMPLEX_MAPPINGS
>> 927 select SWIOTLB
>> 928 select SYS_SUPPORTS_RELOCATABLE
>> 929 help
>> 930 This option supports all of the Octeon reference boards from Cavium
>> 931 Networks. It builds a kernel that dynamically determines the Octeon
>> 932 CPU type and supports all known board reference implementations.
>> 933 Some of the supported boards are:
>> 934 EBT3000
>> 935 EBH3000
>> 936 EBH3100
>> 937 Thunder
>> 938 Kodama
>> 939 Hikari
>> 940 Say Y here for most Octeon reference boards.
>> 941
>> 942 config NLM_XLR_BOARD
>> 943 bool "Netlogic XLR/XLS based systems"
>> 944 select BOOT_ELF32
>> 945 select NLM_COMMON
>> 946 select SYS_HAS_CPU_XLR
>> 947 select SYS_SUPPORTS_SMP
>> 948 select HAVE_PCI
>> 949 select SWAP_IO_SPACE
>> 950 select SYS_SUPPORTS_32BIT_KERNEL
>> 951 select SYS_SUPPORTS_64BIT_KERNEL
>> 952 select PHYS_ADDR_T_64BIT
>> 953 select SYS_SUPPORTS_BIG_ENDIAN
>> 954 select SYS_SUPPORTS_HIGHMEM
>> 955 select NR_CPUS_DEFAULT_32
>> 956 select CEVT_R4K
>> 957 select CSRC_R4K
>> 958 select IRQ_MIPS_CPU
>> 959 select ZONE_DMA32 if 64BIT
>> 960 select SYNC_R4K
>> 961 select SYS_HAS_EARLY_PRINTK
>> 962 select SYS_SUPPORTS_ZBOOT
>> 963 select SYS_SUPPORTS_ZBOOT_UART16550
>> 964 help
>> 965 Support for systems based on Netlogic XLR and XLS processors.
>> 966 Say Y here if you have a XLR or XLS based board.
>> 967
>> 968 config NLM_XLP_BOARD
>> 969 bool "Netlogic XLP based systems"
>> 970 select BOOT_ELF32
>> 971 select NLM_COMMON
>> 972 select SYS_HAS_CPU_XLP
>> 973 select SYS_SUPPORTS_SMP
>> 974 select HAVE_PCI
>> 975 select SYS_SUPPORTS_32BIT_KERNEL
>> 976 select SYS_SUPPORTS_64BIT_KERNEL
>> 977 select PHYS_ADDR_T_64BIT
>> 978 select GPIOLIB
>> 979 select SYS_SUPPORTS_BIG_ENDIAN
>> 980 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 981 select SYS_SUPPORTS_HIGHMEM
>> 982 select NR_CPUS_DEFAULT_32
>> 983 select CEVT_R4K
>> 984 select CSRC_R4K
>> 985 select IRQ_MIPS_CPU
>> 986 select ZONE_DMA32 if 64BIT
>> 987 select SYNC_R4K
>> 988 select SYS_HAS_EARLY_PRINTK
>> 989 select USE_OF
>> 990 select SYS_SUPPORTS_ZBOOT
>> 991 select SYS_SUPPORTS_ZBOOT_UART16550
>> 992 help
>> 993 This board is based on Netlogic XLP Processor.
>> 994 Say Y here if you have a XLP based board.
>> 995
>> 996 config MIPS_PARAVIRT
>> 997 bool "Para-Virtualized guest system"
>> 998 select CEVT_R4K
>> 999 select CSRC_R4K
>> 1000 select SYS_SUPPORTS_64BIT_KERNEL
>> 1001 select SYS_SUPPORTS_32BIT_KERNEL
>> 1002 select SYS_SUPPORTS_BIG_ENDIAN
>> 1003 select SYS_SUPPORTS_SMP
>> 1004 select NR_CPUS_DEFAULT_4
>> 1005 select SYS_HAS_EARLY_PRINTK
>> 1006 select SYS_HAS_CPU_MIPS32_R2
>> 1007 select SYS_HAS_CPU_MIPS64_R2
>> 1008 select SYS_HAS_CPU_CAVIUM_OCTEON
>> 1009 select HAVE_PCI
>> 1010 select SWAP_IO_SPACE
>> 1011 help
>> 1012 This option supports guest running under ????
294 1013
295 config 64BIT !! 1014 endchoice
296 def_bool y <<
297 1015
298 config MMU !! 1016 source "arch/mips/alchemy/Kconfig"
299 def_bool y !! 1017 source "arch/mips/ath25/Kconfig"
>> 1018 source "arch/mips/ath79/Kconfig"
>> 1019 source "arch/mips/bcm47xx/Kconfig"
>> 1020 source "arch/mips/bcm63xx/Kconfig"
>> 1021 source "arch/mips/bmips/Kconfig"
>> 1022 source "arch/mips/generic/Kconfig"
>> 1023 source "arch/mips/jazz/Kconfig"
>> 1024 source "arch/mips/jz4740/Kconfig"
>> 1025 source "arch/mips/lantiq/Kconfig"
>> 1026 source "arch/mips/lasat/Kconfig"
>> 1027 source "arch/mips/pic32/Kconfig"
>> 1028 source "arch/mips/pistachio/Kconfig"
>> 1029 source "arch/mips/pmcs-msp71xx/Kconfig"
>> 1030 source "arch/mips/ralink/Kconfig"
>> 1031 source "arch/mips/sgi-ip27/Kconfig"
>> 1032 source "arch/mips/sibyte/Kconfig"
>> 1033 source "arch/mips/txx9/Kconfig"
>> 1034 source "arch/mips/vr41xx/Kconfig"
>> 1035 source "arch/mips/cavium-octeon/Kconfig"
>> 1036 source "arch/mips/loongson32/Kconfig"
>> 1037 source "arch/mips/loongson64/Kconfig"
>> 1038 source "arch/mips/netlogic/Kconfig"
>> 1039 source "arch/mips/paravirt/Kconfig"
300 1040
301 config ARM64_CONT_PTE_SHIFT !! 1041 endmenu
302 int <<
303 default 5 if PAGE_SIZE_64KB <<
304 default 7 if PAGE_SIZE_16KB <<
305 default 4 <<
306 1042
307 config ARM64_CONT_PMD_SHIFT !! 1043 config GENERIC_HWEIGHT
308 int !! 1044 bool
309 default 5 if PAGE_SIZE_64KB !! 1045 default y
310 default 5 if PAGE_SIZE_16KB <<
311 default 4 <<
312 1046
313 config ARCH_MMAP_RND_BITS_MIN !! 1047 config GENERIC_CALIBRATE_DELAY
314 default 14 if PAGE_SIZE_64KB !! 1048 bool
315 default 16 if PAGE_SIZE_16KB !! 1049 default y
316 default 18 <<
317 1050
318 # max bits determined by the following formula !! 1051 config SCHED_OMIT_FRAME_POINTER
319 # VA_BITS - PAGE_SHIFT - 3 !! 1052 bool
320 config ARCH_MMAP_RND_BITS_MAX !! 1053 default y
321 default 19 if ARM64_VA_BITS=36 <<
322 default 24 if ARM64_VA_BITS=39 <<
323 default 27 if ARM64_VA_BITS=42 <<
324 default 30 if ARM64_VA_BITS=47 <<
325 default 29 if ARM64_VA_BITS=48 && ARM6 <<
326 default 31 if ARM64_VA_BITS=48 && ARM6 <<
327 default 33 if ARM64_VA_BITS=48 <<
328 default 14 if ARM64_64K_PAGES <<
329 default 16 if ARM64_16K_PAGES <<
330 default 18 <<
331 1054
332 config ARCH_MMAP_RND_COMPAT_BITS_MIN !! 1055 #
333 default 7 if ARM64_64K_PAGES !! 1056 # Select some configuration options automatically based on user selections.
334 default 9 if ARM64_16K_PAGES !! 1057 #
335 default 11 !! 1058 config FW_ARC
>> 1059 bool
336 1060
337 config ARCH_MMAP_RND_COMPAT_BITS_MAX !! 1061 config ARCH_MAY_HAVE_PC_FDC
338 default 16 !! 1062 bool
339 1063
340 config NO_IOPORT_MAP !! 1064 config BOOT_RAW
341 def_bool y if !PCI !! 1065 bool
342 1066
343 config STACKTRACE_SUPPORT !! 1067 config CEVT_BCM1480
344 def_bool y !! 1068 bool
345 1069
346 config ILLEGAL_POINTER_VALUE !! 1070 config CEVT_DS1287
347 hex !! 1071 bool
348 default 0xdead000000000000 <<
349 1072
350 config LOCKDEP_SUPPORT !! 1073 config CEVT_GT641XX
351 def_bool y !! 1074 bool
352 1075
353 config GENERIC_BUG !! 1076 config CEVT_R4K
354 def_bool y !! 1077 bool
355 depends on BUG <<
356 1078
357 config GENERIC_BUG_RELATIVE_POINTERS !! 1079 config CEVT_SB1250
358 def_bool y !! 1080 bool
359 depends on GENERIC_BUG <<
360 1081
361 config GENERIC_HWEIGHT !! 1082 config CEVT_TXX9
362 def_bool y !! 1083 bool
363 1084
364 config GENERIC_CSUM !! 1085 config CSRC_BCM1480
365 def_bool y !! 1086 bool
366 1087
367 config GENERIC_CALIBRATE_DELAY !! 1088 config CSRC_IOASIC
368 def_bool y !! 1089 bool
369 1090
370 config SMP !! 1091 config CSRC_R4K
371 def_bool y !! 1092 bool
372 1093
373 config KERNEL_MODE_NEON !! 1094 config CSRC_SB1250
374 def_bool y !! 1095 bool
375 1096
376 config FIX_EARLYCON_MEM !! 1097 config MIPS_CLOCK_VSYSCALL
377 def_bool y !! 1098 def_bool CSRC_R4K || CLKSRC_MIPS_GIC
378 1099
379 config PGTABLE_LEVELS !! 1100 config GPIO_TXX9
380 int !! 1101 select GPIOLIB
381 default 2 if ARM64_16K_PAGES && ARM64_ !! 1102 bool
382 default 2 if ARM64_64K_PAGES && ARM64_ !! 1103
383 default 3 if ARM64_64K_PAGES && (ARM64 !! 1104 config FW_CFE
384 default 3 if ARM64_4K_PAGES && ARM64_V !! 1105 bool
385 default 3 if ARM64_16K_PAGES && ARM64_ <<
386 default 4 if ARM64_16K_PAGES && (ARM64 <<
387 default 4 if !ARM64_64K_PAGES && ARM64 <<
388 default 5 if ARM64_4K_PAGES && ARM64_V <<
389 1106
390 config ARCH_SUPPORTS_UPROBES 1107 config ARCH_SUPPORTS_UPROBES
391 def_bool y !! 1108 bool
392 1109
393 config ARCH_PROC_KCORE_TEXT !! 1110 config DMA_MAYBE_COHERENT
394 def_bool y !! 1111 select ARCH_HAS_DMA_COHERENCE_H
>> 1112 select DMA_NONCOHERENT
>> 1113 bool
395 1114
396 config BROKEN_GAS_INST !! 1115 config DMA_PERDEV_COHERENT
397 def_bool !$(as-instr,1:\n.inst 0\n.rep !! 1116 bool
>> 1117 select ARCH_HAS_SETUP_DMA_OPS
>> 1118 select DMA_NONCOHERENT
398 1119
399 config BUILTIN_RETURN_ADDRESS_STRIPS_PAC !! 1120 config DMA_NONCOHERENT
400 bool 1121 bool
401 # Clang's __builtin_return_address() s !! 1122 select ARCH_HAS_DMA_MMAP_PGPROT
402 # https://github.com/llvm/llvm-project !! 1123 select ARCH_HAS_SYNC_DMA_FOR_DEVICE
403 default y if CC_IS_CLANG !! 1124 select ARCH_HAS_UNCACHED_SEGMENT
404 # GCC's __builtin_return_address() str !! 1125 select NEED_DMA_MAP_STATE
405 # and this was backported to 10.2.0, 9 !! 1126 select ARCH_HAS_DMA_COHERENT_TO_PFN
406 # https://gcc.gnu.org/bugzilla/show_bu !! 1127 select DMA_NONCOHERENT_CACHE_SYNC
407 default y if CC_IS_GCC && (GCC_VERSION <<
408 default y if CC_IS_GCC && (GCC_VERSION <<
409 default y if CC_IS_GCC && (GCC_VERSION <<
410 default y if CC_IS_GCC && (GCC_VERSION <<
411 default n <<
412 1128
413 config KASAN_SHADOW_OFFSET !! 1129 config SYS_HAS_EARLY_PRINTK
414 hex !! 1130 bool
415 depends on KASAN_GENERIC || KASAN_SW_T <<
416 default 0xdfff800000000000 if (ARM64_V <<
417 default 0xdfffc00000000000 if (ARM64_V <<
418 default 0xdffffe0000000000 if ARM64_VA <<
419 default 0xdfffffc000000000 if ARM64_VA <<
420 default 0xdffffff800000000 if ARM64_VA <<
421 default 0xefff800000000000 if (ARM64_V <<
422 default 0xefffc00000000000 if (ARM64_V <<
423 default 0xeffffe0000000000 if ARM64_VA <<
424 default 0xefffffc000000000 if ARM64_VA <<
425 default 0xeffffff800000000 if ARM64_VA <<
426 default 0xffffffffffffffff <<
427 <<
428 config UNWIND_TABLES <<
429 bool <<
430 <<
431 source "arch/arm64/Kconfig.platforms" <<
432 <<
433 menu "Kernel Features" <<
434 <<
435 menu "ARM errata workarounds via the alternati <<
436 <<
437 config AMPERE_ERRATUM_AC03_CPU_38 <<
438 bool "AmpereOne: AC03_CPU_38: Certain <<
439 default y <<
440 help <<
441 This option adds an alternative code <<
442 errata AC03_CPU_38 and AC04_CPU_10 o <<
443 <<
444 The affected design reports FEAT_HAF <<
445 ID_AA64MMFR1_EL1.HAFDBS, but (V)TCR_ <<
446 as required by the architecture. The <<
447 implementation suffers from an addit <<
448 A/D updates can occur after a PTE ha <<
449 <<
450 The workaround forces KVM to explici <<
451 which avoids enabling unadvertised h <<
452 at stage-2. <<
453 1131
454 If unsure, say Y. !! 1132 config SYS_SUPPORTS_HOTPLUG_CPU
>> 1133 bool
455 1134
456 config ARM64_WORKAROUND_CLEAN_CACHE !! 1135 config MIPS_BONITO64
457 bool 1136 bool
458 1137
459 config ARM64_ERRATUM_826319 !! 1138 config MIPS_MSC
460 bool "Cortex-A53: 826319: System might !! 1139 bool
461 default y <<
462 select ARM64_WORKAROUND_CLEAN_CACHE <<
463 help <<
464 This option adds an alternative code <<
465 erratum 826319 on Cortex-A53 parts u <<
466 AXI master interface and an L2 cache <<
467 1140
468 If a Cortex-A53 uses an AMBA AXI4 AC !! 1141 config MIPS_NILE4
469 and is unable to accept a certain wr !! 1142 bool
470 not progress on read data presented <<
471 system can deadlock. <<
472 1143
473 The workaround promotes data cache c !! 1144 config SYNC_R4K
474 data cache clean-and-invalidate. !! 1145 bool
475 Please note that this does not neces <<
476 as it depends on the alternative fra <<
477 the kernel if an affected CPU is det <<
478 1146
479 If unsure, say Y. !! 1147 config MIPS_MACHINE
>> 1148 def_bool n
480 1149
481 config ARM64_ERRATUM_827319 !! 1150 config NO_IOPORT_MAP
482 bool "Cortex-A53: 827319: Data cache c !! 1151 def_bool n
483 default y <<
484 select ARM64_WORKAROUND_CLEAN_CACHE <<
485 help <<
486 This option adds an alternative code <<
487 erratum 827319 on Cortex-A53 parts u <<
488 master interface and an L2 cache. <<
489 <<
490 Under certain conditions this erratu <<
491 to occur at the same time as another <<
492 on the AMBA 5 CHI interface, which c <<
493 interconnect reorders the two transa <<
494 <<
495 The workaround promotes data cache c <<
496 data cache clean-and-invalidate. <<
497 Please note that this does not neces <<
498 as it depends on the alternative fra <<
499 the kernel if an affected CPU is det <<
500 1152
501 If unsure, say Y. !! 1153 config GENERIC_CSUM
>> 1154 bool
>> 1155 default y if !CPU_HAS_LOAD_STORE_LR
502 1156
503 config ARM64_ERRATUM_824069 !! 1157 config GENERIC_ISA_DMA
504 bool "Cortex-A53: 824069: Cache line m !! 1158 bool
505 default y !! 1159 select ZONE_DMA if GENERIC_ISA_DMA_SUPPORT_BROKEN=n
506 select ARM64_WORKAROUND_CLEAN_CACHE !! 1160 select ISA_DMA_API
507 help <<
508 This option adds an alternative code <<
509 erratum 824069 on Cortex-A53 parts u <<
510 to a coherent interconnect. <<
511 <<
512 If a Cortex-A53 processor is executi <<
513 write instruction at the same time a <<
514 cluster is executing a cache mainten <<
515 address, then this erratum might cau <<
516 incorrectly marked as dirty. <<
517 <<
518 The workaround promotes data cache c <<
519 data cache clean-and-invalidate. <<
520 Please note that this option does no <<
521 workaround, as it depends on the alt <<
522 only patch the kernel if an affected <<
523 1161
524 If unsure, say Y. !! 1162 config GENERIC_ISA_DMA_SUPPORT_BROKEN
>> 1163 bool
>> 1164 select GENERIC_ISA_DMA
525 1165
526 config ARM64_ERRATUM_819472 !! 1166 config ISA_DMA_API
527 bool "Cortex-A53: 819472: Store exclus !! 1167 bool
528 default y <<
529 select ARM64_WORKAROUND_CLEAN_CACHE <<
530 help <<
531 This option adds an alternative code <<
532 erratum 819472 on Cortex-A53 parts u <<
533 present when it is connected to a co <<
534 <<
535 If the processor is executing a load <<
536 the same time as a processor in anot <<
537 maintenance operation to the same ad <<
538 cause data corruption. <<
539 <<
540 The workaround promotes data cache c <<
541 data cache clean-and-invalidate. <<
542 Please note that this does not neces <<
543 as it depends on the alternative fra <<
544 the kernel if an affected CPU is det <<
545 1168
546 If unsure, say Y. !! 1169 config HOLES_IN_ZONE
>> 1170 bool
547 1171
548 config ARM64_ERRATUM_832075 !! 1172 config SYS_SUPPORTS_RELOCATABLE
549 bool "Cortex-A57: 832075: possible dea !! 1173 bool
550 default y <<
551 help 1174 help
552 This option adds an alternative code !! 1175 Selected if the platform supports relocating the kernel.
553 erratum 832075 on Cortex-A57 parts u !! 1176 The platform must provide plat_get_fdt() if it selects CONFIG_USE_OF
554 !! 1177 to allow access to command line and entropy sources.
555 Affected Cortex-A57 parts might dead <<
556 instructions to Write-Back memory ar <<
557 1178
558 The workaround is to promote device !! 1179 config MIPS_CBPF_JIT
559 semantics. !! 1180 def_bool y
560 Please note that this does not neces !! 1181 depends on BPF_JIT && HAVE_CBPF_JIT
561 as it depends on the alternative fra <<
562 the kernel if an affected CPU is det <<
563 <<
564 If unsure, say Y. <<
565 1182
566 config ARM64_ERRATUM_834220 !! 1183 config MIPS_EBPF_JIT
567 bool "Cortex-A57: 834220: Stage 2 tran !! 1184 def_bool y
568 depends on KVM !! 1185 depends on BPF_JIT && HAVE_EBPF_JIT
569 help <<
570 This option adds an alternative code <<
571 erratum 834220 on Cortex-A57 parts u <<
572 <<
573 Affected Cortex-A57 parts might repo <<
574 fault as the result of a Stage 1 fau <<
575 page boundary when there is a permis <<
576 alignment fault at Stage 1 and a tra <<
577 <<
578 The workaround is to verify that the <<
579 doesn't generate a fault before hand <<
580 Please note that this does not neces <<
581 as it depends on the alternative fra <<
582 the kernel if an affected CPU is det <<
583 1186
584 If unsure, say N. <<
585 1187
586 config ARM64_ERRATUM_1742098 !! 1188 #
587 bool "Cortex-A57/A72: 1742098: ELR rec !! 1189 # Endianness selection. Sufficiently obscure so many users don't know what to
588 depends on COMPAT !! 1190 # answer,so we try hard to limit the available choices. Also the use of a
589 default y !! 1191 # choice statement should be more obvious to the user.
>> 1192 #
>> 1193 choice
>> 1194 prompt "Endianness selection"
590 help 1195 help
591 This option removes the AES hwcap fo !! 1196 Some MIPS machines can be configured for either little or big endian
592 workaround erratum 1742098 on Cortex !! 1197 byte order. These modes require different kernels and a different
593 !! 1198 Linux distribution. In general there is one preferred byteorder for a
594 Affected parts may corrupt the AES s !! 1199 particular system but some systems are just as commonly used in the
595 taken between a pair of AES instruct !! 1200 one or the other endianness.
596 are only present if the cryptography <<
597 All software should have a fallback <<
598 that don't implement the cryptograph <<
599 <<
600 If unsure, say Y. <<
601 1201
602 config ARM64_ERRATUM_845719 !! 1202 config CPU_BIG_ENDIAN
603 bool "Cortex-A53: 845719: a load might !! 1203 bool "Big endian"
604 depends on COMPAT !! 1204 depends on SYS_SUPPORTS_BIG_ENDIAN
605 default y <<
606 help <<
607 This option adds an alternative code <<
608 erratum 845719 on Cortex-A53 parts u <<
609 <<
610 When running a compat (AArch32) user <<
611 part, a load at EL0 from a virtual a <<
612 bits of the virtual address used by <<
613 might return incorrect data. <<
614 <<
615 The workaround is to write the conte <<
616 return to a 32-bit task. <<
617 Please note that this does not neces <<
618 as it depends on the alternative fra <<
619 the kernel if an affected CPU is det <<
620 <<
621 If unsure, say Y. <<
622 1205
623 config ARM64_ERRATUM_843419 !! 1206 config CPU_LITTLE_ENDIAN
624 bool "Cortex-A53: 843419: A load or st !! 1207 bool "Little endian"
625 default y !! 1208 depends on SYS_SUPPORTS_LITTLE_ENDIAN
626 help <<
627 This option links the kernel with '- <<
628 enables PLT support to replace certa <<
629 cause subsequent memory accesses to <<
630 Cortex-A53 parts up to r0p4. <<
631 1209
632 If unsure, say Y. !! 1210 endchoice
633 1211
634 config ARM64_LD_HAS_FIX_ERRATUM_843419 !! 1212 config EXPORT_UASM
635 def_bool $(ld-option,--fix-cortex-a53- !! 1213 bool
636 1214
637 config ARM64_ERRATUM_1024718 !! 1215 config SYS_SUPPORTS_APM_EMULATION
638 bool "Cortex-A55: 1024718: Update of D !! 1216 bool
639 default y <<
640 help <<
641 This option adds a workaround for AR <<
642 1217
643 Affected Cortex-A55 cores (all revis !! 1218 config SYS_SUPPORTS_BIG_ENDIAN
644 update of the hardware dirty bit whe !! 1219 bool
645 without a break-before-make. The wor <<
646 of hardware DBM locally on the affec <<
647 this erratum will continue to use th <<
648 1220
649 If unsure, say Y. !! 1221 config SYS_SUPPORTS_LITTLE_ENDIAN
>> 1222 bool
650 1223
651 config ARM64_ERRATUM_1418040 !! 1224 config SYS_SUPPORTS_HUGETLBFS
652 bool "Cortex-A76/Neoverse-N1: MRC read !! 1225 bool
>> 1226 depends on CPU_SUPPORTS_HUGEPAGES && 64BIT
653 default y 1227 default y
654 depends on COMPAT <<
655 help <<
656 This option adds a workaround for AR <<
657 errata 1188873 and 1418040. <<
658 1228
659 Affected Cortex-A76/Neoverse-N1 core !! 1229 config MIPS_HUGE_TLB_SUPPORT
660 cause register corruption when acces !! 1230 def_bool HUGETLB_PAGE || TRANSPARENT_HUGEPAGE
661 from AArch32 userspace. <<
662 1231
663 If unsure, say Y. !! 1232 config IRQ_CPU_RM7K
664 <<
665 config ARM64_WORKAROUND_SPECULATIVE_AT <<
666 bool 1233 bool
667 1234
668 config ARM64_ERRATUM_1165522 !! 1235 config IRQ_MSP_SLP
669 bool "Cortex-A76: 1165522: Speculative !! 1236 bool
670 default y <<
671 select ARM64_WORKAROUND_SPECULATIVE_AT <<
672 help <<
673 This option adds a workaround for AR <<
674 1237
675 Affected Cortex-A76 cores (r0p0, r1p !! 1238 config IRQ_MSP_CIC
676 corrupted TLBs by speculating an AT !! 1239 bool
677 context switch. <<
678 1240
679 If unsure, say Y. !! 1241 config IRQ_TXX9
>> 1242 bool
680 1243
681 config ARM64_ERRATUM_1319367 !! 1244 config IRQ_GT641XX
682 bool "Cortex-A57/A72: 1319537: Specula !! 1245 bool
683 default y <<
684 select ARM64_WORKAROUND_SPECULATIVE_AT <<
685 help <<
686 This option adds work arounds for AR <<
687 and A72 erratum 1319367 <<
688 1246
689 Cortex-A57 and A72 cores could end-u !! 1247 config PCI_GT64XXX_PCI0
690 speculating an AT instruction during !! 1248 bool
691 1249
692 If unsure, say Y. !! 1250 config PCI_XTALK_BRIDGE
>> 1251 bool
693 1252
694 config ARM64_ERRATUM_1530923 !! 1253 config NO_EXCEPT_FILL
695 bool "Cortex-A55: 1530923: Speculative !! 1254 bool
696 default y <<
697 select ARM64_WORKAROUND_SPECULATIVE_AT <<
698 help <<
699 This option adds a workaround for AR <<
700 1255
701 Affected Cortex-A55 cores (r0p0, r0p !! 1256 config SOC_EMMA2RH
702 corrupted TLBs by speculating an AT !! 1257 bool
703 context switch. !! 1258 select CEVT_R4K
>> 1259 select CSRC_R4K
>> 1260 select DMA_NONCOHERENT
>> 1261 select IRQ_MIPS_CPU
>> 1262 select SWAP_IO_SPACE
>> 1263 select SYS_HAS_CPU_R5500
>> 1264 select SYS_SUPPORTS_32BIT_KERNEL
>> 1265 select SYS_SUPPORTS_64BIT_KERNEL
>> 1266 select SYS_SUPPORTS_BIG_ENDIAN
704 1267
705 If unsure, say Y. !! 1268 config SOC_PNX833X
>> 1269 bool
>> 1270 select CEVT_R4K
>> 1271 select CSRC_R4K
>> 1272 select IRQ_MIPS_CPU
>> 1273 select DMA_NONCOHERENT
>> 1274 select SYS_HAS_CPU_MIPS32_R2
>> 1275 select SYS_SUPPORTS_32BIT_KERNEL
>> 1276 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 1277 select SYS_SUPPORTS_BIG_ENDIAN
>> 1278 select SYS_SUPPORTS_MIPS16
>> 1279 select CPU_MIPSR2_IRQ_VI
706 1280
707 config ARM64_WORKAROUND_REPEAT_TLBI !! 1281 config SOC_PNX8335
708 bool 1282 bool
>> 1283 select SOC_PNX833X
709 1284
710 config ARM64_ERRATUM_2441007 !! 1285 config MIPS_SPRAM
711 bool "Cortex-A55: Completion of affect !! 1286 bool
712 select ARM64_WORKAROUND_REPEAT_TLBI <<
713 help <<
714 This option adds a workaround for AR <<
715 1287
716 Under very rare circumstances, affec !! 1288 config SWAP_IO_SPACE
717 may not handle a race between a brea !! 1289 bool
718 CPU, and another CPU accessing the s <<
719 store to a page that has been unmapp <<
720 1290
721 Work around this by adding the affec !! 1291 config SGI_HAS_INDYDOG
722 TLB sequences to be done twice. !! 1292 bool
723 1293
724 If unsure, say N. !! 1294 config SGI_HAS_HAL2
>> 1295 bool
725 1296
726 config ARM64_ERRATUM_1286807 !! 1297 config SGI_HAS_SEEQ
727 bool "Cortex-A76: Modification of the !! 1298 bool
728 select ARM64_WORKAROUND_REPEAT_TLBI <<
729 help <<
730 This option adds a workaround for AR <<
731 <<
732 On the affected Cortex-A76 cores (r0 <<
733 address for a cacheable mapping of a <<
734 accessed by a core while another cor <<
735 address to a new physical page using <<
736 break-before-make sequence, then und <<
737 TLBI+DSB completes before a read usi <<
738 invalidated has been observed by oth <<
739 workaround repeats the TLBI+DSB oper <<
740 1299
741 If unsure, say N. !! 1300 config SGI_HAS_WD93
>> 1301 bool
742 1302
743 config ARM64_ERRATUM_1463225 !! 1303 config SGI_HAS_ZILOG
744 bool "Cortex-A76: Software Step might !! 1304 bool
745 default y <<
746 help <<
747 This option adds a workaround for Ar <<
748 1305
749 On the affected Cortex-A76 cores (r0 !! 1306 config SGI_HAS_I8042
750 of a system call instruction (SVC) c !! 1307 bool
751 subsequent interrupts when software <<
752 exception handler of the system call <<
753 is enabled or VHE is in use. <<
754 1308
755 Work around the erratum by triggerin !! 1309 config DEFAULT_SGI_PARTITION
756 when handling a system call from a t !! 1310 bool
757 in a VHE configuration of the kernel <<
758 1311
759 If unsure, say Y. !! 1312 config FW_ARC32
>> 1313 bool
760 1314
761 config ARM64_ERRATUM_1542419 !! 1315 config FW_SNIPROM
762 bool "Neoverse-N1: workaround mis-orde !! 1316 bool
763 help <<
764 This option adds a workaround for AR <<
765 1542419. <<
766 1317
767 Affected Neoverse-N1 cores could exe !! 1318 config BOOT_ELF32
768 modified by another CPU. The workaro !! 1319 bool
769 counterpart. <<
770 1320
771 Workaround the issue by hiding the D !! 1321 config MIPS_L1_CACHE_SHIFT_4
772 forces user-space to perform cache m !! 1322 bool
773 1323
774 If unsure, say N. !! 1324 config MIPS_L1_CACHE_SHIFT_5
>> 1325 bool
775 1326
776 config ARM64_ERRATUM_1508412 !! 1327 config MIPS_L1_CACHE_SHIFT_6
777 bool "Cortex-A77: 1508412: workaround !! 1328 bool
778 default y <<
779 help <<
780 This option adds a workaround for Ar <<
781 1329
782 Affected Cortex-A77 cores (r0p0, r1p !! 1330 config MIPS_L1_CACHE_SHIFT_7
783 of a store-exclusive or read of PAR_ !! 1331 bool
784 non-cacheable memory attributes. The <<
785 counterpart. <<
786 1332
787 KVM guests must also have the workar !! 1333 config MIPS_L1_CACHE_SHIFT
788 deadlock the system. !! 1334 int
>> 1335 default "7" if MIPS_L1_CACHE_SHIFT_7
>> 1336 default "6" if MIPS_L1_CACHE_SHIFT_6
>> 1337 default "5" if MIPS_L1_CACHE_SHIFT_5
>> 1338 default "4" if MIPS_L1_CACHE_SHIFT_4
>> 1339 default "5"
789 1340
790 Work around the issue by inserting D !! 1341 config HAVE_STD_PC_SERIAL_PORT
791 register reads and warning KVM users !! 1342 bool
792 to prevent a speculative PAR_EL1 rea <<
793 1343
794 If unsure, say Y. !! 1344 config ARC_CONSOLE
>> 1345 bool "ARC console support"
>> 1346 depends on SGI_IP22 || SGI_IP28 || (SNI_RM && CPU_LITTLE_ENDIAN)
795 1347
796 config ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MO !! 1348 config ARC_MEMORY
797 bool 1349 bool
798 !! 1350 depends on MACH_JAZZ || SNI_RM || SGI_IP32
799 config ARM64_ERRATUM_2051678 <<
800 bool "Cortex-A510: 2051678: disable Ha <<
801 default y 1351 default y
802 help <<
803 This options adds the workaround for <<
804 Affected Cortex-A510 might not respe <<
805 hardware update of the page table's <<
806 is to not enable the feature on affe <<
807 1352
808 If unsure, say Y. !! 1353 config ARC_PROMLIB
809 !! 1354 bool
810 config ARM64_ERRATUM_2077057 !! 1355 depends on MACH_JAZZ || SNI_RM || SGI_IP22 || SGI_IP28 || SGI_IP32
811 bool "Cortex-A510: 2077057: workaround <<
812 default y 1356 default y
813 help <<
814 This option adds the workaround for <<
815 Affected Cortex-A510 may corrupt SPS <<
816 expected, but a Pointer Authenticati <<
817 erratum causes SPSR_EL1 to be copied <<
818 EL1 to cause a return to EL2 with a <<
819 1357
820 This can only happen when EL2 is ste !! 1358 config FW_ARC64
>> 1359 bool
821 1360
822 When these conditions occur, the SPS !! 1361 config BOOT_ELF64
823 previous guest entry, and can be res !! 1362 bool
824 1363
825 If unsure, say Y. !! 1364 menu "CPU selection"
826 1365
827 config ARM64_ERRATUM_2658417 !! 1366 choice
828 bool "Cortex-A510: 2658417: remove BF1 !! 1367 prompt "CPU type"
829 default y !! 1368 default CPU_R4X00
830 help <<
831 This option adds the workaround for <<
832 Affected Cortex-A510 (r0p0 to r1p1) <<
833 BFMMLA or VMMLA instructions in rare <<
834 A510 CPUs are using shared neon hard <<
835 discoverable by the kernel, hide the <<
836 user-space should not be using these <<
837 1369
838 If unsure, say Y. !! 1370 config CPU_LOONGSON3
>> 1371 bool "Loongson 3 CPU"
>> 1372 depends on SYS_HAS_CPU_LOONGSON3
>> 1373 select ARCH_HAS_PHYS_TO_DMA
>> 1374 select CPU_SUPPORTS_64BIT_KERNEL
>> 1375 select CPU_SUPPORTS_HIGHMEM
>> 1376 select CPU_SUPPORTS_HUGEPAGES
>> 1377 select CPU_HAS_LOAD_STORE_LR
>> 1378 select WEAK_ORDERING
>> 1379 select WEAK_REORDERING_BEYOND_LLSC
>> 1380 select MIPS_PGD_C0_CONTEXT
>> 1381 select MIPS_L1_CACHE_SHIFT_6
>> 1382 select GPIOLIB
>> 1383 select SWIOTLB
>> 1384 help
>> 1385 The Loongson 3 processor implements the MIPS64R2 instruction
>> 1386 set with many extensions.
839 1387
840 config ARM64_ERRATUM_2119858 !! 1388 config LOONGSON3_ENHANCEMENT
841 bool "Cortex-A710/X2: 2119858: workaro !! 1389 bool "New Loongson 3 CPU Enhancements"
842 default y !! 1390 default n
843 depends on CORESIGHT_TRBE !! 1391 select CPU_MIPSR2
844 select ARM64_WORKAROUND_TRBE_OVERWRITE !! 1392 select CPU_HAS_PREFETCH
>> 1393 depends on CPU_LOONGSON3
>> 1394 help
>> 1395 New Loongson 3 CPU (since Loongson-3A R2, as opposed to Loongson-3A
>> 1396 R1, Loongson-3B R1 and Loongson-3B R2) has many enhancements, such as
>> 1397 FTLB, L1-VCache, EI/DI/Wait/Prefetch instruction, DSP/DSPv2 ASE, User
>> 1398 Local register, Read-Inhibit/Execute-Inhibit, SFB (Store Fill Buffer),
>> 1399 Fast TLB refill support, etc.
>> 1400
>> 1401 This option enable those enhancements which are not probed at run
>> 1402 time. If you want a generic kernel to run on all Loongson 3 machines,
>> 1403 please say 'N' here. If you want a high-performance kernel to run on
>> 1404 new Loongson 3 machines only, please say 'Y' here.
>> 1405
>> 1406 config CPU_LOONGSON3_WORKAROUNDS
>> 1407 bool "Old Loongson 3 LLSC Workarounds"
>> 1408 default y if SMP
>> 1409 depends on CPU_LOONGSON3
>> 1410 help
>> 1411 Loongson 3 processors have the llsc issues which require workarounds.
>> 1412 Without workarounds the system may hang unexpectedly.
>> 1413
>> 1414 Newer Loongson 3 will fix these issues and no workarounds are needed.
>> 1415 The workarounds have no significant side effect on them but may
>> 1416 decrease the performance of the system so this option should be
>> 1417 disabled unless the kernel is intended to be run on old systems.
>> 1418
>> 1419 If unsure, please say Y.
>> 1420
>> 1421 config CPU_LOONGSON2E
>> 1422 bool "Loongson 2E"
>> 1423 depends on SYS_HAS_CPU_LOONGSON2E
>> 1424 select CPU_LOONGSON2
>> 1425 help
>> 1426 The Loongson 2E processor implements the MIPS III instruction set
>> 1427 with many extensions.
>> 1428
>> 1429 It has an internal FPGA northbridge, which is compatible to
>> 1430 bonito64.
>> 1431
>> 1432 config CPU_LOONGSON2F
>> 1433 bool "Loongson 2F"
>> 1434 depends on SYS_HAS_CPU_LOONGSON2F
>> 1435 select CPU_LOONGSON2
>> 1436 select GPIOLIB
>> 1437 help
>> 1438 The Loongson 2F processor implements the MIPS III instruction set
>> 1439 with many extensions.
>> 1440
>> 1441 Loongson2F have built-in DDR2 and PCIX controller. The PCIX controller
>> 1442 have a similar programming interface with FPGA northbridge used in
>> 1443 Loongson2E.
>> 1444
>> 1445 config CPU_LOONGSON1B
>> 1446 bool "Loongson 1B"
>> 1447 depends on SYS_HAS_CPU_LOONGSON1B
>> 1448 select CPU_LOONGSON1
>> 1449 select LEDS_GPIO_REGISTER
>> 1450 help
>> 1451 The Loongson 1B is a 32-bit SoC, which implements the MIPS32
>> 1452 Release 1 instruction set and part of the MIPS32 Release 2
>> 1453 instruction set.
>> 1454
>> 1455 config CPU_LOONGSON1C
>> 1456 bool "Loongson 1C"
>> 1457 depends on SYS_HAS_CPU_LOONGSON1C
>> 1458 select CPU_LOONGSON1
>> 1459 select LEDS_GPIO_REGISTER
>> 1460 help
>> 1461 The Loongson 1C is a 32-bit SoC, which implements the MIPS32
>> 1462 Release 1 instruction set and part of the MIPS32 Release 2
>> 1463 instruction set.
>> 1464
>> 1465 config CPU_MIPS32_R1
>> 1466 bool "MIPS32 Release 1"
>> 1467 depends on SYS_HAS_CPU_MIPS32_R1
>> 1468 select CPU_HAS_PREFETCH
>> 1469 select CPU_HAS_LOAD_STORE_LR
>> 1470 select CPU_SUPPORTS_32BIT_KERNEL
>> 1471 select CPU_SUPPORTS_HIGHMEM
>> 1472 help
>> 1473 Choose this option to build a kernel for release 1 or later of the
>> 1474 MIPS32 architecture. Most modern embedded systems with a 32-bit
>> 1475 MIPS processor are based on a MIPS32 processor. If you know the
>> 1476 specific type of processor in your system, choose those that one
>> 1477 otherwise CPU_MIPS32_R1 is a safe bet for any MIPS32 system.
>> 1478 Release 2 of the MIPS32 architecture is available since several
>> 1479 years so chances are you even have a MIPS32 Release 2 processor
>> 1480 in which case you should choose CPU_MIPS32_R2 instead for better
>> 1481 performance.
>> 1482
>> 1483 config CPU_MIPS32_R2
>> 1484 bool "MIPS32 Release 2"
>> 1485 depends on SYS_HAS_CPU_MIPS32_R2
>> 1486 select CPU_HAS_PREFETCH
>> 1487 select CPU_HAS_LOAD_STORE_LR
>> 1488 select CPU_SUPPORTS_32BIT_KERNEL
>> 1489 select CPU_SUPPORTS_HIGHMEM
>> 1490 select CPU_SUPPORTS_MSA
>> 1491 select HAVE_KVM
>> 1492 help
>> 1493 Choose this option to build a kernel for release 2 or later of the
>> 1494 MIPS32 architecture. Most modern embedded systems with a 32-bit
>> 1495 MIPS processor are based on a MIPS32 processor. If you know the
>> 1496 specific type of processor in your system, choose those that one
>> 1497 otherwise CPU_MIPS32_R1 is a safe bet for any MIPS32 system.
>> 1498
>> 1499 config CPU_MIPS32_R6
>> 1500 bool "MIPS32 Release 6"
>> 1501 depends on SYS_HAS_CPU_MIPS32_R6
>> 1502 select CPU_HAS_PREFETCH
>> 1503 select CPU_SUPPORTS_32BIT_KERNEL
>> 1504 select CPU_SUPPORTS_HIGHMEM
>> 1505 select CPU_SUPPORTS_MSA
>> 1506 select HAVE_KVM
>> 1507 select MIPS_O32_FP64_SUPPORT
>> 1508 help
>> 1509 Choose this option to build a kernel for release 6 or later of the
>> 1510 MIPS32 architecture. New MIPS processors, starting with the Warrior
>> 1511 family, are based on a MIPS32r6 processor. If you own an older
>> 1512 processor, you probably need to select MIPS32r1 or MIPS32r2 instead.
>> 1513
>> 1514 config CPU_MIPS64_R1
>> 1515 bool "MIPS64 Release 1"
>> 1516 depends on SYS_HAS_CPU_MIPS64_R1
>> 1517 select CPU_HAS_PREFETCH
>> 1518 select CPU_HAS_LOAD_STORE_LR
>> 1519 select CPU_SUPPORTS_32BIT_KERNEL
>> 1520 select CPU_SUPPORTS_64BIT_KERNEL
>> 1521 select CPU_SUPPORTS_HIGHMEM
>> 1522 select CPU_SUPPORTS_HUGEPAGES
>> 1523 help
>> 1524 Choose this option to build a kernel for release 1 or later of the
>> 1525 MIPS64 architecture. Many modern embedded systems with a 64-bit
>> 1526 MIPS processor are based on a MIPS64 processor. If you know the
>> 1527 specific type of processor in your system, choose those that one
>> 1528 otherwise CPU_MIPS64_R1 is a safe bet for any MIPS64 system.
>> 1529 Release 2 of the MIPS64 architecture is available since several
>> 1530 years so chances are you even have a MIPS64 Release 2 processor
>> 1531 in which case you should choose CPU_MIPS64_R2 instead for better
>> 1532 performance.
>> 1533
>> 1534 config CPU_MIPS64_R2
>> 1535 bool "MIPS64 Release 2"
>> 1536 depends on SYS_HAS_CPU_MIPS64_R2
>> 1537 select CPU_HAS_PREFETCH
>> 1538 select CPU_HAS_LOAD_STORE_LR
>> 1539 select CPU_SUPPORTS_32BIT_KERNEL
>> 1540 select CPU_SUPPORTS_64BIT_KERNEL
>> 1541 select CPU_SUPPORTS_HIGHMEM
>> 1542 select CPU_SUPPORTS_HUGEPAGES
>> 1543 select CPU_SUPPORTS_MSA
>> 1544 select HAVE_KVM
>> 1545 help
>> 1546 Choose this option to build a kernel for release 2 or later of the
>> 1547 MIPS64 architecture. Many modern embedded systems with a 64-bit
>> 1548 MIPS processor are based on a MIPS64 processor. If you know the
>> 1549 specific type of processor in your system, choose those that one
>> 1550 otherwise CPU_MIPS64_R1 is a safe bet for any MIPS64 system.
>> 1551
>> 1552 config CPU_MIPS64_R6
>> 1553 bool "MIPS64 Release 6"
>> 1554 depends on SYS_HAS_CPU_MIPS64_R6
>> 1555 select CPU_HAS_PREFETCH
>> 1556 select CPU_SUPPORTS_32BIT_KERNEL
>> 1557 select CPU_SUPPORTS_64BIT_KERNEL
>> 1558 select CPU_SUPPORTS_HIGHMEM
>> 1559 select CPU_SUPPORTS_HUGEPAGES
>> 1560 select CPU_SUPPORTS_MSA
>> 1561 select MIPS_O32_FP64_SUPPORT if 32BIT || MIPS32_O32
>> 1562 select HAVE_KVM
>> 1563 help
>> 1564 Choose this option to build a kernel for release 6 or later of the
>> 1565 MIPS64 architecture. New MIPS processors, starting with the Warrior
>> 1566 family, are based on a MIPS64r6 processor. If you own an older
>> 1567 processor, you probably need to select MIPS64r1 or MIPS64r2 instead.
>> 1568
>> 1569 config CPU_R3000
>> 1570 bool "R3000"
>> 1571 depends on SYS_HAS_CPU_R3000
>> 1572 select CPU_HAS_WB
>> 1573 select CPU_HAS_LOAD_STORE_LR
>> 1574 select CPU_SUPPORTS_32BIT_KERNEL
>> 1575 select CPU_SUPPORTS_HIGHMEM
>> 1576 help
>> 1577 Please make sure to pick the right CPU type. Linux/MIPS is not
>> 1578 designed to be generic, i.e. Kernels compiled for R3000 CPUs will
>> 1579 *not* work on R4000 machines and vice versa. However, since most
>> 1580 of the supported machines have an R4000 (or similar) CPU, R4x00
>> 1581 might be a safe bet. If the resulting kernel does not work,
>> 1582 try to recompile with R3000.
>> 1583
>> 1584 config CPU_TX39XX
>> 1585 bool "R39XX"
>> 1586 depends on SYS_HAS_CPU_TX39XX
>> 1587 select CPU_SUPPORTS_32BIT_KERNEL
>> 1588 select CPU_HAS_LOAD_STORE_LR
>> 1589
>> 1590 config CPU_VR41XX
>> 1591 bool "R41xx"
>> 1592 depends on SYS_HAS_CPU_VR41XX
>> 1593 select CPU_SUPPORTS_32BIT_KERNEL
>> 1594 select CPU_SUPPORTS_64BIT_KERNEL
>> 1595 select CPU_HAS_LOAD_STORE_LR
>> 1596 help
>> 1597 The options selects support for the NEC VR4100 series of processors.
>> 1598 Only choose this option if you have one of these processors as a
>> 1599 kernel built with this option will not run on any other type of
>> 1600 processor or vice versa.
>> 1601
>> 1602 config CPU_R4300
>> 1603 bool "R4300"
>> 1604 depends on SYS_HAS_CPU_R4300
>> 1605 select CPU_SUPPORTS_32BIT_KERNEL
>> 1606 select CPU_SUPPORTS_64BIT_KERNEL
>> 1607 select CPU_HAS_LOAD_STORE_LR
>> 1608 help
>> 1609 MIPS Technologies R4300-series processors.
>> 1610
>> 1611 config CPU_R4X00
>> 1612 bool "R4x00"
>> 1613 depends on SYS_HAS_CPU_R4X00
>> 1614 select CPU_SUPPORTS_32BIT_KERNEL
>> 1615 select CPU_SUPPORTS_64BIT_KERNEL
>> 1616 select CPU_SUPPORTS_HUGEPAGES
>> 1617 select CPU_HAS_LOAD_STORE_LR
>> 1618 help
>> 1619 MIPS Technologies R4000-series processors other than 4300, including
>> 1620 the R4000, R4400, R4600, and 4700.
>> 1621
>> 1622 config CPU_TX49XX
>> 1623 bool "R49XX"
>> 1624 depends on SYS_HAS_CPU_TX49XX
>> 1625 select CPU_HAS_PREFETCH
>> 1626 select CPU_HAS_LOAD_STORE_LR
>> 1627 select CPU_SUPPORTS_32BIT_KERNEL
>> 1628 select CPU_SUPPORTS_64BIT_KERNEL
>> 1629 select CPU_SUPPORTS_HUGEPAGES
>> 1630
>> 1631 config CPU_R5000
>> 1632 bool "R5000"
>> 1633 depends on SYS_HAS_CPU_R5000
>> 1634 select CPU_SUPPORTS_32BIT_KERNEL
>> 1635 select CPU_SUPPORTS_64BIT_KERNEL
>> 1636 select CPU_SUPPORTS_HUGEPAGES
>> 1637 select CPU_HAS_LOAD_STORE_LR
>> 1638 help
>> 1639 MIPS Technologies R5000-series processors other than the Nevada.
>> 1640
>> 1641 config CPU_R5432
>> 1642 bool "R5432"
>> 1643 depends on SYS_HAS_CPU_R5432
>> 1644 select CPU_SUPPORTS_32BIT_KERNEL
>> 1645 select CPU_SUPPORTS_64BIT_KERNEL
>> 1646 select CPU_SUPPORTS_HUGEPAGES
>> 1647 select CPU_HAS_LOAD_STORE_LR
>> 1648
>> 1649 config CPU_R5500
>> 1650 bool "R5500"
>> 1651 depends on SYS_HAS_CPU_R5500
>> 1652 select CPU_SUPPORTS_32BIT_KERNEL
>> 1653 select CPU_SUPPORTS_64BIT_KERNEL
>> 1654 select CPU_SUPPORTS_HUGEPAGES
>> 1655 select CPU_HAS_LOAD_STORE_LR
>> 1656 help
>> 1657 NEC VR5500 and VR5500A series processors implement 64-bit MIPS IV
>> 1658 instruction set.
>> 1659
>> 1660 config CPU_NEVADA
>> 1661 bool "RM52xx"
>> 1662 depends on SYS_HAS_CPU_NEVADA
>> 1663 select CPU_SUPPORTS_32BIT_KERNEL
>> 1664 select CPU_SUPPORTS_64BIT_KERNEL
>> 1665 select CPU_SUPPORTS_HUGEPAGES
>> 1666 select CPU_HAS_LOAD_STORE_LR
>> 1667 help
>> 1668 QED / PMC-Sierra RM52xx-series ("Nevada") processors.
>> 1669
>> 1670 config CPU_R8000
>> 1671 bool "R8000"
>> 1672 depends on SYS_HAS_CPU_R8000
>> 1673 select CPU_HAS_PREFETCH
>> 1674 select CPU_HAS_LOAD_STORE_LR
>> 1675 select CPU_SUPPORTS_64BIT_KERNEL
>> 1676 help
>> 1677 MIPS Technologies R8000 processors. Note these processors are
>> 1678 uncommon and the support for them is incomplete.
>> 1679
>> 1680 config CPU_R10000
>> 1681 bool "R10000"
>> 1682 depends on SYS_HAS_CPU_R10000
>> 1683 select CPU_HAS_PREFETCH
>> 1684 select CPU_HAS_LOAD_STORE_LR
>> 1685 select CPU_SUPPORTS_32BIT_KERNEL
>> 1686 select CPU_SUPPORTS_64BIT_KERNEL
>> 1687 select CPU_SUPPORTS_HIGHMEM
>> 1688 select CPU_SUPPORTS_HUGEPAGES
>> 1689 help
>> 1690 MIPS Technologies R10000-series processors.
>> 1691
>> 1692 config CPU_RM7000
>> 1693 bool "RM7000"
>> 1694 depends on SYS_HAS_CPU_RM7000
>> 1695 select CPU_HAS_PREFETCH
>> 1696 select CPU_HAS_LOAD_STORE_LR
>> 1697 select CPU_SUPPORTS_32BIT_KERNEL
>> 1698 select CPU_SUPPORTS_64BIT_KERNEL
>> 1699 select CPU_SUPPORTS_HIGHMEM
>> 1700 select CPU_SUPPORTS_HUGEPAGES
>> 1701
>> 1702 config CPU_SB1
>> 1703 bool "SB1"
>> 1704 depends on SYS_HAS_CPU_SB1
>> 1705 select CPU_HAS_LOAD_STORE_LR
>> 1706 select CPU_SUPPORTS_32BIT_KERNEL
>> 1707 select CPU_SUPPORTS_64BIT_KERNEL
>> 1708 select CPU_SUPPORTS_HIGHMEM
>> 1709 select CPU_SUPPORTS_HUGEPAGES
>> 1710 select WEAK_ORDERING
>> 1711
>> 1712 config CPU_CAVIUM_OCTEON
>> 1713 bool "Cavium Octeon processor"
>> 1714 depends on SYS_HAS_CPU_CAVIUM_OCTEON
>> 1715 select CPU_HAS_PREFETCH
>> 1716 select CPU_HAS_LOAD_STORE_LR
>> 1717 select CPU_SUPPORTS_64BIT_KERNEL
>> 1718 select WEAK_ORDERING
>> 1719 select CPU_SUPPORTS_HIGHMEM
>> 1720 select CPU_SUPPORTS_HUGEPAGES
>> 1721 select USB_EHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 1722 select USB_OHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 1723 select MIPS_L1_CACHE_SHIFT_7
>> 1724 select HAVE_KVM
>> 1725 help
>> 1726 The Cavium Octeon processor is a highly integrated chip containing
>> 1727 many ethernet hardware widgets for networking tasks. The processor
>> 1728 can have up to 16 Mips64v2 cores and 8 integrated gigabit ethernets.
>> 1729 Full details can be found at http://www.caviumnetworks.com.
>> 1730
>> 1731 config CPU_BMIPS
>> 1732 bool "Broadcom BMIPS"
>> 1733 depends on SYS_HAS_CPU_BMIPS
>> 1734 select CPU_MIPS32
>> 1735 select CPU_BMIPS32_3300 if SYS_HAS_CPU_BMIPS32_3300
>> 1736 select CPU_BMIPS4350 if SYS_HAS_CPU_BMIPS4350
>> 1737 select CPU_BMIPS4380 if SYS_HAS_CPU_BMIPS4380
>> 1738 select CPU_BMIPS5000 if SYS_HAS_CPU_BMIPS5000
>> 1739 select CPU_SUPPORTS_32BIT_KERNEL
>> 1740 select DMA_NONCOHERENT
>> 1741 select IRQ_MIPS_CPU
>> 1742 select SWAP_IO_SPACE
>> 1743 select WEAK_ORDERING
>> 1744 select CPU_SUPPORTS_HIGHMEM
>> 1745 select CPU_HAS_PREFETCH
>> 1746 select CPU_HAS_LOAD_STORE_LR
>> 1747 select CPU_SUPPORTS_CPUFREQ
>> 1748 select MIPS_EXTERNAL_TIMER
>> 1749 help
>> 1750 Support for BMIPS32/3300/4350/4380 and BMIPS5000 processors.
>> 1751
>> 1752 config CPU_XLR
>> 1753 bool "Netlogic XLR SoC"
>> 1754 depends on SYS_HAS_CPU_XLR
>> 1755 select CPU_HAS_LOAD_STORE_LR
>> 1756 select CPU_SUPPORTS_32BIT_KERNEL
>> 1757 select CPU_SUPPORTS_64BIT_KERNEL
>> 1758 select CPU_SUPPORTS_HIGHMEM
>> 1759 select CPU_SUPPORTS_HUGEPAGES
>> 1760 select WEAK_ORDERING
>> 1761 select WEAK_REORDERING_BEYOND_LLSC
>> 1762 help
>> 1763 Netlogic Microsystems XLR/XLS processors.
>> 1764
>> 1765 config CPU_XLP
>> 1766 bool "Netlogic XLP SoC"
>> 1767 depends on SYS_HAS_CPU_XLP
>> 1768 select CPU_SUPPORTS_32BIT_KERNEL
>> 1769 select CPU_SUPPORTS_64BIT_KERNEL
>> 1770 select CPU_SUPPORTS_HIGHMEM
>> 1771 select WEAK_ORDERING
>> 1772 select WEAK_REORDERING_BEYOND_LLSC
>> 1773 select CPU_HAS_PREFETCH
>> 1774 select CPU_HAS_LOAD_STORE_LR
>> 1775 select CPU_MIPSR2
>> 1776 select CPU_SUPPORTS_HUGEPAGES
>> 1777 select MIPS_ASID_BITS_VARIABLE
845 help 1778 help
846 This option adds the workaround for !! 1779 Netlogic Microsystems XLP processors.
>> 1780 endchoice
847 1781
848 Affected Cortex-A710/X2 cores could !! 1782 config CPU_MIPS32_3_5_FEATURES
849 data at the base of the buffer (poin !! 1783 bool "MIPS32 Release 3.5 Features"
850 the event of a WRAP event. !! 1784 depends on SYS_HAS_CPU_MIPS32_R3_5
>> 1785 depends on CPU_MIPS32_R2 || CPU_MIPS32_R6
>> 1786 help
>> 1787 Choose this option to build a kernel for release 2 or later of the
>> 1788 MIPS32 architecture including features from the 3.5 release such as
>> 1789 support for Enhanced Virtual Addressing (EVA).
>> 1790
>> 1791 config CPU_MIPS32_3_5_EVA
>> 1792 bool "Enhanced Virtual Addressing (EVA)"
>> 1793 depends on CPU_MIPS32_3_5_FEATURES
>> 1794 select EVA
>> 1795 default y
>> 1796 help
>> 1797 Choose this option if you want to enable the Enhanced Virtual
>> 1798 Addressing (EVA) on your MIPS32 core (such as proAptiv).
>> 1799 One of its primary benefits is an increase in the maximum size
>> 1800 of lowmem (up to 3GB). If unsure, say 'N' here.
>> 1801
>> 1802 config CPU_MIPS32_R5_FEATURES
>> 1803 bool "MIPS32 Release 5 Features"
>> 1804 depends on SYS_HAS_CPU_MIPS32_R5
>> 1805 depends on CPU_MIPS32_R2
>> 1806 help
>> 1807 Choose this option to build a kernel for release 2 or later of the
>> 1808 MIPS32 architecture including features from release 5 such as
>> 1809 support for Extended Physical Addressing (XPA).
>> 1810
>> 1811 config CPU_MIPS32_R5_XPA
>> 1812 bool "Extended Physical Addressing (XPA)"
>> 1813 depends on CPU_MIPS32_R5_FEATURES
>> 1814 depends on !EVA
>> 1815 depends on !PAGE_SIZE_4KB
>> 1816 depends on SYS_SUPPORTS_HIGHMEM
>> 1817 select XPA
>> 1818 select HIGHMEM
>> 1819 select PHYS_ADDR_T_64BIT
>> 1820 default n
>> 1821 help
>> 1822 Choose this option if you want to enable the Extended Physical
>> 1823 Addressing (XPA) on your MIPS32 core (such as P5600 series). The
>> 1824 benefit is to increase physical addressing equal to or greater
>> 1825 than 40 bits. Note that this has the side effect of turning on
>> 1826 64-bit addressing which in turn makes the PTEs 64-bit in size.
>> 1827 If unsure, say 'N' here.
851 1828
852 Work around the issue by always maki !! 1829 if CPU_LOONGSON2F
853 256 bytes before enabling the buffer !! 1830 config CPU_NOP_WORKAROUNDS
854 the buffer with ETM ignore packets u !! 1831 bool
855 1832
856 If unsure, say Y. !! 1833 config CPU_JUMP_WORKAROUNDS
>> 1834 bool
857 1835
858 config ARM64_ERRATUM_2139208 !! 1836 config CPU_LOONGSON2F_WORKAROUNDS
859 bool "Neoverse-N2: 2139208: workaround !! 1837 bool "Loongson 2F Workarounds"
860 default y 1838 default y
861 depends on CORESIGHT_TRBE !! 1839 select CPU_NOP_WORKAROUNDS
862 select ARM64_WORKAROUND_TRBE_OVERWRITE !! 1840 select CPU_JUMP_WORKAROUNDS
863 help 1841 help
864 This option adds the workaround for !! 1842 Loongson 2F01 / 2F02 processors have the NOP & JUMP issues which
>> 1843 require workarounds. Without workarounds the system may hang
>> 1844 unexpectedly. For more information please refer to the gas
>> 1845 -mfix-loongson2f-nop and -mfix-loongson2f-jump options.
>> 1846
>> 1847 Loongson 2F03 and later have fixed these issues and no workarounds
>> 1848 are needed. The workarounds have no significant side effect on them
>> 1849 but may decrease the performance of the system so this option should
>> 1850 be disabled unless the kernel is intended to be run on 2F01 or 2F02
>> 1851 systems.
865 1852
866 Affected Neoverse-N2 cores could ove !! 1853 If unsure, please say Y.
867 data at the base of the buffer (poin !! 1854 endif # CPU_LOONGSON2F
868 the event of a WRAP event. <<
869 <<
870 Work around the issue by always maki <<
871 256 bytes before enabling the buffer <<
872 the buffer with ETM ignore packets u <<
873 <<
874 If unsure, say Y. <<
875 1855
876 config ARM64_WORKAROUND_TSB_FLUSH_FAILURE !! 1856 config SYS_SUPPORTS_ZBOOT
877 bool 1857 bool
>> 1858 select HAVE_KERNEL_GZIP
>> 1859 select HAVE_KERNEL_BZIP2
>> 1860 select HAVE_KERNEL_LZ4
>> 1861 select HAVE_KERNEL_LZMA
>> 1862 select HAVE_KERNEL_LZO
>> 1863 select HAVE_KERNEL_XZ
878 1864
879 config ARM64_ERRATUM_2054223 !! 1865 config SYS_SUPPORTS_ZBOOT_UART16550
880 bool "Cortex-A710: 2054223: workaround !! 1866 bool
881 default y !! 1867 select SYS_SUPPORTS_ZBOOT
882 select ARM64_WORKAROUND_TSB_FLUSH_FAIL <<
883 help <<
884 Enable workaround for ARM Cortex-A71 <<
885 1868
886 Affected cores may fail to flush the !! 1869 config SYS_SUPPORTS_ZBOOT_UART_PROM
887 the PE is in trace prohibited state. !! 1870 bool
888 of the trace cached. !! 1871 select SYS_SUPPORTS_ZBOOT
889 1872
890 Workaround is to issue two TSB conse !! 1873 config CPU_LOONGSON2
>> 1874 bool
>> 1875 select CPU_SUPPORTS_32BIT_KERNEL
>> 1876 select CPU_SUPPORTS_64BIT_KERNEL
>> 1877 select CPU_SUPPORTS_HIGHMEM
>> 1878 select CPU_SUPPORTS_HUGEPAGES
>> 1879 select ARCH_HAS_PHYS_TO_DMA
>> 1880 select CPU_HAS_LOAD_STORE_LR
891 1881
892 If unsure, say Y. !! 1882 config CPU_LOONGSON1
>> 1883 bool
>> 1884 select CPU_MIPS32
>> 1885 select CPU_MIPSR2
>> 1886 select CPU_HAS_PREFETCH
>> 1887 select CPU_HAS_LOAD_STORE_LR
>> 1888 select CPU_SUPPORTS_32BIT_KERNEL
>> 1889 select CPU_SUPPORTS_HIGHMEM
>> 1890 select CPU_SUPPORTS_CPUFREQ
893 1891
894 config ARM64_ERRATUM_2067961 !! 1892 config CPU_BMIPS32_3300
895 bool "Neoverse-N2: 2067961: workaround !! 1893 select SMP_UP if SMP
896 default y !! 1894 bool
897 select ARM64_WORKAROUND_TSB_FLUSH_FAIL <<
898 help <<
899 Enable workaround for ARM Neoverse-N <<
900 1895
901 Affected cores may fail to flush the !! 1896 config CPU_BMIPS4350
902 the PE is in trace prohibited state. !! 1897 bool
903 of the trace cached. !! 1898 select SYS_SUPPORTS_SMP
>> 1899 select SYS_SUPPORTS_HOTPLUG_CPU
904 1900
905 Workaround is to issue two TSB conse !! 1901 config CPU_BMIPS4380
>> 1902 bool
>> 1903 select MIPS_L1_CACHE_SHIFT_6
>> 1904 select SYS_SUPPORTS_SMP
>> 1905 select SYS_SUPPORTS_HOTPLUG_CPU
>> 1906 select CPU_HAS_RIXI
906 1907
907 If unsure, say Y. !! 1908 config CPU_BMIPS5000
>> 1909 bool
>> 1910 select MIPS_CPU_SCACHE
>> 1911 select MIPS_L1_CACHE_SHIFT_7
>> 1912 select SYS_SUPPORTS_SMP
>> 1913 select SYS_SUPPORTS_HOTPLUG_CPU
>> 1914 select CPU_HAS_RIXI
908 1915
909 config ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANG !! 1916 config SYS_HAS_CPU_LOONGSON3
910 bool 1917 bool
>> 1918 select CPU_SUPPORTS_CPUFREQ
>> 1919 select CPU_HAS_RIXI
911 1920
912 config ARM64_ERRATUM_2253138 !! 1921 config SYS_HAS_CPU_LOONGSON2E
913 bool "Neoverse-N2: 2253138: workaround !! 1922 bool
914 depends on CORESIGHT_TRBE <<
915 default y <<
916 select ARM64_WORKAROUND_TRBE_WRITE_OUT <<
917 help <<
918 This option adds the workaround for <<
919 1923
920 Affected Neoverse-N2 cores might wri !! 1924 config SYS_HAS_CPU_LOONGSON2F
921 for TRBE. Under some conditions, the !! 1925 bool
922 virtually addressed page following t !! 1926 select CPU_SUPPORTS_CPUFREQ
923 (i.e., the TRBLIMITR_EL1.LIMIT), ins !! 1927 select CPU_SUPPORTS_ADDRWINCFG if 64BIT
>> 1928 select CPU_SUPPORTS_UNCACHED_ACCELERATED
924 1929
925 Work around this in the driver by al !! 1930 config SYS_HAS_CPU_LOONGSON1B
926 page beyond the TRBLIMITR_EL1.LIMIT, !! 1931 bool
927 1932
928 If unsure, say Y. !! 1933 config SYS_HAS_CPU_LOONGSON1C
>> 1934 bool
929 1935
930 config ARM64_ERRATUM_2224489 !! 1936 config SYS_HAS_CPU_MIPS32_R1
931 bool "Cortex-A710/X2: 2224489: workaro !! 1937 bool
932 depends on CORESIGHT_TRBE <<
933 default y <<
934 select ARM64_WORKAROUND_TRBE_WRITE_OUT <<
935 help <<
936 This option adds the workaround for <<
937 1938
938 Affected Cortex-A710/X2 cores might !! 1939 config SYS_HAS_CPU_MIPS32_R2
939 for TRBE. Under some conditions, the !! 1940 bool
940 virtually addressed page following t <<
941 (i.e., the TRBLIMITR_EL1.LIMIT), ins <<
942 1941
943 Work around this in the driver by al !! 1942 config SYS_HAS_CPU_MIPS32_R3_5
944 page beyond the TRBLIMITR_EL1.LIMIT, !! 1943 bool
945 1944
946 If unsure, say Y. !! 1945 config SYS_HAS_CPU_MIPS32_R5
>> 1946 bool
>> 1947 select ARCH_HAS_SYNC_DMA_FOR_CPU if DMA_NONCOHERENT
947 1948
948 config ARM64_ERRATUM_2441009 !! 1949 config SYS_HAS_CPU_MIPS32_R6
949 bool "Cortex-A510: Completion of affec !! 1950 bool
950 select ARM64_WORKAROUND_REPEAT_TLBI !! 1951 select ARCH_HAS_SYNC_DMA_FOR_CPU if DMA_NONCOHERENT
951 help <<
952 This option adds a workaround for AR <<
953 <<
954 Under very rare circumstances, affec <<
955 may not handle a race between a brea <<
956 CPU, and another CPU accessing the s <<
957 store to a page that has been unmapp <<
958 1952
959 Work around this by adding the affec !! 1953 config SYS_HAS_CPU_MIPS64_R1
960 TLB sequences to be done twice. !! 1954 bool
961 1955
962 If unsure, say N. !! 1956 config SYS_HAS_CPU_MIPS64_R2
>> 1957 bool
963 1958
964 config ARM64_ERRATUM_2064142 !! 1959 config SYS_HAS_CPU_MIPS64_R6
965 bool "Cortex-A510: 2064142: workaround !! 1960 bool
966 depends on CORESIGHT_TRBE !! 1961 select ARCH_HAS_SYNC_DMA_FOR_CPU if DMA_NONCOHERENT
967 default y <<
968 help <<
969 This option adds the workaround for <<
970 1962
971 Affected Cortex-A510 core might fail !! 1963 config SYS_HAS_CPU_R3000
972 TRBE has been disabled. Under some c !! 1964 bool
973 writes into TRBE registers TRBLIMITR <<
974 and TRBTRG_EL1 will be ignored and w <<
975 1965
976 Work around this in the driver by ex !! 1966 config SYS_HAS_CPU_TX39XX
977 is stopped and before performing a s !! 1967 bool
978 registers. <<
979 1968
980 If unsure, say Y. !! 1969 config SYS_HAS_CPU_VR41XX
>> 1970 bool
981 1971
982 config ARM64_ERRATUM_2038923 !! 1972 config SYS_HAS_CPU_R4300
983 bool "Cortex-A510: 2038923: workaround !! 1973 bool
984 depends on CORESIGHT_TRBE <<
985 default y <<
986 help <<
987 This option adds the workaround for <<
988 <<
989 Affected Cortex-A510 core might caus <<
990 prohibited within the CPU. As a resu <<
991 might be corrupted. This happens aft <<
992 TRBLIMITR_EL1.E, followed by just a <<
993 execution changes from a context, in <<
994 isn't, or vice versa. In these menti <<
995 is prohibited is inconsistent betwee <<
996 the trace buffer state might be corr <<
997 <<
998 Work around this in the driver by pr <<
999 trace is prohibited or not based on <<
1000 change to TRBLIMITR_EL1.E with at l <<
1001 two ISB instructions if no ERET is <<
1002 1974
1003 If unsure, say Y. !! 1975 config SYS_HAS_CPU_R4X00
>> 1976 bool
1004 1977
1005 config ARM64_ERRATUM_1902691 !! 1978 config SYS_HAS_CPU_TX49XX
1006 bool "Cortex-A510: 1902691: workaroun !! 1979 bool
1007 depends on CORESIGHT_TRBE <<
1008 default y <<
1009 help <<
1010 This option adds the workaround for <<
1011 1980
1012 Affected Cortex-A510 core might cau !! 1981 config SYS_HAS_CPU_R5000
1013 into the memory. Effectively TRBE i !! 1982 bool
1014 trace data. <<
1015 1983
1016 Work around this problem in the dri !! 1984 config SYS_HAS_CPU_R5432
1017 affected cpus. The firmware must ha !! 1985 bool
1018 on such implementations. This will <<
1019 do this already. <<
1020 1986
1021 If unsure, say Y. !! 1987 config SYS_HAS_CPU_R5500
>> 1988 bool
1022 1989
1023 config ARM64_ERRATUM_2457168 !! 1990 config SYS_HAS_CPU_NEVADA
1024 bool "Cortex-A510: 2457168: workaroun !! 1991 bool
1025 depends on ARM64_AMU_EXTN <<
1026 default y <<
1027 help <<
1028 This option adds the workaround for <<
1029 1992
1030 The AMU counter AMEVCNTR01 (constan !! 1993 config SYS_HAS_CPU_R8000
1031 as the system counter. On affected !! 1994 bool
1032 incorrectly giving a significantly <<
1033 1995
1034 Work around this problem by returni !! 1996 config SYS_HAS_CPU_R10000
1035 key locations that results in disab !! 1997 bool
1036 is the same to firmware disabling a !! 1998 select ARCH_HAS_SYNC_DMA_FOR_CPU if DMA_NONCOHERENT
1037 1999
1038 If unsure, say Y. !! 2000 config SYS_HAS_CPU_RM7000
>> 2001 bool
1039 2002
1040 config ARM64_ERRATUM_2645198 !! 2003 config SYS_HAS_CPU_SB1
1041 bool "Cortex-A715: 2645198: Workaroun !! 2004 bool
1042 default y <<
1043 help <<
1044 This option adds the workaround for <<
1045 2005
1046 If a Cortex-A715 cpu sees a page ma !! 2006 config SYS_HAS_CPU_CAVIUM_OCTEON
1047 to non-executable, it may corrupt t !! 2007 bool
1048 next instruction abort caused by pe <<
1049 2008
1050 Only user-space does executable to !! 2009 config SYS_HAS_CPU_BMIPS
1051 mprotect() system call. Workaround !! 2010 bool
1052 TLB invalidation, for all changes t <<
1053 2011
1054 If unsure, say Y. !! 2012 config SYS_HAS_CPU_BMIPS32_3300
>> 2013 bool
>> 2014 select SYS_HAS_CPU_BMIPS
1055 2015
1056 config ARM64_WORKAROUND_SPECULATIVE_UNPRIV_LO !! 2016 config SYS_HAS_CPU_BMIPS4350
1057 bool 2017 bool
>> 2018 select SYS_HAS_CPU_BMIPS
1058 2019
1059 config ARM64_ERRATUM_2966298 !! 2020 config SYS_HAS_CPU_BMIPS4380
1060 bool "Cortex-A520: 2966298: workaroun !! 2021 bool
1061 select ARM64_WORKAROUND_SPECULATIVE_U !! 2022 select SYS_HAS_CPU_BMIPS
1062 default y <<
1063 help <<
1064 This option adds the workaround for <<
1065 2023
1066 On an affected Cortex-A520 core, a !! 2024 config SYS_HAS_CPU_BMIPS5000
1067 load might leak data from a privile !! 2025 bool
>> 2026 select SYS_HAS_CPU_BMIPS
>> 2027 select ARCH_HAS_SYNC_DMA_FOR_CPU
1068 2028
1069 Work around this problem by executi !! 2029 config SYS_HAS_CPU_XLR
>> 2030 bool
1070 2031
1071 If unsure, say Y. !! 2032 config SYS_HAS_CPU_XLP
>> 2033 bool
1072 2034
1073 config ARM64_ERRATUM_3117295 !! 2035 #
1074 bool "Cortex-A510: 3117295: workaroun !! 2036 # CPU may reorder R->R, R->W, W->R, W->W
1075 select ARM64_WORKAROUND_SPECULATIVE_U !! 2037 # Reordering beyond LL and SC is handled in WEAK_REORDERING_BEYOND_LLSC
1076 default y !! 2038 #
1077 help !! 2039 config WEAK_ORDERING
1078 This option adds the workaround for !! 2040 bool
1079 2041
1080 On an affected Cortex-A510 core, a !! 2042 #
1081 load might leak data from a privile !! 2043 # CPU may reorder reads and writes beyond LL/SC
>> 2044 # CPU may reorder R->LL, R->LL, W->LL, W->LL, R->SC, R->SC, W->SC, W->SC
>> 2045 #
>> 2046 config WEAK_REORDERING_BEYOND_LLSC
>> 2047 bool
>> 2048 endmenu
1082 2049
1083 Work around this problem by executi !! 2050 #
>> 2051 # These two indicate any level of the MIPS32 and MIPS64 architecture
>> 2052 #
>> 2053 config CPU_MIPS32
>> 2054 bool
>> 2055 default y if CPU_MIPS32_R1 || CPU_MIPS32_R2 || CPU_MIPS32_R6
1084 2056
1085 If unsure, say Y. !! 2057 config CPU_MIPS64
>> 2058 bool
>> 2059 default y if CPU_MIPS64_R1 || CPU_MIPS64_R2 || CPU_MIPS64_R6
1086 2060
1087 config ARM64_ERRATUM_3194386 !! 2061 #
1088 bool "Cortex-*/Neoverse-*: workaround !! 2062 # These indicate the revision of the architecture
1089 default y !! 2063 #
1090 help !! 2064 config CPU_MIPSR1
1091 This option adds the workaround for !! 2065 bool
>> 2066 default y if CPU_MIPS32_R1 || CPU_MIPS64_R1
1092 2067
1093 * ARM Cortex-A76 erratum 3324349 !! 2068 config CPU_MIPSR2
1094 * ARM Cortex-A77 erratum 3324348 !! 2069 bool
1095 * ARM Cortex-A78 erratum 3324344 !! 2070 default y if CPU_MIPS32_R2 || CPU_MIPS64_R2 || CPU_CAVIUM_OCTEON
1096 * ARM Cortex-A78C erratum 3324346 !! 2071 select CPU_HAS_RIXI
1097 * ARM Cortex-A78C erratum 3324347 !! 2072 select MIPS_SPRAM
1098 * ARM Cortex-A710 erratam 3324338 <<
1099 * ARM Cortex-A715 errartum 3456084 <<
1100 * ARM Cortex-A720 erratum 3456091 <<
1101 * ARM Cortex-A725 erratum 3456106 <<
1102 * ARM Cortex-X1 erratum 3324344 <<
1103 * ARM Cortex-X1C erratum 3324346 <<
1104 * ARM Cortex-X2 erratum 3324338 <<
1105 * ARM Cortex-X3 erratum 3324335 <<
1106 * ARM Cortex-X4 erratum 3194386 <<
1107 * ARM Cortex-X925 erratum 3324334 <<
1108 * ARM Neoverse-N1 erratum 3324349 <<
1109 * ARM Neoverse N2 erratum 3324339 <<
1110 * ARM Neoverse-N3 erratum 3456111 <<
1111 * ARM Neoverse-V1 erratum 3324341 <<
1112 * ARM Neoverse V2 erratum 3324336 <<
1113 * ARM Neoverse-V3 erratum 3312417 <<
1114 <<
1115 On affected cores "MSR SSBS, #0" in <<
1116 subsequent speculative instructions <<
1117 speculative store bypassing. <<
1118 <<
1119 Work around this problem by placing <<
1120 Instruction Synchronization Barrier <<
1121 SSBS. The presence of the SSBS spec <<
1122 from hwcaps and EL0 reads of ID_AA6 <<
1123 will use the PR_SPEC_STORE_BYPASS p <<
1124 2073
1125 If unsure, say Y. !! 2074 config CPU_MIPSR6
>> 2075 bool
>> 2076 default y if CPU_MIPS32_R6 || CPU_MIPS64_R6
>> 2077 select CPU_HAS_RIXI
>> 2078 select HAVE_ARCH_BITREVERSE
>> 2079 select MIPS_ASID_BITS_VARIABLE
>> 2080 select MIPS_CRC_SUPPORT
>> 2081 select MIPS_SPRAM
1126 2082
1127 config CAVIUM_ERRATUM_22375 !! 2083 config TARGET_ISA_REV
1128 bool "Cavium erratum 22375, 24313" !! 2084 int
1129 default y !! 2085 default 1 if CPU_MIPSR1
>> 2086 default 2 if CPU_MIPSR2
>> 2087 default 6 if CPU_MIPSR6
>> 2088 default 0
1130 help 2089 help
1131 Enable workaround for errata 22375 !! 2090 Reflects the ISA revision being targeted by the kernel build. This
1132 !! 2091 is effectively the Kconfig equivalent of MIPS_ISA_REV.
1133 This implements two gicv3-its errat <<
1134 with a small impact affecting only <<
1135 2092
1136 erratum 22375: only alloc 8MB tab !! 2093 config EVA
1137 erratum 24313: ignore memory acce !! 2094 bool
1138 2095
1139 The fixes are in ITS initialization !! 2096 config XPA
1140 type and table size provided by the !! 2097 bool
1141 2098
1142 If unsure, say Y. !! 2099 config SYS_SUPPORTS_32BIT_KERNEL
>> 2100 bool
>> 2101 config SYS_SUPPORTS_64BIT_KERNEL
>> 2102 bool
>> 2103 config CPU_SUPPORTS_32BIT_KERNEL
>> 2104 bool
>> 2105 config CPU_SUPPORTS_64BIT_KERNEL
>> 2106 bool
>> 2107 config CPU_SUPPORTS_CPUFREQ
>> 2108 bool
>> 2109 config CPU_SUPPORTS_ADDRWINCFG
>> 2110 bool
>> 2111 config CPU_SUPPORTS_HUGEPAGES
>> 2112 bool
>> 2113 config CPU_SUPPORTS_UNCACHED_ACCELERATED
>> 2114 bool
>> 2115 config MIPS_PGD_C0_CONTEXT
>> 2116 bool
>> 2117 default y if 64BIT && (CPU_MIPSR2 || CPU_MIPSR6) && !CPU_XLP
1143 2118
1144 config CAVIUM_ERRATUM_23144 !! 2119 #
1145 bool "Cavium erratum 23144: ITS SYNC !! 2120 # Set to y for ptrace access to watch registers.
1146 depends on NUMA !! 2121 #
1147 default y !! 2122 config HARDWARE_WATCHPOINTS
1148 help !! 2123 bool
1149 ITS SYNC command hang for cross nod !! 2124 default y if CPU_MIPSR1 || CPU_MIPSR2 || CPU_MIPSR6
1150 2125
1151 If unsure, say Y. !! 2126 menu "Kernel type"
1152 2127
1153 config CAVIUM_ERRATUM_23154 !! 2128 choice
1154 bool "Cavium errata 23154 and 38545: !! 2129 prompt "Kernel code model"
1155 default y <<
1156 help 2130 help
1157 The ThunderX GICv3 implementation r !! 2131 You should only select this option if you have a workload that
1158 reading the IAR status to ensure da !! 2132 actually benefits from 64-bit processing or if your machine has
1159 (access to icc_iar1_el1 is not sync !! 2133 large memory. You will only be presented a single option in this
1160 !! 2134 menu if your system does not support both 32-bit and 64-bit kernels.
1161 It also suffers from erratum 38545 !! 2135
1162 OcteonTX and OcteonTX2), resulting !! 2136 config 32BIT
1163 spuriously presented to the CPU int !! 2137 bool "32-bit kernel"
1164 !! 2138 depends on CPU_SUPPORTS_32BIT_KERNEL && SYS_SUPPORTS_32BIT_KERNEL
1165 If unsure, say Y. !! 2139 select TRAD_SIGNALS
1166 <<
1167 config CAVIUM_ERRATUM_27456 <<
1168 bool "Cavium erratum 27456: Broadcast <<
1169 default y <<
1170 help 2140 help
1171 On ThunderX T88 pass 1.x through 2. !! 2141 Select this option if you want to build a 32-bit kernel.
1172 instructions may cause the icache t <<
1173 contains data for a non-current ASI <<
1174 invalidate the icache when changing <<
1175 <<
1176 If unsure, say Y. <<
1177 2142
1178 config CAVIUM_ERRATUM_30115 !! 2143 config 64BIT
1179 bool "Cavium erratum 30115: Guest may !! 2144 bool "64-bit kernel"
1180 default y !! 2145 depends on CPU_SUPPORTS_64BIT_KERNEL && SYS_SUPPORTS_64BIT_KERNEL
1181 help 2146 help
1182 On ThunderX T88 pass 1.x through 2. !! 2147 Select this option if you want to build a 64-bit kernel.
1183 1.2, and T83 Pass 1.0, KVM guest ex <<
1184 interrupts in host. Trapping both G <<
1185 accesses sidesteps the issue. <<
1186 2148
1187 If unsure, say Y. !! 2149 endchoice
1188 <<
1189 config CAVIUM_TX2_ERRATUM_219 <<
1190 bool "Cavium ThunderX2 erratum 219: P <<
1191 default y <<
1192 help <<
1193 On Cavium ThunderX2, a load, store <<
1194 TTBR update and the corresponding c <<
1195 cause a spurious Data Abort to be d <<
1196 the CPU core. <<
1197 <<
1198 Work around the issue by avoiding t <<
1199 trapping KVM guest TTBRx_EL1 writes <<
1200 trap handler performs the correspon <<
1201 instruction and ensures context syn <<
1202 exception return. <<
1203 2150
1204 If unsure, say Y. !! 2151 config KVM_GUEST
>> 2152 bool "KVM Guest Kernel"
>> 2153 depends on BROKEN_ON_SMP
>> 2154 help
>> 2155 Select this option if building a guest kernel for KVM (Trap & Emulate)
>> 2156 mode.
>> 2157
>> 2158 config KVM_GUEST_TIMER_FREQ
>> 2159 int "Count/Compare Timer Frequency (MHz)"
>> 2160 depends on KVM_GUEST
>> 2161 default 100
>> 2162 help
>> 2163 Set this to non-zero if building a guest kernel for KVM to skip RTC
>> 2164 emulation when determining guest CPU Frequency. Instead, the guest's
>> 2165 timer frequency is specified directly.
>> 2166
>> 2167 config MIPS_VA_BITS_48
>> 2168 bool "48 bits virtual memory"
>> 2169 depends on 64BIT
>> 2170 help
>> 2171 Support a maximum at least 48 bits of application virtual
>> 2172 memory. Default is 40 bits or less, depending on the CPU.
>> 2173 For page sizes 16k and above, this option results in a small
>> 2174 memory overhead for page tables. For 4k page size, a fourth
>> 2175 level of page tables is added which imposes both a memory
>> 2176 overhead as well as slower TLB fault handling.
1205 2177
1206 config FUJITSU_ERRATUM_010001 !! 2178 If unsure, say N.
1207 bool "Fujitsu-A64FX erratum E#010001: <<
1208 default y <<
1209 help <<
1210 This option adds a workaround for F <<
1211 On some variants of the Fujitsu-A64 <<
1212 accesses may cause undefined fault <<
1213 This fault occurs under a specific <<
1214 load/store instruction performs an <<
1215 case-1 TTBR0_EL1 with TCR_EL1.NFD0 <<
1216 case-2 TTBR0_EL2 with TCR_EL2.NFD0 <<
1217 case-3 TTBR1_EL1 with TCR_EL1.NFD1 <<
1218 case-4 TTBR1_EL2 with TCR_EL2.NFD1 <<
1219 2179
1220 The workaround is to ensure these b !! 2180 choice
1221 The workaround only affects the Fuj !! 2181 prompt "Kernel page size"
>> 2182 default PAGE_SIZE_4KB
1222 2183
1223 If unsure, say Y. !! 2184 config PAGE_SIZE_4KB
>> 2185 bool "4kB"
>> 2186 depends on !CPU_LOONGSON2 && !CPU_LOONGSON3
>> 2187 help
>> 2188 This option select the standard 4kB Linux page size. On some
>> 2189 R3000-family processors this is the only available page size. Using
>> 2190 4kB page size will minimize memory consumption and is therefore
>> 2191 recommended for low memory systems.
>> 2192
>> 2193 config PAGE_SIZE_8KB
>> 2194 bool "8kB"
>> 2195 depends on CPU_R8000 || CPU_CAVIUM_OCTEON
>> 2196 depends on !MIPS_VA_BITS_48
>> 2197 help
>> 2198 Using 8kB page size will result in higher performance kernel at
>> 2199 the price of higher memory consumption. This option is available
>> 2200 only on R8000 and cnMIPS processors. Note that you will need a
>> 2201 suitable Linux distribution to support this.
>> 2202
>> 2203 config PAGE_SIZE_16KB
>> 2204 bool "16kB"
>> 2205 depends on !CPU_R3000 && !CPU_TX39XX
>> 2206 help
>> 2207 Using 16kB page size will result in higher performance kernel at
>> 2208 the price of higher memory consumption. This option is available on
>> 2209 all non-R3000 family processors. Note that you will need a suitable
>> 2210 Linux distribution to support this.
>> 2211
>> 2212 config PAGE_SIZE_32KB
>> 2213 bool "32kB"
>> 2214 depends on CPU_CAVIUM_OCTEON
>> 2215 depends on !MIPS_VA_BITS_48
>> 2216 help
>> 2217 Using 32kB page size will result in higher performance kernel at
>> 2218 the price of higher memory consumption. This option is available
>> 2219 only on cnMIPS cores. Note that you will need a suitable Linux
>> 2220 distribution to support this.
>> 2221
>> 2222 config PAGE_SIZE_64KB
>> 2223 bool "64kB"
>> 2224 depends on !CPU_R3000 && !CPU_TX39XX
>> 2225 help
>> 2226 Using 64kB page size will result in higher performance kernel at
>> 2227 the price of higher memory consumption. This option is available on
>> 2228 all non-R3000 family processor. Not that at the time of this
>> 2229 writing this option is still high experimental.
1224 2230
1225 config HISILICON_ERRATUM_161600802 !! 2231 endchoice
1226 bool "Hip07 161600802: Erroneous redi <<
1227 default y <<
1228 help <<
1229 The HiSilicon Hip07 SoC uses the wr <<
1230 when issued ITS commands such as VM <<
1231 a 128kB offset to be applied to the <<
1232 2232
1233 If unsure, say Y. !! 2233 config FORCE_MAX_ZONEORDER
>> 2234 int "Maximum zone order"
>> 2235 range 14 64 if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_64KB
>> 2236 default "14" if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_64KB
>> 2237 range 13 64 if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_32KB
>> 2238 default "13" if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_32KB
>> 2239 range 12 64 if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_16KB
>> 2240 default "12" if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_16KB
>> 2241 range 11 64
>> 2242 default "11"
>> 2243 help
>> 2244 The kernel memory allocator divides physically contiguous memory
>> 2245 blocks into "zones", where each zone is a power of two number of
>> 2246 pages. This option selects the largest power of two that the kernel
>> 2247 keeps in the memory allocator. If you need to allocate very large
>> 2248 blocks of physically contiguous memory, then you may need to
>> 2249 increase this value.
1234 2250
1235 config QCOM_FALKOR_ERRATUM_1003 !! 2251 This config option is actually maximum order plus one. For example,
1236 bool "Falkor E1003: Incorrect transla !! 2252 a value of 11 means that the largest free memory block is 2^10 pages.
1237 default y <<
1238 help <<
1239 On Falkor v1, an incorrect ASID may <<
1240 and BADDR are changed together in T <<
1241 in TTBR1_EL1, this situation only o <<
1242 then only for entries in the walk c <<
1243 is unchanged. Work around the errat <<
1244 entries for the trampoline before e <<
1245 2253
1246 config QCOM_FALKOR_ERRATUM_1009 !! 2254 The page size is not necessarily 4KB. Keep this in mind
1247 bool "Falkor E1009: Prematurely compl !! 2255 when choosing a value for this option.
1248 default y <<
1249 select ARM64_WORKAROUND_REPEAT_TLBI <<
1250 help <<
1251 On Falkor v1, the CPU may premature <<
1252 TLBI xxIS invalidate maintenance op <<
1253 one more time to fix the issue. <<
1254 2256
1255 If unsure, say Y. !! 2257 config BOARD_SCACHE
>> 2258 bool
1256 2259
1257 config QCOM_QDF2400_ERRATUM_0065 !! 2260 config IP22_CPU_SCACHE
1258 bool "QDF2400 E0065: Incorrect GITS_T !! 2261 bool
1259 default y !! 2262 select BOARD_SCACHE
1260 help <<
1261 On Qualcomm Datacenter Technologies <<
1262 ITE size incorrectly. The GITS_TYPE <<
1263 been indicated as 16Bytes (0xf), no <<
1264 2263
1265 If unsure, say Y. !! 2264 #
>> 2265 # Support for a MIPS32 / MIPS64 style S-caches
>> 2266 #
>> 2267 config MIPS_CPU_SCACHE
>> 2268 bool
>> 2269 select BOARD_SCACHE
1266 2270
1267 config QCOM_FALKOR_ERRATUM_E1041 !! 2271 config R5000_CPU_SCACHE
1268 bool "Falkor E1041: Speculative instr !! 2272 bool
1269 default y !! 2273 select BOARD_SCACHE
1270 help <<
1271 Falkor CPU may speculatively fetch <<
1272 memory location when MMU translatio <<
1273 to SCTLR_ELn[M]=0. Prefix an ISB in <<
1274 2274
1275 If unsure, say Y. !! 2275 config RM7000_CPU_SCACHE
>> 2276 bool
>> 2277 select BOARD_SCACHE
1276 2278
1277 config NVIDIA_CARMEL_CNP_ERRATUM !! 2279 config SIBYTE_DMA_PAGEOPS
1278 bool "NVIDIA Carmel CNP: CNP on Carme !! 2280 bool "Use DMA to clear/copy pages"
1279 default y !! 2281 depends on CPU_SB1
1280 help 2282 help
1281 If CNP is enabled on Carmel cores, !! 2283 Instead of using the CPU to zero and copy pages, use a Data Mover
1282 invalidate shared TLB entries insta !! 2284 channel. These DMA channels are otherwise unused by the standard
1283 on standard ARM cores. !! 2285 SiByte Linux port. Seems to give a small performance benefit.
1284 2286
1285 If unsure, say Y. !! 2287 config CPU_HAS_PREFETCH
1286 !! 2288 bool
1287 config ROCKCHIP_ERRATUM_3588001 <<
1288 bool "Rockchip 3588001: GIC600 can no <<
1289 default y <<
1290 help <<
1291 The Rockchip RK3588 GIC600 SoC inte <<
1292 This means, that its sharability fe <<
1293 is supported by the IP itself. <<
1294 2289
1295 If unsure, say Y. !! 2290 config CPU_GENERIC_DUMP_TLB
>> 2291 bool
>> 2292 default y if !(CPU_R3000 || CPU_R8000 || CPU_TX39XX)
1296 2293
1297 config SOCIONEXT_SYNQUACER_PREITS !! 2294 config MIPS_FP_SUPPORT
1298 bool "Socionext Synquacer: Workaround !! 2295 bool "Floating Point support" if EXPERT
1299 default y 2296 default y
1300 help 2297 help
1301 Socionext Synquacer SoCs implement !! 2298 Select y to include support for floating point in the kernel
1302 MSI doorbell writes with non-zero v !! 2299 including initialization of FPU hardware, FP context save & restore
>> 2300 and emulation of an FPU where necessary. Without this support any
>> 2301 userland program attempting to use floating point instructions will
>> 2302 receive a SIGILL.
1303 2303
1304 If unsure, say Y. !! 2304 If you know that your userland will not attempt to use floating point
>> 2305 instructions then you can say n here to shrink the kernel a little.
1305 2306
1306 endmenu # "ARM errata workarounds via the alt !! 2307 If unsure, say y.
1307 2308
1308 choice !! 2309 config CPU_R2300_FPU
1309 prompt "Page size" !! 2310 bool
1310 default ARM64_4K_PAGES !! 2311 depends on MIPS_FP_SUPPORT
1311 help !! 2312 default y if CPU_R3000 || CPU_TX39XX
1312 Page size (translation granule) con <<
1313 2313
1314 config ARM64_4K_PAGES !! 2314 config CPU_R4K_FPU
1315 bool "4KB" !! 2315 bool
1316 select HAVE_PAGE_SIZE_4KB !! 2316 depends on MIPS_FP_SUPPORT
1317 help !! 2317 default y if !CPU_R2300_FPU
1318 This feature enables 4KB pages supp <<
1319 2318
1320 config ARM64_16K_PAGES !! 2319 config CPU_R4K_CACHE_TLB
1321 bool "16KB" !! 2320 bool
1322 select HAVE_PAGE_SIZE_16KB !! 2321 default y if !(CPU_R3000 || CPU_R8000 || CPU_SB1 || CPU_TX39XX || CPU_CAVIUM_OCTEON)
1323 help <<
1324 The system will use 16KB pages supp <<
1325 requires applications compiled with <<
1326 aligned segments. <<
1327 2322
1328 config ARM64_64K_PAGES !! 2323 config MIPS_MT_SMP
1329 bool "64KB" !! 2324 bool "MIPS MT SMP support (1 TC on each available VPE)"
1330 select HAVE_PAGE_SIZE_64KB !! 2325 default y
1331 help !! 2326 depends on SYS_SUPPORTS_MULTITHREADING && !CPU_MIPSR6 && !CPU_MICROMIPS
1332 This feature enables 64KB pages sup !! 2327 select CPU_MIPSR2_IRQ_VI
1333 allowing only two levels of page ta !! 2328 select CPU_MIPSR2_IRQ_EI
1334 look-up. AArch32 emulation requires !! 2329 select SYNC_R4K
1335 with 64K aligned segments. !! 2330 select MIPS_MT
>> 2331 select SMP
>> 2332 select SMP_UP
>> 2333 select SYS_SUPPORTS_SMP
>> 2334 select SYS_SUPPORTS_SCHED_SMT
>> 2335 select MIPS_PERF_SHARED_TC_COUNTERS
>> 2336 help
>> 2337 This is a kernel model which is known as SMVP. This is supported
>> 2338 on cores with the MT ASE and uses the available VPEs to implement
>> 2339 virtual processors which supports SMP. This is equivalent to the
>> 2340 Intel Hyperthreading feature. For further information go to
>> 2341 <http://www.imgtec.com/mips/mips-multithreading.asp>.
1336 2342
1337 endchoice !! 2343 config MIPS_MT
>> 2344 bool
1338 2345
1339 choice !! 2346 config SCHED_SMT
1340 prompt "Virtual address space size" !! 2347 bool "SMT (multithreading) scheduler support"
1341 default ARM64_VA_BITS_52 !! 2348 depends on SYS_SUPPORTS_SCHED_SMT
>> 2349 default n
1342 help 2350 help
1343 Allows choosing one of multiple pos !! 2351 SMT scheduler support improves the CPU scheduler's decision making
1344 space sizes. The level of translati !! 2352 when dealing with MIPS MT enabled cores at a cost of slightly
1345 a combination of page size and virt !! 2353 increased overhead in some places. If unsure say N here.
1346 <<
1347 config ARM64_VA_BITS_36 <<
1348 bool "36-bit" if EXPERT <<
1349 depends on PAGE_SIZE_16KB <<
1350 <<
1351 config ARM64_VA_BITS_39 <<
1352 bool "39-bit" <<
1353 depends on PAGE_SIZE_4KB <<
1354 <<
1355 config ARM64_VA_BITS_42 <<
1356 bool "42-bit" <<
1357 depends on PAGE_SIZE_64KB <<
1358 <<
1359 config ARM64_VA_BITS_47 <<
1360 bool "47-bit" <<
1361 depends on PAGE_SIZE_16KB <<
1362 <<
1363 config ARM64_VA_BITS_48 <<
1364 bool "48-bit" <<
1365 <<
1366 config ARM64_VA_BITS_52 <<
1367 bool "52-bit" <<
1368 depends on ARM64_PAN || !ARM64_SW_TTB <<
1369 help <<
1370 Enable 52-bit virtual addressing fo <<
1371 requested via a hint to mmap(). The <<
1372 virtual addresses for its own mappi <<
1373 this feature is available, otherwis <<
1374 <<
1375 NOTE: Enabling 52-bit virtual addre <<
1376 ARMv8.3 Pointer Authentication will <<
1377 reduced from 7 bits to 3 bits, whic <<
1378 impact on its susceptibility to bru <<
1379 <<
1380 If unsure, select 48-bit virtual ad <<
1381 2354
1382 endchoice !! 2355 config SYS_SUPPORTS_SCHED_SMT
>> 2356 bool
1383 2357
1384 config ARM64_FORCE_52BIT !! 2358 config SYS_SUPPORTS_MULTITHREADING
1385 bool "Force 52-bit virtual addresses !! 2359 bool
1386 depends on ARM64_VA_BITS_52 && EXPERT <<
1387 help <<
1388 For systems with 52-bit userspace V <<
1389 to maintain compatibility with olde <<
1390 unless a hint is supplied to mmap. <<
1391 <<
1392 This configuration option disables <<
1393 forces all userspace addresses to b <<
1394 should only enable this configurati <<
1395 memory management code. If unsure s <<
1396 2360
1397 config ARM64_VA_BITS !! 2361 config MIPS_MT_FPAFF
1398 int !! 2362 bool "Dynamic FPU affinity for FP-intensive threads"
1399 default 36 if ARM64_VA_BITS_36 !! 2363 default y
1400 default 39 if ARM64_VA_BITS_39 !! 2364 depends on MIPS_MT_SMP
1401 default 42 if ARM64_VA_BITS_42 <<
1402 default 47 if ARM64_VA_BITS_47 <<
1403 default 48 if ARM64_VA_BITS_48 <<
1404 default 52 if ARM64_VA_BITS_52 <<
1405 2365
1406 choice !! 2366 config MIPSR2_TO_R6_EMULATOR
1407 prompt "Physical address space size" !! 2367 bool "MIPS R2-to-R6 emulator"
1408 default ARM64_PA_BITS_48 !! 2368 depends on CPU_MIPSR6
>> 2369 depends on MIPS_FP_SUPPORT
>> 2370 default y
1409 help 2371 help
1410 Choose the maximum physical address !! 2372 Choose this option if you want to run non-R6 MIPS userland code.
1411 support. !! 2373 Even if you say 'Y' here, the emulator will still be disabled by
1412 !! 2374 default. You can enable it using the 'mipsr2emu' kernel option.
1413 config ARM64_PA_BITS_48 !! 2375 The only reason this is a build-time option is to save ~14K from the
1414 bool "48-bit" !! 2376 final kernel image.
1415 depends on ARM64_64K_PAGES || !ARM64_ <<
1416 <<
1417 config ARM64_PA_BITS_52 <<
1418 bool "52-bit" <<
1419 depends on ARM64_64K_PAGES || ARM64_V <<
1420 depends on ARM64_PAN || !ARM64_SW_TTB <<
1421 help <<
1422 Enable support for a 52-bit physica <<
1423 part of the ARMv8.2-LPA extension. <<
1424 <<
1425 With this enabled, the kernel will <<
1426 do not support ARMv8.2-LPA, but wit <<
1427 minor performance overhead). <<
1428 <<
1429 endchoice <<
1430 2377
1431 config ARM64_PA_BITS !! 2378 config SYS_SUPPORTS_VPE_LOADER
1432 int !! 2379 bool
1433 default 48 if ARM64_PA_BITS_48 !! 2380 depends on SYS_SUPPORTS_MULTITHREADING
1434 default 52 if ARM64_PA_BITS_52 <<
1435 <<
1436 config ARM64_LPA2 <<
1437 def_bool y <<
1438 depends on ARM64_PA_BITS_52 && !ARM64 <<
1439 <<
1440 choice <<
1441 prompt "Endianness" <<
1442 default CPU_LITTLE_ENDIAN <<
1443 help 2381 help
1444 Select the endianness of data acces !! 2382 Indicates that the platform supports the VPE loader, and provides
1445 applications will need to be compil !! 2383 physical_memsize.
1446 that is selected here. <<
1447 2384
1448 config CPU_BIG_ENDIAN !! 2385 config MIPS_VPE_LOADER
1449 bool "Build big-endian kernel" !! 2386 bool "VPE loader support."
1450 # https://github.com/llvm/llvm-projec !! 2387 depends on SYS_SUPPORTS_VPE_LOADER && MODULES
1451 depends on AS_IS_GNU || AS_VERSION >= !! 2388 select CPU_MIPSR2_IRQ_VI
>> 2389 select CPU_MIPSR2_IRQ_EI
>> 2390 select MIPS_MT
1452 help 2391 help
1453 Say Y if you plan on running a kern !! 2392 Includes a loader for loading an elf relocatable object
>> 2393 onto another VPE and running it.
1454 2394
1455 config CPU_LITTLE_ENDIAN !! 2395 config MIPS_VPE_LOADER_CMP
1456 bool "Build little-endian kernel" !! 2396 bool
1457 help !! 2397 default "y"
1458 Say Y if you plan on running a kern !! 2398 depends on MIPS_VPE_LOADER && MIPS_CMP
1459 This is usually the case for distri <<
1460 2399
1461 endchoice !! 2400 config MIPS_VPE_LOADER_MT
>> 2401 bool
>> 2402 default "y"
>> 2403 depends on MIPS_VPE_LOADER && !MIPS_CMP
1462 2404
1463 config SCHED_MC !! 2405 config MIPS_VPE_LOADER_TOM
1464 bool "Multi-core scheduler support" !! 2406 bool "Load VPE program into memory hidden from linux"
>> 2407 depends on MIPS_VPE_LOADER
>> 2408 default y
1465 help 2409 help
1466 Multi-core scheduler support improv !! 2410 The loader can use memory that is present but has been hidden from
1467 making when dealing with multi-core !! 2411 Linux using the kernel command line option "mem=xxMB". It's up to
1468 increased overhead in some places. !! 2412 you to ensure the amount you put in the option and the space your
>> 2413 program requires is less or equal to the amount physically present.
1469 2414
1470 config SCHED_CLUSTER !! 2415 config MIPS_VPE_APSP_API
1471 bool "Cluster scheduler support" !! 2416 bool "Enable support for AP/SP API (RTLX)"
1472 help !! 2417 depends on MIPS_VPE_LOADER
1473 Cluster scheduler support improves <<
1474 making when dealing with machines t <<
1475 Cluster usually means a couple of C <<
1476 by sharing mid-level caches, last-l <<
1477 busses. <<
1478 2418
1479 config SCHED_SMT !! 2419 config MIPS_VPE_APSP_API_CMP
1480 bool "SMT scheduler support" !! 2420 bool
1481 help !! 2421 default "y"
1482 Improves the CPU scheduler's decisi !! 2422 depends on MIPS_VPE_APSP_API && MIPS_CMP
1483 MultiThreading at a cost of slightl <<
1484 places. If unsure say N here. <<
1485 2423
1486 config NR_CPUS !! 2424 config MIPS_VPE_APSP_API_MT
1487 int "Maximum number of CPUs (2-4096)" !! 2425 bool
1488 range 2 4096 !! 2426 default "y"
1489 default "512" !! 2427 depends on MIPS_VPE_APSP_API && !MIPS_CMP
1490 2428
1491 config HOTPLUG_CPU !! 2429 config MIPS_CMP
1492 bool "Support for hot-pluggable CPUs" !! 2430 bool "MIPS CMP framework support (DEPRECATED)"
1493 select GENERIC_IRQ_MIGRATION !! 2431 depends on SYS_SUPPORTS_MIPS_CMP && !CPU_MIPSR6
>> 2432 select SMP
>> 2433 select SYNC_R4K
>> 2434 select SYS_SUPPORTS_SMP
>> 2435 select WEAK_ORDERING
>> 2436 default n
1494 help 2437 help
1495 Say Y here to experiment with turni !! 2438 Select this if you are using a bootloader which implements the "CMP
1496 can be controlled through /sys/devi !! 2439 framework" protocol (ie. YAMON) and want your kernel to make use of
>> 2440 its ability to start secondary CPUs.
>> 2441
>> 2442 Unless you have a specific need, you should use CONFIG_MIPS_CPS
>> 2443 instead of this.
>> 2444
>> 2445 config MIPS_CPS
>> 2446 bool "MIPS Coherent Processing System support"
>> 2447 depends on SYS_SUPPORTS_MIPS_CPS
>> 2448 select MIPS_CM
>> 2449 select MIPS_CPS_PM if HOTPLUG_CPU
>> 2450 select SMP
>> 2451 select SYNC_R4K if (CEVT_R4K || CSRC_R4K)
>> 2452 select SYS_SUPPORTS_HOTPLUG_CPU
>> 2453 select SYS_SUPPORTS_SCHED_SMT if CPU_MIPSR6
>> 2454 select SYS_SUPPORTS_SMP
>> 2455 select WEAK_ORDERING
>> 2456 help
>> 2457 Select this if you wish to run an SMP kernel across multiple cores
>> 2458 within a MIPS Coherent Processing System. When this option is
>> 2459 enabled the kernel will probe for other cores and boot them with
>> 2460 no external assistance. It is safe to enable this when hardware
>> 2461 support is unavailable.
1497 2462
1498 # Common NUMA Features !! 2463 config MIPS_CPS_PM
1499 config NUMA !! 2464 depends on MIPS_CPS
1500 bool "NUMA Memory Allocation and Sche !! 2465 bool
1501 select GENERIC_ARCH_NUMA <<
1502 select OF_NUMA <<
1503 select HAVE_SETUP_PER_CPU_AREA <<
1504 select NEED_PER_CPU_EMBED_FIRST_CHUNK <<
1505 select NEED_PER_CPU_PAGE_FIRST_CHUNK <<
1506 select USE_PERCPU_NUMA_NODE_ID <<
1507 help <<
1508 Enable NUMA (Non-Uniform Memory Acc <<
1509 <<
1510 The kernel will try to allocate mem <<
1511 local memory of the CPU and add som <<
1512 NUMA awareness to the kernel. <<
1513 2466
1514 config NODES_SHIFT !! 2467 config MIPS_CM
1515 int "Maximum NUMA Nodes (as a power o !! 2468 bool
1516 range 1 10 !! 2469 select MIPS_CPC
1517 default "4" <<
1518 depends on NUMA <<
1519 help <<
1520 Specify the maximum number of NUMA <<
1521 system. Increases memory reserved <<
1522 2470
1523 source "kernel/Kconfig.hz" !! 2471 config MIPS_CPC
>> 2472 bool
1524 2473
1525 config ARCH_SPARSEMEM_ENABLE !! 2474 config SB1_PASS_2_WORKAROUNDS
1526 def_bool y !! 2475 bool
1527 select SPARSEMEM_VMEMMAP_ENABLE !! 2476 depends on CPU_SB1 && (CPU_SB1_PASS_2_2 || CPU_SB1_PASS_2)
1528 select SPARSEMEM_VMEMMAP !! 2477 default y
1529 2478
1530 config HW_PERF_EVENTS !! 2479 config SB1_PASS_2_1_WORKAROUNDS
1531 def_bool y !! 2480 bool
1532 depends on ARM_PMU !! 2481 depends on CPU_SB1 && CPU_SB1_PASS_2
>> 2482 default y
1533 2483
1534 # Supported by clang >= 7.0 or GCC >= 12.0.0 !! 2484 choice
1535 config CC_HAVE_SHADOW_CALL_STACK !! 2485 prompt "SmartMIPS or microMIPS ASE support"
1536 def_bool $(cc-option, -fsanitize=shad <<
1537 2486
1538 config PARAVIRT !! 2487 config CPU_NEEDS_NO_SMARTMIPS_OR_MICROMIPS
1539 bool "Enable paravirtualization code" !! 2488 bool "None"
1540 help 2489 help
1541 This changes the kernel so it can m !! 2490 Select this if you want neither microMIPS nor SmartMIPS support
1542 under a hypervisor, potentially imp <<
1543 over full virtualization. <<
1544 2491
1545 config PARAVIRT_TIME_ACCOUNTING !! 2492 config CPU_HAS_SMARTMIPS
1546 bool "Paravirtual steal time accounti !! 2493 depends on SYS_SUPPORTS_SMARTMIPS
1547 select PARAVIRT !! 2494 bool "SmartMIPS"
>> 2495 help
>> 2496 SmartMIPS is a extension of the MIPS32 architecture aimed at
>> 2497 increased security at both hardware and software level for
>> 2498 smartcards. Enabling this option will allow proper use of the
>> 2499 SmartMIPS instructions by Linux applications. However a kernel with
>> 2500 this option will not work on a MIPS core without SmartMIPS core. If
>> 2501 you don't know you probably don't have SmartMIPS and should say N
>> 2502 here.
>> 2503
>> 2504 config CPU_MICROMIPS
>> 2505 depends on 32BIT && SYS_SUPPORTS_MICROMIPS && !CPU_MIPSR6
>> 2506 bool "microMIPS"
1548 help 2507 help
1549 Select this option to enable fine g !! 2508 When this option is enabled the kernel will be built using the
1550 accounting. Time spent executing ot !! 2509 microMIPS ISA
1551 the current vCPU is discounted from <<
1552 that, there can be a small performa <<
1553 <<
1554 If in doubt, say N here. <<
1555 <<
1556 config ARCH_SUPPORTS_KEXEC <<
1557 def_bool PM_SLEEP_SMP <<
1558 <<
1559 config ARCH_SUPPORTS_KEXEC_FILE <<
1560 def_bool y <<
1561 <<
1562 config ARCH_SELECTS_KEXEC_FILE <<
1563 def_bool y <<
1564 depends on KEXEC_FILE <<
1565 select HAVE_IMA_KEXEC if IMA <<
1566 <<
1567 config ARCH_SUPPORTS_KEXEC_SIG <<
1568 def_bool y <<
1569 2510
1570 config ARCH_SUPPORTS_KEXEC_IMAGE_VERIFY_SIG !! 2511 endchoice
1571 def_bool y <<
1572 2512
1573 config ARCH_DEFAULT_KEXEC_IMAGE_VERIFY_SIG !! 2513 config CPU_HAS_MSA
1574 def_bool y !! 2514 bool "Support for the MIPS SIMD Architecture"
>> 2515 depends on CPU_SUPPORTS_MSA
>> 2516 depends on MIPS_FP_SUPPORT
>> 2517 depends on 64BIT || MIPS_O32_FP64_SUPPORT
>> 2518 help
>> 2519 MIPS SIMD Architecture (MSA) introduces 128 bit wide vector registers
>> 2520 and a set of SIMD instructions to operate on them. When this option
>> 2521 is enabled the kernel will support allocating & switching MSA
>> 2522 vector register contexts. If you know that your kernel will only be
>> 2523 running on CPUs which do not support MSA or that your userland will
>> 2524 not be making use of it then you may wish to say N here to reduce
>> 2525 the size & complexity of your kernel.
1575 2526
1576 config ARCH_SUPPORTS_CRASH_DUMP !! 2527 If unsure, say Y.
1577 def_bool y <<
1578 2528
1579 config ARCH_HAS_GENERIC_CRASHKERNEL_RESERVATI !! 2529 config CPU_HAS_WB
1580 def_bool CRASH_RESERVE !! 2530 bool
1581 2531
1582 config TRANS_TABLE !! 2532 config XKS01
1583 def_bool y !! 2533 bool
1584 depends on HIBERNATION || KEXEC_CORE <<
1585 2534
1586 config XEN_DOM0 !! 2535 config CPU_HAS_RIXI
1587 def_bool y !! 2536 bool
1588 depends on XEN <<
1589 2537
1590 config XEN !! 2538 config CPU_HAS_LOAD_STORE_LR
1591 bool "Xen guest support on ARM64" !! 2539 bool
1592 depends on ARM64 && OF <<
1593 select SWIOTLB_XEN <<
1594 select PARAVIRT <<
1595 help 2540 help
1596 Say Y if you want to run Linux in a !! 2541 CPU has support for unaligned load and store instructions:
>> 2542 LWL, LWR, SWL, SWR (Load/store word left/right).
>> 2543 LDL, LDR, SDL, SDR (Load/store doubleword left/right, for 64bit systems).
1597 2544
1598 # include/linux/mmzone.h requires the followi <<
1599 # <<
1600 # MAX_PAGE_ORDER + PAGE_SHIFT <= SECTION_SI <<
1601 # 2545 #
1602 # so the maximum value of MAX_PAGE_ORDER is S !! 2546 # Vectored interrupt mode is an R2 feature
1603 # 2547 #
1604 # | SECTION_SIZE_BITS | PAGE_SHIFT | m !! 2548 config CPU_MIPSR2_IRQ_VI
1605 # ----+-------------------+--------------+--- !! 2549 bool
1606 # 4K | 27 | 12 | <<
1607 # 16K | 27 | 14 | <<
1608 # 64K | 29 | 16 | <<
1609 config ARCH_FORCE_MAX_ORDER <<
1610 int <<
1611 default "13" if ARM64_64K_PAGES <<
1612 default "11" if ARM64_16K_PAGES <<
1613 default "10" <<
1614 help <<
1615 The kernel page allocator limits th <<
1616 contiguous allocations. The limit i <<
1617 defines the maximal power of two of <<
1618 allocated as a single contiguous bl <<
1619 overriding the default setting when <<
1620 large blocks of physically contiguo <<
1621 <<
1622 The maximal size of allocation cann <<
1623 section, so the value of MAX_PAGE_O <<
1624 <<
1625 MAX_PAGE_ORDER + PAGE_SHIFT <= SE <<
1626 <<
1627 Don't change if unsure. <<
1628 <<
1629 config UNMAP_KERNEL_AT_EL0 <<
1630 bool "Unmap kernel when running in us <<
1631 default y <<
1632 help <<
1633 Speculation attacks against some hi <<
1634 be used to bypass MMU permission ch <<
1635 userspace. This can be defended aga <<
1636 when running in userspace, mapping <<
1637 via a trampoline page in the vector <<
1638 <<
1639 If unsure, say Y. <<
1640 2550
1641 config MITIGATE_SPECTRE_BRANCH_HISTORY !! 2551 #
1642 bool "Mitigate Spectre style attacks !! 2552 # Extended interrupt mode is an R2 feature
1643 default y !! 2553 #
1644 help !! 2554 config CPU_MIPSR2_IRQ_EI
1645 Speculation attacks against some hi !! 2555 bool
1646 make use of branch history to influ <<
1647 When taking an exception from user- <<
1648 or a firmware call overwrites the b <<
1649 2556
1650 config RODATA_FULL_DEFAULT_ENABLED !! 2557 config CPU_HAS_SYNC
1651 bool "Apply r/o permissions of VM are !! 2558 bool
>> 2559 depends on !CPU_R3000
1652 default y 2560 default y
1653 help <<
1654 Apply read-only attributes of VM ar <<
1655 the backing pages as well. This pre <<
1656 from being modified (inadvertently <<
1657 mapping of the same memory page. Th <<
1658 be turned off at runtime by passing <<
1659 with rodata=full if this option is <<
1660 <<
1661 This requires the linear region to <<
1662 which may adversely affect performa <<
1663 2561
1664 config ARM64_SW_TTBR0_PAN !! 2562 #
1665 bool "Emulate Privileged Access Never !! 2563 # CPU non-features
1666 depends on !KCSAN !! 2564 #
1667 help !! 2565 config CPU_DADDI_WORKAROUNDS
1668 Enabling this option prevents the k !! 2566 bool
1669 user-space memory directly by point <<
1670 zeroed area and reserved ASID. The <<
1671 restore the valid TTBR0_EL1 tempora <<
1672 2567
1673 config ARM64_TAGGED_ADDR_ABI !! 2568 config CPU_R4000_WORKAROUNDS
1674 bool "Enable the tagged user addresse !! 2569 bool
1675 default y !! 2570 select CPU_R4400_WORKAROUNDS
1676 help <<
1677 When this option is enabled, user a <<
1678 relaxed ABI via prctl() allowing ta <<
1679 to system calls as pointer argument <<
1680 Documentation/arch/arm64/tagged-add <<
1681 2571
1682 menuconfig COMPAT !! 2572 config CPU_R4400_WORKAROUNDS
1683 bool "Kernel support for 32-bit EL0" !! 2573 bool
1684 depends on ARM64_4K_PAGES || EXPERT <<
1685 select HAVE_UID16 <<
1686 select OLD_SIGSUSPEND3 <<
1687 select COMPAT_OLD_SIGACTION <<
1688 help <<
1689 This option enables support for a 3 <<
1690 kernel at EL1. AArch32-specific com <<
1691 the user helper functions, VFP supp <<
1692 handled appropriately by the kernel <<
1693 2574
1694 If you use a page size other than 4 !! 2575 config MIPS_ASID_SHIFT
1695 that you will only be able to execu !! 2576 int
1696 with page size aligned segments. !! 2577 default 6 if CPU_R3000 || CPU_TX39XX
>> 2578 default 4 if CPU_R8000
>> 2579 default 0
1697 2580
1698 If you want to execute 32-bit users !! 2581 config MIPS_ASID_BITS
>> 2582 int
>> 2583 default 0 if MIPS_ASID_BITS_VARIABLE
>> 2584 default 6 if CPU_R3000 || CPU_TX39XX
>> 2585 default 8
1699 2586
1700 if COMPAT !! 2587 config MIPS_ASID_BITS_VARIABLE
>> 2588 bool
1701 2589
1702 config KUSER_HELPERS !! 2590 config MIPS_CRC_SUPPORT
1703 bool "Enable kuser helpers page for 3 !! 2591 bool
1704 default y <<
1705 help <<
1706 Warning: disabling this option may <<
1707 2592
1708 Provide kuser helpers to compat tas !! 2593 #
1709 helper code to userspace in read on !! 2594 # - Highmem only makes sense for the 32-bit kernel.
1710 to allow userspace to be independen !! 2595 # - The current highmem code will only work properly on physically indexed
1711 the system. This permits binaries t !! 2596 # caches such as R3000, SB1, R7000 or those that look like they're virtually
1712 to ARMv8 without modification. !! 2597 # indexed such as R4000/R4400 SC and MC versions or R10000. So for the
>> 2598 # moment we protect the user and offer the highmem option only on machines
>> 2599 # where it's known to be safe. This will not offer highmem on a few systems
>> 2600 # such as MIPS32 and MIPS64 CPUs which may have virtual and physically
>> 2601 # indexed CPUs but we're playing safe.
>> 2602 # - We use SYS_SUPPORTS_HIGHMEM to offer highmem only for systems where we
>> 2603 # know they might have memory configurations that could make use of highmem
>> 2604 # support.
>> 2605 #
>> 2606 config HIGHMEM
>> 2607 bool "High Memory Support"
>> 2608 depends on 32BIT && CPU_SUPPORTS_HIGHMEM && SYS_SUPPORTS_HIGHMEM && !CPU_MIPS32_3_5_EVA
1713 2609
1714 See Documentation/arch/arm/kernel_u !! 2610 config CPU_SUPPORTS_HIGHMEM
>> 2611 bool
1715 2612
1716 However, the fixed address nature o !! 2613 config SYS_SUPPORTS_HIGHMEM
1717 by ROP (return orientated programmi !! 2614 bool
1718 exploits. <<
1719 2615
1720 If all of the binaries and librarie !! 2616 config SYS_SUPPORTS_SMARTMIPS
1721 are built specifically for your pla !! 2617 bool
1722 these helpers, then you can turn th <<
1723 such exploits. However, in that cas <<
1724 relying on those helpers is run, it <<
1725 2618
1726 Say N here only if you are absolute !! 2619 config SYS_SUPPORTS_MICROMIPS
1727 need these helpers; otherwise, the !! 2620 bool
1728 2621
1729 config COMPAT_VDSO !! 2622 config SYS_SUPPORTS_MIPS16
1730 bool "Enable vDSO for 32-bit applicat !! 2623 bool
1731 depends on !CPU_BIG_ENDIAN <<
1732 depends on (CC_IS_CLANG && LD_IS_LLD) <<
1733 select GENERIC_COMPAT_VDSO <<
1734 default y <<
1735 help 2624 help
1736 Place in the process address space !! 2625 This option must be set if a kernel might be executed on a MIPS16-
1737 ELF shared object providing fast im !! 2626 enabled CPU even if MIPS16 is not actually being used. In other
1738 and clock_gettime. !! 2627 words, it makes the kernel MIPS16-tolerant.
1739 2628
1740 You must have a 32-bit build of gli !! 2629 config CPU_SUPPORTS_MSA
1741 to seamlessly take advantage of thi !! 2630 bool
1742 <<
1743 config THUMB2_COMPAT_VDSO <<
1744 bool "Compile the 32-bit vDSO for Thu <<
1745 depends on COMPAT_VDSO <<
1746 default y <<
1747 help <<
1748 Compile the compat vDSO with '-mthu <<
1749 otherwise with '-marm'. <<
1750 2631
1751 config COMPAT_ALIGNMENT_FIXUPS !! 2632 config ARCH_FLATMEM_ENABLE
1752 bool "Fix up misaligned multi-word lo !! 2633 def_bool y
>> 2634 depends on !NUMA && !CPU_LOONGSON2
1753 2635
1754 menuconfig ARMV8_DEPRECATED !! 2636 config ARCH_DISCONTIGMEM_ENABLE
1755 bool "Emulate deprecated/obsolete ARM !! 2637 bool
1756 depends on SYSCTL !! 2638 default y if SGI_IP27
1757 help 2639 help
1758 Legacy software support may require !! 2640 Say Y to support efficient handling of discontiguous physical memory,
1759 that have been deprecated or obsole !! 2641 for architectures which are either NUMA (Non-Uniform Memory Access)
>> 2642 or have huge holes in the physical address space for other reasons.
>> 2643 See <file:Documentation/vm/numa.rst> for more.
1760 2644
1761 Enable this config to enable select !! 2645 config ARCH_SPARSEMEM_ENABLE
1762 features. !! 2646 bool
1763 !! 2647 select SPARSEMEM_STATIC
1764 If unsure, say Y <<
1765 <<
1766 if ARMV8_DEPRECATED <<
1767 2648
1768 config SWP_EMULATION !! 2649 config NUMA
1769 bool "Emulate SWP/SWPB instructions" !! 2650 bool "NUMA Support"
>> 2651 depends on SYS_SUPPORTS_NUMA
1770 help 2652 help
1771 ARMv8 obsoletes the use of A32 SWP/ !! 2653 Say Y to compile the kernel to support NUMA (Non-Uniform Memory
1772 they are always undefined. Say Y he !! 2654 Access). This option improves performance on systems with more
1773 emulation of these instructions for !! 2655 than two nodes; on two node systems it is generally better to
1774 This feature can be controlled at r !! 2656 leave it disabled; on single node systems disable this option
1775 sysctl which is disabled by default !! 2657 disabled.
1776 <<
1777 In some older versions of glibc [<= <<
1778 trylock() operations with the assum <<
1779 be preempted. This invalid assumpti <<
1780 with SWP emulation enabled, leading <<
1781 application. <<
1782 2658
1783 NOTE: when accessing uncached share !! 2659 config SYS_SUPPORTS_NUMA
1784 on an external transaction monitori !! 2660 bool
1785 monitor to maintain update atomicit <<
1786 implement a global monitor, this op <<
1787 perform SWP operations to uncached <<
1788 <<
1789 If unsure, say Y <<
1790 2661
1791 config CP15_BARRIER_EMULATION !! 2662 config RELOCATABLE
1792 bool "Emulate CP15 Barrier instructio !! 2663 bool "Relocatable kernel"
>> 2664 depends on SYS_SUPPORTS_RELOCATABLE && (CPU_MIPS32_R2 || CPU_MIPS64_R2 || CPU_MIPS32_R6 || CPU_MIPS64_R6 || CAVIUM_OCTEON_SOC)
1793 help 2665 help
1794 The CP15 barrier instructions - CP1 !! 2666 This builds a kernel image that retains relocation information
1795 CP15DMB - are deprecated in ARMv8 ( !! 2667 so it can be loaded someplace besides the default 1MB.
1796 strongly recommended to use the ISB !! 2668 The relocations make the kernel binary about 15% larger,
1797 instructions instead. !! 2669 but are discarded at runtime
>> 2670
>> 2671 config RELOCATION_TABLE_SIZE
>> 2672 hex "Relocation table size"
>> 2673 depends on RELOCATABLE
>> 2674 range 0x0 0x01000000
>> 2675 default "0x00100000"
>> 2676 ---help---
>> 2677 A table of relocation data will be appended to the kernel binary
>> 2678 and parsed at boot to fix up the relocated kernel.
1798 2679
1799 Say Y here to enable software emula !! 2680 This option allows the amount of space reserved for the table to be
1800 instructions for AArch32 userspace !! 2681 adjusted, although the default of 1Mb should be ok in most cases.
1801 enabled, CP15 barrier usage is trac <<
1802 identify software that needs updati <<
1803 controlled at runtime with the abi. <<
1804 2682
1805 If unsure, say Y !! 2683 The build will fail and a valid size suggested if this is too small.
1806 2684
1807 config SETEND_EMULATION !! 2685 If unsure, leave at the default value.
1808 bool "Emulate SETEND instruction" <<
1809 help <<
1810 The SETEND instruction alters the d <<
1811 AArch32 EL0, and is deprecated in A <<
1812 2686
1813 Say Y here to enable software emula !! 2687 config RANDOMIZE_BASE
1814 for AArch32 userspace code. This fe !! 2688 bool "Randomize the address of the kernel image"
1815 at runtime with the abi.setend sysc !! 2689 depends on RELOCATABLE
>> 2690 ---help---
>> 2691 Randomizes the physical and virtual address at which the
>> 2692 kernel image is loaded, as a security feature that
>> 2693 deters exploit attempts relying on knowledge of the location
>> 2694 of kernel internals.
1816 2695
1817 Note: All the cpus on the system mu !! 2696 Entropy is generated using any coprocessor 0 registers available.
1818 for this feature to be enabled. If <<
1819 endian - is hotplugged in after thi <<
1820 be unexpected results in the applic <<
1821 2697
1822 If unsure, say Y !! 2698 The kernel will be offset by up to RANDOMIZE_BASE_MAX_OFFSET.
1823 endif # ARMV8_DEPRECATED <<
1824 2699
1825 endif # COMPAT !! 2700 If unsure, say N.
1826 2701
1827 menu "ARMv8.1 architectural features" !! 2702 config RANDOMIZE_BASE_MAX_OFFSET
>> 2703 hex "Maximum kASLR offset" if EXPERT
>> 2704 depends on RANDOMIZE_BASE
>> 2705 range 0x0 0x40000000 if EVA || 64BIT
>> 2706 range 0x0 0x08000000
>> 2707 default "0x01000000"
>> 2708 ---help---
>> 2709 When kASLR is active, this provides the maximum offset that will
>> 2710 be applied to the kernel image. It should be set according to the
>> 2711 amount of physical RAM available in the target system minus
>> 2712 PHYSICAL_START and must be a power of 2.
1828 2713
1829 config ARM64_HW_AFDBM !! 2714 This is limited by the size of KSEG0, 256Mb on 32-bit or 1Gb with
1830 bool "Support for hardware updates of !! 2715 EVA or 64-bit. The default is 16Mb.
1831 default y <<
1832 help <<
1833 The ARMv8.1 architecture extensions <<
1834 hardware updates of the access and <<
1835 table entries. When enabled in TCR_ <<
1836 capable processors, accesses to pag <<
1837 set this bit instead of raising an <<
1838 Similarly, writes to read-only page <<
1839 clear the read-only bit (AP[2]) ins <<
1840 permission fault. <<
1841 2716
1842 Kernels built with this configurati !! 2717 config NODES_SHIFT
1843 to work on pre-ARMv8.1 hardware and !! 2718 int
1844 minimal. If unsure, say Y. !! 2719 default "6"
>> 2720 depends on NEED_MULTIPLE_NODES
1845 2721
1846 config ARM64_PAN !! 2722 config HW_PERF_EVENTS
1847 bool "Enable support for Privileged A !! 2723 bool "Enable hardware performance counter support for perf events"
>> 2724 depends on PERF_EVENTS && !OPROFILE && (CPU_MIPS32 || CPU_MIPS64 || CPU_R10000 || CPU_SB1 || CPU_CAVIUM_OCTEON || CPU_XLP || CPU_LOONGSON3)
1848 default y 2725 default y
1849 help 2726 help
1850 Privileged Access Never (PAN; part !! 2727 Enable hardware performance counter support for perf events. If
1851 prevents the kernel or hypervisor f !! 2728 disabled, perf events will use software events only.
1852 memory directly. <<
1853 2729
1854 Choosing this option will cause any !! 2730 config SMP
1855 copy_to_user et al) memory access t !! 2731 bool "Multi-Processing support"
>> 2732 depends on SYS_SUPPORTS_SMP
>> 2733 help
>> 2734 This enables support for systems with more than one CPU. If you have
>> 2735 a system with only one CPU, say N. If you have a system with more
>> 2736 than one CPU, say Y.
>> 2737
>> 2738 If you say N here, the kernel will run on uni- and multiprocessor
>> 2739 machines, but will use only one CPU of a multiprocessor machine. If
>> 2740 you say Y here, the kernel will run on many, but not all,
>> 2741 uniprocessor machines. On a uniprocessor machine, the kernel
>> 2742 will run faster if you say N here.
1856 2743
1857 The feature is detected at runtime, !! 2744 People using multiprocessor machines who say Y here should also say
1858 instruction if the cpu does not imp !! 2745 Y to "Enhanced Real Time Clock Support", below.
1859 2746
1860 config AS_HAS_LSE_ATOMICS !! 2747 See also the SMP-HOWTO available at
1861 def_bool $(as-instr,.arch_extension l !! 2748 <http://www.tldp.org/docs.html#howto>.
1862 2749
1863 config ARM64_LSE_ATOMICS !! 2750 If you don't know what to do here, say N.
1864 bool <<
1865 default ARM64_USE_LSE_ATOMICS <<
1866 depends on AS_HAS_LSE_ATOMICS <<
1867 2751
1868 config ARM64_USE_LSE_ATOMICS !! 2752 config HOTPLUG_CPU
1869 bool "Atomic instructions" !! 2753 bool "Support for hot-pluggable CPUs"
1870 default y !! 2754 depends on SMP && SYS_SUPPORTS_HOTPLUG_CPU
1871 help 2755 help
1872 As part of the Large System Extensi !! 2756 Say Y here to allow turning CPUs off and on. CPUs can be
1873 atomic instructions that are design !! 2757 controlled through /sys/devices/system/cpu.
1874 very large systems. !! 2758 (Note: power management support will enable this option
>> 2759 automatically on SMP systems. )
>> 2760 Say N if you want to disable CPU hotplug.
1875 2761
1876 Say Y here to make use of these ins !! 2762 config SMP_UP
1877 atomic routines. This incurs a smal !! 2763 bool
1878 not support these instructions and <<
1879 built with binutils >= 2.25 in orde <<
1880 to be used. <<
1881 2764
1882 endmenu # "ARMv8.1 architectural features" !! 2765 config SYS_SUPPORTS_MIPS_CMP
>> 2766 bool
1883 2767
1884 menu "ARMv8.2 architectural features" !! 2768 config SYS_SUPPORTS_MIPS_CPS
>> 2769 bool
1885 2770
1886 config AS_HAS_ARMV8_2 !! 2771 config SYS_SUPPORTS_SMP
1887 def_bool $(cc-option,-Wa$(comma)-marc !! 2772 bool
1888 2773
1889 config AS_HAS_SHA3 !! 2774 config NR_CPUS_DEFAULT_4
1890 def_bool $(as-instr,.arch armv8.2-a+s !! 2775 bool
1891 2776
1892 config ARM64_PMEM !! 2777 config NR_CPUS_DEFAULT_8
1893 bool "Enable support for persistent m !! 2778 bool
1894 select ARCH_HAS_PMEM_API <<
1895 select ARCH_HAS_UACCESS_FLUSHCACHE <<
1896 help <<
1897 Say Y to enable support for the per <<
1898 ARMv8.2 DCPoP feature. <<
1899 2779
1900 The feature is detected at runtime, !! 2780 config NR_CPUS_DEFAULT_16
1901 operations if DC CVAP is not suppor !! 2781 bool
1902 DC CVAP itself if the system does n <<
1903 2782
1904 config ARM64_RAS_EXTN !! 2783 config NR_CPUS_DEFAULT_32
1905 bool "Enable support for RAS CPU Exte !! 2784 bool
1906 default y <<
1907 help <<
1908 CPUs that support the Reliability, <<
1909 (RAS) Extensions, part of ARMv8.2 a <<
1910 errors, classify them and report th <<
1911 2785
1912 On CPUs with these extensions syste !! 2786 config NR_CPUS_DEFAULT_64
1913 barriers to determine if faults are !! 2787 bool
1914 classification from a new set of re <<
1915 2788
1916 Selecting this feature will allow t !! 2789 config NR_CPUS
1917 and access the new registers if the !! 2790 int "Maximum number of CPUs (2-256)"
1918 Platform RAS features may additiona !! 2791 range 2 256
>> 2792 depends on SMP
>> 2793 default "4" if NR_CPUS_DEFAULT_4
>> 2794 default "8" if NR_CPUS_DEFAULT_8
>> 2795 default "16" if NR_CPUS_DEFAULT_16
>> 2796 default "32" if NR_CPUS_DEFAULT_32
>> 2797 default "64" if NR_CPUS_DEFAULT_64
>> 2798 help
>> 2799 This allows you to specify the maximum number of CPUs which this
>> 2800 kernel will support. The maximum supported value is 32 for 32-bit
>> 2801 kernel and 64 for 64-bit kernels; the minimum value which makes
>> 2802 sense is 1 for Qemu (useful only for kernel debugging purposes)
>> 2803 and 2 for all others.
>> 2804
>> 2805 This is purely to save memory - each supported CPU adds
>> 2806 approximately eight kilobytes to the kernel image. For best
>> 2807 performance should round up your number of processors to the next
>> 2808 power of two.
1919 2809
1920 config ARM64_CNP !! 2810 config MIPS_PERF_SHARED_TC_COUNTERS
1921 bool "Enable support for Common Not P !! 2811 bool
1922 default y <<
1923 depends on ARM64_PAN || !ARM64_SW_TTB <<
1924 help <<
1925 Common Not Private (CNP) allows tra <<
1926 be shared between different PEs in <<
1927 domain, so the hardware can use thi <<
1928 caching of such entries in the TLB. <<
1929 2812
1930 Selecting this option allows the CN !! 2813 config MIPS_NR_CPU_NR_MAP_1024
1931 at runtime, and does not affect PEs !! 2814 bool
1932 this feature. <<
1933 2815
1934 endmenu # "ARMv8.2 architectural features" !! 2816 config MIPS_NR_CPU_NR_MAP
>> 2817 int
>> 2818 depends on SMP
>> 2819 default 1024 if MIPS_NR_CPU_NR_MAP_1024
>> 2820 default NR_CPUS if !MIPS_NR_CPU_NR_MAP_1024
1935 2821
1936 menu "ARMv8.3 architectural features" !! 2822 #
>> 2823 # Timer Interrupt Frequency Configuration
>> 2824 #
1937 2825
1938 config ARM64_PTR_AUTH !! 2826 choice
1939 bool "Enable support for pointer auth !! 2827 prompt "Timer frequency"
1940 default y !! 2828 default HZ_250
1941 help 2829 help
1942 Pointer authentication (part of the !! 2830 Allows the configuration of the timer frequency.
1943 instructions for signing and authen <<
1944 keys, which can be used to mitigate <<
1945 and other attacks. <<
1946 2831
1947 This option enables these instructi !! 2832 config HZ_24
1948 Choosing this option will cause the !! 2833 bool "24 HZ" if SYS_SUPPORTS_24HZ || SYS_SUPPORTS_ARBIT_HZ
1949 for each process at exec() time, wi <<
1950 context-switched along with the pro <<
1951 2834
1952 The feature is detected at runtime. !! 2835 config HZ_48
1953 hardware it will not be advertised !! 2836 bool "48 HZ" if SYS_SUPPORTS_48HZ || SYS_SUPPORTS_ARBIT_HZ
1954 be enabled. <<
1955 2837
1956 If the feature is present on the bo !! 2838 config HZ_100
1957 the late CPU will be parked. Also, !! 2839 bool "100 HZ" if SYS_SUPPORTS_100HZ || SYS_SUPPORTS_ARBIT_HZ
1958 address auth and the late CPU has t <<
1959 but with the feature disabled. On s <<
1960 not be selected. <<
1961 2840
1962 config ARM64_PTR_AUTH_KERNEL !! 2841 config HZ_128
1963 bool "Use pointer authentication for !! 2842 bool "128 HZ" if SYS_SUPPORTS_128HZ || SYS_SUPPORTS_ARBIT_HZ
1964 default y <<
1965 depends on ARM64_PTR_AUTH <<
1966 depends on (CC_HAS_SIGN_RETURN_ADDRES <<
1967 # Modern compilers insert a .note.gnu <<
1968 # which is only understood by binutil <<
1969 depends on LD_IS_LLD || LD_VERSION >= <<
1970 depends on !CC_IS_CLANG || AS_HAS_CFI <<
1971 depends on (!FUNCTION_GRAPH_TRACER || <<
1972 help <<
1973 If the compiler supports the -mbran <<
1974 -msign-return-address flag (e.g. GC <<
1975 will cause the kernel itself to be <<
1976 protection. In this case, and if th <<
1977 support pointer authentication, the <<
1978 disabled with minimal loss of prote <<
1979 2843
1980 This feature works with FUNCTION_GR !! 2844 config HZ_250
1981 DYNAMIC_FTRACE_WITH_ARGS is enabled !! 2845 bool "250 HZ" if SYS_SUPPORTS_250HZ || SYS_SUPPORTS_ARBIT_HZ
1982 2846
1983 config CC_HAS_BRANCH_PROT_PAC_RET !! 2847 config HZ_256
1984 # GCC 9 or later, clang 8 or later !! 2848 bool "256 HZ" if SYS_SUPPORTS_256HZ || SYS_SUPPORTS_ARBIT_HZ
1985 def_bool $(cc-option,-mbranch-protect <<
1986 2849
1987 config CC_HAS_SIGN_RETURN_ADDRESS !! 2850 config HZ_1000
1988 # GCC 7, 8 !! 2851 bool "1000 HZ" if SYS_SUPPORTS_1000HZ || SYS_SUPPORTS_ARBIT_HZ
1989 def_bool $(cc-option,-msign-return-ad <<
1990 2852
1991 config AS_HAS_ARMV8_3 !! 2853 config HZ_1024
1992 def_bool $(cc-option,-Wa$(comma)-marc !! 2854 bool "1024 HZ" if SYS_SUPPORTS_1024HZ || SYS_SUPPORTS_ARBIT_HZ
1993 2855
1994 config AS_HAS_CFI_NEGATE_RA_STATE !! 2856 endchoice
1995 def_bool $(as-instr,.cfi_startproc\n. <<
1996 <<
1997 config AS_HAS_LDAPR <<
1998 def_bool $(as-instr,.arch_extension r <<
1999 2857
2000 endmenu # "ARMv8.3 architectural features" !! 2858 config SYS_SUPPORTS_24HZ
>> 2859 bool
2001 2860
2002 menu "ARMv8.4 architectural features" !! 2861 config SYS_SUPPORTS_48HZ
>> 2862 bool
2003 2863
2004 config ARM64_AMU_EXTN !! 2864 config SYS_SUPPORTS_100HZ
2005 bool "Enable support for the Activity !! 2865 bool
2006 default y <<
2007 help <<
2008 The activity monitors extension is <<
2009 by the ARMv8.4 CPU architecture. Th <<
2010 of the activity monitors architectu <<
2011 2866
2012 To enable the use of this extension !! 2867 config SYS_SUPPORTS_128HZ
>> 2868 bool
2013 2869
2014 Note that for architectural reasons !! 2870 config SYS_SUPPORTS_250HZ
2015 support when running on CPUs that p !! 2871 bool
2016 extension. The required support is <<
2017 * Version 1.5 and later of the AR <<
2018 2872
2019 For kernels that have this configur !! 2873 config SYS_SUPPORTS_256HZ
2020 firmware, you may need to say N her !! 2874 bool
2021 Otherwise you may experience firmwa <<
2022 accessing the counter registers. Ev <<
2023 symptoms, the values returned by th <<
2024 correctly reflect reality. Most com <<
2025 indicating that the counter is not <<
2026 2875
2027 config AS_HAS_ARMV8_4 !! 2876 config SYS_SUPPORTS_1000HZ
2028 def_bool $(cc-option,-Wa$(comma)-marc !! 2877 bool
2029 2878
2030 config ARM64_TLB_RANGE !! 2879 config SYS_SUPPORTS_1024HZ
2031 bool "Enable support for tlbi range f !! 2880 bool
2032 default y <<
2033 depends on AS_HAS_ARMV8_4 <<
2034 help <<
2035 ARMv8.4-TLBI provides TLBI invalida <<
2036 range of input addresses. <<
2037 2881
2038 The feature introduces new assembly !! 2882 config SYS_SUPPORTS_ARBIT_HZ
2039 support when binutils >= 2.30. !! 2883 bool
>> 2884 default y if !SYS_SUPPORTS_24HZ && \
>> 2885 !SYS_SUPPORTS_48HZ && \
>> 2886 !SYS_SUPPORTS_100HZ && \
>> 2887 !SYS_SUPPORTS_128HZ && \
>> 2888 !SYS_SUPPORTS_250HZ && \
>> 2889 !SYS_SUPPORTS_256HZ && \
>> 2890 !SYS_SUPPORTS_1000HZ && \
>> 2891 !SYS_SUPPORTS_1024HZ
2040 2892
2041 endmenu # "ARMv8.4 architectural features" !! 2893 config HZ
>> 2894 int
>> 2895 default 24 if HZ_24
>> 2896 default 48 if HZ_48
>> 2897 default 100 if HZ_100
>> 2898 default 128 if HZ_128
>> 2899 default 250 if HZ_250
>> 2900 default 256 if HZ_256
>> 2901 default 1000 if HZ_1000
>> 2902 default 1024 if HZ_1024
>> 2903
>> 2904 config SCHED_HRTICK
>> 2905 def_bool HIGH_RES_TIMERS
>> 2906
>> 2907 config KEXEC
>> 2908 bool "Kexec system call"
>> 2909 select KEXEC_CORE
>> 2910 help
>> 2911 kexec is a system call that implements the ability to shutdown your
>> 2912 current kernel, and to start another kernel. It is like a reboot
>> 2913 but it is independent of the system firmware. And like a reboot
>> 2914 you can start any kernel with it, not just Linux.
>> 2915
>> 2916 The name comes from the similarity to the exec system call.
>> 2917
>> 2918 It is an ongoing process to be certain the hardware in a machine
>> 2919 is properly shutdown, so do not be surprised if this code does not
>> 2920 initially work for you. As of this writing the exact hardware
>> 2921 interface is strongly in flux, so no good recommendation can be
>> 2922 made.
>> 2923
>> 2924 config CRASH_DUMP
>> 2925 bool "Kernel crash dumps"
>> 2926 help
>> 2927 Generate crash dump after being started by kexec.
>> 2928 This should be normally only set in special crash dump kernels
>> 2929 which are loaded in the main kernel with kexec-tools into
>> 2930 a specially reserved region and then later executed after
>> 2931 a crash by kdump/kexec. The crash dump kernel must be compiled
>> 2932 to a memory address not used by the main kernel or firmware using
>> 2933 PHYSICAL_START.
>> 2934
>> 2935 config PHYSICAL_START
>> 2936 hex "Physical address where the kernel is loaded"
>> 2937 default "0xffffffff84000000"
>> 2938 depends on CRASH_DUMP
>> 2939 help
>> 2940 This gives the CKSEG0 or KSEG0 address where the kernel is loaded.
>> 2941 If you plan to use kernel for capturing the crash dump change
>> 2942 this value to start of the reserved region (the "X" value as
>> 2943 specified in the "crashkernel=YM@XM" command line boot parameter
>> 2944 passed to the panic-ed kernel).
>> 2945
>> 2946 config SECCOMP
>> 2947 bool "Enable seccomp to safely compute untrusted bytecode"
>> 2948 depends on PROC_FS
>> 2949 default y
>> 2950 help
>> 2951 This kernel feature is useful for number crunching applications
>> 2952 that may need to compute untrusted bytecode during their
>> 2953 execution. By using pipes or other transports made available to
>> 2954 the process as file descriptors supporting the read/write
>> 2955 syscalls, it's possible to isolate those applications in
>> 2956 their own address space using seccomp. Once seccomp is
>> 2957 enabled via /proc/<pid>/seccomp, it cannot be disabled
>> 2958 and the task is only allowed to execute a few safe syscalls
>> 2959 defined by each seccomp mode.
>> 2960
>> 2961 If unsure, say Y. Only embedded should say N here.
>> 2962
>> 2963 config MIPS_O32_FP64_SUPPORT
>> 2964 bool "Support for O32 binaries using 64-bit FP" if !CPU_MIPSR6
>> 2965 depends on 32BIT || MIPS32_O32
>> 2966 help
>> 2967 When this is enabled, the kernel will support use of 64-bit floating
>> 2968 point registers with binaries using the O32 ABI along with the
>> 2969 EF_MIPS_FP64 ELF header flag (typically built with -mfp64). On
>> 2970 32-bit MIPS systems this support is at the cost of increasing the
>> 2971 size and complexity of the compiled FPU emulator. Thus if you are
>> 2972 running a MIPS32 system and know that none of your userland binaries
>> 2973 will require 64-bit floating point, you may wish to reduce the size
>> 2974 of your kernel & potentially improve FP emulation performance by
>> 2975 saying N here.
>> 2976
>> 2977 Although binutils currently supports use of this flag the details
>> 2978 concerning its effect upon the O32 ABI in userland are still being
>> 2979 worked on. In order to avoid userland becoming dependant upon current
>> 2980 behaviour before the details have been finalised, this option should
>> 2981 be considered experimental and only enabled by those working upon
>> 2982 said details.
2042 2983
2043 menu "ARMv8.5 architectural features" !! 2984 If unsure, say N.
2044 2985
2045 config AS_HAS_ARMV8_5 !! 2986 config USE_OF
2046 def_bool $(cc-option,-Wa$(comma)-marc !! 2987 bool
>> 2988 select OF
>> 2989 select OF_EARLY_FLATTREE
>> 2990 select IRQ_DOMAIN
2047 2991
2048 config ARM64_BTI !! 2992 config UHI_BOOT
2049 bool "Branch Target Identification su !! 2993 bool
2050 default y <<
2051 help <<
2052 Branch Target Identification (part <<
2053 provides a mechanism to limit the s <<
2054 branch instructions such as BR or B <<
2055 2994
2056 To make use of BTI on CPUs that sup !! 2995 config BUILTIN_DTB
>> 2996 bool
2057 2997
2058 BTI is intended to provide compleme !! 2998 choice
2059 flow integrity protection mechanism !! 2999 prompt "Kernel appended dtb support" if USE_OF
2060 authentication mechanism provided a !! 3000 default MIPS_NO_APPENDED_DTB
2061 For this reason, it does not make s <<
2062 also enabling support for pointer a <<
2063 enabling this option you should als <<
2064 3001
2065 Userspace binaries must also be spe !! 3002 config MIPS_NO_APPENDED_DTB
2066 this mechanism. If you say N here !! 3003 bool "None"
2067 BTI, such binaries can still run, b !! 3004 help
2068 enforcement of branch destinations. !! 3005 Do not enable appended dtb support.
>> 3006
>> 3007 config MIPS_ELF_APPENDED_DTB
>> 3008 bool "vmlinux"
>> 3009 help
>> 3010 With this option, the boot code will look for a device tree binary
>> 3011 DTB) included in the vmlinux ELF section .appended_dtb. By default
>> 3012 it is empty and the DTB can be appended using binutils command
>> 3013 objcopy:
>> 3014
>> 3015 objcopy --update-section .appended_dtb=<filename>.dtb vmlinux
>> 3016
>> 3017 This is meant as a backward compatiblity convenience for those
>> 3018 systems with a bootloader that can't be upgraded to accommodate
>> 3019 the documented boot protocol using a device tree.
>> 3020
>> 3021 config MIPS_RAW_APPENDED_DTB
>> 3022 bool "vmlinux.bin or vmlinuz.bin"
>> 3023 help
>> 3024 With this option, the boot code will look for a device tree binary
>> 3025 DTB) appended to raw vmlinux.bin or vmlinuz.bin.
>> 3026 (e.g. cat vmlinux.bin <filename>.dtb > vmlinux_w_dtb).
>> 3027
>> 3028 This is meant as a backward compatibility convenience for those
>> 3029 systems with a bootloader that can't be upgraded to accommodate
>> 3030 the documented boot protocol using a device tree.
>> 3031
>> 3032 Beware that there is very little in terms of protection against
>> 3033 this option being confused by leftover garbage in memory that might
>> 3034 look like a DTB header after a reboot if no actual DTB is appended
>> 3035 to vmlinux.bin. Do not leave this option active in a production kernel
>> 3036 if you don't intend to always append a DTB.
>> 3037 endchoice
2069 3038
2070 config ARM64_BTI_KERNEL !! 3039 choice
2071 bool "Use Branch Target Identificatio !! 3040 prompt "Kernel command line type" if !CMDLINE_OVERRIDE
2072 default y !! 3041 default MIPS_CMDLINE_FROM_DTB if USE_OF && !ATH79 && !MACH_INGENIC && \
2073 depends on ARM64_BTI !! 3042 !MIPS_MALTA && \
2074 depends on ARM64_PTR_AUTH_KERNEL !! 3043 !CAVIUM_OCTEON_SOC
2075 depends on CC_HAS_BRANCH_PROT_PAC_RET !! 3044 default MIPS_CMDLINE_FROM_BOOTLOADER
2076 # https://gcc.gnu.org/bugzilla/show_b !! 3045
2077 depends on !CC_IS_GCC || GCC_VERSION !! 3046 config MIPS_CMDLINE_FROM_DTB
2078 # https://gcc.gnu.org/bugzilla/show_b !! 3047 depends on USE_OF
2079 depends on !CC_IS_GCC !! 3048 bool "Dtb kernel arguments if available"
2080 depends on (!FUNCTION_GRAPH_TRACER || !! 3049
2081 help !! 3050 config MIPS_CMDLINE_DTB_EXTEND
2082 Build the kernel with Branch Target !! 3051 depends on USE_OF
2083 and enable enforcement of this for !! 3052 bool "Extend dtb kernel arguments with bootloader arguments"
2084 is enabled and the system supports !! 3053
2085 modular code must have BTI enabled. !! 3054 config MIPS_CMDLINE_FROM_BOOTLOADER
>> 3055 bool "Bootloader kernel arguments if available"
>> 3056
>> 3057 config MIPS_CMDLINE_BUILTIN_EXTEND
>> 3058 depends on CMDLINE_BOOL
>> 3059 bool "Extend builtin kernel arguments with bootloader arguments"
>> 3060 endchoice
2086 3061
2087 config CC_HAS_BRANCH_PROT_PAC_RET_BTI !! 3062 endmenu
2088 # GCC 9 or later, clang 8 or later <<
2089 def_bool $(cc-option,-mbranch-protect <<
2090 3063
2091 config ARM64_E0PD !! 3064 config LOCKDEP_SUPPORT
2092 bool "Enable support for E0PD" !! 3065 bool
2093 default y 3066 default y
2094 help <<
2095 E0PD (part of the ARMv8.5 extension <<
2096 that EL0 accesses made via TTBR1 al <<
2097 providing similar benefits to KASLR <<
2098 with lower overhead and without dis <<
2099 kernel memory such as SPE. <<
2100 <<
2101 This option enables E0PD for TTBR1 <<
2102 <<
2103 config ARM64_AS_HAS_MTE <<
2104 # Initial support for MTE went in bin <<
2105 # ".arch armv8.5-a+memtag" below. How <<
2106 # as a late addition to the final arc <<
2107 # is only supported in the newer 2.32 <<
2108 # versions, hence the extra "stgm" in <<
2109 def_bool $(as-instr,.arch armv8.5-a+m <<
2110 3067
2111 config ARM64_MTE !! 3068 config STACKTRACE_SUPPORT
2112 bool "Memory Tagging Extension suppor !! 3069 bool
2113 default y 3070 default y
2114 depends on ARM64_AS_HAS_MTE && ARM64_ <<
2115 depends on AS_HAS_ARMV8_5 <<
2116 depends on AS_HAS_LSE_ATOMICS <<
2117 # Required for tag checking in the ua <<
2118 depends on ARM64_PAN <<
2119 select ARCH_HAS_SUBPAGE_FAULTS <<
2120 select ARCH_USES_HIGH_VMA_FLAGS <<
2121 select ARCH_USES_PG_ARCH_2 <<
2122 select ARCH_USES_PG_ARCH_3 <<
2123 help <<
2124 Memory Tagging (part of the ARMv8.5 <<
2125 architectural support for run-time, <<
2126 various classes of memory error to <<
2127 to eliminate vulnerabilities arisin <<
2128 languages. <<
2129 3071
2130 This option enables the support for !! 3072 config HAVE_LATENCYTOP_SUPPORT
2131 Extension at EL0 (i.e. for userspac !! 3073 bool
2132 <<
2133 Selecting this option allows the fe <<
2134 runtime. Any secondary CPU not impl <<
2135 not be allowed a late bring-up. <<
2136 <<
2137 Userspace binaries that want to use <<
2138 explicitly opt in. The mechanism fo <<
2139 described in: <<
2140 <<
2141 Documentation/arch/arm64/memory-tag <<
2142 <<
2143 endmenu # "ARMv8.5 architectural features" <<
2144 <<
2145 menu "ARMv8.7 architectural features" <<
2146 <<
2147 config ARM64_EPAN <<
2148 bool "Enable support for Enhanced Pri <<
2149 default y 3074 default y
2150 depends on ARM64_PAN <<
2151 help <<
2152 Enhanced Privileged Access Never (E <<
2153 Access Never to be used with Execut <<
2154 <<
2155 The feature is detected at runtime, <<
2156 if the cpu does not implement the f <<
2157 endmenu # "ARMv8.7 architectural features" <<
2158 <<
2159 menu "ARMv8.9 architectural features" <<
2160 <<
2161 config ARM64_POE <<
2162 prompt "Permission Overlay Extension" <<
2163 def_bool y <<
2164 select ARCH_USES_HIGH_VMA_FLAGS <<
2165 select ARCH_HAS_PKEYS <<
2166 help <<
2167 The Permission Overlay Extension is <<
2168 Protection Keys. Memory Protection <<
2169 enforcing page-based protections, b <<
2170 of the page tables when an applicat <<
2171 <<
2172 For details, see Documentation/core <<
2173 3075
2174 If unsure, say y. !! 3076 config PGTABLE_LEVELS
2175 <<
2176 config ARCH_PKEY_BITS <<
2177 int 3077 int
2178 default 3 !! 3078 default 4 if PAGE_SIZE_4KB && MIPS_VA_BITS_48
>> 3079 default 3 if 64BIT && !PAGE_SIZE_64KB
>> 3080 default 2
2179 3081
2180 endmenu # "ARMv8.9 architectural features" !! 3082 config MIPS_AUTO_PFN_OFFSET
2181 !! 3083 bool
2182 config ARM64_SVE <<
2183 bool "ARM Scalable Vector Extension s <<
2184 default y <<
2185 help <<
2186 The Scalable Vector Extension (SVE) <<
2187 execution state which complements a <<
2188 of the base architecture to support <<
2189 additional vectorisation opportunit <<
2190 <<
2191 To enable use of this extension on <<
2192 3084
2193 On CPUs that support the SVE2 exten !! 3085 menu "Bus options (PCI, PCMCIA, EISA, ISA, TC)"
2194 those too. <<
2195 3086
2196 Note that for architectural reasons !! 3087 config PCI_DRIVERS_GENERIC
2197 support when running on SVE capable !! 3088 select PCI_DOMAINS_GENERIC if PCI
2198 is present in: !! 3089 bool
2199 3090
2200 * version 1.5 and later of the AR !! 3091 config PCI_DRIVERS_LEGACY
2201 * the AArch64 boot wrapper since !! 3092 def_bool !PCI_DRIVERS_GENERIC
2202 ("bootwrapper: SVE: Enable SVE !! 3093 select NO_GENERIC_PCI_IOPORT_MAP
>> 3094 select PCI_DOMAINS if PCI
2203 3095
2204 For other firmware implementations, !! 3096 #
2205 or vendor. !! 3097 # ISA support is now enabled via select. Too many systems still have the one
>> 3098 # or other ISA chip on the board that users don't know about so don't expect
>> 3099 # users to choose the right thing ...
>> 3100 #
>> 3101 config ISA
>> 3102 bool
2206 3103
2207 If you need the kernel to boot on S !! 3104 config TC
2208 firmware, you may need to say N her !! 3105 bool "TURBOchannel support"
2209 fixed. Otherwise, you may experien !! 3106 depends on MACH_DECSTATION
2210 booting the kernel. If unsure and !! 3107 help
2211 symptoms, you should assume that it !! 3108 TURBOchannel is a DEC (now Compaq (now HP)) bus for Alpha and MIPS
>> 3109 processors. TURBOchannel programming specifications are available
>> 3110 at:
>> 3111 <ftp://ftp.hp.com/pub/alphaserver/archive/triadd/>
>> 3112 and:
>> 3113 <http://www.computer-refuge.org/classiccmp/ftp.digital.com/pub/DEC/TriAdd/>
>> 3114 Linux driver support status is documented at:
>> 3115 <http://www.linux-mips.org/wiki/DECstation>
2212 3116
2213 config ARM64_SME !! 3117 config MMU
2214 bool "ARM Scalable Matrix Extension s !! 3118 bool
2215 default y 3119 default y
2216 depends on ARM64_SVE <<
2217 depends on BROKEN <<
2218 help <<
2219 The Scalable Matrix Extension (SME) <<
2220 execution state which utilises a su <<
2221 instruction set, together with the <<
2222 register state capable of holding t <<
2223 enable various matrix operations. <<
2224 <<
2225 config ARM64_PSEUDO_NMI <<
2226 bool "Support for NMI-like interrupts <<
2227 select ARM_GIC_V3 <<
2228 help <<
2229 Adds support for mimicking Non-Mask <<
2230 GIC interrupt priority. This suppor <<
2231 ARM GIC. <<
2232 <<
2233 This high priority configuration fo <<
2234 explicitly enabled by setting the k <<
2235 "irqchip.gicv3_pseudo_nmi" to 1. <<
2236 <<
2237 If unsure, say N <<
2238 3120
2239 if ARM64_PSEUDO_NMI !! 3121 config ARCH_MMAP_RND_BITS_MIN
2240 config ARM64_DEBUG_PRIORITY_MASKING !! 3122 default 12 if 64BIT
2241 bool "Debug interrupt priority maskin !! 3123 default 8
2242 help <<
2243 This adds runtime checks to functio <<
2244 interrupts when using priority mask <<
2245 the validity of ICC_PMR_EL1 when ca <<
2246 <<
2247 If unsure, say N <<
2248 endif # ARM64_PSEUDO_NMI <<
2249 3124
2250 config RELOCATABLE !! 3125 config ARCH_MMAP_RND_BITS_MAX
2251 bool "Build a relocatable kernel imag !! 3126 default 18 if 64BIT
2252 select ARCH_HAS_RELR !! 3127 default 15
2253 default y <<
2254 help <<
2255 This builds the kernel as a Positio <<
2256 which retains all relocation metada <<
2257 kernel binary at runtime to a diffe <<
2258 address it was linked at. <<
2259 Since AArch64 uses the RELA relocat <<
2260 relocation pass at runtime even if <<
2261 same address it was linked at. <<
2262 3128
2263 config RANDOMIZE_BASE !! 3129 config ARCH_MMAP_RND_COMPAT_BITS_MIN
2264 bool "Randomize the address of the ke !! 3130 default 8
2265 select RELOCATABLE <<
2266 help <<
2267 Randomizes the virtual address at w <<
2268 loaded, as a security feature that <<
2269 relying on knowledge of the locatio <<
2270 <<
2271 It is the bootloader's job to provi <<
2272 random u64 value in /chosen/kaslr-s <<
2273 <<
2274 When booting via the UEFI stub, it <<
2275 EFI_RNG_PROTOCOL implementation (if <<
2276 to the kernel proper. In addition, <<
2277 location of the kernel Image as wel <<
2278 3131
2279 If unsure, say N. !! 3132 config ARCH_MMAP_RND_COMPAT_BITS_MAX
>> 3133 default 15
2280 3134
2281 config RANDOMIZE_MODULE_REGION_FULL !! 3135 config I8253
2282 bool "Randomize the module region ove !! 3136 bool
2283 depends on RANDOMIZE_BASE !! 3137 select CLKSRC_I8253
2284 default y !! 3138 select CLKEVT_I8253
2285 help !! 3139 select MIPS_EXTERNAL_TIMER
2286 Randomizes the location of the modu <<
2287 covering the core kernel. This way, <<
2288 to leak information about the locat <<
2289 but it does imply that function cal <<
2290 kernel will need to be resolved via <<
2291 <<
2292 When this option is not set, the mo <<
2293 a limited range that contains the [ <<
2294 core kernel, so branch relocations <<
2295 the region is exhausted. In this pa <<
2296 exhaustion, modules might be able t <<
2297 3140
2298 config CC_HAVE_STACKPROTECTOR_SYSREG !! 3141 config ZONE_DMA
2299 def_bool $(cc-option,-mstack-protecto !! 3142 bool
2300 3143
2301 config STACKPROTECTOR_PER_TASK !! 3144 config ZONE_DMA32
2302 def_bool y !! 3145 bool
2303 depends on STACKPROTECTOR && CC_HAVE_ <<
2304 3146
2305 config UNWIND_PATCH_PAC_INTO_SCS !! 3147 endmenu
2306 bool "Enable shadow call stack dynami <<
2307 # needs Clang with https://github.com <<
2308 depends on CC_IS_CLANG && CLANG_VERSI <<
2309 depends on ARM64_PTR_AUTH_KERNEL && C <<
2310 depends on SHADOW_CALL_STACK <<
2311 select UNWIND_TABLES <<
2312 select DYNAMIC_SCS <<
2313 <<
2314 config ARM64_CONTPTE <<
2315 bool "Contiguous PTE mappings for use <<
2316 depends on TRANSPARENT_HUGEPAGE <<
2317 default y <<
2318 help <<
2319 When enabled, user mappings are con <<
2320 bit, for any mappings that meet the <<
2321 This reduces TLB pressure and impro <<
2322 <<
2323 endmenu # "Kernel Features" <<
2324 <<
2325 menu "Boot options" <<
2326 <<
2327 config ARM64_ACPI_PARKING_PROTOCOL <<
2328 bool "Enable support for the ARM64 AC <<
2329 depends on ACPI <<
2330 help <<
2331 Enable support for the ARM64 ACPI p <<
2332 the kernel will not allow booting t <<
2333 protocol even if the corresponding <<
2334 MADT table. <<
2335 <<
2336 config CMDLINE <<
2337 string "Default kernel command string <<
2338 default "" <<
2339 help <<
2340 Provide a set of default command-li <<
2341 entering them here. As a minimum, y <<
2342 root device (e.g. root=/dev/nfs). <<
2343 3148
2344 choice !! 3149 config TRAD_SIGNALS
2345 prompt "Kernel command line type" !! 3150 bool
2346 depends on CMDLINE != "" <<
2347 default CMDLINE_FROM_BOOTLOADER <<
2348 help <<
2349 Choose how the kernel will handle t <<
2350 command line string. <<
2351 <<
2352 config CMDLINE_FROM_BOOTLOADER <<
2353 bool "Use bootloader kernel arguments <<
2354 help <<
2355 Uses the command-line options passe <<
2356 the boot loader doesn't provide any <<
2357 string provided in CMDLINE will be <<
2358 <<
2359 config CMDLINE_FORCE <<
2360 bool "Always use the default kernel c <<
2361 help <<
2362 Always use the default kernel comma <<
2363 loader passes other arguments to th <<
2364 This is useful if you cannot or don <<
2365 command-line options your boot load <<
2366 3151
2367 endchoice !! 3152 config MIPS32_COMPAT
>> 3153 bool
2368 3154
2369 config EFI_STUB !! 3155 config COMPAT
2370 bool 3156 bool
2371 3157
2372 config EFI !! 3158 config SYSVIPC_COMPAT
2373 bool "UEFI runtime support" !! 3159 bool
2374 depends on OF && !CPU_BIG_ENDIAN <<
2375 depends on KERNEL_MODE_NEON <<
2376 select ARCH_SUPPORTS_ACPI <<
2377 select LIBFDT <<
2378 select UCS2_STRING <<
2379 select EFI_PARAMS_FROM_FDT <<
2380 select EFI_RUNTIME_WRAPPERS <<
2381 select EFI_STUB <<
2382 select EFI_GENERIC_STUB <<
2383 imply IMA_SECURE_AND_OR_TRUSTED_BOOT <<
2384 default y <<
2385 help <<
2386 This option provides support for ru <<
2387 by UEFI firmware (such as non-volat <<
2388 clock, and platform reset). A UEFI <<
2389 allow the kernel to be booted as an <<
2390 is only useful on systems that have <<
2391 3160
2392 config COMPRESSED_INSTALL !! 3161 config MIPS32_O32
2393 bool "Install compressed image by def !! 3162 bool "Kernel support for o32 binaries"
2394 help !! 3163 depends on 64BIT
2395 This makes the regular "make instal !! 3164 select ARCH_WANT_OLD_COMPAT_IPC
2396 image we built, not the legacy unco !! 3165 select COMPAT
>> 3166 select MIPS32_COMPAT
>> 3167 select SYSVIPC_COMPAT if SYSVIPC
>> 3168 help
>> 3169 Select this option if you want to run o32 binaries. These are pure
>> 3170 32-bit binaries as used by the 32-bit Linux/MIPS port. Most of
>> 3171 existing binaries are in this format.
2397 3172
2398 You can check that a compressed ima !! 3173 If unsure, say Y.
2399 "make zinstall" first, and verifyin <<
2400 in your environment before making " <<
2401 you. <<
2402 3174
2403 config DMI !! 3175 config MIPS32_N32
2404 bool "Enable support for SMBIOS (DMI) !! 3176 bool "Kernel support for n32 binaries"
2405 depends on EFI !! 3177 depends on 64BIT
2406 default y !! 3178 select ARCH_WANT_COMPAT_IPC_PARSE_VERSION
2407 help !! 3179 select COMPAT
2408 This enables SMBIOS/DMI feature for !! 3180 select MIPS32_COMPAT
>> 3181 select SYSVIPC_COMPAT if SYSVIPC
>> 3182 help
>> 3183 Select this option if you want to run n32 binaries. These are
>> 3184 64-bit binaries using 32-bit quantities for addressing and certain
>> 3185 data that would normally be 64-bit. They are used in special
>> 3186 cases.
2409 3187
2410 This option is only useful on syste !! 3188 If unsure, say N.
2411 However, even with this option, the <<
2412 continue to boot on existing non-UE <<
2413 3189
2414 endmenu # "Boot options" !! 3190 config BINFMT_ELF32
>> 3191 bool
>> 3192 default y if MIPS32_O32 || MIPS32_N32
>> 3193 select ELFCORE
2415 3194
2416 menu "Power management options" 3195 menu "Power management options"
2417 3196
2418 source "kernel/power/Kconfig" <<
2419 <<
2420 config ARCH_HIBERNATION_POSSIBLE 3197 config ARCH_HIBERNATION_POSSIBLE
2421 def_bool y 3198 def_bool y
2422 depends on CPU_PM !! 3199 depends on SYS_SUPPORTS_HOTPLUG_CPU || !SMP
2423 <<
2424 config ARCH_HIBERNATION_HEADER <<
2425 def_bool y <<
2426 depends on HIBERNATION <<
2427 3200
2428 config ARCH_SUSPEND_POSSIBLE 3201 config ARCH_SUSPEND_POSSIBLE
2429 def_bool y 3202 def_bool y
>> 3203 depends on SYS_SUPPORTS_HOTPLUG_CPU || !SMP
2430 3204
2431 endmenu # "Power management options" !! 3205 source "kernel/power/Kconfig"
2432 3206
2433 menu "CPU Power Management" !! 3207 endmenu
2434 3208
2435 source "drivers/cpuidle/Kconfig" !! 3209 config MIPS_EXTERNAL_TIMER
>> 3210 bool
2436 3211
>> 3212 menu "CPU Power Management"
>> 3213
>> 3214 if CPU_SUPPORTS_CPUFREQ && MIPS_EXTERNAL_TIMER
2437 source "drivers/cpufreq/Kconfig" 3215 source "drivers/cpufreq/Kconfig"
>> 3216 endif
2438 3217
2439 endmenu # "CPU Power Management" !! 3218 source "drivers/cpuidle/Kconfig"
2440 3219
2441 source "drivers/acpi/Kconfig" !! 3220 endmenu
2442 3221
2443 source "arch/arm64/kvm/Kconfig" !! 3222 source "drivers/firmware/Kconfig"
2444 3223
>> 3224 source "arch/mips/kvm/Kconfig"
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