1 # SPDX-License-Identifier: GPL-2.0-only !! 1 # SPDX-License-Identifier: GPL-2.0
2 config ARM64 !! 2 config MIPS
3 def_bool y !! 3 bool
4 select ACPI_APMT if ACPI !! 4 default y
5 select ACPI_CCA_REQUIRED if ACPI !! 5 select ARCH_32BIT_OFF_T if !64BIT
6 select ACPI_GENERIC_GSI if ACPI !! 6 select ARCH_BINFMT_ELF_STATE if MIPS_FP_SUPPORT
7 select ACPI_GTDT if ACPI !! 7 select ARCH_CLOCKSOURCE_DATA
8 select ACPI_HOTPLUG_CPU if ACPI_PROCES !! 8 select ARCH_HAS_CPU_FINALIZE_INIT
9 select ACPI_IORT if ACPI <<
10 select ACPI_REDUCED_HARDWARE_ONLY if A <<
11 select ACPI_MCFG if (ACPI && PCI) <<
12 select ACPI_SPCR_TABLE if ACPI <<
13 select ACPI_PPTT if ACPI <<
14 select ARCH_HAS_DEBUG_WX <<
15 select ARCH_BINFMT_ELF_EXTRA_PHDRS <<
16 select ARCH_BINFMT_ELF_STATE <<
17 select ARCH_CORRECT_STACKTRACE_ON_KRET <<
18 select ARCH_ENABLE_HUGEPAGE_MIGRATION <<
19 select ARCH_ENABLE_MEMORY_HOTPLUG <<
20 select ARCH_ENABLE_MEMORY_HOTREMOVE <<
21 select ARCH_ENABLE_SPLIT_PMD_PTLOCK if <<
22 select ARCH_ENABLE_THP_MIGRATION if TR <<
23 select ARCH_HAS_CACHE_LINE_SIZE <<
24 select ARCH_HAS_CURRENT_STACK_POINTER <<
25 select ARCH_HAS_DEBUG_VIRTUAL <<
26 select ARCH_HAS_DEBUG_VM_PGTABLE <<
27 select ARCH_HAS_DMA_OPS if XEN <<
28 select ARCH_HAS_DMA_PREP_COHERENT <<
29 select ARCH_HAS_ACPI_TABLE_UPGRADE if <<
30 select ARCH_HAS_FAST_MULTIPLIER <<
31 select ARCH_HAS_FORTIFY_SOURCE <<
32 select ARCH_HAS_GCOV_PROFILE_ALL <<
33 select ARCH_HAS_GIGANTIC_PAGE <<
34 select ARCH_HAS_KCOV <<
35 select ARCH_HAS_KERNEL_FPU_SUPPORT if <<
36 select ARCH_HAS_KEEPINITRD <<
37 select ARCH_HAS_MEMBARRIER_SYNC_CORE <<
38 select ARCH_HAS_MEM_ENCRYPT <<
39 select ARCH_HAS_NMI_SAFE_THIS_CPU_OPS <<
40 select ARCH_HAS_NON_OVERLAPPING_ADDRES <<
41 select ARCH_HAS_PTE_DEVMAP <<
42 select ARCH_HAS_PTE_SPECIAL <<
43 select ARCH_HAS_HW_PTE_YOUNG <<
44 select ARCH_HAS_SETUP_DMA_OPS <<
45 select ARCH_HAS_SET_DIRECT_MAP <<
46 select ARCH_HAS_SET_MEMORY <<
47 select ARCH_STACKWALK <<
48 select ARCH_HAS_STRICT_KERNEL_RWX <<
49 select ARCH_HAS_STRICT_MODULE_RWX <<
50 select ARCH_HAS_SYNC_DMA_FOR_DEVICE <<
51 select ARCH_HAS_SYNC_DMA_FOR_CPU <<
52 select ARCH_HAS_SYSCALL_WRAPPER <<
53 select ARCH_HAS_TICK_BROADCAST if GENE 9 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
54 select ARCH_HAS_ZONE_DMA_SET if EXPERT !! 10 select ARCH_HAS_UBSAN_SANITIZE_ALL
55 select ARCH_HAVE_ELF_PROT !! 11 select ARCH_SUPPORTS_UPROBES
56 select ARCH_HAVE_NMI_SAFE_CMPXCHG !! 12 select ARCH_USE_BUILTIN_BSWAP
57 select ARCH_HAVE_TRACE_MMIO_ACCESS !! 13 select ARCH_USE_CMPXCHG_LOCKREF if 64BIT
58 select ARCH_INLINE_READ_LOCK if !PREEM <<
59 select ARCH_INLINE_READ_LOCK_BH if !PR <<
60 select ARCH_INLINE_READ_LOCK_IRQ if !P <<
61 select ARCH_INLINE_READ_LOCK_IRQSAVE i <<
62 select ARCH_INLINE_READ_UNLOCK if !PRE <<
63 select ARCH_INLINE_READ_UNLOCK_BH if ! <<
64 select ARCH_INLINE_READ_UNLOCK_IRQ if <<
65 select ARCH_INLINE_READ_UNLOCK_IRQREST <<
66 select ARCH_INLINE_WRITE_LOCK if !PREE <<
67 select ARCH_INLINE_WRITE_LOCK_BH if !P <<
68 select ARCH_INLINE_WRITE_LOCK_IRQ if ! <<
69 select ARCH_INLINE_WRITE_LOCK_IRQSAVE <<
70 select ARCH_INLINE_WRITE_UNLOCK if !PR <<
71 select ARCH_INLINE_WRITE_UNLOCK_BH if <<
72 select ARCH_INLINE_WRITE_UNLOCK_IRQ if <<
73 select ARCH_INLINE_WRITE_UNLOCK_IRQRES <<
74 select ARCH_INLINE_SPIN_TRYLOCK if !PR <<
75 select ARCH_INLINE_SPIN_TRYLOCK_BH if <<
76 select ARCH_INLINE_SPIN_LOCK if !PREEM <<
77 select ARCH_INLINE_SPIN_LOCK_BH if !PR <<
78 select ARCH_INLINE_SPIN_LOCK_IRQ if !P <<
79 select ARCH_INLINE_SPIN_LOCK_IRQSAVE i <<
80 select ARCH_INLINE_SPIN_UNLOCK if !PRE <<
81 select ARCH_INLINE_SPIN_UNLOCK_BH if ! <<
82 select ARCH_INLINE_SPIN_UNLOCK_IRQ if <<
83 select ARCH_INLINE_SPIN_UNLOCK_IRQREST <<
84 select ARCH_KEEP_MEMBLOCK <<
85 select ARCH_MHP_MEMMAP_ON_MEMORY_ENABL <<
86 select ARCH_USE_CMPXCHG_LOCKREF <<
87 select ARCH_USE_GNU_PROPERTY <<
88 select ARCH_USE_MEMTEST <<
89 select ARCH_USE_QUEUED_RWLOCKS 14 select ARCH_USE_QUEUED_RWLOCKS
90 select ARCH_USE_QUEUED_SPINLOCKS 15 select ARCH_USE_QUEUED_SPINLOCKS
91 select ARCH_USE_SYM_ANNOTATIONS !! 16 select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT if MMU
92 select ARCH_SUPPORTS_DEBUG_PAGEALLOC !! 17 select ARCH_WANT_IPC_PARSE_VERSION
93 select ARCH_SUPPORTS_HUGETLBFS !! 18 select BUILDTIME_EXTABLE_SORT
94 select ARCH_SUPPORTS_MEMORY_FAILURE <<
95 select ARCH_SUPPORTS_SHADOW_CALL_STACK <<
96 select ARCH_SUPPORTS_LTO_CLANG if CPU_ <<
97 select ARCH_SUPPORTS_LTO_CLANG_THIN <<
98 select ARCH_SUPPORTS_CFI_CLANG <<
99 select ARCH_SUPPORTS_ATOMIC_RMW <<
100 select ARCH_SUPPORTS_INT128 if CC_HAS_ <<
101 select ARCH_SUPPORTS_NUMA_BALANCING <<
102 select ARCH_SUPPORTS_PAGE_TABLE_CHECK <<
103 select ARCH_SUPPORTS_PER_VMA_LOCK <<
104 select ARCH_SUPPORTS_HUGE_PFNMAP if TR <<
105 select ARCH_SUPPORTS_RT <<
106 select ARCH_WANT_BATCHED_UNMAP_TLB_FLU <<
107 select ARCH_WANT_COMPAT_IPC_PARSE_VERS <<
108 select ARCH_WANT_DEFAULT_BPF_JIT <<
109 select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_ <<
110 select ARCH_WANT_FRAME_POINTERS <<
111 select ARCH_WANT_HUGE_PMD_SHARE if ARM <<
112 select ARCH_WANT_LD_ORPHAN_WARN <<
113 select ARCH_WANTS_EXECMEM_LATE if EXEC <<
114 select ARCH_WANTS_NO_INSTR <<
115 select ARCH_WANTS_THP_SWAP if ARM64_4K <<
116 select ARCH_HAS_UBSAN <<
117 select ARM_AMBA <<
118 select ARM_ARCH_TIMER <<
119 select ARM_GIC <<
120 select AUDIT_ARCH_COMPAT_GENERIC <<
121 select ARM_GIC_V2M if PCI <<
122 select ARM_GIC_V3 <<
123 select ARM_GIC_V3_ITS if PCI <<
124 select ARM_PSCI_FW <<
125 select BUILDTIME_TABLE_SORT <<
126 select CLONE_BACKWARDS 19 select CLONE_BACKWARDS
127 select COMMON_CLK !! 20 select CPU_NO_EFFICIENT_FFS if (TARGET_ISA_REV < 1)
128 select CPU_PM if (SUSPEND || CPU_IDLE) !! 21 select CPU_PM if CPU_IDLE
129 select CPUMASK_OFFSTACK if NR_CPUS > 2 !! 22 select GENERIC_ATOMIC64 if !64BIT
130 select CRC32 !! 23 select GENERIC_CLOCKEVENTS
131 select DCACHE_WORD_ACCESS !! 24 select GENERIC_CMOS_UPDATE
132 select DYNAMIC_FTRACE if FUNCTION_TRAC <<
133 select DMA_BOUNCE_UNALIGNED_KMALLOC <<
134 select DMA_DIRECT_REMAP <<
135 select EDAC_SUPPORT <<
136 select FRAME_POINTER <<
137 select FUNCTION_ALIGNMENT_4B <<
138 select FUNCTION_ALIGNMENT_8B if DYNAMI <<
139 select GENERIC_ALLOCATOR <<
140 select GENERIC_ARCH_TOPOLOGY <<
141 select GENERIC_CLOCKEVENTS_BROADCAST <<
142 select GENERIC_CPU_AUTOPROBE 25 select GENERIC_CPU_AUTOPROBE
143 select GENERIC_CPU_DEVICES !! 26 select GENERIC_GETTIMEOFDAY
144 select GENERIC_CPU_VULNERABILITIES !! 27 select GENERIC_IOMAP
145 select GENERIC_EARLY_IOREMAP <<
146 select GENERIC_IDLE_POLL_SETUP <<
147 select GENERIC_IOREMAP <<
148 select GENERIC_IRQ_IPI <<
149 select GENERIC_IRQ_PROBE 28 select GENERIC_IRQ_PROBE
150 select GENERIC_IRQ_SHOW 29 select GENERIC_IRQ_SHOW
151 select GENERIC_IRQ_SHOW_LEVEL !! 30 select GENERIC_ISA_DMA if EISA
152 select GENERIC_LIB_DEVMEM_IS_ALLOWED !! 31 select GENERIC_LIB_ASHLDI3
153 select GENERIC_PCI_IOMAP !! 32 select GENERIC_LIB_ASHRDI3
154 select GENERIC_PTDUMP !! 33 select GENERIC_LIB_CMPDI2
155 select GENERIC_SCHED_CLOCK !! 34 select GENERIC_LIB_LSHRDI3
>> 35 select GENERIC_LIB_UCMPDI2
>> 36 select GENERIC_SCHED_CLOCK if !CAVIUM_OCTEON_SOC
156 select GENERIC_SMP_IDLE_THREAD 37 select GENERIC_SMP_IDLE_THREAD
157 select GENERIC_TIME_VSYSCALL 38 select GENERIC_TIME_VSYSCALL
158 select GENERIC_GETTIMEOFDAY !! 39 select GUP_GET_PTE_LOW_HIGH if CPU_MIPS32 && PHYS_ADDR_T_64BIT
159 select GENERIC_VDSO_TIME_NS !! 40 select HANDLE_DOMAIN_IRQ
160 select HARDIRQS_SW_RESEND <<
161 select HAS_IOPORT <<
162 select HAVE_MOVE_PMD <<
163 select HAVE_MOVE_PUD <<
164 select HAVE_PCI <<
165 select HAVE_ACPI_APEI if (ACPI && EFI) <<
166 select HAVE_ALIGNED_STRUCT_PAGE <<
167 select HAVE_ARCH_AUDITSYSCALL <<
168 select HAVE_ARCH_BITREVERSE <<
169 select HAVE_ARCH_COMPILER_H 41 select HAVE_ARCH_COMPILER_H
170 select HAVE_ARCH_HUGE_VMALLOC <<
171 select HAVE_ARCH_HUGE_VMAP <<
172 select HAVE_ARCH_JUMP_LABEL 42 select HAVE_ARCH_JUMP_LABEL
173 select HAVE_ARCH_JUMP_LABEL_RELATIVE <<
174 select HAVE_ARCH_KASAN <<
175 select HAVE_ARCH_KASAN_VMALLOC <<
176 select HAVE_ARCH_KASAN_SW_TAGS <<
177 select HAVE_ARCH_KASAN_HW_TAGS if ARM6 <<
178 # Some instrumentation may be unsound, <<
179 select HAVE_ARCH_KCSAN if EXPERT <<
180 select HAVE_ARCH_KFENCE <<
181 select HAVE_ARCH_KGDB 43 select HAVE_ARCH_KGDB
182 select HAVE_ARCH_MMAP_RND_BITS !! 44 select HAVE_ARCH_MMAP_RND_BITS if MMU
183 select HAVE_ARCH_MMAP_RND_COMPAT_BITS !! 45 select HAVE_ARCH_MMAP_RND_COMPAT_BITS if MMU && COMPAT
184 select HAVE_ARCH_PREL32_RELOCATIONS <<
185 select HAVE_ARCH_RANDOMIZE_KSTACK_OFFS <<
186 select HAVE_ARCH_SECCOMP_FILTER 46 select HAVE_ARCH_SECCOMP_FILTER
187 select HAVE_ARCH_STACKLEAK <<
188 select HAVE_ARCH_THREAD_STRUCT_WHITELI <<
189 select HAVE_ARCH_TRACEHOOK 47 select HAVE_ARCH_TRACEHOOK
190 select HAVE_ARCH_TRANSPARENT_HUGEPAGE !! 48 select HAVE_ARCH_TRANSPARENT_HUGEPAGE if CPU_SUPPORTS_HUGEPAGES
191 select HAVE_ARCH_VMAP_STACK <<
192 select HAVE_ARM_SMCCC <<
193 select HAVE_ASM_MODVERSIONS 49 select HAVE_ASM_MODVERSIONS
194 select HAVE_EBPF_JIT !! 50 select HAVE_CBPF_JIT if !64BIT && !CPU_MICROMIPS
>> 51 select HAVE_EBPF_JIT if 64BIT && !CPU_MICROMIPS && TARGET_ISA_REV >= 2
>> 52 select HAVE_CONTEXT_TRACKING
>> 53 select HAVE_COPY_THREAD_TLS
195 select HAVE_C_RECORDMCOUNT 54 select HAVE_C_RECORDMCOUNT
196 select HAVE_CMPXCHG_DOUBLE <<
197 select HAVE_CMPXCHG_LOCAL <<
198 select HAVE_CONTEXT_TRACKING_USER <<
199 select HAVE_DEBUG_KMEMLEAK 55 select HAVE_DEBUG_KMEMLEAK
>> 56 select HAVE_DEBUG_STACKOVERFLOW
200 select HAVE_DMA_CONTIGUOUS 57 select HAVE_DMA_CONTIGUOUS
201 select HAVE_DYNAMIC_FTRACE 58 select HAVE_DYNAMIC_FTRACE
202 select HAVE_DYNAMIC_FTRACE_WITH_ARGS \ !! 59 select HAVE_EXIT_THREAD
203 if (GCC_SUPPORTS_DYNAMIC_FTRAC !! 60 select HAVE_FAST_GUP
204 CLANG_SUPPORTS_DYNAMIC_FTR <<
205 select HAVE_DYNAMIC_FTRACE_WITH_DIRECT <<
206 if DYNAMIC_FTRACE_WITH_ARGS && <<
207 select HAVE_DYNAMIC_FTRACE_WITH_CALL_O <<
208 if (DYNAMIC_FTRACE_WITH_ARGS & <<
209 (CC_IS_CLANG || !CC_OPTIMI <<
210 select FTRACE_MCOUNT_USE_PATCHABLE_FUN <<
211 if DYNAMIC_FTRACE_WITH_ARGS <<
212 select HAVE_SAMPLE_FTRACE_DIRECT <<
213 select HAVE_SAMPLE_FTRACE_DIRECT_MULTI <<
214 select HAVE_EFFICIENT_UNALIGNED_ACCESS <<
215 select HAVE_GUP_FAST <<
216 select HAVE_FTRACE_MCOUNT_RECORD 61 select HAVE_FTRACE_MCOUNT_RECORD
217 select HAVE_FUNCTION_TRACER <<
218 select HAVE_FUNCTION_ERROR_INJECTION <<
219 select HAVE_FUNCTION_GRAPH_TRACER 62 select HAVE_FUNCTION_GRAPH_TRACER
220 select HAVE_FUNCTION_GRAPH_RETVAL !! 63 select HAVE_FUNCTION_TRACER
221 select HAVE_GCC_PLUGINS !! 64 select HAVE_IDE
222 select HAVE_HARDLOCKUP_DETECTOR_PERF i <<
223 HW_PERF_EVENTS && HAVE_PERF_EV <<
224 select HAVE_HW_BREAKPOINT if PERF_EVEN <<
225 select HAVE_IOREMAP_PROT 65 select HAVE_IOREMAP_PROT
>> 66 select HAVE_IRQ_EXIT_ON_IRQ_STACK
226 select HAVE_IRQ_TIME_ACCOUNTING 67 select HAVE_IRQ_TIME_ACCOUNTING
>> 68 select HAVE_KPROBES
>> 69 select HAVE_KRETPROBES
>> 70 select HAVE_LD_DEAD_CODE_DATA_ELIMINATION
>> 71 select HAVE_MEMBLOCK_NODE_MAP
227 select HAVE_MOD_ARCH_SPECIFIC 72 select HAVE_MOD_ARCH_SPECIFIC
228 select HAVE_NMI 73 select HAVE_NMI
>> 74 select HAVE_OPROFILE
229 select HAVE_PERF_EVENTS 75 select HAVE_PERF_EVENTS
230 select HAVE_PERF_EVENTS_NMI if ARM64_P <<
231 select HAVE_PERF_REGS <<
232 select HAVE_PERF_USER_STACK_DUMP <<
233 select HAVE_PREEMPT_DYNAMIC_KEY <<
234 select HAVE_REGS_AND_STACK_ACCESS_API 76 select HAVE_REGS_AND_STACK_ACCESS_API
235 select HAVE_POSIX_CPU_TIMERS_TASK_WORK <<
236 select HAVE_FUNCTION_ARG_ACCESS_API <<
237 select MMU_GATHER_RCU_TABLE_FREE <<
238 select HAVE_RSEQ 77 select HAVE_RSEQ
239 select HAVE_RUST if RUSTC_SUPPORTS_ARM <<
240 select HAVE_STACKPROTECTOR 78 select HAVE_STACKPROTECTOR
241 select HAVE_SYSCALL_TRACEPOINTS 79 select HAVE_SYSCALL_TRACEPOINTS
242 select HAVE_KPROBES !! 80 select HAVE_VIRT_CPU_ACCOUNTING_GEN if 64BIT || !SMP
243 select HAVE_KRETPROBES <<
244 select HAVE_GENERIC_VDSO 81 select HAVE_GENERIC_VDSO
245 select HOTPLUG_CORE_SYNC_DEAD if HOTPL <<
246 select IRQ_DOMAIN <<
247 select IRQ_FORCED_THREADING 82 select IRQ_FORCED_THREADING
248 select KASAN_VMALLOC if KASAN !! 83 select ISA if EISA
249 select LOCK_MM_AND_FIND_VMA !! 84 select MODULES_USE_ELF_RELA if MODULES && 64BIT
250 select MODULES_USE_ELF_RELA !! 85 select MODULES_USE_ELF_REL if MODULES
251 select NEED_DMA_MAP_STATE !! 86 select PERF_USE_VMALLOC
252 select NEED_SG_DMA_LENGTH !! 87 select RTC_LIB
253 select OF <<
254 select OF_EARLY_FLATTREE <<
255 select PCI_DOMAINS_GENERIC if PCI <<
256 select PCI_ECAM if (ACPI && PCI) <<
257 select PCI_SYSCALL if PCI <<
258 select POWER_RESET <<
259 select POWER_SUPPLY <<
260 select SPARSE_IRQ <<
261 select SWIOTLB <<
262 select SYSCTL_EXCEPTION_TRACE 88 select SYSCTL_EXCEPTION_TRACE
263 select THREAD_INFO_IN_TASK !! 89 select VIRT_TO_BUS
264 select HAVE_ARCH_USERFAULTFD_MINOR if !! 90 select ARCH_HAS_PTE_SPECIAL if !(32BIT && CPU_HAS_RIXI)
265 select HAVE_ARCH_USERFAULTFD_WP if USE <<
266 select TRACE_IRQFLAGS_SUPPORT <<
267 select TRACE_IRQFLAGS_NMI_SUPPORT <<
268 select HAVE_SOFTIRQ_ON_OWN_STACK <<
269 select USER_STACKTRACE_SUPPORT <<
270 select VDSO_GETRANDOM <<
271 help <<
272 ARM 64-bit (AArch64) Linux support. <<
273 <<
274 config RUSTC_SUPPORTS_ARM64 <<
275 def_bool y <<
276 depends on CPU_LITTLE_ENDIAN <<
277 # Shadow call stack is only supported <<
278 # <<
279 # When using the UNWIND_PATCH_PAC_INTO <<
280 # required due to use of the -Zfixed-x <<
281 # <<
282 # Otherwise, rustc version 1.82+ is re <<
283 # -Zsanitizer=shadow-call-stack flag. <<
284 depends on !SHADOW_CALL_STACK || RUSTC <<
285 <<
286 config CLANG_SUPPORTS_DYNAMIC_FTRACE_WITH_ARGS <<
287 def_bool CC_IS_CLANG <<
288 # https://github.com/ClangBuiltLinux/l <<
289 depends on AS_IS_GNU || (AS_IS_LLVM && <<
290 <<
291 config GCC_SUPPORTS_DYNAMIC_FTRACE_WITH_ARGS <<
292 def_bool CC_IS_GCC <<
293 depends on $(cc-option,-fpatchable-fun <<
294 91
295 config 64BIT !! 92 menu "Machine selection"
296 def_bool y <<
297 93
298 config MMU !! 94 choice
299 def_bool y !! 95 prompt "System type"
300 !! 96 default MIPS_GENERIC
301 config ARM64_CONT_PTE_SHIFT <<
302 int <<
303 default 5 if PAGE_SIZE_64KB <<
304 default 7 if PAGE_SIZE_16KB <<
305 default 4 <<
306 <<
307 config ARM64_CONT_PMD_SHIFT <<
308 int <<
309 default 5 if PAGE_SIZE_64KB <<
310 default 5 if PAGE_SIZE_16KB <<
311 default 4 <<
312 <<
313 config ARCH_MMAP_RND_BITS_MIN <<
314 default 14 if PAGE_SIZE_64KB <<
315 default 16 if PAGE_SIZE_16KB <<
316 default 18 <<
317 <<
318 # max bits determined by the following formula <<
319 # VA_BITS - PAGE_SHIFT - 3 <<
320 config ARCH_MMAP_RND_BITS_MAX <<
321 default 19 if ARM64_VA_BITS=36 <<
322 default 24 if ARM64_VA_BITS=39 <<
323 default 27 if ARM64_VA_BITS=42 <<
324 default 30 if ARM64_VA_BITS=47 <<
325 default 29 if ARM64_VA_BITS=48 && ARM6 <<
326 default 31 if ARM64_VA_BITS=48 && ARM6 <<
327 default 33 if ARM64_VA_BITS=48 <<
328 default 14 if ARM64_64K_PAGES <<
329 default 16 if ARM64_16K_PAGES <<
330 default 18 <<
331 <<
332 config ARCH_MMAP_RND_COMPAT_BITS_MIN <<
333 default 7 if ARM64_64K_PAGES <<
334 default 9 if ARM64_16K_PAGES <<
335 default 11 <<
336 97
337 config ARCH_MMAP_RND_COMPAT_BITS_MAX !! 98 config MIPS_GENERIC
338 default 16 !! 99 bool "Generic board-agnostic MIPS kernel"
>> 100 select BOOT_RAW
>> 101 select BUILTIN_DTB
>> 102 select CEVT_R4K
>> 103 select CLKSRC_MIPS_GIC
>> 104 select COMMON_CLK
>> 105 select CPU_MIPSR2_IRQ_VI
>> 106 select CPU_MIPSR2_IRQ_EI
>> 107 select CSRC_R4K
>> 108 select DMA_PERDEV_COHERENT
>> 109 select HAVE_PCI
>> 110 select IRQ_MIPS_CPU
>> 111 select LIBFDT
>> 112 select MIPS_AUTO_PFN_OFFSET
>> 113 select MIPS_CPU_SCACHE
>> 114 select MIPS_GIC
>> 115 select MIPS_L1_CACHE_SHIFT_7
>> 116 select NO_EXCEPT_FILL
>> 117 select PCI_DRIVERS_GENERIC
>> 118 select PINCTRL
>> 119 select SMP_UP if SMP
>> 120 select SWAP_IO_SPACE
>> 121 select SYS_HAS_CPU_MIPS32_R1
>> 122 select SYS_HAS_CPU_MIPS32_R2
>> 123 select SYS_HAS_CPU_MIPS32_R6
>> 124 select SYS_HAS_CPU_MIPS64_R1
>> 125 select SYS_HAS_CPU_MIPS64_R2
>> 126 select SYS_HAS_CPU_MIPS64_R6
>> 127 select SYS_SUPPORTS_32BIT_KERNEL
>> 128 select SYS_SUPPORTS_64BIT_KERNEL
>> 129 select SYS_SUPPORTS_BIG_ENDIAN
>> 130 select SYS_SUPPORTS_HIGHMEM
>> 131 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 132 select SYS_SUPPORTS_MICROMIPS
>> 133 select SYS_SUPPORTS_MIPS_CPS
>> 134 select SYS_SUPPORTS_MIPS16
>> 135 select SYS_SUPPORTS_MULTITHREADING
>> 136 select SYS_SUPPORTS_RELOCATABLE
>> 137 select SYS_SUPPORTS_SMARTMIPS
>> 138 select USB_EHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
>> 139 select USB_EHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 140 select USB_OHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
>> 141 select USB_OHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 142 select USB_UHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
>> 143 select USB_UHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 144 select USE_OF
>> 145 select UHI_BOOT
>> 146 help
>> 147 Select this to build a kernel which aims to support multiple boards,
>> 148 generally using a flattened device tree passed from the bootloader
>> 149 using the boot protocol defined in the UHI (Unified Hosting
>> 150 Interface) specification.
>> 151
>> 152 config MIPS_ALCHEMY
>> 153 bool "Alchemy processor based machines"
>> 154 select PHYS_ADDR_T_64BIT
>> 155 select CEVT_R4K
>> 156 select CSRC_R4K
>> 157 select IRQ_MIPS_CPU
>> 158 select DMA_MAYBE_COHERENT # Au1000,1500,1100 aren't, rest is
>> 159 select SYS_HAS_CPU_MIPS32_R1
>> 160 select SYS_SUPPORTS_32BIT_KERNEL
>> 161 select SYS_SUPPORTS_APM_EMULATION
>> 162 select GPIOLIB
>> 163 select SYS_SUPPORTS_ZBOOT
>> 164 select COMMON_CLK
339 165
340 config NO_IOPORT_MAP !! 166 config AR7
341 def_bool y if !PCI !! 167 bool "Texas Instruments AR7"
>> 168 select BOOT_ELF32
>> 169 select DMA_NONCOHERENT
>> 170 select CEVT_R4K
>> 171 select CSRC_R4K
>> 172 select IRQ_MIPS_CPU
>> 173 select NO_EXCEPT_FILL
>> 174 select SWAP_IO_SPACE
>> 175 select SYS_HAS_CPU_MIPS32_R1
>> 176 select SYS_HAS_EARLY_PRINTK
>> 177 select SYS_SUPPORTS_32BIT_KERNEL
>> 178 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 179 select SYS_SUPPORTS_MIPS16
>> 180 select SYS_SUPPORTS_ZBOOT_UART16550
>> 181 select GPIOLIB
>> 182 select VLYNQ
>> 183 select HAVE_CLK
>> 184 help
>> 185 Support for the Texas Instruments AR7 System-on-a-Chip
>> 186 family: TNETD7100, 7200 and 7300.
>> 187
>> 188 config ATH25
>> 189 bool "Atheros AR231x/AR531x SoC support"
>> 190 select CEVT_R4K
>> 191 select CSRC_R4K
>> 192 select DMA_NONCOHERENT
>> 193 select IRQ_MIPS_CPU
>> 194 select IRQ_DOMAIN
>> 195 select SYS_HAS_CPU_MIPS32_R1
>> 196 select SYS_SUPPORTS_BIG_ENDIAN
>> 197 select SYS_SUPPORTS_32BIT_KERNEL
>> 198 select SYS_HAS_EARLY_PRINTK
>> 199 help
>> 200 Support for Atheros AR231x and Atheros AR531x based boards
>> 201
>> 202 config ATH79
>> 203 bool "Atheros AR71XX/AR724X/AR913X based boards"
>> 204 select ARCH_HAS_RESET_CONTROLLER
>> 205 select BOOT_RAW
>> 206 select CEVT_R4K
>> 207 select CSRC_R4K
>> 208 select DMA_NONCOHERENT
>> 209 select GPIOLIB
>> 210 select PINCTRL
>> 211 select HAVE_CLK
>> 212 select COMMON_CLK
>> 213 select CLKDEV_LOOKUP
>> 214 select IRQ_MIPS_CPU
>> 215 select SYS_HAS_CPU_MIPS32_R2
>> 216 select SYS_HAS_EARLY_PRINTK
>> 217 select SYS_SUPPORTS_32BIT_KERNEL
>> 218 select SYS_SUPPORTS_BIG_ENDIAN
>> 219 select SYS_SUPPORTS_MIPS16
>> 220 select SYS_SUPPORTS_ZBOOT_UART_PROM
>> 221 select USE_OF
>> 222 select USB_EHCI_ROOT_HUB_TT if USB_EHCI_HCD_PLATFORM
>> 223 help
>> 224 Support for the Atheros AR71XX/AR724X/AR913X SoCs.
>> 225
>> 226 config BMIPS_GENERIC
>> 227 bool "Broadcom Generic BMIPS kernel"
>> 228 select ARCH_HAS_SYNC_DMA_FOR_CPU_ALL
>> 229 select ARCH_HAS_PHYS_TO_DMA
>> 230 select BOOT_RAW
>> 231 select NO_EXCEPT_FILL
>> 232 select USE_OF
>> 233 select CEVT_R4K
>> 234 select CSRC_R4K
>> 235 select SYNC_R4K
>> 236 select COMMON_CLK
>> 237 select BCM6345_L1_IRQ
>> 238 select BCM7038_L1_IRQ
>> 239 select BCM7120_L2_IRQ
>> 240 select BRCMSTB_L2_IRQ
>> 241 select IRQ_MIPS_CPU
>> 242 select DMA_NONCOHERENT
>> 243 select SYS_SUPPORTS_32BIT_KERNEL
>> 244 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 245 select SYS_SUPPORTS_BIG_ENDIAN
>> 246 select SYS_SUPPORTS_HIGHMEM
>> 247 select SYS_HAS_CPU_BMIPS32_3300
>> 248 select SYS_HAS_CPU_BMIPS4350
>> 249 select SYS_HAS_CPU_BMIPS4380
>> 250 select SYS_HAS_CPU_BMIPS5000
>> 251 select SWAP_IO_SPACE
>> 252 select USB_EHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
>> 253 select USB_EHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 254 select USB_OHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
>> 255 select USB_OHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 256 select HARDIRQS_SW_RESEND
>> 257 help
>> 258 Build a generic DT-based kernel image that boots on select
>> 259 BCM33xx cable modem chips, BCM63xx DSL chips, and BCM7xxx set-top
>> 260 box chips. Note that CONFIG_CPU_BIG_ENDIAN/CONFIG_CPU_LITTLE_ENDIAN
>> 261 must be set appropriately for your board.
>> 262
>> 263 config BCM47XX
>> 264 bool "Broadcom BCM47XX based boards"
>> 265 select BOOT_RAW
>> 266 select CEVT_R4K
>> 267 select CSRC_R4K
>> 268 select DMA_NONCOHERENT
>> 269 select HAVE_PCI
>> 270 select IRQ_MIPS_CPU
>> 271 select SYS_HAS_CPU_MIPS32_R1
>> 272 select NO_EXCEPT_FILL
>> 273 select SYS_SUPPORTS_32BIT_KERNEL
>> 274 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 275 select SYS_SUPPORTS_MIPS16
>> 276 select SYS_SUPPORTS_ZBOOT
>> 277 select SYS_HAS_EARLY_PRINTK
>> 278 select USE_GENERIC_EARLY_PRINTK_8250
>> 279 select GPIOLIB
>> 280 select LEDS_GPIO_REGISTER
>> 281 select BCM47XX_NVRAM
>> 282 select BCM47XX_SPROM
>> 283 select BCM47XX_SSB if !BCM47XX_BCMA
>> 284 help
>> 285 Support for BCM47XX based boards
>> 286
>> 287 config BCM63XX
>> 288 bool "Broadcom BCM63XX based boards"
>> 289 select BOOT_RAW
>> 290 select CEVT_R4K
>> 291 select CSRC_R4K
>> 292 select SYNC_R4K
>> 293 select DMA_NONCOHERENT
>> 294 select IRQ_MIPS_CPU
>> 295 select SYS_SUPPORTS_32BIT_KERNEL
>> 296 select SYS_SUPPORTS_BIG_ENDIAN
>> 297 select SYS_HAS_EARLY_PRINTK
>> 298 select SYS_HAS_CPU_BMIPS32_3300
>> 299 select SYS_HAS_CPU_BMIPS4350
>> 300 select SYS_HAS_CPU_BMIPS4380
>> 301 select SWAP_IO_SPACE
>> 302 select GPIOLIB
>> 303 select HAVE_CLK
>> 304 select MIPS_L1_CACHE_SHIFT_4
>> 305 select CLKDEV_LOOKUP
>> 306 help
>> 307 Support for BCM63XX based boards
>> 308
>> 309 config MIPS_COBALT
>> 310 bool "Cobalt Server"
>> 311 select CEVT_R4K
>> 312 select CSRC_R4K
>> 313 select CEVT_GT641XX
>> 314 select DMA_NONCOHERENT
>> 315 select FORCE_PCI
>> 316 select I8253
>> 317 select I8259
>> 318 select IRQ_MIPS_CPU
>> 319 select IRQ_GT641XX
>> 320 select PCI_GT64XXX_PCI0
>> 321 select SYS_HAS_CPU_NEVADA
>> 322 select SYS_HAS_EARLY_PRINTK
>> 323 select SYS_SUPPORTS_32BIT_KERNEL
>> 324 select SYS_SUPPORTS_64BIT_KERNEL
>> 325 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 326 select USE_GENERIC_EARLY_PRINTK_8250
>> 327
>> 328 config MACH_DECSTATION
>> 329 bool "DECstations"
>> 330 select BOOT_ELF32
>> 331 select CEVT_DS1287
>> 332 select CEVT_R4K if CPU_R4X00
>> 333 select CSRC_IOASIC
>> 334 select CSRC_R4K if CPU_R4X00
>> 335 select CPU_DADDI_WORKAROUNDS if 64BIT
>> 336 select CPU_R4000_WORKAROUNDS if 64BIT
>> 337 select CPU_R4400_WORKAROUNDS if 64BIT
>> 338 select DMA_NONCOHERENT
>> 339 select NO_IOPORT_MAP
>> 340 select IRQ_MIPS_CPU
>> 341 select SYS_HAS_CPU_R3000
>> 342 select SYS_HAS_CPU_R4X00
>> 343 select SYS_SUPPORTS_32BIT_KERNEL
>> 344 select SYS_SUPPORTS_64BIT_KERNEL
>> 345 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 346 select SYS_SUPPORTS_128HZ
>> 347 select SYS_SUPPORTS_256HZ
>> 348 select SYS_SUPPORTS_1024HZ
>> 349 select MIPS_L1_CACHE_SHIFT_4
>> 350 help
>> 351 This enables support for DEC's MIPS based workstations. For details
>> 352 see the Linux/MIPS FAQ on <http://www.linux-mips.org/> and the
>> 353 DECstation porting pages on <http://decstation.unix-ag.org/>.
>> 354
>> 355 If you have one of the following DECstation Models you definitely
>> 356 want to choose R4xx0 for the CPU Type:
>> 357
>> 358 DECstation 5000/50
>> 359 DECstation 5000/150
>> 360 DECstation 5000/260
>> 361 DECsystem 5900/260
>> 362
>> 363 otherwise choose R3000.
>> 364
>> 365 config MACH_JAZZ
>> 366 bool "Jazz family of machines"
>> 367 select ARCH_MIGHT_HAVE_PC_PARPORT
>> 368 select ARCH_MIGHT_HAVE_PC_SERIO
>> 369 select FW_ARC
>> 370 select FW_ARC32
>> 371 select ARCH_MAY_HAVE_PC_FDC
>> 372 select CEVT_R4K
>> 373 select CSRC_R4K
>> 374 select DEFAULT_SGI_PARTITION if CPU_BIG_ENDIAN
>> 375 select GENERIC_ISA_DMA
>> 376 select HAVE_PCSPKR_PLATFORM
>> 377 select IRQ_MIPS_CPU
>> 378 select I8253
>> 379 select I8259
>> 380 select ISA
>> 381 select SYS_HAS_CPU_R4X00
>> 382 select SYS_SUPPORTS_32BIT_KERNEL
>> 383 select SYS_SUPPORTS_64BIT_KERNEL
>> 384 select SYS_SUPPORTS_100HZ
>> 385 help
>> 386 This a family of machines based on the MIPS R4030 chipset which was
>> 387 used by several vendors to build RISC/os and Windows NT workstations.
>> 388 Members include the Acer PICA, MIPS Magnum 4000, MIPS Millennium and
>> 389 Olivetti M700-10 workstations.
>> 390
>> 391 config MACH_INGENIC
>> 392 bool "Ingenic SoC based machines"
>> 393 select SYS_SUPPORTS_32BIT_KERNEL
>> 394 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 395 select SYS_SUPPORTS_ZBOOT_UART16550
>> 396 select CPU_SUPPORTS_HUGEPAGES
>> 397 select DMA_NONCOHERENT
>> 398 select IRQ_MIPS_CPU
>> 399 select PINCTRL
>> 400 select GPIOLIB
>> 401 select COMMON_CLK
>> 402 select GENERIC_IRQ_CHIP
>> 403 select BUILTIN_DTB if MIPS_NO_APPENDED_DTB
>> 404 select USE_OF
>> 405 select LIBFDT
342 406
343 config STACKTRACE_SUPPORT !! 407 config LANTIQ
344 def_bool y !! 408 bool "Lantiq based platforms"
>> 409 select DMA_NONCOHERENT
>> 410 select IRQ_MIPS_CPU
>> 411 select CEVT_R4K
>> 412 select CSRC_R4K
>> 413 select SYS_HAS_CPU_MIPS32_R1
>> 414 select SYS_HAS_CPU_MIPS32_R2
>> 415 select SYS_SUPPORTS_BIG_ENDIAN
>> 416 select SYS_SUPPORTS_32BIT_KERNEL
>> 417 select SYS_SUPPORTS_MIPS16
>> 418 select SYS_SUPPORTS_MULTITHREADING
>> 419 select SYS_SUPPORTS_VPE_LOADER
>> 420 select SYS_HAS_EARLY_PRINTK
>> 421 select GPIOLIB
>> 422 select SWAP_IO_SPACE
>> 423 select BOOT_RAW
>> 424 select CLKDEV_LOOKUP
>> 425 select USE_OF
>> 426 select PINCTRL
>> 427 select PINCTRL_LANTIQ
>> 428 select ARCH_HAS_RESET_CONTROLLER
>> 429 select RESET_CONTROLLER
>> 430
>> 431 config LASAT
>> 432 bool "LASAT Networks platforms"
>> 433 select CEVT_R4K
>> 434 select CRC32
>> 435 select CSRC_R4K
>> 436 select DMA_NONCOHERENT
>> 437 select SYS_HAS_EARLY_PRINTK
>> 438 select HAVE_PCI
>> 439 select IRQ_MIPS_CPU
>> 440 select PCI_GT64XXX_PCI0
>> 441 select MIPS_NILE4
>> 442 select R5000_CPU_SCACHE
>> 443 select SYS_HAS_CPU_R5000
>> 444 select SYS_SUPPORTS_32BIT_KERNEL
>> 445 select SYS_SUPPORTS_64BIT_KERNEL if BROKEN
>> 446 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 447
>> 448 config MACH_LOONGSON32
>> 449 bool "Loongson-1 family of machines"
>> 450 select SYS_SUPPORTS_ZBOOT
>> 451 help
>> 452 This enables support for the Loongson-1 family of machines.
>> 453
>> 454 Loongson-1 is a family of 32-bit MIPS-compatible SoCs developed by
>> 455 the Institute of Computing Technology (ICT), Chinese Academy of
>> 456 Sciences (CAS).
>> 457
>> 458 config MACH_LOONGSON64
>> 459 bool "Loongson-2/3 family of machines"
>> 460 select SYS_SUPPORTS_ZBOOT
>> 461 help
>> 462 This enables the support of Loongson-2/3 family of machines.
>> 463
>> 464 Loongson-2 is a family of single-core CPUs and Loongson-3 is a
>> 465 family of multi-core CPUs. They are both 64-bit general-purpose
>> 466 MIPS-compatible CPUs. Loongson-2/3 are developed by the Institute
>> 467 of Computing Technology (ICT), Chinese Academy of Sciences (CAS)
>> 468 in the People's Republic of China. The chief architect is Professor
>> 469 Weiwu Hu.
>> 470
>> 471 config MACH_PISTACHIO
>> 472 bool "IMG Pistachio SoC based boards"
>> 473 select BOOT_ELF32
>> 474 select BOOT_RAW
>> 475 select CEVT_R4K
>> 476 select CLKSRC_MIPS_GIC
>> 477 select COMMON_CLK
>> 478 select CSRC_R4K
>> 479 select DMA_NONCOHERENT
>> 480 select GPIOLIB
>> 481 select IRQ_MIPS_CPU
>> 482 select LIBFDT
>> 483 select MFD_SYSCON
>> 484 select MIPS_CPU_SCACHE
>> 485 select MIPS_GIC
>> 486 select PINCTRL
>> 487 select REGULATOR
>> 488 select SYS_HAS_CPU_MIPS32_R2
>> 489 select SYS_SUPPORTS_32BIT_KERNEL
>> 490 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 491 select SYS_SUPPORTS_MIPS_CPS
>> 492 select SYS_SUPPORTS_MULTITHREADING
>> 493 select SYS_SUPPORTS_RELOCATABLE
>> 494 select SYS_SUPPORTS_ZBOOT
>> 495 select SYS_HAS_EARLY_PRINTK
>> 496 select USE_GENERIC_EARLY_PRINTK_8250
>> 497 select USE_OF
>> 498 help
>> 499 This enables support for the IMG Pistachio SoC platform.
>> 500
>> 501 config MIPS_MALTA
>> 502 bool "MIPS Malta board"
>> 503 select ARCH_MAY_HAVE_PC_FDC
>> 504 select ARCH_MIGHT_HAVE_PC_PARPORT
>> 505 select ARCH_MIGHT_HAVE_PC_SERIO
>> 506 select BOOT_ELF32
>> 507 select BOOT_RAW
>> 508 select BUILTIN_DTB
>> 509 select CEVT_R4K
>> 510 select CLKSRC_MIPS_GIC
>> 511 select COMMON_CLK
>> 512 select CSRC_R4K
>> 513 select DMA_MAYBE_COHERENT
>> 514 select GENERIC_ISA_DMA
>> 515 select HAVE_PCSPKR_PLATFORM
>> 516 select HAVE_PCI
>> 517 select I8253
>> 518 select I8259
>> 519 select IRQ_MIPS_CPU
>> 520 select LIBFDT
>> 521 select MIPS_BONITO64
>> 522 select MIPS_CPU_SCACHE
>> 523 select MIPS_GIC
>> 524 select MIPS_L1_CACHE_SHIFT_6
>> 525 select MIPS_MSC
>> 526 select PCI_GT64XXX_PCI0
>> 527 select SMP_UP if SMP
>> 528 select SWAP_IO_SPACE
>> 529 select SYS_HAS_CPU_MIPS32_R1
>> 530 select SYS_HAS_CPU_MIPS32_R2
>> 531 select SYS_HAS_CPU_MIPS32_R3_5
>> 532 select SYS_HAS_CPU_MIPS32_R5
>> 533 select SYS_HAS_CPU_MIPS32_R6
>> 534 select SYS_HAS_CPU_MIPS64_R1
>> 535 select SYS_HAS_CPU_MIPS64_R2
>> 536 select SYS_HAS_CPU_MIPS64_R6
>> 537 select SYS_HAS_CPU_NEVADA
>> 538 select SYS_HAS_CPU_RM7000
>> 539 select SYS_SUPPORTS_32BIT_KERNEL
>> 540 select SYS_SUPPORTS_64BIT_KERNEL
>> 541 select SYS_SUPPORTS_BIG_ENDIAN
>> 542 select SYS_SUPPORTS_HIGHMEM
>> 543 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 544 select SYS_SUPPORTS_MICROMIPS
>> 545 select SYS_SUPPORTS_MIPS16
>> 546 select SYS_SUPPORTS_MIPS_CMP
>> 547 select SYS_SUPPORTS_MIPS_CPS
>> 548 select SYS_SUPPORTS_MULTITHREADING
>> 549 select SYS_SUPPORTS_RELOCATABLE
>> 550 select SYS_SUPPORTS_SMARTMIPS
>> 551 select SYS_SUPPORTS_VPE_LOADER
>> 552 select SYS_SUPPORTS_ZBOOT
>> 553 select USE_OF
>> 554 select ZONE_DMA32 if 64BIT
>> 555 help
>> 556 This enables support for the MIPS Technologies Malta evaluation
>> 557 board.
>> 558
>> 559 config MACH_PIC32
>> 560 bool "Microchip PIC32 Family"
>> 561 help
>> 562 This enables support for the Microchip PIC32 family of platforms.
>> 563
>> 564 Microchip PIC32 is a family of general-purpose 32 bit MIPS core
>> 565 microcontrollers.
>> 566
>> 567 config NEC_MARKEINS
>> 568 bool "NEC EMMA2RH Mark-eins board"
>> 569 select SOC_EMMA2RH
>> 570 select HAVE_PCI
>> 571 help
>> 572 This enables support for the NEC Electronics Mark-eins boards.
345 573
346 config ILLEGAL_POINTER_VALUE !! 574 config MACH_VR41XX
347 hex !! 575 bool "NEC VR4100 series based machines"
348 default 0xdead000000000000 !! 576 select CEVT_R4K
>> 577 select CSRC_R4K
>> 578 select SYS_HAS_CPU_VR41XX
>> 579 select SYS_SUPPORTS_MIPS16
>> 580 select GPIOLIB
>> 581
>> 582 config NXP_STB220
>> 583 bool "NXP STB220 board"
>> 584 select SOC_PNX833X
>> 585 help
>> 586 Support for NXP Semiconductors STB220 Development Board.
>> 587
>> 588 config NXP_STB225
>> 589 bool "NXP 225 board"
>> 590 select SOC_PNX833X
>> 591 select SOC_PNX8335
>> 592 help
>> 593 Support for NXP Semiconductors STB225 Development Board.
>> 594
>> 595 config PMC_MSP
>> 596 bool "PMC-Sierra MSP chipsets"
>> 597 select CEVT_R4K
>> 598 select CSRC_R4K
>> 599 select DMA_NONCOHERENT
>> 600 select SWAP_IO_SPACE
>> 601 select NO_EXCEPT_FILL
>> 602 select BOOT_RAW
>> 603 select SYS_HAS_CPU_MIPS32_R1
>> 604 select SYS_HAS_CPU_MIPS32_R2
>> 605 select SYS_SUPPORTS_32BIT_KERNEL
>> 606 select SYS_SUPPORTS_BIG_ENDIAN
>> 607 select SYS_SUPPORTS_MIPS16
>> 608 select IRQ_MIPS_CPU
>> 609 select SERIAL_8250
>> 610 select SERIAL_8250_CONSOLE
>> 611 select USB_EHCI_BIG_ENDIAN_MMIO
>> 612 select USB_EHCI_BIG_ENDIAN_DESC
>> 613 help
>> 614 This adds support for the PMC-Sierra family of Multi-Service
>> 615 Processor System-On-A-Chips. These parts include a number
>> 616 of integrated peripherals, interfaces and DSPs in addition to
>> 617 a variety of MIPS cores.
>> 618
>> 619 config RALINK
>> 620 bool "Ralink based machines"
>> 621 select CEVT_R4K
>> 622 select CSRC_R4K
>> 623 select BOOT_RAW
>> 624 select DMA_NONCOHERENT
>> 625 select IRQ_MIPS_CPU
>> 626 select USE_OF
>> 627 select SYS_HAS_CPU_MIPS32_R1
>> 628 select SYS_HAS_CPU_MIPS32_R2
>> 629 select SYS_SUPPORTS_32BIT_KERNEL
>> 630 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 631 select SYS_SUPPORTS_MIPS16
>> 632 select SYS_HAS_EARLY_PRINTK
>> 633 select CLKDEV_LOOKUP
>> 634 select ARCH_HAS_RESET_CONTROLLER
>> 635 select RESET_CONTROLLER
>> 636
>> 637 config SGI_IP22
>> 638 bool "SGI IP22 (Indy/Indigo2)"
>> 639 select FW_ARC
>> 640 select FW_ARC32
>> 641 select ARCH_MIGHT_HAVE_PC_SERIO
>> 642 select BOOT_ELF32
>> 643 select CEVT_R4K
>> 644 select CSRC_R4K
>> 645 select DEFAULT_SGI_PARTITION
>> 646 select DMA_NONCOHERENT
>> 647 select HAVE_EISA
>> 648 select I8253
>> 649 select I8259
>> 650 select IP22_CPU_SCACHE
>> 651 select IRQ_MIPS_CPU
>> 652 select GENERIC_ISA_DMA_SUPPORT_BROKEN
>> 653 select SGI_HAS_I8042
>> 654 select SGI_HAS_INDYDOG
>> 655 select SGI_HAS_HAL2
>> 656 select SGI_HAS_SEEQ
>> 657 select SGI_HAS_WD93
>> 658 select SGI_HAS_ZILOG
>> 659 select SWAP_IO_SPACE
>> 660 select SYS_HAS_CPU_R4X00
>> 661 select SYS_HAS_CPU_R5000
>> 662 #
>> 663 # Disable EARLY_PRINTK for now since it leads to overwritten prom
>> 664 # memory during early boot on some machines.
>> 665 #
>> 666 # See http://www.linux-mips.org/cgi-bin/mesg.cgi?a=linux-mips&i=20091119164009.GA15038%40deprecation.cyrius.com
>> 667 # for a more details discussion
>> 668 #
>> 669 # select SYS_HAS_EARLY_PRINTK
>> 670 select SYS_SUPPORTS_32BIT_KERNEL
>> 671 select SYS_SUPPORTS_64BIT_KERNEL
>> 672 select SYS_SUPPORTS_BIG_ENDIAN
>> 673 select MIPS_L1_CACHE_SHIFT_7
>> 674 help
>> 675 This are the SGI Indy, Challenge S and Indigo2, as well as certain
>> 676 OEM variants like the Tandem CMN B006S. To compile a Linux kernel
>> 677 that runs on these, say Y here.
>> 678
>> 679 config SGI_IP27
>> 680 bool "SGI IP27 (Origin200/2000)"
>> 681 select ARCH_HAS_PHYS_TO_DMA
>> 682 select FW_ARC
>> 683 select FW_ARC64
>> 684 select BOOT_ELF64
>> 685 select DEFAULT_SGI_PARTITION
>> 686 select SYS_HAS_EARLY_PRINTK
>> 687 select HAVE_PCI
>> 688 select IRQ_MIPS_CPU
>> 689 select IRQ_DOMAIN_HIERARCHY
>> 690 select NR_CPUS_DEFAULT_64
>> 691 select PCI_DRIVERS_GENERIC
>> 692 select PCI_XTALK_BRIDGE
>> 693 select SYS_HAS_CPU_R10000
>> 694 select SYS_SUPPORTS_64BIT_KERNEL
>> 695 select SYS_SUPPORTS_BIG_ENDIAN
>> 696 select SYS_SUPPORTS_NUMA
>> 697 select SYS_SUPPORTS_SMP
>> 698 select MIPS_L1_CACHE_SHIFT_7
>> 699 help
>> 700 This are the SGI Origin 200, Origin 2000 and Onyx 2 Graphics
>> 701 workstations. To compile a Linux kernel that runs on these, say Y
>> 702 here.
>> 703
>> 704 config SGI_IP28
>> 705 bool "SGI IP28 (Indigo2 R10k)"
>> 706 select FW_ARC
>> 707 select FW_ARC64
>> 708 select ARCH_MIGHT_HAVE_PC_SERIO
>> 709 select BOOT_ELF64
>> 710 select CEVT_R4K
>> 711 select CSRC_R4K
>> 712 select DEFAULT_SGI_PARTITION
>> 713 select DMA_NONCOHERENT
>> 714 select GENERIC_ISA_DMA_SUPPORT_BROKEN
>> 715 select IRQ_MIPS_CPU
>> 716 select HAVE_EISA
>> 717 select I8253
>> 718 select I8259
>> 719 select SGI_HAS_I8042
>> 720 select SGI_HAS_INDYDOG
>> 721 select SGI_HAS_HAL2
>> 722 select SGI_HAS_SEEQ
>> 723 select SGI_HAS_WD93
>> 724 select SGI_HAS_ZILOG
>> 725 select SWAP_IO_SPACE
>> 726 select SYS_HAS_CPU_R10000
>> 727 #
>> 728 # Disable EARLY_PRINTK for now since it leads to overwritten prom
>> 729 # memory during early boot on some machines.
>> 730 #
>> 731 # See http://www.linux-mips.org/cgi-bin/mesg.cgi?a=linux-mips&i=20091119164009.GA15038%40deprecation.cyrius.com
>> 732 # for a more details discussion
>> 733 #
>> 734 # select SYS_HAS_EARLY_PRINTK
>> 735 select SYS_SUPPORTS_64BIT_KERNEL
>> 736 select SYS_SUPPORTS_BIG_ENDIAN
>> 737 select MIPS_L1_CACHE_SHIFT_7
>> 738 help
>> 739 This is the SGI Indigo2 with R10000 processor. To compile a Linux
>> 740 kernel that runs on these, say Y here.
>> 741
>> 742 config SGI_IP32
>> 743 bool "SGI IP32 (O2)"
>> 744 select ARCH_HAS_PHYS_TO_DMA
>> 745 select FW_ARC
>> 746 select FW_ARC32
>> 747 select BOOT_ELF32
>> 748 select CEVT_R4K
>> 749 select CSRC_R4K
>> 750 select DMA_NONCOHERENT
>> 751 select HAVE_PCI
>> 752 select IRQ_MIPS_CPU
>> 753 select R5000_CPU_SCACHE
>> 754 select RM7000_CPU_SCACHE
>> 755 select SYS_HAS_CPU_R5000
>> 756 select SYS_HAS_CPU_R10000 if BROKEN
>> 757 select SYS_HAS_CPU_RM7000
>> 758 select SYS_HAS_CPU_NEVADA
>> 759 select SYS_SUPPORTS_64BIT_KERNEL
>> 760 select SYS_SUPPORTS_BIG_ENDIAN
>> 761 help
>> 762 If you want this kernel to run on SGI O2 workstation, say Y here.
>> 763
>> 764 config SIBYTE_CRHINE
>> 765 bool "Sibyte BCM91120C-CRhine"
>> 766 select BOOT_ELF32
>> 767 select SIBYTE_BCM1120
>> 768 select SWAP_IO_SPACE
>> 769 select SYS_HAS_CPU_SB1
>> 770 select SYS_SUPPORTS_BIG_ENDIAN
>> 771 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 772
>> 773 config SIBYTE_CARMEL
>> 774 bool "Sibyte BCM91120x-Carmel"
>> 775 select BOOT_ELF32
>> 776 select SIBYTE_BCM1120
>> 777 select SWAP_IO_SPACE
>> 778 select SYS_HAS_CPU_SB1
>> 779 select SYS_SUPPORTS_BIG_ENDIAN
>> 780 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 781
>> 782 config SIBYTE_CRHONE
>> 783 bool "Sibyte BCM91125C-CRhone"
>> 784 select BOOT_ELF32
>> 785 select SIBYTE_BCM1125
>> 786 select SWAP_IO_SPACE
>> 787 select SYS_HAS_CPU_SB1
>> 788 select SYS_SUPPORTS_BIG_ENDIAN
>> 789 select SYS_SUPPORTS_HIGHMEM
>> 790 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 791
>> 792 config SIBYTE_RHONE
>> 793 bool "Sibyte BCM91125E-Rhone"
>> 794 select BOOT_ELF32
>> 795 select SIBYTE_BCM1125H
>> 796 select SWAP_IO_SPACE
>> 797 select SYS_HAS_CPU_SB1
>> 798 select SYS_SUPPORTS_BIG_ENDIAN
>> 799 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 800
>> 801 config SIBYTE_SWARM
>> 802 bool "Sibyte BCM91250A-SWARM"
>> 803 select BOOT_ELF32
>> 804 select HAVE_PATA_PLATFORM
>> 805 select SIBYTE_SB1250
>> 806 select SWAP_IO_SPACE
>> 807 select SYS_HAS_CPU_SB1
>> 808 select SYS_SUPPORTS_BIG_ENDIAN
>> 809 select SYS_SUPPORTS_HIGHMEM
>> 810 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 811 select ZONE_DMA32 if 64BIT
>> 812 select SWIOTLB if ARCH_DMA_ADDR_T_64BIT && PCI
>> 813
>> 814 config SIBYTE_LITTLESUR
>> 815 bool "Sibyte BCM91250C2-LittleSur"
>> 816 select BOOT_ELF32
>> 817 select HAVE_PATA_PLATFORM
>> 818 select SIBYTE_SB1250
>> 819 select SWAP_IO_SPACE
>> 820 select SYS_HAS_CPU_SB1
>> 821 select SYS_SUPPORTS_BIG_ENDIAN
>> 822 select SYS_SUPPORTS_HIGHMEM
>> 823 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 824 select ZONE_DMA32 if 64BIT
>> 825
>> 826 config SIBYTE_SENTOSA
>> 827 bool "Sibyte BCM91250E-Sentosa"
>> 828 select BOOT_ELF32
>> 829 select SIBYTE_SB1250
>> 830 select SWAP_IO_SPACE
>> 831 select SYS_HAS_CPU_SB1
>> 832 select SYS_SUPPORTS_BIG_ENDIAN
>> 833 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 834 select SWIOTLB if ARCH_DMA_ADDR_T_64BIT && PCI
>> 835
>> 836 config SIBYTE_BIGSUR
>> 837 bool "Sibyte BCM91480B-BigSur"
>> 838 select BOOT_ELF32
>> 839 select NR_CPUS_DEFAULT_4
>> 840 select SIBYTE_BCM1x80
>> 841 select SWAP_IO_SPACE
>> 842 select SYS_HAS_CPU_SB1
>> 843 select SYS_SUPPORTS_BIG_ENDIAN
>> 844 select SYS_SUPPORTS_HIGHMEM
>> 845 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 846 select ZONE_DMA32 if 64BIT
>> 847 select SWIOTLB if ARCH_DMA_ADDR_T_64BIT && PCI
>> 848
>> 849 config SNI_RM
>> 850 bool "SNI RM200/300/400"
>> 851 select FW_ARC if CPU_LITTLE_ENDIAN
>> 852 select FW_ARC32 if CPU_LITTLE_ENDIAN
>> 853 select FW_SNIPROM if CPU_BIG_ENDIAN
>> 854 select ARCH_MAY_HAVE_PC_FDC
>> 855 select ARCH_MIGHT_HAVE_PC_PARPORT
>> 856 select ARCH_MIGHT_HAVE_PC_SERIO
>> 857 select BOOT_ELF32
>> 858 select CEVT_R4K
>> 859 select CSRC_R4K
>> 860 select DEFAULT_SGI_PARTITION if CPU_BIG_ENDIAN
>> 861 select DMA_NONCOHERENT
>> 862 select GENERIC_ISA_DMA
>> 863 select HAVE_EISA
>> 864 select HAVE_PCSPKR_PLATFORM
>> 865 select HAVE_PCI
>> 866 select IRQ_MIPS_CPU
>> 867 select I8253
>> 868 select I8259
>> 869 select ISA
>> 870 select MIPS_L1_CACHE_SHIFT_6
>> 871 select SWAP_IO_SPACE if CPU_BIG_ENDIAN
>> 872 select SYS_HAS_CPU_R4X00
>> 873 select SYS_HAS_CPU_R5000
>> 874 select SYS_HAS_CPU_R10000
>> 875 select R5000_CPU_SCACHE
>> 876 select SYS_HAS_EARLY_PRINTK
>> 877 select SYS_SUPPORTS_32BIT_KERNEL
>> 878 select SYS_SUPPORTS_64BIT_KERNEL
>> 879 select SYS_SUPPORTS_BIG_ENDIAN
>> 880 select SYS_SUPPORTS_HIGHMEM
>> 881 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 882 help
>> 883 The SNI RM200/300/400 are MIPS-based machines manufactured by
>> 884 Siemens Nixdorf Informationssysteme (SNI), parent company of Pyramid
>> 885 Technology and now in turn merged with Fujitsu. Say Y here to
>> 886 support this machine type.
>> 887
>> 888 config MACH_TX39XX
>> 889 bool "Toshiba TX39 series based machines"
>> 890
>> 891 config MACH_TX49XX
>> 892 bool "Toshiba TX49 series based machines"
>> 893
>> 894 config MIKROTIK_RB532
>> 895 bool "Mikrotik RB532 boards"
>> 896 select CEVT_R4K
>> 897 select CSRC_R4K
>> 898 select DMA_NONCOHERENT
>> 899 select HAVE_PCI
>> 900 select IRQ_MIPS_CPU
>> 901 select SYS_HAS_CPU_MIPS32_R1
>> 902 select SYS_SUPPORTS_32BIT_KERNEL
>> 903 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 904 select SWAP_IO_SPACE
>> 905 select BOOT_RAW
>> 906 select GPIOLIB
>> 907 select MIPS_L1_CACHE_SHIFT_4
>> 908 help
>> 909 Support the Mikrotik(tm) RouterBoard 532 series,
>> 910 based on the IDT RC32434 SoC.
>> 911
>> 912 config CAVIUM_OCTEON_SOC
>> 913 bool "Cavium Networks Octeon SoC based boards"
>> 914 select CEVT_R4K
>> 915 select ARCH_HAS_PHYS_TO_DMA
>> 916 select HAVE_RAPIDIO
>> 917 select PHYS_ADDR_T_64BIT
>> 918 select SYS_SUPPORTS_64BIT_KERNEL
>> 919 select SYS_SUPPORTS_BIG_ENDIAN
>> 920 select EDAC_SUPPORT
>> 921 select EDAC_ATOMIC_SCRUB
>> 922 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 923 select SYS_SUPPORTS_HOTPLUG_CPU if CPU_BIG_ENDIAN
>> 924 select SYS_HAS_EARLY_PRINTK
>> 925 select SYS_HAS_CPU_CAVIUM_OCTEON
>> 926 select HAVE_PCI
>> 927 select ZONE_DMA32
>> 928 select HOLES_IN_ZONE
>> 929 select GPIOLIB
>> 930 select LIBFDT
>> 931 select USE_OF
>> 932 select ARCH_SPARSEMEM_ENABLE
>> 933 select SYS_SUPPORTS_SMP
>> 934 select NR_CPUS_DEFAULT_64
>> 935 select MIPS_NR_CPU_NR_MAP_1024
>> 936 select BUILTIN_DTB
>> 937 select MTD_COMPLEX_MAPPINGS
>> 938 select SWIOTLB
>> 939 select SYS_SUPPORTS_RELOCATABLE
>> 940 help
>> 941 This option supports all of the Octeon reference boards from Cavium
>> 942 Networks. It builds a kernel that dynamically determines the Octeon
>> 943 CPU type and supports all known board reference implementations.
>> 944 Some of the supported boards are:
>> 945 EBT3000
>> 946 EBH3000
>> 947 EBH3100
>> 948 Thunder
>> 949 Kodama
>> 950 Hikari
>> 951 Say Y here for most Octeon reference boards.
>> 952
>> 953 config NLM_XLR_BOARD
>> 954 bool "Netlogic XLR/XLS based systems"
>> 955 select BOOT_ELF32
>> 956 select NLM_COMMON
>> 957 select SYS_HAS_CPU_XLR
>> 958 select SYS_SUPPORTS_SMP
>> 959 select HAVE_PCI
>> 960 select SWAP_IO_SPACE
>> 961 select SYS_SUPPORTS_32BIT_KERNEL
>> 962 select SYS_SUPPORTS_64BIT_KERNEL
>> 963 select PHYS_ADDR_T_64BIT
>> 964 select SYS_SUPPORTS_BIG_ENDIAN
>> 965 select SYS_SUPPORTS_HIGHMEM
>> 966 select NR_CPUS_DEFAULT_32
>> 967 select CEVT_R4K
>> 968 select CSRC_R4K
>> 969 select IRQ_MIPS_CPU
>> 970 select ZONE_DMA32 if 64BIT
>> 971 select SYNC_R4K
>> 972 select SYS_HAS_EARLY_PRINTK
>> 973 select SYS_SUPPORTS_ZBOOT
>> 974 select SYS_SUPPORTS_ZBOOT_UART16550
>> 975 help
>> 976 Support for systems based on Netlogic XLR and XLS processors.
>> 977 Say Y here if you have a XLR or XLS based board.
>> 978
>> 979 config NLM_XLP_BOARD
>> 980 bool "Netlogic XLP based systems"
>> 981 select BOOT_ELF32
>> 982 select NLM_COMMON
>> 983 select SYS_HAS_CPU_XLP
>> 984 select SYS_SUPPORTS_SMP
>> 985 select HAVE_PCI
>> 986 select SYS_SUPPORTS_32BIT_KERNEL
>> 987 select SYS_SUPPORTS_64BIT_KERNEL
>> 988 select PHYS_ADDR_T_64BIT
>> 989 select GPIOLIB
>> 990 select SYS_SUPPORTS_BIG_ENDIAN
>> 991 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 992 select SYS_SUPPORTS_HIGHMEM
>> 993 select NR_CPUS_DEFAULT_32
>> 994 select CEVT_R4K
>> 995 select CSRC_R4K
>> 996 select IRQ_MIPS_CPU
>> 997 select ZONE_DMA32 if 64BIT
>> 998 select SYNC_R4K
>> 999 select SYS_HAS_EARLY_PRINTK
>> 1000 select USE_OF
>> 1001 select SYS_SUPPORTS_ZBOOT
>> 1002 select SYS_SUPPORTS_ZBOOT_UART16550
>> 1003 help
>> 1004 This board is based on Netlogic XLP Processor.
>> 1005 Say Y here if you have a XLP based board.
>> 1006
>> 1007 config MIPS_PARAVIRT
>> 1008 bool "Para-Virtualized guest system"
>> 1009 select CEVT_R4K
>> 1010 select CSRC_R4K
>> 1011 select SYS_SUPPORTS_64BIT_KERNEL
>> 1012 select SYS_SUPPORTS_32BIT_KERNEL
>> 1013 select SYS_SUPPORTS_BIG_ENDIAN
>> 1014 select SYS_SUPPORTS_SMP
>> 1015 select NR_CPUS_DEFAULT_4
>> 1016 select SYS_HAS_EARLY_PRINTK
>> 1017 select SYS_HAS_CPU_MIPS32_R2
>> 1018 select SYS_HAS_CPU_MIPS64_R2
>> 1019 select SYS_HAS_CPU_CAVIUM_OCTEON
>> 1020 select HAVE_PCI
>> 1021 select SWAP_IO_SPACE
>> 1022 help
>> 1023 This option supports guest running under ????
349 1024
350 config LOCKDEP_SUPPORT !! 1025 endchoice
351 def_bool y <<
352 1026
353 config GENERIC_BUG !! 1027 source "arch/mips/alchemy/Kconfig"
354 def_bool y !! 1028 source "arch/mips/ath25/Kconfig"
355 depends on BUG !! 1029 source "arch/mips/ath79/Kconfig"
>> 1030 source "arch/mips/bcm47xx/Kconfig"
>> 1031 source "arch/mips/bcm63xx/Kconfig"
>> 1032 source "arch/mips/bmips/Kconfig"
>> 1033 source "arch/mips/generic/Kconfig"
>> 1034 source "arch/mips/jazz/Kconfig"
>> 1035 source "arch/mips/jz4740/Kconfig"
>> 1036 source "arch/mips/lantiq/Kconfig"
>> 1037 source "arch/mips/lasat/Kconfig"
>> 1038 source "arch/mips/pic32/Kconfig"
>> 1039 source "arch/mips/pistachio/Kconfig"
>> 1040 source "arch/mips/pmcs-msp71xx/Kconfig"
>> 1041 source "arch/mips/ralink/Kconfig"
>> 1042 source "arch/mips/sgi-ip27/Kconfig"
>> 1043 source "arch/mips/sibyte/Kconfig"
>> 1044 source "arch/mips/txx9/Kconfig"
>> 1045 source "arch/mips/vr41xx/Kconfig"
>> 1046 source "arch/mips/cavium-octeon/Kconfig"
>> 1047 source "arch/mips/loongson32/Kconfig"
>> 1048 source "arch/mips/loongson64/Kconfig"
>> 1049 source "arch/mips/netlogic/Kconfig"
>> 1050 source "arch/mips/paravirt/Kconfig"
356 1051
357 config GENERIC_BUG_RELATIVE_POINTERS !! 1052 endmenu
358 def_bool y <<
359 depends on GENERIC_BUG <<
360 1053
361 config GENERIC_HWEIGHT 1054 config GENERIC_HWEIGHT
362 def_bool y <<
363 <<
364 config GENERIC_CSUM <<
365 def_bool y <<
366 <<
367 config GENERIC_CALIBRATE_DELAY <<
368 def_bool y <<
369 <<
370 config SMP <<
371 def_bool y <<
372 <<
373 config KERNEL_MODE_NEON <<
374 def_bool y <<
375 <<
376 config FIX_EARLYCON_MEM <<
377 def_bool y <<
378 <<
379 config PGTABLE_LEVELS <<
380 int <<
381 default 2 if ARM64_16K_PAGES && ARM64_ <<
382 default 2 if ARM64_64K_PAGES && ARM64_ <<
383 default 3 if ARM64_64K_PAGES && (ARM64 <<
384 default 3 if ARM64_4K_PAGES && ARM64_V <<
385 default 3 if ARM64_16K_PAGES && ARM64_ <<
386 default 4 if ARM64_16K_PAGES && (ARM64 <<
387 default 4 if !ARM64_64K_PAGES && ARM64 <<
388 default 5 if ARM64_4K_PAGES && ARM64_V <<
389 <<
390 config ARCH_SUPPORTS_UPROBES <<
391 def_bool y <<
392 <<
393 config ARCH_PROC_KCORE_TEXT <<
394 def_bool y <<
395 <<
396 config BROKEN_GAS_INST <<
397 def_bool !$(as-instr,1:\n.inst 0\n.rep <<
398 <<
399 config BUILTIN_RETURN_ADDRESS_STRIPS_PAC <<
400 bool <<
401 # Clang's __builtin_return_address() s <<
402 # https://github.com/llvm/llvm-project <<
403 default y if CC_IS_CLANG <<
404 # GCC's __builtin_return_address() str <<
405 # and this was backported to 10.2.0, 9 <<
406 # https://gcc.gnu.org/bugzilla/show_bu <<
407 default y if CC_IS_GCC && (GCC_VERSION <<
408 default y if CC_IS_GCC && (GCC_VERSION <<
409 default y if CC_IS_GCC && (GCC_VERSION <<
410 default y if CC_IS_GCC && (GCC_VERSION <<
411 default n <<
412 <<
413 config KASAN_SHADOW_OFFSET <<
414 hex <<
415 depends on KASAN_GENERIC || KASAN_SW_T <<
416 default 0xdfff800000000000 if (ARM64_V <<
417 default 0xdfffc00000000000 if (ARM64_V <<
418 default 0xdffffe0000000000 if ARM64_VA <<
419 default 0xdfffffc000000000 if ARM64_VA <<
420 default 0xdffffff800000000 if ARM64_VA <<
421 default 0xefff800000000000 if (ARM64_V <<
422 default 0xefffc00000000000 if (ARM64_V <<
423 default 0xeffffe0000000000 if ARM64_VA <<
424 default 0xefffffc000000000 if ARM64_VA <<
425 default 0xeffffff800000000 if ARM64_VA <<
426 default 0xffffffffffffffff <<
427 <<
428 config UNWIND_TABLES <<
429 bool <<
430 <<
431 source "arch/arm64/Kconfig.platforms" <<
432 <<
433 menu "Kernel Features" <<
434 <<
435 menu "ARM errata workarounds via the alternati <<
436 <<
437 config AMPERE_ERRATUM_AC03_CPU_38 <<
438 bool "AmpereOne: AC03_CPU_38: Certain <<
439 default y <<
440 help <<
441 This option adds an alternative code <<
442 errata AC03_CPU_38 and AC04_CPU_10 o <<
443 <<
444 The affected design reports FEAT_HAF <<
445 ID_AA64MMFR1_EL1.HAFDBS, but (V)TCR_ <<
446 as required by the architecture. The <<
447 implementation suffers from an addit <<
448 A/D updates can occur after a PTE ha <<
449 <<
450 The workaround forces KVM to explici <<
451 which avoids enabling unadvertised h <<
452 at stage-2. <<
453 <<
454 If unsure, say Y. <<
455 <<
456 config ARM64_WORKAROUND_CLEAN_CACHE <<
457 bool 1055 bool
458 <<
459 config ARM64_ERRATUM_826319 <<
460 bool "Cortex-A53: 826319: System might <<
461 default y 1056 default y
462 select ARM64_WORKAROUND_CLEAN_CACHE <<
463 help <<
464 This option adds an alternative code <<
465 erratum 826319 on Cortex-A53 parts u <<
466 AXI master interface and an L2 cache <<
467 1057
468 If a Cortex-A53 uses an AMBA AXI4 AC !! 1058 config GENERIC_CALIBRATE_DELAY
469 and is unable to accept a certain wr !! 1059 bool
470 not progress on read data presented <<
471 system can deadlock. <<
472 <<
473 The workaround promotes data cache c <<
474 data cache clean-and-invalidate. <<
475 Please note that this does not neces <<
476 as it depends on the alternative fra <<
477 the kernel if an affected CPU is det <<
478 <<
479 If unsure, say Y. <<
480 <<
481 config ARM64_ERRATUM_827319 <<
482 bool "Cortex-A53: 827319: Data cache c <<
483 default y 1060 default y
484 select ARM64_WORKAROUND_CLEAN_CACHE <<
485 help <<
486 This option adds an alternative code <<
487 erratum 827319 on Cortex-A53 parts u <<
488 master interface and an L2 cache. <<
489 <<
490 Under certain conditions this erratu <<
491 to occur at the same time as another <<
492 on the AMBA 5 CHI interface, which c <<
493 interconnect reorders the two transa <<
494 <<
495 The workaround promotes data cache c <<
496 data cache clean-and-invalidate. <<
497 Please note that this does not neces <<
498 as it depends on the alternative fra <<
499 the kernel if an affected CPU is det <<
500 <<
501 If unsure, say Y. <<
502 1061
503 config ARM64_ERRATUM_824069 !! 1062 config SCHED_OMIT_FRAME_POINTER
504 bool "Cortex-A53: 824069: Cache line m !! 1063 bool
505 default y 1064 default y
506 select ARM64_WORKAROUND_CLEAN_CACHE <<
507 help <<
508 This option adds an alternative code <<
509 erratum 824069 on Cortex-A53 parts u <<
510 to a coherent interconnect. <<
511 <<
512 If a Cortex-A53 processor is executi <<
513 write instruction at the same time a <<
514 cluster is executing a cache mainten <<
515 address, then this erratum might cau <<
516 incorrectly marked as dirty. <<
517 <<
518 The workaround promotes data cache c <<
519 data cache clean-and-invalidate. <<
520 Please note that this option does no <<
521 workaround, as it depends on the alt <<
522 only patch the kernel if an affected <<
523 1065
524 If unsure, say Y. !! 1066 #
>> 1067 # Select some configuration options automatically based on user selections.
>> 1068 #
>> 1069 config FW_ARC
>> 1070 bool
525 1071
526 config ARM64_ERRATUM_819472 !! 1072 config ARCH_MAY_HAVE_PC_FDC
527 bool "Cortex-A53: 819472: Store exclus !! 1073 bool
528 default y <<
529 select ARM64_WORKAROUND_CLEAN_CACHE <<
530 help <<
531 This option adds an alternative code <<
532 erratum 819472 on Cortex-A53 parts u <<
533 present when it is connected to a co <<
534 <<
535 If the processor is executing a load <<
536 the same time as a processor in anot <<
537 maintenance operation to the same ad <<
538 cause data corruption. <<
539 <<
540 The workaround promotes data cache c <<
541 data cache clean-and-invalidate. <<
542 Please note that this does not neces <<
543 as it depends on the alternative fra <<
544 the kernel if an affected CPU is det <<
545 1074
546 If unsure, say Y. !! 1075 config BOOT_RAW
>> 1076 bool
547 1077
548 config ARM64_ERRATUM_832075 !! 1078 config CEVT_BCM1480
549 bool "Cortex-A57: 832075: possible dea !! 1079 bool
550 default y <<
551 help <<
552 This option adds an alternative code <<
553 erratum 832075 on Cortex-A57 parts u <<
554 1080
555 Affected Cortex-A57 parts might dead !! 1081 config CEVT_DS1287
556 instructions to Write-Back memory ar !! 1082 bool
557 1083
558 The workaround is to promote device !! 1084 config CEVT_GT641XX
559 semantics. !! 1085 bool
560 Please note that this does not neces <<
561 as it depends on the alternative fra <<
562 the kernel if an affected CPU is det <<
563 1086
564 If unsure, say Y. !! 1087 config CEVT_R4K
>> 1088 bool
565 1089
566 config ARM64_ERRATUM_834220 !! 1090 config CEVT_SB1250
567 bool "Cortex-A57: 834220: Stage 2 tran !! 1091 bool
568 depends on KVM <<
569 help <<
570 This option adds an alternative code <<
571 erratum 834220 on Cortex-A57 parts u <<
572 <<
573 Affected Cortex-A57 parts might repo <<
574 fault as the result of a Stage 1 fau <<
575 page boundary when there is a permis <<
576 alignment fault at Stage 1 and a tra <<
577 <<
578 The workaround is to verify that the <<
579 doesn't generate a fault before hand <<
580 Please note that this does not neces <<
581 as it depends on the alternative fra <<
582 the kernel if an affected CPU is det <<
583 1092
584 If unsure, say N. !! 1093 config CEVT_TXX9
>> 1094 bool
585 1095
586 config ARM64_ERRATUM_1742098 !! 1096 config CSRC_BCM1480
587 bool "Cortex-A57/A72: 1742098: ELR rec !! 1097 bool
588 depends on COMPAT <<
589 default y <<
590 help <<
591 This option removes the AES hwcap fo <<
592 workaround erratum 1742098 on Cortex <<
593 <<
594 Affected parts may corrupt the AES s <<
595 taken between a pair of AES instruct <<
596 are only present if the cryptography <<
597 All software should have a fallback <<
598 that don't implement the cryptograph <<
599 1098
600 If unsure, say Y. !! 1099 config CSRC_IOASIC
>> 1100 bool
601 1101
602 config ARM64_ERRATUM_845719 !! 1102 config CSRC_R4K
603 bool "Cortex-A53: 845719: a load might !! 1103 bool
604 depends on COMPAT <<
605 default y <<
606 help <<
607 This option adds an alternative code <<
608 erratum 845719 on Cortex-A53 parts u <<
609 <<
610 When running a compat (AArch32) user <<
611 part, a load at EL0 from a virtual a <<
612 bits of the virtual address used by <<
613 might return incorrect data. <<
614 <<
615 The workaround is to write the conte <<
616 return to a 32-bit task. <<
617 Please note that this does not neces <<
618 as it depends on the alternative fra <<
619 the kernel if an affected CPU is det <<
620 1104
621 If unsure, say Y. !! 1105 config CSRC_SB1250
>> 1106 bool
622 1107
623 config ARM64_ERRATUM_843419 !! 1108 config MIPS_CLOCK_VSYSCALL
624 bool "Cortex-A53: 843419: A load or st !! 1109 def_bool CSRC_R4K || CLKSRC_MIPS_GIC
625 default y <<
626 help <<
627 This option links the kernel with '- <<
628 enables PLT support to replace certa <<
629 cause subsequent memory accesses to <<
630 Cortex-A53 parts up to r0p4. <<
631 1110
632 If unsure, say Y. !! 1111 config GPIO_TXX9
>> 1112 select GPIOLIB
>> 1113 bool
633 1114
634 config ARM64_LD_HAS_FIX_ERRATUM_843419 !! 1115 config FW_CFE
635 def_bool $(ld-option,--fix-cortex-a53- !! 1116 bool
636 1117
637 config ARM64_ERRATUM_1024718 !! 1118 config ARCH_SUPPORTS_UPROBES
638 bool "Cortex-A55: 1024718: Update of D !! 1119 bool
639 default y <<
640 help <<
641 This option adds a workaround for AR <<
642 1120
643 Affected Cortex-A55 cores (all revis !! 1121 config DMA_MAYBE_COHERENT
644 update of the hardware dirty bit whe !! 1122 select ARCH_HAS_DMA_COHERENCE_H
645 without a break-before-make. The wor !! 1123 select DMA_NONCOHERENT
646 of hardware DBM locally on the affec !! 1124 bool
647 this erratum will continue to use th <<
648 1125
649 If unsure, say Y. !! 1126 config DMA_PERDEV_COHERENT
>> 1127 bool
>> 1128 select ARCH_HAS_SETUP_DMA_OPS
>> 1129 select DMA_NONCOHERENT
650 1130
651 config ARM64_ERRATUM_1418040 !! 1131 config DMA_NONCOHERENT
652 bool "Cortex-A76/Neoverse-N1: MRC read !! 1132 bool
653 default y !! 1133 #
654 depends on COMPAT !! 1134 # MIPS allows mixing "slightly different" Cacheability and Coherency
655 help !! 1135 # Attribute bits. It is believed that the uncached access through
656 This option adds a workaround for AR !! 1136 # KSEG1 and the implementation specific "uncached accelerated" used
657 errata 1188873 and 1418040. !! 1137 # by pgprot_writcombine can be mixed, and the latter sometimes provides
>> 1138 # significant advantages.
>> 1139 #
>> 1140 select ARCH_HAS_DMA_WRITE_COMBINE
>> 1141 select ARCH_HAS_SYNC_DMA_FOR_DEVICE
>> 1142 select ARCH_HAS_UNCACHED_SEGMENT
>> 1143 select NEED_DMA_MAP_STATE
>> 1144 select ARCH_HAS_DMA_COHERENT_TO_PFN
>> 1145 select DMA_NONCOHERENT_CACHE_SYNC
658 1146
659 Affected Cortex-A76/Neoverse-N1 core !! 1147 config SYS_HAS_EARLY_PRINTK
660 cause register corruption when acces !! 1148 bool
661 from AArch32 userspace. <<
662 1149
663 If unsure, say Y. !! 1150 config SYS_SUPPORTS_HOTPLUG_CPU
>> 1151 bool
664 1152
665 config ARM64_WORKAROUND_SPECULATIVE_AT !! 1153 config MIPS_BONITO64
666 bool 1154 bool
667 1155
668 config ARM64_ERRATUM_1165522 !! 1156 config MIPS_MSC
669 bool "Cortex-A76: 1165522: Speculative !! 1157 bool
670 default y <<
671 select ARM64_WORKAROUND_SPECULATIVE_AT <<
672 help <<
673 This option adds a workaround for AR <<
674 1158
675 Affected Cortex-A76 cores (r0p0, r1p !! 1159 config MIPS_NILE4
676 corrupted TLBs by speculating an AT !! 1160 bool
677 context switch. <<
678 1161
679 If unsure, say Y. !! 1162 config SYNC_R4K
>> 1163 bool
680 1164
681 config ARM64_ERRATUM_1319367 !! 1165 config MIPS_MACHINE
682 bool "Cortex-A57/A72: 1319537: Specula !! 1166 def_bool n
683 default y <<
684 select ARM64_WORKAROUND_SPECULATIVE_AT <<
685 help <<
686 This option adds work arounds for AR <<
687 and A72 erratum 1319367 <<
688 1167
689 Cortex-A57 and A72 cores could end-u !! 1168 config NO_IOPORT_MAP
690 speculating an AT instruction during !! 1169 def_bool n
691 1170
692 If unsure, say Y. !! 1171 config GENERIC_CSUM
>> 1172 bool
>> 1173 default y if !CPU_HAS_LOAD_STORE_LR
693 1174
694 config ARM64_ERRATUM_1530923 !! 1175 config GENERIC_ISA_DMA
695 bool "Cortex-A55: 1530923: Speculative !! 1176 bool
696 default y !! 1177 select ZONE_DMA if GENERIC_ISA_DMA_SUPPORT_BROKEN=n
697 select ARM64_WORKAROUND_SPECULATIVE_AT !! 1178 select ISA_DMA_API
698 help <<
699 This option adds a workaround for AR <<
700 1179
701 Affected Cortex-A55 cores (r0p0, r0p !! 1180 config GENERIC_ISA_DMA_SUPPORT_BROKEN
702 corrupted TLBs by speculating an AT !! 1181 bool
703 context switch. !! 1182 select GENERIC_ISA_DMA
704 1183
705 If unsure, say Y. !! 1184 config ISA_DMA_API
>> 1185 bool
706 1186
707 config ARM64_WORKAROUND_REPEAT_TLBI !! 1187 config HOLES_IN_ZONE
708 bool 1188 bool
709 1189
710 config ARM64_ERRATUM_2441007 !! 1190 config SYS_SUPPORTS_RELOCATABLE
711 bool "Cortex-A55: Completion of affect !! 1191 bool
712 select ARM64_WORKAROUND_REPEAT_TLBI <<
713 help 1192 help
714 This option adds a workaround for AR !! 1193 Selected if the platform supports relocating the kernel.
>> 1194 The platform must provide plat_get_fdt() if it selects CONFIG_USE_OF
>> 1195 to allow access to command line and entropy sources.
715 1196
716 Under very rare circumstances, affec !! 1197 config MIPS_CBPF_JIT
717 may not handle a race between a brea !! 1198 def_bool y
718 CPU, and another CPU accessing the s !! 1199 depends on BPF_JIT && HAVE_CBPF_JIT
719 store to a page that has been unmapp <<
720 <<
721 Work around this by adding the affec <<
722 TLB sequences to be done twice. <<
723 <<
724 If unsure, say N. <<
725 1200
726 config ARM64_ERRATUM_1286807 !! 1201 config MIPS_EBPF_JIT
727 bool "Cortex-A76: Modification of the !! 1202 def_bool y
728 select ARM64_WORKAROUND_REPEAT_TLBI !! 1203 depends on BPF_JIT && HAVE_EBPF_JIT
729 help <<
730 This option adds a workaround for AR <<
731 <<
732 On the affected Cortex-A76 cores (r0 <<
733 address for a cacheable mapping of a <<
734 accessed by a core while another cor <<
735 address to a new physical page using <<
736 break-before-make sequence, then und <<
737 TLBI+DSB completes before a read usi <<
738 invalidated has been observed by oth <<
739 workaround repeats the TLBI+DSB oper <<
740 1204
741 If unsure, say N. <<
742 1205
743 config ARM64_ERRATUM_1463225 !! 1206 #
744 bool "Cortex-A76: Software Step might !! 1207 # Endianness selection. Sufficiently obscure so many users don't know what to
745 default y !! 1208 # answer,so we try hard to limit the available choices. Also the use of a
>> 1209 # choice statement should be more obvious to the user.
>> 1210 #
>> 1211 choice
>> 1212 prompt "Endianness selection"
746 help 1213 help
747 This option adds a workaround for Ar !! 1214 Some MIPS machines can be configured for either little or big endian
>> 1215 byte order. These modes require different kernels and a different
>> 1216 Linux distribution. In general there is one preferred byteorder for a
>> 1217 particular system but some systems are just as commonly used in the
>> 1218 one or the other endianness.
748 1219
749 On the affected Cortex-A76 cores (r0 !! 1220 config CPU_BIG_ENDIAN
750 of a system call instruction (SVC) c !! 1221 bool "Big endian"
751 subsequent interrupts when software !! 1222 depends on SYS_SUPPORTS_BIG_ENDIAN
752 exception handler of the system call <<
753 is enabled or VHE is in use. <<
754 1223
755 Work around the erratum by triggerin !! 1224 config CPU_LITTLE_ENDIAN
756 when handling a system call from a t !! 1225 bool "Little endian"
757 in a VHE configuration of the kernel !! 1226 depends on SYS_SUPPORTS_LITTLE_ENDIAN
758 1227
759 If unsure, say Y. !! 1228 endchoice
760 1229
761 config ARM64_ERRATUM_1542419 !! 1230 config EXPORT_UASM
762 bool "Neoverse-N1: workaround mis-orde !! 1231 bool
763 help <<
764 This option adds a workaround for AR <<
765 1542419. <<
766 1232
767 Affected Neoverse-N1 cores could exe !! 1233 config SYS_SUPPORTS_APM_EMULATION
768 modified by another CPU. The workaro !! 1234 bool
769 counterpart. <<
770 1235
771 Workaround the issue by hiding the D !! 1236 config SYS_SUPPORTS_BIG_ENDIAN
772 forces user-space to perform cache m !! 1237 bool
773 1238
774 If unsure, say N. !! 1239 config SYS_SUPPORTS_LITTLE_ENDIAN
>> 1240 bool
775 1241
776 config ARM64_ERRATUM_1508412 !! 1242 config SYS_SUPPORTS_HUGETLBFS
777 bool "Cortex-A77: 1508412: workaround !! 1243 bool
>> 1244 depends on CPU_SUPPORTS_HUGEPAGES
778 default y 1245 default y
779 help <<
780 This option adds a workaround for Ar <<
781 <<
782 Affected Cortex-A77 cores (r0p0, r1p <<
783 of a store-exclusive or read of PAR_ <<
784 non-cacheable memory attributes. The <<
785 counterpart. <<
786 1246
787 KVM guests must also have the workar !! 1247 config MIPS_HUGE_TLB_SUPPORT
788 deadlock the system. !! 1248 def_bool HUGETLB_PAGE || TRANSPARENT_HUGEPAGE
789 1249
790 Work around the issue by inserting D !! 1250 config IRQ_CPU_RM7K
791 register reads and warning KVM users <<
792 to prevent a speculative PAR_EL1 rea <<
793 <<
794 If unsure, say Y. <<
795 <<
796 config ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MO <<
797 bool 1251 bool
798 1252
799 config ARM64_ERRATUM_2051678 !! 1253 config IRQ_MSP_SLP
800 bool "Cortex-A510: 2051678: disable Ha !! 1254 bool
801 default y <<
802 help <<
803 This options adds the workaround for <<
804 Affected Cortex-A510 might not respe <<
805 hardware update of the page table's <<
806 is to not enable the feature on affe <<
807 <<
808 If unsure, say Y. <<
809 1255
810 config ARM64_ERRATUM_2077057 !! 1256 config IRQ_MSP_CIC
811 bool "Cortex-A510: 2077057: workaround !! 1257 bool
812 default y <<
813 help <<
814 This option adds the workaround for <<
815 Affected Cortex-A510 may corrupt SPS <<
816 expected, but a Pointer Authenticati <<
817 erratum causes SPSR_EL1 to be copied <<
818 EL1 to cause a return to EL2 with a <<
819 1258
820 This can only happen when EL2 is ste !! 1259 config IRQ_TXX9
>> 1260 bool
821 1261
822 When these conditions occur, the SPS !! 1262 config IRQ_GT641XX
823 previous guest entry, and can be res !! 1263 bool
824 1264
825 If unsure, say Y. !! 1265 config PCI_GT64XXX_PCI0
>> 1266 bool
826 1267
827 config ARM64_ERRATUM_2658417 !! 1268 config PCI_XTALK_BRIDGE
828 bool "Cortex-A510: 2658417: remove BF1 !! 1269 bool
829 default y <<
830 help <<
831 This option adds the workaround for <<
832 Affected Cortex-A510 (r0p0 to r1p1) <<
833 BFMMLA or VMMLA instructions in rare <<
834 A510 CPUs are using shared neon hard <<
835 discoverable by the kernel, hide the <<
836 user-space should not be using these <<
837 1270
838 If unsure, say Y. !! 1271 config NO_EXCEPT_FILL
>> 1272 bool
839 1273
840 config ARM64_ERRATUM_2119858 !! 1274 config SOC_EMMA2RH
841 bool "Cortex-A710/X2: 2119858: workaro !! 1275 bool
842 default y !! 1276 select CEVT_R4K
843 depends on CORESIGHT_TRBE !! 1277 select CSRC_R4K
844 select ARM64_WORKAROUND_TRBE_OVERWRITE !! 1278 select DMA_NONCOHERENT
845 help !! 1279 select IRQ_MIPS_CPU
846 This option adds the workaround for !! 1280 select SWAP_IO_SPACE
>> 1281 select SYS_HAS_CPU_R5500
>> 1282 select SYS_SUPPORTS_32BIT_KERNEL
>> 1283 select SYS_SUPPORTS_64BIT_KERNEL
>> 1284 select SYS_SUPPORTS_BIG_ENDIAN
847 1285
848 Affected Cortex-A710/X2 cores could !! 1286 config SOC_PNX833X
849 data at the base of the buffer (poin !! 1287 bool
850 the event of a WRAP event. !! 1288 select CEVT_R4K
>> 1289 select CSRC_R4K
>> 1290 select IRQ_MIPS_CPU
>> 1291 select DMA_NONCOHERENT
>> 1292 select SYS_HAS_CPU_MIPS32_R2
>> 1293 select SYS_SUPPORTS_32BIT_KERNEL
>> 1294 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 1295 select SYS_SUPPORTS_BIG_ENDIAN
>> 1296 select SYS_SUPPORTS_MIPS16
>> 1297 select CPU_MIPSR2_IRQ_VI
851 1298
852 Work around the issue by always maki !! 1299 config SOC_PNX8335
853 256 bytes before enabling the buffer !! 1300 bool
854 the buffer with ETM ignore packets u !! 1301 select SOC_PNX833X
855 1302
856 If unsure, say Y. !! 1303 config MIPS_SPRAM
>> 1304 bool
857 1305
858 config ARM64_ERRATUM_2139208 !! 1306 config SWAP_IO_SPACE
859 bool "Neoverse-N2: 2139208: workaround !! 1307 bool
860 default y <<
861 depends on CORESIGHT_TRBE <<
862 select ARM64_WORKAROUND_TRBE_OVERWRITE <<
863 help <<
864 This option adds the workaround for <<
865 1308
866 Affected Neoverse-N2 cores could ove !! 1309 config SGI_HAS_INDYDOG
867 data at the base of the buffer (poin !! 1310 bool
868 the event of a WRAP event. <<
869 1311
870 Work around the issue by always maki !! 1312 config SGI_HAS_HAL2
871 256 bytes before enabling the buffer !! 1313 bool
872 the buffer with ETM ignore packets u <<
873 1314
874 If unsure, say Y. !! 1315 config SGI_HAS_SEEQ
>> 1316 bool
875 1317
876 config ARM64_WORKAROUND_TSB_FLUSH_FAILURE !! 1318 config SGI_HAS_WD93
877 bool 1319 bool
878 1320
879 config ARM64_ERRATUM_2054223 !! 1321 config SGI_HAS_ZILOG
880 bool "Cortex-A710: 2054223: workaround !! 1322 bool
881 default y <<
882 select ARM64_WORKAROUND_TSB_FLUSH_FAIL <<
883 help <<
884 Enable workaround for ARM Cortex-A71 <<
885 1323
886 Affected cores may fail to flush the !! 1324 config SGI_HAS_I8042
887 the PE is in trace prohibited state. !! 1325 bool
888 of the trace cached. <<
889 1326
890 Workaround is to issue two TSB conse !! 1327 config DEFAULT_SGI_PARTITION
>> 1328 bool
891 1329
892 If unsure, say Y. !! 1330 config FW_ARC32
>> 1331 bool
893 1332
894 config ARM64_ERRATUM_2067961 !! 1333 config FW_SNIPROM
895 bool "Neoverse-N2: 2067961: workaround !! 1334 bool
896 default y <<
897 select ARM64_WORKAROUND_TSB_FLUSH_FAIL <<
898 help <<
899 Enable workaround for ARM Neoverse-N <<
900 1335
901 Affected cores may fail to flush the !! 1336 config BOOT_ELF32
902 the PE is in trace prohibited state. !! 1337 bool
903 of the trace cached. <<
904 1338
905 Workaround is to issue two TSB conse !! 1339 config MIPS_L1_CACHE_SHIFT_4
>> 1340 bool
906 1341
907 If unsure, say Y. !! 1342 config MIPS_L1_CACHE_SHIFT_5
>> 1343 bool
908 1344
909 config ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANG !! 1345 config MIPS_L1_CACHE_SHIFT_6
910 bool 1346 bool
911 1347
912 config ARM64_ERRATUM_2253138 !! 1348 config MIPS_L1_CACHE_SHIFT_7
913 bool "Neoverse-N2: 2253138: workaround !! 1349 bool
914 depends on CORESIGHT_TRBE <<
915 default y <<
916 select ARM64_WORKAROUND_TRBE_WRITE_OUT <<
917 help <<
918 This option adds the workaround for <<
919 1350
920 Affected Neoverse-N2 cores might wri !! 1351 config MIPS_L1_CACHE_SHIFT
921 for TRBE. Under some conditions, the !! 1352 int
922 virtually addressed page following t !! 1353 default "7" if MIPS_L1_CACHE_SHIFT_7
923 (i.e., the TRBLIMITR_EL1.LIMIT), ins !! 1354 default "6" if MIPS_L1_CACHE_SHIFT_6
>> 1355 default "5" if MIPS_L1_CACHE_SHIFT_5
>> 1356 default "4" if MIPS_L1_CACHE_SHIFT_4
>> 1357 default "5"
924 1358
925 Work around this in the driver by al !! 1359 config HAVE_STD_PC_SERIAL_PORT
926 page beyond the TRBLIMITR_EL1.LIMIT, !! 1360 bool
927 1361
928 If unsure, say Y. !! 1362 config ARC_CONSOLE
>> 1363 bool "ARC console support"
>> 1364 depends on SGI_IP22 || SGI_IP28 || (SNI_RM && CPU_LITTLE_ENDIAN)
929 1365
930 config ARM64_ERRATUM_2224489 !! 1366 config ARC_MEMORY
931 bool "Cortex-A710/X2: 2224489: workaro !! 1367 bool
932 depends on CORESIGHT_TRBE !! 1368 depends on MACH_JAZZ || SNI_RM || SGI_IP32
933 default y 1369 default y
934 select ARM64_WORKAROUND_TRBE_WRITE_OUT <<
935 help <<
936 This option adds the workaround for <<
937 <<
938 Affected Cortex-A710/X2 cores might <<
939 for TRBE. Under some conditions, the <<
940 virtually addressed page following t <<
941 (i.e., the TRBLIMITR_EL1.LIMIT), ins <<
942 <<
943 Work around this in the driver by al <<
944 page beyond the TRBLIMITR_EL1.LIMIT, <<
945 1370
946 If unsure, say Y. !! 1371 config ARC_PROMLIB
947 !! 1372 bool
948 config ARM64_ERRATUM_2441009 !! 1373 depends on MACH_JAZZ || SNI_RM || SGI_IP22 || SGI_IP28 || SGI_IP32
949 bool "Cortex-A510: Completion of affec <<
950 select ARM64_WORKAROUND_REPEAT_TLBI <<
951 help <<
952 This option adds a workaround for AR <<
953 <<
954 Under very rare circumstances, affec <<
955 may not handle a race between a brea <<
956 CPU, and another CPU accessing the s <<
957 store to a page that has been unmapp <<
958 <<
959 Work around this by adding the affec <<
960 TLB sequences to be done twice. <<
961 <<
962 If unsure, say N. <<
963 <<
964 config ARM64_ERRATUM_2064142 <<
965 bool "Cortex-A510: 2064142: workaround <<
966 depends on CORESIGHT_TRBE <<
967 default y 1374 default y
968 help <<
969 This option adds the workaround for <<
970 1375
971 Affected Cortex-A510 core might fail !! 1376 config FW_ARC64
972 TRBE has been disabled. Under some c !! 1377 bool
973 writes into TRBE registers TRBLIMITR <<
974 and TRBTRG_EL1 will be ignored and w <<
975 1378
976 Work around this in the driver by ex !! 1379 config BOOT_ELF64
977 is stopped and before performing a s !! 1380 bool
978 registers. <<
979 1381
980 If unsure, say Y. !! 1382 menu "CPU selection"
981 1383
982 config ARM64_ERRATUM_2038923 !! 1384 choice
983 bool "Cortex-A510: 2038923: workaround !! 1385 prompt "CPU type"
984 depends on CORESIGHT_TRBE !! 1386 default CPU_R4X00
985 default y <<
986 help <<
987 This option adds the workaround for <<
988 <<
989 Affected Cortex-A510 core might caus <<
990 prohibited within the CPU. As a resu <<
991 might be corrupted. This happens aft <<
992 TRBLIMITR_EL1.E, followed by just a <<
993 execution changes from a context, in <<
994 isn't, or vice versa. In these menti <<
995 is prohibited is inconsistent betwee <<
996 the trace buffer state might be corr <<
997 <<
998 Work around this in the driver by pr <<
999 trace is prohibited or not based on <<
1000 change to TRBLIMITR_EL1.E with at l <<
1001 two ISB instructions if no ERET is <<
1002 1387
1003 If unsure, say Y. !! 1388 config CPU_LOONGSON3
>> 1389 bool "Loongson 3 CPU"
>> 1390 depends on SYS_HAS_CPU_LOONGSON3
>> 1391 select ARCH_HAS_PHYS_TO_DMA
>> 1392 select CPU_SUPPORTS_64BIT_KERNEL
>> 1393 select CPU_SUPPORTS_HIGHMEM
>> 1394 select CPU_SUPPORTS_HUGEPAGES
>> 1395 select CPU_HAS_LOAD_STORE_LR
>> 1396 select WEAK_ORDERING
>> 1397 select WEAK_REORDERING_BEYOND_LLSC
>> 1398 select MIPS_PGD_C0_CONTEXT
>> 1399 select MIPS_L1_CACHE_SHIFT_6
>> 1400 select MIPS_FP_SUPPORT
>> 1401 select GPIOLIB
>> 1402 select SWIOTLB
>> 1403 help
>> 1404 The Loongson 3 processor implements the MIPS64R2 instruction
>> 1405 set with many extensions.
1004 1406
1005 config ARM64_ERRATUM_1902691 !! 1407 config LOONGSON3_ENHANCEMENT
1006 bool "Cortex-A510: 1902691: workaroun !! 1408 bool "New Loongson 3 CPU Enhancements"
1007 depends on CORESIGHT_TRBE !! 1409 default n
1008 default y !! 1410 select CPU_MIPSR2
>> 1411 select CPU_HAS_PREFETCH
>> 1412 depends on CPU_LOONGSON3
>> 1413 help
>> 1414 New Loongson 3 CPU (since Loongson-3A R2, as opposed to Loongson-3A
>> 1415 R1, Loongson-3B R1 and Loongson-3B R2) has many enhancements, such as
>> 1416 FTLB, L1-VCache, EI/DI/Wait/Prefetch instruction, DSP/DSPv2 ASE, User
>> 1417 Local register, Read-Inhibit/Execute-Inhibit, SFB (Store Fill Buffer),
>> 1418 Fast TLB refill support, etc.
>> 1419
>> 1420 This option enable those enhancements which are not probed at run
>> 1421 time. If you want a generic kernel to run on all Loongson 3 machines,
>> 1422 please say 'N' here. If you want a high-performance kernel to run on
>> 1423 new Loongson 3 machines only, please say 'Y' here.
>> 1424
>> 1425 config CPU_LOONGSON3_WORKAROUNDS
>> 1426 bool "Old Loongson 3 LLSC Workarounds"
>> 1427 default y if SMP
>> 1428 depends on CPU_LOONGSON3
>> 1429 help
>> 1430 Loongson 3 processors have the llsc issues which require workarounds.
>> 1431 Without workarounds the system may hang unexpectedly.
>> 1432
>> 1433 Newer Loongson 3 will fix these issues and no workarounds are needed.
>> 1434 The workarounds have no significant side effect on them but may
>> 1435 decrease the performance of the system so this option should be
>> 1436 disabled unless the kernel is intended to be run on old systems.
>> 1437
>> 1438 If unsure, please say Y.
>> 1439
>> 1440 config CPU_LOONGSON2E
>> 1441 bool "Loongson 2E"
>> 1442 depends on SYS_HAS_CPU_LOONGSON2E
>> 1443 select CPU_LOONGSON2
>> 1444 help
>> 1445 The Loongson 2E processor implements the MIPS III instruction set
>> 1446 with many extensions.
>> 1447
>> 1448 It has an internal FPGA northbridge, which is compatible to
>> 1449 bonito64.
>> 1450
>> 1451 config CPU_LOONGSON2F
>> 1452 bool "Loongson 2F"
>> 1453 depends on SYS_HAS_CPU_LOONGSON2F
>> 1454 select CPU_LOONGSON2
>> 1455 select GPIOLIB
>> 1456 help
>> 1457 The Loongson 2F processor implements the MIPS III instruction set
>> 1458 with many extensions.
>> 1459
>> 1460 Loongson2F have built-in DDR2 and PCIX controller. The PCIX controller
>> 1461 have a similar programming interface with FPGA northbridge used in
>> 1462 Loongson2E.
>> 1463
>> 1464 config CPU_LOONGSON1B
>> 1465 bool "Loongson 1B"
>> 1466 depends on SYS_HAS_CPU_LOONGSON1B
>> 1467 select CPU_LOONGSON1
>> 1468 select LEDS_GPIO_REGISTER
>> 1469 help
>> 1470 The Loongson 1B is a 32-bit SoC, which implements the MIPS32
>> 1471 Release 1 instruction set and part of the MIPS32 Release 2
>> 1472 instruction set.
>> 1473
>> 1474 config CPU_LOONGSON1C
>> 1475 bool "Loongson 1C"
>> 1476 depends on SYS_HAS_CPU_LOONGSON1C
>> 1477 select CPU_LOONGSON1
>> 1478 select LEDS_GPIO_REGISTER
>> 1479 help
>> 1480 The Loongson 1C is a 32-bit SoC, which implements the MIPS32
>> 1481 Release 1 instruction set and part of the MIPS32 Release 2
>> 1482 instruction set.
>> 1483
>> 1484 config CPU_MIPS32_R1
>> 1485 bool "MIPS32 Release 1"
>> 1486 depends on SYS_HAS_CPU_MIPS32_R1
>> 1487 select CPU_HAS_PREFETCH
>> 1488 select CPU_HAS_LOAD_STORE_LR
>> 1489 select CPU_SUPPORTS_32BIT_KERNEL
>> 1490 select CPU_SUPPORTS_HIGHMEM
>> 1491 help
>> 1492 Choose this option to build a kernel for release 1 or later of the
>> 1493 MIPS32 architecture. Most modern embedded systems with a 32-bit
>> 1494 MIPS processor are based on a MIPS32 processor. If you know the
>> 1495 specific type of processor in your system, choose those that one
>> 1496 otherwise CPU_MIPS32_R1 is a safe bet for any MIPS32 system.
>> 1497 Release 2 of the MIPS32 architecture is available since several
>> 1498 years so chances are you even have a MIPS32 Release 2 processor
>> 1499 in which case you should choose CPU_MIPS32_R2 instead for better
>> 1500 performance.
>> 1501
>> 1502 config CPU_MIPS32_R2
>> 1503 bool "MIPS32 Release 2"
>> 1504 depends on SYS_HAS_CPU_MIPS32_R2
>> 1505 select CPU_HAS_PREFETCH
>> 1506 select CPU_HAS_LOAD_STORE_LR
>> 1507 select CPU_SUPPORTS_32BIT_KERNEL
>> 1508 select CPU_SUPPORTS_HIGHMEM
>> 1509 select CPU_SUPPORTS_MSA
>> 1510 select HAVE_KVM
>> 1511 help
>> 1512 Choose this option to build a kernel for release 2 or later of the
>> 1513 MIPS32 architecture. Most modern embedded systems with a 32-bit
>> 1514 MIPS processor are based on a MIPS32 processor. If you know the
>> 1515 specific type of processor in your system, choose those that one
>> 1516 otherwise CPU_MIPS32_R1 is a safe bet for any MIPS32 system.
>> 1517
>> 1518 config CPU_MIPS32_R6
>> 1519 bool "MIPS32 Release 6"
>> 1520 depends on SYS_HAS_CPU_MIPS32_R6
>> 1521 select CPU_HAS_PREFETCH
>> 1522 select CPU_SUPPORTS_32BIT_KERNEL
>> 1523 select CPU_SUPPORTS_HIGHMEM
>> 1524 select CPU_SUPPORTS_MSA
>> 1525 select HAVE_KVM
>> 1526 select MIPS_O32_FP64_SUPPORT
>> 1527 help
>> 1528 Choose this option to build a kernel for release 6 or later of the
>> 1529 MIPS32 architecture. New MIPS processors, starting with the Warrior
>> 1530 family, are based on a MIPS32r6 processor. If you own an older
>> 1531 processor, you probably need to select MIPS32r1 or MIPS32r2 instead.
>> 1532
>> 1533 config CPU_MIPS64_R1
>> 1534 bool "MIPS64 Release 1"
>> 1535 depends on SYS_HAS_CPU_MIPS64_R1
>> 1536 select CPU_HAS_PREFETCH
>> 1537 select CPU_HAS_LOAD_STORE_LR
>> 1538 select CPU_SUPPORTS_32BIT_KERNEL
>> 1539 select CPU_SUPPORTS_64BIT_KERNEL
>> 1540 select CPU_SUPPORTS_HIGHMEM
>> 1541 select CPU_SUPPORTS_HUGEPAGES
>> 1542 help
>> 1543 Choose this option to build a kernel for release 1 or later of the
>> 1544 MIPS64 architecture. Many modern embedded systems with a 64-bit
>> 1545 MIPS processor are based on a MIPS64 processor. If you know the
>> 1546 specific type of processor in your system, choose those that one
>> 1547 otherwise CPU_MIPS64_R1 is a safe bet for any MIPS64 system.
>> 1548 Release 2 of the MIPS64 architecture is available since several
>> 1549 years so chances are you even have a MIPS64 Release 2 processor
>> 1550 in which case you should choose CPU_MIPS64_R2 instead for better
>> 1551 performance.
>> 1552
>> 1553 config CPU_MIPS64_R2
>> 1554 bool "MIPS64 Release 2"
>> 1555 depends on SYS_HAS_CPU_MIPS64_R2
>> 1556 select CPU_HAS_PREFETCH
>> 1557 select CPU_HAS_LOAD_STORE_LR
>> 1558 select CPU_SUPPORTS_32BIT_KERNEL
>> 1559 select CPU_SUPPORTS_64BIT_KERNEL
>> 1560 select CPU_SUPPORTS_HIGHMEM
>> 1561 select CPU_SUPPORTS_HUGEPAGES
>> 1562 select CPU_SUPPORTS_MSA
>> 1563 select HAVE_KVM
>> 1564 help
>> 1565 Choose this option to build a kernel for release 2 or later of the
>> 1566 MIPS64 architecture. Many modern embedded systems with a 64-bit
>> 1567 MIPS processor are based on a MIPS64 processor. If you know the
>> 1568 specific type of processor in your system, choose those that one
>> 1569 otherwise CPU_MIPS64_R1 is a safe bet for any MIPS64 system.
>> 1570
>> 1571 config CPU_MIPS64_R6
>> 1572 bool "MIPS64 Release 6"
>> 1573 depends on SYS_HAS_CPU_MIPS64_R6
>> 1574 select CPU_HAS_PREFETCH
>> 1575 select CPU_SUPPORTS_32BIT_KERNEL
>> 1576 select CPU_SUPPORTS_64BIT_KERNEL
>> 1577 select CPU_SUPPORTS_HIGHMEM
>> 1578 select CPU_SUPPORTS_HUGEPAGES
>> 1579 select CPU_SUPPORTS_MSA
>> 1580 select MIPS_O32_FP64_SUPPORT if 32BIT || MIPS32_O32
>> 1581 select HAVE_KVM
>> 1582 help
>> 1583 Choose this option to build a kernel for release 6 or later of the
>> 1584 MIPS64 architecture. New MIPS processors, starting with the Warrior
>> 1585 family, are based on a MIPS64r6 processor. If you own an older
>> 1586 processor, you probably need to select MIPS64r1 or MIPS64r2 instead.
>> 1587
>> 1588 config CPU_R3000
>> 1589 bool "R3000"
>> 1590 depends on SYS_HAS_CPU_R3000
>> 1591 select CPU_HAS_WB
>> 1592 select CPU_HAS_LOAD_STORE_LR
>> 1593 select CPU_R3K_TLB
>> 1594 select CPU_SUPPORTS_32BIT_KERNEL
>> 1595 select CPU_SUPPORTS_HIGHMEM
>> 1596 help
>> 1597 Please make sure to pick the right CPU type. Linux/MIPS is not
>> 1598 designed to be generic, i.e. Kernels compiled for R3000 CPUs will
>> 1599 *not* work on R4000 machines and vice versa. However, since most
>> 1600 of the supported machines have an R4000 (or similar) CPU, R4x00
>> 1601 might be a safe bet. If the resulting kernel does not work,
>> 1602 try to recompile with R3000.
>> 1603
>> 1604 config CPU_TX39XX
>> 1605 bool "R39XX"
>> 1606 depends on SYS_HAS_CPU_TX39XX
>> 1607 select CPU_SUPPORTS_32BIT_KERNEL
>> 1608 select CPU_HAS_LOAD_STORE_LR
>> 1609 select CPU_R3K_TLB
>> 1610
>> 1611 config CPU_VR41XX
>> 1612 bool "R41xx"
>> 1613 depends on SYS_HAS_CPU_VR41XX
>> 1614 select CPU_SUPPORTS_32BIT_KERNEL
>> 1615 select CPU_SUPPORTS_64BIT_KERNEL
>> 1616 select CPU_HAS_LOAD_STORE_LR
>> 1617 help
>> 1618 The options selects support for the NEC VR4100 series of processors.
>> 1619 Only choose this option if you have one of these processors as a
>> 1620 kernel built with this option will not run on any other type of
>> 1621 processor or vice versa.
>> 1622
>> 1623 config CPU_R4X00
>> 1624 bool "R4x00"
>> 1625 depends on SYS_HAS_CPU_R4X00
>> 1626 select CPU_SUPPORTS_32BIT_KERNEL
>> 1627 select CPU_SUPPORTS_64BIT_KERNEL
>> 1628 select CPU_SUPPORTS_HUGEPAGES
>> 1629 select CPU_HAS_LOAD_STORE_LR
>> 1630 help
>> 1631 MIPS Technologies R4000-series processors other than 4300, including
>> 1632 the R4000, R4400, R4600, and 4700.
>> 1633
>> 1634 config CPU_TX49XX
>> 1635 bool "R49XX"
>> 1636 depends on SYS_HAS_CPU_TX49XX
>> 1637 select CPU_HAS_PREFETCH
>> 1638 select CPU_HAS_LOAD_STORE_LR
>> 1639 select CPU_SUPPORTS_32BIT_KERNEL
>> 1640 select CPU_SUPPORTS_64BIT_KERNEL
>> 1641 select CPU_SUPPORTS_HUGEPAGES
>> 1642
>> 1643 config CPU_R5000
>> 1644 bool "R5000"
>> 1645 depends on SYS_HAS_CPU_R5000
>> 1646 select CPU_SUPPORTS_32BIT_KERNEL
>> 1647 select CPU_SUPPORTS_64BIT_KERNEL
>> 1648 select CPU_SUPPORTS_HUGEPAGES
>> 1649 select CPU_HAS_LOAD_STORE_LR
>> 1650 help
>> 1651 MIPS Technologies R5000-series processors other than the Nevada.
>> 1652
>> 1653 config CPU_R5500
>> 1654 bool "R5500"
>> 1655 depends on SYS_HAS_CPU_R5500
>> 1656 select CPU_SUPPORTS_32BIT_KERNEL
>> 1657 select CPU_SUPPORTS_64BIT_KERNEL
>> 1658 select CPU_SUPPORTS_HUGEPAGES
>> 1659 select CPU_HAS_LOAD_STORE_LR
>> 1660 help
>> 1661 NEC VR5500 and VR5500A series processors implement 64-bit MIPS IV
>> 1662 instruction set.
>> 1663
>> 1664 config CPU_NEVADA
>> 1665 bool "RM52xx"
>> 1666 depends on SYS_HAS_CPU_NEVADA
>> 1667 select CPU_SUPPORTS_32BIT_KERNEL
>> 1668 select CPU_SUPPORTS_64BIT_KERNEL
>> 1669 select CPU_SUPPORTS_HUGEPAGES
>> 1670 select CPU_HAS_LOAD_STORE_LR
>> 1671 help
>> 1672 QED / PMC-Sierra RM52xx-series ("Nevada") processors.
>> 1673
>> 1674 config CPU_R10000
>> 1675 bool "R10000"
>> 1676 depends on SYS_HAS_CPU_R10000
>> 1677 select CPU_HAS_PREFETCH
>> 1678 select CPU_HAS_LOAD_STORE_LR
>> 1679 select CPU_SUPPORTS_32BIT_KERNEL
>> 1680 select CPU_SUPPORTS_64BIT_KERNEL
>> 1681 select CPU_SUPPORTS_HIGHMEM
>> 1682 select CPU_SUPPORTS_HUGEPAGES
>> 1683 help
>> 1684 MIPS Technologies R10000-series processors.
>> 1685
>> 1686 config CPU_RM7000
>> 1687 bool "RM7000"
>> 1688 depends on SYS_HAS_CPU_RM7000
>> 1689 select CPU_HAS_PREFETCH
>> 1690 select CPU_HAS_LOAD_STORE_LR
>> 1691 select CPU_SUPPORTS_32BIT_KERNEL
>> 1692 select CPU_SUPPORTS_64BIT_KERNEL
>> 1693 select CPU_SUPPORTS_HIGHMEM
>> 1694 select CPU_SUPPORTS_HUGEPAGES
>> 1695
>> 1696 config CPU_SB1
>> 1697 bool "SB1"
>> 1698 depends on SYS_HAS_CPU_SB1
>> 1699 select CPU_HAS_LOAD_STORE_LR
>> 1700 select CPU_SUPPORTS_32BIT_KERNEL
>> 1701 select CPU_SUPPORTS_64BIT_KERNEL
>> 1702 select CPU_SUPPORTS_HIGHMEM
>> 1703 select CPU_SUPPORTS_HUGEPAGES
>> 1704 select WEAK_ORDERING
>> 1705
>> 1706 config CPU_CAVIUM_OCTEON
>> 1707 bool "Cavium Octeon processor"
>> 1708 depends on SYS_HAS_CPU_CAVIUM_OCTEON
>> 1709 select CPU_HAS_PREFETCH
>> 1710 select CPU_HAS_LOAD_STORE_LR
>> 1711 select CPU_SUPPORTS_64BIT_KERNEL
>> 1712 select WEAK_ORDERING
>> 1713 select CPU_SUPPORTS_HIGHMEM
>> 1714 select CPU_SUPPORTS_HUGEPAGES
>> 1715 select USB_EHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 1716 select USB_OHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 1717 select MIPS_L1_CACHE_SHIFT_7
>> 1718 select HAVE_KVM
>> 1719 help
>> 1720 The Cavium Octeon processor is a highly integrated chip containing
>> 1721 many ethernet hardware widgets for networking tasks. The processor
>> 1722 can have up to 16 Mips64v2 cores and 8 integrated gigabit ethernets.
>> 1723 Full details can be found at http://www.caviumnetworks.com.
>> 1724
>> 1725 config CPU_BMIPS
>> 1726 bool "Broadcom BMIPS"
>> 1727 depends on SYS_HAS_CPU_BMIPS
>> 1728 select CPU_MIPS32
>> 1729 select CPU_BMIPS32_3300 if SYS_HAS_CPU_BMIPS32_3300
>> 1730 select CPU_BMIPS4350 if SYS_HAS_CPU_BMIPS4350
>> 1731 select CPU_BMIPS4380 if SYS_HAS_CPU_BMIPS4380
>> 1732 select CPU_BMIPS5000 if SYS_HAS_CPU_BMIPS5000
>> 1733 select CPU_SUPPORTS_32BIT_KERNEL
>> 1734 select DMA_NONCOHERENT
>> 1735 select IRQ_MIPS_CPU
>> 1736 select SWAP_IO_SPACE
>> 1737 select WEAK_ORDERING
>> 1738 select CPU_SUPPORTS_HIGHMEM
>> 1739 select CPU_HAS_PREFETCH
>> 1740 select CPU_HAS_LOAD_STORE_LR
>> 1741 select CPU_SUPPORTS_CPUFREQ
>> 1742 select MIPS_EXTERNAL_TIMER
>> 1743 help
>> 1744 Support for BMIPS32/3300/4350/4380 and BMIPS5000 processors.
>> 1745
>> 1746 config CPU_XLR
>> 1747 bool "Netlogic XLR SoC"
>> 1748 depends on SYS_HAS_CPU_XLR
>> 1749 select CPU_HAS_LOAD_STORE_LR
>> 1750 select CPU_SUPPORTS_32BIT_KERNEL
>> 1751 select CPU_SUPPORTS_64BIT_KERNEL
>> 1752 select CPU_SUPPORTS_HIGHMEM
>> 1753 select CPU_SUPPORTS_HUGEPAGES
>> 1754 select WEAK_ORDERING
>> 1755 select WEAK_REORDERING_BEYOND_LLSC
>> 1756 help
>> 1757 Netlogic Microsystems XLR/XLS processors.
>> 1758
>> 1759 config CPU_XLP
>> 1760 bool "Netlogic XLP SoC"
>> 1761 depends on SYS_HAS_CPU_XLP
>> 1762 select CPU_SUPPORTS_32BIT_KERNEL
>> 1763 select CPU_SUPPORTS_64BIT_KERNEL
>> 1764 select CPU_SUPPORTS_HIGHMEM
>> 1765 select WEAK_ORDERING
>> 1766 select WEAK_REORDERING_BEYOND_LLSC
>> 1767 select CPU_HAS_PREFETCH
>> 1768 select CPU_HAS_LOAD_STORE_LR
>> 1769 select CPU_MIPSR2
>> 1770 select CPU_SUPPORTS_HUGEPAGES
>> 1771 select MIPS_ASID_BITS_VARIABLE
1009 help 1772 help
1010 This option adds the workaround for !! 1773 Netlogic Microsystems XLP processors.
>> 1774 endchoice
1011 1775
1012 Affected Cortex-A510 core might cau !! 1776 config CPU_MIPS32_3_5_FEATURES
1013 into the memory. Effectively TRBE i !! 1777 bool "MIPS32 Release 3.5 Features"
1014 trace data. !! 1778 depends on SYS_HAS_CPU_MIPS32_R3_5
>> 1779 depends on CPU_MIPS32_R2 || CPU_MIPS32_R6
>> 1780 help
>> 1781 Choose this option to build a kernel for release 2 or later of the
>> 1782 MIPS32 architecture including features from the 3.5 release such as
>> 1783 support for Enhanced Virtual Addressing (EVA).
>> 1784
>> 1785 config CPU_MIPS32_3_5_EVA
>> 1786 bool "Enhanced Virtual Addressing (EVA)"
>> 1787 depends on CPU_MIPS32_3_5_FEATURES
>> 1788 select EVA
>> 1789 default y
>> 1790 help
>> 1791 Choose this option if you want to enable the Enhanced Virtual
>> 1792 Addressing (EVA) on your MIPS32 core (such as proAptiv).
>> 1793 One of its primary benefits is an increase in the maximum size
>> 1794 of lowmem (up to 3GB). If unsure, say 'N' here.
>> 1795
>> 1796 config CPU_MIPS32_R5_FEATURES
>> 1797 bool "MIPS32 Release 5 Features"
>> 1798 depends on SYS_HAS_CPU_MIPS32_R5
>> 1799 depends on CPU_MIPS32_R2
>> 1800 help
>> 1801 Choose this option to build a kernel for release 2 or later of the
>> 1802 MIPS32 architecture including features from release 5 such as
>> 1803 support for Extended Physical Addressing (XPA).
>> 1804
>> 1805 config CPU_MIPS32_R5_XPA
>> 1806 bool "Extended Physical Addressing (XPA)"
>> 1807 depends on CPU_MIPS32_R5_FEATURES
>> 1808 depends on !EVA
>> 1809 depends on !PAGE_SIZE_4KB
>> 1810 depends on SYS_SUPPORTS_HIGHMEM
>> 1811 select XPA
>> 1812 select HIGHMEM
>> 1813 select PHYS_ADDR_T_64BIT
>> 1814 default n
>> 1815 help
>> 1816 Choose this option if you want to enable the Extended Physical
>> 1817 Addressing (XPA) on your MIPS32 core (such as P5600 series). The
>> 1818 benefit is to increase physical addressing equal to or greater
>> 1819 than 40 bits. Note that this has the side effect of turning on
>> 1820 64-bit addressing which in turn makes the PTEs 64-bit in size.
>> 1821 If unsure, say 'N' here.
1015 1822
1016 Work around this problem in the dri !! 1823 if CPU_LOONGSON2F
1017 affected cpus. The firmware must ha !! 1824 config CPU_NOP_WORKAROUNDS
1018 on such implementations. This will !! 1825 bool
1019 do this already. <<
1020 1826
1021 If unsure, say Y. !! 1827 config CPU_JUMP_WORKAROUNDS
>> 1828 bool
1022 1829
1023 config ARM64_ERRATUM_2457168 !! 1830 config CPU_LOONGSON2F_WORKAROUNDS
1024 bool "Cortex-A510: 2457168: workaroun !! 1831 bool "Loongson 2F Workarounds"
1025 depends on ARM64_AMU_EXTN <<
1026 default y 1832 default y
>> 1833 select CPU_NOP_WORKAROUNDS
>> 1834 select CPU_JUMP_WORKAROUNDS
1027 help 1835 help
1028 This option adds the workaround for !! 1836 Loongson 2F01 / 2F02 processors have the NOP & JUMP issues which
>> 1837 require workarounds. Without workarounds the system may hang
>> 1838 unexpectedly. For more information please refer to the gas
>> 1839 -mfix-loongson2f-nop and -mfix-loongson2f-jump options.
>> 1840
>> 1841 Loongson 2F03 and later have fixed these issues and no workarounds
>> 1842 are needed. The workarounds have no significant side effect on them
>> 1843 but may decrease the performance of the system so this option should
>> 1844 be disabled unless the kernel is intended to be run on 2F01 or 2F02
>> 1845 systems.
1029 1846
1030 The AMU counter AMEVCNTR01 (constan !! 1847 If unsure, please say Y.
1031 as the system counter. On affected !! 1848 endif # CPU_LOONGSON2F
1032 incorrectly giving a significantly <<
1033 1849
1034 Work around this problem by returni !! 1850 config SYS_SUPPORTS_ZBOOT
1035 key locations that results in disab !! 1851 bool
1036 is the same to firmware disabling a !! 1852 select HAVE_KERNEL_GZIP
>> 1853 select HAVE_KERNEL_BZIP2
>> 1854 select HAVE_KERNEL_LZ4
>> 1855 select HAVE_KERNEL_LZMA
>> 1856 select HAVE_KERNEL_LZO
>> 1857 select HAVE_KERNEL_XZ
1037 1858
1038 If unsure, say Y. !! 1859 config SYS_SUPPORTS_ZBOOT_UART16550
>> 1860 bool
>> 1861 select SYS_SUPPORTS_ZBOOT
1039 1862
1040 config ARM64_ERRATUM_2645198 !! 1863 config SYS_SUPPORTS_ZBOOT_UART_PROM
1041 bool "Cortex-A715: 2645198: Workaroun !! 1864 bool
1042 default y !! 1865 select SYS_SUPPORTS_ZBOOT
1043 help <<
1044 This option adds the workaround for <<
1045 1866
1046 If a Cortex-A715 cpu sees a page ma !! 1867 config CPU_LOONGSON2
1047 to non-executable, it may corrupt t !! 1868 bool
1048 next instruction abort caused by pe !! 1869 select CPU_SUPPORTS_32BIT_KERNEL
>> 1870 select CPU_SUPPORTS_64BIT_KERNEL
>> 1871 select CPU_SUPPORTS_HIGHMEM
>> 1872 select CPU_SUPPORTS_HUGEPAGES
>> 1873 select ARCH_HAS_PHYS_TO_DMA
>> 1874 select CPU_HAS_LOAD_STORE_LR
1049 1875
1050 Only user-space does executable to !! 1876 config CPU_LOONGSON1
1051 mprotect() system call. Workaround !! 1877 bool
1052 TLB invalidation, for all changes t !! 1878 select CPU_MIPS32
>> 1879 select CPU_MIPSR2
>> 1880 select CPU_HAS_PREFETCH
>> 1881 select CPU_HAS_LOAD_STORE_LR
>> 1882 select CPU_SUPPORTS_32BIT_KERNEL
>> 1883 select CPU_SUPPORTS_HIGHMEM
>> 1884 select CPU_SUPPORTS_CPUFREQ
1053 1885
1054 If unsure, say Y. !! 1886 config CPU_BMIPS32_3300
>> 1887 select SMP_UP if SMP
>> 1888 bool
1055 1889
1056 config ARM64_WORKAROUND_SPECULATIVE_UNPRIV_LO !! 1890 config CPU_BMIPS4350
1057 bool 1891 bool
>> 1892 select SYS_SUPPORTS_SMP
>> 1893 select SYS_SUPPORTS_HOTPLUG_CPU
1058 1894
1059 config ARM64_ERRATUM_2966298 !! 1895 config CPU_BMIPS4380
1060 bool "Cortex-A520: 2966298: workaroun !! 1896 bool
1061 select ARM64_WORKAROUND_SPECULATIVE_U !! 1897 select MIPS_L1_CACHE_SHIFT_6
1062 default y !! 1898 select SYS_SUPPORTS_SMP
1063 help !! 1899 select SYS_SUPPORTS_HOTPLUG_CPU
1064 This option adds the workaround for !! 1900 select CPU_HAS_RIXI
1065 1901
1066 On an affected Cortex-A520 core, a !! 1902 config CPU_BMIPS5000
1067 load might leak data from a privile !! 1903 bool
>> 1904 select MIPS_CPU_SCACHE
>> 1905 select MIPS_L1_CACHE_SHIFT_7
>> 1906 select SYS_SUPPORTS_SMP
>> 1907 select SYS_SUPPORTS_HOTPLUG_CPU
>> 1908 select CPU_HAS_RIXI
1068 1909
1069 Work around this problem by executi !! 1910 config SYS_HAS_CPU_LOONGSON3
>> 1911 bool
>> 1912 select CPU_SUPPORTS_CPUFREQ
>> 1913 select CPU_HAS_RIXI
1070 1914
1071 If unsure, say Y. !! 1915 config SYS_HAS_CPU_LOONGSON2E
>> 1916 bool
1072 1917
1073 config ARM64_ERRATUM_3117295 !! 1918 config SYS_HAS_CPU_LOONGSON2F
1074 bool "Cortex-A510: 3117295: workaroun !! 1919 bool
1075 select ARM64_WORKAROUND_SPECULATIVE_U !! 1920 select CPU_SUPPORTS_CPUFREQ
1076 default y !! 1921 select CPU_SUPPORTS_ADDRWINCFG if 64BIT
1077 help !! 1922 select CPU_SUPPORTS_UNCACHED_ACCELERATED
1078 This option adds the workaround for <<
1079 1923
1080 On an affected Cortex-A510 core, a !! 1924 config SYS_HAS_CPU_LOONGSON1B
1081 load might leak data from a privile !! 1925 bool
1082 1926
1083 Work around this problem by executi !! 1927 config SYS_HAS_CPU_LOONGSON1C
>> 1928 bool
1084 1929
1085 If unsure, say Y. !! 1930 config SYS_HAS_CPU_MIPS32_R1
>> 1931 bool
1086 1932
1087 config ARM64_ERRATUM_3194386 !! 1933 config SYS_HAS_CPU_MIPS32_R2
1088 bool "Cortex-*/Neoverse-*: workaround !! 1934 bool
1089 default y <<
1090 help <<
1091 This option adds the workaround for <<
1092 1935
1093 * ARM Cortex-A76 erratum 3324349 !! 1936 config SYS_HAS_CPU_MIPS32_R3_5
1094 * ARM Cortex-A77 erratum 3324348 !! 1937 bool
1095 * ARM Cortex-A78 erratum 3324344 <<
1096 * ARM Cortex-A78C erratum 3324346 <<
1097 * ARM Cortex-A78C erratum 3324347 <<
1098 * ARM Cortex-A710 erratam 3324338 <<
1099 * ARM Cortex-A715 errartum 3456084 <<
1100 * ARM Cortex-A720 erratum 3456091 <<
1101 * ARM Cortex-A725 erratum 3456106 <<
1102 * ARM Cortex-X1 erratum 3324344 <<
1103 * ARM Cortex-X1C erratum 3324346 <<
1104 * ARM Cortex-X2 erratum 3324338 <<
1105 * ARM Cortex-X3 erratum 3324335 <<
1106 * ARM Cortex-X4 erratum 3194386 <<
1107 * ARM Cortex-X925 erratum 3324334 <<
1108 * ARM Neoverse-N1 erratum 3324349 <<
1109 * ARM Neoverse N2 erratum 3324339 <<
1110 * ARM Neoverse-N3 erratum 3456111 <<
1111 * ARM Neoverse-V1 erratum 3324341 <<
1112 * ARM Neoverse V2 erratum 3324336 <<
1113 * ARM Neoverse-V3 erratum 3312417 <<
1114 <<
1115 On affected cores "MSR SSBS, #0" in <<
1116 subsequent speculative instructions <<
1117 speculative store bypassing. <<
1118 <<
1119 Work around this problem by placing <<
1120 Instruction Synchronization Barrier <<
1121 SSBS. The presence of the SSBS spec <<
1122 from hwcaps and EL0 reads of ID_AA6 <<
1123 will use the PR_SPEC_STORE_BYPASS p <<
1124 1938
1125 If unsure, say Y. !! 1939 config SYS_HAS_CPU_MIPS32_R5
>> 1940 bool
>> 1941 select ARCH_HAS_SYNC_DMA_FOR_CPU if DMA_NONCOHERENT
1126 1942
1127 config CAVIUM_ERRATUM_22375 !! 1943 config SYS_HAS_CPU_MIPS32_R6
1128 bool "Cavium erratum 22375, 24313" !! 1944 bool
1129 default y !! 1945 select ARCH_HAS_SYNC_DMA_FOR_CPU if DMA_NONCOHERENT
1130 help <<
1131 Enable workaround for errata 22375 <<
1132 1946
1133 This implements two gicv3-its errat !! 1947 config SYS_HAS_CPU_MIPS64_R1
1134 with a small impact affecting only !! 1948 bool
1135 1949
1136 erratum 22375: only alloc 8MB tab !! 1950 config SYS_HAS_CPU_MIPS64_R2
1137 erratum 24313: ignore memory acce !! 1951 bool
1138 1952
1139 The fixes are in ITS initialization !! 1953 config SYS_HAS_CPU_MIPS64_R6
1140 type and table size provided by the !! 1954 bool
>> 1955 select ARCH_HAS_SYNC_DMA_FOR_CPU if DMA_NONCOHERENT
1141 1956
1142 If unsure, say Y. !! 1957 config SYS_HAS_CPU_R3000
>> 1958 bool
1143 1959
1144 config CAVIUM_ERRATUM_23144 !! 1960 config SYS_HAS_CPU_TX39XX
1145 bool "Cavium erratum 23144: ITS SYNC !! 1961 bool
1146 depends on NUMA <<
1147 default y <<
1148 help <<
1149 ITS SYNC command hang for cross nod <<
1150 1962
1151 If unsure, say Y. !! 1963 config SYS_HAS_CPU_VR41XX
>> 1964 bool
1152 1965
1153 config CAVIUM_ERRATUM_23154 !! 1966 config SYS_HAS_CPU_R4X00
1154 bool "Cavium errata 23154 and 38545: !! 1967 bool
1155 default y <<
1156 help <<
1157 The ThunderX GICv3 implementation r <<
1158 reading the IAR status to ensure da <<
1159 (access to icc_iar1_el1 is not sync <<
1160 1968
1161 It also suffers from erratum 38545 !! 1969 config SYS_HAS_CPU_TX49XX
1162 OcteonTX and OcteonTX2), resulting !! 1970 bool
1163 spuriously presented to the CPU int <<
1164 1971
1165 If unsure, say Y. !! 1972 config SYS_HAS_CPU_R5000
>> 1973 bool
1166 1974
1167 config CAVIUM_ERRATUM_27456 !! 1975 config SYS_HAS_CPU_R5500
1168 bool "Cavium erratum 27456: Broadcast !! 1976 bool
1169 default y <<
1170 help <<
1171 On ThunderX T88 pass 1.x through 2. <<
1172 instructions may cause the icache t <<
1173 contains data for a non-current ASI <<
1174 invalidate the icache when changing <<
1175 1977
1176 If unsure, say Y. !! 1978 config SYS_HAS_CPU_NEVADA
>> 1979 bool
1177 1980
1178 config CAVIUM_ERRATUM_30115 !! 1981 config SYS_HAS_CPU_R10000
1179 bool "Cavium erratum 30115: Guest may !! 1982 bool
1180 default y !! 1983 select ARCH_HAS_SYNC_DMA_FOR_CPU if DMA_NONCOHERENT
1181 help <<
1182 On ThunderX T88 pass 1.x through 2. <<
1183 1.2, and T83 Pass 1.0, KVM guest ex <<
1184 interrupts in host. Trapping both G <<
1185 accesses sidesteps the issue. <<
1186 1984
1187 If unsure, say Y. !! 1985 config SYS_HAS_CPU_RM7000
>> 1986 bool
1188 1987
1189 config CAVIUM_TX2_ERRATUM_219 !! 1988 config SYS_HAS_CPU_SB1
1190 bool "Cavium ThunderX2 erratum 219: P !! 1989 bool
1191 default y <<
1192 help <<
1193 On Cavium ThunderX2, a load, store <<
1194 TTBR update and the corresponding c <<
1195 cause a spurious Data Abort to be d <<
1196 the CPU core. <<
1197 <<
1198 Work around the issue by avoiding t <<
1199 trapping KVM guest TTBRx_EL1 writes <<
1200 trap handler performs the correspon <<
1201 instruction and ensures context syn <<
1202 exception return. <<
1203 1990
1204 If unsure, say Y. !! 1991 config SYS_HAS_CPU_CAVIUM_OCTEON
>> 1992 bool
1205 1993
1206 config FUJITSU_ERRATUM_010001 !! 1994 config SYS_HAS_CPU_BMIPS
1207 bool "Fujitsu-A64FX erratum E#010001: !! 1995 bool
1208 default y <<
1209 help <<
1210 This option adds a workaround for F <<
1211 On some variants of the Fujitsu-A64 <<
1212 accesses may cause undefined fault <<
1213 This fault occurs under a specific <<
1214 load/store instruction performs an <<
1215 case-1 TTBR0_EL1 with TCR_EL1.NFD0 <<
1216 case-2 TTBR0_EL2 with TCR_EL2.NFD0 <<
1217 case-3 TTBR1_EL1 with TCR_EL1.NFD1 <<
1218 case-4 TTBR1_EL2 with TCR_EL2.NFD1 <<
1219 1996
1220 The workaround is to ensure these b !! 1997 config SYS_HAS_CPU_BMIPS32_3300
1221 The workaround only affects the Fuj !! 1998 bool
>> 1999 select SYS_HAS_CPU_BMIPS
1222 2000
1223 If unsure, say Y. !! 2001 config SYS_HAS_CPU_BMIPS4350
>> 2002 bool
>> 2003 select SYS_HAS_CPU_BMIPS
1224 2004
1225 config HISILICON_ERRATUM_161600802 !! 2005 config SYS_HAS_CPU_BMIPS4380
1226 bool "Hip07 161600802: Erroneous redi !! 2006 bool
1227 default y !! 2007 select SYS_HAS_CPU_BMIPS
1228 help <<
1229 The HiSilicon Hip07 SoC uses the wr <<
1230 when issued ITS commands such as VM <<
1231 a 128kB offset to be applied to the <<
1232 2008
1233 If unsure, say Y. !! 2009 config SYS_HAS_CPU_BMIPS5000
>> 2010 bool
>> 2011 select SYS_HAS_CPU_BMIPS
>> 2012 select ARCH_HAS_SYNC_DMA_FOR_CPU
1234 2013
1235 config QCOM_FALKOR_ERRATUM_1003 !! 2014 config SYS_HAS_CPU_XLR
1236 bool "Falkor E1003: Incorrect transla !! 2015 bool
1237 default y <<
1238 help <<
1239 On Falkor v1, an incorrect ASID may <<
1240 and BADDR are changed together in T <<
1241 in TTBR1_EL1, this situation only o <<
1242 then only for entries in the walk c <<
1243 is unchanged. Work around the errat <<
1244 entries for the trampoline before e <<
1245 2016
1246 config QCOM_FALKOR_ERRATUM_1009 !! 2017 config SYS_HAS_CPU_XLP
1247 bool "Falkor E1009: Prematurely compl !! 2018 bool
1248 default y <<
1249 select ARM64_WORKAROUND_REPEAT_TLBI <<
1250 help <<
1251 On Falkor v1, the CPU may premature <<
1252 TLBI xxIS invalidate maintenance op <<
1253 one more time to fix the issue. <<
1254 2019
1255 If unsure, say Y. !! 2020 #
>> 2021 # CPU may reorder R->R, R->W, W->R, W->W
>> 2022 # Reordering beyond LL and SC is handled in WEAK_REORDERING_BEYOND_LLSC
>> 2023 #
>> 2024 config WEAK_ORDERING
>> 2025 bool
1256 2026
1257 config QCOM_QDF2400_ERRATUM_0065 !! 2027 #
1258 bool "QDF2400 E0065: Incorrect GITS_T !! 2028 # CPU may reorder reads and writes beyond LL/SC
1259 default y !! 2029 # CPU may reorder R->LL, R->LL, W->LL, W->LL, R->SC, R->SC, W->SC, W->SC
1260 help !! 2030 #
1261 On Qualcomm Datacenter Technologies !! 2031 config WEAK_REORDERING_BEYOND_LLSC
1262 ITE size incorrectly. The GITS_TYPE !! 2032 bool
1263 been indicated as 16Bytes (0xf), no !! 2033 endmenu
1264 2034
1265 If unsure, say Y. !! 2035 #
>> 2036 # These two indicate any level of the MIPS32 and MIPS64 architecture
>> 2037 #
>> 2038 config CPU_MIPS32
>> 2039 bool
>> 2040 default y if CPU_MIPS32_R1 || CPU_MIPS32_R2 || CPU_MIPS32_R6
1266 2041
1267 config QCOM_FALKOR_ERRATUM_E1041 !! 2042 config CPU_MIPS64
1268 bool "Falkor E1041: Speculative instr !! 2043 bool
1269 default y !! 2044 default y if CPU_MIPS64_R1 || CPU_MIPS64_R2 || CPU_MIPS64_R6
1270 help <<
1271 Falkor CPU may speculatively fetch <<
1272 memory location when MMU translatio <<
1273 to SCTLR_ELn[M]=0. Prefix an ISB in <<
1274 2045
1275 If unsure, say Y. !! 2046 #
>> 2047 # These indicate the revision of the architecture
>> 2048 #
>> 2049 config CPU_MIPSR1
>> 2050 bool
>> 2051 default y if CPU_MIPS32_R1 || CPU_MIPS64_R1
1276 2052
1277 config NVIDIA_CARMEL_CNP_ERRATUM !! 2053 config CPU_MIPSR2
1278 bool "NVIDIA Carmel CNP: CNP on Carme !! 2054 bool
1279 default y !! 2055 default y if CPU_MIPS32_R2 || CPU_MIPS64_R2 || CPU_CAVIUM_OCTEON
1280 help !! 2056 select CPU_HAS_RIXI
1281 If CNP is enabled on Carmel cores, !! 2057 select MIPS_SPRAM
1282 invalidate shared TLB entries insta <<
1283 on standard ARM cores. <<
1284 2058
1285 If unsure, say Y. !! 2059 config CPU_MIPSR6
>> 2060 bool
>> 2061 default y if CPU_MIPS32_R6 || CPU_MIPS64_R6
>> 2062 select CPU_HAS_RIXI
>> 2063 select HAVE_ARCH_BITREVERSE
>> 2064 select MIPS_ASID_BITS_VARIABLE
>> 2065 select MIPS_CRC_SUPPORT
>> 2066 select MIPS_SPRAM
1286 2067
1287 config ROCKCHIP_ERRATUM_3588001 !! 2068 config TARGET_ISA_REV
1288 bool "Rockchip 3588001: GIC600 can no !! 2069 int
1289 default y !! 2070 default 1 if CPU_MIPSR1
>> 2071 default 2 if CPU_MIPSR2
>> 2072 default 6 if CPU_MIPSR6
>> 2073 default 0
1290 help 2074 help
1291 The Rockchip RK3588 GIC600 SoC inte !! 2075 Reflects the ISA revision being targeted by the kernel build. This
1292 This means, that its sharability fe !! 2076 is effectively the Kconfig equivalent of MIPS_ISA_REV.
1293 is supported by the IP itself. <<
1294 <<
1295 If unsure, say Y. <<
1296 2077
1297 config SOCIONEXT_SYNQUACER_PREITS !! 2078 config EVA
1298 bool "Socionext Synquacer: Workaround !! 2079 bool
1299 default y <<
1300 help <<
1301 Socionext Synquacer SoCs implement <<
1302 MSI doorbell writes with non-zero v <<
1303 2080
1304 If unsure, say Y. !! 2081 config XPA
>> 2082 bool
1305 2083
1306 endmenu # "ARM errata workarounds via the alt !! 2084 config SYS_SUPPORTS_32BIT_KERNEL
>> 2085 bool
>> 2086 config SYS_SUPPORTS_64BIT_KERNEL
>> 2087 bool
>> 2088 config CPU_SUPPORTS_32BIT_KERNEL
>> 2089 bool
>> 2090 config CPU_SUPPORTS_64BIT_KERNEL
>> 2091 bool
>> 2092 config CPU_SUPPORTS_CPUFREQ
>> 2093 bool
>> 2094 config CPU_SUPPORTS_ADDRWINCFG
>> 2095 bool
>> 2096 config CPU_SUPPORTS_HUGEPAGES
>> 2097 bool
>> 2098 depends on !(32BIT && (ARCH_PHYS_ADDR_T_64BIT || EVA))
>> 2099 config CPU_SUPPORTS_UNCACHED_ACCELERATED
>> 2100 bool
>> 2101 config MIPS_PGD_C0_CONTEXT
>> 2102 bool
>> 2103 default y if 64BIT && (CPU_MIPSR2 || CPU_MIPSR6) && !CPU_XLP
1307 2104
1308 choice !! 2105 #
1309 prompt "Page size" !! 2106 # Set to y for ptrace access to watch registers.
1310 default ARM64_4K_PAGES !! 2107 #
1311 help !! 2108 config HARDWARE_WATCHPOINTS
1312 Page size (translation granule) con !! 2109 bool
>> 2110 default y if CPU_MIPSR1 || CPU_MIPSR2 || CPU_MIPSR6
1313 2111
1314 config ARM64_4K_PAGES !! 2112 menu "Kernel type"
1315 bool "4KB" <<
1316 select HAVE_PAGE_SIZE_4KB <<
1317 help <<
1318 This feature enables 4KB pages supp <<
1319 2113
1320 config ARM64_16K_PAGES !! 2114 choice
1321 bool "16KB" !! 2115 prompt "Kernel code model"
1322 select HAVE_PAGE_SIZE_16KB <<
1323 help 2116 help
1324 The system will use 16KB pages supp !! 2117 You should only select this option if you have a workload that
1325 requires applications compiled with !! 2118 actually benefits from 64-bit processing or if your machine has
1326 aligned segments. !! 2119 large memory. You will only be presented a single option in this
1327 !! 2120 menu if your system does not support both 32-bit and 64-bit kernels.
1328 config ARM64_64K_PAGES !! 2121
1329 bool "64KB" !! 2122 config 32BIT
1330 select HAVE_PAGE_SIZE_64KB !! 2123 bool "32-bit kernel"
>> 2124 depends on CPU_SUPPORTS_32BIT_KERNEL && SYS_SUPPORTS_32BIT_KERNEL
>> 2125 select TRAD_SIGNALS
1331 help 2126 help
1332 This feature enables 64KB pages sup !! 2127 Select this option if you want to build a 32-bit kernel.
1333 allowing only two levels of page ta <<
1334 look-up. AArch32 emulation requires <<
1335 with 64K aligned segments. <<
1336 <<
1337 endchoice <<
1338 2128
1339 choice !! 2129 config 64BIT
1340 prompt "Virtual address space size" !! 2130 bool "64-bit kernel"
1341 default ARM64_VA_BITS_52 !! 2131 depends on CPU_SUPPORTS_64BIT_KERNEL && SYS_SUPPORTS_64BIT_KERNEL
1342 help 2132 help
1343 Allows choosing one of multiple pos !! 2133 Select this option if you want to build a 64-bit kernel.
1344 space sizes. The level of translati <<
1345 a combination of page size and virt <<
1346 <<
1347 config ARM64_VA_BITS_36 <<
1348 bool "36-bit" if EXPERT <<
1349 depends on PAGE_SIZE_16KB <<
1350 <<
1351 config ARM64_VA_BITS_39 <<
1352 bool "39-bit" <<
1353 depends on PAGE_SIZE_4KB <<
1354 <<
1355 config ARM64_VA_BITS_42 <<
1356 bool "42-bit" <<
1357 depends on PAGE_SIZE_64KB <<
1358 <<
1359 config ARM64_VA_BITS_47 <<
1360 bool "47-bit" <<
1361 depends on PAGE_SIZE_16KB <<
1362 <<
1363 config ARM64_VA_BITS_48 <<
1364 bool "48-bit" <<
1365 <<
1366 config ARM64_VA_BITS_52 <<
1367 bool "52-bit" <<
1368 depends on ARM64_PAN || !ARM64_SW_TTB <<
1369 help <<
1370 Enable 52-bit virtual addressing fo <<
1371 requested via a hint to mmap(). The <<
1372 virtual addresses for its own mappi <<
1373 this feature is available, otherwis <<
1374 <<
1375 NOTE: Enabling 52-bit virtual addre <<
1376 ARMv8.3 Pointer Authentication will <<
1377 reduced from 7 bits to 3 bits, whic <<
1378 impact on its susceptibility to bru <<
1379 <<
1380 If unsure, select 48-bit virtual ad <<
1381 2134
1382 endchoice 2135 endchoice
1383 2136
1384 config ARM64_FORCE_52BIT !! 2137 config KVM_GUEST
1385 bool "Force 52-bit virtual addresses !! 2138 bool "KVM Guest Kernel"
1386 depends on ARM64_VA_BITS_52 && EXPERT !! 2139 depends on BROKEN_ON_SMP
1387 help !! 2140 help
1388 For systems with 52-bit userspace V !! 2141 Select this option if building a guest kernel for KVM (Trap & Emulate)
1389 to maintain compatibility with olde !! 2142 mode.
1390 unless a hint is supplied to mmap. !! 2143
1391 !! 2144 config KVM_GUEST_TIMER_FREQ
1392 This configuration option disables !! 2145 int "Count/Compare Timer Frequency (MHz)"
1393 forces all userspace addresses to b !! 2146 depends on KVM_GUEST
1394 should only enable this configurati !! 2147 default 100
1395 memory management code. If unsure s !! 2148 help
>> 2149 Set this to non-zero if building a guest kernel for KVM to skip RTC
>> 2150 emulation when determining guest CPU Frequency. Instead, the guest's
>> 2151 timer frequency is specified directly.
>> 2152
>> 2153 config MIPS_VA_BITS_48
>> 2154 bool "48 bits virtual memory"
>> 2155 depends on 64BIT
>> 2156 help
>> 2157 Support a maximum at least 48 bits of application virtual
>> 2158 memory. Default is 40 bits or less, depending on the CPU.
>> 2159 For page sizes 16k and above, this option results in a small
>> 2160 memory overhead for page tables. For 4k page size, a fourth
>> 2161 level of page tables is added which imposes both a memory
>> 2162 overhead as well as slower TLB fault handling.
1396 2163
1397 config ARM64_VA_BITS !! 2164 If unsure, say N.
1398 int <<
1399 default 36 if ARM64_VA_BITS_36 <<
1400 default 39 if ARM64_VA_BITS_39 <<
1401 default 42 if ARM64_VA_BITS_42 <<
1402 default 47 if ARM64_VA_BITS_47 <<
1403 default 48 if ARM64_VA_BITS_48 <<
1404 default 52 if ARM64_VA_BITS_52 <<
1405 2165
1406 choice 2166 choice
1407 prompt "Physical address space size" !! 2167 prompt "Kernel page size"
1408 default ARM64_PA_BITS_48 !! 2168 default PAGE_SIZE_4KB
1409 help <<
1410 Choose the maximum physical address <<
1411 support. <<
1412 2169
1413 config ARM64_PA_BITS_48 !! 2170 config PAGE_SIZE_4KB
1414 bool "48-bit" !! 2171 bool "4kB"
1415 depends on ARM64_64K_PAGES || !ARM64_ !! 2172 depends on !CPU_LOONGSON2 && !CPU_LOONGSON3
1416 !! 2173 help
1417 config ARM64_PA_BITS_52 !! 2174 This option select the standard 4kB Linux page size. On some
1418 bool "52-bit" !! 2175 R3000-family processors this is the only available page size. Using
1419 depends on ARM64_64K_PAGES || ARM64_V !! 2176 4kB page size will minimize memory consumption and is therefore
1420 depends on ARM64_PAN || !ARM64_SW_TTB !! 2177 recommended for low memory systems.
1421 help !! 2178
1422 Enable support for a 52-bit physica !! 2179 config PAGE_SIZE_8KB
1423 part of the ARMv8.2-LPA extension. !! 2180 bool "8kB"
1424 !! 2181 depends on CPU_CAVIUM_OCTEON
1425 With this enabled, the kernel will !! 2182 depends on !MIPS_VA_BITS_48
1426 do not support ARMv8.2-LPA, but wit !! 2183 help
1427 minor performance overhead). !! 2184 Using 8kB page size will result in higher performance kernel at
>> 2185 the price of higher memory consumption. This option is available
>> 2186 only on cnMIPS processors. Note that you will need a suitable Linux
>> 2187 distribution to support this.
>> 2188
>> 2189 config PAGE_SIZE_16KB
>> 2190 bool "16kB"
>> 2191 depends on !CPU_R3000 && !CPU_TX39XX
>> 2192 help
>> 2193 Using 16kB page size will result in higher performance kernel at
>> 2194 the price of higher memory consumption. This option is available on
>> 2195 all non-R3000 family processors. Note that you will need a suitable
>> 2196 Linux distribution to support this.
>> 2197
>> 2198 config PAGE_SIZE_32KB
>> 2199 bool "32kB"
>> 2200 depends on CPU_CAVIUM_OCTEON
>> 2201 depends on !MIPS_VA_BITS_48
>> 2202 help
>> 2203 Using 32kB page size will result in higher performance kernel at
>> 2204 the price of higher memory consumption. This option is available
>> 2205 only on cnMIPS cores. Note that you will need a suitable Linux
>> 2206 distribution to support this.
>> 2207
>> 2208 config PAGE_SIZE_64KB
>> 2209 bool "64kB"
>> 2210 depends on !CPU_R3000 && !CPU_TX39XX
>> 2211 help
>> 2212 Using 64kB page size will result in higher performance kernel at
>> 2213 the price of higher memory consumption. This option is available on
>> 2214 all non-R3000 family processor. Not that at the time of this
>> 2215 writing this option is still high experimental.
1428 2216
1429 endchoice 2217 endchoice
1430 2218
1431 config ARM64_PA_BITS !! 2219 config FORCE_MAX_ZONEORDER
1432 int !! 2220 int "Maximum zone order"
1433 default 48 if ARM64_PA_BITS_48 !! 2221 range 14 64 if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_64KB
1434 default 52 if ARM64_PA_BITS_52 !! 2222 default "14" if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_64KB
1435 !! 2223 range 13 64 if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_32KB
1436 config ARM64_LPA2 !! 2224 default "13" if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_32KB
1437 def_bool y !! 2225 range 12 64 if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_16KB
1438 depends on ARM64_PA_BITS_52 && !ARM64 !! 2226 default "12" if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_16KB
1439 !! 2227 range 11 64
1440 choice !! 2228 default "11"
1441 prompt "Endianness" !! 2229 help
1442 default CPU_LITTLE_ENDIAN !! 2230 The kernel memory allocator divides physically contiguous memory
1443 help !! 2231 blocks into "zones", where each zone is a power of two number of
1444 Select the endianness of data acces !! 2232 pages. This option selects the largest power of two that the kernel
1445 applications will need to be compil !! 2233 keeps in the memory allocator. If you need to allocate very large
1446 that is selected here. !! 2234 blocks of physically contiguous memory, then you may need to
1447 !! 2235 increase this value.
1448 config CPU_BIG_ENDIAN <<
1449 bool "Build big-endian kernel" <<
1450 # https://github.com/llvm/llvm-projec <<
1451 depends on AS_IS_GNU || AS_VERSION >= <<
1452 help <<
1453 Say Y if you plan on running a kern <<
1454 <<
1455 config CPU_LITTLE_ENDIAN <<
1456 bool "Build little-endian kernel" <<
1457 help <<
1458 Say Y if you plan on running a kern <<
1459 This is usually the case for distri <<
1460 2236
1461 endchoice !! 2237 This config option is actually maximum order plus one. For example,
>> 2238 a value of 11 means that the largest free memory block is 2^10 pages.
1462 2239
1463 config SCHED_MC !! 2240 The page size is not necessarily 4KB. Keep this in mind
1464 bool "Multi-core scheduler support" !! 2241 when choosing a value for this option.
1465 help <<
1466 Multi-core scheduler support improv <<
1467 making when dealing with multi-core <<
1468 increased overhead in some places. <<
1469 2242
1470 config SCHED_CLUSTER !! 2243 config BOARD_SCACHE
1471 bool "Cluster scheduler support" !! 2244 bool
1472 help <<
1473 Cluster scheduler support improves <<
1474 making when dealing with machines t <<
1475 Cluster usually means a couple of C <<
1476 by sharing mid-level caches, last-l <<
1477 busses. <<
1478 2245
1479 config SCHED_SMT !! 2246 config IP22_CPU_SCACHE
1480 bool "SMT scheduler support" !! 2247 bool
1481 help !! 2248 select BOARD_SCACHE
1482 Improves the CPU scheduler's decisi <<
1483 MultiThreading at a cost of slightl <<
1484 places. If unsure say N here. <<
1485 2249
1486 config NR_CPUS !! 2250 #
1487 int "Maximum number of CPUs (2-4096)" !! 2251 # Support for a MIPS32 / MIPS64 style S-caches
1488 range 2 4096 !! 2252 #
1489 default "512" !! 2253 config MIPS_CPU_SCACHE
>> 2254 bool
>> 2255 select BOARD_SCACHE
1490 2256
1491 config HOTPLUG_CPU !! 2257 config R5000_CPU_SCACHE
1492 bool "Support for hot-pluggable CPUs" !! 2258 bool
1493 select GENERIC_IRQ_MIGRATION !! 2259 select BOARD_SCACHE
1494 help <<
1495 Say Y here to experiment with turni <<
1496 can be controlled through /sys/devi <<
1497 2260
1498 # Common NUMA Features !! 2261 config RM7000_CPU_SCACHE
1499 config NUMA !! 2262 bool
1500 bool "NUMA Memory Allocation and Sche !! 2263 select BOARD_SCACHE
1501 select GENERIC_ARCH_NUMA <<
1502 select OF_NUMA <<
1503 select HAVE_SETUP_PER_CPU_AREA <<
1504 select NEED_PER_CPU_EMBED_FIRST_CHUNK <<
1505 select NEED_PER_CPU_PAGE_FIRST_CHUNK <<
1506 select USE_PERCPU_NUMA_NODE_ID <<
1507 help <<
1508 Enable NUMA (Non-Uniform Memory Acc <<
1509 <<
1510 The kernel will try to allocate mem <<
1511 local memory of the CPU and add som <<
1512 NUMA awareness to the kernel. <<
1513 2264
1514 config NODES_SHIFT !! 2265 config SIBYTE_DMA_PAGEOPS
1515 int "Maximum NUMA Nodes (as a power o !! 2266 bool "Use DMA to clear/copy pages"
1516 range 1 10 !! 2267 depends on CPU_SB1
1517 default "4" <<
1518 depends on NUMA <<
1519 help 2268 help
1520 Specify the maximum number of NUMA !! 2269 Instead of using the CPU to zero and copy pages, use a Data Mover
1521 system. Increases memory reserved !! 2270 channel. These DMA channels are otherwise unused by the standard
1522 !! 2271 SiByte Linux port. Seems to give a small performance benefit.
1523 source "kernel/Kconfig.hz" <<
1524 <<
1525 config ARCH_SPARSEMEM_ENABLE <<
1526 def_bool y <<
1527 select SPARSEMEM_VMEMMAP_ENABLE <<
1528 select SPARSEMEM_VMEMMAP <<
1529 <<
1530 config HW_PERF_EVENTS <<
1531 def_bool y <<
1532 depends on ARM_PMU <<
1533 2272
1534 # Supported by clang >= 7.0 or GCC >= 12.0.0 !! 2273 config CPU_HAS_PREFETCH
1535 config CC_HAVE_SHADOW_CALL_STACK !! 2274 bool
1536 def_bool $(cc-option, -fsanitize=shad <<
1537 2275
1538 config PARAVIRT !! 2276 config CPU_GENERIC_DUMP_TLB
1539 bool "Enable paravirtualization code" !! 2277 bool
1540 help !! 2278 default y if !(CPU_R3000 || CPU_TX39XX)
1541 This changes the kernel so it can m <<
1542 under a hypervisor, potentially imp <<
1543 over full virtualization. <<
1544 2279
1545 config PARAVIRT_TIME_ACCOUNTING !! 2280 config MIPS_FP_SUPPORT
1546 bool "Paravirtual steal time accounti !! 2281 bool "Floating Point support" if EXPERT
1547 select PARAVIRT !! 2282 default y
1548 help 2283 help
1549 Select this option to enable fine g !! 2284 Select y to include support for floating point in the kernel
1550 accounting. Time spent executing ot !! 2285 including initialization of FPU hardware, FP context save & restore
1551 the current vCPU is discounted from !! 2286 and emulation of an FPU where necessary. Without this support any
1552 that, there can be a small performa !! 2287 userland program attempting to use floating point instructions will
>> 2288 receive a SIGILL.
1553 2289
1554 If in doubt, say N here. !! 2290 If you know that your userland will not attempt to use floating point
>> 2291 instructions then you can say n here to shrink the kernel a little.
1555 2292
1556 config ARCH_SUPPORTS_KEXEC !! 2293 If unsure, say y.
1557 def_bool PM_SLEEP_SMP <<
1558 <<
1559 config ARCH_SUPPORTS_KEXEC_FILE <<
1560 def_bool y <<
1561 <<
1562 config ARCH_SELECTS_KEXEC_FILE <<
1563 def_bool y <<
1564 depends on KEXEC_FILE <<
1565 select HAVE_IMA_KEXEC if IMA <<
1566 <<
1567 config ARCH_SUPPORTS_KEXEC_SIG <<
1568 def_bool y <<
1569 <<
1570 config ARCH_SUPPORTS_KEXEC_IMAGE_VERIFY_SIG <<
1571 def_bool y <<
1572 2294
1573 config ARCH_DEFAULT_KEXEC_IMAGE_VERIFY_SIG !! 2295 config CPU_R2300_FPU
1574 def_bool y !! 2296 bool
>> 2297 depends on MIPS_FP_SUPPORT
>> 2298 default y if CPU_R3000 || CPU_TX39XX
1575 2299
1576 config ARCH_SUPPORTS_CRASH_DUMP !! 2300 config CPU_R3K_TLB
1577 def_bool y !! 2301 bool
1578 2302
1579 config ARCH_HAS_GENERIC_CRASHKERNEL_RESERVATI !! 2303 config CPU_R4K_FPU
1580 def_bool CRASH_RESERVE !! 2304 bool
>> 2305 depends on MIPS_FP_SUPPORT
>> 2306 default y if !CPU_R2300_FPU
1581 2307
1582 config TRANS_TABLE !! 2308 config CPU_R4K_CACHE_TLB
1583 def_bool y !! 2309 bool
1584 depends on HIBERNATION || KEXEC_CORE !! 2310 default y if !(CPU_R3K_TLB || CPU_SB1 || CPU_CAVIUM_OCTEON)
1585 2311
1586 config XEN_DOM0 !! 2312 config MIPS_MT_SMP
1587 def_bool y !! 2313 bool "MIPS MT SMP support (1 TC on each available VPE)"
1588 depends on XEN !! 2314 default y
>> 2315 depends on SYS_SUPPORTS_MULTITHREADING && !CPU_MIPSR6 && !CPU_MICROMIPS
>> 2316 select CPU_MIPSR2_IRQ_VI
>> 2317 select CPU_MIPSR2_IRQ_EI
>> 2318 select SYNC_R4K
>> 2319 select MIPS_MT
>> 2320 select SMP
>> 2321 select SMP_UP
>> 2322 select SYS_SUPPORTS_SMP
>> 2323 select SYS_SUPPORTS_SCHED_SMT
>> 2324 select MIPS_PERF_SHARED_TC_COUNTERS
>> 2325 help
>> 2326 This is a kernel model which is known as SMVP. This is supported
>> 2327 on cores with the MT ASE and uses the available VPEs to implement
>> 2328 virtual processors which supports SMP. This is equivalent to the
>> 2329 Intel Hyperthreading feature. For further information go to
>> 2330 <http://www.imgtec.com/mips/mips-multithreading.asp>.
1589 2331
1590 config XEN !! 2332 config MIPS_MT
1591 bool "Xen guest support on ARM64" !! 2333 bool
1592 depends on ARM64 && OF <<
1593 select SWIOTLB_XEN <<
1594 select PARAVIRT <<
1595 help <<
1596 Say Y if you want to run Linux in a <<
1597 2334
1598 # include/linux/mmzone.h requires the followi !! 2335 config SCHED_SMT
1599 # !! 2336 bool "SMT (multithreading) scheduler support"
1600 # MAX_PAGE_ORDER + PAGE_SHIFT <= SECTION_SI !! 2337 depends on SYS_SUPPORTS_SCHED_SMT
1601 # !! 2338 default n
1602 # so the maximum value of MAX_PAGE_ORDER is S <<
1603 # <<
1604 # | SECTION_SIZE_BITS | PAGE_SHIFT | m <<
1605 # ----+-------------------+--------------+--- <<
1606 # 4K | 27 | 12 | <<
1607 # 16K | 27 | 14 | <<
1608 # 64K | 29 | 16 | <<
1609 config ARCH_FORCE_MAX_ORDER <<
1610 int <<
1611 default "13" if ARM64_64K_PAGES <<
1612 default "11" if ARM64_16K_PAGES <<
1613 default "10" <<
1614 help 2339 help
1615 The kernel page allocator limits th !! 2340 SMT scheduler support improves the CPU scheduler's decision making
1616 contiguous allocations. The limit i !! 2341 when dealing with MIPS MT enabled cores at a cost of slightly
1617 defines the maximal power of two of !! 2342 increased overhead in some places. If unsure say N here.
1618 allocated as a single contiguous bl <<
1619 overriding the default setting when <<
1620 large blocks of physically contiguo <<
1621 2343
1622 The maximal size of allocation cann !! 2344 config SYS_SUPPORTS_SCHED_SMT
1623 section, so the value of MAX_PAGE_O !! 2345 bool
1624 2346
1625 MAX_PAGE_ORDER + PAGE_SHIFT <= SE !! 2347 config SYS_SUPPORTS_MULTITHREADING
>> 2348 bool
1626 2349
1627 Don't change if unsure. !! 2350 config MIPS_MT_FPAFF
>> 2351 bool "Dynamic FPU affinity for FP-intensive threads"
>> 2352 default y
>> 2353 depends on MIPS_MT_SMP
1628 2354
1629 config UNMAP_KERNEL_AT_EL0 !! 2355 config MIPSR2_TO_R6_EMULATOR
1630 bool "Unmap kernel when running in us !! 2356 bool "MIPS R2-to-R6 emulator"
>> 2357 depends on CPU_MIPSR6
>> 2358 depends on MIPS_FP_SUPPORT
1631 default y 2359 default y
1632 help 2360 help
1633 Speculation attacks against some hi !! 2361 Choose this option if you want to run non-R6 MIPS userland code.
1634 be used to bypass MMU permission ch !! 2362 Even if you say 'Y' here, the emulator will still be disabled by
1635 userspace. This can be defended aga !! 2363 default. You can enable it using the 'mipsr2emu' kernel option.
1636 when running in userspace, mapping !! 2364 The only reason this is a build-time option is to save ~14K from the
1637 via a trampoline page in the vector !! 2365 final kernel image.
1638 <<
1639 If unsure, say Y. <<
1640 2366
1641 config MITIGATE_SPECTRE_BRANCH_HISTORY !! 2367 config SYS_SUPPORTS_VPE_LOADER
1642 bool "Mitigate Spectre style attacks !! 2368 bool
1643 default y !! 2369 depends on SYS_SUPPORTS_MULTITHREADING
1644 help 2370 help
1645 Speculation attacks against some hi !! 2371 Indicates that the platform supports the VPE loader, and provides
1646 make use of branch history to influ !! 2372 physical_memsize.
1647 When taking an exception from user- <<
1648 or a firmware call overwrites the b <<
1649 2373
1650 config RODATA_FULL_DEFAULT_ENABLED !! 2374 config MIPS_VPE_LOADER
1651 bool "Apply r/o permissions of VM are !! 2375 bool "VPE loader support."
1652 default y !! 2376 depends on SYS_SUPPORTS_VPE_LOADER && MODULES
>> 2377 select CPU_MIPSR2_IRQ_VI
>> 2378 select CPU_MIPSR2_IRQ_EI
>> 2379 select MIPS_MT
1653 help 2380 help
1654 Apply read-only attributes of VM ar !! 2381 Includes a loader for loading an elf relocatable object
1655 the backing pages as well. This pre !! 2382 onto another VPE and running it.
1656 from being modified (inadvertently <<
1657 mapping of the same memory page. Th <<
1658 be turned off at runtime by passing <<
1659 with rodata=full if this option is <<
1660 2383
1661 This requires the linear region to !! 2384 config MIPS_VPE_LOADER_CMP
1662 which may adversely affect performa !! 2385 bool
>> 2386 default "y"
>> 2387 depends on MIPS_VPE_LOADER && MIPS_CMP
1663 2388
1664 config ARM64_SW_TTBR0_PAN !! 2389 config MIPS_VPE_LOADER_MT
1665 bool "Emulate Privileged Access Never !! 2390 bool
1666 depends on !KCSAN !! 2391 default "y"
1667 help !! 2392 depends on MIPS_VPE_LOADER && !MIPS_CMP
1668 Enabling this option prevents the k <<
1669 user-space memory directly by point <<
1670 zeroed area and reserved ASID. The <<
1671 restore the valid TTBR0_EL1 tempora <<
1672 2393
1673 config ARM64_TAGGED_ADDR_ABI !! 2394 config MIPS_VPE_LOADER_TOM
1674 bool "Enable the tagged user addresse !! 2395 bool "Load VPE program into memory hidden from linux"
>> 2396 depends on MIPS_VPE_LOADER
1675 default y 2397 default y
1676 help 2398 help
1677 When this option is enabled, user a !! 2399 The loader can use memory that is present but has been hidden from
1678 relaxed ABI via prctl() allowing ta !! 2400 Linux using the kernel command line option "mem=xxMB". It's up to
1679 to system calls as pointer argument !! 2401 you to ensure the amount you put in the option and the space your
1680 Documentation/arch/arm64/tagged-add !! 2402 program requires is less or equal to the amount physically present.
1681 <<
1682 menuconfig COMPAT <<
1683 bool "Kernel support for 32-bit EL0" <<
1684 depends on ARM64_4K_PAGES || EXPERT <<
1685 select HAVE_UID16 <<
1686 select OLD_SIGSUSPEND3 <<
1687 select COMPAT_OLD_SIGACTION <<
1688 help <<
1689 This option enables support for a 3 <<
1690 kernel at EL1. AArch32-specific com <<
1691 the user helper functions, VFP supp <<
1692 handled appropriately by the kernel <<
1693 2403
1694 If you use a page size other than 4 !! 2404 config MIPS_VPE_APSP_API
1695 that you will only be able to execu !! 2405 bool "Enable support for AP/SP API (RTLX)"
1696 with page size aligned segments. !! 2406 depends on MIPS_VPE_LOADER
1697 2407
1698 If you want to execute 32-bit users !! 2408 config MIPS_VPE_APSP_API_CMP
>> 2409 bool
>> 2410 default "y"
>> 2411 depends on MIPS_VPE_APSP_API && MIPS_CMP
1699 2412
1700 if COMPAT !! 2413 config MIPS_VPE_APSP_API_MT
>> 2414 bool
>> 2415 default "y"
>> 2416 depends on MIPS_VPE_APSP_API && !MIPS_CMP
1701 2417
1702 config KUSER_HELPERS !! 2418 config MIPS_CMP
1703 bool "Enable kuser helpers page for 3 !! 2419 bool "MIPS CMP framework support (DEPRECATED)"
1704 default y !! 2420 depends on SYS_SUPPORTS_MIPS_CMP && !CPU_MIPSR6
>> 2421 select SMP
>> 2422 select SYNC_R4K
>> 2423 select SYS_SUPPORTS_SMP
>> 2424 select WEAK_ORDERING
>> 2425 default n
1705 help 2426 help
1706 Warning: disabling this option may !! 2427 Select this if you are using a bootloader which implements the "CMP
1707 !! 2428 framework" protocol (ie. YAMON) and want your kernel to make use of
1708 Provide kuser helpers to compat tas !! 2429 its ability to start secondary CPUs.
1709 helper code to userspace in read on !! 2430
1710 to allow userspace to be independen !! 2431 Unless you have a specific need, you should use CONFIG_MIPS_CPS
1711 the system. This permits binaries t !! 2432 instead of this.
1712 to ARMv8 without modification. !! 2433
1713 !! 2434 config MIPS_CPS
1714 See Documentation/arch/arm/kernel_u !! 2435 bool "MIPS Coherent Processing System support"
>> 2436 depends on SYS_SUPPORTS_MIPS_CPS
>> 2437 select MIPS_CM
>> 2438 select MIPS_CPS_PM if HOTPLUG_CPU
>> 2439 select SMP
>> 2440 select SYNC_R4K if (CEVT_R4K || CSRC_R4K)
>> 2441 select SYS_SUPPORTS_HOTPLUG_CPU
>> 2442 select SYS_SUPPORTS_SCHED_SMT if CPU_MIPSR6
>> 2443 select SYS_SUPPORTS_SMP
>> 2444 select WEAK_ORDERING
>> 2445 help
>> 2446 Select this if you wish to run an SMP kernel across multiple cores
>> 2447 within a MIPS Coherent Processing System. When this option is
>> 2448 enabled the kernel will probe for other cores and boot them with
>> 2449 no external assistance. It is safe to enable this when hardware
>> 2450 support is unavailable.
1715 2451
1716 However, the fixed address nature o !! 2452 config MIPS_CPS_PM
1717 by ROP (return orientated programmi !! 2453 depends on MIPS_CPS
1718 exploits. !! 2454 bool
1719 2455
1720 If all of the binaries and librarie !! 2456 config MIPS_CM
1721 are built specifically for your pla !! 2457 bool
1722 these helpers, then you can turn th !! 2458 select MIPS_CPC
1723 such exploits. However, in that cas <<
1724 relying on those helpers is run, it <<
1725 2459
1726 Say N here only if you are absolute !! 2460 config MIPS_CPC
1727 need these helpers; otherwise, the !! 2461 bool
1728 2462
1729 config COMPAT_VDSO !! 2463 config SB1_PASS_2_WORKAROUNDS
1730 bool "Enable vDSO for 32-bit applicat !! 2464 bool
1731 depends on !CPU_BIG_ENDIAN !! 2465 depends on CPU_SB1 && (CPU_SB1_PASS_2_2 || CPU_SB1_PASS_2)
1732 depends on (CC_IS_CLANG && LD_IS_LLD) <<
1733 select GENERIC_COMPAT_VDSO <<
1734 default y 2466 default y
1735 help <<
1736 Place in the process address space <<
1737 ELF shared object providing fast im <<
1738 and clock_gettime. <<
1739 <<
1740 You must have a 32-bit build of gli <<
1741 to seamlessly take advantage of thi <<
1742 2467
1743 config THUMB2_COMPAT_VDSO !! 2468 config SB1_PASS_2_1_WORKAROUNDS
1744 bool "Compile the 32-bit vDSO for Thu !! 2469 bool
1745 depends on COMPAT_VDSO !! 2470 depends on CPU_SB1 && CPU_SB1_PASS_2
1746 default y 2471 default y
1747 help <<
1748 Compile the compat vDSO with '-mthu <<
1749 otherwise with '-marm'. <<
1750 2472
1751 config COMPAT_ALIGNMENT_FIXUPS !! 2473 choice
1752 bool "Fix up misaligned multi-word lo !! 2474 prompt "SmartMIPS or microMIPS ASE support"
1753 2475
1754 menuconfig ARMV8_DEPRECATED !! 2476 config CPU_NEEDS_NO_SMARTMIPS_OR_MICROMIPS
1755 bool "Emulate deprecated/obsolete ARM !! 2477 bool "None"
1756 depends on SYSCTL <<
1757 help 2478 help
1758 Legacy software support may require !! 2479 Select this if you want neither microMIPS nor SmartMIPS support
1759 that have been deprecated or obsole <<
1760 2480
1761 Enable this config to enable select !! 2481 config CPU_HAS_SMARTMIPS
1762 features. !! 2482 depends on SYS_SUPPORTS_SMARTMIPS
>> 2483 bool "SmartMIPS"
>> 2484 help
>> 2485 SmartMIPS is a extension of the MIPS32 architecture aimed at
>> 2486 increased security at both hardware and software level for
>> 2487 smartcards. Enabling this option will allow proper use of the
>> 2488 SmartMIPS instructions by Linux applications. However a kernel with
>> 2489 this option will not work on a MIPS core without SmartMIPS core. If
>> 2490 you don't know you probably don't have SmartMIPS and should say N
>> 2491 here.
>> 2492
>> 2493 config CPU_MICROMIPS
>> 2494 depends on 32BIT && SYS_SUPPORTS_MICROMIPS && !CPU_MIPSR6
>> 2495 bool "microMIPS"
>> 2496 help
>> 2497 When this option is enabled the kernel will be built using the
>> 2498 microMIPS ISA
1763 2499
1764 If unsure, say Y !! 2500 endchoice
1765 2501
1766 if ARMV8_DEPRECATED !! 2502 config CPU_HAS_MSA
>> 2503 bool "Support for the MIPS SIMD Architecture"
>> 2504 depends on CPU_SUPPORTS_MSA
>> 2505 depends on MIPS_FP_SUPPORT
>> 2506 depends on 64BIT || MIPS_O32_FP64_SUPPORT
>> 2507 help
>> 2508 MIPS SIMD Architecture (MSA) introduces 128 bit wide vector registers
>> 2509 and a set of SIMD instructions to operate on them. When this option
>> 2510 is enabled the kernel will support allocating & switching MSA
>> 2511 vector register contexts. If you know that your kernel will only be
>> 2512 running on CPUs which do not support MSA or that your userland will
>> 2513 not be making use of it then you may wish to say N here to reduce
>> 2514 the size & complexity of your kernel.
1767 2515
1768 config SWP_EMULATION !! 2516 If unsure, say Y.
1769 bool "Emulate SWP/SWPB instructions" <<
1770 help <<
1771 ARMv8 obsoletes the use of A32 SWP/ <<
1772 they are always undefined. Say Y he <<
1773 emulation of these instructions for <<
1774 This feature can be controlled at r <<
1775 sysctl which is disabled by default <<
1776 2517
1777 In some older versions of glibc [<= !! 2518 config CPU_HAS_WB
1778 trylock() operations with the assum !! 2519 bool
1779 be preempted. This invalid assumpti <<
1780 with SWP emulation enabled, leading <<
1781 application. <<
1782 2520
1783 NOTE: when accessing uncached share !! 2521 config XKS01
1784 on an external transaction monitori !! 2522 bool
1785 monitor to maintain update atomicit <<
1786 implement a global monitor, this op <<
1787 perform SWP operations to uncached <<
1788 2523
1789 If unsure, say Y !! 2524 config CPU_HAS_RIXI
>> 2525 bool
1790 2526
1791 config CP15_BARRIER_EMULATION !! 2527 config CPU_HAS_LOAD_STORE_LR
1792 bool "Emulate CP15 Barrier instructio !! 2528 bool
1793 help 2529 help
1794 The CP15 barrier instructions - CP1 !! 2530 CPU has support for unaligned load and store instructions:
1795 CP15DMB - are deprecated in ARMv8 ( !! 2531 LWL, LWR, SWL, SWR (Load/store word left/right).
1796 strongly recommended to use the ISB !! 2532 LDL, LDR, SDL, SDR (Load/store doubleword left/right, for 64bit systems).
1797 instructions instead. <<
1798 2533
1799 Say Y here to enable software emula !! 2534 #
1800 instructions for AArch32 userspace !! 2535 # Vectored interrupt mode is an R2 feature
1801 enabled, CP15 barrier usage is trac !! 2536 #
1802 identify software that needs updati !! 2537 config CPU_MIPSR2_IRQ_VI
1803 controlled at runtime with the abi. !! 2538 bool
1804 2539
1805 If unsure, say Y !! 2540 #
>> 2541 # Extended interrupt mode is an R2 feature
>> 2542 #
>> 2543 config CPU_MIPSR2_IRQ_EI
>> 2544 bool
1806 2545
1807 config SETEND_EMULATION !! 2546 config CPU_HAS_SYNC
1808 bool "Emulate SETEND instruction" !! 2547 bool
1809 help !! 2548 depends on !CPU_R3000
1810 The SETEND instruction alters the d !! 2549 default y
1811 AArch32 EL0, and is deprecated in A <<
1812 2550
1813 Say Y here to enable software emula !! 2551 #
1814 for AArch32 userspace code. This fe !! 2552 # CPU non-features
1815 at runtime with the abi.setend sysc !! 2553 #
>> 2554 config CPU_DADDI_WORKAROUNDS
>> 2555 bool
1816 2556
1817 Note: All the cpus on the system mu !! 2557 config CPU_R4000_WORKAROUNDS
1818 for this feature to be enabled. If !! 2558 bool
1819 endian - is hotplugged in after thi !! 2559 select CPU_R4400_WORKAROUNDS
1820 be unexpected results in the applic <<
1821 2560
1822 If unsure, say Y !! 2561 config CPU_R4400_WORKAROUNDS
1823 endif # ARMV8_DEPRECATED !! 2562 bool
1824 2563
1825 endif # COMPAT !! 2564 config MIPS_ASID_SHIFT
>> 2565 int
>> 2566 default 6 if CPU_R3000 || CPU_TX39XX
>> 2567 default 0
1826 2568
1827 menu "ARMv8.1 architectural features" !! 2569 config MIPS_ASID_BITS
>> 2570 int
>> 2571 default 0 if MIPS_ASID_BITS_VARIABLE
>> 2572 default 6 if CPU_R3000 || CPU_TX39XX
>> 2573 default 8
1828 2574
1829 config ARM64_HW_AFDBM !! 2575 config MIPS_ASID_BITS_VARIABLE
1830 bool "Support for hardware updates of !! 2576 bool
1831 default y <<
1832 help <<
1833 The ARMv8.1 architecture extensions <<
1834 hardware updates of the access and <<
1835 table entries. When enabled in TCR_ <<
1836 capable processors, accesses to pag <<
1837 set this bit instead of raising an <<
1838 Similarly, writes to read-only page <<
1839 clear the read-only bit (AP[2]) ins <<
1840 permission fault. <<
1841 2577
1842 Kernels built with this configurati !! 2578 config MIPS_CRC_SUPPORT
1843 to work on pre-ARMv8.1 hardware and !! 2579 bool
1844 minimal. If unsure, say Y. <<
1845 2580
1846 config ARM64_PAN !! 2581 #
1847 bool "Enable support for Privileged A !! 2582 # - Highmem only makes sense for the 32-bit kernel.
1848 default y !! 2583 # - The current highmem code will only work properly on physically indexed
1849 help !! 2584 # caches such as R3000, SB1, R7000 or those that look like they're virtually
1850 Privileged Access Never (PAN; part !! 2585 # indexed such as R4000/R4400 SC and MC versions or R10000. So for the
1851 prevents the kernel or hypervisor f !! 2586 # moment we protect the user and offer the highmem option only on machines
1852 memory directly. !! 2587 # where it's known to be safe. This will not offer highmem on a few systems
>> 2588 # such as MIPS32 and MIPS64 CPUs which may have virtual and physically
>> 2589 # indexed CPUs but we're playing safe.
>> 2590 # - We use SYS_SUPPORTS_HIGHMEM to offer highmem only for systems where we
>> 2591 # know they might have memory configurations that could make use of highmem
>> 2592 # support.
>> 2593 #
>> 2594 config HIGHMEM
>> 2595 bool "High Memory Support"
>> 2596 depends on 32BIT && CPU_SUPPORTS_HIGHMEM && SYS_SUPPORTS_HIGHMEM && !CPU_MIPS32_3_5_EVA
1853 2597
1854 Choosing this option will cause any !! 2598 config CPU_SUPPORTS_HIGHMEM
1855 copy_to_user et al) memory access t !! 2599 bool
1856 2600
1857 The feature is detected at runtime, !! 2601 config SYS_SUPPORTS_HIGHMEM
1858 instruction if the cpu does not imp !! 2602 bool
1859 2603
1860 config AS_HAS_LSE_ATOMICS !! 2604 config SYS_SUPPORTS_SMARTMIPS
1861 def_bool $(as-instr,.arch_extension l !! 2605 bool
1862 2606
1863 config ARM64_LSE_ATOMICS !! 2607 config SYS_SUPPORTS_MICROMIPS
1864 bool 2608 bool
1865 default ARM64_USE_LSE_ATOMICS <<
1866 depends on AS_HAS_LSE_ATOMICS <<
1867 2609
1868 config ARM64_USE_LSE_ATOMICS !! 2610 config SYS_SUPPORTS_MIPS16
1869 bool "Atomic instructions" !! 2611 bool
1870 default y <<
1871 help 2612 help
1872 As part of the Large System Extensi !! 2613 This option must be set if a kernel might be executed on a MIPS16-
1873 atomic instructions that are design !! 2614 enabled CPU even if MIPS16 is not actually being used. In other
1874 very large systems. !! 2615 words, it makes the kernel MIPS16-tolerant.
1875 2616
1876 Say Y here to make use of these ins !! 2617 config CPU_SUPPORTS_MSA
1877 atomic routines. This incurs a smal !! 2618 bool
1878 not support these instructions and <<
1879 built with binutils >= 2.25 in orde <<
1880 to be used. <<
1881 <<
1882 endmenu # "ARMv8.1 architectural features" <<
1883 2619
1884 menu "ARMv8.2 architectural features" !! 2620 config ARCH_FLATMEM_ENABLE
>> 2621 def_bool y
>> 2622 depends on !NUMA && !CPU_LOONGSON2
1885 2623
1886 config AS_HAS_ARMV8_2 !! 2624 config ARCH_DISCONTIGMEM_ENABLE
1887 def_bool $(cc-option,-Wa$(comma)-marc !! 2625 bool
>> 2626 default y if SGI_IP27
>> 2627 help
>> 2628 Say Y to support efficient handling of discontiguous physical memory,
>> 2629 for architectures which are either NUMA (Non-Uniform Memory Access)
>> 2630 or have huge holes in the physical address space for other reasons.
>> 2631 See <file:Documentation/vm/numa.rst> for more.
1888 2632
1889 config AS_HAS_SHA3 !! 2633 config ARCH_SPARSEMEM_ENABLE
1890 def_bool $(as-instr,.arch armv8.2-a+s !! 2634 bool
>> 2635 select SPARSEMEM_STATIC
1891 2636
1892 config ARM64_PMEM !! 2637 config NUMA
1893 bool "Enable support for persistent m !! 2638 bool "NUMA Support"
1894 select ARCH_HAS_PMEM_API !! 2639 depends on SYS_SUPPORTS_NUMA
1895 select ARCH_HAS_UACCESS_FLUSHCACHE <<
1896 help 2640 help
1897 Say Y to enable support for the per !! 2641 Say Y to compile the kernel to support NUMA (Non-Uniform Memory
1898 ARMv8.2 DCPoP feature. !! 2642 Access). This option improves performance on systems with more
>> 2643 than two nodes; on two node systems it is generally better to
>> 2644 leave it disabled; on single node systems disable this option
>> 2645 disabled.
1899 2646
1900 The feature is detected at runtime, !! 2647 config SYS_SUPPORTS_NUMA
1901 operations if DC CVAP is not suppor !! 2648 bool
1902 DC CVAP itself if the system does n <<
1903 2649
1904 config ARM64_RAS_EXTN !! 2650 config RELOCATABLE
1905 bool "Enable support for RAS CPU Exte !! 2651 bool "Relocatable kernel"
1906 default y !! 2652 depends on SYS_SUPPORTS_RELOCATABLE && (CPU_MIPS32_R2 || CPU_MIPS64_R2 || CPU_MIPS32_R6 || CPU_MIPS64_R6 || CAVIUM_OCTEON_SOC)
1907 help 2653 help
1908 CPUs that support the Reliability, !! 2654 This builds a kernel image that retains relocation information
1909 (RAS) Extensions, part of ARMv8.2 a !! 2655 so it can be loaded someplace besides the default 1MB.
1910 errors, classify them and report th !! 2656 The relocations make the kernel binary about 15% larger,
>> 2657 but are discarded at runtime
>> 2658
>> 2659 config RELOCATION_TABLE_SIZE
>> 2660 hex "Relocation table size"
>> 2661 depends on RELOCATABLE
>> 2662 range 0x0 0x01000000
>> 2663 default "0x00100000"
>> 2664 ---help---
>> 2665 A table of relocation data will be appended to the kernel binary
>> 2666 and parsed at boot to fix up the relocated kernel.
1911 2667
1912 On CPUs with these extensions syste !! 2668 This option allows the amount of space reserved for the table to be
1913 barriers to determine if faults are !! 2669 adjusted, although the default of 1Mb should be ok in most cases.
1914 classification from a new set of re <<
1915 2670
1916 Selecting this feature will allow t !! 2671 The build will fail and a valid size suggested if this is too small.
1917 and access the new registers if the <<
1918 Platform RAS features may additiona <<
1919 2672
1920 config ARM64_CNP !! 2673 If unsure, leave at the default value.
1921 bool "Enable support for Common Not P <<
1922 default y <<
1923 depends on ARM64_PAN || !ARM64_SW_TTB <<
1924 help <<
1925 Common Not Private (CNP) allows tra <<
1926 be shared between different PEs in <<
1927 domain, so the hardware can use thi <<
1928 caching of such entries in the TLB. <<
1929 2674
1930 Selecting this option allows the CN !! 2675 config RANDOMIZE_BASE
1931 at runtime, and does not affect PEs !! 2676 bool "Randomize the address of the kernel image"
1932 this feature. !! 2677 depends on RELOCATABLE
>> 2678 ---help---
>> 2679 Randomizes the physical and virtual address at which the
>> 2680 kernel image is loaded, as a security feature that
>> 2681 deters exploit attempts relying on knowledge of the location
>> 2682 of kernel internals.
1933 2683
1934 endmenu # "ARMv8.2 architectural features" !! 2684 Entropy is generated using any coprocessor 0 registers available.
1935 2685
1936 menu "ARMv8.3 architectural features" !! 2686 The kernel will be offset by up to RANDOMIZE_BASE_MAX_OFFSET.
1937 2687
1938 config ARM64_PTR_AUTH !! 2688 If unsure, say N.
1939 bool "Enable support for pointer auth <<
1940 default y <<
1941 help <<
1942 Pointer authentication (part of the <<
1943 instructions for signing and authen <<
1944 keys, which can be used to mitigate <<
1945 and other attacks. <<
1946 2689
1947 This option enables these instructi !! 2690 config RANDOMIZE_BASE_MAX_OFFSET
1948 Choosing this option will cause the !! 2691 hex "Maximum kASLR offset" if EXPERT
1949 for each process at exec() time, wi !! 2692 depends on RANDOMIZE_BASE
1950 context-switched along with the pro !! 2693 range 0x0 0x40000000 if EVA || 64BIT
>> 2694 range 0x0 0x08000000
>> 2695 default "0x01000000"
>> 2696 ---help---
>> 2697 When kASLR is active, this provides the maximum offset that will
>> 2698 be applied to the kernel image. It should be set according to the
>> 2699 amount of physical RAM available in the target system minus
>> 2700 PHYSICAL_START and must be a power of 2.
1951 2701
1952 The feature is detected at runtime. !! 2702 This is limited by the size of KSEG0, 256Mb on 32-bit or 1Gb with
1953 hardware it will not be advertised !! 2703 EVA or 64-bit. The default is 16Mb.
1954 be enabled. <<
1955 2704
1956 If the feature is present on the bo !! 2705 config NODES_SHIFT
1957 the late CPU will be parked. Also, !! 2706 int
1958 address auth and the late CPU has t !! 2707 default "6"
1959 but with the feature disabled. On s !! 2708 depends on NEED_MULTIPLE_NODES
1960 not be selected. <<
1961 2709
1962 config ARM64_PTR_AUTH_KERNEL !! 2710 config HW_PERF_EVENTS
1963 bool "Use pointer authentication for !! 2711 bool "Enable hardware performance counter support for perf events"
>> 2712 depends on PERF_EVENTS && !OPROFILE && (CPU_MIPS32 || CPU_MIPS64 || CPU_R10000 || CPU_SB1 || CPU_CAVIUM_OCTEON || CPU_XLP || CPU_LOONGSON3)
1964 default y 2713 default y
1965 depends on ARM64_PTR_AUTH <<
1966 depends on (CC_HAS_SIGN_RETURN_ADDRES <<
1967 # Modern compilers insert a .note.gnu <<
1968 # which is only understood by binutil <<
1969 depends on LD_IS_LLD || LD_VERSION >= <<
1970 depends on !CC_IS_CLANG || AS_HAS_CFI <<
1971 depends on (!FUNCTION_GRAPH_TRACER || <<
1972 help 2714 help
1973 If the compiler supports the -mbran !! 2715 Enable hardware performance counter support for perf events. If
1974 -msign-return-address flag (e.g. GC !! 2716 disabled, perf events will use software events only.
1975 will cause the kernel itself to be <<
1976 protection. In this case, and if th <<
1977 support pointer authentication, the <<
1978 disabled with minimal loss of prote <<
1979 2717
1980 This feature works with FUNCTION_GR !! 2718 config SMP
1981 DYNAMIC_FTRACE_WITH_ARGS is enabled !! 2719 bool "Multi-Processing support"
>> 2720 depends on SYS_SUPPORTS_SMP
>> 2721 help
>> 2722 This enables support for systems with more than one CPU. If you have
>> 2723 a system with only one CPU, say N. If you have a system with more
>> 2724 than one CPU, say Y.
>> 2725
>> 2726 If you say N here, the kernel will run on uni- and multiprocessor
>> 2727 machines, but will use only one CPU of a multiprocessor machine. If
>> 2728 you say Y here, the kernel will run on many, but not all,
>> 2729 uniprocessor machines. On a uniprocessor machine, the kernel
>> 2730 will run faster if you say N here.
1982 2731
1983 config CC_HAS_BRANCH_PROT_PAC_RET !! 2732 People using multiprocessor machines who say Y here should also say
1984 # GCC 9 or later, clang 8 or later !! 2733 Y to "Enhanced Real Time Clock Support", below.
1985 def_bool $(cc-option,-mbranch-protect <<
1986 2734
1987 config CC_HAS_SIGN_RETURN_ADDRESS !! 2735 See also the SMP-HOWTO available at
1988 # GCC 7, 8 !! 2736 <http://www.tldp.org/docs.html#howto>.
1989 def_bool $(cc-option,-msign-return-ad <<
1990 2737
1991 config AS_HAS_ARMV8_3 !! 2738 If you don't know what to do here, say N.
1992 def_bool $(cc-option,-Wa$(comma)-marc <<
1993 2739
1994 config AS_HAS_CFI_NEGATE_RA_STATE !! 2740 config HOTPLUG_CPU
1995 def_bool $(as-instr,.cfi_startproc\n. !! 2741 bool "Support for hot-pluggable CPUs"
>> 2742 depends on SMP && SYS_SUPPORTS_HOTPLUG_CPU
>> 2743 help
>> 2744 Say Y here to allow turning CPUs off and on. CPUs can be
>> 2745 controlled through /sys/devices/system/cpu.
>> 2746 (Note: power management support will enable this option
>> 2747 automatically on SMP systems. )
>> 2748 Say N if you want to disable CPU hotplug.
1996 2749
1997 config AS_HAS_LDAPR !! 2750 config SMP_UP
1998 def_bool $(as-instr,.arch_extension r !! 2751 bool
1999 2752
2000 endmenu # "ARMv8.3 architectural features" !! 2753 config SYS_SUPPORTS_MIPS_CMP
>> 2754 bool
2001 2755
2002 menu "ARMv8.4 architectural features" !! 2756 config SYS_SUPPORTS_MIPS_CPS
>> 2757 bool
2003 2758
2004 config ARM64_AMU_EXTN !! 2759 config SYS_SUPPORTS_SMP
2005 bool "Enable support for the Activity !! 2760 bool
2006 default y !! 2761
2007 help !! 2762 config NR_CPUS_DEFAULT_4
2008 The activity monitors extension is !! 2763 bool
2009 by the ARMv8.4 CPU architecture. Th <<
2010 of the activity monitors architectu <<
2011 2764
2012 To enable the use of this extension !! 2765 config NR_CPUS_DEFAULT_8
>> 2766 bool
2013 2767
2014 Note that for architectural reasons !! 2768 config NR_CPUS_DEFAULT_16
2015 support when running on CPUs that p !! 2769 bool
2016 extension. The required support is <<
2017 * Version 1.5 and later of the AR <<
2018 2770
2019 For kernels that have this configur !! 2771 config NR_CPUS_DEFAULT_32
2020 firmware, you may need to say N her !! 2772 bool
2021 Otherwise you may experience firmwa <<
2022 accessing the counter registers. Ev <<
2023 symptoms, the values returned by th <<
2024 correctly reflect reality. Most com <<
2025 indicating that the counter is not <<
2026 2773
2027 config AS_HAS_ARMV8_4 !! 2774 config NR_CPUS_DEFAULT_64
2028 def_bool $(cc-option,-Wa$(comma)-marc !! 2775 bool
2029 2776
2030 config ARM64_TLB_RANGE !! 2777 config NR_CPUS
2031 bool "Enable support for tlbi range f !! 2778 int "Maximum number of CPUs (2-256)"
2032 default y !! 2779 range 2 256
2033 depends on AS_HAS_ARMV8_4 !! 2780 depends on SMP
2034 help !! 2781 default "4" if NR_CPUS_DEFAULT_4
2035 ARMv8.4-TLBI provides TLBI invalida !! 2782 default "8" if NR_CPUS_DEFAULT_8
2036 range of input addresses. !! 2783 default "16" if NR_CPUS_DEFAULT_16
>> 2784 default "32" if NR_CPUS_DEFAULT_32
>> 2785 default "64" if NR_CPUS_DEFAULT_64
>> 2786 help
>> 2787 This allows you to specify the maximum number of CPUs which this
>> 2788 kernel will support. The maximum supported value is 32 for 32-bit
>> 2789 kernel and 64 for 64-bit kernels; the minimum value which makes
>> 2790 sense is 1 for Qemu (useful only for kernel debugging purposes)
>> 2791 and 2 for all others.
>> 2792
>> 2793 This is purely to save memory - each supported CPU adds
>> 2794 approximately eight kilobytes to the kernel image. For best
>> 2795 performance should round up your number of processors to the next
>> 2796 power of two.
2037 2797
2038 The feature introduces new assembly !! 2798 config MIPS_PERF_SHARED_TC_COUNTERS
2039 support when binutils >= 2.30. !! 2799 bool
2040 2800
2041 endmenu # "ARMv8.4 architectural features" !! 2801 config MIPS_NR_CPU_NR_MAP_1024
>> 2802 bool
2042 2803
2043 menu "ARMv8.5 architectural features" !! 2804 config MIPS_NR_CPU_NR_MAP
>> 2805 int
>> 2806 depends on SMP
>> 2807 default 1024 if MIPS_NR_CPU_NR_MAP_1024
>> 2808 default NR_CPUS if !MIPS_NR_CPU_NR_MAP_1024
2044 2809
2045 config AS_HAS_ARMV8_5 !! 2810 #
2046 def_bool $(cc-option,-Wa$(comma)-marc !! 2811 # Timer Interrupt Frequency Configuration
>> 2812 #
2047 2813
2048 config ARM64_BTI !! 2814 choice
2049 bool "Branch Target Identification su !! 2815 prompt "Timer frequency"
2050 default y !! 2816 default HZ_250
2051 help 2817 help
2052 Branch Target Identification (part !! 2818 Allows the configuration of the timer frequency.
2053 provides a mechanism to limit the s <<
2054 branch instructions such as BR or B <<
2055 2819
2056 To make use of BTI on CPUs that sup !! 2820 config HZ_24
>> 2821 bool "24 HZ" if SYS_SUPPORTS_24HZ || SYS_SUPPORTS_ARBIT_HZ
2057 2822
2058 BTI is intended to provide compleme !! 2823 config HZ_48
2059 flow integrity protection mechanism !! 2824 bool "48 HZ" if SYS_SUPPORTS_48HZ || SYS_SUPPORTS_ARBIT_HZ
2060 authentication mechanism provided a <<
2061 For this reason, it does not make s <<
2062 also enabling support for pointer a <<
2063 enabling this option you should als <<
2064 2825
2065 Userspace binaries must also be spe !! 2826 config HZ_100
2066 this mechanism. If you say N here !! 2827 bool "100 HZ" if SYS_SUPPORTS_100HZ || SYS_SUPPORTS_ARBIT_HZ
2067 BTI, such binaries can still run, b <<
2068 enforcement of branch destinations. <<
2069 2828
2070 config ARM64_BTI_KERNEL !! 2829 config HZ_128
2071 bool "Use Branch Target Identificatio !! 2830 bool "128 HZ" if SYS_SUPPORTS_128HZ || SYS_SUPPORTS_ARBIT_HZ
2072 default y <<
2073 depends on ARM64_BTI <<
2074 depends on ARM64_PTR_AUTH_KERNEL <<
2075 depends on CC_HAS_BRANCH_PROT_PAC_RET <<
2076 # https://gcc.gnu.org/bugzilla/show_b <<
2077 depends on !CC_IS_GCC || GCC_VERSION <<
2078 # https://gcc.gnu.org/bugzilla/show_b <<
2079 depends on !CC_IS_GCC <<
2080 depends on (!FUNCTION_GRAPH_TRACER || <<
2081 help <<
2082 Build the kernel with Branch Target <<
2083 and enable enforcement of this for <<
2084 is enabled and the system supports <<
2085 modular code must have BTI enabled. <<
2086 2831
2087 config CC_HAS_BRANCH_PROT_PAC_RET_BTI !! 2832 config HZ_250
2088 # GCC 9 or later, clang 8 or later !! 2833 bool "250 HZ" if SYS_SUPPORTS_250HZ || SYS_SUPPORTS_ARBIT_HZ
2089 def_bool $(cc-option,-mbranch-protect <<
2090 2834
2091 config ARM64_E0PD !! 2835 config HZ_256
2092 bool "Enable support for E0PD" !! 2836 bool "256 HZ" if SYS_SUPPORTS_256HZ || SYS_SUPPORTS_ARBIT_HZ
2093 default y <<
2094 help <<
2095 E0PD (part of the ARMv8.5 extension <<
2096 that EL0 accesses made via TTBR1 al <<
2097 providing similar benefits to KASLR <<
2098 with lower overhead and without dis <<
2099 kernel memory such as SPE. <<
2100 2837
2101 This option enables E0PD for TTBR1 !! 2838 config HZ_1000
>> 2839 bool "1000 HZ" if SYS_SUPPORTS_1000HZ || SYS_SUPPORTS_ARBIT_HZ
2102 2840
2103 config ARM64_AS_HAS_MTE !! 2841 config HZ_1024
2104 # Initial support for MTE went in bin !! 2842 bool "1024 HZ" if SYS_SUPPORTS_1024HZ || SYS_SUPPORTS_ARBIT_HZ
2105 # ".arch armv8.5-a+memtag" below. How <<
2106 # as a late addition to the final arc <<
2107 # is only supported in the newer 2.32 <<
2108 # versions, hence the extra "stgm" in <<
2109 def_bool $(as-instr,.arch armv8.5-a+m <<
2110 2843
2111 config ARM64_MTE !! 2844 endchoice
2112 bool "Memory Tagging Extension suppor <<
2113 default y <<
2114 depends on ARM64_AS_HAS_MTE && ARM64_ <<
2115 depends on AS_HAS_ARMV8_5 <<
2116 depends on AS_HAS_LSE_ATOMICS <<
2117 # Required for tag checking in the ua <<
2118 depends on ARM64_PAN <<
2119 select ARCH_HAS_SUBPAGE_FAULTS <<
2120 select ARCH_USES_HIGH_VMA_FLAGS <<
2121 select ARCH_USES_PG_ARCH_2 <<
2122 select ARCH_USES_PG_ARCH_3 <<
2123 help <<
2124 Memory Tagging (part of the ARMv8.5 <<
2125 architectural support for run-time, <<
2126 various classes of memory error to <<
2127 to eliminate vulnerabilities arisin <<
2128 languages. <<
2129 2845
2130 This option enables the support for !! 2846 config SYS_SUPPORTS_24HZ
2131 Extension at EL0 (i.e. for userspac !! 2847 bool
2132 2848
2133 Selecting this option allows the fe !! 2849 config SYS_SUPPORTS_48HZ
2134 runtime. Any secondary CPU not impl !! 2850 bool
2135 not be allowed a late bring-up. <<
2136 2851
2137 Userspace binaries that want to use !! 2852 config SYS_SUPPORTS_100HZ
2138 explicitly opt in. The mechanism fo !! 2853 bool
2139 described in: <<
2140 2854
2141 Documentation/arch/arm64/memory-tag !! 2855 config SYS_SUPPORTS_128HZ
>> 2856 bool
2142 2857
2143 endmenu # "ARMv8.5 architectural features" !! 2858 config SYS_SUPPORTS_250HZ
>> 2859 bool
2144 2860
2145 menu "ARMv8.7 architectural features" !! 2861 config SYS_SUPPORTS_256HZ
>> 2862 bool
2146 2863
2147 config ARM64_EPAN !! 2864 config SYS_SUPPORTS_1000HZ
2148 bool "Enable support for Enhanced Pri !! 2865 bool
2149 default y <<
2150 depends on ARM64_PAN <<
2151 help <<
2152 Enhanced Privileged Access Never (E <<
2153 Access Never to be used with Execut <<
2154 2866
2155 The feature is detected at runtime, !! 2867 config SYS_SUPPORTS_1024HZ
2156 if the cpu does not implement the f !! 2868 bool
2157 endmenu # "ARMv8.7 architectural features" <<
2158 2869
2159 menu "ARMv8.9 architectural features" !! 2870 config SYS_SUPPORTS_ARBIT_HZ
>> 2871 bool
>> 2872 default y if !SYS_SUPPORTS_24HZ && \
>> 2873 !SYS_SUPPORTS_48HZ && \
>> 2874 !SYS_SUPPORTS_100HZ && \
>> 2875 !SYS_SUPPORTS_128HZ && \
>> 2876 !SYS_SUPPORTS_250HZ && \
>> 2877 !SYS_SUPPORTS_256HZ && \
>> 2878 !SYS_SUPPORTS_1000HZ && \
>> 2879 !SYS_SUPPORTS_1024HZ
2160 2880
2161 config ARM64_POE !! 2881 config HZ
2162 prompt "Permission Overlay Extension" !! 2882 int
2163 def_bool y !! 2883 default 24 if HZ_24
2164 select ARCH_USES_HIGH_VMA_FLAGS !! 2884 default 48 if HZ_48
2165 select ARCH_HAS_PKEYS !! 2885 default 100 if HZ_100
2166 help !! 2886 default 128 if HZ_128
2167 The Permission Overlay Extension is !! 2887 default 250 if HZ_250
2168 Protection Keys. Memory Protection !! 2888 default 256 if HZ_256
2169 enforcing page-based protections, b !! 2889 default 1000 if HZ_1000
2170 of the page tables when an applicat !! 2890 default 1024 if HZ_1024
>> 2891
>> 2892 config SCHED_HRTICK
>> 2893 def_bool HIGH_RES_TIMERS
>> 2894
>> 2895 config KEXEC
>> 2896 bool "Kexec system call"
>> 2897 select KEXEC_CORE
>> 2898 help
>> 2899 kexec is a system call that implements the ability to shutdown your
>> 2900 current kernel, and to start another kernel. It is like a reboot
>> 2901 but it is independent of the system firmware. And like a reboot
>> 2902 you can start any kernel with it, not just Linux.
>> 2903
>> 2904 The name comes from the similarity to the exec system call.
>> 2905
>> 2906 It is an ongoing process to be certain the hardware in a machine
>> 2907 is properly shutdown, so do not be surprised if this code does not
>> 2908 initially work for you. As of this writing the exact hardware
>> 2909 interface is strongly in flux, so no good recommendation can be
>> 2910 made.
>> 2911
>> 2912 config CRASH_DUMP
>> 2913 bool "Kernel crash dumps"
>> 2914 help
>> 2915 Generate crash dump after being started by kexec.
>> 2916 This should be normally only set in special crash dump kernels
>> 2917 which are loaded in the main kernel with kexec-tools into
>> 2918 a specially reserved region and then later executed after
>> 2919 a crash by kdump/kexec. The crash dump kernel must be compiled
>> 2920 to a memory address not used by the main kernel or firmware using
>> 2921 PHYSICAL_START.
>> 2922
>> 2923 config PHYSICAL_START
>> 2924 hex "Physical address where the kernel is loaded"
>> 2925 default "0xffffffff84000000"
>> 2926 depends on CRASH_DUMP
>> 2927 help
>> 2928 This gives the CKSEG0 or KSEG0 address where the kernel is loaded.
>> 2929 If you plan to use kernel for capturing the crash dump change
>> 2930 this value to start of the reserved region (the "X" value as
>> 2931 specified in the "crashkernel=YM@XM" command line boot parameter
>> 2932 passed to the panic-ed kernel).
>> 2933
>> 2934 config SECCOMP
>> 2935 bool "Enable seccomp to safely compute untrusted bytecode"
>> 2936 depends on PROC_FS
>> 2937 default y
>> 2938 help
>> 2939 This kernel feature is useful for number crunching applications
>> 2940 that may need to compute untrusted bytecode during their
>> 2941 execution. By using pipes or other transports made available to
>> 2942 the process as file descriptors supporting the read/write
>> 2943 syscalls, it's possible to isolate those applications in
>> 2944 their own address space using seccomp. Once seccomp is
>> 2945 enabled via /proc/<pid>/seccomp, it cannot be disabled
>> 2946 and the task is only allowed to execute a few safe syscalls
>> 2947 defined by each seccomp mode.
>> 2948
>> 2949 If unsure, say Y. Only embedded should say N here.
>> 2950
>> 2951 config MIPS_O32_FP64_SUPPORT
>> 2952 bool "Support for O32 binaries using 64-bit FP" if !CPU_MIPSR6
>> 2953 depends on 32BIT || MIPS32_O32
>> 2954 help
>> 2955 When this is enabled, the kernel will support use of 64-bit floating
>> 2956 point registers with binaries using the O32 ABI along with the
>> 2957 EF_MIPS_FP64 ELF header flag (typically built with -mfp64). On
>> 2958 32-bit MIPS systems this support is at the cost of increasing the
>> 2959 size and complexity of the compiled FPU emulator. Thus if you are
>> 2960 running a MIPS32 system and know that none of your userland binaries
>> 2961 will require 64-bit floating point, you may wish to reduce the size
>> 2962 of your kernel & potentially improve FP emulation performance by
>> 2963 saying N here.
>> 2964
>> 2965 Although binutils currently supports use of this flag the details
>> 2966 concerning its effect upon the O32 ABI in userland are still being
>> 2967 worked on. In order to avoid userland becoming dependant upon current
>> 2968 behaviour before the details have been finalised, this option should
>> 2969 be considered experimental and only enabled by those working upon
>> 2970 said details.
2171 2971
2172 For details, see Documentation/core !! 2972 If unsure, say N.
2173 2973
2174 If unsure, say y. !! 2974 config USE_OF
>> 2975 bool
>> 2976 select OF
>> 2977 select OF_EARLY_FLATTREE
>> 2978 select IRQ_DOMAIN
2175 2979
2176 config ARCH_PKEY_BITS !! 2980 config UHI_BOOT
2177 int !! 2981 bool
2178 default 3 <<
2179 2982
2180 endmenu # "ARMv8.9 architectural features" !! 2983 config BUILTIN_DTB
>> 2984 bool
2181 2985
2182 config ARM64_SVE !! 2986 choice
2183 bool "ARM Scalable Vector Extension s !! 2987 prompt "Kernel appended dtb support" if USE_OF
2184 default y !! 2988 default MIPS_NO_APPENDED_DTB
2185 help <<
2186 The Scalable Vector Extension (SVE) <<
2187 execution state which complements a <<
2188 of the base architecture to support <<
2189 additional vectorisation opportunit <<
2190 2989
2191 To enable use of this extension on !! 2990 config MIPS_NO_APPENDED_DTB
>> 2991 bool "None"
>> 2992 help
>> 2993 Do not enable appended dtb support.
>> 2994
>> 2995 config MIPS_ELF_APPENDED_DTB
>> 2996 bool "vmlinux"
>> 2997 help
>> 2998 With this option, the boot code will look for a device tree binary
>> 2999 DTB) included in the vmlinux ELF section .appended_dtb. By default
>> 3000 it is empty and the DTB can be appended using binutils command
>> 3001 objcopy:
>> 3002
>> 3003 objcopy --update-section .appended_dtb=<filename>.dtb vmlinux
>> 3004
>> 3005 This is meant as a backward compatiblity convenience for those
>> 3006 systems with a bootloader that can't be upgraded to accommodate
>> 3007 the documented boot protocol using a device tree.
>> 3008
>> 3009 config MIPS_RAW_APPENDED_DTB
>> 3010 bool "vmlinux.bin or vmlinuz.bin"
>> 3011 help
>> 3012 With this option, the boot code will look for a device tree binary
>> 3013 DTB) appended to raw vmlinux.bin or vmlinuz.bin.
>> 3014 (e.g. cat vmlinux.bin <filename>.dtb > vmlinux_w_dtb).
>> 3015
>> 3016 This is meant as a backward compatibility convenience for those
>> 3017 systems with a bootloader that can't be upgraded to accommodate
>> 3018 the documented boot protocol using a device tree.
>> 3019
>> 3020 Beware that there is very little in terms of protection against
>> 3021 this option being confused by leftover garbage in memory that might
>> 3022 look like a DTB header after a reboot if no actual DTB is appended
>> 3023 to vmlinux.bin. Do not leave this option active in a production kernel
>> 3024 if you don't intend to always append a DTB.
>> 3025 endchoice
2192 3026
2193 On CPUs that support the SVE2 exten !! 3027 choice
2194 those too. !! 3028 prompt "Kernel command line type" if !CMDLINE_OVERRIDE
>> 3029 default MIPS_CMDLINE_FROM_DTB if USE_OF && !ATH79 && !MACH_INGENIC && \
>> 3030 !MIPS_MALTA && \
>> 3031 !CAVIUM_OCTEON_SOC
>> 3032 default MIPS_CMDLINE_FROM_BOOTLOADER
>> 3033
>> 3034 config MIPS_CMDLINE_FROM_DTB
>> 3035 depends on USE_OF
>> 3036 bool "Dtb kernel arguments if available"
>> 3037
>> 3038 config MIPS_CMDLINE_DTB_EXTEND
>> 3039 depends on USE_OF
>> 3040 bool "Extend dtb kernel arguments with bootloader arguments"
>> 3041
>> 3042 config MIPS_CMDLINE_FROM_BOOTLOADER
>> 3043 bool "Bootloader kernel arguments if available"
>> 3044
>> 3045 config MIPS_CMDLINE_BUILTIN_EXTEND
>> 3046 depends on CMDLINE_BOOL
>> 3047 bool "Extend builtin kernel arguments with bootloader arguments"
>> 3048 endchoice
2195 3049
2196 Note that for architectural reasons !! 3050 endmenu
2197 support when running on SVE capable <<
2198 is present in: <<
2199 3051
2200 * version 1.5 and later of the AR !! 3052 config LOCKDEP_SUPPORT
2201 * the AArch64 boot wrapper since !! 3053 bool
2202 ("bootwrapper: SVE: Enable SVE !! 3054 default y
2203 3055
2204 For other firmware implementations, !! 3056 config STACKTRACE_SUPPORT
2205 or vendor. !! 3057 bool
>> 3058 default y
2206 3059
2207 If you need the kernel to boot on S !! 3060 config PGTABLE_LEVELS
2208 firmware, you may need to say N her !! 3061 int
2209 fixed. Otherwise, you may experien !! 3062 default 4 if PAGE_SIZE_4KB && MIPS_VA_BITS_48
2210 booting the kernel. If unsure and !! 3063 default 3 if 64BIT && (!PAGE_SIZE_64KB || MIPS_VA_BITS_48)
2211 symptoms, you should assume that it !! 3064 default 2
2212 3065
2213 config ARM64_SME !! 3066 config MIPS_AUTO_PFN_OFFSET
2214 bool "ARM Scalable Matrix Extension s !! 3067 bool
2215 default y <<
2216 depends on ARM64_SVE <<
2217 depends on BROKEN <<
2218 help <<
2219 The Scalable Matrix Extension (SME) <<
2220 execution state which utilises a su <<
2221 instruction set, together with the <<
2222 register state capable of holding t <<
2223 enable various matrix operations. <<
2224 3068
2225 config ARM64_PSEUDO_NMI !! 3069 menu "Bus options (PCI, PCMCIA, EISA, ISA, TC)"
2226 bool "Support for NMI-like interrupts <<
2227 select ARM_GIC_V3 <<
2228 help <<
2229 Adds support for mimicking Non-Mask <<
2230 GIC interrupt priority. This suppor <<
2231 ARM GIC. <<
2232 3070
2233 This high priority configuration fo !! 3071 config PCI_DRIVERS_GENERIC
2234 explicitly enabled by setting the k !! 3072 select PCI_DOMAINS_GENERIC if PCI
2235 "irqchip.gicv3_pseudo_nmi" to 1. !! 3073 bool
2236 3074
2237 If unsure, say N !! 3075 config PCI_DRIVERS_LEGACY
>> 3076 def_bool !PCI_DRIVERS_GENERIC
>> 3077 select NO_GENERIC_PCI_IOPORT_MAP
>> 3078 select PCI_DOMAINS if PCI
2238 3079
2239 if ARM64_PSEUDO_NMI !! 3080 #
2240 config ARM64_DEBUG_PRIORITY_MASKING !! 3081 # ISA support is now enabled via select. Too many systems still have the one
2241 bool "Debug interrupt priority maskin !! 3082 # or other ISA chip on the board that users don't know about so don't expect
2242 help !! 3083 # users to choose the right thing ...
2243 This adds runtime checks to functio !! 3084 #
2244 interrupts when using priority mask !! 3085 config ISA
2245 the validity of ICC_PMR_EL1 when ca !! 3086 bool
2246 3087
2247 If unsure, say N !! 3088 config TC
2248 endif # ARM64_PSEUDO_NMI !! 3089 bool "TURBOchannel support"
>> 3090 depends on MACH_DECSTATION
>> 3091 help
>> 3092 TURBOchannel is a DEC (now Compaq (now HP)) bus for Alpha and MIPS
>> 3093 processors. TURBOchannel programming specifications are available
>> 3094 at:
>> 3095 <ftp://ftp.hp.com/pub/alphaserver/archive/triadd/>
>> 3096 and:
>> 3097 <http://www.computer-refuge.org/classiccmp/ftp.digital.com/pub/DEC/TriAdd/>
>> 3098 Linux driver support status is documented at:
>> 3099 <http://www.linux-mips.org/wiki/DECstation>
2249 3100
2250 config RELOCATABLE !! 3101 config MMU
2251 bool "Build a relocatable kernel imag !! 3102 bool
2252 select ARCH_HAS_RELR <<
2253 default y 3103 default y
2254 help <<
2255 This builds the kernel as a Positio <<
2256 which retains all relocation metada <<
2257 kernel binary at runtime to a diffe <<
2258 address it was linked at. <<
2259 Since AArch64 uses the RELA relocat <<
2260 relocation pass at runtime even if <<
2261 same address it was linked at. <<
2262 3104
2263 config RANDOMIZE_BASE !! 3105 config ARCH_MMAP_RND_BITS_MIN
2264 bool "Randomize the address of the ke !! 3106 default 12 if 64BIT
2265 select RELOCATABLE !! 3107 default 8
2266 help <<
2267 Randomizes the virtual address at w <<
2268 loaded, as a security feature that <<
2269 relying on knowledge of the locatio <<
2270 <<
2271 It is the bootloader's job to provi <<
2272 random u64 value in /chosen/kaslr-s <<
2273 <<
2274 When booting via the UEFI stub, it <<
2275 EFI_RNG_PROTOCOL implementation (if <<
2276 to the kernel proper. In addition, <<
2277 location of the kernel Image as wel <<
2278 3108
2279 If unsure, say N. !! 3109 config ARCH_MMAP_RND_BITS_MAX
>> 3110 default 18 if 64BIT
>> 3111 default 15
2280 3112
2281 config RANDOMIZE_MODULE_REGION_FULL !! 3113 config ARCH_MMAP_RND_COMPAT_BITS_MIN
2282 bool "Randomize the module region ove !! 3114 default 8
2283 depends on RANDOMIZE_BASE <<
2284 default y <<
2285 help <<
2286 Randomizes the location of the modu <<
2287 covering the core kernel. This way, <<
2288 to leak information about the locat <<
2289 but it does imply that function cal <<
2290 kernel will need to be resolved via <<
2291 <<
2292 When this option is not set, the mo <<
2293 a limited range that contains the [ <<
2294 core kernel, so branch relocations <<
2295 the region is exhausted. In this pa <<
2296 exhaustion, modules might be able t <<
2297 3115
2298 config CC_HAVE_STACKPROTECTOR_SYSREG !! 3116 config ARCH_MMAP_RND_COMPAT_BITS_MAX
2299 def_bool $(cc-option,-mstack-protecto !! 3117 default 15
2300 3118
2301 config STACKPROTECTOR_PER_TASK !! 3119 config I8253
2302 def_bool y !! 3120 bool
2303 depends on STACKPROTECTOR && CC_HAVE_ !! 3121 select CLKSRC_I8253
>> 3122 select CLKEVT_I8253
>> 3123 select MIPS_EXTERNAL_TIMER
2304 3124
2305 config UNWIND_PATCH_PAC_INTO_SCS !! 3125 config ZONE_DMA
2306 bool "Enable shadow call stack dynami !! 3126 bool
2307 # needs Clang with https://github.com <<
2308 depends on CC_IS_CLANG && CLANG_VERSI <<
2309 depends on ARM64_PTR_AUTH_KERNEL && C <<
2310 depends on SHADOW_CALL_STACK <<
2311 select UNWIND_TABLES <<
2312 select DYNAMIC_SCS <<
2313 <<
2314 config ARM64_CONTPTE <<
2315 bool "Contiguous PTE mappings for use <<
2316 depends on TRANSPARENT_HUGEPAGE <<
2317 default y <<
2318 help <<
2319 When enabled, user mappings are con <<
2320 bit, for any mappings that meet the <<
2321 This reduces TLB pressure and impro <<
2322 <<
2323 endmenu # "Kernel Features" <<
2324 <<
2325 menu "Boot options" <<
2326 <<
2327 config ARM64_ACPI_PARKING_PROTOCOL <<
2328 bool "Enable support for the ARM64 AC <<
2329 depends on ACPI <<
2330 help <<
2331 Enable support for the ARM64 ACPI p <<
2332 the kernel will not allow booting t <<
2333 protocol even if the corresponding <<
2334 MADT table. <<
2335 <<
2336 config CMDLINE <<
2337 string "Default kernel command string <<
2338 default "" <<
2339 help <<
2340 Provide a set of default command-li <<
2341 entering them here. As a minimum, y <<
2342 root device (e.g. root=/dev/nfs). <<
2343 3127
2344 choice !! 3128 config ZONE_DMA32
2345 prompt "Kernel command line type" !! 3129 bool
2346 depends on CMDLINE != "" <<
2347 default CMDLINE_FROM_BOOTLOADER <<
2348 help <<
2349 Choose how the kernel will handle t <<
2350 command line string. <<
2351 <<
2352 config CMDLINE_FROM_BOOTLOADER <<
2353 bool "Use bootloader kernel arguments <<
2354 help <<
2355 Uses the command-line options passe <<
2356 the boot loader doesn't provide any <<
2357 string provided in CMDLINE will be <<
2358 <<
2359 config CMDLINE_FORCE <<
2360 bool "Always use the default kernel c <<
2361 help <<
2362 Always use the default kernel comma <<
2363 loader passes other arguments to th <<
2364 This is useful if you cannot or don <<
2365 command-line options your boot load <<
2366 3130
2367 endchoice !! 3131 endmenu
2368 3132
2369 config EFI_STUB !! 3133 config TRAD_SIGNALS
2370 bool 3134 bool
2371 3135
2372 config EFI !! 3136 config MIPS32_COMPAT
2373 bool "UEFI runtime support" !! 3137 bool
2374 depends on OF && !CPU_BIG_ENDIAN <<
2375 depends on KERNEL_MODE_NEON <<
2376 select ARCH_SUPPORTS_ACPI <<
2377 select LIBFDT <<
2378 select UCS2_STRING <<
2379 select EFI_PARAMS_FROM_FDT <<
2380 select EFI_RUNTIME_WRAPPERS <<
2381 select EFI_STUB <<
2382 select EFI_GENERIC_STUB <<
2383 imply IMA_SECURE_AND_OR_TRUSTED_BOOT <<
2384 default y <<
2385 help <<
2386 This option provides support for ru <<
2387 by UEFI firmware (such as non-volat <<
2388 clock, and platform reset). A UEFI <<
2389 allow the kernel to be booted as an <<
2390 is only useful on systems that have <<
2391 3138
2392 config COMPRESSED_INSTALL !! 3139 config COMPAT
2393 bool "Install compressed image by def !! 3140 bool
2394 help <<
2395 This makes the regular "make instal <<
2396 image we built, not the legacy unco <<
2397 3141
2398 You can check that a compressed ima !! 3142 config SYSVIPC_COMPAT
2399 "make zinstall" first, and verifyin !! 3143 bool
2400 in your environment before making " <<
2401 you. <<
2402 3144
2403 config DMI !! 3145 config MIPS32_O32
2404 bool "Enable support for SMBIOS (DMI) !! 3146 bool "Kernel support for o32 binaries"
2405 depends on EFI !! 3147 depends on 64BIT
2406 default y !! 3148 select ARCH_WANT_OLD_COMPAT_IPC
2407 help !! 3149 select COMPAT
2408 This enables SMBIOS/DMI feature for !! 3150 select MIPS32_COMPAT
>> 3151 select SYSVIPC_COMPAT if SYSVIPC
>> 3152 help
>> 3153 Select this option if you want to run o32 binaries. These are pure
>> 3154 32-bit binaries as used by the 32-bit Linux/MIPS port. Most of
>> 3155 existing binaries are in this format.
2409 3156
2410 This option is only useful on syste !! 3157 If unsure, say Y.
2411 However, even with this option, the <<
2412 continue to boot on existing non-UE <<
2413 3158
2414 endmenu # "Boot options" !! 3159 config MIPS32_N32
>> 3160 bool "Kernel support for n32 binaries"
>> 3161 depends on 64BIT
>> 3162 select ARCH_WANT_COMPAT_IPC_PARSE_VERSION
>> 3163 select COMPAT
>> 3164 select MIPS32_COMPAT
>> 3165 select SYSVIPC_COMPAT if SYSVIPC
>> 3166 help
>> 3167 Select this option if you want to run n32 binaries. These are
>> 3168 64-bit binaries using 32-bit quantities for addressing and certain
>> 3169 data that would normally be 64-bit. They are used in special
>> 3170 cases.
2415 3171
2416 menu "Power management options" !! 3172 If unsure, say N.
2417 3173
2418 source "kernel/power/Kconfig" !! 3174 config BINFMT_ELF32
>> 3175 bool
>> 3176 default y if MIPS32_O32 || MIPS32_N32
>> 3177 select ELFCORE
2419 3178
2420 config ARCH_HIBERNATION_POSSIBLE !! 3179 menu "Power management options"
2421 def_bool y <<
2422 depends on CPU_PM <<
2423 3180
2424 config ARCH_HIBERNATION_HEADER !! 3181 config ARCH_HIBERNATION_POSSIBLE
2425 def_bool y 3182 def_bool y
2426 depends on HIBERNATION !! 3183 depends on SYS_SUPPORTS_HOTPLUG_CPU || !SMP
2427 3184
2428 config ARCH_SUSPEND_POSSIBLE 3185 config ARCH_SUSPEND_POSSIBLE
2429 def_bool y 3186 def_bool y
>> 3187 depends on SYS_SUPPORTS_HOTPLUG_CPU || !SMP
2430 3188
2431 endmenu # "Power management options" !! 3189 source "kernel/power/Kconfig"
2432 3190
2433 menu "CPU Power Management" !! 3191 endmenu
2434 3192
2435 source "drivers/cpuidle/Kconfig" !! 3193 config MIPS_EXTERNAL_TIMER
>> 3194 bool
2436 3195
>> 3196 menu "CPU Power Management"
>> 3197
>> 3198 if CPU_SUPPORTS_CPUFREQ && MIPS_EXTERNAL_TIMER
2437 source "drivers/cpufreq/Kconfig" 3199 source "drivers/cpufreq/Kconfig"
>> 3200 endif
2438 3201
2439 endmenu # "CPU Power Management" !! 3202 source "drivers/cpuidle/Kconfig"
2440 3203
2441 source "drivers/acpi/Kconfig" !! 3204 endmenu
2442 3205
2443 source "arch/arm64/kvm/Kconfig" !! 3206 source "drivers/firmware/Kconfig"
2444 3207
>> 3208 source "arch/mips/kvm/Kconfig"
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