1 # SPDX-License-Identifier: GPL-2.0-only !! 1 # SPDX-License-Identifier: GPL-2.0
2 config ARM64 !! 2 config MIPS
3 def_bool y !! 3 bool
4 select ACPI_APMT if ACPI !! 4 default y
5 select ACPI_CCA_REQUIRED if ACPI !! 5 select ARCH_32BIT_OFF_T if !64BIT
6 select ACPI_GENERIC_GSI if ACPI !! 6 select ARCH_BINFMT_ELF_STATE if MIPS_FP_SUPPORT
7 select ACPI_GTDT if ACPI !! 7 select ARCH_CLOCKSOURCE_DATA
8 select ACPI_HOTPLUG_CPU if ACPI_PROCES <<
9 select ACPI_IORT if ACPI <<
10 select ACPI_REDUCED_HARDWARE_ONLY if A <<
11 select ACPI_MCFG if (ACPI && PCI) <<
12 select ACPI_SPCR_TABLE if ACPI <<
13 select ACPI_PPTT if ACPI <<
14 select ARCH_HAS_DEBUG_WX <<
15 select ARCH_BINFMT_ELF_EXTRA_PHDRS <<
16 select ARCH_BINFMT_ELF_STATE <<
17 select ARCH_CORRECT_STACKTRACE_ON_KRET <<
18 select ARCH_ENABLE_HUGEPAGE_MIGRATION <<
19 select ARCH_ENABLE_MEMORY_HOTPLUG <<
20 select ARCH_ENABLE_MEMORY_HOTREMOVE <<
21 select ARCH_ENABLE_SPLIT_PMD_PTLOCK if <<
22 select ARCH_ENABLE_THP_MIGRATION if TR <<
23 select ARCH_HAS_CACHE_LINE_SIZE <<
24 select ARCH_HAS_CURRENT_STACK_POINTER <<
25 select ARCH_HAS_DEBUG_VIRTUAL <<
26 select ARCH_HAS_DEBUG_VM_PGTABLE <<
27 select ARCH_HAS_DMA_OPS if XEN <<
28 select ARCH_HAS_DMA_PREP_COHERENT <<
29 select ARCH_HAS_ACPI_TABLE_UPGRADE if <<
30 select ARCH_HAS_FAST_MULTIPLIER <<
31 select ARCH_HAS_FORTIFY_SOURCE 8 select ARCH_HAS_FORTIFY_SOURCE
32 select ARCH_HAS_GCOV_PROFILE_ALL <<
33 select ARCH_HAS_GIGANTIC_PAGE <<
34 select ARCH_HAS_KCOV 9 select ARCH_HAS_KCOV
35 select ARCH_HAS_KERNEL_FPU_SUPPORT if !! 10 select ARCH_HAS_PTE_SPECIAL if !(32BIT && CPU_HAS_RIXI)
36 select ARCH_HAS_KEEPINITRD <<
37 select ARCH_HAS_MEMBARRIER_SYNC_CORE <<
38 select ARCH_HAS_MEM_ENCRYPT <<
39 select ARCH_HAS_NMI_SAFE_THIS_CPU_OPS <<
40 select ARCH_HAS_NON_OVERLAPPING_ADDRES <<
41 select ARCH_HAS_PTE_DEVMAP <<
42 select ARCH_HAS_PTE_SPECIAL <<
43 select ARCH_HAS_HW_PTE_YOUNG <<
44 select ARCH_HAS_SETUP_DMA_OPS <<
45 select ARCH_HAS_SET_DIRECT_MAP <<
46 select ARCH_HAS_SET_MEMORY <<
47 select ARCH_STACKWALK <<
48 select ARCH_HAS_STRICT_KERNEL_RWX <<
49 select ARCH_HAS_STRICT_MODULE_RWX <<
50 select ARCH_HAS_SYNC_DMA_FOR_DEVICE <<
51 select ARCH_HAS_SYNC_DMA_FOR_CPU <<
52 select ARCH_HAS_SYSCALL_WRAPPER <<
53 select ARCH_HAS_TICK_BROADCAST if GENE 11 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
54 select ARCH_HAS_ZONE_DMA_SET if EXPERT !! 12 select ARCH_HAS_UBSAN_SANITIZE_ALL
55 select ARCH_HAVE_ELF_PROT !! 13 select ARCH_SUPPORTS_UPROBES
56 select ARCH_HAVE_NMI_SAFE_CMPXCHG !! 14 select ARCH_USE_BUILTIN_BSWAP
57 select ARCH_HAVE_TRACE_MMIO_ACCESS !! 15 select ARCH_USE_CMPXCHG_LOCKREF if 64BIT
58 select ARCH_INLINE_READ_LOCK if !PREEM <<
59 select ARCH_INLINE_READ_LOCK_BH if !PR <<
60 select ARCH_INLINE_READ_LOCK_IRQ if !P <<
61 select ARCH_INLINE_READ_LOCK_IRQSAVE i <<
62 select ARCH_INLINE_READ_UNLOCK if !PRE <<
63 select ARCH_INLINE_READ_UNLOCK_BH if ! <<
64 select ARCH_INLINE_READ_UNLOCK_IRQ if <<
65 select ARCH_INLINE_READ_UNLOCK_IRQREST <<
66 select ARCH_INLINE_WRITE_LOCK if !PREE <<
67 select ARCH_INLINE_WRITE_LOCK_BH if !P <<
68 select ARCH_INLINE_WRITE_LOCK_IRQ if ! <<
69 select ARCH_INLINE_WRITE_LOCK_IRQSAVE <<
70 select ARCH_INLINE_WRITE_UNLOCK if !PR <<
71 select ARCH_INLINE_WRITE_UNLOCK_BH if <<
72 select ARCH_INLINE_WRITE_UNLOCK_IRQ if <<
73 select ARCH_INLINE_WRITE_UNLOCK_IRQRES <<
74 select ARCH_INLINE_SPIN_TRYLOCK if !PR <<
75 select ARCH_INLINE_SPIN_TRYLOCK_BH if <<
76 select ARCH_INLINE_SPIN_LOCK if !PREEM <<
77 select ARCH_INLINE_SPIN_LOCK_BH if !PR <<
78 select ARCH_INLINE_SPIN_LOCK_IRQ if !P <<
79 select ARCH_INLINE_SPIN_LOCK_IRQSAVE i <<
80 select ARCH_INLINE_SPIN_UNLOCK if !PRE <<
81 select ARCH_INLINE_SPIN_UNLOCK_BH if ! <<
82 select ARCH_INLINE_SPIN_UNLOCK_IRQ if <<
83 select ARCH_INLINE_SPIN_UNLOCK_IRQREST <<
84 select ARCH_KEEP_MEMBLOCK <<
85 select ARCH_MHP_MEMMAP_ON_MEMORY_ENABL <<
86 select ARCH_USE_CMPXCHG_LOCKREF <<
87 select ARCH_USE_GNU_PROPERTY <<
88 select ARCH_USE_MEMTEST <<
89 select ARCH_USE_QUEUED_RWLOCKS 16 select ARCH_USE_QUEUED_RWLOCKS
90 select ARCH_USE_QUEUED_SPINLOCKS 17 select ARCH_USE_QUEUED_SPINLOCKS
91 select ARCH_USE_SYM_ANNOTATIONS !! 18 select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT if MMU
92 select ARCH_SUPPORTS_DEBUG_PAGEALLOC !! 19 select ARCH_WANT_IPC_PARSE_VERSION
93 select ARCH_SUPPORTS_HUGETLBFS <<
94 select ARCH_SUPPORTS_MEMORY_FAILURE <<
95 select ARCH_SUPPORTS_SHADOW_CALL_STACK <<
96 select ARCH_SUPPORTS_LTO_CLANG if CPU_ <<
97 select ARCH_SUPPORTS_LTO_CLANG_THIN <<
98 select ARCH_SUPPORTS_CFI_CLANG <<
99 select ARCH_SUPPORTS_ATOMIC_RMW <<
100 select ARCH_SUPPORTS_INT128 if CC_HAS_ <<
101 select ARCH_SUPPORTS_NUMA_BALANCING <<
102 select ARCH_SUPPORTS_PAGE_TABLE_CHECK <<
103 select ARCH_SUPPORTS_PER_VMA_LOCK <<
104 select ARCH_SUPPORTS_HUGE_PFNMAP if TR <<
105 select ARCH_SUPPORTS_RT <<
106 select ARCH_WANT_BATCHED_UNMAP_TLB_FLU <<
107 select ARCH_WANT_COMPAT_IPC_PARSE_VERS <<
108 select ARCH_WANT_DEFAULT_BPF_JIT <<
109 select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_ <<
110 select ARCH_WANT_FRAME_POINTERS <<
111 select ARCH_WANT_HUGE_PMD_SHARE if ARM <<
112 select ARCH_WANT_LD_ORPHAN_WARN <<
113 select ARCH_WANTS_EXECMEM_LATE if EXEC <<
114 select ARCH_WANTS_NO_INSTR <<
115 select ARCH_WANTS_THP_SWAP if ARM64_4K <<
116 select ARCH_HAS_UBSAN <<
117 select ARM_AMBA <<
118 select ARM_ARCH_TIMER <<
119 select ARM_GIC <<
120 select AUDIT_ARCH_COMPAT_GENERIC <<
121 select ARM_GIC_V2M if PCI <<
122 select ARM_GIC_V3 <<
123 select ARM_GIC_V3_ITS if PCI <<
124 select ARM_PSCI_FW <<
125 select BUILDTIME_TABLE_SORT 20 select BUILDTIME_TABLE_SORT
126 select CLONE_BACKWARDS 21 select CLONE_BACKWARDS
127 select COMMON_CLK !! 22 select CPU_NO_EFFICIENT_FFS if (TARGET_ISA_REV < 1)
128 select CPU_PM if (SUSPEND || CPU_IDLE) !! 23 select CPU_PM if CPU_IDLE
129 select CPUMASK_OFFSTACK if NR_CPUS > 2 !! 24 select GENERIC_ATOMIC64 if !64BIT
130 select CRC32 !! 25 select GENERIC_CLOCKEVENTS
131 select DCACHE_WORD_ACCESS !! 26 select GENERIC_CMOS_UPDATE
132 select DYNAMIC_FTRACE if FUNCTION_TRAC <<
133 select DMA_BOUNCE_UNALIGNED_KMALLOC <<
134 select DMA_DIRECT_REMAP <<
135 select EDAC_SUPPORT <<
136 select FRAME_POINTER <<
137 select FUNCTION_ALIGNMENT_4B <<
138 select FUNCTION_ALIGNMENT_8B if DYNAMI <<
139 select GENERIC_ALLOCATOR <<
140 select GENERIC_ARCH_TOPOLOGY <<
141 select GENERIC_CLOCKEVENTS_BROADCAST <<
142 select GENERIC_CPU_AUTOPROBE 27 select GENERIC_CPU_AUTOPROBE
143 select GENERIC_CPU_DEVICES !! 28 select GENERIC_GETTIMEOFDAY
144 select GENERIC_CPU_VULNERABILITIES !! 29 select GENERIC_IOMAP
145 select GENERIC_EARLY_IOREMAP <<
146 select GENERIC_IDLE_POLL_SETUP <<
147 select GENERIC_IOREMAP <<
148 select GENERIC_IRQ_IPI <<
149 select GENERIC_IRQ_PROBE 30 select GENERIC_IRQ_PROBE
150 select GENERIC_IRQ_SHOW 31 select GENERIC_IRQ_SHOW
151 select GENERIC_IRQ_SHOW_LEVEL !! 32 select GENERIC_ISA_DMA if EISA
152 select GENERIC_LIB_DEVMEM_IS_ALLOWED !! 33 select GENERIC_LIB_ASHLDI3
153 select GENERIC_PCI_IOMAP !! 34 select GENERIC_LIB_ASHRDI3
154 select GENERIC_PTDUMP !! 35 select GENERIC_LIB_CMPDI2
155 select GENERIC_SCHED_CLOCK !! 36 select GENERIC_LIB_LSHRDI3
>> 37 select GENERIC_LIB_UCMPDI2
>> 38 select GENERIC_SCHED_CLOCK if !CAVIUM_OCTEON_SOC
156 select GENERIC_SMP_IDLE_THREAD 39 select GENERIC_SMP_IDLE_THREAD
157 select GENERIC_TIME_VSYSCALL 40 select GENERIC_TIME_VSYSCALL
158 select GENERIC_GETTIMEOFDAY !! 41 select GUP_GET_PTE_LOW_HIGH if CPU_MIPS32 && PHYS_ADDR_T_64BIT
159 select GENERIC_VDSO_TIME_NS !! 42 select HANDLE_DOMAIN_IRQ
160 select HARDIRQS_SW_RESEND <<
161 select HAS_IOPORT <<
162 select HAVE_MOVE_PMD <<
163 select HAVE_MOVE_PUD <<
164 select HAVE_PCI <<
165 select HAVE_ACPI_APEI if (ACPI && EFI) <<
166 select HAVE_ALIGNED_STRUCT_PAGE <<
167 select HAVE_ARCH_AUDITSYSCALL <<
168 select HAVE_ARCH_BITREVERSE <<
169 select HAVE_ARCH_COMPILER_H 43 select HAVE_ARCH_COMPILER_H
170 select HAVE_ARCH_HUGE_VMALLOC <<
171 select HAVE_ARCH_HUGE_VMAP <<
172 select HAVE_ARCH_JUMP_LABEL 44 select HAVE_ARCH_JUMP_LABEL
173 select HAVE_ARCH_JUMP_LABEL_RELATIVE <<
174 select HAVE_ARCH_KASAN <<
175 select HAVE_ARCH_KASAN_VMALLOC <<
176 select HAVE_ARCH_KASAN_SW_TAGS <<
177 select HAVE_ARCH_KASAN_HW_TAGS if ARM6 <<
178 # Some instrumentation may be unsound, <<
179 select HAVE_ARCH_KCSAN if EXPERT <<
180 select HAVE_ARCH_KFENCE <<
181 select HAVE_ARCH_KGDB 45 select HAVE_ARCH_KGDB
182 select HAVE_ARCH_MMAP_RND_BITS !! 46 select HAVE_ARCH_MMAP_RND_BITS if MMU
183 select HAVE_ARCH_MMAP_RND_COMPAT_BITS !! 47 select HAVE_ARCH_MMAP_RND_COMPAT_BITS if MMU && COMPAT
184 select HAVE_ARCH_PREL32_RELOCATIONS <<
185 select HAVE_ARCH_RANDOMIZE_KSTACK_OFFS <<
186 select HAVE_ARCH_SECCOMP_FILTER 48 select HAVE_ARCH_SECCOMP_FILTER
187 select HAVE_ARCH_STACKLEAK <<
188 select HAVE_ARCH_THREAD_STRUCT_WHITELI <<
189 select HAVE_ARCH_TRACEHOOK 49 select HAVE_ARCH_TRACEHOOK
190 select HAVE_ARCH_TRANSPARENT_HUGEPAGE !! 50 select HAVE_ARCH_TRANSPARENT_HUGEPAGE if CPU_SUPPORTS_HUGEPAGES
191 select HAVE_ARCH_VMAP_STACK <<
192 select HAVE_ARM_SMCCC <<
193 select HAVE_ASM_MODVERSIONS 51 select HAVE_ASM_MODVERSIONS
194 select HAVE_EBPF_JIT !! 52 select HAVE_CBPF_JIT if !64BIT && !CPU_MICROMIPS
>> 53 select HAVE_CONTEXT_TRACKING
>> 54 select HAVE_COPY_THREAD_TLS
195 select HAVE_C_RECORDMCOUNT 55 select HAVE_C_RECORDMCOUNT
196 select HAVE_CMPXCHG_DOUBLE <<
197 select HAVE_CMPXCHG_LOCAL <<
198 select HAVE_CONTEXT_TRACKING_USER <<
199 select HAVE_DEBUG_KMEMLEAK 56 select HAVE_DEBUG_KMEMLEAK
>> 57 select HAVE_DEBUG_STACKOVERFLOW
200 select HAVE_DMA_CONTIGUOUS 58 select HAVE_DMA_CONTIGUOUS
201 select HAVE_DYNAMIC_FTRACE 59 select HAVE_DYNAMIC_FTRACE
202 select HAVE_DYNAMIC_FTRACE_WITH_ARGS \ !! 60 select HAVE_EBPF_JIT if 64BIT && !CPU_MICROMIPS && TARGET_ISA_REV >= 2
203 if (GCC_SUPPORTS_DYNAMIC_FTRAC !! 61 select HAVE_EXIT_THREAD
204 CLANG_SUPPORTS_DYNAMIC_FTR !! 62 select HAVE_FAST_GUP
205 select HAVE_DYNAMIC_FTRACE_WITH_DIRECT <<
206 if DYNAMIC_FTRACE_WITH_ARGS && <<
207 select HAVE_DYNAMIC_FTRACE_WITH_CALL_O <<
208 if (DYNAMIC_FTRACE_WITH_ARGS & <<
209 (CC_IS_CLANG || !CC_OPTIMI <<
210 select FTRACE_MCOUNT_USE_PATCHABLE_FUN <<
211 if DYNAMIC_FTRACE_WITH_ARGS <<
212 select HAVE_SAMPLE_FTRACE_DIRECT <<
213 select HAVE_SAMPLE_FTRACE_DIRECT_MULTI <<
214 select HAVE_EFFICIENT_UNALIGNED_ACCESS <<
215 select HAVE_GUP_FAST <<
216 select HAVE_FTRACE_MCOUNT_RECORD 63 select HAVE_FTRACE_MCOUNT_RECORD
217 select HAVE_FUNCTION_TRACER <<
218 select HAVE_FUNCTION_ERROR_INJECTION <<
219 select HAVE_FUNCTION_GRAPH_TRACER 64 select HAVE_FUNCTION_GRAPH_TRACER
220 select HAVE_FUNCTION_GRAPH_RETVAL !! 65 select HAVE_FUNCTION_TRACER
221 select HAVE_GCC_PLUGINS 66 select HAVE_GCC_PLUGINS
222 select HAVE_HARDLOCKUP_DETECTOR_PERF i !! 67 select HAVE_GENERIC_VDSO
223 HW_PERF_EVENTS && HAVE_PERF_EV !! 68 select HAVE_IDE
224 select HAVE_HW_BREAKPOINT if PERF_EVEN <<
225 select HAVE_IOREMAP_PROT 69 select HAVE_IOREMAP_PROT
>> 70 select HAVE_IRQ_EXIT_ON_IRQ_STACK
226 select HAVE_IRQ_TIME_ACCOUNTING 71 select HAVE_IRQ_TIME_ACCOUNTING
>> 72 select HAVE_KPROBES
>> 73 select HAVE_KRETPROBES
>> 74 select HAVE_LD_DEAD_CODE_DATA_ELIMINATION
>> 75 select HAVE_MEMBLOCK_NODE_MAP
227 select HAVE_MOD_ARCH_SPECIFIC 76 select HAVE_MOD_ARCH_SPECIFIC
228 select HAVE_NMI 77 select HAVE_NMI
>> 78 select HAVE_OPROFILE
229 select HAVE_PERF_EVENTS 79 select HAVE_PERF_EVENTS
230 select HAVE_PERF_EVENTS_NMI if ARM64_P <<
231 select HAVE_PERF_REGS <<
232 select HAVE_PERF_USER_STACK_DUMP <<
233 select HAVE_PREEMPT_DYNAMIC_KEY <<
234 select HAVE_REGS_AND_STACK_ACCESS_API 80 select HAVE_REGS_AND_STACK_ACCESS_API
235 select HAVE_POSIX_CPU_TIMERS_TASK_WORK <<
236 select HAVE_FUNCTION_ARG_ACCESS_API <<
237 select MMU_GATHER_RCU_TABLE_FREE <<
238 select HAVE_RSEQ 81 select HAVE_RSEQ
239 select HAVE_RUST if RUSTC_SUPPORTS_ARM !! 82 select HAVE_SPARSE_SYSCALL_NR
240 select HAVE_STACKPROTECTOR 83 select HAVE_STACKPROTECTOR
241 select HAVE_SYSCALL_TRACEPOINTS 84 select HAVE_SYSCALL_TRACEPOINTS
242 select HAVE_KPROBES !! 85 select HAVE_VIRT_CPU_ACCOUNTING_GEN if 64BIT || !SMP
243 select HAVE_KRETPROBES <<
244 select HAVE_GENERIC_VDSO <<
245 select HOTPLUG_CORE_SYNC_DEAD if HOTPL <<
246 select IRQ_DOMAIN <<
247 select IRQ_FORCED_THREADING 86 select IRQ_FORCED_THREADING
248 select KASAN_VMALLOC if KASAN !! 87 select ISA if EISA
249 select LOCK_MM_AND_FIND_VMA !! 88 select MODULES_USE_ELF_REL if MODULES
250 select MODULES_USE_ELF_RELA !! 89 select MODULES_USE_ELF_RELA if MODULES && 64BIT
251 select NEED_DMA_MAP_STATE !! 90 select PERF_USE_VMALLOC
252 select NEED_SG_DMA_LENGTH !! 91 select RTC_LIB
253 select OF <<
254 select OF_EARLY_FLATTREE <<
255 select PCI_DOMAINS_GENERIC if PCI <<
256 select PCI_ECAM if (ACPI && PCI) <<
257 select PCI_SYSCALL if PCI <<
258 select POWER_RESET <<
259 select POWER_SUPPLY <<
260 select SPARSE_IRQ <<
261 select SWIOTLB <<
262 select SYSCTL_EXCEPTION_TRACE 92 select SYSCTL_EXCEPTION_TRACE
263 select THREAD_INFO_IN_TASK !! 93 select VIRT_TO_BUS
264 select HAVE_ARCH_USERFAULTFD_MINOR if <<
265 select HAVE_ARCH_USERFAULTFD_WP if USE <<
266 select TRACE_IRQFLAGS_SUPPORT <<
267 select TRACE_IRQFLAGS_NMI_SUPPORT <<
268 select HAVE_SOFTIRQ_ON_OWN_STACK <<
269 select USER_STACKTRACE_SUPPORT <<
270 select VDSO_GETRANDOM <<
271 help <<
272 ARM 64-bit (AArch64) Linux support. <<
273 94
274 config RUSTC_SUPPORTS_ARM64 !! 95 menu "Machine selection"
275 def_bool y <<
276 depends on CPU_LITTLE_ENDIAN <<
277 # Shadow call stack is only supported <<
278 # <<
279 # When using the UNWIND_PATCH_PAC_INTO <<
280 # required due to use of the -Zfixed-x <<
281 # <<
282 # Otherwise, rustc version 1.82+ is re <<
283 # -Zsanitizer=shadow-call-stack flag. <<
284 depends on !SHADOW_CALL_STACK || RUSTC <<
285 <<
286 config CLANG_SUPPORTS_DYNAMIC_FTRACE_WITH_ARGS <<
287 def_bool CC_IS_CLANG <<
288 # https://github.com/ClangBuiltLinux/l <<
289 depends on AS_IS_GNU || (AS_IS_LLVM && <<
290 <<
291 config GCC_SUPPORTS_DYNAMIC_FTRACE_WITH_ARGS <<
292 def_bool CC_IS_GCC <<
293 depends on $(cc-option,-fpatchable-fun <<
294 96
295 config 64BIT !! 97 choice
296 def_bool y !! 98 prompt "System type"
>> 99 default MIPS_GENERIC
297 100
298 config MMU !! 101 config MIPS_GENERIC
299 def_bool y !! 102 bool "Generic board-agnostic MIPS kernel"
>> 103 select BOOT_RAW
>> 104 select BUILTIN_DTB
>> 105 select CEVT_R4K
>> 106 select CLKSRC_MIPS_GIC
>> 107 select COMMON_CLK
>> 108 select CPU_MIPSR2_IRQ_EI
>> 109 select CPU_MIPSR2_IRQ_VI
>> 110 select CSRC_R4K
>> 111 select DMA_PERDEV_COHERENT
>> 112 select HAVE_PCI
>> 113 select IRQ_MIPS_CPU
>> 114 select MIPS_AUTO_PFN_OFFSET
>> 115 select MIPS_CPU_SCACHE
>> 116 select MIPS_GIC
>> 117 select MIPS_L1_CACHE_SHIFT_7
>> 118 select NO_EXCEPT_FILL
>> 119 select PCI_DRIVERS_GENERIC
>> 120 select SMP_UP if SMP
>> 121 select SWAP_IO_SPACE
>> 122 select SYS_HAS_CPU_MIPS32_R1
>> 123 select SYS_HAS_CPU_MIPS32_R2
>> 124 select SYS_HAS_CPU_MIPS32_R6
>> 125 select SYS_HAS_CPU_MIPS64_R1
>> 126 select SYS_HAS_CPU_MIPS64_R2
>> 127 select SYS_HAS_CPU_MIPS64_R6
>> 128 select SYS_SUPPORTS_32BIT_KERNEL
>> 129 select SYS_SUPPORTS_64BIT_KERNEL
>> 130 select SYS_SUPPORTS_BIG_ENDIAN
>> 131 select SYS_SUPPORTS_HIGHMEM
>> 132 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 133 select SYS_SUPPORTS_MICROMIPS
>> 134 select SYS_SUPPORTS_MIPS16
>> 135 select SYS_SUPPORTS_MIPS_CPS
>> 136 select SYS_SUPPORTS_MULTITHREADING
>> 137 select SYS_SUPPORTS_RELOCATABLE
>> 138 select SYS_SUPPORTS_SMARTMIPS
>> 139 select UHI_BOOT
>> 140 select USB_EHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
>> 141 select USB_EHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 142 select USB_OHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
>> 143 select USB_OHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 144 select USB_UHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
>> 145 select USB_UHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 146 select USE_OF
>> 147 help
>> 148 Select this to build a kernel which aims to support multiple boards,
>> 149 generally using a flattened device tree passed from the bootloader
>> 150 using the boot protocol defined in the UHI (Unified Hosting
>> 151 Interface) specification.
>> 152
>> 153 config MIPS_ALCHEMY
>> 154 bool "Alchemy processor based machines"
>> 155 select PHYS_ADDR_T_64BIT
>> 156 select CEVT_R4K
>> 157 select CSRC_R4K
>> 158 select IRQ_MIPS_CPU
>> 159 select DMA_MAYBE_COHERENT # Au1000,1500,1100 aren't, rest is
>> 160 select SYS_HAS_CPU_MIPS32_R1
>> 161 select SYS_SUPPORTS_32BIT_KERNEL
>> 162 select SYS_SUPPORTS_APM_EMULATION
>> 163 select GPIOLIB
>> 164 select SYS_SUPPORTS_ZBOOT
>> 165 select COMMON_CLK
300 166
301 config ARM64_CONT_PTE_SHIFT !! 167 config AR7
302 int !! 168 bool "Texas Instruments AR7"
303 default 5 if PAGE_SIZE_64KB !! 169 select BOOT_ELF32
304 default 7 if PAGE_SIZE_16KB !! 170 select DMA_NONCOHERENT
305 default 4 !! 171 select CEVT_R4K
>> 172 select CSRC_R4K
>> 173 select IRQ_MIPS_CPU
>> 174 select NO_EXCEPT_FILL
>> 175 select SWAP_IO_SPACE
>> 176 select SYS_HAS_CPU_MIPS32_R1
>> 177 select SYS_HAS_EARLY_PRINTK
>> 178 select SYS_SUPPORTS_32BIT_KERNEL
>> 179 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 180 select SYS_SUPPORTS_MIPS16
>> 181 select SYS_SUPPORTS_ZBOOT_UART16550
>> 182 select GPIOLIB
>> 183 select VLYNQ
>> 184 select HAVE_CLK
>> 185 help
>> 186 Support for the Texas Instruments AR7 System-on-a-Chip
>> 187 family: TNETD7100, 7200 and 7300.
>> 188
>> 189 config ATH25
>> 190 bool "Atheros AR231x/AR531x SoC support"
>> 191 select CEVT_R4K
>> 192 select CSRC_R4K
>> 193 select DMA_NONCOHERENT
>> 194 select IRQ_MIPS_CPU
>> 195 select IRQ_DOMAIN
>> 196 select SYS_HAS_CPU_MIPS32_R1
>> 197 select SYS_SUPPORTS_BIG_ENDIAN
>> 198 select SYS_SUPPORTS_32BIT_KERNEL
>> 199 select SYS_HAS_EARLY_PRINTK
>> 200 help
>> 201 Support for Atheros AR231x and Atheros AR531x based boards
>> 202
>> 203 config ATH79
>> 204 bool "Atheros AR71XX/AR724X/AR913X based boards"
>> 205 select ARCH_HAS_RESET_CONTROLLER
>> 206 select BOOT_RAW
>> 207 select CEVT_R4K
>> 208 select CSRC_R4K
>> 209 select DMA_NONCOHERENT
>> 210 select GPIOLIB
>> 211 select PINCTRL
>> 212 select HAVE_CLK
>> 213 select COMMON_CLK
>> 214 select CLKDEV_LOOKUP
>> 215 select IRQ_MIPS_CPU
>> 216 select SYS_HAS_CPU_MIPS32_R2
>> 217 select SYS_HAS_EARLY_PRINTK
>> 218 select SYS_SUPPORTS_32BIT_KERNEL
>> 219 select SYS_SUPPORTS_BIG_ENDIAN
>> 220 select SYS_SUPPORTS_MIPS16
>> 221 select SYS_SUPPORTS_ZBOOT_UART_PROM
>> 222 select USE_OF
>> 223 select USB_EHCI_ROOT_HUB_TT if USB_EHCI_HCD_PLATFORM
>> 224 help
>> 225 Support for the Atheros AR71XX/AR724X/AR913X SoCs.
>> 226
>> 227 config BMIPS_GENERIC
>> 228 bool "Broadcom Generic BMIPS kernel"
>> 229 select ARCH_HAS_SYNC_DMA_FOR_CPU_ALL
>> 230 select ARCH_HAS_PHYS_TO_DMA
>> 231 select BOOT_RAW
>> 232 select NO_EXCEPT_FILL
>> 233 select USE_OF
>> 234 select CEVT_R4K
>> 235 select CSRC_R4K
>> 236 select SYNC_R4K
>> 237 select COMMON_CLK
>> 238 select BCM6345_L1_IRQ
>> 239 select BCM7038_L1_IRQ
>> 240 select BCM7120_L2_IRQ
>> 241 select BRCMSTB_L2_IRQ
>> 242 select IRQ_MIPS_CPU
>> 243 select DMA_NONCOHERENT
>> 244 select SYS_SUPPORTS_32BIT_KERNEL
>> 245 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 246 select SYS_SUPPORTS_BIG_ENDIAN
>> 247 select SYS_SUPPORTS_HIGHMEM
>> 248 select SYS_HAS_CPU_BMIPS32_3300
>> 249 select SYS_HAS_CPU_BMIPS4350
>> 250 select SYS_HAS_CPU_BMIPS4380
>> 251 select SYS_HAS_CPU_BMIPS5000
>> 252 select SWAP_IO_SPACE
>> 253 select USB_EHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
>> 254 select USB_EHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 255 select USB_OHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
>> 256 select USB_OHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 257 select HARDIRQS_SW_RESEND
>> 258 help
>> 259 Build a generic DT-based kernel image that boots on select
>> 260 BCM33xx cable modem chips, BCM63xx DSL chips, and BCM7xxx set-top
>> 261 box chips. Note that CONFIG_CPU_BIG_ENDIAN/CONFIG_CPU_LITTLE_ENDIAN
>> 262 must be set appropriately for your board.
>> 263
>> 264 config BCM47XX
>> 265 bool "Broadcom BCM47XX based boards"
>> 266 select BOOT_RAW
>> 267 select CEVT_R4K
>> 268 select CSRC_R4K
>> 269 select DMA_NONCOHERENT
>> 270 select HAVE_PCI
>> 271 select IRQ_MIPS_CPU
>> 272 select SYS_HAS_CPU_MIPS32_R1
>> 273 select NO_EXCEPT_FILL
>> 274 select SYS_SUPPORTS_32BIT_KERNEL
>> 275 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 276 select SYS_SUPPORTS_MIPS16
>> 277 select SYS_SUPPORTS_ZBOOT
>> 278 select SYS_HAS_EARLY_PRINTK
>> 279 select USE_GENERIC_EARLY_PRINTK_8250
>> 280 select GPIOLIB
>> 281 select LEDS_GPIO_REGISTER
>> 282 select BCM47XX_NVRAM
>> 283 select BCM47XX_SPROM
>> 284 select BCM47XX_SSB if !BCM47XX_BCMA
>> 285 help
>> 286 Support for BCM47XX based boards
>> 287
>> 288 config BCM63XX
>> 289 bool "Broadcom BCM63XX based boards"
>> 290 select BOOT_RAW
>> 291 select CEVT_R4K
>> 292 select CSRC_R4K
>> 293 select SYNC_R4K
>> 294 select DMA_NONCOHERENT
>> 295 select IRQ_MIPS_CPU
>> 296 select SYS_SUPPORTS_32BIT_KERNEL
>> 297 select SYS_SUPPORTS_BIG_ENDIAN
>> 298 select SYS_HAS_EARLY_PRINTK
>> 299 select SWAP_IO_SPACE
>> 300 select GPIOLIB
>> 301 select HAVE_CLK
>> 302 select MIPS_L1_CACHE_SHIFT_4
>> 303 select CLKDEV_LOOKUP
>> 304 help
>> 305 Support for BCM63XX based boards
>> 306
>> 307 config MIPS_COBALT
>> 308 bool "Cobalt Server"
>> 309 select CEVT_R4K
>> 310 select CSRC_R4K
>> 311 select CEVT_GT641XX
>> 312 select DMA_NONCOHERENT
>> 313 select FORCE_PCI
>> 314 select I8253
>> 315 select I8259
>> 316 select IRQ_MIPS_CPU
>> 317 select IRQ_GT641XX
>> 318 select PCI_GT64XXX_PCI0
>> 319 select SYS_HAS_CPU_NEVADA
>> 320 select SYS_HAS_EARLY_PRINTK
>> 321 select SYS_SUPPORTS_32BIT_KERNEL
>> 322 select SYS_SUPPORTS_64BIT_KERNEL
>> 323 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 324 select USE_GENERIC_EARLY_PRINTK_8250
>> 325
>> 326 config MACH_DECSTATION
>> 327 bool "DECstations"
>> 328 select BOOT_ELF32
>> 329 select CEVT_DS1287
>> 330 select CEVT_R4K if CPU_R4X00
>> 331 select CSRC_IOASIC
>> 332 select CSRC_R4K if CPU_R4X00
>> 333 select CPU_DADDI_WORKAROUNDS if 64BIT
>> 334 select CPU_R4000_WORKAROUNDS if 64BIT
>> 335 select CPU_R4400_WORKAROUNDS if 64BIT
>> 336 select DMA_NONCOHERENT
>> 337 select NO_IOPORT_MAP
>> 338 select IRQ_MIPS_CPU
>> 339 select SYS_HAS_CPU_R3000
>> 340 select SYS_HAS_CPU_R4X00
>> 341 select SYS_SUPPORTS_32BIT_KERNEL
>> 342 select SYS_SUPPORTS_64BIT_KERNEL
>> 343 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 344 select SYS_SUPPORTS_128HZ
>> 345 select SYS_SUPPORTS_256HZ
>> 346 select SYS_SUPPORTS_1024HZ
>> 347 select MIPS_L1_CACHE_SHIFT_4
>> 348 help
>> 349 This enables support for DEC's MIPS based workstations. For details
>> 350 see the Linux/MIPS FAQ on <http://www.linux-mips.org/> and the
>> 351 DECstation porting pages on <http://decstation.unix-ag.org/>.
>> 352
>> 353 If you have one of the following DECstation Models you definitely
>> 354 want to choose R4xx0 for the CPU Type:
>> 355
>> 356 DECstation 5000/50
>> 357 DECstation 5000/150
>> 358 DECstation 5000/260
>> 359 DECsystem 5900/260
>> 360
>> 361 otherwise choose R3000.
>> 362
>> 363 config MACH_JAZZ
>> 364 bool "Jazz family of machines"
>> 365 select ARC_MEMORY
>> 366 select ARC_PROMLIB
>> 367 select ARCH_MIGHT_HAVE_PC_PARPORT
>> 368 select ARCH_MIGHT_HAVE_PC_SERIO
>> 369 select FW_ARC
>> 370 select FW_ARC32
>> 371 select ARCH_MAY_HAVE_PC_FDC
>> 372 select CEVT_R4K
>> 373 select CSRC_R4K
>> 374 select DEFAULT_SGI_PARTITION if CPU_BIG_ENDIAN
>> 375 select GENERIC_ISA_DMA
>> 376 select HAVE_PCSPKR_PLATFORM
>> 377 select IRQ_MIPS_CPU
>> 378 select I8253
>> 379 select I8259
>> 380 select ISA
>> 381 select SYS_HAS_CPU_R4X00
>> 382 select SYS_SUPPORTS_32BIT_KERNEL
>> 383 select SYS_SUPPORTS_64BIT_KERNEL
>> 384 select SYS_SUPPORTS_100HZ
>> 385 help
>> 386 This a family of machines based on the MIPS R4030 chipset which was
>> 387 used by several vendors to build RISC/os and Windows NT workstations.
>> 388 Members include the Acer PICA, MIPS Magnum 4000, MIPS Millennium and
>> 389 Olivetti M700-10 workstations.
>> 390
>> 391 config MACH_INGENIC
>> 392 bool "Ingenic SoC based machines"
>> 393 select SYS_SUPPORTS_32BIT_KERNEL
>> 394 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 395 select SYS_SUPPORTS_ZBOOT_UART16550
>> 396 select CPU_SUPPORTS_HUGEPAGES
>> 397 select DMA_NONCOHERENT
>> 398 select IRQ_MIPS_CPU
>> 399 select PINCTRL
>> 400 select GPIOLIB
>> 401 select COMMON_CLK
>> 402 select GENERIC_IRQ_CHIP
>> 403 select BUILTIN_DTB if MIPS_NO_APPENDED_DTB
>> 404 select USE_OF
>> 405
>> 406 config LANTIQ
>> 407 bool "Lantiq based platforms"
>> 408 select DMA_NONCOHERENT
>> 409 select IRQ_MIPS_CPU
>> 410 select CEVT_R4K
>> 411 select CSRC_R4K
>> 412 select SYS_HAS_CPU_MIPS32_R1
>> 413 select SYS_HAS_CPU_MIPS32_R2
>> 414 select SYS_SUPPORTS_BIG_ENDIAN
>> 415 select SYS_SUPPORTS_32BIT_KERNEL
>> 416 select SYS_SUPPORTS_MIPS16
>> 417 select SYS_SUPPORTS_MULTITHREADING
>> 418 select SYS_SUPPORTS_VPE_LOADER
>> 419 select SYS_HAS_EARLY_PRINTK
>> 420 select GPIOLIB
>> 421 select SWAP_IO_SPACE
>> 422 select BOOT_RAW
>> 423 select CLKDEV_LOOKUP
>> 424 select USE_OF
>> 425 select PINCTRL
>> 426 select PINCTRL_LANTIQ
>> 427 select ARCH_HAS_RESET_CONTROLLER
>> 428 select RESET_CONTROLLER
>> 429
>> 430 config LASAT
>> 431 bool "LASAT Networks platforms"
>> 432 select CEVT_R4K
>> 433 select CRC32
>> 434 select CSRC_R4K
>> 435 select DMA_NONCOHERENT
>> 436 select SYS_HAS_EARLY_PRINTK
>> 437 select HAVE_PCI
>> 438 select IRQ_MIPS_CPU
>> 439 select PCI_GT64XXX_PCI0
>> 440 select MIPS_NILE4
>> 441 select R5000_CPU_SCACHE
>> 442 select SYS_HAS_CPU_R5000
>> 443 select SYS_SUPPORTS_32BIT_KERNEL
>> 444 select SYS_SUPPORTS_64BIT_KERNEL if BROKEN
>> 445 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 446
>> 447 config MACH_LOONGSON32
>> 448 bool "Loongson 32-bit family of machines"
>> 449 select SYS_SUPPORTS_ZBOOT
>> 450 help
>> 451 This enables support for the Loongson-1 family of machines.
>> 452
>> 453 Loongson-1 is a family of 32-bit MIPS-compatible SoCs developed by
>> 454 the Institute of Computing Technology (ICT), Chinese Academy of
>> 455 Sciences (CAS).
>> 456
>> 457 config MACH_LOONGSON2EF
>> 458 bool "Loongson-2E/F family of machines"
>> 459 select SYS_SUPPORTS_ZBOOT
>> 460 help
>> 461 This enables the support of early Loongson-2E/F family of machines.
>> 462
>> 463 config MACH_LOONGSON64
>> 464 bool "Loongson 64-bit family of machines"
>> 465 select ARCH_SPARSEMEM_ENABLE
>> 466 select ARCH_MIGHT_HAVE_PC_PARPORT
>> 467 select ARCH_MIGHT_HAVE_PC_SERIO
>> 468 select GENERIC_ISA_DMA_SUPPORT_BROKEN
>> 469 select BOOT_ELF32
>> 470 select BOARD_SCACHE
>> 471 select CSRC_R4K
>> 472 select CEVT_R4K
>> 473 select CPU_HAS_WB
>> 474 select FORCE_PCI
>> 475 select ISA
>> 476 select I8259
>> 477 select IRQ_MIPS_CPU
>> 478 select NR_CPUS_DEFAULT_4
>> 479 select USE_GENERIC_EARLY_PRINTK_8250
>> 480 select SYS_HAS_CPU_LOONGSON64
>> 481 select SYS_HAS_EARLY_PRINTK
>> 482 select SYS_SUPPORTS_SMP
>> 483 select SYS_SUPPORTS_HOTPLUG_CPU
>> 484 select SYS_SUPPORTS_NUMA
>> 485 select SYS_SUPPORTS_64BIT_KERNEL
>> 486 select SYS_SUPPORTS_HIGHMEM
>> 487 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 488 select SYS_SUPPORTS_ZBOOT
>> 489 select LOONGSON_MC146818
>> 490 select ZONE_DMA32
>> 491 select NUMA
>> 492 help
>> 493 This enables the support of Loongson-2/3 family of machines.
>> 494
>> 495 Loongson-2 and Loongson-3 are 64-bit general-purpose processors with
>> 496 GS264/GS464/GS464E/GS464V microarchitecture (except old Loongson-2E
>> 497 and Loongson-2F which will be removed), developed by the Institute
>> 498 of Computing Technology (ICT), Chinese Academy of Sciences (CAS).
>> 499
>> 500 config MACH_PISTACHIO
>> 501 bool "IMG Pistachio SoC based boards"
>> 502 select BOOT_ELF32
>> 503 select BOOT_RAW
>> 504 select CEVT_R4K
>> 505 select CLKSRC_MIPS_GIC
>> 506 select COMMON_CLK
>> 507 select CSRC_R4K
>> 508 select DMA_NONCOHERENT
>> 509 select GPIOLIB
>> 510 select IRQ_MIPS_CPU
>> 511 select MFD_SYSCON
>> 512 select MIPS_CPU_SCACHE
>> 513 select MIPS_GIC
>> 514 select PINCTRL
>> 515 select REGULATOR
>> 516 select SYS_HAS_CPU_MIPS32_R2
>> 517 select SYS_SUPPORTS_32BIT_KERNEL
>> 518 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 519 select SYS_SUPPORTS_MIPS_CPS
>> 520 select SYS_SUPPORTS_MULTITHREADING
>> 521 select SYS_SUPPORTS_RELOCATABLE
>> 522 select SYS_SUPPORTS_ZBOOT
>> 523 select SYS_HAS_EARLY_PRINTK
>> 524 select USE_GENERIC_EARLY_PRINTK_8250
>> 525 select USE_OF
>> 526 help
>> 527 This enables support for the IMG Pistachio SoC platform.
>> 528
>> 529 config MIPS_MALTA
>> 530 bool "MIPS Malta board"
>> 531 select ARCH_MAY_HAVE_PC_FDC
>> 532 select ARCH_MIGHT_HAVE_PC_PARPORT
>> 533 select ARCH_MIGHT_HAVE_PC_SERIO
>> 534 select BOOT_ELF32
>> 535 select BOOT_RAW
>> 536 select BUILTIN_DTB
>> 537 select CEVT_R4K
>> 538 select CLKSRC_MIPS_GIC
>> 539 select COMMON_CLK
>> 540 select CSRC_R4K
>> 541 select DMA_MAYBE_COHERENT
>> 542 select GENERIC_ISA_DMA
>> 543 select HAVE_PCSPKR_PLATFORM
>> 544 select HAVE_PCI
>> 545 select I8253
>> 546 select I8259
>> 547 select IRQ_MIPS_CPU
>> 548 select MIPS_BONITO64
>> 549 select MIPS_CPU_SCACHE
>> 550 select MIPS_GIC
>> 551 select MIPS_L1_CACHE_SHIFT_6
>> 552 select MIPS_MSC
>> 553 select PCI_GT64XXX_PCI0
>> 554 select SMP_UP if SMP
>> 555 select SWAP_IO_SPACE
>> 556 select SYS_HAS_CPU_MIPS32_R1
>> 557 select SYS_HAS_CPU_MIPS32_R2
>> 558 select SYS_HAS_CPU_MIPS32_R3_5
>> 559 select SYS_HAS_CPU_MIPS32_R5
>> 560 select SYS_HAS_CPU_MIPS32_R6
>> 561 select SYS_HAS_CPU_MIPS64_R1
>> 562 select SYS_HAS_CPU_MIPS64_R2
>> 563 select SYS_HAS_CPU_MIPS64_R6
>> 564 select SYS_HAS_CPU_NEVADA
>> 565 select SYS_HAS_CPU_RM7000
>> 566 select SYS_SUPPORTS_32BIT_KERNEL
>> 567 select SYS_SUPPORTS_64BIT_KERNEL
>> 568 select SYS_SUPPORTS_BIG_ENDIAN
>> 569 select SYS_SUPPORTS_HIGHMEM
>> 570 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 571 select SYS_SUPPORTS_MICROMIPS
>> 572 select SYS_SUPPORTS_MIPS16
>> 573 select SYS_SUPPORTS_MIPS_CMP
>> 574 select SYS_SUPPORTS_MIPS_CPS
>> 575 select SYS_SUPPORTS_MULTITHREADING
>> 576 select SYS_SUPPORTS_RELOCATABLE
>> 577 select SYS_SUPPORTS_SMARTMIPS
>> 578 select SYS_SUPPORTS_VPE_LOADER
>> 579 select SYS_SUPPORTS_ZBOOT
>> 580 select USE_OF
>> 581 select ZONE_DMA32 if 64BIT
>> 582 help
>> 583 This enables support for the MIPS Technologies Malta evaluation
>> 584 board.
>> 585
>> 586 config MACH_PIC32
>> 587 bool "Microchip PIC32 Family"
>> 588 help
>> 589 This enables support for the Microchip PIC32 family of platforms.
>> 590
>> 591 Microchip PIC32 is a family of general-purpose 32 bit MIPS core
>> 592 microcontrollers.
>> 593
>> 594 config NEC_MARKEINS
>> 595 bool "NEC EMMA2RH Mark-eins board"
>> 596 select SOC_EMMA2RH
>> 597 select HAVE_PCI
>> 598 help
>> 599 This enables support for the NEC Electronics Mark-eins boards.
306 600
307 config ARM64_CONT_PMD_SHIFT !! 601 config MACH_VR41XX
308 int !! 602 bool "NEC VR4100 series based machines"
309 default 5 if PAGE_SIZE_64KB !! 603 select CEVT_R4K
310 default 5 if PAGE_SIZE_16KB !! 604 select CSRC_R4K
311 default 4 !! 605 select SYS_HAS_CPU_VR41XX
>> 606 select SYS_SUPPORTS_MIPS16
>> 607 select GPIOLIB
>> 608
>> 609 config NXP_STB220
>> 610 bool "NXP STB220 board"
>> 611 select SOC_PNX833X
>> 612 help
>> 613 Support for NXP Semiconductors STB220 Development Board.
>> 614
>> 615 config NXP_STB225
>> 616 bool "NXP 225 board"
>> 617 select SOC_PNX833X
>> 618 select SOC_PNX8335
>> 619 help
>> 620 Support for NXP Semiconductors STB225 Development Board.
>> 621
>> 622 config PMC_MSP
>> 623 bool "PMC-Sierra MSP chipsets"
>> 624 select CEVT_R4K
>> 625 select CSRC_R4K
>> 626 select DMA_NONCOHERENT
>> 627 select SWAP_IO_SPACE
>> 628 select NO_EXCEPT_FILL
>> 629 select BOOT_RAW
>> 630 select SYS_HAS_CPU_MIPS32_R1
>> 631 select SYS_HAS_CPU_MIPS32_R2
>> 632 select SYS_SUPPORTS_32BIT_KERNEL
>> 633 select SYS_SUPPORTS_BIG_ENDIAN
>> 634 select SYS_SUPPORTS_MIPS16
>> 635 select IRQ_MIPS_CPU
>> 636 select SERIAL_8250
>> 637 select SERIAL_8250_CONSOLE
>> 638 select USB_EHCI_BIG_ENDIAN_MMIO
>> 639 select USB_EHCI_BIG_ENDIAN_DESC
>> 640 help
>> 641 This adds support for the PMC-Sierra family of Multi-Service
>> 642 Processor System-On-A-Chips. These parts include a number
>> 643 of integrated peripherals, interfaces and DSPs in addition to
>> 644 a variety of MIPS cores.
>> 645
>> 646 config RALINK
>> 647 bool "Ralink based machines"
>> 648 select CEVT_R4K
>> 649 select CSRC_R4K
>> 650 select BOOT_RAW
>> 651 select DMA_NONCOHERENT
>> 652 select IRQ_MIPS_CPU
>> 653 select USE_OF
>> 654 select SYS_HAS_CPU_MIPS32_R1
>> 655 select SYS_HAS_CPU_MIPS32_R2
>> 656 select SYS_SUPPORTS_32BIT_KERNEL
>> 657 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 658 select SYS_SUPPORTS_MIPS16
>> 659 select SYS_HAS_EARLY_PRINTK
>> 660 select CLKDEV_LOOKUP
>> 661 select ARCH_HAS_RESET_CONTROLLER
>> 662 select RESET_CONTROLLER
>> 663
>> 664 config SGI_IP22
>> 665 bool "SGI IP22 (Indy/Indigo2)"
>> 666 select ARC_MEMORY
>> 667 select ARC_PROMLIB
>> 668 select FW_ARC
>> 669 select FW_ARC32
>> 670 select ARCH_MIGHT_HAVE_PC_SERIO
>> 671 select BOOT_ELF32
>> 672 select CEVT_R4K
>> 673 select CSRC_R4K
>> 674 select DEFAULT_SGI_PARTITION
>> 675 select DMA_NONCOHERENT
>> 676 select HAVE_EISA
>> 677 select I8253
>> 678 select I8259
>> 679 select IP22_CPU_SCACHE
>> 680 select IRQ_MIPS_CPU
>> 681 select GENERIC_ISA_DMA_SUPPORT_BROKEN
>> 682 select SGI_HAS_I8042
>> 683 select SGI_HAS_INDYDOG
>> 684 select SGI_HAS_HAL2
>> 685 select SGI_HAS_SEEQ
>> 686 select SGI_HAS_WD93
>> 687 select SGI_HAS_ZILOG
>> 688 select SWAP_IO_SPACE
>> 689 select SYS_HAS_CPU_R4X00
>> 690 select SYS_HAS_CPU_R5000
>> 691 select SYS_HAS_EARLY_PRINTK
>> 692 select SYS_SUPPORTS_32BIT_KERNEL
>> 693 select SYS_SUPPORTS_64BIT_KERNEL
>> 694 select SYS_SUPPORTS_BIG_ENDIAN
>> 695 select MIPS_L1_CACHE_SHIFT_7
>> 696 help
>> 697 This are the SGI Indy, Challenge S and Indigo2, as well as certain
>> 698 OEM variants like the Tandem CMN B006S. To compile a Linux kernel
>> 699 that runs on these, say Y here.
>> 700
>> 701 config SGI_IP27
>> 702 bool "SGI IP27 (Origin200/2000)"
>> 703 select ARCH_HAS_PHYS_TO_DMA
>> 704 select ARCH_SPARSEMEM_ENABLE
>> 705 select FW_ARC
>> 706 select FW_ARC64
>> 707 select ARC_CMDLINE_ONLY
>> 708 select BOOT_ELF64
>> 709 select DEFAULT_SGI_PARTITION
>> 710 select SYS_HAS_EARLY_PRINTK
>> 711 select HAVE_PCI
>> 712 select IRQ_MIPS_CPU
>> 713 select IRQ_DOMAIN_HIERARCHY
>> 714 select NR_CPUS_DEFAULT_64
>> 715 select PCI_DRIVERS_GENERIC
>> 716 select PCI_XTALK_BRIDGE
>> 717 select SYS_HAS_CPU_R10000
>> 718 select SYS_SUPPORTS_64BIT_KERNEL
>> 719 select SYS_SUPPORTS_BIG_ENDIAN
>> 720 select SYS_SUPPORTS_NUMA
>> 721 select SYS_SUPPORTS_SMP
>> 722 select MIPS_L1_CACHE_SHIFT_7
>> 723 help
>> 724 This are the SGI Origin 200, Origin 2000 and Onyx 2 Graphics
>> 725 workstations. To compile a Linux kernel that runs on these, say Y
>> 726 here.
>> 727
>> 728 config SGI_IP28
>> 729 bool "SGI IP28 (Indigo2 R10k)"
>> 730 select ARC_MEMORY
>> 731 select ARC_PROMLIB
>> 732 select FW_ARC
>> 733 select FW_ARC64
>> 734 select ARCH_MIGHT_HAVE_PC_SERIO
>> 735 select BOOT_ELF64
>> 736 select CEVT_R4K
>> 737 select CSRC_R4K
>> 738 select DEFAULT_SGI_PARTITION
>> 739 select DMA_NONCOHERENT
>> 740 select GENERIC_ISA_DMA_SUPPORT_BROKEN
>> 741 select IRQ_MIPS_CPU
>> 742 select HAVE_EISA
>> 743 select I8253
>> 744 select I8259
>> 745 select SGI_HAS_I8042
>> 746 select SGI_HAS_INDYDOG
>> 747 select SGI_HAS_HAL2
>> 748 select SGI_HAS_SEEQ
>> 749 select SGI_HAS_WD93
>> 750 select SGI_HAS_ZILOG
>> 751 select SWAP_IO_SPACE
>> 752 select SYS_HAS_CPU_R10000
>> 753 select SYS_HAS_EARLY_PRINTK
>> 754 select SYS_SUPPORTS_64BIT_KERNEL
>> 755 select SYS_SUPPORTS_BIG_ENDIAN
>> 756 select MIPS_L1_CACHE_SHIFT_7
>> 757 help
>> 758 This is the SGI Indigo2 with R10000 processor. To compile a Linux
>> 759 kernel that runs on these, say Y here.
>> 760
>> 761 config SGI_IP30
>> 762 bool "SGI IP30 (Octane/Octane2)"
>> 763 select ARCH_HAS_PHYS_TO_DMA
>> 764 select FW_ARC
>> 765 select FW_ARC64
>> 766 select BOOT_ELF64
>> 767 select CEVT_R4K
>> 768 select CSRC_R4K
>> 769 select SYNC_R4K if SMP
>> 770 select ZONE_DMA32
>> 771 select HAVE_PCI
>> 772 select IRQ_MIPS_CPU
>> 773 select IRQ_DOMAIN_HIERARCHY
>> 774 select NR_CPUS_DEFAULT_2
>> 775 select PCI_DRIVERS_GENERIC
>> 776 select PCI_XTALK_BRIDGE
>> 777 select SYS_HAS_EARLY_PRINTK
>> 778 select SYS_HAS_CPU_R10000
>> 779 select SYS_SUPPORTS_64BIT_KERNEL
>> 780 select SYS_SUPPORTS_BIG_ENDIAN
>> 781 select SYS_SUPPORTS_SMP
>> 782 select MIPS_L1_CACHE_SHIFT_7
>> 783 select ARC_MEMORY
>> 784 help
>> 785 These are the SGI Octane and Octane2 graphics workstations. To
>> 786 compile a Linux kernel that runs on these, say Y here.
>> 787
>> 788 config SGI_IP32
>> 789 bool "SGI IP32 (O2)"
>> 790 select ARC_MEMORY
>> 791 select ARC_PROMLIB
>> 792 select ARCH_HAS_PHYS_TO_DMA
>> 793 select FW_ARC
>> 794 select FW_ARC32
>> 795 select BOOT_ELF32
>> 796 select CEVT_R4K
>> 797 select CSRC_R4K
>> 798 select DMA_NONCOHERENT
>> 799 select HAVE_PCI
>> 800 select IRQ_MIPS_CPU
>> 801 select R5000_CPU_SCACHE
>> 802 select RM7000_CPU_SCACHE
>> 803 select SYS_HAS_CPU_R5000
>> 804 select SYS_HAS_CPU_R10000 if BROKEN
>> 805 select SYS_HAS_CPU_RM7000
>> 806 select SYS_HAS_CPU_NEVADA
>> 807 select SYS_SUPPORTS_64BIT_KERNEL
>> 808 select SYS_SUPPORTS_BIG_ENDIAN
>> 809 help
>> 810 If you want this kernel to run on SGI O2 workstation, say Y here.
>> 811
>> 812 config SIBYTE_CRHINE
>> 813 bool "Sibyte BCM91120C-CRhine"
>> 814 select BOOT_ELF32
>> 815 select SIBYTE_BCM1120
>> 816 select SWAP_IO_SPACE
>> 817 select SYS_HAS_CPU_SB1
>> 818 select SYS_SUPPORTS_BIG_ENDIAN
>> 819 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 820
>> 821 config SIBYTE_CARMEL
>> 822 bool "Sibyte BCM91120x-Carmel"
>> 823 select BOOT_ELF32
>> 824 select SIBYTE_BCM1120
>> 825 select SWAP_IO_SPACE
>> 826 select SYS_HAS_CPU_SB1
>> 827 select SYS_SUPPORTS_BIG_ENDIAN
>> 828 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 829
>> 830 config SIBYTE_CRHONE
>> 831 bool "Sibyte BCM91125C-CRhone"
>> 832 select BOOT_ELF32
>> 833 select SIBYTE_BCM1125
>> 834 select SWAP_IO_SPACE
>> 835 select SYS_HAS_CPU_SB1
>> 836 select SYS_SUPPORTS_BIG_ENDIAN
>> 837 select SYS_SUPPORTS_HIGHMEM
>> 838 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 839
>> 840 config SIBYTE_RHONE
>> 841 bool "Sibyte BCM91125E-Rhone"
>> 842 select BOOT_ELF32
>> 843 select SIBYTE_BCM1125H
>> 844 select SWAP_IO_SPACE
>> 845 select SYS_HAS_CPU_SB1
>> 846 select SYS_SUPPORTS_BIG_ENDIAN
>> 847 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 848
>> 849 config SIBYTE_SWARM
>> 850 bool "Sibyte BCM91250A-SWARM"
>> 851 select BOOT_ELF32
>> 852 select HAVE_PATA_PLATFORM
>> 853 select SIBYTE_SB1250
>> 854 select SWAP_IO_SPACE
>> 855 select SYS_HAS_CPU_SB1
>> 856 select SYS_SUPPORTS_BIG_ENDIAN
>> 857 select SYS_SUPPORTS_HIGHMEM
>> 858 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 859 select ZONE_DMA32 if 64BIT
>> 860 select SWIOTLB if ARCH_DMA_ADDR_T_64BIT && PCI
>> 861
>> 862 config SIBYTE_LITTLESUR
>> 863 bool "Sibyte BCM91250C2-LittleSur"
>> 864 select BOOT_ELF32
>> 865 select HAVE_PATA_PLATFORM
>> 866 select SIBYTE_SB1250
>> 867 select SWAP_IO_SPACE
>> 868 select SYS_HAS_CPU_SB1
>> 869 select SYS_SUPPORTS_BIG_ENDIAN
>> 870 select SYS_SUPPORTS_HIGHMEM
>> 871 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 872 select ZONE_DMA32 if 64BIT
>> 873
>> 874 config SIBYTE_SENTOSA
>> 875 bool "Sibyte BCM91250E-Sentosa"
>> 876 select BOOT_ELF32
>> 877 select SIBYTE_SB1250
>> 878 select SWAP_IO_SPACE
>> 879 select SYS_HAS_CPU_SB1
>> 880 select SYS_SUPPORTS_BIG_ENDIAN
>> 881 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 882 select SWIOTLB if ARCH_DMA_ADDR_T_64BIT && PCI
>> 883
>> 884 config SIBYTE_BIGSUR
>> 885 bool "Sibyte BCM91480B-BigSur"
>> 886 select BOOT_ELF32
>> 887 select NR_CPUS_DEFAULT_4
>> 888 select SIBYTE_BCM1x80
>> 889 select SWAP_IO_SPACE
>> 890 select SYS_HAS_CPU_SB1
>> 891 select SYS_SUPPORTS_BIG_ENDIAN
>> 892 select SYS_SUPPORTS_HIGHMEM
>> 893 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 894 select ZONE_DMA32 if 64BIT
>> 895 select SWIOTLB if ARCH_DMA_ADDR_T_64BIT && PCI
>> 896
>> 897 config SNI_RM
>> 898 bool "SNI RM200/300/400"
>> 899 select ARC_MEMORY
>> 900 select ARC_PROMLIB
>> 901 select FW_ARC if CPU_LITTLE_ENDIAN
>> 902 select FW_ARC32 if CPU_LITTLE_ENDIAN
>> 903 select FW_SNIPROM if CPU_BIG_ENDIAN
>> 904 select ARCH_MAY_HAVE_PC_FDC
>> 905 select ARCH_MIGHT_HAVE_PC_PARPORT
>> 906 select ARCH_MIGHT_HAVE_PC_SERIO
>> 907 select BOOT_ELF32
>> 908 select CEVT_R4K
>> 909 select CSRC_R4K
>> 910 select DEFAULT_SGI_PARTITION if CPU_BIG_ENDIAN
>> 911 select DMA_NONCOHERENT
>> 912 select GENERIC_ISA_DMA
>> 913 select HAVE_EISA
>> 914 select HAVE_PCSPKR_PLATFORM
>> 915 select HAVE_PCI
>> 916 select IRQ_MIPS_CPU
>> 917 select I8253
>> 918 select I8259
>> 919 select ISA
>> 920 select SWAP_IO_SPACE if CPU_BIG_ENDIAN
>> 921 select SYS_HAS_CPU_R4X00
>> 922 select SYS_HAS_CPU_R5000
>> 923 select SYS_HAS_CPU_R10000
>> 924 select R5000_CPU_SCACHE
>> 925 select SYS_HAS_EARLY_PRINTK
>> 926 select SYS_SUPPORTS_32BIT_KERNEL
>> 927 select SYS_SUPPORTS_64BIT_KERNEL
>> 928 select SYS_SUPPORTS_BIG_ENDIAN
>> 929 select SYS_SUPPORTS_HIGHMEM
>> 930 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 931 help
>> 932 The SNI RM200/300/400 are MIPS-based machines manufactured by
>> 933 Siemens Nixdorf Informationssysteme (SNI), parent company of Pyramid
>> 934 Technology and now in turn merged with Fujitsu. Say Y here to
>> 935 support this machine type.
>> 936
>> 937 config MACH_TX39XX
>> 938 bool "Toshiba TX39 series based machines"
>> 939
>> 940 config MACH_TX49XX
>> 941 bool "Toshiba TX49 series based machines"
>> 942
>> 943 config MIKROTIK_RB532
>> 944 bool "Mikrotik RB532 boards"
>> 945 select CEVT_R4K
>> 946 select CSRC_R4K
>> 947 select DMA_NONCOHERENT
>> 948 select HAVE_PCI
>> 949 select IRQ_MIPS_CPU
>> 950 select SYS_HAS_CPU_MIPS32_R1
>> 951 select SYS_SUPPORTS_32BIT_KERNEL
>> 952 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 953 select SWAP_IO_SPACE
>> 954 select BOOT_RAW
>> 955 select GPIOLIB
>> 956 select MIPS_L1_CACHE_SHIFT_4
>> 957 help
>> 958 Support the Mikrotik(tm) RouterBoard 532 series,
>> 959 based on the IDT RC32434 SoC.
>> 960
>> 961 config CAVIUM_OCTEON_SOC
>> 962 bool "Cavium Networks Octeon SoC based boards"
>> 963 select CEVT_R4K
>> 964 select ARCH_HAS_PHYS_TO_DMA
>> 965 select HAVE_RAPIDIO
>> 966 select PHYS_ADDR_T_64BIT
>> 967 select SYS_SUPPORTS_64BIT_KERNEL
>> 968 select SYS_SUPPORTS_BIG_ENDIAN
>> 969 select EDAC_SUPPORT
>> 970 select EDAC_ATOMIC_SCRUB
>> 971 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 972 select SYS_SUPPORTS_HOTPLUG_CPU if CPU_BIG_ENDIAN
>> 973 select SYS_HAS_EARLY_PRINTK
>> 974 select SYS_HAS_CPU_CAVIUM_OCTEON
>> 975 select HAVE_PCI
>> 976 select ZONE_DMA32
>> 977 select HOLES_IN_ZONE
>> 978 select GPIOLIB
>> 979 select USE_OF
>> 980 select ARCH_SPARSEMEM_ENABLE
>> 981 select SYS_SUPPORTS_SMP
>> 982 select NR_CPUS_DEFAULT_64
>> 983 select MIPS_NR_CPU_NR_MAP_1024
>> 984 select BUILTIN_DTB
>> 985 select MTD_COMPLEX_MAPPINGS
>> 986 select SWIOTLB
>> 987 select SYS_SUPPORTS_RELOCATABLE
>> 988 help
>> 989 This option supports all of the Octeon reference boards from Cavium
>> 990 Networks. It builds a kernel that dynamically determines the Octeon
>> 991 CPU type and supports all known board reference implementations.
>> 992 Some of the supported boards are:
>> 993 EBT3000
>> 994 EBH3000
>> 995 EBH3100
>> 996 Thunder
>> 997 Kodama
>> 998 Hikari
>> 999 Say Y here for most Octeon reference boards.
>> 1000
>> 1001 config NLM_XLR_BOARD
>> 1002 bool "Netlogic XLR/XLS based systems"
>> 1003 select BOOT_ELF32
>> 1004 select NLM_COMMON
>> 1005 select SYS_HAS_CPU_XLR
>> 1006 select SYS_SUPPORTS_SMP
>> 1007 select HAVE_PCI
>> 1008 select SWAP_IO_SPACE
>> 1009 select SYS_SUPPORTS_32BIT_KERNEL
>> 1010 select SYS_SUPPORTS_64BIT_KERNEL
>> 1011 select PHYS_ADDR_T_64BIT
>> 1012 select SYS_SUPPORTS_BIG_ENDIAN
>> 1013 select SYS_SUPPORTS_HIGHMEM
>> 1014 select NR_CPUS_DEFAULT_32
>> 1015 select CEVT_R4K
>> 1016 select CSRC_R4K
>> 1017 select IRQ_MIPS_CPU
>> 1018 select ZONE_DMA32 if 64BIT
>> 1019 select SYNC_R4K
>> 1020 select SYS_HAS_EARLY_PRINTK
>> 1021 select SYS_SUPPORTS_ZBOOT
>> 1022 select SYS_SUPPORTS_ZBOOT_UART16550
>> 1023 help
>> 1024 Support for systems based on Netlogic XLR and XLS processors.
>> 1025 Say Y here if you have a XLR or XLS based board.
>> 1026
>> 1027 config NLM_XLP_BOARD
>> 1028 bool "Netlogic XLP based systems"
>> 1029 select BOOT_ELF32
>> 1030 select NLM_COMMON
>> 1031 select SYS_HAS_CPU_XLP
>> 1032 select SYS_SUPPORTS_SMP
>> 1033 select HAVE_PCI
>> 1034 select SYS_SUPPORTS_32BIT_KERNEL
>> 1035 select SYS_SUPPORTS_64BIT_KERNEL
>> 1036 select PHYS_ADDR_T_64BIT
>> 1037 select GPIOLIB
>> 1038 select SYS_SUPPORTS_BIG_ENDIAN
>> 1039 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 1040 select SYS_SUPPORTS_HIGHMEM
>> 1041 select NR_CPUS_DEFAULT_32
>> 1042 select CEVT_R4K
>> 1043 select CSRC_R4K
>> 1044 select IRQ_MIPS_CPU
>> 1045 select ZONE_DMA32 if 64BIT
>> 1046 select SYNC_R4K
>> 1047 select SYS_HAS_EARLY_PRINTK
>> 1048 select USE_OF
>> 1049 select SYS_SUPPORTS_ZBOOT
>> 1050 select SYS_SUPPORTS_ZBOOT_UART16550
>> 1051 help
>> 1052 This board is based on Netlogic XLP Processor.
>> 1053 Say Y here if you have a XLP based board.
>> 1054
>> 1055 config MIPS_PARAVIRT
>> 1056 bool "Para-Virtualized guest system"
>> 1057 select CEVT_R4K
>> 1058 select CSRC_R4K
>> 1059 select SYS_SUPPORTS_64BIT_KERNEL
>> 1060 select SYS_SUPPORTS_32BIT_KERNEL
>> 1061 select SYS_SUPPORTS_BIG_ENDIAN
>> 1062 select SYS_SUPPORTS_SMP
>> 1063 select NR_CPUS_DEFAULT_4
>> 1064 select SYS_HAS_EARLY_PRINTK
>> 1065 select SYS_HAS_CPU_MIPS32_R2
>> 1066 select SYS_HAS_CPU_MIPS64_R2
>> 1067 select SYS_HAS_CPU_CAVIUM_OCTEON
>> 1068 select HAVE_PCI
>> 1069 select SWAP_IO_SPACE
>> 1070 help
>> 1071 This option supports guest running under ????
312 1072
313 config ARCH_MMAP_RND_BITS_MIN !! 1073 endchoice
314 default 14 if PAGE_SIZE_64KB <<
315 default 16 if PAGE_SIZE_16KB <<
316 default 18 <<
317 1074
318 # max bits determined by the following formula !! 1075 source "arch/mips/alchemy/Kconfig"
319 # VA_BITS - PAGE_SHIFT - 3 !! 1076 source "arch/mips/ath25/Kconfig"
320 config ARCH_MMAP_RND_BITS_MAX !! 1077 source "arch/mips/ath79/Kconfig"
321 default 19 if ARM64_VA_BITS=36 !! 1078 source "arch/mips/bcm47xx/Kconfig"
322 default 24 if ARM64_VA_BITS=39 !! 1079 source "arch/mips/bcm63xx/Kconfig"
323 default 27 if ARM64_VA_BITS=42 !! 1080 source "arch/mips/bmips/Kconfig"
324 default 30 if ARM64_VA_BITS=47 !! 1081 source "arch/mips/generic/Kconfig"
325 default 29 if ARM64_VA_BITS=48 && ARM6 !! 1082 source "arch/mips/jazz/Kconfig"
326 default 31 if ARM64_VA_BITS=48 && ARM6 !! 1083 source "arch/mips/jz4740/Kconfig"
327 default 33 if ARM64_VA_BITS=48 !! 1084 source "arch/mips/lantiq/Kconfig"
328 default 14 if ARM64_64K_PAGES !! 1085 source "arch/mips/lasat/Kconfig"
329 default 16 if ARM64_16K_PAGES !! 1086 source "arch/mips/pic32/Kconfig"
330 default 18 !! 1087 source "arch/mips/pistachio/Kconfig"
>> 1088 source "arch/mips/pmcs-msp71xx/Kconfig"
>> 1089 source "arch/mips/ralink/Kconfig"
>> 1090 source "arch/mips/sgi-ip27/Kconfig"
>> 1091 source "arch/mips/sibyte/Kconfig"
>> 1092 source "arch/mips/txx9/Kconfig"
>> 1093 source "arch/mips/vr41xx/Kconfig"
>> 1094 source "arch/mips/cavium-octeon/Kconfig"
>> 1095 source "arch/mips/loongson2ef/Kconfig"
>> 1096 source "arch/mips/loongson32/Kconfig"
>> 1097 source "arch/mips/loongson64/Kconfig"
>> 1098 source "arch/mips/netlogic/Kconfig"
>> 1099 source "arch/mips/paravirt/Kconfig"
331 1100
332 config ARCH_MMAP_RND_COMPAT_BITS_MIN !! 1101 endmenu
333 default 7 if ARM64_64K_PAGES <<
334 default 9 if ARM64_16K_PAGES <<
335 default 11 <<
336 1102
337 config ARCH_MMAP_RND_COMPAT_BITS_MAX !! 1103 config GENERIC_HWEIGHT
338 default 16 !! 1104 bool
>> 1105 default y
339 1106
340 config NO_IOPORT_MAP !! 1107 config GENERIC_CALIBRATE_DELAY
341 def_bool y if !PCI !! 1108 bool
>> 1109 default y
342 1110
343 config STACKTRACE_SUPPORT !! 1111 config SCHED_OMIT_FRAME_POINTER
344 def_bool y !! 1112 bool
>> 1113 default y
345 1114
346 config ILLEGAL_POINTER_VALUE !! 1115 #
347 hex !! 1116 # Select some configuration options automatically based on user selections.
348 default 0xdead000000000000 !! 1117 #
>> 1118 config FW_ARC
>> 1119 bool
349 1120
350 config LOCKDEP_SUPPORT !! 1121 config ARCH_MAY_HAVE_PC_FDC
351 def_bool y !! 1122 bool
352 1123
353 config GENERIC_BUG !! 1124 config BOOT_RAW
354 def_bool y !! 1125 bool
355 depends on BUG <<
356 1126
357 config GENERIC_BUG_RELATIVE_POINTERS !! 1127 config CEVT_BCM1480
358 def_bool y !! 1128 bool
359 depends on GENERIC_BUG <<
360 1129
361 config GENERIC_HWEIGHT !! 1130 config CEVT_DS1287
362 def_bool y !! 1131 bool
363 1132
364 config GENERIC_CSUM !! 1133 config CEVT_GT641XX
365 def_bool y !! 1134 bool
366 1135
367 config GENERIC_CALIBRATE_DELAY !! 1136 config CEVT_R4K
368 def_bool y !! 1137 bool
369 1138
370 config SMP !! 1139 config CEVT_SB1250
371 def_bool y !! 1140 bool
372 1141
373 config KERNEL_MODE_NEON !! 1142 config CEVT_TXX9
374 def_bool y !! 1143 bool
375 1144
376 config FIX_EARLYCON_MEM !! 1145 config CSRC_BCM1480
377 def_bool y !! 1146 bool
378 1147
379 config PGTABLE_LEVELS !! 1148 config CSRC_IOASIC
380 int !! 1149 bool
381 default 2 if ARM64_16K_PAGES && ARM64_ <<
382 default 2 if ARM64_64K_PAGES && ARM64_ <<
383 default 3 if ARM64_64K_PAGES && (ARM64 <<
384 default 3 if ARM64_4K_PAGES && ARM64_V <<
385 default 3 if ARM64_16K_PAGES && ARM64_ <<
386 default 4 if ARM64_16K_PAGES && (ARM64 <<
387 default 4 if !ARM64_64K_PAGES && ARM64 <<
388 default 5 if ARM64_4K_PAGES && ARM64_V <<
389 1150
390 config ARCH_SUPPORTS_UPROBES !! 1151 config CSRC_R4K
391 def_bool y !! 1152 bool
392 1153
393 config ARCH_PROC_KCORE_TEXT !! 1154 config CSRC_SB1250
394 def_bool y !! 1155 bool
395 1156
396 config BROKEN_GAS_INST !! 1157 config MIPS_CLOCK_VSYSCALL
397 def_bool !$(as-instr,1:\n.inst 0\n.rep !! 1158 def_bool CSRC_R4K || CLKSRC_MIPS_GIC
398 1159
399 config BUILTIN_RETURN_ADDRESS_STRIPS_PAC !! 1160 config GPIO_TXX9
>> 1161 select GPIOLIB
400 bool 1162 bool
401 # Clang's __builtin_return_address() s <<
402 # https://github.com/llvm/llvm-project <<
403 default y if CC_IS_CLANG <<
404 # GCC's __builtin_return_address() str <<
405 # and this was backported to 10.2.0, 9 <<
406 # https://gcc.gnu.org/bugzilla/show_bu <<
407 default y if CC_IS_GCC && (GCC_VERSION <<
408 default y if CC_IS_GCC && (GCC_VERSION <<
409 default y if CC_IS_GCC && (GCC_VERSION <<
410 default y if CC_IS_GCC && (GCC_VERSION <<
411 default n <<
412 1163
413 config KASAN_SHADOW_OFFSET !! 1164 config FW_CFE
414 hex <<
415 depends on KASAN_GENERIC || KASAN_SW_T <<
416 default 0xdfff800000000000 if (ARM64_V <<
417 default 0xdfffc00000000000 if (ARM64_V <<
418 default 0xdffffe0000000000 if ARM64_VA <<
419 default 0xdfffffc000000000 if ARM64_VA <<
420 default 0xdffffff800000000 if ARM64_VA <<
421 default 0xefff800000000000 if (ARM64_V <<
422 default 0xefffc00000000000 if (ARM64_V <<
423 default 0xeffffe0000000000 if ARM64_VA <<
424 default 0xefffffc000000000 if ARM64_VA <<
425 default 0xeffffff800000000 if ARM64_VA <<
426 default 0xffffffffffffffff <<
427 <<
428 config UNWIND_TABLES <<
429 bool 1165 bool
430 1166
431 source "arch/arm64/Kconfig.platforms" !! 1167 config ARCH_SUPPORTS_UPROBES
>> 1168 bool
432 1169
433 menu "Kernel Features" !! 1170 config DMA_MAYBE_COHERENT
>> 1171 select ARCH_HAS_DMA_COHERENCE_H
>> 1172 select DMA_NONCOHERENT
>> 1173 bool
434 1174
435 menu "ARM errata workarounds via the alternati !! 1175 config DMA_PERDEV_COHERENT
>> 1176 bool
>> 1177 select ARCH_HAS_SETUP_DMA_OPS
>> 1178 select DMA_NONCOHERENT
436 1179
437 config AMPERE_ERRATUM_AC03_CPU_38 !! 1180 config DMA_NONCOHERENT
438 bool "AmpereOne: AC03_CPU_38: Certain !! 1181 bool
439 default y !! 1182 #
440 help !! 1183 # MIPS allows mixing "slightly different" Cacheability and Coherency
441 This option adds an alternative code !! 1184 # Attribute bits. It is believed that the uncached access through
442 errata AC03_CPU_38 and AC04_CPU_10 o !! 1185 # KSEG1 and the implementation specific "uncached accelerated" used
>> 1186 # by pgprot_writcombine can be mixed, and the latter sometimes provides
>> 1187 # significant advantages.
>> 1188 #
>> 1189 select ARCH_HAS_DMA_WRITE_COMBINE
>> 1190 select ARCH_HAS_SYNC_DMA_FOR_DEVICE
>> 1191 select ARCH_HAS_UNCACHED_SEGMENT
>> 1192 select DMA_NONCOHERENT_MMAP
>> 1193 select DMA_NONCOHERENT_CACHE_SYNC
>> 1194 select NEED_DMA_MAP_STATE
443 1195
444 The affected design reports FEAT_HAF !! 1196 config SYS_HAS_EARLY_PRINTK
445 ID_AA64MMFR1_EL1.HAFDBS, but (V)TCR_ !! 1197 bool
446 as required by the architecture. The <<
447 implementation suffers from an addit <<
448 A/D updates can occur after a PTE ha <<
449 <<
450 The workaround forces KVM to explici <<
451 which avoids enabling unadvertised h <<
452 at stage-2. <<
453 1198
454 If unsure, say Y. !! 1199 config SYS_SUPPORTS_HOTPLUG_CPU
>> 1200 bool
455 1201
456 config ARM64_WORKAROUND_CLEAN_CACHE !! 1202 config MIPS_BONITO64
457 bool 1203 bool
458 1204
459 config ARM64_ERRATUM_826319 !! 1205 config MIPS_MSC
460 bool "Cortex-A53: 826319: System might !! 1206 bool
461 default y <<
462 select ARM64_WORKAROUND_CLEAN_CACHE <<
463 help <<
464 This option adds an alternative code <<
465 erratum 826319 on Cortex-A53 parts u <<
466 AXI master interface and an L2 cache <<
467 <<
468 If a Cortex-A53 uses an AMBA AXI4 AC <<
469 and is unable to accept a certain wr <<
470 not progress on read data presented <<
471 system can deadlock. <<
472 <<
473 The workaround promotes data cache c <<
474 data cache clean-and-invalidate. <<
475 Please note that this does not neces <<
476 as it depends on the alternative fra <<
477 the kernel if an affected CPU is det <<
478 1207
479 If unsure, say Y. !! 1208 config MIPS_NILE4
>> 1209 bool
480 1210
481 config ARM64_ERRATUM_827319 !! 1211 config SYNC_R4K
482 bool "Cortex-A53: 827319: Data cache c !! 1212 bool
483 default y <<
484 select ARM64_WORKAROUND_CLEAN_CACHE <<
485 help <<
486 This option adds an alternative code <<
487 erratum 827319 on Cortex-A53 parts u <<
488 master interface and an L2 cache. <<
489 <<
490 Under certain conditions this erratu <<
491 to occur at the same time as another <<
492 on the AMBA 5 CHI interface, which c <<
493 interconnect reorders the two transa <<
494 <<
495 The workaround promotes data cache c <<
496 data cache clean-and-invalidate. <<
497 Please note that this does not neces <<
498 as it depends on the alternative fra <<
499 the kernel if an affected CPU is det <<
500 1213
501 If unsure, say Y. !! 1214 config MIPS_MACHINE
>> 1215 def_bool n
502 1216
503 config ARM64_ERRATUM_824069 !! 1217 config NO_IOPORT_MAP
504 bool "Cortex-A53: 824069: Cache line m !! 1218 def_bool n
505 default y <<
506 select ARM64_WORKAROUND_CLEAN_CACHE <<
507 help <<
508 This option adds an alternative code <<
509 erratum 824069 on Cortex-A53 parts u <<
510 to a coherent interconnect. <<
511 <<
512 If a Cortex-A53 processor is executi <<
513 write instruction at the same time a <<
514 cluster is executing a cache mainten <<
515 address, then this erratum might cau <<
516 incorrectly marked as dirty. <<
517 <<
518 The workaround promotes data cache c <<
519 data cache clean-and-invalidate. <<
520 Please note that this option does no <<
521 workaround, as it depends on the alt <<
522 only patch the kernel if an affected <<
523 1219
524 If unsure, say Y. !! 1220 config GENERIC_CSUM
>> 1221 def_bool CPU_NO_LOAD_STORE_LR
525 1222
526 config ARM64_ERRATUM_819472 !! 1223 config GENERIC_ISA_DMA
527 bool "Cortex-A53: 819472: Store exclus !! 1224 bool
528 default y !! 1225 select ZONE_DMA if GENERIC_ISA_DMA_SUPPORT_BROKEN=n
529 select ARM64_WORKAROUND_CLEAN_CACHE !! 1226 select ISA_DMA_API
530 help <<
531 This option adds an alternative code <<
532 erratum 819472 on Cortex-A53 parts u <<
533 present when it is connected to a co <<
534 <<
535 If the processor is executing a load <<
536 the same time as a processor in anot <<
537 maintenance operation to the same ad <<
538 cause data corruption. <<
539 <<
540 The workaround promotes data cache c <<
541 data cache clean-and-invalidate. <<
542 Please note that this does not neces <<
543 as it depends on the alternative fra <<
544 the kernel if an affected CPU is det <<
545 1227
546 If unsure, say Y. !! 1228 config GENERIC_ISA_DMA_SUPPORT_BROKEN
>> 1229 bool
>> 1230 select GENERIC_ISA_DMA
547 1231
548 config ARM64_ERRATUM_832075 !! 1232 config ISA_DMA_API
549 bool "Cortex-A57: 832075: possible dea !! 1233 bool
550 default y <<
551 help <<
552 This option adds an alternative code <<
553 erratum 832075 on Cortex-A57 parts u <<
554 1234
555 Affected Cortex-A57 parts might dead !! 1235 config HOLES_IN_ZONE
556 instructions to Write-Back memory ar !! 1236 bool
557 1237
558 The workaround is to promote device !! 1238 config SYS_SUPPORTS_RELOCATABLE
559 semantics. !! 1239 bool
560 Please note that this does not neces !! 1240 help
561 as it depends on the alternative fra !! 1241 Selected if the platform supports relocating the kernel.
562 the kernel if an affected CPU is det !! 1242 The platform must provide plat_get_fdt() if it selects CONFIG_USE_OF
>> 1243 to allow access to command line and entropy sources.
563 1244
564 If unsure, say Y. !! 1245 config MIPS_CBPF_JIT
>> 1246 def_bool y
>> 1247 depends on BPF_JIT && HAVE_CBPF_JIT
565 1248
566 config ARM64_ERRATUM_834220 !! 1249 config MIPS_EBPF_JIT
567 bool "Cortex-A57: 834220: Stage 2 tran !! 1250 def_bool y
568 depends on KVM !! 1251 depends on BPF_JIT && HAVE_EBPF_JIT
569 help <<
570 This option adds an alternative code <<
571 erratum 834220 on Cortex-A57 parts u <<
572 <<
573 Affected Cortex-A57 parts might repo <<
574 fault as the result of a Stage 1 fau <<
575 page boundary when there is a permis <<
576 alignment fault at Stage 1 and a tra <<
577 <<
578 The workaround is to verify that the <<
579 doesn't generate a fault before hand <<
580 Please note that this does not neces <<
581 as it depends on the alternative fra <<
582 the kernel if an affected CPU is det <<
583 1252
584 If unsure, say N. <<
585 1253
586 config ARM64_ERRATUM_1742098 !! 1254 #
587 bool "Cortex-A57/A72: 1742098: ELR rec !! 1255 # Endianness selection. Sufficiently obscure so many users don't know what to
588 depends on COMPAT !! 1256 # answer,so we try hard to limit the available choices. Also the use of a
589 default y !! 1257 # choice statement should be more obvious to the user.
>> 1258 #
>> 1259 choice
>> 1260 prompt "Endianness selection"
590 help 1261 help
591 This option removes the AES hwcap fo !! 1262 Some MIPS machines can be configured for either little or big endian
592 workaround erratum 1742098 on Cortex !! 1263 byte order. These modes require different kernels and a different
593 !! 1264 Linux distribution. In general there is one preferred byteorder for a
594 Affected parts may corrupt the AES s !! 1265 particular system but some systems are just as commonly used in the
595 taken between a pair of AES instruct !! 1266 one or the other endianness.
596 are only present if the cryptography <<
597 All software should have a fallback <<
598 that don't implement the cryptograph <<
599 1267
600 If unsure, say Y. !! 1268 config CPU_BIG_ENDIAN
>> 1269 bool "Big endian"
>> 1270 depends on SYS_SUPPORTS_BIG_ENDIAN
601 1271
602 config ARM64_ERRATUM_845719 !! 1272 config CPU_LITTLE_ENDIAN
603 bool "Cortex-A53: 845719: a load might !! 1273 bool "Little endian"
604 depends on COMPAT !! 1274 depends on SYS_SUPPORTS_LITTLE_ENDIAN
605 default y <<
606 help <<
607 This option adds an alternative code <<
608 erratum 845719 on Cortex-A53 parts u <<
609 1275
610 When running a compat (AArch32) user !! 1276 endchoice
611 part, a load at EL0 from a virtual a <<
612 bits of the virtual address used by <<
613 might return incorrect data. <<
614 <<
615 The workaround is to write the conte <<
616 return to a 32-bit task. <<
617 Please note that this does not neces <<
618 as it depends on the alternative fra <<
619 the kernel if an affected CPU is det <<
620 1277
621 If unsure, say Y. !! 1278 config EXPORT_UASM
>> 1279 bool
622 1280
623 config ARM64_ERRATUM_843419 !! 1281 config SYS_SUPPORTS_APM_EMULATION
624 bool "Cortex-A53: 843419: A load or st !! 1282 bool
625 default y <<
626 help <<
627 This option links the kernel with '- <<
628 enables PLT support to replace certa <<
629 cause subsequent memory accesses to <<
630 Cortex-A53 parts up to r0p4. <<
631 1283
632 If unsure, say Y. !! 1284 config SYS_SUPPORTS_BIG_ENDIAN
>> 1285 bool
633 1286
634 config ARM64_LD_HAS_FIX_ERRATUM_843419 !! 1287 config SYS_SUPPORTS_LITTLE_ENDIAN
635 def_bool $(ld-option,--fix-cortex-a53- !! 1288 bool
636 1289
637 config ARM64_ERRATUM_1024718 !! 1290 config SYS_SUPPORTS_HUGETLBFS
638 bool "Cortex-A55: 1024718: Update of D !! 1291 bool
>> 1292 depends on CPU_SUPPORTS_HUGEPAGES
639 default y 1293 default y
640 help <<
641 This option adds a workaround for AR <<
642 1294
643 Affected Cortex-A55 cores (all revis !! 1295 config MIPS_HUGE_TLB_SUPPORT
644 update of the hardware dirty bit whe !! 1296 def_bool HUGETLB_PAGE || TRANSPARENT_HUGEPAGE
645 without a break-before-make. The wor <<
646 of hardware DBM locally on the affec <<
647 this erratum will continue to use th <<
648 1297
649 If unsure, say Y. !! 1298 config IRQ_CPU_RM7K
>> 1299 bool
650 1300
651 config ARM64_ERRATUM_1418040 !! 1301 config IRQ_MSP_SLP
652 bool "Cortex-A76/Neoverse-N1: MRC read !! 1302 bool
653 default y <<
654 depends on COMPAT <<
655 help <<
656 This option adds a workaround for AR <<
657 errata 1188873 and 1418040. <<
658 1303
659 Affected Cortex-A76/Neoverse-N1 core !! 1304 config IRQ_MSP_CIC
660 cause register corruption when acces !! 1305 bool
661 from AArch32 userspace. <<
662 1306
663 If unsure, say Y. !! 1307 config IRQ_TXX9
>> 1308 bool
664 1309
665 config ARM64_WORKAROUND_SPECULATIVE_AT !! 1310 config IRQ_GT641XX
666 bool 1311 bool
667 1312
668 config ARM64_ERRATUM_1165522 !! 1313 config PCI_GT64XXX_PCI0
669 bool "Cortex-A76: 1165522: Speculative !! 1314 bool
670 default y <<
671 select ARM64_WORKAROUND_SPECULATIVE_AT <<
672 help <<
673 This option adds a workaround for AR <<
674 1315
675 Affected Cortex-A76 cores (r0p0, r1p !! 1316 config PCI_XTALK_BRIDGE
676 corrupted TLBs by speculating an AT !! 1317 bool
677 context switch. <<
678 1318
679 If unsure, say Y. !! 1319 config NO_EXCEPT_FILL
>> 1320 bool
680 1321
681 config ARM64_ERRATUM_1319367 !! 1322 config SOC_EMMA2RH
682 bool "Cortex-A57/A72: 1319537: Specula !! 1323 bool
683 default y !! 1324 select CEVT_R4K
684 select ARM64_WORKAROUND_SPECULATIVE_AT !! 1325 select CSRC_R4K
685 help !! 1326 select DMA_NONCOHERENT
686 This option adds work arounds for AR !! 1327 select IRQ_MIPS_CPU
687 and A72 erratum 1319367 !! 1328 select SWAP_IO_SPACE
>> 1329 select SYS_HAS_CPU_R5500
>> 1330 select SYS_SUPPORTS_32BIT_KERNEL
>> 1331 select SYS_SUPPORTS_64BIT_KERNEL
>> 1332 select SYS_SUPPORTS_BIG_ENDIAN
688 1333
689 Cortex-A57 and A72 cores could end-u !! 1334 config SOC_PNX833X
690 speculating an AT instruction during !! 1335 bool
>> 1336 select CEVT_R4K
>> 1337 select CSRC_R4K
>> 1338 select IRQ_MIPS_CPU
>> 1339 select DMA_NONCOHERENT
>> 1340 select SYS_HAS_CPU_MIPS32_R2
>> 1341 select SYS_SUPPORTS_32BIT_KERNEL
>> 1342 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 1343 select SYS_SUPPORTS_BIG_ENDIAN
>> 1344 select SYS_SUPPORTS_MIPS16
>> 1345 select CPU_MIPSR2_IRQ_VI
691 1346
692 If unsure, say Y. !! 1347 config SOC_PNX8335
>> 1348 bool
>> 1349 select SOC_PNX833X
693 1350
694 config ARM64_ERRATUM_1530923 !! 1351 config MIPS_SPRAM
695 bool "Cortex-A55: 1530923: Speculative !! 1352 bool
696 default y <<
697 select ARM64_WORKAROUND_SPECULATIVE_AT <<
698 help <<
699 This option adds a workaround for AR <<
700 1353
701 Affected Cortex-A55 cores (r0p0, r0p !! 1354 config SWAP_IO_SPACE
702 corrupted TLBs by speculating an AT !! 1355 bool
703 context switch. <<
704 1356
705 If unsure, say Y. !! 1357 config SGI_HAS_INDYDOG
>> 1358 bool
706 1359
707 config ARM64_WORKAROUND_REPEAT_TLBI !! 1360 config SGI_HAS_HAL2
708 bool 1361 bool
709 1362
710 config ARM64_ERRATUM_2441007 !! 1363 config SGI_HAS_SEEQ
711 bool "Cortex-A55: Completion of affect !! 1364 bool
712 select ARM64_WORKAROUND_REPEAT_TLBI <<
713 help <<
714 This option adds a workaround for AR <<
715 1365
716 Under very rare circumstances, affec !! 1366 config SGI_HAS_WD93
717 may not handle a race between a brea !! 1367 bool
718 CPU, and another CPU accessing the s <<
719 store to a page that has been unmapp <<
720 1368
721 Work around this by adding the affec !! 1369 config SGI_HAS_ZILOG
722 TLB sequences to be done twice. !! 1370 bool
723 1371
724 If unsure, say N. !! 1372 config SGI_HAS_I8042
>> 1373 bool
725 1374
726 config ARM64_ERRATUM_1286807 !! 1375 config DEFAULT_SGI_PARTITION
727 bool "Cortex-A76: Modification of the !! 1376 bool
728 select ARM64_WORKAROUND_REPEAT_TLBI <<
729 help <<
730 This option adds a workaround for AR <<
731 <<
732 On the affected Cortex-A76 cores (r0 <<
733 address for a cacheable mapping of a <<
734 accessed by a core while another cor <<
735 address to a new physical page using <<
736 break-before-make sequence, then und <<
737 TLBI+DSB completes before a read usi <<
738 invalidated has been observed by oth <<
739 workaround repeats the TLBI+DSB oper <<
740 1377
741 If unsure, say N. !! 1378 config FW_ARC32
>> 1379 bool
742 1380
743 config ARM64_ERRATUM_1463225 !! 1381 config FW_SNIPROM
744 bool "Cortex-A76: Software Step might !! 1382 bool
745 default y <<
746 help <<
747 This option adds a workaround for Ar <<
748 1383
749 On the affected Cortex-A76 cores (r0 !! 1384 config BOOT_ELF32
750 of a system call instruction (SVC) c !! 1385 bool
751 subsequent interrupts when software <<
752 exception handler of the system call <<
753 is enabled or VHE is in use. <<
754 <<
755 Work around the erratum by triggerin <<
756 when handling a system call from a t <<
757 in a VHE configuration of the kernel <<
758 1386
759 If unsure, say Y. !! 1387 config MIPS_L1_CACHE_SHIFT_4
>> 1388 bool
760 1389
761 config ARM64_ERRATUM_1542419 !! 1390 config MIPS_L1_CACHE_SHIFT_5
762 bool "Neoverse-N1: workaround mis-orde !! 1391 bool
763 help <<
764 This option adds a workaround for AR <<
765 1542419. <<
766 1392
767 Affected Neoverse-N1 cores could exe !! 1393 config MIPS_L1_CACHE_SHIFT_6
768 modified by another CPU. The workaro !! 1394 bool
769 counterpart. <<
770 1395
771 Workaround the issue by hiding the D !! 1396 config MIPS_L1_CACHE_SHIFT_7
772 forces user-space to perform cache m !! 1397 bool
773 1398
774 If unsure, say N. !! 1399 config MIPS_L1_CACHE_SHIFT
>> 1400 int
>> 1401 default "7" if MIPS_L1_CACHE_SHIFT_7
>> 1402 default "6" if MIPS_L1_CACHE_SHIFT_6
>> 1403 default "5" if MIPS_L1_CACHE_SHIFT_5
>> 1404 default "4" if MIPS_L1_CACHE_SHIFT_4
>> 1405 default "5"
775 1406
776 config ARM64_ERRATUM_1508412 !! 1407 config HAVE_STD_PC_SERIAL_PORT
777 bool "Cortex-A77: 1508412: workaround !! 1408 bool
778 default y <<
779 help <<
780 This option adds a workaround for Ar <<
781 1409
782 Affected Cortex-A77 cores (r0p0, r1p !! 1410 config ARC_CMDLINE_ONLY
783 of a store-exclusive or read of PAR_ !! 1411 bool
784 non-cacheable memory attributes. The <<
785 counterpart. <<
786 <<
787 KVM guests must also have the workar <<
788 deadlock the system. <<
789 <<
790 Work around the issue by inserting D <<
791 register reads and warning KVM users <<
792 to prevent a speculative PAR_EL1 rea <<
793 1412
794 If unsure, say Y. !! 1413 config ARC_CONSOLE
>> 1414 bool "ARC console support"
>> 1415 depends on SGI_IP22 || SGI_IP28 || (SNI_RM && CPU_LITTLE_ENDIAN)
795 1416
796 config ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MO !! 1417 config ARC_MEMORY
797 bool 1418 bool
798 1419
799 config ARM64_ERRATUM_2051678 !! 1420 config ARC_PROMLIB
800 bool "Cortex-A510: 2051678: disable Ha !! 1421 bool
801 default y <<
802 help <<
803 This options adds the workaround for <<
804 Affected Cortex-A510 might not respe <<
805 hardware update of the page table's <<
806 is to not enable the feature on affe <<
807 <<
808 If unsure, say Y. <<
809 1422
810 config ARM64_ERRATUM_2077057 !! 1423 config FW_ARC64
811 bool "Cortex-A510: 2077057: workaround !! 1424 bool
812 default y <<
813 help <<
814 This option adds the workaround for <<
815 Affected Cortex-A510 may corrupt SPS <<
816 expected, but a Pointer Authenticati <<
817 erratum causes SPSR_EL1 to be copied <<
818 EL1 to cause a return to EL2 with a <<
819 1425
820 This can only happen when EL2 is ste !! 1426 config BOOT_ELF64
>> 1427 bool
821 1428
822 When these conditions occur, the SPS !! 1429 menu "CPU selection"
823 previous guest entry, and can be res <<
824 1430
825 If unsure, say Y. !! 1431 choice
>> 1432 prompt "CPU type"
>> 1433 default CPU_R4X00
826 1434
827 config ARM64_ERRATUM_2658417 !! 1435 config CPU_LOONGSON64
828 bool "Cortex-A510: 2658417: remove BF1 !! 1436 bool "Loongson 64-bit CPU"
829 default y !! 1437 depends on SYS_HAS_CPU_LOONGSON64
>> 1438 select ARCH_HAS_PHYS_TO_DMA
>> 1439 select CPU_MIPSR2
>> 1440 select CPU_HAS_PREFETCH
>> 1441 select CPU_SUPPORTS_64BIT_KERNEL
>> 1442 select CPU_SUPPORTS_HIGHMEM
>> 1443 select CPU_SUPPORTS_HUGEPAGES
>> 1444 select CPU_SUPPORTS_MSA
>> 1445 select CPU_DIEI_BROKEN if !LOONGSON3_ENHANCEMENT
>> 1446 select CPU_MIPSR2_IRQ_VI
>> 1447 select WEAK_ORDERING
>> 1448 select WEAK_REORDERING_BEYOND_LLSC
>> 1449 select MIPS_ASID_BITS_VARIABLE
>> 1450 select MIPS_PGD_C0_CONTEXT
>> 1451 select MIPS_L1_CACHE_SHIFT_6
>> 1452 select GPIOLIB
>> 1453 select SWIOTLB
830 help 1454 help
831 This option adds the workaround for !! 1455 The Loongson GSx64(GS264/GS464/GS464E/GS464V) series of processor
832 Affected Cortex-A510 (r0p0 to r1p1) !! 1456 cores implements the MIPS64R2 instruction set with many extensions,
833 BFMMLA or VMMLA instructions in rare !! 1457 including most 64-bit Loongson-2 (2H, 2K) and Loongson-3 (3A1000,
834 A510 CPUs are using shared neon hard !! 1458 3B1000, 3B1500, 3A2000, 3A3000 and 3A4000) processors. However, old
835 discoverable by the kernel, hide the !! 1459 Loongson-2E/2F is not covered here and will be removed in future.
836 user-space should not be using these <<
837 1460
838 If unsure, say Y. !! 1461 config LOONGSON3_ENHANCEMENT
>> 1462 bool "New Loongson-3 CPU Enhancements"
>> 1463 default n
>> 1464 depends on CPU_LOONGSON64
>> 1465 help
>> 1466 New Loongson-3 cores (since Loongson-3A R2, as opposed to Loongson-3A
>> 1467 R1, Loongson-3B R1 and Loongson-3B R2) has many enhancements, such as
>> 1468 FTLB, L1-VCache, EI/DI/Wait/Prefetch instruction, DSP/DSPr2 ASE, User
>> 1469 Local register, Read-Inhibit/Execute-Inhibit, SFB (Store Fill Buffer),
>> 1470 Fast TLB refill support, etc.
>> 1471
>> 1472 This option enable those enhancements which are not probed at run
>> 1473 time. If you want a generic kernel to run on all Loongson 3 machines,
>> 1474 please say 'N' here. If you want a high-performance kernel to run on
>> 1475 new Loongson-3 machines only, please say 'Y' here.
>> 1476
>> 1477 config CPU_LOONGSON3_WORKAROUNDS
>> 1478 bool "Old Loongson-3 LLSC Workarounds"
>> 1479 default y if SMP
>> 1480 depends on CPU_LOONGSON64
>> 1481 help
>> 1482 Loongson-3 processors have the llsc issues which require workarounds.
>> 1483 Without workarounds the system may hang unexpectedly.
>> 1484
>> 1485 Newer Loongson-3 will fix these issues and no workarounds are needed.
>> 1486 The workarounds have no significant side effect on them but may
>> 1487 decrease the performance of the system so this option should be
>> 1488 disabled unless the kernel is intended to be run on old systems.
>> 1489
>> 1490 If unsure, please say Y.
>> 1491
>> 1492 config CPU_LOONGSON2E
>> 1493 bool "Loongson 2E"
>> 1494 depends on SYS_HAS_CPU_LOONGSON2E
>> 1495 select CPU_LOONGSON2EF
>> 1496 help
>> 1497 The Loongson 2E processor implements the MIPS III instruction set
>> 1498 with many extensions.
>> 1499
>> 1500 It has an internal FPGA northbridge, which is compatible to
>> 1501 bonito64.
>> 1502
>> 1503 config CPU_LOONGSON2F
>> 1504 bool "Loongson 2F"
>> 1505 depends on SYS_HAS_CPU_LOONGSON2F
>> 1506 select CPU_LOONGSON2EF
>> 1507 select GPIOLIB
>> 1508 help
>> 1509 The Loongson 2F processor implements the MIPS III instruction set
>> 1510 with many extensions.
>> 1511
>> 1512 Loongson2F have built-in DDR2 and PCIX controller. The PCIX controller
>> 1513 have a similar programming interface with FPGA northbridge used in
>> 1514 Loongson2E.
>> 1515
>> 1516 config CPU_LOONGSON1B
>> 1517 bool "Loongson 1B"
>> 1518 depends on SYS_HAS_CPU_LOONGSON1B
>> 1519 select CPU_LOONGSON32
>> 1520 select LEDS_GPIO_REGISTER
>> 1521 help
>> 1522 The Loongson 1B is a 32-bit SoC, which implements the MIPS32
>> 1523 Release 1 instruction set and part of the MIPS32 Release 2
>> 1524 instruction set.
>> 1525
>> 1526 config CPU_LOONGSON1C
>> 1527 bool "Loongson 1C"
>> 1528 depends on SYS_HAS_CPU_LOONGSON1C
>> 1529 select CPU_LOONGSON32
>> 1530 select LEDS_GPIO_REGISTER
>> 1531 help
>> 1532 The Loongson 1C is a 32-bit SoC, which implements the MIPS32
>> 1533 Release 1 instruction set and part of the MIPS32 Release 2
>> 1534 instruction set.
>> 1535
>> 1536 config CPU_MIPS32_R1
>> 1537 bool "MIPS32 Release 1"
>> 1538 depends on SYS_HAS_CPU_MIPS32_R1
>> 1539 select CPU_HAS_PREFETCH
>> 1540 select CPU_SUPPORTS_32BIT_KERNEL
>> 1541 select CPU_SUPPORTS_HIGHMEM
>> 1542 help
>> 1543 Choose this option to build a kernel for release 1 or later of the
>> 1544 MIPS32 architecture. Most modern embedded systems with a 32-bit
>> 1545 MIPS processor are based on a MIPS32 processor. If you know the
>> 1546 specific type of processor in your system, choose those that one
>> 1547 otherwise CPU_MIPS32_R1 is a safe bet for any MIPS32 system.
>> 1548 Release 2 of the MIPS32 architecture is available since several
>> 1549 years so chances are you even have a MIPS32 Release 2 processor
>> 1550 in which case you should choose CPU_MIPS32_R2 instead for better
>> 1551 performance.
>> 1552
>> 1553 config CPU_MIPS32_R2
>> 1554 bool "MIPS32 Release 2"
>> 1555 depends on SYS_HAS_CPU_MIPS32_R2
>> 1556 select CPU_HAS_PREFETCH
>> 1557 select CPU_SUPPORTS_32BIT_KERNEL
>> 1558 select CPU_SUPPORTS_HIGHMEM
>> 1559 select CPU_SUPPORTS_MSA
>> 1560 select HAVE_KVM
>> 1561 help
>> 1562 Choose this option to build a kernel for release 2 or later of the
>> 1563 MIPS32 architecture. Most modern embedded systems with a 32-bit
>> 1564 MIPS processor are based on a MIPS32 processor. If you know the
>> 1565 specific type of processor in your system, choose those that one
>> 1566 otherwise CPU_MIPS32_R1 is a safe bet for any MIPS32 system.
>> 1567
>> 1568 config CPU_MIPS32_R6
>> 1569 bool "MIPS32 Release 6"
>> 1570 depends on SYS_HAS_CPU_MIPS32_R6
>> 1571 select CPU_HAS_PREFETCH
>> 1572 select CPU_NO_LOAD_STORE_LR
>> 1573 select CPU_SUPPORTS_32BIT_KERNEL
>> 1574 select CPU_SUPPORTS_HIGHMEM
>> 1575 select CPU_SUPPORTS_MSA
>> 1576 select HAVE_KVM
>> 1577 select MIPS_O32_FP64_SUPPORT
>> 1578 help
>> 1579 Choose this option to build a kernel for release 6 or later of the
>> 1580 MIPS32 architecture. New MIPS processors, starting with the Warrior
>> 1581 family, are based on a MIPS32r6 processor. If you own an older
>> 1582 processor, you probably need to select MIPS32r1 or MIPS32r2 instead.
>> 1583
>> 1584 config CPU_MIPS64_R1
>> 1585 bool "MIPS64 Release 1"
>> 1586 depends on SYS_HAS_CPU_MIPS64_R1
>> 1587 select CPU_HAS_PREFETCH
>> 1588 select CPU_SUPPORTS_32BIT_KERNEL
>> 1589 select CPU_SUPPORTS_64BIT_KERNEL
>> 1590 select CPU_SUPPORTS_HIGHMEM
>> 1591 select CPU_SUPPORTS_HUGEPAGES
>> 1592 help
>> 1593 Choose this option to build a kernel for release 1 or later of the
>> 1594 MIPS64 architecture. Many modern embedded systems with a 64-bit
>> 1595 MIPS processor are based on a MIPS64 processor. If you know the
>> 1596 specific type of processor in your system, choose those that one
>> 1597 otherwise CPU_MIPS64_R1 is a safe bet for any MIPS64 system.
>> 1598 Release 2 of the MIPS64 architecture is available since several
>> 1599 years so chances are you even have a MIPS64 Release 2 processor
>> 1600 in which case you should choose CPU_MIPS64_R2 instead for better
>> 1601 performance.
>> 1602
>> 1603 config CPU_MIPS64_R2
>> 1604 bool "MIPS64 Release 2"
>> 1605 depends on SYS_HAS_CPU_MIPS64_R2
>> 1606 select CPU_HAS_PREFETCH
>> 1607 select CPU_SUPPORTS_32BIT_KERNEL
>> 1608 select CPU_SUPPORTS_64BIT_KERNEL
>> 1609 select CPU_SUPPORTS_HIGHMEM
>> 1610 select CPU_SUPPORTS_HUGEPAGES
>> 1611 select CPU_SUPPORTS_MSA
>> 1612 select HAVE_KVM
>> 1613 help
>> 1614 Choose this option to build a kernel for release 2 or later of the
>> 1615 MIPS64 architecture. Many modern embedded systems with a 64-bit
>> 1616 MIPS processor are based on a MIPS64 processor. If you know the
>> 1617 specific type of processor in your system, choose those that one
>> 1618 otherwise CPU_MIPS64_R1 is a safe bet for any MIPS64 system.
>> 1619
>> 1620 config CPU_MIPS64_R6
>> 1621 bool "MIPS64 Release 6"
>> 1622 depends on SYS_HAS_CPU_MIPS64_R6
>> 1623 select CPU_HAS_PREFETCH
>> 1624 select CPU_NO_LOAD_STORE_LR
>> 1625 select CPU_SUPPORTS_32BIT_KERNEL
>> 1626 select CPU_SUPPORTS_64BIT_KERNEL
>> 1627 select CPU_SUPPORTS_HIGHMEM
>> 1628 select CPU_SUPPORTS_HUGEPAGES
>> 1629 select CPU_SUPPORTS_MSA
>> 1630 select MIPS_O32_FP64_SUPPORT if 32BIT || MIPS32_O32
>> 1631 select HAVE_KVM
>> 1632 help
>> 1633 Choose this option to build a kernel for release 6 or later of the
>> 1634 MIPS64 architecture. New MIPS processors, starting with the Warrior
>> 1635 family, are based on a MIPS64r6 processor. If you own an older
>> 1636 processor, you probably need to select MIPS64r1 or MIPS64r2 instead.
>> 1637
>> 1638 config CPU_R3000
>> 1639 bool "R3000"
>> 1640 depends on SYS_HAS_CPU_R3000
>> 1641 select CPU_HAS_WB
>> 1642 select CPU_R3K_TLB
>> 1643 select CPU_SUPPORTS_32BIT_KERNEL
>> 1644 select CPU_SUPPORTS_HIGHMEM
>> 1645 help
>> 1646 Please make sure to pick the right CPU type. Linux/MIPS is not
>> 1647 designed to be generic, i.e. Kernels compiled for R3000 CPUs will
>> 1648 *not* work on R4000 machines and vice versa. However, since most
>> 1649 of the supported machines have an R4000 (or similar) CPU, R4x00
>> 1650 might be a safe bet. If the resulting kernel does not work,
>> 1651 try to recompile with R3000.
>> 1652
>> 1653 config CPU_TX39XX
>> 1654 bool "R39XX"
>> 1655 depends on SYS_HAS_CPU_TX39XX
>> 1656 select CPU_SUPPORTS_32BIT_KERNEL
>> 1657 select CPU_R3K_TLB
>> 1658
>> 1659 config CPU_VR41XX
>> 1660 bool "R41xx"
>> 1661 depends on SYS_HAS_CPU_VR41XX
>> 1662 select CPU_SUPPORTS_32BIT_KERNEL
>> 1663 select CPU_SUPPORTS_64BIT_KERNEL
>> 1664 help
>> 1665 The options selects support for the NEC VR4100 series of processors.
>> 1666 Only choose this option if you have one of these processors as a
>> 1667 kernel built with this option will not run on any other type of
>> 1668 processor or vice versa.
>> 1669
>> 1670 config CPU_R4X00
>> 1671 bool "R4x00"
>> 1672 depends on SYS_HAS_CPU_R4X00
>> 1673 select CPU_SUPPORTS_32BIT_KERNEL
>> 1674 select CPU_SUPPORTS_64BIT_KERNEL
>> 1675 select CPU_SUPPORTS_HUGEPAGES
>> 1676 help
>> 1677 MIPS Technologies R4000-series processors other than 4300, including
>> 1678 the R4000, R4400, R4600, and 4700.
>> 1679
>> 1680 config CPU_TX49XX
>> 1681 bool "R49XX"
>> 1682 depends on SYS_HAS_CPU_TX49XX
>> 1683 select CPU_HAS_PREFETCH
>> 1684 select CPU_SUPPORTS_32BIT_KERNEL
>> 1685 select CPU_SUPPORTS_64BIT_KERNEL
>> 1686 select CPU_SUPPORTS_HUGEPAGES
>> 1687
>> 1688 config CPU_R5000
>> 1689 bool "R5000"
>> 1690 depends on SYS_HAS_CPU_R5000
>> 1691 select CPU_SUPPORTS_32BIT_KERNEL
>> 1692 select CPU_SUPPORTS_64BIT_KERNEL
>> 1693 select CPU_SUPPORTS_HUGEPAGES
>> 1694 help
>> 1695 MIPS Technologies R5000-series processors other than the Nevada.
>> 1696
>> 1697 config CPU_R5500
>> 1698 bool "R5500"
>> 1699 depends on SYS_HAS_CPU_R5500
>> 1700 select CPU_SUPPORTS_32BIT_KERNEL
>> 1701 select CPU_SUPPORTS_64BIT_KERNEL
>> 1702 select CPU_SUPPORTS_HUGEPAGES
>> 1703 help
>> 1704 NEC VR5500 and VR5500A series processors implement 64-bit MIPS IV
>> 1705 instruction set.
>> 1706
>> 1707 config CPU_NEVADA
>> 1708 bool "RM52xx"
>> 1709 depends on SYS_HAS_CPU_NEVADA
>> 1710 select CPU_SUPPORTS_32BIT_KERNEL
>> 1711 select CPU_SUPPORTS_64BIT_KERNEL
>> 1712 select CPU_SUPPORTS_HUGEPAGES
>> 1713 help
>> 1714 QED / PMC-Sierra RM52xx-series ("Nevada") processors.
>> 1715
>> 1716 config CPU_R10000
>> 1717 bool "R10000"
>> 1718 depends on SYS_HAS_CPU_R10000
>> 1719 select CPU_HAS_PREFETCH
>> 1720 select CPU_SUPPORTS_32BIT_KERNEL
>> 1721 select CPU_SUPPORTS_64BIT_KERNEL
>> 1722 select CPU_SUPPORTS_HIGHMEM
>> 1723 select CPU_SUPPORTS_HUGEPAGES
>> 1724 help
>> 1725 MIPS Technologies R10000-series processors.
>> 1726
>> 1727 config CPU_RM7000
>> 1728 bool "RM7000"
>> 1729 depends on SYS_HAS_CPU_RM7000
>> 1730 select CPU_HAS_PREFETCH
>> 1731 select CPU_SUPPORTS_32BIT_KERNEL
>> 1732 select CPU_SUPPORTS_64BIT_KERNEL
>> 1733 select CPU_SUPPORTS_HIGHMEM
>> 1734 select CPU_SUPPORTS_HUGEPAGES
>> 1735
>> 1736 config CPU_SB1
>> 1737 bool "SB1"
>> 1738 depends on SYS_HAS_CPU_SB1
>> 1739 select CPU_SUPPORTS_32BIT_KERNEL
>> 1740 select CPU_SUPPORTS_64BIT_KERNEL
>> 1741 select CPU_SUPPORTS_HIGHMEM
>> 1742 select CPU_SUPPORTS_HUGEPAGES
>> 1743 select WEAK_ORDERING
>> 1744
>> 1745 config CPU_CAVIUM_OCTEON
>> 1746 bool "Cavium Octeon processor"
>> 1747 depends on SYS_HAS_CPU_CAVIUM_OCTEON
>> 1748 select CPU_HAS_PREFETCH
>> 1749 select CPU_SUPPORTS_64BIT_KERNEL
>> 1750 select WEAK_ORDERING
>> 1751 select CPU_SUPPORTS_HIGHMEM
>> 1752 select CPU_SUPPORTS_HUGEPAGES
>> 1753 select USB_EHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 1754 select USB_OHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 1755 select MIPS_L1_CACHE_SHIFT_7
>> 1756 select HAVE_KVM
>> 1757 help
>> 1758 The Cavium Octeon processor is a highly integrated chip containing
>> 1759 many ethernet hardware widgets for networking tasks. The processor
>> 1760 can have up to 16 Mips64v2 cores and 8 integrated gigabit ethernets.
>> 1761 Full details can be found at http://www.caviumnetworks.com.
>> 1762
>> 1763 config CPU_BMIPS
>> 1764 bool "Broadcom BMIPS"
>> 1765 depends on SYS_HAS_CPU_BMIPS
>> 1766 select CPU_MIPS32
>> 1767 select CPU_BMIPS32_3300 if SYS_HAS_CPU_BMIPS32_3300
>> 1768 select CPU_BMIPS4350 if SYS_HAS_CPU_BMIPS4350
>> 1769 select CPU_BMIPS4380 if SYS_HAS_CPU_BMIPS4380
>> 1770 select CPU_BMIPS5000 if SYS_HAS_CPU_BMIPS5000
>> 1771 select CPU_SUPPORTS_32BIT_KERNEL
>> 1772 select DMA_NONCOHERENT
>> 1773 select IRQ_MIPS_CPU
>> 1774 select SWAP_IO_SPACE
>> 1775 select WEAK_ORDERING
>> 1776 select CPU_SUPPORTS_HIGHMEM
>> 1777 select CPU_HAS_PREFETCH
>> 1778 select CPU_SUPPORTS_CPUFREQ
>> 1779 select MIPS_EXTERNAL_TIMER
>> 1780 help
>> 1781 Support for BMIPS32/3300/4350/4380 and BMIPS5000 processors.
>> 1782
>> 1783 config CPU_XLR
>> 1784 bool "Netlogic XLR SoC"
>> 1785 depends on SYS_HAS_CPU_XLR
>> 1786 select CPU_SUPPORTS_32BIT_KERNEL
>> 1787 select CPU_SUPPORTS_64BIT_KERNEL
>> 1788 select CPU_SUPPORTS_HIGHMEM
>> 1789 select CPU_SUPPORTS_HUGEPAGES
>> 1790 select WEAK_ORDERING
>> 1791 select WEAK_REORDERING_BEYOND_LLSC
>> 1792 help
>> 1793 Netlogic Microsystems XLR/XLS processors.
>> 1794
>> 1795 config CPU_XLP
>> 1796 bool "Netlogic XLP SoC"
>> 1797 depends on SYS_HAS_CPU_XLP
>> 1798 select CPU_SUPPORTS_32BIT_KERNEL
>> 1799 select CPU_SUPPORTS_64BIT_KERNEL
>> 1800 select CPU_SUPPORTS_HIGHMEM
>> 1801 select WEAK_ORDERING
>> 1802 select WEAK_REORDERING_BEYOND_LLSC
>> 1803 select CPU_HAS_PREFETCH
>> 1804 select CPU_MIPSR2
>> 1805 select CPU_SUPPORTS_HUGEPAGES
>> 1806 select MIPS_ASID_BITS_VARIABLE
>> 1807 help
>> 1808 Netlogic Microsystems XLP processors.
>> 1809 endchoice
839 1810
840 config ARM64_ERRATUM_2119858 !! 1811 config CPU_MIPS32_3_5_FEATURES
841 bool "Cortex-A710/X2: 2119858: workaro !! 1812 bool "MIPS32 Release 3.5 Features"
842 default y !! 1813 depends on SYS_HAS_CPU_MIPS32_R3_5
843 depends on CORESIGHT_TRBE !! 1814 depends on CPU_MIPS32_R2 || CPU_MIPS32_R6
844 select ARM64_WORKAROUND_TRBE_OVERWRITE !! 1815 help
>> 1816 Choose this option to build a kernel for release 2 or later of the
>> 1817 MIPS32 architecture including features from the 3.5 release such as
>> 1818 support for Enhanced Virtual Addressing (EVA).
>> 1819
>> 1820 config CPU_MIPS32_3_5_EVA
>> 1821 bool "Enhanced Virtual Addressing (EVA)"
>> 1822 depends on CPU_MIPS32_3_5_FEATURES
>> 1823 select EVA
>> 1824 default y
>> 1825 help
>> 1826 Choose this option if you want to enable the Enhanced Virtual
>> 1827 Addressing (EVA) on your MIPS32 core (such as proAptiv).
>> 1828 One of its primary benefits is an increase in the maximum size
>> 1829 of lowmem (up to 3GB). If unsure, say 'N' here.
>> 1830
>> 1831 config CPU_MIPS32_R5_FEATURES
>> 1832 bool "MIPS32 Release 5 Features"
>> 1833 depends on SYS_HAS_CPU_MIPS32_R5
>> 1834 depends on CPU_MIPS32_R2
>> 1835 help
>> 1836 Choose this option to build a kernel for release 2 or later of the
>> 1837 MIPS32 architecture including features from release 5 such as
>> 1838 support for Extended Physical Addressing (XPA).
>> 1839
>> 1840 config CPU_MIPS32_R5_XPA
>> 1841 bool "Extended Physical Addressing (XPA)"
>> 1842 depends on CPU_MIPS32_R5_FEATURES
>> 1843 depends on !EVA
>> 1844 depends on !PAGE_SIZE_4KB
>> 1845 depends on SYS_SUPPORTS_HIGHMEM
>> 1846 select XPA
>> 1847 select HIGHMEM
>> 1848 select PHYS_ADDR_T_64BIT
>> 1849 default n
845 help 1850 help
846 This option adds the workaround for !! 1851 Choose this option if you want to enable the Extended Physical
>> 1852 Addressing (XPA) on your MIPS32 core (such as P5600 series). The
>> 1853 benefit is to increase physical addressing equal to or greater
>> 1854 than 40 bits. Note that this has the side effect of turning on
>> 1855 64-bit addressing which in turn makes the PTEs 64-bit in size.
>> 1856 If unsure, say 'N' here.
847 1857
848 Affected Cortex-A710/X2 cores could !! 1858 if CPU_LOONGSON2F
849 data at the base of the buffer (poin !! 1859 config CPU_NOP_WORKAROUNDS
850 the event of a WRAP event. !! 1860 bool
851 <<
852 Work around the issue by always maki <<
853 256 bytes before enabling the buffer <<
854 the buffer with ETM ignore packets u <<
855 1861
856 If unsure, say Y. !! 1862 config CPU_JUMP_WORKAROUNDS
>> 1863 bool
857 1864
858 config ARM64_ERRATUM_2139208 !! 1865 config CPU_LOONGSON2F_WORKAROUNDS
859 bool "Neoverse-N2: 2139208: workaround !! 1866 bool "Loongson 2F Workarounds"
860 default y 1867 default y
861 depends on CORESIGHT_TRBE !! 1868 select CPU_NOP_WORKAROUNDS
862 select ARM64_WORKAROUND_TRBE_OVERWRITE !! 1869 select CPU_JUMP_WORKAROUNDS
863 help 1870 help
864 This option adds the workaround for !! 1871 Loongson 2F01 / 2F02 processors have the NOP & JUMP issues which
>> 1872 require workarounds. Without workarounds the system may hang
>> 1873 unexpectedly. For more information please refer to the gas
>> 1874 -mfix-loongson2f-nop and -mfix-loongson2f-jump options.
>> 1875
>> 1876 Loongson 2F03 and later have fixed these issues and no workarounds
>> 1877 are needed. The workarounds have no significant side effect on them
>> 1878 but may decrease the performance of the system so this option should
>> 1879 be disabled unless the kernel is intended to be run on 2F01 or 2F02
>> 1880 systems.
865 1881
866 Affected Neoverse-N2 cores could ove !! 1882 If unsure, please say Y.
867 data at the base of the buffer (poin !! 1883 endif # CPU_LOONGSON2F
868 the event of a WRAP event. <<
869 <<
870 Work around the issue by always maki <<
871 256 bytes before enabling the buffer <<
872 the buffer with ETM ignore packets u <<
873 1884
874 If unsure, say Y. !! 1885 config SYS_SUPPORTS_ZBOOT
875 <<
876 config ARM64_WORKAROUND_TSB_FLUSH_FAILURE <<
877 bool 1886 bool
>> 1887 select HAVE_KERNEL_GZIP
>> 1888 select HAVE_KERNEL_BZIP2
>> 1889 select HAVE_KERNEL_LZ4
>> 1890 select HAVE_KERNEL_LZMA
>> 1891 select HAVE_KERNEL_LZO
>> 1892 select HAVE_KERNEL_XZ
878 1893
879 config ARM64_ERRATUM_2054223 !! 1894 config SYS_SUPPORTS_ZBOOT_UART16550
880 bool "Cortex-A710: 2054223: workaround !! 1895 bool
881 default y !! 1896 select SYS_SUPPORTS_ZBOOT
882 select ARM64_WORKAROUND_TSB_FLUSH_FAIL <<
883 help <<
884 Enable workaround for ARM Cortex-A71 <<
885 1897
886 Affected cores may fail to flush the !! 1898 config SYS_SUPPORTS_ZBOOT_UART_PROM
887 the PE is in trace prohibited state. !! 1899 bool
888 of the trace cached. !! 1900 select SYS_SUPPORTS_ZBOOT
889 1901
890 Workaround is to issue two TSB conse !! 1902 config CPU_LOONGSON2EF
>> 1903 bool
>> 1904 select CPU_SUPPORTS_32BIT_KERNEL
>> 1905 select CPU_SUPPORTS_64BIT_KERNEL
>> 1906 select CPU_SUPPORTS_HIGHMEM
>> 1907 select CPU_SUPPORTS_HUGEPAGES
>> 1908 select ARCH_HAS_PHYS_TO_DMA
891 1909
892 If unsure, say Y. !! 1910 config CPU_LOONGSON32
>> 1911 bool
>> 1912 select CPU_MIPS32
>> 1913 select CPU_MIPSR2
>> 1914 select CPU_HAS_PREFETCH
>> 1915 select CPU_SUPPORTS_32BIT_KERNEL
>> 1916 select CPU_SUPPORTS_HIGHMEM
>> 1917 select CPU_SUPPORTS_CPUFREQ
893 1918
894 config ARM64_ERRATUM_2067961 !! 1919 config CPU_BMIPS32_3300
895 bool "Neoverse-N2: 2067961: workaround !! 1920 select SMP_UP if SMP
896 default y !! 1921 bool
897 select ARM64_WORKAROUND_TSB_FLUSH_FAIL <<
898 help <<
899 Enable workaround for ARM Neoverse-N <<
900 1922
901 Affected cores may fail to flush the !! 1923 config CPU_BMIPS4350
902 the PE is in trace prohibited state. !! 1924 bool
903 of the trace cached. !! 1925 select SYS_SUPPORTS_SMP
>> 1926 select SYS_SUPPORTS_HOTPLUG_CPU
904 1927
905 Workaround is to issue two TSB conse !! 1928 config CPU_BMIPS4380
>> 1929 bool
>> 1930 select MIPS_L1_CACHE_SHIFT_6
>> 1931 select SYS_SUPPORTS_SMP
>> 1932 select SYS_SUPPORTS_HOTPLUG_CPU
>> 1933 select CPU_HAS_RIXI
906 1934
907 If unsure, say Y. !! 1935 config CPU_BMIPS5000
>> 1936 bool
>> 1937 select MIPS_CPU_SCACHE
>> 1938 select MIPS_L1_CACHE_SHIFT_7
>> 1939 select SYS_SUPPORTS_SMP
>> 1940 select SYS_SUPPORTS_HOTPLUG_CPU
>> 1941 select CPU_HAS_RIXI
908 1942
909 config ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANG !! 1943 config SYS_HAS_CPU_LOONGSON64
910 bool 1944 bool
>> 1945 select CPU_SUPPORTS_CPUFREQ
>> 1946 select CPU_HAS_RIXI
911 1947
912 config ARM64_ERRATUM_2253138 !! 1948 config SYS_HAS_CPU_LOONGSON2E
913 bool "Neoverse-N2: 2253138: workaround !! 1949 bool
914 depends on CORESIGHT_TRBE <<
915 default y <<
916 select ARM64_WORKAROUND_TRBE_WRITE_OUT <<
917 help <<
918 This option adds the workaround for <<
919 1950
920 Affected Neoverse-N2 cores might wri !! 1951 config SYS_HAS_CPU_LOONGSON2F
921 for TRBE. Under some conditions, the !! 1952 bool
922 virtually addressed page following t !! 1953 select CPU_SUPPORTS_CPUFREQ
923 (i.e., the TRBLIMITR_EL1.LIMIT), ins !! 1954 select CPU_SUPPORTS_ADDRWINCFG if 64BIT
924 1955
925 Work around this in the driver by al !! 1956 config SYS_HAS_CPU_LOONGSON1B
926 page beyond the TRBLIMITR_EL1.LIMIT, !! 1957 bool
927 1958
928 If unsure, say Y. !! 1959 config SYS_HAS_CPU_LOONGSON1C
>> 1960 bool
929 1961
930 config ARM64_ERRATUM_2224489 !! 1962 config SYS_HAS_CPU_MIPS32_R1
931 bool "Cortex-A710/X2: 2224489: workaro !! 1963 bool
932 depends on CORESIGHT_TRBE <<
933 default y <<
934 select ARM64_WORKAROUND_TRBE_WRITE_OUT <<
935 help <<
936 This option adds the workaround for <<
937 1964
938 Affected Cortex-A710/X2 cores might !! 1965 config SYS_HAS_CPU_MIPS32_R2
939 for TRBE. Under some conditions, the !! 1966 bool
940 virtually addressed page following t <<
941 (i.e., the TRBLIMITR_EL1.LIMIT), ins <<
942 1967
943 Work around this in the driver by al !! 1968 config SYS_HAS_CPU_MIPS32_R3_5
944 page beyond the TRBLIMITR_EL1.LIMIT, !! 1969 bool
945 1970
946 If unsure, say Y. !! 1971 config SYS_HAS_CPU_MIPS32_R5
>> 1972 bool
>> 1973 select ARCH_HAS_SYNC_DMA_FOR_CPU if DMA_NONCOHERENT
947 1974
948 config ARM64_ERRATUM_2441009 !! 1975 config SYS_HAS_CPU_MIPS32_R6
949 bool "Cortex-A510: Completion of affec !! 1976 bool
950 select ARM64_WORKAROUND_REPEAT_TLBI !! 1977 select ARCH_HAS_SYNC_DMA_FOR_CPU if DMA_NONCOHERENT
951 help <<
952 This option adds a workaround for AR <<
953 <<
954 Under very rare circumstances, affec <<
955 may not handle a race between a brea <<
956 CPU, and another CPU accessing the s <<
957 store to a page that has been unmapp <<
958 1978
959 Work around this by adding the affec !! 1979 config SYS_HAS_CPU_MIPS64_R1
960 TLB sequences to be done twice. !! 1980 bool
961 1981
962 If unsure, say N. !! 1982 config SYS_HAS_CPU_MIPS64_R2
>> 1983 bool
963 1984
964 config ARM64_ERRATUM_2064142 !! 1985 config SYS_HAS_CPU_MIPS64_R6
965 bool "Cortex-A510: 2064142: workaround !! 1986 bool
966 depends on CORESIGHT_TRBE !! 1987 select ARCH_HAS_SYNC_DMA_FOR_CPU if DMA_NONCOHERENT
967 default y <<
968 help <<
969 This option adds the workaround for <<
970 1988
971 Affected Cortex-A510 core might fail !! 1989 config SYS_HAS_CPU_R3000
972 TRBE has been disabled. Under some c !! 1990 bool
973 writes into TRBE registers TRBLIMITR <<
974 and TRBTRG_EL1 will be ignored and w <<
975 <<
976 Work around this in the driver by ex <<
977 is stopped and before performing a s <<
978 registers. <<
979 1991
980 If unsure, say Y. !! 1992 config SYS_HAS_CPU_TX39XX
>> 1993 bool
981 1994
982 config ARM64_ERRATUM_2038923 !! 1995 config SYS_HAS_CPU_VR41XX
983 bool "Cortex-A510: 2038923: workaround !! 1996 bool
984 depends on CORESIGHT_TRBE <<
985 default y <<
986 help <<
987 This option adds the workaround for <<
988 1997
989 Affected Cortex-A510 core might caus !! 1998 config SYS_HAS_CPU_R4X00
990 prohibited within the CPU. As a resu !! 1999 bool
991 might be corrupted. This happens aft <<
992 TRBLIMITR_EL1.E, followed by just a <<
993 execution changes from a context, in <<
994 isn't, or vice versa. In these menti <<
995 is prohibited is inconsistent betwee <<
996 the trace buffer state might be corr <<
997 <<
998 Work around this in the driver by pr <<
999 trace is prohibited or not based on <<
1000 change to TRBLIMITR_EL1.E with at l <<
1001 two ISB instructions if no ERET is <<
1002 2000
1003 If unsure, say Y. !! 2001 config SYS_HAS_CPU_TX49XX
>> 2002 bool
1004 2003
1005 config ARM64_ERRATUM_1902691 !! 2004 config SYS_HAS_CPU_R5000
1006 bool "Cortex-A510: 1902691: workaroun !! 2005 bool
1007 depends on CORESIGHT_TRBE <<
1008 default y <<
1009 help <<
1010 This option adds the workaround for <<
1011 2006
1012 Affected Cortex-A510 core might cau !! 2007 config SYS_HAS_CPU_R5500
1013 into the memory. Effectively TRBE i !! 2008 bool
1014 trace data. <<
1015 <<
1016 Work around this problem in the dri <<
1017 affected cpus. The firmware must ha <<
1018 on such implementations. This will <<
1019 do this already. <<
1020 2009
1021 If unsure, say Y. !! 2010 config SYS_HAS_CPU_NEVADA
>> 2011 bool
1022 2012
1023 config ARM64_ERRATUM_2457168 !! 2013 config SYS_HAS_CPU_R10000
1024 bool "Cortex-A510: 2457168: workaroun !! 2014 bool
1025 depends on ARM64_AMU_EXTN !! 2015 select ARCH_HAS_SYNC_DMA_FOR_CPU if DMA_NONCOHERENT
1026 default y <<
1027 help <<
1028 This option adds the workaround for <<
1029 2016
1030 The AMU counter AMEVCNTR01 (constan !! 2017 config SYS_HAS_CPU_RM7000
1031 as the system counter. On affected !! 2018 bool
1032 incorrectly giving a significantly <<
1033 <<
1034 Work around this problem by returni <<
1035 key locations that results in disab <<
1036 is the same to firmware disabling a <<
1037 2019
1038 If unsure, say Y. !! 2020 config SYS_HAS_CPU_SB1
>> 2021 bool
1039 2022
1040 config ARM64_ERRATUM_2645198 !! 2023 config SYS_HAS_CPU_CAVIUM_OCTEON
1041 bool "Cortex-A715: 2645198: Workaroun !! 2024 bool
1042 default y <<
1043 help <<
1044 This option adds the workaround for <<
1045 2025
1046 If a Cortex-A715 cpu sees a page ma !! 2026 config SYS_HAS_CPU_BMIPS
1047 to non-executable, it may corrupt t !! 2027 bool
1048 next instruction abort caused by pe <<
1049 <<
1050 Only user-space does executable to <<
1051 mprotect() system call. Workaround <<
1052 TLB invalidation, for all changes t <<
1053 2028
1054 If unsure, say Y. !! 2029 config SYS_HAS_CPU_BMIPS32_3300
>> 2030 bool
>> 2031 select SYS_HAS_CPU_BMIPS
1055 2032
1056 config ARM64_WORKAROUND_SPECULATIVE_UNPRIV_LO !! 2033 config SYS_HAS_CPU_BMIPS4350
1057 bool 2034 bool
>> 2035 select SYS_HAS_CPU_BMIPS
1058 2036
1059 config ARM64_ERRATUM_2966298 !! 2037 config SYS_HAS_CPU_BMIPS4380
1060 bool "Cortex-A520: 2966298: workaroun !! 2038 bool
1061 select ARM64_WORKAROUND_SPECULATIVE_U !! 2039 select SYS_HAS_CPU_BMIPS
1062 default y <<
1063 help <<
1064 This option adds the workaround for <<
1065 2040
1066 On an affected Cortex-A520 core, a !! 2041 config SYS_HAS_CPU_BMIPS5000
1067 load might leak data from a privile !! 2042 bool
>> 2043 select SYS_HAS_CPU_BMIPS
>> 2044 select ARCH_HAS_SYNC_DMA_FOR_CPU
1068 2045
1069 Work around this problem by executi !! 2046 config SYS_HAS_CPU_XLR
>> 2047 bool
1070 2048
1071 If unsure, say Y. !! 2049 config SYS_HAS_CPU_XLP
>> 2050 bool
1072 2051
1073 config ARM64_ERRATUM_3117295 !! 2052 #
1074 bool "Cortex-A510: 3117295: workaroun !! 2053 # CPU may reorder R->R, R->W, W->R, W->W
1075 select ARM64_WORKAROUND_SPECULATIVE_U !! 2054 # Reordering beyond LL and SC is handled in WEAK_REORDERING_BEYOND_LLSC
1076 default y !! 2055 #
1077 help !! 2056 config WEAK_ORDERING
1078 This option adds the workaround for !! 2057 bool
1079 2058
1080 On an affected Cortex-A510 core, a !! 2059 #
1081 load might leak data from a privile !! 2060 # CPU may reorder reads and writes beyond LL/SC
>> 2061 # CPU may reorder R->LL, R->LL, W->LL, W->LL, R->SC, R->SC, W->SC, W->SC
>> 2062 #
>> 2063 config WEAK_REORDERING_BEYOND_LLSC
>> 2064 bool
>> 2065 endmenu
1082 2066
1083 Work around this problem by executi !! 2067 #
>> 2068 # These two indicate any level of the MIPS32 and MIPS64 architecture
>> 2069 #
>> 2070 config CPU_MIPS32
>> 2071 bool
>> 2072 default y if CPU_MIPS32_R1 || CPU_MIPS32_R2 || CPU_MIPS32_R6
1084 2073
1085 If unsure, say Y. !! 2074 config CPU_MIPS64
>> 2075 bool
>> 2076 default y if CPU_MIPS64_R1 || CPU_MIPS64_R2 || CPU_MIPS64_R6
1086 2077
1087 config ARM64_ERRATUM_3194386 !! 2078 #
1088 bool "Cortex-*/Neoverse-*: workaround !! 2079 # These indicate the revision of the architecture
1089 default y !! 2080 #
1090 help !! 2081 config CPU_MIPSR1
1091 This option adds the workaround for !! 2082 bool
>> 2083 default y if CPU_MIPS32_R1 || CPU_MIPS64_R1
1092 2084
1093 * ARM Cortex-A76 erratum 3324349 !! 2085 config CPU_MIPSR2
1094 * ARM Cortex-A77 erratum 3324348 !! 2086 bool
1095 * ARM Cortex-A78 erratum 3324344 !! 2087 default y if CPU_MIPS32_R2 || CPU_MIPS64_R2 || CPU_CAVIUM_OCTEON
1096 * ARM Cortex-A78C erratum 3324346 !! 2088 select CPU_HAS_RIXI
1097 * ARM Cortex-A78C erratum 3324347 !! 2089 select CPU_HAS_DIEI if !CPU_DIEI_BROKEN
1098 * ARM Cortex-A710 erratam 3324338 !! 2090 select MIPS_SPRAM
1099 * ARM Cortex-A715 errartum 3456084 <<
1100 * ARM Cortex-A720 erratum 3456091 <<
1101 * ARM Cortex-A725 erratum 3456106 <<
1102 * ARM Cortex-X1 erratum 3324344 <<
1103 * ARM Cortex-X1C erratum 3324346 <<
1104 * ARM Cortex-X2 erratum 3324338 <<
1105 * ARM Cortex-X3 erratum 3324335 <<
1106 * ARM Cortex-X4 erratum 3194386 <<
1107 * ARM Cortex-X925 erratum 3324334 <<
1108 * ARM Neoverse-N1 erratum 3324349 <<
1109 * ARM Neoverse N2 erratum 3324339 <<
1110 * ARM Neoverse-N3 erratum 3456111 <<
1111 * ARM Neoverse-V1 erratum 3324341 <<
1112 * ARM Neoverse V2 erratum 3324336 <<
1113 * ARM Neoverse-V3 erratum 3312417 <<
1114 <<
1115 On affected cores "MSR SSBS, #0" in <<
1116 subsequent speculative instructions <<
1117 speculative store bypassing. <<
1118 <<
1119 Work around this problem by placing <<
1120 Instruction Synchronization Barrier <<
1121 SSBS. The presence of the SSBS spec <<
1122 from hwcaps and EL0 reads of ID_AA6 <<
1123 will use the PR_SPEC_STORE_BYPASS p <<
1124 2091
1125 If unsure, say Y. !! 2092 config CPU_MIPSR6
>> 2093 bool
>> 2094 default y if CPU_MIPS32_R6 || CPU_MIPS64_R6
>> 2095 select CPU_HAS_RIXI
>> 2096 select CPU_HAS_DIEI if !CPU_DIEI_BROKEN
>> 2097 select HAVE_ARCH_BITREVERSE
>> 2098 select MIPS_ASID_BITS_VARIABLE
>> 2099 select MIPS_CRC_SUPPORT
>> 2100 select MIPS_SPRAM
1126 2101
1127 config CAVIUM_ERRATUM_22375 !! 2102 config TARGET_ISA_REV
1128 bool "Cavium erratum 22375, 24313" !! 2103 int
1129 default y !! 2104 default 1 if CPU_MIPSR1
>> 2105 default 2 if CPU_MIPSR2
>> 2106 default 6 if CPU_MIPSR6
>> 2107 default 0
1130 help 2108 help
1131 Enable workaround for errata 22375 !! 2109 Reflects the ISA revision being targeted by the kernel build. This
>> 2110 is effectively the Kconfig equivalent of MIPS_ISA_REV.
1132 2111
1133 This implements two gicv3-its errat !! 2112 config EVA
1134 with a small impact affecting only !! 2113 bool
1135 2114
1136 erratum 22375: only alloc 8MB tab !! 2115 config XPA
1137 erratum 24313: ignore memory acce !! 2116 bool
1138 2117
1139 The fixes are in ITS initialization !! 2118 config SYS_SUPPORTS_32BIT_KERNEL
1140 type and table size provided by the !! 2119 bool
>> 2120 config SYS_SUPPORTS_64BIT_KERNEL
>> 2121 bool
>> 2122 config CPU_SUPPORTS_32BIT_KERNEL
>> 2123 bool
>> 2124 config CPU_SUPPORTS_64BIT_KERNEL
>> 2125 bool
>> 2126 config CPU_SUPPORTS_CPUFREQ
>> 2127 bool
>> 2128 config CPU_SUPPORTS_ADDRWINCFG
>> 2129 bool
>> 2130 config CPU_SUPPORTS_HUGEPAGES
>> 2131 bool
>> 2132 depends on !(32BIT && (ARCH_PHYS_ADDR_T_64BIT || EVA))
>> 2133 config MIPS_PGD_C0_CONTEXT
>> 2134 bool
>> 2135 default y if 64BIT && (CPU_MIPSR2 || CPU_MIPSR6) && !CPU_XLP
1141 2136
1142 If unsure, say Y. !! 2137 #
>> 2138 # Set to y for ptrace access to watch registers.
>> 2139 #
>> 2140 config HARDWARE_WATCHPOINTS
>> 2141 bool
>> 2142 default y if CPU_MIPSR1 || CPU_MIPSR2 || CPU_MIPSR6
1143 2143
1144 config CAVIUM_ERRATUM_23144 !! 2144 menu "Kernel type"
1145 bool "Cavium erratum 23144: ITS SYNC <<
1146 depends on NUMA <<
1147 default y <<
1148 help <<
1149 ITS SYNC command hang for cross nod <<
1150 2145
1151 If unsure, say Y. !! 2146 choice
>> 2147 prompt "Kernel code model"
>> 2148 help
>> 2149 You should only select this option if you have a workload that
>> 2150 actually benefits from 64-bit processing or if your machine has
>> 2151 large memory. You will only be presented a single option in this
>> 2152 menu if your system does not support both 32-bit and 64-bit kernels.
>> 2153
>> 2154 config 32BIT
>> 2155 bool "32-bit kernel"
>> 2156 depends on CPU_SUPPORTS_32BIT_KERNEL && SYS_SUPPORTS_32BIT_KERNEL
>> 2157 select TRAD_SIGNALS
>> 2158 help
>> 2159 Select this option if you want to build a 32-bit kernel.
1152 2160
1153 config CAVIUM_ERRATUM_23154 !! 2161 config 64BIT
1154 bool "Cavium errata 23154 and 38545: !! 2162 bool "64-bit kernel"
1155 default y !! 2163 depends on CPU_SUPPORTS_64BIT_KERNEL && SYS_SUPPORTS_64BIT_KERNEL
1156 help 2164 help
1157 The ThunderX GICv3 implementation r !! 2165 Select this option if you want to build a 64-bit kernel.
1158 reading the IAR status to ensure da <<
1159 (access to icc_iar1_el1 is not sync <<
1160 <<
1161 It also suffers from erratum 38545 <<
1162 OcteonTX and OcteonTX2), resulting <<
1163 spuriously presented to the CPU int <<
1164 2166
1165 If unsure, say Y. !! 2167 endchoice
1166 2168
1167 config CAVIUM_ERRATUM_27456 !! 2169 config KVM_GUEST
1168 bool "Cavium erratum 27456: Broadcast !! 2170 bool "KVM Guest Kernel"
1169 default y !! 2171 depends on BROKEN_ON_SMP
1170 help !! 2172 help
1171 On ThunderX T88 pass 1.x through 2. !! 2173 Select this option if building a guest kernel for KVM (Trap & Emulate)
1172 instructions may cause the icache t !! 2174 mode.
1173 contains data for a non-current ASI !! 2175
1174 invalidate the icache when changing !! 2176 config KVM_GUEST_TIMER_FREQ
>> 2177 int "Count/Compare Timer Frequency (MHz)"
>> 2178 depends on KVM_GUEST
>> 2179 default 100
>> 2180 help
>> 2181 Set this to non-zero if building a guest kernel for KVM to skip RTC
>> 2182 emulation when determining guest CPU Frequency. Instead, the guest's
>> 2183 timer frequency is specified directly.
>> 2184
>> 2185 config MIPS_VA_BITS_48
>> 2186 bool "48 bits virtual memory"
>> 2187 depends on 64BIT
>> 2188 help
>> 2189 Support a maximum at least 48 bits of application virtual
>> 2190 memory. Default is 40 bits or less, depending on the CPU.
>> 2191 For page sizes 16k and above, this option results in a small
>> 2192 memory overhead for page tables. For 4k page size, a fourth
>> 2193 level of page tables is added which imposes both a memory
>> 2194 overhead as well as slower TLB fault handling.
1175 2195
1176 If unsure, say Y. !! 2196 If unsure, say N.
1177 2197
1178 config CAVIUM_ERRATUM_30115 !! 2198 choice
1179 bool "Cavium erratum 30115: Guest may !! 2199 prompt "Kernel page size"
1180 default y !! 2200 default PAGE_SIZE_4KB
1181 help <<
1182 On ThunderX T88 pass 1.x through 2. <<
1183 1.2, and T83 Pass 1.0, KVM guest ex <<
1184 interrupts in host. Trapping both G <<
1185 accesses sidesteps the issue. <<
1186 2201
1187 If unsure, say Y. !! 2202 config PAGE_SIZE_4KB
>> 2203 bool "4kB"
>> 2204 depends on !CPU_LOONGSON2EF && !CPU_LOONGSON64
>> 2205 help
>> 2206 This option select the standard 4kB Linux page size. On some
>> 2207 R3000-family processors this is the only available page size. Using
>> 2208 4kB page size will minimize memory consumption and is therefore
>> 2209 recommended for low memory systems.
>> 2210
>> 2211 config PAGE_SIZE_8KB
>> 2212 bool "8kB"
>> 2213 depends on CPU_CAVIUM_OCTEON
>> 2214 depends on !MIPS_VA_BITS_48
>> 2215 help
>> 2216 Using 8kB page size will result in higher performance kernel at
>> 2217 the price of higher memory consumption. This option is available
>> 2218 only on cnMIPS processors. Note that you will need a suitable Linux
>> 2219 distribution to support this.
>> 2220
>> 2221 config PAGE_SIZE_16KB
>> 2222 bool "16kB"
>> 2223 depends on !CPU_R3000 && !CPU_TX39XX
>> 2224 help
>> 2225 Using 16kB page size will result in higher performance kernel at
>> 2226 the price of higher memory consumption. This option is available on
>> 2227 all non-R3000 family processors. Note that you will need a suitable
>> 2228 Linux distribution to support this.
>> 2229
>> 2230 config PAGE_SIZE_32KB
>> 2231 bool "32kB"
>> 2232 depends on CPU_CAVIUM_OCTEON
>> 2233 depends on !MIPS_VA_BITS_48
>> 2234 help
>> 2235 Using 32kB page size will result in higher performance kernel at
>> 2236 the price of higher memory consumption. This option is available
>> 2237 only on cnMIPS cores. Note that you will need a suitable Linux
>> 2238 distribution to support this.
>> 2239
>> 2240 config PAGE_SIZE_64KB
>> 2241 bool "64kB"
>> 2242 depends on !CPU_R3000 && !CPU_TX39XX
>> 2243 help
>> 2244 Using 64kB page size will result in higher performance kernel at
>> 2245 the price of higher memory consumption. This option is available on
>> 2246 all non-R3000 family processor. Not that at the time of this
>> 2247 writing this option is still high experimental.
1188 2248
1189 config CAVIUM_TX2_ERRATUM_219 !! 2249 endchoice
1190 bool "Cavium ThunderX2 erratum 219: P <<
1191 default y <<
1192 help <<
1193 On Cavium ThunderX2, a load, store <<
1194 TTBR update and the corresponding c <<
1195 cause a spurious Data Abort to be d <<
1196 the CPU core. <<
1197 <<
1198 Work around the issue by avoiding t <<
1199 trapping KVM guest TTBRx_EL1 writes <<
1200 trap handler performs the correspon <<
1201 instruction and ensures context syn <<
1202 exception return. <<
1203 2250
1204 If unsure, say Y. !! 2251 config FORCE_MAX_ZONEORDER
>> 2252 int "Maximum zone order"
>> 2253 range 14 64 if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_64KB
>> 2254 default "14" if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_64KB
>> 2255 range 13 64 if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_32KB
>> 2256 default "13" if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_32KB
>> 2257 range 12 64 if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_16KB
>> 2258 default "12" if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_16KB
>> 2259 range 11 64
>> 2260 default "11"
>> 2261 help
>> 2262 The kernel memory allocator divides physically contiguous memory
>> 2263 blocks into "zones", where each zone is a power of two number of
>> 2264 pages. This option selects the largest power of two that the kernel
>> 2265 keeps in the memory allocator. If you need to allocate very large
>> 2266 blocks of physically contiguous memory, then you may need to
>> 2267 increase this value.
1205 2268
1206 config FUJITSU_ERRATUM_010001 !! 2269 This config option is actually maximum order plus one. For example,
1207 bool "Fujitsu-A64FX erratum E#010001: !! 2270 a value of 11 means that the largest free memory block is 2^10 pages.
1208 default y <<
1209 help <<
1210 This option adds a workaround for F <<
1211 On some variants of the Fujitsu-A64 <<
1212 accesses may cause undefined fault <<
1213 This fault occurs under a specific <<
1214 load/store instruction performs an <<
1215 case-1 TTBR0_EL1 with TCR_EL1.NFD0 <<
1216 case-2 TTBR0_EL2 with TCR_EL2.NFD0 <<
1217 case-3 TTBR1_EL1 with TCR_EL1.NFD1 <<
1218 case-4 TTBR1_EL2 with TCR_EL2.NFD1 <<
1219 2271
1220 The workaround is to ensure these b !! 2272 The page size is not necessarily 4KB. Keep this in mind
1221 The workaround only affects the Fuj !! 2273 when choosing a value for this option.
1222 2274
1223 If unsure, say Y. !! 2275 config BOARD_SCACHE
>> 2276 bool
1224 2277
1225 config HISILICON_ERRATUM_161600802 !! 2278 config IP22_CPU_SCACHE
1226 bool "Hip07 161600802: Erroneous redi !! 2279 bool
1227 default y !! 2280 select BOARD_SCACHE
1228 help <<
1229 The HiSilicon Hip07 SoC uses the wr <<
1230 when issued ITS commands such as VM <<
1231 a 128kB offset to be applied to the <<
1232 2281
1233 If unsure, say Y. !! 2282 #
>> 2283 # Support for a MIPS32 / MIPS64 style S-caches
>> 2284 #
>> 2285 config MIPS_CPU_SCACHE
>> 2286 bool
>> 2287 select BOARD_SCACHE
1234 2288
1235 config QCOM_FALKOR_ERRATUM_1003 !! 2289 config R5000_CPU_SCACHE
1236 bool "Falkor E1003: Incorrect transla !! 2290 bool
1237 default y !! 2291 select BOARD_SCACHE
1238 help <<
1239 On Falkor v1, an incorrect ASID may <<
1240 and BADDR are changed together in T <<
1241 in TTBR1_EL1, this situation only o <<
1242 then only for entries in the walk c <<
1243 is unchanged. Work around the errat <<
1244 entries for the trampoline before e <<
1245 2292
1246 config QCOM_FALKOR_ERRATUM_1009 !! 2293 config RM7000_CPU_SCACHE
1247 bool "Falkor E1009: Prematurely compl !! 2294 bool
1248 default y !! 2295 select BOARD_SCACHE
1249 select ARM64_WORKAROUND_REPEAT_TLBI !! 2296
>> 2297 config SIBYTE_DMA_PAGEOPS
>> 2298 bool "Use DMA to clear/copy pages"
>> 2299 depends on CPU_SB1
1250 help 2300 help
1251 On Falkor v1, the CPU may premature !! 2301 Instead of using the CPU to zero and copy pages, use a Data Mover
1252 TLBI xxIS invalidate maintenance op !! 2302 channel. These DMA channels are otherwise unused by the standard
1253 one more time to fix the issue. !! 2303 SiByte Linux port. Seems to give a small performance benefit.
1254 2304
1255 If unsure, say Y. !! 2305 config CPU_HAS_PREFETCH
>> 2306 bool
>> 2307
>> 2308 config CPU_GENERIC_DUMP_TLB
>> 2309 bool
>> 2310 default y if !(CPU_R3000 || CPU_TX39XX)
1256 2311
1257 config QCOM_QDF2400_ERRATUM_0065 !! 2312 config MIPS_FP_SUPPORT
1258 bool "QDF2400 E0065: Incorrect GITS_T !! 2313 bool "Floating Point support" if EXPERT
1259 default y 2314 default y
1260 help 2315 help
1261 On Qualcomm Datacenter Technologies !! 2316 Select y to include support for floating point in the kernel
1262 ITE size incorrectly. The GITS_TYPE !! 2317 including initialization of FPU hardware, FP context save & restore
1263 been indicated as 16Bytes (0xf), no !! 2318 and emulation of an FPU where necessary. Without this support any
>> 2319 userland program attempting to use floating point instructions will
>> 2320 receive a SIGILL.
1264 2321
1265 If unsure, say Y. !! 2322 If you know that your userland will not attempt to use floating point
>> 2323 instructions then you can say n here to shrink the kernel a little.
1266 2324
1267 config QCOM_FALKOR_ERRATUM_E1041 !! 2325 If unsure, say y.
1268 bool "Falkor E1041: Speculative instr <<
1269 default y <<
1270 help <<
1271 Falkor CPU may speculatively fetch <<
1272 memory location when MMU translatio <<
1273 to SCTLR_ELn[M]=0. Prefix an ISB in <<
1274 2326
1275 If unsure, say Y. !! 2327 config CPU_R2300_FPU
>> 2328 bool
>> 2329 depends on MIPS_FP_SUPPORT
>> 2330 default y if CPU_R3000 || CPU_TX39XX
1276 2331
1277 config NVIDIA_CARMEL_CNP_ERRATUM !! 2332 config CPU_R3K_TLB
1278 bool "NVIDIA Carmel CNP: CNP on Carme !! 2333 bool
1279 default y <<
1280 help <<
1281 If CNP is enabled on Carmel cores, <<
1282 invalidate shared TLB entries insta <<
1283 on standard ARM cores. <<
1284 2334
1285 If unsure, say Y. !! 2335 config CPU_R4K_FPU
>> 2336 bool
>> 2337 depends on MIPS_FP_SUPPORT
>> 2338 default y if !CPU_R2300_FPU
1286 2339
1287 config ROCKCHIP_ERRATUM_3588001 !! 2340 config CPU_R4K_CACHE_TLB
1288 bool "Rockchip 3588001: GIC600 can no !! 2341 bool
>> 2342 default y if !(CPU_R3K_TLB || CPU_SB1 || CPU_CAVIUM_OCTEON)
>> 2343
>> 2344 config MIPS_MT_SMP
>> 2345 bool "MIPS MT SMP support (1 TC on each available VPE)"
1289 default y 2346 default y
1290 help !! 2347 depends on SYS_SUPPORTS_MULTITHREADING && !CPU_MIPSR6 && !CPU_MICROMIPS
1291 The Rockchip RK3588 GIC600 SoC inte !! 2348 select CPU_MIPSR2_IRQ_VI
1292 This means, that its sharability fe !! 2349 select CPU_MIPSR2_IRQ_EI
1293 is supported by the IP itself. !! 2350 select SYNC_R4K
>> 2351 select MIPS_MT
>> 2352 select SMP
>> 2353 select SMP_UP
>> 2354 select SYS_SUPPORTS_SMP
>> 2355 select SYS_SUPPORTS_SCHED_SMT
>> 2356 select MIPS_PERF_SHARED_TC_COUNTERS
>> 2357 help
>> 2358 This is a kernel model which is known as SMVP. This is supported
>> 2359 on cores with the MT ASE and uses the available VPEs to implement
>> 2360 virtual processors which supports SMP. This is equivalent to the
>> 2361 Intel Hyperthreading feature. For further information go to
>> 2362 <http://www.imgtec.com/mips/mips-multithreading.asp>.
1294 2363
1295 If unsure, say Y. !! 2364 config MIPS_MT
>> 2365 bool
1296 2366
1297 config SOCIONEXT_SYNQUACER_PREITS !! 2367 config SCHED_SMT
1298 bool "Socionext Synquacer: Workaround !! 2368 bool "SMT (multithreading) scheduler support"
1299 default y !! 2369 depends on SYS_SUPPORTS_SCHED_SMT
>> 2370 default n
1300 help 2371 help
1301 Socionext Synquacer SoCs implement !! 2372 SMT scheduler support improves the CPU scheduler's decision making
1302 MSI doorbell writes with non-zero v !! 2373 when dealing with MIPS MT enabled cores at a cost of slightly
>> 2374 increased overhead in some places. If unsure say N here.
1303 2375
1304 If unsure, say Y. !! 2376 config SYS_SUPPORTS_SCHED_SMT
>> 2377 bool
1305 2378
1306 endmenu # "ARM errata workarounds via the alt !! 2379 config SYS_SUPPORTS_MULTITHREADING
>> 2380 bool
1307 2381
1308 choice !! 2382 config MIPS_MT_FPAFF
1309 prompt "Page size" !! 2383 bool "Dynamic FPU affinity for FP-intensive threads"
1310 default ARM64_4K_PAGES !! 2384 default y
1311 help !! 2385 depends on MIPS_MT_SMP
1312 Page size (translation granule) con <<
1313 2386
1314 config ARM64_4K_PAGES !! 2387 config MIPSR2_TO_R6_EMULATOR
1315 bool "4KB" !! 2388 bool "MIPS R2-to-R6 emulator"
1316 select HAVE_PAGE_SIZE_4KB !! 2389 depends on CPU_MIPSR6
>> 2390 depends on MIPS_FP_SUPPORT
>> 2391 default y
1317 help 2392 help
1318 This feature enables 4KB pages supp !! 2393 Choose this option if you want to run non-R6 MIPS userland code.
>> 2394 Even if you say 'Y' here, the emulator will still be disabled by
>> 2395 default. You can enable it using the 'mipsr2emu' kernel option.
>> 2396 The only reason this is a build-time option is to save ~14K from the
>> 2397 final kernel image.
1319 2398
1320 config ARM64_16K_PAGES !! 2399 config SYS_SUPPORTS_VPE_LOADER
1321 bool "16KB" !! 2400 bool
1322 select HAVE_PAGE_SIZE_16KB !! 2401 depends on SYS_SUPPORTS_MULTITHREADING
1323 help 2402 help
1324 The system will use 16KB pages supp !! 2403 Indicates that the platform supports the VPE loader, and provides
1325 requires applications compiled with !! 2404 physical_memsize.
1326 aligned segments. <<
1327 2405
1328 config ARM64_64K_PAGES !! 2406 config MIPS_VPE_LOADER
1329 bool "64KB" !! 2407 bool "VPE loader support."
1330 select HAVE_PAGE_SIZE_64KB !! 2408 depends on SYS_SUPPORTS_VPE_LOADER && MODULES
>> 2409 select CPU_MIPSR2_IRQ_VI
>> 2410 select CPU_MIPSR2_IRQ_EI
>> 2411 select MIPS_MT
1331 help 2412 help
1332 This feature enables 64KB pages sup !! 2413 Includes a loader for loading an elf relocatable object
1333 allowing only two levels of page ta !! 2414 onto another VPE and running it.
1334 look-up. AArch32 emulation requires <<
1335 with 64K aligned segments. <<
1336 2415
1337 endchoice !! 2416 config MIPS_VPE_LOADER_CMP
>> 2417 bool
>> 2418 default "y"
>> 2419 depends on MIPS_VPE_LOADER && MIPS_CMP
1338 2420
1339 choice !! 2421 config MIPS_VPE_LOADER_MT
1340 prompt "Virtual address space size" !! 2422 bool
1341 default ARM64_VA_BITS_52 !! 2423 default "y"
1342 help !! 2424 depends on MIPS_VPE_LOADER && !MIPS_CMP
1343 Allows choosing one of multiple pos <<
1344 space sizes. The level of translati <<
1345 a combination of page size and virt <<
1346 <<
1347 config ARM64_VA_BITS_36 <<
1348 bool "36-bit" if EXPERT <<
1349 depends on PAGE_SIZE_16KB <<
1350 <<
1351 config ARM64_VA_BITS_39 <<
1352 bool "39-bit" <<
1353 depends on PAGE_SIZE_4KB <<
1354 <<
1355 config ARM64_VA_BITS_42 <<
1356 bool "42-bit" <<
1357 depends on PAGE_SIZE_64KB <<
1358 <<
1359 config ARM64_VA_BITS_47 <<
1360 bool "47-bit" <<
1361 depends on PAGE_SIZE_16KB <<
1362 <<
1363 config ARM64_VA_BITS_48 <<
1364 bool "48-bit" <<
1365 <<
1366 config ARM64_VA_BITS_52 <<
1367 bool "52-bit" <<
1368 depends on ARM64_PAN || !ARM64_SW_TTB <<
1369 help <<
1370 Enable 52-bit virtual addressing fo <<
1371 requested via a hint to mmap(). The <<
1372 virtual addresses for its own mappi <<
1373 this feature is available, otherwis <<
1374 <<
1375 NOTE: Enabling 52-bit virtual addre <<
1376 ARMv8.3 Pointer Authentication will <<
1377 reduced from 7 bits to 3 bits, whic <<
1378 impact on its susceptibility to bru <<
1379 2425
1380 If unsure, select 48-bit virtual ad !! 2426 config MIPS_VPE_LOADER_TOM
>> 2427 bool "Load VPE program into memory hidden from linux"
>> 2428 depends on MIPS_VPE_LOADER
>> 2429 default y
>> 2430 help
>> 2431 The loader can use memory that is present but has been hidden from
>> 2432 Linux using the kernel command line option "mem=xxMB". It's up to
>> 2433 you to ensure the amount you put in the option and the space your
>> 2434 program requires is less or equal to the amount physically present.
1381 2435
1382 endchoice !! 2436 config MIPS_VPE_APSP_API
>> 2437 bool "Enable support for AP/SP API (RTLX)"
>> 2438 depends on MIPS_VPE_LOADER
1383 2439
1384 config ARM64_FORCE_52BIT !! 2440 config MIPS_VPE_APSP_API_CMP
1385 bool "Force 52-bit virtual addresses !! 2441 bool
1386 depends on ARM64_VA_BITS_52 && EXPERT !! 2442 default "y"
1387 help !! 2443 depends on MIPS_VPE_APSP_API && MIPS_CMP
1388 For systems with 52-bit userspace V <<
1389 to maintain compatibility with olde <<
1390 unless a hint is supplied to mmap. <<
1391 <<
1392 This configuration option disables <<
1393 forces all userspace addresses to b <<
1394 should only enable this configurati <<
1395 memory management code. If unsure s <<
1396 2444
1397 config ARM64_VA_BITS !! 2445 config MIPS_VPE_APSP_API_MT
1398 int !! 2446 bool
1399 default 36 if ARM64_VA_BITS_36 !! 2447 default "y"
1400 default 39 if ARM64_VA_BITS_39 !! 2448 depends on MIPS_VPE_APSP_API && !MIPS_CMP
1401 default 42 if ARM64_VA_BITS_42 <<
1402 default 47 if ARM64_VA_BITS_47 <<
1403 default 48 if ARM64_VA_BITS_48 <<
1404 default 52 if ARM64_VA_BITS_52 <<
1405 2449
1406 choice !! 2450 config MIPS_CMP
1407 prompt "Physical address space size" !! 2451 bool "MIPS CMP framework support (DEPRECATED)"
1408 default ARM64_PA_BITS_48 !! 2452 depends on SYS_SUPPORTS_MIPS_CMP && !CPU_MIPSR6
>> 2453 select SMP
>> 2454 select SYNC_R4K
>> 2455 select SYS_SUPPORTS_SMP
>> 2456 select WEAK_ORDERING
>> 2457 default n
1409 help 2458 help
1410 Choose the maximum physical address !! 2459 Select this if you are using a bootloader which implements the "CMP
1411 support. !! 2460 framework" protocol (ie. YAMON) and want your kernel to make use of
>> 2461 its ability to start secondary CPUs.
>> 2462
>> 2463 Unless you have a specific need, you should use CONFIG_MIPS_CPS
>> 2464 instead of this.
>> 2465
>> 2466 config MIPS_CPS
>> 2467 bool "MIPS Coherent Processing System support"
>> 2468 depends on SYS_SUPPORTS_MIPS_CPS
>> 2469 select MIPS_CM
>> 2470 select MIPS_CPS_PM if HOTPLUG_CPU
>> 2471 select SMP
>> 2472 select SYNC_R4K if (CEVT_R4K || CSRC_R4K)
>> 2473 select SYS_SUPPORTS_HOTPLUG_CPU
>> 2474 select SYS_SUPPORTS_SCHED_SMT if CPU_MIPSR6
>> 2475 select SYS_SUPPORTS_SMP
>> 2476 select WEAK_ORDERING
>> 2477 help
>> 2478 Select this if you wish to run an SMP kernel across multiple cores
>> 2479 within a MIPS Coherent Processing System. When this option is
>> 2480 enabled the kernel will probe for other cores and boot them with
>> 2481 no external assistance. It is safe to enable this when hardware
>> 2482 support is unavailable.
1412 2483
1413 config ARM64_PA_BITS_48 !! 2484 config MIPS_CPS_PM
1414 bool "48-bit" !! 2485 depends on MIPS_CPS
1415 depends on ARM64_64K_PAGES || !ARM64_ !! 2486 bool
1416 <<
1417 config ARM64_PA_BITS_52 <<
1418 bool "52-bit" <<
1419 depends on ARM64_64K_PAGES || ARM64_V <<
1420 depends on ARM64_PAN || !ARM64_SW_TTB <<
1421 help <<
1422 Enable support for a 52-bit physica <<
1423 part of the ARMv8.2-LPA extension. <<
1424 <<
1425 With this enabled, the kernel will <<
1426 do not support ARMv8.2-LPA, but wit <<
1427 minor performance overhead). <<
1428 2487
1429 endchoice !! 2488 config MIPS_CM
>> 2489 bool
>> 2490 select MIPS_CPC
1430 2491
1431 config ARM64_PA_BITS !! 2492 config MIPS_CPC
1432 int !! 2493 bool
1433 default 48 if ARM64_PA_BITS_48 <<
1434 default 52 if ARM64_PA_BITS_52 <<
1435 2494
1436 config ARM64_LPA2 !! 2495 config SB1_PASS_2_WORKAROUNDS
1437 def_bool y !! 2496 bool
1438 depends on ARM64_PA_BITS_52 && !ARM64 !! 2497 depends on CPU_SB1 && (CPU_SB1_PASS_2_2 || CPU_SB1_PASS_2)
>> 2498 default y
>> 2499
>> 2500 config SB1_PASS_2_1_WORKAROUNDS
>> 2501 bool
>> 2502 depends on CPU_SB1 && CPU_SB1_PASS_2
>> 2503 default y
1439 2504
1440 choice 2505 choice
1441 prompt "Endianness" !! 2506 prompt "SmartMIPS or microMIPS ASE support"
1442 default CPU_LITTLE_ENDIAN <<
1443 help <<
1444 Select the endianness of data acces <<
1445 applications will need to be compil <<
1446 that is selected here. <<
1447 2507
1448 config CPU_BIG_ENDIAN !! 2508 config CPU_NEEDS_NO_SMARTMIPS_OR_MICROMIPS
1449 bool "Build big-endian kernel" !! 2509 bool "None"
1450 # https://github.com/llvm/llvm-projec <<
1451 depends on AS_IS_GNU || AS_VERSION >= <<
1452 help 2510 help
1453 Say Y if you plan on running a kern !! 2511 Select this if you want neither microMIPS nor SmartMIPS support
1454 2512
1455 config CPU_LITTLE_ENDIAN !! 2513 config CPU_HAS_SMARTMIPS
1456 bool "Build little-endian kernel" !! 2514 depends on SYS_SUPPORTS_SMARTMIPS
>> 2515 bool "SmartMIPS"
>> 2516 help
>> 2517 SmartMIPS is a extension of the MIPS32 architecture aimed at
>> 2518 increased security at both hardware and software level for
>> 2519 smartcards. Enabling this option will allow proper use of the
>> 2520 SmartMIPS instructions by Linux applications. However a kernel with
>> 2521 this option will not work on a MIPS core without SmartMIPS core. If
>> 2522 you don't know you probably don't have SmartMIPS and should say N
>> 2523 here.
>> 2524
>> 2525 config CPU_MICROMIPS
>> 2526 depends on 32BIT && SYS_SUPPORTS_MICROMIPS && !CPU_MIPSR6
>> 2527 bool "microMIPS"
1457 help 2528 help
1458 Say Y if you plan on running a kern !! 2529 When this option is enabled the kernel will be built using the
1459 This is usually the case for distri !! 2530 microMIPS ISA
1460 2531
1461 endchoice 2532 endchoice
1462 2533
1463 config SCHED_MC !! 2534 config CPU_HAS_MSA
1464 bool "Multi-core scheduler support" !! 2535 bool "Support for the MIPS SIMD Architecture"
1465 help !! 2536 depends on CPU_SUPPORTS_MSA
1466 Multi-core scheduler support improv !! 2537 depends on MIPS_FP_SUPPORT
1467 making when dealing with multi-core !! 2538 depends on 64BIT || MIPS_O32_FP64_SUPPORT
1468 increased overhead in some places. !! 2539 help
>> 2540 MIPS SIMD Architecture (MSA) introduces 128 bit wide vector registers
>> 2541 and a set of SIMD instructions to operate on them. When this option
>> 2542 is enabled the kernel will support allocating & switching MSA
>> 2543 vector register contexts. If you know that your kernel will only be
>> 2544 running on CPUs which do not support MSA or that your userland will
>> 2545 not be making use of it then you may wish to say N here to reduce
>> 2546 the size & complexity of your kernel.
1469 2547
1470 config SCHED_CLUSTER !! 2548 If unsure, say Y.
1471 bool "Cluster scheduler support" <<
1472 help <<
1473 Cluster scheduler support improves <<
1474 making when dealing with machines t <<
1475 Cluster usually means a couple of C <<
1476 by sharing mid-level caches, last-l <<
1477 busses. <<
1478 2549
1479 config SCHED_SMT !! 2550 config CPU_HAS_WB
1480 bool "SMT scheduler support" !! 2551 bool
1481 help <<
1482 Improves the CPU scheduler's decisi <<
1483 MultiThreading at a cost of slightl <<
1484 places. If unsure say N here. <<
1485 2552
1486 config NR_CPUS !! 2553 config XKS01
1487 int "Maximum number of CPUs (2-4096)" !! 2554 bool
1488 range 2 4096 <<
1489 default "512" <<
1490 2555
1491 config HOTPLUG_CPU !! 2556 config CPU_HAS_DIEI
1492 bool "Support for hot-pluggable CPUs" !! 2557 depends on !CPU_DIEI_BROKEN
1493 select GENERIC_IRQ_MIGRATION !! 2558 bool
1494 help <<
1495 Say Y here to experiment with turni <<
1496 can be controlled through /sys/devi <<
1497 2559
1498 # Common NUMA Features !! 2560 config CPU_DIEI_BROKEN
1499 config NUMA !! 2561 bool
1500 bool "NUMA Memory Allocation and Sche <<
1501 select GENERIC_ARCH_NUMA <<
1502 select OF_NUMA <<
1503 select HAVE_SETUP_PER_CPU_AREA <<
1504 select NEED_PER_CPU_EMBED_FIRST_CHUNK <<
1505 select NEED_PER_CPU_PAGE_FIRST_CHUNK <<
1506 select USE_PERCPU_NUMA_NODE_ID <<
1507 help <<
1508 Enable NUMA (Non-Uniform Memory Acc <<
1509 <<
1510 The kernel will try to allocate mem <<
1511 local memory of the CPU and add som <<
1512 NUMA awareness to the kernel. <<
1513 2562
1514 config NODES_SHIFT !! 2563 config CPU_HAS_RIXI
1515 int "Maximum NUMA Nodes (as a power o !! 2564 bool
1516 range 1 10 <<
1517 default "4" <<
1518 depends on NUMA <<
1519 help <<
1520 Specify the maximum number of NUMA <<
1521 system. Increases memory reserved <<
1522 2565
1523 source "kernel/Kconfig.hz" !! 2566 config CPU_NO_LOAD_STORE_LR
>> 2567 bool
>> 2568 help
>> 2569 CPU lacks support for unaligned load and store instructions:
>> 2570 LWL, LWR, SWL, SWR (Load/store word left/right).
>> 2571 LDL, LDR, SDL, SDR (Load/store doubleword left/right, for 64bit
>> 2572 systems).
1524 2573
1525 config ARCH_SPARSEMEM_ENABLE !! 2574 #
1526 def_bool y !! 2575 # Vectored interrupt mode is an R2 feature
1527 select SPARSEMEM_VMEMMAP_ENABLE !! 2576 #
1528 select SPARSEMEM_VMEMMAP !! 2577 config CPU_MIPSR2_IRQ_VI
>> 2578 bool
1529 2579
1530 config HW_PERF_EVENTS !! 2580 #
1531 def_bool y !! 2581 # Extended interrupt mode is an R2 feature
1532 depends on ARM_PMU !! 2582 #
>> 2583 config CPU_MIPSR2_IRQ_EI
>> 2584 bool
1533 2585
1534 # Supported by clang >= 7.0 or GCC >= 12.0.0 !! 2586 config CPU_HAS_SYNC
1535 config CC_HAVE_SHADOW_CALL_STACK !! 2587 bool
1536 def_bool $(cc-option, -fsanitize=shad !! 2588 depends on !CPU_R3000
>> 2589 default y
1537 2590
1538 config PARAVIRT !! 2591 #
1539 bool "Enable paravirtualization code" !! 2592 # CPU non-features
1540 help !! 2593 #
1541 This changes the kernel so it can m !! 2594 config CPU_DADDI_WORKAROUNDS
1542 under a hypervisor, potentially imp !! 2595 bool
1543 over full virtualization. <<
1544 2596
1545 config PARAVIRT_TIME_ACCOUNTING !! 2597 config CPU_R4000_WORKAROUNDS
1546 bool "Paravirtual steal time accounti !! 2598 bool
1547 select PARAVIRT !! 2599 select CPU_R4400_WORKAROUNDS
1548 help <<
1549 Select this option to enable fine g <<
1550 accounting. Time spent executing ot <<
1551 the current vCPU is discounted from <<
1552 that, there can be a small performa <<
1553 2600
1554 If in doubt, say N here. !! 2601 config CPU_R4400_WORKAROUNDS
>> 2602 bool
1555 2603
1556 config ARCH_SUPPORTS_KEXEC !! 2604 config CPU_R4X00_BUGS64
1557 def_bool PM_SLEEP_SMP !! 2605 bool
>> 2606 default y if SYS_HAS_CPU_R4X00 && 64BIT && (TARGET_ISA_REV < 1)
1558 2607
1559 config ARCH_SUPPORTS_KEXEC_FILE !! 2608 config MIPS_ASID_SHIFT
1560 def_bool y !! 2609 int
>> 2610 default 6 if CPU_R3000 || CPU_TX39XX
>> 2611 default 0
1561 2612
1562 config ARCH_SELECTS_KEXEC_FILE !! 2613 config MIPS_ASID_BITS
1563 def_bool y !! 2614 int
1564 depends on KEXEC_FILE !! 2615 default 0 if MIPS_ASID_BITS_VARIABLE
1565 select HAVE_IMA_KEXEC if IMA !! 2616 default 6 if CPU_R3000 || CPU_TX39XX
>> 2617 default 8
1566 2618
1567 config ARCH_SUPPORTS_KEXEC_SIG !! 2619 config MIPS_ASID_BITS_VARIABLE
1568 def_bool y !! 2620 bool
1569 2621
1570 config ARCH_SUPPORTS_KEXEC_IMAGE_VERIFY_SIG !! 2622 config MIPS_CRC_SUPPORT
1571 def_bool y !! 2623 bool
1572 2624
1573 config ARCH_DEFAULT_KEXEC_IMAGE_VERIFY_SIG !! 2625 #
1574 def_bool y !! 2626 # - Highmem only makes sense for the 32-bit kernel.
>> 2627 # - The current highmem code will only work properly on physically indexed
>> 2628 # caches such as R3000, SB1, R7000 or those that look like they're virtually
>> 2629 # indexed such as R4000/R4400 SC and MC versions or R10000. So for the
>> 2630 # moment we protect the user and offer the highmem option only on machines
>> 2631 # where it's known to be safe. This will not offer highmem on a few systems
>> 2632 # such as MIPS32 and MIPS64 CPUs which may have virtual and physically
>> 2633 # indexed CPUs but we're playing safe.
>> 2634 # - We use SYS_SUPPORTS_HIGHMEM to offer highmem only for systems where we
>> 2635 # know they might have memory configurations that could make use of highmem
>> 2636 # support.
>> 2637 #
>> 2638 config HIGHMEM
>> 2639 bool "High Memory Support"
>> 2640 depends on 32BIT && CPU_SUPPORTS_HIGHMEM && SYS_SUPPORTS_HIGHMEM && !CPU_MIPS32_3_5_EVA
1575 2641
1576 config ARCH_SUPPORTS_CRASH_DUMP !! 2642 config CPU_SUPPORTS_HIGHMEM
1577 def_bool y !! 2643 bool
1578 2644
1579 config ARCH_HAS_GENERIC_CRASHKERNEL_RESERVATI !! 2645 config SYS_SUPPORTS_HIGHMEM
1580 def_bool CRASH_RESERVE !! 2646 bool
1581 2647
1582 config TRANS_TABLE !! 2648 config SYS_SUPPORTS_SMARTMIPS
1583 def_bool y !! 2649 bool
1584 depends on HIBERNATION || KEXEC_CORE <<
1585 2650
1586 config XEN_DOM0 !! 2651 config SYS_SUPPORTS_MICROMIPS
1587 def_bool y !! 2652 bool
1588 depends on XEN <<
1589 2653
1590 config XEN !! 2654 config SYS_SUPPORTS_MIPS16
1591 bool "Xen guest support on ARM64" !! 2655 bool
1592 depends on ARM64 && OF <<
1593 select SWIOTLB_XEN <<
1594 select PARAVIRT <<
1595 help 2656 help
1596 Say Y if you want to run Linux in a !! 2657 This option must be set if a kernel might be executed on a MIPS16-
>> 2658 enabled CPU even if MIPS16 is not actually being used. In other
>> 2659 words, it makes the kernel MIPS16-tolerant.
1597 2660
1598 # include/linux/mmzone.h requires the followi !! 2661 config CPU_SUPPORTS_MSA
1599 # !! 2662 bool
1600 # MAX_PAGE_ORDER + PAGE_SHIFT <= SECTION_SI <<
1601 # <<
1602 # so the maximum value of MAX_PAGE_ORDER is S <<
1603 # <<
1604 # | SECTION_SIZE_BITS | PAGE_SHIFT | m <<
1605 # ----+-------------------+--------------+--- <<
1606 # 4K | 27 | 12 | <<
1607 # 16K | 27 | 14 | <<
1608 # 64K | 29 | 16 | <<
1609 config ARCH_FORCE_MAX_ORDER <<
1610 int <<
1611 default "13" if ARM64_64K_PAGES <<
1612 default "11" if ARM64_16K_PAGES <<
1613 default "10" <<
1614 help <<
1615 The kernel page allocator limits th <<
1616 contiguous allocations. The limit i <<
1617 defines the maximal power of two of <<
1618 allocated as a single contiguous bl <<
1619 overriding the default setting when <<
1620 large blocks of physically contiguo <<
1621 <<
1622 The maximal size of allocation cann <<
1623 section, so the value of MAX_PAGE_O <<
1624 2663
1625 MAX_PAGE_ORDER + PAGE_SHIFT <= SE !! 2664 config ARCH_FLATMEM_ENABLE
>> 2665 def_bool y
>> 2666 depends on !NUMA && !CPU_LOONGSON2EF
1626 2667
1627 Don't change if unsure. !! 2668 config ARCH_SPARSEMEM_ENABLE
>> 2669 bool
>> 2670 select SPARSEMEM_STATIC if !SGI_IP27
1628 2671
1629 config UNMAP_KERNEL_AT_EL0 !! 2672 config NUMA
1630 bool "Unmap kernel when running in us !! 2673 bool "NUMA Support"
1631 default y !! 2674 depends on SYS_SUPPORTS_NUMA
1632 help 2675 help
1633 Speculation attacks against some hi !! 2676 Say Y to compile the kernel to support NUMA (Non-Uniform Memory
1634 be used to bypass MMU permission ch !! 2677 Access). This option improves performance on systems with more
1635 userspace. This can be defended aga !! 2678 than two nodes; on two node systems it is generally better to
1636 when running in userspace, mapping !! 2679 leave it disabled; on single node systems disable this option
1637 via a trampoline page in the vector !! 2680 disabled.
1638 2681
1639 If unsure, say Y. !! 2682 config SYS_SUPPORTS_NUMA
>> 2683 bool
1640 2684
1641 config MITIGATE_SPECTRE_BRANCH_HISTORY !! 2685 config HAVE_SETUP_PER_CPU_AREA
1642 bool "Mitigate Spectre style attacks !! 2686 def_bool y
1643 default y !! 2687 depends on NUMA
1644 help <<
1645 Speculation attacks against some hi <<
1646 make use of branch history to influ <<
1647 When taking an exception from user- <<
1648 or a firmware call overwrites the b <<
1649 2688
1650 config RODATA_FULL_DEFAULT_ENABLED !! 2689 config NEED_PER_CPU_EMBED_FIRST_CHUNK
1651 bool "Apply r/o permissions of VM are !! 2690 def_bool y
1652 default y !! 2691 depends on NUMA
1653 help <<
1654 Apply read-only attributes of VM ar <<
1655 the backing pages as well. This pre <<
1656 from being modified (inadvertently <<
1657 mapping of the same memory page. Th <<
1658 be turned off at runtime by passing <<
1659 with rodata=full if this option is <<
1660 <<
1661 This requires the linear region to <<
1662 which may adversely affect performa <<
1663 <<
1664 config ARM64_SW_TTBR0_PAN <<
1665 bool "Emulate Privileged Access Never <<
1666 depends on !KCSAN <<
1667 help <<
1668 Enabling this option prevents the k <<
1669 user-space memory directly by point <<
1670 zeroed area and reserved ASID. The <<
1671 restore the valid TTBR0_EL1 tempora <<
1672 2692
1673 config ARM64_TAGGED_ADDR_ABI !! 2693 config RELOCATABLE
1674 bool "Enable the tagged user addresse !! 2694 bool "Relocatable kernel"
1675 default y !! 2695 depends on SYS_SUPPORTS_RELOCATABLE && (CPU_MIPS32_R2 || CPU_MIPS64_R2 || CPU_MIPS32_R6 || CPU_MIPS64_R6 || CAVIUM_OCTEON_SOC)
1676 help 2696 help
1677 When this option is enabled, user a !! 2697 This builds a kernel image that retains relocation information
1678 relaxed ABI via prctl() allowing ta !! 2698 so it can be loaded someplace besides the default 1MB.
1679 to system calls as pointer argument !! 2699 The relocations make the kernel binary about 15% larger,
1680 Documentation/arch/arm64/tagged-add !! 2700 but are discarded at runtime
1681 !! 2701
1682 menuconfig COMPAT !! 2702 config RELOCATION_TABLE_SIZE
1683 bool "Kernel support for 32-bit EL0" !! 2703 hex "Relocation table size"
1684 depends on ARM64_4K_PAGES || EXPERT !! 2704 depends on RELOCATABLE
1685 select HAVE_UID16 !! 2705 range 0x0 0x01000000
1686 select OLD_SIGSUSPEND3 !! 2706 default "0x00100000"
1687 select COMPAT_OLD_SIGACTION !! 2707 ---help---
1688 help !! 2708 A table of relocation data will be appended to the kernel binary
1689 This option enables support for a 3 !! 2709 and parsed at boot to fix up the relocated kernel.
1690 kernel at EL1. AArch32-specific com <<
1691 the user helper functions, VFP supp <<
1692 handled appropriately by the kernel <<
1693 <<
1694 If you use a page size other than 4 <<
1695 that you will only be able to execu <<
1696 with page size aligned segments. <<
1697 2710
1698 If you want to execute 32-bit users !! 2711 This option allows the amount of space reserved for the table to be
>> 2712 adjusted, although the default of 1Mb should be ok in most cases.
1699 2713
1700 if COMPAT !! 2714 The build will fail and a valid size suggested if this is too small.
1701 2715
1702 config KUSER_HELPERS !! 2716 If unsure, leave at the default value.
1703 bool "Enable kuser helpers page for 3 <<
1704 default y <<
1705 help <<
1706 Warning: disabling this option may <<
1707 2717
1708 Provide kuser helpers to compat tas !! 2718 config RANDOMIZE_BASE
1709 helper code to userspace in read on !! 2719 bool "Randomize the address of the kernel image"
1710 to allow userspace to be independen !! 2720 depends on RELOCATABLE
1711 the system. This permits binaries t !! 2721 ---help---
1712 to ARMv8 without modification. !! 2722 Randomizes the physical and virtual address at which the
1713 !! 2723 kernel image is loaded, as a security feature that
1714 See Documentation/arch/arm/kernel_u !! 2724 deters exploit attempts relying on knowledge of the location
1715 !! 2725 of kernel internals.
1716 However, the fixed address nature o <<
1717 by ROP (return orientated programmi <<
1718 exploits. <<
1719 <<
1720 If all of the binaries and librarie <<
1721 are built specifically for your pla <<
1722 these helpers, then you can turn th <<
1723 such exploits. However, in that cas <<
1724 relying on those helpers is run, it <<
1725 <<
1726 Say N here only if you are absolute <<
1727 need these helpers; otherwise, the <<
1728 <<
1729 config COMPAT_VDSO <<
1730 bool "Enable vDSO for 32-bit applicat <<
1731 depends on !CPU_BIG_ENDIAN <<
1732 depends on (CC_IS_CLANG && LD_IS_LLD) <<
1733 select GENERIC_COMPAT_VDSO <<
1734 default y <<
1735 help <<
1736 Place in the process address space <<
1737 ELF shared object providing fast im <<
1738 and clock_gettime. <<
1739 <<
1740 You must have a 32-bit build of gli <<
1741 to seamlessly take advantage of thi <<
1742 <<
1743 config THUMB2_COMPAT_VDSO <<
1744 bool "Compile the 32-bit vDSO for Thu <<
1745 depends on COMPAT_VDSO <<
1746 default y <<
1747 help <<
1748 Compile the compat vDSO with '-mthu <<
1749 otherwise with '-marm'. <<
1750 <<
1751 config COMPAT_ALIGNMENT_FIXUPS <<
1752 bool "Fix up misaligned multi-word lo <<
1753 <<
1754 menuconfig ARMV8_DEPRECATED <<
1755 bool "Emulate deprecated/obsolete ARM <<
1756 depends on SYSCTL <<
1757 help <<
1758 Legacy software support may require <<
1759 that have been deprecated or obsole <<
1760 2726
1761 Enable this config to enable select !! 2727 Entropy is generated using any coprocessor 0 registers available.
1762 features. <<
1763 2728
1764 If unsure, say Y !! 2729 The kernel will be offset by up to RANDOMIZE_BASE_MAX_OFFSET.
1765 2730
1766 if ARMV8_DEPRECATED !! 2731 If unsure, say N.
1767 2732
1768 config SWP_EMULATION !! 2733 config RANDOMIZE_BASE_MAX_OFFSET
1769 bool "Emulate SWP/SWPB instructions" !! 2734 hex "Maximum kASLR offset" if EXPERT
1770 help !! 2735 depends on RANDOMIZE_BASE
1771 ARMv8 obsoletes the use of A32 SWP/ !! 2736 range 0x0 0x40000000 if EVA || 64BIT
1772 they are always undefined. Say Y he !! 2737 range 0x0 0x08000000
1773 emulation of these instructions for !! 2738 default "0x01000000"
1774 This feature can be controlled at r !! 2739 ---help---
1775 sysctl which is disabled by default !! 2740 When kASLR is active, this provides the maximum offset that will
>> 2741 be applied to the kernel image. It should be set according to the
>> 2742 amount of physical RAM available in the target system minus
>> 2743 PHYSICAL_START and must be a power of 2.
1776 2744
1777 In some older versions of glibc [<= !! 2745 This is limited by the size of KSEG0, 256Mb on 32-bit or 1Gb with
1778 trylock() operations with the assum !! 2746 EVA or 64-bit. The default is 16Mb.
1779 be preempted. This invalid assumpti <<
1780 with SWP emulation enabled, leading <<
1781 application. <<
1782 2747
1783 NOTE: when accessing uncached share !! 2748 config NODES_SHIFT
1784 on an external transaction monitori !! 2749 int
1785 monitor to maintain update atomicit !! 2750 default "6"
1786 implement a global monitor, this op !! 2751 depends on NEED_MULTIPLE_NODES
1787 perform SWP operations to uncached <<
1788 2752
1789 If unsure, say Y !! 2753 config HW_PERF_EVENTS
>> 2754 bool "Enable hardware performance counter support for perf events"
>> 2755 depends on PERF_EVENTS && !OPROFILE && (CPU_MIPS32 || CPU_MIPS64 || CPU_R10000 || CPU_SB1 || CPU_CAVIUM_OCTEON || CPU_XLP || CPU_LOONGSON64)
>> 2756 default y
>> 2757 help
>> 2758 Enable hardware performance counter support for perf events. If
>> 2759 disabled, perf events will use software events only.
1790 2760
1791 config CP15_BARRIER_EMULATION !! 2761 config SMP
1792 bool "Emulate CP15 Barrier instructio !! 2762 bool "Multi-Processing support"
>> 2763 depends on SYS_SUPPORTS_SMP
1793 help 2764 help
1794 The CP15 barrier instructions - CP1 !! 2765 This enables support for systems with more than one CPU. If you have
1795 CP15DMB - are deprecated in ARMv8 ( !! 2766 a system with only one CPU, say N. If you have a system with more
1796 strongly recommended to use the ISB !! 2767 than one CPU, say Y.
1797 instructions instead. !! 2768
>> 2769 If you say N here, the kernel will run on uni- and multiprocessor
>> 2770 machines, but will use only one CPU of a multiprocessor machine. If
>> 2771 you say Y here, the kernel will run on many, but not all,
>> 2772 uniprocessor machines. On a uniprocessor machine, the kernel
>> 2773 will run faster if you say N here.
1798 2774
1799 Say Y here to enable software emula !! 2775 People using multiprocessor machines who say Y here should also say
1800 instructions for AArch32 userspace !! 2776 Y to "Enhanced Real Time Clock Support", below.
1801 enabled, CP15 barrier usage is trac <<
1802 identify software that needs updati <<
1803 controlled at runtime with the abi. <<
1804 2777
1805 If unsure, say Y !! 2778 See also the SMP-HOWTO available at
>> 2779 <http://www.tldp.org/docs.html#howto>.
1806 2780
1807 config SETEND_EMULATION !! 2781 If you don't know what to do here, say N.
1808 bool "Emulate SETEND instruction" !! 2782
>> 2783 config HOTPLUG_CPU
>> 2784 bool "Support for hot-pluggable CPUs"
>> 2785 depends on SMP && SYS_SUPPORTS_HOTPLUG_CPU
1809 help 2786 help
1810 The SETEND instruction alters the d !! 2787 Say Y here to allow turning CPUs off and on. CPUs can be
1811 AArch32 EL0, and is deprecated in A !! 2788 controlled through /sys/devices/system/cpu.
>> 2789 (Note: power management support will enable this option
>> 2790 automatically on SMP systems. )
>> 2791 Say N if you want to disable CPU hotplug.
1812 2792
1813 Say Y here to enable software emula !! 2793 config SMP_UP
1814 for AArch32 userspace code. This fe !! 2794 bool
1815 at runtime with the abi.setend sysc <<
1816 2795
1817 Note: All the cpus on the system mu !! 2796 config SYS_SUPPORTS_MIPS_CMP
1818 for this feature to be enabled. If !! 2797 bool
1819 endian - is hotplugged in after thi <<
1820 be unexpected results in the applic <<
1821 2798
1822 If unsure, say Y !! 2799 config SYS_SUPPORTS_MIPS_CPS
1823 endif # ARMV8_DEPRECATED !! 2800 bool
1824 2801
1825 endif # COMPAT !! 2802 config SYS_SUPPORTS_SMP
>> 2803 bool
1826 2804
1827 menu "ARMv8.1 architectural features" !! 2805 config NR_CPUS_DEFAULT_4
>> 2806 bool
1828 2807
1829 config ARM64_HW_AFDBM !! 2808 config NR_CPUS_DEFAULT_8
1830 bool "Support for hardware updates of !! 2809 bool
1831 default y <<
1832 help <<
1833 The ARMv8.1 architecture extensions <<
1834 hardware updates of the access and <<
1835 table entries. When enabled in TCR_ <<
1836 capable processors, accesses to pag <<
1837 set this bit instead of raising an <<
1838 Similarly, writes to read-only page <<
1839 clear the read-only bit (AP[2]) ins <<
1840 permission fault. <<
1841 <<
1842 Kernels built with this configurati <<
1843 to work on pre-ARMv8.1 hardware and <<
1844 minimal. If unsure, say Y. <<
1845 2810
1846 config ARM64_PAN !! 2811 config NR_CPUS_DEFAULT_16
1847 bool "Enable support for Privileged A !! 2812 bool
1848 default y <<
1849 help <<
1850 Privileged Access Never (PAN; part <<
1851 prevents the kernel or hypervisor f <<
1852 memory directly. <<
1853 2813
1854 Choosing this option will cause any !! 2814 config NR_CPUS_DEFAULT_32
1855 copy_to_user et al) memory access t !! 2815 bool
1856 2816
1857 The feature is detected at runtime, !! 2817 config NR_CPUS_DEFAULT_64
1858 instruction if the cpu does not imp !! 2818 bool
1859 2819
1860 config AS_HAS_LSE_ATOMICS !! 2820 config NR_CPUS
1861 def_bool $(as-instr,.arch_extension l !! 2821 int "Maximum number of CPUs (2-256)"
>> 2822 range 2 256
>> 2823 depends on SMP
>> 2824 default "4" if NR_CPUS_DEFAULT_4
>> 2825 default "8" if NR_CPUS_DEFAULT_8
>> 2826 default "16" if NR_CPUS_DEFAULT_16
>> 2827 default "32" if NR_CPUS_DEFAULT_32
>> 2828 default "64" if NR_CPUS_DEFAULT_64
>> 2829 help
>> 2830 This allows you to specify the maximum number of CPUs which this
>> 2831 kernel will support. The maximum supported value is 32 for 32-bit
>> 2832 kernel and 64 for 64-bit kernels; the minimum value which makes
>> 2833 sense is 1 for Qemu (useful only for kernel debugging purposes)
>> 2834 and 2 for all others.
>> 2835
>> 2836 This is purely to save memory - each supported CPU adds
>> 2837 approximately eight kilobytes to the kernel image. For best
>> 2838 performance should round up your number of processors to the next
>> 2839 power of two.
1862 2840
1863 config ARM64_LSE_ATOMICS !! 2841 config MIPS_PERF_SHARED_TC_COUNTERS
1864 bool 2842 bool
1865 default ARM64_USE_LSE_ATOMICS <<
1866 depends on AS_HAS_LSE_ATOMICS <<
1867 2843
1868 config ARM64_USE_LSE_ATOMICS !! 2844 config MIPS_NR_CPU_NR_MAP_1024
1869 bool "Atomic instructions" !! 2845 bool
1870 default y !! 2846
1871 help !! 2847 config MIPS_NR_CPU_NR_MAP
1872 As part of the Large System Extensi !! 2848 int
1873 atomic instructions that are design !! 2849 depends on SMP
1874 very large systems. !! 2850 default 1024 if MIPS_NR_CPU_NR_MAP_1024
>> 2851 default NR_CPUS if !MIPS_NR_CPU_NR_MAP_1024
1875 2852
1876 Say Y here to make use of these ins !! 2853 #
1877 atomic routines. This incurs a smal !! 2854 # Timer Interrupt Frequency Configuration
1878 not support these instructions and !! 2855 #
1879 built with binutils >= 2.25 in orde <<
1880 to be used. <<
1881 2856
1882 endmenu # "ARMv8.1 architectural features" !! 2857 choice
>> 2858 prompt "Timer frequency"
>> 2859 default HZ_250
>> 2860 help
>> 2861 Allows the configuration of the timer frequency.
1883 2862
1884 menu "ARMv8.2 architectural features" !! 2863 config HZ_24
>> 2864 bool "24 HZ" if SYS_SUPPORTS_24HZ || SYS_SUPPORTS_ARBIT_HZ
1885 2865
1886 config AS_HAS_ARMV8_2 !! 2866 config HZ_48
1887 def_bool $(cc-option,-Wa$(comma)-marc !! 2867 bool "48 HZ" if SYS_SUPPORTS_48HZ || SYS_SUPPORTS_ARBIT_HZ
1888 2868
1889 config AS_HAS_SHA3 !! 2869 config HZ_100
1890 def_bool $(as-instr,.arch armv8.2-a+s !! 2870 bool "100 HZ" if SYS_SUPPORTS_100HZ || SYS_SUPPORTS_ARBIT_HZ
1891 2871
1892 config ARM64_PMEM !! 2872 config HZ_128
1893 bool "Enable support for persistent m !! 2873 bool "128 HZ" if SYS_SUPPORTS_128HZ || SYS_SUPPORTS_ARBIT_HZ
1894 select ARCH_HAS_PMEM_API <<
1895 select ARCH_HAS_UACCESS_FLUSHCACHE <<
1896 help <<
1897 Say Y to enable support for the per <<
1898 ARMv8.2 DCPoP feature. <<
1899 2874
1900 The feature is detected at runtime, !! 2875 config HZ_250
1901 operations if DC CVAP is not suppor !! 2876 bool "250 HZ" if SYS_SUPPORTS_250HZ || SYS_SUPPORTS_ARBIT_HZ
1902 DC CVAP itself if the system does n <<
1903 2877
1904 config ARM64_RAS_EXTN !! 2878 config HZ_256
1905 bool "Enable support for RAS CPU Exte !! 2879 bool "256 HZ" if SYS_SUPPORTS_256HZ || SYS_SUPPORTS_ARBIT_HZ
1906 default y <<
1907 help <<
1908 CPUs that support the Reliability, <<
1909 (RAS) Extensions, part of ARMv8.2 a <<
1910 errors, classify them and report th <<
1911 <<
1912 On CPUs with these extensions syste <<
1913 barriers to determine if faults are <<
1914 classification from a new set of re <<
1915 <<
1916 Selecting this feature will allow t <<
1917 and access the new registers if the <<
1918 Platform RAS features may additiona <<
1919 2880
1920 config ARM64_CNP !! 2881 config HZ_1000
1921 bool "Enable support for Common Not P !! 2882 bool "1000 HZ" if SYS_SUPPORTS_1000HZ || SYS_SUPPORTS_ARBIT_HZ
1922 default y <<
1923 depends on ARM64_PAN || !ARM64_SW_TTB <<
1924 help <<
1925 Common Not Private (CNP) allows tra <<
1926 be shared between different PEs in <<
1927 domain, so the hardware can use thi <<
1928 caching of such entries in the TLB. <<
1929 2883
1930 Selecting this option allows the CN !! 2884 config HZ_1024
1931 at runtime, and does not affect PEs !! 2885 bool "1024 HZ" if SYS_SUPPORTS_1024HZ || SYS_SUPPORTS_ARBIT_HZ
1932 this feature. <<
1933 2886
1934 endmenu # "ARMv8.2 architectural features" !! 2887 endchoice
1935 2888
1936 menu "ARMv8.3 architectural features" !! 2889 config SYS_SUPPORTS_24HZ
>> 2890 bool
1937 2891
1938 config ARM64_PTR_AUTH !! 2892 config SYS_SUPPORTS_48HZ
1939 bool "Enable support for pointer auth !! 2893 bool
1940 default y <<
1941 help <<
1942 Pointer authentication (part of the <<
1943 instructions for signing and authen <<
1944 keys, which can be used to mitigate <<
1945 and other attacks. <<
1946 <<
1947 This option enables these instructi <<
1948 Choosing this option will cause the <<
1949 for each process at exec() time, wi <<
1950 context-switched along with the pro <<
1951 <<
1952 The feature is detected at runtime. <<
1953 hardware it will not be advertised <<
1954 be enabled. <<
1955 <<
1956 If the feature is present on the bo <<
1957 the late CPU will be parked. Also, <<
1958 address auth and the late CPU has t <<
1959 but with the feature disabled. On s <<
1960 not be selected. <<
1961 2894
1962 config ARM64_PTR_AUTH_KERNEL !! 2895 config SYS_SUPPORTS_100HZ
1963 bool "Use pointer authentication for !! 2896 bool
1964 default y <<
1965 depends on ARM64_PTR_AUTH <<
1966 depends on (CC_HAS_SIGN_RETURN_ADDRES <<
1967 # Modern compilers insert a .note.gnu <<
1968 # which is only understood by binutil <<
1969 depends on LD_IS_LLD || LD_VERSION >= <<
1970 depends on !CC_IS_CLANG || AS_HAS_CFI <<
1971 depends on (!FUNCTION_GRAPH_TRACER || <<
1972 help <<
1973 If the compiler supports the -mbran <<
1974 -msign-return-address flag (e.g. GC <<
1975 will cause the kernel itself to be <<
1976 protection. In this case, and if th <<
1977 support pointer authentication, the <<
1978 disabled with minimal loss of prote <<
1979 <<
1980 This feature works with FUNCTION_GR <<
1981 DYNAMIC_FTRACE_WITH_ARGS is enabled <<
1982 <<
1983 config CC_HAS_BRANCH_PROT_PAC_RET <<
1984 # GCC 9 or later, clang 8 or later <<
1985 def_bool $(cc-option,-mbranch-protect <<
1986 <<
1987 config CC_HAS_SIGN_RETURN_ADDRESS <<
1988 # GCC 7, 8 <<
1989 def_bool $(cc-option,-msign-return-ad <<
1990 <<
1991 config AS_HAS_ARMV8_3 <<
1992 def_bool $(cc-option,-Wa$(comma)-marc <<
1993 <<
1994 config AS_HAS_CFI_NEGATE_RA_STATE <<
1995 def_bool $(as-instr,.cfi_startproc\n. <<
1996 <<
1997 config AS_HAS_LDAPR <<
1998 def_bool $(as-instr,.arch_extension r <<
1999 2897
2000 endmenu # "ARMv8.3 architectural features" !! 2898 config SYS_SUPPORTS_128HZ
>> 2899 bool
2001 2900
2002 menu "ARMv8.4 architectural features" !! 2901 config SYS_SUPPORTS_250HZ
>> 2902 bool
2003 2903
2004 config ARM64_AMU_EXTN !! 2904 config SYS_SUPPORTS_256HZ
2005 bool "Enable support for the Activity !! 2905 bool
2006 default y <<
2007 help <<
2008 The activity monitors extension is <<
2009 by the ARMv8.4 CPU architecture. Th <<
2010 of the activity monitors architectu <<
2011 <<
2012 To enable the use of this extension <<
2013 <<
2014 Note that for architectural reasons <<
2015 support when running on CPUs that p <<
2016 extension. The required support is <<
2017 * Version 1.5 and later of the AR <<
2018 <<
2019 For kernels that have this configur <<
2020 firmware, you may need to say N her <<
2021 Otherwise you may experience firmwa <<
2022 accessing the counter registers. Ev <<
2023 symptoms, the values returned by th <<
2024 correctly reflect reality. Most com <<
2025 indicating that the counter is not <<
2026 2906
2027 config AS_HAS_ARMV8_4 !! 2907 config SYS_SUPPORTS_1000HZ
2028 def_bool $(cc-option,-Wa$(comma)-marc !! 2908 bool
2029 2909
2030 config ARM64_TLB_RANGE !! 2910 config SYS_SUPPORTS_1024HZ
2031 bool "Enable support for tlbi range f !! 2911 bool
2032 default y <<
2033 depends on AS_HAS_ARMV8_4 <<
2034 help <<
2035 ARMv8.4-TLBI provides TLBI invalida <<
2036 range of input addresses. <<
2037 2912
2038 The feature introduces new assembly !! 2913 config SYS_SUPPORTS_ARBIT_HZ
2039 support when binutils >= 2.30. !! 2914 bool
>> 2915 default y if !SYS_SUPPORTS_24HZ && \
>> 2916 !SYS_SUPPORTS_48HZ && \
>> 2917 !SYS_SUPPORTS_100HZ && \
>> 2918 !SYS_SUPPORTS_128HZ && \
>> 2919 !SYS_SUPPORTS_250HZ && \
>> 2920 !SYS_SUPPORTS_256HZ && \
>> 2921 !SYS_SUPPORTS_1000HZ && \
>> 2922 !SYS_SUPPORTS_1024HZ
2040 2923
2041 endmenu # "ARMv8.4 architectural features" !! 2924 config HZ
>> 2925 int
>> 2926 default 24 if HZ_24
>> 2927 default 48 if HZ_48
>> 2928 default 100 if HZ_100
>> 2929 default 128 if HZ_128
>> 2930 default 250 if HZ_250
>> 2931 default 256 if HZ_256
>> 2932 default 1000 if HZ_1000
>> 2933 default 1024 if HZ_1024
>> 2934
>> 2935 config SCHED_HRTICK
>> 2936 def_bool HIGH_RES_TIMERS
>> 2937
>> 2938 config KEXEC
>> 2939 bool "Kexec system call"
>> 2940 select KEXEC_CORE
>> 2941 help
>> 2942 kexec is a system call that implements the ability to shutdown your
>> 2943 current kernel, and to start another kernel. It is like a reboot
>> 2944 but it is independent of the system firmware. And like a reboot
>> 2945 you can start any kernel with it, not just Linux.
>> 2946
>> 2947 The name comes from the similarity to the exec system call.
>> 2948
>> 2949 It is an ongoing process to be certain the hardware in a machine
>> 2950 is properly shutdown, so do not be surprised if this code does not
>> 2951 initially work for you. As of this writing the exact hardware
>> 2952 interface is strongly in flux, so no good recommendation can be
>> 2953 made.
>> 2954
>> 2955 config CRASH_DUMP
>> 2956 bool "Kernel crash dumps"
>> 2957 help
>> 2958 Generate crash dump after being started by kexec.
>> 2959 This should be normally only set in special crash dump kernels
>> 2960 which are loaded in the main kernel with kexec-tools into
>> 2961 a specially reserved region and then later executed after
>> 2962 a crash by kdump/kexec. The crash dump kernel must be compiled
>> 2963 to a memory address not used by the main kernel or firmware using
>> 2964 PHYSICAL_START.
>> 2965
>> 2966 config PHYSICAL_START
>> 2967 hex "Physical address where the kernel is loaded"
>> 2968 default "0xffffffff84000000"
>> 2969 depends on CRASH_DUMP
>> 2970 help
>> 2971 This gives the CKSEG0 or KSEG0 address where the kernel is loaded.
>> 2972 If you plan to use kernel for capturing the crash dump change
>> 2973 this value to start of the reserved region (the "X" value as
>> 2974 specified in the "crashkernel=YM@XM" command line boot parameter
>> 2975 passed to the panic-ed kernel).
>> 2976
>> 2977 config SECCOMP
>> 2978 bool "Enable seccomp to safely compute untrusted bytecode"
>> 2979 depends on PROC_FS
>> 2980 default y
>> 2981 help
>> 2982 This kernel feature is useful for number crunching applications
>> 2983 that may need to compute untrusted bytecode during their
>> 2984 execution. By using pipes or other transports made available to
>> 2985 the process as file descriptors supporting the read/write
>> 2986 syscalls, it's possible to isolate those applications in
>> 2987 their own address space using seccomp. Once seccomp is
>> 2988 enabled via /proc/<pid>/seccomp, it cannot be disabled
>> 2989 and the task is only allowed to execute a few safe syscalls
>> 2990 defined by each seccomp mode.
>> 2991
>> 2992 If unsure, say Y. Only embedded should say N here.
>> 2993
>> 2994 config MIPS_O32_FP64_SUPPORT
>> 2995 bool "Support for O32 binaries using 64-bit FP" if !CPU_MIPSR6
>> 2996 depends on 32BIT || MIPS32_O32
>> 2997 help
>> 2998 When this is enabled, the kernel will support use of 64-bit floating
>> 2999 point registers with binaries using the O32 ABI along with the
>> 3000 EF_MIPS_FP64 ELF header flag (typically built with -mfp64). On
>> 3001 32-bit MIPS systems this support is at the cost of increasing the
>> 3002 size and complexity of the compiled FPU emulator. Thus if you are
>> 3003 running a MIPS32 system and know that none of your userland binaries
>> 3004 will require 64-bit floating point, you may wish to reduce the size
>> 3005 of your kernel & potentially improve FP emulation performance by
>> 3006 saying N here.
>> 3007
>> 3008 Although binutils currently supports use of this flag the details
>> 3009 concerning its effect upon the O32 ABI in userland are still being
>> 3010 worked on. In order to avoid userland becoming dependant upon current
>> 3011 behaviour before the details have been finalised, this option should
>> 3012 be considered experimental and only enabled by those working upon
>> 3013 said details.
2042 3014
2043 menu "ARMv8.5 architectural features" !! 3015 If unsure, say N.
2044 3016
2045 config AS_HAS_ARMV8_5 !! 3017 config USE_OF
2046 def_bool $(cc-option,-Wa$(comma)-marc !! 3018 bool
>> 3019 select OF
>> 3020 select OF_EARLY_FLATTREE
>> 3021 select IRQ_DOMAIN
2047 3022
2048 config ARM64_BTI !! 3023 config UHI_BOOT
2049 bool "Branch Target Identification su !! 3024 bool
2050 default y <<
2051 help <<
2052 Branch Target Identification (part <<
2053 provides a mechanism to limit the s <<
2054 branch instructions such as BR or B <<
2055 <<
2056 To make use of BTI on CPUs that sup <<
2057 <<
2058 BTI is intended to provide compleme <<
2059 flow integrity protection mechanism <<
2060 authentication mechanism provided a <<
2061 For this reason, it does not make s <<
2062 also enabling support for pointer a <<
2063 enabling this option you should als <<
2064 <<
2065 Userspace binaries must also be spe <<
2066 this mechanism. If you say N here <<
2067 BTI, such binaries can still run, b <<
2068 enforcement of branch destinations. <<
2069 3025
2070 config ARM64_BTI_KERNEL !! 3026 config BUILTIN_DTB
2071 bool "Use Branch Target Identificatio !! 3027 bool
2072 default y <<
2073 depends on ARM64_BTI <<
2074 depends on ARM64_PTR_AUTH_KERNEL <<
2075 depends on CC_HAS_BRANCH_PROT_PAC_RET <<
2076 # https://gcc.gnu.org/bugzilla/show_b <<
2077 depends on !CC_IS_GCC || GCC_VERSION <<
2078 # https://gcc.gnu.org/bugzilla/show_b <<
2079 depends on !CC_IS_GCC <<
2080 depends on (!FUNCTION_GRAPH_TRACER || <<
2081 help <<
2082 Build the kernel with Branch Target <<
2083 and enable enforcement of this for <<
2084 is enabled and the system supports <<
2085 modular code must have BTI enabled. <<
2086 <<
2087 config CC_HAS_BRANCH_PROT_PAC_RET_BTI <<
2088 # GCC 9 or later, clang 8 or later <<
2089 def_bool $(cc-option,-mbranch-protect <<
2090 3028
2091 config ARM64_E0PD !! 3029 choice
2092 bool "Enable support for E0PD" !! 3030 prompt "Kernel appended dtb support" if USE_OF
2093 default y !! 3031 default MIPS_NO_APPENDED_DTB
2094 help <<
2095 E0PD (part of the ARMv8.5 extension <<
2096 that EL0 accesses made via TTBR1 al <<
2097 providing similar benefits to KASLR <<
2098 with lower overhead and without dis <<
2099 kernel memory such as SPE. <<
2100 <<
2101 This option enables E0PD for TTBR1 <<
2102 <<
2103 config ARM64_AS_HAS_MTE <<
2104 # Initial support for MTE went in bin <<
2105 # ".arch armv8.5-a+memtag" below. How <<
2106 # as a late addition to the final arc <<
2107 # is only supported in the newer 2.32 <<
2108 # versions, hence the extra "stgm" in <<
2109 def_bool $(as-instr,.arch armv8.5-a+m <<
2110 3032
2111 config ARM64_MTE !! 3033 config MIPS_NO_APPENDED_DTB
2112 bool "Memory Tagging Extension suppor !! 3034 bool "None"
2113 default y !! 3035 help
2114 depends on ARM64_AS_HAS_MTE && ARM64_ !! 3036 Do not enable appended dtb support.
2115 depends on AS_HAS_ARMV8_5 !! 3037
2116 depends on AS_HAS_LSE_ATOMICS !! 3038 config MIPS_ELF_APPENDED_DTB
2117 # Required for tag checking in the ua !! 3039 bool "vmlinux"
2118 depends on ARM64_PAN !! 3040 help
2119 select ARCH_HAS_SUBPAGE_FAULTS !! 3041 With this option, the boot code will look for a device tree binary
2120 select ARCH_USES_HIGH_VMA_FLAGS !! 3042 DTB) included in the vmlinux ELF section .appended_dtb. By default
2121 select ARCH_USES_PG_ARCH_2 !! 3043 it is empty and the DTB can be appended using binutils command
2122 select ARCH_USES_PG_ARCH_3 !! 3044 objcopy:
2123 help !! 3045
2124 Memory Tagging (part of the ARMv8.5 !! 3046 objcopy --update-section .appended_dtb=<filename>.dtb vmlinux
2125 architectural support for run-time, !! 3047
2126 various classes of memory error to !! 3048 This is meant as a backward compatiblity convenience for those
2127 to eliminate vulnerabilities arisin !! 3049 systems with a bootloader that can't be upgraded to accommodate
2128 languages. !! 3050 the documented boot protocol using a device tree.
2129 !! 3051
2130 This option enables the support for !! 3052 config MIPS_RAW_APPENDED_DTB
2131 Extension at EL0 (i.e. for userspac !! 3053 bool "vmlinux.bin or vmlinuz.bin"
2132 !! 3054 help
2133 Selecting this option allows the fe !! 3055 With this option, the boot code will look for a device tree binary
2134 runtime. Any secondary CPU not impl !! 3056 DTB) appended to raw vmlinux.bin or vmlinuz.bin.
2135 not be allowed a late bring-up. !! 3057 (e.g. cat vmlinux.bin <filename>.dtb > vmlinux_w_dtb).
2136 !! 3058
2137 Userspace binaries that want to use !! 3059 This is meant as a backward compatibility convenience for those
2138 explicitly opt in. The mechanism fo !! 3060 systems with a bootloader that can't be upgraded to accommodate
2139 described in: !! 3061 the documented boot protocol using a device tree.
>> 3062
>> 3063 Beware that there is very little in terms of protection against
>> 3064 this option being confused by leftover garbage in memory that might
>> 3065 look like a DTB header after a reboot if no actual DTB is appended
>> 3066 to vmlinux.bin. Do not leave this option active in a production kernel
>> 3067 if you don't intend to always append a DTB.
>> 3068 endchoice
2140 3069
2141 Documentation/arch/arm64/memory-tag !! 3070 choice
>> 3071 prompt "Kernel command line type" if !CMDLINE_OVERRIDE
>> 3072 default MIPS_CMDLINE_FROM_DTB if USE_OF && !ATH79 && !MACH_INGENIC && \
>> 3073 !MIPS_MALTA && \
>> 3074 !CAVIUM_OCTEON_SOC
>> 3075 default MIPS_CMDLINE_FROM_BOOTLOADER
>> 3076
>> 3077 config MIPS_CMDLINE_FROM_DTB
>> 3078 depends on USE_OF
>> 3079 bool "Dtb kernel arguments if available"
>> 3080
>> 3081 config MIPS_CMDLINE_DTB_EXTEND
>> 3082 depends on USE_OF
>> 3083 bool "Extend dtb kernel arguments with bootloader arguments"
>> 3084
>> 3085 config MIPS_CMDLINE_FROM_BOOTLOADER
>> 3086 bool "Bootloader kernel arguments if available"
>> 3087
>> 3088 config MIPS_CMDLINE_BUILTIN_EXTEND
>> 3089 depends on CMDLINE_BOOL
>> 3090 bool "Extend builtin kernel arguments with bootloader arguments"
>> 3091 endchoice
2142 3092
2143 endmenu # "ARMv8.5 architectural features" !! 3093 endmenu
2144 3094
2145 menu "ARMv8.7 architectural features" !! 3095 config LOCKDEP_SUPPORT
>> 3096 bool
>> 3097 default y
2146 3098
2147 config ARM64_EPAN !! 3099 config STACKTRACE_SUPPORT
2148 bool "Enable support for Enhanced Pri !! 3100 bool
2149 default y 3101 default y
2150 depends on ARM64_PAN <<
2151 help <<
2152 Enhanced Privileged Access Never (E <<
2153 Access Never to be used with Execut <<
2154 3102
2155 The feature is detected at runtime, !! 3103 config PGTABLE_LEVELS
2156 if the cpu does not implement the f !! 3104 int
2157 endmenu # "ARMv8.7 architectural features" !! 3105 default 4 if PAGE_SIZE_4KB && MIPS_VA_BITS_48
>> 3106 default 3 if 64BIT && !PAGE_SIZE_64KB
>> 3107 default 2
2158 3108
2159 menu "ARMv8.9 architectural features" !! 3109 config MIPS_AUTO_PFN_OFFSET
>> 3110 bool
2160 3111
2161 config ARM64_POE !! 3112 menu "Bus options (PCI, PCMCIA, EISA, ISA, TC)"
2162 prompt "Permission Overlay Extension" <<
2163 def_bool y <<
2164 select ARCH_USES_HIGH_VMA_FLAGS <<
2165 select ARCH_HAS_PKEYS <<
2166 help <<
2167 The Permission Overlay Extension is <<
2168 Protection Keys. Memory Protection <<
2169 enforcing page-based protections, b <<
2170 of the page tables when an applicat <<
2171 3113
2172 For details, see Documentation/core !! 3114 config PCI_DRIVERS_GENERIC
>> 3115 select PCI_DOMAINS_GENERIC if PCI
>> 3116 bool
2173 3117
2174 If unsure, say y. !! 3118 config PCI_DRIVERS_LEGACY
>> 3119 def_bool !PCI_DRIVERS_GENERIC
>> 3120 select NO_GENERIC_PCI_IOPORT_MAP
>> 3121 select PCI_DOMAINS if PCI
2175 3122
2176 config ARCH_PKEY_BITS !! 3123 #
2177 int !! 3124 # ISA support is now enabled via select. Too many systems still have the one
2178 default 3 !! 3125 # or other ISA chip on the board that users don't know about so don't expect
>> 3126 # users to choose the right thing ...
>> 3127 #
>> 3128 config ISA
>> 3129 bool
2179 3130
2180 endmenu # "ARMv8.9 architectural features" !! 3131 config TC
>> 3132 bool "TURBOchannel support"
>> 3133 depends on MACH_DECSTATION
>> 3134 help
>> 3135 TURBOchannel is a DEC (now Compaq (now HP)) bus for Alpha and MIPS
>> 3136 processors. TURBOchannel programming specifications are available
>> 3137 at:
>> 3138 <ftp://ftp.hp.com/pub/alphaserver/archive/triadd/>
>> 3139 and:
>> 3140 <http://www.computer-refuge.org/classiccmp/ftp.digital.com/pub/DEC/TriAdd/>
>> 3141 Linux driver support status is documented at:
>> 3142 <http://www.linux-mips.org/wiki/DECstation>
2181 3143
2182 config ARM64_SVE !! 3144 config MMU
2183 bool "ARM Scalable Vector Extension s !! 3145 bool
2184 default y 3146 default y
2185 help <<
2186 The Scalable Vector Extension (SVE) <<
2187 execution state which complements a <<
2188 of the base architecture to support <<
2189 additional vectorisation opportunit <<
2190 <<
2191 To enable use of this extension on <<
2192 <<
2193 On CPUs that support the SVE2 exten <<
2194 those too. <<
2195 <<
2196 Note that for architectural reasons <<
2197 support when running on SVE capable <<
2198 is present in: <<
2199 <<
2200 * version 1.5 and later of the AR <<
2201 * the AArch64 boot wrapper since <<
2202 ("bootwrapper: SVE: Enable SVE <<
2203 <<
2204 For other firmware implementations, <<
2205 or vendor. <<
2206 <<
2207 If you need the kernel to boot on S <<
2208 firmware, you may need to say N her <<
2209 fixed. Otherwise, you may experien <<
2210 booting the kernel. If unsure and <<
2211 symptoms, you should assume that it <<
2212 3147
2213 config ARM64_SME !! 3148 config ARCH_MMAP_RND_BITS_MIN
2214 bool "ARM Scalable Matrix Extension s !! 3149 default 12 if 64BIT
2215 default y !! 3150 default 8
2216 depends on ARM64_SVE <<
2217 depends on BROKEN <<
2218 help <<
2219 The Scalable Matrix Extension (SME) <<
2220 execution state which utilises a su <<
2221 instruction set, together with the <<
2222 register state capable of holding t <<
2223 enable various matrix operations. <<
2224 <<
2225 config ARM64_PSEUDO_NMI <<
2226 bool "Support for NMI-like interrupts <<
2227 select ARM_GIC_V3 <<
2228 help <<
2229 Adds support for mimicking Non-Mask <<
2230 GIC interrupt priority. This suppor <<
2231 ARM GIC. <<
2232 <<
2233 This high priority configuration fo <<
2234 explicitly enabled by setting the k <<
2235 "irqchip.gicv3_pseudo_nmi" to 1. <<
2236 <<
2237 If unsure, say N <<
2238 <<
2239 if ARM64_PSEUDO_NMI <<
2240 config ARM64_DEBUG_PRIORITY_MASKING <<
2241 bool "Debug interrupt priority maskin <<
2242 help <<
2243 This adds runtime checks to functio <<
2244 interrupts when using priority mask <<
2245 the validity of ICC_PMR_EL1 when ca <<
2246 3151
2247 If unsure, say N !! 3152 config ARCH_MMAP_RND_BITS_MAX
2248 endif # ARM64_PSEUDO_NMI !! 3153 default 18 if 64BIT
>> 3154 default 15
2249 3155
2250 config RELOCATABLE !! 3156 config ARCH_MMAP_RND_COMPAT_BITS_MIN
2251 bool "Build a relocatable kernel imag !! 3157 default 8
2252 select ARCH_HAS_RELR <<
2253 default y <<
2254 help <<
2255 This builds the kernel as a Positio <<
2256 which retains all relocation metada <<
2257 kernel binary at runtime to a diffe <<
2258 address it was linked at. <<
2259 Since AArch64 uses the RELA relocat <<
2260 relocation pass at runtime even if <<
2261 same address it was linked at. <<
2262 3158
2263 config RANDOMIZE_BASE !! 3159 config ARCH_MMAP_RND_COMPAT_BITS_MAX
2264 bool "Randomize the address of the ke !! 3160 default 15
2265 select RELOCATABLE <<
2266 help <<
2267 Randomizes the virtual address at w <<
2268 loaded, as a security feature that <<
2269 relying on knowledge of the locatio <<
2270 <<
2271 It is the bootloader's job to provi <<
2272 random u64 value in /chosen/kaslr-s <<
2273 <<
2274 When booting via the UEFI stub, it <<
2275 EFI_RNG_PROTOCOL implementation (if <<
2276 to the kernel proper. In addition, <<
2277 location of the kernel Image as wel <<
2278 3161
2279 If unsure, say N. !! 3162 config I8253
>> 3163 bool
>> 3164 select CLKSRC_I8253
>> 3165 select CLKEVT_I8253
>> 3166 select MIPS_EXTERNAL_TIMER
2280 3167
2281 config RANDOMIZE_MODULE_REGION_FULL !! 3168 config ZONE_DMA
2282 bool "Randomize the module region ove !! 3169 bool
2283 depends on RANDOMIZE_BASE <<
2284 default y <<
2285 help <<
2286 Randomizes the location of the modu <<
2287 covering the core kernel. This way, <<
2288 to leak information about the locat <<
2289 but it does imply that function cal <<
2290 kernel will need to be resolved via <<
2291 <<
2292 When this option is not set, the mo <<
2293 a limited range that contains the [ <<
2294 core kernel, so branch relocations <<
2295 the region is exhausted. In this pa <<
2296 exhaustion, modules might be able t <<
2297 3170
2298 config CC_HAVE_STACKPROTECTOR_SYSREG !! 3171 config ZONE_DMA32
2299 def_bool $(cc-option,-mstack-protecto !! 3172 bool
2300 3173
2301 config STACKPROTECTOR_PER_TASK !! 3174 endmenu
2302 def_bool y <<
2303 depends on STACKPROTECTOR && CC_HAVE_ <<
2304 3175
2305 config UNWIND_PATCH_PAC_INTO_SCS !! 3176 config TRAD_SIGNALS
2306 bool "Enable shadow call stack dynami !! 3177 bool
2307 # needs Clang with https://github.com <<
2308 depends on CC_IS_CLANG && CLANG_VERSI <<
2309 depends on ARM64_PTR_AUTH_KERNEL && C <<
2310 depends on SHADOW_CALL_STACK <<
2311 select UNWIND_TABLES <<
2312 select DYNAMIC_SCS <<
2313 <<
2314 config ARM64_CONTPTE <<
2315 bool "Contiguous PTE mappings for use <<
2316 depends on TRANSPARENT_HUGEPAGE <<
2317 default y <<
2318 help <<
2319 When enabled, user mappings are con <<
2320 bit, for any mappings that meet the <<
2321 This reduces TLB pressure and impro <<
2322 <<
2323 endmenu # "Kernel Features" <<
2324 <<
2325 menu "Boot options" <<
2326 <<
2327 config ARM64_ACPI_PARKING_PROTOCOL <<
2328 bool "Enable support for the ARM64 AC <<
2329 depends on ACPI <<
2330 help <<
2331 Enable support for the ARM64 ACPI p <<
2332 the kernel will not allow booting t <<
2333 protocol even if the corresponding <<
2334 MADT table. <<
2335 <<
2336 config CMDLINE <<
2337 string "Default kernel command string <<
2338 default "" <<
2339 help <<
2340 Provide a set of default command-li <<
2341 entering them here. As a minimum, y <<
2342 root device (e.g. root=/dev/nfs). <<
2343 3178
2344 choice !! 3179 config MIPS32_COMPAT
2345 prompt "Kernel command line type" !! 3180 bool
2346 depends on CMDLINE != "" <<
2347 default CMDLINE_FROM_BOOTLOADER <<
2348 help <<
2349 Choose how the kernel will handle t <<
2350 command line string. <<
2351 <<
2352 config CMDLINE_FROM_BOOTLOADER <<
2353 bool "Use bootloader kernel arguments <<
2354 help <<
2355 Uses the command-line options passe <<
2356 the boot loader doesn't provide any <<
2357 string provided in CMDLINE will be <<
2358 <<
2359 config CMDLINE_FORCE <<
2360 bool "Always use the default kernel c <<
2361 help <<
2362 Always use the default kernel comma <<
2363 loader passes other arguments to th <<
2364 This is useful if you cannot or don <<
2365 command-line options your boot load <<
2366 3181
2367 endchoice !! 3182 config COMPAT
>> 3183 bool
2368 3184
2369 config EFI_STUB !! 3185 config SYSVIPC_COMPAT
2370 bool 3186 bool
2371 3187
2372 config EFI !! 3188 config MIPS32_O32
2373 bool "UEFI runtime support" !! 3189 bool "Kernel support for o32 binaries"
2374 depends on OF && !CPU_BIG_ENDIAN !! 3190 depends on 64BIT
2375 depends on KERNEL_MODE_NEON !! 3191 select ARCH_WANT_OLD_COMPAT_IPC
2376 select ARCH_SUPPORTS_ACPI !! 3192 select COMPAT
2377 select LIBFDT !! 3193 select MIPS32_COMPAT
2378 select UCS2_STRING !! 3194 select SYSVIPC_COMPAT if SYSVIPC
2379 select EFI_PARAMS_FROM_FDT !! 3195 help
2380 select EFI_RUNTIME_WRAPPERS !! 3196 Select this option if you want to run o32 binaries. These are pure
2381 select EFI_STUB !! 3197 32-bit binaries as used by the 32-bit Linux/MIPS port. Most of
2382 select EFI_GENERIC_STUB !! 3198 existing binaries are in this format.
2383 imply IMA_SECURE_AND_OR_TRUSTED_BOOT <<
2384 default y <<
2385 help <<
2386 This option provides support for ru <<
2387 by UEFI firmware (such as non-volat <<
2388 clock, and platform reset). A UEFI <<
2389 allow the kernel to be booted as an <<
2390 is only useful on systems that have <<
2391 <<
2392 config COMPRESSED_INSTALL <<
2393 bool "Install compressed image by def <<
2394 help <<
2395 This makes the regular "make instal <<
2396 image we built, not the legacy unco <<
2397 <<
2398 You can check that a compressed ima <<
2399 "make zinstall" first, and verifyin <<
2400 in your environment before making " <<
2401 you. <<
2402 <<
2403 config DMI <<
2404 bool "Enable support for SMBIOS (DMI) <<
2405 depends on EFI <<
2406 default y <<
2407 help <<
2408 This enables SMBIOS/DMI feature for <<
2409 3199
2410 This option is only useful on syste !! 3200 If unsure, say Y.
2411 However, even with this option, the <<
2412 continue to boot on existing non-UE <<
2413 3201
2414 endmenu # "Boot options" !! 3202 config MIPS32_N32
>> 3203 bool "Kernel support for n32 binaries"
>> 3204 depends on 64BIT
>> 3205 select ARCH_WANT_COMPAT_IPC_PARSE_VERSION
>> 3206 select COMPAT
>> 3207 select MIPS32_COMPAT
>> 3208 select SYSVIPC_COMPAT if SYSVIPC
>> 3209 help
>> 3210 Select this option if you want to run n32 binaries. These are
>> 3211 64-bit binaries using 32-bit quantities for addressing and certain
>> 3212 data that would normally be 64-bit. They are used in special
>> 3213 cases.
2415 3214
2416 menu "Power management options" !! 3215 If unsure, say N.
2417 3216
2418 source "kernel/power/Kconfig" !! 3217 config BINFMT_ELF32
>> 3218 bool
>> 3219 default y if MIPS32_O32 || MIPS32_N32
>> 3220 select ELFCORE
2419 3221
2420 config ARCH_HIBERNATION_POSSIBLE !! 3222 menu "Power management options"
2421 def_bool y <<
2422 depends on CPU_PM <<
2423 3223
2424 config ARCH_HIBERNATION_HEADER !! 3224 config ARCH_HIBERNATION_POSSIBLE
2425 def_bool y 3225 def_bool y
2426 depends on HIBERNATION !! 3226 depends on SYS_SUPPORTS_HOTPLUG_CPU || !SMP
2427 3227
2428 config ARCH_SUSPEND_POSSIBLE 3228 config ARCH_SUSPEND_POSSIBLE
2429 def_bool y 3229 def_bool y
>> 3230 depends on SYS_SUPPORTS_HOTPLUG_CPU || !SMP
2430 3231
2431 endmenu # "Power management options" !! 3232 source "kernel/power/Kconfig"
2432 3233
2433 menu "CPU Power Management" !! 3234 endmenu
2434 3235
2435 source "drivers/cpuidle/Kconfig" !! 3236 config MIPS_EXTERNAL_TIMER
>> 3237 bool
2436 3238
>> 3239 menu "CPU Power Management"
>> 3240
>> 3241 if CPU_SUPPORTS_CPUFREQ && MIPS_EXTERNAL_TIMER
2437 source "drivers/cpufreq/Kconfig" 3242 source "drivers/cpufreq/Kconfig"
>> 3243 endif
2438 3244
2439 endmenu # "CPU Power Management" !! 3245 source "drivers/cpuidle/Kconfig"
2440 3246
2441 source "drivers/acpi/Kconfig" !! 3247 endmenu
2442 3248
2443 source "arch/arm64/kvm/Kconfig" !! 3249 source "drivers/firmware/Kconfig"
2444 3250
>> 3251 source "arch/mips/kvm/Kconfig"
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