1 # SPDX-License-Identifier: GPL-2.0-only !! 1 # SPDX-License-Identifier: GPL-2.0
2 config ARM64 !! 2 config MIPS
3 def_bool y !! 3 bool
4 select ACPI_APMT if ACPI !! 4 default y
5 select ACPI_CCA_REQUIRED if ACPI !! 5 select ARCH_32BIT_OFF_T if !64BIT
6 select ACPI_GENERIC_GSI if ACPI !! 6 select ARCH_BINFMT_ELF_STATE if MIPS_FP_SUPPORT
7 select ACPI_GTDT if ACPI <<
8 select ACPI_HOTPLUG_CPU if ACPI_PROCES <<
9 select ACPI_IORT if ACPI <<
10 select ACPI_REDUCED_HARDWARE_ONLY if A <<
11 select ACPI_MCFG if (ACPI && PCI) <<
12 select ACPI_SPCR_TABLE if ACPI <<
13 select ACPI_PPTT if ACPI <<
14 select ARCH_HAS_DEBUG_WX <<
15 select ARCH_BINFMT_ELF_EXTRA_PHDRS <<
16 select ARCH_BINFMT_ELF_STATE <<
17 select ARCH_CORRECT_STACKTRACE_ON_KRET <<
18 select ARCH_ENABLE_HUGEPAGE_MIGRATION <<
19 select ARCH_ENABLE_MEMORY_HOTPLUG <<
20 select ARCH_ENABLE_MEMORY_HOTREMOVE <<
21 select ARCH_ENABLE_SPLIT_PMD_PTLOCK if <<
22 select ARCH_ENABLE_THP_MIGRATION if TR <<
23 select ARCH_HAS_CACHE_LINE_SIZE <<
24 select ARCH_HAS_CURRENT_STACK_POINTER <<
25 select ARCH_HAS_DEBUG_VIRTUAL <<
26 select ARCH_HAS_DEBUG_VM_PGTABLE <<
27 select ARCH_HAS_DMA_OPS if XEN <<
28 select ARCH_HAS_DMA_PREP_COHERENT <<
29 select ARCH_HAS_ACPI_TABLE_UPGRADE if <<
30 select ARCH_HAS_FAST_MULTIPLIER <<
31 select ARCH_HAS_FORTIFY_SOURCE 7 select ARCH_HAS_FORTIFY_SOURCE
32 select ARCH_HAS_GCOV_PROFILE_ALL <<
33 select ARCH_HAS_GIGANTIC_PAGE <<
34 select ARCH_HAS_KCOV 8 select ARCH_HAS_KCOV
35 select ARCH_HAS_KERNEL_FPU_SUPPORT if !! 9 select ARCH_HAS_PTE_SPECIAL if !(32BIT && CPU_HAS_RIXI)
36 select ARCH_HAS_KEEPINITRD <<
37 select ARCH_HAS_MEMBARRIER_SYNC_CORE <<
38 select ARCH_HAS_MEM_ENCRYPT <<
39 select ARCH_HAS_NMI_SAFE_THIS_CPU_OPS <<
40 select ARCH_HAS_NON_OVERLAPPING_ADDRES <<
41 select ARCH_HAS_PTE_DEVMAP <<
42 select ARCH_HAS_PTE_SPECIAL <<
43 select ARCH_HAS_HW_PTE_YOUNG <<
44 select ARCH_HAS_SETUP_DMA_OPS <<
45 select ARCH_HAS_SET_DIRECT_MAP <<
46 select ARCH_HAS_SET_MEMORY <<
47 select ARCH_STACKWALK <<
48 select ARCH_HAS_STRICT_KERNEL_RWX <<
49 select ARCH_HAS_STRICT_MODULE_RWX <<
50 select ARCH_HAS_SYNC_DMA_FOR_DEVICE <<
51 select ARCH_HAS_SYNC_DMA_FOR_CPU <<
52 select ARCH_HAS_SYSCALL_WRAPPER <<
53 select ARCH_HAS_TICK_BROADCAST if GENE 10 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
54 select ARCH_HAS_ZONE_DMA_SET if EXPERT !! 11 select ARCH_HAS_UBSAN_SANITIZE_ALL
55 select ARCH_HAVE_ELF_PROT !! 12 select ARCH_SUPPORTS_UPROBES
56 select ARCH_HAVE_NMI_SAFE_CMPXCHG !! 13 select ARCH_USE_BUILTIN_BSWAP
57 select ARCH_HAVE_TRACE_MMIO_ACCESS !! 14 select ARCH_USE_CMPXCHG_LOCKREF if 64BIT
58 select ARCH_INLINE_READ_LOCK if !PREEM <<
59 select ARCH_INLINE_READ_LOCK_BH if !PR <<
60 select ARCH_INLINE_READ_LOCK_IRQ if !P <<
61 select ARCH_INLINE_READ_LOCK_IRQSAVE i <<
62 select ARCH_INLINE_READ_UNLOCK if !PRE <<
63 select ARCH_INLINE_READ_UNLOCK_BH if ! <<
64 select ARCH_INLINE_READ_UNLOCK_IRQ if <<
65 select ARCH_INLINE_READ_UNLOCK_IRQREST <<
66 select ARCH_INLINE_WRITE_LOCK if !PREE <<
67 select ARCH_INLINE_WRITE_LOCK_BH if !P <<
68 select ARCH_INLINE_WRITE_LOCK_IRQ if ! <<
69 select ARCH_INLINE_WRITE_LOCK_IRQSAVE <<
70 select ARCH_INLINE_WRITE_UNLOCK if !PR <<
71 select ARCH_INLINE_WRITE_UNLOCK_BH if <<
72 select ARCH_INLINE_WRITE_UNLOCK_IRQ if <<
73 select ARCH_INLINE_WRITE_UNLOCK_IRQRES <<
74 select ARCH_INLINE_SPIN_TRYLOCK if !PR <<
75 select ARCH_INLINE_SPIN_TRYLOCK_BH if <<
76 select ARCH_INLINE_SPIN_LOCK if !PREEM <<
77 select ARCH_INLINE_SPIN_LOCK_BH if !PR <<
78 select ARCH_INLINE_SPIN_LOCK_IRQ if !P <<
79 select ARCH_INLINE_SPIN_LOCK_IRQSAVE i <<
80 select ARCH_INLINE_SPIN_UNLOCK if !PRE <<
81 select ARCH_INLINE_SPIN_UNLOCK_BH if ! <<
82 select ARCH_INLINE_SPIN_UNLOCK_IRQ if <<
83 select ARCH_INLINE_SPIN_UNLOCK_IRQREST <<
84 select ARCH_KEEP_MEMBLOCK <<
85 select ARCH_MHP_MEMMAP_ON_MEMORY_ENABL <<
86 select ARCH_USE_CMPXCHG_LOCKREF <<
87 select ARCH_USE_GNU_PROPERTY <<
88 select ARCH_USE_MEMTEST <<
89 select ARCH_USE_QUEUED_RWLOCKS 15 select ARCH_USE_QUEUED_RWLOCKS
90 select ARCH_USE_QUEUED_SPINLOCKS 16 select ARCH_USE_QUEUED_SPINLOCKS
91 select ARCH_USE_SYM_ANNOTATIONS !! 17 select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT if MMU
92 select ARCH_SUPPORTS_DEBUG_PAGEALLOC !! 18 select ARCH_WANT_IPC_PARSE_VERSION
93 select ARCH_SUPPORTS_HUGETLBFS <<
94 select ARCH_SUPPORTS_MEMORY_FAILURE <<
95 select ARCH_SUPPORTS_SHADOW_CALL_STACK <<
96 select ARCH_SUPPORTS_LTO_CLANG if CPU_ <<
97 select ARCH_SUPPORTS_LTO_CLANG_THIN <<
98 select ARCH_SUPPORTS_CFI_CLANG <<
99 select ARCH_SUPPORTS_ATOMIC_RMW <<
100 select ARCH_SUPPORTS_INT128 if CC_HAS_ <<
101 select ARCH_SUPPORTS_NUMA_BALANCING <<
102 select ARCH_SUPPORTS_PAGE_TABLE_CHECK <<
103 select ARCH_SUPPORTS_PER_VMA_LOCK <<
104 select ARCH_SUPPORTS_HUGE_PFNMAP if TR <<
105 select ARCH_SUPPORTS_RT <<
106 select ARCH_WANT_BATCHED_UNMAP_TLB_FLU <<
107 select ARCH_WANT_COMPAT_IPC_PARSE_VERS <<
108 select ARCH_WANT_DEFAULT_BPF_JIT <<
109 select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_ <<
110 select ARCH_WANT_FRAME_POINTERS <<
111 select ARCH_WANT_HUGE_PMD_SHARE if ARM <<
112 select ARCH_WANT_LD_ORPHAN_WARN <<
113 select ARCH_WANTS_EXECMEM_LATE if EXEC <<
114 select ARCH_WANTS_NO_INSTR <<
115 select ARCH_WANTS_THP_SWAP if ARM64_4K <<
116 select ARCH_HAS_UBSAN <<
117 select ARM_AMBA <<
118 select ARM_ARCH_TIMER <<
119 select ARM_GIC <<
120 select AUDIT_ARCH_COMPAT_GENERIC <<
121 select ARM_GIC_V2M if PCI <<
122 select ARM_GIC_V3 <<
123 select ARM_GIC_V3_ITS if PCI <<
124 select ARM_PSCI_FW <<
125 select BUILDTIME_TABLE_SORT 19 select BUILDTIME_TABLE_SORT
126 select CLONE_BACKWARDS 20 select CLONE_BACKWARDS
127 select COMMON_CLK !! 21 select CPU_NO_EFFICIENT_FFS if (TARGET_ISA_REV < 1)
128 select CPU_PM if (SUSPEND || CPU_IDLE) !! 22 select CPU_PM if CPU_IDLE
129 select CPUMASK_OFFSTACK if NR_CPUS > 2 !! 23 select GENERIC_ATOMIC64 if !64BIT
130 select CRC32 !! 24 select GENERIC_CLOCKEVENTS
131 select DCACHE_WORD_ACCESS !! 25 select GENERIC_CMOS_UPDATE
132 select DYNAMIC_FTRACE if FUNCTION_TRAC <<
133 select DMA_BOUNCE_UNALIGNED_KMALLOC <<
134 select DMA_DIRECT_REMAP <<
135 select EDAC_SUPPORT <<
136 select FRAME_POINTER <<
137 select FUNCTION_ALIGNMENT_4B <<
138 select FUNCTION_ALIGNMENT_8B if DYNAMI <<
139 select GENERIC_ALLOCATOR <<
140 select GENERIC_ARCH_TOPOLOGY <<
141 select GENERIC_CLOCKEVENTS_BROADCAST <<
142 select GENERIC_CPU_AUTOPROBE 26 select GENERIC_CPU_AUTOPROBE
143 select GENERIC_CPU_DEVICES !! 27 select GENERIC_GETTIMEOFDAY
144 select GENERIC_CPU_VULNERABILITIES !! 28 select GENERIC_IOMAP
145 select GENERIC_EARLY_IOREMAP <<
146 select GENERIC_IDLE_POLL_SETUP <<
147 select GENERIC_IOREMAP <<
148 select GENERIC_IRQ_IPI <<
149 select GENERIC_IRQ_PROBE 29 select GENERIC_IRQ_PROBE
150 select GENERIC_IRQ_SHOW 30 select GENERIC_IRQ_SHOW
151 select GENERIC_IRQ_SHOW_LEVEL !! 31 select GENERIC_ISA_DMA if EISA
152 select GENERIC_LIB_DEVMEM_IS_ALLOWED !! 32 select GENERIC_LIB_ASHLDI3
153 select GENERIC_PCI_IOMAP !! 33 select GENERIC_LIB_ASHRDI3
154 select GENERIC_PTDUMP !! 34 select GENERIC_LIB_CMPDI2
155 select GENERIC_SCHED_CLOCK !! 35 select GENERIC_LIB_LSHRDI3
>> 36 select GENERIC_LIB_UCMPDI2
>> 37 select GENERIC_SCHED_CLOCK if !CAVIUM_OCTEON_SOC
156 select GENERIC_SMP_IDLE_THREAD 38 select GENERIC_SMP_IDLE_THREAD
157 select GENERIC_TIME_VSYSCALL 39 select GENERIC_TIME_VSYSCALL
158 select GENERIC_GETTIMEOFDAY !! 40 select GUP_GET_PTE_LOW_HIGH if CPU_MIPS32 && PHYS_ADDR_T_64BIT
159 select GENERIC_VDSO_TIME_NS !! 41 select HANDLE_DOMAIN_IRQ
160 select HARDIRQS_SW_RESEND <<
161 select HAS_IOPORT <<
162 select HAVE_MOVE_PMD <<
163 select HAVE_MOVE_PUD <<
164 select HAVE_PCI <<
165 select HAVE_ACPI_APEI if (ACPI && EFI) <<
166 select HAVE_ALIGNED_STRUCT_PAGE <<
167 select HAVE_ARCH_AUDITSYSCALL <<
168 select HAVE_ARCH_BITREVERSE <<
169 select HAVE_ARCH_COMPILER_H 42 select HAVE_ARCH_COMPILER_H
170 select HAVE_ARCH_HUGE_VMALLOC <<
171 select HAVE_ARCH_HUGE_VMAP <<
172 select HAVE_ARCH_JUMP_LABEL 43 select HAVE_ARCH_JUMP_LABEL
173 select HAVE_ARCH_JUMP_LABEL_RELATIVE <<
174 select HAVE_ARCH_KASAN <<
175 select HAVE_ARCH_KASAN_VMALLOC <<
176 select HAVE_ARCH_KASAN_SW_TAGS <<
177 select HAVE_ARCH_KASAN_HW_TAGS if ARM6 <<
178 # Some instrumentation may be unsound, <<
179 select HAVE_ARCH_KCSAN if EXPERT <<
180 select HAVE_ARCH_KFENCE <<
181 select HAVE_ARCH_KGDB 44 select HAVE_ARCH_KGDB
182 select HAVE_ARCH_MMAP_RND_BITS !! 45 select HAVE_ARCH_MMAP_RND_BITS if MMU
183 select HAVE_ARCH_MMAP_RND_COMPAT_BITS !! 46 select HAVE_ARCH_MMAP_RND_COMPAT_BITS if MMU && COMPAT
184 select HAVE_ARCH_PREL32_RELOCATIONS <<
185 select HAVE_ARCH_RANDOMIZE_KSTACK_OFFS <<
186 select HAVE_ARCH_SECCOMP_FILTER 47 select HAVE_ARCH_SECCOMP_FILTER
187 select HAVE_ARCH_STACKLEAK <<
188 select HAVE_ARCH_THREAD_STRUCT_WHITELI <<
189 select HAVE_ARCH_TRACEHOOK 48 select HAVE_ARCH_TRACEHOOK
190 select HAVE_ARCH_TRANSPARENT_HUGEPAGE !! 49 select HAVE_ARCH_TRANSPARENT_HUGEPAGE if CPU_SUPPORTS_HUGEPAGES
191 select HAVE_ARCH_VMAP_STACK <<
192 select HAVE_ARM_SMCCC <<
193 select HAVE_ASM_MODVERSIONS 50 select HAVE_ASM_MODVERSIONS
194 select HAVE_EBPF_JIT !! 51 select HAVE_CBPF_JIT if !64BIT && !CPU_MICROMIPS
>> 52 select HAVE_CONTEXT_TRACKING
>> 53 select HAVE_TIF_NOHZ
>> 54 select HAVE_COPY_THREAD_TLS
195 select HAVE_C_RECORDMCOUNT 55 select HAVE_C_RECORDMCOUNT
196 select HAVE_CMPXCHG_DOUBLE <<
197 select HAVE_CMPXCHG_LOCAL <<
198 select HAVE_CONTEXT_TRACKING_USER <<
199 select HAVE_DEBUG_KMEMLEAK 56 select HAVE_DEBUG_KMEMLEAK
>> 57 select HAVE_DEBUG_STACKOVERFLOW
200 select HAVE_DMA_CONTIGUOUS 58 select HAVE_DMA_CONTIGUOUS
201 select HAVE_DYNAMIC_FTRACE 59 select HAVE_DYNAMIC_FTRACE
202 select HAVE_DYNAMIC_FTRACE_WITH_ARGS \ !! 60 select HAVE_EBPF_JIT if 64BIT && !CPU_MICROMIPS && TARGET_ISA_REV >= 2
203 if (GCC_SUPPORTS_DYNAMIC_FTRAC !! 61 select HAVE_EXIT_THREAD
204 CLANG_SUPPORTS_DYNAMIC_FTR !! 62 select HAVE_FAST_GUP
205 select HAVE_DYNAMIC_FTRACE_WITH_DIRECT <<
206 if DYNAMIC_FTRACE_WITH_ARGS && <<
207 select HAVE_DYNAMIC_FTRACE_WITH_CALL_O <<
208 if (DYNAMIC_FTRACE_WITH_ARGS & <<
209 (CC_IS_CLANG || !CC_OPTIMI <<
210 select FTRACE_MCOUNT_USE_PATCHABLE_FUN <<
211 if DYNAMIC_FTRACE_WITH_ARGS <<
212 select HAVE_SAMPLE_FTRACE_DIRECT <<
213 select HAVE_SAMPLE_FTRACE_DIRECT_MULTI <<
214 select HAVE_EFFICIENT_UNALIGNED_ACCESS <<
215 select HAVE_GUP_FAST <<
216 select HAVE_FTRACE_MCOUNT_RECORD 63 select HAVE_FTRACE_MCOUNT_RECORD
217 select HAVE_FUNCTION_TRACER <<
218 select HAVE_FUNCTION_ERROR_INJECTION <<
219 select HAVE_FUNCTION_GRAPH_TRACER 64 select HAVE_FUNCTION_GRAPH_TRACER
220 select HAVE_FUNCTION_GRAPH_RETVAL !! 65 select HAVE_FUNCTION_TRACER
221 select HAVE_GCC_PLUGINS 66 select HAVE_GCC_PLUGINS
222 select HAVE_HARDLOCKUP_DETECTOR_PERF i !! 67 select HAVE_GENERIC_VDSO
223 HW_PERF_EVENTS && HAVE_PERF_EV !! 68 select HAVE_IDE
224 select HAVE_HW_BREAKPOINT if PERF_EVEN <<
225 select HAVE_IOREMAP_PROT 69 select HAVE_IOREMAP_PROT
>> 70 select HAVE_IRQ_EXIT_ON_IRQ_STACK
226 select HAVE_IRQ_TIME_ACCOUNTING 71 select HAVE_IRQ_TIME_ACCOUNTING
>> 72 select HAVE_KPROBES
>> 73 select HAVE_KRETPROBES
>> 74 select HAVE_LD_DEAD_CODE_DATA_ELIMINATION
>> 75 select HAVE_MEMBLOCK_NODE_MAP
227 select HAVE_MOD_ARCH_SPECIFIC 76 select HAVE_MOD_ARCH_SPECIFIC
228 select HAVE_NMI 77 select HAVE_NMI
>> 78 select HAVE_OPROFILE
229 select HAVE_PERF_EVENTS 79 select HAVE_PERF_EVENTS
230 select HAVE_PERF_EVENTS_NMI if ARM64_P <<
231 select HAVE_PERF_REGS <<
232 select HAVE_PERF_USER_STACK_DUMP <<
233 select HAVE_PREEMPT_DYNAMIC_KEY <<
234 select HAVE_REGS_AND_STACK_ACCESS_API 80 select HAVE_REGS_AND_STACK_ACCESS_API
235 select HAVE_POSIX_CPU_TIMERS_TASK_WORK <<
236 select HAVE_FUNCTION_ARG_ACCESS_API <<
237 select MMU_GATHER_RCU_TABLE_FREE <<
238 select HAVE_RSEQ 81 select HAVE_RSEQ
239 select HAVE_RUST if RUSTC_SUPPORTS_ARM !! 82 select HAVE_SPARSE_SYSCALL_NR
240 select HAVE_STACKPROTECTOR 83 select HAVE_STACKPROTECTOR
241 select HAVE_SYSCALL_TRACEPOINTS 84 select HAVE_SYSCALL_TRACEPOINTS
242 select HAVE_KPROBES !! 85 select HAVE_VIRT_CPU_ACCOUNTING_GEN if 64BIT || !SMP
243 select HAVE_KRETPROBES <<
244 select HAVE_GENERIC_VDSO <<
245 select HOTPLUG_CORE_SYNC_DEAD if HOTPL <<
246 select IRQ_DOMAIN <<
247 select IRQ_FORCED_THREADING 86 select IRQ_FORCED_THREADING
248 select KASAN_VMALLOC if KASAN !! 87 select ISA if EISA
249 select LOCK_MM_AND_FIND_VMA !! 88 select MODULES_USE_ELF_REL if MODULES
250 select MODULES_USE_ELF_RELA !! 89 select MODULES_USE_ELF_RELA if MODULES && 64BIT
251 select NEED_DMA_MAP_STATE !! 90 select PERF_USE_VMALLOC
252 select NEED_SG_DMA_LENGTH !! 91 select RTC_LIB
253 select OF <<
254 select OF_EARLY_FLATTREE <<
255 select PCI_DOMAINS_GENERIC if PCI <<
256 select PCI_ECAM if (ACPI && PCI) <<
257 select PCI_SYSCALL if PCI <<
258 select POWER_RESET <<
259 select POWER_SUPPLY <<
260 select SPARSE_IRQ <<
261 select SWIOTLB <<
262 select SYSCTL_EXCEPTION_TRACE 92 select SYSCTL_EXCEPTION_TRACE
263 select THREAD_INFO_IN_TASK !! 93 select VIRT_TO_BUS
264 select HAVE_ARCH_USERFAULTFD_MINOR if <<
265 select HAVE_ARCH_USERFAULTFD_WP if USE <<
266 select TRACE_IRQFLAGS_SUPPORT <<
267 select TRACE_IRQFLAGS_NMI_SUPPORT <<
268 select HAVE_SOFTIRQ_ON_OWN_STACK <<
269 select USER_STACKTRACE_SUPPORT <<
270 select VDSO_GETRANDOM <<
271 help <<
272 ARM 64-bit (AArch64) Linux support. <<
273 94
274 config RUSTC_SUPPORTS_ARM64 !! 95 menu "Machine selection"
275 def_bool y <<
276 depends on CPU_LITTLE_ENDIAN <<
277 # Shadow call stack is only supported <<
278 # <<
279 # When using the UNWIND_PATCH_PAC_INTO <<
280 # required due to use of the -Zfixed-x <<
281 # <<
282 # Otherwise, rustc version 1.82+ is re <<
283 # -Zsanitizer=shadow-call-stack flag. <<
284 depends on !SHADOW_CALL_STACK || RUSTC <<
285 <<
286 config CLANG_SUPPORTS_DYNAMIC_FTRACE_WITH_ARGS <<
287 def_bool CC_IS_CLANG <<
288 # https://github.com/ClangBuiltLinux/l <<
289 depends on AS_IS_GNU || (AS_IS_LLVM && <<
290 <<
291 config GCC_SUPPORTS_DYNAMIC_FTRACE_WITH_ARGS <<
292 def_bool CC_IS_GCC <<
293 depends on $(cc-option,-fpatchable-fun <<
294 96
295 config 64BIT !! 97 choice
296 def_bool y !! 98 prompt "System type"
297 !! 99 default MIPS_GENERIC
298 config MMU <<
299 def_bool y <<
300 100
301 config ARM64_CONT_PTE_SHIFT !! 101 config MIPS_GENERIC
302 int !! 102 bool "Generic board-agnostic MIPS kernel"
303 default 5 if PAGE_SIZE_64KB !! 103 select BOOT_RAW
304 default 7 if PAGE_SIZE_16KB !! 104 select BUILTIN_DTB
305 default 4 !! 105 select CEVT_R4K
>> 106 select CLKSRC_MIPS_GIC
>> 107 select COMMON_CLK
>> 108 select CPU_MIPSR2_IRQ_EI
>> 109 select CPU_MIPSR2_IRQ_VI
>> 110 select CSRC_R4K
>> 111 select DMA_PERDEV_COHERENT
>> 112 select HAVE_PCI
>> 113 select IRQ_MIPS_CPU
>> 114 select MIPS_AUTO_PFN_OFFSET
>> 115 select MIPS_CPU_SCACHE
>> 116 select MIPS_GIC
>> 117 select MIPS_L1_CACHE_SHIFT_7
>> 118 select NO_EXCEPT_FILL
>> 119 select PCI_DRIVERS_GENERIC
>> 120 select SMP_UP if SMP
>> 121 select SWAP_IO_SPACE
>> 122 select SYS_HAS_CPU_MIPS32_R1
>> 123 select SYS_HAS_CPU_MIPS32_R2
>> 124 select SYS_HAS_CPU_MIPS32_R6
>> 125 select SYS_HAS_CPU_MIPS64_R1
>> 126 select SYS_HAS_CPU_MIPS64_R2
>> 127 select SYS_HAS_CPU_MIPS64_R6
>> 128 select SYS_SUPPORTS_32BIT_KERNEL
>> 129 select SYS_SUPPORTS_64BIT_KERNEL
>> 130 select SYS_SUPPORTS_BIG_ENDIAN
>> 131 select SYS_SUPPORTS_HIGHMEM
>> 132 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 133 select SYS_SUPPORTS_MICROMIPS
>> 134 select SYS_SUPPORTS_MIPS16
>> 135 select SYS_SUPPORTS_MIPS_CPS
>> 136 select SYS_SUPPORTS_MULTITHREADING
>> 137 select SYS_SUPPORTS_RELOCATABLE
>> 138 select SYS_SUPPORTS_SMARTMIPS
>> 139 select UHI_BOOT
>> 140 select USB_EHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
>> 141 select USB_EHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 142 select USB_OHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
>> 143 select USB_OHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 144 select USB_UHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
>> 145 select USB_UHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 146 select USE_OF
>> 147 help
>> 148 Select this to build a kernel which aims to support multiple boards,
>> 149 generally using a flattened device tree passed from the bootloader
>> 150 using the boot protocol defined in the UHI (Unified Hosting
>> 151 Interface) specification.
>> 152
>> 153 config MIPS_ALCHEMY
>> 154 bool "Alchemy processor based machines"
>> 155 select PHYS_ADDR_T_64BIT
>> 156 select CEVT_R4K
>> 157 select CSRC_R4K
>> 158 select IRQ_MIPS_CPU
>> 159 select DMA_MAYBE_COHERENT # Au1000,1500,1100 aren't, rest is
>> 160 select SYS_HAS_CPU_MIPS32_R1
>> 161 select SYS_SUPPORTS_32BIT_KERNEL
>> 162 select SYS_SUPPORTS_APM_EMULATION
>> 163 select GPIOLIB
>> 164 select SYS_SUPPORTS_ZBOOT
>> 165 select COMMON_CLK
306 166
307 config ARM64_CONT_PMD_SHIFT !! 167 config AR7
308 int !! 168 bool "Texas Instruments AR7"
309 default 5 if PAGE_SIZE_64KB !! 169 select BOOT_ELF32
310 default 5 if PAGE_SIZE_16KB !! 170 select DMA_NONCOHERENT
311 default 4 !! 171 select CEVT_R4K
>> 172 select CSRC_R4K
>> 173 select IRQ_MIPS_CPU
>> 174 select NO_EXCEPT_FILL
>> 175 select SWAP_IO_SPACE
>> 176 select SYS_HAS_CPU_MIPS32_R1
>> 177 select SYS_HAS_EARLY_PRINTK
>> 178 select SYS_SUPPORTS_32BIT_KERNEL
>> 179 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 180 select SYS_SUPPORTS_MIPS16
>> 181 select SYS_SUPPORTS_ZBOOT_UART16550
>> 182 select GPIOLIB
>> 183 select VLYNQ
>> 184 select HAVE_CLK
>> 185 help
>> 186 Support for the Texas Instruments AR7 System-on-a-Chip
>> 187 family: TNETD7100, 7200 and 7300.
>> 188
>> 189 config ATH25
>> 190 bool "Atheros AR231x/AR531x SoC support"
>> 191 select CEVT_R4K
>> 192 select CSRC_R4K
>> 193 select DMA_NONCOHERENT
>> 194 select IRQ_MIPS_CPU
>> 195 select IRQ_DOMAIN
>> 196 select SYS_HAS_CPU_MIPS32_R1
>> 197 select SYS_SUPPORTS_BIG_ENDIAN
>> 198 select SYS_SUPPORTS_32BIT_KERNEL
>> 199 select SYS_HAS_EARLY_PRINTK
>> 200 help
>> 201 Support for Atheros AR231x and Atheros AR531x based boards
>> 202
>> 203 config ATH79
>> 204 bool "Atheros AR71XX/AR724X/AR913X based boards"
>> 205 select ARCH_HAS_RESET_CONTROLLER
>> 206 select BOOT_RAW
>> 207 select CEVT_R4K
>> 208 select CSRC_R4K
>> 209 select DMA_NONCOHERENT
>> 210 select GPIOLIB
>> 211 select PINCTRL
>> 212 select HAVE_CLK
>> 213 select COMMON_CLK
>> 214 select CLKDEV_LOOKUP
>> 215 select IRQ_MIPS_CPU
>> 216 select SYS_HAS_CPU_MIPS32_R2
>> 217 select SYS_HAS_EARLY_PRINTK
>> 218 select SYS_SUPPORTS_32BIT_KERNEL
>> 219 select SYS_SUPPORTS_BIG_ENDIAN
>> 220 select SYS_SUPPORTS_MIPS16
>> 221 select SYS_SUPPORTS_ZBOOT_UART_PROM
>> 222 select USE_OF
>> 223 select USB_EHCI_ROOT_HUB_TT if USB_EHCI_HCD_PLATFORM
>> 224 help
>> 225 Support for the Atheros AR71XX/AR724X/AR913X SoCs.
>> 226
>> 227 config BMIPS_GENERIC
>> 228 bool "Broadcom Generic BMIPS kernel"
>> 229 select ARCH_HAS_SYNC_DMA_FOR_CPU_ALL
>> 230 select ARCH_HAS_PHYS_TO_DMA
>> 231 select BOOT_RAW
>> 232 select NO_EXCEPT_FILL
>> 233 select USE_OF
>> 234 select CEVT_R4K
>> 235 select CSRC_R4K
>> 236 select SYNC_R4K
>> 237 select COMMON_CLK
>> 238 select BCM6345_L1_IRQ
>> 239 select BCM7038_L1_IRQ
>> 240 select BCM7120_L2_IRQ
>> 241 select BRCMSTB_L2_IRQ
>> 242 select IRQ_MIPS_CPU
>> 243 select DMA_NONCOHERENT
>> 244 select SYS_SUPPORTS_32BIT_KERNEL
>> 245 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 246 select SYS_SUPPORTS_BIG_ENDIAN
>> 247 select SYS_SUPPORTS_HIGHMEM
>> 248 select SYS_HAS_CPU_BMIPS32_3300
>> 249 select SYS_HAS_CPU_BMIPS4350
>> 250 select SYS_HAS_CPU_BMIPS4380
>> 251 select SYS_HAS_CPU_BMIPS5000
>> 252 select SWAP_IO_SPACE
>> 253 select USB_EHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
>> 254 select USB_EHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 255 select USB_OHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
>> 256 select USB_OHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 257 select HARDIRQS_SW_RESEND
>> 258 help
>> 259 Build a generic DT-based kernel image that boots on select
>> 260 BCM33xx cable modem chips, BCM63xx DSL chips, and BCM7xxx set-top
>> 261 box chips. Note that CONFIG_CPU_BIG_ENDIAN/CONFIG_CPU_LITTLE_ENDIAN
>> 262 must be set appropriately for your board.
>> 263
>> 264 config BCM47XX
>> 265 bool "Broadcom BCM47XX based boards"
>> 266 select BOOT_RAW
>> 267 select CEVT_R4K
>> 268 select CSRC_R4K
>> 269 select DMA_NONCOHERENT
>> 270 select HAVE_PCI
>> 271 select IRQ_MIPS_CPU
>> 272 select SYS_HAS_CPU_MIPS32_R1
>> 273 select NO_EXCEPT_FILL
>> 274 select SYS_SUPPORTS_32BIT_KERNEL
>> 275 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 276 select SYS_SUPPORTS_MIPS16
>> 277 select SYS_SUPPORTS_ZBOOT
>> 278 select SYS_HAS_EARLY_PRINTK
>> 279 select USE_GENERIC_EARLY_PRINTK_8250
>> 280 select GPIOLIB
>> 281 select LEDS_GPIO_REGISTER
>> 282 select BCM47XX_NVRAM
>> 283 select BCM47XX_SPROM
>> 284 select BCM47XX_SSB if !BCM47XX_BCMA
>> 285 help
>> 286 Support for BCM47XX based boards
>> 287
>> 288 config BCM63XX
>> 289 bool "Broadcom BCM63XX based boards"
>> 290 select BOOT_RAW
>> 291 select CEVT_R4K
>> 292 select CSRC_R4K
>> 293 select SYNC_R4K
>> 294 select DMA_NONCOHERENT
>> 295 select IRQ_MIPS_CPU
>> 296 select SYS_SUPPORTS_32BIT_KERNEL
>> 297 select SYS_SUPPORTS_BIG_ENDIAN
>> 298 select SYS_HAS_EARLY_PRINTK
>> 299 select SWAP_IO_SPACE
>> 300 select GPIOLIB
>> 301 select HAVE_CLK
>> 302 select MIPS_L1_CACHE_SHIFT_4
>> 303 select CLKDEV_LOOKUP
>> 304 help
>> 305 Support for BCM63XX based boards
>> 306
>> 307 config MIPS_COBALT
>> 308 bool "Cobalt Server"
>> 309 select CEVT_R4K
>> 310 select CSRC_R4K
>> 311 select CEVT_GT641XX
>> 312 select DMA_NONCOHERENT
>> 313 select FORCE_PCI
>> 314 select I8253
>> 315 select I8259
>> 316 select IRQ_MIPS_CPU
>> 317 select IRQ_GT641XX
>> 318 select PCI_GT64XXX_PCI0
>> 319 select SYS_HAS_CPU_NEVADA
>> 320 select SYS_HAS_EARLY_PRINTK
>> 321 select SYS_SUPPORTS_32BIT_KERNEL
>> 322 select SYS_SUPPORTS_64BIT_KERNEL
>> 323 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 324 select USE_GENERIC_EARLY_PRINTK_8250
>> 325
>> 326 config MACH_DECSTATION
>> 327 bool "DECstations"
>> 328 select BOOT_ELF32
>> 329 select CEVT_DS1287
>> 330 select CEVT_R4K if CPU_R4X00
>> 331 select CSRC_IOASIC
>> 332 select CSRC_R4K if CPU_R4X00
>> 333 select CPU_DADDI_WORKAROUNDS if 64BIT
>> 334 select CPU_R4000_WORKAROUNDS if 64BIT
>> 335 select CPU_R4400_WORKAROUNDS if 64BIT
>> 336 select DMA_NONCOHERENT
>> 337 select NO_IOPORT_MAP
>> 338 select IRQ_MIPS_CPU
>> 339 select SYS_HAS_CPU_R3000
>> 340 select SYS_HAS_CPU_R4X00
>> 341 select SYS_SUPPORTS_32BIT_KERNEL
>> 342 select SYS_SUPPORTS_64BIT_KERNEL
>> 343 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 344 select SYS_SUPPORTS_128HZ
>> 345 select SYS_SUPPORTS_256HZ
>> 346 select SYS_SUPPORTS_1024HZ
>> 347 select MIPS_L1_CACHE_SHIFT_4
>> 348 help
>> 349 This enables support for DEC's MIPS based workstations. For details
>> 350 see the Linux/MIPS FAQ on <http://www.linux-mips.org/> and the
>> 351 DECstation porting pages on <http://decstation.unix-ag.org/>.
>> 352
>> 353 If you have one of the following DECstation Models you definitely
>> 354 want to choose R4xx0 for the CPU Type:
>> 355
>> 356 DECstation 5000/50
>> 357 DECstation 5000/150
>> 358 DECstation 5000/260
>> 359 DECsystem 5900/260
>> 360
>> 361 otherwise choose R3000.
>> 362
>> 363 config MACH_JAZZ
>> 364 bool "Jazz family of machines"
>> 365 select ARC_MEMORY
>> 366 select ARC_PROMLIB
>> 367 select ARCH_MIGHT_HAVE_PC_PARPORT
>> 368 select ARCH_MIGHT_HAVE_PC_SERIO
>> 369 select FW_ARC
>> 370 select FW_ARC32
>> 371 select ARCH_MAY_HAVE_PC_FDC
>> 372 select CEVT_R4K
>> 373 select CSRC_R4K
>> 374 select DEFAULT_SGI_PARTITION if CPU_BIG_ENDIAN
>> 375 select GENERIC_ISA_DMA
>> 376 select HAVE_PCSPKR_PLATFORM
>> 377 select IRQ_MIPS_CPU
>> 378 select I8253
>> 379 select I8259
>> 380 select ISA
>> 381 select SYS_HAS_CPU_R4X00
>> 382 select SYS_SUPPORTS_32BIT_KERNEL
>> 383 select SYS_SUPPORTS_64BIT_KERNEL
>> 384 select SYS_SUPPORTS_100HZ
>> 385 help
>> 386 This a family of machines based on the MIPS R4030 chipset which was
>> 387 used by several vendors to build RISC/os and Windows NT workstations.
>> 388 Members include the Acer PICA, MIPS Magnum 4000, MIPS Millennium and
>> 389 Olivetti M700-10 workstations.
>> 390
>> 391 config MACH_INGENIC
>> 392 bool "Ingenic SoC based machines"
>> 393 select SYS_SUPPORTS_32BIT_KERNEL
>> 394 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 395 select SYS_SUPPORTS_ZBOOT_UART16550
>> 396 select CPU_SUPPORTS_HUGEPAGES
>> 397 select DMA_NONCOHERENT
>> 398 select IRQ_MIPS_CPU
>> 399 select PINCTRL
>> 400 select GPIOLIB
>> 401 select COMMON_CLK
>> 402 select GENERIC_IRQ_CHIP
>> 403 select BUILTIN_DTB if MIPS_NO_APPENDED_DTB
>> 404 select USE_OF
>> 405
>> 406 config LANTIQ
>> 407 bool "Lantiq based platforms"
>> 408 select DMA_NONCOHERENT
>> 409 select IRQ_MIPS_CPU
>> 410 select CEVT_R4K
>> 411 select CSRC_R4K
>> 412 select SYS_HAS_CPU_MIPS32_R1
>> 413 select SYS_HAS_CPU_MIPS32_R2
>> 414 select SYS_SUPPORTS_BIG_ENDIAN
>> 415 select SYS_SUPPORTS_32BIT_KERNEL
>> 416 select SYS_SUPPORTS_MIPS16
>> 417 select SYS_SUPPORTS_MULTITHREADING
>> 418 select SYS_SUPPORTS_VPE_LOADER
>> 419 select SYS_HAS_EARLY_PRINTK
>> 420 select GPIOLIB
>> 421 select SWAP_IO_SPACE
>> 422 select BOOT_RAW
>> 423 select CLKDEV_LOOKUP
>> 424 select USE_OF
>> 425 select PINCTRL
>> 426 select PINCTRL_LANTIQ
>> 427 select ARCH_HAS_RESET_CONTROLLER
>> 428 select RESET_CONTROLLER
>> 429
>> 430 config LASAT
>> 431 bool "LASAT Networks platforms"
>> 432 select CEVT_R4K
>> 433 select CRC32
>> 434 select CSRC_R4K
>> 435 select DMA_NONCOHERENT
>> 436 select SYS_HAS_EARLY_PRINTK
>> 437 select HAVE_PCI
>> 438 select IRQ_MIPS_CPU
>> 439 select PCI_GT64XXX_PCI0
>> 440 select MIPS_NILE4
>> 441 select R5000_CPU_SCACHE
>> 442 select SYS_HAS_CPU_R5000
>> 443 select SYS_SUPPORTS_32BIT_KERNEL
>> 444 select SYS_SUPPORTS_64BIT_KERNEL if BROKEN
>> 445 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 446
>> 447 config MACH_LOONGSON32
>> 448 bool "Loongson 32-bit family of machines"
>> 449 select SYS_SUPPORTS_ZBOOT
>> 450 help
>> 451 This enables support for the Loongson-1 family of machines.
>> 452
>> 453 Loongson-1 is a family of 32-bit MIPS-compatible SoCs developed by
>> 454 the Institute of Computing Technology (ICT), Chinese Academy of
>> 455 Sciences (CAS).
>> 456
>> 457 config MACH_LOONGSON2EF
>> 458 bool "Loongson-2E/F family of machines"
>> 459 select SYS_SUPPORTS_ZBOOT
>> 460 help
>> 461 This enables the support of early Loongson-2E/F family of machines.
>> 462
>> 463 config MACH_LOONGSON64
>> 464 bool "Loongson 64-bit family of machines"
>> 465 select ARCH_SPARSEMEM_ENABLE
>> 466 select ARCH_MIGHT_HAVE_PC_PARPORT
>> 467 select ARCH_MIGHT_HAVE_PC_SERIO
>> 468 select GENERIC_ISA_DMA_SUPPORT_BROKEN
>> 469 select BOOT_ELF32
>> 470 select BOARD_SCACHE
>> 471 select CSRC_R4K
>> 472 select CEVT_R4K
>> 473 select CPU_HAS_WB
>> 474 select FORCE_PCI
>> 475 select ISA
>> 476 select I8259
>> 477 select IRQ_MIPS_CPU
>> 478 select NR_CPUS_DEFAULT_4
>> 479 select USE_GENERIC_EARLY_PRINTK_8250
>> 480 select SYS_HAS_CPU_LOONGSON64
>> 481 select SYS_HAS_EARLY_PRINTK
>> 482 select SYS_SUPPORTS_SMP
>> 483 select SYS_SUPPORTS_HOTPLUG_CPU
>> 484 select SYS_SUPPORTS_NUMA
>> 485 select SYS_SUPPORTS_64BIT_KERNEL
>> 486 select SYS_SUPPORTS_HIGHMEM
>> 487 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 488 select SYS_SUPPORTS_ZBOOT
>> 489 select ZONE_DMA32
>> 490 select NUMA
>> 491 select COMMON_CLK
>> 492 select USE_OF
>> 493 select BUILTIN_DTB
>> 494 help
>> 495 This enables the support of Loongson-2/3 family of machines.
312 496
313 config ARCH_MMAP_RND_BITS_MIN !! 497 Loongson-2 and Loongson-3 are 64-bit general-purpose processors with
314 default 14 if PAGE_SIZE_64KB !! 498 GS264/GS464/GS464E/GS464V microarchitecture (except old Loongson-2E
315 default 16 if PAGE_SIZE_16KB !! 499 and Loongson-2F which will be removed), developed by the Institute
316 default 18 !! 500 of Computing Technology (ICT), Chinese Academy of Sciences (CAS).
>> 501
>> 502 config MACH_PISTACHIO
>> 503 bool "IMG Pistachio SoC based boards"
>> 504 select BOOT_ELF32
>> 505 select BOOT_RAW
>> 506 select CEVT_R4K
>> 507 select CLKSRC_MIPS_GIC
>> 508 select COMMON_CLK
>> 509 select CSRC_R4K
>> 510 select DMA_NONCOHERENT
>> 511 select GPIOLIB
>> 512 select IRQ_MIPS_CPU
>> 513 select MFD_SYSCON
>> 514 select MIPS_CPU_SCACHE
>> 515 select MIPS_GIC
>> 516 select PINCTRL
>> 517 select REGULATOR
>> 518 select SYS_HAS_CPU_MIPS32_R2
>> 519 select SYS_SUPPORTS_32BIT_KERNEL
>> 520 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 521 select SYS_SUPPORTS_MIPS_CPS
>> 522 select SYS_SUPPORTS_MULTITHREADING
>> 523 select SYS_SUPPORTS_RELOCATABLE
>> 524 select SYS_SUPPORTS_ZBOOT
>> 525 select SYS_HAS_EARLY_PRINTK
>> 526 select USE_GENERIC_EARLY_PRINTK_8250
>> 527 select USE_OF
>> 528 help
>> 529 This enables support for the IMG Pistachio SoC platform.
>> 530
>> 531 config MIPS_MALTA
>> 532 bool "MIPS Malta board"
>> 533 select ARCH_MAY_HAVE_PC_FDC
>> 534 select ARCH_MIGHT_HAVE_PC_PARPORT
>> 535 select ARCH_MIGHT_HAVE_PC_SERIO
>> 536 select BOOT_ELF32
>> 537 select BOOT_RAW
>> 538 select BUILTIN_DTB
>> 539 select CEVT_R4K
>> 540 select CLKSRC_MIPS_GIC
>> 541 select COMMON_CLK
>> 542 select CSRC_R4K
>> 543 select DMA_MAYBE_COHERENT
>> 544 select GENERIC_ISA_DMA
>> 545 select HAVE_PCSPKR_PLATFORM
>> 546 select HAVE_PCI
>> 547 select I8253
>> 548 select I8259
>> 549 select IRQ_MIPS_CPU
>> 550 select MIPS_BONITO64
>> 551 select MIPS_CPU_SCACHE
>> 552 select MIPS_GIC
>> 553 select MIPS_L1_CACHE_SHIFT_6
>> 554 select MIPS_MSC
>> 555 select PCI_GT64XXX_PCI0
>> 556 select SMP_UP if SMP
>> 557 select SWAP_IO_SPACE
>> 558 select SYS_HAS_CPU_MIPS32_R1
>> 559 select SYS_HAS_CPU_MIPS32_R2
>> 560 select SYS_HAS_CPU_MIPS32_R3_5
>> 561 select SYS_HAS_CPU_MIPS32_R5
>> 562 select SYS_HAS_CPU_MIPS32_R6
>> 563 select SYS_HAS_CPU_MIPS64_R1
>> 564 select SYS_HAS_CPU_MIPS64_R2
>> 565 select SYS_HAS_CPU_MIPS64_R6
>> 566 select SYS_HAS_CPU_NEVADA
>> 567 select SYS_HAS_CPU_RM7000
>> 568 select SYS_SUPPORTS_32BIT_KERNEL
>> 569 select SYS_SUPPORTS_64BIT_KERNEL
>> 570 select SYS_SUPPORTS_BIG_ENDIAN
>> 571 select SYS_SUPPORTS_HIGHMEM
>> 572 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 573 select SYS_SUPPORTS_MICROMIPS
>> 574 select SYS_SUPPORTS_MIPS16
>> 575 select SYS_SUPPORTS_MIPS_CMP
>> 576 select SYS_SUPPORTS_MIPS_CPS
>> 577 select SYS_SUPPORTS_MULTITHREADING
>> 578 select SYS_SUPPORTS_RELOCATABLE
>> 579 select SYS_SUPPORTS_SMARTMIPS
>> 580 select SYS_SUPPORTS_VPE_LOADER
>> 581 select SYS_SUPPORTS_ZBOOT
>> 582 select USE_OF
>> 583 select ZONE_DMA32 if 64BIT
>> 584 help
>> 585 This enables support for the MIPS Technologies Malta evaluation
>> 586 board.
>> 587
>> 588 config MACH_PIC32
>> 589 bool "Microchip PIC32 Family"
>> 590 help
>> 591 This enables support for the Microchip PIC32 family of platforms.
>> 592
>> 593 Microchip PIC32 is a family of general-purpose 32 bit MIPS core
>> 594 microcontrollers.
>> 595
>> 596 config NEC_MARKEINS
>> 597 bool "NEC EMMA2RH Mark-eins board"
>> 598 select SOC_EMMA2RH
>> 599 select HAVE_PCI
>> 600 help
>> 601 This enables support for the NEC Electronics Mark-eins boards.
317 602
318 # max bits determined by the following formula !! 603 config MACH_VR41XX
319 # VA_BITS - PAGE_SHIFT - 3 !! 604 bool "NEC VR4100 series based machines"
320 config ARCH_MMAP_RND_BITS_MAX !! 605 select CEVT_R4K
321 default 19 if ARM64_VA_BITS=36 !! 606 select CSRC_R4K
322 default 24 if ARM64_VA_BITS=39 !! 607 select SYS_HAS_CPU_VR41XX
323 default 27 if ARM64_VA_BITS=42 !! 608 select SYS_SUPPORTS_MIPS16
324 default 30 if ARM64_VA_BITS=47 !! 609 select GPIOLIB
325 default 29 if ARM64_VA_BITS=48 && ARM6 !! 610
326 default 31 if ARM64_VA_BITS=48 && ARM6 !! 611 config NXP_STB220
327 default 33 if ARM64_VA_BITS=48 !! 612 bool "NXP STB220 board"
328 default 14 if ARM64_64K_PAGES !! 613 select SOC_PNX833X
329 default 16 if ARM64_16K_PAGES !! 614 help
330 default 18 !! 615 Support for NXP Semiconductors STB220 Development Board.
>> 616
>> 617 config NXP_STB225
>> 618 bool "NXP 225 board"
>> 619 select SOC_PNX833X
>> 620 select SOC_PNX8335
>> 621 help
>> 622 Support for NXP Semiconductors STB225 Development Board.
>> 623
>> 624 config PMC_MSP
>> 625 bool "PMC-Sierra MSP chipsets"
>> 626 select CEVT_R4K
>> 627 select CSRC_R4K
>> 628 select DMA_NONCOHERENT
>> 629 select SWAP_IO_SPACE
>> 630 select NO_EXCEPT_FILL
>> 631 select BOOT_RAW
>> 632 select SYS_HAS_CPU_MIPS32_R1
>> 633 select SYS_HAS_CPU_MIPS32_R2
>> 634 select SYS_SUPPORTS_32BIT_KERNEL
>> 635 select SYS_SUPPORTS_BIG_ENDIAN
>> 636 select SYS_SUPPORTS_MIPS16
>> 637 select IRQ_MIPS_CPU
>> 638 select SERIAL_8250
>> 639 select SERIAL_8250_CONSOLE
>> 640 select USB_EHCI_BIG_ENDIAN_MMIO
>> 641 select USB_EHCI_BIG_ENDIAN_DESC
>> 642 help
>> 643 This adds support for the PMC-Sierra family of Multi-Service
>> 644 Processor System-On-A-Chips. These parts include a number
>> 645 of integrated peripherals, interfaces and DSPs in addition to
>> 646 a variety of MIPS cores.
>> 647
>> 648 config RALINK
>> 649 bool "Ralink based machines"
>> 650 select CEVT_R4K
>> 651 select CSRC_R4K
>> 652 select BOOT_RAW
>> 653 select DMA_NONCOHERENT
>> 654 select IRQ_MIPS_CPU
>> 655 select USE_OF
>> 656 select SYS_HAS_CPU_MIPS32_R1
>> 657 select SYS_HAS_CPU_MIPS32_R2
>> 658 select SYS_SUPPORTS_32BIT_KERNEL
>> 659 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 660 select SYS_SUPPORTS_MIPS16
>> 661 select SYS_HAS_EARLY_PRINTK
>> 662 select CLKDEV_LOOKUP
>> 663 select ARCH_HAS_RESET_CONTROLLER
>> 664 select RESET_CONTROLLER
>> 665
>> 666 config SGI_IP22
>> 667 bool "SGI IP22 (Indy/Indigo2)"
>> 668 select ARC_MEMORY
>> 669 select ARC_PROMLIB
>> 670 select FW_ARC
>> 671 select FW_ARC32
>> 672 select ARCH_MIGHT_HAVE_PC_SERIO
>> 673 select BOOT_ELF32
>> 674 select CEVT_R4K
>> 675 select CSRC_R4K
>> 676 select DEFAULT_SGI_PARTITION
>> 677 select DMA_NONCOHERENT
>> 678 select HAVE_EISA
>> 679 select I8253
>> 680 select I8259
>> 681 select IP22_CPU_SCACHE
>> 682 select IRQ_MIPS_CPU
>> 683 select GENERIC_ISA_DMA_SUPPORT_BROKEN
>> 684 select SGI_HAS_I8042
>> 685 select SGI_HAS_INDYDOG
>> 686 select SGI_HAS_HAL2
>> 687 select SGI_HAS_SEEQ
>> 688 select SGI_HAS_WD93
>> 689 select SGI_HAS_ZILOG
>> 690 select SWAP_IO_SPACE
>> 691 select SYS_HAS_CPU_R4X00
>> 692 select SYS_HAS_CPU_R5000
>> 693 select SYS_HAS_EARLY_PRINTK
>> 694 select SYS_SUPPORTS_32BIT_KERNEL
>> 695 select SYS_SUPPORTS_64BIT_KERNEL
>> 696 select SYS_SUPPORTS_BIG_ENDIAN
>> 697 select MIPS_L1_CACHE_SHIFT_7
>> 698 help
>> 699 This are the SGI Indy, Challenge S and Indigo2, as well as certain
>> 700 OEM variants like the Tandem CMN B006S. To compile a Linux kernel
>> 701 that runs on these, say Y here.
>> 702
>> 703 config SGI_IP27
>> 704 bool "SGI IP27 (Origin200/2000)"
>> 705 select ARCH_HAS_PHYS_TO_DMA
>> 706 select ARCH_SPARSEMEM_ENABLE
>> 707 select FW_ARC
>> 708 select FW_ARC64
>> 709 select ARC_CMDLINE_ONLY
>> 710 select BOOT_ELF64
>> 711 select DEFAULT_SGI_PARTITION
>> 712 select SYS_HAS_EARLY_PRINTK
>> 713 select HAVE_PCI
>> 714 select IRQ_MIPS_CPU
>> 715 select IRQ_DOMAIN_HIERARCHY
>> 716 select NR_CPUS_DEFAULT_64
>> 717 select PCI_DRIVERS_GENERIC
>> 718 select PCI_XTALK_BRIDGE
>> 719 select SYS_HAS_CPU_R10000
>> 720 select SYS_SUPPORTS_64BIT_KERNEL
>> 721 select SYS_SUPPORTS_BIG_ENDIAN
>> 722 select SYS_SUPPORTS_NUMA
>> 723 select SYS_SUPPORTS_SMP
>> 724 select MIPS_L1_CACHE_SHIFT_7
>> 725 select NUMA
>> 726 help
>> 727 This are the SGI Origin 200, Origin 2000 and Onyx 2 Graphics
>> 728 workstations. To compile a Linux kernel that runs on these, say Y
>> 729 here.
>> 730
>> 731 config SGI_IP28
>> 732 bool "SGI IP28 (Indigo2 R10k)"
>> 733 select ARC_MEMORY
>> 734 select ARC_PROMLIB
>> 735 select FW_ARC
>> 736 select FW_ARC64
>> 737 select ARCH_MIGHT_HAVE_PC_SERIO
>> 738 select BOOT_ELF64
>> 739 select CEVT_R4K
>> 740 select CSRC_R4K
>> 741 select DEFAULT_SGI_PARTITION
>> 742 select DMA_NONCOHERENT
>> 743 select GENERIC_ISA_DMA_SUPPORT_BROKEN
>> 744 select IRQ_MIPS_CPU
>> 745 select HAVE_EISA
>> 746 select I8253
>> 747 select I8259
>> 748 select SGI_HAS_I8042
>> 749 select SGI_HAS_INDYDOG
>> 750 select SGI_HAS_HAL2
>> 751 select SGI_HAS_SEEQ
>> 752 select SGI_HAS_WD93
>> 753 select SGI_HAS_ZILOG
>> 754 select SWAP_IO_SPACE
>> 755 select SYS_HAS_CPU_R10000
>> 756 select SYS_HAS_EARLY_PRINTK
>> 757 select SYS_SUPPORTS_64BIT_KERNEL
>> 758 select SYS_SUPPORTS_BIG_ENDIAN
>> 759 select MIPS_L1_CACHE_SHIFT_7
>> 760 help
>> 761 This is the SGI Indigo2 with R10000 processor. To compile a Linux
>> 762 kernel that runs on these, say Y here.
>> 763
>> 764 config SGI_IP30
>> 765 bool "SGI IP30 (Octane/Octane2)"
>> 766 select ARCH_HAS_PHYS_TO_DMA
>> 767 select FW_ARC
>> 768 select FW_ARC64
>> 769 select BOOT_ELF64
>> 770 select CEVT_R4K
>> 771 select CSRC_R4K
>> 772 select SYNC_R4K if SMP
>> 773 select ZONE_DMA32
>> 774 select HAVE_PCI
>> 775 select IRQ_MIPS_CPU
>> 776 select IRQ_DOMAIN_HIERARCHY
>> 777 select NR_CPUS_DEFAULT_2
>> 778 select PCI_DRIVERS_GENERIC
>> 779 select PCI_XTALK_BRIDGE
>> 780 select SYS_HAS_EARLY_PRINTK
>> 781 select SYS_HAS_CPU_R10000
>> 782 select SYS_SUPPORTS_64BIT_KERNEL
>> 783 select SYS_SUPPORTS_BIG_ENDIAN
>> 784 select SYS_SUPPORTS_SMP
>> 785 select MIPS_L1_CACHE_SHIFT_7
>> 786 select ARC_MEMORY
>> 787 help
>> 788 These are the SGI Octane and Octane2 graphics workstations. To
>> 789 compile a Linux kernel that runs on these, say Y here.
>> 790
>> 791 config SGI_IP32
>> 792 bool "SGI IP32 (O2)"
>> 793 select ARC_MEMORY
>> 794 select ARC_PROMLIB
>> 795 select ARCH_HAS_PHYS_TO_DMA
>> 796 select FW_ARC
>> 797 select FW_ARC32
>> 798 select BOOT_ELF32
>> 799 select CEVT_R4K
>> 800 select CSRC_R4K
>> 801 select DMA_NONCOHERENT
>> 802 select HAVE_PCI
>> 803 select IRQ_MIPS_CPU
>> 804 select R5000_CPU_SCACHE
>> 805 select RM7000_CPU_SCACHE
>> 806 select SYS_HAS_CPU_R5000
>> 807 select SYS_HAS_CPU_R10000 if BROKEN
>> 808 select SYS_HAS_CPU_RM7000
>> 809 select SYS_HAS_CPU_NEVADA
>> 810 select SYS_SUPPORTS_64BIT_KERNEL
>> 811 select SYS_SUPPORTS_BIG_ENDIAN
>> 812 help
>> 813 If you want this kernel to run on SGI O2 workstation, say Y here.
>> 814
>> 815 config SIBYTE_CRHINE
>> 816 bool "Sibyte BCM91120C-CRhine"
>> 817 select BOOT_ELF32
>> 818 select SIBYTE_BCM1120
>> 819 select SWAP_IO_SPACE
>> 820 select SYS_HAS_CPU_SB1
>> 821 select SYS_SUPPORTS_BIG_ENDIAN
>> 822 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 823
>> 824 config SIBYTE_CARMEL
>> 825 bool "Sibyte BCM91120x-Carmel"
>> 826 select BOOT_ELF32
>> 827 select SIBYTE_BCM1120
>> 828 select SWAP_IO_SPACE
>> 829 select SYS_HAS_CPU_SB1
>> 830 select SYS_SUPPORTS_BIG_ENDIAN
>> 831 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 832
>> 833 config SIBYTE_CRHONE
>> 834 bool "Sibyte BCM91125C-CRhone"
>> 835 select BOOT_ELF32
>> 836 select SIBYTE_BCM1125
>> 837 select SWAP_IO_SPACE
>> 838 select SYS_HAS_CPU_SB1
>> 839 select SYS_SUPPORTS_BIG_ENDIAN
>> 840 select SYS_SUPPORTS_HIGHMEM
>> 841 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 842
>> 843 config SIBYTE_RHONE
>> 844 bool "Sibyte BCM91125E-Rhone"
>> 845 select BOOT_ELF32
>> 846 select SIBYTE_BCM1125H
>> 847 select SWAP_IO_SPACE
>> 848 select SYS_HAS_CPU_SB1
>> 849 select SYS_SUPPORTS_BIG_ENDIAN
>> 850 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 851
>> 852 config SIBYTE_SWARM
>> 853 bool "Sibyte BCM91250A-SWARM"
>> 854 select BOOT_ELF32
>> 855 select HAVE_PATA_PLATFORM
>> 856 select SIBYTE_SB1250
>> 857 select SWAP_IO_SPACE
>> 858 select SYS_HAS_CPU_SB1
>> 859 select SYS_SUPPORTS_BIG_ENDIAN
>> 860 select SYS_SUPPORTS_HIGHMEM
>> 861 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 862 select ZONE_DMA32 if 64BIT
>> 863 select SWIOTLB if ARCH_DMA_ADDR_T_64BIT && PCI
>> 864
>> 865 config SIBYTE_LITTLESUR
>> 866 bool "Sibyte BCM91250C2-LittleSur"
>> 867 select BOOT_ELF32
>> 868 select HAVE_PATA_PLATFORM
>> 869 select SIBYTE_SB1250
>> 870 select SWAP_IO_SPACE
>> 871 select SYS_HAS_CPU_SB1
>> 872 select SYS_SUPPORTS_BIG_ENDIAN
>> 873 select SYS_SUPPORTS_HIGHMEM
>> 874 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 875 select ZONE_DMA32 if 64BIT
>> 876
>> 877 config SIBYTE_SENTOSA
>> 878 bool "Sibyte BCM91250E-Sentosa"
>> 879 select BOOT_ELF32
>> 880 select SIBYTE_SB1250
>> 881 select SWAP_IO_SPACE
>> 882 select SYS_HAS_CPU_SB1
>> 883 select SYS_SUPPORTS_BIG_ENDIAN
>> 884 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 885 select SWIOTLB if ARCH_DMA_ADDR_T_64BIT && PCI
>> 886
>> 887 config SIBYTE_BIGSUR
>> 888 bool "Sibyte BCM91480B-BigSur"
>> 889 select BOOT_ELF32
>> 890 select NR_CPUS_DEFAULT_4
>> 891 select SIBYTE_BCM1x80
>> 892 select SWAP_IO_SPACE
>> 893 select SYS_HAS_CPU_SB1
>> 894 select SYS_SUPPORTS_BIG_ENDIAN
>> 895 select SYS_SUPPORTS_HIGHMEM
>> 896 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 897 select ZONE_DMA32 if 64BIT
>> 898 select SWIOTLB if ARCH_DMA_ADDR_T_64BIT && PCI
>> 899
>> 900 config SNI_RM
>> 901 bool "SNI RM200/300/400"
>> 902 select ARC_MEMORY
>> 903 select ARC_PROMLIB
>> 904 select FW_ARC if CPU_LITTLE_ENDIAN
>> 905 select FW_ARC32 if CPU_LITTLE_ENDIAN
>> 906 select FW_SNIPROM if CPU_BIG_ENDIAN
>> 907 select ARCH_MAY_HAVE_PC_FDC
>> 908 select ARCH_MIGHT_HAVE_PC_PARPORT
>> 909 select ARCH_MIGHT_HAVE_PC_SERIO
>> 910 select BOOT_ELF32
>> 911 select CEVT_R4K
>> 912 select CSRC_R4K
>> 913 select DEFAULT_SGI_PARTITION if CPU_BIG_ENDIAN
>> 914 select DMA_NONCOHERENT
>> 915 select GENERIC_ISA_DMA
>> 916 select HAVE_EISA
>> 917 select HAVE_PCSPKR_PLATFORM
>> 918 select HAVE_PCI
>> 919 select IRQ_MIPS_CPU
>> 920 select I8253
>> 921 select I8259
>> 922 select ISA
>> 923 select SWAP_IO_SPACE if CPU_BIG_ENDIAN
>> 924 select SYS_HAS_CPU_R4X00
>> 925 select SYS_HAS_CPU_R5000
>> 926 select SYS_HAS_CPU_R10000
>> 927 select R5000_CPU_SCACHE
>> 928 select SYS_HAS_EARLY_PRINTK
>> 929 select SYS_SUPPORTS_32BIT_KERNEL
>> 930 select SYS_SUPPORTS_64BIT_KERNEL
>> 931 select SYS_SUPPORTS_BIG_ENDIAN
>> 932 select SYS_SUPPORTS_HIGHMEM
>> 933 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 934 help
>> 935 The SNI RM200/300/400 are MIPS-based machines manufactured by
>> 936 Siemens Nixdorf Informationssysteme (SNI), parent company of Pyramid
>> 937 Technology and now in turn merged with Fujitsu. Say Y here to
>> 938 support this machine type.
>> 939
>> 940 config MACH_TX39XX
>> 941 bool "Toshiba TX39 series based machines"
>> 942
>> 943 config MACH_TX49XX
>> 944 bool "Toshiba TX49 series based machines"
>> 945
>> 946 config MIKROTIK_RB532
>> 947 bool "Mikrotik RB532 boards"
>> 948 select CEVT_R4K
>> 949 select CSRC_R4K
>> 950 select DMA_NONCOHERENT
>> 951 select HAVE_PCI
>> 952 select IRQ_MIPS_CPU
>> 953 select SYS_HAS_CPU_MIPS32_R1
>> 954 select SYS_SUPPORTS_32BIT_KERNEL
>> 955 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 956 select SWAP_IO_SPACE
>> 957 select BOOT_RAW
>> 958 select GPIOLIB
>> 959 select MIPS_L1_CACHE_SHIFT_4
>> 960 help
>> 961 Support the Mikrotik(tm) RouterBoard 532 series,
>> 962 based on the IDT RC32434 SoC.
>> 963
>> 964 config CAVIUM_OCTEON_SOC
>> 965 bool "Cavium Networks Octeon SoC based boards"
>> 966 select CEVT_R4K
>> 967 select ARCH_HAS_PHYS_TO_DMA
>> 968 select HAVE_RAPIDIO
>> 969 select PHYS_ADDR_T_64BIT
>> 970 select SYS_SUPPORTS_64BIT_KERNEL
>> 971 select SYS_SUPPORTS_BIG_ENDIAN
>> 972 select EDAC_SUPPORT
>> 973 select EDAC_ATOMIC_SCRUB
>> 974 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 975 select SYS_SUPPORTS_HOTPLUG_CPU if CPU_BIG_ENDIAN
>> 976 select SYS_HAS_EARLY_PRINTK
>> 977 select SYS_HAS_CPU_CAVIUM_OCTEON
>> 978 select HAVE_PCI
>> 979 select HAVE_PLAT_DELAY
>> 980 select HAVE_PLAT_FW_INIT_CMDLINE
>> 981 select HAVE_PLAT_MEMCPY
>> 982 select ZONE_DMA32
>> 983 select HOLES_IN_ZONE
>> 984 select GPIOLIB
>> 985 select USE_OF
>> 986 select ARCH_SPARSEMEM_ENABLE
>> 987 select SYS_SUPPORTS_SMP
>> 988 select NR_CPUS_DEFAULT_64
>> 989 select MIPS_NR_CPU_NR_MAP_1024
>> 990 select BUILTIN_DTB
>> 991 select MTD_COMPLEX_MAPPINGS
>> 992 select SWIOTLB
>> 993 select SYS_SUPPORTS_RELOCATABLE
>> 994 help
>> 995 This option supports all of the Octeon reference boards from Cavium
>> 996 Networks. It builds a kernel that dynamically determines the Octeon
>> 997 CPU type and supports all known board reference implementations.
>> 998 Some of the supported boards are:
>> 999 EBT3000
>> 1000 EBH3000
>> 1001 EBH3100
>> 1002 Thunder
>> 1003 Kodama
>> 1004 Hikari
>> 1005 Say Y here for most Octeon reference boards.
>> 1006
>> 1007 config NLM_XLR_BOARD
>> 1008 bool "Netlogic XLR/XLS based systems"
>> 1009 select BOOT_ELF32
>> 1010 select NLM_COMMON
>> 1011 select SYS_HAS_CPU_XLR
>> 1012 select SYS_SUPPORTS_SMP
>> 1013 select HAVE_PCI
>> 1014 select SWAP_IO_SPACE
>> 1015 select SYS_SUPPORTS_32BIT_KERNEL
>> 1016 select SYS_SUPPORTS_64BIT_KERNEL
>> 1017 select PHYS_ADDR_T_64BIT
>> 1018 select SYS_SUPPORTS_BIG_ENDIAN
>> 1019 select SYS_SUPPORTS_HIGHMEM
>> 1020 select NR_CPUS_DEFAULT_32
>> 1021 select CEVT_R4K
>> 1022 select CSRC_R4K
>> 1023 select IRQ_MIPS_CPU
>> 1024 select ZONE_DMA32 if 64BIT
>> 1025 select SYNC_R4K
>> 1026 select SYS_HAS_EARLY_PRINTK
>> 1027 select SYS_SUPPORTS_ZBOOT
>> 1028 select SYS_SUPPORTS_ZBOOT_UART16550
>> 1029 help
>> 1030 Support for systems based on Netlogic XLR and XLS processors.
>> 1031 Say Y here if you have a XLR or XLS based board.
>> 1032
>> 1033 config NLM_XLP_BOARD
>> 1034 bool "Netlogic XLP based systems"
>> 1035 select BOOT_ELF32
>> 1036 select NLM_COMMON
>> 1037 select SYS_HAS_CPU_XLP
>> 1038 select SYS_SUPPORTS_SMP
>> 1039 select HAVE_PCI
>> 1040 select SYS_SUPPORTS_32BIT_KERNEL
>> 1041 select SYS_SUPPORTS_64BIT_KERNEL
>> 1042 select PHYS_ADDR_T_64BIT
>> 1043 select GPIOLIB
>> 1044 select SYS_SUPPORTS_BIG_ENDIAN
>> 1045 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 1046 select SYS_SUPPORTS_HIGHMEM
>> 1047 select NR_CPUS_DEFAULT_32
>> 1048 select CEVT_R4K
>> 1049 select CSRC_R4K
>> 1050 select IRQ_MIPS_CPU
>> 1051 select ZONE_DMA32 if 64BIT
>> 1052 select SYNC_R4K
>> 1053 select SYS_HAS_EARLY_PRINTK
>> 1054 select USE_OF
>> 1055 select SYS_SUPPORTS_ZBOOT
>> 1056 select SYS_SUPPORTS_ZBOOT_UART16550
>> 1057 help
>> 1058 This board is based on Netlogic XLP Processor.
>> 1059 Say Y here if you have a XLP based board.
>> 1060
>> 1061 config MIPS_PARAVIRT
>> 1062 bool "Para-Virtualized guest system"
>> 1063 select CEVT_R4K
>> 1064 select CSRC_R4K
>> 1065 select SYS_SUPPORTS_64BIT_KERNEL
>> 1066 select SYS_SUPPORTS_32BIT_KERNEL
>> 1067 select SYS_SUPPORTS_BIG_ENDIAN
>> 1068 select SYS_SUPPORTS_SMP
>> 1069 select NR_CPUS_DEFAULT_4
>> 1070 select SYS_HAS_EARLY_PRINTK
>> 1071 select SYS_HAS_CPU_MIPS32_R2
>> 1072 select SYS_HAS_CPU_MIPS64_R2
>> 1073 select SYS_HAS_CPU_CAVIUM_OCTEON
>> 1074 select HAVE_PCI
>> 1075 select SWAP_IO_SPACE
>> 1076 help
>> 1077 This option supports guest running under ????
331 1078
332 config ARCH_MMAP_RND_COMPAT_BITS_MIN !! 1079 endchoice
333 default 7 if ARM64_64K_PAGES <<
334 default 9 if ARM64_16K_PAGES <<
335 default 11 <<
336 1080
337 config ARCH_MMAP_RND_COMPAT_BITS_MAX !! 1081 source "arch/mips/alchemy/Kconfig"
338 default 16 !! 1082 source "arch/mips/ath25/Kconfig"
>> 1083 source "arch/mips/ath79/Kconfig"
>> 1084 source "arch/mips/bcm47xx/Kconfig"
>> 1085 source "arch/mips/bcm63xx/Kconfig"
>> 1086 source "arch/mips/bmips/Kconfig"
>> 1087 source "arch/mips/generic/Kconfig"
>> 1088 source "arch/mips/jazz/Kconfig"
>> 1089 source "arch/mips/jz4740/Kconfig"
>> 1090 source "arch/mips/lantiq/Kconfig"
>> 1091 source "arch/mips/lasat/Kconfig"
>> 1092 source "arch/mips/pic32/Kconfig"
>> 1093 source "arch/mips/pistachio/Kconfig"
>> 1094 source "arch/mips/pmcs-msp71xx/Kconfig"
>> 1095 source "arch/mips/ralink/Kconfig"
>> 1096 source "arch/mips/sgi-ip27/Kconfig"
>> 1097 source "arch/mips/sibyte/Kconfig"
>> 1098 source "arch/mips/txx9/Kconfig"
>> 1099 source "arch/mips/vr41xx/Kconfig"
>> 1100 source "arch/mips/cavium-octeon/Kconfig"
>> 1101 source "arch/mips/loongson2ef/Kconfig"
>> 1102 source "arch/mips/loongson32/Kconfig"
>> 1103 source "arch/mips/loongson64/Kconfig"
>> 1104 source "arch/mips/netlogic/Kconfig"
>> 1105 source "arch/mips/paravirt/Kconfig"
339 1106
340 config NO_IOPORT_MAP !! 1107 endmenu
341 def_bool y if !PCI <<
342 1108
343 config STACKTRACE_SUPPORT !! 1109 config GENERIC_HWEIGHT
344 def_bool y !! 1110 bool
>> 1111 default y
345 1112
346 config ILLEGAL_POINTER_VALUE !! 1113 config GENERIC_CALIBRATE_DELAY
347 hex !! 1114 bool
348 default 0xdead000000000000 !! 1115 default y
349 1116
350 config LOCKDEP_SUPPORT !! 1117 config SCHED_OMIT_FRAME_POINTER
351 def_bool y !! 1118 bool
>> 1119 default y
352 1120
353 config GENERIC_BUG !! 1121 #
354 def_bool y !! 1122 # Select some configuration options automatically based on user selections.
355 depends on BUG !! 1123 #
>> 1124 config FW_ARC
>> 1125 bool
356 1126
357 config GENERIC_BUG_RELATIVE_POINTERS !! 1127 config ARCH_MAY_HAVE_PC_FDC
358 def_bool y !! 1128 bool
359 depends on GENERIC_BUG <<
360 1129
361 config GENERIC_HWEIGHT !! 1130 config BOOT_RAW
362 def_bool y !! 1131 bool
363 1132
364 config GENERIC_CSUM !! 1133 config CEVT_BCM1480
365 def_bool y !! 1134 bool
366 1135
367 config GENERIC_CALIBRATE_DELAY !! 1136 config CEVT_DS1287
368 def_bool y !! 1137 bool
369 1138
370 config SMP !! 1139 config CEVT_GT641XX
371 def_bool y !! 1140 bool
372 1141
373 config KERNEL_MODE_NEON !! 1142 config CEVT_R4K
374 def_bool y !! 1143 bool
375 1144
376 config FIX_EARLYCON_MEM !! 1145 config CEVT_SB1250
377 def_bool y !! 1146 bool
378 1147
379 config PGTABLE_LEVELS !! 1148 config CEVT_TXX9
380 int !! 1149 bool
381 default 2 if ARM64_16K_PAGES && ARM64_ <<
382 default 2 if ARM64_64K_PAGES && ARM64_ <<
383 default 3 if ARM64_64K_PAGES && (ARM64 <<
384 default 3 if ARM64_4K_PAGES && ARM64_V <<
385 default 3 if ARM64_16K_PAGES && ARM64_ <<
386 default 4 if ARM64_16K_PAGES && (ARM64 <<
387 default 4 if !ARM64_64K_PAGES && ARM64 <<
388 default 5 if ARM64_4K_PAGES && ARM64_V <<
389 1150
390 config ARCH_SUPPORTS_UPROBES !! 1151 config CSRC_BCM1480
391 def_bool y !! 1152 bool
392 1153
393 config ARCH_PROC_KCORE_TEXT !! 1154 config CSRC_IOASIC
394 def_bool y !! 1155 bool
395 1156
396 config BROKEN_GAS_INST !! 1157 config CSRC_R4K
397 def_bool !$(as-instr,1:\n.inst 0\n.rep !! 1158 bool
398 1159
399 config BUILTIN_RETURN_ADDRESS_STRIPS_PAC !! 1160 config CSRC_SB1250
400 bool 1161 bool
401 # Clang's __builtin_return_address() s <<
402 # https://github.com/llvm/llvm-project <<
403 default y if CC_IS_CLANG <<
404 # GCC's __builtin_return_address() str <<
405 # and this was backported to 10.2.0, 9 <<
406 # https://gcc.gnu.org/bugzilla/show_bu <<
407 default y if CC_IS_GCC && (GCC_VERSION <<
408 default y if CC_IS_GCC && (GCC_VERSION <<
409 default y if CC_IS_GCC && (GCC_VERSION <<
410 default y if CC_IS_GCC && (GCC_VERSION <<
411 default n <<
412 1162
413 config KASAN_SHADOW_OFFSET !! 1163 config MIPS_CLOCK_VSYSCALL
414 hex !! 1164 def_bool CSRC_R4K || CLKSRC_MIPS_GIC
415 depends on KASAN_GENERIC || KASAN_SW_T <<
416 default 0xdfff800000000000 if (ARM64_V <<
417 default 0xdfffc00000000000 if (ARM64_V <<
418 default 0xdffffe0000000000 if ARM64_VA <<
419 default 0xdfffffc000000000 if ARM64_VA <<
420 default 0xdffffff800000000 if ARM64_VA <<
421 default 0xefff800000000000 if (ARM64_V <<
422 default 0xefffc00000000000 if (ARM64_V <<
423 default 0xeffffe0000000000 if ARM64_VA <<
424 default 0xefffffc000000000 if ARM64_VA <<
425 default 0xeffffff800000000 if ARM64_VA <<
426 default 0xffffffffffffffff <<
427 <<
428 config UNWIND_TABLES <<
429 bool <<
430 <<
431 source "arch/arm64/Kconfig.platforms" <<
432 <<
433 menu "Kernel Features" <<
434 <<
435 menu "ARM errata workarounds via the alternati <<
436 <<
437 config AMPERE_ERRATUM_AC03_CPU_38 <<
438 bool "AmpereOne: AC03_CPU_38: Certain <<
439 default y <<
440 help <<
441 This option adds an alternative code <<
442 errata AC03_CPU_38 and AC04_CPU_10 o <<
443 <<
444 The affected design reports FEAT_HAF <<
445 ID_AA64MMFR1_EL1.HAFDBS, but (V)TCR_ <<
446 as required by the architecture. The <<
447 implementation suffers from an addit <<
448 A/D updates can occur after a PTE ha <<
449 <<
450 The workaround forces KVM to explici <<
451 which avoids enabling unadvertised h <<
452 at stage-2. <<
453 1165
454 If unsure, say Y. !! 1166 config GPIO_TXX9
>> 1167 select GPIOLIB
>> 1168 bool
455 1169
456 config ARM64_WORKAROUND_CLEAN_CACHE !! 1170 config FW_CFE
457 bool 1171 bool
458 1172
459 config ARM64_ERRATUM_826319 !! 1173 config ARCH_SUPPORTS_UPROBES
460 bool "Cortex-A53: 826319: System might !! 1174 bool
461 default y <<
462 select ARM64_WORKAROUND_CLEAN_CACHE <<
463 help <<
464 This option adds an alternative code <<
465 erratum 826319 on Cortex-A53 parts u <<
466 AXI master interface and an L2 cache <<
467 1175
468 If a Cortex-A53 uses an AMBA AXI4 AC !! 1176 config DMA_MAYBE_COHERENT
469 and is unable to accept a certain wr !! 1177 select ARCH_HAS_DMA_COHERENCE_H
470 not progress on read data presented !! 1178 select DMA_NONCOHERENT
471 system can deadlock. !! 1179 bool
472 1180
473 The workaround promotes data cache c !! 1181 config DMA_PERDEV_COHERENT
474 data cache clean-and-invalidate. !! 1182 bool
475 Please note that this does not neces !! 1183 select ARCH_HAS_SETUP_DMA_OPS
476 as it depends on the alternative fra !! 1184 select DMA_NONCOHERENT
477 the kernel if an affected CPU is det <<
478 1185
479 If unsure, say Y. !! 1186 config DMA_NONCOHERENT
>> 1187 bool
>> 1188 #
>> 1189 # MIPS allows mixing "slightly different" Cacheability and Coherency
>> 1190 # Attribute bits. It is believed that the uncached access through
>> 1191 # KSEG1 and the implementation specific "uncached accelerated" used
>> 1192 # by pgprot_writcombine can be mixed, and the latter sometimes provides
>> 1193 # significant advantages.
>> 1194 #
>> 1195 select ARCH_HAS_DMA_WRITE_COMBINE
>> 1196 select ARCH_HAS_DMA_PREP_COHERENT
>> 1197 select ARCH_HAS_SYNC_DMA_FOR_DEVICE
>> 1198 select ARCH_HAS_DMA_SET_UNCACHED
>> 1199 select DMA_NONCOHERENT_MMAP
>> 1200 select DMA_NONCOHERENT_CACHE_SYNC
>> 1201 select NEED_DMA_MAP_STATE
480 1202
481 config ARM64_ERRATUM_827319 !! 1203 config SYS_HAS_EARLY_PRINTK
482 bool "Cortex-A53: 827319: Data cache c !! 1204 bool
483 default y <<
484 select ARM64_WORKAROUND_CLEAN_CACHE <<
485 help <<
486 This option adds an alternative code <<
487 erratum 827319 on Cortex-A53 parts u <<
488 master interface and an L2 cache. <<
489 <<
490 Under certain conditions this erratu <<
491 to occur at the same time as another <<
492 on the AMBA 5 CHI interface, which c <<
493 interconnect reorders the two transa <<
494 <<
495 The workaround promotes data cache c <<
496 data cache clean-and-invalidate. <<
497 Please note that this does not neces <<
498 as it depends on the alternative fra <<
499 the kernel if an affected CPU is det <<
500 1205
501 If unsure, say Y. !! 1206 config SYS_SUPPORTS_HOTPLUG_CPU
>> 1207 bool
502 1208
503 config ARM64_ERRATUM_824069 !! 1209 config MIPS_BONITO64
504 bool "Cortex-A53: 824069: Cache line m !! 1210 bool
505 default y <<
506 select ARM64_WORKAROUND_CLEAN_CACHE <<
507 help <<
508 This option adds an alternative code <<
509 erratum 824069 on Cortex-A53 parts u <<
510 to a coherent interconnect. <<
511 <<
512 If a Cortex-A53 processor is executi <<
513 write instruction at the same time a <<
514 cluster is executing a cache mainten <<
515 address, then this erratum might cau <<
516 incorrectly marked as dirty. <<
517 <<
518 The workaround promotes data cache c <<
519 data cache clean-and-invalidate. <<
520 Please note that this option does no <<
521 workaround, as it depends on the alt <<
522 only patch the kernel if an affected <<
523 1211
524 If unsure, say Y. !! 1212 config MIPS_MSC
>> 1213 bool
525 1214
526 config ARM64_ERRATUM_819472 !! 1215 config MIPS_NILE4
527 bool "Cortex-A53: 819472: Store exclus !! 1216 bool
528 default y <<
529 select ARM64_WORKAROUND_CLEAN_CACHE <<
530 help <<
531 This option adds an alternative code <<
532 erratum 819472 on Cortex-A53 parts u <<
533 present when it is connected to a co <<
534 <<
535 If the processor is executing a load <<
536 the same time as a processor in anot <<
537 maintenance operation to the same ad <<
538 cause data corruption. <<
539 <<
540 The workaround promotes data cache c <<
541 data cache clean-and-invalidate. <<
542 Please note that this does not neces <<
543 as it depends on the alternative fra <<
544 the kernel if an affected CPU is det <<
545 1217
546 If unsure, say Y. !! 1218 config SYNC_R4K
>> 1219 bool
547 1220
548 config ARM64_ERRATUM_832075 !! 1221 config MIPS_MACHINE
549 bool "Cortex-A57: 832075: possible dea !! 1222 def_bool n
550 default y <<
551 help <<
552 This option adds an alternative code <<
553 erratum 832075 on Cortex-A57 parts u <<
554 1223
555 Affected Cortex-A57 parts might dead !! 1224 config NO_IOPORT_MAP
556 instructions to Write-Back memory ar !! 1225 def_bool n
557 1226
558 The workaround is to promote device !! 1227 config GENERIC_CSUM
559 semantics. !! 1228 def_bool CPU_NO_LOAD_STORE_LR
560 Please note that this does not neces <<
561 as it depends on the alternative fra <<
562 the kernel if an affected CPU is det <<
563 1229
564 If unsure, say Y. !! 1230 config GENERIC_ISA_DMA
>> 1231 bool
>> 1232 select ZONE_DMA if GENERIC_ISA_DMA_SUPPORT_BROKEN=n
>> 1233 select ISA_DMA_API
565 1234
566 config ARM64_ERRATUM_834220 !! 1235 config GENERIC_ISA_DMA_SUPPORT_BROKEN
567 bool "Cortex-A57: 834220: Stage 2 tran !! 1236 bool
568 depends on KVM !! 1237 select GENERIC_ISA_DMA
569 help <<
570 This option adds an alternative code <<
571 erratum 834220 on Cortex-A57 parts u <<
572 <<
573 Affected Cortex-A57 parts might repo <<
574 fault as the result of a Stage 1 fau <<
575 page boundary when there is a permis <<
576 alignment fault at Stage 1 and a tra <<
577 <<
578 The workaround is to verify that the <<
579 doesn't generate a fault before hand <<
580 Please note that this does not neces <<
581 as it depends on the alternative fra <<
582 the kernel if an affected CPU is det <<
583 1238
584 If unsure, say N. !! 1239 config HAVE_PLAT_DELAY
>> 1240 bool
585 1241
586 config ARM64_ERRATUM_1742098 !! 1242 config HAVE_PLAT_FW_INIT_CMDLINE
587 bool "Cortex-A57/A72: 1742098: ELR rec !! 1243 bool
588 depends on COMPAT <<
589 default y <<
590 help <<
591 This option removes the AES hwcap fo <<
592 workaround erratum 1742098 on Cortex <<
593 <<
594 Affected parts may corrupt the AES s <<
595 taken between a pair of AES instruct <<
596 are only present if the cryptography <<
597 All software should have a fallback <<
598 that don't implement the cryptograph <<
599 1244
600 If unsure, say Y. !! 1245 config HAVE_PLAT_MEMCPY
>> 1246 bool
601 1247
602 config ARM64_ERRATUM_845719 !! 1248 config ISA_DMA_API
603 bool "Cortex-A53: 845719: a load might !! 1249 bool
604 depends on COMPAT <<
605 default y <<
606 help <<
607 This option adds an alternative code <<
608 erratum 845719 on Cortex-A53 parts u <<
609 <<
610 When running a compat (AArch32) user <<
611 part, a load at EL0 from a virtual a <<
612 bits of the virtual address used by <<
613 might return incorrect data. <<
614 <<
615 The workaround is to write the conte <<
616 return to a 32-bit task. <<
617 Please note that this does not neces <<
618 as it depends on the alternative fra <<
619 the kernel if an affected CPU is det <<
620 1250
621 If unsure, say Y. !! 1251 config HOLES_IN_ZONE
>> 1252 bool
622 1253
623 config ARM64_ERRATUM_843419 !! 1254 config SYS_SUPPORTS_RELOCATABLE
624 bool "Cortex-A53: 843419: A load or st !! 1255 bool
625 default y <<
626 help 1256 help
627 This option links the kernel with '- !! 1257 Selected if the platform supports relocating the kernel.
628 enables PLT support to replace certa !! 1258 The platform must provide plat_get_fdt() if it selects CONFIG_USE_OF
629 cause subsequent memory accesses to !! 1259 to allow access to command line and entropy sources.
630 Cortex-A53 parts up to r0p4. <<
631 1260
632 If unsure, say Y. !! 1261 config MIPS_CBPF_JIT
633 !! 1262 def_bool y
634 config ARM64_LD_HAS_FIX_ERRATUM_843419 !! 1263 depends on BPF_JIT && HAVE_CBPF_JIT
635 def_bool $(ld-option,--fix-cortex-a53- <<
636 <<
637 config ARM64_ERRATUM_1024718 <<
638 bool "Cortex-A55: 1024718: Update of D <<
639 default y <<
640 help <<
641 This option adds a workaround for AR <<
642 1264
643 Affected Cortex-A55 cores (all revis !! 1265 config MIPS_EBPF_JIT
644 update of the hardware dirty bit whe !! 1266 def_bool y
645 without a break-before-make. The wor !! 1267 depends on BPF_JIT && HAVE_EBPF_JIT
646 of hardware DBM locally on the affec <<
647 this erratum will continue to use th <<
648 1268
649 If unsure, say Y. <<
650 1269
651 config ARM64_ERRATUM_1418040 !! 1270 #
652 bool "Cortex-A76/Neoverse-N1: MRC read !! 1271 # Endianness selection. Sufficiently obscure so many users don't know what to
653 default y !! 1272 # answer,so we try hard to limit the available choices. Also the use of a
654 depends on COMPAT !! 1273 # choice statement should be more obvious to the user.
>> 1274 #
>> 1275 choice
>> 1276 prompt "Endianness selection"
655 help 1277 help
656 This option adds a workaround for AR !! 1278 Some MIPS machines can be configured for either little or big endian
657 errata 1188873 and 1418040. !! 1279 byte order. These modes require different kernels and a different
>> 1280 Linux distribution. In general there is one preferred byteorder for a
>> 1281 particular system but some systems are just as commonly used in the
>> 1282 one or the other endianness.
658 1283
659 Affected Cortex-A76/Neoverse-N1 core !! 1284 config CPU_BIG_ENDIAN
660 cause register corruption when acces !! 1285 bool "Big endian"
661 from AArch32 userspace. !! 1286 depends on SYS_SUPPORTS_BIG_ENDIAN
662 1287
663 If unsure, say Y. !! 1288 config CPU_LITTLE_ENDIAN
>> 1289 bool "Little endian"
>> 1290 depends on SYS_SUPPORTS_LITTLE_ENDIAN
>> 1291
>> 1292 endchoice
664 1293
665 config ARM64_WORKAROUND_SPECULATIVE_AT !! 1294 config EXPORT_UASM
666 bool 1295 bool
667 1296
668 config ARM64_ERRATUM_1165522 !! 1297 config SYS_SUPPORTS_APM_EMULATION
669 bool "Cortex-A76: 1165522: Speculative !! 1298 bool
670 default y <<
671 select ARM64_WORKAROUND_SPECULATIVE_AT <<
672 help <<
673 This option adds a workaround for AR <<
674 1299
675 Affected Cortex-A76 cores (r0p0, r1p !! 1300 config SYS_SUPPORTS_BIG_ENDIAN
676 corrupted TLBs by speculating an AT !! 1301 bool
677 context switch. <<
678 1302
679 If unsure, say Y. !! 1303 config SYS_SUPPORTS_LITTLE_ENDIAN
>> 1304 bool
680 1305
681 config ARM64_ERRATUM_1319367 !! 1306 config SYS_SUPPORTS_HUGETLBFS
682 bool "Cortex-A57/A72: 1319537: Specula !! 1307 bool
>> 1308 depends on CPU_SUPPORTS_HUGEPAGES
683 default y 1309 default y
684 select ARM64_WORKAROUND_SPECULATIVE_AT <<
685 help <<
686 This option adds work arounds for AR <<
687 and A72 erratum 1319367 <<
688 1310
689 Cortex-A57 and A72 cores could end-u !! 1311 config MIPS_HUGE_TLB_SUPPORT
690 speculating an AT instruction during !! 1312 def_bool HUGETLB_PAGE || TRANSPARENT_HUGEPAGE
691 1313
692 If unsure, say Y. !! 1314 config IRQ_CPU_RM7K
>> 1315 bool
693 1316
694 config ARM64_ERRATUM_1530923 !! 1317 config IRQ_MSP_SLP
695 bool "Cortex-A55: 1530923: Speculative !! 1318 bool
696 default y <<
697 select ARM64_WORKAROUND_SPECULATIVE_AT <<
698 help <<
699 This option adds a workaround for AR <<
700 1319
701 Affected Cortex-A55 cores (r0p0, r0p !! 1320 config IRQ_MSP_CIC
702 corrupted TLBs by speculating an AT !! 1321 bool
703 context switch. <<
704 1322
705 If unsure, say Y. !! 1323 config IRQ_TXX9
>> 1324 bool
706 1325
707 config ARM64_WORKAROUND_REPEAT_TLBI !! 1326 config IRQ_GT641XX
708 bool 1327 bool
709 1328
710 config ARM64_ERRATUM_2441007 !! 1329 config PCI_GT64XXX_PCI0
711 bool "Cortex-A55: Completion of affect !! 1330 bool
712 select ARM64_WORKAROUND_REPEAT_TLBI <<
713 help <<
714 This option adds a workaround for AR <<
715 1331
716 Under very rare circumstances, affec !! 1332 config PCI_XTALK_BRIDGE
717 may not handle a race between a brea !! 1333 bool
718 CPU, and another CPU accessing the s <<
719 store to a page that has been unmapp <<
720 1334
721 Work around this by adding the affec !! 1335 config NO_EXCEPT_FILL
722 TLB sequences to be done twice. !! 1336 bool
723 1337
724 If unsure, say N. !! 1338 config SOC_EMMA2RH
>> 1339 bool
>> 1340 select CEVT_R4K
>> 1341 select CSRC_R4K
>> 1342 select DMA_NONCOHERENT
>> 1343 select IRQ_MIPS_CPU
>> 1344 select SWAP_IO_SPACE
>> 1345 select SYS_HAS_CPU_R5500
>> 1346 select SYS_SUPPORTS_32BIT_KERNEL
>> 1347 select SYS_SUPPORTS_64BIT_KERNEL
>> 1348 select SYS_SUPPORTS_BIG_ENDIAN
725 1349
726 config ARM64_ERRATUM_1286807 !! 1350 config SOC_PNX833X
727 bool "Cortex-A76: Modification of the !! 1351 bool
728 select ARM64_WORKAROUND_REPEAT_TLBI !! 1352 select CEVT_R4K
729 help !! 1353 select CSRC_R4K
730 This option adds a workaround for AR !! 1354 select IRQ_MIPS_CPU
731 !! 1355 select DMA_NONCOHERENT
732 On the affected Cortex-A76 cores (r0 !! 1356 select SYS_HAS_CPU_MIPS32_R2
733 address for a cacheable mapping of a !! 1357 select SYS_SUPPORTS_32BIT_KERNEL
734 accessed by a core while another cor !! 1358 select SYS_SUPPORTS_LITTLE_ENDIAN
735 address to a new physical page using !! 1359 select SYS_SUPPORTS_BIG_ENDIAN
736 break-before-make sequence, then und !! 1360 select SYS_SUPPORTS_MIPS16
737 TLBI+DSB completes before a read usi !! 1361 select CPU_MIPSR2_IRQ_VI
738 invalidated has been observed by oth <<
739 workaround repeats the TLBI+DSB oper <<
740 1362
741 If unsure, say N. !! 1363 config SOC_PNX8335
>> 1364 bool
>> 1365 select SOC_PNX833X
742 1366
743 config ARM64_ERRATUM_1463225 !! 1367 config MIPS_SPRAM
744 bool "Cortex-A76: Software Step might !! 1368 bool
745 default y <<
746 help <<
747 This option adds a workaround for Ar <<
748 1369
749 On the affected Cortex-A76 cores (r0 !! 1370 config SWAP_IO_SPACE
750 of a system call instruction (SVC) c !! 1371 bool
751 subsequent interrupts when software <<
752 exception handler of the system call <<
753 is enabled or VHE is in use. <<
754 1372
755 Work around the erratum by triggerin !! 1373 config SGI_HAS_INDYDOG
756 when handling a system call from a t !! 1374 bool
757 in a VHE configuration of the kernel <<
758 1375
759 If unsure, say Y. !! 1376 config SGI_HAS_HAL2
>> 1377 bool
760 1378
761 config ARM64_ERRATUM_1542419 !! 1379 config SGI_HAS_SEEQ
762 bool "Neoverse-N1: workaround mis-orde !! 1380 bool
763 help <<
764 This option adds a workaround for AR <<
765 1542419. <<
766 1381
767 Affected Neoverse-N1 cores could exe !! 1382 config SGI_HAS_WD93
768 modified by another CPU. The workaro !! 1383 bool
769 counterpart. <<
770 1384
771 Workaround the issue by hiding the D !! 1385 config SGI_HAS_ZILOG
772 forces user-space to perform cache m !! 1386 bool
773 1387
774 If unsure, say N. !! 1388 config SGI_HAS_I8042
>> 1389 bool
775 1390
776 config ARM64_ERRATUM_1508412 !! 1391 config DEFAULT_SGI_PARTITION
777 bool "Cortex-A77: 1508412: workaround !! 1392 bool
778 default y <<
779 help <<
780 This option adds a workaround for Ar <<
781 1393
782 Affected Cortex-A77 cores (r0p0, r1p !! 1394 config FW_ARC32
783 of a store-exclusive or read of PAR_ !! 1395 bool
784 non-cacheable memory attributes. The <<
785 counterpart. <<
786 1396
787 KVM guests must also have the workar !! 1397 config FW_SNIPROM
788 deadlock the system. !! 1398 bool
789 1399
790 Work around the issue by inserting D !! 1400 config BOOT_ELF32
791 register reads and warning KVM users !! 1401 bool
792 to prevent a speculative PAR_EL1 rea <<
793 1402
794 If unsure, say Y. !! 1403 config MIPS_L1_CACHE_SHIFT_4
>> 1404 bool
795 1405
796 config ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MO !! 1406 config MIPS_L1_CACHE_SHIFT_5
797 bool 1407 bool
798 1408
799 config ARM64_ERRATUM_2051678 !! 1409 config MIPS_L1_CACHE_SHIFT_6
800 bool "Cortex-A510: 2051678: disable Ha !! 1410 bool
801 default y <<
802 help <<
803 This options adds the workaround for <<
804 Affected Cortex-A510 might not respe <<
805 hardware update of the page table's <<
806 is to not enable the feature on affe <<
807 1411
808 If unsure, say Y. !! 1412 config MIPS_L1_CACHE_SHIFT_7
>> 1413 bool
809 1414
810 config ARM64_ERRATUM_2077057 !! 1415 config MIPS_L1_CACHE_SHIFT
811 bool "Cortex-A510: 2077057: workaround !! 1416 int
812 default y !! 1417 default "7" if MIPS_L1_CACHE_SHIFT_7
813 help !! 1418 default "6" if MIPS_L1_CACHE_SHIFT_6
814 This option adds the workaround for !! 1419 default "5" if MIPS_L1_CACHE_SHIFT_5
815 Affected Cortex-A510 may corrupt SPS !! 1420 default "4" if MIPS_L1_CACHE_SHIFT_4
816 expected, but a Pointer Authenticati !! 1421 default "5"
817 erratum causes SPSR_EL1 to be copied <<
818 EL1 to cause a return to EL2 with a <<
819 1422
820 This can only happen when EL2 is ste !! 1423 config HAVE_STD_PC_SERIAL_PORT
>> 1424 bool
821 1425
822 When these conditions occur, the SPS !! 1426 config ARC_CMDLINE_ONLY
823 previous guest entry, and can be res !! 1427 bool
824 1428
825 If unsure, say Y. !! 1429 config ARC_CONSOLE
>> 1430 bool "ARC console support"
>> 1431 depends on SGI_IP22 || SGI_IP28 || (SNI_RM && CPU_LITTLE_ENDIAN)
826 1432
827 config ARM64_ERRATUM_2658417 !! 1433 config ARC_MEMORY
828 bool "Cortex-A510: 2658417: remove BF1 !! 1434 bool
829 default y <<
830 help <<
831 This option adds the workaround for <<
832 Affected Cortex-A510 (r0p0 to r1p1) <<
833 BFMMLA or VMMLA instructions in rare <<
834 A510 CPUs are using shared neon hard <<
835 discoverable by the kernel, hide the <<
836 user-space should not be using these <<
837 1435
838 If unsure, say Y. !! 1436 config ARC_PROMLIB
>> 1437 bool
839 1438
840 config ARM64_ERRATUM_2119858 !! 1439 config FW_ARC64
841 bool "Cortex-A710/X2: 2119858: workaro !! 1440 bool
842 default y <<
843 depends on CORESIGHT_TRBE <<
844 select ARM64_WORKAROUND_TRBE_OVERWRITE <<
845 help <<
846 This option adds the workaround for <<
847 1441
848 Affected Cortex-A710/X2 cores could !! 1442 config BOOT_ELF64
849 data at the base of the buffer (poin !! 1443 bool
850 the event of a WRAP event. <<
851 1444
852 Work around the issue by always maki !! 1445 menu "CPU selection"
853 256 bytes before enabling the buffer <<
854 the buffer with ETM ignore packets u <<
855 1446
856 If unsure, say Y. !! 1447 choice
>> 1448 prompt "CPU type"
>> 1449 default CPU_R4X00
857 1450
858 config ARM64_ERRATUM_2139208 !! 1451 config CPU_LOONGSON64
859 bool "Neoverse-N2: 2139208: workaround !! 1452 bool "Loongson 64-bit CPU"
860 default y !! 1453 depends on SYS_HAS_CPU_LOONGSON64
861 depends on CORESIGHT_TRBE !! 1454 select ARCH_HAS_PHYS_TO_DMA
862 select ARM64_WORKAROUND_TRBE_OVERWRITE !! 1455 select CPU_MIPSR2
>> 1456 select CPU_HAS_PREFETCH
>> 1457 select CPU_SUPPORTS_64BIT_KERNEL
>> 1458 select CPU_SUPPORTS_HIGHMEM
>> 1459 select CPU_SUPPORTS_HUGEPAGES
>> 1460 select CPU_SUPPORTS_MSA
>> 1461 select CPU_DIEI_BROKEN if !LOONGSON3_ENHANCEMENT
>> 1462 select CPU_MIPSR2_IRQ_VI
>> 1463 select WEAK_ORDERING
>> 1464 select WEAK_REORDERING_BEYOND_LLSC
>> 1465 select MIPS_ASID_BITS_VARIABLE
>> 1466 select MIPS_PGD_C0_CONTEXT
>> 1467 select MIPS_L1_CACHE_SHIFT_6
>> 1468 select GPIOLIB
>> 1469 select SWIOTLB
863 help 1470 help
864 This option adds the workaround for !! 1471 The Loongson GSx64(GS264/GS464/GS464E/GS464V) series of processor
>> 1472 cores implements the MIPS64R2 instruction set with many extensions,
>> 1473 including most 64-bit Loongson-2 (2H, 2K) and Loongson-3 (3A1000,
>> 1474 3B1000, 3B1500, 3A2000, 3A3000 and 3A4000) processors. However, old
>> 1475 Loongson-2E/2F is not covered here and will be removed in future.
865 1476
866 Affected Neoverse-N2 cores could ove !! 1477 config LOONGSON3_ENHANCEMENT
867 data at the base of the buffer (poin !! 1478 bool "New Loongson-3 CPU Enhancements"
868 the event of a WRAP event. !! 1479 default n
>> 1480 depends on CPU_LOONGSON64
>> 1481 help
>> 1482 New Loongson-3 cores (since Loongson-3A R2, as opposed to Loongson-3A
>> 1483 R1, Loongson-3B R1 and Loongson-3B R2) has many enhancements, such as
>> 1484 FTLB, L1-VCache, EI/DI/Wait/Prefetch instruction, DSP/DSPr2 ASE, User
>> 1485 Local register, Read-Inhibit/Execute-Inhibit, SFB (Store Fill Buffer),
>> 1486 Fast TLB refill support, etc.
>> 1487
>> 1488 This option enable those enhancements which are not probed at run
>> 1489 time. If you want a generic kernel to run on all Loongson 3 machines,
>> 1490 please say 'N' here. If you want a high-performance kernel to run on
>> 1491 new Loongson-3 machines only, please say 'Y' here.
>> 1492
>> 1493 config CPU_LOONGSON3_WORKAROUNDS
>> 1494 bool "Old Loongson-3 LLSC Workarounds"
>> 1495 default y if SMP
>> 1496 depends on CPU_LOONGSON64
>> 1497 help
>> 1498 Loongson-3 processors have the llsc issues which require workarounds.
>> 1499 Without workarounds the system may hang unexpectedly.
>> 1500
>> 1501 Newer Loongson-3 will fix these issues and no workarounds are needed.
>> 1502 The workarounds have no significant side effect on them but may
>> 1503 decrease the performance of the system so this option should be
>> 1504 disabled unless the kernel is intended to be run on old systems.
>> 1505
>> 1506 If unsure, please say Y.
>> 1507
>> 1508 config CPU_LOONGSON2E
>> 1509 bool "Loongson 2E"
>> 1510 depends on SYS_HAS_CPU_LOONGSON2E
>> 1511 select CPU_LOONGSON2EF
>> 1512 help
>> 1513 The Loongson 2E processor implements the MIPS III instruction set
>> 1514 with many extensions.
>> 1515
>> 1516 It has an internal FPGA northbridge, which is compatible to
>> 1517 bonito64.
>> 1518
>> 1519 config CPU_LOONGSON2F
>> 1520 bool "Loongson 2F"
>> 1521 depends on SYS_HAS_CPU_LOONGSON2F
>> 1522 select CPU_LOONGSON2EF
>> 1523 select GPIOLIB
>> 1524 help
>> 1525 The Loongson 2F processor implements the MIPS III instruction set
>> 1526 with many extensions.
>> 1527
>> 1528 Loongson2F have built-in DDR2 and PCIX controller. The PCIX controller
>> 1529 have a similar programming interface with FPGA northbridge used in
>> 1530 Loongson2E.
>> 1531
>> 1532 config CPU_LOONGSON1B
>> 1533 bool "Loongson 1B"
>> 1534 depends on SYS_HAS_CPU_LOONGSON1B
>> 1535 select CPU_LOONGSON32
>> 1536 select LEDS_GPIO_REGISTER
>> 1537 help
>> 1538 The Loongson 1B is a 32-bit SoC, which implements the MIPS32
>> 1539 Release 1 instruction set and part of the MIPS32 Release 2
>> 1540 instruction set.
>> 1541
>> 1542 config CPU_LOONGSON1C
>> 1543 bool "Loongson 1C"
>> 1544 depends on SYS_HAS_CPU_LOONGSON1C
>> 1545 select CPU_LOONGSON32
>> 1546 select LEDS_GPIO_REGISTER
>> 1547 help
>> 1548 The Loongson 1C is a 32-bit SoC, which implements the MIPS32
>> 1549 Release 1 instruction set and part of the MIPS32 Release 2
>> 1550 instruction set.
>> 1551
>> 1552 config CPU_MIPS32_R1
>> 1553 bool "MIPS32 Release 1"
>> 1554 depends on SYS_HAS_CPU_MIPS32_R1
>> 1555 select CPU_HAS_PREFETCH
>> 1556 select CPU_SUPPORTS_32BIT_KERNEL
>> 1557 select CPU_SUPPORTS_HIGHMEM
>> 1558 help
>> 1559 Choose this option to build a kernel for release 1 or later of the
>> 1560 MIPS32 architecture. Most modern embedded systems with a 32-bit
>> 1561 MIPS processor are based on a MIPS32 processor. If you know the
>> 1562 specific type of processor in your system, choose those that one
>> 1563 otherwise CPU_MIPS32_R1 is a safe bet for any MIPS32 system.
>> 1564 Release 2 of the MIPS32 architecture is available since several
>> 1565 years so chances are you even have a MIPS32 Release 2 processor
>> 1566 in which case you should choose CPU_MIPS32_R2 instead for better
>> 1567 performance.
>> 1568
>> 1569 config CPU_MIPS32_R2
>> 1570 bool "MIPS32 Release 2"
>> 1571 depends on SYS_HAS_CPU_MIPS32_R2
>> 1572 select CPU_HAS_PREFETCH
>> 1573 select CPU_SUPPORTS_32BIT_KERNEL
>> 1574 select CPU_SUPPORTS_HIGHMEM
>> 1575 select CPU_SUPPORTS_MSA
>> 1576 select HAVE_KVM
>> 1577 help
>> 1578 Choose this option to build a kernel for release 2 or later of the
>> 1579 MIPS32 architecture. Most modern embedded systems with a 32-bit
>> 1580 MIPS processor are based on a MIPS32 processor. If you know the
>> 1581 specific type of processor in your system, choose those that one
>> 1582 otherwise CPU_MIPS32_R1 is a safe bet for any MIPS32 system.
>> 1583
>> 1584 config CPU_MIPS32_R6
>> 1585 bool "MIPS32 Release 6"
>> 1586 depends on SYS_HAS_CPU_MIPS32_R6
>> 1587 select CPU_HAS_PREFETCH
>> 1588 select CPU_NO_LOAD_STORE_LR
>> 1589 select CPU_SUPPORTS_32BIT_KERNEL
>> 1590 select CPU_SUPPORTS_HIGHMEM
>> 1591 select CPU_SUPPORTS_MSA
>> 1592 select HAVE_KVM
>> 1593 select MIPS_O32_FP64_SUPPORT
>> 1594 help
>> 1595 Choose this option to build a kernel for release 6 or later of the
>> 1596 MIPS32 architecture. New MIPS processors, starting with the Warrior
>> 1597 family, are based on a MIPS32r6 processor. If you own an older
>> 1598 processor, you probably need to select MIPS32r1 or MIPS32r2 instead.
>> 1599
>> 1600 config CPU_MIPS64_R1
>> 1601 bool "MIPS64 Release 1"
>> 1602 depends on SYS_HAS_CPU_MIPS64_R1
>> 1603 select CPU_HAS_PREFETCH
>> 1604 select CPU_SUPPORTS_32BIT_KERNEL
>> 1605 select CPU_SUPPORTS_64BIT_KERNEL
>> 1606 select CPU_SUPPORTS_HIGHMEM
>> 1607 select CPU_SUPPORTS_HUGEPAGES
>> 1608 help
>> 1609 Choose this option to build a kernel for release 1 or later of the
>> 1610 MIPS64 architecture. Many modern embedded systems with a 64-bit
>> 1611 MIPS processor are based on a MIPS64 processor. If you know the
>> 1612 specific type of processor in your system, choose those that one
>> 1613 otherwise CPU_MIPS64_R1 is a safe bet for any MIPS64 system.
>> 1614 Release 2 of the MIPS64 architecture is available since several
>> 1615 years so chances are you even have a MIPS64 Release 2 processor
>> 1616 in which case you should choose CPU_MIPS64_R2 instead for better
>> 1617 performance.
>> 1618
>> 1619 config CPU_MIPS64_R2
>> 1620 bool "MIPS64 Release 2"
>> 1621 depends on SYS_HAS_CPU_MIPS64_R2
>> 1622 select CPU_HAS_PREFETCH
>> 1623 select CPU_SUPPORTS_32BIT_KERNEL
>> 1624 select CPU_SUPPORTS_64BIT_KERNEL
>> 1625 select CPU_SUPPORTS_HIGHMEM
>> 1626 select CPU_SUPPORTS_HUGEPAGES
>> 1627 select CPU_SUPPORTS_MSA
>> 1628 select HAVE_KVM
>> 1629 help
>> 1630 Choose this option to build a kernel for release 2 or later of the
>> 1631 MIPS64 architecture. Many modern embedded systems with a 64-bit
>> 1632 MIPS processor are based on a MIPS64 processor. If you know the
>> 1633 specific type of processor in your system, choose those that one
>> 1634 otherwise CPU_MIPS64_R1 is a safe bet for any MIPS64 system.
>> 1635
>> 1636 config CPU_MIPS64_R6
>> 1637 bool "MIPS64 Release 6"
>> 1638 depends on SYS_HAS_CPU_MIPS64_R6
>> 1639 select CPU_HAS_PREFETCH
>> 1640 select CPU_NO_LOAD_STORE_LR
>> 1641 select CPU_SUPPORTS_32BIT_KERNEL
>> 1642 select CPU_SUPPORTS_64BIT_KERNEL
>> 1643 select CPU_SUPPORTS_HIGHMEM
>> 1644 select CPU_SUPPORTS_HUGEPAGES
>> 1645 select CPU_SUPPORTS_MSA
>> 1646 select MIPS_O32_FP64_SUPPORT if 32BIT || MIPS32_O32
>> 1647 select HAVE_KVM
>> 1648 help
>> 1649 Choose this option to build a kernel for release 6 or later of the
>> 1650 MIPS64 architecture. New MIPS processors, starting with the Warrior
>> 1651 family, are based on a MIPS64r6 processor. If you own an older
>> 1652 processor, you probably need to select MIPS64r1 or MIPS64r2 instead.
>> 1653
>> 1654 config CPU_R3000
>> 1655 bool "R3000"
>> 1656 depends on SYS_HAS_CPU_R3000
>> 1657 select CPU_HAS_WB
>> 1658 select CPU_R3K_TLB
>> 1659 select CPU_SUPPORTS_32BIT_KERNEL
>> 1660 select CPU_SUPPORTS_HIGHMEM
>> 1661 help
>> 1662 Please make sure to pick the right CPU type. Linux/MIPS is not
>> 1663 designed to be generic, i.e. Kernels compiled for R3000 CPUs will
>> 1664 *not* work on R4000 machines and vice versa. However, since most
>> 1665 of the supported machines have an R4000 (or similar) CPU, R4x00
>> 1666 might be a safe bet. If the resulting kernel does not work,
>> 1667 try to recompile with R3000.
>> 1668
>> 1669 config CPU_TX39XX
>> 1670 bool "R39XX"
>> 1671 depends on SYS_HAS_CPU_TX39XX
>> 1672 select CPU_SUPPORTS_32BIT_KERNEL
>> 1673 select CPU_R3K_TLB
>> 1674
>> 1675 config CPU_VR41XX
>> 1676 bool "R41xx"
>> 1677 depends on SYS_HAS_CPU_VR41XX
>> 1678 select CPU_SUPPORTS_32BIT_KERNEL
>> 1679 select CPU_SUPPORTS_64BIT_KERNEL
>> 1680 help
>> 1681 The options selects support for the NEC VR4100 series of processors.
>> 1682 Only choose this option if you have one of these processors as a
>> 1683 kernel built with this option will not run on any other type of
>> 1684 processor or vice versa.
>> 1685
>> 1686 config CPU_R4X00
>> 1687 bool "R4x00"
>> 1688 depends on SYS_HAS_CPU_R4X00
>> 1689 select CPU_SUPPORTS_32BIT_KERNEL
>> 1690 select CPU_SUPPORTS_64BIT_KERNEL
>> 1691 select CPU_SUPPORTS_HUGEPAGES
>> 1692 help
>> 1693 MIPS Technologies R4000-series processors other than 4300, including
>> 1694 the R4000, R4400, R4600, and 4700.
>> 1695
>> 1696 config CPU_TX49XX
>> 1697 bool "R49XX"
>> 1698 depends on SYS_HAS_CPU_TX49XX
>> 1699 select CPU_HAS_PREFETCH
>> 1700 select CPU_SUPPORTS_32BIT_KERNEL
>> 1701 select CPU_SUPPORTS_64BIT_KERNEL
>> 1702 select CPU_SUPPORTS_HUGEPAGES
>> 1703
>> 1704 config CPU_R5000
>> 1705 bool "R5000"
>> 1706 depends on SYS_HAS_CPU_R5000
>> 1707 select CPU_SUPPORTS_32BIT_KERNEL
>> 1708 select CPU_SUPPORTS_64BIT_KERNEL
>> 1709 select CPU_SUPPORTS_HUGEPAGES
>> 1710 help
>> 1711 MIPS Technologies R5000-series processors other than the Nevada.
>> 1712
>> 1713 config CPU_R5500
>> 1714 bool "R5500"
>> 1715 depends on SYS_HAS_CPU_R5500
>> 1716 select CPU_SUPPORTS_32BIT_KERNEL
>> 1717 select CPU_SUPPORTS_64BIT_KERNEL
>> 1718 select CPU_SUPPORTS_HUGEPAGES
>> 1719 help
>> 1720 NEC VR5500 and VR5500A series processors implement 64-bit MIPS IV
>> 1721 instruction set.
>> 1722
>> 1723 config CPU_NEVADA
>> 1724 bool "RM52xx"
>> 1725 depends on SYS_HAS_CPU_NEVADA
>> 1726 select CPU_SUPPORTS_32BIT_KERNEL
>> 1727 select CPU_SUPPORTS_64BIT_KERNEL
>> 1728 select CPU_SUPPORTS_HUGEPAGES
>> 1729 help
>> 1730 QED / PMC-Sierra RM52xx-series ("Nevada") processors.
>> 1731
>> 1732 config CPU_R10000
>> 1733 bool "R10000"
>> 1734 depends on SYS_HAS_CPU_R10000
>> 1735 select CPU_HAS_PREFETCH
>> 1736 select CPU_SUPPORTS_32BIT_KERNEL
>> 1737 select CPU_SUPPORTS_64BIT_KERNEL
>> 1738 select CPU_SUPPORTS_HIGHMEM
>> 1739 select CPU_SUPPORTS_HUGEPAGES
>> 1740 help
>> 1741 MIPS Technologies R10000-series processors.
>> 1742
>> 1743 config CPU_RM7000
>> 1744 bool "RM7000"
>> 1745 depends on SYS_HAS_CPU_RM7000
>> 1746 select CPU_HAS_PREFETCH
>> 1747 select CPU_SUPPORTS_32BIT_KERNEL
>> 1748 select CPU_SUPPORTS_64BIT_KERNEL
>> 1749 select CPU_SUPPORTS_HIGHMEM
>> 1750 select CPU_SUPPORTS_HUGEPAGES
>> 1751
>> 1752 config CPU_SB1
>> 1753 bool "SB1"
>> 1754 depends on SYS_HAS_CPU_SB1
>> 1755 select CPU_SUPPORTS_32BIT_KERNEL
>> 1756 select CPU_SUPPORTS_64BIT_KERNEL
>> 1757 select CPU_SUPPORTS_HIGHMEM
>> 1758 select CPU_SUPPORTS_HUGEPAGES
>> 1759 select WEAK_ORDERING
>> 1760
>> 1761 config CPU_CAVIUM_OCTEON
>> 1762 bool "Cavium Octeon processor"
>> 1763 depends on SYS_HAS_CPU_CAVIUM_OCTEON
>> 1764 select CPU_HAS_PREFETCH
>> 1765 select CPU_SUPPORTS_64BIT_KERNEL
>> 1766 select WEAK_ORDERING
>> 1767 select CPU_SUPPORTS_HIGHMEM
>> 1768 select CPU_SUPPORTS_HUGEPAGES
>> 1769 select USB_EHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 1770 select USB_OHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 1771 select MIPS_L1_CACHE_SHIFT_7
>> 1772 select HAVE_KVM
>> 1773 help
>> 1774 The Cavium Octeon processor is a highly integrated chip containing
>> 1775 many ethernet hardware widgets for networking tasks. The processor
>> 1776 can have up to 16 Mips64v2 cores and 8 integrated gigabit ethernets.
>> 1777 Full details can be found at http://www.caviumnetworks.com.
>> 1778
>> 1779 config CPU_BMIPS
>> 1780 bool "Broadcom BMIPS"
>> 1781 depends on SYS_HAS_CPU_BMIPS
>> 1782 select CPU_MIPS32
>> 1783 select CPU_BMIPS32_3300 if SYS_HAS_CPU_BMIPS32_3300
>> 1784 select CPU_BMIPS4350 if SYS_HAS_CPU_BMIPS4350
>> 1785 select CPU_BMIPS4380 if SYS_HAS_CPU_BMIPS4380
>> 1786 select CPU_BMIPS5000 if SYS_HAS_CPU_BMIPS5000
>> 1787 select CPU_SUPPORTS_32BIT_KERNEL
>> 1788 select DMA_NONCOHERENT
>> 1789 select IRQ_MIPS_CPU
>> 1790 select SWAP_IO_SPACE
>> 1791 select WEAK_ORDERING
>> 1792 select CPU_SUPPORTS_HIGHMEM
>> 1793 select CPU_HAS_PREFETCH
>> 1794 select CPU_SUPPORTS_CPUFREQ
>> 1795 select MIPS_EXTERNAL_TIMER
>> 1796 help
>> 1797 Support for BMIPS32/3300/4350/4380 and BMIPS5000 processors.
>> 1798
>> 1799 config CPU_XLR
>> 1800 bool "Netlogic XLR SoC"
>> 1801 depends on SYS_HAS_CPU_XLR
>> 1802 select CPU_SUPPORTS_32BIT_KERNEL
>> 1803 select CPU_SUPPORTS_64BIT_KERNEL
>> 1804 select CPU_SUPPORTS_HIGHMEM
>> 1805 select CPU_SUPPORTS_HUGEPAGES
>> 1806 select WEAK_ORDERING
>> 1807 select WEAK_REORDERING_BEYOND_LLSC
>> 1808 help
>> 1809 Netlogic Microsystems XLR/XLS processors.
>> 1810
>> 1811 config CPU_XLP
>> 1812 bool "Netlogic XLP SoC"
>> 1813 depends on SYS_HAS_CPU_XLP
>> 1814 select CPU_SUPPORTS_32BIT_KERNEL
>> 1815 select CPU_SUPPORTS_64BIT_KERNEL
>> 1816 select CPU_SUPPORTS_HIGHMEM
>> 1817 select WEAK_ORDERING
>> 1818 select WEAK_REORDERING_BEYOND_LLSC
>> 1819 select CPU_HAS_PREFETCH
>> 1820 select CPU_MIPSR2
>> 1821 select CPU_SUPPORTS_HUGEPAGES
>> 1822 select MIPS_ASID_BITS_VARIABLE
>> 1823 help
>> 1824 Netlogic Microsystems XLP processors.
>> 1825 endchoice
869 1826
870 Work around the issue by always maki !! 1827 config CPU_MIPS32_3_5_FEATURES
871 256 bytes before enabling the buffer !! 1828 bool "MIPS32 Release 3.5 Features"
872 the buffer with ETM ignore packets u !! 1829 depends on SYS_HAS_CPU_MIPS32_R3_5
>> 1830 depends on CPU_MIPS32_R2 || CPU_MIPS32_R6
>> 1831 help
>> 1832 Choose this option to build a kernel for release 2 or later of the
>> 1833 MIPS32 architecture including features from the 3.5 release such as
>> 1834 support for Enhanced Virtual Addressing (EVA).
>> 1835
>> 1836 config CPU_MIPS32_3_5_EVA
>> 1837 bool "Enhanced Virtual Addressing (EVA)"
>> 1838 depends on CPU_MIPS32_3_5_FEATURES
>> 1839 select EVA
>> 1840 default y
>> 1841 help
>> 1842 Choose this option if you want to enable the Enhanced Virtual
>> 1843 Addressing (EVA) on your MIPS32 core (such as proAptiv).
>> 1844 One of its primary benefits is an increase in the maximum size
>> 1845 of lowmem (up to 3GB). If unsure, say 'N' here.
>> 1846
>> 1847 config CPU_MIPS32_R5_FEATURES
>> 1848 bool "MIPS32 Release 5 Features"
>> 1849 depends on SYS_HAS_CPU_MIPS32_R5
>> 1850 depends on CPU_MIPS32_R2
>> 1851 help
>> 1852 Choose this option to build a kernel for release 2 or later of the
>> 1853 MIPS32 architecture including features from release 5 such as
>> 1854 support for Extended Physical Addressing (XPA).
>> 1855
>> 1856 config CPU_MIPS32_R5_XPA
>> 1857 bool "Extended Physical Addressing (XPA)"
>> 1858 depends on CPU_MIPS32_R5_FEATURES
>> 1859 depends on !EVA
>> 1860 depends on !PAGE_SIZE_4KB
>> 1861 depends on SYS_SUPPORTS_HIGHMEM
>> 1862 select XPA
>> 1863 select HIGHMEM
>> 1864 select PHYS_ADDR_T_64BIT
>> 1865 default n
>> 1866 help
>> 1867 Choose this option if you want to enable the Extended Physical
>> 1868 Addressing (XPA) on your MIPS32 core (such as P5600 series). The
>> 1869 benefit is to increase physical addressing equal to or greater
>> 1870 than 40 bits. Note that this has the side effect of turning on
>> 1871 64-bit addressing which in turn makes the PTEs 64-bit in size.
>> 1872 If unsure, say 'N' here.
873 1873
874 If unsure, say Y. !! 1874 if CPU_LOONGSON2F
>> 1875 config CPU_NOP_WORKAROUNDS
>> 1876 bool
875 1877
876 config ARM64_WORKAROUND_TSB_FLUSH_FAILURE !! 1878 config CPU_JUMP_WORKAROUNDS
877 bool 1879 bool
878 1880
879 config ARM64_ERRATUM_2054223 !! 1881 config CPU_LOONGSON2F_WORKAROUNDS
880 bool "Cortex-A710: 2054223: workaround !! 1882 bool "Loongson 2F Workarounds"
881 default y 1883 default y
882 select ARM64_WORKAROUND_TSB_FLUSH_FAIL !! 1884 select CPU_NOP_WORKAROUNDS
>> 1885 select CPU_JUMP_WORKAROUNDS
883 help 1886 help
884 Enable workaround for ARM Cortex-A71 !! 1887 Loongson 2F01 / 2F02 processors have the NOP & JUMP issues which
>> 1888 require workarounds. Without workarounds the system may hang
>> 1889 unexpectedly. For more information please refer to the gas
>> 1890 -mfix-loongson2f-nop and -mfix-loongson2f-jump options.
>> 1891
>> 1892 Loongson 2F03 and later have fixed these issues and no workarounds
>> 1893 are needed. The workarounds have no significant side effect on them
>> 1894 but may decrease the performance of the system so this option should
>> 1895 be disabled unless the kernel is intended to be run on 2F01 or 2F02
>> 1896 systems.
885 1897
886 Affected cores may fail to flush the !! 1898 If unsure, please say Y.
887 the PE is in trace prohibited state. !! 1899 endif # CPU_LOONGSON2F
888 of the trace cached. <<
889 1900
890 Workaround is to issue two TSB conse !! 1901 config SYS_SUPPORTS_ZBOOT
>> 1902 bool
>> 1903 select HAVE_KERNEL_GZIP
>> 1904 select HAVE_KERNEL_BZIP2
>> 1905 select HAVE_KERNEL_LZ4
>> 1906 select HAVE_KERNEL_LZMA
>> 1907 select HAVE_KERNEL_LZO
>> 1908 select HAVE_KERNEL_XZ
891 1909
892 If unsure, say Y. !! 1910 config SYS_SUPPORTS_ZBOOT_UART16550
>> 1911 bool
>> 1912 select SYS_SUPPORTS_ZBOOT
893 1913
894 config ARM64_ERRATUM_2067961 !! 1914 config SYS_SUPPORTS_ZBOOT_UART_PROM
895 bool "Neoverse-N2: 2067961: workaround !! 1915 bool
896 default y !! 1916 select SYS_SUPPORTS_ZBOOT
897 select ARM64_WORKAROUND_TSB_FLUSH_FAIL <<
898 help <<
899 Enable workaround for ARM Neoverse-N <<
900 1917
901 Affected cores may fail to flush the !! 1918 config CPU_LOONGSON2EF
902 the PE is in trace prohibited state. !! 1919 bool
903 of the trace cached. !! 1920 select CPU_SUPPORTS_32BIT_KERNEL
>> 1921 select CPU_SUPPORTS_64BIT_KERNEL
>> 1922 select CPU_SUPPORTS_HIGHMEM
>> 1923 select CPU_SUPPORTS_HUGEPAGES
>> 1924 select ARCH_HAS_PHYS_TO_DMA
904 1925
905 Workaround is to issue two TSB conse !! 1926 config CPU_LOONGSON32
>> 1927 bool
>> 1928 select CPU_MIPS32
>> 1929 select CPU_MIPSR2
>> 1930 select CPU_HAS_PREFETCH
>> 1931 select CPU_SUPPORTS_32BIT_KERNEL
>> 1932 select CPU_SUPPORTS_HIGHMEM
>> 1933 select CPU_SUPPORTS_CPUFREQ
906 1934
907 If unsure, say Y. !! 1935 config CPU_BMIPS32_3300
>> 1936 select SMP_UP if SMP
>> 1937 bool
908 1938
909 config ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANG !! 1939 config CPU_BMIPS4350
910 bool 1940 bool
>> 1941 select SYS_SUPPORTS_SMP
>> 1942 select SYS_SUPPORTS_HOTPLUG_CPU
911 1943
912 config ARM64_ERRATUM_2253138 !! 1944 config CPU_BMIPS4380
913 bool "Neoverse-N2: 2253138: workaround !! 1945 bool
914 depends on CORESIGHT_TRBE !! 1946 select MIPS_L1_CACHE_SHIFT_6
915 default y !! 1947 select SYS_SUPPORTS_SMP
916 select ARM64_WORKAROUND_TRBE_WRITE_OUT !! 1948 select SYS_SUPPORTS_HOTPLUG_CPU
917 help !! 1949 select CPU_HAS_RIXI
918 This option adds the workaround for <<
919 1950
920 Affected Neoverse-N2 cores might wri !! 1951 config CPU_BMIPS5000
921 for TRBE. Under some conditions, the !! 1952 bool
922 virtually addressed page following t !! 1953 select MIPS_CPU_SCACHE
923 (i.e., the TRBLIMITR_EL1.LIMIT), ins !! 1954 select MIPS_L1_CACHE_SHIFT_7
>> 1955 select SYS_SUPPORTS_SMP
>> 1956 select SYS_SUPPORTS_HOTPLUG_CPU
>> 1957 select CPU_HAS_RIXI
924 1958
925 Work around this in the driver by al !! 1959 config SYS_HAS_CPU_LOONGSON64
926 page beyond the TRBLIMITR_EL1.LIMIT, !! 1960 bool
>> 1961 select CPU_SUPPORTS_CPUFREQ
>> 1962 select CPU_HAS_RIXI
927 1963
928 If unsure, say Y. !! 1964 config SYS_HAS_CPU_LOONGSON2E
>> 1965 bool
929 1966
930 config ARM64_ERRATUM_2224489 !! 1967 config SYS_HAS_CPU_LOONGSON2F
931 bool "Cortex-A710/X2: 2224489: workaro !! 1968 bool
932 depends on CORESIGHT_TRBE !! 1969 select CPU_SUPPORTS_CPUFREQ
933 default y !! 1970 select CPU_SUPPORTS_ADDRWINCFG if 64BIT
934 select ARM64_WORKAROUND_TRBE_WRITE_OUT <<
935 help <<
936 This option adds the workaround for <<
937 1971
938 Affected Cortex-A710/X2 cores might !! 1972 config SYS_HAS_CPU_LOONGSON1B
939 for TRBE. Under some conditions, the !! 1973 bool
940 virtually addressed page following t <<
941 (i.e., the TRBLIMITR_EL1.LIMIT), ins <<
942 1974
943 Work around this in the driver by al !! 1975 config SYS_HAS_CPU_LOONGSON1C
944 page beyond the TRBLIMITR_EL1.LIMIT, !! 1976 bool
945 1977
946 If unsure, say Y. !! 1978 config SYS_HAS_CPU_MIPS32_R1
>> 1979 bool
947 1980
948 config ARM64_ERRATUM_2441009 !! 1981 config SYS_HAS_CPU_MIPS32_R2
949 bool "Cortex-A510: Completion of affec !! 1982 bool
950 select ARM64_WORKAROUND_REPEAT_TLBI <<
951 help <<
952 This option adds a workaround for AR <<
953 <<
954 Under very rare circumstances, affec <<
955 may not handle a race between a brea <<
956 CPU, and another CPU accessing the s <<
957 store to a page that has been unmapp <<
958 1983
959 Work around this by adding the affec !! 1984 config SYS_HAS_CPU_MIPS32_R3_5
960 TLB sequences to be done twice. !! 1985 bool
961 1986
962 If unsure, say N. !! 1987 config SYS_HAS_CPU_MIPS32_R5
>> 1988 bool
>> 1989 select ARCH_HAS_SYNC_DMA_FOR_CPU if DMA_NONCOHERENT
963 1990
964 config ARM64_ERRATUM_2064142 !! 1991 config SYS_HAS_CPU_MIPS32_R6
965 bool "Cortex-A510: 2064142: workaround !! 1992 bool
966 depends on CORESIGHT_TRBE !! 1993 select ARCH_HAS_SYNC_DMA_FOR_CPU if DMA_NONCOHERENT
967 default y <<
968 help <<
969 This option adds the workaround for <<
970 1994
971 Affected Cortex-A510 core might fail !! 1995 config SYS_HAS_CPU_MIPS64_R1
972 TRBE has been disabled. Under some c !! 1996 bool
973 writes into TRBE registers TRBLIMITR <<
974 and TRBTRG_EL1 will be ignored and w <<
975 1997
976 Work around this in the driver by ex !! 1998 config SYS_HAS_CPU_MIPS64_R2
977 is stopped and before performing a s !! 1999 bool
978 registers. <<
979 2000
980 If unsure, say Y. !! 2001 config SYS_HAS_CPU_MIPS64_R6
>> 2002 bool
>> 2003 select ARCH_HAS_SYNC_DMA_FOR_CPU if DMA_NONCOHERENT
981 2004
982 config ARM64_ERRATUM_2038923 !! 2005 config SYS_HAS_CPU_R3000
983 bool "Cortex-A510: 2038923: workaround !! 2006 bool
984 depends on CORESIGHT_TRBE <<
985 default y <<
986 help <<
987 This option adds the workaround for <<
988 <<
989 Affected Cortex-A510 core might caus <<
990 prohibited within the CPU. As a resu <<
991 might be corrupted. This happens aft <<
992 TRBLIMITR_EL1.E, followed by just a <<
993 execution changes from a context, in <<
994 isn't, or vice versa. In these menti <<
995 is prohibited is inconsistent betwee <<
996 the trace buffer state might be corr <<
997 <<
998 Work around this in the driver by pr <<
999 trace is prohibited or not based on <<
1000 change to TRBLIMITR_EL1.E with at l <<
1001 two ISB instructions if no ERET is <<
1002 2007
1003 If unsure, say Y. !! 2008 config SYS_HAS_CPU_TX39XX
>> 2009 bool
1004 2010
1005 config ARM64_ERRATUM_1902691 !! 2011 config SYS_HAS_CPU_VR41XX
1006 bool "Cortex-A510: 1902691: workaroun !! 2012 bool
1007 depends on CORESIGHT_TRBE <<
1008 default y <<
1009 help <<
1010 This option adds the workaround for <<
1011 2013
1012 Affected Cortex-A510 core might cau !! 2014 config SYS_HAS_CPU_R4X00
1013 into the memory. Effectively TRBE i !! 2015 bool
1014 trace data. <<
1015 2016
1016 Work around this problem in the dri !! 2017 config SYS_HAS_CPU_TX49XX
1017 affected cpus. The firmware must ha !! 2018 bool
1018 on such implementations. This will <<
1019 do this already. <<
1020 2019
1021 If unsure, say Y. !! 2020 config SYS_HAS_CPU_R5000
>> 2021 bool
1022 2022
1023 config ARM64_ERRATUM_2457168 !! 2023 config SYS_HAS_CPU_R5500
1024 bool "Cortex-A510: 2457168: workaroun !! 2024 bool
1025 depends on ARM64_AMU_EXTN <<
1026 default y <<
1027 help <<
1028 This option adds the workaround for <<
1029 2025
1030 The AMU counter AMEVCNTR01 (constan !! 2026 config SYS_HAS_CPU_NEVADA
1031 as the system counter. On affected !! 2027 bool
1032 incorrectly giving a significantly <<
1033 2028
1034 Work around this problem by returni !! 2029 config SYS_HAS_CPU_R10000
1035 key locations that results in disab !! 2030 bool
1036 is the same to firmware disabling a !! 2031 select ARCH_HAS_SYNC_DMA_FOR_CPU if DMA_NONCOHERENT
1037 2032
1038 If unsure, say Y. !! 2033 config SYS_HAS_CPU_RM7000
>> 2034 bool
1039 2035
1040 config ARM64_ERRATUM_2645198 !! 2036 config SYS_HAS_CPU_SB1
1041 bool "Cortex-A715: 2645198: Workaroun !! 2037 bool
1042 default y <<
1043 help <<
1044 This option adds the workaround for <<
1045 2038
1046 If a Cortex-A715 cpu sees a page ma !! 2039 config SYS_HAS_CPU_CAVIUM_OCTEON
1047 to non-executable, it may corrupt t !! 2040 bool
1048 next instruction abort caused by pe <<
1049 2041
1050 Only user-space does executable to !! 2042 config SYS_HAS_CPU_BMIPS
1051 mprotect() system call. Workaround !! 2043 bool
1052 TLB invalidation, for all changes t <<
1053 2044
1054 If unsure, say Y. !! 2045 config SYS_HAS_CPU_BMIPS32_3300
>> 2046 bool
>> 2047 select SYS_HAS_CPU_BMIPS
1055 2048
1056 config ARM64_WORKAROUND_SPECULATIVE_UNPRIV_LO !! 2049 config SYS_HAS_CPU_BMIPS4350
1057 bool 2050 bool
>> 2051 select SYS_HAS_CPU_BMIPS
1058 2052
1059 config ARM64_ERRATUM_2966298 !! 2053 config SYS_HAS_CPU_BMIPS4380
1060 bool "Cortex-A520: 2966298: workaroun !! 2054 bool
1061 select ARM64_WORKAROUND_SPECULATIVE_U !! 2055 select SYS_HAS_CPU_BMIPS
1062 default y <<
1063 help <<
1064 This option adds the workaround for <<
1065 2056
1066 On an affected Cortex-A520 core, a !! 2057 config SYS_HAS_CPU_BMIPS5000
1067 load might leak data from a privile !! 2058 bool
>> 2059 select SYS_HAS_CPU_BMIPS
>> 2060 select ARCH_HAS_SYNC_DMA_FOR_CPU
1068 2061
1069 Work around this problem by executi !! 2062 config SYS_HAS_CPU_XLR
>> 2063 bool
1070 2064
1071 If unsure, say Y. !! 2065 config SYS_HAS_CPU_XLP
>> 2066 bool
1072 2067
1073 config ARM64_ERRATUM_3117295 !! 2068 #
1074 bool "Cortex-A510: 3117295: workaroun !! 2069 # CPU may reorder R->R, R->W, W->R, W->W
1075 select ARM64_WORKAROUND_SPECULATIVE_U !! 2070 # Reordering beyond LL and SC is handled in WEAK_REORDERING_BEYOND_LLSC
1076 default y !! 2071 #
1077 help !! 2072 config WEAK_ORDERING
1078 This option adds the workaround for !! 2073 bool
1079 2074
1080 On an affected Cortex-A510 core, a !! 2075 #
1081 load might leak data from a privile !! 2076 # CPU may reorder reads and writes beyond LL/SC
>> 2077 # CPU may reorder R->LL, R->LL, W->LL, W->LL, R->SC, R->SC, W->SC, W->SC
>> 2078 #
>> 2079 config WEAK_REORDERING_BEYOND_LLSC
>> 2080 bool
>> 2081 endmenu
1082 2082
1083 Work around this problem by executi !! 2083 #
>> 2084 # These two indicate any level of the MIPS32 and MIPS64 architecture
>> 2085 #
>> 2086 config CPU_MIPS32
>> 2087 bool
>> 2088 default y if CPU_MIPS32_R1 || CPU_MIPS32_R2 || CPU_MIPS32_R6
1084 2089
1085 If unsure, say Y. !! 2090 config CPU_MIPS64
>> 2091 bool
>> 2092 default y if CPU_MIPS64_R1 || CPU_MIPS64_R2 || CPU_MIPS64_R6
1086 2093
1087 config ARM64_ERRATUM_3194386 !! 2094 #
1088 bool "Cortex-*/Neoverse-*: workaround !! 2095 # These indicate the revision of the architecture
1089 default y !! 2096 #
1090 help !! 2097 config CPU_MIPSR1
1091 This option adds the workaround for !! 2098 bool
>> 2099 default y if CPU_MIPS32_R1 || CPU_MIPS64_R1
1092 2100
1093 * ARM Cortex-A76 erratum 3324349 !! 2101 config CPU_MIPSR2
1094 * ARM Cortex-A77 erratum 3324348 !! 2102 bool
1095 * ARM Cortex-A78 erratum 3324344 !! 2103 default y if CPU_MIPS32_R2 || CPU_MIPS64_R2 || CPU_CAVIUM_OCTEON
1096 * ARM Cortex-A78C erratum 3324346 !! 2104 select CPU_HAS_RIXI
1097 * ARM Cortex-A78C erratum 3324347 !! 2105 select CPU_HAS_DIEI if !CPU_DIEI_BROKEN
1098 * ARM Cortex-A710 erratam 3324338 !! 2106 select MIPS_SPRAM
1099 * ARM Cortex-A715 errartum 3456084 <<
1100 * ARM Cortex-A720 erratum 3456091 <<
1101 * ARM Cortex-A725 erratum 3456106 <<
1102 * ARM Cortex-X1 erratum 3324344 <<
1103 * ARM Cortex-X1C erratum 3324346 <<
1104 * ARM Cortex-X2 erratum 3324338 <<
1105 * ARM Cortex-X3 erratum 3324335 <<
1106 * ARM Cortex-X4 erratum 3194386 <<
1107 * ARM Cortex-X925 erratum 3324334 <<
1108 * ARM Neoverse-N1 erratum 3324349 <<
1109 * ARM Neoverse N2 erratum 3324339 <<
1110 * ARM Neoverse-N3 erratum 3456111 <<
1111 * ARM Neoverse-V1 erratum 3324341 <<
1112 * ARM Neoverse V2 erratum 3324336 <<
1113 * ARM Neoverse-V3 erratum 3312417 <<
1114 <<
1115 On affected cores "MSR SSBS, #0" in <<
1116 subsequent speculative instructions <<
1117 speculative store bypassing. <<
1118 <<
1119 Work around this problem by placing <<
1120 Instruction Synchronization Barrier <<
1121 SSBS. The presence of the SSBS spec <<
1122 from hwcaps and EL0 reads of ID_AA6 <<
1123 will use the PR_SPEC_STORE_BYPASS p <<
1124 2107
1125 If unsure, say Y. !! 2108 config CPU_MIPSR6
>> 2109 bool
>> 2110 default y if CPU_MIPS32_R6 || CPU_MIPS64_R6
>> 2111 select CPU_HAS_RIXI
>> 2112 select CPU_HAS_DIEI if !CPU_DIEI_BROKEN
>> 2113 select HAVE_ARCH_BITREVERSE
>> 2114 select MIPS_ASID_BITS_VARIABLE
>> 2115 select MIPS_CRC_SUPPORT
>> 2116 select MIPS_SPRAM
1126 2117
1127 config CAVIUM_ERRATUM_22375 !! 2118 config TARGET_ISA_REV
1128 bool "Cavium erratum 22375, 24313" !! 2119 int
1129 default y !! 2120 default 1 if CPU_MIPSR1
>> 2121 default 2 if CPU_MIPSR2
>> 2122 default 6 if CPU_MIPSR6
>> 2123 default 0
1130 help 2124 help
1131 Enable workaround for errata 22375 !! 2125 Reflects the ISA revision being targeted by the kernel build. This
>> 2126 is effectively the Kconfig equivalent of MIPS_ISA_REV.
1132 2127
1133 This implements two gicv3-its errat !! 2128 config EVA
1134 with a small impact affecting only !! 2129 bool
1135 <<
1136 erratum 22375: only alloc 8MB tab <<
1137 erratum 24313: ignore memory acce <<
1138 2130
1139 The fixes are in ITS initialization !! 2131 config XPA
1140 type and table size provided by the !! 2132 bool
1141 2133
1142 If unsure, say Y. !! 2134 config SYS_SUPPORTS_32BIT_KERNEL
>> 2135 bool
>> 2136 config SYS_SUPPORTS_64BIT_KERNEL
>> 2137 bool
>> 2138 config CPU_SUPPORTS_32BIT_KERNEL
>> 2139 bool
>> 2140 config CPU_SUPPORTS_64BIT_KERNEL
>> 2141 bool
>> 2142 config CPU_SUPPORTS_CPUFREQ
>> 2143 bool
>> 2144 config CPU_SUPPORTS_ADDRWINCFG
>> 2145 bool
>> 2146 config CPU_SUPPORTS_HUGEPAGES
>> 2147 bool
>> 2148 depends on !(32BIT && (ARCH_PHYS_ADDR_T_64BIT || EVA))
>> 2149 config MIPS_PGD_C0_CONTEXT
>> 2150 bool
>> 2151 default y if 64BIT && (CPU_MIPSR2 || CPU_MIPSR6) && !CPU_XLP
1143 2152
1144 config CAVIUM_ERRATUM_23144 !! 2153 #
1145 bool "Cavium erratum 23144: ITS SYNC !! 2154 # Set to y for ptrace access to watch registers.
1146 depends on NUMA !! 2155 #
1147 default y !! 2156 config HARDWARE_WATCHPOINTS
1148 help !! 2157 bool
1149 ITS SYNC command hang for cross nod !! 2158 default y if CPU_MIPSR1 || CPU_MIPSR2 || CPU_MIPSR6
1150 2159
1151 If unsure, say Y. !! 2160 menu "Kernel type"
1152 2161
1153 config CAVIUM_ERRATUM_23154 !! 2162 choice
1154 bool "Cavium errata 23154 and 38545: !! 2163 prompt "Kernel code model"
1155 default y <<
1156 help 2164 help
1157 The ThunderX GICv3 implementation r !! 2165 You should only select this option if you have a workload that
1158 reading the IAR status to ensure da !! 2166 actually benefits from 64-bit processing or if your machine has
1159 (access to icc_iar1_el1 is not sync !! 2167 large memory. You will only be presented a single option in this
1160 !! 2168 menu if your system does not support both 32-bit and 64-bit kernels.
1161 It also suffers from erratum 38545 !! 2169
1162 OcteonTX and OcteonTX2), resulting !! 2170 config 32BIT
1163 spuriously presented to the CPU int !! 2171 bool "32-bit kernel"
1164 !! 2172 depends on CPU_SUPPORTS_32BIT_KERNEL && SYS_SUPPORTS_32BIT_KERNEL
1165 If unsure, say Y. !! 2173 select TRAD_SIGNALS
1166 <<
1167 config CAVIUM_ERRATUM_27456 <<
1168 bool "Cavium erratum 27456: Broadcast <<
1169 default y <<
1170 help 2174 help
1171 On ThunderX T88 pass 1.x through 2. !! 2175 Select this option if you want to build a 32-bit kernel.
1172 instructions may cause the icache t <<
1173 contains data for a non-current ASI <<
1174 invalidate the icache when changing <<
1175 2176
1176 If unsure, say Y. !! 2177 config 64BIT
1177 !! 2178 bool "64-bit kernel"
1178 config CAVIUM_ERRATUM_30115 !! 2179 depends on CPU_SUPPORTS_64BIT_KERNEL && SYS_SUPPORTS_64BIT_KERNEL
1179 bool "Cavium erratum 30115: Guest may <<
1180 default y <<
1181 help 2180 help
1182 On ThunderX T88 pass 1.x through 2. !! 2181 Select this option if you want to build a 64-bit kernel.
1183 1.2, and T83 Pass 1.0, KVM guest ex <<
1184 interrupts in host. Trapping both G <<
1185 accesses sidesteps the issue. <<
1186 <<
1187 If unsure, say Y. <<
1188 2182
1189 config CAVIUM_TX2_ERRATUM_219 !! 2183 endchoice
1190 bool "Cavium ThunderX2 erratum 219: P <<
1191 default y <<
1192 help <<
1193 On Cavium ThunderX2, a load, store <<
1194 TTBR update and the corresponding c <<
1195 cause a spurious Data Abort to be d <<
1196 the CPU core. <<
1197 <<
1198 Work around the issue by avoiding t <<
1199 trapping KVM guest TTBRx_EL1 writes <<
1200 trap handler performs the correspon <<
1201 instruction and ensures context syn <<
1202 exception return. <<
1203 2184
1204 If unsure, say Y. !! 2185 config KVM_GUEST
>> 2186 bool "KVM Guest Kernel"
>> 2187 depends on BROKEN_ON_SMP
>> 2188 help
>> 2189 Select this option if building a guest kernel for KVM (Trap & Emulate)
>> 2190 mode.
>> 2191
>> 2192 config KVM_GUEST_TIMER_FREQ
>> 2193 int "Count/Compare Timer Frequency (MHz)"
>> 2194 depends on KVM_GUEST
>> 2195 default 100
>> 2196 help
>> 2197 Set this to non-zero if building a guest kernel for KVM to skip RTC
>> 2198 emulation when determining guest CPU Frequency. Instead, the guest's
>> 2199 timer frequency is specified directly.
>> 2200
>> 2201 config MIPS_VA_BITS_48
>> 2202 bool "48 bits virtual memory"
>> 2203 depends on 64BIT
>> 2204 help
>> 2205 Support a maximum at least 48 bits of application virtual
>> 2206 memory. Default is 40 bits or less, depending on the CPU.
>> 2207 For page sizes 16k and above, this option results in a small
>> 2208 memory overhead for page tables. For 4k page size, a fourth
>> 2209 level of page tables is added which imposes both a memory
>> 2210 overhead as well as slower TLB fault handling.
1205 2211
1206 config FUJITSU_ERRATUM_010001 !! 2212 If unsure, say N.
1207 bool "Fujitsu-A64FX erratum E#010001: <<
1208 default y <<
1209 help <<
1210 This option adds a workaround for F <<
1211 On some variants of the Fujitsu-A64 <<
1212 accesses may cause undefined fault <<
1213 This fault occurs under a specific <<
1214 load/store instruction performs an <<
1215 case-1 TTBR0_EL1 with TCR_EL1.NFD0 <<
1216 case-2 TTBR0_EL2 with TCR_EL2.NFD0 <<
1217 case-3 TTBR1_EL1 with TCR_EL1.NFD1 <<
1218 case-4 TTBR1_EL2 with TCR_EL2.NFD1 <<
1219 2213
1220 The workaround is to ensure these b !! 2214 choice
1221 The workaround only affects the Fuj !! 2215 prompt "Kernel page size"
>> 2216 default PAGE_SIZE_4KB
1222 2217
1223 If unsure, say Y. !! 2218 config PAGE_SIZE_4KB
>> 2219 bool "4kB"
>> 2220 depends on !CPU_LOONGSON2EF && !CPU_LOONGSON64
>> 2221 help
>> 2222 This option select the standard 4kB Linux page size. On some
>> 2223 R3000-family processors this is the only available page size. Using
>> 2224 4kB page size will minimize memory consumption and is therefore
>> 2225 recommended for low memory systems.
>> 2226
>> 2227 config PAGE_SIZE_8KB
>> 2228 bool "8kB"
>> 2229 depends on CPU_CAVIUM_OCTEON
>> 2230 depends on !MIPS_VA_BITS_48
>> 2231 help
>> 2232 Using 8kB page size will result in higher performance kernel at
>> 2233 the price of higher memory consumption. This option is available
>> 2234 only on cnMIPS processors. Note that you will need a suitable Linux
>> 2235 distribution to support this.
>> 2236
>> 2237 config PAGE_SIZE_16KB
>> 2238 bool "16kB"
>> 2239 depends on !CPU_R3000 && !CPU_TX39XX
>> 2240 help
>> 2241 Using 16kB page size will result in higher performance kernel at
>> 2242 the price of higher memory consumption. This option is available on
>> 2243 all non-R3000 family processors. Note that you will need a suitable
>> 2244 Linux distribution to support this.
>> 2245
>> 2246 config PAGE_SIZE_32KB
>> 2247 bool "32kB"
>> 2248 depends on CPU_CAVIUM_OCTEON
>> 2249 depends on !MIPS_VA_BITS_48
>> 2250 help
>> 2251 Using 32kB page size will result in higher performance kernel at
>> 2252 the price of higher memory consumption. This option is available
>> 2253 only on cnMIPS cores. Note that you will need a suitable Linux
>> 2254 distribution to support this.
>> 2255
>> 2256 config PAGE_SIZE_64KB
>> 2257 bool "64kB"
>> 2258 depends on !CPU_R3000 && !CPU_TX39XX
>> 2259 help
>> 2260 Using 64kB page size will result in higher performance kernel at
>> 2261 the price of higher memory consumption. This option is available on
>> 2262 all non-R3000 family processor. Not that at the time of this
>> 2263 writing this option is still high experimental.
1224 2264
1225 config HISILICON_ERRATUM_161600802 !! 2265 endchoice
1226 bool "Hip07 161600802: Erroneous redi <<
1227 default y <<
1228 help <<
1229 The HiSilicon Hip07 SoC uses the wr <<
1230 when issued ITS commands such as VM <<
1231 a 128kB offset to be applied to the <<
1232 2266
1233 If unsure, say Y. !! 2267 config FORCE_MAX_ZONEORDER
>> 2268 int "Maximum zone order"
>> 2269 range 14 64 if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_64KB
>> 2270 default "14" if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_64KB
>> 2271 range 13 64 if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_32KB
>> 2272 default "13" if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_32KB
>> 2273 range 12 64 if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_16KB
>> 2274 default "12" if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_16KB
>> 2275 range 11 64
>> 2276 default "11"
>> 2277 help
>> 2278 The kernel memory allocator divides physically contiguous memory
>> 2279 blocks into "zones", where each zone is a power of two number of
>> 2280 pages. This option selects the largest power of two that the kernel
>> 2281 keeps in the memory allocator. If you need to allocate very large
>> 2282 blocks of physically contiguous memory, then you may need to
>> 2283 increase this value.
1234 2284
1235 config QCOM_FALKOR_ERRATUM_1003 !! 2285 This config option is actually maximum order plus one. For example,
1236 bool "Falkor E1003: Incorrect transla !! 2286 a value of 11 means that the largest free memory block is 2^10 pages.
1237 default y <<
1238 help <<
1239 On Falkor v1, an incorrect ASID may <<
1240 and BADDR are changed together in T <<
1241 in TTBR1_EL1, this situation only o <<
1242 then only for entries in the walk c <<
1243 is unchanged. Work around the errat <<
1244 entries for the trampoline before e <<
1245 2287
1246 config QCOM_FALKOR_ERRATUM_1009 !! 2288 The page size is not necessarily 4KB. Keep this in mind
1247 bool "Falkor E1009: Prematurely compl !! 2289 when choosing a value for this option.
1248 default y <<
1249 select ARM64_WORKAROUND_REPEAT_TLBI <<
1250 help <<
1251 On Falkor v1, the CPU may premature <<
1252 TLBI xxIS invalidate maintenance op <<
1253 one more time to fix the issue. <<
1254 2290
1255 If unsure, say Y. !! 2291 config BOARD_SCACHE
>> 2292 bool
1256 2293
1257 config QCOM_QDF2400_ERRATUM_0065 !! 2294 config IP22_CPU_SCACHE
1258 bool "QDF2400 E0065: Incorrect GITS_T !! 2295 bool
1259 default y !! 2296 select BOARD_SCACHE
1260 help <<
1261 On Qualcomm Datacenter Technologies <<
1262 ITE size incorrectly. The GITS_TYPE <<
1263 been indicated as 16Bytes (0xf), no <<
1264 2297
1265 If unsure, say Y. !! 2298 #
>> 2299 # Support for a MIPS32 / MIPS64 style S-caches
>> 2300 #
>> 2301 config MIPS_CPU_SCACHE
>> 2302 bool
>> 2303 select BOARD_SCACHE
1266 2304
1267 config QCOM_FALKOR_ERRATUM_E1041 !! 2305 config R5000_CPU_SCACHE
1268 bool "Falkor E1041: Speculative instr !! 2306 bool
1269 default y !! 2307 select BOARD_SCACHE
1270 help <<
1271 Falkor CPU may speculatively fetch <<
1272 memory location when MMU translatio <<
1273 to SCTLR_ELn[M]=0. Prefix an ISB in <<
1274 2308
1275 If unsure, say Y. !! 2309 config RM7000_CPU_SCACHE
>> 2310 bool
>> 2311 select BOARD_SCACHE
1276 2312
1277 config NVIDIA_CARMEL_CNP_ERRATUM !! 2313 config SIBYTE_DMA_PAGEOPS
1278 bool "NVIDIA Carmel CNP: CNP on Carme !! 2314 bool "Use DMA to clear/copy pages"
1279 default y !! 2315 depends on CPU_SB1
1280 help 2316 help
1281 If CNP is enabled on Carmel cores, !! 2317 Instead of using the CPU to zero and copy pages, use a Data Mover
1282 invalidate shared TLB entries insta !! 2318 channel. These DMA channels are otherwise unused by the standard
1283 on standard ARM cores. !! 2319 SiByte Linux port. Seems to give a small performance benefit.
1284 <<
1285 If unsure, say Y. <<
1286 2320
1287 config ROCKCHIP_ERRATUM_3588001 !! 2321 config CPU_HAS_PREFETCH
1288 bool "Rockchip 3588001: GIC600 can no !! 2322 bool
1289 default y <<
1290 help <<
1291 The Rockchip RK3588 GIC600 SoC inte <<
1292 This means, that its sharability fe <<
1293 is supported by the IP itself. <<
1294 2323
1295 If unsure, say Y. !! 2324 config CPU_GENERIC_DUMP_TLB
>> 2325 bool
>> 2326 default y if !(CPU_R3000 || CPU_TX39XX)
1296 2327
1297 config SOCIONEXT_SYNQUACER_PREITS !! 2328 config MIPS_FP_SUPPORT
1298 bool "Socionext Synquacer: Workaround !! 2329 bool "Floating Point support" if EXPERT
1299 default y 2330 default y
1300 help 2331 help
1301 Socionext Synquacer SoCs implement !! 2332 Select y to include support for floating point in the kernel
1302 MSI doorbell writes with non-zero v !! 2333 including initialization of FPU hardware, FP context save & restore
1303 !! 2334 and emulation of an FPU where necessary. Without this support any
1304 If unsure, say Y. !! 2335 userland program attempting to use floating point instructions will
1305 !! 2336 receive a SIGILL.
1306 endmenu # "ARM errata workarounds via the alt <<
1307 <<
1308 choice <<
1309 prompt "Page size" <<
1310 default ARM64_4K_PAGES <<
1311 help <<
1312 Page size (translation granule) con <<
1313 2337
1314 config ARM64_4K_PAGES !! 2338 If you know that your userland will not attempt to use floating point
1315 bool "4KB" !! 2339 instructions then you can say n here to shrink the kernel a little.
1316 select HAVE_PAGE_SIZE_4KB <<
1317 help <<
1318 This feature enables 4KB pages supp <<
1319 <<
1320 config ARM64_16K_PAGES <<
1321 bool "16KB" <<
1322 select HAVE_PAGE_SIZE_16KB <<
1323 help <<
1324 The system will use 16KB pages supp <<
1325 requires applications compiled with <<
1326 aligned segments. <<
1327 2340
1328 config ARM64_64K_PAGES !! 2341 If unsure, say y.
1329 bool "64KB" <<
1330 select HAVE_PAGE_SIZE_64KB <<
1331 help <<
1332 This feature enables 64KB pages sup <<
1333 allowing only two levels of page ta <<
1334 look-up. AArch32 emulation requires <<
1335 with 64K aligned segments. <<
1336 2342
1337 endchoice !! 2343 config CPU_R2300_FPU
>> 2344 bool
>> 2345 depends on MIPS_FP_SUPPORT
>> 2346 default y if CPU_R3000 || CPU_TX39XX
1338 2347
1339 choice !! 2348 config CPU_R3K_TLB
1340 prompt "Virtual address space size" !! 2349 bool
1341 default ARM64_VA_BITS_52 <<
1342 help <<
1343 Allows choosing one of multiple pos <<
1344 space sizes. The level of translati <<
1345 a combination of page size and virt <<
1346 <<
1347 config ARM64_VA_BITS_36 <<
1348 bool "36-bit" if EXPERT <<
1349 depends on PAGE_SIZE_16KB <<
1350 <<
1351 config ARM64_VA_BITS_39 <<
1352 bool "39-bit" <<
1353 depends on PAGE_SIZE_4KB <<
1354 <<
1355 config ARM64_VA_BITS_42 <<
1356 bool "42-bit" <<
1357 depends on PAGE_SIZE_64KB <<
1358 <<
1359 config ARM64_VA_BITS_47 <<
1360 bool "47-bit" <<
1361 depends on PAGE_SIZE_16KB <<
1362 <<
1363 config ARM64_VA_BITS_48 <<
1364 bool "48-bit" <<
1365 <<
1366 config ARM64_VA_BITS_52 <<
1367 bool "52-bit" <<
1368 depends on ARM64_PAN || !ARM64_SW_TTB <<
1369 help <<
1370 Enable 52-bit virtual addressing fo <<
1371 requested via a hint to mmap(). The <<
1372 virtual addresses for its own mappi <<
1373 this feature is available, otherwis <<
1374 <<
1375 NOTE: Enabling 52-bit virtual addre <<
1376 ARMv8.3 Pointer Authentication will <<
1377 reduced from 7 bits to 3 bits, whic <<
1378 impact on its susceptibility to bru <<
1379 2350
1380 If unsure, select 48-bit virtual ad !! 2351 config CPU_R4K_FPU
>> 2352 bool
>> 2353 depends on MIPS_FP_SUPPORT
>> 2354 default y if !CPU_R2300_FPU
1381 2355
1382 endchoice !! 2356 config CPU_R4K_CACHE_TLB
>> 2357 bool
>> 2358 default y if !(CPU_R3K_TLB || CPU_SB1 || CPU_CAVIUM_OCTEON)
1383 2359
1384 config ARM64_FORCE_52BIT !! 2360 config MIPS_MT_SMP
1385 bool "Force 52-bit virtual addresses !! 2361 bool "MIPS MT SMP support (1 TC on each available VPE)"
1386 depends on ARM64_VA_BITS_52 && EXPERT !! 2362 default y
1387 help !! 2363 depends on SYS_SUPPORTS_MULTITHREADING && !CPU_MIPSR6 && !CPU_MICROMIPS
1388 For systems with 52-bit userspace V !! 2364 select CPU_MIPSR2_IRQ_VI
1389 to maintain compatibility with olde !! 2365 select CPU_MIPSR2_IRQ_EI
1390 unless a hint is supplied to mmap. !! 2366 select SYNC_R4K
1391 !! 2367 select MIPS_MT
1392 This configuration option disables !! 2368 select SMP
1393 forces all userspace addresses to b !! 2369 select SMP_UP
1394 should only enable this configurati !! 2370 select SYS_SUPPORTS_SMP
1395 memory management code. If unsure s !! 2371 select SYS_SUPPORTS_SCHED_SMT
>> 2372 select MIPS_PERF_SHARED_TC_COUNTERS
>> 2373 help
>> 2374 This is a kernel model which is known as SMVP. This is supported
>> 2375 on cores with the MT ASE and uses the available VPEs to implement
>> 2376 virtual processors which supports SMP. This is equivalent to the
>> 2377 Intel Hyperthreading feature. For further information go to
>> 2378 <http://www.imgtec.com/mips/mips-multithreading.asp>.
1396 2379
1397 config ARM64_VA_BITS !! 2380 config MIPS_MT
1398 int !! 2381 bool
1399 default 36 if ARM64_VA_BITS_36 <<
1400 default 39 if ARM64_VA_BITS_39 <<
1401 default 42 if ARM64_VA_BITS_42 <<
1402 default 47 if ARM64_VA_BITS_47 <<
1403 default 48 if ARM64_VA_BITS_48 <<
1404 default 52 if ARM64_VA_BITS_52 <<
1405 2382
1406 choice !! 2383 config SCHED_SMT
1407 prompt "Physical address space size" !! 2384 bool "SMT (multithreading) scheduler support"
1408 default ARM64_PA_BITS_48 !! 2385 depends on SYS_SUPPORTS_SCHED_SMT
>> 2386 default n
1409 help 2387 help
1410 Choose the maximum physical address !! 2388 SMT scheduler support improves the CPU scheduler's decision making
1411 support. !! 2389 when dealing with MIPS MT enabled cores at a cost of slightly
1412 !! 2390 increased overhead in some places. If unsure say N here.
1413 config ARM64_PA_BITS_48 <<
1414 bool "48-bit" <<
1415 depends on ARM64_64K_PAGES || !ARM64_ <<
1416 <<
1417 config ARM64_PA_BITS_52 <<
1418 bool "52-bit" <<
1419 depends on ARM64_64K_PAGES || ARM64_V <<
1420 depends on ARM64_PAN || !ARM64_SW_TTB <<
1421 help <<
1422 Enable support for a 52-bit physica <<
1423 part of the ARMv8.2-LPA extension. <<
1424 <<
1425 With this enabled, the kernel will <<
1426 do not support ARMv8.2-LPA, but wit <<
1427 minor performance overhead). <<
1428 2391
1429 endchoice !! 2392 config SYS_SUPPORTS_SCHED_SMT
>> 2393 bool
1430 2394
1431 config ARM64_PA_BITS !! 2395 config SYS_SUPPORTS_MULTITHREADING
1432 int !! 2396 bool
1433 default 48 if ARM64_PA_BITS_48 <<
1434 default 52 if ARM64_PA_BITS_52 <<
1435 2397
1436 config ARM64_LPA2 !! 2398 config MIPS_MT_FPAFF
1437 def_bool y !! 2399 bool "Dynamic FPU affinity for FP-intensive threads"
1438 depends on ARM64_PA_BITS_52 && !ARM64 !! 2400 default y
>> 2401 depends on MIPS_MT_SMP
1439 2402
1440 choice !! 2403 config MIPSR2_TO_R6_EMULATOR
1441 prompt "Endianness" !! 2404 bool "MIPS R2-to-R6 emulator"
1442 default CPU_LITTLE_ENDIAN !! 2405 depends on CPU_MIPSR6
>> 2406 depends on MIPS_FP_SUPPORT
>> 2407 default y
1443 help 2408 help
1444 Select the endianness of data acces !! 2409 Choose this option if you want to run non-R6 MIPS userland code.
1445 applications will need to be compil !! 2410 Even if you say 'Y' here, the emulator will still be disabled by
1446 that is selected here. !! 2411 default. You can enable it using the 'mipsr2emu' kernel option.
>> 2412 The only reason this is a build-time option is to save ~14K from the
>> 2413 final kernel image.
1447 2414
1448 config CPU_BIG_ENDIAN !! 2415 config SYS_SUPPORTS_VPE_LOADER
1449 bool "Build big-endian kernel" !! 2416 bool
1450 # https://github.com/llvm/llvm-projec !! 2417 depends on SYS_SUPPORTS_MULTITHREADING
1451 depends on AS_IS_GNU || AS_VERSION >= <<
1452 help 2418 help
1453 Say Y if you plan on running a kern !! 2419 Indicates that the platform supports the VPE loader, and provides
>> 2420 physical_memsize.
1454 2421
1455 config CPU_LITTLE_ENDIAN !! 2422 config MIPS_VPE_LOADER
1456 bool "Build little-endian kernel" !! 2423 bool "VPE loader support."
>> 2424 depends on SYS_SUPPORTS_VPE_LOADER && MODULES
>> 2425 select CPU_MIPSR2_IRQ_VI
>> 2426 select CPU_MIPSR2_IRQ_EI
>> 2427 select MIPS_MT
1457 help 2428 help
1458 Say Y if you plan on running a kern !! 2429 Includes a loader for loading an elf relocatable object
1459 This is usually the case for distri !! 2430 onto another VPE and running it.
1460 2431
1461 endchoice !! 2432 config MIPS_VPE_LOADER_CMP
>> 2433 bool
>> 2434 default "y"
>> 2435 depends on MIPS_VPE_LOADER && MIPS_CMP
1462 2436
1463 config SCHED_MC !! 2437 config MIPS_VPE_LOADER_MT
1464 bool "Multi-core scheduler support" !! 2438 bool
1465 help !! 2439 default "y"
1466 Multi-core scheduler support improv !! 2440 depends on MIPS_VPE_LOADER && !MIPS_CMP
1467 making when dealing with multi-core <<
1468 increased overhead in some places. <<
1469 2441
1470 config SCHED_CLUSTER !! 2442 config MIPS_VPE_LOADER_TOM
1471 bool "Cluster scheduler support" !! 2443 bool "Load VPE program into memory hidden from linux"
>> 2444 depends on MIPS_VPE_LOADER
>> 2445 default y
1472 help 2446 help
1473 Cluster scheduler support improves !! 2447 The loader can use memory that is present but has been hidden from
1474 making when dealing with machines t !! 2448 Linux using the kernel command line option "mem=xxMB". It's up to
1475 Cluster usually means a couple of C !! 2449 you to ensure the amount you put in the option and the space your
1476 by sharing mid-level caches, last-l !! 2450 program requires is less or equal to the amount physically present.
1477 busses. <<
1478 2451
1479 config SCHED_SMT !! 2452 config MIPS_VPE_APSP_API
1480 bool "SMT scheduler support" !! 2453 bool "Enable support for AP/SP API (RTLX)"
1481 help !! 2454 depends on MIPS_VPE_LOADER
1482 Improves the CPU scheduler's decisi <<
1483 MultiThreading at a cost of slightl <<
1484 places. If unsure say N here. <<
1485 2455
1486 config NR_CPUS !! 2456 config MIPS_VPE_APSP_API_CMP
1487 int "Maximum number of CPUs (2-4096)" !! 2457 bool
1488 range 2 4096 !! 2458 default "y"
1489 default "512" !! 2459 depends on MIPS_VPE_APSP_API && MIPS_CMP
1490 2460
1491 config HOTPLUG_CPU !! 2461 config MIPS_VPE_APSP_API_MT
1492 bool "Support for hot-pluggable CPUs" !! 2462 bool
1493 select GENERIC_IRQ_MIGRATION !! 2463 default "y"
>> 2464 depends on MIPS_VPE_APSP_API && !MIPS_CMP
>> 2465
>> 2466 config MIPS_CMP
>> 2467 bool "MIPS CMP framework support (DEPRECATED)"
>> 2468 depends on SYS_SUPPORTS_MIPS_CMP && !CPU_MIPSR6
>> 2469 select SMP
>> 2470 select SYNC_R4K
>> 2471 select SYS_SUPPORTS_SMP
>> 2472 select WEAK_ORDERING
>> 2473 default n
1494 help 2474 help
1495 Say Y here to experiment with turni !! 2475 Select this if you are using a bootloader which implements the "CMP
1496 can be controlled through /sys/devi !! 2476 framework" protocol (ie. YAMON) and want your kernel to make use of
>> 2477 its ability to start secondary CPUs.
>> 2478
>> 2479 Unless you have a specific need, you should use CONFIG_MIPS_CPS
>> 2480 instead of this.
>> 2481
>> 2482 config MIPS_CPS
>> 2483 bool "MIPS Coherent Processing System support"
>> 2484 depends on SYS_SUPPORTS_MIPS_CPS
>> 2485 select MIPS_CM
>> 2486 select MIPS_CPS_PM if HOTPLUG_CPU
>> 2487 select SMP
>> 2488 select SYNC_R4K if (CEVT_R4K || CSRC_R4K)
>> 2489 select SYS_SUPPORTS_HOTPLUG_CPU
>> 2490 select SYS_SUPPORTS_SCHED_SMT if CPU_MIPSR6
>> 2491 select SYS_SUPPORTS_SMP
>> 2492 select WEAK_ORDERING
>> 2493 help
>> 2494 Select this if you wish to run an SMP kernel across multiple cores
>> 2495 within a MIPS Coherent Processing System. When this option is
>> 2496 enabled the kernel will probe for other cores and boot them with
>> 2497 no external assistance. It is safe to enable this when hardware
>> 2498 support is unavailable.
1497 2499
1498 # Common NUMA Features !! 2500 config MIPS_CPS_PM
1499 config NUMA !! 2501 depends on MIPS_CPS
1500 bool "NUMA Memory Allocation and Sche !! 2502 bool
1501 select GENERIC_ARCH_NUMA <<
1502 select OF_NUMA <<
1503 select HAVE_SETUP_PER_CPU_AREA <<
1504 select NEED_PER_CPU_EMBED_FIRST_CHUNK <<
1505 select NEED_PER_CPU_PAGE_FIRST_CHUNK <<
1506 select USE_PERCPU_NUMA_NODE_ID <<
1507 help <<
1508 Enable NUMA (Non-Uniform Memory Acc <<
1509 <<
1510 The kernel will try to allocate mem <<
1511 local memory of the CPU and add som <<
1512 NUMA awareness to the kernel. <<
1513 2503
1514 config NODES_SHIFT !! 2504 config MIPS_CM
1515 int "Maximum NUMA Nodes (as a power o !! 2505 bool
1516 range 1 10 !! 2506 select MIPS_CPC
1517 default "4" <<
1518 depends on NUMA <<
1519 help <<
1520 Specify the maximum number of NUMA <<
1521 system. Increases memory reserved <<
1522 2507
1523 source "kernel/Kconfig.hz" !! 2508 config MIPS_CPC
>> 2509 bool
1524 2510
1525 config ARCH_SPARSEMEM_ENABLE !! 2511 config SB1_PASS_2_WORKAROUNDS
1526 def_bool y !! 2512 bool
1527 select SPARSEMEM_VMEMMAP_ENABLE !! 2513 depends on CPU_SB1 && (CPU_SB1_PASS_2_2 || CPU_SB1_PASS_2)
1528 select SPARSEMEM_VMEMMAP !! 2514 default y
1529 2515
1530 config HW_PERF_EVENTS !! 2516 config SB1_PASS_2_1_WORKAROUNDS
1531 def_bool y !! 2517 bool
1532 depends on ARM_PMU !! 2518 depends on CPU_SB1 && CPU_SB1_PASS_2
>> 2519 default y
1533 2520
1534 # Supported by clang >= 7.0 or GCC >= 12.0.0 !! 2521 choice
1535 config CC_HAVE_SHADOW_CALL_STACK !! 2522 prompt "SmartMIPS or microMIPS ASE support"
1536 def_bool $(cc-option, -fsanitize=shad <<
1537 2523
1538 config PARAVIRT !! 2524 config CPU_NEEDS_NO_SMARTMIPS_OR_MICROMIPS
1539 bool "Enable paravirtualization code" !! 2525 bool "None"
1540 help 2526 help
1541 This changes the kernel so it can m !! 2527 Select this if you want neither microMIPS nor SmartMIPS support
1542 under a hypervisor, potentially imp <<
1543 over full virtualization. <<
1544 2528
1545 config PARAVIRT_TIME_ACCOUNTING !! 2529 config CPU_HAS_SMARTMIPS
1546 bool "Paravirtual steal time accounti !! 2530 depends on SYS_SUPPORTS_SMARTMIPS
1547 select PARAVIRT !! 2531 bool "SmartMIPS"
>> 2532 help
>> 2533 SmartMIPS is a extension of the MIPS32 architecture aimed at
>> 2534 increased security at both hardware and software level for
>> 2535 smartcards. Enabling this option will allow proper use of the
>> 2536 SmartMIPS instructions by Linux applications. However a kernel with
>> 2537 this option will not work on a MIPS core without SmartMIPS core. If
>> 2538 you don't know you probably don't have SmartMIPS and should say N
>> 2539 here.
>> 2540
>> 2541 config CPU_MICROMIPS
>> 2542 depends on 32BIT && SYS_SUPPORTS_MICROMIPS && !CPU_MIPSR6
>> 2543 bool "microMIPS"
1548 help 2544 help
1549 Select this option to enable fine g !! 2545 When this option is enabled the kernel will be built using the
1550 accounting. Time spent executing ot !! 2546 microMIPS ISA
1551 the current vCPU is discounted from <<
1552 that, there can be a small performa <<
1553 <<
1554 If in doubt, say N here. <<
1555 2547
1556 config ARCH_SUPPORTS_KEXEC !! 2548 endchoice
1557 def_bool PM_SLEEP_SMP <<
1558 2549
1559 config ARCH_SUPPORTS_KEXEC_FILE !! 2550 config CPU_HAS_MSA
1560 def_bool y !! 2551 bool "Support for the MIPS SIMD Architecture"
>> 2552 depends on CPU_SUPPORTS_MSA
>> 2553 depends on MIPS_FP_SUPPORT
>> 2554 depends on 64BIT || MIPS_O32_FP64_SUPPORT
>> 2555 help
>> 2556 MIPS SIMD Architecture (MSA) introduces 128 bit wide vector registers
>> 2557 and a set of SIMD instructions to operate on them. When this option
>> 2558 is enabled the kernel will support allocating & switching MSA
>> 2559 vector register contexts. If you know that your kernel will only be
>> 2560 running on CPUs which do not support MSA or that your userland will
>> 2561 not be making use of it then you may wish to say N here to reduce
>> 2562 the size & complexity of your kernel.
1561 2563
1562 config ARCH_SELECTS_KEXEC_FILE !! 2564 If unsure, say Y.
1563 def_bool y <<
1564 depends on KEXEC_FILE <<
1565 select HAVE_IMA_KEXEC if IMA <<
1566 <<
1567 config ARCH_SUPPORTS_KEXEC_SIG <<
1568 def_bool y <<
1569 <<
1570 config ARCH_SUPPORTS_KEXEC_IMAGE_VERIFY_SIG <<
1571 def_bool y <<
1572 2565
1573 config ARCH_DEFAULT_KEXEC_IMAGE_VERIFY_SIG !! 2566 config CPU_HAS_WB
1574 def_bool y !! 2567 bool
1575 2568
1576 config ARCH_SUPPORTS_CRASH_DUMP !! 2569 config XKS01
1577 def_bool y !! 2570 bool
1578 2571
1579 config ARCH_HAS_GENERIC_CRASHKERNEL_RESERVATI !! 2572 config CPU_HAS_DIEI
1580 def_bool CRASH_RESERVE !! 2573 depends on !CPU_DIEI_BROKEN
>> 2574 bool
1581 2575
1582 config TRANS_TABLE !! 2576 config CPU_DIEI_BROKEN
1583 def_bool y !! 2577 bool
1584 depends on HIBERNATION || KEXEC_CORE <<
1585 2578
1586 config XEN_DOM0 !! 2579 config CPU_HAS_RIXI
1587 def_bool y !! 2580 bool
1588 depends on XEN <<
1589 2581
1590 config XEN !! 2582 config CPU_NO_LOAD_STORE_LR
1591 bool "Xen guest support on ARM64" !! 2583 bool
1592 depends on ARM64 && OF <<
1593 select SWIOTLB_XEN <<
1594 select PARAVIRT <<
1595 help 2584 help
1596 Say Y if you want to run Linux in a !! 2585 CPU lacks support for unaligned load and store instructions:
>> 2586 LWL, LWR, SWL, SWR (Load/store word left/right).
>> 2587 LDL, LDR, SDL, SDR (Load/store doubleword left/right, for 64bit
>> 2588 systems).
1597 2589
1598 # include/linux/mmzone.h requires the followi <<
1599 # <<
1600 # MAX_PAGE_ORDER + PAGE_SHIFT <= SECTION_SI <<
1601 # 2590 #
1602 # so the maximum value of MAX_PAGE_ORDER is S !! 2591 # Vectored interrupt mode is an R2 feature
1603 # 2592 #
1604 # | SECTION_SIZE_BITS | PAGE_SHIFT | m !! 2593 config CPU_MIPSR2_IRQ_VI
1605 # ----+-------------------+--------------+--- !! 2594 bool
1606 # 4K | 27 | 12 | <<
1607 # 16K | 27 | 14 | <<
1608 # 64K | 29 | 16 | <<
1609 config ARCH_FORCE_MAX_ORDER <<
1610 int <<
1611 default "13" if ARM64_64K_PAGES <<
1612 default "11" if ARM64_16K_PAGES <<
1613 default "10" <<
1614 help <<
1615 The kernel page allocator limits th <<
1616 contiguous allocations. The limit i <<
1617 defines the maximal power of two of <<
1618 allocated as a single contiguous bl <<
1619 overriding the default setting when <<
1620 large blocks of physically contiguo <<
1621 <<
1622 The maximal size of allocation cann <<
1623 section, so the value of MAX_PAGE_O <<
1624 <<
1625 MAX_PAGE_ORDER + PAGE_SHIFT <= SE <<
1626 <<
1627 Don't change if unsure. <<
1628 <<
1629 config UNMAP_KERNEL_AT_EL0 <<
1630 bool "Unmap kernel when running in us <<
1631 default y <<
1632 help <<
1633 Speculation attacks against some hi <<
1634 be used to bypass MMU permission ch <<
1635 userspace. This can be defended aga <<
1636 when running in userspace, mapping <<
1637 via a trampoline page in the vector <<
1638 <<
1639 If unsure, say Y. <<
1640 2595
1641 config MITIGATE_SPECTRE_BRANCH_HISTORY !! 2596 #
1642 bool "Mitigate Spectre style attacks !! 2597 # Extended interrupt mode is an R2 feature
1643 default y !! 2598 #
1644 help !! 2599 config CPU_MIPSR2_IRQ_EI
1645 Speculation attacks against some hi !! 2600 bool
1646 make use of branch history to influ <<
1647 When taking an exception from user- <<
1648 or a firmware call overwrites the b <<
1649 2601
1650 config RODATA_FULL_DEFAULT_ENABLED !! 2602 config CPU_HAS_SYNC
1651 bool "Apply r/o permissions of VM are !! 2603 bool
>> 2604 depends on !CPU_R3000
1652 default y 2605 default y
1653 help <<
1654 Apply read-only attributes of VM ar <<
1655 the backing pages as well. This pre <<
1656 from being modified (inadvertently <<
1657 mapping of the same memory page. Th <<
1658 be turned off at runtime by passing <<
1659 with rodata=full if this option is <<
1660 2606
1661 This requires the linear region to !! 2607 #
1662 which may adversely affect performa !! 2608 # CPU non-features
>> 2609 #
>> 2610 config CPU_DADDI_WORKAROUNDS
>> 2611 bool
1663 2612
1664 config ARM64_SW_TTBR0_PAN !! 2613 config CPU_R4000_WORKAROUNDS
1665 bool "Emulate Privileged Access Never !! 2614 bool
1666 depends on !KCSAN !! 2615 select CPU_R4400_WORKAROUNDS
1667 help <<
1668 Enabling this option prevents the k <<
1669 user-space memory directly by point <<
1670 zeroed area and reserved ASID. The <<
1671 restore the valid TTBR0_EL1 tempora <<
1672 2616
1673 config ARM64_TAGGED_ADDR_ABI !! 2617 config CPU_R4400_WORKAROUNDS
1674 bool "Enable the tagged user addresse !! 2618 bool
1675 default y <<
1676 help <<
1677 When this option is enabled, user a <<
1678 relaxed ABI via prctl() allowing ta <<
1679 to system calls as pointer argument <<
1680 Documentation/arch/arm64/tagged-add <<
1681 2619
1682 menuconfig COMPAT !! 2620 config CPU_R4X00_BUGS64
1683 bool "Kernel support for 32-bit EL0" !! 2621 bool
1684 depends on ARM64_4K_PAGES || EXPERT !! 2622 default y if SYS_HAS_CPU_R4X00 && 64BIT && (TARGET_ISA_REV < 1)
1685 select HAVE_UID16 <<
1686 select OLD_SIGSUSPEND3 <<
1687 select COMPAT_OLD_SIGACTION <<
1688 help <<
1689 This option enables support for a 3 <<
1690 kernel at EL1. AArch32-specific com <<
1691 the user helper functions, VFP supp <<
1692 handled appropriately by the kernel <<
1693 2623
1694 If you use a page size other than 4 !! 2624 config MIPS_ASID_SHIFT
1695 that you will only be able to execu !! 2625 int
1696 with page size aligned segments. !! 2626 default 6 if CPU_R3000 || CPU_TX39XX
>> 2627 default 0
1697 2628
1698 If you want to execute 32-bit users !! 2629 config MIPS_ASID_BITS
>> 2630 int
>> 2631 default 0 if MIPS_ASID_BITS_VARIABLE
>> 2632 default 6 if CPU_R3000 || CPU_TX39XX
>> 2633 default 8
1699 2634
1700 if COMPAT !! 2635 config MIPS_ASID_BITS_VARIABLE
>> 2636 bool
1701 2637
1702 config KUSER_HELPERS !! 2638 config MIPS_CRC_SUPPORT
1703 bool "Enable kuser helpers page for 3 !! 2639 bool
1704 default y <<
1705 help <<
1706 Warning: disabling this option may <<
1707 2640
1708 Provide kuser helpers to compat tas !! 2641 #
1709 helper code to userspace in read on !! 2642 # - Highmem only makes sense for the 32-bit kernel.
1710 to allow userspace to be independen !! 2643 # - The current highmem code will only work properly on physically indexed
1711 the system. This permits binaries t !! 2644 # caches such as R3000, SB1, R7000 or those that look like they're virtually
1712 to ARMv8 without modification. !! 2645 # indexed such as R4000/R4400 SC and MC versions or R10000. So for the
>> 2646 # moment we protect the user and offer the highmem option only on machines
>> 2647 # where it's known to be safe. This will not offer highmem on a few systems
>> 2648 # such as MIPS32 and MIPS64 CPUs which may have virtual and physically
>> 2649 # indexed CPUs but we're playing safe.
>> 2650 # - We use SYS_SUPPORTS_HIGHMEM to offer highmem only for systems where we
>> 2651 # know they might have memory configurations that could make use of highmem
>> 2652 # support.
>> 2653 #
>> 2654 config HIGHMEM
>> 2655 bool "High Memory Support"
>> 2656 depends on 32BIT && CPU_SUPPORTS_HIGHMEM && SYS_SUPPORTS_HIGHMEM && !CPU_MIPS32_3_5_EVA
1713 2657
1714 See Documentation/arch/arm/kernel_u !! 2658 config CPU_SUPPORTS_HIGHMEM
>> 2659 bool
1715 2660
1716 However, the fixed address nature o !! 2661 config SYS_SUPPORTS_HIGHMEM
1717 by ROP (return orientated programmi !! 2662 bool
1718 exploits. <<
1719 2663
1720 If all of the binaries and librarie !! 2664 config SYS_SUPPORTS_SMARTMIPS
1721 are built specifically for your pla !! 2665 bool
1722 these helpers, then you can turn th <<
1723 such exploits. However, in that cas <<
1724 relying on those helpers is run, it <<
1725 2666
1726 Say N here only if you are absolute !! 2667 config SYS_SUPPORTS_MICROMIPS
1727 need these helpers; otherwise, the !! 2668 bool
1728 2669
1729 config COMPAT_VDSO !! 2670 config SYS_SUPPORTS_MIPS16
1730 bool "Enable vDSO for 32-bit applicat !! 2671 bool
1731 depends on !CPU_BIG_ENDIAN <<
1732 depends on (CC_IS_CLANG && LD_IS_LLD) <<
1733 select GENERIC_COMPAT_VDSO <<
1734 default y <<
1735 help 2672 help
1736 Place in the process address space !! 2673 This option must be set if a kernel might be executed on a MIPS16-
1737 ELF shared object providing fast im !! 2674 enabled CPU even if MIPS16 is not actually being used. In other
1738 and clock_gettime. !! 2675 words, it makes the kernel MIPS16-tolerant.
1739 2676
1740 You must have a 32-bit build of gli !! 2677 config CPU_SUPPORTS_MSA
1741 to seamlessly take advantage of thi !! 2678 bool
1742 2679
1743 config THUMB2_COMPAT_VDSO !! 2680 config ARCH_FLATMEM_ENABLE
1744 bool "Compile the 32-bit vDSO for Thu !! 2681 def_bool y
1745 depends on COMPAT_VDSO !! 2682 depends on !NUMA && !CPU_LOONGSON2EF
1746 default y <<
1747 help <<
1748 Compile the compat vDSO with '-mthu <<
1749 otherwise with '-marm'. <<
1750 2683
1751 config COMPAT_ALIGNMENT_FIXUPS !! 2684 config ARCH_SPARSEMEM_ENABLE
1752 bool "Fix up misaligned multi-word lo !! 2685 bool
>> 2686 select SPARSEMEM_STATIC if !SGI_IP27
1753 2687
1754 menuconfig ARMV8_DEPRECATED !! 2688 config NUMA
1755 bool "Emulate deprecated/obsolete ARM !! 2689 bool "NUMA Support"
1756 depends on SYSCTL !! 2690 depends on SYS_SUPPORTS_NUMA
1757 help 2691 help
1758 Legacy software support may require !! 2692 Say Y to compile the kernel to support NUMA (Non-Uniform Memory
1759 that have been deprecated or obsole !! 2693 Access). This option improves performance on systems with more
>> 2694 than two nodes; on two node systems it is generally better to
>> 2695 leave it disabled; on single node systems leave this option
>> 2696 disabled.
1760 2697
1761 Enable this config to enable select !! 2698 config SYS_SUPPORTS_NUMA
1762 features. !! 2699 bool
1763 2700
1764 If unsure, say Y !! 2701 config HAVE_SETUP_PER_CPU_AREA
>> 2702 def_bool y
>> 2703 depends on NUMA
1765 2704
1766 if ARMV8_DEPRECATED !! 2705 config NEED_PER_CPU_EMBED_FIRST_CHUNK
>> 2706 def_bool y
>> 2707 depends on NUMA
1767 2708
1768 config SWP_EMULATION !! 2709 config RELOCATABLE
1769 bool "Emulate SWP/SWPB instructions" !! 2710 bool "Relocatable kernel"
>> 2711 depends on SYS_SUPPORTS_RELOCATABLE && (CPU_MIPS32_R2 || CPU_MIPS64_R2 || CPU_MIPS32_R6 || CPU_MIPS64_R6 || CAVIUM_OCTEON_SOC)
1770 help 2712 help
1771 ARMv8 obsoletes the use of A32 SWP/ !! 2713 This builds a kernel image that retains relocation information
1772 they are always undefined. Say Y he !! 2714 so it can be loaded someplace besides the default 1MB.
1773 emulation of these instructions for !! 2715 The relocations make the kernel binary about 15% larger,
1774 This feature can be controlled at r !! 2716 but are discarded at runtime
1775 sysctl which is disabled by default !! 2717
1776 !! 2718 config RELOCATION_TABLE_SIZE
1777 In some older versions of glibc [<= !! 2719 hex "Relocation table size"
1778 trylock() operations with the assum !! 2720 depends on RELOCATABLE
1779 be preempted. This invalid assumpti !! 2721 range 0x0 0x01000000
1780 with SWP emulation enabled, leading !! 2722 default "0x00100000"
1781 application. !! 2723 ---help---
1782 !! 2724 A table of relocation data will be appended to the kernel binary
1783 NOTE: when accessing uncached share !! 2725 and parsed at boot to fix up the relocated kernel.
1784 on an external transaction monitori <<
1785 monitor to maintain update atomicit <<
1786 implement a global monitor, this op <<
1787 perform SWP operations to uncached <<
1788 2726
1789 If unsure, say Y !! 2727 This option allows the amount of space reserved for the table to be
>> 2728 adjusted, although the default of 1Mb should be ok in most cases.
1790 2729
1791 config CP15_BARRIER_EMULATION !! 2730 The build will fail and a valid size suggested if this is too small.
1792 bool "Emulate CP15 Barrier instructio <<
1793 help <<
1794 The CP15 barrier instructions - CP1 <<
1795 CP15DMB - are deprecated in ARMv8 ( <<
1796 strongly recommended to use the ISB <<
1797 instructions instead. <<
1798 2731
1799 Say Y here to enable software emula !! 2732 If unsure, leave at the default value.
1800 instructions for AArch32 userspace <<
1801 enabled, CP15 barrier usage is trac <<
1802 identify software that needs updati <<
1803 controlled at runtime with the abi. <<
1804 2733
1805 If unsure, say Y !! 2734 config RANDOMIZE_BASE
>> 2735 bool "Randomize the address of the kernel image"
>> 2736 depends on RELOCATABLE
>> 2737 ---help---
>> 2738 Randomizes the physical and virtual address at which the
>> 2739 kernel image is loaded, as a security feature that
>> 2740 deters exploit attempts relying on knowledge of the location
>> 2741 of kernel internals.
1806 2742
1807 config SETEND_EMULATION !! 2743 Entropy is generated using any coprocessor 0 registers available.
1808 bool "Emulate SETEND instruction" <<
1809 help <<
1810 The SETEND instruction alters the d <<
1811 AArch32 EL0, and is deprecated in A <<
1812 2744
1813 Say Y here to enable software emula !! 2745 The kernel will be offset by up to RANDOMIZE_BASE_MAX_OFFSET.
1814 for AArch32 userspace code. This fe <<
1815 at runtime with the abi.setend sysc <<
1816 2746
1817 Note: All the cpus on the system mu !! 2747 If unsure, say N.
1818 for this feature to be enabled. If <<
1819 endian - is hotplugged in after thi <<
1820 be unexpected results in the applic <<
1821 2748
1822 If unsure, say Y !! 2749 config RANDOMIZE_BASE_MAX_OFFSET
1823 endif # ARMV8_DEPRECATED !! 2750 hex "Maximum kASLR offset" if EXPERT
>> 2751 depends on RANDOMIZE_BASE
>> 2752 range 0x0 0x40000000 if EVA || 64BIT
>> 2753 range 0x0 0x08000000
>> 2754 default "0x01000000"
>> 2755 ---help---
>> 2756 When kASLR is active, this provides the maximum offset that will
>> 2757 be applied to the kernel image. It should be set according to the
>> 2758 amount of physical RAM available in the target system minus
>> 2759 PHYSICAL_START and must be a power of 2.
1824 2760
1825 endif # COMPAT !! 2761 This is limited by the size of KSEG0, 256Mb on 32-bit or 1Gb with
>> 2762 EVA or 64-bit. The default is 16Mb.
1826 2763
1827 menu "ARMv8.1 architectural features" !! 2764 config NODES_SHIFT
>> 2765 int
>> 2766 default "6"
>> 2767 depends on NEED_MULTIPLE_NODES
1828 2768
1829 config ARM64_HW_AFDBM !! 2769 config HW_PERF_EVENTS
1830 bool "Support for hardware updates of !! 2770 bool "Enable hardware performance counter support for perf events"
>> 2771 depends on PERF_EVENTS && !OPROFILE && (CPU_MIPS32 || CPU_MIPS64 || CPU_R10000 || CPU_SB1 || CPU_CAVIUM_OCTEON || CPU_XLP || CPU_LOONGSON64)
1831 default y 2772 default y
1832 help 2773 help
1833 The ARMv8.1 architecture extensions !! 2774 Enable hardware performance counter support for perf events. If
1834 hardware updates of the access and !! 2775 disabled, perf events will use software events only.
1835 table entries. When enabled in TCR_ <<
1836 capable processors, accesses to pag <<
1837 set this bit instead of raising an <<
1838 Similarly, writes to read-only page <<
1839 clear the read-only bit (AP[2]) ins <<
1840 permission fault. <<
1841 2776
1842 Kernels built with this configurati !! 2777 config DMI
1843 to work on pre-ARMv8.1 hardware and !! 2778 bool "Enable DMI scanning"
1844 minimal. If unsure, say Y. !! 2779 depends on MACH_LOONGSON64
1845 !! 2780 select DMI_SCAN_MACHINE_NON_EFI_FALLBACK
1846 config ARM64_PAN <<
1847 bool "Enable support for Privileged A <<
1848 default y 2781 default y
1849 help 2782 help
1850 Privileged Access Never (PAN; part !! 2783 Enabled scanning of DMI to identify machine quirks. Say Y
1851 prevents the kernel or hypervisor f !! 2784 here unless you have verified that your setup is not
1852 memory directly. !! 2785 affected by entries in the DMI blacklist. Required by PNP
1853 !! 2786 BIOS code.
1854 Choosing this option will cause any <<
1855 copy_to_user et al) memory access t <<
1856 2787
1857 The feature is detected at runtime, !! 2788 config SMP
1858 instruction if the cpu does not imp !! 2789 bool "Multi-Processing support"
1859 !! 2790 depends on SYS_SUPPORTS_SMP
1860 config AS_HAS_LSE_ATOMICS <<
1861 def_bool $(as-instr,.arch_extension l <<
1862 <<
1863 config ARM64_LSE_ATOMICS <<
1864 bool <<
1865 default ARM64_USE_LSE_ATOMICS <<
1866 depends on AS_HAS_LSE_ATOMICS <<
1867 <<
1868 config ARM64_USE_LSE_ATOMICS <<
1869 bool "Atomic instructions" <<
1870 default y <<
1871 help 2791 help
1872 As part of the Large System Extensi !! 2792 This enables support for systems with more than one CPU. If you have
1873 atomic instructions that are design !! 2793 a system with only one CPU, say N. If you have a system with more
1874 very large systems. !! 2794 than one CPU, say Y.
>> 2795
>> 2796 If you say N here, the kernel will run on uni- and multiprocessor
>> 2797 machines, but will use only one CPU of a multiprocessor machine. If
>> 2798 you say Y here, the kernel will run on many, but not all,
>> 2799 uniprocessor machines. On a uniprocessor machine, the kernel
>> 2800 will run faster if you say N here.
1875 2801
1876 Say Y here to make use of these ins !! 2802 People using multiprocessor machines who say Y here should also say
1877 atomic routines. This incurs a smal !! 2803 Y to "Enhanced Real Time Clock Support", below.
1878 not support these instructions and <<
1879 built with binutils >= 2.25 in orde <<
1880 to be used. <<
1881 2804
1882 endmenu # "ARMv8.1 architectural features" !! 2805 See also the SMP-HOWTO available at
>> 2806 <http://www.tldp.org/docs.html#howto>.
1883 2807
1884 menu "ARMv8.2 architectural features" !! 2808 If you don't know what to do here, say N.
1885 2809
1886 config AS_HAS_ARMV8_2 !! 2810 config HOTPLUG_CPU
1887 def_bool $(cc-option,-Wa$(comma)-marc !! 2811 bool "Support for hot-pluggable CPUs"
>> 2812 depends on SMP && SYS_SUPPORTS_HOTPLUG_CPU
>> 2813 help
>> 2814 Say Y here to allow turning CPUs off and on. CPUs can be
>> 2815 controlled through /sys/devices/system/cpu.
>> 2816 (Note: power management support will enable this option
>> 2817 automatically on SMP systems. )
>> 2818 Say N if you want to disable CPU hotplug.
1888 2819
1889 config AS_HAS_SHA3 !! 2820 config SMP_UP
1890 def_bool $(as-instr,.arch armv8.2-a+s !! 2821 bool
1891 2822
1892 config ARM64_PMEM !! 2823 config SYS_SUPPORTS_MIPS_CMP
1893 bool "Enable support for persistent m !! 2824 bool
1894 select ARCH_HAS_PMEM_API <<
1895 select ARCH_HAS_UACCESS_FLUSHCACHE <<
1896 help <<
1897 Say Y to enable support for the per <<
1898 ARMv8.2 DCPoP feature. <<
1899 2825
1900 The feature is detected at runtime, !! 2826 config SYS_SUPPORTS_MIPS_CPS
1901 operations if DC CVAP is not suppor !! 2827 bool
1902 DC CVAP itself if the system does n <<
1903 2828
1904 config ARM64_RAS_EXTN !! 2829 config SYS_SUPPORTS_SMP
1905 bool "Enable support for RAS CPU Exte !! 2830 bool
1906 default y <<
1907 help <<
1908 CPUs that support the Reliability, <<
1909 (RAS) Extensions, part of ARMv8.2 a <<
1910 errors, classify them and report th <<
1911 2831
1912 On CPUs with these extensions syste !! 2832 config NR_CPUS_DEFAULT_4
1913 barriers to determine if faults are !! 2833 bool
1914 classification from a new set of re <<
1915 2834
1916 Selecting this feature will allow t !! 2835 config NR_CPUS_DEFAULT_8
1917 and access the new registers if the !! 2836 bool
1918 Platform RAS features may additiona <<
1919 2837
1920 config ARM64_CNP !! 2838 config NR_CPUS_DEFAULT_16
1921 bool "Enable support for Common Not P !! 2839 bool
1922 default y <<
1923 depends on ARM64_PAN || !ARM64_SW_TTB <<
1924 help <<
1925 Common Not Private (CNP) allows tra <<
1926 be shared between different PEs in <<
1927 domain, so the hardware can use thi <<
1928 caching of such entries in the TLB. <<
1929 2840
1930 Selecting this option allows the CN !! 2841 config NR_CPUS_DEFAULT_32
1931 at runtime, and does not affect PEs !! 2842 bool
1932 this feature. <<
1933 2843
1934 endmenu # "ARMv8.2 architectural features" !! 2844 config NR_CPUS_DEFAULT_64
>> 2845 bool
1935 2846
1936 menu "ARMv8.3 architectural features" !! 2847 config NR_CPUS
>> 2848 int "Maximum number of CPUs (2-256)"
>> 2849 range 2 256
>> 2850 depends on SMP
>> 2851 default "4" if NR_CPUS_DEFAULT_4
>> 2852 default "8" if NR_CPUS_DEFAULT_8
>> 2853 default "16" if NR_CPUS_DEFAULT_16
>> 2854 default "32" if NR_CPUS_DEFAULT_32
>> 2855 default "64" if NR_CPUS_DEFAULT_64
>> 2856 help
>> 2857 This allows you to specify the maximum number of CPUs which this
>> 2858 kernel will support. The maximum supported value is 32 for 32-bit
>> 2859 kernel and 64 for 64-bit kernels; the minimum value which makes
>> 2860 sense is 1 for Qemu (useful only for kernel debugging purposes)
>> 2861 and 2 for all others.
>> 2862
>> 2863 This is purely to save memory - each supported CPU adds
>> 2864 approximately eight kilobytes to the kernel image. For best
>> 2865 performance should round up your number of processors to the next
>> 2866 power of two.
1937 2867
1938 config ARM64_PTR_AUTH !! 2868 config MIPS_PERF_SHARED_TC_COUNTERS
1939 bool "Enable support for pointer auth !! 2869 bool
1940 default y <<
1941 help <<
1942 Pointer authentication (part of the <<
1943 instructions for signing and authen <<
1944 keys, which can be used to mitigate <<
1945 and other attacks. <<
1946 2870
1947 This option enables these instructi !! 2871 config MIPS_NR_CPU_NR_MAP_1024
1948 Choosing this option will cause the !! 2872 bool
1949 for each process at exec() time, wi <<
1950 context-switched along with the pro <<
1951 2873
1952 The feature is detected at runtime. !! 2874 config MIPS_NR_CPU_NR_MAP
1953 hardware it will not be advertised !! 2875 int
1954 be enabled. !! 2876 depends on SMP
>> 2877 default 1024 if MIPS_NR_CPU_NR_MAP_1024
>> 2878 default NR_CPUS if !MIPS_NR_CPU_NR_MAP_1024
1955 2879
1956 If the feature is present on the bo !! 2880 #
1957 the late CPU will be parked. Also, !! 2881 # Timer Interrupt Frequency Configuration
1958 address auth and the late CPU has t !! 2882 #
1959 but with the feature disabled. On s <<
1960 not be selected. <<
1961 2883
1962 config ARM64_PTR_AUTH_KERNEL !! 2884 choice
1963 bool "Use pointer authentication for !! 2885 prompt "Timer frequency"
1964 default y !! 2886 default HZ_250
1965 depends on ARM64_PTR_AUTH <<
1966 depends on (CC_HAS_SIGN_RETURN_ADDRES <<
1967 # Modern compilers insert a .note.gnu <<
1968 # which is only understood by binutil <<
1969 depends on LD_IS_LLD || LD_VERSION >= <<
1970 depends on !CC_IS_CLANG || AS_HAS_CFI <<
1971 depends on (!FUNCTION_GRAPH_TRACER || <<
1972 help 2887 help
1973 If the compiler supports the -mbran !! 2888 Allows the configuration of the timer frequency.
1974 -msign-return-address flag (e.g. GC <<
1975 will cause the kernel itself to be <<
1976 protection. In this case, and if th <<
1977 support pointer authentication, the <<
1978 disabled with minimal loss of prote <<
1979 2889
1980 This feature works with FUNCTION_GR !! 2890 config HZ_24
1981 DYNAMIC_FTRACE_WITH_ARGS is enabled !! 2891 bool "24 HZ" if SYS_SUPPORTS_24HZ || SYS_SUPPORTS_ARBIT_HZ
1982 2892
1983 config CC_HAS_BRANCH_PROT_PAC_RET !! 2893 config HZ_48
1984 # GCC 9 or later, clang 8 or later !! 2894 bool "48 HZ" if SYS_SUPPORTS_48HZ || SYS_SUPPORTS_ARBIT_HZ
1985 def_bool $(cc-option,-mbranch-protect <<
1986 2895
1987 config CC_HAS_SIGN_RETURN_ADDRESS !! 2896 config HZ_100
1988 # GCC 7, 8 !! 2897 bool "100 HZ" if SYS_SUPPORTS_100HZ || SYS_SUPPORTS_ARBIT_HZ
1989 def_bool $(cc-option,-msign-return-ad <<
1990 2898
1991 config AS_HAS_ARMV8_3 !! 2899 config HZ_128
1992 def_bool $(cc-option,-Wa$(comma)-marc !! 2900 bool "128 HZ" if SYS_SUPPORTS_128HZ || SYS_SUPPORTS_ARBIT_HZ
1993 2901
1994 config AS_HAS_CFI_NEGATE_RA_STATE !! 2902 config HZ_250
1995 def_bool $(as-instr,.cfi_startproc\n. !! 2903 bool "250 HZ" if SYS_SUPPORTS_250HZ || SYS_SUPPORTS_ARBIT_HZ
1996 2904
1997 config AS_HAS_LDAPR !! 2905 config HZ_256
1998 def_bool $(as-instr,.arch_extension r !! 2906 bool "256 HZ" if SYS_SUPPORTS_256HZ || SYS_SUPPORTS_ARBIT_HZ
1999 2907
2000 endmenu # "ARMv8.3 architectural features" !! 2908 config HZ_1000
>> 2909 bool "1000 HZ" if SYS_SUPPORTS_1000HZ || SYS_SUPPORTS_ARBIT_HZ
2001 2910
2002 menu "ARMv8.4 architectural features" !! 2911 config HZ_1024
>> 2912 bool "1024 HZ" if SYS_SUPPORTS_1024HZ || SYS_SUPPORTS_ARBIT_HZ
2003 2913
2004 config ARM64_AMU_EXTN !! 2914 endchoice
2005 bool "Enable support for the Activity <<
2006 default y <<
2007 help <<
2008 The activity monitors extension is <<
2009 by the ARMv8.4 CPU architecture. Th <<
2010 of the activity monitors architectu <<
2011 2915
2012 To enable the use of this extension !! 2916 config SYS_SUPPORTS_24HZ
>> 2917 bool
2013 2918
2014 Note that for architectural reasons !! 2919 config SYS_SUPPORTS_48HZ
2015 support when running on CPUs that p !! 2920 bool
2016 extension. The required support is <<
2017 * Version 1.5 and later of the AR <<
2018 2921
2019 For kernels that have this configur !! 2922 config SYS_SUPPORTS_100HZ
2020 firmware, you may need to say N her !! 2923 bool
2021 Otherwise you may experience firmwa <<
2022 accessing the counter registers. Ev <<
2023 symptoms, the values returned by th <<
2024 correctly reflect reality. Most com <<
2025 indicating that the counter is not <<
2026 2924
2027 config AS_HAS_ARMV8_4 !! 2925 config SYS_SUPPORTS_128HZ
2028 def_bool $(cc-option,-Wa$(comma)-marc !! 2926 bool
2029 2927
2030 config ARM64_TLB_RANGE !! 2928 config SYS_SUPPORTS_250HZ
2031 bool "Enable support for tlbi range f !! 2929 bool
2032 default y <<
2033 depends on AS_HAS_ARMV8_4 <<
2034 help <<
2035 ARMv8.4-TLBI provides TLBI invalida <<
2036 range of input addresses. <<
2037 2930
2038 The feature introduces new assembly !! 2931 config SYS_SUPPORTS_256HZ
2039 support when binutils >= 2.30. !! 2932 bool
2040 2933
2041 endmenu # "ARMv8.4 architectural features" !! 2934 config SYS_SUPPORTS_1000HZ
>> 2935 bool
2042 2936
2043 menu "ARMv8.5 architectural features" !! 2937 config SYS_SUPPORTS_1024HZ
>> 2938 bool
2044 2939
2045 config AS_HAS_ARMV8_5 !! 2940 config SYS_SUPPORTS_ARBIT_HZ
2046 def_bool $(cc-option,-Wa$(comma)-marc !! 2941 bool
>> 2942 default y if !SYS_SUPPORTS_24HZ && \
>> 2943 !SYS_SUPPORTS_48HZ && \
>> 2944 !SYS_SUPPORTS_100HZ && \
>> 2945 !SYS_SUPPORTS_128HZ && \
>> 2946 !SYS_SUPPORTS_250HZ && \
>> 2947 !SYS_SUPPORTS_256HZ && \
>> 2948 !SYS_SUPPORTS_1000HZ && \
>> 2949 !SYS_SUPPORTS_1024HZ
2047 2950
2048 config ARM64_BTI !! 2951 config HZ
2049 bool "Branch Target Identification su !! 2952 int
2050 default y !! 2953 default 24 if HZ_24
2051 help !! 2954 default 48 if HZ_48
2052 Branch Target Identification (part !! 2955 default 100 if HZ_100
2053 provides a mechanism to limit the s !! 2956 default 128 if HZ_128
2054 branch instructions such as BR or B !! 2957 default 250 if HZ_250
>> 2958 default 256 if HZ_256
>> 2959 default 1000 if HZ_1000
>> 2960 default 1024 if HZ_1024
>> 2961
>> 2962 config SCHED_HRTICK
>> 2963 def_bool HIGH_RES_TIMERS
>> 2964
>> 2965 config KEXEC
>> 2966 bool "Kexec system call"
>> 2967 select KEXEC_CORE
>> 2968 help
>> 2969 kexec is a system call that implements the ability to shutdown your
>> 2970 current kernel, and to start another kernel. It is like a reboot
>> 2971 but it is independent of the system firmware. And like a reboot
>> 2972 you can start any kernel with it, not just Linux.
>> 2973
>> 2974 The name comes from the similarity to the exec system call.
>> 2975
>> 2976 It is an ongoing process to be certain the hardware in a machine
>> 2977 is properly shutdown, so do not be surprised if this code does not
>> 2978 initially work for you. As of this writing the exact hardware
>> 2979 interface is strongly in flux, so no good recommendation can be
>> 2980 made.
>> 2981
>> 2982 config CRASH_DUMP
>> 2983 bool "Kernel crash dumps"
>> 2984 help
>> 2985 Generate crash dump after being started by kexec.
>> 2986 This should be normally only set in special crash dump kernels
>> 2987 which are loaded in the main kernel with kexec-tools into
>> 2988 a specially reserved region and then later executed after
>> 2989 a crash by kdump/kexec. The crash dump kernel must be compiled
>> 2990 to a memory address not used by the main kernel or firmware using
>> 2991 PHYSICAL_START.
>> 2992
>> 2993 config PHYSICAL_START
>> 2994 hex "Physical address where the kernel is loaded"
>> 2995 default "0xffffffff84000000"
>> 2996 depends on CRASH_DUMP
>> 2997 help
>> 2998 This gives the CKSEG0 or KSEG0 address where the kernel is loaded.
>> 2999 If you plan to use kernel for capturing the crash dump change
>> 3000 this value to start of the reserved region (the "X" value as
>> 3001 specified in the "crashkernel=YM@XM" command line boot parameter
>> 3002 passed to the panic-ed kernel).
>> 3003
>> 3004 config SECCOMP
>> 3005 bool "Enable seccomp to safely compute untrusted bytecode"
>> 3006 depends on PROC_FS
>> 3007 default y
>> 3008 help
>> 3009 This kernel feature is useful for number crunching applications
>> 3010 that may need to compute untrusted bytecode during their
>> 3011 execution. By using pipes or other transports made available to
>> 3012 the process as file descriptors supporting the read/write
>> 3013 syscalls, it's possible to isolate those applications in
>> 3014 their own address space using seccomp. Once seccomp is
>> 3015 enabled via /proc/<pid>/seccomp, it cannot be disabled
>> 3016 and the task is only allowed to execute a few safe syscalls
>> 3017 defined by each seccomp mode.
>> 3018
>> 3019 If unsure, say Y. Only embedded should say N here.
>> 3020
>> 3021 config MIPS_O32_FP64_SUPPORT
>> 3022 bool "Support for O32 binaries using 64-bit FP" if !CPU_MIPSR6
>> 3023 depends on 32BIT || MIPS32_O32
>> 3024 help
>> 3025 When this is enabled, the kernel will support use of 64-bit floating
>> 3026 point registers with binaries using the O32 ABI along with the
>> 3027 EF_MIPS_FP64 ELF header flag (typically built with -mfp64). On
>> 3028 32-bit MIPS systems this support is at the cost of increasing the
>> 3029 size and complexity of the compiled FPU emulator. Thus if you are
>> 3030 running a MIPS32 system and know that none of your userland binaries
>> 3031 will require 64-bit floating point, you may wish to reduce the size
>> 3032 of your kernel & potentially improve FP emulation performance by
>> 3033 saying N here.
>> 3034
>> 3035 Although binutils currently supports use of this flag the details
>> 3036 concerning its effect upon the O32 ABI in userland are still being
>> 3037 worked on. In order to avoid userland becoming dependant upon current
>> 3038 behaviour before the details have been finalised, this option should
>> 3039 be considered experimental and only enabled by those working upon
>> 3040 said details.
2055 3041
2056 To make use of BTI on CPUs that sup !! 3042 If unsure, say N.
2057 3043
2058 BTI is intended to provide compleme !! 3044 config USE_OF
2059 flow integrity protection mechanism !! 3045 bool
2060 authentication mechanism provided a !! 3046 select OF
2061 For this reason, it does not make s !! 3047 select OF_EARLY_FLATTREE
2062 also enabling support for pointer a !! 3048 select IRQ_DOMAIN
2063 enabling this option you should als <<
2064 3049
2065 Userspace binaries must also be spe !! 3050 config UHI_BOOT
2066 this mechanism. If you say N here !! 3051 bool
2067 BTI, such binaries can still run, b <<
2068 enforcement of branch destinations. <<
2069 3052
2070 config ARM64_BTI_KERNEL !! 3053 config BUILTIN_DTB
2071 bool "Use Branch Target Identificatio !! 3054 bool
2072 default y <<
2073 depends on ARM64_BTI <<
2074 depends on ARM64_PTR_AUTH_KERNEL <<
2075 depends on CC_HAS_BRANCH_PROT_PAC_RET <<
2076 # https://gcc.gnu.org/bugzilla/show_b <<
2077 depends on !CC_IS_GCC || GCC_VERSION <<
2078 # https://gcc.gnu.org/bugzilla/show_b <<
2079 depends on !CC_IS_GCC <<
2080 depends on (!FUNCTION_GRAPH_TRACER || <<
2081 help <<
2082 Build the kernel with Branch Target <<
2083 and enable enforcement of this for <<
2084 is enabled and the system supports <<
2085 modular code must have BTI enabled. <<
2086 3055
2087 config CC_HAS_BRANCH_PROT_PAC_RET_BTI !! 3056 choice
2088 # GCC 9 or later, clang 8 or later !! 3057 prompt "Kernel appended dtb support" if USE_OF
2089 def_bool $(cc-option,-mbranch-protect !! 3058 default MIPS_NO_APPENDED_DTB
2090 3059
2091 config ARM64_E0PD !! 3060 config MIPS_NO_APPENDED_DTB
2092 bool "Enable support for E0PD" !! 3061 bool "None"
2093 default y !! 3062 help
2094 help !! 3063 Do not enable appended dtb support.
2095 E0PD (part of the ARMv8.5 extension !! 3064
2096 that EL0 accesses made via TTBR1 al !! 3065 config MIPS_ELF_APPENDED_DTB
2097 providing similar benefits to KASLR !! 3066 bool "vmlinux"
2098 with lower overhead and without dis !! 3067 help
2099 kernel memory such as SPE. !! 3068 With this option, the boot code will look for a device tree binary
>> 3069 DTB) included in the vmlinux ELF section .appended_dtb. By default
>> 3070 it is empty and the DTB can be appended using binutils command
>> 3071 objcopy:
>> 3072
>> 3073 objcopy --update-section .appended_dtb=<filename>.dtb vmlinux
>> 3074
>> 3075 This is meant as a backward compatiblity convenience for those
>> 3076 systems with a bootloader that can't be upgraded to accommodate
>> 3077 the documented boot protocol using a device tree.
>> 3078
>> 3079 config MIPS_RAW_APPENDED_DTB
>> 3080 bool "vmlinux.bin or vmlinuz.bin"
>> 3081 help
>> 3082 With this option, the boot code will look for a device tree binary
>> 3083 DTB) appended to raw vmlinux.bin or vmlinuz.bin.
>> 3084 (e.g. cat vmlinux.bin <filename>.dtb > vmlinux_w_dtb).
>> 3085
>> 3086 This is meant as a backward compatibility convenience for those
>> 3087 systems with a bootloader that can't be upgraded to accommodate
>> 3088 the documented boot protocol using a device tree.
>> 3089
>> 3090 Beware that there is very little in terms of protection against
>> 3091 this option being confused by leftover garbage in memory that might
>> 3092 look like a DTB header after a reboot if no actual DTB is appended
>> 3093 to vmlinux.bin. Do not leave this option active in a production kernel
>> 3094 if you don't intend to always append a DTB.
>> 3095 endchoice
2100 3096
2101 This option enables E0PD for TTBR1 !! 3097 choice
>> 3098 prompt "Kernel command line type" if !CMDLINE_OVERRIDE
>> 3099 default MIPS_CMDLINE_FROM_DTB if USE_OF && !ATH79 && !MACH_INGENIC && \
>> 3100 !MACH_LOONGSON64 && !MIPS_MALTA && \
>> 3101 !CAVIUM_OCTEON_SOC
>> 3102 default MIPS_CMDLINE_FROM_BOOTLOADER
>> 3103
>> 3104 config MIPS_CMDLINE_FROM_DTB
>> 3105 depends on USE_OF
>> 3106 bool "Dtb kernel arguments if available"
>> 3107
>> 3108 config MIPS_CMDLINE_DTB_EXTEND
>> 3109 depends on USE_OF
>> 3110 bool "Extend dtb kernel arguments with bootloader arguments"
>> 3111
>> 3112 config MIPS_CMDLINE_FROM_BOOTLOADER
>> 3113 bool "Bootloader kernel arguments if available"
>> 3114
>> 3115 config MIPS_CMDLINE_BUILTIN_EXTEND
>> 3116 depends on CMDLINE_BOOL
>> 3117 bool "Extend builtin kernel arguments with bootloader arguments"
>> 3118 endchoice
2102 3119
2103 config ARM64_AS_HAS_MTE !! 3120 endmenu
2104 # Initial support for MTE went in bin <<
2105 # ".arch armv8.5-a+memtag" below. How <<
2106 # as a late addition to the final arc <<
2107 # is only supported in the newer 2.32 <<
2108 # versions, hence the extra "stgm" in <<
2109 def_bool $(as-instr,.arch armv8.5-a+m <<
2110 3121
2111 config ARM64_MTE !! 3122 config LOCKDEP_SUPPORT
2112 bool "Memory Tagging Extension suppor !! 3123 bool
2113 default y 3124 default y
2114 depends on ARM64_AS_HAS_MTE && ARM64_ <<
2115 depends on AS_HAS_ARMV8_5 <<
2116 depends on AS_HAS_LSE_ATOMICS <<
2117 # Required for tag checking in the ua <<
2118 depends on ARM64_PAN <<
2119 select ARCH_HAS_SUBPAGE_FAULTS <<
2120 select ARCH_USES_HIGH_VMA_FLAGS <<
2121 select ARCH_USES_PG_ARCH_2 <<
2122 select ARCH_USES_PG_ARCH_3 <<
2123 help <<
2124 Memory Tagging (part of the ARMv8.5 <<
2125 architectural support for run-time, <<
2126 various classes of memory error to <<
2127 to eliminate vulnerabilities arisin <<
2128 languages. <<
2129 <<
2130 This option enables the support for <<
2131 Extension at EL0 (i.e. for userspac <<
2132 <<
2133 Selecting this option allows the fe <<
2134 runtime. Any secondary CPU not impl <<
2135 not be allowed a late bring-up. <<
2136 <<
2137 Userspace binaries that want to use <<
2138 explicitly opt in. The mechanism fo <<
2139 described in: <<
2140 <<
2141 Documentation/arch/arm64/memory-tag <<
2142 3125
2143 endmenu # "ARMv8.5 architectural features" !! 3126 config STACKTRACE_SUPPORT
2144 !! 3127 bool
2145 menu "ARMv8.7 architectural features" <<
2146 <<
2147 config ARM64_EPAN <<
2148 bool "Enable support for Enhanced Pri <<
2149 default y 3128 default y
2150 depends on ARM64_PAN <<
2151 help <<
2152 Enhanced Privileged Access Never (E <<
2153 Access Never to be used with Execut <<
2154 3129
2155 The feature is detected at runtime, !! 3130 config PGTABLE_LEVELS
2156 if the cpu does not implement the f <<
2157 endmenu # "ARMv8.7 architectural features" <<
2158 <<
2159 menu "ARMv8.9 architectural features" <<
2160 <<
2161 config ARM64_POE <<
2162 prompt "Permission Overlay Extension" <<
2163 def_bool y <<
2164 select ARCH_USES_HIGH_VMA_FLAGS <<
2165 select ARCH_HAS_PKEYS <<
2166 help <<
2167 The Permission Overlay Extension is <<
2168 Protection Keys. Memory Protection <<
2169 enforcing page-based protections, b <<
2170 of the page tables when an applicat <<
2171 <<
2172 For details, see Documentation/core <<
2173 <<
2174 If unsure, say y. <<
2175 <<
2176 config ARCH_PKEY_BITS <<
2177 int 3131 int
2178 default 3 !! 3132 default 4 if PAGE_SIZE_4KB && MIPS_VA_BITS_48
>> 3133 default 3 if 64BIT && !PAGE_SIZE_64KB
>> 3134 default 2
2179 3135
2180 endmenu # "ARMv8.9 architectural features" !! 3136 config MIPS_AUTO_PFN_OFFSET
2181 !! 3137 bool
2182 config ARM64_SVE <<
2183 bool "ARM Scalable Vector Extension s <<
2184 default y <<
2185 help <<
2186 The Scalable Vector Extension (SVE) <<
2187 execution state which complements a <<
2188 of the base architecture to support <<
2189 additional vectorisation opportunit <<
2190 <<
2191 To enable use of this extension on <<
2192 3138
2193 On CPUs that support the SVE2 exten !! 3139 menu "Bus options (PCI, PCMCIA, EISA, ISA, TC)"
2194 those too. <<
2195 3140
2196 Note that for architectural reasons !! 3141 config PCI_DRIVERS_GENERIC
2197 support when running on SVE capable !! 3142 select PCI_DOMAINS_GENERIC if PCI
2198 is present in: !! 3143 bool
2199 3144
2200 * version 1.5 and later of the AR !! 3145 config PCI_DRIVERS_LEGACY
2201 * the AArch64 boot wrapper since !! 3146 def_bool !PCI_DRIVERS_GENERIC
2202 ("bootwrapper: SVE: Enable SVE !! 3147 select NO_GENERIC_PCI_IOPORT_MAP
>> 3148 select PCI_DOMAINS if PCI
2203 3149
2204 For other firmware implementations, !! 3150 #
2205 or vendor. !! 3151 # ISA support is now enabled via select. Too many systems still have the one
>> 3152 # or other ISA chip on the board that users don't know about so don't expect
>> 3153 # users to choose the right thing ...
>> 3154 #
>> 3155 config ISA
>> 3156 bool
2206 3157
2207 If you need the kernel to boot on S !! 3158 config TC
2208 firmware, you may need to say N her !! 3159 bool "TURBOchannel support"
2209 fixed. Otherwise, you may experien !! 3160 depends on MACH_DECSTATION
2210 booting the kernel. If unsure and !! 3161 help
2211 symptoms, you should assume that it !! 3162 TURBOchannel is a DEC (now Compaq (now HP)) bus for Alpha and MIPS
>> 3163 processors. TURBOchannel programming specifications are available
>> 3164 at:
>> 3165 <ftp://ftp.hp.com/pub/alphaserver/archive/triadd/>
>> 3166 and:
>> 3167 <http://www.computer-refuge.org/classiccmp/ftp.digital.com/pub/DEC/TriAdd/>
>> 3168 Linux driver support status is documented at:
>> 3169 <http://www.linux-mips.org/wiki/DECstation>
2212 3170
2213 config ARM64_SME !! 3171 config MMU
2214 bool "ARM Scalable Matrix Extension s !! 3172 bool
2215 default y 3173 default y
2216 depends on ARM64_SVE <<
2217 depends on BROKEN <<
2218 help <<
2219 The Scalable Matrix Extension (SME) <<
2220 execution state which utilises a su <<
2221 instruction set, together with the <<
2222 register state capable of holding t <<
2223 enable various matrix operations. <<
2224 3174
2225 config ARM64_PSEUDO_NMI !! 3175 config ARCH_MMAP_RND_BITS_MIN
2226 bool "Support for NMI-like interrupts !! 3176 default 12 if 64BIT
2227 select ARM_GIC_V3 !! 3177 default 8
2228 help <<
2229 Adds support for mimicking Non-Mask <<
2230 GIC interrupt priority. This suppor <<
2231 ARM GIC. <<
2232 <<
2233 This high priority configuration fo <<
2234 explicitly enabled by setting the k <<
2235 "irqchip.gicv3_pseudo_nmi" to 1. <<
2236 <<
2237 If unsure, say N <<
2238 <<
2239 if ARM64_PSEUDO_NMI <<
2240 config ARM64_DEBUG_PRIORITY_MASKING <<
2241 bool "Debug interrupt priority maskin <<
2242 help <<
2243 This adds runtime checks to functio <<
2244 interrupts when using priority mask <<
2245 the validity of ICC_PMR_EL1 when ca <<
2246 3178
2247 If unsure, say N !! 3179 config ARCH_MMAP_RND_BITS_MAX
2248 endif # ARM64_PSEUDO_NMI !! 3180 default 18 if 64BIT
>> 3181 default 15
2249 3182
2250 config RELOCATABLE !! 3183 config ARCH_MMAP_RND_COMPAT_BITS_MIN
2251 bool "Build a relocatable kernel imag !! 3184 default 8
2252 select ARCH_HAS_RELR <<
2253 default y <<
2254 help <<
2255 This builds the kernel as a Positio <<
2256 which retains all relocation metada <<
2257 kernel binary at runtime to a diffe <<
2258 address it was linked at. <<
2259 Since AArch64 uses the RELA relocat <<
2260 relocation pass at runtime even if <<
2261 same address it was linked at. <<
2262 3185
2263 config RANDOMIZE_BASE !! 3186 config ARCH_MMAP_RND_COMPAT_BITS_MAX
2264 bool "Randomize the address of the ke !! 3187 default 15
2265 select RELOCATABLE <<
2266 help <<
2267 Randomizes the virtual address at w <<
2268 loaded, as a security feature that <<
2269 relying on knowledge of the locatio <<
2270 <<
2271 It is the bootloader's job to provi <<
2272 random u64 value in /chosen/kaslr-s <<
2273 <<
2274 When booting via the UEFI stub, it <<
2275 EFI_RNG_PROTOCOL implementation (if <<
2276 to the kernel proper. In addition, <<
2277 location of the kernel Image as wel <<
2278 3188
2279 If unsure, say N. !! 3189 config I8253
>> 3190 bool
>> 3191 select CLKSRC_I8253
>> 3192 select CLKEVT_I8253
>> 3193 select MIPS_EXTERNAL_TIMER
2280 3194
2281 config RANDOMIZE_MODULE_REGION_FULL !! 3195 config ZONE_DMA
2282 bool "Randomize the module region ove !! 3196 bool
2283 depends on RANDOMIZE_BASE <<
2284 default y <<
2285 help <<
2286 Randomizes the location of the modu <<
2287 covering the core kernel. This way, <<
2288 to leak information about the locat <<
2289 but it does imply that function cal <<
2290 kernel will need to be resolved via <<
2291 <<
2292 When this option is not set, the mo <<
2293 a limited range that contains the [ <<
2294 core kernel, so branch relocations <<
2295 the region is exhausted. In this pa <<
2296 exhaustion, modules might be able t <<
2297 3197
2298 config CC_HAVE_STACKPROTECTOR_SYSREG !! 3198 config ZONE_DMA32
2299 def_bool $(cc-option,-mstack-protecto !! 3199 bool
2300 3200
2301 config STACKPROTECTOR_PER_TASK !! 3201 endmenu
2302 def_bool y <<
2303 depends on STACKPROTECTOR && CC_HAVE_ <<
2304 3202
2305 config UNWIND_PATCH_PAC_INTO_SCS !! 3203 config TRAD_SIGNALS
2306 bool "Enable shadow call stack dynami !! 3204 bool
2307 # needs Clang with https://github.com <<
2308 depends on CC_IS_CLANG && CLANG_VERSI <<
2309 depends on ARM64_PTR_AUTH_KERNEL && C <<
2310 depends on SHADOW_CALL_STACK <<
2311 select UNWIND_TABLES <<
2312 select DYNAMIC_SCS <<
2313 <<
2314 config ARM64_CONTPTE <<
2315 bool "Contiguous PTE mappings for use <<
2316 depends on TRANSPARENT_HUGEPAGE <<
2317 default y <<
2318 help <<
2319 When enabled, user mappings are con <<
2320 bit, for any mappings that meet the <<
2321 This reduces TLB pressure and impro <<
2322 <<
2323 endmenu # "Kernel Features" <<
2324 <<
2325 menu "Boot options" <<
2326 <<
2327 config ARM64_ACPI_PARKING_PROTOCOL <<
2328 bool "Enable support for the ARM64 AC <<
2329 depends on ACPI <<
2330 help <<
2331 Enable support for the ARM64 ACPI p <<
2332 the kernel will not allow booting t <<
2333 protocol even if the corresponding <<
2334 MADT table. <<
2335 <<
2336 config CMDLINE <<
2337 string "Default kernel command string <<
2338 default "" <<
2339 help <<
2340 Provide a set of default command-li <<
2341 entering them here. As a minimum, y <<
2342 root device (e.g. root=/dev/nfs). <<
2343 3205
2344 choice !! 3206 config MIPS32_COMPAT
2345 prompt "Kernel command line type" !! 3207 bool
2346 depends on CMDLINE != "" <<
2347 default CMDLINE_FROM_BOOTLOADER <<
2348 help <<
2349 Choose how the kernel will handle t <<
2350 command line string. <<
2351 <<
2352 config CMDLINE_FROM_BOOTLOADER <<
2353 bool "Use bootloader kernel arguments <<
2354 help <<
2355 Uses the command-line options passe <<
2356 the boot loader doesn't provide any <<
2357 string provided in CMDLINE will be <<
2358 <<
2359 config CMDLINE_FORCE <<
2360 bool "Always use the default kernel c <<
2361 help <<
2362 Always use the default kernel comma <<
2363 loader passes other arguments to th <<
2364 This is useful if you cannot or don <<
2365 command-line options your boot load <<
2366 3208
2367 endchoice !! 3209 config COMPAT
>> 3210 bool
2368 3211
2369 config EFI_STUB !! 3212 config SYSVIPC_COMPAT
2370 bool 3213 bool
2371 3214
2372 config EFI !! 3215 config MIPS32_O32
2373 bool "UEFI runtime support" !! 3216 bool "Kernel support for o32 binaries"
2374 depends on OF && !CPU_BIG_ENDIAN !! 3217 depends on 64BIT
2375 depends on KERNEL_MODE_NEON !! 3218 select ARCH_WANT_OLD_COMPAT_IPC
2376 select ARCH_SUPPORTS_ACPI !! 3219 select COMPAT
2377 select LIBFDT !! 3220 select MIPS32_COMPAT
2378 select UCS2_STRING !! 3221 select SYSVIPC_COMPAT if SYSVIPC
2379 select EFI_PARAMS_FROM_FDT !! 3222 help
2380 select EFI_RUNTIME_WRAPPERS !! 3223 Select this option if you want to run o32 binaries. These are pure
2381 select EFI_STUB !! 3224 32-bit binaries as used by the 32-bit Linux/MIPS port. Most of
2382 select EFI_GENERIC_STUB !! 3225 existing binaries are in this format.
2383 imply IMA_SECURE_AND_OR_TRUSTED_BOOT <<
2384 default y <<
2385 help <<
2386 This option provides support for ru <<
2387 by UEFI firmware (such as non-volat <<
2388 clock, and platform reset). A UEFI <<
2389 allow the kernel to be booted as an <<
2390 is only useful on systems that have <<
2391 <<
2392 config COMPRESSED_INSTALL <<
2393 bool "Install compressed image by def <<
2394 help <<
2395 This makes the regular "make instal <<
2396 image we built, not the legacy unco <<
2397 <<
2398 You can check that a compressed ima <<
2399 "make zinstall" first, and verifyin <<
2400 in your environment before making " <<
2401 you. <<
2402 3226
2403 config DMI !! 3227 If unsure, say Y.
2404 bool "Enable support for SMBIOS (DMI) <<
2405 depends on EFI <<
2406 default y <<
2407 help <<
2408 This enables SMBIOS/DMI feature for <<
2409 3228
2410 This option is only useful on syste !! 3229 config MIPS32_N32
2411 However, even with this option, the !! 3230 bool "Kernel support for n32 binaries"
2412 continue to boot on existing non-UE !! 3231 depends on 64BIT
>> 3232 select ARCH_WANT_COMPAT_IPC_PARSE_VERSION
>> 3233 select COMPAT
>> 3234 select MIPS32_COMPAT
>> 3235 select SYSVIPC_COMPAT if SYSVIPC
>> 3236 help
>> 3237 Select this option if you want to run n32 binaries. These are
>> 3238 64-bit binaries using 32-bit quantities for addressing and certain
>> 3239 data that would normally be 64-bit. They are used in special
>> 3240 cases.
2413 3241
2414 endmenu # "Boot options" !! 3242 If unsure, say N.
2415 3243
2416 menu "Power management options" !! 3244 config BINFMT_ELF32
>> 3245 bool
>> 3246 default y if MIPS32_O32 || MIPS32_N32
>> 3247 select ELFCORE
2417 3248
2418 source "kernel/power/Kconfig" !! 3249 menu "Power management options"
2419 3250
2420 config ARCH_HIBERNATION_POSSIBLE 3251 config ARCH_HIBERNATION_POSSIBLE
2421 def_bool y 3252 def_bool y
2422 depends on CPU_PM !! 3253 depends on SYS_SUPPORTS_HOTPLUG_CPU || !SMP
2423 <<
2424 config ARCH_HIBERNATION_HEADER <<
2425 def_bool y <<
2426 depends on HIBERNATION <<
2427 3254
2428 config ARCH_SUSPEND_POSSIBLE 3255 config ARCH_SUSPEND_POSSIBLE
2429 def_bool y 3256 def_bool y
>> 3257 depends on SYS_SUPPORTS_HOTPLUG_CPU || !SMP
2430 3258
2431 endmenu # "Power management options" !! 3259 source "kernel/power/Kconfig"
2432 3260
2433 menu "CPU Power Management" !! 3261 endmenu
2434 3262
2435 source "drivers/cpuidle/Kconfig" !! 3263 config MIPS_EXTERNAL_TIMER
>> 3264 bool
2436 3265
>> 3266 menu "CPU Power Management"
>> 3267
>> 3268 if CPU_SUPPORTS_CPUFREQ && MIPS_EXTERNAL_TIMER
2437 source "drivers/cpufreq/Kconfig" 3269 source "drivers/cpufreq/Kconfig"
>> 3270 endif
2438 3271
2439 endmenu # "CPU Power Management" !! 3272 source "drivers/cpuidle/Kconfig"
2440 3273
2441 source "drivers/acpi/Kconfig" !! 3274 endmenu
2442 3275
2443 source "arch/arm64/kvm/Kconfig" !! 3276 source "drivers/firmware/Kconfig"
2444 3277
>> 3278 source "arch/mips/kvm/Kconfig"
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