1 # SPDX-License-Identifier: GPL-2.0-only !! 1 # SPDX-License-Identifier: GPL-2.0
2 config ARM64 !! 2 config MIPS
3 def_bool y !! 3 bool
4 select ACPI_APMT if ACPI !! 4 default y
5 select ACPI_CCA_REQUIRED if ACPI !! 5 select ARCH_32BIT_OFF_T if !64BIT
6 select ACPI_GENERIC_GSI if ACPI !! 6 select ARCH_BINFMT_ELF_STATE if MIPS_FP_SUPPORT
7 select ACPI_GTDT if ACPI !! 7 select ARCH_HAS_CURRENT_STACK_POINTER if !CC_IS_CLANG || CLANG_VERSION >= 140000
8 select ACPI_HOTPLUG_CPU if ACPI_PROCES !! 8 select ARCH_HAS_DEBUG_VIRTUAL if !64BIT
9 select ACPI_IORT if ACPI <<
10 select ACPI_REDUCED_HARDWARE_ONLY if A <<
11 select ACPI_MCFG if (ACPI && PCI) <<
12 select ACPI_SPCR_TABLE if ACPI <<
13 select ACPI_PPTT if ACPI <<
14 select ARCH_HAS_DEBUG_WX <<
15 select ARCH_BINFMT_ELF_EXTRA_PHDRS <<
16 select ARCH_BINFMT_ELF_STATE <<
17 select ARCH_CORRECT_STACKTRACE_ON_KRET <<
18 select ARCH_ENABLE_HUGEPAGE_MIGRATION <<
19 select ARCH_ENABLE_MEMORY_HOTPLUG <<
20 select ARCH_ENABLE_MEMORY_HOTREMOVE <<
21 select ARCH_ENABLE_SPLIT_PMD_PTLOCK if <<
22 select ARCH_ENABLE_THP_MIGRATION if TR <<
23 select ARCH_HAS_CACHE_LINE_SIZE <<
24 select ARCH_HAS_CURRENT_STACK_POINTER <<
25 select ARCH_HAS_DEBUG_VIRTUAL <<
26 select ARCH_HAS_DEBUG_VM_PGTABLE <<
27 select ARCH_HAS_DMA_OPS if XEN <<
28 select ARCH_HAS_DMA_PREP_COHERENT <<
29 select ARCH_HAS_ACPI_TABLE_UPGRADE if <<
30 select ARCH_HAS_FAST_MULTIPLIER <<
31 select ARCH_HAS_FORTIFY_SOURCE 9 select ARCH_HAS_FORTIFY_SOURCE
32 select ARCH_HAS_GCOV_PROFILE_ALL <<
33 select ARCH_HAS_GIGANTIC_PAGE <<
34 select ARCH_HAS_KCOV 10 select ARCH_HAS_KCOV
35 select ARCH_HAS_KERNEL_FPU_SUPPORT if !! 11 select ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE if !EVA
36 select ARCH_HAS_KEEPINITRD !! 12 select ARCH_HAS_PTE_SPECIAL if !(32BIT && CPU_HAS_RIXI)
37 select ARCH_HAS_MEMBARRIER_SYNC_CORE !! 13 select ARCH_HAS_STRNCPY_FROM_USER
38 select ARCH_HAS_MEM_ENCRYPT !! 14 select ARCH_HAS_STRNLEN_USER
39 select ARCH_HAS_NMI_SAFE_THIS_CPU_OPS <<
40 select ARCH_HAS_NON_OVERLAPPING_ADDRES <<
41 select ARCH_HAS_PTE_DEVMAP <<
42 select ARCH_HAS_PTE_SPECIAL <<
43 select ARCH_HAS_HW_PTE_YOUNG <<
44 select ARCH_HAS_SETUP_DMA_OPS <<
45 select ARCH_HAS_SET_DIRECT_MAP <<
46 select ARCH_HAS_SET_MEMORY <<
47 select ARCH_STACKWALK <<
48 select ARCH_HAS_STRICT_KERNEL_RWX <<
49 select ARCH_HAS_STRICT_MODULE_RWX <<
50 select ARCH_HAS_SYNC_DMA_FOR_DEVICE <<
51 select ARCH_HAS_SYNC_DMA_FOR_CPU <<
52 select ARCH_HAS_SYSCALL_WRAPPER <<
53 select ARCH_HAS_TICK_BROADCAST if GENE 15 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
54 select ARCH_HAS_ZONE_DMA_SET if EXPERT !! 16 select ARCH_HAS_UBSAN_SANITIZE_ALL
55 select ARCH_HAVE_ELF_PROT !! 17 select ARCH_HAS_GCOV_PROFILE_ALL
56 select ARCH_HAVE_NMI_SAFE_CMPXCHG <<
57 select ARCH_HAVE_TRACE_MMIO_ACCESS <<
58 select ARCH_INLINE_READ_LOCK if !PREEM <<
59 select ARCH_INLINE_READ_LOCK_BH if !PR <<
60 select ARCH_INLINE_READ_LOCK_IRQ if !P <<
61 select ARCH_INLINE_READ_LOCK_IRQSAVE i <<
62 select ARCH_INLINE_READ_UNLOCK if !PRE <<
63 select ARCH_INLINE_READ_UNLOCK_BH if ! <<
64 select ARCH_INLINE_READ_UNLOCK_IRQ if <<
65 select ARCH_INLINE_READ_UNLOCK_IRQREST <<
66 select ARCH_INLINE_WRITE_LOCK if !PREE <<
67 select ARCH_INLINE_WRITE_LOCK_BH if !P <<
68 select ARCH_INLINE_WRITE_LOCK_IRQ if ! <<
69 select ARCH_INLINE_WRITE_LOCK_IRQSAVE <<
70 select ARCH_INLINE_WRITE_UNLOCK if !PR <<
71 select ARCH_INLINE_WRITE_UNLOCK_BH if <<
72 select ARCH_INLINE_WRITE_UNLOCK_IRQ if <<
73 select ARCH_INLINE_WRITE_UNLOCK_IRQRES <<
74 select ARCH_INLINE_SPIN_TRYLOCK if !PR <<
75 select ARCH_INLINE_SPIN_TRYLOCK_BH if <<
76 select ARCH_INLINE_SPIN_LOCK if !PREEM <<
77 select ARCH_INLINE_SPIN_LOCK_BH if !PR <<
78 select ARCH_INLINE_SPIN_LOCK_IRQ if !P <<
79 select ARCH_INLINE_SPIN_LOCK_IRQSAVE i <<
80 select ARCH_INLINE_SPIN_UNLOCK if !PRE <<
81 select ARCH_INLINE_SPIN_UNLOCK_BH if ! <<
82 select ARCH_INLINE_SPIN_UNLOCK_IRQ if <<
83 select ARCH_INLINE_SPIN_UNLOCK_IRQREST <<
84 select ARCH_KEEP_MEMBLOCK 18 select ARCH_KEEP_MEMBLOCK
85 select ARCH_MHP_MEMMAP_ON_MEMORY_ENABL !! 19 select ARCH_SUPPORTS_UPROBES
86 select ARCH_USE_CMPXCHG_LOCKREF !! 20 select ARCH_USE_BUILTIN_BSWAP
87 select ARCH_USE_GNU_PROPERTY !! 21 select ARCH_USE_CMPXCHG_LOCKREF if 64BIT
88 select ARCH_USE_MEMTEST 22 select ARCH_USE_MEMTEST
89 select ARCH_USE_QUEUED_RWLOCKS 23 select ARCH_USE_QUEUED_RWLOCKS
90 select ARCH_USE_QUEUED_SPINLOCKS 24 select ARCH_USE_QUEUED_SPINLOCKS
91 select ARCH_USE_SYM_ANNOTATIONS !! 25 select ARCH_SUPPORTS_HUGETLBFS if CPU_SUPPORTS_HUGEPAGES
92 select ARCH_SUPPORTS_DEBUG_PAGEALLOC !! 26 select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT if MMU
93 select ARCH_SUPPORTS_HUGETLBFS !! 27 select ARCH_WANT_IPC_PARSE_VERSION
94 select ARCH_SUPPORTS_MEMORY_FAILURE <<
95 select ARCH_SUPPORTS_SHADOW_CALL_STACK <<
96 select ARCH_SUPPORTS_LTO_CLANG if CPU_ <<
97 select ARCH_SUPPORTS_LTO_CLANG_THIN <<
98 select ARCH_SUPPORTS_CFI_CLANG <<
99 select ARCH_SUPPORTS_ATOMIC_RMW <<
100 select ARCH_SUPPORTS_INT128 if CC_HAS_ <<
101 select ARCH_SUPPORTS_NUMA_BALANCING <<
102 select ARCH_SUPPORTS_PAGE_TABLE_CHECK <<
103 select ARCH_SUPPORTS_PER_VMA_LOCK <<
104 select ARCH_SUPPORTS_HUGE_PFNMAP if TR <<
105 select ARCH_SUPPORTS_RT <<
106 select ARCH_WANT_BATCHED_UNMAP_TLB_FLU <<
107 select ARCH_WANT_COMPAT_IPC_PARSE_VERS <<
108 select ARCH_WANT_DEFAULT_BPF_JIT <<
109 select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_ <<
110 select ARCH_WANT_FRAME_POINTERS <<
111 select ARCH_WANT_HUGE_PMD_SHARE if ARM <<
112 select ARCH_WANT_LD_ORPHAN_WARN 28 select ARCH_WANT_LD_ORPHAN_WARN
113 select ARCH_WANTS_EXECMEM_LATE if EXEC <<
114 select ARCH_WANTS_NO_INSTR <<
115 select ARCH_WANTS_THP_SWAP if ARM64_4K <<
116 select ARCH_HAS_UBSAN <<
117 select ARM_AMBA <<
118 select ARM_ARCH_TIMER <<
119 select ARM_GIC <<
120 select AUDIT_ARCH_COMPAT_GENERIC <<
121 select ARM_GIC_V2M if PCI <<
122 select ARM_GIC_V3 <<
123 select ARM_GIC_V3_ITS if PCI <<
124 select ARM_PSCI_FW <<
125 select BUILDTIME_TABLE_SORT 29 select BUILDTIME_TABLE_SORT
126 select CLONE_BACKWARDS 30 select CLONE_BACKWARDS
127 select COMMON_CLK !! 31 select CPU_NO_EFFICIENT_FFS if (TARGET_ISA_REV < 1)
128 select CPU_PM if (SUSPEND || CPU_IDLE) !! 32 select CPU_PM if CPU_IDLE
129 select CPUMASK_OFFSTACK if NR_CPUS > 2 !! 33 select GENERIC_ATOMIC64 if !64BIT
130 select CRC32 !! 34 select GENERIC_CMOS_UPDATE
131 select DCACHE_WORD_ACCESS <<
132 select DYNAMIC_FTRACE if FUNCTION_TRAC <<
133 select DMA_BOUNCE_UNALIGNED_KMALLOC <<
134 select DMA_DIRECT_REMAP <<
135 select EDAC_SUPPORT <<
136 select FRAME_POINTER <<
137 select FUNCTION_ALIGNMENT_4B <<
138 select FUNCTION_ALIGNMENT_8B if DYNAMI <<
139 select GENERIC_ALLOCATOR <<
140 select GENERIC_ARCH_TOPOLOGY <<
141 select GENERIC_CLOCKEVENTS_BROADCAST <<
142 select GENERIC_CPU_AUTOPROBE 35 select GENERIC_CPU_AUTOPROBE
143 select GENERIC_CPU_DEVICES !! 36 select GENERIC_GETTIMEOFDAY
144 select GENERIC_CPU_VULNERABILITIES !! 37 select GENERIC_IOMAP
145 select GENERIC_EARLY_IOREMAP <<
146 select GENERIC_IDLE_POLL_SETUP <<
147 select GENERIC_IOREMAP <<
148 select GENERIC_IRQ_IPI <<
149 select GENERIC_IRQ_PROBE 38 select GENERIC_IRQ_PROBE
150 select GENERIC_IRQ_SHOW 39 select GENERIC_IRQ_SHOW
151 select GENERIC_IRQ_SHOW_LEVEL !! 40 select GENERIC_ISA_DMA if EISA
152 select GENERIC_LIB_DEVMEM_IS_ALLOWED !! 41 select GENERIC_LIB_ASHLDI3
153 select GENERIC_PCI_IOMAP !! 42 select GENERIC_LIB_ASHRDI3
154 select GENERIC_PTDUMP !! 43 select GENERIC_LIB_CMPDI2
155 select GENERIC_SCHED_CLOCK !! 44 select GENERIC_LIB_LSHRDI3
>> 45 select GENERIC_LIB_UCMPDI2
>> 46 select GENERIC_SCHED_CLOCK if !CAVIUM_OCTEON_SOC
156 select GENERIC_SMP_IDLE_THREAD 47 select GENERIC_SMP_IDLE_THREAD
157 select GENERIC_TIME_VSYSCALL 48 select GENERIC_TIME_VSYSCALL
158 select GENERIC_GETTIMEOFDAY !! 49 select GUP_GET_PTE_LOW_HIGH if CPU_MIPS32 && PHYS_ADDR_T_64BIT
159 select GENERIC_VDSO_TIME_NS <<
160 select HARDIRQS_SW_RESEND <<
161 select HAS_IOPORT <<
162 select HAVE_MOVE_PMD <<
163 select HAVE_MOVE_PUD <<
164 select HAVE_PCI <<
165 select HAVE_ACPI_APEI if (ACPI && EFI) <<
166 select HAVE_ALIGNED_STRUCT_PAGE <<
167 select HAVE_ARCH_AUDITSYSCALL <<
168 select HAVE_ARCH_BITREVERSE <<
169 select HAVE_ARCH_COMPILER_H 50 select HAVE_ARCH_COMPILER_H
170 select HAVE_ARCH_HUGE_VMALLOC <<
171 select HAVE_ARCH_HUGE_VMAP <<
172 select HAVE_ARCH_JUMP_LABEL 51 select HAVE_ARCH_JUMP_LABEL
173 select HAVE_ARCH_JUMP_LABEL_RELATIVE !! 52 select HAVE_ARCH_KGDB if MIPS_FP_SUPPORT
174 select HAVE_ARCH_KASAN !! 53 select HAVE_ARCH_MMAP_RND_BITS if MMU
175 select HAVE_ARCH_KASAN_VMALLOC !! 54 select HAVE_ARCH_MMAP_RND_COMPAT_BITS if MMU && COMPAT
176 select HAVE_ARCH_KASAN_SW_TAGS <<
177 select HAVE_ARCH_KASAN_HW_TAGS if ARM6 <<
178 # Some instrumentation may be unsound, <<
179 select HAVE_ARCH_KCSAN if EXPERT <<
180 select HAVE_ARCH_KFENCE <<
181 select HAVE_ARCH_KGDB <<
182 select HAVE_ARCH_MMAP_RND_BITS <<
183 select HAVE_ARCH_MMAP_RND_COMPAT_BITS <<
184 select HAVE_ARCH_PREL32_RELOCATIONS <<
185 select HAVE_ARCH_RANDOMIZE_KSTACK_OFFS <<
186 select HAVE_ARCH_SECCOMP_FILTER 55 select HAVE_ARCH_SECCOMP_FILTER
187 select HAVE_ARCH_STACKLEAK <<
188 select HAVE_ARCH_THREAD_STRUCT_WHITELI <<
189 select HAVE_ARCH_TRACEHOOK 56 select HAVE_ARCH_TRACEHOOK
190 select HAVE_ARCH_TRANSPARENT_HUGEPAGE !! 57 select HAVE_ARCH_TRANSPARENT_HUGEPAGE if CPU_SUPPORTS_HUGEPAGES
191 select HAVE_ARCH_VMAP_STACK <<
192 select HAVE_ARM_SMCCC <<
193 select HAVE_ASM_MODVERSIONS 58 select HAVE_ASM_MODVERSIONS
194 select HAVE_EBPF_JIT <<
195 select HAVE_C_RECORDMCOUNT <<
196 select HAVE_CMPXCHG_DOUBLE <<
197 select HAVE_CMPXCHG_LOCAL <<
198 select HAVE_CONTEXT_TRACKING_USER 59 select HAVE_CONTEXT_TRACKING_USER
>> 60 select HAVE_TIF_NOHZ
>> 61 select HAVE_C_RECORDMCOUNT
199 select HAVE_DEBUG_KMEMLEAK 62 select HAVE_DEBUG_KMEMLEAK
>> 63 select HAVE_DEBUG_STACKOVERFLOW
200 select HAVE_DMA_CONTIGUOUS 64 select HAVE_DMA_CONTIGUOUS
201 select HAVE_DYNAMIC_FTRACE 65 select HAVE_DYNAMIC_FTRACE
202 select HAVE_DYNAMIC_FTRACE_WITH_ARGS \ !! 66 select HAVE_EBPF_JIT if !CPU_MICROMIPS && \
203 if (GCC_SUPPORTS_DYNAMIC_FTRAC !! 67 !CPU_DADDI_WORKAROUNDS && \
204 CLANG_SUPPORTS_DYNAMIC_FTR !! 68 !CPU_R4000_WORKAROUNDS && \
205 select HAVE_DYNAMIC_FTRACE_WITH_DIRECT !! 69 !CPU_R4400_WORKAROUNDS
206 if DYNAMIC_FTRACE_WITH_ARGS && !! 70 select HAVE_EXIT_THREAD
207 select HAVE_DYNAMIC_FTRACE_WITH_CALL_O !! 71 select HAVE_FAST_GUP
208 if (DYNAMIC_FTRACE_WITH_ARGS & <<
209 (CC_IS_CLANG || !CC_OPTIMI <<
210 select FTRACE_MCOUNT_USE_PATCHABLE_FUN <<
211 if DYNAMIC_FTRACE_WITH_ARGS <<
212 select HAVE_SAMPLE_FTRACE_DIRECT <<
213 select HAVE_SAMPLE_FTRACE_DIRECT_MULTI <<
214 select HAVE_EFFICIENT_UNALIGNED_ACCESS <<
215 select HAVE_GUP_FAST <<
216 select HAVE_FTRACE_MCOUNT_RECORD 72 select HAVE_FTRACE_MCOUNT_RECORD
217 select HAVE_FUNCTION_TRACER <<
218 select HAVE_FUNCTION_ERROR_INJECTION <<
219 select HAVE_FUNCTION_GRAPH_TRACER 73 select HAVE_FUNCTION_GRAPH_TRACER
220 select HAVE_FUNCTION_GRAPH_RETVAL !! 74 select HAVE_FUNCTION_TRACER
221 select HAVE_GCC_PLUGINS 75 select HAVE_GCC_PLUGINS
222 select HAVE_HARDLOCKUP_DETECTOR_PERF i !! 76 select HAVE_GENERIC_VDSO
223 HW_PERF_EVENTS && HAVE_PERF_EV <<
224 select HAVE_HW_BREAKPOINT if PERF_EVEN <<
225 select HAVE_IOREMAP_PROT 77 select HAVE_IOREMAP_PROT
>> 78 select HAVE_IRQ_EXIT_ON_IRQ_STACK
226 select HAVE_IRQ_TIME_ACCOUNTING 79 select HAVE_IRQ_TIME_ACCOUNTING
>> 80 select HAVE_KPROBES
>> 81 select HAVE_KRETPROBES
>> 82 select HAVE_LD_DEAD_CODE_DATA_ELIMINATION
227 select HAVE_MOD_ARCH_SPECIFIC 83 select HAVE_MOD_ARCH_SPECIFIC
228 select HAVE_NMI 84 select HAVE_NMI
229 select HAVE_PERF_EVENTS 85 select HAVE_PERF_EVENTS
230 select HAVE_PERF_EVENTS_NMI if ARM64_P <<
231 select HAVE_PERF_REGS 86 select HAVE_PERF_REGS
232 select HAVE_PERF_USER_STACK_DUMP 87 select HAVE_PERF_USER_STACK_DUMP
233 select HAVE_PREEMPT_DYNAMIC_KEY <<
234 select HAVE_REGS_AND_STACK_ACCESS_API 88 select HAVE_REGS_AND_STACK_ACCESS_API
235 select HAVE_POSIX_CPU_TIMERS_TASK_WORK <<
236 select HAVE_FUNCTION_ARG_ACCESS_API <<
237 select MMU_GATHER_RCU_TABLE_FREE <<
238 select HAVE_RSEQ 89 select HAVE_RSEQ
239 select HAVE_RUST if RUSTC_SUPPORTS_ARM !! 90 select HAVE_SPARSE_SYSCALL_NR
240 select HAVE_STACKPROTECTOR 91 select HAVE_STACKPROTECTOR
241 select HAVE_SYSCALL_TRACEPOINTS 92 select HAVE_SYSCALL_TRACEPOINTS
242 select HAVE_KPROBES !! 93 select HAVE_VIRT_CPU_ACCOUNTING_GEN if 64BIT || !SMP
243 select HAVE_KRETPROBES <<
244 select HAVE_GENERIC_VDSO <<
245 select HOTPLUG_CORE_SYNC_DEAD if HOTPL <<
246 select IRQ_DOMAIN <<
247 select IRQ_FORCED_THREADING 94 select IRQ_FORCED_THREADING
248 select KASAN_VMALLOC if KASAN !! 95 select ISA if EISA
249 select LOCK_MM_AND_FIND_VMA !! 96 select MODULES_USE_ELF_REL if MODULES
250 select MODULES_USE_ELF_RELA !! 97 select MODULES_USE_ELF_RELA if MODULES && 64BIT
251 select NEED_DMA_MAP_STATE !! 98 select PERF_USE_VMALLOC
252 select NEED_SG_DMA_LENGTH !! 99 select PCI_MSI_ARCH_FALLBACKS if PCI_MSI
253 select OF !! 100 select RTC_LIB
254 select OF_EARLY_FLATTREE <<
255 select PCI_DOMAINS_GENERIC if PCI <<
256 select PCI_ECAM if (ACPI && PCI) <<
257 select PCI_SYSCALL if PCI <<
258 select POWER_RESET <<
259 select POWER_SUPPLY <<
260 select SPARSE_IRQ <<
261 select SWIOTLB <<
262 select SYSCTL_EXCEPTION_TRACE 101 select SYSCTL_EXCEPTION_TRACE
263 select THREAD_INFO_IN_TASK <<
264 select HAVE_ARCH_USERFAULTFD_MINOR if <<
265 select HAVE_ARCH_USERFAULTFD_WP if USE <<
266 select TRACE_IRQFLAGS_SUPPORT 102 select TRACE_IRQFLAGS_SUPPORT
267 select TRACE_IRQFLAGS_NMI_SUPPORT !! 103 select ARCH_HAS_ELFCORE_COMPAT
268 select HAVE_SOFTIRQ_ON_OWN_STACK !! 104 select HAVE_ARCH_KCSAN if 64BIT
269 select USER_STACKTRACE_SUPPORT <<
270 select VDSO_GETRANDOM <<
271 help <<
272 ARM 64-bit (AArch64) Linux support. <<
273 <<
274 config RUSTC_SUPPORTS_ARM64 <<
275 def_bool y <<
276 depends on CPU_LITTLE_ENDIAN <<
277 # Shadow call stack is only supported <<
278 # <<
279 # When using the UNWIND_PATCH_PAC_INTO <<
280 # required due to use of the -Zfixed-x <<
281 # <<
282 # Otherwise, rustc version 1.82+ is re <<
283 # -Zsanitizer=shadow-call-stack flag. <<
284 depends on !SHADOW_CALL_STACK || RUSTC <<
285 <<
286 config CLANG_SUPPORTS_DYNAMIC_FTRACE_WITH_ARGS <<
287 def_bool CC_IS_CLANG <<
288 # https://github.com/ClangBuiltLinux/l <<
289 depends on AS_IS_GNU || (AS_IS_LLVM && <<
290 <<
291 config GCC_SUPPORTS_DYNAMIC_FTRACE_WITH_ARGS <<
292 def_bool CC_IS_GCC <<
293 depends on $(cc-option,-fpatchable-fun <<
294 <<
295 config 64BIT <<
296 def_bool y <<
297 <<
298 config MMU <<
299 def_bool y <<
300 <<
301 config ARM64_CONT_PTE_SHIFT <<
302 int <<
303 default 5 if PAGE_SIZE_64KB <<
304 default 7 if PAGE_SIZE_16KB <<
305 default 4 <<
306 105
307 config ARM64_CONT_PMD_SHIFT !! 106 config MIPS_FIXUP_BIGPHYS_ADDR
308 int !! 107 bool
309 default 5 if PAGE_SIZE_64KB <<
310 default 5 if PAGE_SIZE_16KB <<
311 default 4 <<
312 <<
313 config ARCH_MMAP_RND_BITS_MIN <<
314 default 14 if PAGE_SIZE_64KB <<
315 default 16 if PAGE_SIZE_16KB <<
316 default 18 <<
317 108
318 # max bits determined by the following formula !! 109 config MIPS_GENERIC
319 # VA_BITS - PAGE_SHIFT - 3 !! 110 bool
320 config ARCH_MMAP_RND_BITS_MAX <<
321 default 19 if ARM64_VA_BITS=36 <<
322 default 24 if ARM64_VA_BITS=39 <<
323 default 27 if ARM64_VA_BITS=42 <<
324 default 30 if ARM64_VA_BITS=47 <<
325 default 29 if ARM64_VA_BITS=48 && ARM6 <<
326 default 31 if ARM64_VA_BITS=48 && ARM6 <<
327 default 33 if ARM64_VA_BITS=48 <<
328 default 14 if ARM64_64K_PAGES <<
329 default 16 if ARM64_16K_PAGES <<
330 default 18 <<
331 111
332 config ARCH_MMAP_RND_COMPAT_BITS_MIN !! 112 config MACH_INGENIC
333 default 7 if ARM64_64K_PAGES !! 113 bool
334 default 9 if ARM64_16K_PAGES !! 114 select SYS_SUPPORTS_32BIT_KERNEL
335 default 11 !! 115 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 116 select SYS_SUPPORTS_ZBOOT
>> 117 select DMA_NONCOHERENT
>> 118 select ARCH_HAS_SYNC_DMA_FOR_CPU
>> 119 select IRQ_MIPS_CPU
>> 120 select PINCTRL
>> 121 select GPIOLIB
>> 122 select COMMON_CLK
>> 123 select GENERIC_IRQ_CHIP
>> 124 select BUILTIN_DTB if MIPS_NO_APPENDED_DTB
>> 125 select USE_OF
>> 126 select CPU_SUPPORTS_CPUFREQ
>> 127 select MIPS_EXTERNAL_TIMER
336 128
337 config ARCH_MMAP_RND_COMPAT_BITS_MAX !! 129 menu "Machine selection"
338 default 16 <<
339 130
340 config NO_IOPORT_MAP !! 131 choice
341 def_bool y if !PCI !! 132 prompt "System type"
>> 133 default MIPS_GENERIC_KERNEL
342 134
343 config STACKTRACE_SUPPORT !! 135 config MIPS_GENERIC_KERNEL
344 def_bool y !! 136 bool "Generic board-agnostic MIPS kernel"
>> 137 select ARCH_HAS_SETUP_DMA_OPS
>> 138 select MIPS_GENERIC
>> 139 select BOOT_RAW
>> 140 select BUILTIN_DTB
>> 141 select CEVT_R4K
>> 142 select CLKSRC_MIPS_GIC
>> 143 select COMMON_CLK
>> 144 select CPU_MIPSR2_IRQ_EI
>> 145 select CPU_MIPSR2_IRQ_VI
>> 146 select CSRC_R4K
>> 147 select DMA_NONCOHERENT
>> 148 select HAVE_PCI
>> 149 select IRQ_MIPS_CPU
>> 150 select MIPS_AUTO_PFN_OFFSET
>> 151 select MIPS_CPU_SCACHE
>> 152 select MIPS_GIC
>> 153 select MIPS_L1_CACHE_SHIFT_7
>> 154 select NO_EXCEPT_FILL
>> 155 select PCI_DRIVERS_GENERIC
>> 156 select SMP_UP if SMP
>> 157 select SWAP_IO_SPACE
>> 158 select SYS_HAS_CPU_MIPS32_R1
>> 159 select SYS_HAS_CPU_MIPS32_R2
>> 160 select SYS_HAS_CPU_MIPS32_R6
>> 161 select SYS_HAS_CPU_MIPS64_R1
>> 162 select SYS_HAS_CPU_MIPS64_R2
>> 163 select SYS_HAS_CPU_MIPS64_R6
>> 164 select SYS_SUPPORTS_32BIT_KERNEL
>> 165 select SYS_SUPPORTS_64BIT_KERNEL
>> 166 select SYS_SUPPORTS_BIG_ENDIAN
>> 167 select SYS_SUPPORTS_HIGHMEM
>> 168 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 169 select SYS_SUPPORTS_MICROMIPS
>> 170 select SYS_SUPPORTS_MIPS16
>> 171 select SYS_SUPPORTS_MIPS_CPS
>> 172 select SYS_SUPPORTS_MULTITHREADING
>> 173 select SYS_SUPPORTS_RELOCATABLE
>> 174 select SYS_SUPPORTS_SMARTMIPS
>> 175 select SYS_SUPPORTS_ZBOOT
>> 176 select UHI_BOOT
>> 177 select USB_EHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
>> 178 select USB_EHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 179 select USB_OHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
>> 180 select USB_OHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 181 select USB_UHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
>> 182 select USB_UHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 183 select USE_OF
>> 184 help
>> 185 Select this to build a kernel which aims to support multiple boards,
>> 186 generally using a flattened device tree passed from the bootloader
>> 187 using the boot protocol defined in the UHI (Unified Hosting
>> 188 Interface) specification.
>> 189
>> 190 config MIPS_ALCHEMY
>> 191 bool "Alchemy processor based machines"
>> 192 select PHYS_ADDR_T_64BIT
>> 193 select CEVT_R4K
>> 194 select CSRC_R4K
>> 195 select IRQ_MIPS_CPU
>> 196 select DMA_NONCOHERENT # Au1000,1500,1100 aren't, rest is
>> 197 select MIPS_FIXUP_BIGPHYS_ADDR if PCI
>> 198 select SYS_HAS_CPU_MIPS32_R1
>> 199 select SYS_SUPPORTS_32BIT_KERNEL
>> 200 select SYS_SUPPORTS_APM_EMULATION
>> 201 select GPIOLIB
>> 202 select SYS_SUPPORTS_ZBOOT
>> 203 select COMMON_CLK
345 204
346 config ILLEGAL_POINTER_VALUE !! 205 config AR7
347 hex !! 206 bool "Texas Instruments AR7"
348 default 0xdead000000000000 !! 207 select BOOT_ELF32
>> 208 select COMMON_CLK
>> 209 select DMA_NONCOHERENT
>> 210 select CEVT_R4K
>> 211 select CSRC_R4K
>> 212 select IRQ_MIPS_CPU
>> 213 select NO_EXCEPT_FILL
>> 214 select SWAP_IO_SPACE
>> 215 select SYS_HAS_CPU_MIPS32_R1
>> 216 select SYS_HAS_EARLY_PRINTK
>> 217 select SYS_SUPPORTS_32BIT_KERNEL
>> 218 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 219 select SYS_SUPPORTS_MIPS16
>> 220 select SYS_SUPPORTS_ZBOOT_UART16550
>> 221 select GPIOLIB
>> 222 select VLYNQ
>> 223 help
>> 224 Support for the Texas Instruments AR7 System-on-a-Chip
>> 225 family: TNETD7100, 7200 and 7300.
>> 226
>> 227 config ATH25
>> 228 bool "Atheros AR231x/AR531x SoC support"
>> 229 select CEVT_R4K
>> 230 select CSRC_R4K
>> 231 select DMA_NONCOHERENT
>> 232 select IRQ_MIPS_CPU
>> 233 select IRQ_DOMAIN
>> 234 select SYS_HAS_CPU_MIPS32_R1
>> 235 select SYS_SUPPORTS_BIG_ENDIAN
>> 236 select SYS_SUPPORTS_32BIT_KERNEL
>> 237 select SYS_HAS_EARLY_PRINTK
>> 238 help
>> 239 Support for Atheros AR231x and Atheros AR531x based boards
>> 240
>> 241 config ATH79
>> 242 bool "Atheros AR71XX/AR724X/AR913X based boards"
>> 243 select ARCH_HAS_RESET_CONTROLLER
>> 244 select BOOT_RAW
>> 245 select CEVT_R4K
>> 246 select CSRC_R4K
>> 247 select DMA_NONCOHERENT
>> 248 select GPIOLIB
>> 249 select PINCTRL
>> 250 select COMMON_CLK
>> 251 select IRQ_MIPS_CPU
>> 252 select SYS_HAS_CPU_MIPS32_R2
>> 253 select SYS_HAS_EARLY_PRINTK
>> 254 select SYS_SUPPORTS_32BIT_KERNEL
>> 255 select SYS_SUPPORTS_BIG_ENDIAN
>> 256 select SYS_SUPPORTS_MIPS16
>> 257 select SYS_SUPPORTS_ZBOOT_UART_PROM
>> 258 select USE_OF
>> 259 select USB_EHCI_ROOT_HUB_TT if USB_EHCI_HCD_PLATFORM
>> 260 help
>> 261 Support for the Atheros AR71XX/AR724X/AR913X SoCs.
>> 262
>> 263 config BMIPS_GENERIC
>> 264 bool "Broadcom Generic BMIPS kernel"
>> 265 select ARCH_HAS_RESET_CONTROLLER
>> 266 select ARCH_HAS_SYNC_DMA_FOR_CPU_ALL
>> 267 select BOOT_RAW
>> 268 select NO_EXCEPT_FILL
>> 269 select USE_OF
>> 270 select CEVT_R4K
>> 271 select CSRC_R4K
>> 272 select SYNC_R4K
>> 273 select COMMON_CLK
>> 274 select BCM6345_L1_IRQ
>> 275 select BCM7038_L1_IRQ
>> 276 select BCM7120_L2_IRQ
>> 277 select BRCMSTB_L2_IRQ
>> 278 select IRQ_MIPS_CPU
>> 279 select DMA_NONCOHERENT
>> 280 select SYS_SUPPORTS_32BIT_KERNEL
>> 281 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 282 select SYS_SUPPORTS_BIG_ENDIAN
>> 283 select SYS_SUPPORTS_HIGHMEM
>> 284 select SYS_HAS_CPU_BMIPS32_3300
>> 285 select SYS_HAS_CPU_BMIPS4350
>> 286 select SYS_HAS_CPU_BMIPS4380
>> 287 select SYS_HAS_CPU_BMIPS5000
>> 288 select SWAP_IO_SPACE
>> 289 select USB_EHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
>> 290 select USB_EHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 291 select USB_OHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
>> 292 select USB_OHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 293 select HARDIRQS_SW_RESEND
>> 294 select HAVE_PCI
>> 295 select PCI_DRIVERS_GENERIC
>> 296 select FW_CFE
>> 297 help
>> 298 Build a generic DT-based kernel image that boots on select
>> 299 BCM33xx cable modem chips, BCM63xx DSL chips, and BCM7xxx set-top
>> 300 box chips. Note that CONFIG_CPU_BIG_ENDIAN/CONFIG_CPU_LITTLE_ENDIAN
>> 301 must be set appropriately for your board.
>> 302
>> 303 config BCM47XX
>> 304 bool "Broadcom BCM47XX based boards"
>> 305 select BOOT_RAW
>> 306 select CEVT_R4K
>> 307 select CSRC_R4K
>> 308 select DMA_NONCOHERENT
>> 309 select HAVE_PCI
>> 310 select IRQ_MIPS_CPU
>> 311 select SYS_HAS_CPU_MIPS32_R1
>> 312 select NO_EXCEPT_FILL
>> 313 select SYS_SUPPORTS_32BIT_KERNEL
>> 314 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 315 select SYS_SUPPORTS_MIPS16
>> 316 select SYS_SUPPORTS_ZBOOT
>> 317 select SYS_HAS_EARLY_PRINTK
>> 318 select USE_GENERIC_EARLY_PRINTK_8250
>> 319 select GPIOLIB
>> 320 select LEDS_GPIO_REGISTER
>> 321 select BCM47XX_NVRAM
>> 322 select BCM47XX_SPROM
>> 323 select BCM47XX_SSB if !BCM47XX_BCMA
>> 324 help
>> 325 Support for BCM47XX based boards
>> 326
>> 327 config BCM63XX
>> 328 bool "Broadcom BCM63XX based boards"
>> 329 select BOOT_RAW
>> 330 select CEVT_R4K
>> 331 select CSRC_R4K
>> 332 select SYNC_R4K
>> 333 select DMA_NONCOHERENT
>> 334 select IRQ_MIPS_CPU
>> 335 select SYS_SUPPORTS_32BIT_KERNEL
>> 336 select SYS_SUPPORTS_BIG_ENDIAN
>> 337 select SYS_HAS_EARLY_PRINTK
>> 338 select SYS_HAS_CPU_BMIPS32_3300
>> 339 select SYS_HAS_CPU_BMIPS4350
>> 340 select SYS_HAS_CPU_BMIPS4380
>> 341 select SWAP_IO_SPACE
>> 342 select GPIOLIB
>> 343 select MIPS_L1_CACHE_SHIFT_4
>> 344 select HAVE_LEGACY_CLK
>> 345 help
>> 346 Support for BCM63XX based boards
>> 347
>> 348 config MIPS_COBALT
>> 349 bool "Cobalt Server"
>> 350 select CEVT_R4K
>> 351 select CSRC_R4K
>> 352 select CEVT_GT641XX
>> 353 select DMA_NONCOHERENT
>> 354 select FORCE_PCI
>> 355 select I8253
>> 356 select I8259
>> 357 select IRQ_MIPS_CPU
>> 358 select IRQ_GT641XX
>> 359 select PCI_GT64XXX_PCI0
>> 360 select SYS_HAS_CPU_NEVADA
>> 361 select SYS_HAS_EARLY_PRINTK
>> 362 select SYS_SUPPORTS_32BIT_KERNEL
>> 363 select SYS_SUPPORTS_64BIT_KERNEL
>> 364 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 365 select USE_GENERIC_EARLY_PRINTK_8250
>> 366
>> 367 config MACH_DECSTATION
>> 368 bool "DECstations"
>> 369 select BOOT_ELF32
>> 370 select CEVT_DS1287
>> 371 select CEVT_R4K if CPU_R4X00
>> 372 select CSRC_IOASIC
>> 373 select CSRC_R4K if CPU_R4X00
>> 374 select CPU_DADDI_WORKAROUNDS if 64BIT
>> 375 select CPU_R4000_WORKAROUNDS if 64BIT
>> 376 select CPU_R4400_WORKAROUNDS if 64BIT
>> 377 select DMA_NONCOHERENT
>> 378 select NO_IOPORT_MAP
>> 379 select IRQ_MIPS_CPU
>> 380 select SYS_HAS_CPU_R3000
>> 381 select SYS_HAS_CPU_R4X00
>> 382 select SYS_SUPPORTS_32BIT_KERNEL
>> 383 select SYS_SUPPORTS_64BIT_KERNEL
>> 384 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 385 select SYS_SUPPORTS_128HZ
>> 386 select SYS_SUPPORTS_256HZ
>> 387 select SYS_SUPPORTS_1024HZ
>> 388 select MIPS_L1_CACHE_SHIFT_4
>> 389 help
>> 390 This enables support for DEC's MIPS based workstations. For details
>> 391 see the Linux/MIPS FAQ on <http://www.linux-mips.org/> and the
>> 392 DECstation porting pages on <http://decstation.unix-ag.org/>.
>> 393
>> 394 If you have one of the following DECstation Models you definitely
>> 395 want to choose R4xx0 for the CPU Type:
>> 396
>> 397 DECstation 5000/50
>> 398 DECstation 5000/150
>> 399 DECstation 5000/260
>> 400 DECsystem 5900/260
>> 401
>> 402 otherwise choose R3000.
>> 403
>> 404 config MACH_JAZZ
>> 405 bool "Jazz family of machines"
>> 406 select ARC_MEMORY
>> 407 select ARC_PROMLIB
>> 408 select ARCH_MIGHT_HAVE_PC_PARPORT
>> 409 select ARCH_MIGHT_HAVE_PC_SERIO
>> 410 select DMA_OPS
>> 411 select FW_ARC
>> 412 select FW_ARC32
>> 413 select ARCH_MAY_HAVE_PC_FDC
>> 414 select CEVT_R4K
>> 415 select CSRC_R4K
>> 416 select DEFAULT_SGI_PARTITION if CPU_BIG_ENDIAN
>> 417 select GENERIC_ISA_DMA
>> 418 select HAVE_PCSPKR_PLATFORM
>> 419 select IRQ_MIPS_CPU
>> 420 select I8253
>> 421 select I8259
>> 422 select ISA
>> 423 select SYS_HAS_CPU_R4X00
>> 424 select SYS_SUPPORTS_32BIT_KERNEL
>> 425 select SYS_SUPPORTS_64BIT_KERNEL
>> 426 select SYS_SUPPORTS_100HZ
>> 427 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 428 help
>> 429 This a family of machines based on the MIPS R4030 chipset which was
>> 430 used by several vendors to build RISC/os and Windows NT workstations.
>> 431 Members include the Acer PICA, MIPS Magnum 4000, MIPS Millennium and
>> 432 Olivetti M700-10 workstations.
>> 433
>> 434 config MACH_INGENIC_SOC
>> 435 bool "Ingenic SoC based machines"
>> 436 select MIPS_GENERIC
>> 437 select MACH_INGENIC
>> 438 select SYS_SUPPORTS_ZBOOT_UART16550
>> 439 select CPU_SUPPORTS_CPUFREQ
>> 440 select MIPS_EXTERNAL_TIMER
>> 441
>> 442 config LANTIQ
>> 443 bool "Lantiq based platforms"
>> 444 select DMA_NONCOHERENT
>> 445 select IRQ_MIPS_CPU
>> 446 select CEVT_R4K
>> 447 select CSRC_R4K
>> 448 select SYS_HAS_CPU_MIPS32_R1
>> 449 select SYS_HAS_CPU_MIPS32_R2
>> 450 select SYS_SUPPORTS_BIG_ENDIAN
>> 451 select SYS_SUPPORTS_32BIT_KERNEL
>> 452 select SYS_SUPPORTS_MIPS16
>> 453 select SYS_SUPPORTS_MULTITHREADING
>> 454 select SYS_SUPPORTS_VPE_LOADER
>> 455 select SYS_HAS_EARLY_PRINTK
>> 456 select GPIOLIB
>> 457 select SWAP_IO_SPACE
>> 458 select BOOT_RAW
>> 459 select HAVE_LEGACY_CLK
>> 460 select USE_OF
>> 461 select PINCTRL
>> 462 select PINCTRL_LANTIQ
>> 463 select ARCH_HAS_RESET_CONTROLLER
>> 464 select RESET_CONTROLLER
>> 465
>> 466 config MACH_LOONGSON32
>> 467 bool "Loongson 32-bit family of machines"
>> 468 select SYS_SUPPORTS_ZBOOT
>> 469 help
>> 470 This enables support for the Loongson-1 family of machines.
>> 471
>> 472 Loongson-1 is a family of 32-bit MIPS-compatible SoCs developed by
>> 473 the Institute of Computing Technology (ICT), Chinese Academy of
>> 474 Sciences (CAS).
>> 475
>> 476 config MACH_LOONGSON2EF
>> 477 bool "Loongson-2E/F family of machines"
>> 478 select SYS_SUPPORTS_ZBOOT
>> 479 help
>> 480 This enables the support of early Loongson-2E/F family of machines.
>> 481
>> 482 config MACH_LOONGSON64
>> 483 bool "Loongson 64-bit family of machines"
>> 484 select ARCH_SPARSEMEM_ENABLE
>> 485 select ARCH_MIGHT_HAVE_PC_PARPORT
>> 486 select ARCH_MIGHT_HAVE_PC_SERIO
>> 487 select GENERIC_ISA_DMA_SUPPORT_BROKEN
>> 488 select BOOT_ELF32
>> 489 select BOARD_SCACHE
>> 490 select CSRC_R4K
>> 491 select CEVT_R4K
>> 492 select CPU_HAS_WB
>> 493 select FORCE_PCI
>> 494 select ISA
>> 495 select I8259
>> 496 select IRQ_MIPS_CPU
>> 497 select NO_EXCEPT_FILL
>> 498 select NR_CPUS_DEFAULT_64
>> 499 select USE_GENERIC_EARLY_PRINTK_8250
>> 500 select PCI_DRIVERS_GENERIC
>> 501 select SYS_HAS_CPU_LOONGSON64
>> 502 select SYS_HAS_EARLY_PRINTK
>> 503 select SYS_SUPPORTS_SMP
>> 504 select SYS_SUPPORTS_HOTPLUG_CPU
>> 505 select SYS_SUPPORTS_NUMA
>> 506 select SYS_SUPPORTS_64BIT_KERNEL
>> 507 select SYS_SUPPORTS_HIGHMEM
>> 508 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 509 select SYS_SUPPORTS_ZBOOT
>> 510 select SYS_SUPPORTS_RELOCATABLE
>> 511 select ZONE_DMA32
>> 512 select COMMON_CLK
>> 513 select USE_OF
>> 514 select BUILTIN_DTB
>> 515 select PCI_HOST_GENERIC
>> 516 select HAVE_ARCH_NODEDATA_EXTENSION if NUMA
>> 517 help
>> 518 This enables the support of Loongson-2/3 family of machines.
>> 519
>> 520 Loongson-2 and Loongson-3 are 64-bit general-purpose processors with
>> 521 GS264/GS464/GS464E/GS464V microarchitecture (except old Loongson-2E
>> 522 and Loongson-2F which will be removed), developed by the Institute
>> 523 of Computing Technology (ICT), Chinese Academy of Sciences (CAS).
>> 524
>> 525 config MIPS_MALTA
>> 526 bool "MIPS Malta board"
>> 527 select ARCH_MAY_HAVE_PC_FDC
>> 528 select ARCH_MIGHT_HAVE_PC_PARPORT
>> 529 select ARCH_MIGHT_HAVE_PC_SERIO
>> 530 select BOOT_ELF32
>> 531 select BOOT_RAW
>> 532 select BUILTIN_DTB
>> 533 select CEVT_R4K
>> 534 select CLKSRC_MIPS_GIC
>> 535 select COMMON_CLK
>> 536 select CSRC_R4K
>> 537 select DMA_NONCOHERENT
>> 538 select GENERIC_ISA_DMA
>> 539 select HAVE_PCSPKR_PLATFORM
>> 540 select HAVE_PCI
>> 541 select I8253
>> 542 select I8259
>> 543 select IRQ_MIPS_CPU
>> 544 select MIPS_BONITO64
>> 545 select MIPS_CPU_SCACHE
>> 546 select MIPS_GIC
>> 547 select MIPS_L1_CACHE_SHIFT_6
>> 548 select MIPS_MSC
>> 549 select PCI_GT64XXX_PCI0
>> 550 select SMP_UP if SMP
>> 551 select SWAP_IO_SPACE
>> 552 select SYS_HAS_CPU_MIPS32_R1
>> 553 select SYS_HAS_CPU_MIPS32_R2
>> 554 select SYS_HAS_CPU_MIPS32_R3_5
>> 555 select SYS_HAS_CPU_MIPS32_R5
>> 556 select SYS_HAS_CPU_MIPS32_R6
>> 557 select SYS_HAS_CPU_MIPS64_R1
>> 558 select SYS_HAS_CPU_MIPS64_R2
>> 559 select SYS_HAS_CPU_MIPS64_R6
>> 560 select SYS_HAS_CPU_NEVADA
>> 561 select SYS_HAS_CPU_RM7000
>> 562 select SYS_SUPPORTS_32BIT_KERNEL
>> 563 select SYS_SUPPORTS_64BIT_KERNEL
>> 564 select SYS_SUPPORTS_BIG_ENDIAN
>> 565 select SYS_SUPPORTS_HIGHMEM
>> 566 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 567 select SYS_SUPPORTS_MICROMIPS
>> 568 select SYS_SUPPORTS_MIPS16
>> 569 select SYS_SUPPORTS_MIPS_CMP
>> 570 select SYS_SUPPORTS_MIPS_CPS
>> 571 select SYS_SUPPORTS_MULTITHREADING
>> 572 select SYS_SUPPORTS_RELOCATABLE
>> 573 select SYS_SUPPORTS_SMARTMIPS
>> 574 select SYS_SUPPORTS_VPE_LOADER
>> 575 select SYS_SUPPORTS_ZBOOT
>> 576 select USE_OF
>> 577 select WAR_ICACHE_REFILLS
>> 578 select ZONE_DMA32 if 64BIT
>> 579 help
>> 580 This enables support for the MIPS Technologies Malta evaluation
>> 581 board.
>> 582
>> 583 config MACH_PIC32
>> 584 bool "Microchip PIC32 Family"
>> 585 help
>> 586 This enables support for the Microchip PIC32 family of platforms.
>> 587
>> 588 Microchip PIC32 is a family of general-purpose 32 bit MIPS core
>> 589 microcontrollers.
>> 590
>> 591 config MACH_NINTENDO64
>> 592 bool "Nintendo 64 console"
>> 593 select CEVT_R4K
>> 594 select CSRC_R4K
>> 595 select SYS_HAS_CPU_R4300
>> 596 select SYS_SUPPORTS_BIG_ENDIAN
>> 597 select SYS_SUPPORTS_ZBOOT
>> 598 select SYS_SUPPORTS_32BIT_KERNEL
>> 599 select SYS_SUPPORTS_64BIT_KERNEL
>> 600 select DMA_NONCOHERENT
>> 601 select IRQ_MIPS_CPU
>> 602
>> 603 config RALINK
>> 604 bool "Ralink based machines"
>> 605 select CEVT_R4K
>> 606 select COMMON_CLK
>> 607 select CSRC_R4K
>> 608 select BOOT_RAW
>> 609 select DMA_NONCOHERENT
>> 610 select IRQ_MIPS_CPU
>> 611 select USE_OF
>> 612 select SYS_HAS_CPU_MIPS32_R1
>> 613 select SYS_HAS_CPU_MIPS32_R2
>> 614 select SYS_SUPPORTS_32BIT_KERNEL
>> 615 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 616 select SYS_SUPPORTS_MIPS16
>> 617 select SYS_SUPPORTS_ZBOOT
>> 618 select SYS_HAS_EARLY_PRINTK
>> 619 select ARCH_HAS_RESET_CONTROLLER
>> 620 select RESET_CONTROLLER
>> 621
>> 622 config MACH_REALTEK_RTL
>> 623 bool "Realtek RTL838x/RTL839x based machines"
>> 624 select MIPS_GENERIC
>> 625 select DMA_NONCOHERENT
>> 626 select IRQ_MIPS_CPU
>> 627 select CSRC_R4K
>> 628 select CEVT_R4K
>> 629 select SYS_HAS_CPU_MIPS32_R1
>> 630 select SYS_HAS_CPU_MIPS32_R2
>> 631 select SYS_SUPPORTS_BIG_ENDIAN
>> 632 select SYS_SUPPORTS_32BIT_KERNEL
>> 633 select SYS_SUPPORTS_MIPS16
>> 634 select SYS_SUPPORTS_MULTITHREADING
>> 635 select SYS_SUPPORTS_VPE_LOADER
>> 636 select BOOT_RAW
>> 637 select PINCTRL
>> 638 select USE_OF
>> 639
>> 640 config SGI_IP22
>> 641 bool "SGI IP22 (Indy/Indigo2)"
>> 642 select ARC_MEMORY
>> 643 select ARC_PROMLIB
>> 644 select FW_ARC
>> 645 select FW_ARC32
>> 646 select ARCH_MIGHT_HAVE_PC_SERIO
>> 647 select BOOT_ELF32
>> 648 select CEVT_R4K
>> 649 select CSRC_R4K
>> 650 select DEFAULT_SGI_PARTITION
>> 651 select DMA_NONCOHERENT
>> 652 select HAVE_EISA
>> 653 select I8253
>> 654 select I8259
>> 655 select IP22_CPU_SCACHE
>> 656 select IRQ_MIPS_CPU
>> 657 select GENERIC_ISA_DMA_SUPPORT_BROKEN
>> 658 select SGI_HAS_I8042
>> 659 select SGI_HAS_INDYDOG
>> 660 select SGI_HAS_HAL2
>> 661 select SGI_HAS_SEEQ
>> 662 select SGI_HAS_WD93
>> 663 select SGI_HAS_ZILOG
>> 664 select SWAP_IO_SPACE
>> 665 select SYS_HAS_CPU_R4X00
>> 666 select SYS_HAS_CPU_R5000
>> 667 select SYS_HAS_EARLY_PRINTK
>> 668 select SYS_SUPPORTS_32BIT_KERNEL
>> 669 select SYS_SUPPORTS_64BIT_KERNEL
>> 670 select SYS_SUPPORTS_BIG_ENDIAN
>> 671 select WAR_R4600_V1_INDEX_ICACHEOP
>> 672 select WAR_R4600_V1_HIT_CACHEOP
>> 673 select WAR_R4600_V2_HIT_CACHEOP
>> 674 select MIPS_L1_CACHE_SHIFT_7
>> 675 help
>> 676 This are the SGI Indy, Challenge S and Indigo2, as well as certain
>> 677 OEM variants like the Tandem CMN B006S. To compile a Linux kernel
>> 678 that runs on these, say Y here.
>> 679
>> 680 config SGI_IP27
>> 681 bool "SGI IP27 (Origin200/2000)"
>> 682 select ARCH_HAS_PHYS_TO_DMA
>> 683 select ARCH_SPARSEMEM_ENABLE
>> 684 select FW_ARC
>> 685 select FW_ARC64
>> 686 select ARC_CMDLINE_ONLY
>> 687 select BOOT_ELF64
>> 688 select DEFAULT_SGI_PARTITION
>> 689 select FORCE_PCI
>> 690 select SYS_HAS_EARLY_PRINTK
>> 691 select HAVE_PCI
>> 692 select IRQ_MIPS_CPU
>> 693 select IRQ_DOMAIN_HIERARCHY
>> 694 select NR_CPUS_DEFAULT_64
>> 695 select PCI_DRIVERS_GENERIC
>> 696 select PCI_XTALK_BRIDGE
>> 697 select SYS_HAS_CPU_R10000
>> 698 select SYS_SUPPORTS_64BIT_KERNEL
>> 699 select SYS_SUPPORTS_BIG_ENDIAN
>> 700 select SYS_SUPPORTS_NUMA
>> 701 select SYS_SUPPORTS_SMP
>> 702 select WAR_R10000_LLSC
>> 703 select MIPS_L1_CACHE_SHIFT_7
>> 704 select NUMA
>> 705 select HAVE_ARCH_NODEDATA_EXTENSION
>> 706 help
>> 707 This are the SGI Origin 200, Origin 2000 and Onyx 2 Graphics
>> 708 workstations. To compile a Linux kernel that runs on these, say Y
>> 709 here.
>> 710
>> 711 config SGI_IP28
>> 712 bool "SGI IP28 (Indigo2 R10k)"
>> 713 select ARC_MEMORY
>> 714 select ARC_PROMLIB
>> 715 select FW_ARC
>> 716 select FW_ARC64
>> 717 select ARCH_MIGHT_HAVE_PC_SERIO
>> 718 select BOOT_ELF64
>> 719 select CEVT_R4K
>> 720 select CSRC_R4K
>> 721 select DEFAULT_SGI_PARTITION
>> 722 select DMA_NONCOHERENT
>> 723 select GENERIC_ISA_DMA_SUPPORT_BROKEN
>> 724 select IRQ_MIPS_CPU
>> 725 select HAVE_EISA
>> 726 select I8253
>> 727 select I8259
>> 728 select SGI_HAS_I8042
>> 729 select SGI_HAS_INDYDOG
>> 730 select SGI_HAS_HAL2
>> 731 select SGI_HAS_SEEQ
>> 732 select SGI_HAS_WD93
>> 733 select SGI_HAS_ZILOG
>> 734 select SWAP_IO_SPACE
>> 735 select SYS_HAS_CPU_R10000
>> 736 select SYS_HAS_EARLY_PRINTK
>> 737 select SYS_SUPPORTS_64BIT_KERNEL
>> 738 select SYS_SUPPORTS_BIG_ENDIAN
>> 739 select WAR_R10000_LLSC
>> 740 select MIPS_L1_CACHE_SHIFT_7
>> 741 help
>> 742 This is the SGI Indigo2 with R10000 processor. To compile a Linux
>> 743 kernel that runs on these, say Y here.
>> 744
>> 745 config SGI_IP30
>> 746 bool "SGI IP30 (Octane/Octane2)"
>> 747 select ARCH_HAS_PHYS_TO_DMA
>> 748 select FW_ARC
>> 749 select FW_ARC64
>> 750 select BOOT_ELF64
>> 751 select CEVT_R4K
>> 752 select CSRC_R4K
>> 753 select FORCE_PCI
>> 754 select SYNC_R4K if SMP
>> 755 select ZONE_DMA32
>> 756 select HAVE_PCI
>> 757 select IRQ_MIPS_CPU
>> 758 select IRQ_DOMAIN_HIERARCHY
>> 759 select PCI_DRIVERS_GENERIC
>> 760 select PCI_XTALK_BRIDGE
>> 761 select SYS_HAS_EARLY_PRINTK
>> 762 select SYS_HAS_CPU_R10000
>> 763 select SYS_SUPPORTS_64BIT_KERNEL
>> 764 select SYS_SUPPORTS_BIG_ENDIAN
>> 765 select SYS_SUPPORTS_SMP
>> 766 select WAR_R10000_LLSC
>> 767 select MIPS_L1_CACHE_SHIFT_7
>> 768 select ARC_MEMORY
>> 769 help
>> 770 These are the SGI Octane and Octane2 graphics workstations. To
>> 771 compile a Linux kernel that runs on these, say Y here.
>> 772
>> 773 config SGI_IP32
>> 774 bool "SGI IP32 (O2)"
>> 775 select ARC_MEMORY
>> 776 select ARC_PROMLIB
>> 777 select ARCH_HAS_PHYS_TO_DMA
>> 778 select FW_ARC
>> 779 select FW_ARC32
>> 780 select BOOT_ELF32
>> 781 select CEVT_R4K
>> 782 select CSRC_R4K
>> 783 select DMA_NONCOHERENT
>> 784 select HAVE_PCI
>> 785 select IRQ_MIPS_CPU
>> 786 select R5000_CPU_SCACHE
>> 787 select RM7000_CPU_SCACHE
>> 788 select SYS_HAS_CPU_R5000
>> 789 select SYS_HAS_CPU_R10000 if BROKEN
>> 790 select SYS_HAS_CPU_RM7000
>> 791 select SYS_HAS_CPU_NEVADA
>> 792 select SYS_SUPPORTS_64BIT_KERNEL
>> 793 select SYS_SUPPORTS_BIG_ENDIAN
>> 794 select WAR_ICACHE_REFILLS
>> 795 help
>> 796 If you want this kernel to run on SGI O2 workstation, say Y here.
>> 797
>> 798 config SIBYTE_CRHINE
>> 799 bool "Sibyte BCM91120C-CRhine"
>> 800 select BOOT_ELF32
>> 801 select SIBYTE_BCM1120
>> 802 select SWAP_IO_SPACE
>> 803 select SYS_HAS_CPU_SB1
>> 804 select SYS_SUPPORTS_BIG_ENDIAN
>> 805 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 806
>> 807 config SIBYTE_CARMEL
>> 808 bool "Sibyte BCM91120x-Carmel"
>> 809 select BOOT_ELF32
>> 810 select SIBYTE_BCM1120
>> 811 select SWAP_IO_SPACE
>> 812 select SYS_HAS_CPU_SB1
>> 813 select SYS_SUPPORTS_BIG_ENDIAN
>> 814 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 815
>> 816 config SIBYTE_CRHONE
>> 817 bool "Sibyte BCM91125C-CRhone"
>> 818 select BOOT_ELF32
>> 819 select SIBYTE_BCM1125
>> 820 select SWAP_IO_SPACE
>> 821 select SYS_HAS_CPU_SB1
>> 822 select SYS_SUPPORTS_BIG_ENDIAN
>> 823 select SYS_SUPPORTS_HIGHMEM
>> 824 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 825
>> 826 config SIBYTE_RHONE
>> 827 bool "Sibyte BCM91125E-Rhone"
>> 828 select BOOT_ELF32
>> 829 select SIBYTE_BCM1125H
>> 830 select SWAP_IO_SPACE
>> 831 select SYS_HAS_CPU_SB1
>> 832 select SYS_SUPPORTS_BIG_ENDIAN
>> 833 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 834
>> 835 config SIBYTE_SWARM
>> 836 bool "Sibyte BCM91250A-SWARM"
>> 837 select BOOT_ELF32
>> 838 select HAVE_PATA_PLATFORM
>> 839 select SIBYTE_SB1250
>> 840 select SWAP_IO_SPACE
>> 841 select SYS_HAS_CPU_SB1
>> 842 select SYS_SUPPORTS_BIG_ENDIAN
>> 843 select SYS_SUPPORTS_HIGHMEM
>> 844 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 845 select ZONE_DMA32 if 64BIT
>> 846 select SWIOTLB if ARCH_DMA_ADDR_T_64BIT && PCI
>> 847
>> 848 config SIBYTE_LITTLESUR
>> 849 bool "Sibyte BCM91250C2-LittleSur"
>> 850 select BOOT_ELF32
>> 851 select HAVE_PATA_PLATFORM
>> 852 select SIBYTE_SB1250
>> 853 select SWAP_IO_SPACE
>> 854 select SYS_HAS_CPU_SB1
>> 855 select SYS_SUPPORTS_BIG_ENDIAN
>> 856 select SYS_SUPPORTS_HIGHMEM
>> 857 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 858 select ZONE_DMA32 if 64BIT
>> 859
>> 860 config SIBYTE_SENTOSA
>> 861 bool "Sibyte BCM91250E-Sentosa"
>> 862 select BOOT_ELF32
>> 863 select SIBYTE_SB1250
>> 864 select SWAP_IO_SPACE
>> 865 select SYS_HAS_CPU_SB1
>> 866 select SYS_SUPPORTS_BIG_ENDIAN
>> 867 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 868 select SWIOTLB if ARCH_DMA_ADDR_T_64BIT && PCI
>> 869
>> 870 config SIBYTE_BIGSUR
>> 871 bool "Sibyte BCM91480B-BigSur"
>> 872 select BOOT_ELF32
>> 873 select NR_CPUS_DEFAULT_4
>> 874 select SIBYTE_BCM1x80
>> 875 select SWAP_IO_SPACE
>> 876 select SYS_HAS_CPU_SB1
>> 877 select SYS_SUPPORTS_BIG_ENDIAN
>> 878 select SYS_SUPPORTS_HIGHMEM
>> 879 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 880 select ZONE_DMA32 if 64BIT
>> 881 select SWIOTLB if ARCH_DMA_ADDR_T_64BIT && PCI
>> 882
>> 883 config SNI_RM
>> 884 bool "SNI RM200/300/400"
>> 885 select ARC_MEMORY
>> 886 select ARC_PROMLIB
>> 887 select FW_ARC if CPU_LITTLE_ENDIAN
>> 888 select FW_ARC32 if CPU_LITTLE_ENDIAN
>> 889 select FW_SNIPROM if CPU_BIG_ENDIAN
>> 890 select ARCH_MAY_HAVE_PC_FDC
>> 891 select ARCH_MIGHT_HAVE_PC_PARPORT
>> 892 select ARCH_MIGHT_HAVE_PC_SERIO
>> 893 select BOOT_ELF32
>> 894 select CEVT_R4K
>> 895 select CSRC_R4K
>> 896 select DEFAULT_SGI_PARTITION if CPU_BIG_ENDIAN
>> 897 select DMA_NONCOHERENT
>> 898 select GENERIC_ISA_DMA
>> 899 select HAVE_EISA
>> 900 select HAVE_PCSPKR_PLATFORM
>> 901 select HAVE_PCI
>> 902 select IRQ_MIPS_CPU
>> 903 select I8253
>> 904 select I8259
>> 905 select ISA
>> 906 select MIPS_L1_CACHE_SHIFT_6
>> 907 select SWAP_IO_SPACE if CPU_BIG_ENDIAN
>> 908 select SYS_HAS_CPU_R4X00
>> 909 select SYS_HAS_CPU_R5000
>> 910 select SYS_HAS_CPU_R10000
>> 911 select R5000_CPU_SCACHE
>> 912 select SYS_HAS_EARLY_PRINTK
>> 913 select SYS_SUPPORTS_32BIT_KERNEL
>> 914 select SYS_SUPPORTS_64BIT_KERNEL
>> 915 select SYS_SUPPORTS_BIG_ENDIAN
>> 916 select SYS_SUPPORTS_HIGHMEM
>> 917 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 918 select WAR_R4600_V2_HIT_CACHEOP
>> 919 help
>> 920 The SNI RM200/300/400 are MIPS-based machines manufactured by
>> 921 Siemens Nixdorf Informationssysteme (SNI), parent company of Pyramid
>> 922 Technology and now in turn merged with Fujitsu. Say Y here to
>> 923 support this machine type.
>> 924
>> 925 config MACH_TX49XX
>> 926 bool "Toshiba TX49 series based machines"
>> 927 select WAR_TX49XX_ICACHE_INDEX_INV
>> 928
>> 929 config MIKROTIK_RB532
>> 930 bool "Mikrotik RB532 boards"
>> 931 select CEVT_R4K
>> 932 select CSRC_R4K
>> 933 select DMA_NONCOHERENT
>> 934 select HAVE_PCI
>> 935 select IRQ_MIPS_CPU
>> 936 select SYS_HAS_CPU_MIPS32_R1
>> 937 select SYS_SUPPORTS_32BIT_KERNEL
>> 938 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 939 select SWAP_IO_SPACE
>> 940 select BOOT_RAW
>> 941 select GPIOLIB
>> 942 select MIPS_L1_CACHE_SHIFT_4
>> 943 help
>> 944 Support the Mikrotik(tm) RouterBoard 532 series,
>> 945 based on the IDT RC32434 SoC.
>> 946
>> 947 config CAVIUM_OCTEON_SOC
>> 948 bool "Cavium Networks Octeon SoC based boards"
>> 949 select CEVT_R4K
>> 950 select ARCH_HAS_PHYS_TO_DMA
>> 951 select HAVE_RAPIDIO
>> 952 select PHYS_ADDR_T_64BIT
>> 953 select SYS_SUPPORTS_64BIT_KERNEL
>> 954 select SYS_SUPPORTS_BIG_ENDIAN
>> 955 select EDAC_SUPPORT
>> 956 select EDAC_ATOMIC_SCRUB
>> 957 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 958 select SYS_SUPPORTS_HOTPLUG_CPU if CPU_BIG_ENDIAN
>> 959 select SYS_HAS_EARLY_PRINTK
>> 960 select SYS_HAS_CPU_CAVIUM_OCTEON
>> 961 select HAVE_PCI
>> 962 select HAVE_PLAT_DELAY
>> 963 select HAVE_PLAT_FW_INIT_CMDLINE
>> 964 select HAVE_PLAT_MEMCPY
>> 965 select ZONE_DMA32
>> 966 select GPIOLIB
>> 967 select USE_OF
>> 968 select ARCH_SPARSEMEM_ENABLE
>> 969 select SYS_SUPPORTS_SMP
>> 970 select NR_CPUS_DEFAULT_64
>> 971 select MIPS_NR_CPU_NR_MAP_1024
>> 972 select BUILTIN_DTB
>> 973 select MTD
>> 974 select MTD_COMPLEX_MAPPINGS
>> 975 select SWIOTLB
>> 976 select SYS_SUPPORTS_RELOCATABLE
>> 977 help
>> 978 This option supports all of the Octeon reference boards from Cavium
>> 979 Networks. It builds a kernel that dynamically determines the Octeon
>> 980 CPU type and supports all known board reference implementations.
>> 981 Some of the supported boards are:
>> 982 EBT3000
>> 983 EBH3000
>> 984 EBH3100
>> 985 Thunder
>> 986 Kodama
>> 987 Hikari
>> 988 Say Y here for most Octeon reference boards.
349 989
350 config LOCKDEP_SUPPORT !! 990 endchoice
351 def_bool y <<
352 991
353 config GENERIC_BUG !! 992 source "arch/mips/alchemy/Kconfig"
354 def_bool y !! 993 source "arch/mips/ath25/Kconfig"
355 depends on BUG !! 994 source "arch/mips/ath79/Kconfig"
>> 995 source "arch/mips/bcm47xx/Kconfig"
>> 996 source "arch/mips/bcm63xx/Kconfig"
>> 997 source "arch/mips/bmips/Kconfig"
>> 998 source "arch/mips/generic/Kconfig"
>> 999 source "arch/mips/ingenic/Kconfig"
>> 1000 source "arch/mips/jazz/Kconfig"
>> 1001 source "arch/mips/lantiq/Kconfig"
>> 1002 source "arch/mips/pic32/Kconfig"
>> 1003 source "arch/mips/ralink/Kconfig"
>> 1004 source "arch/mips/sgi-ip27/Kconfig"
>> 1005 source "arch/mips/sibyte/Kconfig"
>> 1006 source "arch/mips/txx9/Kconfig"
>> 1007 source "arch/mips/cavium-octeon/Kconfig"
>> 1008 source "arch/mips/loongson2ef/Kconfig"
>> 1009 source "arch/mips/loongson32/Kconfig"
>> 1010 source "arch/mips/loongson64/Kconfig"
356 1011
357 config GENERIC_BUG_RELATIVE_POINTERS !! 1012 endmenu
358 def_bool y <<
359 depends on GENERIC_BUG <<
360 1013
361 config GENERIC_HWEIGHT 1014 config GENERIC_HWEIGHT
362 def_bool y !! 1015 bool
363 !! 1016 default y
364 config GENERIC_CSUM <<
365 def_bool y <<
366 1017
367 config GENERIC_CALIBRATE_DELAY 1018 config GENERIC_CALIBRATE_DELAY
368 def_bool y !! 1019 bool
>> 1020 default y
369 1021
370 config SMP !! 1022 config SCHED_OMIT_FRAME_POINTER
371 def_bool y !! 1023 bool
>> 1024 default y
372 1025
373 config KERNEL_MODE_NEON !! 1026 #
374 def_bool y !! 1027 # Select some configuration options automatically based on user selections.
>> 1028 #
>> 1029 config FW_ARC
>> 1030 bool
375 1031
376 config FIX_EARLYCON_MEM !! 1032 config ARCH_MAY_HAVE_PC_FDC
377 def_bool y !! 1033 bool
378 1034
379 config PGTABLE_LEVELS !! 1035 config BOOT_RAW
380 int !! 1036 bool
381 default 2 if ARM64_16K_PAGES && ARM64_ <<
382 default 2 if ARM64_64K_PAGES && ARM64_ <<
383 default 3 if ARM64_64K_PAGES && (ARM64 <<
384 default 3 if ARM64_4K_PAGES && ARM64_V <<
385 default 3 if ARM64_16K_PAGES && ARM64_ <<
386 default 4 if ARM64_16K_PAGES && (ARM64 <<
387 default 4 if !ARM64_64K_PAGES && ARM64 <<
388 default 5 if ARM64_4K_PAGES && ARM64_V <<
389 1037
390 config ARCH_SUPPORTS_UPROBES !! 1038 config CEVT_BCM1480
391 def_bool y !! 1039 bool
392 1040
393 config ARCH_PROC_KCORE_TEXT !! 1041 config CEVT_DS1287
394 def_bool y !! 1042 bool
395 1043
396 config BROKEN_GAS_INST !! 1044 config CEVT_GT641XX
397 def_bool !$(as-instr,1:\n.inst 0\n.rep !! 1045 bool
398 1046
399 config BUILTIN_RETURN_ADDRESS_STRIPS_PAC !! 1047 config CEVT_R4K
400 bool 1048 bool
401 # Clang's __builtin_return_address() s <<
402 # https://github.com/llvm/llvm-project <<
403 default y if CC_IS_CLANG <<
404 # GCC's __builtin_return_address() str <<
405 # and this was backported to 10.2.0, 9 <<
406 # https://gcc.gnu.org/bugzilla/show_bu <<
407 default y if CC_IS_GCC && (GCC_VERSION <<
408 default y if CC_IS_GCC && (GCC_VERSION <<
409 default y if CC_IS_GCC && (GCC_VERSION <<
410 default y if CC_IS_GCC && (GCC_VERSION <<
411 default n <<
412 1049
413 config KASAN_SHADOW_OFFSET !! 1050 config CEVT_SB1250
414 hex <<
415 depends on KASAN_GENERIC || KASAN_SW_T <<
416 default 0xdfff800000000000 if (ARM64_V <<
417 default 0xdfffc00000000000 if (ARM64_V <<
418 default 0xdffffe0000000000 if ARM64_VA <<
419 default 0xdfffffc000000000 if ARM64_VA <<
420 default 0xdffffff800000000 if ARM64_VA <<
421 default 0xefff800000000000 if (ARM64_V <<
422 default 0xefffc00000000000 if (ARM64_V <<
423 default 0xeffffe0000000000 if ARM64_VA <<
424 default 0xefffffc000000000 if ARM64_VA <<
425 default 0xeffffff800000000 if ARM64_VA <<
426 default 0xffffffffffffffff <<
427 <<
428 config UNWIND_TABLES <<
429 bool 1051 bool
430 1052
431 source "arch/arm64/Kconfig.platforms" !! 1053 config CEVT_TXX9
>> 1054 bool
432 1055
433 menu "Kernel Features" !! 1056 config CSRC_BCM1480
>> 1057 bool
434 1058
435 menu "ARM errata workarounds via the alternati !! 1059 config CSRC_IOASIC
>> 1060 bool
436 1061
437 config AMPERE_ERRATUM_AC03_CPU_38 !! 1062 config CSRC_R4K
438 bool "AmpereOne: AC03_CPU_38: Certain !! 1063 select CLOCKSOURCE_WATCHDOG if CPU_FREQ
439 default y !! 1064 bool
440 help <<
441 This option adds an alternative code <<
442 errata AC03_CPU_38 and AC04_CPU_10 o <<
443 1065
444 The affected design reports FEAT_HAF !! 1066 config CSRC_SB1250
445 ID_AA64MMFR1_EL1.HAFDBS, but (V)TCR_ !! 1067 bool
446 as required by the architecture. The <<
447 implementation suffers from an addit <<
448 A/D updates can occur after a PTE ha <<
449 <<
450 The workaround forces KVM to explici <<
451 which avoids enabling unadvertised h <<
452 at stage-2. <<
453 1068
454 If unsure, say Y. !! 1069 config MIPS_CLOCK_VSYSCALL
>> 1070 def_bool CSRC_R4K || CLKSRC_MIPS_GIC
455 1071
456 config ARM64_WORKAROUND_CLEAN_CACHE !! 1072 config GPIO_TXX9
>> 1073 select GPIOLIB
457 bool 1074 bool
458 1075
459 config ARM64_ERRATUM_826319 !! 1076 config FW_CFE
460 bool "Cortex-A53: 826319: System might !! 1077 bool
461 default y <<
462 select ARM64_WORKAROUND_CLEAN_CACHE <<
463 help <<
464 This option adds an alternative code <<
465 erratum 826319 on Cortex-A53 parts u <<
466 AXI master interface and an L2 cache <<
467 <<
468 If a Cortex-A53 uses an AMBA AXI4 AC <<
469 and is unable to accept a certain wr <<
470 not progress on read data presented <<
471 system can deadlock. <<
472 <<
473 The workaround promotes data cache c <<
474 data cache clean-and-invalidate. <<
475 Please note that this does not neces <<
476 as it depends on the alternative fra <<
477 the kernel if an affected CPU is det <<
478 1078
479 If unsure, say Y. !! 1079 config ARCH_SUPPORTS_UPROBES
>> 1080 bool
480 1081
481 config ARM64_ERRATUM_827319 !! 1082 config DMA_PERDEV_COHERENT
482 bool "Cortex-A53: 827319: Data cache c !! 1083 bool
483 default y !! 1084 select ARCH_HAS_SETUP_DMA_OPS
484 select ARM64_WORKAROUND_CLEAN_CACHE !! 1085 select DMA_NONCOHERENT
485 help <<
486 This option adds an alternative code <<
487 erratum 827319 on Cortex-A53 parts u <<
488 master interface and an L2 cache. <<
489 <<
490 Under certain conditions this erratu <<
491 to occur at the same time as another <<
492 on the AMBA 5 CHI interface, which c <<
493 interconnect reorders the two transa <<
494 <<
495 The workaround promotes data cache c <<
496 data cache clean-and-invalidate. <<
497 Please note that this does not neces <<
498 as it depends on the alternative fra <<
499 the kernel if an affected CPU is det <<
500 1086
501 If unsure, say Y. !! 1087 config DMA_NONCOHERENT
>> 1088 bool
>> 1089 #
>> 1090 # MIPS allows mixing "slightly different" Cacheability and Coherency
>> 1091 # Attribute bits. It is believed that the uncached access through
>> 1092 # KSEG1 and the implementation specific "uncached accelerated" used
>> 1093 # by pgprot_writcombine can be mixed, and the latter sometimes provides
>> 1094 # significant advantages.
>> 1095 #
>> 1096 select ARCH_HAS_DMA_WRITE_COMBINE
>> 1097 select ARCH_HAS_DMA_PREP_COHERENT
>> 1098 select ARCH_HAS_SYNC_DMA_FOR_DEVICE
>> 1099 select ARCH_HAS_DMA_SET_UNCACHED
>> 1100 select DMA_NONCOHERENT_MMAP
>> 1101 select NEED_DMA_MAP_STATE
502 1102
503 config ARM64_ERRATUM_824069 !! 1103 config SYS_HAS_EARLY_PRINTK
504 bool "Cortex-A53: 824069: Cache line m !! 1104 bool
505 default y <<
506 select ARM64_WORKAROUND_CLEAN_CACHE <<
507 help <<
508 This option adds an alternative code <<
509 erratum 824069 on Cortex-A53 parts u <<
510 to a coherent interconnect. <<
511 <<
512 If a Cortex-A53 processor is executi <<
513 write instruction at the same time a <<
514 cluster is executing a cache mainten <<
515 address, then this erratum might cau <<
516 incorrectly marked as dirty. <<
517 <<
518 The workaround promotes data cache c <<
519 data cache clean-and-invalidate. <<
520 Please note that this option does no <<
521 workaround, as it depends on the alt <<
522 only patch the kernel if an affected <<
523 1105
524 If unsure, say Y. !! 1106 config SYS_SUPPORTS_HOTPLUG_CPU
>> 1107 bool
525 1108
526 config ARM64_ERRATUM_819472 !! 1109 config MIPS_BONITO64
527 bool "Cortex-A53: 819472: Store exclus !! 1110 bool
528 default y <<
529 select ARM64_WORKAROUND_CLEAN_CACHE <<
530 help <<
531 This option adds an alternative code <<
532 erratum 819472 on Cortex-A53 parts u <<
533 present when it is connected to a co <<
534 <<
535 If the processor is executing a load <<
536 the same time as a processor in anot <<
537 maintenance operation to the same ad <<
538 cause data corruption. <<
539 <<
540 The workaround promotes data cache c <<
541 data cache clean-and-invalidate. <<
542 Please note that this does not neces <<
543 as it depends on the alternative fra <<
544 the kernel if an affected CPU is det <<
545 1111
546 If unsure, say Y. !! 1112 config MIPS_MSC
>> 1113 bool
547 1114
548 config ARM64_ERRATUM_832075 !! 1115 config SYNC_R4K
549 bool "Cortex-A57: 832075: possible dea !! 1116 bool
550 default y <<
551 help <<
552 This option adds an alternative code <<
553 erratum 832075 on Cortex-A57 parts u <<
554 1117
555 Affected Cortex-A57 parts might dead !! 1118 config NO_IOPORT_MAP
556 instructions to Write-Back memory ar !! 1119 def_bool n
557 1120
558 The workaround is to promote device !! 1121 config GENERIC_CSUM
559 semantics. !! 1122 def_bool CPU_NO_LOAD_STORE_LR
560 Please note that this does not neces <<
561 as it depends on the alternative fra <<
562 the kernel if an affected CPU is det <<
563 1123
564 If unsure, say Y. !! 1124 config GENERIC_ISA_DMA
>> 1125 bool
>> 1126 select ZONE_DMA if GENERIC_ISA_DMA_SUPPORT_BROKEN=n
>> 1127 select ISA_DMA_API
565 1128
566 config ARM64_ERRATUM_834220 !! 1129 config GENERIC_ISA_DMA_SUPPORT_BROKEN
567 bool "Cortex-A57: 834220: Stage 2 tran !! 1130 bool
568 depends on KVM !! 1131 select GENERIC_ISA_DMA
569 help <<
570 This option adds an alternative code <<
571 erratum 834220 on Cortex-A57 parts u <<
572 <<
573 Affected Cortex-A57 parts might repo <<
574 fault as the result of a Stage 1 fau <<
575 page boundary when there is a permis <<
576 alignment fault at Stage 1 and a tra <<
577 <<
578 The workaround is to verify that the <<
579 doesn't generate a fault before hand <<
580 Please note that this does not neces <<
581 as it depends on the alternative fra <<
582 the kernel if an affected CPU is det <<
583 1132
584 If unsure, say N. !! 1133 config HAVE_PLAT_DELAY
>> 1134 bool
585 1135
586 config ARM64_ERRATUM_1742098 !! 1136 config HAVE_PLAT_FW_INIT_CMDLINE
587 bool "Cortex-A57/A72: 1742098: ELR rec !! 1137 bool
588 depends on COMPAT <<
589 default y <<
590 help <<
591 This option removes the AES hwcap fo <<
592 workaround erratum 1742098 on Cortex <<
593 1138
594 Affected parts may corrupt the AES s !! 1139 config HAVE_PLAT_MEMCPY
595 taken between a pair of AES instruct !! 1140 bool
596 are only present if the cryptography <<
597 All software should have a fallback <<
598 that don't implement the cryptograph <<
599 1141
600 If unsure, say Y. !! 1142 config ISA_DMA_API
>> 1143 bool
601 1144
602 config ARM64_ERRATUM_845719 !! 1145 config SYS_SUPPORTS_RELOCATABLE
603 bool "Cortex-A53: 845719: a load might !! 1146 bool
604 depends on COMPAT <<
605 default y <<
606 help 1147 help
607 This option adds an alternative code !! 1148 Selected if the platform supports relocating the kernel.
608 erratum 845719 on Cortex-A53 parts u !! 1149 The platform must provide plat_get_fdt() if it selects CONFIG_USE_OF
609 !! 1150 to allow access to command line and entropy sources.
610 When running a compat (AArch32) user <<
611 part, a load at EL0 from a virtual a <<
612 bits of the virtual address used by <<
613 might return incorrect data. <<
614 <<
615 The workaround is to write the conte <<
616 return to a 32-bit task. <<
617 Please note that this does not neces <<
618 as it depends on the alternative fra <<
619 the kernel if an affected CPU is det <<
620 <<
621 If unsure, say Y. <<
622 1151
623 config ARM64_ERRATUM_843419 !! 1152 #
624 bool "Cortex-A53: 843419: A load or st !! 1153 # Endianness selection. Sufficiently obscure so many users don't know what to
625 default y !! 1154 # answer,so we try hard to limit the available choices. Also the use of a
>> 1155 # choice statement should be more obvious to the user.
>> 1156 #
>> 1157 choice
>> 1158 prompt "Endianness selection"
626 help 1159 help
627 This option links the kernel with '- !! 1160 Some MIPS machines can be configured for either little or big endian
628 enables PLT support to replace certa !! 1161 byte order. These modes require different kernels and a different
629 cause subsequent memory accesses to !! 1162 Linux distribution. In general there is one preferred byteorder for a
630 Cortex-A53 parts up to r0p4. !! 1163 particular system but some systems are just as commonly used in the
>> 1164 one or the other endianness.
631 1165
632 If unsure, say Y. !! 1166 config CPU_BIG_ENDIAN
>> 1167 bool "Big endian"
>> 1168 depends on SYS_SUPPORTS_BIG_ENDIAN
633 1169
634 config ARM64_LD_HAS_FIX_ERRATUM_843419 !! 1170 config CPU_LITTLE_ENDIAN
635 def_bool $(ld-option,--fix-cortex-a53- !! 1171 bool "Little endian"
>> 1172 depends on SYS_SUPPORTS_LITTLE_ENDIAN
636 1173
637 config ARM64_ERRATUM_1024718 !! 1174 endchoice
638 bool "Cortex-A55: 1024718: Update of D <<
639 default y <<
640 help <<
641 This option adds a workaround for AR <<
642 1175
643 Affected Cortex-A55 cores (all revis !! 1176 config EXPORT_UASM
644 update of the hardware dirty bit whe !! 1177 bool
645 without a break-before-make. The wor <<
646 of hardware DBM locally on the affec <<
647 this erratum will continue to use th <<
648 1178
649 If unsure, say Y. !! 1179 config SYS_SUPPORTS_APM_EMULATION
>> 1180 bool
650 1181
651 config ARM64_ERRATUM_1418040 !! 1182 config SYS_SUPPORTS_BIG_ENDIAN
652 bool "Cortex-A76/Neoverse-N1: MRC read !! 1183 bool
653 default y <<
654 depends on COMPAT <<
655 help <<
656 This option adds a workaround for AR <<
657 errata 1188873 and 1418040. <<
658 1184
659 Affected Cortex-A76/Neoverse-N1 core !! 1185 config SYS_SUPPORTS_LITTLE_ENDIAN
660 cause register corruption when acces !! 1186 bool
661 from AArch32 userspace. <<
662 1187
663 If unsure, say Y. !! 1188 config MIPS_HUGE_TLB_SUPPORT
>> 1189 def_bool HUGETLB_PAGE || TRANSPARENT_HUGEPAGE
664 1190
665 config ARM64_WORKAROUND_SPECULATIVE_AT !! 1191 config IRQ_MSP_SLP
666 bool 1192 bool
667 1193
668 config ARM64_ERRATUM_1165522 !! 1194 config IRQ_MSP_CIC
669 bool "Cortex-A76: 1165522: Speculative !! 1195 bool
670 default y <<
671 select ARM64_WORKAROUND_SPECULATIVE_AT <<
672 help <<
673 This option adds a workaround for AR <<
674 <<
675 Affected Cortex-A76 cores (r0p0, r1p <<
676 corrupted TLBs by speculating an AT <<
677 context switch. <<
678 1196
679 If unsure, say Y. !! 1197 config IRQ_TXX9
>> 1198 bool
680 1199
681 config ARM64_ERRATUM_1319367 !! 1200 config IRQ_GT641XX
682 bool "Cortex-A57/A72: 1319537: Specula !! 1201 bool
683 default y <<
684 select ARM64_WORKAROUND_SPECULATIVE_AT <<
685 help <<
686 This option adds work arounds for AR <<
687 and A72 erratum 1319367 <<
688 1202
689 Cortex-A57 and A72 cores could end-u !! 1203 config PCI_GT64XXX_PCI0
690 speculating an AT instruction during !! 1204 bool
691 1205
692 If unsure, say Y. !! 1206 config PCI_XTALK_BRIDGE
>> 1207 bool
693 1208
694 config ARM64_ERRATUM_1530923 !! 1209 config NO_EXCEPT_FILL
695 bool "Cortex-A55: 1530923: Speculative !! 1210 bool
696 default y <<
697 select ARM64_WORKAROUND_SPECULATIVE_AT <<
698 help <<
699 This option adds a workaround for AR <<
700 1211
701 Affected Cortex-A55 cores (r0p0, r0p !! 1212 config MIPS_SPRAM
702 corrupted TLBs by speculating an AT !! 1213 bool
703 context switch. <<
704 1214
705 If unsure, say Y. !! 1215 config SWAP_IO_SPACE
>> 1216 bool
706 1217
707 config ARM64_WORKAROUND_REPEAT_TLBI !! 1218 config SGI_HAS_INDYDOG
708 bool 1219 bool
709 1220
710 config ARM64_ERRATUM_2441007 !! 1221 config SGI_HAS_HAL2
711 bool "Cortex-A55: Completion of affect !! 1222 bool
712 select ARM64_WORKAROUND_REPEAT_TLBI <<
713 help <<
714 This option adds a workaround for AR <<
715 1223
716 Under very rare circumstances, affec !! 1224 config SGI_HAS_SEEQ
717 may not handle a race between a brea !! 1225 bool
718 CPU, and another CPU accessing the s <<
719 store to a page that has been unmapp <<
720 1226
721 Work around this by adding the affec !! 1227 config SGI_HAS_WD93
722 TLB sequences to be done twice. !! 1228 bool
723 1229
724 If unsure, say N. !! 1230 config SGI_HAS_ZILOG
>> 1231 bool
725 1232
726 config ARM64_ERRATUM_1286807 !! 1233 config SGI_HAS_I8042
727 bool "Cortex-A76: Modification of the !! 1234 bool
728 select ARM64_WORKAROUND_REPEAT_TLBI <<
729 help <<
730 This option adds a workaround for AR <<
731 <<
732 On the affected Cortex-A76 cores (r0 <<
733 address for a cacheable mapping of a <<
734 accessed by a core while another cor <<
735 address to a new physical page using <<
736 break-before-make sequence, then und <<
737 TLBI+DSB completes before a read usi <<
738 invalidated has been observed by oth <<
739 workaround repeats the TLBI+DSB oper <<
740 1235
741 If unsure, say N. !! 1236 config DEFAULT_SGI_PARTITION
>> 1237 bool
742 1238
743 config ARM64_ERRATUM_1463225 !! 1239 config FW_ARC32
744 bool "Cortex-A76: Software Step might !! 1240 bool
745 default y <<
746 help <<
747 This option adds a workaround for Ar <<
748 1241
749 On the affected Cortex-A76 cores (r0 !! 1242 config FW_SNIPROM
750 of a system call instruction (SVC) c !! 1243 bool
751 subsequent interrupts when software <<
752 exception handler of the system call <<
753 is enabled or VHE is in use. <<
754 <<
755 Work around the erratum by triggerin <<
756 when handling a system call from a t <<
757 in a VHE configuration of the kernel <<
758 1244
759 If unsure, say Y. !! 1245 config BOOT_ELF32
>> 1246 bool
760 1247
761 config ARM64_ERRATUM_1542419 !! 1248 config MIPS_L1_CACHE_SHIFT_4
762 bool "Neoverse-N1: workaround mis-orde !! 1249 bool
763 help <<
764 This option adds a workaround for AR <<
765 1542419. <<
766 1250
767 Affected Neoverse-N1 cores could exe !! 1251 config MIPS_L1_CACHE_SHIFT_5
768 modified by another CPU. The workaro !! 1252 bool
769 counterpart. <<
770 1253
771 Workaround the issue by hiding the D !! 1254 config MIPS_L1_CACHE_SHIFT_6
772 forces user-space to perform cache m !! 1255 bool
773 1256
774 If unsure, say N. !! 1257 config MIPS_L1_CACHE_SHIFT_7
>> 1258 bool
775 1259
776 config ARM64_ERRATUM_1508412 !! 1260 config MIPS_L1_CACHE_SHIFT
777 bool "Cortex-A77: 1508412: workaround !! 1261 int
778 default y !! 1262 default "7" if MIPS_L1_CACHE_SHIFT_7
779 help !! 1263 default "6" if MIPS_L1_CACHE_SHIFT_6
780 This option adds a workaround for Ar !! 1264 default "5" if MIPS_L1_CACHE_SHIFT_5
>> 1265 default "4" if MIPS_L1_CACHE_SHIFT_4
>> 1266 default "5"
781 1267
782 Affected Cortex-A77 cores (r0p0, r1p !! 1268 config ARC_CMDLINE_ONLY
783 of a store-exclusive or read of PAR_ !! 1269 bool
784 non-cacheable memory attributes. The <<
785 counterpart. <<
786 <<
787 KVM guests must also have the workar <<
788 deadlock the system. <<
789 <<
790 Work around the issue by inserting D <<
791 register reads and warning KVM users <<
792 to prevent a speculative PAR_EL1 rea <<
793 1270
794 If unsure, say Y. !! 1271 config ARC_CONSOLE
>> 1272 bool "ARC console support"
>> 1273 depends on SGI_IP22 || SGI_IP28 || (SNI_RM && CPU_LITTLE_ENDIAN)
795 1274
796 config ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MO !! 1275 config ARC_MEMORY
797 bool 1276 bool
798 1277
799 config ARM64_ERRATUM_2051678 !! 1278 config ARC_PROMLIB
800 bool "Cortex-A510: 2051678: disable Ha !! 1279 bool
801 default y <<
802 help <<
803 This options adds the workaround for <<
804 Affected Cortex-A510 might not respe <<
805 hardware update of the page table's <<
806 is to not enable the feature on affe <<
807 1280
808 If unsure, say Y. !! 1281 config FW_ARC64
>> 1282 bool
809 1283
810 config ARM64_ERRATUM_2077057 !! 1284 config BOOT_ELF64
811 bool "Cortex-A510: 2077057: workaround !! 1285 bool
812 default y <<
813 help <<
814 This option adds the workaround for <<
815 Affected Cortex-A510 may corrupt SPS <<
816 expected, but a Pointer Authenticati <<
817 erratum causes SPSR_EL1 to be copied <<
818 EL1 to cause a return to EL2 with a <<
819 1286
820 This can only happen when EL2 is ste !! 1287 menu "CPU selection"
821 1288
822 When these conditions occur, the SPS !! 1289 choice
823 previous guest entry, and can be res !! 1290 prompt "CPU type"
>> 1291 default CPU_R4X00
824 1292
825 If unsure, say Y. !! 1293 config CPU_LOONGSON64
>> 1294 bool "Loongson 64-bit CPU"
>> 1295 depends on SYS_HAS_CPU_LOONGSON64
>> 1296 select ARCH_HAS_PHYS_TO_DMA
>> 1297 select CPU_MIPSR2
>> 1298 select CPU_HAS_PREFETCH
>> 1299 select CPU_SUPPORTS_64BIT_KERNEL
>> 1300 select CPU_SUPPORTS_HIGHMEM
>> 1301 select CPU_SUPPORTS_HUGEPAGES
>> 1302 select CPU_SUPPORTS_MSA
>> 1303 select CPU_DIEI_BROKEN if !LOONGSON3_ENHANCEMENT
>> 1304 select CPU_MIPSR2_IRQ_VI
>> 1305 select WEAK_ORDERING
>> 1306 select WEAK_REORDERING_BEYOND_LLSC
>> 1307 select MIPS_ASID_BITS_VARIABLE
>> 1308 select MIPS_PGD_C0_CONTEXT
>> 1309 select MIPS_L1_CACHE_SHIFT_6
>> 1310 select MIPS_FP_SUPPORT
>> 1311 select GPIOLIB
>> 1312 select SWIOTLB
>> 1313 select HAVE_KVM
>> 1314 help
>> 1315 The Loongson GSx64(GS264/GS464/GS464E/GS464V) series of processor
>> 1316 cores implements the MIPS64R2 instruction set with many extensions,
>> 1317 including most 64-bit Loongson-2 (2H, 2K) and Loongson-3 (3A1000,
>> 1318 3B1000, 3B1500, 3A2000, 3A3000 and 3A4000) processors. However, old
>> 1319 Loongson-2E/2F is not covered here and will be removed in future.
826 1320
827 config ARM64_ERRATUM_2658417 !! 1321 config LOONGSON3_ENHANCEMENT
828 bool "Cortex-A510: 2658417: remove BF1 !! 1322 bool "New Loongson-3 CPU Enhancements"
829 default y !! 1323 default n
>> 1324 depends on CPU_LOONGSON64
830 help 1325 help
831 This option adds the workaround for !! 1326 New Loongson-3 cores (since Loongson-3A R2, as opposed to Loongson-3A
832 Affected Cortex-A510 (r0p0 to r1p1) !! 1327 R1, Loongson-3B R1 and Loongson-3B R2) has many enhancements, such as
833 BFMMLA or VMMLA instructions in rare !! 1328 FTLB, L1-VCache, EI/DI/Wait/Prefetch instruction, DSP/DSPr2 ASE, User
834 A510 CPUs are using shared neon hard !! 1329 Local register, Read-Inhibit/Execute-Inhibit, SFB (Store Fill Buffer),
835 discoverable by the kernel, hide the !! 1330 Fast TLB refill support, etc.
836 user-space should not be using these !! 1331
>> 1332 This option enable those enhancements which are not probed at run
>> 1333 time. If you want a generic kernel to run on all Loongson 3 machines,
>> 1334 please say 'N' here. If you want a high-performance kernel to run on
>> 1335 new Loongson-3 machines only, please say 'Y' here.
>> 1336
>> 1337 config CPU_LOONGSON3_WORKAROUNDS
>> 1338 bool "Loongson-3 LLSC Workarounds"
>> 1339 default y if SMP
>> 1340 depends on CPU_LOONGSON64
>> 1341 help
>> 1342 Loongson-3 processors have the llsc issues which require workarounds.
>> 1343 Without workarounds the system may hang unexpectedly.
>> 1344
>> 1345 Say Y, unless you know what you are doing.
>> 1346
>> 1347 config CPU_LOONGSON3_CPUCFG_EMULATION
>> 1348 bool "Emulate the CPUCFG instruction on older Loongson cores"
>> 1349 default y
>> 1350 depends on CPU_LOONGSON64
>> 1351 help
>> 1352 Loongson-3A R4 and newer have the CPUCFG instruction available for
>> 1353 userland to query CPU capabilities, much like CPUID on x86. This
>> 1354 option provides emulation of the instruction on older Loongson
>> 1355 cores, back to Loongson-3A1000.
>> 1356
>> 1357 If unsure, please say Y.
>> 1358
>> 1359 config CPU_LOONGSON2E
>> 1360 bool "Loongson 2E"
>> 1361 depends on SYS_HAS_CPU_LOONGSON2E
>> 1362 select CPU_LOONGSON2EF
>> 1363 help
>> 1364 The Loongson 2E processor implements the MIPS III instruction set
>> 1365 with many extensions.
>> 1366
>> 1367 It has an internal FPGA northbridge, which is compatible to
>> 1368 bonito64.
>> 1369
>> 1370 config CPU_LOONGSON2F
>> 1371 bool "Loongson 2F"
>> 1372 depends on SYS_HAS_CPU_LOONGSON2F
>> 1373 select CPU_LOONGSON2EF
>> 1374 select GPIOLIB
>> 1375 help
>> 1376 The Loongson 2F processor implements the MIPS III instruction set
>> 1377 with many extensions.
>> 1378
>> 1379 Loongson2F have built-in DDR2 and PCIX controller. The PCIX controller
>> 1380 have a similar programming interface with FPGA northbridge used in
>> 1381 Loongson2E.
>> 1382
>> 1383 config CPU_LOONGSON1B
>> 1384 bool "Loongson 1B"
>> 1385 depends on SYS_HAS_CPU_LOONGSON1B
>> 1386 select CPU_LOONGSON32
>> 1387 select LEDS_GPIO_REGISTER
>> 1388 help
>> 1389 The Loongson 1B is a 32-bit SoC, which implements the MIPS32
>> 1390 Release 1 instruction set and part of the MIPS32 Release 2
>> 1391 instruction set.
>> 1392
>> 1393 config CPU_LOONGSON1C
>> 1394 bool "Loongson 1C"
>> 1395 depends on SYS_HAS_CPU_LOONGSON1C
>> 1396 select CPU_LOONGSON32
>> 1397 select LEDS_GPIO_REGISTER
>> 1398 help
>> 1399 The Loongson 1C is a 32-bit SoC, which implements the MIPS32
>> 1400 Release 1 instruction set and part of the MIPS32 Release 2
>> 1401 instruction set.
>> 1402
>> 1403 config CPU_MIPS32_R1
>> 1404 bool "MIPS32 Release 1"
>> 1405 depends on SYS_HAS_CPU_MIPS32_R1
>> 1406 select CPU_HAS_PREFETCH
>> 1407 select CPU_SUPPORTS_32BIT_KERNEL
>> 1408 select CPU_SUPPORTS_HIGHMEM
>> 1409 help
>> 1410 Choose this option to build a kernel for release 1 or later of the
>> 1411 MIPS32 architecture. Most modern embedded systems with a 32-bit
>> 1412 MIPS processor are based on a MIPS32 processor. If you know the
>> 1413 specific type of processor in your system, choose those that one
>> 1414 otherwise CPU_MIPS32_R1 is a safe bet for any MIPS32 system.
>> 1415 Release 2 of the MIPS32 architecture is available since several
>> 1416 years so chances are you even have a MIPS32 Release 2 processor
>> 1417 in which case you should choose CPU_MIPS32_R2 instead for better
>> 1418 performance.
>> 1419
>> 1420 config CPU_MIPS32_R2
>> 1421 bool "MIPS32 Release 2"
>> 1422 depends on SYS_HAS_CPU_MIPS32_R2
>> 1423 select CPU_HAS_PREFETCH
>> 1424 select CPU_SUPPORTS_32BIT_KERNEL
>> 1425 select CPU_SUPPORTS_HIGHMEM
>> 1426 select CPU_SUPPORTS_MSA
>> 1427 select HAVE_KVM
>> 1428 help
>> 1429 Choose this option to build a kernel for release 2 or later of the
>> 1430 MIPS32 architecture. Most modern embedded systems with a 32-bit
>> 1431 MIPS processor are based on a MIPS32 processor. If you know the
>> 1432 specific type of processor in your system, choose those that one
>> 1433 otherwise CPU_MIPS32_R1 is a safe bet for any MIPS32 system.
>> 1434
>> 1435 config CPU_MIPS32_R5
>> 1436 bool "MIPS32 Release 5"
>> 1437 depends on SYS_HAS_CPU_MIPS32_R5
>> 1438 select CPU_HAS_PREFETCH
>> 1439 select CPU_SUPPORTS_32BIT_KERNEL
>> 1440 select CPU_SUPPORTS_HIGHMEM
>> 1441 select CPU_SUPPORTS_MSA
>> 1442 select HAVE_KVM
>> 1443 select MIPS_O32_FP64_SUPPORT
>> 1444 help
>> 1445 Choose this option to build a kernel for release 5 or later of the
>> 1446 MIPS32 architecture. New MIPS processors, starting with the Warrior
>> 1447 family, are based on a MIPS32r5 processor. If you own an older
>> 1448 processor, you probably need to select MIPS32r1 or MIPS32r2 instead.
>> 1449
>> 1450 config CPU_MIPS32_R6
>> 1451 bool "MIPS32 Release 6"
>> 1452 depends on SYS_HAS_CPU_MIPS32_R6
>> 1453 select CPU_HAS_PREFETCH
>> 1454 select CPU_NO_LOAD_STORE_LR
>> 1455 select CPU_SUPPORTS_32BIT_KERNEL
>> 1456 select CPU_SUPPORTS_HIGHMEM
>> 1457 select CPU_SUPPORTS_MSA
>> 1458 select HAVE_KVM
>> 1459 select MIPS_O32_FP64_SUPPORT
>> 1460 help
>> 1461 Choose this option to build a kernel for release 6 or later of the
>> 1462 MIPS32 architecture. New MIPS processors, starting with the Warrior
>> 1463 family, are based on a MIPS32r6 processor. If you own an older
>> 1464 processor, you probably need to select MIPS32r1 or MIPS32r2 instead.
>> 1465
>> 1466 config CPU_MIPS64_R1
>> 1467 bool "MIPS64 Release 1"
>> 1468 depends on SYS_HAS_CPU_MIPS64_R1
>> 1469 select CPU_HAS_PREFETCH
>> 1470 select CPU_SUPPORTS_32BIT_KERNEL
>> 1471 select CPU_SUPPORTS_64BIT_KERNEL
>> 1472 select CPU_SUPPORTS_HIGHMEM
>> 1473 select CPU_SUPPORTS_HUGEPAGES
>> 1474 help
>> 1475 Choose this option to build a kernel for release 1 or later of the
>> 1476 MIPS64 architecture. Many modern embedded systems with a 64-bit
>> 1477 MIPS processor are based on a MIPS64 processor. If you know the
>> 1478 specific type of processor in your system, choose those that one
>> 1479 otherwise CPU_MIPS64_R1 is a safe bet for any MIPS64 system.
>> 1480 Release 2 of the MIPS64 architecture is available since several
>> 1481 years so chances are you even have a MIPS64 Release 2 processor
>> 1482 in which case you should choose CPU_MIPS64_R2 instead for better
>> 1483 performance.
>> 1484
>> 1485 config CPU_MIPS64_R2
>> 1486 bool "MIPS64 Release 2"
>> 1487 depends on SYS_HAS_CPU_MIPS64_R2
>> 1488 select CPU_HAS_PREFETCH
>> 1489 select CPU_SUPPORTS_32BIT_KERNEL
>> 1490 select CPU_SUPPORTS_64BIT_KERNEL
>> 1491 select CPU_SUPPORTS_HIGHMEM
>> 1492 select CPU_SUPPORTS_HUGEPAGES
>> 1493 select CPU_SUPPORTS_MSA
>> 1494 select HAVE_KVM
>> 1495 help
>> 1496 Choose this option to build a kernel for release 2 or later of the
>> 1497 MIPS64 architecture. Many modern embedded systems with a 64-bit
>> 1498 MIPS processor are based on a MIPS64 processor. If you know the
>> 1499 specific type of processor in your system, choose those that one
>> 1500 otherwise CPU_MIPS64_R1 is a safe bet for any MIPS64 system.
>> 1501
>> 1502 config CPU_MIPS64_R5
>> 1503 bool "MIPS64 Release 5"
>> 1504 depends on SYS_HAS_CPU_MIPS64_R5
>> 1505 select CPU_HAS_PREFETCH
>> 1506 select CPU_SUPPORTS_32BIT_KERNEL
>> 1507 select CPU_SUPPORTS_64BIT_KERNEL
>> 1508 select CPU_SUPPORTS_HIGHMEM
>> 1509 select CPU_SUPPORTS_HUGEPAGES
>> 1510 select CPU_SUPPORTS_MSA
>> 1511 select MIPS_O32_FP64_SUPPORT if 32BIT || MIPS32_O32
>> 1512 select HAVE_KVM
>> 1513 help
>> 1514 Choose this option to build a kernel for release 5 or later of the
>> 1515 MIPS64 architecture. This is a intermediate MIPS architecture
>> 1516 release partly implementing release 6 features. Though there is no
>> 1517 any hardware known to be based on this release.
>> 1518
>> 1519 config CPU_MIPS64_R6
>> 1520 bool "MIPS64 Release 6"
>> 1521 depends on SYS_HAS_CPU_MIPS64_R6
>> 1522 select CPU_HAS_PREFETCH
>> 1523 select CPU_NO_LOAD_STORE_LR
>> 1524 select CPU_SUPPORTS_32BIT_KERNEL
>> 1525 select CPU_SUPPORTS_64BIT_KERNEL
>> 1526 select CPU_SUPPORTS_HIGHMEM
>> 1527 select CPU_SUPPORTS_HUGEPAGES
>> 1528 select CPU_SUPPORTS_MSA
>> 1529 select MIPS_O32_FP64_SUPPORT if 32BIT || MIPS32_O32
>> 1530 select HAVE_KVM
>> 1531 help
>> 1532 Choose this option to build a kernel for release 6 or later of the
>> 1533 MIPS64 architecture. New MIPS processors, starting with the Warrior
>> 1534 family, are based on a MIPS64r6 processor. If you own an older
>> 1535 processor, you probably need to select MIPS64r1 or MIPS64r2 instead.
>> 1536
>> 1537 config CPU_P5600
>> 1538 bool "MIPS Warrior P5600"
>> 1539 depends on SYS_HAS_CPU_P5600
>> 1540 select CPU_HAS_PREFETCH
>> 1541 select CPU_SUPPORTS_32BIT_KERNEL
>> 1542 select CPU_SUPPORTS_HIGHMEM
>> 1543 select CPU_SUPPORTS_MSA
>> 1544 select CPU_SUPPORTS_CPUFREQ
>> 1545 select CPU_MIPSR2_IRQ_VI
>> 1546 select CPU_MIPSR2_IRQ_EI
>> 1547 select HAVE_KVM
>> 1548 select MIPS_O32_FP64_SUPPORT
>> 1549 help
>> 1550 Choose this option to build a kernel for MIPS Warrior P5600 CPU.
>> 1551 It's based on MIPS32r5 ISA with XPA, EVA, dual/quad issue exec pipes,
>> 1552 MMU with two-levels TLB, UCA, MSA, MDU core level features and system
>> 1553 level features like up to six P5600 calculation cores, CM2 with L2
>> 1554 cache, IOCU/IOMMU (though might be unused depending on the system-
>> 1555 specific IP core configuration), GIC, CPC, virtualisation module,
>> 1556 eJTAG and PDtrace.
>> 1557
>> 1558 config CPU_R3000
>> 1559 bool "R3000"
>> 1560 depends on SYS_HAS_CPU_R3000
>> 1561 select CPU_HAS_WB
>> 1562 select CPU_R3K_TLB
>> 1563 select CPU_SUPPORTS_32BIT_KERNEL
>> 1564 select CPU_SUPPORTS_HIGHMEM
>> 1565 help
>> 1566 Please make sure to pick the right CPU type. Linux/MIPS is not
>> 1567 designed to be generic, i.e. Kernels compiled for R3000 CPUs will
>> 1568 *not* work on R4000 machines and vice versa. However, since most
>> 1569 of the supported machines have an R4000 (or similar) CPU, R4x00
>> 1570 might be a safe bet. If the resulting kernel does not work,
>> 1571 try to recompile with R3000.
>> 1572
>> 1573 config CPU_R4300
>> 1574 bool "R4300"
>> 1575 depends on SYS_HAS_CPU_R4300
>> 1576 select CPU_SUPPORTS_32BIT_KERNEL
>> 1577 select CPU_SUPPORTS_64BIT_KERNEL
>> 1578 help
>> 1579 MIPS Technologies R4300-series processors.
>> 1580
>> 1581 config CPU_R4X00
>> 1582 bool "R4x00"
>> 1583 depends on SYS_HAS_CPU_R4X00
>> 1584 select CPU_SUPPORTS_32BIT_KERNEL
>> 1585 select CPU_SUPPORTS_64BIT_KERNEL
>> 1586 select CPU_SUPPORTS_HUGEPAGES
>> 1587 help
>> 1588 MIPS Technologies R4000-series processors other than 4300, including
>> 1589 the R4000, R4400, R4600, and 4700.
>> 1590
>> 1591 config CPU_TX49XX
>> 1592 bool "R49XX"
>> 1593 depends on SYS_HAS_CPU_TX49XX
>> 1594 select CPU_HAS_PREFETCH
>> 1595 select CPU_SUPPORTS_32BIT_KERNEL
>> 1596 select CPU_SUPPORTS_64BIT_KERNEL
>> 1597 select CPU_SUPPORTS_HUGEPAGES
>> 1598
>> 1599 config CPU_R5000
>> 1600 bool "R5000"
>> 1601 depends on SYS_HAS_CPU_R5000
>> 1602 select CPU_SUPPORTS_32BIT_KERNEL
>> 1603 select CPU_SUPPORTS_64BIT_KERNEL
>> 1604 select CPU_SUPPORTS_HUGEPAGES
>> 1605 help
>> 1606 MIPS Technologies R5000-series processors other than the Nevada.
>> 1607
>> 1608 config CPU_R5500
>> 1609 bool "R5500"
>> 1610 depends on SYS_HAS_CPU_R5500
>> 1611 select CPU_SUPPORTS_32BIT_KERNEL
>> 1612 select CPU_SUPPORTS_64BIT_KERNEL
>> 1613 select CPU_SUPPORTS_HUGEPAGES
>> 1614 help
>> 1615 NEC VR5500 and VR5500A series processors implement 64-bit MIPS IV
>> 1616 instruction set.
>> 1617
>> 1618 config CPU_NEVADA
>> 1619 bool "RM52xx"
>> 1620 depends on SYS_HAS_CPU_NEVADA
>> 1621 select CPU_SUPPORTS_32BIT_KERNEL
>> 1622 select CPU_SUPPORTS_64BIT_KERNEL
>> 1623 select CPU_SUPPORTS_HUGEPAGES
>> 1624 help
>> 1625 QED / PMC-Sierra RM52xx-series ("Nevada") processors.
>> 1626
>> 1627 config CPU_R10000
>> 1628 bool "R10000"
>> 1629 depends on SYS_HAS_CPU_R10000
>> 1630 select CPU_HAS_PREFETCH
>> 1631 select CPU_SUPPORTS_32BIT_KERNEL
>> 1632 select CPU_SUPPORTS_64BIT_KERNEL
>> 1633 select CPU_SUPPORTS_HIGHMEM
>> 1634 select CPU_SUPPORTS_HUGEPAGES
>> 1635 help
>> 1636 MIPS Technologies R10000-series processors.
>> 1637
>> 1638 config CPU_RM7000
>> 1639 bool "RM7000"
>> 1640 depends on SYS_HAS_CPU_RM7000
>> 1641 select CPU_HAS_PREFETCH
>> 1642 select CPU_SUPPORTS_32BIT_KERNEL
>> 1643 select CPU_SUPPORTS_64BIT_KERNEL
>> 1644 select CPU_SUPPORTS_HIGHMEM
>> 1645 select CPU_SUPPORTS_HUGEPAGES
>> 1646
>> 1647 config CPU_SB1
>> 1648 bool "SB1"
>> 1649 depends on SYS_HAS_CPU_SB1
>> 1650 select CPU_SUPPORTS_32BIT_KERNEL
>> 1651 select CPU_SUPPORTS_64BIT_KERNEL
>> 1652 select CPU_SUPPORTS_HIGHMEM
>> 1653 select CPU_SUPPORTS_HUGEPAGES
>> 1654 select WEAK_ORDERING
>> 1655
>> 1656 config CPU_CAVIUM_OCTEON
>> 1657 bool "Cavium Octeon processor"
>> 1658 depends on SYS_HAS_CPU_CAVIUM_OCTEON
>> 1659 select CPU_HAS_PREFETCH
>> 1660 select CPU_SUPPORTS_64BIT_KERNEL
>> 1661 select WEAK_ORDERING
>> 1662 select CPU_SUPPORTS_HIGHMEM
>> 1663 select CPU_SUPPORTS_HUGEPAGES
>> 1664 select USB_EHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 1665 select USB_OHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 1666 select MIPS_L1_CACHE_SHIFT_7
>> 1667 select HAVE_KVM
>> 1668 help
>> 1669 The Cavium Octeon processor is a highly integrated chip containing
>> 1670 many ethernet hardware widgets for networking tasks. The processor
>> 1671 can have up to 16 Mips64v2 cores and 8 integrated gigabit ethernets.
>> 1672 Full details can be found at http://www.caviumnetworks.com.
>> 1673
>> 1674 config CPU_BMIPS
>> 1675 bool "Broadcom BMIPS"
>> 1676 depends on SYS_HAS_CPU_BMIPS
>> 1677 select CPU_MIPS32
>> 1678 select CPU_BMIPS32_3300 if SYS_HAS_CPU_BMIPS32_3300
>> 1679 select CPU_BMIPS4350 if SYS_HAS_CPU_BMIPS4350
>> 1680 select CPU_BMIPS4380 if SYS_HAS_CPU_BMIPS4380
>> 1681 select CPU_BMIPS5000 if SYS_HAS_CPU_BMIPS5000
>> 1682 select CPU_SUPPORTS_32BIT_KERNEL
>> 1683 select DMA_NONCOHERENT
>> 1684 select IRQ_MIPS_CPU
>> 1685 select SWAP_IO_SPACE
>> 1686 select WEAK_ORDERING
>> 1687 select CPU_SUPPORTS_HIGHMEM
>> 1688 select CPU_HAS_PREFETCH
>> 1689 select CPU_SUPPORTS_CPUFREQ
>> 1690 select MIPS_EXTERNAL_TIMER
>> 1691 select GENERIC_IRQ_MIGRATION if HOTPLUG_CPU
>> 1692 help
>> 1693 Support for BMIPS32/3300/4350/4380 and BMIPS5000 processors.
837 1694
838 If unsure, say Y. !! 1695 endchoice
839 1696
840 config ARM64_ERRATUM_2119858 !! 1697 config CPU_MIPS32_3_5_FEATURES
841 bool "Cortex-A710/X2: 2119858: workaro !! 1698 bool "MIPS32 Release 3.5 Features"
842 default y !! 1699 depends on SYS_HAS_CPU_MIPS32_R3_5
843 depends on CORESIGHT_TRBE !! 1700 depends on CPU_MIPS32_R2 || CPU_MIPS32_R5 || CPU_MIPS32_R6 || \
844 select ARM64_WORKAROUND_TRBE_OVERWRITE !! 1701 CPU_P5600
>> 1702 help
>> 1703 Choose this option to build a kernel for release 2 or later of the
>> 1704 MIPS32 architecture including features from the 3.5 release such as
>> 1705 support for Enhanced Virtual Addressing (EVA).
>> 1706
>> 1707 config CPU_MIPS32_3_5_EVA
>> 1708 bool "Enhanced Virtual Addressing (EVA)"
>> 1709 depends on CPU_MIPS32_3_5_FEATURES
>> 1710 select EVA
>> 1711 default y
>> 1712 help
>> 1713 Choose this option if you want to enable the Enhanced Virtual
>> 1714 Addressing (EVA) on your MIPS32 core (such as proAptiv).
>> 1715 One of its primary benefits is an increase in the maximum size
>> 1716 of lowmem (up to 3GB). If unsure, say 'N' here.
>> 1717
>> 1718 config CPU_MIPS32_R5_FEATURES
>> 1719 bool "MIPS32 Release 5 Features"
>> 1720 depends on SYS_HAS_CPU_MIPS32_R5
>> 1721 depends on CPU_MIPS32_R2 || CPU_MIPS32_R5 || CPU_P5600
>> 1722 help
>> 1723 Choose this option to build a kernel for release 2 or later of the
>> 1724 MIPS32 architecture including features from release 5 such as
>> 1725 support for Extended Physical Addressing (XPA).
>> 1726
>> 1727 config CPU_MIPS32_R5_XPA
>> 1728 bool "Extended Physical Addressing (XPA)"
>> 1729 depends on CPU_MIPS32_R5_FEATURES
>> 1730 depends on !EVA
>> 1731 depends on !PAGE_SIZE_4KB
>> 1732 depends on SYS_SUPPORTS_HIGHMEM
>> 1733 select XPA
>> 1734 select HIGHMEM
>> 1735 select PHYS_ADDR_T_64BIT
>> 1736 default n
845 help 1737 help
846 This option adds the workaround for !! 1738 Choose this option if you want to enable the Extended Physical
>> 1739 Addressing (XPA) on your MIPS32 core (such as P5600 series). The
>> 1740 benefit is to increase physical addressing equal to or greater
>> 1741 than 40 bits. Note that this has the side effect of turning on
>> 1742 64-bit addressing which in turn makes the PTEs 64-bit in size.
>> 1743 If unsure, say 'N' here.
847 1744
848 Affected Cortex-A710/X2 cores could !! 1745 if CPU_LOONGSON2F
849 data at the base of the buffer (poin !! 1746 config CPU_NOP_WORKAROUNDS
850 the event of a WRAP event. !! 1747 bool
851 <<
852 Work around the issue by always maki <<
853 256 bytes before enabling the buffer <<
854 the buffer with ETM ignore packets u <<
855 1748
856 If unsure, say Y. !! 1749 config CPU_JUMP_WORKAROUNDS
>> 1750 bool
857 1751
858 config ARM64_ERRATUM_2139208 !! 1752 config CPU_LOONGSON2F_WORKAROUNDS
859 bool "Neoverse-N2: 2139208: workaround !! 1753 bool "Loongson 2F Workarounds"
860 default y 1754 default y
861 depends on CORESIGHT_TRBE !! 1755 select CPU_NOP_WORKAROUNDS
862 select ARM64_WORKAROUND_TRBE_OVERWRITE !! 1756 select CPU_JUMP_WORKAROUNDS
863 help 1757 help
864 This option adds the workaround for !! 1758 Loongson 2F01 / 2F02 processors have the NOP & JUMP issues which
>> 1759 require workarounds. Without workarounds the system may hang
>> 1760 unexpectedly. For more information please refer to the gas
>> 1761 -mfix-loongson2f-nop and -mfix-loongson2f-jump options.
>> 1762
>> 1763 Loongson 2F03 and later have fixed these issues and no workarounds
>> 1764 are needed. The workarounds have no significant side effect on them
>> 1765 but may decrease the performance of the system so this option should
>> 1766 be disabled unless the kernel is intended to be run on 2F01 or 2F02
>> 1767 systems.
865 1768
866 Affected Neoverse-N2 cores could ove !! 1769 If unsure, please say Y.
867 data at the base of the buffer (poin !! 1770 endif # CPU_LOONGSON2F
868 the event of a WRAP event. <<
869 <<
870 Work around the issue by always maki <<
871 256 bytes before enabling the buffer <<
872 the buffer with ETM ignore packets u <<
873 1771
874 If unsure, say Y. !! 1772 config SYS_SUPPORTS_ZBOOT
875 <<
876 config ARM64_WORKAROUND_TSB_FLUSH_FAILURE <<
877 bool 1773 bool
>> 1774 select HAVE_KERNEL_GZIP
>> 1775 select HAVE_KERNEL_BZIP2
>> 1776 select HAVE_KERNEL_LZ4
>> 1777 select HAVE_KERNEL_LZMA
>> 1778 select HAVE_KERNEL_LZO
>> 1779 select HAVE_KERNEL_XZ
>> 1780 select HAVE_KERNEL_ZSTD
878 1781
879 config ARM64_ERRATUM_2054223 !! 1782 config SYS_SUPPORTS_ZBOOT_UART16550
880 bool "Cortex-A710: 2054223: workaround !! 1783 bool
881 default y !! 1784 select SYS_SUPPORTS_ZBOOT
882 select ARM64_WORKAROUND_TSB_FLUSH_FAIL <<
883 help <<
884 Enable workaround for ARM Cortex-A71 <<
885 1785
886 Affected cores may fail to flush the !! 1786 config SYS_SUPPORTS_ZBOOT_UART_PROM
887 the PE is in trace prohibited state. !! 1787 bool
888 of the trace cached. !! 1788 select SYS_SUPPORTS_ZBOOT
889 1789
890 Workaround is to issue two TSB conse !! 1790 config CPU_LOONGSON2EF
>> 1791 bool
>> 1792 select CPU_SUPPORTS_32BIT_KERNEL
>> 1793 select CPU_SUPPORTS_64BIT_KERNEL
>> 1794 select CPU_SUPPORTS_HIGHMEM
>> 1795 select CPU_SUPPORTS_HUGEPAGES
>> 1796 select ARCH_HAS_PHYS_TO_DMA
891 1797
892 If unsure, say Y. !! 1798 config CPU_LOONGSON32
>> 1799 bool
>> 1800 select CPU_MIPS32
>> 1801 select CPU_MIPSR2
>> 1802 select CPU_HAS_PREFETCH
>> 1803 select CPU_SUPPORTS_32BIT_KERNEL
>> 1804 select CPU_SUPPORTS_HIGHMEM
>> 1805 select CPU_SUPPORTS_CPUFREQ
893 1806
894 config ARM64_ERRATUM_2067961 !! 1807 config CPU_BMIPS32_3300
895 bool "Neoverse-N2: 2067961: workaround !! 1808 select SMP_UP if SMP
896 default y !! 1809 bool
897 select ARM64_WORKAROUND_TSB_FLUSH_FAIL <<
898 help <<
899 Enable workaround for ARM Neoverse-N <<
900 1810
901 Affected cores may fail to flush the !! 1811 config CPU_BMIPS4350
902 the PE is in trace prohibited state. !! 1812 bool
903 of the trace cached. !! 1813 select SYS_SUPPORTS_SMP
>> 1814 select SYS_SUPPORTS_HOTPLUG_CPU
904 1815
905 Workaround is to issue two TSB conse !! 1816 config CPU_BMIPS4380
>> 1817 bool
>> 1818 select MIPS_L1_CACHE_SHIFT_6
>> 1819 select SYS_SUPPORTS_SMP
>> 1820 select SYS_SUPPORTS_HOTPLUG_CPU
>> 1821 select CPU_HAS_RIXI
906 1822
907 If unsure, say Y. !! 1823 config CPU_BMIPS5000
>> 1824 bool
>> 1825 select MIPS_CPU_SCACHE
>> 1826 select MIPS_L1_CACHE_SHIFT_7
>> 1827 select SYS_SUPPORTS_SMP
>> 1828 select SYS_SUPPORTS_HOTPLUG_CPU
>> 1829 select CPU_HAS_RIXI
908 1830
909 config ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANG !! 1831 config SYS_HAS_CPU_LOONGSON64
910 bool 1832 bool
>> 1833 select CPU_SUPPORTS_CPUFREQ
>> 1834 select CPU_HAS_RIXI
911 1835
912 config ARM64_ERRATUM_2253138 !! 1836 config SYS_HAS_CPU_LOONGSON2E
913 bool "Neoverse-N2: 2253138: workaround !! 1837 bool
914 depends on CORESIGHT_TRBE <<
915 default y <<
916 select ARM64_WORKAROUND_TRBE_WRITE_OUT <<
917 help <<
918 This option adds the workaround for <<
919 1838
920 Affected Neoverse-N2 cores might wri !! 1839 config SYS_HAS_CPU_LOONGSON2F
921 for TRBE. Under some conditions, the !! 1840 bool
922 virtually addressed page following t !! 1841 select CPU_SUPPORTS_CPUFREQ
923 (i.e., the TRBLIMITR_EL1.LIMIT), ins !! 1842 select CPU_SUPPORTS_ADDRWINCFG if 64BIT
924 1843
925 Work around this in the driver by al !! 1844 config SYS_HAS_CPU_LOONGSON1B
926 page beyond the TRBLIMITR_EL1.LIMIT, !! 1845 bool
927 1846
928 If unsure, say Y. !! 1847 config SYS_HAS_CPU_LOONGSON1C
>> 1848 bool
929 1849
930 config ARM64_ERRATUM_2224489 !! 1850 config SYS_HAS_CPU_MIPS32_R1
931 bool "Cortex-A710/X2: 2224489: workaro !! 1851 bool
932 depends on CORESIGHT_TRBE <<
933 default y <<
934 select ARM64_WORKAROUND_TRBE_WRITE_OUT <<
935 help <<
936 This option adds the workaround for <<
937 1852
938 Affected Cortex-A710/X2 cores might !! 1853 config SYS_HAS_CPU_MIPS32_R2
939 for TRBE. Under some conditions, the !! 1854 bool
940 virtually addressed page following t <<
941 (i.e., the TRBLIMITR_EL1.LIMIT), ins <<
942 1855
943 Work around this in the driver by al !! 1856 config SYS_HAS_CPU_MIPS32_R3_5
944 page beyond the TRBLIMITR_EL1.LIMIT, !! 1857 bool
945 1858
946 If unsure, say Y. !! 1859 config SYS_HAS_CPU_MIPS32_R5
>> 1860 bool
>> 1861 select ARCH_HAS_SYNC_DMA_FOR_CPU if DMA_NONCOHERENT
947 1862
948 config ARM64_ERRATUM_2441009 !! 1863 config SYS_HAS_CPU_MIPS32_R6
949 bool "Cortex-A510: Completion of affec !! 1864 bool
950 select ARM64_WORKAROUND_REPEAT_TLBI !! 1865 select ARCH_HAS_SYNC_DMA_FOR_CPU if DMA_NONCOHERENT
951 help <<
952 This option adds a workaround for AR <<
953 <<
954 Under very rare circumstances, affec <<
955 may not handle a race between a brea <<
956 CPU, and another CPU accessing the s <<
957 store to a page that has been unmapp <<
958 1866
959 Work around this by adding the affec !! 1867 config SYS_HAS_CPU_MIPS64_R1
960 TLB sequences to be done twice. !! 1868 bool
961 1869
962 If unsure, say N. !! 1870 config SYS_HAS_CPU_MIPS64_R2
>> 1871 bool
963 1872
964 config ARM64_ERRATUM_2064142 !! 1873 config SYS_HAS_CPU_MIPS64_R5
965 bool "Cortex-A510: 2064142: workaround !! 1874 bool
966 depends on CORESIGHT_TRBE !! 1875 select ARCH_HAS_SYNC_DMA_FOR_CPU if DMA_NONCOHERENT
967 default y <<
968 help <<
969 This option adds the workaround for <<
970 1876
971 Affected Cortex-A510 core might fail !! 1877 config SYS_HAS_CPU_MIPS64_R6
972 TRBE has been disabled. Under some c !! 1878 bool
973 writes into TRBE registers TRBLIMITR !! 1879 select ARCH_HAS_SYNC_DMA_FOR_CPU if DMA_NONCOHERENT
974 and TRBTRG_EL1 will be ignored and w <<
975 <<
976 Work around this in the driver by ex <<
977 is stopped and before performing a s <<
978 registers. <<
979 1880
980 If unsure, say Y. !! 1881 config SYS_HAS_CPU_P5600
>> 1882 bool
>> 1883 select ARCH_HAS_SYNC_DMA_FOR_CPU if DMA_NONCOHERENT
981 1884
982 config ARM64_ERRATUM_2038923 !! 1885 config SYS_HAS_CPU_R3000
983 bool "Cortex-A510: 2038923: workaround !! 1886 bool
984 depends on CORESIGHT_TRBE <<
985 default y <<
986 help <<
987 This option adds the workaround for <<
988 1887
989 Affected Cortex-A510 core might caus !! 1888 config SYS_HAS_CPU_R4300
990 prohibited within the CPU. As a resu !! 1889 bool
991 might be corrupted. This happens aft <<
992 TRBLIMITR_EL1.E, followed by just a <<
993 execution changes from a context, in <<
994 isn't, or vice versa. In these menti <<
995 is prohibited is inconsistent betwee <<
996 the trace buffer state might be corr <<
997 <<
998 Work around this in the driver by pr <<
999 trace is prohibited or not based on <<
1000 change to TRBLIMITR_EL1.E with at l <<
1001 two ISB instructions if no ERET is <<
1002 1890
1003 If unsure, say Y. !! 1891 config SYS_HAS_CPU_R4X00
>> 1892 bool
1004 1893
1005 config ARM64_ERRATUM_1902691 !! 1894 config SYS_HAS_CPU_TX49XX
1006 bool "Cortex-A510: 1902691: workaroun !! 1895 bool
1007 depends on CORESIGHT_TRBE <<
1008 default y <<
1009 help <<
1010 This option adds the workaround for <<
1011 1896
1012 Affected Cortex-A510 core might cau !! 1897 config SYS_HAS_CPU_R5000
1013 into the memory. Effectively TRBE i !! 1898 bool
1014 trace data. <<
1015 <<
1016 Work around this problem in the dri <<
1017 affected cpus. The firmware must ha <<
1018 on such implementations. This will <<
1019 do this already. <<
1020 1899
1021 If unsure, say Y. !! 1900 config SYS_HAS_CPU_R5500
>> 1901 bool
1022 1902
1023 config ARM64_ERRATUM_2457168 !! 1903 config SYS_HAS_CPU_NEVADA
1024 bool "Cortex-A510: 2457168: workaroun !! 1904 bool
1025 depends on ARM64_AMU_EXTN <<
1026 default y <<
1027 help <<
1028 This option adds the workaround for <<
1029 1905
1030 The AMU counter AMEVCNTR01 (constan !! 1906 config SYS_HAS_CPU_R10000
1031 as the system counter. On affected !! 1907 bool
1032 incorrectly giving a significantly !! 1908 select ARCH_HAS_SYNC_DMA_FOR_CPU if DMA_NONCOHERENT
1033 <<
1034 Work around this problem by returni <<
1035 key locations that results in disab <<
1036 is the same to firmware disabling a <<
1037 1909
1038 If unsure, say Y. !! 1910 config SYS_HAS_CPU_RM7000
>> 1911 bool
1039 1912
1040 config ARM64_ERRATUM_2645198 !! 1913 config SYS_HAS_CPU_SB1
1041 bool "Cortex-A715: 2645198: Workaroun !! 1914 bool
1042 default y <<
1043 help <<
1044 This option adds the workaround for <<
1045 1915
1046 If a Cortex-A715 cpu sees a page ma !! 1916 config SYS_HAS_CPU_CAVIUM_OCTEON
1047 to non-executable, it may corrupt t !! 1917 bool
1048 next instruction abort caused by pe <<
1049 <<
1050 Only user-space does executable to <<
1051 mprotect() system call. Workaround <<
1052 TLB invalidation, for all changes t <<
1053 1918
1054 If unsure, say Y. !! 1919 config SYS_HAS_CPU_BMIPS
>> 1920 bool
1055 1921
1056 config ARM64_WORKAROUND_SPECULATIVE_UNPRIV_LO !! 1922 config SYS_HAS_CPU_BMIPS32_3300
1057 bool 1923 bool
>> 1924 select SYS_HAS_CPU_BMIPS
1058 1925
1059 config ARM64_ERRATUM_2966298 !! 1926 config SYS_HAS_CPU_BMIPS4350
1060 bool "Cortex-A520: 2966298: workaroun !! 1927 bool
1061 select ARM64_WORKAROUND_SPECULATIVE_U !! 1928 select SYS_HAS_CPU_BMIPS
1062 default y <<
1063 help <<
1064 This option adds the workaround for <<
1065 1929
1066 On an affected Cortex-A520 core, a !! 1930 config SYS_HAS_CPU_BMIPS4380
1067 load might leak data from a privile !! 1931 bool
>> 1932 select SYS_HAS_CPU_BMIPS
1068 1933
1069 Work around this problem by executi !! 1934 config SYS_HAS_CPU_BMIPS5000
>> 1935 bool
>> 1936 select SYS_HAS_CPU_BMIPS
>> 1937 select ARCH_HAS_SYNC_DMA_FOR_CPU
1070 1938
1071 If unsure, say Y. !! 1939 #
>> 1940 # CPU may reorder R->R, R->W, W->R, W->W
>> 1941 # Reordering beyond LL and SC is handled in WEAK_REORDERING_BEYOND_LLSC
>> 1942 #
>> 1943 config WEAK_ORDERING
>> 1944 bool
1072 1945
1073 config ARM64_ERRATUM_3117295 !! 1946 #
1074 bool "Cortex-A510: 3117295: workaroun !! 1947 # CPU may reorder reads and writes beyond LL/SC
1075 select ARM64_WORKAROUND_SPECULATIVE_U !! 1948 # CPU may reorder R->LL, R->LL, W->LL, W->LL, R->SC, R->SC, W->SC, W->SC
1076 default y !! 1949 #
1077 help !! 1950 config WEAK_REORDERING_BEYOND_LLSC
1078 This option adds the workaround for !! 1951 bool
>> 1952 endmenu
1079 1953
1080 On an affected Cortex-A510 core, a !! 1954 #
1081 load might leak data from a privile !! 1955 # These two indicate any level of the MIPS32 and MIPS64 architecture
>> 1956 #
>> 1957 config CPU_MIPS32
>> 1958 bool
>> 1959 default y if CPU_MIPS32_R1 || CPU_MIPS32_R2 || CPU_MIPS32_R5 || \
>> 1960 CPU_MIPS32_R6 || CPU_P5600
1082 1961
1083 Work around this problem by executi !! 1962 config CPU_MIPS64
>> 1963 bool
>> 1964 default y if CPU_MIPS64_R1 || CPU_MIPS64_R2 || CPU_MIPS64_R5 || \
>> 1965 CPU_MIPS64_R6 || CPU_LOONGSON64 || CPU_CAVIUM_OCTEON
1084 1966
1085 If unsure, say Y. !! 1967 #
>> 1968 # These indicate the revision of the architecture
>> 1969 #
>> 1970 config CPU_MIPSR1
>> 1971 bool
>> 1972 default y if CPU_MIPS32_R1 || CPU_MIPS64_R1
1086 1973
1087 config ARM64_ERRATUM_3194386 !! 1974 config CPU_MIPSR2
1088 bool "Cortex-*/Neoverse-*: workaround !! 1975 bool
1089 default y !! 1976 default y if CPU_MIPS32_R2 || CPU_MIPS64_R2 || CPU_CAVIUM_OCTEON
1090 help !! 1977 select CPU_HAS_RIXI
1091 This option adds the workaround for !! 1978 select CPU_HAS_DIEI if !CPU_DIEI_BROKEN
>> 1979 select MIPS_SPRAM
1092 1980
1093 * ARM Cortex-A76 erratum 3324349 !! 1981 config CPU_MIPSR5
1094 * ARM Cortex-A77 erratum 3324348 !! 1982 bool
1095 * ARM Cortex-A78 erratum 3324344 !! 1983 default y if CPU_MIPS32_R5 || CPU_MIPS64_R5 || CPU_P5600
1096 * ARM Cortex-A78C erratum 3324346 !! 1984 select CPU_HAS_RIXI
1097 * ARM Cortex-A78C erratum 3324347 !! 1985 select CPU_HAS_DIEI if !CPU_DIEI_BROKEN
1098 * ARM Cortex-A710 erratam 3324338 !! 1986 select MIPS_SPRAM
1099 * ARM Cortex-A715 errartum 3456084 <<
1100 * ARM Cortex-A720 erratum 3456091 <<
1101 * ARM Cortex-A725 erratum 3456106 <<
1102 * ARM Cortex-X1 erratum 3324344 <<
1103 * ARM Cortex-X1C erratum 3324346 <<
1104 * ARM Cortex-X2 erratum 3324338 <<
1105 * ARM Cortex-X3 erratum 3324335 <<
1106 * ARM Cortex-X4 erratum 3194386 <<
1107 * ARM Cortex-X925 erratum 3324334 <<
1108 * ARM Neoverse-N1 erratum 3324349 <<
1109 * ARM Neoverse N2 erratum 3324339 <<
1110 * ARM Neoverse-N3 erratum 3456111 <<
1111 * ARM Neoverse-V1 erratum 3324341 <<
1112 * ARM Neoverse V2 erratum 3324336 <<
1113 * ARM Neoverse-V3 erratum 3312417 <<
1114 <<
1115 On affected cores "MSR SSBS, #0" in <<
1116 subsequent speculative instructions <<
1117 speculative store bypassing. <<
1118 <<
1119 Work around this problem by placing <<
1120 Instruction Synchronization Barrier <<
1121 SSBS. The presence of the SSBS spec <<
1122 from hwcaps and EL0 reads of ID_AA6 <<
1123 will use the PR_SPEC_STORE_BYPASS p <<
1124 1987
1125 If unsure, say Y. !! 1988 config CPU_MIPSR6
>> 1989 bool
>> 1990 default y if CPU_MIPS32_R6 || CPU_MIPS64_R6
>> 1991 select CPU_HAS_RIXI
>> 1992 select CPU_HAS_DIEI if !CPU_DIEI_BROKEN
>> 1993 select HAVE_ARCH_BITREVERSE
>> 1994 select MIPS_ASID_BITS_VARIABLE
>> 1995 select MIPS_CRC_SUPPORT
>> 1996 select MIPS_SPRAM
1126 1997
1127 config CAVIUM_ERRATUM_22375 !! 1998 config TARGET_ISA_REV
1128 bool "Cavium erratum 22375, 24313" !! 1999 int
1129 default y !! 2000 default 1 if CPU_MIPSR1
>> 2001 default 2 if CPU_MIPSR2
>> 2002 default 5 if CPU_MIPSR5
>> 2003 default 6 if CPU_MIPSR6
>> 2004 default 0
1130 help 2005 help
1131 Enable workaround for errata 22375 !! 2006 Reflects the ISA revision being targeted by the kernel build. This
>> 2007 is effectively the Kconfig equivalent of MIPS_ISA_REV.
1132 2008
1133 This implements two gicv3-its errat !! 2009 config EVA
1134 with a small impact affecting only !! 2010 bool
1135 2011
1136 erratum 22375: only alloc 8MB tab !! 2012 config XPA
1137 erratum 24313: ignore memory acce !! 2013 bool
1138 2014
1139 The fixes are in ITS initialization !! 2015 config SYS_SUPPORTS_32BIT_KERNEL
1140 type and table size provided by the !! 2016 bool
>> 2017 config SYS_SUPPORTS_64BIT_KERNEL
>> 2018 bool
>> 2019 config CPU_SUPPORTS_32BIT_KERNEL
>> 2020 bool
>> 2021 config CPU_SUPPORTS_64BIT_KERNEL
>> 2022 bool
>> 2023 config CPU_SUPPORTS_CPUFREQ
>> 2024 bool
>> 2025 config CPU_SUPPORTS_ADDRWINCFG
>> 2026 bool
>> 2027 config CPU_SUPPORTS_HUGEPAGES
>> 2028 bool
>> 2029 depends on !(32BIT && (PHYS_ADDR_T_64BIT || EVA))
>> 2030 config MIPS_PGD_C0_CONTEXT
>> 2031 bool
>> 2032 depends on 64BIT
>> 2033 default y if (CPU_MIPSR2 || CPU_MIPSR6)
1141 2034
1142 If unsure, say Y. !! 2035 #
>> 2036 # Set to y for ptrace access to watch registers.
>> 2037 #
>> 2038 config HARDWARE_WATCHPOINTS
>> 2039 bool
>> 2040 default y if CPU_MIPSR1 || CPU_MIPSR2 || CPU_MIPSR6
1143 2041
1144 config CAVIUM_ERRATUM_23144 !! 2042 menu "Kernel type"
1145 bool "Cavium erratum 23144: ITS SYNC <<
1146 depends on NUMA <<
1147 default y <<
1148 help <<
1149 ITS SYNC command hang for cross nod <<
1150 2043
1151 If unsure, say Y. !! 2044 choice
>> 2045 prompt "Kernel code model"
>> 2046 help
>> 2047 You should only select this option if you have a workload that
>> 2048 actually benefits from 64-bit processing or if your machine has
>> 2049 large memory. You will only be presented a single option in this
>> 2050 menu if your system does not support both 32-bit and 64-bit kernels.
>> 2051
>> 2052 config 32BIT
>> 2053 bool "32-bit kernel"
>> 2054 depends on CPU_SUPPORTS_32BIT_KERNEL && SYS_SUPPORTS_32BIT_KERNEL
>> 2055 select TRAD_SIGNALS
>> 2056 help
>> 2057 Select this option if you want to build a 32-bit kernel.
1152 2058
1153 config CAVIUM_ERRATUM_23154 !! 2059 config 64BIT
1154 bool "Cavium errata 23154 and 38545: !! 2060 bool "64-bit kernel"
1155 default y !! 2061 depends on CPU_SUPPORTS_64BIT_KERNEL && SYS_SUPPORTS_64BIT_KERNEL
1156 help 2062 help
1157 The ThunderX GICv3 implementation r !! 2063 Select this option if you want to build a 64-bit kernel.
1158 reading the IAR status to ensure da <<
1159 (access to icc_iar1_el1 is not sync <<
1160 <<
1161 It also suffers from erratum 38545 <<
1162 OcteonTX and OcteonTX2), resulting <<
1163 spuriously presented to the CPU int <<
1164 2064
1165 If unsure, say Y. !! 2065 endchoice
1166 2066
1167 config CAVIUM_ERRATUM_27456 !! 2067 config MIPS_VA_BITS_48
1168 bool "Cavium erratum 27456: Broadcast !! 2068 bool "48 bits virtual memory"
1169 default y !! 2069 depends on 64BIT
1170 help !! 2070 help
1171 On ThunderX T88 pass 1.x through 2. !! 2071 Support a maximum at least 48 bits of application virtual
1172 instructions may cause the icache t !! 2072 memory. Default is 40 bits or less, depending on the CPU.
1173 contains data for a non-current ASI !! 2073 For page sizes 16k and above, this option results in a small
1174 invalidate the icache when changing !! 2074 memory overhead for page tables. For 4k page size, a fourth
>> 2075 level of page tables is added which imposes both a memory
>> 2076 overhead as well as slower TLB fault handling.
1175 2077
1176 If unsure, say Y. !! 2078 If unsure, say N.
1177 2079
1178 config CAVIUM_ERRATUM_30115 !! 2080 config ZBOOT_LOAD_ADDRESS
1179 bool "Cavium erratum 30115: Guest may !! 2081 hex "Compressed kernel load address"
1180 default y !! 2082 default 0xffffffff80400000 if BCM47XX
>> 2083 default 0x0
>> 2084 depends on SYS_SUPPORTS_ZBOOT
1181 help 2085 help
1182 On ThunderX T88 pass 1.x through 2. !! 2086 The address to load compressed kernel, aka vmlinuz.
1183 1.2, and T83 Pass 1.0, KVM guest ex <<
1184 interrupts in host. Trapping both G <<
1185 accesses sidesteps the issue. <<
1186 2087
1187 If unsure, say Y. !! 2088 This is only used if non-zero.
1188 2089
1189 config CAVIUM_TX2_ERRATUM_219 !! 2090 choice
1190 bool "Cavium ThunderX2 erratum 219: P !! 2091 prompt "Kernel page size"
1191 default y !! 2092 default PAGE_SIZE_4KB
1192 help <<
1193 On Cavium ThunderX2, a load, store <<
1194 TTBR update and the corresponding c <<
1195 cause a spurious Data Abort to be d <<
1196 the CPU core. <<
1197 <<
1198 Work around the issue by avoiding t <<
1199 trapping KVM guest TTBRx_EL1 writes <<
1200 trap handler performs the correspon <<
1201 instruction and ensures context syn <<
1202 exception return. <<
1203 2093
1204 If unsure, say Y. !! 2094 config PAGE_SIZE_4KB
>> 2095 bool "4kB"
>> 2096 depends on !CPU_LOONGSON2EF && !CPU_LOONGSON64
>> 2097 help
>> 2098 This option select the standard 4kB Linux page size. On some
>> 2099 R3000-family processors this is the only available page size. Using
>> 2100 4kB page size will minimize memory consumption and is therefore
>> 2101 recommended for low memory systems.
>> 2102
>> 2103 config PAGE_SIZE_8KB
>> 2104 bool "8kB"
>> 2105 depends on CPU_CAVIUM_OCTEON
>> 2106 depends on !MIPS_VA_BITS_48
>> 2107 help
>> 2108 Using 8kB page size will result in higher performance kernel at
>> 2109 the price of higher memory consumption. This option is available
>> 2110 only on cnMIPS processors. Note that you will need a suitable Linux
>> 2111 distribution to support this.
>> 2112
>> 2113 config PAGE_SIZE_16KB
>> 2114 bool "16kB"
>> 2115 depends on !CPU_R3000
>> 2116 help
>> 2117 Using 16kB page size will result in higher performance kernel at
>> 2118 the price of higher memory consumption. This option is available on
>> 2119 all non-R3000 family processors. Note that you will need a suitable
>> 2120 Linux distribution to support this.
>> 2121
>> 2122 config PAGE_SIZE_32KB
>> 2123 bool "32kB"
>> 2124 depends on CPU_CAVIUM_OCTEON
>> 2125 depends on !MIPS_VA_BITS_48
>> 2126 help
>> 2127 Using 32kB page size will result in higher performance kernel at
>> 2128 the price of higher memory consumption. This option is available
>> 2129 only on cnMIPS cores. Note that you will need a suitable Linux
>> 2130 distribution to support this.
>> 2131
>> 2132 config PAGE_SIZE_64KB
>> 2133 bool "64kB"
>> 2134 depends on !CPU_R3000
>> 2135 help
>> 2136 Using 64kB page size will result in higher performance kernel at
>> 2137 the price of higher memory consumption. This option is available on
>> 2138 all non-R3000 family processor. Not that at the time of this
>> 2139 writing this option is still high experimental.
1205 2140
1206 config FUJITSU_ERRATUM_010001 !! 2141 endchoice
1207 bool "Fujitsu-A64FX erratum E#010001: <<
1208 default y <<
1209 help <<
1210 This option adds a workaround for F <<
1211 On some variants of the Fujitsu-A64 <<
1212 accesses may cause undefined fault <<
1213 This fault occurs under a specific <<
1214 load/store instruction performs an <<
1215 case-1 TTBR0_EL1 with TCR_EL1.NFD0 <<
1216 case-2 TTBR0_EL2 with TCR_EL2.NFD0 <<
1217 case-3 TTBR1_EL1 with TCR_EL1.NFD1 <<
1218 case-4 TTBR1_EL2 with TCR_EL2.NFD1 <<
1219 2142
1220 The workaround is to ensure these b !! 2143 config FORCE_MAX_ZONEORDER
1221 The workaround only affects the Fuj !! 2144 int "Maximum zone order"
>> 2145 range 14 64 if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_64KB
>> 2146 default "14" if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_64KB
>> 2147 range 13 64 if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_32KB
>> 2148 default "13" if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_32KB
>> 2149 range 12 64 if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_16KB
>> 2150 default "12" if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_16KB
>> 2151 range 0 64
>> 2152 default "11"
>> 2153 help
>> 2154 The kernel memory allocator divides physically contiguous memory
>> 2155 blocks into "zones", where each zone is a power of two number of
>> 2156 pages. This option selects the largest power of two that the kernel
>> 2157 keeps in the memory allocator. If you need to allocate very large
>> 2158 blocks of physically contiguous memory, then you may need to
>> 2159 increase this value.
1222 2160
1223 If unsure, say Y. !! 2161 This config option is actually maximum order plus one. For example,
>> 2162 a value of 11 means that the largest free memory block is 2^10 pages.
1224 2163
1225 config HISILICON_ERRATUM_161600802 !! 2164 The page size is not necessarily 4KB. Keep this in mind
1226 bool "Hip07 161600802: Erroneous redi !! 2165 when choosing a value for this option.
1227 default y <<
1228 help <<
1229 The HiSilicon Hip07 SoC uses the wr <<
1230 when issued ITS commands such as VM <<
1231 a 128kB offset to be applied to the <<
1232 2166
1233 If unsure, say Y. !! 2167 config BOARD_SCACHE
>> 2168 bool
1234 2169
1235 config QCOM_FALKOR_ERRATUM_1003 !! 2170 config IP22_CPU_SCACHE
1236 bool "Falkor E1003: Incorrect transla !! 2171 bool
1237 default y !! 2172 select BOARD_SCACHE
1238 help <<
1239 On Falkor v1, an incorrect ASID may <<
1240 and BADDR are changed together in T <<
1241 in TTBR1_EL1, this situation only o <<
1242 then only for entries in the walk c <<
1243 is unchanged. Work around the errat <<
1244 entries for the trampoline before e <<
1245 2173
1246 config QCOM_FALKOR_ERRATUM_1009 !! 2174 #
1247 bool "Falkor E1009: Prematurely compl !! 2175 # Support for a MIPS32 / MIPS64 style S-caches
1248 default y !! 2176 #
1249 select ARM64_WORKAROUND_REPEAT_TLBI !! 2177 config MIPS_CPU_SCACHE
1250 help !! 2178 bool
1251 On Falkor v1, the CPU may premature !! 2179 select BOARD_SCACHE
1252 TLBI xxIS invalidate maintenance op <<
1253 one more time to fix the issue. <<
1254 2180
1255 If unsure, say Y. !! 2181 config R5000_CPU_SCACHE
>> 2182 bool
>> 2183 select BOARD_SCACHE
1256 2184
1257 config QCOM_QDF2400_ERRATUM_0065 !! 2185 config RM7000_CPU_SCACHE
1258 bool "QDF2400 E0065: Incorrect GITS_T !! 2186 bool
1259 default y !! 2187 select BOARD_SCACHE
>> 2188
>> 2189 config SIBYTE_DMA_PAGEOPS
>> 2190 bool "Use DMA to clear/copy pages"
>> 2191 depends on CPU_SB1
1260 help 2192 help
1261 On Qualcomm Datacenter Technologies !! 2193 Instead of using the CPU to zero and copy pages, use a Data Mover
1262 ITE size incorrectly. The GITS_TYPE !! 2194 channel. These DMA channels are otherwise unused by the standard
1263 been indicated as 16Bytes (0xf), no !! 2195 SiByte Linux port. Seems to give a small performance benefit.
1264 2196
1265 If unsure, say Y. !! 2197 config CPU_HAS_PREFETCH
>> 2198 bool
>> 2199
>> 2200 config CPU_GENERIC_DUMP_TLB
>> 2201 bool
>> 2202 default y if !CPU_R3000
1266 2203
1267 config QCOM_FALKOR_ERRATUM_E1041 !! 2204 config MIPS_FP_SUPPORT
1268 bool "Falkor E1041: Speculative instr !! 2205 bool "Floating Point support" if EXPERT
1269 default y 2206 default y
1270 help 2207 help
1271 Falkor CPU may speculatively fetch !! 2208 Select y to include support for floating point in the kernel
1272 memory location when MMU translatio !! 2209 including initialization of FPU hardware, FP context save & restore
1273 to SCTLR_ELn[M]=0. Prefix an ISB in !! 2210 and emulation of an FPU where necessary. Without this support any
>> 2211 userland program attempting to use floating point instructions will
>> 2212 receive a SIGILL.
1274 2213
1275 If unsure, say Y. !! 2214 If you know that your userland will not attempt to use floating point
>> 2215 instructions then you can say n here to shrink the kernel a little.
1276 2216
1277 config NVIDIA_CARMEL_CNP_ERRATUM !! 2217 If unsure, say y.
1278 bool "NVIDIA Carmel CNP: CNP on Carme <<
1279 default y <<
1280 help <<
1281 If CNP is enabled on Carmel cores, <<
1282 invalidate shared TLB entries insta <<
1283 on standard ARM cores. <<
1284 2218
1285 If unsure, say Y. !! 2219 config CPU_R2300_FPU
>> 2220 bool
>> 2221 depends on MIPS_FP_SUPPORT
>> 2222 default y if CPU_R3000
1286 2223
1287 config ROCKCHIP_ERRATUM_3588001 !! 2224 config CPU_R3K_TLB
1288 bool "Rockchip 3588001: GIC600 can no !! 2225 bool
1289 default y <<
1290 help <<
1291 The Rockchip RK3588 GIC600 SoC inte <<
1292 This means, that its sharability fe <<
1293 is supported by the IP itself. <<
1294 2226
1295 If unsure, say Y. !! 2227 config CPU_R4K_FPU
>> 2228 bool
>> 2229 depends on MIPS_FP_SUPPORT
>> 2230 default y if !CPU_R2300_FPU
>> 2231
>> 2232 config CPU_R4K_CACHE_TLB
>> 2233 bool
>> 2234 default y if !(CPU_R3K_TLB || CPU_SB1 || CPU_CAVIUM_OCTEON)
1296 2235
1297 config SOCIONEXT_SYNQUACER_PREITS !! 2236 config MIPS_MT_SMP
1298 bool "Socionext Synquacer: Workaround !! 2237 bool "MIPS MT SMP support (1 TC on each available VPE)"
1299 default y 2238 default y
>> 2239 depends on SYS_SUPPORTS_MULTITHREADING && !CPU_MIPSR6 && !CPU_MICROMIPS
>> 2240 select CPU_MIPSR2_IRQ_VI
>> 2241 select CPU_MIPSR2_IRQ_EI
>> 2242 select SYNC_R4K
>> 2243 select MIPS_MT
>> 2244 select SMP
>> 2245 select SMP_UP
>> 2246 select SYS_SUPPORTS_SMP
>> 2247 select SYS_SUPPORTS_SCHED_SMT
>> 2248 select MIPS_PERF_SHARED_TC_COUNTERS
>> 2249 help
>> 2250 This is a kernel model which is known as SMVP. This is supported
>> 2251 on cores with the MT ASE and uses the available VPEs to implement
>> 2252 virtual processors which supports SMP. This is equivalent to the
>> 2253 Intel Hyperthreading feature. For further information go to
>> 2254 <http://www.imgtec.com/mips/mips-multithreading.asp>.
>> 2255
>> 2256 config MIPS_MT
>> 2257 bool
>> 2258
>> 2259 config SCHED_SMT
>> 2260 bool "SMT (multithreading) scheduler support"
>> 2261 depends on SYS_SUPPORTS_SCHED_SMT
>> 2262 default n
1300 help 2263 help
1301 Socionext Synquacer SoCs implement !! 2264 SMT scheduler support improves the CPU scheduler's decision making
1302 MSI doorbell writes with non-zero v !! 2265 when dealing with MIPS MT enabled cores at a cost of slightly
>> 2266 increased overhead in some places. If unsure say N here.
1303 2267
1304 If unsure, say Y. !! 2268 config SYS_SUPPORTS_SCHED_SMT
>> 2269 bool
1305 2270
1306 endmenu # "ARM errata workarounds via the alt !! 2271 config SYS_SUPPORTS_MULTITHREADING
>> 2272 bool
1307 2273
1308 choice !! 2274 config MIPS_MT_FPAFF
1309 prompt "Page size" !! 2275 bool "Dynamic FPU affinity for FP-intensive threads"
1310 default ARM64_4K_PAGES !! 2276 default y
1311 help !! 2277 depends on MIPS_MT_SMP
1312 Page size (translation granule) con <<
1313 2278
1314 config ARM64_4K_PAGES !! 2279 config MIPSR2_TO_R6_EMULATOR
1315 bool "4KB" !! 2280 bool "MIPS R2-to-R6 emulator"
1316 select HAVE_PAGE_SIZE_4KB !! 2281 depends on CPU_MIPSR6
>> 2282 depends on MIPS_FP_SUPPORT
>> 2283 default y
1317 help 2284 help
1318 This feature enables 4KB pages supp !! 2285 Choose this option if you want to run non-R6 MIPS userland code.
>> 2286 Even if you say 'Y' here, the emulator will still be disabled by
>> 2287 default. You can enable it using the 'mipsr2emu' kernel option.
>> 2288 The only reason this is a build-time option is to save ~14K from the
>> 2289 final kernel image.
1319 2290
1320 config ARM64_16K_PAGES !! 2291 config SYS_SUPPORTS_VPE_LOADER
1321 bool "16KB" !! 2292 bool
1322 select HAVE_PAGE_SIZE_16KB !! 2293 depends on SYS_SUPPORTS_MULTITHREADING
1323 help 2294 help
1324 The system will use 16KB pages supp !! 2295 Indicates that the platform supports the VPE loader, and provides
1325 requires applications compiled with !! 2296 physical_memsize.
1326 aligned segments. <<
1327 2297
1328 config ARM64_64K_PAGES !! 2298 config MIPS_VPE_LOADER
1329 bool "64KB" !! 2299 bool "VPE loader support."
1330 select HAVE_PAGE_SIZE_64KB !! 2300 depends on SYS_SUPPORTS_VPE_LOADER && MODULES
>> 2301 select CPU_MIPSR2_IRQ_VI
>> 2302 select CPU_MIPSR2_IRQ_EI
>> 2303 select MIPS_MT
1331 help 2304 help
1332 This feature enables 64KB pages sup !! 2305 Includes a loader for loading an elf relocatable object
1333 allowing only two levels of page ta !! 2306 onto another VPE and running it.
1334 look-up. AArch32 emulation requires <<
1335 with 64K aligned segments. <<
1336 2307
1337 endchoice !! 2308 config MIPS_VPE_LOADER_CMP
>> 2309 bool
>> 2310 default "y"
>> 2311 depends on MIPS_VPE_LOADER && MIPS_CMP
1338 2312
1339 choice !! 2313 config MIPS_VPE_LOADER_MT
1340 prompt "Virtual address space size" !! 2314 bool
1341 default ARM64_VA_BITS_52 !! 2315 default "y"
1342 help !! 2316 depends on MIPS_VPE_LOADER && !MIPS_CMP
1343 Allows choosing one of multiple pos <<
1344 space sizes. The level of translati <<
1345 a combination of page size and virt <<
1346 <<
1347 config ARM64_VA_BITS_36 <<
1348 bool "36-bit" if EXPERT <<
1349 depends on PAGE_SIZE_16KB <<
1350 <<
1351 config ARM64_VA_BITS_39 <<
1352 bool "39-bit" <<
1353 depends on PAGE_SIZE_4KB <<
1354 <<
1355 config ARM64_VA_BITS_42 <<
1356 bool "42-bit" <<
1357 depends on PAGE_SIZE_64KB <<
1358 <<
1359 config ARM64_VA_BITS_47 <<
1360 bool "47-bit" <<
1361 depends on PAGE_SIZE_16KB <<
1362 <<
1363 config ARM64_VA_BITS_48 <<
1364 bool "48-bit" <<
1365 <<
1366 config ARM64_VA_BITS_52 <<
1367 bool "52-bit" <<
1368 depends on ARM64_PAN || !ARM64_SW_TTB <<
1369 help <<
1370 Enable 52-bit virtual addressing fo <<
1371 requested via a hint to mmap(). The <<
1372 virtual addresses for its own mappi <<
1373 this feature is available, otherwis <<
1374 <<
1375 NOTE: Enabling 52-bit virtual addre <<
1376 ARMv8.3 Pointer Authentication will <<
1377 reduced from 7 bits to 3 bits, whic <<
1378 impact on its susceptibility to bru <<
1379 2317
1380 If unsure, select 48-bit virtual ad !! 2318 config MIPS_VPE_LOADER_TOM
>> 2319 bool "Load VPE program into memory hidden from linux"
>> 2320 depends on MIPS_VPE_LOADER
>> 2321 default y
>> 2322 help
>> 2323 The loader can use memory that is present but has been hidden from
>> 2324 Linux using the kernel command line option "mem=xxMB". It's up to
>> 2325 you to ensure the amount you put in the option and the space your
>> 2326 program requires is less or equal to the amount physically present.
1381 2327
1382 endchoice !! 2328 config MIPS_VPE_APSP_API
>> 2329 bool "Enable support for AP/SP API (RTLX)"
>> 2330 depends on MIPS_VPE_LOADER
1383 2331
1384 config ARM64_FORCE_52BIT !! 2332 config MIPS_VPE_APSP_API_CMP
1385 bool "Force 52-bit virtual addresses !! 2333 bool
1386 depends on ARM64_VA_BITS_52 && EXPERT !! 2334 default "y"
1387 help !! 2335 depends on MIPS_VPE_APSP_API && MIPS_CMP
1388 For systems with 52-bit userspace V <<
1389 to maintain compatibility with olde <<
1390 unless a hint is supplied to mmap. <<
1391 <<
1392 This configuration option disables <<
1393 forces all userspace addresses to b <<
1394 should only enable this configurati <<
1395 memory management code. If unsure s <<
1396 2336
1397 config ARM64_VA_BITS !! 2337 config MIPS_VPE_APSP_API_MT
1398 int !! 2338 bool
1399 default 36 if ARM64_VA_BITS_36 !! 2339 default "y"
1400 default 39 if ARM64_VA_BITS_39 !! 2340 depends on MIPS_VPE_APSP_API && !MIPS_CMP
1401 default 42 if ARM64_VA_BITS_42 <<
1402 default 47 if ARM64_VA_BITS_47 <<
1403 default 48 if ARM64_VA_BITS_48 <<
1404 default 52 if ARM64_VA_BITS_52 <<
1405 2341
1406 choice !! 2342 config MIPS_CMP
1407 prompt "Physical address space size" !! 2343 bool "MIPS CMP framework support (DEPRECATED)"
1408 default ARM64_PA_BITS_48 !! 2344 depends on SYS_SUPPORTS_MIPS_CMP && !CPU_MIPSR6
>> 2345 select SMP
>> 2346 select SYNC_R4K
>> 2347 select SYS_SUPPORTS_SMP
>> 2348 select WEAK_ORDERING
>> 2349 default n
1409 help 2350 help
1410 Choose the maximum physical address !! 2351 Select this if you are using a bootloader which implements the "CMP
1411 support. !! 2352 framework" protocol (ie. YAMON) and want your kernel to make use of
>> 2353 its ability to start secondary CPUs.
>> 2354
>> 2355 Unless you have a specific need, you should use CONFIG_MIPS_CPS
>> 2356 instead of this.
>> 2357
>> 2358 config MIPS_CPS
>> 2359 bool "MIPS Coherent Processing System support"
>> 2360 depends on SYS_SUPPORTS_MIPS_CPS
>> 2361 select MIPS_CM
>> 2362 select MIPS_CPS_PM if HOTPLUG_CPU
>> 2363 select SMP
>> 2364 select SYNC_R4K if (CEVT_R4K || CSRC_R4K)
>> 2365 select SYS_SUPPORTS_HOTPLUG_CPU
>> 2366 select SYS_SUPPORTS_SCHED_SMT if CPU_MIPSR6
>> 2367 select SYS_SUPPORTS_SMP
>> 2368 select WEAK_ORDERING
>> 2369 select GENERIC_IRQ_MIGRATION if HOTPLUG_CPU
>> 2370 help
>> 2371 Select this if you wish to run an SMP kernel across multiple cores
>> 2372 within a MIPS Coherent Processing System. When this option is
>> 2373 enabled the kernel will probe for other cores and boot them with
>> 2374 no external assistance. It is safe to enable this when hardware
>> 2375 support is unavailable.
1412 2376
1413 config ARM64_PA_BITS_48 !! 2377 config MIPS_CPS_PM
1414 bool "48-bit" !! 2378 depends on MIPS_CPS
1415 depends on ARM64_64K_PAGES || !ARM64_ !! 2379 bool
1416 <<
1417 config ARM64_PA_BITS_52 <<
1418 bool "52-bit" <<
1419 depends on ARM64_64K_PAGES || ARM64_V <<
1420 depends on ARM64_PAN || !ARM64_SW_TTB <<
1421 help <<
1422 Enable support for a 52-bit physica <<
1423 part of the ARMv8.2-LPA extension. <<
1424 <<
1425 With this enabled, the kernel will <<
1426 do not support ARMv8.2-LPA, but wit <<
1427 minor performance overhead). <<
1428 2380
1429 endchoice !! 2381 config MIPS_CM
>> 2382 bool
>> 2383 select MIPS_CPC
1430 2384
1431 config ARM64_PA_BITS !! 2385 config MIPS_CPC
1432 int !! 2386 bool
1433 default 48 if ARM64_PA_BITS_48 <<
1434 default 52 if ARM64_PA_BITS_52 <<
1435 2387
1436 config ARM64_LPA2 !! 2388 config SB1_PASS_2_WORKAROUNDS
1437 def_bool y !! 2389 bool
1438 depends on ARM64_PA_BITS_52 && !ARM64 !! 2390 depends on CPU_SB1 && (CPU_SB1_PASS_2_2 || CPU_SB1_PASS_2)
>> 2391 default y
>> 2392
>> 2393 config SB1_PASS_2_1_WORKAROUNDS
>> 2394 bool
>> 2395 depends on CPU_SB1 && CPU_SB1_PASS_2
>> 2396 default y
1439 2397
1440 choice 2398 choice
1441 prompt "Endianness" !! 2399 prompt "SmartMIPS or microMIPS ASE support"
1442 default CPU_LITTLE_ENDIAN <<
1443 help <<
1444 Select the endianness of data acces <<
1445 applications will need to be compil <<
1446 that is selected here. <<
1447 2400
1448 config CPU_BIG_ENDIAN !! 2401 config CPU_NEEDS_NO_SMARTMIPS_OR_MICROMIPS
1449 bool "Build big-endian kernel" !! 2402 bool "None"
1450 # https://github.com/llvm/llvm-projec <<
1451 depends on AS_IS_GNU || AS_VERSION >= <<
1452 help 2403 help
1453 Say Y if you plan on running a kern !! 2404 Select this if you want neither microMIPS nor SmartMIPS support
1454 2405
1455 config CPU_LITTLE_ENDIAN !! 2406 config CPU_HAS_SMARTMIPS
1456 bool "Build little-endian kernel" !! 2407 depends on SYS_SUPPORTS_SMARTMIPS
>> 2408 bool "SmartMIPS"
>> 2409 help
>> 2410 SmartMIPS is a extension of the MIPS32 architecture aimed at
>> 2411 increased security at both hardware and software level for
>> 2412 smartcards. Enabling this option will allow proper use of the
>> 2413 SmartMIPS instructions by Linux applications. However a kernel with
>> 2414 this option will not work on a MIPS core without SmartMIPS core. If
>> 2415 you don't know you probably don't have SmartMIPS and should say N
>> 2416 here.
>> 2417
>> 2418 config CPU_MICROMIPS
>> 2419 depends on 32BIT && SYS_SUPPORTS_MICROMIPS && !CPU_MIPSR6
>> 2420 bool "microMIPS"
1457 help 2421 help
1458 Say Y if you plan on running a kern !! 2422 When this option is enabled the kernel will be built using the
1459 This is usually the case for distri !! 2423 microMIPS ISA
1460 2424
1461 endchoice 2425 endchoice
1462 2426
1463 config SCHED_MC !! 2427 config CPU_HAS_MSA
1464 bool "Multi-core scheduler support" !! 2428 bool "Support for the MIPS SIMD Architecture"
1465 help !! 2429 depends on CPU_SUPPORTS_MSA
1466 Multi-core scheduler support improv !! 2430 depends on MIPS_FP_SUPPORT
1467 making when dealing with multi-core !! 2431 depends on 64BIT || MIPS_O32_FP64_SUPPORT
1468 increased overhead in some places. !! 2432 help
>> 2433 MIPS SIMD Architecture (MSA) introduces 128 bit wide vector registers
>> 2434 and a set of SIMD instructions to operate on them. When this option
>> 2435 is enabled the kernel will support allocating & switching MSA
>> 2436 vector register contexts. If you know that your kernel will only be
>> 2437 running on CPUs which do not support MSA or that your userland will
>> 2438 not be making use of it then you may wish to say N here to reduce
>> 2439 the size & complexity of your kernel.
1469 2440
1470 config SCHED_CLUSTER !! 2441 If unsure, say Y.
1471 bool "Cluster scheduler support" <<
1472 help <<
1473 Cluster scheduler support improves <<
1474 making when dealing with machines t <<
1475 Cluster usually means a couple of C <<
1476 by sharing mid-level caches, last-l <<
1477 busses. <<
1478 2442
1479 config SCHED_SMT !! 2443 config CPU_HAS_WB
1480 bool "SMT scheduler support" !! 2444 bool
1481 help <<
1482 Improves the CPU scheduler's decisi <<
1483 MultiThreading at a cost of slightl <<
1484 places. If unsure say N here. <<
1485 2445
1486 config NR_CPUS !! 2446 config XKS01
1487 int "Maximum number of CPUs (2-4096)" !! 2447 bool
1488 range 2 4096 <<
1489 default "512" <<
1490 2448
1491 config HOTPLUG_CPU !! 2449 config CPU_HAS_DIEI
1492 bool "Support for hot-pluggable CPUs" !! 2450 depends on !CPU_DIEI_BROKEN
1493 select GENERIC_IRQ_MIGRATION !! 2451 bool
1494 help <<
1495 Say Y here to experiment with turni <<
1496 can be controlled through /sys/devi <<
1497 2452
1498 # Common NUMA Features !! 2453 config CPU_DIEI_BROKEN
1499 config NUMA !! 2454 bool
1500 bool "NUMA Memory Allocation and Sche <<
1501 select GENERIC_ARCH_NUMA <<
1502 select OF_NUMA <<
1503 select HAVE_SETUP_PER_CPU_AREA <<
1504 select NEED_PER_CPU_EMBED_FIRST_CHUNK <<
1505 select NEED_PER_CPU_PAGE_FIRST_CHUNK <<
1506 select USE_PERCPU_NUMA_NODE_ID <<
1507 help <<
1508 Enable NUMA (Non-Uniform Memory Acc <<
1509 2455
1510 The kernel will try to allocate mem !! 2456 config CPU_HAS_RIXI
1511 local memory of the CPU and add som !! 2457 bool
1512 NUMA awareness to the kernel. <<
1513 2458
1514 config NODES_SHIFT !! 2459 config CPU_NO_LOAD_STORE_LR
1515 int "Maximum NUMA Nodes (as a power o !! 2460 bool
1516 range 1 10 <<
1517 default "4" <<
1518 depends on NUMA <<
1519 help 2461 help
1520 Specify the maximum number of NUMA !! 2462 CPU lacks support for unaligned load and store instructions:
1521 system. Increases memory reserved !! 2463 LWL, LWR, SWL, SWR (Load/store word left/right).
>> 2464 LDL, LDR, SDL, SDR (Load/store doubleword left/right, for 64bit
>> 2465 systems).
1522 2466
1523 source "kernel/Kconfig.hz" !! 2467 #
>> 2468 # Vectored interrupt mode is an R2 feature
>> 2469 #
>> 2470 config CPU_MIPSR2_IRQ_VI
>> 2471 bool
1524 2472
1525 config ARCH_SPARSEMEM_ENABLE !! 2473 #
1526 def_bool y !! 2474 # Extended interrupt mode is an R2 feature
1527 select SPARSEMEM_VMEMMAP_ENABLE !! 2475 #
1528 select SPARSEMEM_VMEMMAP !! 2476 config CPU_MIPSR2_IRQ_EI
>> 2477 bool
1529 2478
1530 config HW_PERF_EVENTS !! 2479 config CPU_HAS_SYNC
1531 def_bool y !! 2480 bool
1532 depends on ARM_PMU !! 2481 depends on !CPU_R3000
>> 2482 default y
1533 2483
1534 # Supported by clang >= 7.0 or GCC >= 12.0.0 !! 2484 #
1535 config CC_HAVE_SHADOW_CALL_STACK !! 2485 # CPU non-features
1536 def_bool $(cc-option, -fsanitize=shad !! 2486 #
1537 2487
1538 config PARAVIRT !! 2488 # Work around the "daddi" and "daddiu" CPU errata:
1539 bool "Enable paravirtualization code" !! 2489 #
1540 help !! 2490 # - The `daddi' instruction fails to trap on overflow.
1541 This changes the kernel so it can m !! 2491 # "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0",
1542 under a hypervisor, potentially imp !! 2492 # erratum #23
1543 over full virtualization. !! 2493 #
>> 2494 # - The `daddiu' instruction can produce an incorrect result.
>> 2495 # "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0",
>> 2496 # erratum #41
>> 2497 # "MIPS R4000MC Errata, Processor Revision 2.2 and 3.0", erratum
>> 2498 # #15
>> 2499 # "MIPS R4400PC/SC Errata, Processor Revision 1.0", erratum #7
>> 2500 # "MIPS R4400MC Errata, Processor Revision 1.0", erratum #5
>> 2501 config CPU_DADDI_WORKAROUNDS
>> 2502 bool
1544 2503
1545 config PARAVIRT_TIME_ACCOUNTING !! 2504 # Work around certain R4000 CPU errata (as implemented by GCC):
1546 bool "Paravirtual steal time accounti !! 2505 #
1547 select PARAVIRT !! 2506 # - A double-word or a variable shift may give an incorrect result
1548 help !! 2507 # if executed immediately after starting an integer division:
1549 Select this option to enable fine g !! 2508 # "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0",
1550 accounting. Time spent executing ot !! 2509 # erratum #28
1551 the current vCPU is discounted from !! 2510 # "MIPS R4000MC Errata, Processor Revision 2.2 and 3.0", erratum
1552 that, there can be a small performa !! 2511 # #19
>> 2512 #
>> 2513 # - A double-word or a variable shift may give an incorrect result
>> 2514 # if executed while an integer multiplication is in progress:
>> 2515 # "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0",
>> 2516 # errata #16 & #28
>> 2517 #
>> 2518 # - An integer division may give an incorrect result if started in
>> 2519 # a delay slot of a taken branch or a jump:
>> 2520 # "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0",
>> 2521 # erratum #52
>> 2522 config CPU_R4000_WORKAROUNDS
>> 2523 bool
>> 2524 select CPU_R4400_WORKAROUNDS
1553 2525
1554 If in doubt, say N here. !! 2526 # Work around certain R4400 CPU errata (as implemented by GCC):
>> 2527 #
>> 2528 # - A double-word or a variable shift may give an incorrect result
>> 2529 # if executed immediately after starting an integer division:
>> 2530 # "MIPS R4400MC Errata, Processor Revision 1.0", erratum #10
>> 2531 # "MIPS R4400MC Errata, Processor Revision 2.0 & 3.0", erratum #4
>> 2532 config CPU_R4400_WORKAROUNDS
>> 2533 bool
1555 2534
1556 config ARCH_SUPPORTS_KEXEC !! 2535 config CPU_R4X00_BUGS64
1557 def_bool PM_SLEEP_SMP !! 2536 bool
>> 2537 default y if SYS_HAS_CPU_R4X00 && 64BIT && (TARGET_ISA_REV < 1)
1558 2538
1559 config ARCH_SUPPORTS_KEXEC_FILE !! 2539 config MIPS_ASID_SHIFT
1560 def_bool y !! 2540 int
>> 2541 default 6 if CPU_R3000
>> 2542 default 0
1561 2543
1562 config ARCH_SELECTS_KEXEC_FILE !! 2544 config MIPS_ASID_BITS
1563 def_bool y !! 2545 int
1564 depends on KEXEC_FILE !! 2546 default 0 if MIPS_ASID_BITS_VARIABLE
1565 select HAVE_IMA_KEXEC if IMA !! 2547 default 6 if CPU_R3000
>> 2548 default 8
1566 2549
1567 config ARCH_SUPPORTS_KEXEC_SIG !! 2550 config MIPS_ASID_BITS_VARIABLE
1568 def_bool y !! 2551 bool
1569 2552
1570 config ARCH_SUPPORTS_KEXEC_IMAGE_VERIFY_SIG !! 2553 config MIPS_CRC_SUPPORT
1571 def_bool y !! 2554 bool
1572 2555
1573 config ARCH_DEFAULT_KEXEC_IMAGE_VERIFY_SIG !! 2556 # R4600 erratum. Due to the lack of errata information the exact
1574 def_bool y !! 2557 # technical details aren't known. I've experimentally found that disabling
>> 2558 # interrupts during indexed I-cache flushes seems to be sufficient to deal
>> 2559 # with the issue.
>> 2560 config WAR_R4600_V1_INDEX_ICACHEOP
>> 2561 bool
1575 2562
1576 config ARCH_SUPPORTS_CRASH_DUMP !! 2563 # Pleasures of the R4600 V1.x. Cite from the IDT R4600 V1.7 errata:
1577 def_bool y !! 2564 #
>> 2565 # 18. The CACHE instructions Hit_Writeback_Invalidate_D, Hit_Writeback_D,
>> 2566 # Hit_Invalidate_D and Create_Dirty_Excl_D should only be
>> 2567 # executed if there is no other dcache activity. If the dcache is
>> 2568 # accessed for another instruction immediately preceding when these
>> 2569 # cache instructions are executing, it is possible that the dcache
>> 2570 # tag match outputs used by these cache instructions will be
>> 2571 # incorrect. These cache instructions should be preceded by at least
>> 2572 # four instructions that are not any kind of load or store
>> 2573 # instruction.
>> 2574 #
>> 2575 # This is not allowed: lw
>> 2576 # nop
>> 2577 # nop
>> 2578 # nop
>> 2579 # cache Hit_Writeback_Invalidate_D
>> 2580 #
>> 2581 # This is allowed: lw
>> 2582 # nop
>> 2583 # nop
>> 2584 # nop
>> 2585 # nop
>> 2586 # cache Hit_Writeback_Invalidate_D
>> 2587 config WAR_R4600_V1_HIT_CACHEOP
>> 2588 bool
1578 2589
1579 config ARCH_HAS_GENERIC_CRASHKERNEL_RESERVATI !! 2590 # Writeback and invalidate the primary cache dcache before DMA.
1580 def_bool CRASH_RESERVE !! 2591 #
>> 2592 # R4600 v2.0 bug: "The CACHE instructions Hit_Writeback_Inv_D,
>> 2593 # Hit_Writeback_D, Hit_Invalidate_D and Create_Dirty_Exclusive_D will only
>> 2594 # operate correctly if the internal data cache refill buffer is empty. These
>> 2595 # CACHE instructions should be separated from any potential data cache miss
>> 2596 # by a load instruction to an uncached address to empty the response buffer."
>> 2597 # (Revision 2.0 device errata from IDT available on https://www.idt.com/
>> 2598 # in .pdf format.)
>> 2599 config WAR_R4600_V2_HIT_CACHEOP
>> 2600 bool
1581 2601
1582 config TRANS_TABLE !! 2602 # From TX49/H2 manual: "If the instruction (i.e. CACHE) is issued for
1583 def_bool y !! 2603 # the line which this instruction itself exists, the following
1584 depends on HIBERNATION || KEXEC_CORE !! 2604 # operation is not guaranteed."
>> 2605 #
>> 2606 # Workaround: do two phase flushing for Index_Invalidate_I
>> 2607 config WAR_TX49XX_ICACHE_INDEX_INV
>> 2608 bool
1585 2609
1586 config XEN_DOM0 !! 2610 # The RM7000 processors and the E9000 cores have a bug (though PMC-Sierra
1587 def_bool y !! 2611 # opposes it being called that) where invalid instructions in the same
1588 depends on XEN !! 2612 # I-cache line worth of instructions being fetched may case spurious
>> 2613 # exceptions.
>> 2614 config WAR_ICACHE_REFILLS
>> 2615 bool
1589 2616
1590 config XEN !! 2617 # On the R10000 up to version 2.6 (not sure about 2.7) there is a bug that
1591 bool "Xen guest support on ARM64" !! 2618 # may cause ll / sc and lld / scd sequences to execute non-atomically.
1592 depends on ARM64 && OF !! 2619 config WAR_R10000_LLSC
1593 select SWIOTLB_XEN !! 2620 bool
1594 select PARAVIRT !! 2621
1595 help !! 2622 # 34K core erratum: "Problems Executing the TLBR Instruction"
1596 Say Y if you want to run Linux in a !! 2623 config WAR_MIPS34K_MISSED_ITLB
>> 2624 bool
1597 2625
1598 # include/linux/mmzone.h requires the followi <<
1599 # <<
1600 # MAX_PAGE_ORDER + PAGE_SHIFT <= SECTION_SI <<
1601 # 2626 #
1602 # so the maximum value of MAX_PAGE_ORDER is S !! 2627 # - Highmem only makes sense for the 32-bit kernel.
>> 2628 # - The current highmem code will only work properly on physically indexed
>> 2629 # caches such as R3000, SB1, R7000 or those that look like they're virtually
>> 2630 # indexed such as R4000/R4400 SC and MC versions or R10000. So for the
>> 2631 # moment we protect the user and offer the highmem option only on machines
>> 2632 # where it's known to be safe. This will not offer highmem on a few systems
>> 2633 # such as MIPS32 and MIPS64 CPUs which may have virtual and physically
>> 2634 # indexed CPUs but we're playing safe.
>> 2635 # - We use SYS_SUPPORTS_HIGHMEM to offer highmem only for systems where we
>> 2636 # know they might have memory configurations that could make use of highmem
>> 2637 # support.
1603 # 2638 #
1604 # | SECTION_SIZE_BITS | PAGE_SHIFT | m !! 2639 config HIGHMEM
1605 # ----+-------------------+--------------+--- !! 2640 bool "High Memory Support"
1606 # 4K | 27 | 12 | !! 2641 depends on 32BIT && CPU_SUPPORTS_HIGHMEM && SYS_SUPPORTS_HIGHMEM && !CPU_MIPS32_3_5_EVA
1607 # 16K | 27 | 14 | !! 2642 select KMAP_LOCAL
1608 # 64K | 29 | 16 | <<
1609 config ARCH_FORCE_MAX_ORDER <<
1610 int <<
1611 default "13" if ARM64_64K_PAGES <<
1612 default "11" if ARM64_16K_PAGES <<
1613 default "10" <<
1614 help <<
1615 The kernel page allocator limits th <<
1616 contiguous allocations. The limit i <<
1617 defines the maximal power of two of <<
1618 allocated as a single contiguous bl <<
1619 overriding the default setting when <<
1620 large blocks of physically contiguo <<
1621 <<
1622 The maximal size of allocation cann <<
1623 section, so the value of MAX_PAGE_O <<
1624 <<
1625 MAX_PAGE_ORDER + PAGE_SHIFT <= SE <<
1626 2643
1627 Don't change if unsure. !! 2644 config CPU_SUPPORTS_HIGHMEM
>> 2645 bool
1628 2646
1629 config UNMAP_KERNEL_AT_EL0 !! 2647 config SYS_SUPPORTS_HIGHMEM
1630 bool "Unmap kernel when running in us !! 2648 bool
1631 default y <<
1632 help <<
1633 Speculation attacks against some hi <<
1634 be used to bypass MMU permission ch <<
1635 userspace. This can be defended aga <<
1636 when running in userspace, mapping <<
1637 via a trampoline page in the vector <<
1638 2649
1639 If unsure, say Y. !! 2650 config SYS_SUPPORTS_SMARTMIPS
>> 2651 bool
1640 2652
1641 config MITIGATE_SPECTRE_BRANCH_HISTORY !! 2653 config SYS_SUPPORTS_MICROMIPS
1642 bool "Mitigate Spectre style attacks !! 2654 bool
1643 default y <<
1644 help <<
1645 Speculation attacks against some hi <<
1646 make use of branch history to influ <<
1647 When taking an exception from user- <<
1648 or a firmware call overwrites the b <<
1649 2655
1650 config RODATA_FULL_DEFAULT_ENABLED !! 2656 config SYS_SUPPORTS_MIPS16
1651 bool "Apply r/o permissions of VM are !! 2657 bool
1652 default y <<
1653 help 2658 help
1654 Apply read-only attributes of VM ar !! 2659 This option must be set if a kernel might be executed on a MIPS16-
1655 the backing pages as well. This pre !! 2660 enabled CPU even if MIPS16 is not actually being used. In other
1656 from being modified (inadvertently !! 2661 words, it makes the kernel MIPS16-tolerant.
1657 mapping of the same memory page. Th <<
1658 be turned off at runtime by passing <<
1659 with rodata=full if this option is <<
1660 <<
1661 This requires the linear region to <<
1662 which may adversely affect performa <<
1663 <<
1664 config ARM64_SW_TTBR0_PAN <<
1665 bool "Emulate Privileged Access Never <<
1666 depends on !KCSAN <<
1667 help <<
1668 Enabling this option prevents the k <<
1669 user-space memory directly by point <<
1670 zeroed area and reserved ASID. The <<
1671 restore the valid TTBR0_EL1 tempora <<
1672 2662
1673 config ARM64_TAGGED_ADDR_ABI !! 2663 config CPU_SUPPORTS_MSA
1674 bool "Enable the tagged user addresse !! 2664 bool
1675 default y <<
1676 help <<
1677 When this option is enabled, user a <<
1678 relaxed ABI via prctl() allowing ta <<
1679 to system calls as pointer argument <<
1680 Documentation/arch/arm64/tagged-add <<
1681 <<
1682 menuconfig COMPAT <<
1683 bool "Kernel support for 32-bit EL0" <<
1684 depends on ARM64_4K_PAGES || EXPERT <<
1685 select HAVE_UID16 <<
1686 select OLD_SIGSUSPEND3 <<
1687 select COMPAT_OLD_SIGACTION <<
1688 help <<
1689 This option enables support for a 3 <<
1690 kernel at EL1. AArch32-specific com <<
1691 the user helper functions, VFP supp <<
1692 handled appropriately by the kernel <<
1693 <<
1694 If you use a page size other than 4 <<
1695 that you will only be able to execu <<
1696 with page size aligned segments. <<
1697 2665
1698 If you want to execute 32-bit users !! 2666 config ARCH_FLATMEM_ENABLE
>> 2667 def_bool y
>> 2668 depends on !NUMA && !CPU_LOONGSON2EF
1699 2669
1700 if COMPAT !! 2670 config ARCH_SPARSEMEM_ENABLE
>> 2671 bool
1701 2672
1702 config KUSER_HELPERS !! 2673 config NUMA
1703 bool "Enable kuser helpers page for 3 !! 2674 bool "NUMA Support"
1704 default y !! 2675 depends on SYS_SUPPORTS_NUMA
>> 2676 select SMP
>> 2677 select HAVE_SETUP_PER_CPU_AREA
>> 2678 select NEED_PER_CPU_EMBED_FIRST_CHUNK
1705 help 2679 help
1706 Warning: disabling this option may !! 2680 Say Y to compile the kernel to support NUMA (Non-Uniform Memory
>> 2681 Access). This option improves performance on systems with more
>> 2682 than two nodes; on two node systems it is generally better to
>> 2683 leave it disabled; on single node systems leave this option
>> 2684 disabled.
1707 2685
1708 Provide kuser helpers to compat tas !! 2686 config SYS_SUPPORTS_NUMA
1709 helper code to userspace in read on !! 2687 bool
1710 to allow userspace to be independen <<
1711 the system. This permits binaries t <<
1712 to ARMv8 without modification. <<
1713 <<
1714 See Documentation/arch/arm/kernel_u <<
1715 <<
1716 However, the fixed address nature o <<
1717 by ROP (return orientated programmi <<
1718 exploits. <<
1719 <<
1720 If all of the binaries and librarie <<
1721 are built specifically for your pla <<
1722 these helpers, then you can turn th <<
1723 such exploits. However, in that cas <<
1724 relying on those helpers is run, it <<
1725 <<
1726 Say N here only if you are absolute <<
1727 need these helpers; otherwise, the <<
1728 <<
1729 config COMPAT_VDSO <<
1730 bool "Enable vDSO for 32-bit applicat <<
1731 depends on !CPU_BIG_ENDIAN <<
1732 depends on (CC_IS_CLANG && LD_IS_LLD) <<
1733 select GENERIC_COMPAT_VDSO <<
1734 default y <<
1735 help <<
1736 Place in the process address space <<
1737 ELF shared object providing fast im <<
1738 and clock_gettime. <<
1739 <<
1740 You must have a 32-bit build of gli <<
1741 to seamlessly take advantage of thi <<
1742 <<
1743 config THUMB2_COMPAT_VDSO <<
1744 bool "Compile the 32-bit vDSO for Thu <<
1745 depends on COMPAT_VDSO <<
1746 default y <<
1747 help <<
1748 Compile the compat vDSO with '-mthu <<
1749 otherwise with '-marm'. <<
1750 2688
1751 config COMPAT_ALIGNMENT_FIXUPS !! 2689 config HAVE_ARCH_NODEDATA_EXTENSION
1752 bool "Fix up misaligned multi-word lo !! 2690 bool
1753 2691
1754 menuconfig ARMV8_DEPRECATED !! 2692 config RELOCATABLE
1755 bool "Emulate deprecated/obsolete ARM !! 2693 bool "Relocatable kernel"
1756 depends on SYSCTL !! 2694 depends on SYS_SUPPORTS_RELOCATABLE
1757 help !! 2695 depends on CPU_MIPS32_R2 || CPU_MIPS64_R2 || \
1758 Legacy software support may require !! 2696 CPU_MIPS32_R5 || CPU_MIPS64_R5 || \
1759 that have been deprecated or obsole !! 2697 CPU_MIPS32_R6 || CPU_MIPS64_R6 || \
>> 2698 CPU_P5600 || CAVIUM_OCTEON_SOC || \
>> 2699 CPU_LOONGSON64
>> 2700 help
>> 2701 This builds a kernel image that retains relocation information
>> 2702 so it can be loaded someplace besides the default 1MB.
>> 2703 The relocations make the kernel binary about 15% larger,
>> 2704 but are discarded at runtime
>> 2705
>> 2706 config RELOCATION_TABLE_SIZE
>> 2707 hex "Relocation table size"
>> 2708 depends on RELOCATABLE
>> 2709 range 0x0 0x01000000
>> 2710 default "0x00200000" if CPU_LOONGSON64
>> 2711 default "0x00100000"
>> 2712 help
>> 2713 A table of relocation data will be appended to the kernel binary
>> 2714 and parsed at boot to fix up the relocated kernel.
1760 2715
1761 Enable this config to enable select !! 2716 This option allows the amount of space reserved for the table to be
1762 features. !! 2717 adjusted, although the default of 1Mb should be ok in most cases.
1763 2718
1764 If unsure, say Y !! 2719 The build will fail and a valid size suggested if this is too small.
1765 2720
1766 if ARMV8_DEPRECATED !! 2721 If unsure, leave at the default value.
1767 2722
1768 config SWP_EMULATION !! 2723 config RANDOMIZE_BASE
1769 bool "Emulate SWP/SWPB instructions" !! 2724 bool "Randomize the address of the kernel image"
>> 2725 depends on RELOCATABLE
1770 help 2726 help
1771 ARMv8 obsoletes the use of A32 SWP/ !! 2727 Randomizes the physical and virtual address at which the
1772 they are always undefined. Say Y he !! 2728 kernel image is loaded, as a security feature that
1773 emulation of these instructions for !! 2729 deters exploit attempts relying on knowledge of the location
1774 This feature can be controlled at r !! 2730 of kernel internals.
1775 sysctl which is disabled by default <<
1776 2731
1777 In some older versions of glibc [<= !! 2732 Entropy is generated using any coprocessor 0 registers available.
1778 trylock() operations with the assum <<
1779 be preempted. This invalid assumpti <<
1780 with SWP emulation enabled, leading <<
1781 application. <<
1782 2733
1783 NOTE: when accessing uncached share !! 2734 The kernel will be offset by up to RANDOMIZE_BASE_MAX_OFFSET.
1784 on an external transaction monitori <<
1785 monitor to maintain update atomicit <<
1786 implement a global monitor, this op <<
1787 perform SWP operations to uncached <<
1788 2735
1789 If unsure, say Y !! 2736 If unsure, say N.
1790 2737
1791 config CP15_BARRIER_EMULATION !! 2738 config RANDOMIZE_BASE_MAX_OFFSET
1792 bool "Emulate CP15 Barrier instructio !! 2739 hex "Maximum kASLR offset" if EXPERT
1793 help !! 2740 depends on RANDOMIZE_BASE
1794 The CP15 barrier instructions - CP1 !! 2741 range 0x0 0x40000000 if EVA || 64BIT
1795 CP15DMB - are deprecated in ARMv8 ( !! 2742 range 0x0 0x08000000
1796 strongly recommended to use the ISB !! 2743 default "0x01000000"
1797 instructions instead. !! 2744 help
>> 2745 When kASLR is active, this provides the maximum offset that will
>> 2746 be applied to the kernel image. It should be set according to the
>> 2747 amount of physical RAM available in the target system minus
>> 2748 PHYSICAL_START and must be a power of 2.
1798 2749
1799 Say Y here to enable software emula !! 2750 This is limited by the size of KSEG0, 256Mb on 32-bit or 1Gb with
1800 instructions for AArch32 userspace !! 2751 EVA or 64-bit. The default is 16Mb.
1801 enabled, CP15 barrier usage is trac <<
1802 identify software that needs updati <<
1803 controlled at runtime with the abi. <<
1804 2752
1805 If unsure, say Y !! 2753 config NODES_SHIFT
>> 2754 int
>> 2755 default "6"
>> 2756 depends on NUMA
1806 2757
1807 config SETEND_EMULATION !! 2758 config HW_PERF_EVENTS
1808 bool "Emulate SETEND instruction" !! 2759 bool "Enable hardware performance counter support for perf events"
>> 2760 depends on PERF_EVENTS && (CPU_MIPS32 || CPU_MIPS64 || CPU_R10000 || CPU_SB1 || CPU_CAVIUM_OCTEON || CPU_LOONGSON64)
>> 2761 default y
1809 help 2762 help
1810 The SETEND instruction alters the d !! 2763 Enable hardware performance counter support for perf events. If
1811 AArch32 EL0, and is deprecated in A !! 2764 disabled, perf events will use software events only.
1812 2765
1813 Say Y here to enable software emula !! 2766 config DMI
1814 for AArch32 userspace code. This fe !! 2767 bool "Enable DMI scanning"
1815 at runtime with the abi.setend sysc !! 2768 depends on MACH_LOONGSON64
>> 2769 select DMI_SCAN_MACHINE_NON_EFI_FALLBACK
>> 2770 default y
>> 2771 help
>> 2772 Enabled scanning of DMI to identify machine quirks. Say Y
>> 2773 here unless you have verified that your setup is not
>> 2774 affected by entries in the DMI blacklist. Required by PNP
>> 2775 BIOS code.
1816 2776
1817 Note: All the cpus on the system mu !! 2777 config SMP
1818 for this feature to be enabled. If !! 2778 bool "Multi-Processing support"
1819 endian - is hotplugged in after thi !! 2779 depends on SYS_SUPPORTS_SMP
1820 be unexpected results in the applic !! 2780 help
>> 2781 This enables support for systems with more than one CPU. If you have
>> 2782 a system with only one CPU, say N. If you have a system with more
>> 2783 than one CPU, say Y.
>> 2784
>> 2785 If you say N here, the kernel will run on uni- and multiprocessor
>> 2786 machines, but will use only one CPU of a multiprocessor machine. If
>> 2787 you say Y here, the kernel will run on many, but not all,
>> 2788 uniprocessor machines. On a uniprocessor machine, the kernel
>> 2789 will run faster if you say N here.
1821 2790
1822 If unsure, say Y !! 2791 People using multiprocessor machines who say Y here should also say
1823 endif # ARMV8_DEPRECATED !! 2792 Y to "Enhanced Real Time Clock Support", below.
1824 2793
1825 endif # COMPAT !! 2794 See also the SMP-HOWTO available at
>> 2795 <https://www.tldp.org/docs.html#howto>.
1826 2796
1827 menu "ARMv8.1 architectural features" !! 2797 If you don't know what to do here, say N.
1828 2798
1829 config ARM64_HW_AFDBM !! 2799 config HOTPLUG_CPU
1830 bool "Support for hardware updates of !! 2800 bool "Support for hot-pluggable CPUs"
1831 default y !! 2801 depends on SMP && SYS_SUPPORTS_HOTPLUG_CPU
1832 help 2802 help
1833 The ARMv8.1 architecture extensions !! 2803 Say Y here to allow turning CPUs off and on. CPUs can be
1834 hardware updates of the access and !! 2804 controlled through /sys/devices/system/cpu.
1835 table entries. When enabled in TCR_ !! 2805 (Note: power management support will enable this option
1836 capable processors, accesses to pag !! 2806 automatically on SMP systems. )
1837 set this bit instead of raising an !! 2807 Say N if you want to disable CPU hotplug.
1838 Similarly, writes to read-only page <<
1839 clear the read-only bit (AP[2]) ins <<
1840 permission fault. <<
1841 <<
1842 Kernels built with this configurati <<
1843 to work on pre-ARMv8.1 hardware and <<
1844 minimal. If unsure, say Y. <<
1845 2808
1846 config ARM64_PAN !! 2809 config SMP_UP
1847 bool "Enable support for Privileged A !! 2810 bool
1848 default y <<
1849 help <<
1850 Privileged Access Never (PAN; part <<
1851 prevents the kernel or hypervisor f <<
1852 memory directly. <<
1853 2811
1854 Choosing this option will cause any !! 2812 config SYS_SUPPORTS_MIPS_CMP
1855 copy_to_user et al) memory access t !! 2813 bool
1856 2814
1857 The feature is detected at runtime, !! 2815 config SYS_SUPPORTS_MIPS_CPS
1858 instruction if the cpu does not imp !! 2816 bool
1859 2817
1860 config AS_HAS_LSE_ATOMICS !! 2818 config SYS_SUPPORTS_SMP
1861 def_bool $(as-instr,.arch_extension l !! 2819 bool
1862 2820
1863 config ARM64_LSE_ATOMICS !! 2821 config NR_CPUS_DEFAULT_4
1864 bool 2822 bool
1865 default ARM64_USE_LSE_ATOMICS <<
1866 depends on AS_HAS_LSE_ATOMICS <<
1867 2823
1868 config ARM64_USE_LSE_ATOMICS !! 2824 config NR_CPUS_DEFAULT_8
1869 bool "Atomic instructions" !! 2825 bool
1870 default y <<
1871 help <<
1872 As part of the Large System Extensi <<
1873 atomic instructions that are design <<
1874 very large systems. <<
1875 2826
1876 Say Y here to make use of these ins !! 2827 config NR_CPUS_DEFAULT_16
1877 atomic routines. This incurs a smal !! 2828 bool
1878 not support these instructions and <<
1879 built with binutils >= 2.25 in orde <<
1880 to be used. <<
1881 2829
1882 endmenu # "ARMv8.1 architectural features" !! 2830 config NR_CPUS_DEFAULT_32
>> 2831 bool
1883 2832
1884 menu "ARMv8.2 architectural features" !! 2833 config NR_CPUS_DEFAULT_64
>> 2834 bool
1885 2835
1886 config AS_HAS_ARMV8_2 !! 2836 config NR_CPUS
1887 def_bool $(cc-option,-Wa$(comma)-marc !! 2837 int "Maximum number of CPUs (2-256)"
>> 2838 range 2 256
>> 2839 depends on SMP
>> 2840 default "4" if NR_CPUS_DEFAULT_4
>> 2841 default "8" if NR_CPUS_DEFAULT_8
>> 2842 default "16" if NR_CPUS_DEFAULT_16
>> 2843 default "32" if NR_CPUS_DEFAULT_32
>> 2844 default "64" if NR_CPUS_DEFAULT_64
>> 2845 help
>> 2846 This allows you to specify the maximum number of CPUs which this
>> 2847 kernel will support. The maximum supported value is 32 for 32-bit
>> 2848 kernel and 64 for 64-bit kernels; the minimum value which makes
>> 2849 sense is 1 for Qemu (useful only for kernel debugging purposes)
>> 2850 and 2 for all others.
>> 2851
>> 2852 This is purely to save memory - each supported CPU adds
>> 2853 approximately eight kilobytes to the kernel image. For best
>> 2854 performance should round up your number of processors to the next
>> 2855 power of two.
1888 2856
1889 config AS_HAS_SHA3 !! 2857 config MIPS_PERF_SHARED_TC_COUNTERS
1890 def_bool $(as-instr,.arch armv8.2-a+s !! 2858 bool
1891 2859
1892 config ARM64_PMEM !! 2860 config MIPS_NR_CPU_NR_MAP_1024
1893 bool "Enable support for persistent m !! 2861 bool
1894 select ARCH_HAS_PMEM_API <<
1895 select ARCH_HAS_UACCESS_FLUSHCACHE <<
1896 help <<
1897 Say Y to enable support for the per <<
1898 ARMv8.2 DCPoP feature. <<
1899 2862
1900 The feature is detected at runtime, !! 2863 config MIPS_NR_CPU_NR_MAP
1901 operations if DC CVAP is not suppor !! 2864 int
1902 DC CVAP itself if the system does n !! 2865 depends on SMP
>> 2866 default 1024 if MIPS_NR_CPU_NR_MAP_1024
>> 2867 default NR_CPUS if !MIPS_NR_CPU_NR_MAP_1024
1903 2868
1904 config ARM64_RAS_EXTN !! 2869 #
1905 bool "Enable support for RAS CPU Exte !! 2870 # Timer Interrupt Frequency Configuration
1906 default y !! 2871 #
1907 help <<
1908 CPUs that support the Reliability, <<
1909 (RAS) Extensions, part of ARMv8.2 a <<
1910 errors, classify them and report th <<
1911 <<
1912 On CPUs with these extensions syste <<
1913 barriers to determine if faults are <<
1914 classification from a new set of re <<
1915 <<
1916 Selecting this feature will allow t <<
1917 and access the new registers if the <<
1918 Platform RAS features may additiona <<
1919 2872
1920 config ARM64_CNP !! 2873 choice
1921 bool "Enable support for Common Not P !! 2874 prompt "Timer frequency"
1922 default y !! 2875 default HZ_250
1923 depends on ARM64_PAN || !ARM64_SW_TTB <<
1924 help 2876 help
1925 Common Not Private (CNP) allows tra !! 2877 Allows the configuration of the timer frequency.
1926 be shared between different PEs in <<
1927 domain, so the hardware can use thi <<
1928 caching of such entries in the TLB. <<
1929 <<
1930 Selecting this option allows the CN <<
1931 at runtime, and does not affect PEs <<
1932 this feature. <<
1933 2878
1934 endmenu # "ARMv8.2 architectural features" !! 2879 config HZ_24
>> 2880 bool "24 HZ" if SYS_SUPPORTS_24HZ || SYS_SUPPORTS_ARBIT_HZ
1935 2881
1936 menu "ARMv8.3 architectural features" !! 2882 config HZ_48
1937 !! 2883 bool "48 HZ" if SYS_SUPPORTS_48HZ || SYS_SUPPORTS_ARBIT_HZ
1938 config ARM64_PTR_AUTH <<
1939 bool "Enable support for pointer auth <<
1940 default y <<
1941 help <<
1942 Pointer authentication (part of the <<
1943 instructions for signing and authen <<
1944 keys, which can be used to mitigate <<
1945 and other attacks. <<
1946 <<
1947 This option enables these instructi <<
1948 Choosing this option will cause the <<
1949 for each process at exec() time, wi <<
1950 context-switched along with the pro <<
1951 <<
1952 The feature is detected at runtime. <<
1953 hardware it will not be advertised <<
1954 be enabled. <<
1955 <<
1956 If the feature is present on the bo <<
1957 the late CPU will be parked. Also, <<
1958 address auth and the late CPU has t <<
1959 but with the feature disabled. On s <<
1960 not be selected. <<
1961 2884
1962 config ARM64_PTR_AUTH_KERNEL !! 2885 config HZ_100
1963 bool "Use pointer authentication for !! 2886 bool "100 HZ" if SYS_SUPPORTS_100HZ || SYS_SUPPORTS_ARBIT_HZ
1964 default y <<
1965 depends on ARM64_PTR_AUTH <<
1966 depends on (CC_HAS_SIGN_RETURN_ADDRES <<
1967 # Modern compilers insert a .note.gnu <<
1968 # which is only understood by binutil <<
1969 depends on LD_IS_LLD || LD_VERSION >= <<
1970 depends on !CC_IS_CLANG || AS_HAS_CFI <<
1971 depends on (!FUNCTION_GRAPH_TRACER || <<
1972 help <<
1973 If the compiler supports the -mbran <<
1974 -msign-return-address flag (e.g. GC <<
1975 will cause the kernel itself to be <<
1976 protection. In this case, and if th <<
1977 support pointer authentication, the <<
1978 disabled with minimal loss of prote <<
1979 <<
1980 This feature works with FUNCTION_GR <<
1981 DYNAMIC_FTRACE_WITH_ARGS is enabled <<
1982 <<
1983 config CC_HAS_BRANCH_PROT_PAC_RET <<
1984 # GCC 9 or later, clang 8 or later <<
1985 def_bool $(cc-option,-mbranch-protect <<
1986 <<
1987 config CC_HAS_SIGN_RETURN_ADDRESS <<
1988 # GCC 7, 8 <<
1989 def_bool $(cc-option,-msign-return-ad <<
1990 <<
1991 config AS_HAS_ARMV8_3 <<
1992 def_bool $(cc-option,-Wa$(comma)-marc <<
1993 <<
1994 config AS_HAS_CFI_NEGATE_RA_STATE <<
1995 def_bool $(as-instr,.cfi_startproc\n. <<
1996 <<
1997 config AS_HAS_LDAPR <<
1998 def_bool $(as-instr,.arch_extension r <<
1999 2887
2000 endmenu # "ARMv8.3 architectural features" !! 2888 config HZ_128
>> 2889 bool "128 HZ" if SYS_SUPPORTS_128HZ || SYS_SUPPORTS_ARBIT_HZ
2001 2890
2002 menu "ARMv8.4 architectural features" !! 2891 config HZ_250
>> 2892 bool "250 HZ" if SYS_SUPPORTS_250HZ || SYS_SUPPORTS_ARBIT_HZ
2003 2893
2004 config ARM64_AMU_EXTN !! 2894 config HZ_256
2005 bool "Enable support for the Activity !! 2895 bool "256 HZ" if SYS_SUPPORTS_256HZ || SYS_SUPPORTS_ARBIT_HZ
2006 default y <<
2007 help <<
2008 The activity monitors extension is <<
2009 by the ARMv8.4 CPU architecture. Th <<
2010 of the activity monitors architectu <<
2011 <<
2012 To enable the use of this extension <<
2013 <<
2014 Note that for architectural reasons <<
2015 support when running on CPUs that p <<
2016 extension. The required support is <<
2017 * Version 1.5 and later of the AR <<
2018 <<
2019 For kernels that have this configur <<
2020 firmware, you may need to say N her <<
2021 Otherwise you may experience firmwa <<
2022 accessing the counter registers. Ev <<
2023 symptoms, the values returned by th <<
2024 correctly reflect reality. Most com <<
2025 indicating that the counter is not <<
2026 2896
2027 config AS_HAS_ARMV8_4 !! 2897 config HZ_1000
2028 def_bool $(cc-option,-Wa$(comma)-marc !! 2898 bool "1000 HZ" if SYS_SUPPORTS_1000HZ || SYS_SUPPORTS_ARBIT_HZ
2029 2899
2030 config ARM64_TLB_RANGE !! 2900 config HZ_1024
2031 bool "Enable support for tlbi range f !! 2901 bool "1024 HZ" if SYS_SUPPORTS_1024HZ || SYS_SUPPORTS_ARBIT_HZ
2032 default y <<
2033 depends on AS_HAS_ARMV8_4 <<
2034 help <<
2035 ARMv8.4-TLBI provides TLBI invalida <<
2036 range of input addresses. <<
2037 2902
2038 The feature introduces new assembly !! 2903 endchoice
2039 support when binutils >= 2.30. <<
2040 2904
2041 endmenu # "ARMv8.4 architectural features" !! 2905 config SYS_SUPPORTS_24HZ
>> 2906 bool
2042 2907
2043 menu "ARMv8.5 architectural features" !! 2908 config SYS_SUPPORTS_48HZ
>> 2909 bool
2044 2910
2045 config AS_HAS_ARMV8_5 !! 2911 config SYS_SUPPORTS_100HZ
2046 def_bool $(cc-option,-Wa$(comma)-marc !! 2912 bool
2047 2913
2048 config ARM64_BTI !! 2914 config SYS_SUPPORTS_128HZ
2049 bool "Branch Target Identification su !! 2915 bool
2050 default y <<
2051 help <<
2052 Branch Target Identification (part <<
2053 provides a mechanism to limit the s <<
2054 branch instructions such as BR or B <<
2055 <<
2056 To make use of BTI on CPUs that sup <<
2057 <<
2058 BTI is intended to provide compleme <<
2059 flow integrity protection mechanism <<
2060 authentication mechanism provided a <<
2061 For this reason, it does not make s <<
2062 also enabling support for pointer a <<
2063 enabling this option you should als <<
2064 <<
2065 Userspace binaries must also be spe <<
2066 this mechanism. If you say N here <<
2067 BTI, such binaries can still run, b <<
2068 enforcement of branch destinations. <<
2069 2916
2070 config ARM64_BTI_KERNEL !! 2917 config SYS_SUPPORTS_250HZ
2071 bool "Use Branch Target Identificatio !! 2918 bool
2072 default y <<
2073 depends on ARM64_BTI <<
2074 depends on ARM64_PTR_AUTH_KERNEL <<
2075 depends on CC_HAS_BRANCH_PROT_PAC_RET <<
2076 # https://gcc.gnu.org/bugzilla/show_b <<
2077 depends on !CC_IS_GCC || GCC_VERSION <<
2078 # https://gcc.gnu.org/bugzilla/show_b <<
2079 depends on !CC_IS_GCC <<
2080 depends on (!FUNCTION_GRAPH_TRACER || <<
2081 help <<
2082 Build the kernel with Branch Target <<
2083 and enable enforcement of this for <<
2084 is enabled and the system supports <<
2085 modular code must have BTI enabled. <<
2086 <<
2087 config CC_HAS_BRANCH_PROT_PAC_RET_BTI <<
2088 # GCC 9 or later, clang 8 or later <<
2089 def_bool $(cc-option,-mbranch-protect <<
2090 2919
2091 config ARM64_E0PD !! 2920 config SYS_SUPPORTS_256HZ
2092 bool "Enable support for E0PD" !! 2921 bool
2093 default y <<
2094 help <<
2095 E0PD (part of the ARMv8.5 extension <<
2096 that EL0 accesses made via TTBR1 al <<
2097 providing similar benefits to KASLR <<
2098 with lower overhead and without dis <<
2099 kernel memory such as SPE. <<
2100 <<
2101 This option enables E0PD for TTBR1 <<
2102 <<
2103 config ARM64_AS_HAS_MTE <<
2104 # Initial support for MTE went in bin <<
2105 # ".arch armv8.5-a+memtag" below. How <<
2106 # as a late addition to the final arc <<
2107 # is only supported in the newer 2.32 <<
2108 # versions, hence the extra "stgm" in <<
2109 def_bool $(as-instr,.arch armv8.5-a+m <<
2110 2922
2111 config ARM64_MTE !! 2923 config SYS_SUPPORTS_1000HZ
2112 bool "Memory Tagging Extension suppor !! 2924 bool
2113 default y <<
2114 depends on ARM64_AS_HAS_MTE && ARM64_ <<
2115 depends on AS_HAS_ARMV8_5 <<
2116 depends on AS_HAS_LSE_ATOMICS <<
2117 # Required for tag checking in the ua <<
2118 depends on ARM64_PAN <<
2119 select ARCH_HAS_SUBPAGE_FAULTS <<
2120 select ARCH_USES_HIGH_VMA_FLAGS <<
2121 select ARCH_USES_PG_ARCH_2 <<
2122 select ARCH_USES_PG_ARCH_3 <<
2123 help <<
2124 Memory Tagging (part of the ARMv8.5 <<
2125 architectural support for run-time, <<
2126 various classes of memory error to <<
2127 to eliminate vulnerabilities arisin <<
2128 languages. <<
2129 <<
2130 This option enables the support for <<
2131 Extension at EL0 (i.e. for userspac <<
2132 <<
2133 Selecting this option allows the fe <<
2134 runtime. Any secondary CPU not impl <<
2135 not be allowed a late bring-up. <<
2136 <<
2137 Userspace binaries that want to use <<
2138 explicitly opt in. The mechanism fo <<
2139 described in: <<
2140 2925
2141 Documentation/arch/arm64/memory-tag !! 2926 config SYS_SUPPORTS_1024HZ
>> 2927 bool
2142 2928
2143 endmenu # "ARMv8.5 architectural features" !! 2929 config SYS_SUPPORTS_ARBIT_HZ
>> 2930 bool
>> 2931 default y if !SYS_SUPPORTS_24HZ && \
>> 2932 !SYS_SUPPORTS_48HZ && \
>> 2933 !SYS_SUPPORTS_100HZ && \
>> 2934 !SYS_SUPPORTS_128HZ && \
>> 2935 !SYS_SUPPORTS_250HZ && \
>> 2936 !SYS_SUPPORTS_256HZ && \
>> 2937 !SYS_SUPPORTS_1000HZ && \
>> 2938 !SYS_SUPPORTS_1024HZ
2144 2939
2145 menu "ARMv8.7 architectural features" !! 2940 config HZ
>> 2941 int
>> 2942 default 24 if HZ_24
>> 2943 default 48 if HZ_48
>> 2944 default 100 if HZ_100
>> 2945 default 128 if HZ_128
>> 2946 default 250 if HZ_250
>> 2947 default 256 if HZ_256
>> 2948 default 1000 if HZ_1000
>> 2949 default 1024 if HZ_1024
>> 2950
>> 2951 config SCHED_HRTICK
>> 2952 def_bool HIGH_RES_TIMERS
>> 2953
>> 2954 config KEXEC
>> 2955 bool "Kexec system call"
>> 2956 select KEXEC_CORE
>> 2957 help
>> 2958 kexec is a system call that implements the ability to shutdown your
>> 2959 current kernel, and to start another kernel. It is like a reboot
>> 2960 but it is independent of the system firmware. And like a reboot
>> 2961 you can start any kernel with it, not just Linux.
>> 2962
>> 2963 The name comes from the similarity to the exec system call.
>> 2964
>> 2965 It is an ongoing process to be certain the hardware in a machine
>> 2966 is properly shutdown, so do not be surprised if this code does not
>> 2967 initially work for you. As of this writing the exact hardware
>> 2968 interface is strongly in flux, so no good recommendation can be
>> 2969 made.
>> 2970
>> 2971 config CRASH_DUMP
>> 2972 bool "Kernel crash dumps"
>> 2973 help
>> 2974 Generate crash dump after being started by kexec.
>> 2975 This should be normally only set in special crash dump kernels
>> 2976 which are loaded in the main kernel with kexec-tools into
>> 2977 a specially reserved region and then later executed after
>> 2978 a crash by kdump/kexec. The crash dump kernel must be compiled
>> 2979 to a memory address not used by the main kernel or firmware using
>> 2980 PHYSICAL_START.
>> 2981
>> 2982 config PHYSICAL_START
>> 2983 hex "Physical address where the kernel is loaded"
>> 2984 default "0xffffffff84000000"
>> 2985 depends on CRASH_DUMP
>> 2986 help
>> 2987 This gives the CKSEG0 or KSEG0 address where the kernel is loaded.
>> 2988 If you plan to use kernel for capturing the crash dump change
>> 2989 this value to start of the reserved region (the "X" value as
>> 2990 specified in the "crashkernel=YM@XM" command line boot parameter
>> 2991 passed to the panic-ed kernel).
>> 2992
>> 2993 config MIPS_O32_FP64_SUPPORT
>> 2994 bool "Support for O32 binaries using 64-bit FP" if !CPU_MIPSR6
>> 2995 depends on 32BIT || MIPS32_O32
>> 2996 help
>> 2997 When this is enabled, the kernel will support use of 64-bit floating
>> 2998 point registers with binaries using the O32 ABI along with the
>> 2999 EF_MIPS_FP64 ELF header flag (typically built with -mfp64). On
>> 3000 32-bit MIPS systems this support is at the cost of increasing the
>> 3001 size and complexity of the compiled FPU emulator. Thus if you are
>> 3002 running a MIPS32 system and know that none of your userland binaries
>> 3003 will require 64-bit floating point, you may wish to reduce the size
>> 3004 of your kernel & potentially improve FP emulation performance by
>> 3005 saying N here.
>> 3006
>> 3007 Although binutils currently supports use of this flag the details
>> 3008 concerning its effect upon the O32 ABI in userland are still being
>> 3009 worked on. In order to avoid userland becoming dependent upon current
>> 3010 behaviour before the details have been finalised, this option should
>> 3011 be considered experimental and only enabled by those working upon
>> 3012 said details.
2146 3013
2147 config ARM64_EPAN !! 3014 If unsure, say N.
2148 bool "Enable support for Enhanced Pri <<
2149 default y <<
2150 depends on ARM64_PAN <<
2151 help <<
2152 Enhanced Privileged Access Never (E <<
2153 Access Never to be used with Execut <<
2154 3015
2155 The feature is detected at runtime, !! 3016 config USE_OF
2156 if the cpu does not implement the f !! 3017 bool
2157 endmenu # "ARMv8.7 architectural features" !! 3018 select OF
>> 3019 select OF_EARLY_FLATTREE
>> 3020 select IRQ_DOMAIN
2158 3021
2159 menu "ARMv8.9 architectural features" !! 3022 config UHI_BOOT
>> 3023 bool
2160 3024
2161 config ARM64_POE !! 3025 config BUILTIN_DTB
2162 prompt "Permission Overlay Extension" !! 3026 bool
2163 def_bool y <<
2164 select ARCH_USES_HIGH_VMA_FLAGS <<
2165 select ARCH_HAS_PKEYS <<
2166 help <<
2167 The Permission Overlay Extension is <<
2168 Protection Keys. Memory Protection <<
2169 enforcing page-based protections, b <<
2170 of the page tables when an applicat <<
2171 3027
2172 For details, see Documentation/core !! 3028 choice
>> 3029 prompt "Kernel appended dtb support" if USE_OF
>> 3030 default MIPS_NO_APPENDED_DTB
2173 3031
2174 If unsure, say y. !! 3032 config MIPS_NO_APPENDED_DTB
>> 3033 bool "None"
>> 3034 help
>> 3035 Do not enable appended dtb support.
>> 3036
>> 3037 config MIPS_ELF_APPENDED_DTB
>> 3038 bool "vmlinux"
>> 3039 help
>> 3040 With this option, the boot code will look for a device tree binary
>> 3041 DTB) included in the vmlinux ELF section .appended_dtb. By default
>> 3042 it is empty and the DTB can be appended using binutils command
>> 3043 objcopy:
>> 3044
>> 3045 objcopy --update-section .appended_dtb=<filename>.dtb vmlinux
>> 3046
>> 3047 This is meant as a backward compatibility convenience for those
>> 3048 systems with a bootloader that can't be upgraded to accommodate
>> 3049 the documented boot protocol using a device tree.
>> 3050
>> 3051 config MIPS_RAW_APPENDED_DTB
>> 3052 bool "vmlinux.bin or vmlinuz.bin"
>> 3053 help
>> 3054 With this option, the boot code will look for a device tree binary
>> 3055 DTB) appended to raw vmlinux.bin or vmlinuz.bin.
>> 3056 (e.g. cat vmlinux.bin <filename>.dtb > vmlinux_w_dtb).
>> 3057
>> 3058 This is meant as a backward compatibility convenience for those
>> 3059 systems with a bootloader that can't be upgraded to accommodate
>> 3060 the documented boot protocol using a device tree.
>> 3061
>> 3062 Beware that there is very little in terms of protection against
>> 3063 this option being confused by leftover garbage in memory that might
>> 3064 look like a DTB header after a reboot if no actual DTB is appended
>> 3065 to vmlinux.bin. Do not leave this option active in a production kernel
>> 3066 if you don't intend to always append a DTB.
>> 3067 endchoice
2175 3068
2176 config ARCH_PKEY_BITS !! 3069 choice
2177 int !! 3070 prompt "Kernel command line type" if !CMDLINE_OVERRIDE
2178 default 3 !! 3071 default MIPS_CMDLINE_FROM_DTB if USE_OF && !ATH79 && !MACH_INGENIC && \
>> 3072 !MACH_LOONGSON64 && !MIPS_MALTA && \
>> 3073 !CAVIUM_OCTEON_SOC
>> 3074 default MIPS_CMDLINE_FROM_BOOTLOADER
>> 3075
>> 3076 config MIPS_CMDLINE_FROM_DTB
>> 3077 depends on USE_OF
>> 3078 bool "Dtb kernel arguments if available"
>> 3079
>> 3080 config MIPS_CMDLINE_DTB_EXTEND
>> 3081 depends on USE_OF
>> 3082 bool "Extend dtb kernel arguments with bootloader arguments"
>> 3083
>> 3084 config MIPS_CMDLINE_FROM_BOOTLOADER
>> 3085 bool "Bootloader kernel arguments if available"
>> 3086
>> 3087 config MIPS_CMDLINE_BUILTIN_EXTEND
>> 3088 depends on CMDLINE_BOOL
>> 3089 bool "Extend builtin kernel arguments with bootloader arguments"
>> 3090 endchoice
2179 3091
2180 endmenu # "ARMv8.9 architectural features" !! 3092 endmenu
2181 3093
2182 config ARM64_SVE !! 3094 config LOCKDEP_SUPPORT
2183 bool "ARM Scalable Vector Extension s !! 3095 bool
2184 default y 3096 default y
2185 help <<
2186 The Scalable Vector Extension (SVE) <<
2187 execution state which complements a <<
2188 of the base architecture to support <<
2189 additional vectorisation opportunit <<
2190 <<
2191 To enable use of this extension on <<
2192 <<
2193 On CPUs that support the SVE2 exten <<
2194 those too. <<
2195 <<
2196 Note that for architectural reasons <<
2197 support when running on SVE capable <<
2198 is present in: <<
2199 <<
2200 * version 1.5 and later of the AR <<
2201 * the AArch64 boot wrapper since <<
2202 ("bootwrapper: SVE: Enable SVE <<
2203 <<
2204 For other firmware implementations, <<
2205 or vendor. <<
2206 <<
2207 If you need the kernel to boot on S <<
2208 firmware, you may need to say N her <<
2209 fixed. Otherwise, you may experien <<
2210 booting the kernel. If unsure and <<
2211 symptoms, you should assume that it <<
2212 3097
2213 config ARM64_SME !! 3098 config STACKTRACE_SUPPORT
2214 bool "ARM Scalable Matrix Extension s !! 3099 bool
2215 default y 3100 default y
2216 depends on ARM64_SVE <<
2217 depends on BROKEN <<
2218 help <<
2219 The Scalable Matrix Extension (SME) <<
2220 execution state which utilises a su <<
2221 instruction set, together with the <<
2222 register state capable of holding t <<
2223 enable various matrix operations. <<
2224 <<
2225 config ARM64_PSEUDO_NMI <<
2226 bool "Support for NMI-like interrupts <<
2227 select ARM_GIC_V3 <<
2228 help <<
2229 Adds support for mimicking Non-Mask <<
2230 GIC interrupt priority. This suppor <<
2231 ARM GIC. <<
2232 <<
2233 This high priority configuration fo <<
2234 explicitly enabled by setting the k <<
2235 "irqchip.gicv3_pseudo_nmi" to 1. <<
2236 <<
2237 If unsure, say N <<
2238 <<
2239 if ARM64_PSEUDO_NMI <<
2240 config ARM64_DEBUG_PRIORITY_MASKING <<
2241 bool "Debug interrupt priority maskin <<
2242 help <<
2243 This adds runtime checks to functio <<
2244 interrupts when using priority mask <<
2245 the validity of ICC_PMR_EL1 when ca <<
2246 3101
2247 If unsure, say N !! 3102 config PGTABLE_LEVELS
2248 endif # ARM64_PSEUDO_NMI !! 3103 int
>> 3104 default 4 if PAGE_SIZE_4KB && MIPS_VA_BITS_48
>> 3105 default 3 if 64BIT && (!PAGE_SIZE_64KB || MIPS_VA_BITS_48)
>> 3106 default 2
2249 3107
2250 config RELOCATABLE !! 3108 config MIPS_AUTO_PFN_OFFSET
2251 bool "Build a relocatable kernel imag !! 3109 bool
2252 select ARCH_HAS_RELR <<
2253 default y <<
2254 help <<
2255 This builds the kernel as a Positio <<
2256 which retains all relocation metada <<
2257 kernel binary at runtime to a diffe <<
2258 address it was linked at. <<
2259 Since AArch64 uses the RELA relocat <<
2260 relocation pass at runtime even if <<
2261 same address it was linked at. <<
2262 3110
2263 config RANDOMIZE_BASE !! 3111 menu "Bus options (PCI, PCMCIA, EISA, ISA, TC)"
2264 bool "Randomize the address of the ke <<
2265 select RELOCATABLE <<
2266 help <<
2267 Randomizes the virtual address at w <<
2268 loaded, as a security feature that <<
2269 relying on knowledge of the locatio <<
2270 <<
2271 It is the bootloader's job to provi <<
2272 random u64 value in /chosen/kaslr-s <<
2273 <<
2274 When booting via the UEFI stub, it <<
2275 EFI_RNG_PROTOCOL implementation (if <<
2276 to the kernel proper. In addition, <<
2277 location of the kernel Image as wel <<
2278 3112
2279 If unsure, say N. !! 3113 config PCI_DRIVERS_GENERIC
>> 3114 select PCI_DOMAINS_GENERIC if PCI
>> 3115 bool
2280 3116
2281 config RANDOMIZE_MODULE_REGION_FULL !! 3117 config PCI_DRIVERS_LEGACY
2282 bool "Randomize the module region ove !! 3118 def_bool !PCI_DRIVERS_GENERIC
2283 depends on RANDOMIZE_BASE !! 3119 select NO_GENERIC_PCI_IOPORT_MAP
2284 default y !! 3120 select PCI_DOMAINS if PCI
2285 help <<
2286 Randomizes the location of the modu <<
2287 covering the core kernel. This way, <<
2288 to leak information about the locat <<
2289 but it does imply that function cal <<
2290 kernel will need to be resolved via <<
2291 <<
2292 When this option is not set, the mo <<
2293 a limited range that contains the [ <<
2294 core kernel, so branch relocations <<
2295 the region is exhausted. In this pa <<
2296 exhaustion, modules might be able t <<
2297 3121
2298 config CC_HAVE_STACKPROTECTOR_SYSREG !! 3122 #
2299 def_bool $(cc-option,-mstack-protecto !! 3123 # ISA support is now enabled via select. Too many systems still have the one
>> 3124 # or other ISA chip on the board that users don't know about so don't expect
>> 3125 # users to choose the right thing ...
>> 3126 #
>> 3127 config ISA
>> 3128 bool
2300 3129
2301 config STACKPROTECTOR_PER_TASK !! 3130 config TC
2302 def_bool y !! 3131 bool "TURBOchannel support"
2303 depends on STACKPROTECTOR && CC_HAVE_ !! 3132 depends on MACH_DECSTATION
>> 3133 help
>> 3134 TURBOchannel is a DEC (now Compaq (now HP)) bus for Alpha and MIPS
>> 3135 processors. TURBOchannel programming specifications are available
>> 3136 at:
>> 3137 <ftp://ftp.hp.com/pub/alphaserver/archive/triadd/>
>> 3138 and:
>> 3139 <http://www.computer-refuge.org/classiccmp/ftp.digital.com/pub/DEC/TriAdd/>
>> 3140 Linux driver support status is documented at:
>> 3141 <http://www.linux-mips.org/wiki/DECstation>
2304 3142
2305 config UNWIND_PATCH_PAC_INTO_SCS !! 3143 config MMU
2306 bool "Enable shadow call stack dynami !! 3144 bool
2307 # needs Clang with https://github.com <<
2308 depends on CC_IS_CLANG && CLANG_VERSI <<
2309 depends on ARM64_PTR_AUTH_KERNEL && C <<
2310 depends on SHADOW_CALL_STACK <<
2311 select UNWIND_TABLES <<
2312 select DYNAMIC_SCS <<
2313 <<
2314 config ARM64_CONTPTE <<
2315 bool "Contiguous PTE mappings for use <<
2316 depends on TRANSPARENT_HUGEPAGE <<
2317 default y 3145 default y
2318 help <<
2319 When enabled, user mappings are con <<
2320 bit, for any mappings that meet the <<
2321 This reduces TLB pressure and impro <<
2322 <<
2323 endmenu # "Kernel Features" <<
2324 <<
2325 menu "Boot options" <<
2326 <<
2327 config ARM64_ACPI_PARKING_PROTOCOL <<
2328 bool "Enable support for the ARM64 AC <<
2329 depends on ACPI <<
2330 help <<
2331 Enable support for the ARM64 ACPI p <<
2332 the kernel will not allow booting t <<
2333 protocol even if the corresponding <<
2334 MADT table. <<
2335 <<
2336 config CMDLINE <<
2337 string "Default kernel command string <<
2338 default "" <<
2339 help <<
2340 Provide a set of default command-li <<
2341 entering them here. As a minimum, y <<
2342 root device (e.g. root=/dev/nfs). <<
2343 3146
2344 choice !! 3147 config ARCH_MMAP_RND_BITS_MIN
2345 prompt "Kernel command line type" !! 3148 default 12 if 64BIT
2346 depends on CMDLINE != "" !! 3149 default 8
2347 default CMDLINE_FROM_BOOTLOADER <<
2348 help <<
2349 Choose how the kernel will handle t <<
2350 command line string. <<
2351 <<
2352 config CMDLINE_FROM_BOOTLOADER <<
2353 bool "Use bootloader kernel arguments <<
2354 help <<
2355 Uses the command-line options passe <<
2356 the boot loader doesn't provide any <<
2357 string provided in CMDLINE will be <<
2358 <<
2359 config CMDLINE_FORCE <<
2360 bool "Always use the default kernel c <<
2361 help <<
2362 Always use the default kernel comma <<
2363 loader passes other arguments to th <<
2364 This is useful if you cannot or don <<
2365 command-line options your boot load <<
2366 3150
2367 endchoice !! 3151 config ARCH_MMAP_RND_BITS_MAX
>> 3152 default 18 if 64BIT
>> 3153 default 15
2368 3154
2369 config EFI_STUB !! 3155 config ARCH_MMAP_RND_COMPAT_BITS_MIN
>> 3156 default 8
>> 3157
>> 3158 config ARCH_MMAP_RND_COMPAT_BITS_MAX
>> 3159 default 15
>> 3160
>> 3161 config I8253
2370 bool 3162 bool
>> 3163 select CLKSRC_I8253
>> 3164 select CLKEVT_I8253
>> 3165 select MIPS_EXTERNAL_TIMER
>> 3166 endmenu
2371 3167
2372 config EFI !! 3168 config TRAD_SIGNALS
2373 bool "UEFI runtime support" !! 3169 bool
2374 depends on OF && !CPU_BIG_ENDIAN <<
2375 depends on KERNEL_MODE_NEON <<
2376 select ARCH_SUPPORTS_ACPI <<
2377 select LIBFDT <<
2378 select UCS2_STRING <<
2379 select EFI_PARAMS_FROM_FDT <<
2380 select EFI_RUNTIME_WRAPPERS <<
2381 select EFI_STUB <<
2382 select EFI_GENERIC_STUB <<
2383 imply IMA_SECURE_AND_OR_TRUSTED_BOOT <<
2384 default y <<
2385 help <<
2386 This option provides support for ru <<
2387 by UEFI firmware (such as non-volat <<
2388 clock, and platform reset). A UEFI <<
2389 allow the kernel to be booted as an <<
2390 is only useful on systems that have <<
2391 <<
2392 config COMPRESSED_INSTALL <<
2393 bool "Install compressed image by def <<
2394 help <<
2395 This makes the regular "make instal <<
2396 image we built, not the legacy unco <<
2397 <<
2398 You can check that a compressed ima <<
2399 "make zinstall" first, and verifyin <<
2400 in your environment before making " <<
2401 you. <<
2402 3170
2403 config DMI !! 3171 config MIPS32_COMPAT
2404 bool "Enable support for SMBIOS (DMI) !! 3172 bool
2405 depends on EFI <<
2406 default y <<
2407 help <<
2408 This enables SMBIOS/DMI feature for <<
2409 3173
2410 This option is only useful on syste !! 3174 config COMPAT
2411 However, even with this option, the !! 3175 bool
2412 continue to boot on existing non-UE <<
2413 3176
2414 endmenu # "Boot options" !! 3177 config MIPS32_O32
>> 3178 bool "Kernel support for o32 binaries"
>> 3179 depends on 64BIT
>> 3180 select ARCH_WANT_OLD_COMPAT_IPC
>> 3181 select COMPAT
>> 3182 select MIPS32_COMPAT
>> 3183 help
>> 3184 Select this option if you want to run o32 binaries. These are pure
>> 3185 32-bit binaries as used by the 32-bit Linux/MIPS port. Most of
>> 3186 existing binaries are in this format.
2415 3187
2416 menu "Power management options" !! 3188 If unsure, say Y.
2417 3189
2418 source "kernel/power/Kconfig" !! 3190 config MIPS32_N32
>> 3191 bool "Kernel support for n32 binaries"
>> 3192 depends on 64BIT
>> 3193 select ARCH_WANT_COMPAT_IPC_PARSE_VERSION
>> 3194 select COMPAT
>> 3195 select MIPS32_COMPAT
>> 3196 help
>> 3197 Select this option if you want to run n32 binaries. These are
>> 3198 64-bit binaries using 32-bit quantities for addressing and certain
>> 3199 data that would normally be 64-bit. They are used in special
>> 3200 cases.
2419 3201
2420 config ARCH_HIBERNATION_POSSIBLE !! 3202 If unsure, say N.
>> 3203
>> 3204 config CC_HAS_MNO_BRANCH_LIKELY
2421 def_bool y 3205 def_bool y
2422 depends on CPU_PM !! 3206 depends on $(cc-option,-mno-branch-likely)
>> 3207
>> 3208 menu "Power management options"
2423 3209
2424 config ARCH_HIBERNATION_HEADER !! 3210 config ARCH_HIBERNATION_POSSIBLE
2425 def_bool y 3211 def_bool y
2426 depends on HIBERNATION !! 3212 depends on SYS_SUPPORTS_HOTPLUG_CPU || !SMP
2427 3213
2428 config ARCH_SUSPEND_POSSIBLE 3214 config ARCH_SUSPEND_POSSIBLE
2429 def_bool y 3215 def_bool y
>> 3216 depends on SYS_SUPPORTS_HOTPLUG_CPU || !SMP
2430 3217
2431 endmenu # "Power management options" !! 3218 source "kernel/power/Kconfig"
2432 3219
2433 menu "CPU Power Management" !! 3220 endmenu
2434 3221
2435 source "drivers/cpuidle/Kconfig" !! 3222 config MIPS_EXTERNAL_TIMER
>> 3223 bool
2436 3224
>> 3225 menu "CPU Power Management"
>> 3226
>> 3227 if CPU_SUPPORTS_CPUFREQ && MIPS_EXTERNAL_TIMER
2437 source "drivers/cpufreq/Kconfig" 3228 source "drivers/cpufreq/Kconfig"
>> 3229 endif # CPU_SUPPORTS_CPUFREQ && MIPS_EXTERNAL_TIMER
2438 3230
2439 endmenu # "CPU Power Management" !! 3231 source "drivers/cpuidle/Kconfig"
2440 3232
2441 source "drivers/acpi/Kconfig" !! 3233 endmenu
2442 3234
2443 source "arch/arm64/kvm/Kconfig" !! 3235 source "arch/mips/kvm/Kconfig"
2444 3236
>> 3237 source "arch/mips/vdso/Kconfig"
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