1 # SPDX-License-Identifier: GPL-2.0-only !! 1 # SPDX-License-Identifier: GPL-2.0
2 config ARM64 !! 2 config MIPS
3 def_bool y !! 3 bool
4 select ACPI_APMT if ACPI !! 4 default y
5 select ACPI_CCA_REQUIRED if ACPI !! 5 select ARCH_32BIT_OFF_T if !64BIT
6 select ACPI_GENERIC_GSI if ACPI !! 6 select ARCH_BINFMT_ELF_STATE if MIPS_FP_SUPPORT
7 select ACPI_GTDT if ACPI !! 7 select ARCH_HAS_CPU_CACHE_ALIASING
8 select ACPI_HOTPLUG_CPU if ACPI_PROCES !! 8 select ARCH_HAS_CPU_FINALIZE_INIT
9 select ACPI_IORT if ACPI !! 9 select ARCH_HAS_CURRENT_STACK_POINTER if !CC_IS_CLANG || CLANG_VERSION >= 140000
10 select ACPI_REDUCED_HARDWARE_ONLY if A !! 10 select ARCH_HAS_DEBUG_VIRTUAL if !64BIT
11 select ACPI_MCFG if (ACPI && PCI) <<
12 select ACPI_SPCR_TABLE if ACPI <<
13 select ACPI_PPTT if ACPI <<
14 select ARCH_HAS_DEBUG_WX <<
15 select ARCH_BINFMT_ELF_EXTRA_PHDRS <<
16 select ARCH_BINFMT_ELF_STATE <<
17 select ARCH_CORRECT_STACKTRACE_ON_KRET <<
18 select ARCH_ENABLE_HUGEPAGE_MIGRATION <<
19 select ARCH_ENABLE_MEMORY_HOTPLUG <<
20 select ARCH_ENABLE_MEMORY_HOTREMOVE <<
21 select ARCH_ENABLE_SPLIT_PMD_PTLOCK if <<
22 select ARCH_ENABLE_THP_MIGRATION if TR <<
23 select ARCH_HAS_CACHE_LINE_SIZE <<
24 select ARCH_HAS_CURRENT_STACK_POINTER <<
25 select ARCH_HAS_DEBUG_VIRTUAL <<
26 select ARCH_HAS_DEBUG_VM_PGTABLE <<
27 select ARCH_HAS_DMA_OPS if XEN <<
28 select ARCH_HAS_DMA_PREP_COHERENT <<
29 select ARCH_HAS_ACPI_TABLE_UPGRADE if <<
30 select ARCH_HAS_FAST_MULTIPLIER <<
31 select ARCH_HAS_FORTIFY_SOURCE 11 select ARCH_HAS_FORTIFY_SOURCE
32 select ARCH_HAS_GCOV_PROFILE_ALL <<
33 select ARCH_HAS_GIGANTIC_PAGE <<
34 select ARCH_HAS_KCOV 12 select ARCH_HAS_KCOV
35 select ARCH_HAS_KERNEL_FPU_SUPPORT if !! 13 select ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE if !EVA
36 select ARCH_HAS_KEEPINITRD !! 14 select ARCH_HAS_PTE_SPECIAL if !(32BIT && CPU_HAS_RIXI)
37 select ARCH_HAS_MEMBARRIER_SYNC_CORE !! 15 select ARCH_HAS_STRNCPY_FROM_USER
38 select ARCH_HAS_MEM_ENCRYPT !! 16 select ARCH_HAS_STRNLEN_USER
39 select ARCH_HAS_NMI_SAFE_THIS_CPU_OPS <<
40 select ARCH_HAS_NON_OVERLAPPING_ADDRES <<
41 select ARCH_HAS_PTE_DEVMAP <<
42 select ARCH_HAS_PTE_SPECIAL <<
43 select ARCH_HAS_HW_PTE_YOUNG <<
44 select ARCH_HAS_SETUP_DMA_OPS <<
45 select ARCH_HAS_SET_DIRECT_MAP <<
46 select ARCH_HAS_SET_MEMORY <<
47 select ARCH_STACKWALK <<
48 select ARCH_HAS_STRICT_KERNEL_RWX <<
49 select ARCH_HAS_STRICT_MODULE_RWX <<
50 select ARCH_HAS_SYNC_DMA_FOR_DEVICE <<
51 select ARCH_HAS_SYNC_DMA_FOR_CPU <<
52 select ARCH_HAS_SYSCALL_WRAPPER <<
53 select ARCH_HAS_TICK_BROADCAST if GENE 17 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
54 select ARCH_HAS_ZONE_DMA_SET if EXPERT !! 18 select ARCH_HAS_UBSAN
55 select ARCH_HAVE_ELF_PROT !! 19 select ARCH_HAS_GCOV_PROFILE_ALL
56 select ARCH_HAVE_NMI_SAFE_CMPXCHG <<
57 select ARCH_HAVE_TRACE_MMIO_ACCESS <<
58 select ARCH_INLINE_READ_LOCK if !PREEM <<
59 select ARCH_INLINE_READ_LOCK_BH if !PR <<
60 select ARCH_INLINE_READ_LOCK_IRQ if !P <<
61 select ARCH_INLINE_READ_LOCK_IRQSAVE i <<
62 select ARCH_INLINE_READ_UNLOCK if !PRE <<
63 select ARCH_INLINE_READ_UNLOCK_BH if ! <<
64 select ARCH_INLINE_READ_UNLOCK_IRQ if <<
65 select ARCH_INLINE_READ_UNLOCK_IRQREST <<
66 select ARCH_INLINE_WRITE_LOCK if !PREE <<
67 select ARCH_INLINE_WRITE_LOCK_BH if !P <<
68 select ARCH_INLINE_WRITE_LOCK_IRQ if ! <<
69 select ARCH_INLINE_WRITE_LOCK_IRQSAVE <<
70 select ARCH_INLINE_WRITE_UNLOCK if !PR <<
71 select ARCH_INLINE_WRITE_UNLOCK_BH if <<
72 select ARCH_INLINE_WRITE_UNLOCK_IRQ if <<
73 select ARCH_INLINE_WRITE_UNLOCK_IRQRES <<
74 select ARCH_INLINE_SPIN_TRYLOCK if !PR <<
75 select ARCH_INLINE_SPIN_TRYLOCK_BH if <<
76 select ARCH_INLINE_SPIN_LOCK if !PREEM <<
77 select ARCH_INLINE_SPIN_LOCK_BH if !PR <<
78 select ARCH_INLINE_SPIN_LOCK_IRQ if !P <<
79 select ARCH_INLINE_SPIN_LOCK_IRQSAVE i <<
80 select ARCH_INLINE_SPIN_UNLOCK if !PRE <<
81 select ARCH_INLINE_SPIN_UNLOCK_BH if ! <<
82 select ARCH_INLINE_SPIN_UNLOCK_IRQ if <<
83 select ARCH_INLINE_SPIN_UNLOCK_IRQREST <<
84 select ARCH_KEEP_MEMBLOCK 20 select ARCH_KEEP_MEMBLOCK
85 select ARCH_MHP_MEMMAP_ON_MEMORY_ENABL !! 21 select ARCH_USE_BUILTIN_BSWAP
86 select ARCH_USE_CMPXCHG_LOCKREF !! 22 select ARCH_USE_CMPXCHG_LOCKREF if 64BIT
87 select ARCH_USE_GNU_PROPERTY <<
88 select ARCH_USE_MEMTEST 23 select ARCH_USE_MEMTEST
89 select ARCH_USE_QUEUED_RWLOCKS 24 select ARCH_USE_QUEUED_RWLOCKS
90 select ARCH_USE_QUEUED_SPINLOCKS 25 select ARCH_USE_QUEUED_SPINLOCKS
91 select ARCH_USE_SYM_ANNOTATIONS !! 26 select ARCH_SUPPORTS_HUGETLBFS if CPU_SUPPORTS_HUGEPAGES
92 select ARCH_SUPPORTS_DEBUG_PAGEALLOC !! 27 select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT if MMU
93 select ARCH_SUPPORTS_HUGETLBFS !! 28 select ARCH_WANT_IPC_PARSE_VERSION
94 select ARCH_SUPPORTS_MEMORY_FAILURE <<
95 select ARCH_SUPPORTS_SHADOW_CALL_STACK <<
96 select ARCH_SUPPORTS_LTO_CLANG if CPU_ <<
97 select ARCH_SUPPORTS_LTO_CLANG_THIN <<
98 select ARCH_SUPPORTS_CFI_CLANG <<
99 select ARCH_SUPPORTS_ATOMIC_RMW <<
100 select ARCH_SUPPORTS_INT128 if CC_HAS_ <<
101 select ARCH_SUPPORTS_NUMA_BALANCING <<
102 select ARCH_SUPPORTS_PAGE_TABLE_CHECK <<
103 select ARCH_SUPPORTS_PER_VMA_LOCK <<
104 select ARCH_SUPPORTS_HUGE_PFNMAP if TR <<
105 select ARCH_SUPPORTS_RT <<
106 select ARCH_WANT_BATCHED_UNMAP_TLB_FLU <<
107 select ARCH_WANT_COMPAT_IPC_PARSE_VERS <<
108 select ARCH_WANT_DEFAULT_BPF_JIT <<
109 select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_ <<
110 select ARCH_WANT_FRAME_POINTERS <<
111 select ARCH_WANT_HUGE_PMD_SHARE if ARM <<
112 select ARCH_WANT_LD_ORPHAN_WARN 29 select ARCH_WANT_LD_ORPHAN_WARN
113 select ARCH_WANTS_EXECMEM_LATE if EXEC <<
114 select ARCH_WANTS_NO_INSTR <<
115 select ARCH_WANTS_THP_SWAP if ARM64_4K <<
116 select ARCH_HAS_UBSAN <<
117 select ARM_AMBA <<
118 select ARM_ARCH_TIMER <<
119 select ARM_GIC <<
120 select AUDIT_ARCH_COMPAT_GENERIC <<
121 select ARM_GIC_V2M if PCI <<
122 select ARM_GIC_V3 <<
123 select ARM_GIC_V3_ITS if PCI <<
124 select ARM_PSCI_FW <<
125 select BUILDTIME_TABLE_SORT 30 select BUILDTIME_TABLE_SORT
126 select CLONE_BACKWARDS 31 select CLONE_BACKWARDS
127 select COMMON_CLK !! 32 select CPU_NO_EFFICIENT_FFS if (TARGET_ISA_REV < 1)
128 select CPU_PM if (SUSPEND || CPU_IDLE) !! 33 select CPU_PM if CPU_IDLE
129 select CPUMASK_OFFSTACK if NR_CPUS > 2 !! 34 select GENERIC_ATOMIC64 if !64BIT
130 select CRC32 !! 35 select GENERIC_CMOS_UPDATE
131 select DCACHE_WORD_ACCESS <<
132 select DYNAMIC_FTRACE if FUNCTION_TRAC <<
133 select DMA_BOUNCE_UNALIGNED_KMALLOC <<
134 select DMA_DIRECT_REMAP <<
135 select EDAC_SUPPORT <<
136 select FRAME_POINTER <<
137 select FUNCTION_ALIGNMENT_4B <<
138 select FUNCTION_ALIGNMENT_8B if DYNAMI <<
139 select GENERIC_ALLOCATOR <<
140 select GENERIC_ARCH_TOPOLOGY <<
141 select GENERIC_CLOCKEVENTS_BROADCAST <<
142 select GENERIC_CPU_AUTOPROBE 36 select GENERIC_CPU_AUTOPROBE
143 select GENERIC_CPU_DEVICES !! 37 select GENERIC_GETTIMEOFDAY
144 select GENERIC_CPU_VULNERABILITIES !! 38 select GENERIC_IOMAP
145 select GENERIC_EARLY_IOREMAP <<
146 select GENERIC_IDLE_POLL_SETUP <<
147 select GENERIC_IOREMAP <<
148 select GENERIC_IRQ_IPI <<
149 select GENERIC_IRQ_PROBE 39 select GENERIC_IRQ_PROBE
150 select GENERIC_IRQ_SHOW 40 select GENERIC_IRQ_SHOW
151 select GENERIC_IRQ_SHOW_LEVEL !! 41 select GENERIC_ISA_DMA if EISA
152 select GENERIC_LIB_DEVMEM_IS_ALLOWED !! 42 select GENERIC_LIB_ASHLDI3
153 select GENERIC_PCI_IOMAP !! 43 select GENERIC_LIB_ASHRDI3
154 select GENERIC_PTDUMP !! 44 select GENERIC_LIB_CMPDI2
155 select GENERIC_SCHED_CLOCK !! 45 select GENERIC_LIB_LSHRDI3
>> 46 select GENERIC_LIB_UCMPDI2
>> 47 select GENERIC_SCHED_CLOCK if !CAVIUM_OCTEON_SOC
156 select GENERIC_SMP_IDLE_THREAD 48 select GENERIC_SMP_IDLE_THREAD
>> 49 select GENERIC_IDLE_POLL_SETUP
157 select GENERIC_TIME_VSYSCALL 50 select GENERIC_TIME_VSYSCALL
158 select GENERIC_GETTIMEOFDAY !! 51 select GUP_GET_PXX_LOW_HIGH if CPU_MIPS32 && PHYS_ADDR_T_64BIT
159 select GENERIC_VDSO_TIME_NS !! 52 select HAS_IOPORT if !NO_IOPORT_MAP || ISA
160 select HARDIRQS_SW_RESEND <<
161 select HAS_IOPORT <<
162 select HAVE_MOVE_PMD <<
163 select HAVE_MOVE_PUD <<
164 select HAVE_PCI <<
165 select HAVE_ACPI_APEI if (ACPI && EFI) <<
166 select HAVE_ALIGNED_STRUCT_PAGE <<
167 select HAVE_ARCH_AUDITSYSCALL <<
168 select HAVE_ARCH_BITREVERSE <<
169 select HAVE_ARCH_COMPILER_H 53 select HAVE_ARCH_COMPILER_H
170 select HAVE_ARCH_HUGE_VMALLOC <<
171 select HAVE_ARCH_HUGE_VMAP <<
172 select HAVE_ARCH_JUMP_LABEL 54 select HAVE_ARCH_JUMP_LABEL
173 select HAVE_ARCH_JUMP_LABEL_RELATIVE !! 55 select HAVE_ARCH_KGDB if MIPS_FP_SUPPORT
174 select HAVE_ARCH_KASAN !! 56 select HAVE_ARCH_MMAP_RND_BITS if MMU
175 select HAVE_ARCH_KASAN_VMALLOC !! 57 select HAVE_ARCH_MMAP_RND_COMPAT_BITS if MMU && COMPAT
176 select HAVE_ARCH_KASAN_SW_TAGS <<
177 select HAVE_ARCH_KASAN_HW_TAGS if ARM6 <<
178 # Some instrumentation may be unsound, <<
179 select HAVE_ARCH_KCSAN if EXPERT <<
180 select HAVE_ARCH_KFENCE <<
181 select HAVE_ARCH_KGDB <<
182 select HAVE_ARCH_MMAP_RND_BITS <<
183 select HAVE_ARCH_MMAP_RND_COMPAT_BITS <<
184 select HAVE_ARCH_PREL32_RELOCATIONS <<
185 select HAVE_ARCH_RANDOMIZE_KSTACK_OFFS <<
186 select HAVE_ARCH_SECCOMP_FILTER 58 select HAVE_ARCH_SECCOMP_FILTER
187 select HAVE_ARCH_STACKLEAK <<
188 select HAVE_ARCH_THREAD_STRUCT_WHITELI <<
189 select HAVE_ARCH_TRACEHOOK 59 select HAVE_ARCH_TRACEHOOK
190 select HAVE_ARCH_TRANSPARENT_HUGEPAGE !! 60 select HAVE_ARCH_TRANSPARENT_HUGEPAGE if CPU_SUPPORTS_HUGEPAGES
191 select HAVE_ARCH_VMAP_STACK <<
192 select HAVE_ARM_SMCCC <<
193 select HAVE_ASM_MODVERSIONS 61 select HAVE_ASM_MODVERSIONS
194 select HAVE_EBPF_JIT <<
195 select HAVE_C_RECORDMCOUNT <<
196 select HAVE_CMPXCHG_DOUBLE <<
197 select HAVE_CMPXCHG_LOCAL <<
198 select HAVE_CONTEXT_TRACKING_USER 62 select HAVE_CONTEXT_TRACKING_USER
>> 63 select HAVE_TIF_NOHZ
>> 64 select HAVE_C_RECORDMCOUNT
199 select HAVE_DEBUG_KMEMLEAK 65 select HAVE_DEBUG_KMEMLEAK
>> 66 select HAVE_DEBUG_STACKOVERFLOW
200 select HAVE_DMA_CONTIGUOUS 67 select HAVE_DMA_CONTIGUOUS
201 select HAVE_DYNAMIC_FTRACE 68 select HAVE_DYNAMIC_FTRACE
202 select HAVE_DYNAMIC_FTRACE_WITH_ARGS \ !! 69 select HAVE_EBPF_JIT if !CPU_MICROMIPS
203 if (GCC_SUPPORTS_DYNAMIC_FTRAC !! 70 select HAVE_EXIT_THREAD
204 CLANG_SUPPORTS_DYNAMIC_FTR <<
205 select HAVE_DYNAMIC_FTRACE_WITH_DIRECT <<
206 if DYNAMIC_FTRACE_WITH_ARGS && <<
207 select HAVE_DYNAMIC_FTRACE_WITH_CALL_O <<
208 if (DYNAMIC_FTRACE_WITH_ARGS & <<
209 (CC_IS_CLANG || !CC_OPTIMI <<
210 select FTRACE_MCOUNT_USE_PATCHABLE_FUN <<
211 if DYNAMIC_FTRACE_WITH_ARGS <<
212 select HAVE_SAMPLE_FTRACE_DIRECT <<
213 select HAVE_SAMPLE_FTRACE_DIRECT_MULTI <<
214 select HAVE_EFFICIENT_UNALIGNED_ACCESS <<
215 select HAVE_GUP_FAST 71 select HAVE_GUP_FAST
216 select HAVE_FTRACE_MCOUNT_RECORD 72 select HAVE_FTRACE_MCOUNT_RECORD
217 select HAVE_FUNCTION_TRACER <<
218 select HAVE_FUNCTION_ERROR_INJECTION <<
219 select HAVE_FUNCTION_GRAPH_TRACER 73 select HAVE_FUNCTION_GRAPH_TRACER
220 select HAVE_FUNCTION_GRAPH_RETVAL !! 74 select HAVE_FUNCTION_TRACER
221 select HAVE_GCC_PLUGINS 75 select HAVE_GCC_PLUGINS
222 select HAVE_HARDLOCKUP_DETECTOR_PERF i !! 76 select HAVE_GENERIC_VDSO
223 HW_PERF_EVENTS && HAVE_PERF_EV <<
224 select HAVE_HW_BREAKPOINT if PERF_EVEN <<
225 select HAVE_IOREMAP_PROT 77 select HAVE_IOREMAP_PROT
>> 78 select HAVE_IRQ_EXIT_ON_IRQ_STACK
226 select HAVE_IRQ_TIME_ACCOUNTING 79 select HAVE_IRQ_TIME_ACCOUNTING
>> 80 select HAVE_KPROBES
>> 81 select HAVE_KRETPROBES
>> 82 select HAVE_LD_DEAD_CODE_DATA_ELIMINATION
227 select HAVE_MOD_ARCH_SPECIFIC 83 select HAVE_MOD_ARCH_SPECIFIC
228 select HAVE_NMI 84 select HAVE_NMI
>> 85 select HAVE_PAGE_SIZE_4KB if !CPU_LOONGSON2EF && !CPU_LOONGSON64
>> 86 select HAVE_PAGE_SIZE_16KB if !CPU_R3000
>> 87 select HAVE_PAGE_SIZE_64KB if !CPU_R3000
229 select HAVE_PERF_EVENTS 88 select HAVE_PERF_EVENTS
230 select HAVE_PERF_EVENTS_NMI if ARM64_P <<
231 select HAVE_PERF_REGS 89 select HAVE_PERF_REGS
232 select HAVE_PERF_USER_STACK_DUMP 90 select HAVE_PERF_USER_STACK_DUMP
233 select HAVE_PREEMPT_DYNAMIC_KEY <<
234 select HAVE_REGS_AND_STACK_ACCESS_API 91 select HAVE_REGS_AND_STACK_ACCESS_API
235 select HAVE_POSIX_CPU_TIMERS_TASK_WORK <<
236 select HAVE_FUNCTION_ARG_ACCESS_API <<
237 select MMU_GATHER_RCU_TABLE_FREE <<
238 select HAVE_RSEQ 92 select HAVE_RSEQ
239 select HAVE_RUST if RUSTC_SUPPORTS_ARM !! 93 select HAVE_SPARSE_SYSCALL_NR
240 select HAVE_STACKPROTECTOR 94 select HAVE_STACKPROTECTOR
241 select HAVE_SYSCALL_TRACEPOINTS 95 select HAVE_SYSCALL_TRACEPOINTS
242 select HAVE_KPROBES !! 96 select HAVE_VIRT_CPU_ACCOUNTING_GEN if 64BIT || !SMP
243 select HAVE_KRETPROBES <<
244 select HAVE_GENERIC_VDSO <<
245 select HOTPLUG_CORE_SYNC_DEAD if HOTPL <<
246 select IRQ_DOMAIN <<
247 select IRQ_FORCED_THREADING 97 select IRQ_FORCED_THREADING
248 select KASAN_VMALLOC if KASAN !! 98 select ISA if EISA
249 select LOCK_MM_AND_FIND_VMA 99 select LOCK_MM_AND_FIND_VMA
250 select MODULES_USE_ELF_RELA !! 100 select MODULES_USE_ELF_REL if MODULES
251 select NEED_DMA_MAP_STATE !! 101 select MODULES_USE_ELF_RELA if MODULES && 64BIT
252 select NEED_SG_DMA_LENGTH !! 102 select PERF_USE_VMALLOC
253 select OF !! 103 select PCI_MSI_ARCH_FALLBACKS if PCI_MSI
254 select OF_EARLY_FLATTREE !! 104 select RTC_LIB
255 select PCI_DOMAINS_GENERIC if PCI <<
256 select PCI_ECAM if (ACPI && PCI) <<
257 select PCI_SYSCALL if PCI <<
258 select POWER_RESET <<
259 select POWER_SUPPLY <<
260 select SPARSE_IRQ <<
261 select SWIOTLB <<
262 select SYSCTL_EXCEPTION_TRACE 105 select SYSCTL_EXCEPTION_TRACE
263 select THREAD_INFO_IN_TASK <<
264 select HAVE_ARCH_USERFAULTFD_MINOR if <<
265 select HAVE_ARCH_USERFAULTFD_WP if USE <<
266 select TRACE_IRQFLAGS_SUPPORT 106 select TRACE_IRQFLAGS_SUPPORT
267 select TRACE_IRQFLAGS_NMI_SUPPORT !! 107 select ARCH_HAS_ELFCORE_COMPAT
268 select HAVE_SOFTIRQ_ON_OWN_STACK !! 108 select HAVE_ARCH_KCSAN if 64BIT
269 select USER_STACKTRACE_SUPPORT <<
270 select VDSO_GETRANDOM <<
271 help <<
272 ARM 64-bit (AArch64) Linux support. <<
273 <<
274 config RUSTC_SUPPORTS_ARM64 <<
275 def_bool y <<
276 depends on CPU_LITTLE_ENDIAN <<
277 # Shadow call stack is only supported <<
278 # <<
279 # When using the UNWIND_PATCH_PAC_INTO <<
280 # required due to use of the -Zfixed-x <<
281 # <<
282 # Otherwise, rustc version 1.82+ is re <<
283 # -Zsanitizer=shadow-call-stack flag. <<
284 depends on !SHADOW_CALL_STACK || RUSTC <<
285 <<
286 config CLANG_SUPPORTS_DYNAMIC_FTRACE_WITH_ARGS <<
287 def_bool CC_IS_CLANG <<
288 # https://github.com/ClangBuiltLinux/l <<
289 depends on AS_IS_GNU || (AS_IS_LLVM && <<
290 <<
291 config GCC_SUPPORTS_DYNAMIC_FTRACE_WITH_ARGS <<
292 def_bool CC_IS_GCC <<
293 depends on $(cc-option,-fpatchable-fun <<
294 <<
295 config 64BIT <<
296 def_bool y <<
297 109
298 config MMU !! 110 config MIPS_FIXUP_BIGPHYS_ADDR
299 def_bool y !! 111 bool
300 112
301 config ARM64_CONT_PTE_SHIFT !! 113 config MIPS_GENERIC
302 int !! 114 bool
303 default 5 if PAGE_SIZE_64KB <<
304 default 7 if PAGE_SIZE_16KB <<
305 default 4 <<
306 115
307 config ARM64_CONT_PMD_SHIFT !! 116 config MACH_GENERIC_CORE
308 int !! 117 bool
309 default 5 if PAGE_SIZE_64KB <<
310 default 5 if PAGE_SIZE_16KB <<
311 default 4 <<
312 118
313 config ARCH_MMAP_RND_BITS_MIN !! 119 config MACH_INGENIC
314 default 14 if PAGE_SIZE_64KB !! 120 bool
315 default 16 if PAGE_SIZE_16KB !! 121 select SYS_SUPPORTS_32BIT_KERNEL
316 default 18 !! 122 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 123 select SYS_SUPPORTS_ZBOOT
>> 124 select DMA_NONCOHERENT
>> 125 select IRQ_MIPS_CPU
>> 126 select PINCTRL
>> 127 select GPIOLIB
>> 128 select COMMON_CLK
>> 129 select GENERIC_IRQ_CHIP
>> 130 select BUILTIN_DTB if MIPS_NO_APPENDED_DTB
>> 131 select USE_OF
>> 132 select CPU_SUPPORTS_CPUFREQ
>> 133 select MIPS_EXTERNAL_TIMER
317 134
318 # max bits determined by the following formula !! 135 menu "Machine selection"
319 # VA_BITS - PAGE_SHIFT - 3 <<
320 config ARCH_MMAP_RND_BITS_MAX <<
321 default 19 if ARM64_VA_BITS=36 <<
322 default 24 if ARM64_VA_BITS=39 <<
323 default 27 if ARM64_VA_BITS=42 <<
324 default 30 if ARM64_VA_BITS=47 <<
325 default 29 if ARM64_VA_BITS=48 && ARM6 <<
326 default 31 if ARM64_VA_BITS=48 && ARM6 <<
327 default 33 if ARM64_VA_BITS=48 <<
328 default 14 if ARM64_64K_PAGES <<
329 default 16 if ARM64_16K_PAGES <<
330 default 18 <<
331 136
332 config ARCH_MMAP_RND_COMPAT_BITS_MIN !! 137 choice
333 default 7 if ARM64_64K_PAGES !! 138 prompt "System type"
334 default 9 if ARM64_16K_PAGES !! 139 default MIPS_GENERIC_KERNEL
335 default 11 <<
336 140
337 config ARCH_MMAP_RND_COMPAT_BITS_MAX !! 141 config MIPS_GENERIC_KERNEL
338 default 16 !! 142 bool "Generic board-agnostic MIPS kernel"
>> 143 select MIPS_GENERIC
>> 144 select BOOT_RAW
>> 145 select BUILTIN_DTB
>> 146 select CEVT_R4K
>> 147 select CLKSRC_MIPS_GIC
>> 148 select COMMON_CLK
>> 149 select CPU_MIPSR2_IRQ_EI
>> 150 select CPU_MIPSR2_IRQ_VI
>> 151 select CSRC_R4K
>> 152 select DMA_NONCOHERENT
>> 153 select HAVE_PCI
>> 154 select IRQ_MIPS_CPU
>> 155 select MACH_GENERIC_CORE
>> 156 select MIPS_AUTO_PFN_OFFSET
>> 157 select MIPS_CPU_SCACHE
>> 158 select MIPS_GIC
>> 159 select MIPS_L1_CACHE_SHIFT_7
>> 160 select NO_EXCEPT_FILL
>> 161 select PCI_DRIVERS_GENERIC
>> 162 select SMP_UP if SMP
>> 163 select SWAP_IO_SPACE
>> 164 select SYS_HAS_CPU_MIPS32_R1
>> 165 select SYS_HAS_CPU_MIPS32_R2
>> 166 select SYS_HAS_CPU_MIPS32_R5
>> 167 select SYS_HAS_CPU_MIPS32_R6
>> 168 select SYS_HAS_CPU_MIPS64_R1
>> 169 select SYS_HAS_CPU_MIPS64_R2
>> 170 select SYS_HAS_CPU_MIPS64_R5
>> 171 select SYS_HAS_CPU_MIPS64_R6
>> 172 select SYS_SUPPORTS_32BIT_KERNEL
>> 173 select SYS_SUPPORTS_64BIT_KERNEL
>> 174 select SYS_SUPPORTS_BIG_ENDIAN
>> 175 select SYS_SUPPORTS_HIGHMEM
>> 176 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 177 select SYS_SUPPORTS_MICROMIPS
>> 178 select SYS_SUPPORTS_MIPS16
>> 179 select SYS_SUPPORTS_MIPS_CPS
>> 180 select SYS_SUPPORTS_MULTITHREADING
>> 181 select SYS_SUPPORTS_RELOCATABLE
>> 182 select SYS_SUPPORTS_SMARTMIPS
>> 183 select SYS_SUPPORTS_ZBOOT
>> 184 select UHI_BOOT
>> 185 select USB_EHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
>> 186 select USB_EHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 187 select USB_OHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
>> 188 select USB_OHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 189 select USB_UHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
>> 190 select USB_UHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 191 select USE_OF
>> 192 help
>> 193 Select this to build a kernel which aims to support multiple boards,
>> 194 generally using a flattened device tree passed from the bootloader
>> 195 using the boot protocol defined in the UHI (Unified Hosting
>> 196 Interface) specification.
>> 197
>> 198 config MIPS_ALCHEMY
>> 199 bool "Alchemy processor based machines"
>> 200 select PHYS_ADDR_T_64BIT
>> 201 select CEVT_R4K
>> 202 select CSRC_R4K
>> 203 select IRQ_MIPS_CPU
>> 204 select DMA_NONCOHERENT # Au1000,1500,1100 aren't, rest is
>> 205 select MIPS_FIXUP_BIGPHYS_ADDR if PCI
>> 206 select SYS_HAS_CPU_MIPS32_R1
>> 207 select SYS_SUPPORTS_32BIT_KERNEL
>> 208 select SYS_SUPPORTS_APM_EMULATION
>> 209 select GPIOLIB
>> 210 select SYS_SUPPORTS_ZBOOT
>> 211 select COMMON_CLK
339 212
340 config NO_IOPORT_MAP !! 213 config ATH25
341 def_bool y if !PCI !! 214 bool "Atheros AR231x/AR531x SoC support"
>> 215 select CEVT_R4K
>> 216 select CSRC_R4K
>> 217 select DMA_NONCOHERENT
>> 218 select IRQ_MIPS_CPU
>> 219 select IRQ_DOMAIN
>> 220 select SYS_HAS_CPU_MIPS32_R1
>> 221 select SYS_SUPPORTS_BIG_ENDIAN
>> 222 select SYS_SUPPORTS_32BIT_KERNEL
>> 223 select SYS_HAS_EARLY_PRINTK
>> 224 help
>> 225 Support for Atheros AR231x and Atheros AR531x based boards
>> 226
>> 227 config ATH79
>> 228 bool "Atheros AR71XX/AR724X/AR913X based boards"
>> 229 select ARCH_HAS_RESET_CONTROLLER
>> 230 select BOOT_RAW
>> 231 select CEVT_R4K
>> 232 select CSRC_R4K
>> 233 select DMA_NONCOHERENT
>> 234 select GPIOLIB
>> 235 select PINCTRL
>> 236 select COMMON_CLK
>> 237 select IRQ_MIPS_CPU
>> 238 select SYS_HAS_CPU_MIPS32_R2
>> 239 select SYS_HAS_EARLY_PRINTK
>> 240 select SYS_SUPPORTS_32BIT_KERNEL
>> 241 select SYS_SUPPORTS_BIG_ENDIAN
>> 242 select SYS_SUPPORTS_MIPS16
>> 243 select SYS_SUPPORTS_ZBOOT_UART_PROM
>> 244 select USE_OF
>> 245 select USB_EHCI_ROOT_HUB_TT if USB_EHCI_HCD_PLATFORM
>> 246 help
>> 247 Support for the Atheros AR71XX/AR724X/AR913X SoCs.
>> 248
>> 249 config BMIPS_GENERIC
>> 250 bool "Broadcom Generic BMIPS kernel"
>> 251 select ARCH_HAS_RESET_CONTROLLER
>> 252 select ARCH_HAS_SYNC_DMA_FOR_CPU_ALL
>> 253 select BOOT_RAW
>> 254 select NO_EXCEPT_FILL
>> 255 select USE_OF
>> 256 select CEVT_R4K
>> 257 select CSRC_R4K
>> 258 select SYNC_R4K
>> 259 select COMMON_CLK
>> 260 select BCM6345_L1_IRQ
>> 261 select BCM7038_L1_IRQ
>> 262 select BCM7120_L2_IRQ
>> 263 select BRCMSTB_L2_IRQ
>> 264 select IRQ_MIPS_CPU
>> 265 select DMA_NONCOHERENT
>> 266 select SYS_SUPPORTS_32BIT_KERNEL
>> 267 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 268 select SYS_SUPPORTS_BIG_ENDIAN
>> 269 select SYS_SUPPORTS_HIGHMEM
>> 270 select SYS_HAS_CPU_BMIPS32_3300
>> 271 select SYS_HAS_CPU_BMIPS4350
>> 272 select SYS_HAS_CPU_BMIPS4380
>> 273 select SYS_HAS_CPU_BMIPS5000
>> 274 select SWAP_IO_SPACE
>> 275 select USB_EHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
>> 276 select USB_EHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 277 select USB_OHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
>> 278 select USB_OHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 279 select HARDIRQS_SW_RESEND
>> 280 select HAVE_PCI
>> 281 select PCI_DRIVERS_GENERIC
>> 282 select FW_CFE
>> 283 help
>> 284 Build a generic DT-based kernel image that boots on select
>> 285 BCM33xx cable modem chips, BCM63xx DSL chips, and BCM7xxx set-top
>> 286 box chips. Note that CONFIG_CPU_BIG_ENDIAN/CONFIG_CPU_LITTLE_ENDIAN
>> 287 must be set appropriately for your board.
>> 288
>> 289 config BCM47XX
>> 290 bool "Broadcom BCM47XX based boards"
>> 291 select BOOT_RAW
>> 292 select CEVT_R4K
>> 293 select CSRC_R4K
>> 294 select DMA_NONCOHERENT
>> 295 select HAVE_PCI
>> 296 select IRQ_MIPS_CPU
>> 297 select SYS_HAS_CPU_MIPS32_R1
>> 298 select NO_EXCEPT_FILL
>> 299 select SYS_SUPPORTS_32BIT_KERNEL
>> 300 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 301 select SYS_SUPPORTS_MIPS16
>> 302 select SYS_SUPPORTS_ZBOOT
>> 303 select SYS_HAS_EARLY_PRINTK
>> 304 select USE_GENERIC_EARLY_PRINTK_8250
>> 305 select GPIOLIB
>> 306 select LEDS_GPIO_REGISTER
>> 307 select BCM47XX_NVRAM
>> 308 select BCM47XX_SPROM
>> 309 select BCM47XX_SSB if !BCM47XX_BCMA
>> 310 help
>> 311 Support for BCM47XX based boards
>> 312
>> 313 config BCM63XX
>> 314 bool "Broadcom BCM63XX based boards"
>> 315 select BOOT_RAW
>> 316 select CEVT_R4K
>> 317 select CSRC_R4K
>> 318 select SYNC_R4K
>> 319 select DMA_NONCOHERENT
>> 320 select IRQ_MIPS_CPU
>> 321 select SYS_SUPPORTS_32BIT_KERNEL
>> 322 select SYS_SUPPORTS_BIG_ENDIAN
>> 323 select SYS_HAS_EARLY_PRINTK
>> 324 select SYS_HAS_CPU_BMIPS32_3300
>> 325 select SYS_HAS_CPU_BMIPS4350
>> 326 select SYS_HAS_CPU_BMIPS4380
>> 327 select SWAP_IO_SPACE
>> 328 select GPIOLIB
>> 329 select MIPS_L1_CACHE_SHIFT_4
>> 330 select HAVE_LEGACY_CLK
>> 331 help
>> 332 Support for BCM63XX based boards
>> 333
>> 334 config MIPS_COBALT
>> 335 bool "Cobalt Server"
>> 336 select CEVT_R4K
>> 337 select CSRC_R4K
>> 338 select CEVT_GT641XX
>> 339 select DMA_NONCOHERENT
>> 340 select FORCE_PCI
>> 341 select I8253
>> 342 select I8259
>> 343 select IRQ_MIPS_CPU
>> 344 select IRQ_GT641XX
>> 345 select PCI_GT64XXX_PCI0
>> 346 select SYS_HAS_CPU_NEVADA
>> 347 select SYS_HAS_EARLY_PRINTK
>> 348 select SYS_SUPPORTS_32BIT_KERNEL
>> 349 select SYS_SUPPORTS_64BIT_KERNEL
>> 350 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 351 select USE_GENERIC_EARLY_PRINTK_8250
>> 352
>> 353 config MACH_DECSTATION
>> 354 bool "DECstations"
>> 355 select BOOT_ELF32
>> 356 select CEVT_DS1287
>> 357 select CEVT_R4K if CPU_R4X00
>> 358 select CSRC_IOASIC
>> 359 select CSRC_R4K if CPU_R4X00
>> 360 select CPU_DADDI_WORKAROUNDS if 64BIT
>> 361 select CPU_R4000_WORKAROUNDS if 64BIT
>> 362 select CPU_R4400_WORKAROUNDS if 64BIT
>> 363 select DMA_NONCOHERENT
>> 364 select NO_IOPORT_MAP
>> 365 select IRQ_MIPS_CPU
>> 366 select SYS_HAS_CPU_R3000
>> 367 select SYS_HAS_CPU_R4X00
>> 368 select SYS_SUPPORTS_32BIT_KERNEL
>> 369 select SYS_SUPPORTS_64BIT_KERNEL
>> 370 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 371 select SYS_SUPPORTS_128HZ
>> 372 select SYS_SUPPORTS_256HZ
>> 373 select SYS_SUPPORTS_1024HZ
>> 374 select MIPS_L1_CACHE_SHIFT_4
>> 375 help
>> 376 This enables support for DEC's MIPS based workstations. For details
>> 377 see the Linux/MIPS FAQ on <http://www.linux-mips.org/> and the
>> 378 DECstation porting pages on <http://decstation.unix-ag.org/>.
>> 379
>> 380 If you have one of the following DECstation Models you definitely
>> 381 want to choose R4xx0 for the CPU Type:
>> 382
>> 383 DECstation 5000/50
>> 384 DECstation 5000/150
>> 385 DECstation 5000/260
>> 386 DECsystem 5900/260
>> 387
>> 388 otherwise choose R3000.
>> 389
>> 390 config MACH_JAZZ
>> 391 bool "Jazz family of machines"
>> 392 select ARC_MEMORY
>> 393 select ARC_PROMLIB
>> 394 select ARCH_MIGHT_HAVE_PC_PARPORT
>> 395 select ARCH_MIGHT_HAVE_PC_SERIO
>> 396 select DMA_OPS
>> 397 select FW_ARC
>> 398 select FW_ARC32
>> 399 select ARCH_MAY_HAVE_PC_FDC
>> 400 select CEVT_R4K
>> 401 select CSRC_R4K
>> 402 select DEFAULT_SGI_PARTITION if CPU_BIG_ENDIAN
>> 403 select GENERIC_ISA_DMA
>> 404 select HAVE_PCSPKR_PLATFORM
>> 405 select IRQ_MIPS_CPU
>> 406 select I8253
>> 407 select I8259
>> 408 select ISA
>> 409 select SYS_HAS_CPU_R4X00
>> 410 select SYS_SUPPORTS_32BIT_KERNEL
>> 411 select SYS_SUPPORTS_64BIT_KERNEL
>> 412 select SYS_SUPPORTS_100HZ
>> 413 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 414 help
>> 415 This a family of machines based on the MIPS R4030 chipset which was
>> 416 used by several vendors to build RISC/os and Windows NT workstations.
>> 417 Members include the Acer PICA, MIPS Magnum 4000, MIPS Millennium and
>> 418 Olivetti M700-10 workstations.
>> 419
>> 420 config MACH_INGENIC_SOC
>> 421 bool "Ingenic SoC based machines"
>> 422 select MIPS_GENERIC
>> 423 select MACH_INGENIC
>> 424 select MACH_GENERIC_CORE
>> 425 select SYS_SUPPORTS_ZBOOT_UART16550
>> 426 select CPU_SUPPORTS_CPUFREQ
>> 427 select MIPS_EXTERNAL_TIMER
>> 428
>> 429 config LANTIQ
>> 430 bool "Lantiq based platforms"
>> 431 select DMA_NONCOHERENT
>> 432 select IRQ_MIPS_CPU
>> 433 select CEVT_R4K
>> 434 select CSRC_R4K
>> 435 select NO_EXCEPT_FILL
>> 436 select SYS_HAS_CPU_MIPS32_R1
>> 437 select SYS_HAS_CPU_MIPS32_R2
>> 438 select SYS_SUPPORTS_BIG_ENDIAN
>> 439 select SYS_SUPPORTS_32BIT_KERNEL
>> 440 select SYS_SUPPORTS_MIPS16
>> 441 select SYS_SUPPORTS_MULTITHREADING
>> 442 select SYS_SUPPORTS_VPE_LOADER
>> 443 select SYS_HAS_EARLY_PRINTK
>> 444 select GPIOLIB
>> 445 select SWAP_IO_SPACE
>> 446 select BOOT_RAW
>> 447 select HAVE_LEGACY_CLK
>> 448 select USE_OF
>> 449 select PINCTRL
>> 450 select PINCTRL_LANTIQ
>> 451 select ARCH_HAS_RESET_CONTROLLER
>> 452 select RESET_CONTROLLER
>> 453
>> 454 config MACH_LOONGSON32
>> 455 bool "Loongson 32-bit family of machines"
>> 456 select SYS_SUPPORTS_ZBOOT
>> 457 help
>> 458 This enables support for the Loongson-1 family of machines.
>> 459
>> 460 Loongson-1 is a family of 32-bit MIPS-compatible SoCs developed by
>> 461 the Institute of Computing Technology (ICT), Chinese Academy of
>> 462 Sciences (CAS).
>> 463
>> 464 config MACH_LOONGSON2EF
>> 465 bool "Loongson-2E/F family of machines"
>> 466 select SYS_SUPPORTS_ZBOOT
>> 467 help
>> 468 This enables the support of early Loongson-2E/F family of machines.
>> 469
>> 470 config MACH_LOONGSON64
>> 471 bool "Loongson 64-bit family of machines"
>> 472 select ARCH_DMA_DEFAULT_COHERENT
>> 473 select ARCH_SPARSEMEM_ENABLE
>> 474 select ARCH_MIGHT_HAVE_PC_PARPORT
>> 475 select ARCH_MIGHT_HAVE_PC_SERIO
>> 476 select GENERIC_ISA_DMA_SUPPORT_BROKEN
>> 477 select BOOT_ELF32
>> 478 select BOARD_SCACHE
>> 479 select CSRC_R4K
>> 480 select CEVT_R4K
>> 481 select FORCE_PCI
>> 482 select ISA
>> 483 select I8259
>> 484 select IRQ_MIPS_CPU
>> 485 select NO_EXCEPT_FILL
>> 486 select NR_CPUS_DEFAULT_64
>> 487 select USE_GENERIC_EARLY_PRINTK_8250
>> 488 select PCI_DRIVERS_GENERIC
>> 489 select SYS_HAS_CPU_LOONGSON64
>> 490 select SYS_HAS_EARLY_PRINTK
>> 491 select SYS_SUPPORTS_SMP
>> 492 select SYS_SUPPORTS_HOTPLUG_CPU
>> 493 select SYS_SUPPORTS_NUMA
>> 494 select SYS_SUPPORTS_64BIT_KERNEL
>> 495 select SYS_SUPPORTS_HIGHMEM
>> 496 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 497 select SYS_SUPPORTS_ZBOOT
>> 498 select SYS_SUPPORTS_RELOCATABLE
>> 499 select ZONE_DMA32
>> 500 select COMMON_CLK
>> 501 select USE_OF
>> 502 select BUILTIN_DTB
>> 503 select PCI_HOST_GENERIC
>> 504 select HAVE_ARCH_NODEDATA_EXTENSION if NUMA
>> 505 help
>> 506 This enables the support of Loongson-2/3 family of machines.
>> 507
>> 508 Loongson-2 and Loongson-3 are 64-bit general-purpose processors with
>> 509 GS264/GS464/GS464E/GS464V microarchitecture (except old Loongson-2E
>> 510 and Loongson-2F which will be removed), developed by the Institute
>> 511 of Computing Technology (ICT), Chinese Academy of Sciences (CAS).
>> 512
>> 513 config MIPS_MALTA
>> 514 bool "MIPS Malta board"
>> 515 select ARCH_MAY_HAVE_PC_FDC
>> 516 select ARCH_MIGHT_HAVE_PC_PARPORT
>> 517 select ARCH_MIGHT_HAVE_PC_SERIO
>> 518 select BOOT_ELF32
>> 519 select BOOT_RAW
>> 520 select BUILTIN_DTB
>> 521 select CEVT_R4K
>> 522 select CLKSRC_MIPS_GIC
>> 523 select COMMON_CLK
>> 524 select CSRC_R4K
>> 525 select DMA_NONCOHERENT
>> 526 select GENERIC_ISA_DMA
>> 527 select HAVE_PCSPKR_PLATFORM
>> 528 select HAVE_PCI
>> 529 select I8253
>> 530 select I8259
>> 531 select IRQ_MIPS_CPU
>> 532 select MIPS_BONITO64
>> 533 select MIPS_CPU_SCACHE
>> 534 select MIPS_GIC
>> 535 select MIPS_L1_CACHE_SHIFT_6
>> 536 select MIPS_MSC
>> 537 select PCI_GT64XXX_PCI0
>> 538 select SMP_UP if SMP
>> 539 select SWAP_IO_SPACE
>> 540 select SYS_HAS_CPU_MIPS32_R1
>> 541 select SYS_HAS_CPU_MIPS32_R2
>> 542 select SYS_HAS_CPU_MIPS32_R3_5
>> 543 select SYS_HAS_CPU_MIPS32_R5
>> 544 select SYS_HAS_CPU_MIPS32_R6
>> 545 select SYS_HAS_CPU_MIPS64_R1
>> 546 select SYS_HAS_CPU_MIPS64_R2
>> 547 select SYS_HAS_CPU_MIPS64_R6
>> 548 select SYS_HAS_CPU_NEVADA
>> 549 select SYS_HAS_CPU_RM7000
>> 550 select SYS_SUPPORTS_32BIT_KERNEL
>> 551 select SYS_SUPPORTS_64BIT_KERNEL
>> 552 select SYS_SUPPORTS_BIG_ENDIAN
>> 553 select SYS_SUPPORTS_HIGHMEM
>> 554 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 555 select SYS_SUPPORTS_MICROMIPS
>> 556 select SYS_SUPPORTS_MIPS16
>> 557 select SYS_SUPPORTS_MIPS_CPS
>> 558 select SYS_SUPPORTS_MULTITHREADING
>> 559 select SYS_SUPPORTS_RELOCATABLE
>> 560 select SYS_SUPPORTS_SMARTMIPS
>> 561 select SYS_SUPPORTS_VPE_LOADER
>> 562 select SYS_SUPPORTS_ZBOOT
>> 563 select USE_OF
>> 564 select WAR_ICACHE_REFILLS
>> 565 select ZONE_DMA32 if 64BIT
>> 566 help
>> 567 This enables support for the MIPS Technologies Malta evaluation
>> 568 board.
>> 569
>> 570 config MACH_PIC32
>> 571 bool "Microchip PIC32 Family"
>> 572 help
>> 573 This enables support for the Microchip PIC32 family of platforms.
>> 574
>> 575 Microchip PIC32 is a family of general-purpose 32 bit MIPS core
>> 576 microcontrollers.
>> 577
>> 578 config MACH_EYEQ5
>> 579 bool "Mobileye EyeQ5 SoC"
>> 580 select MACH_GENERIC_CORE
>> 581 select ARM_AMBA
>> 582 select PHYSICAL_START_BOOL
>> 583 select ARCH_SPARSEMEM_DEFAULT if 64BIT
>> 584 select BOOT_RAW
>> 585 select BUILTIN_DTB
>> 586 select CEVT_R4K
>> 587 select CLKSRC_MIPS_GIC
>> 588 select COMMON_CLK
>> 589 select CPU_MIPSR2_IRQ_EI
>> 590 select CPU_MIPSR2_IRQ_VI
>> 591 select CSRC_R4K
>> 592 select DMA_NONCOHERENT
>> 593 select HAVE_PCI
>> 594 select IRQ_MIPS_CPU
>> 595 select MIPS_AUTO_PFN_OFFSET
>> 596 select MIPS_CPU_SCACHE
>> 597 select MIPS_GIC
>> 598 select MIPS_L1_CACHE_SHIFT_7
>> 599 select PCI_DRIVERS_GENERIC
>> 600 select SMP_UP if SMP
>> 601 select SWAP_IO_SPACE
>> 602 select SYS_HAS_CPU_MIPS64_R6
>> 603 select SYS_SUPPORTS_64BIT_KERNEL
>> 604 select SYS_SUPPORTS_HIGHMEM
>> 605 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 606 select SYS_SUPPORTS_MIPS_CPS
>> 607 select SYS_SUPPORTS_RELOCATABLE
>> 608 select SYS_SUPPORTS_ZBOOT
>> 609 select UHI_BOOT
>> 610 select USB_EHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
>> 611 select USB_EHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 612 select USB_OHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
>> 613 select USB_OHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 614 select USB_UHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
>> 615 select USB_UHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 616 select USE_OF
>> 617 help
>> 618 Select this to build a kernel supporting EyeQ5 SoC from Mobileye.
342 619
343 config STACKTRACE_SUPPORT !! 620 bool
344 def_bool y <<
345 621
346 config ILLEGAL_POINTER_VALUE !! 622 config MACH_NINTENDO64
347 hex !! 623 bool "Nintendo 64 console"
348 default 0xdead000000000000 !! 624 select CEVT_R4K
>> 625 select CSRC_R4K
>> 626 select SYS_HAS_CPU_R4300
>> 627 select SYS_SUPPORTS_BIG_ENDIAN
>> 628 select SYS_SUPPORTS_ZBOOT
>> 629 select SYS_SUPPORTS_32BIT_KERNEL
>> 630 select SYS_SUPPORTS_64BIT_KERNEL
>> 631 select DMA_NONCOHERENT
>> 632 select IRQ_MIPS_CPU
>> 633
>> 634 config RALINK
>> 635 bool "Ralink based machines"
>> 636 select CEVT_R4K
>> 637 select COMMON_CLK
>> 638 select CSRC_R4K
>> 639 select BOOT_RAW
>> 640 select DMA_NONCOHERENT
>> 641 select IRQ_MIPS_CPU
>> 642 select USE_OF
>> 643 select SYS_HAS_CPU_MIPS32_R2
>> 644 select SYS_SUPPORTS_32BIT_KERNEL
>> 645 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 646 select SYS_SUPPORTS_MIPS16
>> 647 select SYS_SUPPORTS_ZBOOT
>> 648 select SYS_HAS_EARLY_PRINTK
>> 649 select ARCH_HAS_RESET_CONTROLLER
>> 650 select RESET_CONTROLLER
>> 651
>> 652 config MACH_REALTEK_RTL
>> 653 bool "Realtek RTL838x/RTL839x based machines"
>> 654 select MIPS_GENERIC
>> 655 select MACH_GENERIC_CORE
>> 656 select DMA_NONCOHERENT
>> 657 select IRQ_MIPS_CPU
>> 658 select CSRC_R4K
>> 659 select CEVT_R4K
>> 660 select SYS_HAS_CPU_MIPS32_R1
>> 661 select SYS_HAS_CPU_MIPS32_R2
>> 662 select SYS_SUPPORTS_BIG_ENDIAN
>> 663 select SYS_SUPPORTS_32BIT_KERNEL
>> 664 select SYS_SUPPORTS_MIPS16
>> 665 select SYS_SUPPORTS_MULTITHREADING
>> 666 select SYS_SUPPORTS_VPE_LOADER
>> 667 select BOOT_RAW
>> 668 select PINCTRL
>> 669 select USE_OF
>> 670
>> 671 config SGI_IP22
>> 672 bool "SGI IP22 (Indy/Indigo2)"
>> 673 select ARC_MEMORY
>> 674 select ARC_PROMLIB
>> 675 select FW_ARC
>> 676 select FW_ARC32
>> 677 select ARCH_MIGHT_HAVE_PC_SERIO
>> 678 select BOOT_ELF32
>> 679 select CEVT_R4K
>> 680 select CSRC_R4K
>> 681 select DEFAULT_SGI_PARTITION
>> 682 select DMA_NONCOHERENT
>> 683 select HAVE_EISA
>> 684 select I8253
>> 685 select I8259
>> 686 select IP22_CPU_SCACHE
>> 687 select IRQ_MIPS_CPU
>> 688 select GENERIC_ISA_DMA_SUPPORT_BROKEN
>> 689 select SGI_HAS_I8042
>> 690 select SGI_HAS_INDYDOG
>> 691 select SGI_HAS_HAL2
>> 692 select SGI_HAS_SEEQ
>> 693 select SGI_HAS_WD93
>> 694 select SGI_HAS_ZILOG
>> 695 select SWAP_IO_SPACE
>> 696 select SYS_HAS_CPU_R4X00
>> 697 select SYS_HAS_CPU_R5000
>> 698 select SYS_HAS_EARLY_PRINTK
>> 699 select SYS_SUPPORTS_32BIT_KERNEL
>> 700 select SYS_SUPPORTS_64BIT_KERNEL
>> 701 select SYS_SUPPORTS_BIG_ENDIAN
>> 702 select WAR_R4600_V1_INDEX_ICACHEOP
>> 703 select WAR_R4600_V1_HIT_CACHEOP
>> 704 select WAR_R4600_V2_HIT_CACHEOP
>> 705 select MIPS_L1_CACHE_SHIFT_7
>> 706 help
>> 707 This are the SGI Indy, Challenge S and Indigo2, as well as certain
>> 708 OEM variants like the Tandem CMN B006S. To compile a Linux kernel
>> 709 that runs on these, say Y here.
>> 710
>> 711 config SGI_IP27
>> 712 bool "SGI IP27 (Origin200/2000)"
>> 713 select ARCH_HAS_PHYS_TO_DMA
>> 714 select ARCH_SPARSEMEM_ENABLE
>> 715 select FW_ARC
>> 716 select FW_ARC64
>> 717 select ARC_CMDLINE_ONLY
>> 718 select BOOT_ELF64
>> 719 select DEFAULT_SGI_PARTITION
>> 720 select FORCE_PCI
>> 721 select SYS_HAS_EARLY_PRINTK
>> 722 select HAVE_PCI
>> 723 select IRQ_MIPS_CPU
>> 724 select IRQ_DOMAIN_HIERARCHY
>> 725 select NR_CPUS_DEFAULT_64
>> 726 select PCI_DRIVERS_GENERIC
>> 727 select PCI_XTALK_BRIDGE
>> 728 select SYS_HAS_CPU_R10000
>> 729 select SYS_SUPPORTS_64BIT_KERNEL
>> 730 select SYS_SUPPORTS_BIG_ENDIAN
>> 731 select SYS_SUPPORTS_NUMA
>> 732 select SYS_SUPPORTS_SMP
>> 733 select WAR_R10000_LLSC
>> 734 select MIPS_L1_CACHE_SHIFT_7
>> 735 select NUMA
>> 736 select HAVE_ARCH_NODEDATA_EXTENSION
>> 737 help
>> 738 This are the SGI Origin 200, Origin 2000 and Onyx 2 Graphics
>> 739 workstations. To compile a Linux kernel that runs on these, say Y
>> 740 here.
>> 741
>> 742 config SGI_IP28
>> 743 bool "SGI IP28 (Indigo2 R10k)"
>> 744 select ARC_MEMORY
>> 745 select ARC_PROMLIB
>> 746 select FW_ARC
>> 747 select FW_ARC64
>> 748 select ARCH_MIGHT_HAVE_PC_SERIO
>> 749 select BOOT_ELF64
>> 750 select CEVT_R4K
>> 751 select CSRC_R4K
>> 752 select DEFAULT_SGI_PARTITION
>> 753 select DMA_NONCOHERENT
>> 754 select GENERIC_ISA_DMA_SUPPORT_BROKEN
>> 755 select IRQ_MIPS_CPU
>> 756 select HAVE_EISA
>> 757 select I8253
>> 758 select I8259
>> 759 select SGI_HAS_I8042
>> 760 select SGI_HAS_INDYDOG
>> 761 select SGI_HAS_HAL2
>> 762 select SGI_HAS_SEEQ
>> 763 select SGI_HAS_WD93
>> 764 select SGI_HAS_ZILOG
>> 765 select SWAP_IO_SPACE
>> 766 select SYS_HAS_CPU_R10000
>> 767 select SYS_HAS_EARLY_PRINTK
>> 768 select SYS_SUPPORTS_64BIT_KERNEL
>> 769 select SYS_SUPPORTS_BIG_ENDIAN
>> 770 select WAR_R10000_LLSC
>> 771 select MIPS_L1_CACHE_SHIFT_7
>> 772 help
>> 773 This is the SGI Indigo2 with R10000 processor. To compile a Linux
>> 774 kernel that runs on these, say Y here.
>> 775
>> 776 config SGI_IP30
>> 777 bool "SGI IP30 (Octane/Octane2)"
>> 778 select ARCH_HAS_PHYS_TO_DMA
>> 779 select FW_ARC
>> 780 select FW_ARC64
>> 781 select BOOT_ELF64
>> 782 select CEVT_R4K
>> 783 select CSRC_R4K
>> 784 select FORCE_PCI
>> 785 select SYNC_R4K if SMP
>> 786 select ZONE_DMA32
>> 787 select HAVE_PCI
>> 788 select IRQ_MIPS_CPU
>> 789 select IRQ_DOMAIN_HIERARCHY
>> 790 select PCI_DRIVERS_GENERIC
>> 791 select PCI_XTALK_BRIDGE
>> 792 select SYS_HAS_EARLY_PRINTK
>> 793 select SYS_HAS_CPU_R10000
>> 794 select SYS_SUPPORTS_64BIT_KERNEL
>> 795 select SYS_SUPPORTS_BIG_ENDIAN
>> 796 select SYS_SUPPORTS_SMP
>> 797 select WAR_R10000_LLSC
>> 798 select MIPS_L1_CACHE_SHIFT_7
>> 799 select ARC_MEMORY
>> 800 help
>> 801 These are the SGI Octane and Octane2 graphics workstations. To
>> 802 compile a Linux kernel that runs on these, say Y here.
>> 803
>> 804 config SGI_IP32
>> 805 bool "SGI IP32 (O2)"
>> 806 select ARC_MEMORY
>> 807 select ARC_PROMLIB
>> 808 select ARCH_HAS_PHYS_TO_DMA
>> 809 select FW_ARC
>> 810 select FW_ARC32
>> 811 select BOOT_ELF32
>> 812 select CEVT_R4K
>> 813 select CSRC_R4K
>> 814 select DMA_NONCOHERENT
>> 815 select HAVE_PCI
>> 816 select IRQ_MIPS_CPU
>> 817 select R5000_CPU_SCACHE
>> 818 select RM7000_CPU_SCACHE
>> 819 select SYS_HAS_CPU_R5000
>> 820 select SYS_HAS_CPU_R10000 if BROKEN
>> 821 select SYS_HAS_CPU_RM7000
>> 822 select SYS_HAS_CPU_NEVADA
>> 823 select SYS_SUPPORTS_64BIT_KERNEL
>> 824 select SYS_SUPPORTS_BIG_ENDIAN
>> 825 select WAR_ICACHE_REFILLS
>> 826 help
>> 827 If you want this kernel to run on SGI O2 workstation, say Y here.
>> 828
>> 829 config SIBYTE_CRHONE
>> 830 bool "Sibyte BCM91125C-CRhone"
>> 831 select BOOT_ELF32
>> 832 select SIBYTE_BCM1125
>> 833 select SWAP_IO_SPACE
>> 834 select SYS_HAS_CPU_SB1
>> 835 select SYS_SUPPORTS_BIG_ENDIAN
>> 836 select SYS_SUPPORTS_HIGHMEM
>> 837 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 838
>> 839 config SIBYTE_RHONE
>> 840 bool "Sibyte BCM91125E-Rhone"
>> 841 select BOOT_ELF32
>> 842 select SIBYTE_SB1250
>> 843 select SWAP_IO_SPACE
>> 844 select SYS_HAS_CPU_SB1
>> 845 select SYS_SUPPORTS_BIG_ENDIAN
>> 846 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 847
>> 848 config SIBYTE_SWARM
>> 849 bool "Sibyte BCM91250A-SWARM"
>> 850 select BOOT_ELF32
>> 851 select HAVE_PATA_PLATFORM
>> 852 select SIBYTE_SB1250
>> 853 select SWAP_IO_SPACE
>> 854 select SYS_HAS_CPU_SB1
>> 855 select SYS_SUPPORTS_BIG_ENDIAN
>> 856 select SYS_SUPPORTS_HIGHMEM
>> 857 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 858 select ZONE_DMA32 if 64BIT
>> 859 select SWIOTLB if ARCH_DMA_ADDR_T_64BIT && PCI
>> 860
>> 861 config SIBYTE_LITTLESUR
>> 862 bool "Sibyte BCM91250C2-LittleSur"
>> 863 select BOOT_ELF32
>> 864 select HAVE_PATA_PLATFORM
>> 865 select SIBYTE_SB1250
>> 866 select SWAP_IO_SPACE
>> 867 select SYS_HAS_CPU_SB1
>> 868 select SYS_SUPPORTS_BIG_ENDIAN
>> 869 select SYS_SUPPORTS_HIGHMEM
>> 870 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 871 select ZONE_DMA32 if 64BIT
>> 872
>> 873 config SIBYTE_SENTOSA
>> 874 bool "Sibyte BCM91250E-Sentosa"
>> 875 select BOOT_ELF32
>> 876 select SIBYTE_SB1250
>> 877 select SWAP_IO_SPACE
>> 878 select SYS_HAS_CPU_SB1
>> 879 select SYS_SUPPORTS_BIG_ENDIAN
>> 880 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 881 select SWIOTLB if ARCH_DMA_ADDR_T_64BIT && PCI
>> 882
>> 883 config SIBYTE_BIGSUR
>> 884 bool "Sibyte BCM91480B-BigSur"
>> 885 select BOOT_ELF32
>> 886 select NR_CPUS_DEFAULT_4
>> 887 select SIBYTE_BCM1x80
>> 888 select SWAP_IO_SPACE
>> 889 select SYS_HAS_CPU_SB1
>> 890 select SYS_SUPPORTS_BIG_ENDIAN
>> 891 select SYS_SUPPORTS_HIGHMEM
>> 892 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 893 select ZONE_DMA32 if 64BIT
>> 894 select SWIOTLB if ARCH_DMA_ADDR_T_64BIT && PCI
>> 895
>> 896 config SNI_RM
>> 897 bool "SNI RM200/300/400"
>> 898 select ARC_MEMORY
>> 899 select ARC_PROMLIB
>> 900 select FW_ARC if CPU_LITTLE_ENDIAN
>> 901 select FW_ARC32 if CPU_LITTLE_ENDIAN
>> 902 select FW_SNIPROM if CPU_BIG_ENDIAN
>> 903 select ARCH_MAY_HAVE_PC_FDC
>> 904 select ARCH_MIGHT_HAVE_PC_PARPORT
>> 905 select ARCH_MIGHT_HAVE_PC_SERIO
>> 906 select BOOT_ELF32
>> 907 select CEVT_R4K
>> 908 select CSRC_R4K
>> 909 select DEFAULT_SGI_PARTITION if CPU_BIG_ENDIAN
>> 910 select DMA_NONCOHERENT
>> 911 select GENERIC_ISA_DMA
>> 912 select HAVE_EISA
>> 913 select HAVE_PCSPKR_PLATFORM
>> 914 select HAVE_PCI
>> 915 select IRQ_MIPS_CPU
>> 916 select I8253
>> 917 select I8259
>> 918 select ISA
>> 919 select MIPS_L1_CACHE_SHIFT_6
>> 920 select SWAP_IO_SPACE if CPU_BIG_ENDIAN
>> 921 select SYS_HAS_CPU_R4X00
>> 922 select SYS_HAS_CPU_R5000
>> 923 select SYS_HAS_CPU_R10000
>> 924 select R5000_CPU_SCACHE
>> 925 select SYS_HAS_EARLY_PRINTK
>> 926 select SYS_SUPPORTS_32BIT_KERNEL
>> 927 select SYS_SUPPORTS_64BIT_KERNEL
>> 928 select SYS_SUPPORTS_BIG_ENDIAN
>> 929 select SYS_SUPPORTS_HIGHMEM
>> 930 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 931 select WAR_R4600_V2_HIT_CACHEOP
>> 932 help
>> 933 The SNI RM200/300/400 are MIPS-based machines manufactured by
>> 934 Siemens Nixdorf Informationssysteme (SNI), parent company of Pyramid
>> 935 Technology and now in turn merged with Fujitsu. Say Y here to
>> 936 support this machine type.
>> 937
>> 938 config MACH_TX49XX
>> 939 bool "Toshiba TX49 series based machines"
>> 940 select WAR_TX49XX_ICACHE_INDEX_INV
>> 941
>> 942 config MIKROTIK_RB532
>> 943 bool "Mikrotik RB532 boards"
>> 944 select CEVT_R4K
>> 945 select CSRC_R4K
>> 946 select DMA_NONCOHERENT
>> 947 select HAVE_PCI
>> 948 select IRQ_MIPS_CPU
>> 949 select SYS_HAS_CPU_MIPS32_R1
>> 950 select SYS_SUPPORTS_32BIT_KERNEL
>> 951 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 952 select SWAP_IO_SPACE
>> 953 select BOOT_RAW
>> 954 select GPIOLIB
>> 955 select MIPS_L1_CACHE_SHIFT_4
>> 956 help
>> 957 Support the Mikrotik(tm) RouterBoard 532 series,
>> 958 based on the IDT RC32434 SoC.
>> 959
>> 960 config CAVIUM_OCTEON_SOC
>> 961 bool "Cavium Networks Octeon SoC based boards"
>> 962 select CEVT_R4K
>> 963 select ARCH_HAS_PHYS_TO_DMA
>> 964 select HAVE_RAPIDIO
>> 965 select PHYS_ADDR_T_64BIT
>> 966 select SYS_SUPPORTS_64BIT_KERNEL
>> 967 select SYS_SUPPORTS_BIG_ENDIAN
>> 968 select EDAC_SUPPORT
>> 969 select EDAC_ATOMIC_SCRUB
>> 970 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 971 select SYS_SUPPORTS_HOTPLUG_CPU if CPU_BIG_ENDIAN
>> 972 select SYS_HAS_EARLY_PRINTK
>> 973 select SYS_HAS_CPU_CAVIUM_OCTEON
>> 974 select HAVE_PCI
>> 975 select HAVE_PLAT_DELAY
>> 976 select HAVE_PLAT_FW_INIT_CMDLINE
>> 977 select HAVE_PLAT_MEMCPY
>> 978 select ZONE_DMA32
>> 979 select GPIOLIB
>> 980 select USE_OF
>> 981 select ARCH_SPARSEMEM_ENABLE
>> 982 select SYS_SUPPORTS_SMP
>> 983 select NR_CPUS_DEFAULT_64
>> 984 select MIPS_NR_CPU_NR_MAP_1024
>> 985 select BUILTIN_DTB
>> 986 select MTD
>> 987 select MTD_COMPLEX_MAPPINGS
>> 988 select SWIOTLB
>> 989 select SYS_SUPPORTS_RELOCATABLE
>> 990 help
>> 991 This option supports all of the Octeon reference boards from Cavium
>> 992 Networks. It builds a kernel that dynamically determines the Octeon
>> 993 CPU type and supports all known board reference implementations.
>> 994 Some of the supported boards are:
>> 995 EBT3000
>> 996 EBH3000
>> 997 EBH3100
>> 998 Thunder
>> 999 Kodama
>> 1000 Hikari
>> 1001 Say Y here for most Octeon reference boards.
349 1002
350 config LOCKDEP_SUPPORT !! 1003 endchoice
351 def_bool y <<
352 1004
353 config GENERIC_BUG !! 1005 config FIT_IMAGE_FDT_EPM5
354 def_bool y !! 1006 bool "Include FDT for Mobileye EyeQ5 development platforms"
355 depends on BUG !! 1007 depends on MACH_EYEQ5
>> 1008 default n
>> 1009 help
>> 1010 Enable this to include the FDT for the EyeQ5 development platforms
>> 1011 from Mobileye in the FIT kernel image.
>> 1012 This requires u-boot on the platform.
>> 1013
>> 1014 source "arch/mips/alchemy/Kconfig"
>> 1015 source "arch/mips/ath25/Kconfig"
>> 1016 source "arch/mips/ath79/Kconfig"
>> 1017 source "arch/mips/bcm47xx/Kconfig"
>> 1018 source "arch/mips/bcm63xx/Kconfig"
>> 1019 source "arch/mips/bmips/Kconfig"
>> 1020 source "arch/mips/generic/Kconfig"
>> 1021 source "arch/mips/ingenic/Kconfig"
>> 1022 source "arch/mips/jazz/Kconfig"
>> 1023 source "arch/mips/lantiq/Kconfig"
>> 1024 source "arch/mips/pic32/Kconfig"
>> 1025 source "arch/mips/ralink/Kconfig"
>> 1026 source "arch/mips/sgi-ip27/Kconfig"
>> 1027 source "arch/mips/sibyte/Kconfig"
>> 1028 source "arch/mips/txx9/Kconfig"
>> 1029 source "arch/mips/cavium-octeon/Kconfig"
>> 1030 source "arch/mips/loongson2ef/Kconfig"
>> 1031 source "arch/mips/loongson32/Kconfig"
>> 1032 source "arch/mips/loongson64/Kconfig"
356 1033
357 config GENERIC_BUG_RELATIVE_POINTERS !! 1034 endmenu
358 def_bool y <<
359 depends on GENERIC_BUG <<
360 1035
361 config GENERIC_HWEIGHT 1036 config GENERIC_HWEIGHT
362 def_bool y !! 1037 bool
363 !! 1038 default y
364 config GENERIC_CSUM <<
365 def_bool y <<
366 1039
367 config GENERIC_CALIBRATE_DELAY 1040 config GENERIC_CALIBRATE_DELAY
368 def_bool y !! 1041 bool
>> 1042 default y
369 1043
370 config SMP !! 1044 config SCHED_OMIT_FRAME_POINTER
371 def_bool y !! 1045 bool
>> 1046 default y
372 1047
373 config KERNEL_MODE_NEON !! 1048 #
374 def_bool y !! 1049 # Select some configuration options automatically based on user selections.
>> 1050 #
>> 1051 config FW_ARC
>> 1052 bool
375 1053
376 config FIX_EARLYCON_MEM !! 1054 config ARCH_MAY_HAVE_PC_FDC
377 def_bool y !! 1055 bool
378 1056
379 config PGTABLE_LEVELS !! 1057 config BOOT_RAW
380 int !! 1058 bool
381 default 2 if ARM64_16K_PAGES && ARM64_ <<
382 default 2 if ARM64_64K_PAGES && ARM64_ <<
383 default 3 if ARM64_64K_PAGES && (ARM64 <<
384 default 3 if ARM64_4K_PAGES && ARM64_V <<
385 default 3 if ARM64_16K_PAGES && ARM64_ <<
386 default 4 if ARM64_16K_PAGES && (ARM64 <<
387 default 4 if !ARM64_64K_PAGES && ARM64 <<
388 default 5 if ARM64_4K_PAGES && ARM64_V <<
389 1059
390 config ARCH_SUPPORTS_UPROBES !! 1060 config CEVT_BCM1480
391 def_bool y !! 1061 bool
392 1062
393 config ARCH_PROC_KCORE_TEXT !! 1063 config CEVT_DS1287
394 def_bool y !! 1064 bool
395 1065
396 config BROKEN_GAS_INST !! 1066 config CEVT_GT641XX
397 def_bool !$(as-instr,1:\n.inst 0\n.rep !! 1067 bool
398 1068
399 config BUILTIN_RETURN_ADDRESS_STRIPS_PAC !! 1069 config CEVT_R4K
400 bool 1070 bool
401 # Clang's __builtin_return_address() s <<
402 # https://github.com/llvm/llvm-project <<
403 default y if CC_IS_CLANG <<
404 # GCC's __builtin_return_address() str <<
405 # and this was backported to 10.2.0, 9 <<
406 # https://gcc.gnu.org/bugzilla/show_bu <<
407 default y if CC_IS_GCC && (GCC_VERSION <<
408 default y if CC_IS_GCC && (GCC_VERSION <<
409 default y if CC_IS_GCC && (GCC_VERSION <<
410 default y if CC_IS_GCC && (GCC_VERSION <<
411 default n <<
412 1071
413 config KASAN_SHADOW_OFFSET !! 1072 config CEVT_SB1250
414 hex <<
415 depends on KASAN_GENERIC || KASAN_SW_T <<
416 default 0xdfff800000000000 if (ARM64_V <<
417 default 0xdfffc00000000000 if (ARM64_V <<
418 default 0xdffffe0000000000 if ARM64_VA <<
419 default 0xdfffffc000000000 if ARM64_VA <<
420 default 0xdffffff800000000 if ARM64_VA <<
421 default 0xefff800000000000 if (ARM64_V <<
422 default 0xefffc00000000000 if (ARM64_V <<
423 default 0xeffffe0000000000 if ARM64_VA <<
424 default 0xefffffc000000000 if ARM64_VA <<
425 default 0xeffffff800000000 if ARM64_VA <<
426 default 0xffffffffffffffff <<
427 <<
428 config UNWIND_TABLES <<
429 bool 1073 bool
430 1074
431 source "arch/arm64/Kconfig.platforms" !! 1075 config CEVT_TXX9
>> 1076 bool
432 1077
433 menu "Kernel Features" !! 1078 config CSRC_BCM1480
>> 1079 bool
434 1080
435 menu "ARM errata workarounds via the alternati !! 1081 config CSRC_IOASIC
>> 1082 bool
436 1083
437 config AMPERE_ERRATUM_AC03_CPU_38 !! 1084 config CSRC_R4K
438 bool "AmpereOne: AC03_CPU_38: Certain !! 1085 select CLOCKSOURCE_WATCHDOG if CPU_FREQ
439 default y !! 1086 bool
440 help <<
441 This option adds an alternative code <<
442 errata AC03_CPU_38 and AC04_CPU_10 o <<
443 1087
444 The affected design reports FEAT_HAF !! 1088 config CSRC_SB1250
445 ID_AA64MMFR1_EL1.HAFDBS, but (V)TCR_ !! 1089 bool
446 as required by the architecture. The <<
447 implementation suffers from an addit <<
448 A/D updates can occur after a PTE ha <<
449 <<
450 The workaround forces KVM to explici <<
451 which avoids enabling unadvertised h <<
452 at stage-2. <<
453 1090
454 If unsure, say Y. !! 1091 config MIPS_CLOCK_VSYSCALL
>> 1092 def_bool CSRC_R4K || CLKSRC_MIPS_GIC
455 1093
456 config ARM64_WORKAROUND_CLEAN_CACHE !! 1094 config GPIO_TXX9
>> 1095 select GPIOLIB
457 bool 1096 bool
458 1097
459 config ARM64_ERRATUM_826319 !! 1098 config FW_CFE
460 bool "Cortex-A53: 826319: System might !! 1099 bool
461 default y <<
462 select ARM64_WORKAROUND_CLEAN_CACHE <<
463 help <<
464 This option adds an alternative code <<
465 erratum 826319 on Cortex-A53 parts u <<
466 AXI master interface and an L2 cache <<
467 <<
468 If a Cortex-A53 uses an AMBA AXI4 AC <<
469 and is unable to accept a certain wr <<
470 not progress on read data presented <<
471 system can deadlock. <<
472 <<
473 The workaround promotes data cache c <<
474 data cache clean-and-invalidate. <<
475 Please note that this does not neces <<
476 as it depends on the alternative fra <<
477 the kernel if an affected CPU is det <<
478 <<
479 If unsure, say Y. <<
480 1100
481 config ARM64_ERRATUM_827319 !! 1101 config ARCH_SUPPORTS_UPROBES
482 bool "Cortex-A53: 827319: Data cache c !! 1102 def_bool y
483 default y <<
484 select ARM64_WORKAROUND_CLEAN_CACHE <<
485 help <<
486 This option adds an alternative code <<
487 erratum 827319 on Cortex-A53 parts u <<
488 master interface and an L2 cache. <<
489 <<
490 Under certain conditions this erratu <<
491 to occur at the same time as another <<
492 on the AMBA 5 CHI interface, which c <<
493 interconnect reorders the two transa <<
494 <<
495 The workaround promotes data cache c <<
496 data cache clean-and-invalidate. <<
497 Please note that this does not neces <<
498 as it depends on the alternative fra <<
499 the kernel if an affected CPU is det <<
500 1103
501 If unsure, say Y. !! 1104 config DMA_NONCOHERENT
>> 1105 bool
>> 1106 #
>> 1107 # MIPS allows mixing "slightly different" Cacheability and Coherency
>> 1108 # Attribute bits. It is believed that the uncached access through
>> 1109 # KSEG1 and the implementation specific "uncached accelerated" used
>> 1110 # by pgprot_writcombine can be mixed, and the latter sometimes provides
>> 1111 # significant advantages.
>> 1112 #
>> 1113 select ARCH_HAS_SETUP_DMA_OPS
>> 1114 select ARCH_HAS_DMA_WRITE_COMBINE
>> 1115 select ARCH_HAS_DMA_PREP_COHERENT
>> 1116 select ARCH_HAS_SYNC_DMA_FOR_CPU
>> 1117 select ARCH_HAS_SYNC_DMA_FOR_DEVICE
>> 1118 select ARCH_HAS_DMA_SET_UNCACHED
>> 1119 select DMA_NONCOHERENT_MMAP
>> 1120 select NEED_DMA_MAP_STATE
502 1121
503 config ARM64_ERRATUM_824069 !! 1122 config SYS_HAS_EARLY_PRINTK
504 bool "Cortex-A53: 824069: Cache line m !! 1123 bool
505 default y <<
506 select ARM64_WORKAROUND_CLEAN_CACHE <<
507 help <<
508 This option adds an alternative code <<
509 erratum 824069 on Cortex-A53 parts u <<
510 to a coherent interconnect. <<
511 <<
512 If a Cortex-A53 processor is executi <<
513 write instruction at the same time a <<
514 cluster is executing a cache mainten <<
515 address, then this erratum might cau <<
516 incorrectly marked as dirty. <<
517 <<
518 The workaround promotes data cache c <<
519 data cache clean-and-invalidate. <<
520 Please note that this option does no <<
521 workaround, as it depends on the alt <<
522 only patch the kernel if an affected <<
523 1124
524 If unsure, say Y. !! 1125 config SYS_SUPPORTS_HOTPLUG_CPU
>> 1126 bool
525 1127
526 config ARM64_ERRATUM_819472 !! 1128 config MIPS_BONITO64
527 bool "Cortex-A53: 819472: Store exclus !! 1129 bool
528 default y <<
529 select ARM64_WORKAROUND_CLEAN_CACHE <<
530 help <<
531 This option adds an alternative code <<
532 erratum 819472 on Cortex-A53 parts u <<
533 present when it is connected to a co <<
534 <<
535 If the processor is executing a load <<
536 the same time as a processor in anot <<
537 maintenance operation to the same ad <<
538 cause data corruption. <<
539 <<
540 The workaround promotes data cache c <<
541 data cache clean-and-invalidate. <<
542 Please note that this does not neces <<
543 as it depends on the alternative fra <<
544 the kernel if an affected CPU is det <<
545 1130
546 If unsure, say Y. !! 1131 config MIPS_MSC
>> 1132 bool
547 1133
548 config ARM64_ERRATUM_832075 !! 1134 config SYNC_R4K
549 bool "Cortex-A57: 832075: possible dea !! 1135 bool
550 default y <<
551 help <<
552 This option adds an alternative code <<
553 erratum 832075 on Cortex-A57 parts u <<
554 1136
555 Affected Cortex-A57 parts might dead !! 1137 config NO_IOPORT_MAP
556 instructions to Write-Back memory ar !! 1138 def_bool n
557 1139
558 The workaround is to promote device !! 1140 config GENERIC_CSUM
559 semantics. !! 1141 def_bool CPU_NO_LOAD_STORE_LR
560 Please note that this does not neces <<
561 as it depends on the alternative fra <<
562 the kernel if an affected CPU is det <<
563 1142
564 If unsure, say Y. !! 1143 config GENERIC_ISA_DMA
>> 1144 bool
>> 1145 select ZONE_DMA if GENERIC_ISA_DMA_SUPPORT_BROKEN=n
>> 1146 select ISA_DMA_API
565 1147
566 config ARM64_ERRATUM_834220 !! 1148 config GENERIC_ISA_DMA_SUPPORT_BROKEN
567 bool "Cortex-A57: 834220: Stage 2 tran !! 1149 bool
568 depends on KVM !! 1150 select GENERIC_ISA_DMA
569 help <<
570 This option adds an alternative code <<
571 erratum 834220 on Cortex-A57 parts u <<
572 <<
573 Affected Cortex-A57 parts might repo <<
574 fault as the result of a Stage 1 fau <<
575 page boundary when there is a permis <<
576 alignment fault at Stage 1 and a tra <<
577 <<
578 The workaround is to verify that the <<
579 doesn't generate a fault before hand <<
580 Please note that this does not neces <<
581 as it depends on the alternative fra <<
582 the kernel if an affected CPU is det <<
583 1151
584 If unsure, say N. !! 1152 config HAVE_PLAT_DELAY
>> 1153 bool
585 1154
586 config ARM64_ERRATUM_1742098 !! 1155 config HAVE_PLAT_FW_INIT_CMDLINE
587 bool "Cortex-A57/A72: 1742098: ELR rec !! 1156 bool
588 depends on COMPAT <<
589 default y <<
590 help <<
591 This option removes the AES hwcap fo <<
592 workaround erratum 1742098 on Cortex <<
593 1157
594 Affected parts may corrupt the AES s !! 1158 config HAVE_PLAT_MEMCPY
595 taken between a pair of AES instruct !! 1159 bool
596 are only present if the cryptography <<
597 All software should have a fallback <<
598 that don't implement the cryptograph <<
599 1160
600 If unsure, say Y. !! 1161 config ISA_DMA_API
>> 1162 bool
601 1163
602 config ARM64_ERRATUM_845719 !! 1164 config SYS_SUPPORTS_RELOCATABLE
603 bool "Cortex-A53: 845719: a load might !! 1165 bool
604 depends on COMPAT <<
605 default y <<
606 help 1166 help
607 This option adds an alternative code !! 1167 Selected if the platform supports relocating the kernel.
608 erratum 845719 on Cortex-A53 parts u !! 1168 The platform must provide plat_get_fdt() if it selects CONFIG_USE_OF
609 !! 1169 to allow access to command line and entropy sources.
610 When running a compat (AArch32) user <<
611 part, a load at EL0 from a virtual a <<
612 bits of the virtual address used by <<
613 might return incorrect data. <<
614 <<
615 The workaround is to write the conte <<
616 return to a 32-bit task. <<
617 Please note that this does not neces <<
618 as it depends on the alternative fra <<
619 the kernel if an affected CPU is det <<
620 1170
621 If unsure, say Y. !! 1171 #
622 !! 1172 # Endianness selection. Sufficiently obscure so many users don't know what to
623 config ARM64_ERRATUM_843419 !! 1173 # answer,so we try hard to limit the available choices. Also the use of a
624 bool "Cortex-A53: 843419: A load or st !! 1174 # choice statement should be more obvious to the user.
625 default y !! 1175 #
>> 1176 choice
>> 1177 prompt "Endianness selection"
626 help 1178 help
627 This option links the kernel with '- !! 1179 Some MIPS machines can be configured for either little or big endian
628 enables PLT support to replace certa !! 1180 byte order. These modes require different kernels and a different
629 cause subsequent memory accesses to !! 1181 Linux distribution. In general there is one preferred byteorder for a
630 Cortex-A53 parts up to r0p4. !! 1182 particular system but some systems are just as commonly used in the
>> 1183 one or the other endianness.
631 1184
632 If unsure, say Y. !! 1185 config CPU_BIG_ENDIAN
>> 1186 bool "Big endian"
>> 1187 depends on SYS_SUPPORTS_BIG_ENDIAN
633 1188
634 config ARM64_LD_HAS_FIX_ERRATUM_843419 !! 1189 config CPU_LITTLE_ENDIAN
635 def_bool $(ld-option,--fix-cortex-a53- !! 1190 bool "Little endian"
>> 1191 depends on SYS_SUPPORTS_LITTLE_ENDIAN
636 1192
637 config ARM64_ERRATUM_1024718 !! 1193 endchoice
638 bool "Cortex-A55: 1024718: Update of D <<
639 default y <<
640 help <<
641 This option adds a workaround for AR <<
642 1194
643 Affected Cortex-A55 cores (all revis !! 1195 config EXPORT_UASM
644 update of the hardware dirty bit whe !! 1196 bool
645 without a break-before-make. The wor <<
646 of hardware DBM locally on the affec <<
647 this erratum will continue to use th <<
648 1197
649 If unsure, say Y. !! 1198 config SYS_SUPPORTS_APM_EMULATION
>> 1199 bool
650 1200
651 config ARM64_ERRATUM_1418040 !! 1201 config SYS_SUPPORTS_BIG_ENDIAN
652 bool "Cortex-A76/Neoverse-N1: MRC read !! 1202 bool
653 default y <<
654 depends on COMPAT <<
655 help <<
656 This option adds a workaround for AR <<
657 errata 1188873 and 1418040. <<
658 1203
659 Affected Cortex-A76/Neoverse-N1 core !! 1204 config SYS_SUPPORTS_LITTLE_ENDIAN
660 cause register corruption when acces !! 1205 bool
661 from AArch32 userspace. <<
662 1206
663 If unsure, say Y. !! 1207 config MIPS_HUGE_TLB_SUPPORT
>> 1208 def_bool HUGETLB_PAGE || TRANSPARENT_HUGEPAGE
664 1209
665 config ARM64_WORKAROUND_SPECULATIVE_AT !! 1210 config IRQ_TXX9
666 bool 1211 bool
667 1212
668 config ARM64_ERRATUM_1165522 !! 1213 config IRQ_GT641XX
669 bool "Cortex-A76: 1165522: Speculative !! 1214 bool
670 default y <<
671 select ARM64_WORKAROUND_SPECULATIVE_AT <<
672 help <<
673 This option adds a workaround for AR <<
674 1215
675 Affected Cortex-A76 cores (r0p0, r1p !! 1216 config PCI_GT64XXX_PCI0
676 corrupted TLBs by speculating an AT !! 1217 bool
677 context switch. <<
678 1218
679 If unsure, say Y. !! 1219 config PCI_XTALK_BRIDGE
>> 1220 bool
680 1221
681 config ARM64_ERRATUM_1319367 !! 1222 config NO_EXCEPT_FILL
682 bool "Cortex-A57/A72: 1319537: Specula !! 1223 bool
683 default y <<
684 select ARM64_WORKAROUND_SPECULATIVE_AT <<
685 help <<
686 This option adds work arounds for AR <<
687 and A72 erratum 1319367 <<
688 1224
689 Cortex-A57 and A72 cores could end-u !! 1225 config MIPS_SPRAM
690 speculating an AT instruction during !! 1226 bool
691 1227
692 If unsure, say Y. !! 1228 config SWAP_IO_SPACE
>> 1229 bool
693 1230
694 config ARM64_ERRATUM_1530923 !! 1231 config SGI_HAS_INDYDOG
695 bool "Cortex-A55: 1530923: Speculative !! 1232 bool
696 default y <<
697 select ARM64_WORKAROUND_SPECULATIVE_AT <<
698 help <<
699 This option adds a workaround for AR <<
700 1233
701 Affected Cortex-A55 cores (r0p0, r0p !! 1234 config SGI_HAS_HAL2
702 corrupted TLBs by speculating an AT !! 1235 bool
703 context switch. <<
704 1236
705 If unsure, say Y. !! 1237 config SGI_HAS_SEEQ
>> 1238 bool
706 1239
707 config ARM64_WORKAROUND_REPEAT_TLBI !! 1240 config SGI_HAS_WD93
708 bool 1241 bool
709 1242
710 config ARM64_ERRATUM_2441007 !! 1243 config SGI_HAS_ZILOG
711 bool "Cortex-A55: Completion of affect !! 1244 bool
712 select ARM64_WORKAROUND_REPEAT_TLBI <<
713 help <<
714 This option adds a workaround for AR <<
715 1245
716 Under very rare circumstances, affec !! 1246 config SGI_HAS_I8042
717 may not handle a race between a brea !! 1247 bool
718 CPU, and another CPU accessing the s <<
719 store to a page that has been unmapp <<
720 1248
721 Work around this by adding the affec !! 1249 config DEFAULT_SGI_PARTITION
722 TLB sequences to be done twice. !! 1250 bool
723 1251
724 If unsure, say N. !! 1252 config FW_ARC32
>> 1253 bool
725 1254
726 config ARM64_ERRATUM_1286807 !! 1255 config FW_SNIPROM
727 bool "Cortex-A76: Modification of the !! 1256 bool
728 select ARM64_WORKAROUND_REPEAT_TLBI <<
729 help <<
730 This option adds a workaround for AR <<
731 <<
732 On the affected Cortex-A76 cores (r0 <<
733 address for a cacheable mapping of a <<
734 accessed by a core while another cor <<
735 address to a new physical page using <<
736 break-before-make sequence, then und <<
737 TLBI+DSB completes before a read usi <<
738 invalidated has been observed by oth <<
739 workaround repeats the TLBI+DSB oper <<
740 1257
741 If unsure, say N. !! 1258 config BOOT_ELF32
>> 1259 bool
742 1260
743 config ARM64_ERRATUM_1463225 !! 1261 config MIPS_L1_CACHE_SHIFT_4
744 bool "Cortex-A76: Software Step might !! 1262 bool
745 default y <<
746 help <<
747 This option adds a workaround for Ar <<
748 1263
749 On the affected Cortex-A76 cores (r0 !! 1264 config MIPS_L1_CACHE_SHIFT_5
750 of a system call instruction (SVC) c !! 1265 bool
751 subsequent interrupts when software <<
752 exception handler of the system call <<
753 is enabled or VHE is in use. <<
754 <<
755 Work around the erratum by triggerin <<
756 when handling a system call from a t <<
757 in a VHE configuration of the kernel <<
758 1266
759 If unsure, say Y. !! 1267 config MIPS_L1_CACHE_SHIFT_6
>> 1268 bool
760 1269
761 config ARM64_ERRATUM_1542419 !! 1270 config MIPS_L1_CACHE_SHIFT_7
762 bool "Neoverse-N1: workaround mis-orde !! 1271 bool
763 help <<
764 This option adds a workaround for AR <<
765 1542419. <<
766 1272
767 Affected Neoverse-N1 cores could exe !! 1273 config MIPS_L1_CACHE_SHIFT
768 modified by another CPU. The workaro !! 1274 int
769 counterpart. !! 1275 default "7" if MIPS_L1_CACHE_SHIFT_7
>> 1276 default "6" if MIPS_L1_CACHE_SHIFT_6
>> 1277 default "5" if MIPS_L1_CACHE_SHIFT_5
>> 1278 default "4" if MIPS_L1_CACHE_SHIFT_4
>> 1279 default "5"
770 1280
771 Workaround the issue by hiding the D !! 1281 config ARC_CMDLINE_ONLY
772 forces user-space to perform cache m !! 1282 bool
773 1283
774 If unsure, say N. !! 1284 config ARC_CONSOLE
>> 1285 bool "ARC console support"
>> 1286 depends on SGI_IP22 || SGI_IP28 || (SNI_RM && CPU_LITTLE_ENDIAN)
775 1287
776 config ARM64_ERRATUM_1508412 !! 1288 config ARC_MEMORY
777 bool "Cortex-A77: 1508412: workaround !! 1289 bool
778 default y <<
779 help <<
780 This option adds a workaround for Ar <<
781 1290
782 Affected Cortex-A77 cores (r0p0, r1p !! 1291 config ARC_PROMLIB
783 of a store-exclusive or read of PAR_ !! 1292 bool
784 non-cacheable memory attributes. The <<
785 counterpart. <<
786 <<
787 KVM guests must also have the workar <<
788 deadlock the system. <<
789 <<
790 Work around the issue by inserting D <<
791 register reads and warning KVM users <<
792 to prevent a speculative PAR_EL1 rea <<
793 1293
794 If unsure, say Y. !! 1294 config FW_ARC64
>> 1295 bool
795 1296
796 config ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MO !! 1297 config BOOT_ELF64
797 bool 1298 bool
798 1299
799 config ARM64_ERRATUM_2051678 !! 1300 menu "CPU selection"
800 bool "Cortex-A510: 2051678: disable Ha <<
801 default y <<
802 help <<
803 This options adds the workaround for <<
804 Affected Cortex-A510 might not respe <<
805 hardware update of the page table's <<
806 is to not enable the feature on affe <<
807 1301
808 If unsure, say Y. !! 1302 choice
>> 1303 prompt "CPU type"
>> 1304 default CPU_R4X00
809 1305
810 config ARM64_ERRATUM_2077057 !! 1306 config CPU_LOONGSON64
811 bool "Cortex-A510: 2077057: workaround !! 1307 bool "Loongson 64-bit CPU"
812 default y !! 1308 depends on SYS_HAS_CPU_LOONGSON64
>> 1309 select ARCH_HAS_PHYS_TO_DMA
>> 1310 select CPU_MIPSR2
>> 1311 select CPU_HAS_PREFETCH
>> 1312 select CPU_SUPPORTS_64BIT_KERNEL
>> 1313 select CPU_SUPPORTS_HIGHMEM
>> 1314 select CPU_SUPPORTS_HUGEPAGES
>> 1315 select CPU_SUPPORTS_MSA
>> 1316 select CPU_SUPPORTS_VZ
>> 1317 select CPU_DIEI_BROKEN if !LOONGSON3_ENHANCEMENT
>> 1318 select CPU_MIPSR2_IRQ_VI
>> 1319 select DMA_NONCOHERENT
>> 1320 select WEAK_ORDERING
>> 1321 select WEAK_REORDERING_BEYOND_LLSC
>> 1322 select MIPS_ASID_BITS_VARIABLE
>> 1323 select MIPS_PGD_C0_CONTEXT
>> 1324 select MIPS_L1_CACHE_SHIFT_6
>> 1325 select MIPS_FP_SUPPORT
>> 1326 select GPIOLIB
>> 1327 select SWIOTLB
813 help 1328 help
814 This option adds the workaround for !! 1329 The Loongson GSx64(GS264/GS464/GS464E/GS464V) series of processor
815 Affected Cortex-A510 may corrupt SPS !! 1330 cores implements the MIPS64R2 instruction set with many extensions,
816 expected, but a Pointer Authenticati !! 1331 including most 64-bit Loongson-2 (2H, 2K) and Loongson-3 (3A1000,
817 erratum causes SPSR_EL1 to be copied !! 1332 3B1000, 3B1500, 3A2000, 3A3000 and 3A4000) processors. However, old
818 EL1 to cause a return to EL2 with a !! 1333 Loongson-2E/2F is not covered here and will be removed in future.
819 !! 1334
820 This can only happen when EL2 is ste !! 1335 config CPU_LOONGSON2E
821 !! 1336 bool "Loongson 2E"
822 When these conditions occur, the SPS !! 1337 depends on SYS_HAS_CPU_LOONGSON2E
823 previous guest entry, and can be res !! 1338 select CPU_LOONGSON2EF
824 !! 1339 help
825 If unsure, say Y. !! 1340 The Loongson 2E processor implements the MIPS III instruction set
826 !! 1341 with many extensions.
827 config ARM64_ERRATUM_2658417 !! 1342
828 bool "Cortex-A510: 2658417: remove BF1 !! 1343 It has an internal FPGA northbridge, which is compatible to
829 default y !! 1344 bonito64.
>> 1345
>> 1346 config CPU_LOONGSON2F
>> 1347 bool "Loongson 2F"
>> 1348 depends on SYS_HAS_CPU_LOONGSON2F
>> 1349 select CPU_LOONGSON2EF
>> 1350 help
>> 1351 The Loongson 2F processor implements the MIPS III instruction set
>> 1352 with many extensions.
>> 1353
>> 1354 Loongson2F have built-in DDR2 and PCIX controller. The PCIX controller
>> 1355 have a similar programming interface with FPGA northbridge used in
>> 1356 Loongson2E.
>> 1357
>> 1358 config CPU_LOONGSON1B
>> 1359 bool "Loongson 1B"
>> 1360 depends on SYS_HAS_CPU_LOONGSON1B
>> 1361 select CPU_LOONGSON32
>> 1362 select LEDS_GPIO_REGISTER
>> 1363 help
>> 1364 The Loongson 1B is a 32-bit SoC, which implements the MIPS32
>> 1365 Release 1 instruction set and part of the MIPS32 Release 2
>> 1366 instruction set.
>> 1367
>> 1368 config CPU_LOONGSON1C
>> 1369 bool "Loongson 1C"
>> 1370 depends on SYS_HAS_CPU_LOONGSON1C
>> 1371 select CPU_LOONGSON32
>> 1372 select LEDS_GPIO_REGISTER
>> 1373 help
>> 1374 The Loongson 1C is a 32-bit SoC, which implements the MIPS32
>> 1375 Release 1 instruction set and part of the MIPS32 Release 2
>> 1376 instruction set.
>> 1377
>> 1378 config CPU_MIPS32_R1
>> 1379 bool "MIPS32 Release 1"
>> 1380 depends on SYS_HAS_CPU_MIPS32_R1
>> 1381 select CPU_HAS_PREFETCH
>> 1382 select CPU_SUPPORTS_32BIT_KERNEL
>> 1383 select CPU_SUPPORTS_HIGHMEM
>> 1384 help
>> 1385 Choose this option to build a kernel for release 1 or later of the
>> 1386 MIPS32 architecture. Most modern embedded systems with a 32-bit
>> 1387 MIPS processor are based on a MIPS32 processor. If you know the
>> 1388 specific type of processor in your system, choose those that one
>> 1389 otherwise CPU_MIPS32_R1 is a safe bet for any MIPS32 system.
>> 1390 Release 2 of the MIPS32 architecture is available since several
>> 1391 years so chances are you even have a MIPS32 Release 2 processor
>> 1392 in which case you should choose CPU_MIPS32_R2 instead for better
>> 1393 performance.
>> 1394
>> 1395 config CPU_MIPS32_R2
>> 1396 bool "MIPS32 Release 2"
>> 1397 depends on SYS_HAS_CPU_MIPS32_R2
>> 1398 select CPU_HAS_PREFETCH
>> 1399 select CPU_SUPPORTS_32BIT_KERNEL
>> 1400 select CPU_SUPPORTS_HIGHMEM
>> 1401 select CPU_SUPPORTS_MSA
>> 1402 help
>> 1403 Choose this option to build a kernel for release 2 or later of the
>> 1404 MIPS32 architecture. Most modern embedded systems with a 32-bit
>> 1405 MIPS processor are based on a MIPS32 processor. If you know the
>> 1406 specific type of processor in your system, choose those that one
>> 1407 otherwise CPU_MIPS32_R1 is a safe bet for any MIPS32 system.
>> 1408
>> 1409 config CPU_MIPS32_R5
>> 1410 bool "MIPS32 Release 5"
>> 1411 depends on SYS_HAS_CPU_MIPS32_R5
>> 1412 select CPU_HAS_PREFETCH
>> 1413 select CPU_SUPPORTS_32BIT_KERNEL
>> 1414 select CPU_SUPPORTS_HIGHMEM
>> 1415 select CPU_SUPPORTS_MSA
>> 1416 select CPU_SUPPORTS_VZ
>> 1417 select MIPS_O32_FP64_SUPPORT
>> 1418 help
>> 1419 Choose this option to build a kernel for release 5 or later of the
>> 1420 MIPS32 architecture. New MIPS processors, starting with the Warrior
>> 1421 family, are based on a MIPS32r5 processor. If you own an older
>> 1422 processor, you probably need to select MIPS32r1 or MIPS32r2 instead.
>> 1423
>> 1424 config CPU_MIPS32_R6
>> 1425 bool "MIPS32 Release 6"
>> 1426 depends on SYS_HAS_CPU_MIPS32_R6
>> 1427 select CPU_HAS_PREFETCH
>> 1428 select CPU_NO_LOAD_STORE_LR
>> 1429 select CPU_SUPPORTS_32BIT_KERNEL
>> 1430 select CPU_SUPPORTS_HIGHMEM
>> 1431 select CPU_SUPPORTS_MSA
>> 1432 select CPU_SUPPORTS_VZ
>> 1433 select MIPS_O32_FP64_SUPPORT
>> 1434 help
>> 1435 Choose this option to build a kernel for release 6 or later of the
>> 1436 MIPS32 architecture. New MIPS processors, starting with the Warrior
>> 1437 family, are based on a MIPS32r6 processor. If you own an older
>> 1438 processor, you probably need to select MIPS32r1 or MIPS32r2 instead.
>> 1439
>> 1440 config CPU_MIPS64_R1
>> 1441 bool "MIPS64 Release 1"
>> 1442 depends on SYS_HAS_CPU_MIPS64_R1
>> 1443 select CPU_HAS_PREFETCH
>> 1444 select CPU_SUPPORTS_32BIT_KERNEL
>> 1445 select CPU_SUPPORTS_64BIT_KERNEL
>> 1446 select CPU_SUPPORTS_HIGHMEM
>> 1447 select CPU_SUPPORTS_HUGEPAGES
>> 1448 help
>> 1449 Choose this option to build a kernel for release 1 or later of the
>> 1450 MIPS64 architecture. Many modern embedded systems with a 64-bit
>> 1451 MIPS processor are based on a MIPS64 processor. If you know the
>> 1452 specific type of processor in your system, choose those that one
>> 1453 otherwise CPU_MIPS64_R1 is a safe bet for any MIPS64 system.
>> 1454 Release 2 of the MIPS64 architecture is available since several
>> 1455 years so chances are you even have a MIPS64 Release 2 processor
>> 1456 in which case you should choose CPU_MIPS64_R2 instead for better
>> 1457 performance.
>> 1458
>> 1459 config CPU_MIPS64_R2
>> 1460 bool "MIPS64 Release 2"
>> 1461 depends on SYS_HAS_CPU_MIPS64_R2
>> 1462 select CPU_HAS_PREFETCH
>> 1463 select CPU_SUPPORTS_32BIT_KERNEL
>> 1464 select CPU_SUPPORTS_64BIT_KERNEL
>> 1465 select CPU_SUPPORTS_HIGHMEM
>> 1466 select CPU_SUPPORTS_HUGEPAGES
>> 1467 select CPU_SUPPORTS_MSA
>> 1468 help
>> 1469 Choose this option to build a kernel for release 2 or later of the
>> 1470 MIPS64 architecture. Many modern embedded systems with a 64-bit
>> 1471 MIPS processor are based on a MIPS64 processor. If you know the
>> 1472 specific type of processor in your system, choose those that one
>> 1473 otherwise CPU_MIPS64_R1 is a safe bet for any MIPS64 system.
>> 1474
>> 1475 config CPU_MIPS64_R5
>> 1476 bool "MIPS64 Release 5"
>> 1477 depends on SYS_HAS_CPU_MIPS64_R5
>> 1478 select CPU_HAS_PREFETCH
>> 1479 select CPU_SUPPORTS_32BIT_KERNEL
>> 1480 select CPU_SUPPORTS_64BIT_KERNEL
>> 1481 select CPU_SUPPORTS_HIGHMEM
>> 1482 select CPU_SUPPORTS_HUGEPAGES
>> 1483 select CPU_SUPPORTS_MSA
>> 1484 select MIPS_O32_FP64_SUPPORT if 32BIT || MIPS32_O32
>> 1485 select CPU_SUPPORTS_VZ
>> 1486 help
>> 1487 Choose this option to build a kernel for release 5 or later of the
>> 1488 MIPS64 architecture. This is a intermediate MIPS architecture
>> 1489 release partly implementing release 6 features. Though there is no
>> 1490 any hardware known to be based on this release.
>> 1491
>> 1492 config CPU_MIPS64_R6
>> 1493 bool "MIPS64 Release 6"
>> 1494 depends on SYS_HAS_CPU_MIPS64_R6
>> 1495 select CPU_HAS_PREFETCH
>> 1496 select CPU_NO_LOAD_STORE_LR
>> 1497 select CPU_SUPPORTS_32BIT_KERNEL
>> 1498 select CPU_SUPPORTS_64BIT_KERNEL
>> 1499 select CPU_SUPPORTS_HIGHMEM
>> 1500 select CPU_SUPPORTS_HUGEPAGES
>> 1501 select CPU_SUPPORTS_MSA
>> 1502 select MIPS_O32_FP64_SUPPORT if 32BIT || MIPS32_O32
>> 1503 select CPU_SUPPORTS_VZ
>> 1504 help
>> 1505 Choose this option to build a kernel for release 6 or later of the
>> 1506 MIPS64 architecture. New MIPS processors, starting with the Warrior
>> 1507 family, are based on a MIPS64r6 processor. If you own an older
>> 1508 processor, you probably need to select MIPS64r1 or MIPS64r2 instead.
>> 1509
>> 1510 config CPU_P5600
>> 1511 bool "MIPS Warrior P5600"
>> 1512 depends on SYS_HAS_CPU_P5600
>> 1513 select CPU_HAS_PREFETCH
>> 1514 select CPU_SUPPORTS_32BIT_KERNEL
>> 1515 select CPU_SUPPORTS_HIGHMEM
>> 1516 select CPU_SUPPORTS_MSA
>> 1517 select CPU_SUPPORTS_CPUFREQ
>> 1518 select CPU_SUPPORTS_VZ
>> 1519 select CPU_MIPSR2_IRQ_VI
>> 1520 select CPU_MIPSR2_IRQ_EI
>> 1521 select MIPS_O32_FP64_SUPPORT
>> 1522 help
>> 1523 Choose this option to build a kernel for MIPS Warrior P5600 CPU.
>> 1524 It's based on MIPS32r5 ISA with XPA, EVA, dual/quad issue exec pipes,
>> 1525 MMU with two-levels TLB, UCA, MSA, MDU core level features and system
>> 1526 level features like up to six P5600 calculation cores, CM2 with L2
>> 1527 cache, IOCU/IOMMU (though might be unused depending on the system-
>> 1528 specific IP core configuration), GIC, CPC, virtualisation module,
>> 1529 eJTAG and PDtrace.
>> 1530
>> 1531 config CPU_R3000
>> 1532 bool "R3000"
>> 1533 depends on SYS_HAS_CPU_R3000
>> 1534 select CPU_HAS_WB
>> 1535 select CPU_R3K_TLB
>> 1536 select CPU_SUPPORTS_32BIT_KERNEL
>> 1537 select CPU_SUPPORTS_HIGHMEM
>> 1538 help
>> 1539 Please make sure to pick the right CPU type. Linux/MIPS is not
>> 1540 designed to be generic, i.e. Kernels compiled for R3000 CPUs will
>> 1541 *not* work on R4000 machines and vice versa. However, since most
>> 1542 of the supported machines have an R4000 (or similar) CPU, R4x00
>> 1543 might be a safe bet. If the resulting kernel does not work,
>> 1544 try to recompile with R3000.
>> 1545
>> 1546 config CPU_R4300
>> 1547 bool "R4300"
>> 1548 depends on SYS_HAS_CPU_R4300
>> 1549 select CPU_SUPPORTS_32BIT_KERNEL
>> 1550 select CPU_SUPPORTS_64BIT_KERNEL
>> 1551 help
>> 1552 MIPS Technologies R4300-series processors.
>> 1553
>> 1554 config CPU_R4X00
>> 1555 bool "R4x00"
>> 1556 depends on SYS_HAS_CPU_R4X00
>> 1557 select CPU_SUPPORTS_32BIT_KERNEL
>> 1558 select CPU_SUPPORTS_64BIT_KERNEL
>> 1559 select CPU_SUPPORTS_HUGEPAGES
>> 1560 help
>> 1561 MIPS Technologies R4000-series processors other than 4300, including
>> 1562 the R4000, R4400, R4600, and 4700.
>> 1563
>> 1564 config CPU_TX49XX
>> 1565 bool "R49XX"
>> 1566 depends on SYS_HAS_CPU_TX49XX
>> 1567 select CPU_HAS_PREFETCH
>> 1568 select CPU_SUPPORTS_32BIT_KERNEL
>> 1569 select CPU_SUPPORTS_64BIT_KERNEL
>> 1570 select CPU_SUPPORTS_HUGEPAGES
>> 1571
>> 1572 config CPU_R5000
>> 1573 bool "R5000"
>> 1574 depends on SYS_HAS_CPU_R5000
>> 1575 select CPU_SUPPORTS_32BIT_KERNEL
>> 1576 select CPU_SUPPORTS_64BIT_KERNEL
>> 1577 select CPU_SUPPORTS_HUGEPAGES
>> 1578 help
>> 1579 MIPS Technologies R5000-series processors other than the Nevada.
>> 1580
>> 1581 config CPU_R5500
>> 1582 bool "R5500"
>> 1583 depends on SYS_HAS_CPU_R5500
>> 1584 select CPU_SUPPORTS_32BIT_KERNEL
>> 1585 select CPU_SUPPORTS_64BIT_KERNEL
>> 1586 select CPU_SUPPORTS_HUGEPAGES
>> 1587 help
>> 1588 NEC VR5500 and VR5500A series processors implement 64-bit MIPS IV
>> 1589 instruction set.
>> 1590
>> 1591 config CPU_NEVADA
>> 1592 bool "RM52xx"
>> 1593 depends on SYS_HAS_CPU_NEVADA
>> 1594 select CPU_SUPPORTS_32BIT_KERNEL
>> 1595 select CPU_SUPPORTS_64BIT_KERNEL
>> 1596 select CPU_SUPPORTS_HUGEPAGES
>> 1597 help
>> 1598 QED / PMC-Sierra RM52xx-series ("Nevada") processors.
>> 1599
>> 1600 config CPU_R10000
>> 1601 bool "R10000"
>> 1602 depends on SYS_HAS_CPU_R10000
>> 1603 select CPU_HAS_PREFETCH
>> 1604 select CPU_SUPPORTS_32BIT_KERNEL
>> 1605 select CPU_SUPPORTS_64BIT_KERNEL
>> 1606 select CPU_SUPPORTS_HIGHMEM
>> 1607 select CPU_SUPPORTS_HUGEPAGES
>> 1608 help
>> 1609 MIPS Technologies R10000-series processors.
>> 1610
>> 1611 config CPU_RM7000
>> 1612 bool "RM7000"
>> 1613 depends on SYS_HAS_CPU_RM7000
>> 1614 select CPU_HAS_PREFETCH
>> 1615 select CPU_SUPPORTS_32BIT_KERNEL
>> 1616 select CPU_SUPPORTS_64BIT_KERNEL
>> 1617 select CPU_SUPPORTS_HIGHMEM
>> 1618 select CPU_SUPPORTS_HUGEPAGES
>> 1619
>> 1620 config CPU_SB1
>> 1621 bool "SB1"
>> 1622 depends on SYS_HAS_CPU_SB1
>> 1623 select CPU_SUPPORTS_32BIT_KERNEL
>> 1624 select CPU_SUPPORTS_64BIT_KERNEL
>> 1625 select CPU_SUPPORTS_HIGHMEM
>> 1626 select CPU_SUPPORTS_HUGEPAGES
>> 1627 select WEAK_ORDERING
>> 1628
>> 1629 config CPU_CAVIUM_OCTEON
>> 1630 bool "Cavium Octeon processor"
>> 1631 depends on SYS_HAS_CPU_CAVIUM_OCTEON
>> 1632 select CPU_HAS_PREFETCH
>> 1633 select CPU_SUPPORTS_64BIT_KERNEL
>> 1634 select HAVE_PAGE_SIZE_8KB if !MIPS_VA_BITS_48
>> 1635 select HAVE_PAGE_SIZE_32KB if !MIPS_VA_BITS_48
>> 1636 select WEAK_ORDERING
>> 1637 select CPU_SUPPORTS_HIGHMEM
>> 1638 select CPU_SUPPORTS_HUGEPAGES
>> 1639 select USB_EHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 1640 select USB_OHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 1641 select MIPS_L1_CACHE_SHIFT_7
>> 1642 select CPU_SUPPORTS_VZ
>> 1643 help
>> 1644 The Cavium Octeon processor is a highly integrated chip containing
>> 1645 many ethernet hardware widgets for networking tasks. The processor
>> 1646 can have up to 16 Mips64v2 cores and 8 integrated gigabit ethernets.
>> 1647 Full details can be found at http://www.caviumnetworks.com.
>> 1648
>> 1649 config CPU_BMIPS
>> 1650 bool "Broadcom BMIPS"
>> 1651 depends on SYS_HAS_CPU_BMIPS
>> 1652 select CPU_MIPS32
>> 1653 select CPU_BMIPS32_3300 if SYS_HAS_CPU_BMIPS32_3300
>> 1654 select CPU_BMIPS4350 if SYS_HAS_CPU_BMIPS4350
>> 1655 select CPU_BMIPS4380 if SYS_HAS_CPU_BMIPS4380
>> 1656 select CPU_BMIPS5000 if SYS_HAS_CPU_BMIPS5000
>> 1657 select CPU_SUPPORTS_32BIT_KERNEL
>> 1658 select DMA_NONCOHERENT
>> 1659 select IRQ_MIPS_CPU
>> 1660 select SWAP_IO_SPACE
>> 1661 select WEAK_ORDERING
>> 1662 select CPU_SUPPORTS_HIGHMEM
>> 1663 select CPU_HAS_PREFETCH
>> 1664 select CPU_SUPPORTS_CPUFREQ
>> 1665 select MIPS_EXTERNAL_TIMER
>> 1666 select GENERIC_IRQ_MIGRATION if HOTPLUG_CPU
830 help 1667 help
831 This option adds the workaround for !! 1668 Support for BMIPS32/3300/4350/4380 and BMIPS5000 processors.
832 Affected Cortex-A510 (r0p0 to r1p1) <<
833 BFMMLA or VMMLA instructions in rare <<
834 A510 CPUs are using shared neon hard <<
835 discoverable by the kernel, hide the <<
836 user-space should not be using these <<
837 1669
838 If unsure, say Y. !! 1670 endchoice
839 1671
840 config ARM64_ERRATUM_2119858 !! 1672 config LOONGSON3_ENHANCEMENT
841 bool "Cortex-A710/X2: 2119858: workaro !! 1673 bool "New Loongson-3 CPU Enhancements"
842 default y !! 1674 default n
843 depends on CORESIGHT_TRBE !! 1675 depends on CPU_LOONGSON64
844 select ARM64_WORKAROUND_TRBE_OVERWRITE <<
845 help 1676 help
846 This option adds the workaround for !! 1677 New Loongson-3 cores (since Loongson-3A R2, as opposed to Loongson-3A
>> 1678 R1, Loongson-3B R1 and Loongson-3B R2) has many enhancements, such as
>> 1679 FTLB, L1-VCache, EI/DI/Wait/Prefetch instruction, DSP/DSPr2 ASE, User
>> 1680 Local register, Read-Inhibit/Execute-Inhibit, SFB (Store Fill Buffer),
>> 1681 Fast TLB refill support, etc.
>> 1682
>> 1683 This option enable those enhancements which are not probed at run
>> 1684 time. If you want a generic kernel to run on all Loongson 3 machines,
>> 1685 please say 'N' here. If you want a high-performance kernel to run on
>> 1686 new Loongson-3 machines only, please say 'Y' here.
>> 1687
>> 1688 config CPU_LOONGSON3_WORKAROUNDS
>> 1689 bool "Loongson-3 LLSC Workarounds"
>> 1690 default y if SMP
>> 1691 depends on CPU_LOONGSON64
>> 1692 help
>> 1693 Loongson-3 processors have the llsc issues which require workarounds.
>> 1694 Without workarounds the system may hang unexpectedly.
>> 1695
>> 1696 Say Y, unless you know what you are doing.
>> 1697
>> 1698 config CPU_LOONGSON3_CPUCFG_EMULATION
>> 1699 bool "Emulate the CPUCFG instruction on older Loongson cores"
>> 1700 default y
>> 1701 depends on CPU_LOONGSON64
>> 1702 help
>> 1703 Loongson-3A R4 and newer have the CPUCFG instruction available for
>> 1704 userland to query CPU capabilities, much like CPUID on x86. This
>> 1705 option provides emulation of the instruction on older Loongson
>> 1706 cores, back to Loongson-3A1000.
>> 1707
>> 1708 If unsure, please say Y.
>> 1709
>> 1710 config CPU_MIPS32_3_5_FEATURES
>> 1711 bool "MIPS32 Release 3.5 Features"
>> 1712 depends on SYS_HAS_CPU_MIPS32_R3_5
>> 1713 depends on CPU_MIPS32_R2 || CPU_MIPS32_R5 || CPU_MIPS32_R6 || \
>> 1714 CPU_P5600
>> 1715 help
>> 1716 Choose this option to build a kernel for release 2 or later of the
>> 1717 MIPS32 architecture including features from the 3.5 release such as
>> 1718 support for Enhanced Virtual Addressing (EVA).
>> 1719
>> 1720 config CPU_MIPS32_3_5_EVA
>> 1721 bool "Enhanced Virtual Addressing (EVA)"
>> 1722 depends on CPU_MIPS32_3_5_FEATURES
>> 1723 select EVA
>> 1724 default y
>> 1725 help
>> 1726 Choose this option if you want to enable the Enhanced Virtual
>> 1727 Addressing (EVA) on your MIPS32 core (such as proAptiv).
>> 1728 One of its primary benefits is an increase in the maximum size
>> 1729 of lowmem (up to 3GB). If unsure, say 'N' here.
>> 1730
>> 1731 config CPU_MIPS32_R5_FEATURES
>> 1732 bool "MIPS32 Release 5 Features"
>> 1733 depends on SYS_HAS_CPU_MIPS32_R5
>> 1734 depends on CPU_MIPS32_R2 || CPU_MIPS32_R5 || CPU_P5600
>> 1735 help
>> 1736 Choose this option to build a kernel for release 2 or later of the
>> 1737 MIPS32 architecture including features from release 5 such as
>> 1738 support for Extended Physical Addressing (XPA).
>> 1739
>> 1740 config CPU_MIPS32_R5_XPA
>> 1741 bool "Extended Physical Addressing (XPA)"
>> 1742 depends on CPU_MIPS32_R5_FEATURES
>> 1743 depends on !EVA
>> 1744 depends on !PAGE_SIZE_4KB
>> 1745 depends on SYS_SUPPORTS_HIGHMEM
>> 1746 select XPA
>> 1747 select HIGHMEM
>> 1748 select PHYS_ADDR_T_64BIT
>> 1749 default n
>> 1750 help
>> 1751 Choose this option if you want to enable the Extended Physical
>> 1752 Addressing (XPA) on your MIPS32 core (such as P5600 series). The
>> 1753 benefit is to increase physical addressing equal to or greater
>> 1754 than 40 bits. Note that this has the side effect of turning on
>> 1755 64-bit addressing which in turn makes the PTEs 64-bit in size.
>> 1756 If unsure, say 'N' here.
847 1757
848 Affected Cortex-A710/X2 cores could !! 1758 if CPU_LOONGSON2F
849 data at the base of the buffer (poin !! 1759 config CPU_NOP_WORKAROUNDS
850 the event of a WRAP event. !! 1760 bool
851 <<
852 Work around the issue by always maki <<
853 256 bytes before enabling the buffer <<
854 the buffer with ETM ignore packets u <<
855 1761
856 If unsure, say Y. !! 1762 config CPU_JUMP_WORKAROUNDS
>> 1763 bool
857 1764
858 config ARM64_ERRATUM_2139208 !! 1765 config CPU_LOONGSON2F_WORKAROUNDS
859 bool "Neoverse-N2: 2139208: workaround !! 1766 bool "Loongson 2F Workarounds"
860 default y 1767 default y
861 depends on CORESIGHT_TRBE !! 1768 select CPU_NOP_WORKAROUNDS
862 select ARM64_WORKAROUND_TRBE_OVERWRITE !! 1769 select CPU_JUMP_WORKAROUNDS
863 help 1770 help
864 This option adds the workaround for !! 1771 Loongson 2F01 / 2F02 processors have the NOP & JUMP issues which
>> 1772 require workarounds. Without workarounds the system may hang
>> 1773 unexpectedly. For more information please refer to the gas
>> 1774 -mfix-loongson2f-nop and -mfix-loongson2f-jump options.
>> 1775
>> 1776 Loongson 2F03 and later have fixed these issues and no workarounds
>> 1777 are needed. The workarounds have no significant side effect on them
>> 1778 but may decrease the performance of the system so this option should
>> 1779 be disabled unless the kernel is intended to be run on 2F01 or 2F02
>> 1780 systems.
865 1781
866 Affected Neoverse-N2 cores could ove !! 1782 If unsure, please say Y.
867 data at the base of the buffer (poin !! 1783 endif # CPU_LOONGSON2F
868 the event of a WRAP event. <<
869 <<
870 Work around the issue by always maki <<
871 256 bytes before enabling the buffer <<
872 the buffer with ETM ignore packets u <<
873 1784
874 If unsure, say Y. !! 1785 config SYS_SUPPORTS_ZBOOT
875 <<
876 config ARM64_WORKAROUND_TSB_FLUSH_FAILURE <<
877 bool 1786 bool
>> 1787 select HAVE_KERNEL_GZIP
>> 1788 select HAVE_KERNEL_BZIP2
>> 1789 select HAVE_KERNEL_LZ4
>> 1790 select HAVE_KERNEL_LZMA
>> 1791 select HAVE_KERNEL_LZO
>> 1792 select HAVE_KERNEL_XZ
>> 1793 select HAVE_KERNEL_ZSTD
878 1794
879 config ARM64_ERRATUM_2054223 !! 1795 config SYS_SUPPORTS_ZBOOT_UART16550
880 bool "Cortex-A710: 2054223: workaround !! 1796 bool
881 default y !! 1797 select SYS_SUPPORTS_ZBOOT
882 select ARM64_WORKAROUND_TSB_FLUSH_FAIL <<
883 help <<
884 Enable workaround for ARM Cortex-A71 <<
885 1798
886 Affected cores may fail to flush the !! 1799 config SYS_SUPPORTS_ZBOOT_UART_PROM
887 the PE is in trace prohibited state. !! 1800 bool
888 of the trace cached. !! 1801 select SYS_SUPPORTS_ZBOOT
889 1802
890 Workaround is to issue two TSB conse !! 1803 config CPU_LOONGSON2EF
>> 1804 bool
>> 1805 select CPU_SUPPORTS_32BIT_KERNEL
>> 1806 select CPU_SUPPORTS_64BIT_KERNEL
>> 1807 select CPU_SUPPORTS_HIGHMEM
>> 1808 select CPU_SUPPORTS_HUGEPAGES
891 1809
892 If unsure, say Y. !! 1810 config CPU_LOONGSON32
>> 1811 bool
>> 1812 select CPU_MIPS32
>> 1813 select CPU_MIPSR2
>> 1814 select CPU_HAS_PREFETCH
>> 1815 select CPU_SUPPORTS_32BIT_KERNEL
>> 1816 select CPU_SUPPORTS_HIGHMEM
>> 1817 select CPU_SUPPORTS_CPUFREQ
893 1818
894 config ARM64_ERRATUM_2067961 !! 1819 config CPU_BMIPS32_3300
895 bool "Neoverse-N2: 2067961: workaround !! 1820 select SMP_UP if SMP
896 default y !! 1821 bool
897 select ARM64_WORKAROUND_TSB_FLUSH_FAIL <<
898 help <<
899 Enable workaround for ARM Neoverse-N <<
900 1822
901 Affected cores may fail to flush the !! 1823 config CPU_BMIPS4350
902 the PE is in trace prohibited state. !! 1824 bool
903 of the trace cached. !! 1825 select SYS_SUPPORTS_SMP
>> 1826 select SYS_SUPPORTS_HOTPLUG_CPU
904 1827
905 Workaround is to issue two TSB conse !! 1828 config CPU_BMIPS4380
>> 1829 bool
>> 1830 select MIPS_L1_CACHE_SHIFT_6
>> 1831 select SYS_SUPPORTS_SMP
>> 1832 select SYS_SUPPORTS_HOTPLUG_CPU
>> 1833 select CPU_HAS_RIXI
906 1834
907 If unsure, say Y. !! 1835 config CPU_BMIPS5000
>> 1836 bool
>> 1837 select MIPS_CPU_SCACHE
>> 1838 select MIPS_L1_CACHE_SHIFT_7
>> 1839 select SYS_SUPPORTS_SMP
>> 1840 select SYS_SUPPORTS_HOTPLUG_CPU
>> 1841 select CPU_HAS_RIXI
908 1842
909 config ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANG !! 1843 config SYS_HAS_CPU_LOONGSON64
910 bool 1844 bool
>> 1845 select CPU_SUPPORTS_CPUFREQ
>> 1846 select CPU_HAS_RIXI
911 1847
912 config ARM64_ERRATUM_2253138 !! 1848 config SYS_HAS_CPU_LOONGSON2E
913 bool "Neoverse-N2: 2253138: workaround !! 1849 bool
914 depends on CORESIGHT_TRBE <<
915 default y <<
916 select ARM64_WORKAROUND_TRBE_WRITE_OUT <<
917 help <<
918 This option adds the workaround for <<
919 1850
920 Affected Neoverse-N2 cores might wri !! 1851 config SYS_HAS_CPU_LOONGSON2F
921 for TRBE. Under some conditions, the !! 1852 bool
922 virtually addressed page following t !! 1853 select CPU_SUPPORTS_CPUFREQ
923 (i.e., the TRBLIMITR_EL1.LIMIT), ins !! 1854 select CPU_SUPPORTS_ADDRWINCFG if 64BIT
924 1855
925 Work around this in the driver by al !! 1856 config SYS_HAS_CPU_LOONGSON1B
926 page beyond the TRBLIMITR_EL1.LIMIT, !! 1857 bool
927 1858
928 If unsure, say Y. !! 1859 config SYS_HAS_CPU_LOONGSON1C
>> 1860 bool
929 1861
930 config ARM64_ERRATUM_2224489 !! 1862 config SYS_HAS_CPU_MIPS32_R1
931 bool "Cortex-A710/X2: 2224489: workaro !! 1863 bool
932 depends on CORESIGHT_TRBE <<
933 default y <<
934 select ARM64_WORKAROUND_TRBE_WRITE_OUT <<
935 help <<
936 This option adds the workaround for <<
937 1864
938 Affected Cortex-A710/X2 cores might !! 1865 config SYS_HAS_CPU_MIPS32_R2
939 for TRBE. Under some conditions, the !! 1866 bool
940 virtually addressed page following t <<
941 (i.e., the TRBLIMITR_EL1.LIMIT), ins <<
942 1867
943 Work around this in the driver by al !! 1868 config SYS_HAS_CPU_MIPS32_R3_5
944 page beyond the TRBLIMITR_EL1.LIMIT, !! 1869 bool
945 1870
946 If unsure, say Y. !! 1871 config SYS_HAS_CPU_MIPS32_R5
>> 1872 bool
947 1873
948 config ARM64_ERRATUM_2441009 !! 1874 config SYS_HAS_CPU_MIPS32_R6
949 bool "Cortex-A510: Completion of affec !! 1875 bool
950 select ARM64_WORKAROUND_REPEAT_TLBI <<
951 help <<
952 This option adds a workaround for AR <<
953 <<
954 Under very rare circumstances, affec <<
955 may not handle a race between a brea <<
956 CPU, and another CPU accessing the s <<
957 store to a page that has been unmapp <<
958 1876
959 Work around this by adding the affec !! 1877 config SYS_HAS_CPU_MIPS64_R1
960 TLB sequences to be done twice. !! 1878 bool
961 1879
962 If unsure, say N. !! 1880 config SYS_HAS_CPU_MIPS64_R2
>> 1881 bool
963 1882
964 config ARM64_ERRATUM_2064142 !! 1883 config SYS_HAS_CPU_MIPS64_R5
965 bool "Cortex-A510: 2064142: workaround !! 1884 bool
966 depends on CORESIGHT_TRBE <<
967 default y <<
968 help <<
969 This option adds the workaround for <<
970 1885
971 Affected Cortex-A510 core might fail !! 1886 config SYS_HAS_CPU_MIPS64_R6
972 TRBE has been disabled. Under some c !! 1887 bool
973 writes into TRBE registers TRBLIMITR <<
974 and TRBTRG_EL1 will be ignored and w <<
975 <<
976 Work around this in the driver by ex <<
977 is stopped and before performing a s <<
978 registers. <<
979 1888
980 If unsure, say Y. !! 1889 config SYS_HAS_CPU_P5600
>> 1890 bool
981 1891
982 config ARM64_ERRATUM_2038923 !! 1892 config SYS_HAS_CPU_R3000
983 bool "Cortex-A510: 2038923: workaround !! 1893 bool
984 depends on CORESIGHT_TRBE <<
985 default y <<
986 help <<
987 This option adds the workaround for <<
988 1894
989 Affected Cortex-A510 core might caus !! 1895 config SYS_HAS_CPU_R4300
990 prohibited within the CPU. As a resu !! 1896 bool
991 might be corrupted. This happens aft <<
992 TRBLIMITR_EL1.E, followed by just a <<
993 execution changes from a context, in <<
994 isn't, or vice versa. In these menti <<
995 is prohibited is inconsistent betwee <<
996 the trace buffer state might be corr <<
997 <<
998 Work around this in the driver by pr <<
999 trace is prohibited or not based on <<
1000 change to TRBLIMITR_EL1.E with at l <<
1001 two ISB instructions if no ERET is <<
1002 1897
1003 If unsure, say Y. !! 1898 config SYS_HAS_CPU_R4X00
>> 1899 bool
1004 1900
1005 config ARM64_ERRATUM_1902691 !! 1901 config SYS_HAS_CPU_TX49XX
1006 bool "Cortex-A510: 1902691: workaroun !! 1902 bool
1007 depends on CORESIGHT_TRBE <<
1008 default y <<
1009 help <<
1010 This option adds the workaround for <<
1011 1903
1012 Affected Cortex-A510 core might cau !! 1904 config SYS_HAS_CPU_R5000
1013 into the memory. Effectively TRBE i !! 1905 bool
1014 trace data. <<
1015 <<
1016 Work around this problem in the dri <<
1017 affected cpus. The firmware must ha <<
1018 on such implementations. This will <<
1019 do this already. <<
1020 1906
1021 If unsure, say Y. !! 1907 config SYS_HAS_CPU_R5500
>> 1908 bool
1022 1909
1023 config ARM64_ERRATUM_2457168 !! 1910 config SYS_HAS_CPU_NEVADA
1024 bool "Cortex-A510: 2457168: workaroun !! 1911 bool
1025 depends on ARM64_AMU_EXTN <<
1026 default y <<
1027 help <<
1028 This option adds the workaround for <<
1029 1912
1030 The AMU counter AMEVCNTR01 (constan !! 1913 config SYS_HAS_CPU_R10000
1031 as the system counter. On affected !! 1914 bool
1032 incorrectly giving a significantly <<
1033 <<
1034 Work around this problem by returni <<
1035 key locations that results in disab <<
1036 is the same to firmware disabling a <<
1037 1915
1038 If unsure, say Y. !! 1916 config SYS_HAS_CPU_RM7000
>> 1917 bool
1039 1918
1040 config ARM64_ERRATUM_2645198 !! 1919 config SYS_HAS_CPU_SB1
1041 bool "Cortex-A715: 2645198: Workaroun !! 1920 bool
1042 default y <<
1043 help <<
1044 This option adds the workaround for <<
1045 1921
1046 If a Cortex-A715 cpu sees a page ma !! 1922 config SYS_HAS_CPU_CAVIUM_OCTEON
1047 to non-executable, it may corrupt t !! 1923 bool
1048 next instruction abort caused by pe <<
1049 <<
1050 Only user-space does executable to <<
1051 mprotect() system call. Workaround <<
1052 TLB invalidation, for all changes t <<
1053 1924
1054 If unsure, say Y. !! 1925 config SYS_HAS_CPU_BMIPS
>> 1926 bool
1055 1927
1056 config ARM64_WORKAROUND_SPECULATIVE_UNPRIV_LO !! 1928 config SYS_HAS_CPU_BMIPS32_3300
1057 bool 1929 bool
>> 1930 select SYS_HAS_CPU_BMIPS
1058 1931
1059 config ARM64_ERRATUM_2966298 !! 1932 config SYS_HAS_CPU_BMIPS4350
1060 bool "Cortex-A520: 2966298: workaroun !! 1933 bool
1061 select ARM64_WORKAROUND_SPECULATIVE_U !! 1934 select SYS_HAS_CPU_BMIPS
1062 default y <<
1063 help <<
1064 This option adds the workaround for <<
1065 1935
1066 On an affected Cortex-A520 core, a !! 1936 config SYS_HAS_CPU_BMIPS4380
1067 load might leak data from a privile !! 1937 bool
>> 1938 select SYS_HAS_CPU_BMIPS
1068 1939
1069 Work around this problem by executi !! 1940 config SYS_HAS_CPU_BMIPS5000
>> 1941 bool
>> 1942 select SYS_HAS_CPU_BMIPS
1070 1943
1071 If unsure, say Y. !! 1944 #
>> 1945 # CPU may reorder R->R, R->W, W->R, W->W
>> 1946 # Reordering beyond LL and SC is handled in WEAK_REORDERING_BEYOND_LLSC
>> 1947 #
>> 1948 config WEAK_ORDERING
>> 1949 bool
1072 1950
1073 config ARM64_ERRATUM_3117295 !! 1951 #
1074 bool "Cortex-A510: 3117295: workaroun !! 1952 # CPU may reorder reads and writes beyond LL/SC
1075 select ARM64_WORKAROUND_SPECULATIVE_U !! 1953 # CPU may reorder R->LL, R->LL, W->LL, W->LL, R->SC, R->SC, W->SC, W->SC
1076 default y !! 1954 #
1077 help !! 1955 config WEAK_REORDERING_BEYOND_LLSC
1078 This option adds the workaround for !! 1956 bool
>> 1957 endmenu
1079 1958
1080 On an affected Cortex-A510 core, a !! 1959 #
1081 load might leak data from a privile !! 1960 # These two indicate any level of the MIPS32 and MIPS64 architecture
>> 1961 #
>> 1962 config CPU_MIPS32
>> 1963 bool
>> 1964 default y if CPU_MIPS32_R1 || CPU_MIPS32_R2 || CPU_MIPS32_R5 || \
>> 1965 CPU_MIPS32_R6 || CPU_P5600
1082 1966
1083 Work around this problem by executi !! 1967 config CPU_MIPS64
>> 1968 bool
>> 1969 default y if CPU_MIPS64_R1 || CPU_MIPS64_R2 || CPU_MIPS64_R5 || \
>> 1970 CPU_MIPS64_R6 || CPU_LOONGSON64 || CPU_CAVIUM_OCTEON
1084 1971
1085 If unsure, say Y. !! 1972 #
>> 1973 # These indicate the revision of the architecture
>> 1974 #
>> 1975 config CPU_MIPSR1
>> 1976 bool
>> 1977 default y if CPU_MIPS32_R1 || CPU_MIPS64_R1
1086 1978
1087 config ARM64_ERRATUM_3194386 !! 1979 config CPU_MIPSR2
1088 bool "Cortex-*/Neoverse-*: workaround !! 1980 bool
1089 default y !! 1981 default y if CPU_MIPS32_R2 || CPU_MIPS64_R2 || CPU_CAVIUM_OCTEON
1090 help !! 1982 select CPU_HAS_RIXI
1091 This option adds the workaround for !! 1983 select CPU_HAS_DIEI if !CPU_DIEI_BROKEN
>> 1984 select MIPS_SPRAM
1092 1985
1093 * ARM Cortex-A76 erratum 3324349 !! 1986 config CPU_MIPSR5
1094 * ARM Cortex-A77 erratum 3324348 !! 1987 bool
1095 * ARM Cortex-A78 erratum 3324344 !! 1988 default y if CPU_MIPS32_R5 || CPU_MIPS64_R5 || CPU_P5600
1096 * ARM Cortex-A78C erratum 3324346 !! 1989 select CPU_HAS_RIXI
1097 * ARM Cortex-A78C erratum 3324347 !! 1990 select CPU_HAS_DIEI if !CPU_DIEI_BROKEN
1098 * ARM Cortex-A710 erratam 3324338 !! 1991 select MIPS_SPRAM
1099 * ARM Cortex-A715 errartum 3456084 <<
1100 * ARM Cortex-A720 erratum 3456091 <<
1101 * ARM Cortex-A725 erratum 3456106 <<
1102 * ARM Cortex-X1 erratum 3324344 <<
1103 * ARM Cortex-X1C erratum 3324346 <<
1104 * ARM Cortex-X2 erratum 3324338 <<
1105 * ARM Cortex-X3 erratum 3324335 <<
1106 * ARM Cortex-X4 erratum 3194386 <<
1107 * ARM Cortex-X925 erratum 3324334 <<
1108 * ARM Neoverse-N1 erratum 3324349 <<
1109 * ARM Neoverse N2 erratum 3324339 <<
1110 * ARM Neoverse-N3 erratum 3456111 <<
1111 * ARM Neoverse-V1 erratum 3324341 <<
1112 * ARM Neoverse V2 erratum 3324336 <<
1113 * ARM Neoverse-V3 erratum 3312417 <<
1114 <<
1115 On affected cores "MSR SSBS, #0" in <<
1116 subsequent speculative instructions <<
1117 speculative store bypassing. <<
1118 <<
1119 Work around this problem by placing <<
1120 Instruction Synchronization Barrier <<
1121 SSBS. The presence of the SSBS spec <<
1122 from hwcaps and EL0 reads of ID_AA6 <<
1123 will use the PR_SPEC_STORE_BYPASS p <<
1124 1992
1125 If unsure, say Y. !! 1993 config CPU_MIPSR6
>> 1994 bool
>> 1995 default y if CPU_MIPS32_R6 || CPU_MIPS64_R6
>> 1996 select CPU_HAS_RIXI
>> 1997 select CPU_HAS_DIEI if !CPU_DIEI_BROKEN
>> 1998 select HAVE_ARCH_BITREVERSE
>> 1999 select MIPS_ASID_BITS_VARIABLE
>> 2000 select MIPS_CRC_SUPPORT
>> 2001 select MIPS_SPRAM
1126 2002
1127 config CAVIUM_ERRATUM_22375 !! 2003 config TARGET_ISA_REV
1128 bool "Cavium erratum 22375, 24313" !! 2004 int
1129 default y !! 2005 default 1 if CPU_MIPSR1
>> 2006 default 2 if CPU_MIPSR2
>> 2007 default 5 if CPU_MIPSR5
>> 2008 default 6 if CPU_MIPSR6
>> 2009 default 0
1130 help 2010 help
1131 Enable workaround for errata 22375 !! 2011 Reflects the ISA revision being targeted by the kernel build. This
>> 2012 is effectively the Kconfig equivalent of MIPS_ISA_REV.
1132 2013
1133 This implements two gicv3-its errat !! 2014 config EVA
1134 with a small impact affecting only !! 2015 bool
1135 2016
1136 erratum 22375: only alloc 8MB tab !! 2017 config XPA
1137 erratum 24313: ignore memory acce !! 2018 bool
1138 2019
1139 The fixes are in ITS initialization !! 2020 config SYS_SUPPORTS_32BIT_KERNEL
1140 type and table size provided by the !! 2021 bool
>> 2022 config SYS_SUPPORTS_64BIT_KERNEL
>> 2023 bool
>> 2024 config CPU_SUPPORTS_32BIT_KERNEL
>> 2025 bool
>> 2026 config CPU_SUPPORTS_64BIT_KERNEL
>> 2027 bool
>> 2028 config CPU_SUPPORTS_CPUFREQ
>> 2029 bool
>> 2030 config CPU_SUPPORTS_ADDRWINCFG
>> 2031 bool
>> 2032 config CPU_SUPPORTS_HUGEPAGES
>> 2033 bool
>> 2034 depends on !(32BIT && (PHYS_ADDR_T_64BIT || EVA))
>> 2035 config CPU_SUPPORTS_VZ
>> 2036 bool
>> 2037 config MIPS_PGD_C0_CONTEXT
>> 2038 bool
>> 2039 depends on 64BIT
>> 2040 default y if (CPU_MIPSR2 || CPU_MIPSR6)
1141 2041
1142 If unsure, say Y. !! 2042 #
>> 2043 # Set to y for ptrace access to watch registers.
>> 2044 #
>> 2045 config HARDWARE_WATCHPOINTS
>> 2046 bool
>> 2047 default y if CPU_MIPSR1 || CPU_MIPSR2 || CPU_MIPSR6
1143 2048
1144 config CAVIUM_ERRATUM_23144 !! 2049 menu "Kernel type"
1145 bool "Cavium erratum 23144: ITS SYNC <<
1146 depends on NUMA <<
1147 default y <<
1148 help <<
1149 ITS SYNC command hang for cross nod <<
1150 2050
1151 If unsure, say Y. !! 2051 choice
>> 2052 prompt "Kernel code model"
>> 2053 help
>> 2054 You should only select this option if you have a workload that
>> 2055 actually benefits from 64-bit processing or if your machine has
>> 2056 large memory. You will only be presented a single option in this
>> 2057 menu if your system does not support both 32-bit and 64-bit kernels.
>> 2058
>> 2059 config 32BIT
>> 2060 bool "32-bit kernel"
>> 2061 depends on CPU_SUPPORTS_32BIT_KERNEL && SYS_SUPPORTS_32BIT_KERNEL
>> 2062 select TRAD_SIGNALS
>> 2063 help
>> 2064 Select this option if you want to build a 32-bit kernel.
1152 2065
1153 config CAVIUM_ERRATUM_23154 !! 2066 config 64BIT
1154 bool "Cavium errata 23154 and 38545: !! 2067 bool "64-bit kernel"
1155 default y !! 2068 depends on CPU_SUPPORTS_64BIT_KERNEL && SYS_SUPPORTS_64BIT_KERNEL
1156 help 2069 help
1157 The ThunderX GICv3 implementation r !! 2070 Select this option if you want to build a 64-bit kernel.
1158 reading the IAR status to ensure da <<
1159 (access to icc_iar1_el1 is not sync <<
1160 <<
1161 It also suffers from erratum 38545 <<
1162 OcteonTX and OcteonTX2), resulting <<
1163 spuriously presented to the CPU int <<
1164 2071
1165 If unsure, say Y. !! 2072 endchoice
1166 2073
1167 config CAVIUM_ERRATUM_27456 !! 2074 config MIPS_VA_BITS_48
1168 bool "Cavium erratum 27456: Broadcast !! 2075 bool "48 bits virtual memory"
1169 default y !! 2076 depends on 64BIT
1170 help !! 2077 help
1171 On ThunderX T88 pass 1.x through 2. !! 2078 Support a maximum at least 48 bits of application virtual
1172 instructions may cause the icache t !! 2079 memory. Default is 40 bits or less, depending on the CPU.
1173 contains data for a non-current ASI !! 2080 For page sizes 16k and above, this option results in a small
1174 invalidate the icache when changing !! 2081 memory overhead for page tables. For 4k page size, a fourth
>> 2082 level of page tables is added which imposes both a memory
>> 2083 overhead as well as slower TLB fault handling.
1175 2084
1176 If unsure, say Y. !! 2085 If unsure, say N.
1177 2086
1178 config CAVIUM_ERRATUM_30115 !! 2087 config ZBOOT_LOAD_ADDRESS
1179 bool "Cavium erratum 30115: Guest may !! 2088 hex "Compressed kernel load address"
1180 default y !! 2089 default 0xffffffff80400000 if BCM47XX
>> 2090 default 0x0
>> 2091 depends on SYS_SUPPORTS_ZBOOT
1181 help 2092 help
1182 On ThunderX T88 pass 1.x through 2. !! 2093 The address to load compressed kernel, aka vmlinuz.
1183 1.2, and T83 Pass 1.0, KVM guest ex <<
1184 interrupts in host. Trapping both G <<
1185 accesses sidesteps the issue. <<
1186 2094
1187 If unsure, say Y. !! 2095 This is only used if non-zero.
1188 2096
1189 config CAVIUM_TX2_ERRATUM_219 !! 2097 config ARCH_FORCE_MAX_ORDER
1190 bool "Cavium ThunderX2 erratum 219: P !! 2098 int "Maximum zone order"
1191 default y !! 2099 default "13" if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_64KB
>> 2100 default "12" if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_32KB
>> 2101 default "11" if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_16KB
>> 2102 default "10"
1192 help 2103 help
1193 On Cavium ThunderX2, a load, store !! 2104 The kernel memory allocator divides physically contiguous memory
1194 TTBR update and the corresponding c !! 2105 blocks into "zones", where each zone is a power of two number of
1195 cause a spurious Data Abort to be d !! 2106 pages. This option selects the largest power of two that the kernel
1196 the CPU core. !! 2107 keeps in the memory allocator. If you need to allocate very large
1197 !! 2108 blocks of physically contiguous memory, then you may need to
1198 Work around the issue by avoiding t !! 2109 increase this value.
1199 trapping KVM guest TTBRx_EL1 writes <<
1200 trap handler performs the correspon <<
1201 instruction and ensures context syn <<
1202 exception return. <<
1203 2110
1204 If unsure, say Y. !! 2111 The page size is not necessarily 4KB. Keep this in mind
>> 2112 when choosing a value for this option.
1205 2113
1206 config FUJITSU_ERRATUM_010001 !! 2114 config BOARD_SCACHE
1207 bool "Fujitsu-A64FX erratum E#010001: !! 2115 bool
1208 default y <<
1209 help <<
1210 This option adds a workaround for F <<
1211 On some variants of the Fujitsu-A64 <<
1212 accesses may cause undefined fault <<
1213 This fault occurs under a specific <<
1214 load/store instruction performs an <<
1215 case-1 TTBR0_EL1 with TCR_EL1.NFD0 <<
1216 case-2 TTBR0_EL2 with TCR_EL2.NFD0 <<
1217 case-3 TTBR1_EL1 with TCR_EL1.NFD1 <<
1218 case-4 TTBR1_EL2 with TCR_EL2.NFD1 <<
1219 2116
1220 The workaround is to ensure these b !! 2117 config IP22_CPU_SCACHE
1221 The workaround only affects the Fuj !! 2118 bool
>> 2119 select BOARD_SCACHE
1222 2120
1223 If unsure, say Y. !! 2121 #
>> 2122 # Support for a MIPS32 / MIPS64 style S-caches
>> 2123 #
>> 2124 config MIPS_CPU_SCACHE
>> 2125 bool
>> 2126 select BOARD_SCACHE
1224 2127
1225 config HISILICON_ERRATUM_161600802 !! 2128 config R5000_CPU_SCACHE
1226 bool "Hip07 161600802: Erroneous redi !! 2129 bool
1227 default y !! 2130 select BOARD_SCACHE
1228 help <<
1229 The HiSilicon Hip07 SoC uses the wr <<
1230 when issued ITS commands such as VM <<
1231 a 128kB offset to be applied to the <<
1232 2131
1233 If unsure, say Y. !! 2132 config RM7000_CPU_SCACHE
>> 2133 bool
>> 2134 select BOARD_SCACHE
1234 2135
1235 config QCOM_FALKOR_ERRATUM_1003 !! 2136 config SIBYTE_DMA_PAGEOPS
1236 bool "Falkor E1003: Incorrect transla !! 2137 bool "Use DMA to clear/copy pages"
1237 default y !! 2138 depends on CPU_SB1
1238 help 2139 help
1239 On Falkor v1, an incorrect ASID may !! 2140 Instead of using the CPU to zero and copy pages, use a Data Mover
1240 and BADDR are changed together in T !! 2141 channel. These DMA channels are otherwise unused by the standard
1241 in TTBR1_EL1, this situation only o !! 2142 SiByte Linux port. Seems to give a small performance benefit.
1242 then only for entries in the walk c <<
1243 is unchanged. Work around the errat <<
1244 entries for the trampoline before e <<
1245 2143
1246 config QCOM_FALKOR_ERRATUM_1009 !! 2144 config CPU_HAS_PREFETCH
1247 bool "Falkor E1009: Prematurely compl !! 2145 bool
1248 default y <<
1249 select ARM64_WORKAROUND_REPEAT_TLBI <<
1250 help <<
1251 On Falkor v1, the CPU may premature <<
1252 TLBI xxIS invalidate maintenance op <<
1253 one more time to fix the issue. <<
1254 2146
1255 If unsure, say Y. !! 2147 config CPU_GENERIC_DUMP_TLB
>> 2148 bool
>> 2149 default y if !CPU_R3000
1256 2150
1257 config QCOM_QDF2400_ERRATUM_0065 !! 2151 config MIPS_FP_SUPPORT
1258 bool "QDF2400 E0065: Incorrect GITS_T !! 2152 bool "Floating Point support" if EXPERT
1259 default y 2153 default y
1260 help 2154 help
1261 On Qualcomm Datacenter Technologies !! 2155 Select y to include support for floating point in the kernel
1262 ITE size incorrectly. The GITS_TYPE !! 2156 including initialization of FPU hardware, FP context save & restore
1263 been indicated as 16Bytes (0xf), no !! 2157 and emulation of an FPU where necessary. Without this support any
>> 2158 userland program attempting to use floating point instructions will
>> 2159 receive a SIGILL.
1264 2160
1265 If unsure, say Y. !! 2161 If you know that your userland will not attempt to use floating point
>> 2162 instructions then you can say n here to shrink the kernel a little.
1266 2163
1267 config QCOM_FALKOR_ERRATUM_E1041 !! 2164 If unsure, say y.
1268 bool "Falkor E1041: Speculative instr <<
1269 default y <<
1270 help <<
1271 Falkor CPU may speculatively fetch <<
1272 memory location when MMU translatio <<
1273 to SCTLR_ELn[M]=0. Prefix an ISB in <<
1274 2165
1275 If unsure, say Y. !! 2166 config CPU_R2300_FPU
>> 2167 bool
>> 2168 depends on MIPS_FP_SUPPORT
>> 2169 default y if CPU_R3000
1276 2170
1277 config NVIDIA_CARMEL_CNP_ERRATUM !! 2171 config CPU_R3K_TLB
1278 bool "NVIDIA Carmel CNP: CNP on Carme !! 2172 bool
1279 default y <<
1280 help <<
1281 If CNP is enabled on Carmel cores, <<
1282 invalidate shared TLB entries insta <<
1283 on standard ARM cores. <<
1284 2173
1285 If unsure, say Y. !! 2174 config CPU_R4K_FPU
>> 2175 bool
>> 2176 depends on MIPS_FP_SUPPORT
>> 2177 default y if !CPU_R2300_FPU
1286 2178
1287 config ROCKCHIP_ERRATUM_3588001 !! 2179 config CPU_R4K_CACHE_TLB
1288 bool "Rockchip 3588001: GIC600 can no !! 2180 bool
>> 2181 default y if !(CPU_R3K_TLB || CPU_SB1 || CPU_CAVIUM_OCTEON)
>> 2182
>> 2183 config MIPS_MT_SMP
>> 2184 bool "MIPS MT SMP support (1 TC on each available VPE)"
1289 default y 2185 default y
1290 help !! 2186 depends on TARGET_ISA_REV > 0 && TARGET_ISA_REV < 6
1291 The Rockchip RK3588 GIC600 SoC inte !! 2187 depends on SYS_SUPPORTS_MULTITHREADING && !CPU_MICROMIPS
1292 This means, that its sharability fe !! 2188 select CPU_MIPSR2_IRQ_VI
1293 is supported by the IP itself. !! 2189 select CPU_MIPSR2_IRQ_EI
>> 2190 select SYNC_R4K
>> 2191 select MIPS_MT
>> 2192 select SMP
>> 2193 select SMP_UP
>> 2194 select SYS_SUPPORTS_SMP
>> 2195 select SYS_SUPPORTS_SCHED_SMT
>> 2196 select MIPS_PERF_SHARED_TC_COUNTERS
>> 2197 help
>> 2198 This is a kernel model which is known as SMVP. This is supported
>> 2199 on cores with the MT ASE and uses the available VPEs to implement
>> 2200 virtual processors which supports SMP. This is equivalent to the
>> 2201 Intel Hyperthreading feature. For further information go to
>> 2202 <http://www.imgtec.com/mips/mips-multithreading.asp>.
1294 2203
1295 If unsure, say Y. !! 2204 config MIPS_MT
>> 2205 bool
1296 2206
1297 config SOCIONEXT_SYNQUACER_PREITS !! 2207 config SCHED_SMT
1298 bool "Socionext Synquacer: Workaround !! 2208 bool "SMT (multithreading) scheduler support"
1299 default y !! 2209 depends on SYS_SUPPORTS_SCHED_SMT
>> 2210 default n
1300 help 2211 help
1301 Socionext Synquacer SoCs implement !! 2212 SMT scheduler support improves the CPU scheduler's decision making
1302 MSI doorbell writes with non-zero v !! 2213 when dealing with MIPS MT enabled cores at a cost of slightly
>> 2214 increased overhead in some places. If unsure say N here.
1303 2215
1304 If unsure, say Y. !! 2216 config SYS_SUPPORTS_SCHED_SMT
>> 2217 bool
1305 2218
1306 endmenu # "ARM errata workarounds via the alt !! 2219 config SYS_SUPPORTS_MULTITHREADING
>> 2220 bool
1307 2221
1308 choice !! 2222 config MIPS_MT_FPAFF
1309 prompt "Page size" !! 2223 bool "Dynamic FPU affinity for FP-intensive threads"
1310 default ARM64_4K_PAGES !! 2224 default y
1311 help !! 2225 depends on MIPS_MT_SMP
1312 Page size (translation granule) con <<
1313 2226
1314 config ARM64_4K_PAGES !! 2227 config MIPSR2_TO_R6_EMULATOR
1315 bool "4KB" !! 2228 bool "MIPS R2-to-R6 emulator"
1316 select HAVE_PAGE_SIZE_4KB !! 2229 depends on CPU_MIPSR6
>> 2230 depends on MIPS_FP_SUPPORT
>> 2231 default y
1317 help 2232 help
1318 This feature enables 4KB pages supp !! 2233 Choose this option if you want to run non-R6 MIPS userland code.
>> 2234 Even if you say 'Y' here, the emulator will still be disabled by
>> 2235 default. You can enable it using the 'mipsr2emu' kernel option.
>> 2236 The only reason this is a build-time option is to save ~14K from the
>> 2237 final kernel image.
1319 2238
1320 config ARM64_16K_PAGES !! 2239 config SYS_SUPPORTS_VPE_LOADER
1321 bool "16KB" !! 2240 bool
1322 select HAVE_PAGE_SIZE_16KB !! 2241 depends on SYS_SUPPORTS_MULTITHREADING
1323 help 2242 help
1324 The system will use 16KB pages supp !! 2243 Indicates that the platform supports the VPE loader, and provides
1325 requires applications compiled with !! 2244 physical_memsize.
1326 aligned segments. <<
1327 2245
1328 config ARM64_64K_PAGES !! 2246 config MIPS_VPE_LOADER
1329 bool "64KB" !! 2247 bool "VPE loader support."
1330 select HAVE_PAGE_SIZE_64KB !! 2248 depends on SYS_SUPPORTS_VPE_LOADER && MODULES
>> 2249 select CPU_MIPSR2_IRQ_VI
>> 2250 select CPU_MIPSR2_IRQ_EI
>> 2251 select MIPS_MT
1331 help 2252 help
1332 This feature enables 64KB pages sup !! 2253 Includes a loader for loading an elf relocatable object
1333 allowing only two levels of page ta !! 2254 onto another VPE and running it.
1334 look-up. AArch32 emulation requires <<
1335 with 64K aligned segments. <<
1336 2255
1337 endchoice !! 2256 config MIPS_VPE_LOADER_MT
>> 2257 bool
>> 2258 default "y"
>> 2259 depends on MIPS_VPE_LOADER
1338 2260
1339 choice !! 2261 config MIPS_VPE_LOADER_TOM
1340 prompt "Virtual address space size" !! 2262 bool "Load VPE program into memory hidden from linux"
1341 default ARM64_VA_BITS_52 !! 2263 depends on MIPS_VPE_LOADER
>> 2264 default y
1342 help 2265 help
1343 Allows choosing one of multiple pos !! 2266 The loader can use memory that is present but has been hidden from
1344 space sizes. The level of translati !! 2267 Linux using the kernel command line option "mem=xxMB". It's up to
1345 a combination of page size and virt !! 2268 you to ensure the amount you put in the option and the space your
1346 !! 2269 program requires is less or equal to the amount physically present.
1347 config ARM64_VA_BITS_36 <<
1348 bool "36-bit" if EXPERT <<
1349 depends on PAGE_SIZE_16KB <<
1350 <<
1351 config ARM64_VA_BITS_39 <<
1352 bool "39-bit" <<
1353 depends on PAGE_SIZE_4KB <<
1354 <<
1355 config ARM64_VA_BITS_42 <<
1356 bool "42-bit" <<
1357 depends on PAGE_SIZE_64KB <<
1358 <<
1359 config ARM64_VA_BITS_47 <<
1360 bool "47-bit" <<
1361 depends on PAGE_SIZE_16KB <<
1362 <<
1363 config ARM64_VA_BITS_48 <<
1364 bool "48-bit" <<
1365 <<
1366 config ARM64_VA_BITS_52 <<
1367 bool "52-bit" <<
1368 depends on ARM64_PAN || !ARM64_SW_TTB <<
1369 help <<
1370 Enable 52-bit virtual addressing fo <<
1371 requested via a hint to mmap(). The <<
1372 virtual addresses for its own mappi <<
1373 this feature is available, otherwis <<
1374 <<
1375 NOTE: Enabling 52-bit virtual addre <<
1376 ARMv8.3 Pointer Authentication will <<
1377 reduced from 7 bits to 3 bits, whic <<
1378 impact on its susceptibility to bru <<
1379 2270
1380 If unsure, select 48-bit virtual ad !! 2271 config MIPS_VPE_APSP_API
>> 2272 bool "Enable support for AP/SP API (RTLX)"
>> 2273 depends on MIPS_VPE_LOADER
1381 2274
1382 endchoice !! 2275 config MIPS_VPE_APSP_API_MT
1383 !! 2276 bool
1384 config ARM64_FORCE_52BIT !! 2277 default "y"
1385 bool "Force 52-bit virtual addresses !! 2278 depends on MIPS_VPE_APSP_API
1386 depends on ARM64_VA_BITS_52 && EXPERT <<
1387 help <<
1388 For systems with 52-bit userspace V <<
1389 to maintain compatibility with olde <<
1390 unless a hint is supplied to mmap. <<
1391 <<
1392 This configuration option disables <<
1393 forces all userspace addresses to b <<
1394 should only enable this configurati <<
1395 memory management code. If unsure s <<
1396 2279
1397 config ARM64_VA_BITS !! 2280 config MIPS_CPS
1398 int !! 2281 bool "MIPS Coherent Processing System support"
1399 default 36 if ARM64_VA_BITS_36 !! 2282 depends on SYS_SUPPORTS_MIPS_CPS
1400 default 39 if ARM64_VA_BITS_39 !! 2283 select MIPS_CM
1401 default 42 if ARM64_VA_BITS_42 !! 2284 select MIPS_CPS_PM if HOTPLUG_CPU
1402 default 47 if ARM64_VA_BITS_47 !! 2285 select SMP
1403 default 48 if ARM64_VA_BITS_48 !! 2286 select HOTPLUG_CORE_SYNC_DEAD if HOTPLUG_CPU
1404 default 52 if ARM64_VA_BITS_52 !! 2287 select SYNC_R4K if (CEVT_R4K || CSRC_R4K)
>> 2288 select SYS_SUPPORTS_HOTPLUG_CPU
>> 2289 select SYS_SUPPORTS_SCHED_SMT if CPU_MIPSR6
>> 2290 select SYS_SUPPORTS_SMP
>> 2291 select WEAK_ORDERING
>> 2292 select GENERIC_IRQ_MIGRATION if HOTPLUG_CPU
>> 2293 help
>> 2294 Select this if you wish to run an SMP kernel across multiple cores
>> 2295 within a MIPS Coherent Processing System. When this option is
>> 2296 enabled the kernel will probe for other cores and boot them with
>> 2297 no external assistance. It is safe to enable this when hardware
>> 2298 support is unavailable.
1405 2299
1406 choice !! 2300 config MIPS_CPS_PM
1407 prompt "Physical address space size" !! 2301 depends on MIPS_CPS
1408 default ARM64_PA_BITS_48 !! 2302 bool
1409 help <<
1410 Choose the maximum physical address <<
1411 support. <<
1412 2303
1413 config ARM64_PA_BITS_48 !! 2304 config MIPS_CM
1414 bool "48-bit" !! 2305 bool
1415 depends on ARM64_64K_PAGES || !ARM64_ !! 2306 select MIPS_CPC
1416 <<
1417 config ARM64_PA_BITS_52 <<
1418 bool "52-bit" <<
1419 depends on ARM64_64K_PAGES || ARM64_V <<
1420 depends on ARM64_PAN || !ARM64_SW_TTB <<
1421 help <<
1422 Enable support for a 52-bit physica <<
1423 part of the ARMv8.2-LPA extension. <<
1424 <<
1425 With this enabled, the kernel will <<
1426 do not support ARMv8.2-LPA, but wit <<
1427 minor performance overhead). <<
1428 2307
1429 endchoice !! 2308 config MIPS_CPC
>> 2309 bool
1430 2310
1431 config ARM64_PA_BITS !! 2311 config SB1_PASS_2_WORKAROUNDS
1432 int !! 2312 bool
1433 default 48 if ARM64_PA_BITS_48 !! 2313 depends on CPU_SB1 && (CPU_SB1_PASS_2_2 || CPU_SB1_PASS_2)
1434 default 52 if ARM64_PA_BITS_52 !! 2314 default y
1435 2315
1436 config ARM64_LPA2 !! 2316 config SB1_PASS_2_1_WORKAROUNDS
1437 def_bool y !! 2317 bool
1438 depends on ARM64_PA_BITS_52 && !ARM64 !! 2318 depends on CPU_SB1 && CPU_SB1_PASS_2
>> 2319 default y
1439 2320
1440 choice 2321 choice
1441 prompt "Endianness" !! 2322 prompt "SmartMIPS or microMIPS ASE support"
1442 default CPU_LITTLE_ENDIAN <<
1443 help <<
1444 Select the endianness of data acces <<
1445 applications will need to be compil <<
1446 that is selected here. <<
1447 2323
1448 config CPU_BIG_ENDIAN !! 2324 config CPU_NEEDS_NO_SMARTMIPS_OR_MICROMIPS
1449 bool "Build big-endian kernel" !! 2325 bool "None"
1450 # https://github.com/llvm/llvm-projec <<
1451 depends on AS_IS_GNU || AS_VERSION >= <<
1452 help 2326 help
1453 Say Y if you plan on running a kern !! 2327 Select this if you want neither microMIPS nor SmartMIPS support
1454 2328
1455 config CPU_LITTLE_ENDIAN !! 2329 config CPU_HAS_SMARTMIPS
1456 bool "Build little-endian kernel" !! 2330 depends on SYS_SUPPORTS_SMARTMIPS
>> 2331 bool "SmartMIPS"
>> 2332 help
>> 2333 SmartMIPS is a extension of the MIPS32 architecture aimed at
>> 2334 increased security at both hardware and software level for
>> 2335 smartcards. Enabling this option will allow proper use of the
>> 2336 SmartMIPS instructions by Linux applications. However a kernel with
>> 2337 this option will not work on a MIPS core without SmartMIPS core. If
>> 2338 you don't know you probably don't have SmartMIPS and should say N
>> 2339 here.
>> 2340
>> 2341 config CPU_MICROMIPS
>> 2342 depends on 32BIT && SYS_SUPPORTS_MICROMIPS && !CPU_MIPSR6
>> 2343 bool "microMIPS"
1457 help 2344 help
1458 Say Y if you plan on running a kern !! 2345 When this option is enabled the kernel will be built using the
1459 This is usually the case for distri !! 2346 microMIPS ISA
1460 2347
1461 endchoice 2348 endchoice
1462 2349
1463 config SCHED_MC !! 2350 config CPU_HAS_MSA
1464 bool "Multi-core scheduler support" !! 2351 bool "Support for the MIPS SIMD Architecture"
1465 help !! 2352 depends on CPU_SUPPORTS_MSA
1466 Multi-core scheduler support improv !! 2353 depends on MIPS_FP_SUPPORT
1467 making when dealing with multi-core !! 2354 depends on 64BIT || MIPS_O32_FP64_SUPPORT
1468 increased overhead in some places. !! 2355 help
>> 2356 MIPS SIMD Architecture (MSA) introduces 128 bit wide vector registers
>> 2357 and a set of SIMD instructions to operate on them. When this option
>> 2358 is enabled the kernel will support allocating & switching MSA
>> 2359 vector register contexts. If you know that your kernel will only be
>> 2360 running on CPUs which do not support MSA or that your userland will
>> 2361 not be making use of it then you may wish to say N here to reduce
>> 2362 the size & complexity of your kernel.
1469 2363
1470 config SCHED_CLUSTER !! 2364 If unsure, say Y.
1471 bool "Cluster scheduler support" <<
1472 help <<
1473 Cluster scheduler support improves <<
1474 making when dealing with machines t <<
1475 Cluster usually means a couple of C <<
1476 by sharing mid-level caches, last-l <<
1477 busses. <<
1478 2365
1479 config SCHED_SMT !! 2366 config CPU_HAS_WB
1480 bool "SMT scheduler support" !! 2367 bool
1481 help <<
1482 Improves the CPU scheduler's decisi <<
1483 MultiThreading at a cost of slightl <<
1484 places. If unsure say N here. <<
1485 2368
1486 config NR_CPUS !! 2369 config XKS01
1487 int "Maximum number of CPUs (2-4096)" !! 2370 bool
1488 range 2 4096 <<
1489 default "512" <<
1490 2371
1491 config HOTPLUG_CPU !! 2372 config CPU_HAS_DIEI
1492 bool "Support for hot-pluggable CPUs" !! 2373 depends on !CPU_DIEI_BROKEN
1493 select GENERIC_IRQ_MIGRATION !! 2374 bool
1494 help <<
1495 Say Y here to experiment with turni <<
1496 can be controlled through /sys/devi <<
1497 2375
1498 # Common NUMA Features !! 2376 config CPU_DIEI_BROKEN
1499 config NUMA !! 2377 bool
1500 bool "NUMA Memory Allocation and Sche <<
1501 select GENERIC_ARCH_NUMA <<
1502 select OF_NUMA <<
1503 select HAVE_SETUP_PER_CPU_AREA <<
1504 select NEED_PER_CPU_EMBED_FIRST_CHUNK <<
1505 select NEED_PER_CPU_PAGE_FIRST_CHUNK <<
1506 select USE_PERCPU_NUMA_NODE_ID <<
1507 help <<
1508 Enable NUMA (Non-Uniform Memory Acc <<
1509 2378
1510 The kernel will try to allocate mem !! 2379 config CPU_HAS_RIXI
1511 local memory of the CPU and add som !! 2380 bool
1512 NUMA awareness to the kernel. <<
1513 2381
1514 config NODES_SHIFT !! 2382 config CPU_NO_LOAD_STORE_LR
1515 int "Maximum NUMA Nodes (as a power o !! 2383 bool
1516 range 1 10 <<
1517 default "4" <<
1518 depends on NUMA <<
1519 help 2384 help
1520 Specify the maximum number of NUMA !! 2385 CPU lacks support for unaligned load and store instructions:
1521 system. Increases memory reserved !! 2386 LWL, LWR, SWL, SWR (Load/store word left/right).
>> 2387 LDL, LDR, SDL, SDR (Load/store doubleword left/right, for 64bit
>> 2388 systems).
1522 2389
1523 source "kernel/Kconfig.hz" !! 2390 #
>> 2391 # Vectored interrupt mode is an R2 feature
>> 2392 #
>> 2393 config CPU_MIPSR2_IRQ_VI
>> 2394 bool
1524 2395
1525 config ARCH_SPARSEMEM_ENABLE !! 2396 #
1526 def_bool y !! 2397 # Extended interrupt mode is an R2 feature
1527 select SPARSEMEM_VMEMMAP_ENABLE !! 2398 #
1528 select SPARSEMEM_VMEMMAP !! 2399 config CPU_MIPSR2_IRQ_EI
>> 2400 bool
1529 2401
1530 config HW_PERF_EVENTS !! 2402 config CPU_HAS_SYNC
1531 def_bool y !! 2403 bool
1532 depends on ARM_PMU !! 2404 depends on !CPU_R3000
>> 2405 default y
1533 2406
1534 # Supported by clang >= 7.0 or GCC >= 12.0.0 !! 2407 #
1535 config CC_HAVE_SHADOW_CALL_STACK !! 2408 # CPU non-features
1536 def_bool $(cc-option, -fsanitize=shad !! 2409 #
1537 2410
1538 config PARAVIRT !! 2411 # Work around the "daddi" and "daddiu" CPU errata:
1539 bool "Enable paravirtualization code" !! 2412 #
1540 help !! 2413 # - The `daddi' instruction fails to trap on overflow.
1541 This changes the kernel so it can m !! 2414 # "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0",
1542 under a hypervisor, potentially imp !! 2415 # erratum #23
1543 over full virtualization. !! 2416 #
>> 2417 # - The `daddiu' instruction can produce an incorrect result.
>> 2418 # "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0",
>> 2419 # erratum #41
>> 2420 # "MIPS R4000MC Errata, Processor Revision 2.2 and 3.0", erratum
>> 2421 # #15
>> 2422 # "MIPS R4400PC/SC Errata, Processor Revision 1.0", erratum #7
>> 2423 # "MIPS R4400MC Errata, Processor Revision 1.0", erratum #5
>> 2424 config CPU_DADDI_WORKAROUNDS
>> 2425 bool
1544 2426
1545 config PARAVIRT_TIME_ACCOUNTING !! 2427 # Work around certain R4000 CPU errata (as implemented by GCC):
1546 bool "Paravirtual steal time accounti !! 2428 #
1547 select PARAVIRT !! 2429 # - A double-word or a variable shift may give an incorrect result
1548 help !! 2430 # if executed immediately after starting an integer division:
1549 Select this option to enable fine g !! 2431 # "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0",
1550 accounting. Time spent executing ot !! 2432 # erratum #28
1551 the current vCPU is discounted from !! 2433 # "MIPS R4000MC Errata, Processor Revision 2.2 and 3.0", erratum
1552 that, there can be a small performa !! 2434 # #19
>> 2435 #
>> 2436 # - A double-word or a variable shift may give an incorrect result
>> 2437 # if executed while an integer multiplication is in progress:
>> 2438 # "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0",
>> 2439 # errata #16 & #28
>> 2440 #
>> 2441 # - An integer division may give an incorrect result if started in
>> 2442 # a delay slot of a taken branch or a jump:
>> 2443 # "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0",
>> 2444 # erratum #52
>> 2445 config CPU_R4000_WORKAROUNDS
>> 2446 bool
>> 2447 select CPU_R4400_WORKAROUNDS
1553 2448
1554 If in doubt, say N here. !! 2449 # Work around certain R4400 CPU errata (as implemented by GCC):
>> 2450 #
>> 2451 # - A double-word or a variable shift may give an incorrect result
>> 2452 # if executed immediately after starting an integer division:
>> 2453 # "MIPS R4400MC Errata, Processor Revision 1.0", erratum #10
>> 2454 # "MIPS R4400MC Errata, Processor Revision 2.0 & 3.0", erratum #4
>> 2455 config CPU_R4400_WORKAROUNDS
>> 2456 bool
1555 2457
1556 config ARCH_SUPPORTS_KEXEC !! 2458 config CPU_R4X00_BUGS64
1557 def_bool PM_SLEEP_SMP !! 2459 bool
>> 2460 default y if SYS_HAS_CPU_R4X00 && 64BIT && (TARGET_ISA_REV < 1)
1558 2461
1559 config ARCH_SUPPORTS_KEXEC_FILE !! 2462 config MIPS_ASID_SHIFT
1560 def_bool y !! 2463 int
>> 2464 default 6 if CPU_R3000
>> 2465 default 0
1561 2466
1562 config ARCH_SELECTS_KEXEC_FILE !! 2467 config MIPS_ASID_BITS
1563 def_bool y !! 2468 int
1564 depends on KEXEC_FILE !! 2469 default 0 if MIPS_ASID_BITS_VARIABLE
1565 select HAVE_IMA_KEXEC if IMA !! 2470 default 6 if CPU_R3000
>> 2471 default 8
1566 2472
1567 config ARCH_SUPPORTS_KEXEC_SIG !! 2473 config MIPS_ASID_BITS_VARIABLE
1568 def_bool y !! 2474 bool
1569 2475
1570 config ARCH_SUPPORTS_KEXEC_IMAGE_VERIFY_SIG !! 2476 config MIPS_CRC_SUPPORT
1571 def_bool y !! 2477 bool
1572 2478
1573 config ARCH_DEFAULT_KEXEC_IMAGE_VERIFY_SIG !! 2479 # R4600 erratum. Due to the lack of errata information the exact
1574 def_bool y !! 2480 # technical details aren't known. I've experimentally found that disabling
>> 2481 # interrupts during indexed I-cache flushes seems to be sufficient to deal
>> 2482 # with the issue.
>> 2483 config WAR_R4600_V1_INDEX_ICACHEOP
>> 2484 bool
1575 2485
1576 config ARCH_SUPPORTS_CRASH_DUMP !! 2486 # Pleasures of the R4600 V1.x. Cite from the IDT R4600 V1.7 errata:
1577 def_bool y !! 2487 #
>> 2488 # 18. The CACHE instructions Hit_Writeback_Invalidate_D, Hit_Writeback_D,
>> 2489 # Hit_Invalidate_D and Create_Dirty_Excl_D should only be
>> 2490 # executed if there is no other dcache activity. If the dcache is
>> 2491 # accessed for another instruction immediately preceding when these
>> 2492 # cache instructions are executing, it is possible that the dcache
>> 2493 # tag match outputs used by these cache instructions will be
>> 2494 # incorrect. These cache instructions should be preceded by at least
>> 2495 # four instructions that are not any kind of load or store
>> 2496 # instruction.
>> 2497 #
>> 2498 # This is not allowed: lw
>> 2499 # nop
>> 2500 # nop
>> 2501 # nop
>> 2502 # cache Hit_Writeback_Invalidate_D
>> 2503 #
>> 2504 # This is allowed: lw
>> 2505 # nop
>> 2506 # nop
>> 2507 # nop
>> 2508 # nop
>> 2509 # cache Hit_Writeback_Invalidate_D
>> 2510 config WAR_R4600_V1_HIT_CACHEOP
>> 2511 bool
>> 2512
>> 2513 # Writeback and invalidate the primary cache dcache before DMA.
>> 2514 #
>> 2515 # R4600 v2.0 bug: "The CACHE instructions Hit_Writeback_Inv_D,
>> 2516 # Hit_Writeback_D, Hit_Invalidate_D and Create_Dirty_Exclusive_D will only
>> 2517 # operate correctly if the internal data cache refill buffer is empty. These
>> 2518 # CACHE instructions should be separated from any potential data cache miss
>> 2519 # by a load instruction to an uncached address to empty the response buffer."
>> 2520 # (Revision 2.0 device errata from IDT available on https://www.idt.com/
>> 2521 # in .pdf format.)
>> 2522 config WAR_R4600_V2_HIT_CACHEOP
>> 2523 bool
1578 2524
1579 config ARCH_HAS_GENERIC_CRASHKERNEL_RESERVATI !! 2525 # From TX49/H2 manual: "If the instruction (i.e. CACHE) is issued for
1580 def_bool CRASH_RESERVE !! 2526 # the line which this instruction itself exists, the following
>> 2527 # operation is not guaranteed."
>> 2528 #
>> 2529 # Workaround: do two phase flushing for Index_Invalidate_I
>> 2530 config WAR_TX49XX_ICACHE_INDEX_INV
>> 2531 bool
1581 2532
1582 config TRANS_TABLE !! 2533 # The RM7000 processors and the E9000 cores have a bug (though PMC-Sierra
1583 def_bool y !! 2534 # opposes it being called that) where invalid instructions in the same
1584 depends on HIBERNATION || KEXEC_CORE !! 2535 # I-cache line worth of instructions being fetched may case spurious
>> 2536 # exceptions.
>> 2537 config WAR_ICACHE_REFILLS
>> 2538 bool
1585 2539
1586 config XEN_DOM0 !! 2540 # On the R10000 up to version 2.6 (not sure about 2.7) there is a bug that
1587 def_bool y !! 2541 # may cause ll / sc and lld / scd sequences to execute non-atomically.
1588 depends on XEN !! 2542 config WAR_R10000_LLSC
>> 2543 bool
1589 2544
1590 config XEN !! 2545 # 34K core erratum: "Problems Executing the TLBR Instruction"
1591 bool "Xen guest support on ARM64" !! 2546 config WAR_MIPS34K_MISSED_ITLB
1592 depends on ARM64 && OF !! 2547 bool
1593 select SWIOTLB_XEN <<
1594 select PARAVIRT <<
1595 help <<
1596 Say Y if you want to run Linux in a <<
1597 2548
1598 # include/linux/mmzone.h requires the followi <<
1599 # <<
1600 # MAX_PAGE_ORDER + PAGE_SHIFT <= SECTION_SI <<
1601 # 2549 #
1602 # so the maximum value of MAX_PAGE_ORDER is S !! 2550 # - Highmem only makes sense for the 32-bit kernel.
>> 2551 # - The current highmem code will only work properly on physically indexed
>> 2552 # caches such as R3000, SB1, R7000 or those that look like they're virtually
>> 2553 # indexed such as R4000/R4400 SC and MC versions or R10000. So for the
>> 2554 # moment we protect the user and offer the highmem option only on machines
>> 2555 # where it's known to be safe. This will not offer highmem on a few systems
>> 2556 # such as MIPS32 and MIPS64 CPUs which may have virtual and physically
>> 2557 # indexed CPUs but we're playing safe.
>> 2558 # - We use SYS_SUPPORTS_HIGHMEM to offer highmem only for systems where we
>> 2559 # know they might have memory configurations that could make use of highmem
>> 2560 # support.
1603 # 2561 #
1604 # | SECTION_SIZE_BITS | PAGE_SHIFT | m !! 2562 config HIGHMEM
1605 # ----+-------------------+--------------+--- !! 2563 bool "High Memory Support"
1606 # 4K | 27 | 12 | !! 2564 depends on 32BIT && CPU_SUPPORTS_HIGHMEM && SYS_SUPPORTS_HIGHMEM && !CPU_MIPS32_3_5_EVA
1607 # 16K | 27 | 14 | !! 2565 select KMAP_LOCAL
1608 # 64K | 29 | 16 | <<
1609 config ARCH_FORCE_MAX_ORDER <<
1610 int <<
1611 default "13" if ARM64_64K_PAGES <<
1612 default "11" if ARM64_16K_PAGES <<
1613 default "10" <<
1614 help <<
1615 The kernel page allocator limits th <<
1616 contiguous allocations. The limit i <<
1617 defines the maximal power of two of <<
1618 allocated as a single contiguous bl <<
1619 overriding the default setting when <<
1620 large blocks of physically contiguo <<
1621 <<
1622 The maximal size of allocation cann <<
1623 section, so the value of MAX_PAGE_O <<
1624 <<
1625 MAX_PAGE_ORDER + PAGE_SHIFT <= SE <<
1626 2566
1627 Don't change if unsure. !! 2567 config CPU_SUPPORTS_HIGHMEM
>> 2568 bool
1628 2569
1629 config UNMAP_KERNEL_AT_EL0 !! 2570 config SYS_SUPPORTS_HIGHMEM
1630 bool "Unmap kernel when running in us !! 2571 bool
1631 default y <<
1632 help <<
1633 Speculation attacks against some hi <<
1634 be used to bypass MMU permission ch <<
1635 userspace. This can be defended aga <<
1636 when running in userspace, mapping <<
1637 via a trampoline page in the vector <<
1638 2572
1639 If unsure, say Y. !! 2573 config SYS_SUPPORTS_SMARTMIPS
>> 2574 bool
1640 2575
1641 config MITIGATE_SPECTRE_BRANCH_HISTORY !! 2576 config SYS_SUPPORTS_MICROMIPS
1642 bool "Mitigate Spectre style attacks !! 2577 bool
1643 default y <<
1644 help <<
1645 Speculation attacks against some hi <<
1646 make use of branch history to influ <<
1647 When taking an exception from user- <<
1648 or a firmware call overwrites the b <<
1649 2578
1650 config RODATA_FULL_DEFAULT_ENABLED !! 2579 config SYS_SUPPORTS_MIPS16
1651 bool "Apply r/o permissions of VM are !! 2580 bool
1652 default y <<
1653 help 2581 help
1654 Apply read-only attributes of VM ar !! 2582 This option must be set if a kernel might be executed on a MIPS16-
1655 the backing pages as well. This pre !! 2583 enabled CPU even if MIPS16 is not actually being used. In other
1656 from being modified (inadvertently !! 2584 words, it makes the kernel MIPS16-tolerant.
1657 mapping of the same memory page. Th <<
1658 be turned off at runtime by passing <<
1659 with rodata=full if this option is <<
1660 <<
1661 This requires the linear region to <<
1662 which may adversely affect performa <<
1663 <<
1664 config ARM64_SW_TTBR0_PAN <<
1665 bool "Emulate Privileged Access Never <<
1666 depends on !KCSAN <<
1667 help <<
1668 Enabling this option prevents the k <<
1669 user-space memory directly by point <<
1670 zeroed area and reserved ASID. The <<
1671 restore the valid TTBR0_EL1 tempora <<
1672 2585
1673 config ARM64_TAGGED_ADDR_ABI !! 2586 config CPU_SUPPORTS_MSA
1674 bool "Enable the tagged user addresse !! 2587 bool
1675 default y <<
1676 help <<
1677 When this option is enabled, user a <<
1678 relaxed ABI via prctl() allowing ta <<
1679 to system calls as pointer argument <<
1680 Documentation/arch/arm64/tagged-add <<
1681 <<
1682 menuconfig COMPAT <<
1683 bool "Kernel support for 32-bit EL0" <<
1684 depends on ARM64_4K_PAGES || EXPERT <<
1685 select HAVE_UID16 <<
1686 select OLD_SIGSUSPEND3 <<
1687 select COMPAT_OLD_SIGACTION <<
1688 help <<
1689 This option enables support for a 3 <<
1690 kernel at EL1. AArch32-specific com <<
1691 the user helper functions, VFP supp <<
1692 handled appropriately by the kernel <<
1693 <<
1694 If you use a page size other than 4 <<
1695 that you will only be able to execu <<
1696 with page size aligned segments. <<
1697 2588
1698 If you want to execute 32-bit users !! 2589 config ARCH_FLATMEM_ENABLE
>> 2590 def_bool y
>> 2591 depends on !NUMA && !CPU_LOONGSON2EF
1699 2592
1700 if COMPAT !! 2593 config ARCH_SPARSEMEM_ENABLE
>> 2594 bool
1701 2595
1702 config KUSER_HELPERS !! 2596 config NUMA
1703 bool "Enable kuser helpers page for 3 !! 2597 bool "NUMA Support"
1704 default y !! 2598 depends on SYS_SUPPORTS_NUMA
>> 2599 select SMP
>> 2600 select HAVE_SETUP_PER_CPU_AREA
>> 2601 select NEED_PER_CPU_EMBED_FIRST_CHUNK
1705 help 2602 help
1706 Warning: disabling this option may !! 2603 Say Y to compile the kernel to support NUMA (Non-Uniform Memory
>> 2604 Access). This option improves performance on systems with more
>> 2605 than two nodes; on two node systems it is generally better to
>> 2606 leave it disabled; on single node systems leave this option
>> 2607 disabled.
1707 2608
1708 Provide kuser helpers to compat tas !! 2609 config SYS_SUPPORTS_NUMA
1709 helper code to userspace in read on !! 2610 bool
1710 to allow userspace to be independen <<
1711 the system. This permits binaries t <<
1712 to ARMv8 without modification. <<
1713 <<
1714 See Documentation/arch/arm/kernel_u <<
1715 <<
1716 However, the fixed address nature o <<
1717 by ROP (return orientated programmi <<
1718 exploits. <<
1719 <<
1720 If all of the binaries and librarie <<
1721 are built specifically for your pla <<
1722 these helpers, then you can turn th <<
1723 such exploits. However, in that cas <<
1724 relying on those helpers is run, it <<
1725 <<
1726 Say N here only if you are absolute <<
1727 need these helpers; otherwise, the <<
1728 <<
1729 config COMPAT_VDSO <<
1730 bool "Enable vDSO for 32-bit applicat <<
1731 depends on !CPU_BIG_ENDIAN <<
1732 depends on (CC_IS_CLANG && LD_IS_LLD) <<
1733 select GENERIC_COMPAT_VDSO <<
1734 default y <<
1735 help <<
1736 Place in the process address space <<
1737 ELF shared object providing fast im <<
1738 and clock_gettime. <<
1739 <<
1740 You must have a 32-bit build of gli <<
1741 to seamlessly take advantage of thi <<
1742 <<
1743 config THUMB2_COMPAT_VDSO <<
1744 bool "Compile the 32-bit vDSO for Thu <<
1745 depends on COMPAT_VDSO <<
1746 default y <<
1747 help <<
1748 Compile the compat vDSO with '-mthu <<
1749 otherwise with '-marm'. <<
1750 2611
1751 config COMPAT_ALIGNMENT_FIXUPS !! 2612 config HAVE_ARCH_NODEDATA_EXTENSION
1752 bool "Fix up misaligned multi-word lo !! 2613 bool
1753 2614
1754 menuconfig ARMV8_DEPRECATED !! 2615 config RELOCATABLE
1755 bool "Emulate deprecated/obsolete ARM !! 2616 bool "Relocatable kernel"
1756 depends on SYSCTL !! 2617 depends on SYS_SUPPORTS_RELOCATABLE
1757 help !! 2618 depends on CPU_MIPS32_R2 || CPU_MIPS64_R2 || \
1758 Legacy software support may require !! 2619 CPU_MIPS32_R5 || CPU_MIPS64_R5 || \
1759 that have been deprecated or obsole !! 2620 CPU_MIPS32_R6 || CPU_MIPS64_R6 || \
>> 2621 CPU_P5600 || CAVIUM_OCTEON_SOC || \
>> 2622 CPU_LOONGSON64
>> 2623 help
>> 2624 This builds a kernel image that retains relocation information
>> 2625 so it can be loaded someplace besides the default 1MB.
>> 2626 The relocations make the kernel binary about 15% larger,
>> 2627 but are discarded at runtime
>> 2628
>> 2629 config RELOCATION_TABLE_SIZE
>> 2630 hex "Relocation table size"
>> 2631 depends on RELOCATABLE
>> 2632 range 0x0 0x01000000
>> 2633 default "0x00200000" if CPU_LOONGSON64
>> 2634 default "0x00100000"
>> 2635 help
>> 2636 A table of relocation data will be appended to the kernel binary
>> 2637 and parsed at boot to fix up the relocated kernel.
1760 2638
1761 Enable this config to enable select !! 2639 This option allows the amount of space reserved for the table to be
1762 features. !! 2640 adjusted, although the default of 1Mb should be ok in most cases.
1763 2641
1764 If unsure, say Y !! 2642 The build will fail and a valid size suggested if this is too small.
1765 2643
1766 if ARMV8_DEPRECATED !! 2644 If unsure, leave at the default value.
1767 2645
1768 config SWP_EMULATION !! 2646 config RANDOMIZE_BASE
1769 bool "Emulate SWP/SWPB instructions" !! 2647 bool "Randomize the address of the kernel image"
>> 2648 depends on RELOCATABLE
1770 help 2649 help
1771 ARMv8 obsoletes the use of A32 SWP/ !! 2650 Randomizes the physical and virtual address at which the
1772 they are always undefined. Say Y he !! 2651 kernel image is loaded, as a security feature that
1773 emulation of these instructions for !! 2652 deters exploit attempts relying on knowledge of the location
1774 This feature can be controlled at r !! 2653 of kernel internals.
1775 sysctl which is disabled by default <<
1776 2654
1777 In some older versions of glibc [<= !! 2655 Entropy is generated using any coprocessor 0 registers available.
1778 trylock() operations with the assum <<
1779 be preempted. This invalid assumpti <<
1780 with SWP emulation enabled, leading <<
1781 application. <<
1782 2656
1783 NOTE: when accessing uncached share !! 2657 The kernel will be offset by up to RANDOMIZE_BASE_MAX_OFFSET.
1784 on an external transaction monitori <<
1785 monitor to maintain update atomicit <<
1786 implement a global monitor, this op <<
1787 perform SWP operations to uncached <<
1788 2658
1789 If unsure, say Y !! 2659 If unsure, say N.
1790 2660
1791 config CP15_BARRIER_EMULATION !! 2661 config RANDOMIZE_BASE_MAX_OFFSET
1792 bool "Emulate CP15 Barrier instructio !! 2662 hex "Maximum kASLR offset" if EXPERT
1793 help !! 2663 depends on RANDOMIZE_BASE
1794 The CP15 barrier instructions - CP1 !! 2664 range 0x0 0x40000000 if EVA || 64BIT
1795 CP15DMB - are deprecated in ARMv8 ( !! 2665 range 0x0 0x08000000
1796 strongly recommended to use the ISB !! 2666 default "0x01000000"
1797 instructions instead. !! 2667 help
>> 2668 When kASLR is active, this provides the maximum offset that will
>> 2669 be applied to the kernel image. It should be set according to the
>> 2670 amount of physical RAM available in the target system minus
>> 2671 PHYSICAL_START and must be a power of 2.
1798 2672
1799 Say Y here to enable software emula !! 2673 This is limited by the size of KSEG0, 256Mb on 32-bit or 1Gb with
1800 instructions for AArch32 userspace !! 2674 EVA or 64-bit. The default is 16Mb.
1801 enabled, CP15 barrier usage is trac <<
1802 identify software that needs updati <<
1803 controlled at runtime with the abi. <<
1804 2675
1805 If unsure, say Y !! 2676 config NODES_SHIFT
>> 2677 int
>> 2678 default "6"
>> 2679 depends on NUMA
1806 2680
1807 config SETEND_EMULATION !! 2681 config HW_PERF_EVENTS
1808 bool "Emulate SETEND instruction" !! 2682 bool "Enable hardware performance counter support for perf events"
>> 2683 depends on PERF_EVENTS && (CPU_MIPS32 || CPU_MIPS64 || CPU_R10000 || CPU_SB1 || CPU_CAVIUM_OCTEON || CPU_LOONGSON64)
>> 2684 default y
1809 help 2685 help
1810 The SETEND instruction alters the d !! 2686 Enable hardware performance counter support for perf events. If
1811 AArch32 EL0, and is deprecated in A !! 2687 disabled, perf events will use software events only.
1812 2688
1813 Say Y here to enable software emula !! 2689 config DMI
1814 for AArch32 userspace code. This fe !! 2690 bool "Enable DMI scanning"
1815 at runtime with the abi.setend sysc !! 2691 depends on MACH_LOONGSON64
>> 2692 select DMI_SCAN_MACHINE_NON_EFI_FALLBACK
>> 2693 default y
>> 2694 help
>> 2695 Enabled scanning of DMI to identify machine quirks. Say Y
>> 2696 here unless you have verified that your setup is not
>> 2697 affected by entries in the DMI blacklist. Required by PNP
>> 2698 BIOS code.
1816 2699
1817 Note: All the cpus on the system mu !! 2700 config SMP
1818 for this feature to be enabled. If !! 2701 bool "Multi-Processing support"
1819 endian - is hotplugged in after thi !! 2702 depends on SYS_SUPPORTS_SMP
1820 be unexpected results in the applic !! 2703 help
>> 2704 This enables support for systems with more than one CPU. If you have
>> 2705 a system with only one CPU, say N. If you have a system with more
>> 2706 than one CPU, say Y.
>> 2707
>> 2708 If you say N here, the kernel will run on uni- and multiprocessor
>> 2709 machines, but will use only one CPU of a multiprocessor machine. If
>> 2710 you say Y here, the kernel will run on many, but not all,
>> 2711 uniprocessor machines. On a uniprocessor machine, the kernel
>> 2712 will run faster if you say N here.
1821 2713
1822 If unsure, say Y !! 2714 People using multiprocessor machines who say Y here should also say
1823 endif # ARMV8_DEPRECATED !! 2715 Y to "Enhanced Real Time Clock Support", below.
1824 2716
1825 endif # COMPAT !! 2717 See also the SMP-HOWTO available at
>> 2718 <https://www.tldp.org/docs.html#howto>.
1826 2719
1827 menu "ARMv8.1 architectural features" !! 2720 If you don't know what to do here, say N.
1828 2721
1829 config ARM64_HW_AFDBM !! 2722 config HOTPLUG_CPU
1830 bool "Support for hardware updates of !! 2723 bool "Support for hot-pluggable CPUs"
1831 default y !! 2724 depends on SMP && SYS_SUPPORTS_HOTPLUG_CPU
1832 help 2725 help
1833 The ARMv8.1 architecture extensions !! 2726 Say Y here to allow turning CPUs off and on. CPUs can be
1834 hardware updates of the access and !! 2727 controlled through /sys/devices/system/cpu.
1835 table entries. When enabled in TCR_ !! 2728 (Note: power management support will enable this option
1836 capable processors, accesses to pag !! 2729 automatically on SMP systems. )
1837 set this bit instead of raising an !! 2730 Say N if you want to disable CPU hotplug.
1838 Similarly, writes to read-only page <<
1839 clear the read-only bit (AP[2]) ins <<
1840 permission fault. <<
1841 <<
1842 Kernels built with this configurati <<
1843 to work on pre-ARMv8.1 hardware and <<
1844 minimal. If unsure, say Y. <<
1845 2731
1846 config ARM64_PAN !! 2732 config SMP_UP
1847 bool "Enable support for Privileged A !! 2733 bool
1848 default y <<
1849 help <<
1850 Privileged Access Never (PAN; part <<
1851 prevents the kernel or hypervisor f <<
1852 memory directly. <<
1853 2734
1854 Choosing this option will cause any !! 2735 config SYS_SUPPORTS_MIPS_CPS
1855 copy_to_user et al) memory access t !! 2736 bool
1856 2737
1857 The feature is detected at runtime, !! 2738 config SYS_SUPPORTS_SMP
1858 instruction if the cpu does not imp !! 2739 bool
1859 2740
1860 config AS_HAS_LSE_ATOMICS !! 2741 config NR_CPUS_DEFAULT_4
1861 def_bool $(as-instr,.arch_extension l !! 2742 bool
1862 2743
1863 config ARM64_LSE_ATOMICS !! 2744 config NR_CPUS_DEFAULT_8
1864 bool 2745 bool
1865 default ARM64_USE_LSE_ATOMICS <<
1866 depends on AS_HAS_LSE_ATOMICS <<
1867 2746
1868 config ARM64_USE_LSE_ATOMICS !! 2747 config NR_CPUS_DEFAULT_16
1869 bool "Atomic instructions" !! 2748 bool
1870 default y <<
1871 help <<
1872 As part of the Large System Extensi <<
1873 atomic instructions that are design <<
1874 very large systems. <<
1875 2749
1876 Say Y here to make use of these ins !! 2750 config NR_CPUS_DEFAULT_32
1877 atomic routines. This incurs a smal !! 2751 bool
1878 not support these instructions and <<
1879 built with binutils >= 2.25 in orde <<
1880 to be used. <<
1881 2752
1882 endmenu # "ARMv8.1 architectural features" !! 2753 config NR_CPUS_DEFAULT_64
>> 2754 bool
1883 2755
1884 menu "ARMv8.2 architectural features" !! 2756 config NR_CPUS
>> 2757 int "Maximum number of CPUs (2-256)"
>> 2758 range 2 256
>> 2759 depends on SMP
>> 2760 default "4" if NR_CPUS_DEFAULT_4
>> 2761 default "8" if NR_CPUS_DEFAULT_8
>> 2762 default "16" if NR_CPUS_DEFAULT_16
>> 2763 default "32" if NR_CPUS_DEFAULT_32
>> 2764 default "64" if NR_CPUS_DEFAULT_64
>> 2765 help
>> 2766 This allows you to specify the maximum number of CPUs which this
>> 2767 kernel will support. The maximum supported value is 32 for 32-bit
>> 2768 kernel and 64 for 64-bit kernels; the minimum value which makes
>> 2769 sense is 1 for Qemu (useful only for kernel debugging purposes)
>> 2770 and 2 for all others.
>> 2771
>> 2772 This is purely to save memory - each supported CPU adds
>> 2773 approximately eight kilobytes to the kernel image. For best
>> 2774 performance should round up your number of processors to the next
>> 2775 power of two.
1885 2776
1886 config AS_HAS_ARMV8_2 !! 2777 config MIPS_PERF_SHARED_TC_COUNTERS
1887 def_bool $(cc-option,-Wa$(comma)-marc !! 2778 bool
1888 2779
1889 config AS_HAS_SHA3 !! 2780 config MIPS_NR_CPU_NR_MAP_1024
1890 def_bool $(as-instr,.arch armv8.2-a+s !! 2781 bool
1891 2782
1892 config ARM64_PMEM !! 2783 config MIPS_NR_CPU_NR_MAP
1893 bool "Enable support for persistent m !! 2784 int
1894 select ARCH_HAS_PMEM_API !! 2785 depends on SMP
1895 select ARCH_HAS_UACCESS_FLUSHCACHE !! 2786 default 1024 if MIPS_NR_CPU_NR_MAP_1024
1896 help !! 2787 default NR_CPUS if !MIPS_NR_CPU_NR_MAP_1024
1897 Say Y to enable support for the per <<
1898 ARMv8.2 DCPoP feature. <<
1899 2788
1900 The feature is detected at runtime, !! 2789 #
1901 operations if DC CVAP is not suppor !! 2790 # Timer Interrupt Frequency Configuration
1902 DC CVAP itself if the system does n !! 2791 #
1903 2792
1904 config ARM64_RAS_EXTN !! 2793 choice
1905 bool "Enable support for RAS CPU Exte !! 2794 prompt "Timer frequency"
1906 default y !! 2795 default HZ_250
1907 help 2796 help
1908 CPUs that support the Reliability, !! 2797 Allows the configuration of the timer frequency.
1909 (RAS) Extensions, part of ARMv8.2 a <<
1910 errors, classify them and report th <<
1911 <<
1912 On CPUs with these extensions syste <<
1913 barriers to determine if faults are <<
1914 classification from a new set of re <<
1915 <<
1916 Selecting this feature will allow t <<
1917 and access the new registers if the <<
1918 Platform RAS features may additiona <<
1919 2798
1920 config ARM64_CNP !! 2799 config HZ_24
1921 bool "Enable support for Common Not P !! 2800 bool "24 HZ" if SYS_SUPPORTS_24HZ || SYS_SUPPORTS_ARBIT_HZ
1922 default y <<
1923 depends on ARM64_PAN || !ARM64_SW_TTB <<
1924 help <<
1925 Common Not Private (CNP) allows tra <<
1926 be shared between different PEs in <<
1927 domain, so the hardware can use thi <<
1928 caching of such entries in the TLB. <<
1929 2801
1930 Selecting this option allows the CN !! 2802 config HZ_48
1931 at runtime, and does not affect PEs !! 2803 bool "48 HZ" if SYS_SUPPORTS_48HZ || SYS_SUPPORTS_ARBIT_HZ
1932 this feature. <<
1933 2804
1934 endmenu # "ARMv8.2 architectural features" !! 2805 config HZ_100
>> 2806 bool "100 HZ" if SYS_SUPPORTS_100HZ || SYS_SUPPORTS_ARBIT_HZ
1935 2807
1936 menu "ARMv8.3 architectural features" !! 2808 config HZ_128
>> 2809 bool "128 HZ" if SYS_SUPPORTS_128HZ || SYS_SUPPORTS_ARBIT_HZ
1937 2810
1938 config ARM64_PTR_AUTH !! 2811 config HZ_250
1939 bool "Enable support for pointer auth !! 2812 bool "250 HZ" if SYS_SUPPORTS_250HZ || SYS_SUPPORTS_ARBIT_HZ
1940 default y <<
1941 help <<
1942 Pointer authentication (part of the <<
1943 instructions for signing and authen <<
1944 keys, which can be used to mitigate <<
1945 and other attacks. <<
1946 <<
1947 This option enables these instructi <<
1948 Choosing this option will cause the <<
1949 for each process at exec() time, wi <<
1950 context-switched along with the pro <<
1951 <<
1952 The feature is detected at runtime. <<
1953 hardware it will not be advertised <<
1954 be enabled. <<
1955 <<
1956 If the feature is present on the bo <<
1957 the late CPU will be parked. Also, <<
1958 address auth and the late CPU has t <<
1959 but with the feature disabled. On s <<
1960 not be selected. <<
1961 2813
1962 config ARM64_PTR_AUTH_KERNEL !! 2814 config HZ_256
1963 bool "Use pointer authentication for !! 2815 bool "256 HZ" if SYS_SUPPORTS_256HZ || SYS_SUPPORTS_ARBIT_HZ
1964 default y <<
1965 depends on ARM64_PTR_AUTH <<
1966 depends on (CC_HAS_SIGN_RETURN_ADDRES <<
1967 # Modern compilers insert a .note.gnu <<
1968 # which is only understood by binutil <<
1969 depends on LD_IS_LLD || LD_VERSION >= <<
1970 depends on !CC_IS_CLANG || AS_HAS_CFI <<
1971 depends on (!FUNCTION_GRAPH_TRACER || <<
1972 help <<
1973 If the compiler supports the -mbran <<
1974 -msign-return-address flag (e.g. GC <<
1975 will cause the kernel itself to be <<
1976 protection. In this case, and if th <<
1977 support pointer authentication, the <<
1978 disabled with minimal loss of prote <<
1979 <<
1980 This feature works with FUNCTION_GR <<
1981 DYNAMIC_FTRACE_WITH_ARGS is enabled <<
1982 <<
1983 config CC_HAS_BRANCH_PROT_PAC_RET <<
1984 # GCC 9 or later, clang 8 or later <<
1985 def_bool $(cc-option,-mbranch-protect <<
1986 <<
1987 config CC_HAS_SIGN_RETURN_ADDRESS <<
1988 # GCC 7, 8 <<
1989 def_bool $(cc-option,-msign-return-ad <<
1990 <<
1991 config AS_HAS_ARMV8_3 <<
1992 def_bool $(cc-option,-Wa$(comma)-marc <<
1993 <<
1994 config AS_HAS_CFI_NEGATE_RA_STATE <<
1995 def_bool $(as-instr,.cfi_startproc\n. <<
1996 <<
1997 config AS_HAS_LDAPR <<
1998 def_bool $(as-instr,.arch_extension r <<
1999 2816
2000 endmenu # "ARMv8.3 architectural features" !! 2817 config HZ_1000
>> 2818 bool "1000 HZ" if SYS_SUPPORTS_1000HZ || SYS_SUPPORTS_ARBIT_HZ
2001 2819
2002 menu "ARMv8.4 architectural features" !! 2820 config HZ_1024
>> 2821 bool "1024 HZ" if SYS_SUPPORTS_1024HZ || SYS_SUPPORTS_ARBIT_HZ
2003 2822
2004 config ARM64_AMU_EXTN !! 2823 endchoice
2005 bool "Enable support for the Activity <<
2006 default y <<
2007 help <<
2008 The activity monitors extension is <<
2009 by the ARMv8.4 CPU architecture. Th <<
2010 of the activity monitors architectu <<
2011 <<
2012 To enable the use of this extension <<
2013 <<
2014 Note that for architectural reasons <<
2015 support when running on CPUs that p <<
2016 extension. The required support is <<
2017 * Version 1.5 and later of the AR <<
2018 <<
2019 For kernels that have this configur <<
2020 firmware, you may need to say N her <<
2021 Otherwise you may experience firmwa <<
2022 accessing the counter registers. Ev <<
2023 symptoms, the values returned by th <<
2024 correctly reflect reality. Most com <<
2025 indicating that the counter is not <<
2026 2824
2027 config AS_HAS_ARMV8_4 !! 2825 config SYS_SUPPORTS_24HZ
2028 def_bool $(cc-option,-Wa$(comma)-marc !! 2826 bool
2029 2827
2030 config ARM64_TLB_RANGE !! 2828 config SYS_SUPPORTS_48HZ
2031 bool "Enable support for tlbi range f !! 2829 bool
2032 default y <<
2033 depends on AS_HAS_ARMV8_4 <<
2034 help <<
2035 ARMv8.4-TLBI provides TLBI invalida <<
2036 range of input addresses. <<
2037 2830
2038 The feature introduces new assembly !! 2831 config SYS_SUPPORTS_100HZ
2039 support when binutils >= 2.30. !! 2832 bool
2040 2833
2041 endmenu # "ARMv8.4 architectural features" !! 2834 config SYS_SUPPORTS_128HZ
>> 2835 bool
2042 2836
2043 menu "ARMv8.5 architectural features" !! 2837 config SYS_SUPPORTS_250HZ
>> 2838 bool
2044 2839
2045 config AS_HAS_ARMV8_5 !! 2840 config SYS_SUPPORTS_256HZ
2046 def_bool $(cc-option,-Wa$(comma)-marc !! 2841 bool
2047 2842
2048 config ARM64_BTI !! 2843 config SYS_SUPPORTS_1000HZ
2049 bool "Branch Target Identification su !! 2844 bool
2050 default y <<
2051 help <<
2052 Branch Target Identification (part <<
2053 provides a mechanism to limit the s <<
2054 branch instructions such as BR or B <<
2055 <<
2056 To make use of BTI on CPUs that sup <<
2057 <<
2058 BTI is intended to provide compleme <<
2059 flow integrity protection mechanism <<
2060 authentication mechanism provided a <<
2061 For this reason, it does not make s <<
2062 also enabling support for pointer a <<
2063 enabling this option you should als <<
2064 <<
2065 Userspace binaries must also be spe <<
2066 this mechanism. If you say N here <<
2067 BTI, such binaries can still run, b <<
2068 enforcement of branch destinations. <<
2069 2845
2070 config ARM64_BTI_KERNEL !! 2846 config SYS_SUPPORTS_1024HZ
2071 bool "Use Branch Target Identificatio !! 2847 bool
2072 default y <<
2073 depends on ARM64_BTI <<
2074 depends on ARM64_PTR_AUTH_KERNEL <<
2075 depends on CC_HAS_BRANCH_PROT_PAC_RET <<
2076 # https://gcc.gnu.org/bugzilla/show_b <<
2077 depends on !CC_IS_GCC || GCC_VERSION <<
2078 # https://gcc.gnu.org/bugzilla/show_b <<
2079 depends on !CC_IS_GCC <<
2080 depends on (!FUNCTION_GRAPH_TRACER || <<
2081 help <<
2082 Build the kernel with Branch Target <<
2083 and enable enforcement of this for <<
2084 is enabled and the system supports <<
2085 modular code must have BTI enabled. <<
2086 <<
2087 config CC_HAS_BRANCH_PROT_PAC_RET_BTI <<
2088 # GCC 9 or later, clang 8 or later <<
2089 def_bool $(cc-option,-mbranch-protect <<
2090 2848
2091 config ARM64_E0PD !! 2849 config SYS_SUPPORTS_ARBIT_HZ
2092 bool "Enable support for E0PD" !! 2850 bool
2093 default y !! 2851 default y if !SYS_SUPPORTS_24HZ && \
2094 help !! 2852 !SYS_SUPPORTS_48HZ && \
2095 E0PD (part of the ARMv8.5 extension !! 2853 !SYS_SUPPORTS_100HZ && \
2096 that EL0 accesses made via TTBR1 al !! 2854 !SYS_SUPPORTS_128HZ && \
2097 providing similar benefits to KASLR !! 2855 !SYS_SUPPORTS_250HZ && \
2098 with lower overhead and without dis !! 2856 !SYS_SUPPORTS_256HZ && \
2099 kernel memory such as SPE. !! 2857 !SYS_SUPPORTS_1000HZ && \
2100 !! 2858 !SYS_SUPPORTS_1024HZ
2101 This option enables E0PD for TTBR1 <<
2102 <<
2103 config ARM64_AS_HAS_MTE <<
2104 # Initial support for MTE went in bin <<
2105 # ".arch armv8.5-a+memtag" below. How <<
2106 # as a late addition to the final arc <<
2107 # is only supported in the newer 2.32 <<
2108 # versions, hence the extra "stgm" in <<
2109 def_bool $(as-instr,.arch armv8.5-a+m <<
2110 2859
2111 config ARM64_MTE !! 2860 config HZ
2112 bool "Memory Tagging Extension suppor !! 2861 int
2113 default y !! 2862 default 24 if HZ_24
2114 depends on ARM64_AS_HAS_MTE && ARM64_ !! 2863 default 48 if HZ_48
2115 depends on AS_HAS_ARMV8_5 !! 2864 default 100 if HZ_100
2116 depends on AS_HAS_LSE_ATOMICS !! 2865 default 128 if HZ_128
2117 # Required for tag checking in the ua !! 2866 default 250 if HZ_250
2118 depends on ARM64_PAN !! 2867 default 256 if HZ_256
2119 select ARCH_HAS_SUBPAGE_FAULTS !! 2868 default 1000 if HZ_1000
2120 select ARCH_USES_HIGH_VMA_FLAGS !! 2869 default 1024 if HZ_1024
2121 select ARCH_USES_PG_ARCH_2 <<
2122 select ARCH_USES_PG_ARCH_3 <<
2123 help <<
2124 Memory Tagging (part of the ARMv8.5 <<
2125 architectural support for run-time, <<
2126 various classes of memory error to <<
2127 to eliminate vulnerabilities arisin <<
2128 languages. <<
2129 <<
2130 This option enables the support for <<
2131 Extension at EL0 (i.e. for userspac <<
2132 <<
2133 Selecting this option allows the fe <<
2134 runtime. Any secondary CPU not impl <<
2135 not be allowed a late bring-up. <<
2136 <<
2137 Userspace binaries that want to use <<
2138 explicitly opt in. The mechanism fo <<
2139 described in: <<
2140 2870
2141 Documentation/arch/arm64/memory-tag !! 2871 config SCHED_HRTICK
>> 2872 def_bool HIGH_RES_TIMERS
2142 2873
2143 endmenu # "ARMv8.5 architectural features" !! 2874 config ARCH_SUPPORTS_KEXEC
>> 2875 def_bool y
2144 2876
2145 menu "ARMv8.7 architectural features" !! 2877 config ARCH_SUPPORTS_CRASH_DUMP
>> 2878 def_bool y
2146 2879
2147 config ARM64_EPAN !! 2880 config PHYSICAL_START
2148 bool "Enable support for Enhanced Pri !! 2881 hex "Physical address where the kernel is loaded"
2149 default y !! 2882 default "0xffffffff84000000"
2150 depends on ARM64_PAN !! 2883 depends on CRASH_DUMP
2151 help !! 2884 help
2152 Enhanced Privileged Access Never (E !! 2885 This gives the CKSEG0 or KSEG0 address where the kernel is loaded.
2153 Access Never to be used with Execut !! 2886 If you plan to use kernel for capturing the crash dump change
>> 2887 this value to start of the reserved region (the "X" value as
>> 2888 specified in the "crashkernel=YM@XM" command line boot parameter
>> 2889 passed to the panic-ed kernel).
>> 2890
>> 2891 config MIPS_O32_FP64_SUPPORT
>> 2892 bool "Support for O32 binaries using 64-bit FP" if !CPU_MIPSR6
>> 2893 depends on 32BIT || MIPS32_O32
>> 2894 help
>> 2895 When this is enabled, the kernel will support use of 64-bit floating
>> 2896 point registers with binaries using the O32 ABI along with the
>> 2897 EF_MIPS_FP64 ELF header flag (typically built with -mfp64). On
>> 2898 32-bit MIPS systems this support is at the cost of increasing the
>> 2899 size and complexity of the compiled FPU emulator. Thus if you are
>> 2900 running a MIPS32 system and know that none of your userland binaries
>> 2901 will require 64-bit floating point, you may wish to reduce the size
>> 2902 of your kernel & potentially improve FP emulation performance by
>> 2903 saying N here.
>> 2904
>> 2905 Although binutils currently supports use of this flag the details
>> 2906 concerning its effect upon the O32 ABI in userland are still being
>> 2907 worked on. In order to avoid userland becoming dependent upon current
>> 2908 behaviour before the details have been finalised, this option should
>> 2909 be considered experimental and only enabled by those working upon
>> 2910 said details.
2154 2911
2155 The feature is detected at runtime, !! 2912 If unsure, say N.
2156 if the cpu does not implement the f <<
2157 endmenu # "ARMv8.7 architectural features" <<
2158 2913
2159 menu "ARMv8.9 architectural features" !! 2914 config USE_OF
>> 2915 bool
>> 2916 select OF
>> 2917 select OF_EARLY_FLATTREE
>> 2918 select IRQ_DOMAIN
2160 2919
2161 config ARM64_POE !! 2920 config UHI_BOOT
2162 prompt "Permission Overlay Extension" !! 2921 bool
2163 def_bool y <<
2164 select ARCH_USES_HIGH_VMA_FLAGS <<
2165 select ARCH_HAS_PKEYS <<
2166 help <<
2167 The Permission Overlay Extension is <<
2168 Protection Keys. Memory Protection <<
2169 enforcing page-based protections, b <<
2170 of the page tables when an applicat <<
2171 2922
2172 For details, see Documentation/core !! 2923 config BUILTIN_DTB
>> 2924 bool
2173 2925
2174 If unsure, say y. !! 2926 choice
>> 2927 prompt "Kernel appended dtb support" if USE_OF
>> 2928 default MIPS_NO_APPENDED_DTB
2175 2929
2176 config ARCH_PKEY_BITS !! 2930 config MIPS_NO_APPENDED_DTB
2177 int !! 2931 bool "None"
2178 default 3 !! 2932 help
>> 2933 Do not enable appended dtb support.
>> 2934
>> 2935 config MIPS_ELF_APPENDED_DTB
>> 2936 bool "vmlinux"
>> 2937 help
>> 2938 With this option, the boot code will look for a device tree binary
>> 2939 DTB) included in the vmlinux ELF section .appended_dtb. By default
>> 2940 it is empty and the DTB can be appended using binutils command
>> 2941 objcopy:
>> 2942
>> 2943 objcopy --update-section .appended_dtb=<filename>.dtb vmlinux
>> 2944
>> 2945 This is meant as a backward compatibility convenience for those
>> 2946 systems with a bootloader that can't be upgraded to accommodate
>> 2947 the documented boot protocol using a device tree.
>> 2948
>> 2949 config MIPS_RAW_APPENDED_DTB
>> 2950 bool "vmlinux.bin or vmlinuz.bin"
>> 2951 help
>> 2952 With this option, the boot code will look for a device tree binary
>> 2953 DTB) appended to raw vmlinux.bin or vmlinuz.bin.
>> 2954 (e.g. cat vmlinux.bin <filename>.dtb > vmlinux_w_dtb).
>> 2955
>> 2956 This is meant as a backward compatibility convenience for those
>> 2957 systems with a bootloader that can't be upgraded to accommodate
>> 2958 the documented boot protocol using a device tree.
>> 2959
>> 2960 Beware that there is very little in terms of protection against
>> 2961 this option being confused by leftover garbage in memory that might
>> 2962 look like a DTB header after a reboot if no actual DTB is appended
>> 2963 to vmlinux.bin. Do not leave this option active in a production kernel
>> 2964 if you don't intend to always append a DTB.
>> 2965 endchoice
>> 2966
>> 2967 choice
>> 2968 prompt "Kernel command line type" if !CMDLINE_OVERRIDE
>> 2969 default MIPS_CMDLINE_FROM_DTB if USE_OF && !ATH79 && !MACH_INGENIC && \
>> 2970 !MACH_LOONGSON64 && !MIPS_MALTA && \
>> 2971 !CAVIUM_OCTEON_SOC
>> 2972 default MIPS_CMDLINE_FROM_BOOTLOADER
>> 2973
>> 2974 config MIPS_CMDLINE_FROM_DTB
>> 2975 depends on USE_OF
>> 2976 bool "Dtb kernel arguments if available"
>> 2977
>> 2978 config MIPS_CMDLINE_DTB_EXTEND
>> 2979 depends on USE_OF
>> 2980 bool "Extend dtb kernel arguments with bootloader arguments"
>> 2981
>> 2982 config MIPS_CMDLINE_FROM_BOOTLOADER
>> 2983 bool "Bootloader kernel arguments if available"
>> 2984
>> 2985 config MIPS_CMDLINE_BUILTIN_EXTEND
>> 2986 depends on CMDLINE_BOOL
>> 2987 bool "Extend builtin kernel arguments with bootloader arguments"
>> 2988 endchoice
2179 2989
2180 endmenu # "ARMv8.9 architectural features" !! 2990 endmenu
2181 2991
2182 config ARM64_SVE !! 2992 config LOCKDEP_SUPPORT
2183 bool "ARM Scalable Vector Extension s !! 2993 bool
2184 default y 2994 default y
2185 help <<
2186 The Scalable Vector Extension (SVE) <<
2187 execution state which complements a <<
2188 of the base architecture to support <<
2189 additional vectorisation opportunit <<
2190 <<
2191 To enable use of this extension on <<
2192 <<
2193 On CPUs that support the SVE2 exten <<
2194 those too. <<
2195 <<
2196 Note that for architectural reasons <<
2197 support when running on SVE capable <<
2198 is present in: <<
2199 <<
2200 * version 1.5 and later of the AR <<
2201 * the AArch64 boot wrapper since <<
2202 ("bootwrapper: SVE: Enable SVE <<
2203 <<
2204 For other firmware implementations, <<
2205 or vendor. <<
2206 <<
2207 If you need the kernel to boot on S <<
2208 firmware, you may need to say N her <<
2209 fixed. Otherwise, you may experien <<
2210 booting the kernel. If unsure and <<
2211 symptoms, you should assume that it <<
2212 2995
2213 config ARM64_SME !! 2996 config STACKTRACE_SUPPORT
2214 bool "ARM Scalable Matrix Extension s !! 2997 bool
2215 default y 2998 default y
2216 depends on ARM64_SVE <<
2217 depends on BROKEN <<
2218 help <<
2219 The Scalable Matrix Extension (SME) <<
2220 execution state which utilises a su <<
2221 instruction set, together with the <<
2222 register state capable of holding t <<
2223 enable various matrix operations. <<
2224 <<
2225 config ARM64_PSEUDO_NMI <<
2226 bool "Support for NMI-like interrupts <<
2227 select ARM_GIC_V3 <<
2228 help <<
2229 Adds support for mimicking Non-Mask <<
2230 GIC interrupt priority. This suppor <<
2231 ARM GIC. <<
2232 <<
2233 This high priority configuration fo <<
2234 explicitly enabled by setting the k <<
2235 "irqchip.gicv3_pseudo_nmi" to 1. <<
2236 <<
2237 If unsure, say N <<
2238 <<
2239 if ARM64_PSEUDO_NMI <<
2240 config ARM64_DEBUG_PRIORITY_MASKING <<
2241 bool "Debug interrupt priority maskin <<
2242 help <<
2243 This adds runtime checks to functio <<
2244 interrupts when using priority mask <<
2245 the validity of ICC_PMR_EL1 when ca <<
2246 2999
2247 If unsure, say N !! 3000 config PGTABLE_LEVELS
2248 endif # ARM64_PSEUDO_NMI !! 3001 int
>> 3002 default 4 if PAGE_SIZE_4KB && MIPS_VA_BITS_48
>> 3003 default 3 if 64BIT && (!PAGE_SIZE_64KB || MIPS_VA_BITS_48)
>> 3004 default 2
2249 3005
2250 config RELOCATABLE !! 3006 config MIPS_AUTO_PFN_OFFSET
2251 bool "Build a relocatable kernel imag !! 3007 bool
2252 select ARCH_HAS_RELR <<
2253 default y <<
2254 help <<
2255 This builds the kernel as a Positio <<
2256 which retains all relocation metada <<
2257 kernel binary at runtime to a diffe <<
2258 address it was linked at. <<
2259 Since AArch64 uses the RELA relocat <<
2260 relocation pass at runtime even if <<
2261 same address it was linked at. <<
2262 3008
2263 config RANDOMIZE_BASE !! 3009 menu "Bus options (PCI, PCMCIA, EISA, ISA, TC)"
2264 bool "Randomize the address of the ke <<
2265 select RELOCATABLE <<
2266 help <<
2267 Randomizes the virtual address at w <<
2268 loaded, as a security feature that <<
2269 relying on knowledge of the locatio <<
2270 <<
2271 It is the bootloader's job to provi <<
2272 random u64 value in /chosen/kaslr-s <<
2273 <<
2274 When booting via the UEFI stub, it <<
2275 EFI_RNG_PROTOCOL implementation (if <<
2276 to the kernel proper. In addition, <<
2277 location of the kernel Image as wel <<
2278 3010
2279 If unsure, say N. !! 3011 config PCI_DRIVERS_GENERIC
>> 3012 select PCI_DOMAINS_GENERIC if PCI
>> 3013 bool
2280 3014
2281 config RANDOMIZE_MODULE_REGION_FULL !! 3015 config PCI_DRIVERS_LEGACY
2282 bool "Randomize the module region ove !! 3016 def_bool !PCI_DRIVERS_GENERIC
2283 depends on RANDOMIZE_BASE !! 3017 select NO_GENERIC_PCI_IOPORT_MAP
2284 default y !! 3018 select PCI_DOMAINS if PCI
2285 help <<
2286 Randomizes the location of the modu <<
2287 covering the core kernel. This way, <<
2288 to leak information about the locat <<
2289 but it does imply that function cal <<
2290 kernel will need to be resolved via <<
2291 <<
2292 When this option is not set, the mo <<
2293 a limited range that contains the [ <<
2294 core kernel, so branch relocations <<
2295 the region is exhausted. In this pa <<
2296 exhaustion, modules might be able t <<
2297 3019
2298 config CC_HAVE_STACKPROTECTOR_SYSREG !! 3020 #
2299 def_bool $(cc-option,-mstack-protecto !! 3021 # ISA support is now enabled via select. Too many systems still have the one
>> 3022 # or other ISA chip on the board that users don't know about so don't expect
>> 3023 # users to choose the right thing ...
>> 3024 #
>> 3025 config ISA
>> 3026 bool
2300 3027
2301 config STACKPROTECTOR_PER_TASK !! 3028 config TC
2302 def_bool y !! 3029 bool "TURBOchannel support"
2303 depends on STACKPROTECTOR && CC_HAVE_ !! 3030 depends on MACH_DECSTATION
>> 3031 help
>> 3032 TURBOchannel is a DEC (now Compaq (now HP)) bus for Alpha and MIPS
>> 3033 processors. TURBOchannel programming specifications are available
>> 3034 at:
>> 3035 <ftp://ftp.hp.com/pub/alphaserver/archive/triadd/>
>> 3036 and:
>> 3037 <http://www.computer-refuge.org/classiccmp/ftp.digital.com/pub/DEC/TriAdd/>
>> 3038 Linux driver support status is documented at:
>> 3039 <http://www.linux-mips.org/wiki/DECstation>
2304 3040
2305 config UNWIND_PATCH_PAC_INTO_SCS !! 3041 config MMU
2306 bool "Enable shadow call stack dynami !! 3042 bool
2307 # needs Clang with https://github.com <<
2308 depends on CC_IS_CLANG && CLANG_VERSI <<
2309 depends on ARM64_PTR_AUTH_KERNEL && C <<
2310 depends on SHADOW_CALL_STACK <<
2311 select UNWIND_TABLES <<
2312 select DYNAMIC_SCS <<
2313 <<
2314 config ARM64_CONTPTE <<
2315 bool "Contiguous PTE mappings for use <<
2316 depends on TRANSPARENT_HUGEPAGE <<
2317 default y 3043 default y
2318 help <<
2319 When enabled, user mappings are con <<
2320 bit, for any mappings that meet the <<
2321 This reduces TLB pressure and impro <<
2322 <<
2323 endmenu # "Kernel Features" <<
2324 <<
2325 menu "Boot options" <<
2326 <<
2327 config ARM64_ACPI_PARKING_PROTOCOL <<
2328 bool "Enable support for the ARM64 AC <<
2329 depends on ACPI <<
2330 help <<
2331 Enable support for the ARM64 ACPI p <<
2332 the kernel will not allow booting t <<
2333 protocol even if the corresponding <<
2334 MADT table. <<
2335 <<
2336 config CMDLINE <<
2337 string "Default kernel command string <<
2338 default "" <<
2339 help <<
2340 Provide a set of default command-li <<
2341 entering them here. As a minimum, y <<
2342 root device (e.g. root=/dev/nfs). <<
2343 3044
2344 choice !! 3045 config ARCH_MMAP_RND_BITS_MIN
2345 prompt "Kernel command line type" !! 3046 default 12 if 64BIT
2346 depends on CMDLINE != "" !! 3047 default 8
2347 default CMDLINE_FROM_BOOTLOADER <<
2348 help <<
2349 Choose how the kernel will handle t <<
2350 command line string. <<
2351 <<
2352 config CMDLINE_FROM_BOOTLOADER <<
2353 bool "Use bootloader kernel arguments <<
2354 help <<
2355 Uses the command-line options passe <<
2356 the boot loader doesn't provide any <<
2357 string provided in CMDLINE will be <<
2358 <<
2359 config CMDLINE_FORCE <<
2360 bool "Always use the default kernel c <<
2361 help <<
2362 Always use the default kernel comma <<
2363 loader passes other arguments to th <<
2364 This is useful if you cannot or don <<
2365 command-line options your boot load <<
2366 3048
2367 endchoice !! 3049 config ARCH_MMAP_RND_BITS_MAX
>> 3050 default 18 if 64BIT
>> 3051 default 15
>> 3052
>> 3053 config ARCH_MMAP_RND_COMPAT_BITS_MIN
>> 3054 default 8
2368 3055
2369 config EFI_STUB !! 3056 config ARCH_MMAP_RND_COMPAT_BITS_MAX
>> 3057 default 15
>> 3058
>> 3059 config I8253
2370 bool 3060 bool
>> 3061 select CLKSRC_I8253
>> 3062 select CLKEVT_I8253
>> 3063 select MIPS_EXTERNAL_TIMER
>> 3064 endmenu
2371 3065
2372 config EFI !! 3066 config TRAD_SIGNALS
2373 bool "UEFI runtime support" !! 3067 bool
2374 depends on OF && !CPU_BIG_ENDIAN <<
2375 depends on KERNEL_MODE_NEON <<
2376 select ARCH_SUPPORTS_ACPI <<
2377 select LIBFDT <<
2378 select UCS2_STRING <<
2379 select EFI_PARAMS_FROM_FDT <<
2380 select EFI_RUNTIME_WRAPPERS <<
2381 select EFI_STUB <<
2382 select EFI_GENERIC_STUB <<
2383 imply IMA_SECURE_AND_OR_TRUSTED_BOOT <<
2384 default y <<
2385 help <<
2386 This option provides support for ru <<
2387 by UEFI firmware (such as non-volat <<
2388 clock, and platform reset). A UEFI <<
2389 allow the kernel to be booted as an <<
2390 is only useful on systems that have <<
2391 <<
2392 config COMPRESSED_INSTALL <<
2393 bool "Install compressed image by def <<
2394 help <<
2395 This makes the regular "make instal <<
2396 image we built, not the legacy unco <<
2397 <<
2398 You can check that a compressed ima <<
2399 "make zinstall" first, and verifyin <<
2400 in your environment before making " <<
2401 you. <<
2402 3068
2403 config DMI !! 3069 config MIPS32_COMPAT
2404 bool "Enable support for SMBIOS (DMI) !! 3070 bool
2405 depends on EFI <<
2406 default y <<
2407 help <<
2408 This enables SMBIOS/DMI feature for <<
2409 3071
2410 This option is only useful on syste !! 3072 config COMPAT
2411 However, even with this option, the !! 3073 bool
2412 continue to boot on existing non-UE <<
2413 3074
2414 endmenu # "Boot options" !! 3075 config MIPS32_O32
>> 3076 bool "Kernel support for o32 binaries"
>> 3077 depends on 64BIT
>> 3078 select ARCH_WANT_OLD_COMPAT_IPC
>> 3079 select COMPAT
>> 3080 select MIPS32_COMPAT
>> 3081 help
>> 3082 Select this option if you want to run o32 binaries. These are pure
>> 3083 32-bit binaries as used by the 32-bit Linux/MIPS port. Most of
>> 3084 existing binaries are in this format.
2415 3085
2416 menu "Power management options" !! 3086 If unsure, say Y.
2417 3087
2418 source "kernel/power/Kconfig" !! 3088 config MIPS32_N32
>> 3089 bool "Kernel support for n32 binaries"
>> 3090 depends on 64BIT
>> 3091 select ARCH_WANT_COMPAT_IPC_PARSE_VERSION
>> 3092 select COMPAT
>> 3093 select MIPS32_COMPAT
>> 3094 help
>> 3095 Select this option if you want to run n32 binaries. These are
>> 3096 64-bit binaries using 32-bit quantities for addressing and certain
>> 3097 data that would normally be 64-bit. They are used in special
>> 3098 cases.
2419 3099
2420 config ARCH_HIBERNATION_POSSIBLE !! 3100 If unsure, say N.
>> 3101
>> 3102 config CC_HAS_MNO_BRANCH_LIKELY
2421 def_bool y 3103 def_bool y
2422 depends on CPU_PM !! 3104 depends on $(cc-option,-mno-branch-likely)
2423 3105
2424 config ARCH_HIBERNATION_HEADER !! 3106 # https://github.com/llvm/llvm-project/issues/61045
>> 3107 config CC_HAS_BROKEN_INLINE_COMPAT_BRANCH
>> 3108 def_bool y if CC_IS_CLANG
>> 3109
>> 3110 menu "Power management options"
>> 3111
>> 3112 config ARCH_HIBERNATION_POSSIBLE
2425 def_bool y 3113 def_bool y
2426 depends on HIBERNATION !! 3114 depends on SYS_SUPPORTS_HOTPLUG_CPU || !SMP
2427 3115
2428 config ARCH_SUSPEND_POSSIBLE 3116 config ARCH_SUSPEND_POSSIBLE
2429 def_bool y 3117 def_bool y
>> 3118 depends on SYS_SUPPORTS_HOTPLUG_CPU || !SMP
2430 3119
2431 endmenu # "Power management options" !! 3120 source "kernel/power/Kconfig"
2432 3121
2433 menu "CPU Power Management" !! 3122 endmenu
2434 3123
2435 source "drivers/cpuidle/Kconfig" !! 3124 config MIPS_EXTERNAL_TIMER
>> 3125 bool
2436 3126
>> 3127 menu "CPU Power Management"
>> 3128
>> 3129 if CPU_SUPPORTS_CPUFREQ && MIPS_EXTERNAL_TIMER
2437 source "drivers/cpufreq/Kconfig" 3130 source "drivers/cpufreq/Kconfig"
>> 3131 endif # CPU_SUPPORTS_CPUFREQ && MIPS_EXTERNAL_TIMER
2438 3132
2439 endmenu # "CPU Power Management" !! 3133 source "drivers/cpuidle/Kconfig"
2440 3134
2441 source "drivers/acpi/Kconfig" !! 3135 endmenu
2442 3136
2443 source "arch/arm64/kvm/Kconfig" !! 3137 source "arch/mips/kvm/Kconfig"
2444 3138
>> 3139 source "arch/mips/vdso/Kconfig"
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