1 # SPDX-License-Identifier: GPL-2.0-only !! 1 # SPDX-License-Identifier: GPL-2.0
2 config ARM64 !! 2 config MIPS
3 def_bool y !! 3 bool
4 select ACPI_APMT if ACPI !! 4 default y
5 select ACPI_CCA_REQUIRED if ACPI !! 5 select ARCH_32BIT_OFF_T if !64BIT
6 select ACPI_GENERIC_GSI if ACPI !! 6 select ARCH_BINFMT_ELF_STATE if MIPS_FP_SUPPORT
7 select ACPI_GTDT if ACPI !! 7 select ARCH_HAS_CURRENT_STACK_POINTER if !CC_IS_CLANG || CLANG_VERSION >= 140000
8 select ACPI_HOTPLUG_CPU if ACPI_PROCES !! 8 select ARCH_HAS_DEBUG_VIRTUAL if !64BIT
9 select ACPI_IORT if ACPI <<
10 select ACPI_REDUCED_HARDWARE_ONLY if A <<
11 select ACPI_MCFG if (ACPI && PCI) <<
12 select ACPI_SPCR_TABLE if ACPI <<
13 select ACPI_PPTT if ACPI <<
14 select ARCH_HAS_DEBUG_WX <<
15 select ARCH_BINFMT_ELF_EXTRA_PHDRS <<
16 select ARCH_BINFMT_ELF_STATE <<
17 select ARCH_CORRECT_STACKTRACE_ON_KRET <<
18 select ARCH_ENABLE_HUGEPAGE_MIGRATION <<
19 select ARCH_ENABLE_MEMORY_HOTPLUG <<
20 select ARCH_ENABLE_MEMORY_HOTREMOVE <<
21 select ARCH_ENABLE_SPLIT_PMD_PTLOCK if <<
22 select ARCH_ENABLE_THP_MIGRATION if TR <<
23 select ARCH_HAS_CACHE_LINE_SIZE <<
24 select ARCH_HAS_CURRENT_STACK_POINTER <<
25 select ARCH_HAS_DEBUG_VIRTUAL <<
26 select ARCH_HAS_DEBUG_VM_PGTABLE <<
27 select ARCH_HAS_DMA_OPS if XEN <<
28 select ARCH_HAS_DMA_PREP_COHERENT <<
29 select ARCH_HAS_ACPI_TABLE_UPGRADE if <<
30 select ARCH_HAS_FAST_MULTIPLIER <<
31 select ARCH_HAS_FORTIFY_SOURCE 9 select ARCH_HAS_FORTIFY_SOURCE
32 select ARCH_HAS_GCOV_PROFILE_ALL <<
33 select ARCH_HAS_GIGANTIC_PAGE <<
34 select ARCH_HAS_KCOV 10 select ARCH_HAS_KCOV
35 select ARCH_HAS_KERNEL_FPU_SUPPORT if !! 11 select ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE if !EVA
36 select ARCH_HAS_KEEPINITRD !! 12 select ARCH_HAS_PTE_SPECIAL if !(32BIT && CPU_HAS_RIXI)
37 select ARCH_HAS_MEMBARRIER_SYNC_CORE !! 13 select ARCH_HAS_STRNCPY_FROM_USER
38 select ARCH_HAS_MEM_ENCRYPT !! 14 select ARCH_HAS_STRNLEN_USER
39 select ARCH_HAS_NMI_SAFE_THIS_CPU_OPS <<
40 select ARCH_HAS_NON_OVERLAPPING_ADDRES <<
41 select ARCH_HAS_PTE_DEVMAP <<
42 select ARCH_HAS_PTE_SPECIAL <<
43 select ARCH_HAS_HW_PTE_YOUNG <<
44 select ARCH_HAS_SETUP_DMA_OPS <<
45 select ARCH_HAS_SET_DIRECT_MAP <<
46 select ARCH_HAS_SET_MEMORY <<
47 select ARCH_STACKWALK <<
48 select ARCH_HAS_STRICT_KERNEL_RWX <<
49 select ARCH_HAS_STRICT_MODULE_RWX <<
50 select ARCH_HAS_SYNC_DMA_FOR_DEVICE <<
51 select ARCH_HAS_SYNC_DMA_FOR_CPU <<
52 select ARCH_HAS_SYSCALL_WRAPPER <<
53 select ARCH_HAS_TICK_BROADCAST if GENE 15 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
54 select ARCH_HAS_ZONE_DMA_SET if EXPERT !! 16 select ARCH_HAS_UBSAN_SANITIZE_ALL
55 select ARCH_HAVE_ELF_PROT !! 17 select ARCH_HAS_GCOV_PROFILE_ALL
56 select ARCH_HAVE_NMI_SAFE_CMPXCHG <<
57 select ARCH_HAVE_TRACE_MMIO_ACCESS <<
58 select ARCH_INLINE_READ_LOCK if !PREEM <<
59 select ARCH_INLINE_READ_LOCK_BH if !PR <<
60 select ARCH_INLINE_READ_LOCK_IRQ if !P <<
61 select ARCH_INLINE_READ_LOCK_IRQSAVE i <<
62 select ARCH_INLINE_READ_UNLOCK if !PRE <<
63 select ARCH_INLINE_READ_UNLOCK_BH if ! <<
64 select ARCH_INLINE_READ_UNLOCK_IRQ if <<
65 select ARCH_INLINE_READ_UNLOCK_IRQREST <<
66 select ARCH_INLINE_WRITE_LOCK if !PREE <<
67 select ARCH_INLINE_WRITE_LOCK_BH if !P <<
68 select ARCH_INLINE_WRITE_LOCK_IRQ if ! <<
69 select ARCH_INLINE_WRITE_LOCK_IRQSAVE <<
70 select ARCH_INLINE_WRITE_UNLOCK if !PR <<
71 select ARCH_INLINE_WRITE_UNLOCK_BH if <<
72 select ARCH_INLINE_WRITE_UNLOCK_IRQ if <<
73 select ARCH_INLINE_WRITE_UNLOCK_IRQRES <<
74 select ARCH_INLINE_SPIN_TRYLOCK if !PR <<
75 select ARCH_INLINE_SPIN_TRYLOCK_BH if <<
76 select ARCH_INLINE_SPIN_LOCK if !PREEM <<
77 select ARCH_INLINE_SPIN_LOCK_BH if !PR <<
78 select ARCH_INLINE_SPIN_LOCK_IRQ if !P <<
79 select ARCH_INLINE_SPIN_LOCK_IRQSAVE i <<
80 select ARCH_INLINE_SPIN_UNLOCK if !PRE <<
81 select ARCH_INLINE_SPIN_UNLOCK_BH if ! <<
82 select ARCH_INLINE_SPIN_UNLOCK_IRQ if <<
83 select ARCH_INLINE_SPIN_UNLOCK_IRQREST <<
84 select ARCH_KEEP_MEMBLOCK 18 select ARCH_KEEP_MEMBLOCK
85 select ARCH_MHP_MEMMAP_ON_MEMORY_ENABL !! 19 select ARCH_SUPPORTS_UPROBES
86 select ARCH_USE_CMPXCHG_LOCKREF !! 20 select ARCH_USE_BUILTIN_BSWAP
87 select ARCH_USE_GNU_PROPERTY !! 21 select ARCH_USE_CMPXCHG_LOCKREF if 64BIT
88 select ARCH_USE_MEMTEST 22 select ARCH_USE_MEMTEST
89 select ARCH_USE_QUEUED_RWLOCKS 23 select ARCH_USE_QUEUED_RWLOCKS
90 select ARCH_USE_QUEUED_SPINLOCKS 24 select ARCH_USE_QUEUED_SPINLOCKS
91 select ARCH_USE_SYM_ANNOTATIONS !! 25 select ARCH_SUPPORTS_HUGETLBFS if CPU_SUPPORTS_HUGEPAGES
92 select ARCH_SUPPORTS_DEBUG_PAGEALLOC !! 26 select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT if MMU
93 select ARCH_SUPPORTS_HUGETLBFS !! 27 select ARCH_WANT_IPC_PARSE_VERSION
94 select ARCH_SUPPORTS_MEMORY_FAILURE <<
95 select ARCH_SUPPORTS_SHADOW_CALL_STACK <<
96 select ARCH_SUPPORTS_LTO_CLANG if CPU_ <<
97 select ARCH_SUPPORTS_LTO_CLANG_THIN <<
98 select ARCH_SUPPORTS_CFI_CLANG <<
99 select ARCH_SUPPORTS_ATOMIC_RMW <<
100 select ARCH_SUPPORTS_INT128 if CC_HAS_ <<
101 select ARCH_SUPPORTS_NUMA_BALANCING <<
102 select ARCH_SUPPORTS_PAGE_TABLE_CHECK <<
103 select ARCH_SUPPORTS_PER_VMA_LOCK <<
104 select ARCH_SUPPORTS_HUGE_PFNMAP if TR <<
105 select ARCH_SUPPORTS_RT <<
106 select ARCH_WANT_BATCHED_UNMAP_TLB_FLU <<
107 select ARCH_WANT_COMPAT_IPC_PARSE_VERS <<
108 select ARCH_WANT_DEFAULT_BPF_JIT <<
109 select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_ <<
110 select ARCH_WANT_FRAME_POINTERS <<
111 select ARCH_WANT_HUGE_PMD_SHARE if ARM <<
112 select ARCH_WANT_LD_ORPHAN_WARN 28 select ARCH_WANT_LD_ORPHAN_WARN
113 select ARCH_WANTS_EXECMEM_LATE if EXEC <<
114 select ARCH_WANTS_NO_INSTR <<
115 select ARCH_WANTS_THP_SWAP if ARM64_4K <<
116 select ARCH_HAS_UBSAN <<
117 select ARM_AMBA <<
118 select ARM_ARCH_TIMER <<
119 select ARM_GIC <<
120 select AUDIT_ARCH_COMPAT_GENERIC <<
121 select ARM_GIC_V2M if PCI <<
122 select ARM_GIC_V3 <<
123 select ARM_GIC_V3_ITS if PCI <<
124 select ARM_PSCI_FW <<
125 select BUILDTIME_TABLE_SORT 29 select BUILDTIME_TABLE_SORT
126 select CLONE_BACKWARDS 30 select CLONE_BACKWARDS
127 select COMMON_CLK !! 31 select CPU_NO_EFFICIENT_FFS if (TARGET_ISA_REV < 1)
128 select CPU_PM if (SUSPEND || CPU_IDLE) !! 32 select CPU_PM if CPU_IDLE
129 select CPUMASK_OFFSTACK if NR_CPUS > 2 !! 33 select GENERIC_ATOMIC64 if !64BIT
130 select CRC32 !! 34 select GENERIC_CMOS_UPDATE
131 select DCACHE_WORD_ACCESS <<
132 select DYNAMIC_FTRACE if FUNCTION_TRAC <<
133 select DMA_BOUNCE_UNALIGNED_KMALLOC <<
134 select DMA_DIRECT_REMAP <<
135 select EDAC_SUPPORT <<
136 select FRAME_POINTER <<
137 select FUNCTION_ALIGNMENT_4B <<
138 select FUNCTION_ALIGNMENT_8B if DYNAMI <<
139 select GENERIC_ALLOCATOR <<
140 select GENERIC_ARCH_TOPOLOGY <<
141 select GENERIC_CLOCKEVENTS_BROADCAST <<
142 select GENERIC_CPU_AUTOPROBE 35 select GENERIC_CPU_AUTOPROBE
143 select GENERIC_CPU_DEVICES !! 36 select GENERIC_GETTIMEOFDAY
144 select GENERIC_CPU_VULNERABILITIES !! 37 select GENERIC_IOMAP
145 select GENERIC_EARLY_IOREMAP <<
146 select GENERIC_IDLE_POLL_SETUP <<
147 select GENERIC_IOREMAP <<
148 select GENERIC_IRQ_IPI <<
149 select GENERIC_IRQ_PROBE 38 select GENERIC_IRQ_PROBE
150 select GENERIC_IRQ_SHOW 39 select GENERIC_IRQ_SHOW
151 select GENERIC_IRQ_SHOW_LEVEL !! 40 select GENERIC_ISA_DMA if EISA
152 select GENERIC_LIB_DEVMEM_IS_ALLOWED !! 41 select GENERIC_LIB_ASHLDI3
153 select GENERIC_PCI_IOMAP !! 42 select GENERIC_LIB_ASHRDI3
154 select GENERIC_PTDUMP !! 43 select GENERIC_LIB_CMPDI2
155 select GENERIC_SCHED_CLOCK !! 44 select GENERIC_LIB_LSHRDI3
>> 45 select GENERIC_LIB_UCMPDI2
>> 46 select GENERIC_SCHED_CLOCK if !CAVIUM_OCTEON_SOC
156 select GENERIC_SMP_IDLE_THREAD 47 select GENERIC_SMP_IDLE_THREAD
157 select GENERIC_TIME_VSYSCALL 48 select GENERIC_TIME_VSYSCALL
158 select GENERIC_GETTIMEOFDAY !! 49 select GUP_GET_PXX_LOW_HIGH if CPU_MIPS32 && PHYS_ADDR_T_64BIT
159 select GENERIC_VDSO_TIME_NS <<
160 select HARDIRQS_SW_RESEND <<
161 select HAS_IOPORT <<
162 select HAVE_MOVE_PMD <<
163 select HAVE_MOVE_PUD <<
164 select HAVE_PCI <<
165 select HAVE_ACPI_APEI if (ACPI && EFI) <<
166 select HAVE_ALIGNED_STRUCT_PAGE <<
167 select HAVE_ARCH_AUDITSYSCALL <<
168 select HAVE_ARCH_BITREVERSE <<
169 select HAVE_ARCH_COMPILER_H 50 select HAVE_ARCH_COMPILER_H
170 select HAVE_ARCH_HUGE_VMALLOC <<
171 select HAVE_ARCH_HUGE_VMAP <<
172 select HAVE_ARCH_JUMP_LABEL 51 select HAVE_ARCH_JUMP_LABEL
173 select HAVE_ARCH_JUMP_LABEL_RELATIVE !! 52 select HAVE_ARCH_KGDB if MIPS_FP_SUPPORT
174 select HAVE_ARCH_KASAN !! 53 select HAVE_ARCH_MMAP_RND_BITS if MMU
175 select HAVE_ARCH_KASAN_VMALLOC !! 54 select HAVE_ARCH_MMAP_RND_COMPAT_BITS if MMU && COMPAT
176 select HAVE_ARCH_KASAN_SW_TAGS <<
177 select HAVE_ARCH_KASAN_HW_TAGS if ARM6 <<
178 # Some instrumentation may be unsound, <<
179 select HAVE_ARCH_KCSAN if EXPERT <<
180 select HAVE_ARCH_KFENCE <<
181 select HAVE_ARCH_KGDB <<
182 select HAVE_ARCH_MMAP_RND_BITS <<
183 select HAVE_ARCH_MMAP_RND_COMPAT_BITS <<
184 select HAVE_ARCH_PREL32_RELOCATIONS <<
185 select HAVE_ARCH_RANDOMIZE_KSTACK_OFFS <<
186 select HAVE_ARCH_SECCOMP_FILTER 55 select HAVE_ARCH_SECCOMP_FILTER
187 select HAVE_ARCH_STACKLEAK <<
188 select HAVE_ARCH_THREAD_STRUCT_WHITELI <<
189 select HAVE_ARCH_TRACEHOOK 56 select HAVE_ARCH_TRACEHOOK
190 select HAVE_ARCH_TRANSPARENT_HUGEPAGE !! 57 select HAVE_ARCH_TRANSPARENT_HUGEPAGE if CPU_SUPPORTS_HUGEPAGES
191 select HAVE_ARCH_VMAP_STACK <<
192 select HAVE_ARM_SMCCC <<
193 select HAVE_ASM_MODVERSIONS 58 select HAVE_ASM_MODVERSIONS
194 select HAVE_EBPF_JIT <<
195 select HAVE_C_RECORDMCOUNT <<
196 select HAVE_CMPXCHG_DOUBLE <<
197 select HAVE_CMPXCHG_LOCAL <<
198 select HAVE_CONTEXT_TRACKING_USER 59 select HAVE_CONTEXT_TRACKING_USER
>> 60 select HAVE_TIF_NOHZ
>> 61 select HAVE_C_RECORDMCOUNT
199 select HAVE_DEBUG_KMEMLEAK 62 select HAVE_DEBUG_KMEMLEAK
>> 63 select HAVE_DEBUG_STACKOVERFLOW
200 select HAVE_DMA_CONTIGUOUS 64 select HAVE_DMA_CONTIGUOUS
201 select HAVE_DYNAMIC_FTRACE 65 select HAVE_DYNAMIC_FTRACE
202 select HAVE_DYNAMIC_FTRACE_WITH_ARGS \ !! 66 select HAVE_EBPF_JIT if !CPU_MICROMIPS && \
203 if (GCC_SUPPORTS_DYNAMIC_FTRAC !! 67 !CPU_DADDI_WORKAROUNDS && \
204 CLANG_SUPPORTS_DYNAMIC_FTR !! 68 !CPU_R4000_WORKAROUNDS && \
205 select HAVE_DYNAMIC_FTRACE_WITH_DIRECT !! 69 !CPU_R4400_WORKAROUNDS
206 if DYNAMIC_FTRACE_WITH_ARGS && !! 70 select HAVE_EXIT_THREAD
207 select HAVE_DYNAMIC_FTRACE_WITH_CALL_O !! 71 select HAVE_FAST_GUP
208 if (DYNAMIC_FTRACE_WITH_ARGS & <<
209 (CC_IS_CLANG || !CC_OPTIMI <<
210 select FTRACE_MCOUNT_USE_PATCHABLE_FUN <<
211 if DYNAMIC_FTRACE_WITH_ARGS <<
212 select HAVE_SAMPLE_FTRACE_DIRECT <<
213 select HAVE_SAMPLE_FTRACE_DIRECT_MULTI <<
214 select HAVE_EFFICIENT_UNALIGNED_ACCESS <<
215 select HAVE_GUP_FAST <<
216 select HAVE_FTRACE_MCOUNT_RECORD 72 select HAVE_FTRACE_MCOUNT_RECORD
217 select HAVE_FUNCTION_TRACER <<
218 select HAVE_FUNCTION_ERROR_INJECTION <<
219 select HAVE_FUNCTION_GRAPH_TRACER 73 select HAVE_FUNCTION_GRAPH_TRACER
220 select HAVE_FUNCTION_GRAPH_RETVAL !! 74 select HAVE_FUNCTION_TRACER
221 select HAVE_GCC_PLUGINS 75 select HAVE_GCC_PLUGINS
222 select HAVE_HARDLOCKUP_DETECTOR_PERF i !! 76 select HAVE_GENERIC_VDSO
223 HW_PERF_EVENTS && HAVE_PERF_EV <<
224 select HAVE_HW_BREAKPOINT if PERF_EVEN <<
225 select HAVE_IOREMAP_PROT 77 select HAVE_IOREMAP_PROT
>> 78 select HAVE_IRQ_EXIT_ON_IRQ_STACK
226 select HAVE_IRQ_TIME_ACCOUNTING 79 select HAVE_IRQ_TIME_ACCOUNTING
>> 80 select HAVE_KPROBES
>> 81 select HAVE_KRETPROBES
>> 82 select HAVE_LD_DEAD_CODE_DATA_ELIMINATION
227 select HAVE_MOD_ARCH_SPECIFIC 83 select HAVE_MOD_ARCH_SPECIFIC
228 select HAVE_NMI 84 select HAVE_NMI
>> 85 select HAVE_PATA_PLATFORM
229 select HAVE_PERF_EVENTS 86 select HAVE_PERF_EVENTS
230 select HAVE_PERF_EVENTS_NMI if ARM64_P <<
231 select HAVE_PERF_REGS 87 select HAVE_PERF_REGS
232 select HAVE_PERF_USER_STACK_DUMP 88 select HAVE_PERF_USER_STACK_DUMP
233 select HAVE_PREEMPT_DYNAMIC_KEY <<
234 select HAVE_REGS_AND_STACK_ACCESS_API 89 select HAVE_REGS_AND_STACK_ACCESS_API
235 select HAVE_POSIX_CPU_TIMERS_TASK_WORK <<
236 select HAVE_FUNCTION_ARG_ACCESS_API <<
237 select MMU_GATHER_RCU_TABLE_FREE <<
238 select HAVE_RSEQ 90 select HAVE_RSEQ
239 select HAVE_RUST if RUSTC_SUPPORTS_ARM !! 91 select HAVE_SPARSE_SYSCALL_NR
240 select HAVE_STACKPROTECTOR 92 select HAVE_STACKPROTECTOR
241 select HAVE_SYSCALL_TRACEPOINTS 93 select HAVE_SYSCALL_TRACEPOINTS
242 select HAVE_KPROBES !! 94 select HAVE_VIRT_CPU_ACCOUNTING_GEN if 64BIT || !SMP
243 select HAVE_KRETPROBES <<
244 select HAVE_GENERIC_VDSO <<
245 select HOTPLUG_CORE_SYNC_DEAD if HOTPL <<
246 select IRQ_DOMAIN <<
247 select IRQ_FORCED_THREADING 95 select IRQ_FORCED_THREADING
248 select KASAN_VMALLOC if KASAN !! 96 select ISA if EISA
249 select LOCK_MM_AND_FIND_VMA 97 select LOCK_MM_AND_FIND_VMA
250 select MODULES_USE_ELF_RELA !! 98 select MODULES_USE_ELF_REL if MODULES
251 select NEED_DMA_MAP_STATE !! 99 select MODULES_USE_ELF_RELA if MODULES && 64BIT
252 select NEED_SG_DMA_LENGTH !! 100 select PERF_USE_VMALLOC
253 select OF !! 101 select PCI_MSI_ARCH_FALLBACKS if PCI_MSI
254 select OF_EARLY_FLATTREE !! 102 select RTC_LIB
255 select PCI_DOMAINS_GENERIC if PCI <<
256 select PCI_ECAM if (ACPI && PCI) <<
257 select PCI_SYSCALL if PCI <<
258 select POWER_RESET <<
259 select POWER_SUPPLY <<
260 select SPARSE_IRQ <<
261 select SWIOTLB <<
262 select SYSCTL_EXCEPTION_TRACE 103 select SYSCTL_EXCEPTION_TRACE
263 select THREAD_INFO_IN_TASK <<
264 select HAVE_ARCH_USERFAULTFD_MINOR if <<
265 select HAVE_ARCH_USERFAULTFD_WP if USE <<
266 select TRACE_IRQFLAGS_SUPPORT 104 select TRACE_IRQFLAGS_SUPPORT
267 select TRACE_IRQFLAGS_NMI_SUPPORT !! 105 select ARCH_HAS_ELFCORE_COMPAT
268 select HAVE_SOFTIRQ_ON_OWN_STACK !! 106 select HAVE_ARCH_KCSAN if 64BIT
269 select USER_STACKTRACE_SUPPORT <<
270 select VDSO_GETRANDOM <<
271 help <<
272 ARM 64-bit (AArch64) Linux support. <<
273 107
274 config RUSTC_SUPPORTS_ARM64 !! 108 config MIPS_FIXUP_BIGPHYS_ADDR
275 def_bool y !! 109 bool
276 depends on CPU_LITTLE_ENDIAN <<
277 # Shadow call stack is only supported <<
278 # <<
279 # When using the UNWIND_PATCH_PAC_INTO <<
280 # required due to use of the -Zfixed-x <<
281 # <<
282 # Otherwise, rustc version 1.82+ is re <<
283 # -Zsanitizer=shadow-call-stack flag. <<
284 depends on !SHADOW_CALL_STACK || RUSTC <<
285 <<
286 config CLANG_SUPPORTS_DYNAMIC_FTRACE_WITH_ARGS <<
287 def_bool CC_IS_CLANG <<
288 # https://github.com/ClangBuiltLinux/l <<
289 depends on AS_IS_GNU || (AS_IS_LLVM && <<
290 <<
291 config GCC_SUPPORTS_DYNAMIC_FTRACE_WITH_ARGS <<
292 def_bool CC_IS_GCC <<
293 depends on $(cc-option,-fpatchable-fun <<
294 <<
295 config 64BIT <<
296 def_bool y <<
297 <<
298 config MMU <<
299 def_bool y <<
300 <<
301 config ARM64_CONT_PTE_SHIFT <<
302 int <<
303 default 5 if PAGE_SIZE_64KB <<
304 default 7 if PAGE_SIZE_16KB <<
305 default 4 <<
306 <<
307 config ARM64_CONT_PMD_SHIFT <<
308 int <<
309 default 5 if PAGE_SIZE_64KB <<
310 default 5 if PAGE_SIZE_16KB <<
311 default 4 <<
312 <<
313 config ARCH_MMAP_RND_BITS_MIN <<
314 default 14 if PAGE_SIZE_64KB <<
315 default 16 if PAGE_SIZE_16KB <<
316 default 18 <<
317 110
318 # max bits determined by the following formula !! 111 config MIPS_GENERIC
319 # VA_BITS - PAGE_SHIFT - 3 !! 112 bool
320 config ARCH_MMAP_RND_BITS_MAX <<
321 default 19 if ARM64_VA_BITS=36 <<
322 default 24 if ARM64_VA_BITS=39 <<
323 default 27 if ARM64_VA_BITS=42 <<
324 default 30 if ARM64_VA_BITS=47 <<
325 default 29 if ARM64_VA_BITS=48 && ARM6 <<
326 default 31 if ARM64_VA_BITS=48 && ARM6 <<
327 default 33 if ARM64_VA_BITS=48 <<
328 default 14 if ARM64_64K_PAGES <<
329 default 16 if ARM64_16K_PAGES <<
330 default 18 <<
331 113
332 config ARCH_MMAP_RND_COMPAT_BITS_MIN !! 114 config MACH_INGENIC
333 default 7 if ARM64_64K_PAGES !! 115 bool
334 default 9 if ARM64_16K_PAGES !! 116 select SYS_SUPPORTS_32BIT_KERNEL
335 default 11 !! 117 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 118 select SYS_SUPPORTS_ZBOOT
>> 119 select DMA_NONCOHERENT
>> 120 select ARCH_HAS_SYNC_DMA_FOR_CPU
>> 121 select IRQ_MIPS_CPU
>> 122 select PINCTRL
>> 123 select GPIOLIB
>> 124 select COMMON_CLK
>> 125 select GENERIC_IRQ_CHIP
>> 126 select BUILTIN_DTB if MIPS_NO_APPENDED_DTB
>> 127 select USE_OF
>> 128 select CPU_SUPPORTS_CPUFREQ
>> 129 select MIPS_EXTERNAL_TIMER
336 130
337 config ARCH_MMAP_RND_COMPAT_BITS_MAX !! 131 menu "Machine selection"
338 default 16 <<
339 132
340 config NO_IOPORT_MAP !! 133 choice
341 def_bool y if !PCI !! 134 prompt "System type"
>> 135 default MIPS_GENERIC_KERNEL
342 136
343 config STACKTRACE_SUPPORT !! 137 config MIPS_GENERIC_KERNEL
344 def_bool y !! 138 bool "Generic board-agnostic MIPS kernel"
>> 139 select ARCH_HAS_SETUP_DMA_OPS
>> 140 select MIPS_GENERIC
>> 141 select BOOT_RAW
>> 142 select BUILTIN_DTB
>> 143 select CEVT_R4K
>> 144 select CLKSRC_MIPS_GIC
>> 145 select COMMON_CLK
>> 146 select CPU_MIPSR2_IRQ_EI
>> 147 select CPU_MIPSR2_IRQ_VI
>> 148 select CSRC_R4K
>> 149 select DMA_NONCOHERENT
>> 150 select HAVE_PCI
>> 151 select IRQ_MIPS_CPU
>> 152 select MIPS_AUTO_PFN_OFFSET
>> 153 select MIPS_CPU_SCACHE
>> 154 select MIPS_GIC
>> 155 select MIPS_L1_CACHE_SHIFT_7
>> 156 select NO_EXCEPT_FILL
>> 157 select PCI_DRIVERS_GENERIC
>> 158 select SMP_UP if SMP
>> 159 select SWAP_IO_SPACE
>> 160 select SYS_HAS_CPU_MIPS32_R1
>> 161 select SYS_HAS_CPU_MIPS32_R2
>> 162 select SYS_HAS_CPU_MIPS32_R6
>> 163 select SYS_HAS_CPU_MIPS64_R1
>> 164 select SYS_HAS_CPU_MIPS64_R2
>> 165 select SYS_HAS_CPU_MIPS64_R6
>> 166 select SYS_SUPPORTS_32BIT_KERNEL
>> 167 select SYS_SUPPORTS_64BIT_KERNEL
>> 168 select SYS_SUPPORTS_BIG_ENDIAN
>> 169 select SYS_SUPPORTS_HIGHMEM
>> 170 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 171 select SYS_SUPPORTS_MICROMIPS
>> 172 select SYS_SUPPORTS_MIPS16
>> 173 select SYS_SUPPORTS_MIPS_CPS
>> 174 select SYS_SUPPORTS_MULTITHREADING
>> 175 select SYS_SUPPORTS_RELOCATABLE
>> 176 select SYS_SUPPORTS_SMARTMIPS
>> 177 select SYS_SUPPORTS_ZBOOT
>> 178 select UHI_BOOT
>> 179 select USB_EHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
>> 180 select USB_EHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 181 select USB_OHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
>> 182 select USB_OHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 183 select USB_UHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
>> 184 select USB_UHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 185 select USE_OF
>> 186 help
>> 187 Select this to build a kernel which aims to support multiple boards,
>> 188 generally using a flattened device tree passed from the bootloader
>> 189 using the boot protocol defined in the UHI (Unified Hosting
>> 190 Interface) specification.
>> 191
>> 192 config MIPS_ALCHEMY
>> 193 bool "Alchemy processor based machines"
>> 194 select PHYS_ADDR_T_64BIT
>> 195 select CEVT_R4K
>> 196 select CSRC_R4K
>> 197 select IRQ_MIPS_CPU
>> 198 select DMA_NONCOHERENT # Au1000,1500,1100 aren't, rest is
>> 199 select MIPS_FIXUP_BIGPHYS_ADDR if PCI
>> 200 select SYS_HAS_CPU_MIPS32_R1
>> 201 select SYS_SUPPORTS_32BIT_KERNEL
>> 202 select SYS_SUPPORTS_APM_EMULATION
>> 203 select GPIOLIB
>> 204 select SYS_SUPPORTS_ZBOOT
>> 205 select COMMON_CLK
345 206
346 config ILLEGAL_POINTER_VALUE !! 207 config AR7
347 hex !! 208 bool "Texas Instruments AR7"
348 default 0xdead000000000000 !! 209 select BOOT_ELF32
>> 210 select COMMON_CLK
>> 211 select DMA_NONCOHERENT
>> 212 select CEVT_R4K
>> 213 select CSRC_R4K
>> 214 select IRQ_MIPS_CPU
>> 215 select NO_EXCEPT_FILL
>> 216 select SWAP_IO_SPACE
>> 217 select SYS_HAS_CPU_MIPS32_R1
>> 218 select SYS_HAS_EARLY_PRINTK
>> 219 select SYS_SUPPORTS_32BIT_KERNEL
>> 220 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 221 select SYS_SUPPORTS_MIPS16
>> 222 select SYS_SUPPORTS_ZBOOT_UART16550
>> 223 select GPIOLIB
>> 224 select VLYNQ
>> 225 help
>> 226 Support for the Texas Instruments AR7 System-on-a-Chip
>> 227 family: TNETD7100, 7200 and 7300.
>> 228
>> 229 config ATH25
>> 230 bool "Atheros AR231x/AR531x SoC support"
>> 231 select CEVT_R4K
>> 232 select CSRC_R4K
>> 233 select DMA_NONCOHERENT
>> 234 select IRQ_MIPS_CPU
>> 235 select IRQ_DOMAIN
>> 236 select SYS_HAS_CPU_MIPS32_R1
>> 237 select SYS_SUPPORTS_BIG_ENDIAN
>> 238 select SYS_SUPPORTS_32BIT_KERNEL
>> 239 select SYS_HAS_EARLY_PRINTK
>> 240 help
>> 241 Support for Atheros AR231x and Atheros AR531x based boards
>> 242
>> 243 config ATH79
>> 244 bool "Atheros AR71XX/AR724X/AR913X based boards"
>> 245 select ARCH_HAS_RESET_CONTROLLER
>> 246 select BOOT_RAW
>> 247 select CEVT_R4K
>> 248 select CSRC_R4K
>> 249 select DMA_NONCOHERENT
>> 250 select GPIOLIB
>> 251 select PINCTRL
>> 252 select COMMON_CLK
>> 253 select IRQ_MIPS_CPU
>> 254 select SYS_HAS_CPU_MIPS32_R2
>> 255 select SYS_HAS_EARLY_PRINTK
>> 256 select SYS_SUPPORTS_32BIT_KERNEL
>> 257 select SYS_SUPPORTS_BIG_ENDIAN
>> 258 select SYS_SUPPORTS_MIPS16
>> 259 select SYS_SUPPORTS_ZBOOT_UART_PROM
>> 260 select USE_OF
>> 261 select USB_EHCI_ROOT_HUB_TT if USB_EHCI_HCD_PLATFORM
>> 262 help
>> 263 Support for the Atheros AR71XX/AR724X/AR913X SoCs.
>> 264
>> 265 config BMIPS_GENERIC
>> 266 bool "Broadcom Generic BMIPS kernel"
>> 267 select ARCH_HAS_RESET_CONTROLLER
>> 268 select ARCH_HAS_SYNC_DMA_FOR_CPU_ALL
>> 269 select BOOT_RAW
>> 270 select NO_EXCEPT_FILL
>> 271 select USE_OF
>> 272 select CEVT_R4K
>> 273 select CSRC_R4K
>> 274 select SYNC_R4K
>> 275 select COMMON_CLK
>> 276 select BCM6345_L1_IRQ
>> 277 select BCM7038_L1_IRQ
>> 278 select BCM7120_L2_IRQ
>> 279 select BRCMSTB_L2_IRQ
>> 280 select IRQ_MIPS_CPU
>> 281 select DMA_NONCOHERENT
>> 282 select SYS_SUPPORTS_32BIT_KERNEL
>> 283 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 284 select SYS_SUPPORTS_BIG_ENDIAN
>> 285 select SYS_SUPPORTS_HIGHMEM
>> 286 select SYS_HAS_CPU_BMIPS32_3300
>> 287 select SYS_HAS_CPU_BMIPS4350
>> 288 select SYS_HAS_CPU_BMIPS4380
>> 289 select SYS_HAS_CPU_BMIPS5000
>> 290 select SWAP_IO_SPACE
>> 291 select USB_EHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
>> 292 select USB_EHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 293 select USB_OHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
>> 294 select USB_OHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 295 select HARDIRQS_SW_RESEND
>> 296 select HAVE_PCI
>> 297 select PCI_DRIVERS_GENERIC
>> 298 select FW_CFE
>> 299 help
>> 300 Build a generic DT-based kernel image that boots on select
>> 301 BCM33xx cable modem chips, BCM63xx DSL chips, and BCM7xxx set-top
>> 302 box chips. Note that CONFIG_CPU_BIG_ENDIAN/CONFIG_CPU_LITTLE_ENDIAN
>> 303 must be set appropriately for your board.
>> 304
>> 305 config BCM47XX
>> 306 bool "Broadcom BCM47XX based boards"
>> 307 select BOOT_RAW
>> 308 select CEVT_R4K
>> 309 select CSRC_R4K
>> 310 select DMA_NONCOHERENT
>> 311 select HAVE_PCI
>> 312 select IRQ_MIPS_CPU
>> 313 select SYS_HAS_CPU_MIPS32_R1
>> 314 select NO_EXCEPT_FILL
>> 315 select SYS_SUPPORTS_32BIT_KERNEL
>> 316 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 317 select SYS_SUPPORTS_MIPS16
>> 318 select SYS_SUPPORTS_ZBOOT
>> 319 select SYS_HAS_EARLY_PRINTK
>> 320 select USE_GENERIC_EARLY_PRINTK_8250
>> 321 select GPIOLIB
>> 322 select LEDS_GPIO_REGISTER
>> 323 select BCM47XX_NVRAM
>> 324 select BCM47XX_SPROM
>> 325 select BCM47XX_SSB if !BCM47XX_BCMA
>> 326 help
>> 327 Support for BCM47XX based boards
>> 328
>> 329 config BCM63XX
>> 330 bool "Broadcom BCM63XX based boards"
>> 331 select BOOT_RAW
>> 332 select CEVT_R4K
>> 333 select CSRC_R4K
>> 334 select SYNC_R4K
>> 335 select DMA_NONCOHERENT
>> 336 select IRQ_MIPS_CPU
>> 337 select SYS_SUPPORTS_32BIT_KERNEL
>> 338 select SYS_SUPPORTS_BIG_ENDIAN
>> 339 select SYS_HAS_EARLY_PRINTK
>> 340 select SYS_HAS_CPU_BMIPS32_3300
>> 341 select SYS_HAS_CPU_BMIPS4350
>> 342 select SYS_HAS_CPU_BMIPS4380
>> 343 select SWAP_IO_SPACE
>> 344 select GPIOLIB
>> 345 select MIPS_L1_CACHE_SHIFT_4
>> 346 select HAVE_LEGACY_CLK
>> 347 help
>> 348 Support for BCM63XX based boards
>> 349
>> 350 config MIPS_COBALT
>> 351 bool "Cobalt Server"
>> 352 select CEVT_R4K
>> 353 select CSRC_R4K
>> 354 select CEVT_GT641XX
>> 355 select DMA_NONCOHERENT
>> 356 select FORCE_PCI
>> 357 select I8253
>> 358 select I8259
>> 359 select IRQ_MIPS_CPU
>> 360 select IRQ_GT641XX
>> 361 select PCI_GT64XXX_PCI0
>> 362 select SYS_HAS_CPU_NEVADA
>> 363 select SYS_HAS_EARLY_PRINTK
>> 364 select SYS_SUPPORTS_32BIT_KERNEL
>> 365 select SYS_SUPPORTS_64BIT_KERNEL
>> 366 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 367 select USE_GENERIC_EARLY_PRINTK_8250
>> 368
>> 369 config MACH_DECSTATION
>> 370 bool "DECstations"
>> 371 select BOOT_ELF32
>> 372 select CEVT_DS1287
>> 373 select CEVT_R4K if CPU_R4X00
>> 374 select CSRC_IOASIC
>> 375 select CSRC_R4K if CPU_R4X00
>> 376 select CPU_DADDI_WORKAROUNDS if 64BIT
>> 377 select CPU_R4000_WORKAROUNDS if 64BIT
>> 378 select CPU_R4400_WORKAROUNDS if 64BIT
>> 379 select DMA_NONCOHERENT
>> 380 select NO_IOPORT_MAP
>> 381 select IRQ_MIPS_CPU
>> 382 select SYS_HAS_CPU_R3000
>> 383 select SYS_HAS_CPU_R4X00
>> 384 select SYS_SUPPORTS_32BIT_KERNEL
>> 385 select SYS_SUPPORTS_64BIT_KERNEL
>> 386 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 387 select SYS_SUPPORTS_128HZ
>> 388 select SYS_SUPPORTS_256HZ
>> 389 select SYS_SUPPORTS_1024HZ
>> 390 select MIPS_L1_CACHE_SHIFT_4
>> 391 help
>> 392 This enables support for DEC's MIPS based workstations. For details
>> 393 see the Linux/MIPS FAQ on <http://www.linux-mips.org/> and the
>> 394 DECstation porting pages on <http://decstation.unix-ag.org/>.
>> 395
>> 396 If you have one of the following DECstation Models you definitely
>> 397 want to choose R4xx0 for the CPU Type:
>> 398
>> 399 DECstation 5000/50
>> 400 DECstation 5000/150
>> 401 DECstation 5000/260
>> 402 DECsystem 5900/260
>> 403
>> 404 otherwise choose R3000.
>> 405
>> 406 config MACH_JAZZ
>> 407 bool "Jazz family of machines"
>> 408 select ARC_MEMORY
>> 409 select ARC_PROMLIB
>> 410 select ARCH_MIGHT_HAVE_PC_PARPORT
>> 411 select ARCH_MIGHT_HAVE_PC_SERIO
>> 412 select DMA_OPS
>> 413 select FW_ARC
>> 414 select FW_ARC32
>> 415 select ARCH_MAY_HAVE_PC_FDC
>> 416 select CEVT_R4K
>> 417 select CSRC_R4K
>> 418 select DEFAULT_SGI_PARTITION if CPU_BIG_ENDIAN
>> 419 select GENERIC_ISA_DMA
>> 420 select HAVE_PCSPKR_PLATFORM
>> 421 select IRQ_MIPS_CPU
>> 422 select I8253
>> 423 select I8259
>> 424 select ISA
>> 425 select SYS_HAS_CPU_R4X00
>> 426 select SYS_SUPPORTS_32BIT_KERNEL
>> 427 select SYS_SUPPORTS_64BIT_KERNEL
>> 428 select SYS_SUPPORTS_100HZ
>> 429 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 430 help
>> 431 This a family of machines based on the MIPS R4030 chipset which was
>> 432 used by several vendors to build RISC/os and Windows NT workstations.
>> 433 Members include the Acer PICA, MIPS Magnum 4000, MIPS Millennium and
>> 434 Olivetti M700-10 workstations.
>> 435
>> 436 config MACH_INGENIC_SOC
>> 437 bool "Ingenic SoC based machines"
>> 438 select MIPS_GENERIC
>> 439 select MACH_INGENIC
>> 440 select SYS_SUPPORTS_ZBOOT_UART16550
>> 441 select CPU_SUPPORTS_CPUFREQ
>> 442 select MIPS_EXTERNAL_TIMER
>> 443
>> 444 config LANTIQ
>> 445 bool "Lantiq based platforms"
>> 446 select DMA_NONCOHERENT
>> 447 select IRQ_MIPS_CPU
>> 448 select CEVT_R4K
>> 449 select CSRC_R4K
>> 450 select NO_EXCEPT_FILL
>> 451 select SYS_HAS_CPU_MIPS32_R1
>> 452 select SYS_HAS_CPU_MIPS32_R2
>> 453 select SYS_SUPPORTS_BIG_ENDIAN
>> 454 select SYS_SUPPORTS_32BIT_KERNEL
>> 455 select SYS_SUPPORTS_MIPS16
>> 456 select SYS_SUPPORTS_MULTITHREADING
>> 457 select SYS_SUPPORTS_VPE_LOADER
>> 458 select SYS_HAS_EARLY_PRINTK
>> 459 select GPIOLIB
>> 460 select SWAP_IO_SPACE
>> 461 select BOOT_RAW
>> 462 select HAVE_LEGACY_CLK
>> 463 select USE_OF
>> 464 select PINCTRL
>> 465 select PINCTRL_LANTIQ
>> 466 select ARCH_HAS_RESET_CONTROLLER
>> 467 select RESET_CONTROLLER
>> 468
>> 469 config MACH_LOONGSON32
>> 470 bool "Loongson 32-bit family of machines"
>> 471 select SYS_SUPPORTS_ZBOOT
>> 472 help
>> 473 This enables support for the Loongson-1 family of machines.
>> 474
>> 475 Loongson-1 is a family of 32-bit MIPS-compatible SoCs developed by
>> 476 the Institute of Computing Technology (ICT), Chinese Academy of
>> 477 Sciences (CAS).
>> 478
>> 479 config MACH_LOONGSON2EF
>> 480 bool "Loongson-2E/F family of machines"
>> 481 select SYS_SUPPORTS_ZBOOT
>> 482 help
>> 483 This enables the support of early Loongson-2E/F family of machines.
>> 484
>> 485 config MACH_LOONGSON64
>> 486 bool "Loongson 64-bit family of machines"
>> 487 select ARCH_SPARSEMEM_ENABLE
>> 488 select ARCH_MIGHT_HAVE_PC_PARPORT
>> 489 select ARCH_MIGHT_HAVE_PC_SERIO
>> 490 select GENERIC_ISA_DMA_SUPPORT_BROKEN
>> 491 select BOOT_ELF32
>> 492 select BOARD_SCACHE
>> 493 select CSRC_R4K
>> 494 select CEVT_R4K
>> 495 select CPU_HAS_WB
>> 496 select FORCE_PCI
>> 497 select ISA
>> 498 select I8259
>> 499 select IRQ_MIPS_CPU
>> 500 select NO_EXCEPT_FILL
>> 501 select NR_CPUS_DEFAULT_64
>> 502 select USE_GENERIC_EARLY_PRINTK_8250
>> 503 select PCI_DRIVERS_GENERIC
>> 504 select SYS_HAS_CPU_LOONGSON64
>> 505 select SYS_HAS_EARLY_PRINTK
>> 506 select SYS_SUPPORTS_SMP
>> 507 select SYS_SUPPORTS_HOTPLUG_CPU
>> 508 select SYS_SUPPORTS_NUMA
>> 509 select SYS_SUPPORTS_64BIT_KERNEL
>> 510 select SYS_SUPPORTS_HIGHMEM
>> 511 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 512 select SYS_SUPPORTS_ZBOOT
>> 513 select SYS_SUPPORTS_RELOCATABLE
>> 514 select ZONE_DMA32
>> 515 select COMMON_CLK
>> 516 select USE_OF
>> 517 select BUILTIN_DTB
>> 518 select PCI_HOST_GENERIC
>> 519 select HAVE_ARCH_NODEDATA_EXTENSION if NUMA
>> 520 help
>> 521 This enables the support of Loongson-2/3 family of machines.
>> 522
>> 523 Loongson-2 and Loongson-3 are 64-bit general-purpose processors with
>> 524 GS264/GS464/GS464E/GS464V microarchitecture (except old Loongson-2E
>> 525 and Loongson-2F which will be removed), developed by the Institute
>> 526 of Computing Technology (ICT), Chinese Academy of Sciences (CAS).
>> 527
>> 528 config MIPS_MALTA
>> 529 bool "MIPS Malta board"
>> 530 select ARCH_MAY_HAVE_PC_FDC
>> 531 select ARCH_MIGHT_HAVE_PC_PARPORT
>> 532 select ARCH_MIGHT_HAVE_PC_SERIO
>> 533 select BOOT_ELF32
>> 534 select BOOT_RAW
>> 535 select BUILTIN_DTB
>> 536 select CEVT_R4K
>> 537 select CLKSRC_MIPS_GIC
>> 538 select COMMON_CLK
>> 539 select CSRC_R4K
>> 540 select DMA_NONCOHERENT
>> 541 select GENERIC_ISA_DMA
>> 542 select HAVE_PCSPKR_PLATFORM
>> 543 select HAVE_PCI
>> 544 select I8253
>> 545 select I8259
>> 546 select IRQ_MIPS_CPU
>> 547 select MIPS_BONITO64
>> 548 select MIPS_CPU_SCACHE
>> 549 select MIPS_GIC
>> 550 select MIPS_L1_CACHE_SHIFT_6
>> 551 select MIPS_MSC
>> 552 select PCI_GT64XXX_PCI0
>> 553 select SMP_UP if SMP
>> 554 select SWAP_IO_SPACE
>> 555 select SYS_HAS_CPU_MIPS32_R1
>> 556 select SYS_HAS_CPU_MIPS32_R2
>> 557 select SYS_HAS_CPU_MIPS32_R3_5
>> 558 select SYS_HAS_CPU_MIPS32_R5
>> 559 select SYS_HAS_CPU_MIPS32_R6
>> 560 select SYS_HAS_CPU_MIPS64_R1
>> 561 select SYS_HAS_CPU_MIPS64_R2
>> 562 select SYS_HAS_CPU_MIPS64_R6
>> 563 select SYS_HAS_CPU_NEVADA
>> 564 select SYS_HAS_CPU_RM7000
>> 565 select SYS_SUPPORTS_32BIT_KERNEL
>> 566 select SYS_SUPPORTS_64BIT_KERNEL
>> 567 select SYS_SUPPORTS_BIG_ENDIAN
>> 568 select SYS_SUPPORTS_HIGHMEM
>> 569 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 570 select SYS_SUPPORTS_MICROMIPS
>> 571 select SYS_SUPPORTS_MIPS16
>> 572 select SYS_SUPPORTS_MIPS_CMP
>> 573 select SYS_SUPPORTS_MIPS_CPS
>> 574 select SYS_SUPPORTS_MULTITHREADING
>> 575 select SYS_SUPPORTS_RELOCATABLE
>> 576 select SYS_SUPPORTS_SMARTMIPS
>> 577 select SYS_SUPPORTS_VPE_LOADER
>> 578 select SYS_SUPPORTS_ZBOOT
>> 579 select USE_OF
>> 580 select WAR_ICACHE_REFILLS
>> 581 select ZONE_DMA32 if 64BIT
>> 582 help
>> 583 This enables support for the MIPS Technologies Malta evaluation
>> 584 board.
>> 585
>> 586 config MACH_PIC32
>> 587 bool "Microchip PIC32 Family"
>> 588 help
>> 589 This enables support for the Microchip PIC32 family of platforms.
>> 590
>> 591 Microchip PIC32 is a family of general-purpose 32 bit MIPS core
>> 592 microcontrollers.
>> 593
>> 594 config MACH_NINTENDO64
>> 595 bool "Nintendo 64 console"
>> 596 select CEVT_R4K
>> 597 select CSRC_R4K
>> 598 select SYS_HAS_CPU_R4300
>> 599 select SYS_SUPPORTS_BIG_ENDIAN
>> 600 select SYS_SUPPORTS_ZBOOT
>> 601 select SYS_SUPPORTS_32BIT_KERNEL
>> 602 select SYS_SUPPORTS_64BIT_KERNEL
>> 603 select DMA_NONCOHERENT
>> 604 select IRQ_MIPS_CPU
>> 605
>> 606 config RALINK
>> 607 bool "Ralink based machines"
>> 608 select CEVT_R4K
>> 609 select COMMON_CLK
>> 610 select CSRC_R4K
>> 611 select BOOT_RAW
>> 612 select DMA_NONCOHERENT
>> 613 select IRQ_MIPS_CPU
>> 614 select USE_OF
>> 615 select SYS_HAS_CPU_MIPS32_R2
>> 616 select SYS_SUPPORTS_32BIT_KERNEL
>> 617 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 618 select SYS_SUPPORTS_MIPS16
>> 619 select SYS_SUPPORTS_ZBOOT
>> 620 select SYS_HAS_EARLY_PRINTK
>> 621 select ARCH_HAS_RESET_CONTROLLER
>> 622 select RESET_CONTROLLER
>> 623
>> 624 config MACH_REALTEK_RTL
>> 625 bool "Realtek RTL838x/RTL839x based machines"
>> 626 select MIPS_GENERIC
>> 627 select DMA_NONCOHERENT
>> 628 select IRQ_MIPS_CPU
>> 629 select CSRC_R4K
>> 630 select CEVT_R4K
>> 631 select SYS_HAS_CPU_MIPS32_R1
>> 632 select SYS_HAS_CPU_MIPS32_R2
>> 633 select SYS_SUPPORTS_BIG_ENDIAN
>> 634 select SYS_SUPPORTS_32BIT_KERNEL
>> 635 select SYS_SUPPORTS_MIPS16
>> 636 select SYS_SUPPORTS_MULTITHREADING
>> 637 select SYS_SUPPORTS_VPE_LOADER
>> 638 select BOOT_RAW
>> 639 select PINCTRL
>> 640 select USE_OF
>> 641
>> 642 config SGI_IP22
>> 643 bool "SGI IP22 (Indy/Indigo2)"
>> 644 select ARC_MEMORY
>> 645 select ARC_PROMLIB
>> 646 select FW_ARC
>> 647 select FW_ARC32
>> 648 select ARCH_MIGHT_HAVE_PC_SERIO
>> 649 select BOOT_ELF32
>> 650 select CEVT_R4K
>> 651 select CSRC_R4K
>> 652 select DEFAULT_SGI_PARTITION
>> 653 select DMA_NONCOHERENT
>> 654 select HAVE_EISA
>> 655 select I8253
>> 656 select I8259
>> 657 select IP22_CPU_SCACHE
>> 658 select IRQ_MIPS_CPU
>> 659 select GENERIC_ISA_DMA_SUPPORT_BROKEN
>> 660 select SGI_HAS_I8042
>> 661 select SGI_HAS_INDYDOG
>> 662 select SGI_HAS_HAL2
>> 663 select SGI_HAS_SEEQ
>> 664 select SGI_HAS_WD93
>> 665 select SGI_HAS_ZILOG
>> 666 select SWAP_IO_SPACE
>> 667 select SYS_HAS_CPU_R4X00
>> 668 select SYS_HAS_CPU_R5000
>> 669 select SYS_HAS_EARLY_PRINTK
>> 670 select SYS_SUPPORTS_32BIT_KERNEL
>> 671 select SYS_SUPPORTS_64BIT_KERNEL
>> 672 select SYS_SUPPORTS_BIG_ENDIAN
>> 673 select WAR_R4600_V1_INDEX_ICACHEOP
>> 674 select WAR_R4600_V1_HIT_CACHEOP
>> 675 select WAR_R4600_V2_HIT_CACHEOP
>> 676 select MIPS_L1_CACHE_SHIFT_7
>> 677 help
>> 678 This are the SGI Indy, Challenge S and Indigo2, as well as certain
>> 679 OEM variants like the Tandem CMN B006S. To compile a Linux kernel
>> 680 that runs on these, say Y here.
>> 681
>> 682 config SGI_IP27
>> 683 bool "SGI IP27 (Origin200/2000)"
>> 684 select ARCH_HAS_PHYS_TO_DMA
>> 685 select ARCH_SPARSEMEM_ENABLE
>> 686 select FW_ARC
>> 687 select FW_ARC64
>> 688 select ARC_CMDLINE_ONLY
>> 689 select BOOT_ELF64
>> 690 select DEFAULT_SGI_PARTITION
>> 691 select FORCE_PCI
>> 692 select SYS_HAS_EARLY_PRINTK
>> 693 select HAVE_PCI
>> 694 select IRQ_MIPS_CPU
>> 695 select IRQ_DOMAIN_HIERARCHY
>> 696 select NR_CPUS_DEFAULT_64
>> 697 select PCI_DRIVERS_GENERIC
>> 698 select PCI_XTALK_BRIDGE
>> 699 select SYS_HAS_CPU_R10000
>> 700 select SYS_SUPPORTS_64BIT_KERNEL
>> 701 select SYS_SUPPORTS_BIG_ENDIAN
>> 702 select SYS_SUPPORTS_NUMA
>> 703 select SYS_SUPPORTS_SMP
>> 704 select WAR_R10000_LLSC
>> 705 select MIPS_L1_CACHE_SHIFT_7
>> 706 select NUMA
>> 707 select HAVE_ARCH_NODEDATA_EXTENSION
>> 708 help
>> 709 This are the SGI Origin 200, Origin 2000 and Onyx 2 Graphics
>> 710 workstations. To compile a Linux kernel that runs on these, say Y
>> 711 here.
>> 712
>> 713 config SGI_IP28
>> 714 bool "SGI IP28 (Indigo2 R10k)"
>> 715 select ARC_MEMORY
>> 716 select ARC_PROMLIB
>> 717 select FW_ARC
>> 718 select FW_ARC64
>> 719 select ARCH_MIGHT_HAVE_PC_SERIO
>> 720 select BOOT_ELF64
>> 721 select CEVT_R4K
>> 722 select CSRC_R4K
>> 723 select DEFAULT_SGI_PARTITION
>> 724 select DMA_NONCOHERENT
>> 725 select GENERIC_ISA_DMA_SUPPORT_BROKEN
>> 726 select IRQ_MIPS_CPU
>> 727 select HAVE_EISA
>> 728 select I8253
>> 729 select I8259
>> 730 select SGI_HAS_I8042
>> 731 select SGI_HAS_INDYDOG
>> 732 select SGI_HAS_HAL2
>> 733 select SGI_HAS_SEEQ
>> 734 select SGI_HAS_WD93
>> 735 select SGI_HAS_ZILOG
>> 736 select SWAP_IO_SPACE
>> 737 select SYS_HAS_CPU_R10000
>> 738 select SYS_HAS_EARLY_PRINTK
>> 739 select SYS_SUPPORTS_64BIT_KERNEL
>> 740 select SYS_SUPPORTS_BIG_ENDIAN
>> 741 select WAR_R10000_LLSC
>> 742 select MIPS_L1_CACHE_SHIFT_7
>> 743 help
>> 744 This is the SGI Indigo2 with R10000 processor. To compile a Linux
>> 745 kernel that runs on these, say Y here.
>> 746
>> 747 config SGI_IP30
>> 748 bool "SGI IP30 (Octane/Octane2)"
>> 749 select ARCH_HAS_PHYS_TO_DMA
>> 750 select FW_ARC
>> 751 select FW_ARC64
>> 752 select BOOT_ELF64
>> 753 select CEVT_R4K
>> 754 select CSRC_R4K
>> 755 select FORCE_PCI
>> 756 select SYNC_R4K if SMP
>> 757 select ZONE_DMA32
>> 758 select HAVE_PCI
>> 759 select IRQ_MIPS_CPU
>> 760 select IRQ_DOMAIN_HIERARCHY
>> 761 select PCI_DRIVERS_GENERIC
>> 762 select PCI_XTALK_BRIDGE
>> 763 select SYS_HAS_EARLY_PRINTK
>> 764 select SYS_HAS_CPU_R10000
>> 765 select SYS_SUPPORTS_64BIT_KERNEL
>> 766 select SYS_SUPPORTS_BIG_ENDIAN
>> 767 select SYS_SUPPORTS_SMP
>> 768 select WAR_R10000_LLSC
>> 769 select MIPS_L1_CACHE_SHIFT_7
>> 770 select ARC_MEMORY
>> 771 help
>> 772 These are the SGI Octane and Octane2 graphics workstations. To
>> 773 compile a Linux kernel that runs on these, say Y here.
>> 774
>> 775 config SGI_IP32
>> 776 bool "SGI IP32 (O2)"
>> 777 select ARC_MEMORY
>> 778 select ARC_PROMLIB
>> 779 select ARCH_HAS_PHYS_TO_DMA
>> 780 select FW_ARC
>> 781 select FW_ARC32
>> 782 select BOOT_ELF32
>> 783 select CEVT_R4K
>> 784 select CSRC_R4K
>> 785 select DMA_NONCOHERENT
>> 786 select HAVE_PCI
>> 787 select IRQ_MIPS_CPU
>> 788 select R5000_CPU_SCACHE
>> 789 select RM7000_CPU_SCACHE
>> 790 select SYS_HAS_CPU_R5000
>> 791 select SYS_HAS_CPU_R10000 if BROKEN
>> 792 select SYS_HAS_CPU_RM7000
>> 793 select SYS_HAS_CPU_NEVADA
>> 794 select SYS_SUPPORTS_64BIT_KERNEL
>> 795 select SYS_SUPPORTS_BIG_ENDIAN
>> 796 select WAR_ICACHE_REFILLS
>> 797 help
>> 798 If you want this kernel to run on SGI O2 workstation, say Y here.
>> 799
>> 800 config SIBYTE_CRHINE
>> 801 bool "Sibyte BCM91120C-CRhine"
>> 802 select BOOT_ELF32
>> 803 select SIBYTE_BCM1120
>> 804 select SWAP_IO_SPACE
>> 805 select SYS_HAS_CPU_SB1
>> 806 select SYS_SUPPORTS_BIG_ENDIAN
>> 807 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 808
>> 809 config SIBYTE_CARMEL
>> 810 bool "Sibyte BCM91120x-Carmel"
>> 811 select BOOT_ELF32
>> 812 select SIBYTE_BCM1120
>> 813 select SWAP_IO_SPACE
>> 814 select SYS_HAS_CPU_SB1
>> 815 select SYS_SUPPORTS_BIG_ENDIAN
>> 816 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 817
>> 818 config SIBYTE_CRHONE
>> 819 bool "Sibyte BCM91125C-CRhone"
>> 820 select BOOT_ELF32
>> 821 select SIBYTE_BCM1125
>> 822 select SWAP_IO_SPACE
>> 823 select SYS_HAS_CPU_SB1
>> 824 select SYS_SUPPORTS_BIG_ENDIAN
>> 825 select SYS_SUPPORTS_HIGHMEM
>> 826 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 827
>> 828 config SIBYTE_RHONE
>> 829 bool "Sibyte BCM91125E-Rhone"
>> 830 select BOOT_ELF32
>> 831 select SIBYTE_BCM1125H
>> 832 select SWAP_IO_SPACE
>> 833 select SYS_HAS_CPU_SB1
>> 834 select SYS_SUPPORTS_BIG_ENDIAN
>> 835 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 836
>> 837 config SIBYTE_SWARM
>> 838 bool "Sibyte BCM91250A-SWARM"
>> 839 select BOOT_ELF32
>> 840 select HAVE_PATA_PLATFORM
>> 841 select SIBYTE_SB1250
>> 842 select SWAP_IO_SPACE
>> 843 select SYS_HAS_CPU_SB1
>> 844 select SYS_SUPPORTS_BIG_ENDIAN
>> 845 select SYS_SUPPORTS_HIGHMEM
>> 846 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 847 select ZONE_DMA32 if 64BIT
>> 848 select SWIOTLB if ARCH_DMA_ADDR_T_64BIT && PCI
>> 849
>> 850 config SIBYTE_LITTLESUR
>> 851 bool "Sibyte BCM91250C2-LittleSur"
>> 852 select BOOT_ELF32
>> 853 select HAVE_PATA_PLATFORM
>> 854 select SIBYTE_SB1250
>> 855 select SWAP_IO_SPACE
>> 856 select SYS_HAS_CPU_SB1
>> 857 select SYS_SUPPORTS_BIG_ENDIAN
>> 858 select SYS_SUPPORTS_HIGHMEM
>> 859 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 860 select ZONE_DMA32 if 64BIT
>> 861
>> 862 config SIBYTE_SENTOSA
>> 863 bool "Sibyte BCM91250E-Sentosa"
>> 864 select BOOT_ELF32
>> 865 select SIBYTE_SB1250
>> 866 select SWAP_IO_SPACE
>> 867 select SYS_HAS_CPU_SB1
>> 868 select SYS_SUPPORTS_BIG_ENDIAN
>> 869 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 870 select SWIOTLB if ARCH_DMA_ADDR_T_64BIT && PCI
>> 871
>> 872 config SIBYTE_BIGSUR
>> 873 bool "Sibyte BCM91480B-BigSur"
>> 874 select BOOT_ELF32
>> 875 select NR_CPUS_DEFAULT_4
>> 876 select SIBYTE_BCM1x80
>> 877 select SWAP_IO_SPACE
>> 878 select SYS_HAS_CPU_SB1
>> 879 select SYS_SUPPORTS_BIG_ENDIAN
>> 880 select SYS_SUPPORTS_HIGHMEM
>> 881 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 882 select ZONE_DMA32 if 64BIT
>> 883 select SWIOTLB if ARCH_DMA_ADDR_T_64BIT && PCI
>> 884
>> 885 config SNI_RM
>> 886 bool "SNI RM200/300/400"
>> 887 select ARC_MEMORY
>> 888 select ARC_PROMLIB
>> 889 select FW_ARC if CPU_LITTLE_ENDIAN
>> 890 select FW_ARC32 if CPU_LITTLE_ENDIAN
>> 891 select FW_SNIPROM if CPU_BIG_ENDIAN
>> 892 select ARCH_MAY_HAVE_PC_FDC
>> 893 select ARCH_MIGHT_HAVE_PC_PARPORT
>> 894 select ARCH_MIGHT_HAVE_PC_SERIO
>> 895 select BOOT_ELF32
>> 896 select CEVT_R4K
>> 897 select CSRC_R4K
>> 898 select DEFAULT_SGI_PARTITION if CPU_BIG_ENDIAN
>> 899 select DMA_NONCOHERENT
>> 900 select GENERIC_ISA_DMA
>> 901 select HAVE_EISA
>> 902 select HAVE_PCSPKR_PLATFORM
>> 903 select HAVE_PCI
>> 904 select IRQ_MIPS_CPU
>> 905 select I8253
>> 906 select I8259
>> 907 select ISA
>> 908 select MIPS_L1_CACHE_SHIFT_6
>> 909 select SWAP_IO_SPACE if CPU_BIG_ENDIAN
>> 910 select SYS_HAS_CPU_R4X00
>> 911 select SYS_HAS_CPU_R5000
>> 912 select SYS_HAS_CPU_R10000
>> 913 select R5000_CPU_SCACHE
>> 914 select SYS_HAS_EARLY_PRINTK
>> 915 select SYS_SUPPORTS_32BIT_KERNEL
>> 916 select SYS_SUPPORTS_64BIT_KERNEL
>> 917 select SYS_SUPPORTS_BIG_ENDIAN
>> 918 select SYS_SUPPORTS_HIGHMEM
>> 919 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 920 select WAR_R4600_V2_HIT_CACHEOP
>> 921 help
>> 922 The SNI RM200/300/400 are MIPS-based machines manufactured by
>> 923 Siemens Nixdorf Informationssysteme (SNI), parent company of Pyramid
>> 924 Technology and now in turn merged with Fujitsu. Say Y here to
>> 925 support this machine type.
>> 926
>> 927 config MACH_TX49XX
>> 928 bool "Toshiba TX49 series based machines"
>> 929 select WAR_TX49XX_ICACHE_INDEX_INV
>> 930
>> 931 config MIKROTIK_RB532
>> 932 bool "Mikrotik RB532 boards"
>> 933 select CEVT_R4K
>> 934 select CSRC_R4K
>> 935 select DMA_NONCOHERENT
>> 936 select HAVE_PCI
>> 937 select IRQ_MIPS_CPU
>> 938 select SYS_HAS_CPU_MIPS32_R1
>> 939 select SYS_SUPPORTS_32BIT_KERNEL
>> 940 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 941 select SWAP_IO_SPACE
>> 942 select BOOT_RAW
>> 943 select GPIOLIB
>> 944 select MIPS_L1_CACHE_SHIFT_4
>> 945 help
>> 946 Support the Mikrotik(tm) RouterBoard 532 series,
>> 947 based on the IDT RC32434 SoC.
>> 948
>> 949 config CAVIUM_OCTEON_SOC
>> 950 bool "Cavium Networks Octeon SoC based boards"
>> 951 select CEVT_R4K
>> 952 select ARCH_HAS_PHYS_TO_DMA
>> 953 select HAVE_RAPIDIO
>> 954 select PHYS_ADDR_T_64BIT
>> 955 select SYS_SUPPORTS_64BIT_KERNEL
>> 956 select SYS_SUPPORTS_BIG_ENDIAN
>> 957 select EDAC_SUPPORT
>> 958 select EDAC_ATOMIC_SCRUB
>> 959 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 960 select SYS_SUPPORTS_HOTPLUG_CPU if CPU_BIG_ENDIAN
>> 961 select SYS_HAS_EARLY_PRINTK
>> 962 select SYS_HAS_CPU_CAVIUM_OCTEON
>> 963 select HAVE_PCI
>> 964 select HAVE_PLAT_DELAY
>> 965 select HAVE_PLAT_FW_INIT_CMDLINE
>> 966 select HAVE_PLAT_MEMCPY
>> 967 select ZONE_DMA32
>> 968 select GPIOLIB
>> 969 select USE_OF
>> 970 select ARCH_SPARSEMEM_ENABLE
>> 971 select SYS_SUPPORTS_SMP
>> 972 select NR_CPUS_DEFAULT_64
>> 973 select MIPS_NR_CPU_NR_MAP_1024
>> 974 select BUILTIN_DTB
>> 975 select MTD
>> 976 select MTD_COMPLEX_MAPPINGS
>> 977 select SWIOTLB
>> 978 select SYS_SUPPORTS_RELOCATABLE
>> 979 help
>> 980 This option supports all of the Octeon reference boards from Cavium
>> 981 Networks. It builds a kernel that dynamically determines the Octeon
>> 982 CPU type and supports all known board reference implementations.
>> 983 Some of the supported boards are:
>> 984 EBT3000
>> 985 EBH3000
>> 986 EBH3100
>> 987 Thunder
>> 988 Kodama
>> 989 Hikari
>> 990 Say Y here for most Octeon reference boards.
349 991
350 config LOCKDEP_SUPPORT !! 992 endchoice
351 def_bool y <<
352 993
353 config GENERIC_BUG !! 994 source "arch/mips/alchemy/Kconfig"
354 def_bool y !! 995 source "arch/mips/ath25/Kconfig"
355 depends on BUG !! 996 source "arch/mips/ath79/Kconfig"
>> 997 source "arch/mips/bcm47xx/Kconfig"
>> 998 source "arch/mips/bcm63xx/Kconfig"
>> 999 source "arch/mips/bmips/Kconfig"
>> 1000 source "arch/mips/generic/Kconfig"
>> 1001 source "arch/mips/ingenic/Kconfig"
>> 1002 source "arch/mips/jazz/Kconfig"
>> 1003 source "arch/mips/lantiq/Kconfig"
>> 1004 source "arch/mips/pic32/Kconfig"
>> 1005 source "arch/mips/ralink/Kconfig"
>> 1006 source "arch/mips/sgi-ip27/Kconfig"
>> 1007 source "arch/mips/sibyte/Kconfig"
>> 1008 source "arch/mips/txx9/Kconfig"
>> 1009 source "arch/mips/cavium-octeon/Kconfig"
>> 1010 source "arch/mips/loongson2ef/Kconfig"
>> 1011 source "arch/mips/loongson32/Kconfig"
>> 1012 source "arch/mips/loongson64/Kconfig"
356 1013
357 config GENERIC_BUG_RELATIVE_POINTERS !! 1014 endmenu
358 def_bool y <<
359 depends on GENERIC_BUG <<
360 1015
361 config GENERIC_HWEIGHT 1016 config GENERIC_HWEIGHT
362 def_bool y !! 1017 bool
363 !! 1018 default y
364 config GENERIC_CSUM <<
365 def_bool y <<
366 1019
367 config GENERIC_CALIBRATE_DELAY 1020 config GENERIC_CALIBRATE_DELAY
368 def_bool y !! 1021 bool
>> 1022 default y
369 1023
370 config SMP !! 1024 config SCHED_OMIT_FRAME_POINTER
371 def_bool y !! 1025 bool
>> 1026 default y
372 1027
373 config KERNEL_MODE_NEON !! 1028 #
374 def_bool y !! 1029 # Select some configuration options automatically based on user selections.
>> 1030 #
>> 1031 config FW_ARC
>> 1032 bool
375 1033
376 config FIX_EARLYCON_MEM !! 1034 config ARCH_MAY_HAVE_PC_FDC
377 def_bool y !! 1035 bool
378 1036
379 config PGTABLE_LEVELS !! 1037 config BOOT_RAW
380 int !! 1038 bool
381 default 2 if ARM64_16K_PAGES && ARM64_ <<
382 default 2 if ARM64_64K_PAGES && ARM64_ <<
383 default 3 if ARM64_64K_PAGES && (ARM64 <<
384 default 3 if ARM64_4K_PAGES && ARM64_V <<
385 default 3 if ARM64_16K_PAGES && ARM64_ <<
386 default 4 if ARM64_16K_PAGES && (ARM64 <<
387 default 4 if !ARM64_64K_PAGES && ARM64 <<
388 default 5 if ARM64_4K_PAGES && ARM64_V <<
389 1039
390 config ARCH_SUPPORTS_UPROBES !! 1040 config CEVT_BCM1480
391 def_bool y !! 1041 bool
392 1042
393 config ARCH_PROC_KCORE_TEXT !! 1043 config CEVT_DS1287
394 def_bool y !! 1044 bool
395 1045
396 config BROKEN_GAS_INST !! 1046 config CEVT_GT641XX
397 def_bool !$(as-instr,1:\n.inst 0\n.rep !! 1047 bool
398 1048
399 config BUILTIN_RETURN_ADDRESS_STRIPS_PAC !! 1049 config CEVT_R4K
400 bool 1050 bool
401 # Clang's __builtin_return_address() s <<
402 # https://github.com/llvm/llvm-project <<
403 default y if CC_IS_CLANG <<
404 # GCC's __builtin_return_address() str <<
405 # and this was backported to 10.2.0, 9 <<
406 # https://gcc.gnu.org/bugzilla/show_bu <<
407 default y if CC_IS_GCC && (GCC_VERSION <<
408 default y if CC_IS_GCC && (GCC_VERSION <<
409 default y if CC_IS_GCC && (GCC_VERSION <<
410 default y if CC_IS_GCC && (GCC_VERSION <<
411 default n <<
412 1051
413 config KASAN_SHADOW_OFFSET !! 1052 config CEVT_SB1250
414 hex <<
415 depends on KASAN_GENERIC || KASAN_SW_T <<
416 default 0xdfff800000000000 if (ARM64_V <<
417 default 0xdfffc00000000000 if (ARM64_V <<
418 default 0xdffffe0000000000 if ARM64_VA <<
419 default 0xdfffffc000000000 if ARM64_VA <<
420 default 0xdffffff800000000 if ARM64_VA <<
421 default 0xefff800000000000 if (ARM64_V <<
422 default 0xefffc00000000000 if (ARM64_V <<
423 default 0xeffffe0000000000 if ARM64_VA <<
424 default 0xefffffc000000000 if ARM64_VA <<
425 default 0xeffffff800000000 if ARM64_VA <<
426 default 0xffffffffffffffff <<
427 <<
428 config UNWIND_TABLES <<
429 bool 1053 bool
430 1054
431 source "arch/arm64/Kconfig.platforms" !! 1055 config CEVT_TXX9
>> 1056 bool
432 1057
433 menu "Kernel Features" !! 1058 config CSRC_BCM1480
>> 1059 bool
434 1060
435 menu "ARM errata workarounds via the alternati !! 1061 config CSRC_IOASIC
>> 1062 bool
436 1063
437 config AMPERE_ERRATUM_AC03_CPU_38 !! 1064 config CSRC_R4K
438 bool "AmpereOne: AC03_CPU_38: Certain !! 1065 select CLOCKSOURCE_WATCHDOG if CPU_FREQ
439 default y !! 1066 bool
440 help <<
441 This option adds an alternative code <<
442 errata AC03_CPU_38 and AC04_CPU_10 o <<
443 1067
444 The affected design reports FEAT_HAF !! 1068 config CSRC_SB1250
445 ID_AA64MMFR1_EL1.HAFDBS, but (V)TCR_ !! 1069 bool
446 as required by the architecture. The <<
447 implementation suffers from an addit <<
448 A/D updates can occur after a PTE ha <<
449 <<
450 The workaround forces KVM to explici <<
451 which avoids enabling unadvertised h <<
452 at stage-2. <<
453 1070
454 If unsure, say Y. !! 1071 config MIPS_CLOCK_VSYSCALL
>> 1072 def_bool CSRC_R4K || CLKSRC_MIPS_GIC
455 1073
456 config ARM64_WORKAROUND_CLEAN_CACHE !! 1074 config GPIO_TXX9
>> 1075 select GPIOLIB
457 bool 1076 bool
458 1077
459 config ARM64_ERRATUM_826319 !! 1078 config FW_CFE
460 bool "Cortex-A53: 826319: System might !! 1079 bool
461 default y <<
462 select ARM64_WORKAROUND_CLEAN_CACHE <<
463 help <<
464 This option adds an alternative code <<
465 erratum 826319 on Cortex-A53 parts u <<
466 AXI master interface and an L2 cache <<
467 <<
468 If a Cortex-A53 uses an AMBA AXI4 AC <<
469 and is unable to accept a certain wr <<
470 not progress on read data presented <<
471 system can deadlock. <<
472 <<
473 The workaround promotes data cache c <<
474 data cache clean-and-invalidate. <<
475 Please note that this does not neces <<
476 as it depends on the alternative fra <<
477 the kernel if an affected CPU is det <<
478 <<
479 If unsure, say Y. <<
480 1080
481 config ARM64_ERRATUM_827319 !! 1081 config ARCH_SUPPORTS_UPROBES
482 bool "Cortex-A53: 827319: Data cache c !! 1082 bool
483 default y <<
484 select ARM64_WORKAROUND_CLEAN_CACHE <<
485 help <<
486 This option adds an alternative code <<
487 erratum 827319 on Cortex-A53 parts u <<
488 master interface and an L2 cache. <<
489 <<
490 Under certain conditions this erratu <<
491 to occur at the same time as another <<
492 on the AMBA 5 CHI interface, which c <<
493 interconnect reorders the two transa <<
494 <<
495 The workaround promotes data cache c <<
496 data cache clean-and-invalidate. <<
497 Please note that this does not neces <<
498 as it depends on the alternative fra <<
499 the kernel if an affected CPU is det <<
500 1083
501 If unsure, say Y. !! 1084 config DMA_NONCOHERENT
>> 1085 bool
>> 1086 #
>> 1087 # MIPS allows mixing "slightly different" Cacheability and Coherency
>> 1088 # Attribute bits. It is believed that the uncached access through
>> 1089 # KSEG1 and the implementation specific "uncached accelerated" used
>> 1090 # by pgprot_writcombine can be mixed, and the latter sometimes provides
>> 1091 # significant advantages.
>> 1092 #
>> 1093 select ARCH_HAS_DMA_WRITE_COMBINE
>> 1094 select ARCH_HAS_DMA_PREP_COHERENT
>> 1095 select ARCH_HAS_SYNC_DMA_FOR_DEVICE
>> 1096 select ARCH_HAS_DMA_SET_UNCACHED
>> 1097 select DMA_NONCOHERENT_MMAP
>> 1098 select NEED_DMA_MAP_STATE
502 1099
503 config ARM64_ERRATUM_824069 !! 1100 config SYS_HAS_EARLY_PRINTK
504 bool "Cortex-A53: 824069: Cache line m !! 1101 bool
505 default y <<
506 select ARM64_WORKAROUND_CLEAN_CACHE <<
507 help <<
508 This option adds an alternative code <<
509 erratum 824069 on Cortex-A53 parts u <<
510 to a coherent interconnect. <<
511 <<
512 If a Cortex-A53 processor is executi <<
513 write instruction at the same time a <<
514 cluster is executing a cache mainten <<
515 address, then this erratum might cau <<
516 incorrectly marked as dirty. <<
517 <<
518 The workaround promotes data cache c <<
519 data cache clean-and-invalidate. <<
520 Please note that this option does no <<
521 workaround, as it depends on the alt <<
522 only patch the kernel if an affected <<
523 1102
524 If unsure, say Y. !! 1103 config SYS_SUPPORTS_HOTPLUG_CPU
>> 1104 bool
525 1105
526 config ARM64_ERRATUM_819472 !! 1106 config MIPS_BONITO64
527 bool "Cortex-A53: 819472: Store exclus !! 1107 bool
528 default y <<
529 select ARM64_WORKAROUND_CLEAN_CACHE <<
530 help <<
531 This option adds an alternative code <<
532 erratum 819472 on Cortex-A53 parts u <<
533 present when it is connected to a co <<
534 <<
535 If the processor is executing a load <<
536 the same time as a processor in anot <<
537 maintenance operation to the same ad <<
538 cause data corruption. <<
539 <<
540 The workaround promotes data cache c <<
541 data cache clean-and-invalidate. <<
542 Please note that this does not neces <<
543 as it depends on the alternative fra <<
544 the kernel if an affected CPU is det <<
545 1108
546 If unsure, say Y. !! 1109 config MIPS_MSC
>> 1110 bool
547 1111
548 config ARM64_ERRATUM_832075 !! 1112 config SYNC_R4K
549 bool "Cortex-A57: 832075: possible dea !! 1113 bool
550 default y <<
551 help <<
552 This option adds an alternative code <<
553 erratum 832075 on Cortex-A57 parts u <<
554 1114
555 Affected Cortex-A57 parts might dead !! 1115 config NO_IOPORT_MAP
556 instructions to Write-Back memory ar !! 1116 def_bool n
557 1117
558 The workaround is to promote device !! 1118 config GENERIC_CSUM
559 semantics. !! 1119 def_bool CPU_NO_LOAD_STORE_LR
560 Please note that this does not neces <<
561 as it depends on the alternative fra <<
562 the kernel if an affected CPU is det <<
563 1120
564 If unsure, say Y. !! 1121 config GENERIC_ISA_DMA
>> 1122 bool
>> 1123 select ZONE_DMA if GENERIC_ISA_DMA_SUPPORT_BROKEN=n
>> 1124 select ISA_DMA_API
565 1125
566 config ARM64_ERRATUM_834220 !! 1126 config GENERIC_ISA_DMA_SUPPORT_BROKEN
567 bool "Cortex-A57: 834220: Stage 2 tran !! 1127 bool
568 depends on KVM !! 1128 select GENERIC_ISA_DMA
569 help <<
570 This option adds an alternative code <<
571 erratum 834220 on Cortex-A57 parts u <<
572 <<
573 Affected Cortex-A57 parts might repo <<
574 fault as the result of a Stage 1 fau <<
575 page boundary when there is a permis <<
576 alignment fault at Stage 1 and a tra <<
577 <<
578 The workaround is to verify that the <<
579 doesn't generate a fault before hand <<
580 Please note that this does not neces <<
581 as it depends on the alternative fra <<
582 the kernel if an affected CPU is det <<
583 1129
584 If unsure, say N. !! 1130 config HAVE_PLAT_DELAY
>> 1131 bool
585 1132
586 config ARM64_ERRATUM_1742098 !! 1133 config HAVE_PLAT_FW_INIT_CMDLINE
587 bool "Cortex-A57/A72: 1742098: ELR rec !! 1134 bool
588 depends on COMPAT <<
589 default y <<
590 help <<
591 This option removes the AES hwcap fo <<
592 workaround erratum 1742098 on Cortex <<
593 1135
594 Affected parts may corrupt the AES s !! 1136 config HAVE_PLAT_MEMCPY
595 taken between a pair of AES instruct !! 1137 bool
596 are only present if the cryptography <<
597 All software should have a fallback <<
598 that don't implement the cryptograph <<
599 1138
600 If unsure, say Y. !! 1139 config ISA_DMA_API
>> 1140 bool
601 1141
602 config ARM64_ERRATUM_845719 !! 1142 config SYS_SUPPORTS_RELOCATABLE
603 bool "Cortex-A53: 845719: a load might !! 1143 bool
604 depends on COMPAT <<
605 default y <<
606 help 1144 help
607 This option adds an alternative code !! 1145 Selected if the platform supports relocating the kernel.
608 erratum 845719 on Cortex-A53 parts u !! 1146 The platform must provide plat_get_fdt() if it selects CONFIG_USE_OF
609 !! 1147 to allow access to command line and entropy sources.
610 When running a compat (AArch32) user <<
611 part, a load at EL0 from a virtual a <<
612 bits of the virtual address used by <<
613 might return incorrect data. <<
614 <<
615 The workaround is to write the conte <<
616 return to a 32-bit task. <<
617 Please note that this does not neces <<
618 as it depends on the alternative fra <<
619 the kernel if an affected CPU is det <<
620 <<
621 If unsure, say Y. <<
622 1148
623 config ARM64_ERRATUM_843419 !! 1149 #
624 bool "Cortex-A53: 843419: A load or st !! 1150 # Endianness selection. Sufficiently obscure so many users don't know what to
625 default y !! 1151 # answer,so we try hard to limit the available choices. Also the use of a
>> 1152 # choice statement should be more obvious to the user.
>> 1153 #
>> 1154 choice
>> 1155 prompt "Endianness selection"
626 help 1156 help
627 This option links the kernel with '- !! 1157 Some MIPS machines can be configured for either little or big endian
628 enables PLT support to replace certa !! 1158 byte order. These modes require different kernels and a different
629 cause subsequent memory accesses to !! 1159 Linux distribution. In general there is one preferred byteorder for a
630 Cortex-A53 parts up to r0p4. !! 1160 particular system but some systems are just as commonly used in the
>> 1161 one or the other endianness.
631 1162
632 If unsure, say Y. !! 1163 config CPU_BIG_ENDIAN
>> 1164 bool "Big endian"
>> 1165 depends on SYS_SUPPORTS_BIG_ENDIAN
633 1166
634 config ARM64_LD_HAS_FIX_ERRATUM_843419 !! 1167 config CPU_LITTLE_ENDIAN
635 def_bool $(ld-option,--fix-cortex-a53- !! 1168 bool "Little endian"
>> 1169 depends on SYS_SUPPORTS_LITTLE_ENDIAN
636 1170
637 config ARM64_ERRATUM_1024718 !! 1171 endchoice
638 bool "Cortex-A55: 1024718: Update of D <<
639 default y <<
640 help <<
641 This option adds a workaround for AR <<
642 1172
643 Affected Cortex-A55 cores (all revis !! 1173 config EXPORT_UASM
644 update of the hardware dirty bit whe !! 1174 bool
645 without a break-before-make. The wor <<
646 of hardware DBM locally on the affec <<
647 this erratum will continue to use th <<
648 1175
649 If unsure, say Y. !! 1176 config SYS_SUPPORTS_APM_EMULATION
>> 1177 bool
650 1178
651 config ARM64_ERRATUM_1418040 !! 1179 config SYS_SUPPORTS_BIG_ENDIAN
652 bool "Cortex-A76/Neoverse-N1: MRC read !! 1180 bool
653 default y <<
654 depends on COMPAT <<
655 help <<
656 This option adds a workaround for AR <<
657 errata 1188873 and 1418040. <<
658 1181
659 Affected Cortex-A76/Neoverse-N1 core !! 1182 config SYS_SUPPORTS_LITTLE_ENDIAN
660 cause register corruption when acces !! 1183 bool
661 from AArch32 userspace. <<
662 1184
663 If unsure, say Y. !! 1185 config MIPS_HUGE_TLB_SUPPORT
>> 1186 def_bool HUGETLB_PAGE || TRANSPARENT_HUGEPAGE
664 1187
665 config ARM64_WORKAROUND_SPECULATIVE_AT !! 1188 config IRQ_MSP_SLP
666 bool 1189 bool
667 1190
668 config ARM64_ERRATUM_1165522 !! 1191 config IRQ_MSP_CIC
669 bool "Cortex-A76: 1165522: Speculative !! 1192 bool
670 default y <<
671 select ARM64_WORKAROUND_SPECULATIVE_AT <<
672 help <<
673 This option adds a workaround for AR <<
674 <<
675 Affected Cortex-A76 cores (r0p0, r1p <<
676 corrupted TLBs by speculating an AT <<
677 context switch. <<
678 1193
679 If unsure, say Y. !! 1194 config IRQ_TXX9
>> 1195 bool
680 1196
681 config ARM64_ERRATUM_1319367 !! 1197 config IRQ_GT641XX
682 bool "Cortex-A57/A72: 1319537: Specula !! 1198 bool
683 default y <<
684 select ARM64_WORKAROUND_SPECULATIVE_AT <<
685 help <<
686 This option adds work arounds for AR <<
687 and A72 erratum 1319367 <<
688 1199
689 Cortex-A57 and A72 cores could end-u !! 1200 config PCI_GT64XXX_PCI0
690 speculating an AT instruction during !! 1201 bool
691 1202
692 If unsure, say Y. !! 1203 config PCI_XTALK_BRIDGE
>> 1204 bool
693 1205
694 config ARM64_ERRATUM_1530923 !! 1206 config NO_EXCEPT_FILL
695 bool "Cortex-A55: 1530923: Speculative !! 1207 bool
696 default y <<
697 select ARM64_WORKAROUND_SPECULATIVE_AT <<
698 help <<
699 This option adds a workaround for AR <<
700 1208
701 Affected Cortex-A55 cores (r0p0, r0p !! 1209 config MIPS_SPRAM
702 corrupted TLBs by speculating an AT !! 1210 bool
703 context switch. <<
704 1211
705 If unsure, say Y. !! 1212 config SWAP_IO_SPACE
>> 1213 bool
706 1214
707 config ARM64_WORKAROUND_REPEAT_TLBI !! 1215 config SGI_HAS_INDYDOG
708 bool 1216 bool
709 1217
710 config ARM64_ERRATUM_2441007 !! 1218 config SGI_HAS_HAL2
711 bool "Cortex-A55: Completion of affect !! 1219 bool
712 select ARM64_WORKAROUND_REPEAT_TLBI <<
713 help <<
714 This option adds a workaround for AR <<
715 1220
716 Under very rare circumstances, affec !! 1221 config SGI_HAS_SEEQ
717 may not handle a race between a brea !! 1222 bool
718 CPU, and another CPU accessing the s <<
719 store to a page that has been unmapp <<
720 1223
721 Work around this by adding the affec !! 1224 config SGI_HAS_WD93
722 TLB sequences to be done twice. !! 1225 bool
723 1226
724 If unsure, say N. !! 1227 config SGI_HAS_ZILOG
>> 1228 bool
725 1229
726 config ARM64_ERRATUM_1286807 !! 1230 config SGI_HAS_I8042
727 bool "Cortex-A76: Modification of the !! 1231 bool
728 select ARM64_WORKAROUND_REPEAT_TLBI <<
729 help <<
730 This option adds a workaround for AR <<
731 <<
732 On the affected Cortex-A76 cores (r0 <<
733 address for a cacheable mapping of a <<
734 accessed by a core while another cor <<
735 address to a new physical page using <<
736 break-before-make sequence, then und <<
737 TLBI+DSB completes before a read usi <<
738 invalidated has been observed by oth <<
739 workaround repeats the TLBI+DSB oper <<
740 1232
741 If unsure, say N. !! 1233 config DEFAULT_SGI_PARTITION
>> 1234 bool
742 1235
743 config ARM64_ERRATUM_1463225 !! 1236 config FW_ARC32
744 bool "Cortex-A76: Software Step might !! 1237 bool
745 default y <<
746 help <<
747 This option adds a workaround for Ar <<
748 1238
749 On the affected Cortex-A76 cores (r0 !! 1239 config FW_SNIPROM
750 of a system call instruction (SVC) c !! 1240 bool
751 subsequent interrupts when software <<
752 exception handler of the system call <<
753 is enabled or VHE is in use. <<
754 <<
755 Work around the erratum by triggerin <<
756 when handling a system call from a t <<
757 in a VHE configuration of the kernel <<
758 1241
759 If unsure, say Y. !! 1242 config BOOT_ELF32
>> 1243 bool
760 1244
761 config ARM64_ERRATUM_1542419 !! 1245 config MIPS_L1_CACHE_SHIFT_4
762 bool "Neoverse-N1: workaround mis-orde !! 1246 bool
763 help <<
764 This option adds a workaround for AR <<
765 1542419. <<
766 1247
767 Affected Neoverse-N1 cores could exe !! 1248 config MIPS_L1_CACHE_SHIFT_5
768 modified by another CPU. The workaro !! 1249 bool
769 counterpart. <<
770 1250
771 Workaround the issue by hiding the D !! 1251 config MIPS_L1_CACHE_SHIFT_6
772 forces user-space to perform cache m !! 1252 bool
773 1253
774 If unsure, say N. !! 1254 config MIPS_L1_CACHE_SHIFT_7
>> 1255 bool
775 1256
776 config ARM64_ERRATUM_1508412 !! 1257 config MIPS_L1_CACHE_SHIFT
777 bool "Cortex-A77: 1508412: workaround !! 1258 int
778 default y !! 1259 default "7" if MIPS_L1_CACHE_SHIFT_7
779 help !! 1260 default "6" if MIPS_L1_CACHE_SHIFT_6
780 This option adds a workaround for Ar !! 1261 default "5" if MIPS_L1_CACHE_SHIFT_5
>> 1262 default "4" if MIPS_L1_CACHE_SHIFT_4
>> 1263 default "5"
781 1264
782 Affected Cortex-A77 cores (r0p0, r1p !! 1265 config ARC_CMDLINE_ONLY
783 of a store-exclusive or read of PAR_ !! 1266 bool
784 non-cacheable memory attributes. The <<
785 counterpart. <<
786 <<
787 KVM guests must also have the workar <<
788 deadlock the system. <<
789 <<
790 Work around the issue by inserting D <<
791 register reads and warning KVM users <<
792 to prevent a speculative PAR_EL1 rea <<
793 1267
794 If unsure, say Y. !! 1268 config ARC_CONSOLE
>> 1269 bool "ARC console support"
>> 1270 depends on SGI_IP22 || SGI_IP28 || (SNI_RM && CPU_LITTLE_ENDIAN)
795 1271
796 config ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MO !! 1272 config ARC_MEMORY
797 bool 1273 bool
798 1274
799 config ARM64_ERRATUM_2051678 !! 1275 config ARC_PROMLIB
800 bool "Cortex-A510: 2051678: disable Ha !! 1276 bool
801 default y <<
802 help <<
803 This options adds the workaround for <<
804 Affected Cortex-A510 might not respe <<
805 hardware update of the page table's <<
806 is to not enable the feature on affe <<
807 1277
808 If unsure, say Y. !! 1278 config FW_ARC64
>> 1279 bool
809 1280
810 config ARM64_ERRATUM_2077057 !! 1281 config BOOT_ELF64
811 bool "Cortex-A510: 2077057: workaround !! 1282 bool
812 default y <<
813 help <<
814 This option adds the workaround for <<
815 Affected Cortex-A510 may corrupt SPS <<
816 expected, but a Pointer Authenticati <<
817 erratum causes SPSR_EL1 to be copied <<
818 EL1 to cause a return to EL2 with a <<
819 1283
820 This can only happen when EL2 is ste !! 1284 menu "CPU selection"
821 1285
822 When these conditions occur, the SPS !! 1286 choice
823 previous guest entry, and can be res !! 1287 prompt "CPU type"
>> 1288 default CPU_R4X00
824 1289
825 If unsure, say Y. !! 1290 config CPU_LOONGSON64
>> 1291 bool "Loongson 64-bit CPU"
>> 1292 depends on SYS_HAS_CPU_LOONGSON64
>> 1293 select ARCH_HAS_PHYS_TO_DMA
>> 1294 select CPU_MIPSR2
>> 1295 select CPU_HAS_PREFETCH
>> 1296 select CPU_SUPPORTS_64BIT_KERNEL
>> 1297 select CPU_SUPPORTS_HIGHMEM
>> 1298 select CPU_SUPPORTS_HUGEPAGES
>> 1299 select CPU_SUPPORTS_MSA
>> 1300 select CPU_DIEI_BROKEN if !LOONGSON3_ENHANCEMENT
>> 1301 select CPU_MIPSR2_IRQ_VI
>> 1302 select WEAK_ORDERING
>> 1303 select WEAK_REORDERING_BEYOND_LLSC
>> 1304 select MIPS_ASID_BITS_VARIABLE
>> 1305 select MIPS_PGD_C0_CONTEXT
>> 1306 select MIPS_L1_CACHE_SHIFT_6
>> 1307 select MIPS_FP_SUPPORT
>> 1308 select GPIOLIB
>> 1309 select SWIOTLB
>> 1310 select HAVE_KVM
>> 1311 help
>> 1312 The Loongson GSx64(GS264/GS464/GS464E/GS464V) series of processor
>> 1313 cores implements the MIPS64R2 instruction set with many extensions,
>> 1314 including most 64-bit Loongson-2 (2H, 2K) and Loongson-3 (3A1000,
>> 1315 3B1000, 3B1500, 3A2000, 3A3000 and 3A4000) processors. However, old
>> 1316 Loongson-2E/2F is not covered here and will be removed in future.
826 1317
827 config ARM64_ERRATUM_2658417 !! 1318 config LOONGSON3_ENHANCEMENT
828 bool "Cortex-A510: 2658417: remove BF1 !! 1319 bool "New Loongson-3 CPU Enhancements"
829 default y !! 1320 default n
>> 1321 depends on CPU_LOONGSON64
>> 1322 help
>> 1323 New Loongson-3 cores (since Loongson-3A R2, as opposed to Loongson-3A
>> 1324 R1, Loongson-3B R1 and Loongson-3B R2) has many enhancements, such as
>> 1325 FTLB, L1-VCache, EI/DI/Wait/Prefetch instruction, DSP/DSPr2 ASE, User
>> 1326 Local register, Read-Inhibit/Execute-Inhibit, SFB (Store Fill Buffer),
>> 1327 Fast TLB refill support, etc.
>> 1328
>> 1329 This option enable those enhancements which are not probed at run
>> 1330 time. If you want a generic kernel to run on all Loongson 3 machines,
>> 1331 please say 'N' here. If you want a high-performance kernel to run on
>> 1332 new Loongson-3 machines only, please say 'Y' here.
>> 1333
>> 1334 config CPU_LOONGSON3_WORKAROUNDS
>> 1335 bool "Loongson-3 LLSC Workarounds"
>> 1336 default y if SMP
>> 1337 depends on CPU_LOONGSON64
>> 1338 help
>> 1339 Loongson-3 processors have the llsc issues which require workarounds.
>> 1340 Without workarounds the system may hang unexpectedly.
>> 1341
>> 1342 Say Y, unless you know what you are doing.
>> 1343
>> 1344 config CPU_LOONGSON3_CPUCFG_EMULATION
>> 1345 bool "Emulate the CPUCFG instruction on older Loongson cores"
>> 1346 default y
>> 1347 depends on CPU_LOONGSON64
>> 1348 help
>> 1349 Loongson-3A R4 and newer have the CPUCFG instruction available for
>> 1350 userland to query CPU capabilities, much like CPUID on x86. This
>> 1351 option provides emulation of the instruction on older Loongson
>> 1352 cores, back to Loongson-3A1000.
>> 1353
>> 1354 If unsure, please say Y.
>> 1355
>> 1356 config CPU_LOONGSON2E
>> 1357 bool "Loongson 2E"
>> 1358 depends on SYS_HAS_CPU_LOONGSON2E
>> 1359 select CPU_LOONGSON2EF
>> 1360 help
>> 1361 The Loongson 2E processor implements the MIPS III instruction set
>> 1362 with many extensions.
>> 1363
>> 1364 It has an internal FPGA northbridge, which is compatible to
>> 1365 bonito64.
>> 1366
>> 1367 config CPU_LOONGSON2F
>> 1368 bool "Loongson 2F"
>> 1369 depends on SYS_HAS_CPU_LOONGSON2F
>> 1370 select CPU_LOONGSON2EF
>> 1371 select GPIOLIB
>> 1372 help
>> 1373 The Loongson 2F processor implements the MIPS III instruction set
>> 1374 with many extensions.
>> 1375
>> 1376 Loongson2F have built-in DDR2 and PCIX controller. The PCIX controller
>> 1377 have a similar programming interface with FPGA northbridge used in
>> 1378 Loongson2E.
>> 1379
>> 1380 config CPU_LOONGSON1B
>> 1381 bool "Loongson 1B"
>> 1382 depends on SYS_HAS_CPU_LOONGSON1B
>> 1383 select CPU_LOONGSON32
>> 1384 select LEDS_GPIO_REGISTER
>> 1385 help
>> 1386 The Loongson 1B is a 32-bit SoC, which implements the MIPS32
>> 1387 Release 1 instruction set and part of the MIPS32 Release 2
>> 1388 instruction set.
>> 1389
>> 1390 config CPU_LOONGSON1C
>> 1391 bool "Loongson 1C"
>> 1392 depends on SYS_HAS_CPU_LOONGSON1C
>> 1393 select CPU_LOONGSON32
>> 1394 select LEDS_GPIO_REGISTER
>> 1395 help
>> 1396 The Loongson 1C is a 32-bit SoC, which implements the MIPS32
>> 1397 Release 1 instruction set and part of the MIPS32 Release 2
>> 1398 instruction set.
>> 1399
>> 1400 config CPU_MIPS32_R1
>> 1401 bool "MIPS32 Release 1"
>> 1402 depends on SYS_HAS_CPU_MIPS32_R1
>> 1403 select CPU_HAS_PREFETCH
>> 1404 select CPU_SUPPORTS_32BIT_KERNEL
>> 1405 select CPU_SUPPORTS_HIGHMEM
>> 1406 help
>> 1407 Choose this option to build a kernel for release 1 or later of the
>> 1408 MIPS32 architecture. Most modern embedded systems with a 32-bit
>> 1409 MIPS processor are based on a MIPS32 processor. If you know the
>> 1410 specific type of processor in your system, choose those that one
>> 1411 otherwise CPU_MIPS32_R1 is a safe bet for any MIPS32 system.
>> 1412 Release 2 of the MIPS32 architecture is available since several
>> 1413 years so chances are you even have a MIPS32 Release 2 processor
>> 1414 in which case you should choose CPU_MIPS32_R2 instead for better
>> 1415 performance.
>> 1416
>> 1417 config CPU_MIPS32_R2
>> 1418 bool "MIPS32 Release 2"
>> 1419 depends on SYS_HAS_CPU_MIPS32_R2
>> 1420 select CPU_HAS_PREFETCH
>> 1421 select CPU_SUPPORTS_32BIT_KERNEL
>> 1422 select CPU_SUPPORTS_HIGHMEM
>> 1423 select CPU_SUPPORTS_MSA
>> 1424 select HAVE_KVM
>> 1425 help
>> 1426 Choose this option to build a kernel for release 2 or later of the
>> 1427 MIPS32 architecture. Most modern embedded systems with a 32-bit
>> 1428 MIPS processor are based on a MIPS32 processor. If you know the
>> 1429 specific type of processor in your system, choose those that one
>> 1430 otherwise CPU_MIPS32_R1 is a safe bet for any MIPS32 system.
>> 1431
>> 1432 config CPU_MIPS32_R5
>> 1433 bool "MIPS32 Release 5"
>> 1434 depends on SYS_HAS_CPU_MIPS32_R5
>> 1435 select CPU_HAS_PREFETCH
>> 1436 select CPU_SUPPORTS_32BIT_KERNEL
>> 1437 select CPU_SUPPORTS_HIGHMEM
>> 1438 select CPU_SUPPORTS_MSA
>> 1439 select HAVE_KVM
>> 1440 select MIPS_O32_FP64_SUPPORT
>> 1441 help
>> 1442 Choose this option to build a kernel for release 5 or later of the
>> 1443 MIPS32 architecture. New MIPS processors, starting with the Warrior
>> 1444 family, are based on a MIPS32r5 processor. If you own an older
>> 1445 processor, you probably need to select MIPS32r1 or MIPS32r2 instead.
>> 1446
>> 1447 config CPU_MIPS32_R6
>> 1448 bool "MIPS32 Release 6"
>> 1449 depends on SYS_HAS_CPU_MIPS32_R6
>> 1450 select CPU_HAS_PREFETCH
>> 1451 select CPU_NO_LOAD_STORE_LR
>> 1452 select CPU_SUPPORTS_32BIT_KERNEL
>> 1453 select CPU_SUPPORTS_HIGHMEM
>> 1454 select CPU_SUPPORTS_MSA
>> 1455 select HAVE_KVM
>> 1456 select MIPS_O32_FP64_SUPPORT
>> 1457 help
>> 1458 Choose this option to build a kernel for release 6 or later of the
>> 1459 MIPS32 architecture. New MIPS processors, starting with the Warrior
>> 1460 family, are based on a MIPS32r6 processor. If you own an older
>> 1461 processor, you probably need to select MIPS32r1 or MIPS32r2 instead.
>> 1462
>> 1463 config CPU_MIPS64_R1
>> 1464 bool "MIPS64 Release 1"
>> 1465 depends on SYS_HAS_CPU_MIPS64_R1
>> 1466 select CPU_HAS_PREFETCH
>> 1467 select CPU_SUPPORTS_32BIT_KERNEL
>> 1468 select CPU_SUPPORTS_64BIT_KERNEL
>> 1469 select CPU_SUPPORTS_HIGHMEM
>> 1470 select CPU_SUPPORTS_HUGEPAGES
>> 1471 help
>> 1472 Choose this option to build a kernel for release 1 or later of the
>> 1473 MIPS64 architecture. Many modern embedded systems with a 64-bit
>> 1474 MIPS processor are based on a MIPS64 processor. If you know the
>> 1475 specific type of processor in your system, choose those that one
>> 1476 otherwise CPU_MIPS64_R1 is a safe bet for any MIPS64 system.
>> 1477 Release 2 of the MIPS64 architecture is available since several
>> 1478 years so chances are you even have a MIPS64 Release 2 processor
>> 1479 in which case you should choose CPU_MIPS64_R2 instead for better
>> 1480 performance.
>> 1481
>> 1482 config CPU_MIPS64_R2
>> 1483 bool "MIPS64 Release 2"
>> 1484 depends on SYS_HAS_CPU_MIPS64_R2
>> 1485 select CPU_HAS_PREFETCH
>> 1486 select CPU_SUPPORTS_32BIT_KERNEL
>> 1487 select CPU_SUPPORTS_64BIT_KERNEL
>> 1488 select CPU_SUPPORTS_HIGHMEM
>> 1489 select CPU_SUPPORTS_HUGEPAGES
>> 1490 select CPU_SUPPORTS_MSA
>> 1491 select HAVE_KVM
>> 1492 help
>> 1493 Choose this option to build a kernel for release 2 or later of the
>> 1494 MIPS64 architecture. Many modern embedded systems with a 64-bit
>> 1495 MIPS processor are based on a MIPS64 processor. If you know the
>> 1496 specific type of processor in your system, choose those that one
>> 1497 otherwise CPU_MIPS64_R1 is a safe bet for any MIPS64 system.
>> 1498
>> 1499 config CPU_MIPS64_R5
>> 1500 bool "MIPS64 Release 5"
>> 1501 depends on SYS_HAS_CPU_MIPS64_R5
>> 1502 select CPU_HAS_PREFETCH
>> 1503 select CPU_SUPPORTS_32BIT_KERNEL
>> 1504 select CPU_SUPPORTS_64BIT_KERNEL
>> 1505 select CPU_SUPPORTS_HIGHMEM
>> 1506 select CPU_SUPPORTS_HUGEPAGES
>> 1507 select CPU_SUPPORTS_MSA
>> 1508 select MIPS_O32_FP64_SUPPORT if 32BIT || MIPS32_O32
>> 1509 select HAVE_KVM
>> 1510 help
>> 1511 Choose this option to build a kernel for release 5 or later of the
>> 1512 MIPS64 architecture. This is a intermediate MIPS architecture
>> 1513 release partly implementing release 6 features. Though there is no
>> 1514 any hardware known to be based on this release.
>> 1515
>> 1516 config CPU_MIPS64_R6
>> 1517 bool "MIPS64 Release 6"
>> 1518 depends on SYS_HAS_CPU_MIPS64_R6
>> 1519 select CPU_HAS_PREFETCH
>> 1520 select CPU_NO_LOAD_STORE_LR
>> 1521 select CPU_SUPPORTS_32BIT_KERNEL
>> 1522 select CPU_SUPPORTS_64BIT_KERNEL
>> 1523 select CPU_SUPPORTS_HIGHMEM
>> 1524 select CPU_SUPPORTS_HUGEPAGES
>> 1525 select CPU_SUPPORTS_MSA
>> 1526 select MIPS_O32_FP64_SUPPORT if 32BIT || MIPS32_O32
>> 1527 select HAVE_KVM
>> 1528 help
>> 1529 Choose this option to build a kernel for release 6 or later of the
>> 1530 MIPS64 architecture. New MIPS processors, starting with the Warrior
>> 1531 family, are based on a MIPS64r6 processor. If you own an older
>> 1532 processor, you probably need to select MIPS64r1 or MIPS64r2 instead.
>> 1533
>> 1534 config CPU_P5600
>> 1535 bool "MIPS Warrior P5600"
>> 1536 depends on SYS_HAS_CPU_P5600
>> 1537 select CPU_HAS_PREFETCH
>> 1538 select CPU_SUPPORTS_32BIT_KERNEL
>> 1539 select CPU_SUPPORTS_HIGHMEM
>> 1540 select CPU_SUPPORTS_MSA
>> 1541 select CPU_SUPPORTS_CPUFREQ
>> 1542 select CPU_MIPSR2_IRQ_VI
>> 1543 select CPU_MIPSR2_IRQ_EI
>> 1544 select HAVE_KVM
>> 1545 select MIPS_O32_FP64_SUPPORT
>> 1546 help
>> 1547 Choose this option to build a kernel for MIPS Warrior P5600 CPU.
>> 1548 It's based on MIPS32r5 ISA with XPA, EVA, dual/quad issue exec pipes,
>> 1549 MMU with two-levels TLB, UCA, MSA, MDU core level features and system
>> 1550 level features like up to six P5600 calculation cores, CM2 with L2
>> 1551 cache, IOCU/IOMMU (though might be unused depending on the system-
>> 1552 specific IP core configuration), GIC, CPC, virtualisation module,
>> 1553 eJTAG and PDtrace.
>> 1554
>> 1555 config CPU_R3000
>> 1556 bool "R3000"
>> 1557 depends on SYS_HAS_CPU_R3000
>> 1558 select CPU_HAS_WB
>> 1559 select CPU_R3K_TLB
>> 1560 select CPU_SUPPORTS_32BIT_KERNEL
>> 1561 select CPU_SUPPORTS_HIGHMEM
>> 1562 help
>> 1563 Please make sure to pick the right CPU type. Linux/MIPS is not
>> 1564 designed to be generic, i.e. Kernels compiled for R3000 CPUs will
>> 1565 *not* work on R4000 machines and vice versa. However, since most
>> 1566 of the supported machines have an R4000 (or similar) CPU, R4x00
>> 1567 might be a safe bet. If the resulting kernel does not work,
>> 1568 try to recompile with R3000.
>> 1569
>> 1570 config CPU_R4300
>> 1571 bool "R4300"
>> 1572 depends on SYS_HAS_CPU_R4300
>> 1573 select CPU_SUPPORTS_32BIT_KERNEL
>> 1574 select CPU_SUPPORTS_64BIT_KERNEL
>> 1575 help
>> 1576 MIPS Technologies R4300-series processors.
>> 1577
>> 1578 config CPU_R4X00
>> 1579 bool "R4x00"
>> 1580 depends on SYS_HAS_CPU_R4X00
>> 1581 select CPU_SUPPORTS_32BIT_KERNEL
>> 1582 select CPU_SUPPORTS_64BIT_KERNEL
>> 1583 select CPU_SUPPORTS_HUGEPAGES
>> 1584 help
>> 1585 MIPS Technologies R4000-series processors other than 4300, including
>> 1586 the R4000, R4400, R4600, and 4700.
>> 1587
>> 1588 config CPU_TX49XX
>> 1589 bool "R49XX"
>> 1590 depends on SYS_HAS_CPU_TX49XX
>> 1591 select CPU_HAS_PREFETCH
>> 1592 select CPU_SUPPORTS_32BIT_KERNEL
>> 1593 select CPU_SUPPORTS_64BIT_KERNEL
>> 1594 select CPU_SUPPORTS_HUGEPAGES
>> 1595
>> 1596 config CPU_R5000
>> 1597 bool "R5000"
>> 1598 depends on SYS_HAS_CPU_R5000
>> 1599 select CPU_SUPPORTS_32BIT_KERNEL
>> 1600 select CPU_SUPPORTS_64BIT_KERNEL
>> 1601 select CPU_SUPPORTS_HUGEPAGES
>> 1602 help
>> 1603 MIPS Technologies R5000-series processors other than the Nevada.
>> 1604
>> 1605 config CPU_R5500
>> 1606 bool "R5500"
>> 1607 depends on SYS_HAS_CPU_R5500
>> 1608 select CPU_SUPPORTS_32BIT_KERNEL
>> 1609 select CPU_SUPPORTS_64BIT_KERNEL
>> 1610 select CPU_SUPPORTS_HUGEPAGES
>> 1611 help
>> 1612 NEC VR5500 and VR5500A series processors implement 64-bit MIPS IV
>> 1613 instruction set.
>> 1614
>> 1615 config CPU_NEVADA
>> 1616 bool "RM52xx"
>> 1617 depends on SYS_HAS_CPU_NEVADA
>> 1618 select CPU_SUPPORTS_32BIT_KERNEL
>> 1619 select CPU_SUPPORTS_64BIT_KERNEL
>> 1620 select CPU_SUPPORTS_HUGEPAGES
>> 1621 help
>> 1622 QED / PMC-Sierra RM52xx-series ("Nevada") processors.
>> 1623
>> 1624 config CPU_R10000
>> 1625 bool "R10000"
>> 1626 depends on SYS_HAS_CPU_R10000
>> 1627 select CPU_HAS_PREFETCH
>> 1628 select CPU_SUPPORTS_32BIT_KERNEL
>> 1629 select CPU_SUPPORTS_64BIT_KERNEL
>> 1630 select CPU_SUPPORTS_HIGHMEM
>> 1631 select CPU_SUPPORTS_HUGEPAGES
>> 1632 help
>> 1633 MIPS Technologies R10000-series processors.
>> 1634
>> 1635 config CPU_RM7000
>> 1636 bool "RM7000"
>> 1637 depends on SYS_HAS_CPU_RM7000
>> 1638 select CPU_HAS_PREFETCH
>> 1639 select CPU_SUPPORTS_32BIT_KERNEL
>> 1640 select CPU_SUPPORTS_64BIT_KERNEL
>> 1641 select CPU_SUPPORTS_HIGHMEM
>> 1642 select CPU_SUPPORTS_HUGEPAGES
>> 1643
>> 1644 config CPU_SB1
>> 1645 bool "SB1"
>> 1646 depends on SYS_HAS_CPU_SB1
>> 1647 select CPU_SUPPORTS_32BIT_KERNEL
>> 1648 select CPU_SUPPORTS_64BIT_KERNEL
>> 1649 select CPU_SUPPORTS_HIGHMEM
>> 1650 select CPU_SUPPORTS_HUGEPAGES
>> 1651 select WEAK_ORDERING
>> 1652
>> 1653 config CPU_CAVIUM_OCTEON
>> 1654 bool "Cavium Octeon processor"
>> 1655 depends on SYS_HAS_CPU_CAVIUM_OCTEON
>> 1656 select CPU_HAS_PREFETCH
>> 1657 select CPU_SUPPORTS_64BIT_KERNEL
>> 1658 select WEAK_ORDERING
>> 1659 select CPU_SUPPORTS_HIGHMEM
>> 1660 select CPU_SUPPORTS_HUGEPAGES
>> 1661 select USB_EHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 1662 select USB_OHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 1663 select MIPS_L1_CACHE_SHIFT_7
>> 1664 select HAVE_KVM
>> 1665 help
>> 1666 The Cavium Octeon processor is a highly integrated chip containing
>> 1667 many ethernet hardware widgets for networking tasks. The processor
>> 1668 can have up to 16 Mips64v2 cores and 8 integrated gigabit ethernets.
>> 1669 Full details can be found at http://www.caviumnetworks.com.
>> 1670
>> 1671 config CPU_BMIPS
>> 1672 bool "Broadcom BMIPS"
>> 1673 depends on SYS_HAS_CPU_BMIPS
>> 1674 select CPU_MIPS32
>> 1675 select CPU_BMIPS32_3300 if SYS_HAS_CPU_BMIPS32_3300
>> 1676 select CPU_BMIPS4350 if SYS_HAS_CPU_BMIPS4350
>> 1677 select CPU_BMIPS4380 if SYS_HAS_CPU_BMIPS4380
>> 1678 select CPU_BMIPS5000 if SYS_HAS_CPU_BMIPS5000
>> 1679 select CPU_SUPPORTS_32BIT_KERNEL
>> 1680 select DMA_NONCOHERENT
>> 1681 select IRQ_MIPS_CPU
>> 1682 select SWAP_IO_SPACE
>> 1683 select WEAK_ORDERING
>> 1684 select CPU_SUPPORTS_HIGHMEM
>> 1685 select CPU_HAS_PREFETCH
>> 1686 select CPU_SUPPORTS_CPUFREQ
>> 1687 select MIPS_EXTERNAL_TIMER
>> 1688 select GENERIC_IRQ_MIGRATION if HOTPLUG_CPU
830 help 1689 help
831 This option adds the workaround for !! 1690 Support for BMIPS32/3300/4350/4380 and BMIPS5000 processors.
832 Affected Cortex-A510 (r0p0 to r1p1) <<
833 BFMMLA or VMMLA instructions in rare <<
834 A510 CPUs are using shared neon hard <<
835 discoverable by the kernel, hide the <<
836 user-space should not be using these <<
837 1691
838 If unsure, say Y. !! 1692 endchoice
839 1693
840 config ARM64_ERRATUM_2119858 !! 1694 config CPU_MIPS32_3_5_FEATURES
841 bool "Cortex-A710/X2: 2119858: workaro !! 1695 bool "MIPS32 Release 3.5 Features"
842 default y !! 1696 depends on SYS_HAS_CPU_MIPS32_R3_5
843 depends on CORESIGHT_TRBE !! 1697 depends on CPU_MIPS32_R2 || CPU_MIPS32_R5 || CPU_MIPS32_R6 || \
844 select ARM64_WORKAROUND_TRBE_OVERWRITE !! 1698 CPU_P5600
>> 1699 help
>> 1700 Choose this option to build a kernel for release 2 or later of the
>> 1701 MIPS32 architecture including features from the 3.5 release such as
>> 1702 support for Enhanced Virtual Addressing (EVA).
>> 1703
>> 1704 config CPU_MIPS32_3_5_EVA
>> 1705 bool "Enhanced Virtual Addressing (EVA)"
>> 1706 depends on CPU_MIPS32_3_5_FEATURES
>> 1707 select EVA
>> 1708 default y
>> 1709 help
>> 1710 Choose this option if you want to enable the Enhanced Virtual
>> 1711 Addressing (EVA) on your MIPS32 core (such as proAptiv).
>> 1712 One of its primary benefits is an increase in the maximum size
>> 1713 of lowmem (up to 3GB). If unsure, say 'N' here.
>> 1714
>> 1715 config CPU_MIPS32_R5_FEATURES
>> 1716 bool "MIPS32 Release 5 Features"
>> 1717 depends on SYS_HAS_CPU_MIPS32_R5
>> 1718 depends on CPU_MIPS32_R2 || CPU_MIPS32_R5 || CPU_P5600
>> 1719 help
>> 1720 Choose this option to build a kernel for release 2 or later of the
>> 1721 MIPS32 architecture including features from release 5 such as
>> 1722 support for Extended Physical Addressing (XPA).
>> 1723
>> 1724 config CPU_MIPS32_R5_XPA
>> 1725 bool "Extended Physical Addressing (XPA)"
>> 1726 depends on CPU_MIPS32_R5_FEATURES
>> 1727 depends on !EVA
>> 1728 depends on !PAGE_SIZE_4KB
>> 1729 depends on SYS_SUPPORTS_HIGHMEM
>> 1730 select XPA
>> 1731 select HIGHMEM
>> 1732 select PHYS_ADDR_T_64BIT
>> 1733 default n
845 help 1734 help
846 This option adds the workaround for !! 1735 Choose this option if you want to enable the Extended Physical
>> 1736 Addressing (XPA) on your MIPS32 core (such as P5600 series). The
>> 1737 benefit is to increase physical addressing equal to or greater
>> 1738 than 40 bits. Note that this has the side effect of turning on
>> 1739 64-bit addressing which in turn makes the PTEs 64-bit in size.
>> 1740 If unsure, say 'N' here.
847 1741
848 Affected Cortex-A710/X2 cores could !! 1742 if CPU_LOONGSON2F
849 data at the base of the buffer (poin !! 1743 config CPU_NOP_WORKAROUNDS
850 the event of a WRAP event. !! 1744 bool
851 <<
852 Work around the issue by always maki <<
853 256 bytes before enabling the buffer <<
854 the buffer with ETM ignore packets u <<
855 1745
856 If unsure, say Y. !! 1746 config CPU_JUMP_WORKAROUNDS
>> 1747 bool
857 1748
858 config ARM64_ERRATUM_2139208 !! 1749 config CPU_LOONGSON2F_WORKAROUNDS
859 bool "Neoverse-N2: 2139208: workaround !! 1750 bool "Loongson 2F Workarounds"
860 default y 1751 default y
861 depends on CORESIGHT_TRBE !! 1752 select CPU_NOP_WORKAROUNDS
862 select ARM64_WORKAROUND_TRBE_OVERWRITE !! 1753 select CPU_JUMP_WORKAROUNDS
863 help 1754 help
864 This option adds the workaround for !! 1755 Loongson 2F01 / 2F02 processors have the NOP & JUMP issues which
>> 1756 require workarounds. Without workarounds the system may hang
>> 1757 unexpectedly. For more information please refer to the gas
>> 1758 -mfix-loongson2f-nop and -mfix-loongson2f-jump options.
>> 1759
>> 1760 Loongson 2F03 and later have fixed these issues and no workarounds
>> 1761 are needed. The workarounds have no significant side effect on them
>> 1762 but may decrease the performance of the system so this option should
>> 1763 be disabled unless the kernel is intended to be run on 2F01 or 2F02
>> 1764 systems.
865 1765
866 Affected Neoverse-N2 cores could ove !! 1766 If unsure, please say Y.
867 data at the base of the buffer (poin !! 1767 endif # CPU_LOONGSON2F
868 the event of a WRAP event. <<
869 <<
870 Work around the issue by always maki <<
871 256 bytes before enabling the buffer <<
872 the buffer with ETM ignore packets u <<
873 <<
874 If unsure, say Y. <<
875 1768
876 config ARM64_WORKAROUND_TSB_FLUSH_FAILURE !! 1769 config SYS_SUPPORTS_ZBOOT
877 bool 1770 bool
>> 1771 select HAVE_KERNEL_GZIP
>> 1772 select HAVE_KERNEL_BZIP2
>> 1773 select HAVE_KERNEL_LZ4
>> 1774 select HAVE_KERNEL_LZMA
>> 1775 select HAVE_KERNEL_LZO
>> 1776 select HAVE_KERNEL_XZ
>> 1777 select HAVE_KERNEL_ZSTD
878 1778
879 config ARM64_ERRATUM_2054223 !! 1779 config SYS_SUPPORTS_ZBOOT_UART16550
880 bool "Cortex-A710: 2054223: workaround !! 1780 bool
881 default y !! 1781 select SYS_SUPPORTS_ZBOOT
882 select ARM64_WORKAROUND_TSB_FLUSH_FAIL <<
883 help <<
884 Enable workaround for ARM Cortex-A71 <<
885 1782
886 Affected cores may fail to flush the !! 1783 config SYS_SUPPORTS_ZBOOT_UART_PROM
887 the PE is in trace prohibited state. !! 1784 bool
888 of the trace cached. !! 1785 select SYS_SUPPORTS_ZBOOT
889 1786
890 Workaround is to issue two TSB conse !! 1787 config CPU_LOONGSON2EF
>> 1788 bool
>> 1789 select CPU_SUPPORTS_32BIT_KERNEL
>> 1790 select CPU_SUPPORTS_64BIT_KERNEL
>> 1791 select CPU_SUPPORTS_HIGHMEM
>> 1792 select CPU_SUPPORTS_HUGEPAGES
>> 1793 select ARCH_HAS_PHYS_TO_DMA
891 1794
892 If unsure, say Y. !! 1795 config CPU_LOONGSON32
>> 1796 bool
>> 1797 select CPU_MIPS32
>> 1798 select CPU_MIPSR2
>> 1799 select CPU_HAS_PREFETCH
>> 1800 select CPU_SUPPORTS_32BIT_KERNEL
>> 1801 select CPU_SUPPORTS_HIGHMEM
>> 1802 select CPU_SUPPORTS_CPUFREQ
893 1803
894 config ARM64_ERRATUM_2067961 !! 1804 config CPU_BMIPS32_3300
895 bool "Neoverse-N2: 2067961: workaround !! 1805 select SMP_UP if SMP
896 default y !! 1806 bool
897 select ARM64_WORKAROUND_TSB_FLUSH_FAIL <<
898 help <<
899 Enable workaround for ARM Neoverse-N <<
900 1807
901 Affected cores may fail to flush the !! 1808 config CPU_BMIPS4350
902 the PE is in trace prohibited state. !! 1809 bool
903 of the trace cached. !! 1810 select SYS_SUPPORTS_SMP
>> 1811 select SYS_SUPPORTS_HOTPLUG_CPU
904 1812
905 Workaround is to issue two TSB conse !! 1813 config CPU_BMIPS4380
>> 1814 bool
>> 1815 select MIPS_L1_CACHE_SHIFT_6
>> 1816 select SYS_SUPPORTS_SMP
>> 1817 select SYS_SUPPORTS_HOTPLUG_CPU
>> 1818 select CPU_HAS_RIXI
906 1819
907 If unsure, say Y. !! 1820 config CPU_BMIPS5000
>> 1821 bool
>> 1822 select MIPS_CPU_SCACHE
>> 1823 select MIPS_L1_CACHE_SHIFT_7
>> 1824 select SYS_SUPPORTS_SMP
>> 1825 select SYS_SUPPORTS_HOTPLUG_CPU
>> 1826 select CPU_HAS_RIXI
908 1827
909 config ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANG !! 1828 config SYS_HAS_CPU_LOONGSON64
910 bool 1829 bool
>> 1830 select CPU_SUPPORTS_CPUFREQ
>> 1831 select CPU_HAS_RIXI
911 1832
912 config ARM64_ERRATUM_2253138 !! 1833 config SYS_HAS_CPU_LOONGSON2E
913 bool "Neoverse-N2: 2253138: workaround !! 1834 bool
914 depends on CORESIGHT_TRBE <<
915 default y <<
916 select ARM64_WORKAROUND_TRBE_WRITE_OUT <<
917 help <<
918 This option adds the workaround for <<
919 1835
920 Affected Neoverse-N2 cores might wri !! 1836 config SYS_HAS_CPU_LOONGSON2F
921 for TRBE. Under some conditions, the !! 1837 bool
922 virtually addressed page following t !! 1838 select CPU_SUPPORTS_CPUFREQ
923 (i.e., the TRBLIMITR_EL1.LIMIT), ins !! 1839 select CPU_SUPPORTS_ADDRWINCFG if 64BIT
924 1840
925 Work around this in the driver by al !! 1841 config SYS_HAS_CPU_LOONGSON1B
926 page beyond the TRBLIMITR_EL1.LIMIT, !! 1842 bool
927 1843
928 If unsure, say Y. !! 1844 config SYS_HAS_CPU_LOONGSON1C
>> 1845 bool
929 1846
930 config ARM64_ERRATUM_2224489 !! 1847 config SYS_HAS_CPU_MIPS32_R1
931 bool "Cortex-A710/X2: 2224489: workaro !! 1848 bool
932 depends on CORESIGHT_TRBE <<
933 default y <<
934 select ARM64_WORKAROUND_TRBE_WRITE_OUT <<
935 help <<
936 This option adds the workaround for <<
937 1849
938 Affected Cortex-A710/X2 cores might !! 1850 config SYS_HAS_CPU_MIPS32_R2
939 for TRBE. Under some conditions, the !! 1851 bool
940 virtually addressed page following t <<
941 (i.e., the TRBLIMITR_EL1.LIMIT), ins <<
942 1852
943 Work around this in the driver by al !! 1853 config SYS_HAS_CPU_MIPS32_R3_5
944 page beyond the TRBLIMITR_EL1.LIMIT, !! 1854 bool
945 1855
946 If unsure, say Y. !! 1856 config SYS_HAS_CPU_MIPS32_R5
>> 1857 bool
>> 1858 select ARCH_HAS_SYNC_DMA_FOR_CPU if DMA_NONCOHERENT
947 1859
948 config ARM64_ERRATUM_2441009 !! 1860 config SYS_HAS_CPU_MIPS32_R6
949 bool "Cortex-A510: Completion of affec !! 1861 bool
950 select ARM64_WORKAROUND_REPEAT_TLBI !! 1862 select ARCH_HAS_SYNC_DMA_FOR_CPU if DMA_NONCOHERENT
951 help <<
952 This option adds a workaround for AR <<
953 <<
954 Under very rare circumstances, affec <<
955 may not handle a race between a brea <<
956 CPU, and another CPU accessing the s <<
957 store to a page that has been unmapp <<
958 1863
959 Work around this by adding the affec !! 1864 config SYS_HAS_CPU_MIPS64_R1
960 TLB sequences to be done twice. !! 1865 bool
961 1866
962 If unsure, say N. !! 1867 config SYS_HAS_CPU_MIPS64_R2
>> 1868 bool
963 1869
964 config ARM64_ERRATUM_2064142 !! 1870 config SYS_HAS_CPU_MIPS64_R5
965 bool "Cortex-A510: 2064142: workaround !! 1871 bool
966 depends on CORESIGHT_TRBE !! 1872 select ARCH_HAS_SYNC_DMA_FOR_CPU if DMA_NONCOHERENT
967 default y <<
968 help <<
969 This option adds the workaround for <<
970 1873
971 Affected Cortex-A510 core might fail !! 1874 config SYS_HAS_CPU_MIPS64_R6
972 TRBE has been disabled. Under some c !! 1875 bool
973 writes into TRBE registers TRBLIMITR !! 1876 select ARCH_HAS_SYNC_DMA_FOR_CPU if DMA_NONCOHERENT
974 and TRBTRG_EL1 will be ignored and w <<
975 <<
976 Work around this in the driver by ex <<
977 is stopped and before performing a s <<
978 registers. <<
979 1877
980 If unsure, say Y. !! 1878 config SYS_HAS_CPU_P5600
>> 1879 bool
>> 1880 select ARCH_HAS_SYNC_DMA_FOR_CPU if DMA_NONCOHERENT
981 1881
982 config ARM64_ERRATUM_2038923 !! 1882 config SYS_HAS_CPU_R3000
983 bool "Cortex-A510: 2038923: workaround !! 1883 bool
984 depends on CORESIGHT_TRBE <<
985 default y <<
986 help <<
987 This option adds the workaround for <<
988 1884
989 Affected Cortex-A510 core might caus !! 1885 config SYS_HAS_CPU_R4300
990 prohibited within the CPU. As a resu !! 1886 bool
991 might be corrupted. This happens aft <<
992 TRBLIMITR_EL1.E, followed by just a <<
993 execution changes from a context, in <<
994 isn't, or vice versa. In these menti <<
995 is prohibited is inconsistent betwee <<
996 the trace buffer state might be corr <<
997 <<
998 Work around this in the driver by pr <<
999 trace is prohibited or not based on <<
1000 change to TRBLIMITR_EL1.E with at l <<
1001 two ISB instructions if no ERET is <<
1002 1887
1003 If unsure, say Y. !! 1888 config SYS_HAS_CPU_R4X00
>> 1889 bool
1004 1890
1005 config ARM64_ERRATUM_1902691 !! 1891 config SYS_HAS_CPU_TX49XX
1006 bool "Cortex-A510: 1902691: workaroun !! 1892 bool
1007 depends on CORESIGHT_TRBE <<
1008 default y <<
1009 help <<
1010 This option adds the workaround for <<
1011 1893
1012 Affected Cortex-A510 core might cau !! 1894 config SYS_HAS_CPU_R5000
1013 into the memory. Effectively TRBE i !! 1895 bool
1014 trace data. <<
1015 <<
1016 Work around this problem in the dri <<
1017 affected cpus. The firmware must ha <<
1018 on such implementations. This will <<
1019 do this already. <<
1020 1896
1021 If unsure, say Y. !! 1897 config SYS_HAS_CPU_R5500
>> 1898 bool
1022 1899
1023 config ARM64_ERRATUM_2457168 !! 1900 config SYS_HAS_CPU_NEVADA
1024 bool "Cortex-A510: 2457168: workaroun !! 1901 bool
1025 depends on ARM64_AMU_EXTN <<
1026 default y <<
1027 help <<
1028 This option adds the workaround for <<
1029 1902
1030 The AMU counter AMEVCNTR01 (constan !! 1903 config SYS_HAS_CPU_R10000
1031 as the system counter. On affected !! 1904 bool
1032 incorrectly giving a significantly !! 1905 select ARCH_HAS_SYNC_DMA_FOR_CPU if DMA_NONCOHERENT
1033 <<
1034 Work around this problem by returni <<
1035 key locations that results in disab <<
1036 is the same to firmware disabling a <<
1037 1906
1038 If unsure, say Y. !! 1907 config SYS_HAS_CPU_RM7000
>> 1908 bool
1039 1909
1040 config ARM64_ERRATUM_2645198 !! 1910 config SYS_HAS_CPU_SB1
1041 bool "Cortex-A715: 2645198: Workaroun !! 1911 bool
1042 default y <<
1043 help <<
1044 This option adds the workaround for <<
1045 1912
1046 If a Cortex-A715 cpu sees a page ma !! 1913 config SYS_HAS_CPU_CAVIUM_OCTEON
1047 to non-executable, it may corrupt t !! 1914 bool
1048 next instruction abort caused by pe <<
1049 <<
1050 Only user-space does executable to <<
1051 mprotect() system call. Workaround <<
1052 TLB invalidation, for all changes t <<
1053 1915
1054 If unsure, say Y. !! 1916 config SYS_HAS_CPU_BMIPS
>> 1917 bool
1055 1918
1056 config ARM64_WORKAROUND_SPECULATIVE_UNPRIV_LO !! 1919 config SYS_HAS_CPU_BMIPS32_3300
1057 bool 1920 bool
>> 1921 select SYS_HAS_CPU_BMIPS
1058 1922
1059 config ARM64_ERRATUM_2966298 !! 1923 config SYS_HAS_CPU_BMIPS4350
1060 bool "Cortex-A520: 2966298: workaroun !! 1924 bool
1061 select ARM64_WORKAROUND_SPECULATIVE_U !! 1925 select SYS_HAS_CPU_BMIPS
1062 default y <<
1063 help <<
1064 This option adds the workaround for <<
1065 1926
1066 On an affected Cortex-A520 core, a !! 1927 config SYS_HAS_CPU_BMIPS4380
1067 load might leak data from a privile !! 1928 bool
>> 1929 select SYS_HAS_CPU_BMIPS
1068 1930
1069 Work around this problem by executi !! 1931 config SYS_HAS_CPU_BMIPS5000
>> 1932 bool
>> 1933 select SYS_HAS_CPU_BMIPS
>> 1934 select ARCH_HAS_SYNC_DMA_FOR_CPU
1070 1935
1071 If unsure, say Y. !! 1936 #
>> 1937 # CPU may reorder R->R, R->W, W->R, W->W
>> 1938 # Reordering beyond LL and SC is handled in WEAK_REORDERING_BEYOND_LLSC
>> 1939 #
>> 1940 config WEAK_ORDERING
>> 1941 bool
1072 1942
1073 config ARM64_ERRATUM_3117295 !! 1943 #
1074 bool "Cortex-A510: 3117295: workaroun !! 1944 # CPU may reorder reads and writes beyond LL/SC
1075 select ARM64_WORKAROUND_SPECULATIVE_U !! 1945 # CPU may reorder R->LL, R->LL, W->LL, W->LL, R->SC, R->SC, W->SC, W->SC
1076 default y !! 1946 #
1077 help !! 1947 config WEAK_REORDERING_BEYOND_LLSC
1078 This option adds the workaround for !! 1948 bool
>> 1949 endmenu
1079 1950
1080 On an affected Cortex-A510 core, a !! 1951 #
1081 load might leak data from a privile !! 1952 # These two indicate any level of the MIPS32 and MIPS64 architecture
>> 1953 #
>> 1954 config CPU_MIPS32
>> 1955 bool
>> 1956 default y if CPU_MIPS32_R1 || CPU_MIPS32_R2 || CPU_MIPS32_R5 || \
>> 1957 CPU_MIPS32_R6 || CPU_P5600
1082 1958
1083 Work around this problem by executi !! 1959 config CPU_MIPS64
>> 1960 bool
>> 1961 default y if CPU_MIPS64_R1 || CPU_MIPS64_R2 || CPU_MIPS64_R5 || \
>> 1962 CPU_MIPS64_R6 || CPU_LOONGSON64 || CPU_CAVIUM_OCTEON
1084 1963
1085 If unsure, say Y. !! 1964 #
>> 1965 # These indicate the revision of the architecture
>> 1966 #
>> 1967 config CPU_MIPSR1
>> 1968 bool
>> 1969 default y if CPU_MIPS32_R1 || CPU_MIPS64_R1
1086 1970
1087 config ARM64_ERRATUM_3194386 !! 1971 config CPU_MIPSR2
1088 bool "Cortex-*/Neoverse-*: workaround !! 1972 bool
1089 default y !! 1973 default y if CPU_MIPS32_R2 || CPU_MIPS64_R2 || CPU_CAVIUM_OCTEON
1090 help !! 1974 select CPU_HAS_RIXI
1091 This option adds the workaround for !! 1975 select CPU_HAS_DIEI if !CPU_DIEI_BROKEN
>> 1976 select MIPS_SPRAM
1092 1977
1093 * ARM Cortex-A76 erratum 3324349 !! 1978 config CPU_MIPSR5
1094 * ARM Cortex-A77 erratum 3324348 !! 1979 bool
1095 * ARM Cortex-A78 erratum 3324344 !! 1980 default y if CPU_MIPS32_R5 || CPU_MIPS64_R5 || CPU_P5600
1096 * ARM Cortex-A78C erratum 3324346 !! 1981 select CPU_HAS_RIXI
1097 * ARM Cortex-A78C erratum 3324347 !! 1982 select CPU_HAS_DIEI if !CPU_DIEI_BROKEN
1098 * ARM Cortex-A710 erratam 3324338 !! 1983 select MIPS_SPRAM
1099 * ARM Cortex-A715 errartum 3456084 <<
1100 * ARM Cortex-A720 erratum 3456091 <<
1101 * ARM Cortex-A725 erratum 3456106 <<
1102 * ARM Cortex-X1 erratum 3324344 <<
1103 * ARM Cortex-X1C erratum 3324346 <<
1104 * ARM Cortex-X2 erratum 3324338 <<
1105 * ARM Cortex-X3 erratum 3324335 <<
1106 * ARM Cortex-X4 erratum 3194386 <<
1107 * ARM Cortex-X925 erratum 3324334 <<
1108 * ARM Neoverse-N1 erratum 3324349 <<
1109 * ARM Neoverse N2 erratum 3324339 <<
1110 * ARM Neoverse-N3 erratum 3456111 <<
1111 * ARM Neoverse-V1 erratum 3324341 <<
1112 * ARM Neoverse V2 erratum 3324336 <<
1113 * ARM Neoverse-V3 erratum 3312417 <<
1114 <<
1115 On affected cores "MSR SSBS, #0" in <<
1116 subsequent speculative instructions <<
1117 speculative store bypassing. <<
1118 <<
1119 Work around this problem by placing <<
1120 Instruction Synchronization Barrier <<
1121 SSBS. The presence of the SSBS spec <<
1122 from hwcaps and EL0 reads of ID_AA6 <<
1123 will use the PR_SPEC_STORE_BYPASS p <<
1124 1984
1125 If unsure, say Y. !! 1985 config CPU_MIPSR6
>> 1986 bool
>> 1987 default y if CPU_MIPS32_R6 || CPU_MIPS64_R6
>> 1988 select CPU_HAS_RIXI
>> 1989 select CPU_HAS_DIEI if !CPU_DIEI_BROKEN
>> 1990 select HAVE_ARCH_BITREVERSE
>> 1991 select MIPS_ASID_BITS_VARIABLE
>> 1992 select MIPS_CRC_SUPPORT
>> 1993 select MIPS_SPRAM
1126 1994
1127 config CAVIUM_ERRATUM_22375 !! 1995 config TARGET_ISA_REV
1128 bool "Cavium erratum 22375, 24313" !! 1996 int
1129 default y !! 1997 default 1 if CPU_MIPSR1
>> 1998 default 2 if CPU_MIPSR2
>> 1999 default 5 if CPU_MIPSR5
>> 2000 default 6 if CPU_MIPSR6
>> 2001 default 0
1130 help 2002 help
1131 Enable workaround for errata 22375 !! 2003 Reflects the ISA revision being targeted by the kernel build. This
>> 2004 is effectively the Kconfig equivalent of MIPS_ISA_REV.
1132 2005
1133 This implements two gicv3-its errat !! 2006 config EVA
1134 with a small impact affecting only !! 2007 bool
1135 2008
1136 erratum 22375: only alloc 8MB tab !! 2009 config XPA
1137 erratum 24313: ignore memory acce !! 2010 bool
1138 2011
1139 The fixes are in ITS initialization !! 2012 config SYS_SUPPORTS_32BIT_KERNEL
1140 type and table size provided by the !! 2013 bool
>> 2014 config SYS_SUPPORTS_64BIT_KERNEL
>> 2015 bool
>> 2016 config CPU_SUPPORTS_32BIT_KERNEL
>> 2017 bool
>> 2018 config CPU_SUPPORTS_64BIT_KERNEL
>> 2019 bool
>> 2020 config CPU_SUPPORTS_CPUFREQ
>> 2021 bool
>> 2022 config CPU_SUPPORTS_ADDRWINCFG
>> 2023 bool
>> 2024 config CPU_SUPPORTS_HUGEPAGES
>> 2025 bool
>> 2026 depends on !(32BIT && (PHYS_ADDR_T_64BIT || EVA))
>> 2027 config MIPS_PGD_C0_CONTEXT
>> 2028 bool
>> 2029 depends on 64BIT
>> 2030 default y if (CPU_MIPSR2 || CPU_MIPSR6)
1141 2031
1142 If unsure, say Y. !! 2032 #
>> 2033 # Set to y for ptrace access to watch registers.
>> 2034 #
>> 2035 config HARDWARE_WATCHPOINTS
>> 2036 bool
>> 2037 default y if CPU_MIPSR1 || CPU_MIPSR2 || CPU_MIPSR6
1143 2038
1144 config CAVIUM_ERRATUM_23144 !! 2039 menu "Kernel type"
1145 bool "Cavium erratum 23144: ITS SYNC <<
1146 depends on NUMA <<
1147 default y <<
1148 help <<
1149 ITS SYNC command hang for cross nod <<
1150 2040
1151 If unsure, say Y. !! 2041 choice
>> 2042 prompt "Kernel code model"
>> 2043 help
>> 2044 You should only select this option if you have a workload that
>> 2045 actually benefits from 64-bit processing or if your machine has
>> 2046 large memory. You will only be presented a single option in this
>> 2047 menu if your system does not support both 32-bit and 64-bit kernels.
>> 2048
>> 2049 config 32BIT
>> 2050 bool "32-bit kernel"
>> 2051 depends on CPU_SUPPORTS_32BIT_KERNEL && SYS_SUPPORTS_32BIT_KERNEL
>> 2052 select TRAD_SIGNALS
>> 2053 help
>> 2054 Select this option if you want to build a 32-bit kernel.
1152 2055
1153 config CAVIUM_ERRATUM_23154 !! 2056 config 64BIT
1154 bool "Cavium errata 23154 and 38545: !! 2057 bool "64-bit kernel"
1155 default y !! 2058 depends on CPU_SUPPORTS_64BIT_KERNEL && SYS_SUPPORTS_64BIT_KERNEL
1156 help 2059 help
1157 The ThunderX GICv3 implementation r !! 2060 Select this option if you want to build a 64-bit kernel.
1158 reading the IAR status to ensure da <<
1159 (access to icc_iar1_el1 is not sync <<
1160 <<
1161 It also suffers from erratum 38545 <<
1162 OcteonTX and OcteonTX2), resulting <<
1163 spuriously presented to the CPU int <<
1164 2061
1165 If unsure, say Y. !! 2062 endchoice
1166 2063
1167 config CAVIUM_ERRATUM_27456 !! 2064 config MIPS_VA_BITS_48
1168 bool "Cavium erratum 27456: Broadcast !! 2065 bool "48 bits virtual memory"
1169 default y !! 2066 depends on 64BIT
1170 help !! 2067 help
1171 On ThunderX T88 pass 1.x through 2. !! 2068 Support a maximum at least 48 bits of application virtual
1172 instructions may cause the icache t !! 2069 memory. Default is 40 bits or less, depending on the CPU.
1173 contains data for a non-current ASI !! 2070 For page sizes 16k and above, this option results in a small
1174 invalidate the icache when changing !! 2071 memory overhead for page tables. For 4k page size, a fourth
>> 2072 level of page tables is added which imposes both a memory
>> 2073 overhead as well as slower TLB fault handling.
1175 2074
1176 If unsure, say Y. !! 2075 If unsure, say N.
1177 2076
1178 config CAVIUM_ERRATUM_30115 !! 2077 config ZBOOT_LOAD_ADDRESS
1179 bool "Cavium erratum 30115: Guest may !! 2078 hex "Compressed kernel load address"
1180 default y !! 2079 default 0xffffffff80400000 if BCM47XX
>> 2080 default 0x0
>> 2081 depends on SYS_SUPPORTS_ZBOOT
1181 help 2082 help
1182 On ThunderX T88 pass 1.x through 2. !! 2083 The address to load compressed kernel, aka vmlinuz.
1183 1.2, and T83 Pass 1.0, KVM guest ex <<
1184 interrupts in host. Trapping both G <<
1185 accesses sidesteps the issue. <<
1186 2084
1187 If unsure, say Y. !! 2085 This is only used if non-zero.
1188 2086
1189 config CAVIUM_TX2_ERRATUM_219 !! 2087 choice
1190 bool "Cavium ThunderX2 erratum 219: P !! 2088 prompt "Kernel page size"
1191 default y !! 2089 default PAGE_SIZE_4KB
1192 help <<
1193 On Cavium ThunderX2, a load, store <<
1194 TTBR update and the corresponding c <<
1195 cause a spurious Data Abort to be d <<
1196 the CPU core. <<
1197 <<
1198 Work around the issue by avoiding t <<
1199 trapping KVM guest TTBRx_EL1 writes <<
1200 trap handler performs the correspon <<
1201 instruction and ensures context syn <<
1202 exception return. <<
1203 2090
1204 If unsure, say Y. !! 2091 config PAGE_SIZE_4KB
>> 2092 bool "4kB"
>> 2093 depends on !CPU_LOONGSON2EF && !CPU_LOONGSON64
>> 2094 help
>> 2095 This option select the standard 4kB Linux page size. On some
>> 2096 R3000-family processors this is the only available page size. Using
>> 2097 4kB page size will minimize memory consumption and is therefore
>> 2098 recommended for low memory systems.
>> 2099
>> 2100 config PAGE_SIZE_8KB
>> 2101 bool "8kB"
>> 2102 depends on CPU_CAVIUM_OCTEON
>> 2103 depends on !MIPS_VA_BITS_48
>> 2104 help
>> 2105 Using 8kB page size will result in higher performance kernel at
>> 2106 the price of higher memory consumption. This option is available
>> 2107 only on cnMIPS processors. Note that you will need a suitable Linux
>> 2108 distribution to support this.
>> 2109
>> 2110 config PAGE_SIZE_16KB
>> 2111 bool "16kB"
>> 2112 depends on !CPU_R3000
>> 2113 help
>> 2114 Using 16kB page size will result in higher performance kernel at
>> 2115 the price of higher memory consumption. This option is available on
>> 2116 all non-R3000 family processors. Note that you will need a suitable
>> 2117 Linux distribution to support this.
>> 2118
>> 2119 config PAGE_SIZE_32KB
>> 2120 bool "32kB"
>> 2121 depends on CPU_CAVIUM_OCTEON
>> 2122 depends on !MIPS_VA_BITS_48
>> 2123 help
>> 2124 Using 32kB page size will result in higher performance kernel at
>> 2125 the price of higher memory consumption. This option is available
>> 2126 only on cnMIPS cores. Note that you will need a suitable Linux
>> 2127 distribution to support this.
>> 2128
>> 2129 config PAGE_SIZE_64KB
>> 2130 bool "64kB"
>> 2131 depends on !CPU_R3000
>> 2132 help
>> 2133 Using 64kB page size will result in higher performance kernel at
>> 2134 the price of higher memory consumption. This option is available on
>> 2135 all non-R3000 family processor. Not that at the time of this
>> 2136 writing this option is still high experimental.
1205 2137
1206 config FUJITSU_ERRATUM_010001 !! 2138 endchoice
1207 bool "Fujitsu-A64FX erratum E#010001: <<
1208 default y <<
1209 help <<
1210 This option adds a workaround for F <<
1211 On some variants of the Fujitsu-A64 <<
1212 accesses may cause undefined fault <<
1213 This fault occurs under a specific <<
1214 load/store instruction performs an <<
1215 case-1 TTBR0_EL1 with TCR_EL1.NFD0 <<
1216 case-2 TTBR0_EL2 with TCR_EL2.NFD0 <<
1217 case-3 TTBR1_EL1 with TCR_EL1.NFD1 <<
1218 case-4 TTBR1_EL2 with TCR_EL2.NFD1 <<
1219 2139
1220 The workaround is to ensure these b !! 2140 config ARCH_FORCE_MAX_ORDER
1221 The workaround only affects the Fuj !! 2141 int "Maximum zone order"
>> 2142 range 14 64 if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_64KB
>> 2143 default "14" if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_64KB
>> 2144 range 13 64 if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_32KB
>> 2145 default "13" if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_32KB
>> 2146 range 12 64 if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_16KB
>> 2147 default "12" if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_16KB
>> 2148 range 0 64
>> 2149 default "11"
>> 2150 help
>> 2151 The kernel memory allocator divides physically contiguous memory
>> 2152 blocks into "zones", where each zone is a power of two number of
>> 2153 pages. This option selects the largest power of two that the kernel
>> 2154 keeps in the memory allocator. If you need to allocate very large
>> 2155 blocks of physically contiguous memory, then you may need to
>> 2156 increase this value.
1222 2157
1223 If unsure, say Y. !! 2158 This config option is actually maximum order plus one. For example,
>> 2159 a value of 11 means that the largest free memory block is 2^10 pages.
1224 2160
1225 config HISILICON_ERRATUM_161600802 !! 2161 The page size is not necessarily 4KB. Keep this in mind
1226 bool "Hip07 161600802: Erroneous redi !! 2162 when choosing a value for this option.
1227 default y <<
1228 help <<
1229 The HiSilicon Hip07 SoC uses the wr <<
1230 when issued ITS commands such as VM <<
1231 a 128kB offset to be applied to the <<
1232 2163
1233 If unsure, say Y. !! 2164 config BOARD_SCACHE
>> 2165 bool
1234 2166
1235 config QCOM_FALKOR_ERRATUM_1003 !! 2167 config IP22_CPU_SCACHE
1236 bool "Falkor E1003: Incorrect transla !! 2168 bool
1237 default y !! 2169 select BOARD_SCACHE
1238 help <<
1239 On Falkor v1, an incorrect ASID may <<
1240 and BADDR are changed together in T <<
1241 in TTBR1_EL1, this situation only o <<
1242 then only for entries in the walk c <<
1243 is unchanged. Work around the errat <<
1244 entries for the trampoline before e <<
1245 2170
1246 config QCOM_FALKOR_ERRATUM_1009 !! 2171 #
1247 bool "Falkor E1009: Prematurely compl !! 2172 # Support for a MIPS32 / MIPS64 style S-caches
1248 default y !! 2173 #
1249 select ARM64_WORKAROUND_REPEAT_TLBI !! 2174 config MIPS_CPU_SCACHE
1250 help !! 2175 bool
1251 On Falkor v1, the CPU may premature !! 2176 select BOARD_SCACHE
1252 TLBI xxIS invalidate maintenance op <<
1253 one more time to fix the issue. <<
1254 2177
1255 If unsure, say Y. !! 2178 config R5000_CPU_SCACHE
>> 2179 bool
>> 2180 select BOARD_SCACHE
1256 2181
1257 config QCOM_QDF2400_ERRATUM_0065 !! 2182 config RM7000_CPU_SCACHE
1258 bool "QDF2400 E0065: Incorrect GITS_T !! 2183 bool
1259 default y !! 2184 select BOARD_SCACHE
>> 2185
>> 2186 config SIBYTE_DMA_PAGEOPS
>> 2187 bool "Use DMA to clear/copy pages"
>> 2188 depends on CPU_SB1
1260 help 2189 help
1261 On Qualcomm Datacenter Technologies !! 2190 Instead of using the CPU to zero and copy pages, use a Data Mover
1262 ITE size incorrectly. The GITS_TYPE !! 2191 channel. These DMA channels are otherwise unused by the standard
1263 been indicated as 16Bytes (0xf), no !! 2192 SiByte Linux port. Seems to give a small performance benefit.
1264 2193
1265 If unsure, say Y. !! 2194 config CPU_HAS_PREFETCH
>> 2195 bool
>> 2196
>> 2197 config CPU_GENERIC_DUMP_TLB
>> 2198 bool
>> 2199 default y if !CPU_R3000
1266 2200
1267 config QCOM_FALKOR_ERRATUM_E1041 !! 2201 config MIPS_FP_SUPPORT
1268 bool "Falkor E1041: Speculative instr !! 2202 bool "Floating Point support" if EXPERT
1269 default y 2203 default y
1270 help 2204 help
1271 Falkor CPU may speculatively fetch !! 2205 Select y to include support for floating point in the kernel
1272 memory location when MMU translatio !! 2206 including initialization of FPU hardware, FP context save & restore
1273 to SCTLR_ELn[M]=0. Prefix an ISB in !! 2207 and emulation of an FPU where necessary. Without this support any
>> 2208 userland program attempting to use floating point instructions will
>> 2209 receive a SIGILL.
1274 2210
1275 If unsure, say Y. !! 2211 If you know that your userland will not attempt to use floating point
>> 2212 instructions then you can say n here to shrink the kernel a little.
1276 2213
1277 config NVIDIA_CARMEL_CNP_ERRATUM !! 2214 If unsure, say y.
1278 bool "NVIDIA Carmel CNP: CNP on Carme <<
1279 default y <<
1280 help <<
1281 If CNP is enabled on Carmel cores, <<
1282 invalidate shared TLB entries insta <<
1283 on standard ARM cores. <<
1284 2215
1285 If unsure, say Y. !! 2216 config CPU_R2300_FPU
>> 2217 bool
>> 2218 depends on MIPS_FP_SUPPORT
>> 2219 default y if CPU_R3000
1286 2220
1287 config ROCKCHIP_ERRATUM_3588001 !! 2221 config CPU_R3K_TLB
1288 bool "Rockchip 3588001: GIC600 can no !! 2222 bool
1289 default y <<
1290 help <<
1291 The Rockchip RK3588 GIC600 SoC inte <<
1292 This means, that its sharability fe <<
1293 is supported by the IP itself. <<
1294 2223
1295 If unsure, say Y. !! 2224 config CPU_R4K_FPU
>> 2225 bool
>> 2226 depends on MIPS_FP_SUPPORT
>> 2227 default y if !CPU_R2300_FPU
1296 2228
1297 config SOCIONEXT_SYNQUACER_PREITS !! 2229 config CPU_R4K_CACHE_TLB
1298 bool "Socionext Synquacer: Workaround !! 2230 bool
>> 2231 default y if !(CPU_R3K_TLB || CPU_SB1 || CPU_CAVIUM_OCTEON)
>> 2232
>> 2233 config MIPS_MT_SMP
>> 2234 bool "MIPS MT SMP support (1 TC on each available VPE)"
1299 default y 2235 default y
>> 2236 depends on SYS_SUPPORTS_MULTITHREADING && !CPU_MIPSR6 && !CPU_MICROMIPS
>> 2237 select CPU_MIPSR2_IRQ_VI
>> 2238 select CPU_MIPSR2_IRQ_EI
>> 2239 select SYNC_R4K
>> 2240 select MIPS_MT
>> 2241 select SMP
>> 2242 select SMP_UP
>> 2243 select SYS_SUPPORTS_SMP
>> 2244 select SYS_SUPPORTS_SCHED_SMT
>> 2245 select MIPS_PERF_SHARED_TC_COUNTERS
>> 2246 help
>> 2247 This is a kernel model which is known as SMVP. This is supported
>> 2248 on cores with the MT ASE and uses the available VPEs to implement
>> 2249 virtual processors which supports SMP. This is equivalent to the
>> 2250 Intel Hyperthreading feature. For further information go to
>> 2251 <http://www.imgtec.com/mips/mips-multithreading.asp>.
>> 2252
>> 2253 config MIPS_MT
>> 2254 bool
>> 2255
>> 2256 config SCHED_SMT
>> 2257 bool "SMT (multithreading) scheduler support"
>> 2258 depends on SYS_SUPPORTS_SCHED_SMT
>> 2259 default n
1300 help 2260 help
1301 Socionext Synquacer SoCs implement !! 2261 SMT scheduler support improves the CPU scheduler's decision making
1302 MSI doorbell writes with non-zero v !! 2262 when dealing with MIPS MT enabled cores at a cost of slightly
>> 2263 increased overhead in some places. If unsure say N here.
1303 2264
1304 If unsure, say Y. !! 2265 config SYS_SUPPORTS_SCHED_SMT
>> 2266 bool
1305 2267
1306 endmenu # "ARM errata workarounds via the alt !! 2268 config SYS_SUPPORTS_MULTITHREADING
>> 2269 bool
1307 2270
1308 choice !! 2271 config MIPS_MT_FPAFF
1309 prompt "Page size" !! 2272 bool "Dynamic FPU affinity for FP-intensive threads"
1310 default ARM64_4K_PAGES !! 2273 default y
1311 help !! 2274 depends on MIPS_MT_SMP
1312 Page size (translation granule) con <<
1313 2275
1314 config ARM64_4K_PAGES !! 2276 config MIPSR2_TO_R6_EMULATOR
1315 bool "4KB" !! 2277 bool "MIPS R2-to-R6 emulator"
1316 select HAVE_PAGE_SIZE_4KB !! 2278 depends on CPU_MIPSR6
>> 2279 depends on MIPS_FP_SUPPORT
>> 2280 default y
1317 help 2281 help
1318 This feature enables 4KB pages supp !! 2282 Choose this option if you want to run non-R6 MIPS userland code.
>> 2283 Even if you say 'Y' here, the emulator will still be disabled by
>> 2284 default. You can enable it using the 'mipsr2emu' kernel option.
>> 2285 The only reason this is a build-time option is to save ~14K from the
>> 2286 final kernel image.
1319 2287
1320 config ARM64_16K_PAGES !! 2288 config SYS_SUPPORTS_VPE_LOADER
1321 bool "16KB" !! 2289 bool
1322 select HAVE_PAGE_SIZE_16KB !! 2290 depends on SYS_SUPPORTS_MULTITHREADING
1323 help 2291 help
1324 The system will use 16KB pages supp !! 2292 Indicates that the platform supports the VPE loader, and provides
1325 requires applications compiled with !! 2293 physical_memsize.
1326 aligned segments. <<
1327 2294
1328 config ARM64_64K_PAGES !! 2295 config MIPS_VPE_LOADER
1329 bool "64KB" !! 2296 bool "VPE loader support."
1330 select HAVE_PAGE_SIZE_64KB !! 2297 depends on SYS_SUPPORTS_VPE_LOADER && MODULES
>> 2298 select CPU_MIPSR2_IRQ_VI
>> 2299 select CPU_MIPSR2_IRQ_EI
>> 2300 select MIPS_MT
1331 help 2301 help
1332 This feature enables 64KB pages sup !! 2302 Includes a loader for loading an elf relocatable object
1333 allowing only two levels of page ta !! 2303 onto another VPE and running it.
1334 look-up. AArch32 emulation requires <<
1335 with 64K aligned segments. <<
1336 2304
1337 endchoice !! 2305 config MIPS_VPE_LOADER_CMP
>> 2306 bool
>> 2307 default "y"
>> 2308 depends on MIPS_VPE_LOADER && MIPS_CMP
1338 2309
1339 choice !! 2310 config MIPS_VPE_LOADER_MT
1340 prompt "Virtual address space size" !! 2311 bool
1341 default ARM64_VA_BITS_52 !! 2312 default "y"
1342 help !! 2313 depends on MIPS_VPE_LOADER && !MIPS_CMP
1343 Allows choosing one of multiple pos <<
1344 space sizes. The level of translati <<
1345 a combination of page size and virt <<
1346 <<
1347 config ARM64_VA_BITS_36 <<
1348 bool "36-bit" if EXPERT <<
1349 depends on PAGE_SIZE_16KB <<
1350 <<
1351 config ARM64_VA_BITS_39 <<
1352 bool "39-bit" <<
1353 depends on PAGE_SIZE_4KB <<
1354 <<
1355 config ARM64_VA_BITS_42 <<
1356 bool "42-bit" <<
1357 depends on PAGE_SIZE_64KB <<
1358 <<
1359 config ARM64_VA_BITS_47 <<
1360 bool "47-bit" <<
1361 depends on PAGE_SIZE_16KB <<
1362 <<
1363 config ARM64_VA_BITS_48 <<
1364 bool "48-bit" <<
1365 <<
1366 config ARM64_VA_BITS_52 <<
1367 bool "52-bit" <<
1368 depends on ARM64_PAN || !ARM64_SW_TTB <<
1369 help <<
1370 Enable 52-bit virtual addressing fo <<
1371 requested via a hint to mmap(). The <<
1372 virtual addresses for its own mappi <<
1373 this feature is available, otherwis <<
1374 <<
1375 NOTE: Enabling 52-bit virtual addre <<
1376 ARMv8.3 Pointer Authentication will <<
1377 reduced from 7 bits to 3 bits, whic <<
1378 impact on its susceptibility to bru <<
1379 2314
1380 If unsure, select 48-bit virtual ad !! 2315 config MIPS_VPE_LOADER_TOM
>> 2316 bool "Load VPE program into memory hidden from linux"
>> 2317 depends on MIPS_VPE_LOADER
>> 2318 default y
>> 2319 help
>> 2320 The loader can use memory that is present but has been hidden from
>> 2321 Linux using the kernel command line option "mem=xxMB". It's up to
>> 2322 you to ensure the amount you put in the option and the space your
>> 2323 program requires is less or equal to the amount physically present.
1381 2324
1382 endchoice !! 2325 config MIPS_VPE_APSP_API
>> 2326 bool "Enable support for AP/SP API (RTLX)"
>> 2327 depends on MIPS_VPE_LOADER
1383 2328
1384 config ARM64_FORCE_52BIT !! 2329 config MIPS_VPE_APSP_API_CMP
1385 bool "Force 52-bit virtual addresses !! 2330 bool
1386 depends on ARM64_VA_BITS_52 && EXPERT !! 2331 default "y"
1387 help !! 2332 depends on MIPS_VPE_APSP_API && MIPS_CMP
1388 For systems with 52-bit userspace V <<
1389 to maintain compatibility with olde <<
1390 unless a hint is supplied to mmap. <<
1391 <<
1392 This configuration option disables <<
1393 forces all userspace addresses to b <<
1394 should only enable this configurati <<
1395 memory management code. If unsure s <<
1396 2333
1397 config ARM64_VA_BITS !! 2334 config MIPS_VPE_APSP_API_MT
1398 int !! 2335 bool
1399 default 36 if ARM64_VA_BITS_36 !! 2336 default "y"
1400 default 39 if ARM64_VA_BITS_39 !! 2337 depends on MIPS_VPE_APSP_API && !MIPS_CMP
1401 default 42 if ARM64_VA_BITS_42 <<
1402 default 47 if ARM64_VA_BITS_47 <<
1403 default 48 if ARM64_VA_BITS_48 <<
1404 default 52 if ARM64_VA_BITS_52 <<
1405 2338
1406 choice !! 2339 config MIPS_CMP
1407 prompt "Physical address space size" !! 2340 bool "MIPS CMP framework support (DEPRECATED)"
1408 default ARM64_PA_BITS_48 !! 2341 depends on SYS_SUPPORTS_MIPS_CMP && !CPU_MIPSR6
>> 2342 select SMP
>> 2343 select SYNC_R4K
>> 2344 select SYS_SUPPORTS_SMP
>> 2345 select WEAK_ORDERING
>> 2346 default n
1409 help 2347 help
1410 Choose the maximum physical address !! 2348 Select this if you are using a bootloader which implements the "CMP
1411 support. !! 2349 framework" protocol (ie. YAMON) and want your kernel to make use of
>> 2350 its ability to start secondary CPUs.
>> 2351
>> 2352 Unless you have a specific need, you should use CONFIG_MIPS_CPS
>> 2353 instead of this.
>> 2354
>> 2355 config MIPS_CPS
>> 2356 bool "MIPS Coherent Processing System support"
>> 2357 depends on SYS_SUPPORTS_MIPS_CPS
>> 2358 select MIPS_CM
>> 2359 select MIPS_CPS_PM if HOTPLUG_CPU
>> 2360 select SMP
>> 2361 select SYNC_R4K if (CEVT_R4K || CSRC_R4K)
>> 2362 select SYS_SUPPORTS_HOTPLUG_CPU
>> 2363 select SYS_SUPPORTS_SCHED_SMT if CPU_MIPSR6
>> 2364 select SYS_SUPPORTS_SMP
>> 2365 select WEAK_ORDERING
>> 2366 select GENERIC_IRQ_MIGRATION if HOTPLUG_CPU
>> 2367 help
>> 2368 Select this if you wish to run an SMP kernel across multiple cores
>> 2369 within a MIPS Coherent Processing System. When this option is
>> 2370 enabled the kernel will probe for other cores and boot them with
>> 2371 no external assistance. It is safe to enable this when hardware
>> 2372 support is unavailable.
1412 2373
1413 config ARM64_PA_BITS_48 !! 2374 config MIPS_CPS_PM
1414 bool "48-bit" !! 2375 depends on MIPS_CPS
1415 depends on ARM64_64K_PAGES || !ARM64_ !! 2376 bool
1416 <<
1417 config ARM64_PA_BITS_52 <<
1418 bool "52-bit" <<
1419 depends on ARM64_64K_PAGES || ARM64_V <<
1420 depends on ARM64_PAN || !ARM64_SW_TTB <<
1421 help <<
1422 Enable support for a 52-bit physica <<
1423 part of the ARMv8.2-LPA extension. <<
1424 <<
1425 With this enabled, the kernel will <<
1426 do not support ARMv8.2-LPA, but wit <<
1427 minor performance overhead). <<
1428 2377
1429 endchoice !! 2378 config MIPS_CM
>> 2379 bool
>> 2380 select MIPS_CPC
1430 2381
1431 config ARM64_PA_BITS !! 2382 config MIPS_CPC
1432 int !! 2383 bool
1433 default 48 if ARM64_PA_BITS_48 <<
1434 default 52 if ARM64_PA_BITS_52 <<
1435 2384
1436 config ARM64_LPA2 !! 2385 config SB1_PASS_2_WORKAROUNDS
1437 def_bool y !! 2386 bool
1438 depends on ARM64_PA_BITS_52 && !ARM64 !! 2387 depends on CPU_SB1 && (CPU_SB1_PASS_2_2 || CPU_SB1_PASS_2)
>> 2388 default y
>> 2389
>> 2390 config SB1_PASS_2_1_WORKAROUNDS
>> 2391 bool
>> 2392 depends on CPU_SB1 && CPU_SB1_PASS_2
>> 2393 default y
1439 2394
1440 choice 2395 choice
1441 prompt "Endianness" !! 2396 prompt "SmartMIPS or microMIPS ASE support"
1442 default CPU_LITTLE_ENDIAN <<
1443 help <<
1444 Select the endianness of data acces <<
1445 applications will need to be compil <<
1446 that is selected here. <<
1447 2397
1448 config CPU_BIG_ENDIAN !! 2398 config CPU_NEEDS_NO_SMARTMIPS_OR_MICROMIPS
1449 bool "Build big-endian kernel" !! 2399 bool "None"
1450 # https://github.com/llvm/llvm-projec <<
1451 depends on AS_IS_GNU || AS_VERSION >= <<
1452 help 2400 help
1453 Say Y if you plan on running a kern !! 2401 Select this if you want neither microMIPS nor SmartMIPS support
1454 2402
1455 config CPU_LITTLE_ENDIAN !! 2403 config CPU_HAS_SMARTMIPS
1456 bool "Build little-endian kernel" !! 2404 depends on SYS_SUPPORTS_SMARTMIPS
>> 2405 bool "SmartMIPS"
>> 2406 help
>> 2407 SmartMIPS is a extension of the MIPS32 architecture aimed at
>> 2408 increased security at both hardware and software level for
>> 2409 smartcards. Enabling this option will allow proper use of the
>> 2410 SmartMIPS instructions by Linux applications. However a kernel with
>> 2411 this option will not work on a MIPS core without SmartMIPS core. If
>> 2412 you don't know you probably don't have SmartMIPS and should say N
>> 2413 here.
>> 2414
>> 2415 config CPU_MICROMIPS
>> 2416 depends on 32BIT && SYS_SUPPORTS_MICROMIPS && !CPU_MIPSR6
>> 2417 bool "microMIPS"
1457 help 2418 help
1458 Say Y if you plan on running a kern !! 2419 When this option is enabled the kernel will be built using the
1459 This is usually the case for distri !! 2420 microMIPS ISA
1460 2421
1461 endchoice 2422 endchoice
1462 2423
1463 config SCHED_MC !! 2424 config CPU_HAS_MSA
1464 bool "Multi-core scheduler support" !! 2425 bool "Support for the MIPS SIMD Architecture"
1465 help !! 2426 depends on CPU_SUPPORTS_MSA
1466 Multi-core scheduler support improv !! 2427 depends on MIPS_FP_SUPPORT
1467 making when dealing with multi-core !! 2428 depends on 64BIT || MIPS_O32_FP64_SUPPORT
1468 increased overhead in some places. !! 2429 help
>> 2430 MIPS SIMD Architecture (MSA) introduces 128 bit wide vector registers
>> 2431 and a set of SIMD instructions to operate on them. When this option
>> 2432 is enabled the kernel will support allocating & switching MSA
>> 2433 vector register contexts. If you know that your kernel will only be
>> 2434 running on CPUs which do not support MSA or that your userland will
>> 2435 not be making use of it then you may wish to say N here to reduce
>> 2436 the size & complexity of your kernel.
1469 2437
1470 config SCHED_CLUSTER !! 2438 If unsure, say Y.
1471 bool "Cluster scheduler support" <<
1472 help <<
1473 Cluster scheduler support improves <<
1474 making when dealing with machines t <<
1475 Cluster usually means a couple of C <<
1476 by sharing mid-level caches, last-l <<
1477 busses. <<
1478 2439
1479 config SCHED_SMT !! 2440 config CPU_HAS_WB
1480 bool "SMT scheduler support" !! 2441 bool
1481 help <<
1482 Improves the CPU scheduler's decisi <<
1483 MultiThreading at a cost of slightl <<
1484 places. If unsure say N here. <<
1485 2442
1486 config NR_CPUS !! 2443 config XKS01
1487 int "Maximum number of CPUs (2-4096)" !! 2444 bool
1488 range 2 4096 <<
1489 default "512" <<
1490 2445
1491 config HOTPLUG_CPU !! 2446 config CPU_HAS_DIEI
1492 bool "Support for hot-pluggable CPUs" !! 2447 depends on !CPU_DIEI_BROKEN
1493 select GENERIC_IRQ_MIGRATION !! 2448 bool
1494 help <<
1495 Say Y here to experiment with turni <<
1496 can be controlled through /sys/devi <<
1497 2449
1498 # Common NUMA Features !! 2450 config CPU_DIEI_BROKEN
1499 config NUMA !! 2451 bool
1500 bool "NUMA Memory Allocation and Sche <<
1501 select GENERIC_ARCH_NUMA <<
1502 select OF_NUMA <<
1503 select HAVE_SETUP_PER_CPU_AREA <<
1504 select NEED_PER_CPU_EMBED_FIRST_CHUNK <<
1505 select NEED_PER_CPU_PAGE_FIRST_CHUNK <<
1506 select USE_PERCPU_NUMA_NODE_ID <<
1507 help <<
1508 Enable NUMA (Non-Uniform Memory Acc <<
1509 2452
1510 The kernel will try to allocate mem !! 2453 config CPU_HAS_RIXI
1511 local memory of the CPU and add som !! 2454 bool
1512 NUMA awareness to the kernel. <<
1513 2455
1514 config NODES_SHIFT !! 2456 config CPU_NO_LOAD_STORE_LR
1515 int "Maximum NUMA Nodes (as a power o !! 2457 bool
1516 range 1 10 <<
1517 default "4" <<
1518 depends on NUMA <<
1519 help 2458 help
1520 Specify the maximum number of NUMA !! 2459 CPU lacks support for unaligned load and store instructions:
1521 system. Increases memory reserved !! 2460 LWL, LWR, SWL, SWR (Load/store word left/right).
>> 2461 LDL, LDR, SDL, SDR (Load/store doubleword left/right, for 64bit
>> 2462 systems).
1522 2463
1523 source "kernel/Kconfig.hz" !! 2464 #
>> 2465 # Vectored interrupt mode is an R2 feature
>> 2466 #
>> 2467 config CPU_MIPSR2_IRQ_VI
>> 2468 bool
1524 2469
1525 config ARCH_SPARSEMEM_ENABLE !! 2470 #
1526 def_bool y !! 2471 # Extended interrupt mode is an R2 feature
1527 select SPARSEMEM_VMEMMAP_ENABLE !! 2472 #
1528 select SPARSEMEM_VMEMMAP !! 2473 config CPU_MIPSR2_IRQ_EI
>> 2474 bool
1529 2475
1530 config HW_PERF_EVENTS !! 2476 config CPU_HAS_SYNC
1531 def_bool y !! 2477 bool
1532 depends on ARM_PMU !! 2478 depends on !CPU_R3000
>> 2479 default y
1533 2480
1534 # Supported by clang >= 7.0 or GCC >= 12.0.0 !! 2481 #
1535 config CC_HAVE_SHADOW_CALL_STACK !! 2482 # CPU non-features
1536 def_bool $(cc-option, -fsanitize=shad !! 2483 #
1537 2484
1538 config PARAVIRT !! 2485 # Work around the "daddi" and "daddiu" CPU errata:
1539 bool "Enable paravirtualization code" !! 2486 #
1540 help !! 2487 # - The `daddi' instruction fails to trap on overflow.
1541 This changes the kernel so it can m !! 2488 # "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0",
1542 under a hypervisor, potentially imp !! 2489 # erratum #23
1543 over full virtualization. !! 2490 #
>> 2491 # - The `daddiu' instruction can produce an incorrect result.
>> 2492 # "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0",
>> 2493 # erratum #41
>> 2494 # "MIPS R4000MC Errata, Processor Revision 2.2 and 3.0", erratum
>> 2495 # #15
>> 2496 # "MIPS R4400PC/SC Errata, Processor Revision 1.0", erratum #7
>> 2497 # "MIPS R4400MC Errata, Processor Revision 1.0", erratum #5
>> 2498 config CPU_DADDI_WORKAROUNDS
>> 2499 bool
1544 2500
1545 config PARAVIRT_TIME_ACCOUNTING !! 2501 # Work around certain R4000 CPU errata (as implemented by GCC):
1546 bool "Paravirtual steal time accounti !! 2502 #
1547 select PARAVIRT !! 2503 # - A double-word or a variable shift may give an incorrect result
1548 help !! 2504 # if executed immediately after starting an integer division:
1549 Select this option to enable fine g !! 2505 # "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0",
1550 accounting. Time spent executing ot !! 2506 # erratum #28
1551 the current vCPU is discounted from !! 2507 # "MIPS R4000MC Errata, Processor Revision 2.2 and 3.0", erratum
1552 that, there can be a small performa !! 2508 # #19
>> 2509 #
>> 2510 # - A double-word or a variable shift may give an incorrect result
>> 2511 # if executed while an integer multiplication is in progress:
>> 2512 # "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0",
>> 2513 # errata #16 & #28
>> 2514 #
>> 2515 # - An integer division may give an incorrect result if started in
>> 2516 # a delay slot of a taken branch or a jump:
>> 2517 # "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0",
>> 2518 # erratum #52
>> 2519 config CPU_R4000_WORKAROUNDS
>> 2520 bool
>> 2521 select CPU_R4400_WORKAROUNDS
1553 2522
1554 If in doubt, say N here. !! 2523 # Work around certain R4400 CPU errata (as implemented by GCC):
>> 2524 #
>> 2525 # - A double-word or a variable shift may give an incorrect result
>> 2526 # if executed immediately after starting an integer division:
>> 2527 # "MIPS R4400MC Errata, Processor Revision 1.0", erratum #10
>> 2528 # "MIPS R4400MC Errata, Processor Revision 2.0 & 3.0", erratum #4
>> 2529 config CPU_R4400_WORKAROUNDS
>> 2530 bool
1555 2531
1556 config ARCH_SUPPORTS_KEXEC !! 2532 config CPU_R4X00_BUGS64
1557 def_bool PM_SLEEP_SMP !! 2533 bool
>> 2534 default y if SYS_HAS_CPU_R4X00 && 64BIT && (TARGET_ISA_REV < 1)
1558 2535
1559 config ARCH_SUPPORTS_KEXEC_FILE !! 2536 config MIPS_ASID_SHIFT
1560 def_bool y !! 2537 int
>> 2538 default 6 if CPU_R3000
>> 2539 default 0
1561 2540
1562 config ARCH_SELECTS_KEXEC_FILE !! 2541 config MIPS_ASID_BITS
1563 def_bool y !! 2542 int
1564 depends on KEXEC_FILE !! 2543 default 0 if MIPS_ASID_BITS_VARIABLE
1565 select HAVE_IMA_KEXEC if IMA !! 2544 default 6 if CPU_R3000
>> 2545 default 8
1566 2546
1567 config ARCH_SUPPORTS_KEXEC_SIG !! 2547 config MIPS_ASID_BITS_VARIABLE
1568 def_bool y !! 2548 bool
1569 2549
1570 config ARCH_SUPPORTS_KEXEC_IMAGE_VERIFY_SIG !! 2550 config MIPS_CRC_SUPPORT
1571 def_bool y !! 2551 bool
1572 2552
1573 config ARCH_DEFAULT_KEXEC_IMAGE_VERIFY_SIG !! 2553 # R4600 erratum. Due to the lack of errata information the exact
1574 def_bool y !! 2554 # technical details aren't known. I've experimentally found that disabling
>> 2555 # interrupts during indexed I-cache flushes seems to be sufficient to deal
>> 2556 # with the issue.
>> 2557 config WAR_R4600_V1_INDEX_ICACHEOP
>> 2558 bool
1575 2559
1576 config ARCH_SUPPORTS_CRASH_DUMP !! 2560 # Pleasures of the R4600 V1.x. Cite from the IDT R4600 V1.7 errata:
1577 def_bool y !! 2561 #
>> 2562 # 18. The CACHE instructions Hit_Writeback_Invalidate_D, Hit_Writeback_D,
>> 2563 # Hit_Invalidate_D and Create_Dirty_Excl_D should only be
>> 2564 # executed if there is no other dcache activity. If the dcache is
>> 2565 # accessed for another instruction immediately preceding when these
>> 2566 # cache instructions are executing, it is possible that the dcache
>> 2567 # tag match outputs used by these cache instructions will be
>> 2568 # incorrect. These cache instructions should be preceded by at least
>> 2569 # four instructions that are not any kind of load or store
>> 2570 # instruction.
>> 2571 #
>> 2572 # This is not allowed: lw
>> 2573 # nop
>> 2574 # nop
>> 2575 # nop
>> 2576 # cache Hit_Writeback_Invalidate_D
>> 2577 #
>> 2578 # This is allowed: lw
>> 2579 # nop
>> 2580 # nop
>> 2581 # nop
>> 2582 # nop
>> 2583 # cache Hit_Writeback_Invalidate_D
>> 2584 config WAR_R4600_V1_HIT_CACHEOP
>> 2585 bool
1578 2586
1579 config ARCH_HAS_GENERIC_CRASHKERNEL_RESERVATI !! 2587 # Writeback and invalidate the primary cache dcache before DMA.
1580 def_bool CRASH_RESERVE !! 2588 #
>> 2589 # R4600 v2.0 bug: "The CACHE instructions Hit_Writeback_Inv_D,
>> 2590 # Hit_Writeback_D, Hit_Invalidate_D and Create_Dirty_Exclusive_D will only
>> 2591 # operate correctly if the internal data cache refill buffer is empty. These
>> 2592 # CACHE instructions should be separated from any potential data cache miss
>> 2593 # by a load instruction to an uncached address to empty the response buffer."
>> 2594 # (Revision 2.0 device errata from IDT available on https://www.idt.com/
>> 2595 # in .pdf format.)
>> 2596 config WAR_R4600_V2_HIT_CACHEOP
>> 2597 bool
1581 2598
1582 config TRANS_TABLE !! 2599 # From TX49/H2 manual: "If the instruction (i.e. CACHE) is issued for
1583 def_bool y !! 2600 # the line which this instruction itself exists, the following
1584 depends on HIBERNATION || KEXEC_CORE !! 2601 # operation is not guaranteed."
>> 2602 #
>> 2603 # Workaround: do two phase flushing for Index_Invalidate_I
>> 2604 config WAR_TX49XX_ICACHE_INDEX_INV
>> 2605 bool
1585 2606
1586 config XEN_DOM0 !! 2607 # The RM7000 processors and the E9000 cores have a bug (though PMC-Sierra
1587 def_bool y !! 2608 # opposes it being called that) where invalid instructions in the same
1588 depends on XEN !! 2609 # I-cache line worth of instructions being fetched may case spurious
>> 2610 # exceptions.
>> 2611 config WAR_ICACHE_REFILLS
>> 2612 bool
1589 2613
1590 config XEN !! 2614 # On the R10000 up to version 2.6 (not sure about 2.7) there is a bug that
1591 bool "Xen guest support on ARM64" !! 2615 # may cause ll / sc and lld / scd sequences to execute non-atomically.
1592 depends on ARM64 && OF !! 2616 config WAR_R10000_LLSC
1593 select SWIOTLB_XEN !! 2617 bool
1594 select PARAVIRT !! 2618
1595 help !! 2619 # 34K core erratum: "Problems Executing the TLBR Instruction"
1596 Say Y if you want to run Linux in a !! 2620 config WAR_MIPS34K_MISSED_ITLB
>> 2621 bool
1597 2622
1598 # include/linux/mmzone.h requires the followi <<
1599 # <<
1600 # MAX_PAGE_ORDER + PAGE_SHIFT <= SECTION_SI <<
1601 # 2623 #
1602 # so the maximum value of MAX_PAGE_ORDER is S !! 2624 # - Highmem only makes sense for the 32-bit kernel.
>> 2625 # - The current highmem code will only work properly on physically indexed
>> 2626 # caches such as R3000, SB1, R7000 or those that look like they're virtually
>> 2627 # indexed such as R4000/R4400 SC and MC versions or R10000. So for the
>> 2628 # moment we protect the user and offer the highmem option only on machines
>> 2629 # where it's known to be safe. This will not offer highmem on a few systems
>> 2630 # such as MIPS32 and MIPS64 CPUs which may have virtual and physically
>> 2631 # indexed CPUs but we're playing safe.
>> 2632 # - We use SYS_SUPPORTS_HIGHMEM to offer highmem only for systems where we
>> 2633 # know they might have memory configurations that could make use of highmem
>> 2634 # support.
1603 # 2635 #
1604 # | SECTION_SIZE_BITS | PAGE_SHIFT | m !! 2636 config HIGHMEM
1605 # ----+-------------------+--------------+--- !! 2637 bool "High Memory Support"
1606 # 4K | 27 | 12 | !! 2638 depends on 32BIT && CPU_SUPPORTS_HIGHMEM && SYS_SUPPORTS_HIGHMEM && !CPU_MIPS32_3_5_EVA
1607 # 16K | 27 | 14 | !! 2639 select KMAP_LOCAL
1608 # 64K | 29 | 16 | <<
1609 config ARCH_FORCE_MAX_ORDER <<
1610 int <<
1611 default "13" if ARM64_64K_PAGES <<
1612 default "11" if ARM64_16K_PAGES <<
1613 default "10" <<
1614 help <<
1615 The kernel page allocator limits th <<
1616 contiguous allocations. The limit i <<
1617 defines the maximal power of two of <<
1618 allocated as a single contiguous bl <<
1619 overriding the default setting when <<
1620 large blocks of physically contiguo <<
1621 <<
1622 The maximal size of allocation cann <<
1623 section, so the value of MAX_PAGE_O <<
1624 <<
1625 MAX_PAGE_ORDER + PAGE_SHIFT <= SE <<
1626 2640
1627 Don't change if unsure. !! 2641 config CPU_SUPPORTS_HIGHMEM
>> 2642 bool
1628 2643
1629 config UNMAP_KERNEL_AT_EL0 !! 2644 config SYS_SUPPORTS_HIGHMEM
1630 bool "Unmap kernel when running in us !! 2645 bool
1631 default y <<
1632 help <<
1633 Speculation attacks against some hi <<
1634 be used to bypass MMU permission ch <<
1635 userspace. This can be defended aga <<
1636 when running in userspace, mapping <<
1637 via a trampoline page in the vector <<
1638 2646
1639 If unsure, say Y. !! 2647 config SYS_SUPPORTS_SMARTMIPS
>> 2648 bool
1640 2649
1641 config MITIGATE_SPECTRE_BRANCH_HISTORY !! 2650 config SYS_SUPPORTS_MICROMIPS
1642 bool "Mitigate Spectre style attacks !! 2651 bool
1643 default y <<
1644 help <<
1645 Speculation attacks against some hi <<
1646 make use of branch history to influ <<
1647 When taking an exception from user- <<
1648 or a firmware call overwrites the b <<
1649 2652
1650 config RODATA_FULL_DEFAULT_ENABLED !! 2653 config SYS_SUPPORTS_MIPS16
1651 bool "Apply r/o permissions of VM are !! 2654 bool
1652 default y <<
1653 help 2655 help
1654 Apply read-only attributes of VM ar !! 2656 This option must be set if a kernel might be executed on a MIPS16-
1655 the backing pages as well. This pre !! 2657 enabled CPU even if MIPS16 is not actually being used. In other
1656 from being modified (inadvertently !! 2658 words, it makes the kernel MIPS16-tolerant.
1657 mapping of the same memory page. Th <<
1658 be turned off at runtime by passing <<
1659 with rodata=full if this option is <<
1660 <<
1661 This requires the linear region to <<
1662 which may adversely affect performa <<
1663 <<
1664 config ARM64_SW_TTBR0_PAN <<
1665 bool "Emulate Privileged Access Never <<
1666 depends on !KCSAN <<
1667 help <<
1668 Enabling this option prevents the k <<
1669 user-space memory directly by point <<
1670 zeroed area and reserved ASID. The <<
1671 restore the valid TTBR0_EL1 tempora <<
1672 2659
1673 config ARM64_TAGGED_ADDR_ABI !! 2660 config CPU_SUPPORTS_MSA
1674 bool "Enable the tagged user addresse !! 2661 bool
1675 default y <<
1676 help <<
1677 When this option is enabled, user a <<
1678 relaxed ABI via prctl() allowing ta <<
1679 to system calls as pointer argument <<
1680 Documentation/arch/arm64/tagged-add <<
1681 <<
1682 menuconfig COMPAT <<
1683 bool "Kernel support for 32-bit EL0" <<
1684 depends on ARM64_4K_PAGES || EXPERT <<
1685 select HAVE_UID16 <<
1686 select OLD_SIGSUSPEND3 <<
1687 select COMPAT_OLD_SIGACTION <<
1688 help <<
1689 This option enables support for a 3 <<
1690 kernel at EL1. AArch32-specific com <<
1691 the user helper functions, VFP supp <<
1692 handled appropriately by the kernel <<
1693 <<
1694 If you use a page size other than 4 <<
1695 that you will only be able to execu <<
1696 with page size aligned segments. <<
1697 2662
1698 If you want to execute 32-bit users !! 2663 config ARCH_FLATMEM_ENABLE
>> 2664 def_bool y
>> 2665 depends on !NUMA && !CPU_LOONGSON2EF
1699 2666
1700 if COMPAT !! 2667 config ARCH_SPARSEMEM_ENABLE
>> 2668 bool
1701 2669
1702 config KUSER_HELPERS !! 2670 config NUMA
1703 bool "Enable kuser helpers page for 3 !! 2671 bool "NUMA Support"
1704 default y !! 2672 depends on SYS_SUPPORTS_NUMA
>> 2673 select SMP
>> 2674 select HAVE_SETUP_PER_CPU_AREA
>> 2675 select NEED_PER_CPU_EMBED_FIRST_CHUNK
1705 help 2676 help
1706 Warning: disabling this option may !! 2677 Say Y to compile the kernel to support NUMA (Non-Uniform Memory
>> 2678 Access). This option improves performance on systems with more
>> 2679 than two nodes; on two node systems it is generally better to
>> 2680 leave it disabled; on single node systems leave this option
>> 2681 disabled.
1707 2682
1708 Provide kuser helpers to compat tas !! 2683 config SYS_SUPPORTS_NUMA
1709 helper code to userspace in read on !! 2684 bool
1710 to allow userspace to be independen <<
1711 the system. This permits binaries t <<
1712 to ARMv8 without modification. <<
1713 <<
1714 See Documentation/arch/arm/kernel_u <<
1715 <<
1716 However, the fixed address nature o <<
1717 by ROP (return orientated programmi <<
1718 exploits. <<
1719 <<
1720 If all of the binaries and librarie <<
1721 are built specifically for your pla <<
1722 these helpers, then you can turn th <<
1723 such exploits. However, in that cas <<
1724 relying on those helpers is run, it <<
1725 <<
1726 Say N here only if you are absolute <<
1727 need these helpers; otherwise, the <<
1728 <<
1729 config COMPAT_VDSO <<
1730 bool "Enable vDSO for 32-bit applicat <<
1731 depends on !CPU_BIG_ENDIAN <<
1732 depends on (CC_IS_CLANG && LD_IS_LLD) <<
1733 select GENERIC_COMPAT_VDSO <<
1734 default y <<
1735 help <<
1736 Place in the process address space <<
1737 ELF shared object providing fast im <<
1738 and clock_gettime. <<
1739 <<
1740 You must have a 32-bit build of gli <<
1741 to seamlessly take advantage of thi <<
1742 <<
1743 config THUMB2_COMPAT_VDSO <<
1744 bool "Compile the 32-bit vDSO for Thu <<
1745 depends on COMPAT_VDSO <<
1746 default y <<
1747 help <<
1748 Compile the compat vDSO with '-mthu <<
1749 otherwise with '-marm'. <<
1750 2685
1751 config COMPAT_ALIGNMENT_FIXUPS !! 2686 config HAVE_ARCH_NODEDATA_EXTENSION
1752 bool "Fix up misaligned multi-word lo !! 2687 bool
1753 2688
1754 menuconfig ARMV8_DEPRECATED !! 2689 config RELOCATABLE
1755 bool "Emulate deprecated/obsolete ARM !! 2690 bool "Relocatable kernel"
1756 depends on SYSCTL !! 2691 depends on SYS_SUPPORTS_RELOCATABLE
1757 help !! 2692 depends on CPU_MIPS32_R2 || CPU_MIPS64_R2 || \
1758 Legacy software support may require !! 2693 CPU_MIPS32_R5 || CPU_MIPS64_R5 || \
1759 that have been deprecated or obsole !! 2694 CPU_MIPS32_R6 || CPU_MIPS64_R6 || \
>> 2695 CPU_P5600 || CAVIUM_OCTEON_SOC || \
>> 2696 CPU_LOONGSON64
>> 2697 help
>> 2698 This builds a kernel image that retains relocation information
>> 2699 so it can be loaded someplace besides the default 1MB.
>> 2700 The relocations make the kernel binary about 15% larger,
>> 2701 but are discarded at runtime
>> 2702
>> 2703 config RELOCATION_TABLE_SIZE
>> 2704 hex "Relocation table size"
>> 2705 depends on RELOCATABLE
>> 2706 range 0x0 0x01000000
>> 2707 default "0x00200000" if CPU_LOONGSON64
>> 2708 default "0x00100000"
>> 2709 help
>> 2710 A table of relocation data will be appended to the kernel binary
>> 2711 and parsed at boot to fix up the relocated kernel.
1760 2712
1761 Enable this config to enable select !! 2713 This option allows the amount of space reserved for the table to be
1762 features. !! 2714 adjusted, although the default of 1Mb should be ok in most cases.
1763 2715
1764 If unsure, say Y !! 2716 The build will fail and a valid size suggested if this is too small.
1765 2717
1766 if ARMV8_DEPRECATED !! 2718 If unsure, leave at the default value.
1767 2719
1768 config SWP_EMULATION !! 2720 config RANDOMIZE_BASE
1769 bool "Emulate SWP/SWPB instructions" !! 2721 bool "Randomize the address of the kernel image"
>> 2722 depends on RELOCATABLE
1770 help 2723 help
1771 ARMv8 obsoletes the use of A32 SWP/ !! 2724 Randomizes the physical and virtual address at which the
1772 they are always undefined. Say Y he !! 2725 kernel image is loaded, as a security feature that
1773 emulation of these instructions for !! 2726 deters exploit attempts relying on knowledge of the location
1774 This feature can be controlled at r !! 2727 of kernel internals.
1775 sysctl which is disabled by default <<
1776 2728
1777 In some older versions of glibc [<= !! 2729 Entropy is generated using any coprocessor 0 registers available.
1778 trylock() operations with the assum <<
1779 be preempted. This invalid assumpti <<
1780 with SWP emulation enabled, leading <<
1781 application. <<
1782 2730
1783 NOTE: when accessing uncached share !! 2731 The kernel will be offset by up to RANDOMIZE_BASE_MAX_OFFSET.
1784 on an external transaction monitori <<
1785 monitor to maintain update atomicit <<
1786 implement a global monitor, this op <<
1787 perform SWP operations to uncached <<
1788 2732
1789 If unsure, say Y !! 2733 If unsure, say N.
1790 2734
1791 config CP15_BARRIER_EMULATION !! 2735 config RANDOMIZE_BASE_MAX_OFFSET
1792 bool "Emulate CP15 Barrier instructio !! 2736 hex "Maximum kASLR offset" if EXPERT
1793 help !! 2737 depends on RANDOMIZE_BASE
1794 The CP15 barrier instructions - CP1 !! 2738 range 0x0 0x40000000 if EVA || 64BIT
1795 CP15DMB - are deprecated in ARMv8 ( !! 2739 range 0x0 0x08000000
1796 strongly recommended to use the ISB !! 2740 default "0x01000000"
1797 instructions instead. !! 2741 help
>> 2742 When kASLR is active, this provides the maximum offset that will
>> 2743 be applied to the kernel image. It should be set according to the
>> 2744 amount of physical RAM available in the target system minus
>> 2745 PHYSICAL_START and must be a power of 2.
1798 2746
1799 Say Y here to enable software emula !! 2747 This is limited by the size of KSEG0, 256Mb on 32-bit or 1Gb with
1800 instructions for AArch32 userspace !! 2748 EVA or 64-bit. The default is 16Mb.
1801 enabled, CP15 barrier usage is trac <<
1802 identify software that needs updati <<
1803 controlled at runtime with the abi. <<
1804 2749
1805 If unsure, say Y !! 2750 config NODES_SHIFT
>> 2751 int
>> 2752 default "6"
>> 2753 depends on NUMA
1806 2754
1807 config SETEND_EMULATION !! 2755 config HW_PERF_EVENTS
1808 bool "Emulate SETEND instruction" !! 2756 bool "Enable hardware performance counter support for perf events"
>> 2757 depends on PERF_EVENTS && (CPU_MIPS32 || CPU_MIPS64 || CPU_R10000 || CPU_SB1 || CPU_CAVIUM_OCTEON || CPU_LOONGSON64)
>> 2758 default y
1809 help 2759 help
1810 The SETEND instruction alters the d !! 2760 Enable hardware performance counter support for perf events. If
1811 AArch32 EL0, and is deprecated in A !! 2761 disabled, perf events will use software events only.
1812 2762
1813 Say Y here to enable software emula !! 2763 config DMI
1814 for AArch32 userspace code. This fe !! 2764 bool "Enable DMI scanning"
1815 at runtime with the abi.setend sysc !! 2765 depends on MACH_LOONGSON64
>> 2766 select DMI_SCAN_MACHINE_NON_EFI_FALLBACK
>> 2767 default y
>> 2768 help
>> 2769 Enabled scanning of DMI to identify machine quirks. Say Y
>> 2770 here unless you have verified that your setup is not
>> 2771 affected by entries in the DMI blacklist. Required by PNP
>> 2772 BIOS code.
1816 2773
1817 Note: All the cpus on the system mu !! 2774 config SMP
1818 for this feature to be enabled. If !! 2775 bool "Multi-Processing support"
1819 endian - is hotplugged in after thi !! 2776 depends on SYS_SUPPORTS_SMP
1820 be unexpected results in the applic !! 2777 help
>> 2778 This enables support for systems with more than one CPU. If you have
>> 2779 a system with only one CPU, say N. If you have a system with more
>> 2780 than one CPU, say Y.
>> 2781
>> 2782 If you say N here, the kernel will run on uni- and multiprocessor
>> 2783 machines, but will use only one CPU of a multiprocessor machine. If
>> 2784 you say Y here, the kernel will run on many, but not all,
>> 2785 uniprocessor machines. On a uniprocessor machine, the kernel
>> 2786 will run faster if you say N here.
1821 2787
1822 If unsure, say Y !! 2788 People using multiprocessor machines who say Y here should also say
1823 endif # ARMV8_DEPRECATED !! 2789 Y to "Enhanced Real Time Clock Support", below.
1824 2790
1825 endif # COMPAT !! 2791 See also the SMP-HOWTO available at
>> 2792 <https://www.tldp.org/docs.html#howto>.
1826 2793
1827 menu "ARMv8.1 architectural features" !! 2794 If you don't know what to do here, say N.
1828 2795
1829 config ARM64_HW_AFDBM !! 2796 config HOTPLUG_CPU
1830 bool "Support for hardware updates of !! 2797 bool "Support for hot-pluggable CPUs"
1831 default y !! 2798 depends on SMP && SYS_SUPPORTS_HOTPLUG_CPU
1832 help 2799 help
1833 The ARMv8.1 architecture extensions !! 2800 Say Y here to allow turning CPUs off and on. CPUs can be
1834 hardware updates of the access and !! 2801 controlled through /sys/devices/system/cpu.
1835 table entries. When enabled in TCR_ !! 2802 (Note: power management support will enable this option
1836 capable processors, accesses to pag !! 2803 automatically on SMP systems. )
1837 set this bit instead of raising an !! 2804 Say N if you want to disable CPU hotplug.
1838 Similarly, writes to read-only page <<
1839 clear the read-only bit (AP[2]) ins <<
1840 permission fault. <<
1841 <<
1842 Kernels built with this configurati <<
1843 to work on pre-ARMv8.1 hardware and <<
1844 minimal. If unsure, say Y. <<
1845 2805
1846 config ARM64_PAN !! 2806 config SMP_UP
1847 bool "Enable support for Privileged A !! 2807 bool
1848 default y <<
1849 help <<
1850 Privileged Access Never (PAN; part <<
1851 prevents the kernel or hypervisor f <<
1852 memory directly. <<
1853 2808
1854 Choosing this option will cause any !! 2809 config SYS_SUPPORTS_MIPS_CMP
1855 copy_to_user et al) memory access t !! 2810 bool
1856 2811
1857 The feature is detected at runtime, !! 2812 config SYS_SUPPORTS_MIPS_CPS
1858 instruction if the cpu does not imp !! 2813 bool
1859 2814
1860 config AS_HAS_LSE_ATOMICS !! 2815 config SYS_SUPPORTS_SMP
1861 def_bool $(as-instr,.arch_extension l !! 2816 bool
1862 2817
1863 config ARM64_LSE_ATOMICS !! 2818 config NR_CPUS_DEFAULT_4
1864 bool 2819 bool
1865 default ARM64_USE_LSE_ATOMICS <<
1866 depends on AS_HAS_LSE_ATOMICS <<
1867 2820
1868 config ARM64_USE_LSE_ATOMICS !! 2821 config NR_CPUS_DEFAULT_8
1869 bool "Atomic instructions" !! 2822 bool
1870 default y <<
1871 help <<
1872 As part of the Large System Extensi <<
1873 atomic instructions that are design <<
1874 very large systems. <<
1875 2823
1876 Say Y here to make use of these ins !! 2824 config NR_CPUS_DEFAULT_16
1877 atomic routines. This incurs a smal !! 2825 bool
1878 not support these instructions and <<
1879 built with binutils >= 2.25 in orde <<
1880 to be used. <<
1881 2826
1882 endmenu # "ARMv8.1 architectural features" !! 2827 config NR_CPUS_DEFAULT_32
>> 2828 bool
1883 2829
1884 menu "ARMv8.2 architectural features" !! 2830 config NR_CPUS_DEFAULT_64
>> 2831 bool
1885 2832
1886 config AS_HAS_ARMV8_2 !! 2833 config NR_CPUS
1887 def_bool $(cc-option,-Wa$(comma)-marc !! 2834 int "Maximum number of CPUs (2-256)"
>> 2835 range 2 256
>> 2836 depends on SMP
>> 2837 default "4" if NR_CPUS_DEFAULT_4
>> 2838 default "8" if NR_CPUS_DEFAULT_8
>> 2839 default "16" if NR_CPUS_DEFAULT_16
>> 2840 default "32" if NR_CPUS_DEFAULT_32
>> 2841 default "64" if NR_CPUS_DEFAULT_64
>> 2842 help
>> 2843 This allows you to specify the maximum number of CPUs which this
>> 2844 kernel will support. The maximum supported value is 32 for 32-bit
>> 2845 kernel and 64 for 64-bit kernels; the minimum value which makes
>> 2846 sense is 1 for Qemu (useful only for kernel debugging purposes)
>> 2847 and 2 for all others.
>> 2848
>> 2849 This is purely to save memory - each supported CPU adds
>> 2850 approximately eight kilobytes to the kernel image. For best
>> 2851 performance should round up your number of processors to the next
>> 2852 power of two.
1888 2853
1889 config AS_HAS_SHA3 !! 2854 config MIPS_PERF_SHARED_TC_COUNTERS
1890 def_bool $(as-instr,.arch armv8.2-a+s !! 2855 bool
1891 2856
1892 config ARM64_PMEM !! 2857 config MIPS_NR_CPU_NR_MAP_1024
1893 bool "Enable support for persistent m !! 2858 bool
1894 select ARCH_HAS_PMEM_API <<
1895 select ARCH_HAS_UACCESS_FLUSHCACHE <<
1896 help <<
1897 Say Y to enable support for the per <<
1898 ARMv8.2 DCPoP feature. <<
1899 2859
1900 The feature is detected at runtime, !! 2860 config MIPS_NR_CPU_NR_MAP
1901 operations if DC CVAP is not suppor !! 2861 int
1902 DC CVAP itself if the system does n !! 2862 depends on SMP
>> 2863 default 1024 if MIPS_NR_CPU_NR_MAP_1024
>> 2864 default NR_CPUS if !MIPS_NR_CPU_NR_MAP_1024
1903 2865
1904 config ARM64_RAS_EXTN !! 2866 #
1905 bool "Enable support for RAS CPU Exte !! 2867 # Timer Interrupt Frequency Configuration
1906 default y !! 2868 #
1907 help <<
1908 CPUs that support the Reliability, <<
1909 (RAS) Extensions, part of ARMv8.2 a <<
1910 errors, classify them and report th <<
1911 <<
1912 On CPUs with these extensions syste <<
1913 barriers to determine if faults are <<
1914 classification from a new set of re <<
1915 <<
1916 Selecting this feature will allow t <<
1917 and access the new registers if the <<
1918 Platform RAS features may additiona <<
1919 2869
1920 config ARM64_CNP !! 2870 choice
1921 bool "Enable support for Common Not P !! 2871 prompt "Timer frequency"
1922 default y !! 2872 default HZ_250
1923 depends on ARM64_PAN || !ARM64_SW_TTB <<
1924 help 2873 help
1925 Common Not Private (CNP) allows tra !! 2874 Allows the configuration of the timer frequency.
1926 be shared between different PEs in <<
1927 domain, so the hardware can use thi <<
1928 caching of such entries in the TLB. <<
1929 <<
1930 Selecting this option allows the CN <<
1931 at runtime, and does not affect PEs <<
1932 this feature. <<
1933 2875
1934 endmenu # "ARMv8.2 architectural features" !! 2876 config HZ_24
>> 2877 bool "24 HZ" if SYS_SUPPORTS_24HZ || SYS_SUPPORTS_ARBIT_HZ
1935 2878
1936 menu "ARMv8.3 architectural features" !! 2879 config HZ_48
1937 !! 2880 bool "48 HZ" if SYS_SUPPORTS_48HZ || SYS_SUPPORTS_ARBIT_HZ
1938 config ARM64_PTR_AUTH <<
1939 bool "Enable support for pointer auth <<
1940 default y <<
1941 help <<
1942 Pointer authentication (part of the <<
1943 instructions for signing and authen <<
1944 keys, which can be used to mitigate <<
1945 and other attacks. <<
1946 <<
1947 This option enables these instructi <<
1948 Choosing this option will cause the <<
1949 for each process at exec() time, wi <<
1950 context-switched along with the pro <<
1951 <<
1952 The feature is detected at runtime. <<
1953 hardware it will not be advertised <<
1954 be enabled. <<
1955 <<
1956 If the feature is present on the bo <<
1957 the late CPU will be parked. Also, <<
1958 address auth and the late CPU has t <<
1959 but with the feature disabled. On s <<
1960 not be selected. <<
1961 2881
1962 config ARM64_PTR_AUTH_KERNEL !! 2882 config HZ_100
1963 bool "Use pointer authentication for !! 2883 bool "100 HZ" if SYS_SUPPORTS_100HZ || SYS_SUPPORTS_ARBIT_HZ
1964 default y <<
1965 depends on ARM64_PTR_AUTH <<
1966 depends on (CC_HAS_SIGN_RETURN_ADDRES <<
1967 # Modern compilers insert a .note.gnu <<
1968 # which is only understood by binutil <<
1969 depends on LD_IS_LLD || LD_VERSION >= <<
1970 depends on !CC_IS_CLANG || AS_HAS_CFI <<
1971 depends on (!FUNCTION_GRAPH_TRACER || <<
1972 help <<
1973 If the compiler supports the -mbran <<
1974 -msign-return-address flag (e.g. GC <<
1975 will cause the kernel itself to be <<
1976 protection. In this case, and if th <<
1977 support pointer authentication, the <<
1978 disabled with minimal loss of prote <<
1979 <<
1980 This feature works with FUNCTION_GR <<
1981 DYNAMIC_FTRACE_WITH_ARGS is enabled <<
1982 <<
1983 config CC_HAS_BRANCH_PROT_PAC_RET <<
1984 # GCC 9 or later, clang 8 or later <<
1985 def_bool $(cc-option,-mbranch-protect <<
1986 <<
1987 config CC_HAS_SIGN_RETURN_ADDRESS <<
1988 # GCC 7, 8 <<
1989 def_bool $(cc-option,-msign-return-ad <<
1990 <<
1991 config AS_HAS_ARMV8_3 <<
1992 def_bool $(cc-option,-Wa$(comma)-marc <<
1993 <<
1994 config AS_HAS_CFI_NEGATE_RA_STATE <<
1995 def_bool $(as-instr,.cfi_startproc\n. <<
1996 <<
1997 config AS_HAS_LDAPR <<
1998 def_bool $(as-instr,.arch_extension r <<
1999 2884
2000 endmenu # "ARMv8.3 architectural features" !! 2885 config HZ_128
>> 2886 bool "128 HZ" if SYS_SUPPORTS_128HZ || SYS_SUPPORTS_ARBIT_HZ
2001 2887
2002 menu "ARMv8.4 architectural features" !! 2888 config HZ_250
>> 2889 bool "250 HZ" if SYS_SUPPORTS_250HZ || SYS_SUPPORTS_ARBIT_HZ
2003 2890
2004 config ARM64_AMU_EXTN !! 2891 config HZ_256
2005 bool "Enable support for the Activity !! 2892 bool "256 HZ" if SYS_SUPPORTS_256HZ || SYS_SUPPORTS_ARBIT_HZ
2006 default y <<
2007 help <<
2008 The activity monitors extension is <<
2009 by the ARMv8.4 CPU architecture. Th <<
2010 of the activity monitors architectu <<
2011 <<
2012 To enable the use of this extension <<
2013 <<
2014 Note that for architectural reasons <<
2015 support when running on CPUs that p <<
2016 extension. The required support is <<
2017 * Version 1.5 and later of the AR <<
2018 <<
2019 For kernels that have this configur <<
2020 firmware, you may need to say N her <<
2021 Otherwise you may experience firmwa <<
2022 accessing the counter registers. Ev <<
2023 symptoms, the values returned by th <<
2024 correctly reflect reality. Most com <<
2025 indicating that the counter is not <<
2026 2893
2027 config AS_HAS_ARMV8_4 !! 2894 config HZ_1000
2028 def_bool $(cc-option,-Wa$(comma)-marc !! 2895 bool "1000 HZ" if SYS_SUPPORTS_1000HZ || SYS_SUPPORTS_ARBIT_HZ
2029 2896
2030 config ARM64_TLB_RANGE !! 2897 config HZ_1024
2031 bool "Enable support for tlbi range f !! 2898 bool "1024 HZ" if SYS_SUPPORTS_1024HZ || SYS_SUPPORTS_ARBIT_HZ
2032 default y <<
2033 depends on AS_HAS_ARMV8_4 <<
2034 help <<
2035 ARMv8.4-TLBI provides TLBI invalida <<
2036 range of input addresses. <<
2037 2899
2038 The feature introduces new assembly !! 2900 endchoice
2039 support when binutils >= 2.30. <<
2040 2901
2041 endmenu # "ARMv8.4 architectural features" !! 2902 config SYS_SUPPORTS_24HZ
>> 2903 bool
2042 2904
2043 menu "ARMv8.5 architectural features" !! 2905 config SYS_SUPPORTS_48HZ
>> 2906 bool
2044 2907
2045 config AS_HAS_ARMV8_5 !! 2908 config SYS_SUPPORTS_100HZ
2046 def_bool $(cc-option,-Wa$(comma)-marc !! 2909 bool
2047 2910
2048 config ARM64_BTI !! 2911 config SYS_SUPPORTS_128HZ
2049 bool "Branch Target Identification su !! 2912 bool
2050 default y <<
2051 help <<
2052 Branch Target Identification (part <<
2053 provides a mechanism to limit the s <<
2054 branch instructions such as BR or B <<
2055 <<
2056 To make use of BTI on CPUs that sup <<
2057 <<
2058 BTI is intended to provide compleme <<
2059 flow integrity protection mechanism <<
2060 authentication mechanism provided a <<
2061 For this reason, it does not make s <<
2062 also enabling support for pointer a <<
2063 enabling this option you should als <<
2064 <<
2065 Userspace binaries must also be spe <<
2066 this mechanism. If you say N here <<
2067 BTI, such binaries can still run, b <<
2068 enforcement of branch destinations. <<
2069 2913
2070 config ARM64_BTI_KERNEL !! 2914 config SYS_SUPPORTS_250HZ
2071 bool "Use Branch Target Identificatio !! 2915 bool
2072 default y <<
2073 depends on ARM64_BTI <<
2074 depends on ARM64_PTR_AUTH_KERNEL <<
2075 depends on CC_HAS_BRANCH_PROT_PAC_RET <<
2076 # https://gcc.gnu.org/bugzilla/show_b <<
2077 depends on !CC_IS_GCC || GCC_VERSION <<
2078 # https://gcc.gnu.org/bugzilla/show_b <<
2079 depends on !CC_IS_GCC <<
2080 depends on (!FUNCTION_GRAPH_TRACER || <<
2081 help <<
2082 Build the kernel with Branch Target <<
2083 and enable enforcement of this for <<
2084 is enabled and the system supports <<
2085 modular code must have BTI enabled. <<
2086 <<
2087 config CC_HAS_BRANCH_PROT_PAC_RET_BTI <<
2088 # GCC 9 or later, clang 8 or later <<
2089 def_bool $(cc-option,-mbranch-protect <<
2090 2916
2091 config ARM64_E0PD !! 2917 config SYS_SUPPORTS_256HZ
2092 bool "Enable support for E0PD" !! 2918 bool
2093 default y <<
2094 help <<
2095 E0PD (part of the ARMv8.5 extension <<
2096 that EL0 accesses made via TTBR1 al <<
2097 providing similar benefits to KASLR <<
2098 with lower overhead and without dis <<
2099 kernel memory such as SPE. <<
2100 <<
2101 This option enables E0PD for TTBR1 <<
2102 <<
2103 config ARM64_AS_HAS_MTE <<
2104 # Initial support for MTE went in bin <<
2105 # ".arch armv8.5-a+memtag" below. How <<
2106 # as a late addition to the final arc <<
2107 # is only supported in the newer 2.32 <<
2108 # versions, hence the extra "stgm" in <<
2109 def_bool $(as-instr,.arch armv8.5-a+m <<
2110 2919
2111 config ARM64_MTE !! 2920 config SYS_SUPPORTS_1000HZ
2112 bool "Memory Tagging Extension suppor !! 2921 bool
2113 default y <<
2114 depends on ARM64_AS_HAS_MTE && ARM64_ <<
2115 depends on AS_HAS_ARMV8_5 <<
2116 depends on AS_HAS_LSE_ATOMICS <<
2117 # Required for tag checking in the ua <<
2118 depends on ARM64_PAN <<
2119 select ARCH_HAS_SUBPAGE_FAULTS <<
2120 select ARCH_USES_HIGH_VMA_FLAGS <<
2121 select ARCH_USES_PG_ARCH_2 <<
2122 select ARCH_USES_PG_ARCH_3 <<
2123 help <<
2124 Memory Tagging (part of the ARMv8.5 <<
2125 architectural support for run-time, <<
2126 various classes of memory error to <<
2127 to eliminate vulnerabilities arisin <<
2128 languages. <<
2129 <<
2130 This option enables the support for <<
2131 Extension at EL0 (i.e. for userspac <<
2132 <<
2133 Selecting this option allows the fe <<
2134 runtime. Any secondary CPU not impl <<
2135 not be allowed a late bring-up. <<
2136 <<
2137 Userspace binaries that want to use <<
2138 explicitly opt in. The mechanism fo <<
2139 described in: <<
2140 2922
2141 Documentation/arch/arm64/memory-tag !! 2923 config SYS_SUPPORTS_1024HZ
>> 2924 bool
2142 2925
2143 endmenu # "ARMv8.5 architectural features" !! 2926 config SYS_SUPPORTS_ARBIT_HZ
>> 2927 bool
>> 2928 default y if !SYS_SUPPORTS_24HZ && \
>> 2929 !SYS_SUPPORTS_48HZ && \
>> 2930 !SYS_SUPPORTS_100HZ && \
>> 2931 !SYS_SUPPORTS_128HZ && \
>> 2932 !SYS_SUPPORTS_250HZ && \
>> 2933 !SYS_SUPPORTS_256HZ && \
>> 2934 !SYS_SUPPORTS_1000HZ && \
>> 2935 !SYS_SUPPORTS_1024HZ
2144 2936
2145 menu "ARMv8.7 architectural features" !! 2937 config HZ
>> 2938 int
>> 2939 default 24 if HZ_24
>> 2940 default 48 if HZ_48
>> 2941 default 100 if HZ_100
>> 2942 default 128 if HZ_128
>> 2943 default 250 if HZ_250
>> 2944 default 256 if HZ_256
>> 2945 default 1000 if HZ_1000
>> 2946 default 1024 if HZ_1024
>> 2947
>> 2948 config SCHED_HRTICK
>> 2949 def_bool HIGH_RES_TIMERS
>> 2950
>> 2951 config KEXEC
>> 2952 bool "Kexec system call"
>> 2953 select KEXEC_CORE
>> 2954 help
>> 2955 kexec is a system call that implements the ability to shutdown your
>> 2956 current kernel, and to start another kernel. It is like a reboot
>> 2957 but it is independent of the system firmware. And like a reboot
>> 2958 you can start any kernel with it, not just Linux.
>> 2959
>> 2960 The name comes from the similarity to the exec system call.
>> 2961
>> 2962 It is an ongoing process to be certain the hardware in a machine
>> 2963 is properly shutdown, so do not be surprised if this code does not
>> 2964 initially work for you. As of this writing the exact hardware
>> 2965 interface is strongly in flux, so no good recommendation can be
>> 2966 made.
>> 2967
>> 2968 config CRASH_DUMP
>> 2969 bool "Kernel crash dumps"
>> 2970 help
>> 2971 Generate crash dump after being started by kexec.
>> 2972 This should be normally only set in special crash dump kernels
>> 2973 which are loaded in the main kernel with kexec-tools into
>> 2974 a specially reserved region and then later executed after
>> 2975 a crash by kdump/kexec. The crash dump kernel must be compiled
>> 2976 to a memory address not used by the main kernel or firmware using
>> 2977 PHYSICAL_START.
>> 2978
>> 2979 config PHYSICAL_START
>> 2980 hex "Physical address where the kernel is loaded"
>> 2981 default "0xffffffff84000000"
>> 2982 depends on CRASH_DUMP
>> 2983 help
>> 2984 This gives the CKSEG0 or KSEG0 address where the kernel is loaded.
>> 2985 If you plan to use kernel for capturing the crash dump change
>> 2986 this value to start of the reserved region (the "X" value as
>> 2987 specified in the "crashkernel=YM@XM" command line boot parameter
>> 2988 passed to the panic-ed kernel).
>> 2989
>> 2990 config MIPS_O32_FP64_SUPPORT
>> 2991 bool "Support for O32 binaries using 64-bit FP" if !CPU_MIPSR6
>> 2992 depends on 32BIT || MIPS32_O32
>> 2993 help
>> 2994 When this is enabled, the kernel will support use of 64-bit floating
>> 2995 point registers with binaries using the O32 ABI along with the
>> 2996 EF_MIPS_FP64 ELF header flag (typically built with -mfp64). On
>> 2997 32-bit MIPS systems this support is at the cost of increasing the
>> 2998 size and complexity of the compiled FPU emulator. Thus if you are
>> 2999 running a MIPS32 system and know that none of your userland binaries
>> 3000 will require 64-bit floating point, you may wish to reduce the size
>> 3001 of your kernel & potentially improve FP emulation performance by
>> 3002 saying N here.
>> 3003
>> 3004 Although binutils currently supports use of this flag the details
>> 3005 concerning its effect upon the O32 ABI in userland are still being
>> 3006 worked on. In order to avoid userland becoming dependent upon current
>> 3007 behaviour before the details have been finalised, this option should
>> 3008 be considered experimental and only enabled by those working upon
>> 3009 said details.
2146 3010
2147 config ARM64_EPAN !! 3011 If unsure, say N.
2148 bool "Enable support for Enhanced Pri <<
2149 default y <<
2150 depends on ARM64_PAN <<
2151 help <<
2152 Enhanced Privileged Access Never (E <<
2153 Access Never to be used with Execut <<
2154 3012
2155 The feature is detected at runtime, !! 3013 config USE_OF
2156 if the cpu does not implement the f !! 3014 bool
2157 endmenu # "ARMv8.7 architectural features" !! 3015 select OF
>> 3016 select OF_EARLY_FLATTREE
>> 3017 select IRQ_DOMAIN
2158 3018
2159 menu "ARMv8.9 architectural features" !! 3019 config UHI_BOOT
>> 3020 bool
2160 3021
2161 config ARM64_POE !! 3022 config BUILTIN_DTB
2162 prompt "Permission Overlay Extension" !! 3023 bool
2163 def_bool y <<
2164 select ARCH_USES_HIGH_VMA_FLAGS <<
2165 select ARCH_HAS_PKEYS <<
2166 help <<
2167 The Permission Overlay Extension is <<
2168 Protection Keys. Memory Protection <<
2169 enforcing page-based protections, b <<
2170 of the page tables when an applicat <<
2171 3024
2172 For details, see Documentation/core !! 3025 choice
>> 3026 prompt "Kernel appended dtb support" if USE_OF
>> 3027 default MIPS_NO_APPENDED_DTB
2173 3028
2174 If unsure, say y. !! 3029 config MIPS_NO_APPENDED_DTB
>> 3030 bool "None"
>> 3031 help
>> 3032 Do not enable appended dtb support.
>> 3033
>> 3034 config MIPS_ELF_APPENDED_DTB
>> 3035 bool "vmlinux"
>> 3036 help
>> 3037 With this option, the boot code will look for a device tree binary
>> 3038 DTB) included in the vmlinux ELF section .appended_dtb. By default
>> 3039 it is empty and the DTB can be appended using binutils command
>> 3040 objcopy:
>> 3041
>> 3042 objcopy --update-section .appended_dtb=<filename>.dtb vmlinux
>> 3043
>> 3044 This is meant as a backward compatibility convenience for those
>> 3045 systems with a bootloader that can't be upgraded to accommodate
>> 3046 the documented boot protocol using a device tree.
>> 3047
>> 3048 config MIPS_RAW_APPENDED_DTB
>> 3049 bool "vmlinux.bin or vmlinuz.bin"
>> 3050 help
>> 3051 With this option, the boot code will look for a device tree binary
>> 3052 DTB) appended to raw vmlinux.bin or vmlinuz.bin.
>> 3053 (e.g. cat vmlinux.bin <filename>.dtb > vmlinux_w_dtb).
>> 3054
>> 3055 This is meant as a backward compatibility convenience for those
>> 3056 systems with a bootloader that can't be upgraded to accommodate
>> 3057 the documented boot protocol using a device tree.
>> 3058
>> 3059 Beware that there is very little in terms of protection against
>> 3060 this option being confused by leftover garbage in memory that might
>> 3061 look like a DTB header after a reboot if no actual DTB is appended
>> 3062 to vmlinux.bin. Do not leave this option active in a production kernel
>> 3063 if you don't intend to always append a DTB.
>> 3064 endchoice
2175 3065
2176 config ARCH_PKEY_BITS !! 3066 choice
2177 int !! 3067 prompt "Kernel command line type" if !CMDLINE_OVERRIDE
2178 default 3 !! 3068 default MIPS_CMDLINE_FROM_DTB if USE_OF && !ATH79 && !MACH_INGENIC && \
>> 3069 !MACH_LOONGSON64 && !MIPS_MALTA && \
>> 3070 !CAVIUM_OCTEON_SOC
>> 3071 default MIPS_CMDLINE_FROM_BOOTLOADER
>> 3072
>> 3073 config MIPS_CMDLINE_FROM_DTB
>> 3074 depends on USE_OF
>> 3075 bool "Dtb kernel arguments if available"
>> 3076
>> 3077 config MIPS_CMDLINE_DTB_EXTEND
>> 3078 depends on USE_OF
>> 3079 bool "Extend dtb kernel arguments with bootloader arguments"
>> 3080
>> 3081 config MIPS_CMDLINE_FROM_BOOTLOADER
>> 3082 bool "Bootloader kernel arguments if available"
>> 3083
>> 3084 config MIPS_CMDLINE_BUILTIN_EXTEND
>> 3085 depends on CMDLINE_BOOL
>> 3086 bool "Extend builtin kernel arguments with bootloader arguments"
>> 3087 endchoice
2179 3088
2180 endmenu # "ARMv8.9 architectural features" !! 3089 endmenu
2181 3090
2182 config ARM64_SVE !! 3091 config LOCKDEP_SUPPORT
2183 bool "ARM Scalable Vector Extension s !! 3092 bool
2184 default y 3093 default y
2185 help <<
2186 The Scalable Vector Extension (SVE) <<
2187 execution state which complements a <<
2188 of the base architecture to support <<
2189 additional vectorisation opportunit <<
2190 <<
2191 To enable use of this extension on <<
2192 <<
2193 On CPUs that support the SVE2 exten <<
2194 those too. <<
2195 <<
2196 Note that for architectural reasons <<
2197 support when running on SVE capable <<
2198 is present in: <<
2199 <<
2200 * version 1.5 and later of the AR <<
2201 * the AArch64 boot wrapper since <<
2202 ("bootwrapper: SVE: Enable SVE <<
2203 <<
2204 For other firmware implementations, <<
2205 or vendor. <<
2206 <<
2207 If you need the kernel to boot on S <<
2208 firmware, you may need to say N her <<
2209 fixed. Otherwise, you may experien <<
2210 booting the kernel. If unsure and <<
2211 symptoms, you should assume that it <<
2212 3094
2213 config ARM64_SME !! 3095 config STACKTRACE_SUPPORT
2214 bool "ARM Scalable Matrix Extension s !! 3096 bool
2215 default y 3097 default y
2216 depends on ARM64_SVE <<
2217 depends on BROKEN <<
2218 help <<
2219 The Scalable Matrix Extension (SME) <<
2220 execution state which utilises a su <<
2221 instruction set, together with the <<
2222 register state capable of holding t <<
2223 enable various matrix operations. <<
2224 <<
2225 config ARM64_PSEUDO_NMI <<
2226 bool "Support for NMI-like interrupts <<
2227 select ARM_GIC_V3 <<
2228 help <<
2229 Adds support for mimicking Non-Mask <<
2230 GIC interrupt priority. This suppor <<
2231 ARM GIC. <<
2232 <<
2233 This high priority configuration fo <<
2234 explicitly enabled by setting the k <<
2235 "irqchip.gicv3_pseudo_nmi" to 1. <<
2236 <<
2237 If unsure, say N <<
2238 <<
2239 if ARM64_PSEUDO_NMI <<
2240 config ARM64_DEBUG_PRIORITY_MASKING <<
2241 bool "Debug interrupt priority maskin <<
2242 help <<
2243 This adds runtime checks to functio <<
2244 interrupts when using priority mask <<
2245 the validity of ICC_PMR_EL1 when ca <<
2246 3098
2247 If unsure, say N !! 3099 config PGTABLE_LEVELS
2248 endif # ARM64_PSEUDO_NMI !! 3100 int
>> 3101 default 4 if PAGE_SIZE_4KB && MIPS_VA_BITS_48
>> 3102 default 3 if 64BIT && (!PAGE_SIZE_64KB || MIPS_VA_BITS_48)
>> 3103 default 2
2249 3104
2250 config RELOCATABLE !! 3105 config MIPS_AUTO_PFN_OFFSET
2251 bool "Build a relocatable kernel imag !! 3106 bool
2252 select ARCH_HAS_RELR <<
2253 default y <<
2254 help <<
2255 This builds the kernel as a Positio <<
2256 which retains all relocation metada <<
2257 kernel binary at runtime to a diffe <<
2258 address it was linked at. <<
2259 Since AArch64 uses the RELA relocat <<
2260 relocation pass at runtime even if <<
2261 same address it was linked at. <<
2262 3107
2263 config RANDOMIZE_BASE !! 3108 menu "Bus options (PCI, PCMCIA, EISA, ISA, TC)"
2264 bool "Randomize the address of the ke <<
2265 select RELOCATABLE <<
2266 help <<
2267 Randomizes the virtual address at w <<
2268 loaded, as a security feature that <<
2269 relying on knowledge of the locatio <<
2270 <<
2271 It is the bootloader's job to provi <<
2272 random u64 value in /chosen/kaslr-s <<
2273 <<
2274 When booting via the UEFI stub, it <<
2275 EFI_RNG_PROTOCOL implementation (if <<
2276 to the kernel proper. In addition, <<
2277 location of the kernel Image as wel <<
2278 3109
2279 If unsure, say N. !! 3110 config PCI_DRIVERS_GENERIC
>> 3111 select PCI_DOMAINS_GENERIC if PCI
>> 3112 bool
2280 3113
2281 config RANDOMIZE_MODULE_REGION_FULL !! 3114 config PCI_DRIVERS_LEGACY
2282 bool "Randomize the module region ove !! 3115 def_bool !PCI_DRIVERS_GENERIC
2283 depends on RANDOMIZE_BASE !! 3116 select NO_GENERIC_PCI_IOPORT_MAP
2284 default y !! 3117 select PCI_DOMAINS if PCI
2285 help <<
2286 Randomizes the location of the modu <<
2287 covering the core kernel. This way, <<
2288 to leak information about the locat <<
2289 but it does imply that function cal <<
2290 kernel will need to be resolved via <<
2291 <<
2292 When this option is not set, the mo <<
2293 a limited range that contains the [ <<
2294 core kernel, so branch relocations <<
2295 the region is exhausted. In this pa <<
2296 exhaustion, modules might be able t <<
2297 3118
2298 config CC_HAVE_STACKPROTECTOR_SYSREG !! 3119 #
2299 def_bool $(cc-option,-mstack-protecto !! 3120 # ISA support is now enabled via select. Too many systems still have the one
>> 3121 # or other ISA chip on the board that users don't know about so don't expect
>> 3122 # users to choose the right thing ...
>> 3123 #
>> 3124 config ISA
>> 3125 bool
2300 3126
2301 config STACKPROTECTOR_PER_TASK !! 3127 config TC
2302 def_bool y !! 3128 bool "TURBOchannel support"
2303 depends on STACKPROTECTOR && CC_HAVE_ !! 3129 depends on MACH_DECSTATION
>> 3130 help
>> 3131 TURBOchannel is a DEC (now Compaq (now HP)) bus for Alpha and MIPS
>> 3132 processors. TURBOchannel programming specifications are available
>> 3133 at:
>> 3134 <ftp://ftp.hp.com/pub/alphaserver/archive/triadd/>
>> 3135 and:
>> 3136 <http://www.computer-refuge.org/classiccmp/ftp.digital.com/pub/DEC/TriAdd/>
>> 3137 Linux driver support status is documented at:
>> 3138 <http://www.linux-mips.org/wiki/DECstation>
2304 3139
2305 config UNWIND_PATCH_PAC_INTO_SCS !! 3140 config MMU
2306 bool "Enable shadow call stack dynami !! 3141 bool
2307 # needs Clang with https://github.com <<
2308 depends on CC_IS_CLANG && CLANG_VERSI <<
2309 depends on ARM64_PTR_AUTH_KERNEL && C <<
2310 depends on SHADOW_CALL_STACK <<
2311 select UNWIND_TABLES <<
2312 select DYNAMIC_SCS <<
2313 <<
2314 config ARM64_CONTPTE <<
2315 bool "Contiguous PTE mappings for use <<
2316 depends on TRANSPARENT_HUGEPAGE <<
2317 default y 3142 default y
2318 help <<
2319 When enabled, user mappings are con <<
2320 bit, for any mappings that meet the <<
2321 This reduces TLB pressure and impro <<
2322 <<
2323 endmenu # "Kernel Features" <<
2324 <<
2325 menu "Boot options" <<
2326 <<
2327 config ARM64_ACPI_PARKING_PROTOCOL <<
2328 bool "Enable support for the ARM64 AC <<
2329 depends on ACPI <<
2330 help <<
2331 Enable support for the ARM64 ACPI p <<
2332 the kernel will not allow booting t <<
2333 protocol even if the corresponding <<
2334 MADT table. <<
2335 <<
2336 config CMDLINE <<
2337 string "Default kernel command string <<
2338 default "" <<
2339 help <<
2340 Provide a set of default command-li <<
2341 entering them here. As a minimum, y <<
2342 root device (e.g. root=/dev/nfs). <<
2343 3143
2344 choice !! 3144 config ARCH_MMAP_RND_BITS_MIN
2345 prompt "Kernel command line type" !! 3145 default 12 if 64BIT
2346 depends on CMDLINE != "" !! 3146 default 8
2347 default CMDLINE_FROM_BOOTLOADER <<
2348 help <<
2349 Choose how the kernel will handle t <<
2350 command line string. <<
2351 <<
2352 config CMDLINE_FROM_BOOTLOADER <<
2353 bool "Use bootloader kernel arguments <<
2354 help <<
2355 Uses the command-line options passe <<
2356 the boot loader doesn't provide any <<
2357 string provided in CMDLINE will be <<
2358 <<
2359 config CMDLINE_FORCE <<
2360 bool "Always use the default kernel c <<
2361 help <<
2362 Always use the default kernel comma <<
2363 loader passes other arguments to th <<
2364 This is useful if you cannot or don <<
2365 command-line options your boot load <<
2366 3147
2367 endchoice !! 3148 config ARCH_MMAP_RND_BITS_MAX
>> 3149 default 18 if 64BIT
>> 3150 default 15
>> 3151
>> 3152 config ARCH_MMAP_RND_COMPAT_BITS_MIN
>> 3153 default 8
2368 3154
2369 config EFI_STUB !! 3155 config ARCH_MMAP_RND_COMPAT_BITS_MAX
>> 3156 default 15
>> 3157
>> 3158 config I8253
2370 bool 3159 bool
>> 3160 select CLKSRC_I8253
>> 3161 select CLKEVT_I8253
>> 3162 select MIPS_EXTERNAL_TIMER
>> 3163 endmenu
2371 3164
2372 config EFI !! 3165 config TRAD_SIGNALS
2373 bool "UEFI runtime support" !! 3166 bool
2374 depends on OF && !CPU_BIG_ENDIAN <<
2375 depends on KERNEL_MODE_NEON <<
2376 select ARCH_SUPPORTS_ACPI <<
2377 select LIBFDT <<
2378 select UCS2_STRING <<
2379 select EFI_PARAMS_FROM_FDT <<
2380 select EFI_RUNTIME_WRAPPERS <<
2381 select EFI_STUB <<
2382 select EFI_GENERIC_STUB <<
2383 imply IMA_SECURE_AND_OR_TRUSTED_BOOT <<
2384 default y <<
2385 help <<
2386 This option provides support for ru <<
2387 by UEFI firmware (such as non-volat <<
2388 clock, and platform reset). A UEFI <<
2389 allow the kernel to be booted as an <<
2390 is only useful on systems that have <<
2391 <<
2392 config COMPRESSED_INSTALL <<
2393 bool "Install compressed image by def <<
2394 help <<
2395 This makes the regular "make instal <<
2396 image we built, not the legacy unco <<
2397 <<
2398 You can check that a compressed ima <<
2399 "make zinstall" first, and verifyin <<
2400 in your environment before making " <<
2401 you. <<
2402 3167
2403 config DMI !! 3168 config MIPS32_COMPAT
2404 bool "Enable support for SMBIOS (DMI) !! 3169 bool
2405 depends on EFI <<
2406 default y <<
2407 help <<
2408 This enables SMBIOS/DMI feature for <<
2409 3170
2410 This option is only useful on syste !! 3171 config COMPAT
2411 However, even with this option, the !! 3172 bool
2412 continue to boot on existing non-UE <<
2413 3173
2414 endmenu # "Boot options" !! 3174 config MIPS32_O32
>> 3175 bool "Kernel support for o32 binaries"
>> 3176 depends on 64BIT
>> 3177 select ARCH_WANT_OLD_COMPAT_IPC
>> 3178 select COMPAT
>> 3179 select MIPS32_COMPAT
>> 3180 help
>> 3181 Select this option if you want to run o32 binaries. These are pure
>> 3182 32-bit binaries as used by the 32-bit Linux/MIPS port. Most of
>> 3183 existing binaries are in this format.
2415 3184
2416 menu "Power management options" !! 3185 If unsure, say Y.
2417 3186
2418 source "kernel/power/Kconfig" !! 3187 config MIPS32_N32
>> 3188 bool "Kernel support for n32 binaries"
>> 3189 depends on 64BIT
>> 3190 select ARCH_WANT_COMPAT_IPC_PARSE_VERSION
>> 3191 select COMPAT
>> 3192 select MIPS32_COMPAT
>> 3193 help
>> 3194 Select this option if you want to run n32 binaries. These are
>> 3195 64-bit binaries using 32-bit quantities for addressing and certain
>> 3196 data that would normally be 64-bit. They are used in special
>> 3197 cases.
2419 3198
2420 config ARCH_HIBERNATION_POSSIBLE !! 3199 If unsure, say N.
>> 3200
>> 3201 config CC_HAS_MNO_BRANCH_LIKELY
2421 def_bool y 3202 def_bool y
2422 depends on CPU_PM !! 3203 depends on $(cc-option,-mno-branch-likely)
2423 3204
2424 config ARCH_HIBERNATION_HEADER !! 3205 # https://github.com/llvm/llvm-project/issues/61045
>> 3206 config CC_HAS_BROKEN_INLINE_COMPAT_BRANCH
>> 3207 def_bool y if CC_IS_CLANG
>> 3208
>> 3209 menu "Power management options"
>> 3210
>> 3211 config ARCH_HIBERNATION_POSSIBLE
2425 def_bool y 3212 def_bool y
2426 depends on HIBERNATION !! 3213 depends on SYS_SUPPORTS_HOTPLUG_CPU || !SMP
2427 3214
2428 config ARCH_SUSPEND_POSSIBLE 3215 config ARCH_SUSPEND_POSSIBLE
2429 def_bool y 3216 def_bool y
>> 3217 depends on SYS_SUPPORTS_HOTPLUG_CPU || !SMP
2430 3218
2431 endmenu # "Power management options" !! 3219 source "kernel/power/Kconfig"
2432 3220
2433 menu "CPU Power Management" !! 3221 endmenu
2434 3222
2435 source "drivers/cpuidle/Kconfig" !! 3223 config MIPS_EXTERNAL_TIMER
>> 3224 bool
2436 3225
>> 3226 menu "CPU Power Management"
>> 3227
>> 3228 if CPU_SUPPORTS_CPUFREQ && MIPS_EXTERNAL_TIMER
2437 source "drivers/cpufreq/Kconfig" 3229 source "drivers/cpufreq/Kconfig"
>> 3230 endif # CPU_SUPPORTS_CPUFREQ && MIPS_EXTERNAL_TIMER
2438 3231
2439 endmenu # "CPU Power Management" !! 3232 source "drivers/cpuidle/Kconfig"
2440 3233
2441 source "drivers/acpi/Kconfig" !! 3234 endmenu
2442 3235
2443 source "arch/arm64/kvm/Kconfig" !! 3236 source "arch/mips/kvm/Kconfig"
2444 3237
>> 3238 source "arch/mips/vdso/Kconfig"
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