1 # SPDX-License-Identifier: GPL-2.0-only !! 1 # SPDX-License-Identifier: GPL-2.0
2 config ARM64 !! 2 config MIPS
3 def_bool y !! 3 bool
4 select ACPI_APMT if ACPI !! 4 default y
5 select ACPI_CCA_REQUIRED if ACPI !! 5 select ARCH_32BIT_OFF_T if !64BIT
6 select ACPI_GENERIC_GSI if ACPI !! 6 select ARCH_BINFMT_ELF_STATE if MIPS_FP_SUPPORT
7 select ACPI_GTDT if ACPI !! 7 select ARCH_HAS_CPU_FINALIZE_INIT
8 select ACPI_HOTPLUG_CPU if ACPI_PROCES !! 8 select ARCH_HAS_CURRENT_STACK_POINTER if !CC_IS_CLANG || CLANG_VERSION >= 140000
9 select ACPI_IORT if ACPI !! 9 select ARCH_HAS_DEBUG_VIRTUAL if !64BIT
10 select ACPI_REDUCED_HARDWARE_ONLY if A <<
11 select ACPI_MCFG if (ACPI && PCI) <<
12 select ACPI_SPCR_TABLE if ACPI <<
13 select ACPI_PPTT if ACPI <<
14 select ARCH_HAS_DEBUG_WX <<
15 select ARCH_BINFMT_ELF_EXTRA_PHDRS <<
16 select ARCH_BINFMT_ELF_STATE <<
17 select ARCH_CORRECT_STACKTRACE_ON_KRET <<
18 select ARCH_ENABLE_HUGEPAGE_MIGRATION <<
19 select ARCH_ENABLE_MEMORY_HOTPLUG <<
20 select ARCH_ENABLE_MEMORY_HOTREMOVE <<
21 select ARCH_ENABLE_SPLIT_PMD_PTLOCK if <<
22 select ARCH_ENABLE_THP_MIGRATION if TR <<
23 select ARCH_HAS_CACHE_LINE_SIZE <<
24 select ARCH_HAS_CURRENT_STACK_POINTER <<
25 select ARCH_HAS_DEBUG_VIRTUAL <<
26 select ARCH_HAS_DEBUG_VM_PGTABLE <<
27 select ARCH_HAS_DMA_OPS if XEN <<
28 select ARCH_HAS_DMA_PREP_COHERENT <<
29 select ARCH_HAS_ACPI_TABLE_UPGRADE if <<
30 select ARCH_HAS_FAST_MULTIPLIER <<
31 select ARCH_HAS_FORTIFY_SOURCE 10 select ARCH_HAS_FORTIFY_SOURCE
32 select ARCH_HAS_GCOV_PROFILE_ALL <<
33 select ARCH_HAS_GIGANTIC_PAGE <<
34 select ARCH_HAS_KCOV 11 select ARCH_HAS_KCOV
35 select ARCH_HAS_KERNEL_FPU_SUPPORT if !! 12 select ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE if !EVA
36 select ARCH_HAS_KEEPINITRD !! 13 select ARCH_HAS_PTE_SPECIAL if !(32BIT && CPU_HAS_RIXI)
37 select ARCH_HAS_MEMBARRIER_SYNC_CORE !! 14 select ARCH_HAS_STRNCPY_FROM_USER
38 select ARCH_HAS_MEM_ENCRYPT !! 15 select ARCH_HAS_STRNLEN_USER
39 select ARCH_HAS_NMI_SAFE_THIS_CPU_OPS <<
40 select ARCH_HAS_NON_OVERLAPPING_ADDRES <<
41 select ARCH_HAS_PTE_DEVMAP <<
42 select ARCH_HAS_PTE_SPECIAL <<
43 select ARCH_HAS_HW_PTE_YOUNG <<
44 select ARCH_HAS_SETUP_DMA_OPS <<
45 select ARCH_HAS_SET_DIRECT_MAP <<
46 select ARCH_HAS_SET_MEMORY <<
47 select ARCH_STACKWALK <<
48 select ARCH_HAS_STRICT_KERNEL_RWX <<
49 select ARCH_HAS_STRICT_MODULE_RWX <<
50 select ARCH_HAS_SYNC_DMA_FOR_DEVICE <<
51 select ARCH_HAS_SYNC_DMA_FOR_CPU <<
52 select ARCH_HAS_SYSCALL_WRAPPER <<
53 select ARCH_HAS_TICK_BROADCAST if GENE 16 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
54 select ARCH_HAS_ZONE_DMA_SET if EXPERT !! 17 select ARCH_HAS_UBSAN_SANITIZE_ALL
55 select ARCH_HAVE_ELF_PROT !! 18 select ARCH_HAS_GCOV_PROFILE_ALL
56 select ARCH_HAVE_NMI_SAFE_CMPXCHG <<
57 select ARCH_HAVE_TRACE_MMIO_ACCESS <<
58 select ARCH_INLINE_READ_LOCK if !PREEM <<
59 select ARCH_INLINE_READ_LOCK_BH if !PR <<
60 select ARCH_INLINE_READ_LOCK_IRQ if !P <<
61 select ARCH_INLINE_READ_LOCK_IRQSAVE i <<
62 select ARCH_INLINE_READ_UNLOCK if !PRE <<
63 select ARCH_INLINE_READ_UNLOCK_BH if ! <<
64 select ARCH_INLINE_READ_UNLOCK_IRQ if <<
65 select ARCH_INLINE_READ_UNLOCK_IRQREST <<
66 select ARCH_INLINE_WRITE_LOCK if !PREE <<
67 select ARCH_INLINE_WRITE_LOCK_BH if !P <<
68 select ARCH_INLINE_WRITE_LOCK_IRQ if ! <<
69 select ARCH_INLINE_WRITE_LOCK_IRQSAVE <<
70 select ARCH_INLINE_WRITE_UNLOCK if !PR <<
71 select ARCH_INLINE_WRITE_UNLOCK_BH if <<
72 select ARCH_INLINE_WRITE_UNLOCK_IRQ if <<
73 select ARCH_INLINE_WRITE_UNLOCK_IRQRES <<
74 select ARCH_INLINE_SPIN_TRYLOCK if !PR <<
75 select ARCH_INLINE_SPIN_TRYLOCK_BH if <<
76 select ARCH_INLINE_SPIN_LOCK if !PREEM <<
77 select ARCH_INLINE_SPIN_LOCK_BH if !PR <<
78 select ARCH_INLINE_SPIN_LOCK_IRQ if !P <<
79 select ARCH_INLINE_SPIN_LOCK_IRQSAVE i <<
80 select ARCH_INLINE_SPIN_UNLOCK if !PRE <<
81 select ARCH_INLINE_SPIN_UNLOCK_BH if ! <<
82 select ARCH_INLINE_SPIN_UNLOCK_IRQ if <<
83 select ARCH_INLINE_SPIN_UNLOCK_IRQREST <<
84 select ARCH_KEEP_MEMBLOCK 19 select ARCH_KEEP_MEMBLOCK
85 select ARCH_MHP_MEMMAP_ON_MEMORY_ENABL !! 20 select ARCH_USE_BUILTIN_BSWAP
86 select ARCH_USE_CMPXCHG_LOCKREF !! 21 select ARCH_USE_CMPXCHG_LOCKREF if 64BIT
87 select ARCH_USE_GNU_PROPERTY <<
88 select ARCH_USE_MEMTEST 22 select ARCH_USE_MEMTEST
89 select ARCH_USE_QUEUED_RWLOCKS 23 select ARCH_USE_QUEUED_RWLOCKS
90 select ARCH_USE_QUEUED_SPINLOCKS 24 select ARCH_USE_QUEUED_SPINLOCKS
91 select ARCH_USE_SYM_ANNOTATIONS !! 25 select ARCH_SUPPORTS_HUGETLBFS if CPU_SUPPORTS_HUGEPAGES
92 select ARCH_SUPPORTS_DEBUG_PAGEALLOC !! 26 select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT if MMU
93 select ARCH_SUPPORTS_HUGETLBFS !! 27 select ARCH_WANT_IPC_PARSE_VERSION
94 select ARCH_SUPPORTS_MEMORY_FAILURE <<
95 select ARCH_SUPPORTS_SHADOW_CALL_STACK <<
96 select ARCH_SUPPORTS_LTO_CLANG if CPU_ <<
97 select ARCH_SUPPORTS_LTO_CLANG_THIN <<
98 select ARCH_SUPPORTS_CFI_CLANG <<
99 select ARCH_SUPPORTS_ATOMIC_RMW <<
100 select ARCH_SUPPORTS_INT128 if CC_HAS_ <<
101 select ARCH_SUPPORTS_NUMA_BALANCING <<
102 select ARCH_SUPPORTS_PAGE_TABLE_CHECK <<
103 select ARCH_SUPPORTS_PER_VMA_LOCK <<
104 select ARCH_SUPPORTS_HUGE_PFNMAP if TR <<
105 select ARCH_SUPPORTS_RT <<
106 select ARCH_WANT_BATCHED_UNMAP_TLB_FLU <<
107 select ARCH_WANT_COMPAT_IPC_PARSE_VERS <<
108 select ARCH_WANT_DEFAULT_BPF_JIT <<
109 select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_ <<
110 select ARCH_WANT_FRAME_POINTERS <<
111 select ARCH_WANT_HUGE_PMD_SHARE if ARM <<
112 select ARCH_WANT_LD_ORPHAN_WARN 28 select ARCH_WANT_LD_ORPHAN_WARN
113 select ARCH_WANTS_EXECMEM_LATE if EXEC <<
114 select ARCH_WANTS_NO_INSTR <<
115 select ARCH_WANTS_THP_SWAP if ARM64_4K <<
116 select ARCH_HAS_UBSAN <<
117 select ARM_AMBA <<
118 select ARM_ARCH_TIMER <<
119 select ARM_GIC <<
120 select AUDIT_ARCH_COMPAT_GENERIC <<
121 select ARM_GIC_V2M if PCI <<
122 select ARM_GIC_V3 <<
123 select ARM_GIC_V3_ITS if PCI <<
124 select ARM_PSCI_FW <<
125 select BUILDTIME_TABLE_SORT 29 select BUILDTIME_TABLE_SORT
126 select CLONE_BACKWARDS 30 select CLONE_BACKWARDS
127 select COMMON_CLK !! 31 select CPU_NO_EFFICIENT_FFS if (TARGET_ISA_REV < 1)
128 select CPU_PM if (SUSPEND || CPU_IDLE) !! 32 select CPU_PM if CPU_IDLE
129 select CPUMASK_OFFSTACK if NR_CPUS > 2 !! 33 select GENERIC_ATOMIC64 if !64BIT
130 select CRC32 !! 34 select GENERIC_CMOS_UPDATE
131 select DCACHE_WORD_ACCESS <<
132 select DYNAMIC_FTRACE if FUNCTION_TRAC <<
133 select DMA_BOUNCE_UNALIGNED_KMALLOC <<
134 select DMA_DIRECT_REMAP <<
135 select EDAC_SUPPORT <<
136 select FRAME_POINTER <<
137 select FUNCTION_ALIGNMENT_4B <<
138 select FUNCTION_ALIGNMENT_8B if DYNAMI <<
139 select GENERIC_ALLOCATOR <<
140 select GENERIC_ARCH_TOPOLOGY <<
141 select GENERIC_CLOCKEVENTS_BROADCAST <<
142 select GENERIC_CPU_AUTOPROBE 35 select GENERIC_CPU_AUTOPROBE
143 select GENERIC_CPU_DEVICES !! 36 select GENERIC_GETTIMEOFDAY
144 select GENERIC_CPU_VULNERABILITIES !! 37 select GENERIC_IOMAP
145 select GENERIC_EARLY_IOREMAP <<
146 select GENERIC_IDLE_POLL_SETUP <<
147 select GENERIC_IOREMAP <<
148 select GENERIC_IRQ_IPI <<
149 select GENERIC_IRQ_PROBE 38 select GENERIC_IRQ_PROBE
150 select GENERIC_IRQ_SHOW 39 select GENERIC_IRQ_SHOW
151 select GENERIC_IRQ_SHOW_LEVEL !! 40 select GENERIC_ISA_DMA if EISA
152 select GENERIC_LIB_DEVMEM_IS_ALLOWED !! 41 select GENERIC_LIB_ASHLDI3
153 select GENERIC_PCI_IOMAP !! 42 select GENERIC_LIB_ASHRDI3
154 select GENERIC_PTDUMP !! 43 select GENERIC_LIB_CMPDI2
155 select GENERIC_SCHED_CLOCK !! 44 select GENERIC_LIB_LSHRDI3
>> 45 select GENERIC_LIB_UCMPDI2
>> 46 select GENERIC_SCHED_CLOCK if !CAVIUM_OCTEON_SOC
156 select GENERIC_SMP_IDLE_THREAD 47 select GENERIC_SMP_IDLE_THREAD
157 select GENERIC_TIME_VSYSCALL 48 select GENERIC_TIME_VSYSCALL
158 select GENERIC_GETTIMEOFDAY !! 49 select GUP_GET_PXX_LOW_HIGH if CPU_MIPS32 && PHYS_ADDR_T_64BIT
159 select GENERIC_VDSO_TIME_NS !! 50 select HAS_IOPORT if !NO_IOPORT_MAP || ISA
160 select HARDIRQS_SW_RESEND <<
161 select HAS_IOPORT <<
162 select HAVE_MOVE_PMD <<
163 select HAVE_MOVE_PUD <<
164 select HAVE_PCI <<
165 select HAVE_ACPI_APEI if (ACPI && EFI) <<
166 select HAVE_ALIGNED_STRUCT_PAGE <<
167 select HAVE_ARCH_AUDITSYSCALL <<
168 select HAVE_ARCH_BITREVERSE <<
169 select HAVE_ARCH_COMPILER_H 51 select HAVE_ARCH_COMPILER_H
170 select HAVE_ARCH_HUGE_VMALLOC <<
171 select HAVE_ARCH_HUGE_VMAP <<
172 select HAVE_ARCH_JUMP_LABEL 52 select HAVE_ARCH_JUMP_LABEL
173 select HAVE_ARCH_JUMP_LABEL_RELATIVE !! 53 select HAVE_ARCH_KGDB if MIPS_FP_SUPPORT
174 select HAVE_ARCH_KASAN !! 54 select HAVE_ARCH_MMAP_RND_BITS if MMU
175 select HAVE_ARCH_KASAN_VMALLOC !! 55 select HAVE_ARCH_MMAP_RND_COMPAT_BITS if MMU && COMPAT
176 select HAVE_ARCH_KASAN_SW_TAGS <<
177 select HAVE_ARCH_KASAN_HW_TAGS if ARM6 <<
178 # Some instrumentation may be unsound, <<
179 select HAVE_ARCH_KCSAN if EXPERT <<
180 select HAVE_ARCH_KFENCE <<
181 select HAVE_ARCH_KGDB <<
182 select HAVE_ARCH_MMAP_RND_BITS <<
183 select HAVE_ARCH_MMAP_RND_COMPAT_BITS <<
184 select HAVE_ARCH_PREL32_RELOCATIONS <<
185 select HAVE_ARCH_RANDOMIZE_KSTACK_OFFS <<
186 select HAVE_ARCH_SECCOMP_FILTER 56 select HAVE_ARCH_SECCOMP_FILTER
187 select HAVE_ARCH_STACKLEAK <<
188 select HAVE_ARCH_THREAD_STRUCT_WHITELI <<
189 select HAVE_ARCH_TRACEHOOK 57 select HAVE_ARCH_TRACEHOOK
190 select HAVE_ARCH_TRANSPARENT_HUGEPAGE !! 58 select HAVE_ARCH_TRANSPARENT_HUGEPAGE if CPU_SUPPORTS_HUGEPAGES
191 select HAVE_ARCH_VMAP_STACK <<
192 select HAVE_ARM_SMCCC <<
193 select HAVE_ASM_MODVERSIONS 59 select HAVE_ASM_MODVERSIONS
194 select HAVE_EBPF_JIT <<
195 select HAVE_C_RECORDMCOUNT <<
196 select HAVE_CMPXCHG_DOUBLE <<
197 select HAVE_CMPXCHG_LOCAL <<
198 select HAVE_CONTEXT_TRACKING_USER 60 select HAVE_CONTEXT_TRACKING_USER
>> 61 select HAVE_TIF_NOHZ
>> 62 select HAVE_C_RECORDMCOUNT
199 select HAVE_DEBUG_KMEMLEAK 63 select HAVE_DEBUG_KMEMLEAK
>> 64 select HAVE_DEBUG_STACKOVERFLOW
200 select HAVE_DMA_CONTIGUOUS 65 select HAVE_DMA_CONTIGUOUS
201 select HAVE_DYNAMIC_FTRACE 66 select HAVE_DYNAMIC_FTRACE
202 select HAVE_DYNAMIC_FTRACE_WITH_ARGS \ !! 67 select HAVE_EBPF_JIT if !CPU_MICROMIPS
203 if (GCC_SUPPORTS_DYNAMIC_FTRAC !! 68 select HAVE_EXIT_THREAD
204 CLANG_SUPPORTS_DYNAMIC_FTR !! 69 select HAVE_FAST_GUP
205 select HAVE_DYNAMIC_FTRACE_WITH_DIRECT <<
206 if DYNAMIC_FTRACE_WITH_ARGS && <<
207 select HAVE_DYNAMIC_FTRACE_WITH_CALL_O <<
208 if (DYNAMIC_FTRACE_WITH_ARGS & <<
209 (CC_IS_CLANG || !CC_OPTIMI <<
210 select FTRACE_MCOUNT_USE_PATCHABLE_FUN <<
211 if DYNAMIC_FTRACE_WITH_ARGS <<
212 select HAVE_SAMPLE_FTRACE_DIRECT <<
213 select HAVE_SAMPLE_FTRACE_DIRECT_MULTI <<
214 select HAVE_EFFICIENT_UNALIGNED_ACCESS <<
215 select HAVE_GUP_FAST <<
216 select HAVE_FTRACE_MCOUNT_RECORD 70 select HAVE_FTRACE_MCOUNT_RECORD
217 select HAVE_FUNCTION_TRACER <<
218 select HAVE_FUNCTION_ERROR_INJECTION <<
219 select HAVE_FUNCTION_GRAPH_TRACER 71 select HAVE_FUNCTION_GRAPH_TRACER
220 select HAVE_FUNCTION_GRAPH_RETVAL !! 72 select HAVE_FUNCTION_TRACER
221 select HAVE_GCC_PLUGINS 73 select HAVE_GCC_PLUGINS
222 select HAVE_HARDLOCKUP_DETECTOR_PERF i !! 74 select HAVE_GENERIC_VDSO
223 HW_PERF_EVENTS && HAVE_PERF_EV <<
224 select HAVE_HW_BREAKPOINT if PERF_EVEN <<
225 select HAVE_IOREMAP_PROT 75 select HAVE_IOREMAP_PROT
>> 76 select HAVE_IRQ_EXIT_ON_IRQ_STACK
226 select HAVE_IRQ_TIME_ACCOUNTING 77 select HAVE_IRQ_TIME_ACCOUNTING
>> 78 select HAVE_KPROBES
>> 79 select HAVE_KRETPROBES
>> 80 select HAVE_LD_DEAD_CODE_DATA_ELIMINATION
227 select HAVE_MOD_ARCH_SPECIFIC 81 select HAVE_MOD_ARCH_SPECIFIC
228 select HAVE_NMI 82 select HAVE_NMI
>> 83 select HAVE_PATA_PLATFORM
229 select HAVE_PERF_EVENTS 84 select HAVE_PERF_EVENTS
230 select HAVE_PERF_EVENTS_NMI if ARM64_P <<
231 select HAVE_PERF_REGS 85 select HAVE_PERF_REGS
232 select HAVE_PERF_USER_STACK_DUMP 86 select HAVE_PERF_USER_STACK_DUMP
233 select HAVE_PREEMPT_DYNAMIC_KEY <<
234 select HAVE_REGS_AND_STACK_ACCESS_API 87 select HAVE_REGS_AND_STACK_ACCESS_API
235 select HAVE_POSIX_CPU_TIMERS_TASK_WORK <<
236 select HAVE_FUNCTION_ARG_ACCESS_API <<
237 select MMU_GATHER_RCU_TABLE_FREE <<
238 select HAVE_RSEQ 88 select HAVE_RSEQ
239 select HAVE_RUST if RUSTC_SUPPORTS_ARM !! 89 select HAVE_SPARSE_SYSCALL_NR
240 select HAVE_STACKPROTECTOR 90 select HAVE_STACKPROTECTOR
241 select HAVE_SYSCALL_TRACEPOINTS 91 select HAVE_SYSCALL_TRACEPOINTS
242 select HAVE_KPROBES !! 92 select HAVE_VIRT_CPU_ACCOUNTING_GEN if 64BIT || !SMP
243 select HAVE_KRETPROBES <<
244 select HAVE_GENERIC_VDSO <<
245 select HOTPLUG_CORE_SYNC_DEAD if HOTPL <<
246 select IRQ_DOMAIN <<
247 select IRQ_FORCED_THREADING 93 select IRQ_FORCED_THREADING
248 select KASAN_VMALLOC if KASAN !! 94 select ISA if EISA
249 select LOCK_MM_AND_FIND_VMA 95 select LOCK_MM_AND_FIND_VMA
250 select MODULES_USE_ELF_RELA !! 96 select MODULES_USE_ELF_REL if MODULES
251 select NEED_DMA_MAP_STATE !! 97 select MODULES_USE_ELF_RELA if MODULES && 64BIT
252 select NEED_SG_DMA_LENGTH !! 98 select PERF_USE_VMALLOC
253 select OF !! 99 select PCI_MSI_ARCH_FALLBACKS if PCI_MSI
254 select OF_EARLY_FLATTREE !! 100 select RTC_LIB
255 select PCI_DOMAINS_GENERIC if PCI <<
256 select PCI_ECAM if (ACPI && PCI) <<
257 select PCI_SYSCALL if PCI <<
258 select POWER_RESET <<
259 select POWER_SUPPLY <<
260 select SPARSE_IRQ <<
261 select SWIOTLB <<
262 select SYSCTL_EXCEPTION_TRACE 101 select SYSCTL_EXCEPTION_TRACE
263 select THREAD_INFO_IN_TASK <<
264 select HAVE_ARCH_USERFAULTFD_MINOR if <<
265 select HAVE_ARCH_USERFAULTFD_WP if USE <<
266 select TRACE_IRQFLAGS_SUPPORT 102 select TRACE_IRQFLAGS_SUPPORT
267 select TRACE_IRQFLAGS_NMI_SUPPORT !! 103 select ARCH_HAS_ELFCORE_COMPAT
268 select HAVE_SOFTIRQ_ON_OWN_STACK !! 104 select HAVE_ARCH_KCSAN if 64BIT
269 select USER_STACKTRACE_SUPPORT <<
270 select VDSO_GETRANDOM <<
271 help <<
272 ARM 64-bit (AArch64) Linux support. <<
273 <<
274 config RUSTC_SUPPORTS_ARM64 <<
275 def_bool y <<
276 depends on CPU_LITTLE_ENDIAN <<
277 # Shadow call stack is only supported <<
278 # <<
279 # When using the UNWIND_PATCH_PAC_INTO <<
280 # required due to use of the -Zfixed-x <<
281 # <<
282 # Otherwise, rustc version 1.82+ is re <<
283 # -Zsanitizer=shadow-call-stack flag. <<
284 depends on !SHADOW_CALL_STACK || RUSTC <<
285 <<
286 config CLANG_SUPPORTS_DYNAMIC_FTRACE_WITH_ARGS <<
287 def_bool CC_IS_CLANG <<
288 # https://github.com/ClangBuiltLinux/l <<
289 depends on AS_IS_GNU || (AS_IS_LLVM && <<
290 <<
291 config GCC_SUPPORTS_DYNAMIC_FTRACE_WITH_ARGS <<
292 def_bool CC_IS_GCC <<
293 depends on $(cc-option,-fpatchable-fun <<
294 <<
295 config 64BIT <<
296 def_bool y <<
297 <<
298 config MMU <<
299 def_bool y <<
300 <<
301 config ARM64_CONT_PTE_SHIFT <<
302 int <<
303 default 5 if PAGE_SIZE_64KB <<
304 default 7 if PAGE_SIZE_16KB <<
305 default 4 <<
306 105
307 config ARM64_CONT_PMD_SHIFT !! 106 config MIPS_FIXUP_BIGPHYS_ADDR
308 int !! 107 bool
309 default 5 if PAGE_SIZE_64KB <<
310 default 5 if PAGE_SIZE_16KB <<
311 default 4 <<
312 <<
313 config ARCH_MMAP_RND_BITS_MIN <<
314 default 14 if PAGE_SIZE_64KB <<
315 default 16 if PAGE_SIZE_16KB <<
316 default 18 <<
317 108
318 # max bits determined by the following formula !! 109 config MIPS_GENERIC
319 # VA_BITS - PAGE_SHIFT - 3 !! 110 bool
320 config ARCH_MMAP_RND_BITS_MAX <<
321 default 19 if ARM64_VA_BITS=36 <<
322 default 24 if ARM64_VA_BITS=39 <<
323 default 27 if ARM64_VA_BITS=42 <<
324 default 30 if ARM64_VA_BITS=47 <<
325 default 29 if ARM64_VA_BITS=48 && ARM6 <<
326 default 31 if ARM64_VA_BITS=48 && ARM6 <<
327 default 33 if ARM64_VA_BITS=48 <<
328 default 14 if ARM64_64K_PAGES <<
329 default 16 if ARM64_16K_PAGES <<
330 default 18 <<
331 111
332 config ARCH_MMAP_RND_COMPAT_BITS_MIN !! 112 config MACH_INGENIC
333 default 7 if ARM64_64K_PAGES !! 113 bool
334 default 9 if ARM64_16K_PAGES !! 114 select SYS_SUPPORTS_32BIT_KERNEL
335 default 11 !! 115 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 116 select SYS_SUPPORTS_ZBOOT
>> 117 select DMA_NONCOHERENT
>> 118 select IRQ_MIPS_CPU
>> 119 select PINCTRL
>> 120 select GPIOLIB
>> 121 select COMMON_CLK
>> 122 select GENERIC_IRQ_CHIP
>> 123 select BUILTIN_DTB if MIPS_NO_APPENDED_DTB
>> 124 select USE_OF
>> 125 select CPU_SUPPORTS_CPUFREQ
>> 126 select MIPS_EXTERNAL_TIMER
336 127
337 config ARCH_MMAP_RND_COMPAT_BITS_MAX !! 128 menu "Machine selection"
338 default 16 <<
339 129
340 config NO_IOPORT_MAP !! 130 choice
341 def_bool y if !PCI !! 131 prompt "System type"
>> 132 default MIPS_GENERIC_KERNEL
342 133
343 config STACKTRACE_SUPPORT !! 134 config MIPS_GENERIC_KERNEL
344 def_bool y !! 135 bool "Generic board-agnostic MIPS kernel"
>> 136 select MIPS_GENERIC
>> 137 select BOOT_RAW
>> 138 select BUILTIN_DTB
>> 139 select CEVT_R4K
>> 140 select CLKSRC_MIPS_GIC
>> 141 select COMMON_CLK
>> 142 select CPU_MIPSR2_IRQ_EI
>> 143 select CPU_MIPSR2_IRQ_VI
>> 144 select CSRC_R4K
>> 145 select DMA_NONCOHERENT
>> 146 select HAVE_PCI
>> 147 select IRQ_MIPS_CPU
>> 148 select MIPS_AUTO_PFN_OFFSET
>> 149 select MIPS_CPU_SCACHE
>> 150 select MIPS_GIC
>> 151 select MIPS_L1_CACHE_SHIFT_7
>> 152 select NO_EXCEPT_FILL
>> 153 select PCI_DRIVERS_GENERIC
>> 154 select SMP_UP if SMP
>> 155 select SWAP_IO_SPACE
>> 156 select SYS_HAS_CPU_MIPS32_R1
>> 157 select SYS_HAS_CPU_MIPS32_R2
>> 158 select SYS_HAS_CPU_MIPS32_R6
>> 159 select SYS_HAS_CPU_MIPS64_R1
>> 160 select SYS_HAS_CPU_MIPS64_R2
>> 161 select SYS_HAS_CPU_MIPS64_R6
>> 162 select SYS_SUPPORTS_32BIT_KERNEL
>> 163 select SYS_SUPPORTS_64BIT_KERNEL
>> 164 select SYS_SUPPORTS_BIG_ENDIAN
>> 165 select SYS_SUPPORTS_HIGHMEM
>> 166 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 167 select SYS_SUPPORTS_MICROMIPS
>> 168 select SYS_SUPPORTS_MIPS16
>> 169 select SYS_SUPPORTS_MIPS_CPS
>> 170 select SYS_SUPPORTS_MULTITHREADING
>> 171 select SYS_SUPPORTS_RELOCATABLE
>> 172 select SYS_SUPPORTS_SMARTMIPS
>> 173 select SYS_SUPPORTS_ZBOOT
>> 174 select UHI_BOOT
>> 175 select USB_EHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
>> 176 select USB_EHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 177 select USB_OHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
>> 178 select USB_OHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 179 select USB_UHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
>> 180 select USB_UHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 181 select USE_OF
>> 182 help
>> 183 Select this to build a kernel which aims to support multiple boards,
>> 184 generally using a flattened device tree passed from the bootloader
>> 185 using the boot protocol defined in the UHI (Unified Hosting
>> 186 Interface) specification.
>> 187
>> 188 config MIPS_ALCHEMY
>> 189 bool "Alchemy processor based machines"
>> 190 select PHYS_ADDR_T_64BIT
>> 191 select CEVT_R4K
>> 192 select CSRC_R4K
>> 193 select IRQ_MIPS_CPU
>> 194 select DMA_NONCOHERENT # Au1000,1500,1100 aren't, rest is
>> 195 select MIPS_FIXUP_BIGPHYS_ADDR if PCI
>> 196 select SYS_HAS_CPU_MIPS32_R1
>> 197 select SYS_SUPPORTS_32BIT_KERNEL
>> 198 select SYS_SUPPORTS_APM_EMULATION
>> 199 select GPIOLIB
>> 200 select SYS_SUPPORTS_ZBOOT
>> 201 select COMMON_CLK
345 202
346 config ILLEGAL_POINTER_VALUE !! 203 config AR7
347 hex !! 204 bool "Texas Instruments AR7"
348 default 0xdead000000000000 !! 205 select BOOT_ELF32
>> 206 select COMMON_CLK
>> 207 select DMA_NONCOHERENT
>> 208 select CEVT_R4K
>> 209 select CSRC_R4K
>> 210 select IRQ_MIPS_CPU
>> 211 select NO_EXCEPT_FILL
>> 212 select SWAP_IO_SPACE
>> 213 select SYS_HAS_CPU_MIPS32_R1
>> 214 select SYS_HAS_EARLY_PRINTK
>> 215 select SYS_SUPPORTS_32BIT_KERNEL
>> 216 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 217 select SYS_SUPPORTS_MIPS16
>> 218 select SYS_SUPPORTS_ZBOOT_UART16550
>> 219 select GPIOLIB
>> 220 select VLYNQ
>> 221 help
>> 222 Support for the Texas Instruments AR7 System-on-a-Chip
>> 223 family: TNETD7100, 7200 and 7300.
>> 224
>> 225 config ATH25
>> 226 bool "Atheros AR231x/AR531x SoC support"
>> 227 select CEVT_R4K
>> 228 select CSRC_R4K
>> 229 select DMA_NONCOHERENT
>> 230 select IRQ_MIPS_CPU
>> 231 select IRQ_DOMAIN
>> 232 select SYS_HAS_CPU_MIPS32_R1
>> 233 select SYS_SUPPORTS_BIG_ENDIAN
>> 234 select SYS_SUPPORTS_32BIT_KERNEL
>> 235 select SYS_HAS_EARLY_PRINTK
>> 236 help
>> 237 Support for Atheros AR231x and Atheros AR531x based boards
>> 238
>> 239 config ATH79
>> 240 bool "Atheros AR71XX/AR724X/AR913X based boards"
>> 241 select ARCH_HAS_RESET_CONTROLLER
>> 242 select BOOT_RAW
>> 243 select CEVT_R4K
>> 244 select CSRC_R4K
>> 245 select DMA_NONCOHERENT
>> 246 select GPIOLIB
>> 247 select PINCTRL
>> 248 select COMMON_CLK
>> 249 select IRQ_MIPS_CPU
>> 250 select SYS_HAS_CPU_MIPS32_R2
>> 251 select SYS_HAS_EARLY_PRINTK
>> 252 select SYS_SUPPORTS_32BIT_KERNEL
>> 253 select SYS_SUPPORTS_BIG_ENDIAN
>> 254 select SYS_SUPPORTS_MIPS16
>> 255 select SYS_SUPPORTS_ZBOOT_UART_PROM
>> 256 select USE_OF
>> 257 select USB_EHCI_ROOT_HUB_TT if USB_EHCI_HCD_PLATFORM
>> 258 help
>> 259 Support for the Atheros AR71XX/AR724X/AR913X SoCs.
>> 260
>> 261 config BMIPS_GENERIC
>> 262 bool "Broadcom Generic BMIPS kernel"
>> 263 select ARCH_HAS_RESET_CONTROLLER
>> 264 select ARCH_HAS_SYNC_DMA_FOR_CPU_ALL
>> 265 select BOOT_RAW
>> 266 select NO_EXCEPT_FILL
>> 267 select USE_OF
>> 268 select CEVT_R4K
>> 269 select CSRC_R4K
>> 270 select SYNC_R4K
>> 271 select COMMON_CLK
>> 272 select BCM6345_L1_IRQ
>> 273 select BCM7038_L1_IRQ
>> 274 select BCM7120_L2_IRQ
>> 275 select BRCMSTB_L2_IRQ
>> 276 select IRQ_MIPS_CPU
>> 277 select DMA_NONCOHERENT
>> 278 select SYS_SUPPORTS_32BIT_KERNEL
>> 279 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 280 select SYS_SUPPORTS_BIG_ENDIAN
>> 281 select SYS_SUPPORTS_HIGHMEM
>> 282 select SYS_HAS_CPU_BMIPS32_3300
>> 283 select SYS_HAS_CPU_BMIPS4350
>> 284 select SYS_HAS_CPU_BMIPS4380
>> 285 select SYS_HAS_CPU_BMIPS5000
>> 286 select SWAP_IO_SPACE
>> 287 select USB_EHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
>> 288 select USB_EHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 289 select USB_OHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
>> 290 select USB_OHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 291 select HARDIRQS_SW_RESEND
>> 292 select HAVE_PCI
>> 293 select PCI_DRIVERS_GENERIC
>> 294 select FW_CFE
>> 295 help
>> 296 Build a generic DT-based kernel image that boots on select
>> 297 BCM33xx cable modem chips, BCM63xx DSL chips, and BCM7xxx set-top
>> 298 box chips. Note that CONFIG_CPU_BIG_ENDIAN/CONFIG_CPU_LITTLE_ENDIAN
>> 299 must be set appropriately for your board.
>> 300
>> 301 config BCM47XX
>> 302 bool "Broadcom BCM47XX based boards"
>> 303 select BOOT_RAW
>> 304 select CEVT_R4K
>> 305 select CSRC_R4K
>> 306 select DMA_NONCOHERENT
>> 307 select HAVE_PCI
>> 308 select IRQ_MIPS_CPU
>> 309 select SYS_HAS_CPU_MIPS32_R1
>> 310 select NO_EXCEPT_FILL
>> 311 select SYS_SUPPORTS_32BIT_KERNEL
>> 312 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 313 select SYS_SUPPORTS_MIPS16
>> 314 select SYS_SUPPORTS_ZBOOT
>> 315 select SYS_HAS_EARLY_PRINTK
>> 316 select USE_GENERIC_EARLY_PRINTK_8250
>> 317 select GPIOLIB
>> 318 select LEDS_GPIO_REGISTER
>> 319 select BCM47XX_NVRAM
>> 320 select BCM47XX_SPROM
>> 321 select BCM47XX_SSB if !BCM47XX_BCMA
>> 322 help
>> 323 Support for BCM47XX based boards
>> 324
>> 325 config BCM63XX
>> 326 bool "Broadcom BCM63XX based boards"
>> 327 select BOOT_RAW
>> 328 select CEVT_R4K
>> 329 select CSRC_R4K
>> 330 select SYNC_R4K
>> 331 select DMA_NONCOHERENT
>> 332 select IRQ_MIPS_CPU
>> 333 select SYS_SUPPORTS_32BIT_KERNEL
>> 334 select SYS_SUPPORTS_BIG_ENDIAN
>> 335 select SYS_HAS_EARLY_PRINTK
>> 336 select SYS_HAS_CPU_BMIPS32_3300
>> 337 select SYS_HAS_CPU_BMIPS4350
>> 338 select SYS_HAS_CPU_BMIPS4380
>> 339 select SWAP_IO_SPACE
>> 340 select GPIOLIB
>> 341 select MIPS_L1_CACHE_SHIFT_4
>> 342 select HAVE_LEGACY_CLK
>> 343 help
>> 344 Support for BCM63XX based boards
>> 345
>> 346 config MIPS_COBALT
>> 347 bool "Cobalt Server"
>> 348 select CEVT_R4K
>> 349 select CSRC_R4K
>> 350 select CEVT_GT641XX
>> 351 select DMA_NONCOHERENT
>> 352 select FORCE_PCI
>> 353 select I8253
>> 354 select I8259
>> 355 select IRQ_MIPS_CPU
>> 356 select IRQ_GT641XX
>> 357 select PCI_GT64XXX_PCI0
>> 358 select SYS_HAS_CPU_NEVADA
>> 359 select SYS_HAS_EARLY_PRINTK
>> 360 select SYS_SUPPORTS_32BIT_KERNEL
>> 361 select SYS_SUPPORTS_64BIT_KERNEL
>> 362 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 363 select USE_GENERIC_EARLY_PRINTK_8250
>> 364
>> 365 config MACH_DECSTATION
>> 366 bool "DECstations"
>> 367 select BOOT_ELF32
>> 368 select CEVT_DS1287
>> 369 select CEVT_R4K if CPU_R4X00
>> 370 select CSRC_IOASIC
>> 371 select CSRC_R4K if CPU_R4X00
>> 372 select CPU_DADDI_WORKAROUNDS if 64BIT
>> 373 select CPU_R4000_WORKAROUNDS if 64BIT
>> 374 select CPU_R4400_WORKAROUNDS if 64BIT
>> 375 select DMA_NONCOHERENT
>> 376 select NO_IOPORT_MAP
>> 377 select IRQ_MIPS_CPU
>> 378 select SYS_HAS_CPU_R3000
>> 379 select SYS_HAS_CPU_R4X00
>> 380 select SYS_SUPPORTS_32BIT_KERNEL
>> 381 select SYS_SUPPORTS_64BIT_KERNEL
>> 382 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 383 select SYS_SUPPORTS_128HZ
>> 384 select SYS_SUPPORTS_256HZ
>> 385 select SYS_SUPPORTS_1024HZ
>> 386 select MIPS_L1_CACHE_SHIFT_4
>> 387 help
>> 388 This enables support for DEC's MIPS based workstations. For details
>> 389 see the Linux/MIPS FAQ on <http://www.linux-mips.org/> and the
>> 390 DECstation porting pages on <http://decstation.unix-ag.org/>.
>> 391
>> 392 If you have one of the following DECstation Models you definitely
>> 393 want to choose R4xx0 for the CPU Type:
>> 394
>> 395 DECstation 5000/50
>> 396 DECstation 5000/150
>> 397 DECstation 5000/260
>> 398 DECsystem 5900/260
>> 399
>> 400 otherwise choose R3000.
>> 401
>> 402 config MACH_JAZZ
>> 403 bool "Jazz family of machines"
>> 404 select ARC_MEMORY
>> 405 select ARC_PROMLIB
>> 406 select ARCH_MIGHT_HAVE_PC_PARPORT
>> 407 select ARCH_MIGHT_HAVE_PC_SERIO
>> 408 select DMA_OPS
>> 409 select FW_ARC
>> 410 select FW_ARC32
>> 411 select ARCH_MAY_HAVE_PC_FDC
>> 412 select CEVT_R4K
>> 413 select CSRC_R4K
>> 414 select DEFAULT_SGI_PARTITION if CPU_BIG_ENDIAN
>> 415 select GENERIC_ISA_DMA
>> 416 select HAVE_PCSPKR_PLATFORM
>> 417 select IRQ_MIPS_CPU
>> 418 select I8253
>> 419 select I8259
>> 420 select ISA
>> 421 select SYS_HAS_CPU_R4X00
>> 422 select SYS_SUPPORTS_32BIT_KERNEL
>> 423 select SYS_SUPPORTS_64BIT_KERNEL
>> 424 select SYS_SUPPORTS_100HZ
>> 425 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 426 help
>> 427 This a family of machines based on the MIPS R4030 chipset which was
>> 428 used by several vendors to build RISC/os and Windows NT workstations.
>> 429 Members include the Acer PICA, MIPS Magnum 4000, MIPS Millennium and
>> 430 Olivetti M700-10 workstations.
>> 431
>> 432 config MACH_INGENIC_SOC
>> 433 bool "Ingenic SoC based machines"
>> 434 select MIPS_GENERIC
>> 435 select MACH_INGENIC
>> 436 select SYS_SUPPORTS_ZBOOT_UART16550
>> 437 select CPU_SUPPORTS_CPUFREQ
>> 438 select MIPS_EXTERNAL_TIMER
>> 439
>> 440 config LANTIQ
>> 441 bool "Lantiq based platforms"
>> 442 select DMA_NONCOHERENT
>> 443 select IRQ_MIPS_CPU
>> 444 select CEVT_R4K
>> 445 select CSRC_R4K
>> 446 select NO_EXCEPT_FILL
>> 447 select SYS_HAS_CPU_MIPS32_R1
>> 448 select SYS_HAS_CPU_MIPS32_R2
>> 449 select SYS_SUPPORTS_BIG_ENDIAN
>> 450 select SYS_SUPPORTS_32BIT_KERNEL
>> 451 select SYS_SUPPORTS_MIPS16
>> 452 select SYS_SUPPORTS_MULTITHREADING
>> 453 select SYS_SUPPORTS_VPE_LOADER
>> 454 select SYS_HAS_EARLY_PRINTK
>> 455 select GPIOLIB
>> 456 select SWAP_IO_SPACE
>> 457 select BOOT_RAW
>> 458 select HAVE_LEGACY_CLK
>> 459 select USE_OF
>> 460 select PINCTRL
>> 461 select PINCTRL_LANTIQ
>> 462 select ARCH_HAS_RESET_CONTROLLER
>> 463 select RESET_CONTROLLER
>> 464
>> 465 config MACH_LOONGSON32
>> 466 bool "Loongson 32-bit family of machines"
>> 467 select SYS_SUPPORTS_ZBOOT
>> 468 help
>> 469 This enables support for the Loongson-1 family of machines.
>> 470
>> 471 Loongson-1 is a family of 32-bit MIPS-compatible SoCs developed by
>> 472 the Institute of Computing Technology (ICT), Chinese Academy of
>> 473 Sciences (CAS).
>> 474
>> 475 config MACH_LOONGSON2EF
>> 476 bool "Loongson-2E/F family of machines"
>> 477 select SYS_SUPPORTS_ZBOOT
>> 478 help
>> 479 This enables the support of early Loongson-2E/F family of machines.
>> 480
>> 481 config MACH_LOONGSON64
>> 482 bool "Loongson 64-bit family of machines"
>> 483 select ARCH_SPARSEMEM_ENABLE
>> 484 select ARCH_MIGHT_HAVE_PC_PARPORT
>> 485 select ARCH_MIGHT_HAVE_PC_SERIO
>> 486 select GENERIC_ISA_DMA_SUPPORT_BROKEN
>> 487 select BOOT_ELF32
>> 488 select BOARD_SCACHE
>> 489 select CSRC_R4K
>> 490 select CEVT_R4K
>> 491 select FORCE_PCI
>> 492 select ISA
>> 493 select I8259
>> 494 select IRQ_MIPS_CPU
>> 495 select NO_EXCEPT_FILL
>> 496 select NR_CPUS_DEFAULT_64
>> 497 select USE_GENERIC_EARLY_PRINTK_8250
>> 498 select PCI_DRIVERS_GENERIC
>> 499 select SYS_HAS_CPU_LOONGSON64
>> 500 select SYS_HAS_EARLY_PRINTK
>> 501 select SYS_SUPPORTS_SMP
>> 502 select SYS_SUPPORTS_HOTPLUG_CPU
>> 503 select SYS_SUPPORTS_NUMA
>> 504 select SYS_SUPPORTS_64BIT_KERNEL
>> 505 select SYS_SUPPORTS_HIGHMEM
>> 506 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 507 select SYS_SUPPORTS_ZBOOT
>> 508 select SYS_SUPPORTS_RELOCATABLE
>> 509 select ZONE_DMA32
>> 510 select COMMON_CLK
>> 511 select USE_OF
>> 512 select BUILTIN_DTB
>> 513 select PCI_HOST_GENERIC
>> 514 select HAVE_ARCH_NODEDATA_EXTENSION if NUMA
>> 515 help
>> 516 This enables the support of Loongson-2/3 family of machines.
>> 517
>> 518 Loongson-2 and Loongson-3 are 64-bit general-purpose processors with
>> 519 GS264/GS464/GS464E/GS464V microarchitecture (except old Loongson-2E
>> 520 and Loongson-2F which will be removed), developed by the Institute
>> 521 of Computing Technology (ICT), Chinese Academy of Sciences (CAS).
>> 522
>> 523 config MIPS_MALTA
>> 524 bool "MIPS Malta board"
>> 525 select ARCH_MAY_HAVE_PC_FDC
>> 526 select ARCH_MIGHT_HAVE_PC_PARPORT
>> 527 select ARCH_MIGHT_HAVE_PC_SERIO
>> 528 select BOOT_ELF32
>> 529 select BOOT_RAW
>> 530 select BUILTIN_DTB
>> 531 select CEVT_R4K
>> 532 select CLKSRC_MIPS_GIC
>> 533 select COMMON_CLK
>> 534 select CSRC_R4K
>> 535 select DMA_NONCOHERENT
>> 536 select GENERIC_ISA_DMA
>> 537 select HAVE_PCSPKR_PLATFORM
>> 538 select HAVE_PCI
>> 539 select I8253
>> 540 select I8259
>> 541 select IRQ_MIPS_CPU
>> 542 select MIPS_BONITO64
>> 543 select MIPS_CPU_SCACHE
>> 544 select MIPS_GIC
>> 545 select MIPS_L1_CACHE_SHIFT_6
>> 546 select MIPS_MSC
>> 547 select PCI_GT64XXX_PCI0
>> 548 select SMP_UP if SMP
>> 549 select SWAP_IO_SPACE
>> 550 select SYS_HAS_CPU_MIPS32_R1
>> 551 select SYS_HAS_CPU_MIPS32_R2
>> 552 select SYS_HAS_CPU_MIPS32_R3_5
>> 553 select SYS_HAS_CPU_MIPS32_R5
>> 554 select SYS_HAS_CPU_MIPS32_R6
>> 555 select SYS_HAS_CPU_MIPS64_R1
>> 556 select SYS_HAS_CPU_MIPS64_R2
>> 557 select SYS_HAS_CPU_MIPS64_R6
>> 558 select SYS_HAS_CPU_NEVADA
>> 559 select SYS_HAS_CPU_RM7000
>> 560 select SYS_SUPPORTS_32BIT_KERNEL
>> 561 select SYS_SUPPORTS_64BIT_KERNEL
>> 562 select SYS_SUPPORTS_BIG_ENDIAN
>> 563 select SYS_SUPPORTS_HIGHMEM
>> 564 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 565 select SYS_SUPPORTS_MICROMIPS
>> 566 select SYS_SUPPORTS_MIPS16
>> 567 select SYS_SUPPORTS_MIPS_CPS
>> 568 select SYS_SUPPORTS_MULTITHREADING
>> 569 select SYS_SUPPORTS_RELOCATABLE
>> 570 select SYS_SUPPORTS_SMARTMIPS
>> 571 select SYS_SUPPORTS_VPE_LOADER
>> 572 select SYS_SUPPORTS_ZBOOT
>> 573 select USE_OF
>> 574 select WAR_ICACHE_REFILLS
>> 575 select ZONE_DMA32 if 64BIT
>> 576 help
>> 577 This enables support for the MIPS Technologies Malta evaluation
>> 578 board.
>> 579
>> 580 config MACH_PIC32
>> 581 bool "Microchip PIC32 Family"
>> 582 help
>> 583 This enables support for the Microchip PIC32 family of platforms.
>> 584
>> 585 Microchip PIC32 is a family of general-purpose 32 bit MIPS core
>> 586 microcontrollers.
>> 587
>> 588 config MACH_NINTENDO64
>> 589 bool "Nintendo 64 console"
>> 590 select CEVT_R4K
>> 591 select CSRC_R4K
>> 592 select SYS_HAS_CPU_R4300
>> 593 select SYS_SUPPORTS_BIG_ENDIAN
>> 594 select SYS_SUPPORTS_ZBOOT
>> 595 select SYS_SUPPORTS_32BIT_KERNEL
>> 596 select SYS_SUPPORTS_64BIT_KERNEL
>> 597 select DMA_NONCOHERENT
>> 598 select IRQ_MIPS_CPU
>> 599
>> 600 config RALINK
>> 601 bool "Ralink based machines"
>> 602 select CEVT_R4K
>> 603 select COMMON_CLK
>> 604 select CSRC_R4K
>> 605 select BOOT_RAW
>> 606 select DMA_NONCOHERENT
>> 607 select IRQ_MIPS_CPU
>> 608 select USE_OF
>> 609 select SYS_HAS_CPU_MIPS32_R2
>> 610 select SYS_SUPPORTS_32BIT_KERNEL
>> 611 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 612 select SYS_SUPPORTS_MIPS16
>> 613 select SYS_SUPPORTS_ZBOOT
>> 614 select SYS_HAS_EARLY_PRINTK
>> 615 select ARCH_HAS_RESET_CONTROLLER
>> 616 select RESET_CONTROLLER
>> 617
>> 618 config MACH_REALTEK_RTL
>> 619 bool "Realtek RTL838x/RTL839x based machines"
>> 620 select MIPS_GENERIC
>> 621 select DMA_NONCOHERENT
>> 622 select IRQ_MIPS_CPU
>> 623 select CSRC_R4K
>> 624 select CEVT_R4K
>> 625 select SYS_HAS_CPU_MIPS32_R1
>> 626 select SYS_HAS_CPU_MIPS32_R2
>> 627 select SYS_SUPPORTS_BIG_ENDIAN
>> 628 select SYS_SUPPORTS_32BIT_KERNEL
>> 629 select SYS_SUPPORTS_MIPS16
>> 630 select SYS_SUPPORTS_MULTITHREADING
>> 631 select SYS_SUPPORTS_VPE_LOADER
>> 632 select BOOT_RAW
>> 633 select PINCTRL
>> 634 select USE_OF
>> 635
>> 636 config SGI_IP22
>> 637 bool "SGI IP22 (Indy/Indigo2)"
>> 638 select ARC_MEMORY
>> 639 select ARC_PROMLIB
>> 640 select FW_ARC
>> 641 select FW_ARC32
>> 642 select ARCH_MIGHT_HAVE_PC_SERIO
>> 643 select BOOT_ELF32
>> 644 select CEVT_R4K
>> 645 select CSRC_R4K
>> 646 select DEFAULT_SGI_PARTITION
>> 647 select DMA_NONCOHERENT
>> 648 select HAVE_EISA
>> 649 select I8253
>> 650 select I8259
>> 651 select IP22_CPU_SCACHE
>> 652 select IRQ_MIPS_CPU
>> 653 select GENERIC_ISA_DMA_SUPPORT_BROKEN
>> 654 select SGI_HAS_I8042
>> 655 select SGI_HAS_INDYDOG
>> 656 select SGI_HAS_HAL2
>> 657 select SGI_HAS_SEEQ
>> 658 select SGI_HAS_WD93
>> 659 select SGI_HAS_ZILOG
>> 660 select SWAP_IO_SPACE
>> 661 select SYS_HAS_CPU_R4X00
>> 662 select SYS_HAS_CPU_R5000
>> 663 select SYS_HAS_EARLY_PRINTK
>> 664 select SYS_SUPPORTS_32BIT_KERNEL
>> 665 select SYS_SUPPORTS_64BIT_KERNEL
>> 666 select SYS_SUPPORTS_BIG_ENDIAN
>> 667 select WAR_R4600_V1_INDEX_ICACHEOP
>> 668 select WAR_R4600_V1_HIT_CACHEOP
>> 669 select WAR_R4600_V2_HIT_CACHEOP
>> 670 select MIPS_L1_CACHE_SHIFT_7
>> 671 help
>> 672 This are the SGI Indy, Challenge S and Indigo2, as well as certain
>> 673 OEM variants like the Tandem CMN B006S. To compile a Linux kernel
>> 674 that runs on these, say Y here.
>> 675
>> 676 config SGI_IP27
>> 677 bool "SGI IP27 (Origin200/2000)"
>> 678 select ARCH_HAS_PHYS_TO_DMA
>> 679 select ARCH_SPARSEMEM_ENABLE
>> 680 select FW_ARC
>> 681 select FW_ARC64
>> 682 select ARC_CMDLINE_ONLY
>> 683 select BOOT_ELF64
>> 684 select DEFAULT_SGI_PARTITION
>> 685 select FORCE_PCI
>> 686 select SYS_HAS_EARLY_PRINTK
>> 687 select HAVE_PCI
>> 688 select IRQ_MIPS_CPU
>> 689 select IRQ_DOMAIN_HIERARCHY
>> 690 select NR_CPUS_DEFAULT_64
>> 691 select PCI_DRIVERS_GENERIC
>> 692 select PCI_XTALK_BRIDGE
>> 693 select SYS_HAS_CPU_R10000
>> 694 select SYS_SUPPORTS_64BIT_KERNEL
>> 695 select SYS_SUPPORTS_BIG_ENDIAN
>> 696 select SYS_SUPPORTS_NUMA
>> 697 select SYS_SUPPORTS_SMP
>> 698 select WAR_R10000_LLSC
>> 699 select MIPS_L1_CACHE_SHIFT_7
>> 700 select NUMA
>> 701 select HAVE_ARCH_NODEDATA_EXTENSION
>> 702 help
>> 703 This are the SGI Origin 200, Origin 2000 and Onyx 2 Graphics
>> 704 workstations. To compile a Linux kernel that runs on these, say Y
>> 705 here.
>> 706
>> 707 config SGI_IP28
>> 708 bool "SGI IP28 (Indigo2 R10k)"
>> 709 select ARC_MEMORY
>> 710 select ARC_PROMLIB
>> 711 select FW_ARC
>> 712 select FW_ARC64
>> 713 select ARCH_MIGHT_HAVE_PC_SERIO
>> 714 select BOOT_ELF64
>> 715 select CEVT_R4K
>> 716 select CSRC_R4K
>> 717 select DEFAULT_SGI_PARTITION
>> 718 select DMA_NONCOHERENT
>> 719 select GENERIC_ISA_DMA_SUPPORT_BROKEN
>> 720 select IRQ_MIPS_CPU
>> 721 select HAVE_EISA
>> 722 select I8253
>> 723 select I8259
>> 724 select SGI_HAS_I8042
>> 725 select SGI_HAS_INDYDOG
>> 726 select SGI_HAS_HAL2
>> 727 select SGI_HAS_SEEQ
>> 728 select SGI_HAS_WD93
>> 729 select SGI_HAS_ZILOG
>> 730 select SWAP_IO_SPACE
>> 731 select SYS_HAS_CPU_R10000
>> 732 select SYS_HAS_EARLY_PRINTK
>> 733 select SYS_SUPPORTS_64BIT_KERNEL
>> 734 select SYS_SUPPORTS_BIG_ENDIAN
>> 735 select WAR_R10000_LLSC
>> 736 select MIPS_L1_CACHE_SHIFT_7
>> 737 help
>> 738 This is the SGI Indigo2 with R10000 processor. To compile a Linux
>> 739 kernel that runs on these, say Y here.
>> 740
>> 741 config SGI_IP30
>> 742 bool "SGI IP30 (Octane/Octane2)"
>> 743 select ARCH_HAS_PHYS_TO_DMA
>> 744 select FW_ARC
>> 745 select FW_ARC64
>> 746 select BOOT_ELF64
>> 747 select CEVT_R4K
>> 748 select CSRC_R4K
>> 749 select FORCE_PCI
>> 750 select SYNC_R4K if SMP
>> 751 select ZONE_DMA32
>> 752 select HAVE_PCI
>> 753 select IRQ_MIPS_CPU
>> 754 select IRQ_DOMAIN_HIERARCHY
>> 755 select PCI_DRIVERS_GENERIC
>> 756 select PCI_XTALK_BRIDGE
>> 757 select SYS_HAS_EARLY_PRINTK
>> 758 select SYS_HAS_CPU_R10000
>> 759 select SYS_SUPPORTS_64BIT_KERNEL
>> 760 select SYS_SUPPORTS_BIG_ENDIAN
>> 761 select SYS_SUPPORTS_SMP
>> 762 select WAR_R10000_LLSC
>> 763 select MIPS_L1_CACHE_SHIFT_7
>> 764 select ARC_MEMORY
>> 765 help
>> 766 These are the SGI Octane and Octane2 graphics workstations. To
>> 767 compile a Linux kernel that runs on these, say Y here.
>> 768
>> 769 config SGI_IP32
>> 770 bool "SGI IP32 (O2)"
>> 771 select ARC_MEMORY
>> 772 select ARC_PROMLIB
>> 773 select ARCH_HAS_PHYS_TO_DMA
>> 774 select FW_ARC
>> 775 select FW_ARC32
>> 776 select BOOT_ELF32
>> 777 select CEVT_R4K
>> 778 select CSRC_R4K
>> 779 select DMA_NONCOHERENT
>> 780 select HAVE_PCI
>> 781 select IRQ_MIPS_CPU
>> 782 select R5000_CPU_SCACHE
>> 783 select RM7000_CPU_SCACHE
>> 784 select SYS_HAS_CPU_R5000
>> 785 select SYS_HAS_CPU_R10000 if BROKEN
>> 786 select SYS_HAS_CPU_RM7000
>> 787 select SYS_HAS_CPU_NEVADA
>> 788 select SYS_SUPPORTS_64BIT_KERNEL
>> 789 select SYS_SUPPORTS_BIG_ENDIAN
>> 790 select WAR_ICACHE_REFILLS
>> 791 help
>> 792 If you want this kernel to run on SGI O2 workstation, say Y here.
>> 793
>> 794 config SIBYTE_CRHONE
>> 795 bool "Sibyte BCM91125C-CRhone"
>> 796 select BOOT_ELF32
>> 797 select SIBYTE_BCM1125
>> 798 select SWAP_IO_SPACE
>> 799 select SYS_HAS_CPU_SB1
>> 800 select SYS_SUPPORTS_BIG_ENDIAN
>> 801 select SYS_SUPPORTS_HIGHMEM
>> 802 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 803
>> 804 config SIBYTE_RHONE
>> 805 bool "Sibyte BCM91125E-Rhone"
>> 806 select BOOT_ELF32
>> 807 select SIBYTE_SB1250
>> 808 select SWAP_IO_SPACE
>> 809 select SYS_HAS_CPU_SB1
>> 810 select SYS_SUPPORTS_BIG_ENDIAN
>> 811 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 812
>> 813 config SIBYTE_SWARM
>> 814 bool "Sibyte BCM91250A-SWARM"
>> 815 select BOOT_ELF32
>> 816 select HAVE_PATA_PLATFORM
>> 817 select SIBYTE_SB1250
>> 818 select SWAP_IO_SPACE
>> 819 select SYS_HAS_CPU_SB1
>> 820 select SYS_SUPPORTS_BIG_ENDIAN
>> 821 select SYS_SUPPORTS_HIGHMEM
>> 822 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 823 select ZONE_DMA32 if 64BIT
>> 824 select SWIOTLB if ARCH_DMA_ADDR_T_64BIT && PCI
>> 825
>> 826 config SIBYTE_LITTLESUR
>> 827 bool "Sibyte BCM91250C2-LittleSur"
>> 828 select BOOT_ELF32
>> 829 select HAVE_PATA_PLATFORM
>> 830 select SIBYTE_SB1250
>> 831 select SWAP_IO_SPACE
>> 832 select SYS_HAS_CPU_SB1
>> 833 select SYS_SUPPORTS_BIG_ENDIAN
>> 834 select SYS_SUPPORTS_HIGHMEM
>> 835 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 836 select ZONE_DMA32 if 64BIT
>> 837
>> 838 config SIBYTE_SENTOSA
>> 839 bool "Sibyte BCM91250E-Sentosa"
>> 840 select BOOT_ELF32
>> 841 select SIBYTE_SB1250
>> 842 select SWAP_IO_SPACE
>> 843 select SYS_HAS_CPU_SB1
>> 844 select SYS_SUPPORTS_BIG_ENDIAN
>> 845 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 846 select SWIOTLB if ARCH_DMA_ADDR_T_64BIT && PCI
>> 847
>> 848 config SIBYTE_BIGSUR
>> 849 bool "Sibyte BCM91480B-BigSur"
>> 850 select BOOT_ELF32
>> 851 select NR_CPUS_DEFAULT_4
>> 852 select SIBYTE_BCM1x80
>> 853 select SWAP_IO_SPACE
>> 854 select SYS_HAS_CPU_SB1
>> 855 select SYS_SUPPORTS_BIG_ENDIAN
>> 856 select SYS_SUPPORTS_HIGHMEM
>> 857 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 858 select ZONE_DMA32 if 64BIT
>> 859 select SWIOTLB if ARCH_DMA_ADDR_T_64BIT && PCI
>> 860
>> 861 config SNI_RM
>> 862 bool "SNI RM200/300/400"
>> 863 select ARC_MEMORY
>> 864 select ARC_PROMLIB
>> 865 select FW_ARC if CPU_LITTLE_ENDIAN
>> 866 select FW_ARC32 if CPU_LITTLE_ENDIAN
>> 867 select FW_SNIPROM if CPU_BIG_ENDIAN
>> 868 select ARCH_MAY_HAVE_PC_FDC
>> 869 select ARCH_MIGHT_HAVE_PC_PARPORT
>> 870 select ARCH_MIGHT_HAVE_PC_SERIO
>> 871 select BOOT_ELF32
>> 872 select CEVT_R4K
>> 873 select CSRC_R4K
>> 874 select DEFAULT_SGI_PARTITION if CPU_BIG_ENDIAN
>> 875 select DMA_NONCOHERENT
>> 876 select GENERIC_ISA_DMA
>> 877 select HAVE_EISA
>> 878 select HAVE_PCSPKR_PLATFORM
>> 879 select HAVE_PCI
>> 880 select IRQ_MIPS_CPU
>> 881 select I8253
>> 882 select I8259
>> 883 select ISA
>> 884 select MIPS_L1_CACHE_SHIFT_6
>> 885 select SWAP_IO_SPACE if CPU_BIG_ENDIAN
>> 886 select SYS_HAS_CPU_R4X00
>> 887 select SYS_HAS_CPU_R5000
>> 888 select SYS_HAS_CPU_R10000
>> 889 select R5000_CPU_SCACHE
>> 890 select SYS_HAS_EARLY_PRINTK
>> 891 select SYS_SUPPORTS_32BIT_KERNEL
>> 892 select SYS_SUPPORTS_64BIT_KERNEL
>> 893 select SYS_SUPPORTS_BIG_ENDIAN
>> 894 select SYS_SUPPORTS_HIGHMEM
>> 895 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 896 select WAR_R4600_V2_HIT_CACHEOP
>> 897 help
>> 898 The SNI RM200/300/400 are MIPS-based machines manufactured by
>> 899 Siemens Nixdorf Informationssysteme (SNI), parent company of Pyramid
>> 900 Technology and now in turn merged with Fujitsu. Say Y here to
>> 901 support this machine type.
>> 902
>> 903 config MACH_TX49XX
>> 904 bool "Toshiba TX49 series based machines"
>> 905 select WAR_TX49XX_ICACHE_INDEX_INV
>> 906
>> 907 config MIKROTIK_RB532
>> 908 bool "Mikrotik RB532 boards"
>> 909 select CEVT_R4K
>> 910 select CSRC_R4K
>> 911 select DMA_NONCOHERENT
>> 912 select HAVE_PCI
>> 913 select IRQ_MIPS_CPU
>> 914 select SYS_HAS_CPU_MIPS32_R1
>> 915 select SYS_SUPPORTS_32BIT_KERNEL
>> 916 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 917 select SWAP_IO_SPACE
>> 918 select BOOT_RAW
>> 919 select GPIOLIB
>> 920 select MIPS_L1_CACHE_SHIFT_4
>> 921 help
>> 922 Support the Mikrotik(tm) RouterBoard 532 series,
>> 923 based on the IDT RC32434 SoC.
>> 924
>> 925 config CAVIUM_OCTEON_SOC
>> 926 bool "Cavium Networks Octeon SoC based boards"
>> 927 select CEVT_R4K
>> 928 select ARCH_HAS_PHYS_TO_DMA
>> 929 select HAVE_RAPIDIO
>> 930 select PHYS_ADDR_T_64BIT
>> 931 select SYS_SUPPORTS_64BIT_KERNEL
>> 932 select SYS_SUPPORTS_BIG_ENDIAN
>> 933 select EDAC_SUPPORT
>> 934 select EDAC_ATOMIC_SCRUB
>> 935 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 936 select SYS_SUPPORTS_HOTPLUG_CPU if CPU_BIG_ENDIAN
>> 937 select SYS_HAS_EARLY_PRINTK
>> 938 select SYS_HAS_CPU_CAVIUM_OCTEON
>> 939 select HAVE_PCI
>> 940 select HAVE_PLAT_DELAY
>> 941 select HAVE_PLAT_FW_INIT_CMDLINE
>> 942 select HAVE_PLAT_MEMCPY
>> 943 select ZONE_DMA32
>> 944 select GPIOLIB
>> 945 select USE_OF
>> 946 select ARCH_SPARSEMEM_ENABLE
>> 947 select SYS_SUPPORTS_SMP
>> 948 select NR_CPUS_DEFAULT_64
>> 949 select MIPS_NR_CPU_NR_MAP_1024
>> 950 select BUILTIN_DTB
>> 951 select MTD
>> 952 select MTD_COMPLEX_MAPPINGS
>> 953 select SWIOTLB
>> 954 select SYS_SUPPORTS_RELOCATABLE
>> 955 help
>> 956 This option supports all of the Octeon reference boards from Cavium
>> 957 Networks. It builds a kernel that dynamically determines the Octeon
>> 958 CPU type and supports all known board reference implementations.
>> 959 Some of the supported boards are:
>> 960 EBT3000
>> 961 EBH3000
>> 962 EBH3100
>> 963 Thunder
>> 964 Kodama
>> 965 Hikari
>> 966 Say Y here for most Octeon reference boards.
349 967
350 config LOCKDEP_SUPPORT !! 968 endchoice
351 def_bool y <<
352 969
353 config GENERIC_BUG !! 970 source "arch/mips/alchemy/Kconfig"
354 def_bool y !! 971 source "arch/mips/ath25/Kconfig"
355 depends on BUG !! 972 source "arch/mips/ath79/Kconfig"
>> 973 source "arch/mips/bcm47xx/Kconfig"
>> 974 source "arch/mips/bcm63xx/Kconfig"
>> 975 source "arch/mips/bmips/Kconfig"
>> 976 source "arch/mips/generic/Kconfig"
>> 977 source "arch/mips/ingenic/Kconfig"
>> 978 source "arch/mips/jazz/Kconfig"
>> 979 source "arch/mips/lantiq/Kconfig"
>> 980 source "arch/mips/pic32/Kconfig"
>> 981 source "arch/mips/ralink/Kconfig"
>> 982 source "arch/mips/sgi-ip27/Kconfig"
>> 983 source "arch/mips/sibyte/Kconfig"
>> 984 source "arch/mips/txx9/Kconfig"
>> 985 source "arch/mips/cavium-octeon/Kconfig"
>> 986 source "arch/mips/loongson2ef/Kconfig"
>> 987 source "arch/mips/loongson32/Kconfig"
>> 988 source "arch/mips/loongson64/Kconfig"
356 989
357 config GENERIC_BUG_RELATIVE_POINTERS !! 990 endmenu
358 def_bool y <<
359 depends on GENERIC_BUG <<
360 991
361 config GENERIC_HWEIGHT 992 config GENERIC_HWEIGHT
362 def_bool y !! 993 bool
363 !! 994 default y
364 config GENERIC_CSUM <<
365 def_bool y <<
366 995
367 config GENERIC_CALIBRATE_DELAY 996 config GENERIC_CALIBRATE_DELAY
368 def_bool y !! 997 bool
>> 998 default y
369 999
370 config SMP !! 1000 config SCHED_OMIT_FRAME_POINTER
371 def_bool y !! 1001 bool
>> 1002 default y
372 1003
373 config KERNEL_MODE_NEON !! 1004 #
374 def_bool y !! 1005 # Select some configuration options automatically based on user selections.
>> 1006 #
>> 1007 config FW_ARC
>> 1008 bool
375 1009
376 config FIX_EARLYCON_MEM !! 1010 config ARCH_MAY_HAVE_PC_FDC
377 def_bool y !! 1011 bool
378 1012
379 config PGTABLE_LEVELS !! 1013 config BOOT_RAW
380 int !! 1014 bool
381 default 2 if ARM64_16K_PAGES && ARM64_ <<
382 default 2 if ARM64_64K_PAGES && ARM64_ <<
383 default 3 if ARM64_64K_PAGES && (ARM64 <<
384 default 3 if ARM64_4K_PAGES && ARM64_V <<
385 default 3 if ARM64_16K_PAGES && ARM64_ <<
386 default 4 if ARM64_16K_PAGES && (ARM64 <<
387 default 4 if !ARM64_64K_PAGES && ARM64 <<
388 default 5 if ARM64_4K_PAGES && ARM64_V <<
389 1015
390 config ARCH_SUPPORTS_UPROBES !! 1016 config CEVT_BCM1480
391 def_bool y !! 1017 bool
392 1018
393 config ARCH_PROC_KCORE_TEXT !! 1019 config CEVT_DS1287
394 def_bool y !! 1020 bool
395 1021
396 config BROKEN_GAS_INST !! 1022 config CEVT_GT641XX
397 def_bool !$(as-instr,1:\n.inst 0\n.rep !! 1023 bool
398 1024
399 config BUILTIN_RETURN_ADDRESS_STRIPS_PAC !! 1025 config CEVT_R4K
400 bool 1026 bool
401 # Clang's __builtin_return_address() s <<
402 # https://github.com/llvm/llvm-project <<
403 default y if CC_IS_CLANG <<
404 # GCC's __builtin_return_address() str <<
405 # and this was backported to 10.2.0, 9 <<
406 # https://gcc.gnu.org/bugzilla/show_bu <<
407 default y if CC_IS_GCC && (GCC_VERSION <<
408 default y if CC_IS_GCC && (GCC_VERSION <<
409 default y if CC_IS_GCC && (GCC_VERSION <<
410 default y if CC_IS_GCC && (GCC_VERSION <<
411 default n <<
412 1027
413 config KASAN_SHADOW_OFFSET !! 1028 config CEVT_SB1250
414 hex <<
415 depends on KASAN_GENERIC || KASAN_SW_T <<
416 default 0xdfff800000000000 if (ARM64_V <<
417 default 0xdfffc00000000000 if (ARM64_V <<
418 default 0xdffffe0000000000 if ARM64_VA <<
419 default 0xdfffffc000000000 if ARM64_VA <<
420 default 0xdffffff800000000 if ARM64_VA <<
421 default 0xefff800000000000 if (ARM64_V <<
422 default 0xefffc00000000000 if (ARM64_V <<
423 default 0xeffffe0000000000 if ARM64_VA <<
424 default 0xefffffc000000000 if ARM64_VA <<
425 default 0xeffffff800000000 if ARM64_VA <<
426 default 0xffffffffffffffff <<
427 <<
428 config UNWIND_TABLES <<
429 bool 1029 bool
430 1030
431 source "arch/arm64/Kconfig.platforms" !! 1031 config CEVT_TXX9
>> 1032 bool
432 1033
433 menu "Kernel Features" !! 1034 config CSRC_BCM1480
>> 1035 bool
434 1036
435 menu "ARM errata workarounds via the alternati !! 1037 config CSRC_IOASIC
>> 1038 bool
436 1039
437 config AMPERE_ERRATUM_AC03_CPU_38 !! 1040 config CSRC_R4K
438 bool "AmpereOne: AC03_CPU_38: Certain !! 1041 select CLOCKSOURCE_WATCHDOG if CPU_FREQ
439 default y !! 1042 bool
440 help <<
441 This option adds an alternative code <<
442 errata AC03_CPU_38 and AC04_CPU_10 o <<
443 1043
444 The affected design reports FEAT_HAF !! 1044 config CSRC_SB1250
445 ID_AA64MMFR1_EL1.HAFDBS, but (V)TCR_ !! 1045 bool
446 as required by the architecture. The <<
447 implementation suffers from an addit <<
448 A/D updates can occur after a PTE ha <<
449 <<
450 The workaround forces KVM to explici <<
451 which avoids enabling unadvertised h <<
452 at stage-2. <<
453 1046
454 If unsure, say Y. !! 1047 config MIPS_CLOCK_VSYSCALL
>> 1048 def_bool CSRC_R4K || CLKSRC_MIPS_GIC
455 1049
456 config ARM64_WORKAROUND_CLEAN_CACHE !! 1050 config GPIO_TXX9
>> 1051 select GPIOLIB
457 bool 1052 bool
458 1053
459 config ARM64_ERRATUM_826319 !! 1054 config FW_CFE
460 bool "Cortex-A53: 826319: System might !! 1055 bool
461 default y <<
462 select ARM64_WORKAROUND_CLEAN_CACHE <<
463 help <<
464 This option adds an alternative code <<
465 erratum 826319 on Cortex-A53 parts u <<
466 AXI master interface and an L2 cache <<
467 <<
468 If a Cortex-A53 uses an AMBA AXI4 AC <<
469 and is unable to accept a certain wr <<
470 not progress on read data presented <<
471 system can deadlock. <<
472 <<
473 The workaround promotes data cache c <<
474 data cache clean-and-invalidate. <<
475 Please note that this does not neces <<
476 as it depends on the alternative fra <<
477 the kernel if an affected CPU is det <<
478 <<
479 If unsure, say Y. <<
480 1056
481 config ARM64_ERRATUM_827319 !! 1057 config ARCH_SUPPORTS_UPROBES
482 bool "Cortex-A53: 827319: Data cache c !! 1058 def_bool y
483 default y <<
484 select ARM64_WORKAROUND_CLEAN_CACHE <<
485 help <<
486 This option adds an alternative code <<
487 erratum 827319 on Cortex-A53 parts u <<
488 master interface and an L2 cache. <<
489 <<
490 Under certain conditions this erratu <<
491 to occur at the same time as another <<
492 on the AMBA 5 CHI interface, which c <<
493 interconnect reorders the two transa <<
494 <<
495 The workaround promotes data cache c <<
496 data cache clean-and-invalidate. <<
497 Please note that this does not neces <<
498 as it depends on the alternative fra <<
499 the kernel if an affected CPU is det <<
500 1059
501 If unsure, say Y. !! 1060 config DMA_NONCOHERENT
>> 1061 bool
>> 1062 #
>> 1063 # MIPS allows mixing "slightly different" Cacheability and Coherency
>> 1064 # Attribute bits. It is believed that the uncached access through
>> 1065 # KSEG1 and the implementation specific "uncached accelerated" used
>> 1066 # by pgprot_writcombine can be mixed, and the latter sometimes provides
>> 1067 # significant advantages.
>> 1068 #
>> 1069 select ARCH_HAS_SETUP_DMA_OPS
>> 1070 select ARCH_HAS_DMA_WRITE_COMBINE
>> 1071 select ARCH_HAS_DMA_PREP_COHERENT
>> 1072 select ARCH_HAS_SYNC_DMA_FOR_CPU
>> 1073 select ARCH_HAS_SYNC_DMA_FOR_DEVICE
>> 1074 select ARCH_HAS_DMA_SET_UNCACHED
>> 1075 select DMA_NONCOHERENT_MMAP
>> 1076 select NEED_DMA_MAP_STATE
502 1077
503 config ARM64_ERRATUM_824069 !! 1078 config SYS_HAS_EARLY_PRINTK
504 bool "Cortex-A53: 824069: Cache line m !! 1079 bool
505 default y <<
506 select ARM64_WORKAROUND_CLEAN_CACHE <<
507 help <<
508 This option adds an alternative code <<
509 erratum 824069 on Cortex-A53 parts u <<
510 to a coherent interconnect. <<
511 <<
512 If a Cortex-A53 processor is executi <<
513 write instruction at the same time a <<
514 cluster is executing a cache mainten <<
515 address, then this erratum might cau <<
516 incorrectly marked as dirty. <<
517 <<
518 The workaround promotes data cache c <<
519 data cache clean-and-invalidate. <<
520 Please note that this option does no <<
521 workaround, as it depends on the alt <<
522 only patch the kernel if an affected <<
523 1080
524 If unsure, say Y. !! 1081 config SYS_SUPPORTS_HOTPLUG_CPU
>> 1082 bool
525 1083
526 config ARM64_ERRATUM_819472 !! 1084 config MIPS_BONITO64
527 bool "Cortex-A53: 819472: Store exclus !! 1085 bool
528 default y <<
529 select ARM64_WORKAROUND_CLEAN_CACHE <<
530 help <<
531 This option adds an alternative code <<
532 erratum 819472 on Cortex-A53 parts u <<
533 present when it is connected to a co <<
534 <<
535 If the processor is executing a load <<
536 the same time as a processor in anot <<
537 maintenance operation to the same ad <<
538 cause data corruption. <<
539 <<
540 The workaround promotes data cache c <<
541 data cache clean-and-invalidate. <<
542 Please note that this does not neces <<
543 as it depends on the alternative fra <<
544 the kernel if an affected CPU is det <<
545 1086
546 If unsure, say Y. !! 1087 config MIPS_MSC
>> 1088 bool
547 1089
548 config ARM64_ERRATUM_832075 !! 1090 config SYNC_R4K
549 bool "Cortex-A57: 832075: possible dea !! 1091 bool
550 default y <<
551 help <<
552 This option adds an alternative code <<
553 erratum 832075 on Cortex-A57 parts u <<
554 1092
555 Affected Cortex-A57 parts might dead !! 1093 config NO_IOPORT_MAP
556 instructions to Write-Back memory ar !! 1094 def_bool n
557 1095
558 The workaround is to promote device !! 1096 config GENERIC_CSUM
559 semantics. !! 1097 def_bool CPU_NO_LOAD_STORE_LR
560 Please note that this does not neces <<
561 as it depends on the alternative fra <<
562 the kernel if an affected CPU is det <<
563 1098
564 If unsure, say Y. !! 1099 config GENERIC_ISA_DMA
>> 1100 bool
>> 1101 select ZONE_DMA if GENERIC_ISA_DMA_SUPPORT_BROKEN=n
>> 1102 select ISA_DMA_API
565 1103
566 config ARM64_ERRATUM_834220 !! 1104 config GENERIC_ISA_DMA_SUPPORT_BROKEN
567 bool "Cortex-A57: 834220: Stage 2 tran !! 1105 bool
568 depends on KVM !! 1106 select GENERIC_ISA_DMA
569 help <<
570 This option adds an alternative code <<
571 erratum 834220 on Cortex-A57 parts u <<
572 <<
573 Affected Cortex-A57 parts might repo <<
574 fault as the result of a Stage 1 fau <<
575 page boundary when there is a permis <<
576 alignment fault at Stage 1 and a tra <<
577 <<
578 The workaround is to verify that the <<
579 doesn't generate a fault before hand <<
580 Please note that this does not neces <<
581 as it depends on the alternative fra <<
582 the kernel if an affected CPU is det <<
583 1107
584 If unsure, say N. !! 1108 config HAVE_PLAT_DELAY
>> 1109 bool
585 1110
586 config ARM64_ERRATUM_1742098 !! 1111 config HAVE_PLAT_FW_INIT_CMDLINE
587 bool "Cortex-A57/A72: 1742098: ELR rec !! 1112 bool
588 depends on COMPAT <<
589 default y <<
590 help <<
591 This option removes the AES hwcap fo <<
592 workaround erratum 1742098 on Cortex <<
593 1113
594 Affected parts may corrupt the AES s !! 1114 config HAVE_PLAT_MEMCPY
595 taken between a pair of AES instruct !! 1115 bool
596 are only present if the cryptography <<
597 All software should have a fallback <<
598 that don't implement the cryptograph <<
599 1116
600 If unsure, say Y. !! 1117 config ISA_DMA_API
>> 1118 bool
601 1119
602 config ARM64_ERRATUM_845719 !! 1120 config SYS_SUPPORTS_RELOCATABLE
603 bool "Cortex-A53: 845719: a load might !! 1121 bool
604 depends on COMPAT <<
605 default y <<
606 help 1122 help
607 This option adds an alternative code !! 1123 Selected if the platform supports relocating the kernel.
608 erratum 845719 on Cortex-A53 parts u !! 1124 The platform must provide plat_get_fdt() if it selects CONFIG_USE_OF
609 !! 1125 to allow access to command line and entropy sources.
610 When running a compat (AArch32) user <<
611 part, a load at EL0 from a virtual a <<
612 bits of the virtual address used by <<
613 might return incorrect data. <<
614 <<
615 The workaround is to write the conte <<
616 return to a 32-bit task. <<
617 Please note that this does not neces <<
618 as it depends on the alternative fra <<
619 the kernel if an affected CPU is det <<
620 <<
621 If unsure, say Y. <<
622 1126
623 config ARM64_ERRATUM_843419 !! 1127 #
624 bool "Cortex-A53: 843419: A load or st !! 1128 # Endianness selection. Sufficiently obscure so many users don't know what to
625 default y !! 1129 # answer,so we try hard to limit the available choices. Also the use of a
>> 1130 # choice statement should be more obvious to the user.
>> 1131 #
>> 1132 choice
>> 1133 prompt "Endianness selection"
626 help 1134 help
627 This option links the kernel with '- !! 1135 Some MIPS machines can be configured for either little or big endian
628 enables PLT support to replace certa !! 1136 byte order. These modes require different kernels and a different
629 cause subsequent memory accesses to !! 1137 Linux distribution. In general there is one preferred byteorder for a
630 Cortex-A53 parts up to r0p4. !! 1138 particular system but some systems are just as commonly used in the
>> 1139 one or the other endianness.
631 1140
632 If unsure, say Y. !! 1141 config CPU_BIG_ENDIAN
>> 1142 bool "Big endian"
>> 1143 depends on SYS_SUPPORTS_BIG_ENDIAN
633 1144
634 config ARM64_LD_HAS_FIX_ERRATUM_843419 !! 1145 config CPU_LITTLE_ENDIAN
635 def_bool $(ld-option,--fix-cortex-a53- !! 1146 bool "Little endian"
>> 1147 depends on SYS_SUPPORTS_LITTLE_ENDIAN
636 1148
637 config ARM64_ERRATUM_1024718 !! 1149 endchoice
638 bool "Cortex-A55: 1024718: Update of D <<
639 default y <<
640 help <<
641 This option adds a workaround for AR <<
642 1150
643 Affected Cortex-A55 cores (all revis !! 1151 config EXPORT_UASM
644 update of the hardware dirty bit whe !! 1152 bool
645 without a break-before-make. The wor <<
646 of hardware DBM locally on the affec <<
647 this erratum will continue to use th <<
648 1153
649 If unsure, say Y. !! 1154 config SYS_SUPPORTS_APM_EMULATION
>> 1155 bool
650 1156
651 config ARM64_ERRATUM_1418040 !! 1157 config SYS_SUPPORTS_BIG_ENDIAN
652 bool "Cortex-A76/Neoverse-N1: MRC read !! 1158 bool
653 default y <<
654 depends on COMPAT <<
655 help <<
656 This option adds a workaround for AR <<
657 errata 1188873 and 1418040. <<
658 1159
659 Affected Cortex-A76/Neoverse-N1 core !! 1160 config SYS_SUPPORTS_LITTLE_ENDIAN
660 cause register corruption when acces !! 1161 bool
661 from AArch32 userspace. <<
662 1162
663 If unsure, say Y. !! 1163 config MIPS_HUGE_TLB_SUPPORT
>> 1164 def_bool HUGETLB_PAGE || TRANSPARENT_HUGEPAGE
664 1165
665 config ARM64_WORKAROUND_SPECULATIVE_AT !! 1166 config IRQ_TXX9
666 bool 1167 bool
667 1168
668 config ARM64_ERRATUM_1165522 !! 1169 config IRQ_GT641XX
669 bool "Cortex-A76: 1165522: Speculative !! 1170 bool
670 default y <<
671 select ARM64_WORKAROUND_SPECULATIVE_AT <<
672 help <<
673 This option adds a workaround for AR <<
674 1171
675 Affected Cortex-A76 cores (r0p0, r1p !! 1172 config PCI_GT64XXX_PCI0
676 corrupted TLBs by speculating an AT !! 1173 bool
677 context switch. <<
678 1174
679 If unsure, say Y. !! 1175 config PCI_XTALK_BRIDGE
>> 1176 bool
680 1177
681 config ARM64_ERRATUM_1319367 !! 1178 config NO_EXCEPT_FILL
682 bool "Cortex-A57/A72: 1319537: Specula !! 1179 bool
683 default y <<
684 select ARM64_WORKAROUND_SPECULATIVE_AT <<
685 help <<
686 This option adds work arounds for AR <<
687 and A72 erratum 1319367 <<
688 1180
689 Cortex-A57 and A72 cores could end-u !! 1181 config MIPS_SPRAM
690 speculating an AT instruction during !! 1182 bool
691 1183
692 If unsure, say Y. !! 1184 config SWAP_IO_SPACE
>> 1185 bool
693 1186
694 config ARM64_ERRATUM_1530923 !! 1187 config SGI_HAS_INDYDOG
695 bool "Cortex-A55: 1530923: Speculative !! 1188 bool
696 default y <<
697 select ARM64_WORKAROUND_SPECULATIVE_AT <<
698 help <<
699 This option adds a workaround for AR <<
700 1189
701 Affected Cortex-A55 cores (r0p0, r0p !! 1190 config SGI_HAS_HAL2
702 corrupted TLBs by speculating an AT !! 1191 bool
703 context switch. <<
704 1192
705 If unsure, say Y. !! 1193 config SGI_HAS_SEEQ
>> 1194 bool
706 1195
707 config ARM64_WORKAROUND_REPEAT_TLBI !! 1196 config SGI_HAS_WD93
708 bool 1197 bool
709 1198
710 config ARM64_ERRATUM_2441007 !! 1199 config SGI_HAS_ZILOG
711 bool "Cortex-A55: Completion of affect !! 1200 bool
712 select ARM64_WORKAROUND_REPEAT_TLBI <<
713 help <<
714 This option adds a workaround for AR <<
715 1201
716 Under very rare circumstances, affec !! 1202 config SGI_HAS_I8042
717 may not handle a race between a brea !! 1203 bool
718 CPU, and another CPU accessing the s <<
719 store to a page that has been unmapp <<
720 1204
721 Work around this by adding the affec !! 1205 config DEFAULT_SGI_PARTITION
722 TLB sequences to be done twice. !! 1206 bool
723 1207
724 If unsure, say N. !! 1208 config FW_ARC32
>> 1209 bool
725 1210
726 config ARM64_ERRATUM_1286807 !! 1211 config FW_SNIPROM
727 bool "Cortex-A76: Modification of the !! 1212 bool
728 select ARM64_WORKAROUND_REPEAT_TLBI <<
729 help <<
730 This option adds a workaround for AR <<
731 <<
732 On the affected Cortex-A76 cores (r0 <<
733 address for a cacheable mapping of a <<
734 accessed by a core while another cor <<
735 address to a new physical page using <<
736 break-before-make sequence, then und <<
737 TLBI+DSB completes before a read usi <<
738 invalidated has been observed by oth <<
739 workaround repeats the TLBI+DSB oper <<
740 1213
741 If unsure, say N. !! 1214 config BOOT_ELF32
>> 1215 bool
742 1216
743 config ARM64_ERRATUM_1463225 !! 1217 config MIPS_L1_CACHE_SHIFT_4
744 bool "Cortex-A76: Software Step might !! 1218 bool
745 default y <<
746 help <<
747 This option adds a workaround for Ar <<
748 1219
749 On the affected Cortex-A76 cores (r0 !! 1220 config MIPS_L1_CACHE_SHIFT_5
750 of a system call instruction (SVC) c !! 1221 bool
751 subsequent interrupts when software <<
752 exception handler of the system call <<
753 is enabled or VHE is in use. <<
754 <<
755 Work around the erratum by triggerin <<
756 when handling a system call from a t <<
757 in a VHE configuration of the kernel <<
758 1222
759 If unsure, say Y. !! 1223 config MIPS_L1_CACHE_SHIFT_6
>> 1224 bool
760 1225
761 config ARM64_ERRATUM_1542419 !! 1226 config MIPS_L1_CACHE_SHIFT_7
762 bool "Neoverse-N1: workaround mis-orde !! 1227 bool
763 help <<
764 This option adds a workaround for AR <<
765 1542419. <<
766 1228
767 Affected Neoverse-N1 cores could exe !! 1229 config MIPS_L1_CACHE_SHIFT
768 modified by another CPU. The workaro !! 1230 int
769 counterpart. !! 1231 default "7" if MIPS_L1_CACHE_SHIFT_7
>> 1232 default "6" if MIPS_L1_CACHE_SHIFT_6
>> 1233 default "5" if MIPS_L1_CACHE_SHIFT_5
>> 1234 default "4" if MIPS_L1_CACHE_SHIFT_4
>> 1235 default "5"
770 1236
771 Workaround the issue by hiding the D !! 1237 config ARC_CMDLINE_ONLY
772 forces user-space to perform cache m !! 1238 bool
773 1239
774 If unsure, say N. !! 1240 config ARC_CONSOLE
>> 1241 bool "ARC console support"
>> 1242 depends on SGI_IP22 || SGI_IP28 || (SNI_RM && CPU_LITTLE_ENDIAN)
775 1243
776 config ARM64_ERRATUM_1508412 !! 1244 config ARC_MEMORY
777 bool "Cortex-A77: 1508412: workaround !! 1245 bool
778 default y <<
779 help <<
780 This option adds a workaround for Ar <<
781 1246
782 Affected Cortex-A77 cores (r0p0, r1p !! 1247 config ARC_PROMLIB
783 of a store-exclusive or read of PAR_ !! 1248 bool
784 non-cacheable memory attributes. The <<
785 counterpart. <<
786 <<
787 KVM guests must also have the workar <<
788 deadlock the system. <<
789 <<
790 Work around the issue by inserting D <<
791 register reads and warning KVM users <<
792 to prevent a speculative PAR_EL1 rea <<
793 1249
794 If unsure, say Y. !! 1250 config FW_ARC64
>> 1251 bool
795 1252
796 config ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MO !! 1253 config BOOT_ELF64
797 bool 1254 bool
798 1255
799 config ARM64_ERRATUM_2051678 !! 1256 menu "CPU selection"
800 bool "Cortex-A510: 2051678: disable Ha <<
801 default y <<
802 help <<
803 This options adds the workaround for <<
804 Affected Cortex-A510 might not respe <<
805 hardware update of the page table's <<
806 is to not enable the feature on affe <<
807 1257
808 If unsure, say Y. !! 1258 choice
>> 1259 prompt "CPU type"
>> 1260 default CPU_R4X00
809 1261
810 config ARM64_ERRATUM_2077057 !! 1262 config CPU_LOONGSON64
811 bool "Cortex-A510: 2077057: workaround !! 1263 bool "Loongson 64-bit CPU"
812 default y !! 1264 depends on SYS_HAS_CPU_LOONGSON64
>> 1265 select ARCH_HAS_PHYS_TO_DMA
>> 1266 select CPU_MIPSR2
>> 1267 select CPU_HAS_PREFETCH
>> 1268 select CPU_SUPPORTS_64BIT_KERNEL
>> 1269 select CPU_SUPPORTS_HIGHMEM
>> 1270 select CPU_SUPPORTS_HUGEPAGES
>> 1271 select CPU_SUPPORTS_MSA
>> 1272 select CPU_DIEI_BROKEN if !LOONGSON3_ENHANCEMENT
>> 1273 select CPU_MIPSR2_IRQ_VI
>> 1274 select WEAK_ORDERING
>> 1275 select WEAK_REORDERING_BEYOND_LLSC
>> 1276 select MIPS_ASID_BITS_VARIABLE
>> 1277 select MIPS_PGD_C0_CONTEXT
>> 1278 select MIPS_L1_CACHE_SHIFT_6
>> 1279 select MIPS_FP_SUPPORT
>> 1280 select GPIOLIB
>> 1281 select SWIOTLB
>> 1282 select HAVE_KVM
813 help 1283 help
814 This option adds the workaround for !! 1284 The Loongson GSx64(GS264/GS464/GS464E/GS464V) series of processor
815 Affected Cortex-A510 may corrupt SPS !! 1285 cores implements the MIPS64R2 instruction set with many extensions,
816 expected, but a Pointer Authenticati !! 1286 including most 64-bit Loongson-2 (2H, 2K) and Loongson-3 (3A1000,
817 erratum causes SPSR_EL1 to be copied !! 1287 3B1000, 3B1500, 3A2000, 3A3000 and 3A4000) processors. However, old
818 EL1 to cause a return to EL2 with a !! 1288 Loongson-2E/2F is not covered here and will be removed in future.
819 <<
820 This can only happen when EL2 is ste <<
821 <<
822 When these conditions occur, the SPS <<
823 previous guest entry, and can be res <<
824 <<
825 If unsure, say Y. <<
826 1289
827 config ARM64_ERRATUM_2658417 !! 1290 config LOONGSON3_ENHANCEMENT
828 bool "Cortex-A510: 2658417: remove BF1 !! 1291 bool "New Loongson-3 CPU Enhancements"
829 default y !! 1292 default n
>> 1293 depends on CPU_LOONGSON64
>> 1294 help
>> 1295 New Loongson-3 cores (since Loongson-3A R2, as opposed to Loongson-3A
>> 1296 R1, Loongson-3B R1 and Loongson-3B R2) has many enhancements, such as
>> 1297 FTLB, L1-VCache, EI/DI/Wait/Prefetch instruction, DSP/DSPr2 ASE, User
>> 1298 Local register, Read-Inhibit/Execute-Inhibit, SFB (Store Fill Buffer),
>> 1299 Fast TLB refill support, etc.
>> 1300
>> 1301 This option enable those enhancements which are not probed at run
>> 1302 time. If you want a generic kernel to run on all Loongson 3 machines,
>> 1303 please say 'N' here. If you want a high-performance kernel to run on
>> 1304 new Loongson-3 machines only, please say 'Y' here.
>> 1305
>> 1306 config CPU_LOONGSON3_WORKAROUNDS
>> 1307 bool "Loongson-3 LLSC Workarounds"
>> 1308 default y if SMP
>> 1309 depends on CPU_LOONGSON64
>> 1310 help
>> 1311 Loongson-3 processors have the llsc issues which require workarounds.
>> 1312 Without workarounds the system may hang unexpectedly.
>> 1313
>> 1314 Say Y, unless you know what you are doing.
>> 1315
>> 1316 config CPU_LOONGSON3_CPUCFG_EMULATION
>> 1317 bool "Emulate the CPUCFG instruction on older Loongson cores"
>> 1318 default y
>> 1319 depends on CPU_LOONGSON64
>> 1320 help
>> 1321 Loongson-3A R4 and newer have the CPUCFG instruction available for
>> 1322 userland to query CPU capabilities, much like CPUID on x86. This
>> 1323 option provides emulation of the instruction on older Loongson
>> 1324 cores, back to Loongson-3A1000.
>> 1325
>> 1326 If unsure, please say Y.
>> 1327
>> 1328 config CPU_LOONGSON2E
>> 1329 bool "Loongson 2E"
>> 1330 depends on SYS_HAS_CPU_LOONGSON2E
>> 1331 select CPU_LOONGSON2EF
>> 1332 help
>> 1333 The Loongson 2E processor implements the MIPS III instruction set
>> 1334 with many extensions.
>> 1335
>> 1336 It has an internal FPGA northbridge, which is compatible to
>> 1337 bonito64.
>> 1338
>> 1339 config CPU_LOONGSON2F
>> 1340 bool "Loongson 2F"
>> 1341 depends on SYS_HAS_CPU_LOONGSON2F
>> 1342 select CPU_LOONGSON2EF
>> 1343 help
>> 1344 The Loongson 2F processor implements the MIPS III instruction set
>> 1345 with many extensions.
>> 1346
>> 1347 Loongson2F have built-in DDR2 and PCIX controller. The PCIX controller
>> 1348 have a similar programming interface with FPGA northbridge used in
>> 1349 Loongson2E.
>> 1350
>> 1351 config CPU_LOONGSON1B
>> 1352 bool "Loongson 1B"
>> 1353 depends on SYS_HAS_CPU_LOONGSON1B
>> 1354 select CPU_LOONGSON32
>> 1355 select LEDS_GPIO_REGISTER
>> 1356 help
>> 1357 The Loongson 1B is a 32-bit SoC, which implements the MIPS32
>> 1358 Release 1 instruction set and part of the MIPS32 Release 2
>> 1359 instruction set.
>> 1360
>> 1361 config CPU_LOONGSON1C
>> 1362 bool "Loongson 1C"
>> 1363 depends on SYS_HAS_CPU_LOONGSON1C
>> 1364 select CPU_LOONGSON32
>> 1365 select LEDS_GPIO_REGISTER
>> 1366 help
>> 1367 The Loongson 1C is a 32-bit SoC, which implements the MIPS32
>> 1368 Release 1 instruction set and part of the MIPS32 Release 2
>> 1369 instruction set.
>> 1370
>> 1371 config CPU_MIPS32_R1
>> 1372 bool "MIPS32 Release 1"
>> 1373 depends on SYS_HAS_CPU_MIPS32_R1
>> 1374 select CPU_HAS_PREFETCH
>> 1375 select CPU_SUPPORTS_32BIT_KERNEL
>> 1376 select CPU_SUPPORTS_HIGHMEM
>> 1377 help
>> 1378 Choose this option to build a kernel for release 1 or later of the
>> 1379 MIPS32 architecture. Most modern embedded systems with a 32-bit
>> 1380 MIPS processor are based on a MIPS32 processor. If you know the
>> 1381 specific type of processor in your system, choose those that one
>> 1382 otherwise CPU_MIPS32_R1 is a safe bet for any MIPS32 system.
>> 1383 Release 2 of the MIPS32 architecture is available since several
>> 1384 years so chances are you even have a MIPS32 Release 2 processor
>> 1385 in which case you should choose CPU_MIPS32_R2 instead for better
>> 1386 performance.
>> 1387
>> 1388 config CPU_MIPS32_R2
>> 1389 bool "MIPS32 Release 2"
>> 1390 depends on SYS_HAS_CPU_MIPS32_R2
>> 1391 select CPU_HAS_PREFETCH
>> 1392 select CPU_SUPPORTS_32BIT_KERNEL
>> 1393 select CPU_SUPPORTS_HIGHMEM
>> 1394 select CPU_SUPPORTS_MSA
>> 1395 select HAVE_KVM
>> 1396 help
>> 1397 Choose this option to build a kernel for release 2 or later of the
>> 1398 MIPS32 architecture. Most modern embedded systems with a 32-bit
>> 1399 MIPS processor are based on a MIPS32 processor. If you know the
>> 1400 specific type of processor in your system, choose those that one
>> 1401 otherwise CPU_MIPS32_R1 is a safe bet for any MIPS32 system.
>> 1402
>> 1403 config CPU_MIPS32_R5
>> 1404 bool "MIPS32 Release 5"
>> 1405 depends on SYS_HAS_CPU_MIPS32_R5
>> 1406 select CPU_HAS_PREFETCH
>> 1407 select CPU_SUPPORTS_32BIT_KERNEL
>> 1408 select CPU_SUPPORTS_HIGHMEM
>> 1409 select CPU_SUPPORTS_MSA
>> 1410 select HAVE_KVM
>> 1411 select MIPS_O32_FP64_SUPPORT
>> 1412 help
>> 1413 Choose this option to build a kernel for release 5 or later of the
>> 1414 MIPS32 architecture. New MIPS processors, starting with the Warrior
>> 1415 family, are based on a MIPS32r5 processor. If you own an older
>> 1416 processor, you probably need to select MIPS32r1 or MIPS32r2 instead.
>> 1417
>> 1418 config CPU_MIPS32_R6
>> 1419 bool "MIPS32 Release 6"
>> 1420 depends on SYS_HAS_CPU_MIPS32_R6
>> 1421 select CPU_HAS_PREFETCH
>> 1422 select CPU_NO_LOAD_STORE_LR
>> 1423 select CPU_SUPPORTS_32BIT_KERNEL
>> 1424 select CPU_SUPPORTS_HIGHMEM
>> 1425 select CPU_SUPPORTS_MSA
>> 1426 select HAVE_KVM
>> 1427 select MIPS_O32_FP64_SUPPORT
>> 1428 help
>> 1429 Choose this option to build a kernel for release 6 or later of the
>> 1430 MIPS32 architecture. New MIPS processors, starting with the Warrior
>> 1431 family, are based on a MIPS32r6 processor. If you own an older
>> 1432 processor, you probably need to select MIPS32r1 or MIPS32r2 instead.
>> 1433
>> 1434 config CPU_MIPS64_R1
>> 1435 bool "MIPS64 Release 1"
>> 1436 depends on SYS_HAS_CPU_MIPS64_R1
>> 1437 select CPU_HAS_PREFETCH
>> 1438 select CPU_SUPPORTS_32BIT_KERNEL
>> 1439 select CPU_SUPPORTS_64BIT_KERNEL
>> 1440 select CPU_SUPPORTS_HIGHMEM
>> 1441 select CPU_SUPPORTS_HUGEPAGES
>> 1442 help
>> 1443 Choose this option to build a kernel for release 1 or later of the
>> 1444 MIPS64 architecture. Many modern embedded systems with a 64-bit
>> 1445 MIPS processor are based on a MIPS64 processor. If you know the
>> 1446 specific type of processor in your system, choose those that one
>> 1447 otherwise CPU_MIPS64_R1 is a safe bet for any MIPS64 system.
>> 1448 Release 2 of the MIPS64 architecture is available since several
>> 1449 years so chances are you even have a MIPS64 Release 2 processor
>> 1450 in which case you should choose CPU_MIPS64_R2 instead for better
>> 1451 performance.
>> 1452
>> 1453 config CPU_MIPS64_R2
>> 1454 bool "MIPS64 Release 2"
>> 1455 depends on SYS_HAS_CPU_MIPS64_R2
>> 1456 select CPU_HAS_PREFETCH
>> 1457 select CPU_SUPPORTS_32BIT_KERNEL
>> 1458 select CPU_SUPPORTS_64BIT_KERNEL
>> 1459 select CPU_SUPPORTS_HIGHMEM
>> 1460 select CPU_SUPPORTS_HUGEPAGES
>> 1461 select CPU_SUPPORTS_MSA
>> 1462 select HAVE_KVM
>> 1463 help
>> 1464 Choose this option to build a kernel for release 2 or later of the
>> 1465 MIPS64 architecture. Many modern embedded systems with a 64-bit
>> 1466 MIPS processor are based on a MIPS64 processor. If you know the
>> 1467 specific type of processor in your system, choose those that one
>> 1468 otherwise CPU_MIPS64_R1 is a safe bet for any MIPS64 system.
>> 1469
>> 1470 config CPU_MIPS64_R5
>> 1471 bool "MIPS64 Release 5"
>> 1472 depends on SYS_HAS_CPU_MIPS64_R5
>> 1473 select CPU_HAS_PREFETCH
>> 1474 select CPU_SUPPORTS_32BIT_KERNEL
>> 1475 select CPU_SUPPORTS_64BIT_KERNEL
>> 1476 select CPU_SUPPORTS_HIGHMEM
>> 1477 select CPU_SUPPORTS_HUGEPAGES
>> 1478 select CPU_SUPPORTS_MSA
>> 1479 select MIPS_O32_FP64_SUPPORT if 32BIT || MIPS32_O32
>> 1480 select HAVE_KVM
>> 1481 help
>> 1482 Choose this option to build a kernel for release 5 or later of the
>> 1483 MIPS64 architecture. This is a intermediate MIPS architecture
>> 1484 release partly implementing release 6 features. Though there is no
>> 1485 any hardware known to be based on this release.
>> 1486
>> 1487 config CPU_MIPS64_R6
>> 1488 bool "MIPS64 Release 6"
>> 1489 depends on SYS_HAS_CPU_MIPS64_R6
>> 1490 select CPU_HAS_PREFETCH
>> 1491 select CPU_NO_LOAD_STORE_LR
>> 1492 select CPU_SUPPORTS_32BIT_KERNEL
>> 1493 select CPU_SUPPORTS_64BIT_KERNEL
>> 1494 select CPU_SUPPORTS_HIGHMEM
>> 1495 select CPU_SUPPORTS_HUGEPAGES
>> 1496 select CPU_SUPPORTS_MSA
>> 1497 select MIPS_O32_FP64_SUPPORT if 32BIT || MIPS32_O32
>> 1498 select HAVE_KVM
>> 1499 help
>> 1500 Choose this option to build a kernel for release 6 or later of the
>> 1501 MIPS64 architecture. New MIPS processors, starting with the Warrior
>> 1502 family, are based on a MIPS64r6 processor. If you own an older
>> 1503 processor, you probably need to select MIPS64r1 or MIPS64r2 instead.
>> 1504
>> 1505 config CPU_P5600
>> 1506 bool "MIPS Warrior P5600"
>> 1507 depends on SYS_HAS_CPU_P5600
>> 1508 select CPU_HAS_PREFETCH
>> 1509 select CPU_SUPPORTS_32BIT_KERNEL
>> 1510 select CPU_SUPPORTS_HIGHMEM
>> 1511 select CPU_SUPPORTS_MSA
>> 1512 select CPU_SUPPORTS_CPUFREQ
>> 1513 select CPU_MIPSR2_IRQ_VI
>> 1514 select CPU_MIPSR2_IRQ_EI
>> 1515 select HAVE_KVM
>> 1516 select MIPS_O32_FP64_SUPPORT
>> 1517 help
>> 1518 Choose this option to build a kernel for MIPS Warrior P5600 CPU.
>> 1519 It's based on MIPS32r5 ISA with XPA, EVA, dual/quad issue exec pipes,
>> 1520 MMU with two-levels TLB, UCA, MSA, MDU core level features and system
>> 1521 level features like up to six P5600 calculation cores, CM2 with L2
>> 1522 cache, IOCU/IOMMU (though might be unused depending on the system-
>> 1523 specific IP core configuration), GIC, CPC, virtualisation module,
>> 1524 eJTAG and PDtrace.
>> 1525
>> 1526 config CPU_R3000
>> 1527 bool "R3000"
>> 1528 depends on SYS_HAS_CPU_R3000
>> 1529 select CPU_HAS_WB
>> 1530 select CPU_R3K_TLB
>> 1531 select CPU_SUPPORTS_32BIT_KERNEL
>> 1532 select CPU_SUPPORTS_HIGHMEM
>> 1533 help
>> 1534 Please make sure to pick the right CPU type. Linux/MIPS is not
>> 1535 designed to be generic, i.e. Kernels compiled for R3000 CPUs will
>> 1536 *not* work on R4000 machines and vice versa. However, since most
>> 1537 of the supported machines have an R4000 (or similar) CPU, R4x00
>> 1538 might be a safe bet. If the resulting kernel does not work,
>> 1539 try to recompile with R3000.
>> 1540
>> 1541 config CPU_R4300
>> 1542 bool "R4300"
>> 1543 depends on SYS_HAS_CPU_R4300
>> 1544 select CPU_SUPPORTS_32BIT_KERNEL
>> 1545 select CPU_SUPPORTS_64BIT_KERNEL
>> 1546 help
>> 1547 MIPS Technologies R4300-series processors.
>> 1548
>> 1549 config CPU_R4X00
>> 1550 bool "R4x00"
>> 1551 depends on SYS_HAS_CPU_R4X00
>> 1552 select CPU_SUPPORTS_32BIT_KERNEL
>> 1553 select CPU_SUPPORTS_64BIT_KERNEL
>> 1554 select CPU_SUPPORTS_HUGEPAGES
>> 1555 help
>> 1556 MIPS Technologies R4000-series processors other than 4300, including
>> 1557 the R4000, R4400, R4600, and 4700.
>> 1558
>> 1559 config CPU_TX49XX
>> 1560 bool "R49XX"
>> 1561 depends on SYS_HAS_CPU_TX49XX
>> 1562 select CPU_HAS_PREFETCH
>> 1563 select CPU_SUPPORTS_32BIT_KERNEL
>> 1564 select CPU_SUPPORTS_64BIT_KERNEL
>> 1565 select CPU_SUPPORTS_HUGEPAGES
>> 1566
>> 1567 config CPU_R5000
>> 1568 bool "R5000"
>> 1569 depends on SYS_HAS_CPU_R5000
>> 1570 select CPU_SUPPORTS_32BIT_KERNEL
>> 1571 select CPU_SUPPORTS_64BIT_KERNEL
>> 1572 select CPU_SUPPORTS_HUGEPAGES
>> 1573 help
>> 1574 MIPS Technologies R5000-series processors other than the Nevada.
>> 1575
>> 1576 config CPU_R5500
>> 1577 bool "R5500"
>> 1578 depends on SYS_HAS_CPU_R5500
>> 1579 select CPU_SUPPORTS_32BIT_KERNEL
>> 1580 select CPU_SUPPORTS_64BIT_KERNEL
>> 1581 select CPU_SUPPORTS_HUGEPAGES
>> 1582 help
>> 1583 NEC VR5500 and VR5500A series processors implement 64-bit MIPS IV
>> 1584 instruction set.
>> 1585
>> 1586 config CPU_NEVADA
>> 1587 bool "RM52xx"
>> 1588 depends on SYS_HAS_CPU_NEVADA
>> 1589 select CPU_SUPPORTS_32BIT_KERNEL
>> 1590 select CPU_SUPPORTS_64BIT_KERNEL
>> 1591 select CPU_SUPPORTS_HUGEPAGES
>> 1592 help
>> 1593 QED / PMC-Sierra RM52xx-series ("Nevada") processors.
>> 1594
>> 1595 config CPU_R10000
>> 1596 bool "R10000"
>> 1597 depends on SYS_HAS_CPU_R10000
>> 1598 select CPU_HAS_PREFETCH
>> 1599 select CPU_SUPPORTS_32BIT_KERNEL
>> 1600 select CPU_SUPPORTS_64BIT_KERNEL
>> 1601 select CPU_SUPPORTS_HIGHMEM
>> 1602 select CPU_SUPPORTS_HUGEPAGES
>> 1603 help
>> 1604 MIPS Technologies R10000-series processors.
>> 1605
>> 1606 config CPU_RM7000
>> 1607 bool "RM7000"
>> 1608 depends on SYS_HAS_CPU_RM7000
>> 1609 select CPU_HAS_PREFETCH
>> 1610 select CPU_SUPPORTS_32BIT_KERNEL
>> 1611 select CPU_SUPPORTS_64BIT_KERNEL
>> 1612 select CPU_SUPPORTS_HIGHMEM
>> 1613 select CPU_SUPPORTS_HUGEPAGES
>> 1614
>> 1615 config CPU_SB1
>> 1616 bool "SB1"
>> 1617 depends on SYS_HAS_CPU_SB1
>> 1618 select CPU_SUPPORTS_32BIT_KERNEL
>> 1619 select CPU_SUPPORTS_64BIT_KERNEL
>> 1620 select CPU_SUPPORTS_HIGHMEM
>> 1621 select CPU_SUPPORTS_HUGEPAGES
>> 1622 select WEAK_ORDERING
>> 1623
>> 1624 config CPU_CAVIUM_OCTEON
>> 1625 bool "Cavium Octeon processor"
>> 1626 depends on SYS_HAS_CPU_CAVIUM_OCTEON
>> 1627 select CPU_HAS_PREFETCH
>> 1628 select CPU_SUPPORTS_64BIT_KERNEL
>> 1629 select WEAK_ORDERING
>> 1630 select CPU_SUPPORTS_HIGHMEM
>> 1631 select CPU_SUPPORTS_HUGEPAGES
>> 1632 select USB_EHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 1633 select USB_OHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 1634 select MIPS_L1_CACHE_SHIFT_7
>> 1635 select HAVE_KVM
>> 1636 help
>> 1637 The Cavium Octeon processor is a highly integrated chip containing
>> 1638 many ethernet hardware widgets for networking tasks. The processor
>> 1639 can have up to 16 Mips64v2 cores and 8 integrated gigabit ethernets.
>> 1640 Full details can be found at http://www.caviumnetworks.com.
>> 1641
>> 1642 config CPU_BMIPS
>> 1643 bool "Broadcom BMIPS"
>> 1644 depends on SYS_HAS_CPU_BMIPS
>> 1645 select CPU_MIPS32
>> 1646 select CPU_BMIPS32_3300 if SYS_HAS_CPU_BMIPS32_3300
>> 1647 select CPU_BMIPS4350 if SYS_HAS_CPU_BMIPS4350
>> 1648 select CPU_BMIPS4380 if SYS_HAS_CPU_BMIPS4380
>> 1649 select CPU_BMIPS5000 if SYS_HAS_CPU_BMIPS5000
>> 1650 select CPU_SUPPORTS_32BIT_KERNEL
>> 1651 select DMA_NONCOHERENT
>> 1652 select IRQ_MIPS_CPU
>> 1653 select SWAP_IO_SPACE
>> 1654 select WEAK_ORDERING
>> 1655 select CPU_SUPPORTS_HIGHMEM
>> 1656 select CPU_HAS_PREFETCH
>> 1657 select CPU_SUPPORTS_CPUFREQ
>> 1658 select MIPS_EXTERNAL_TIMER
>> 1659 select GENERIC_IRQ_MIGRATION if HOTPLUG_CPU
830 help 1660 help
831 This option adds the workaround for !! 1661 Support for BMIPS32/3300/4350/4380 and BMIPS5000 processors.
832 Affected Cortex-A510 (r0p0 to r1p1) <<
833 BFMMLA or VMMLA instructions in rare <<
834 A510 CPUs are using shared neon hard <<
835 discoverable by the kernel, hide the <<
836 user-space should not be using these <<
837 1662
838 If unsure, say Y. !! 1663 endchoice
839 1664
840 config ARM64_ERRATUM_2119858 !! 1665 config CPU_MIPS32_3_5_FEATURES
841 bool "Cortex-A710/X2: 2119858: workaro !! 1666 bool "MIPS32 Release 3.5 Features"
842 default y !! 1667 depends on SYS_HAS_CPU_MIPS32_R3_5
843 depends on CORESIGHT_TRBE !! 1668 depends on CPU_MIPS32_R2 || CPU_MIPS32_R5 || CPU_MIPS32_R6 || \
844 select ARM64_WORKAROUND_TRBE_OVERWRITE !! 1669 CPU_P5600
>> 1670 help
>> 1671 Choose this option to build a kernel for release 2 or later of the
>> 1672 MIPS32 architecture including features from the 3.5 release such as
>> 1673 support for Enhanced Virtual Addressing (EVA).
>> 1674
>> 1675 config CPU_MIPS32_3_5_EVA
>> 1676 bool "Enhanced Virtual Addressing (EVA)"
>> 1677 depends on CPU_MIPS32_3_5_FEATURES
>> 1678 select EVA
>> 1679 default y
>> 1680 help
>> 1681 Choose this option if you want to enable the Enhanced Virtual
>> 1682 Addressing (EVA) on your MIPS32 core (such as proAptiv).
>> 1683 One of its primary benefits is an increase in the maximum size
>> 1684 of lowmem (up to 3GB). If unsure, say 'N' here.
>> 1685
>> 1686 config CPU_MIPS32_R5_FEATURES
>> 1687 bool "MIPS32 Release 5 Features"
>> 1688 depends on SYS_HAS_CPU_MIPS32_R5
>> 1689 depends on CPU_MIPS32_R2 || CPU_MIPS32_R5 || CPU_P5600
>> 1690 help
>> 1691 Choose this option to build a kernel for release 2 or later of the
>> 1692 MIPS32 architecture including features from release 5 such as
>> 1693 support for Extended Physical Addressing (XPA).
>> 1694
>> 1695 config CPU_MIPS32_R5_XPA
>> 1696 bool "Extended Physical Addressing (XPA)"
>> 1697 depends on CPU_MIPS32_R5_FEATURES
>> 1698 depends on !EVA
>> 1699 depends on !PAGE_SIZE_4KB
>> 1700 depends on SYS_SUPPORTS_HIGHMEM
>> 1701 select XPA
>> 1702 select HIGHMEM
>> 1703 select PHYS_ADDR_T_64BIT
>> 1704 default n
845 help 1705 help
846 This option adds the workaround for !! 1706 Choose this option if you want to enable the Extended Physical
>> 1707 Addressing (XPA) on your MIPS32 core (such as P5600 series). The
>> 1708 benefit is to increase physical addressing equal to or greater
>> 1709 than 40 bits. Note that this has the side effect of turning on
>> 1710 64-bit addressing which in turn makes the PTEs 64-bit in size.
>> 1711 If unsure, say 'N' here.
847 1712
848 Affected Cortex-A710/X2 cores could !! 1713 if CPU_LOONGSON2F
849 data at the base of the buffer (poin !! 1714 config CPU_NOP_WORKAROUNDS
850 the event of a WRAP event. !! 1715 bool
851 <<
852 Work around the issue by always maki <<
853 256 bytes before enabling the buffer <<
854 the buffer with ETM ignore packets u <<
855 1716
856 If unsure, say Y. !! 1717 config CPU_JUMP_WORKAROUNDS
>> 1718 bool
857 1719
858 config ARM64_ERRATUM_2139208 !! 1720 config CPU_LOONGSON2F_WORKAROUNDS
859 bool "Neoverse-N2: 2139208: workaround !! 1721 bool "Loongson 2F Workarounds"
860 default y 1722 default y
861 depends on CORESIGHT_TRBE !! 1723 select CPU_NOP_WORKAROUNDS
862 select ARM64_WORKAROUND_TRBE_OVERWRITE !! 1724 select CPU_JUMP_WORKAROUNDS
863 help 1725 help
864 This option adds the workaround for !! 1726 Loongson 2F01 / 2F02 processors have the NOP & JUMP issues which
865 !! 1727 require workarounds. Without workarounds the system may hang
866 Affected Neoverse-N2 cores could ove !! 1728 unexpectedly. For more information please refer to the gas
867 data at the base of the buffer (poin !! 1729 -mfix-loongson2f-nop and -mfix-loongson2f-jump options.
868 the event of a WRAP event. !! 1730
869 !! 1731 Loongson 2F03 and later have fixed these issues and no workarounds
870 Work around the issue by always maki !! 1732 are needed. The workarounds have no significant side effect on them
871 256 bytes before enabling the buffer !! 1733 but may decrease the performance of the system so this option should
872 the buffer with ETM ignore packets u !! 1734 be disabled unless the kernel is intended to be run on 2F01 or 2F02
>> 1735 systems.
873 1736
874 If unsure, say Y. !! 1737 If unsure, please say Y.
>> 1738 endif # CPU_LOONGSON2F
875 1739
876 config ARM64_WORKAROUND_TSB_FLUSH_FAILURE !! 1740 config SYS_SUPPORTS_ZBOOT
877 bool 1741 bool
>> 1742 select HAVE_KERNEL_GZIP
>> 1743 select HAVE_KERNEL_BZIP2
>> 1744 select HAVE_KERNEL_LZ4
>> 1745 select HAVE_KERNEL_LZMA
>> 1746 select HAVE_KERNEL_LZO
>> 1747 select HAVE_KERNEL_XZ
>> 1748 select HAVE_KERNEL_ZSTD
878 1749
879 config ARM64_ERRATUM_2054223 !! 1750 config SYS_SUPPORTS_ZBOOT_UART16550
880 bool "Cortex-A710: 2054223: workaround !! 1751 bool
881 default y !! 1752 select SYS_SUPPORTS_ZBOOT
882 select ARM64_WORKAROUND_TSB_FLUSH_FAIL <<
883 help <<
884 Enable workaround for ARM Cortex-A71 <<
885 1753
886 Affected cores may fail to flush the !! 1754 config SYS_SUPPORTS_ZBOOT_UART_PROM
887 the PE is in trace prohibited state. !! 1755 bool
888 of the trace cached. !! 1756 select SYS_SUPPORTS_ZBOOT
889 1757
890 Workaround is to issue two TSB conse !! 1758 config CPU_LOONGSON2EF
>> 1759 bool
>> 1760 select CPU_SUPPORTS_32BIT_KERNEL
>> 1761 select CPU_SUPPORTS_64BIT_KERNEL
>> 1762 select CPU_SUPPORTS_HIGHMEM
>> 1763 select CPU_SUPPORTS_HUGEPAGES
891 1764
892 If unsure, say Y. !! 1765 config CPU_LOONGSON32
>> 1766 bool
>> 1767 select CPU_MIPS32
>> 1768 select CPU_MIPSR2
>> 1769 select CPU_HAS_PREFETCH
>> 1770 select CPU_SUPPORTS_32BIT_KERNEL
>> 1771 select CPU_SUPPORTS_HIGHMEM
>> 1772 select CPU_SUPPORTS_CPUFREQ
893 1773
894 config ARM64_ERRATUM_2067961 !! 1774 config CPU_BMIPS32_3300
895 bool "Neoverse-N2: 2067961: workaround !! 1775 select SMP_UP if SMP
896 default y !! 1776 bool
897 select ARM64_WORKAROUND_TSB_FLUSH_FAIL <<
898 help <<
899 Enable workaround for ARM Neoverse-N <<
900 1777
901 Affected cores may fail to flush the !! 1778 config CPU_BMIPS4350
902 the PE is in trace prohibited state. !! 1779 bool
903 of the trace cached. !! 1780 select SYS_SUPPORTS_SMP
>> 1781 select SYS_SUPPORTS_HOTPLUG_CPU
904 1782
905 Workaround is to issue two TSB conse !! 1783 config CPU_BMIPS4380
>> 1784 bool
>> 1785 select MIPS_L1_CACHE_SHIFT_6
>> 1786 select SYS_SUPPORTS_SMP
>> 1787 select SYS_SUPPORTS_HOTPLUG_CPU
>> 1788 select CPU_HAS_RIXI
906 1789
907 If unsure, say Y. !! 1790 config CPU_BMIPS5000
>> 1791 bool
>> 1792 select MIPS_CPU_SCACHE
>> 1793 select MIPS_L1_CACHE_SHIFT_7
>> 1794 select SYS_SUPPORTS_SMP
>> 1795 select SYS_SUPPORTS_HOTPLUG_CPU
>> 1796 select CPU_HAS_RIXI
908 1797
909 config ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANG !! 1798 config SYS_HAS_CPU_LOONGSON64
910 bool 1799 bool
>> 1800 select CPU_SUPPORTS_CPUFREQ
>> 1801 select CPU_HAS_RIXI
911 1802
912 config ARM64_ERRATUM_2253138 !! 1803 config SYS_HAS_CPU_LOONGSON2E
913 bool "Neoverse-N2: 2253138: workaround !! 1804 bool
914 depends on CORESIGHT_TRBE <<
915 default y <<
916 select ARM64_WORKAROUND_TRBE_WRITE_OUT <<
917 help <<
918 This option adds the workaround for <<
919 1805
920 Affected Neoverse-N2 cores might wri !! 1806 config SYS_HAS_CPU_LOONGSON2F
921 for TRBE. Under some conditions, the !! 1807 bool
922 virtually addressed page following t !! 1808 select CPU_SUPPORTS_CPUFREQ
923 (i.e., the TRBLIMITR_EL1.LIMIT), ins !! 1809 select CPU_SUPPORTS_ADDRWINCFG if 64BIT
924 1810
925 Work around this in the driver by al !! 1811 config SYS_HAS_CPU_LOONGSON1B
926 page beyond the TRBLIMITR_EL1.LIMIT, !! 1812 bool
927 1813
928 If unsure, say Y. !! 1814 config SYS_HAS_CPU_LOONGSON1C
>> 1815 bool
929 1816
930 config ARM64_ERRATUM_2224489 !! 1817 config SYS_HAS_CPU_MIPS32_R1
931 bool "Cortex-A710/X2: 2224489: workaro !! 1818 bool
932 depends on CORESIGHT_TRBE <<
933 default y <<
934 select ARM64_WORKAROUND_TRBE_WRITE_OUT <<
935 help <<
936 This option adds the workaround for <<
937 1819
938 Affected Cortex-A710/X2 cores might !! 1820 config SYS_HAS_CPU_MIPS32_R2
939 for TRBE. Under some conditions, the !! 1821 bool
940 virtually addressed page following t <<
941 (i.e., the TRBLIMITR_EL1.LIMIT), ins <<
942 1822
943 Work around this in the driver by al !! 1823 config SYS_HAS_CPU_MIPS32_R3_5
944 page beyond the TRBLIMITR_EL1.LIMIT, !! 1824 bool
945 1825
946 If unsure, say Y. !! 1826 config SYS_HAS_CPU_MIPS32_R5
>> 1827 bool
947 1828
948 config ARM64_ERRATUM_2441009 !! 1829 config SYS_HAS_CPU_MIPS32_R6
949 bool "Cortex-A510: Completion of affec !! 1830 bool
950 select ARM64_WORKAROUND_REPEAT_TLBI <<
951 help <<
952 This option adds a workaround for AR <<
953 <<
954 Under very rare circumstances, affec <<
955 may not handle a race between a brea <<
956 CPU, and another CPU accessing the s <<
957 store to a page that has been unmapp <<
958 1831
959 Work around this by adding the affec !! 1832 config SYS_HAS_CPU_MIPS64_R1
960 TLB sequences to be done twice. !! 1833 bool
961 1834
962 If unsure, say N. !! 1835 config SYS_HAS_CPU_MIPS64_R2
>> 1836 bool
963 1837
964 config ARM64_ERRATUM_2064142 !! 1838 config SYS_HAS_CPU_MIPS64_R5
965 bool "Cortex-A510: 2064142: workaround !! 1839 bool
966 depends on CORESIGHT_TRBE <<
967 default y <<
968 help <<
969 This option adds the workaround for <<
970 1840
971 Affected Cortex-A510 core might fail !! 1841 config SYS_HAS_CPU_MIPS64_R6
972 TRBE has been disabled. Under some c !! 1842 bool
973 writes into TRBE registers TRBLIMITR <<
974 and TRBTRG_EL1 will be ignored and w <<
975 <<
976 Work around this in the driver by ex <<
977 is stopped and before performing a s <<
978 registers. <<
979 1843
980 If unsure, say Y. !! 1844 config SYS_HAS_CPU_P5600
>> 1845 bool
981 1846
982 config ARM64_ERRATUM_2038923 !! 1847 config SYS_HAS_CPU_R3000
983 bool "Cortex-A510: 2038923: workaround !! 1848 bool
984 depends on CORESIGHT_TRBE <<
985 default y <<
986 help <<
987 This option adds the workaround for <<
988 1849
989 Affected Cortex-A510 core might caus !! 1850 config SYS_HAS_CPU_R4300
990 prohibited within the CPU. As a resu !! 1851 bool
991 might be corrupted. This happens aft <<
992 TRBLIMITR_EL1.E, followed by just a <<
993 execution changes from a context, in <<
994 isn't, or vice versa. In these menti <<
995 is prohibited is inconsistent betwee <<
996 the trace buffer state might be corr <<
997 <<
998 Work around this in the driver by pr <<
999 trace is prohibited or not based on <<
1000 change to TRBLIMITR_EL1.E with at l <<
1001 two ISB instructions if no ERET is <<
1002 1852
1003 If unsure, say Y. !! 1853 config SYS_HAS_CPU_R4X00
>> 1854 bool
1004 1855
1005 config ARM64_ERRATUM_1902691 !! 1856 config SYS_HAS_CPU_TX49XX
1006 bool "Cortex-A510: 1902691: workaroun !! 1857 bool
1007 depends on CORESIGHT_TRBE <<
1008 default y <<
1009 help <<
1010 This option adds the workaround for <<
1011 1858
1012 Affected Cortex-A510 core might cau !! 1859 config SYS_HAS_CPU_R5000
1013 into the memory. Effectively TRBE i !! 1860 bool
1014 trace data. <<
1015 <<
1016 Work around this problem in the dri <<
1017 affected cpus. The firmware must ha <<
1018 on such implementations. This will <<
1019 do this already. <<
1020 1861
1021 If unsure, say Y. !! 1862 config SYS_HAS_CPU_R5500
>> 1863 bool
1022 1864
1023 config ARM64_ERRATUM_2457168 !! 1865 config SYS_HAS_CPU_NEVADA
1024 bool "Cortex-A510: 2457168: workaroun !! 1866 bool
1025 depends on ARM64_AMU_EXTN <<
1026 default y <<
1027 help <<
1028 This option adds the workaround for <<
1029 1867
1030 The AMU counter AMEVCNTR01 (constan !! 1868 config SYS_HAS_CPU_R10000
1031 as the system counter. On affected !! 1869 bool
1032 incorrectly giving a significantly <<
1033 <<
1034 Work around this problem by returni <<
1035 key locations that results in disab <<
1036 is the same to firmware disabling a <<
1037 1870
1038 If unsure, say Y. !! 1871 config SYS_HAS_CPU_RM7000
>> 1872 bool
1039 1873
1040 config ARM64_ERRATUM_2645198 !! 1874 config SYS_HAS_CPU_SB1
1041 bool "Cortex-A715: 2645198: Workaroun !! 1875 bool
1042 default y <<
1043 help <<
1044 This option adds the workaround for <<
1045 1876
1046 If a Cortex-A715 cpu sees a page ma !! 1877 config SYS_HAS_CPU_CAVIUM_OCTEON
1047 to non-executable, it may corrupt t !! 1878 bool
1048 next instruction abort caused by pe <<
1049 <<
1050 Only user-space does executable to <<
1051 mprotect() system call. Workaround <<
1052 TLB invalidation, for all changes t <<
1053 1879
1054 If unsure, say Y. !! 1880 config SYS_HAS_CPU_BMIPS
>> 1881 bool
1055 1882
1056 config ARM64_WORKAROUND_SPECULATIVE_UNPRIV_LO !! 1883 config SYS_HAS_CPU_BMIPS32_3300
1057 bool 1884 bool
>> 1885 select SYS_HAS_CPU_BMIPS
1058 1886
1059 config ARM64_ERRATUM_2966298 !! 1887 config SYS_HAS_CPU_BMIPS4350
1060 bool "Cortex-A520: 2966298: workaroun !! 1888 bool
1061 select ARM64_WORKAROUND_SPECULATIVE_U !! 1889 select SYS_HAS_CPU_BMIPS
1062 default y <<
1063 help <<
1064 This option adds the workaround for <<
1065 1890
1066 On an affected Cortex-A520 core, a !! 1891 config SYS_HAS_CPU_BMIPS4380
1067 load might leak data from a privile !! 1892 bool
>> 1893 select SYS_HAS_CPU_BMIPS
1068 1894
1069 Work around this problem by executi !! 1895 config SYS_HAS_CPU_BMIPS5000
>> 1896 bool
>> 1897 select SYS_HAS_CPU_BMIPS
1070 1898
1071 If unsure, say Y. !! 1899 #
>> 1900 # CPU may reorder R->R, R->W, W->R, W->W
>> 1901 # Reordering beyond LL and SC is handled in WEAK_REORDERING_BEYOND_LLSC
>> 1902 #
>> 1903 config WEAK_ORDERING
>> 1904 bool
1072 1905
1073 config ARM64_ERRATUM_3117295 !! 1906 #
1074 bool "Cortex-A510: 3117295: workaroun !! 1907 # CPU may reorder reads and writes beyond LL/SC
1075 select ARM64_WORKAROUND_SPECULATIVE_U !! 1908 # CPU may reorder R->LL, R->LL, W->LL, W->LL, R->SC, R->SC, W->SC, W->SC
1076 default y !! 1909 #
1077 help !! 1910 config WEAK_REORDERING_BEYOND_LLSC
1078 This option adds the workaround for !! 1911 bool
>> 1912 endmenu
1079 1913
1080 On an affected Cortex-A510 core, a !! 1914 #
1081 load might leak data from a privile !! 1915 # These two indicate any level of the MIPS32 and MIPS64 architecture
>> 1916 #
>> 1917 config CPU_MIPS32
>> 1918 bool
>> 1919 default y if CPU_MIPS32_R1 || CPU_MIPS32_R2 || CPU_MIPS32_R5 || \
>> 1920 CPU_MIPS32_R6 || CPU_P5600
1082 1921
1083 Work around this problem by executi !! 1922 config CPU_MIPS64
>> 1923 bool
>> 1924 default y if CPU_MIPS64_R1 || CPU_MIPS64_R2 || CPU_MIPS64_R5 || \
>> 1925 CPU_MIPS64_R6 || CPU_LOONGSON64 || CPU_CAVIUM_OCTEON
1084 1926
1085 If unsure, say Y. !! 1927 #
>> 1928 # These indicate the revision of the architecture
>> 1929 #
>> 1930 config CPU_MIPSR1
>> 1931 bool
>> 1932 default y if CPU_MIPS32_R1 || CPU_MIPS64_R1
1086 1933
1087 config ARM64_ERRATUM_3194386 !! 1934 config CPU_MIPSR2
1088 bool "Cortex-*/Neoverse-*: workaround !! 1935 bool
1089 default y !! 1936 default y if CPU_MIPS32_R2 || CPU_MIPS64_R2 || CPU_CAVIUM_OCTEON
1090 help !! 1937 select CPU_HAS_RIXI
1091 This option adds the workaround for !! 1938 select CPU_HAS_DIEI if !CPU_DIEI_BROKEN
>> 1939 select MIPS_SPRAM
1092 1940
1093 * ARM Cortex-A76 erratum 3324349 !! 1941 config CPU_MIPSR5
1094 * ARM Cortex-A77 erratum 3324348 !! 1942 bool
1095 * ARM Cortex-A78 erratum 3324344 !! 1943 default y if CPU_MIPS32_R5 || CPU_MIPS64_R5 || CPU_P5600
1096 * ARM Cortex-A78C erratum 3324346 !! 1944 select CPU_HAS_RIXI
1097 * ARM Cortex-A78C erratum 3324347 !! 1945 select CPU_HAS_DIEI if !CPU_DIEI_BROKEN
1098 * ARM Cortex-A710 erratam 3324338 !! 1946 select MIPS_SPRAM
1099 * ARM Cortex-A715 errartum 3456084 <<
1100 * ARM Cortex-A720 erratum 3456091 <<
1101 * ARM Cortex-A725 erratum 3456106 <<
1102 * ARM Cortex-X1 erratum 3324344 <<
1103 * ARM Cortex-X1C erratum 3324346 <<
1104 * ARM Cortex-X2 erratum 3324338 <<
1105 * ARM Cortex-X3 erratum 3324335 <<
1106 * ARM Cortex-X4 erratum 3194386 <<
1107 * ARM Cortex-X925 erratum 3324334 <<
1108 * ARM Neoverse-N1 erratum 3324349 <<
1109 * ARM Neoverse N2 erratum 3324339 <<
1110 * ARM Neoverse-N3 erratum 3456111 <<
1111 * ARM Neoverse-V1 erratum 3324341 <<
1112 * ARM Neoverse V2 erratum 3324336 <<
1113 * ARM Neoverse-V3 erratum 3312417 <<
1114 <<
1115 On affected cores "MSR SSBS, #0" in <<
1116 subsequent speculative instructions <<
1117 speculative store bypassing. <<
1118 <<
1119 Work around this problem by placing <<
1120 Instruction Synchronization Barrier <<
1121 SSBS. The presence of the SSBS spec <<
1122 from hwcaps and EL0 reads of ID_AA6 <<
1123 will use the PR_SPEC_STORE_BYPASS p <<
1124 1947
1125 If unsure, say Y. !! 1948 config CPU_MIPSR6
>> 1949 bool
>> 1950 default y if CPU_MIPS32_R6 || CPU_MIPS64_R6
>> 1951 select CPU_HAS_RIXI
>> 1952 select CPU_HAS_DIEI if !CPU_DIEI_BROKEN
>> 1953 select HAVE_ARCH_BITREVERSE
>> 1954 select MIPS_ASID_BITS_VARIABLE
>> 1955 select MIPS_CRC_SUPPORT
>> 1956 select MIPS_SPRAM
1126 1957
1127 config CAVIUM_ERRATUM_22375 !! 1958 config TARGET_ISA_REV
1128 bool "Cavium erratum 22375, 24313" !! 1959 int
1129 default y !! 1960 default 1 if CPU_MIPSR1
>> 1961 default 2 if CPU_MIPSR2
>> 1962 default 5 if CPU_MIPSR5
>> 1963 default 6 if CPU_MIPSR6
>> 1964 default 0
1130 help 1965 help
1131 Enable workaround for errata 22375 !! 1966 Reflects the ISA revision being targeted by the kernel build. This
>> 1967 is effectively the Kconfig equivalent of MIPS_ISA_REV.
1132 1968
1133 This implements two gicv3-its errat !! 1969 config EVA
1134 with a small impact affecting only !! 1970 bool
1135 1971
1136 erratum 22375: only alloc 8MB tab !! 1972 config XPA
1137 erratum 24313: ignore memory acce !! 1973 bool
1138 1974
1139 The fixes are in ITS initialization !! 1975 config SYS_SUPPORTS_32BIT_KERNEL
1140 type and table size provided by the !! 1976 bool
>> 1977 config SYS_SUPPORTS_64BIT_KERNEL
>> 1978 bool
>> 1979 config CPU_SUPPORTS_32BIT_KERNEL
>> 1980 bool
>> 1981 config CPU_SUPPORTS_64BIT_KERNEL
>> 1982 bool
>> 1983 config CPU_SUPPORTS_CPUFREQ
>> 1984 bool
>> 1985 config CPU_SUPPORTS_ADDRWINCFG
>> 1986 bool
>> 1987 config CPU_SUPPORTS_HUGEPAGES
>> 1988 bool
>> 1989 depends on !(32BIT && (PHYS_ADDR_T_64BIT || EVA))
>> 1990 config MIPS_PGD_C0_CONTEXT
>> 1991 bool
>> 1992 depends on 64BIT
>> 1993 default y if (CPU_MIPSR2 || CPU_MIPSR6)
1141 1994
1142 If unsure, say Y. !! 1995 #
>> 1996 # Set to y for ptrace access to watch registers.
>> 1997 #
>> 1998 config HARDWARE_WATCHPOINTS
>> 1999 bool
>> 2000 default y if CPU_MIPSR1 || CPU_MIPSR2 || CPU_MIPSR6
1143 2001
1144 config CAVIUM_ERRATUM_23144 !! 2002 menu "Kernel type"
1145 bool "Cavium erratum 23144: ITS SYNC <<
1146 depends on NUMA <<
1147 default y <<
1148 help <<
1149 ITS SYNC command hang for cross nod <<
1150 2003
1151 If unsure, say Y. !! 2004 choice
>> 2005 prompt "Kernel code model"
>> 2006 help
>> 2007 You should only select this option if you have a workload that
>> 2008 actually benefits from 64-bit processing or if your machine has
>> 2009 large memory. You will only be presented a single option in this
>> 2010 menu if your system does not support both 32-bit and 64-bit kernels.
>> 2011
>> 2012 config 32BIT
>> 2013 bool "32-bit kernel"
>> 2014 depends on CPU_SUPPORTS_32BIT_KERNEL && SYS_SUPPORTS_32BIT_KERNEL
>> 2015 select TRAD_SIGNALS
>> 2016 help
>> 2017 Select this option if you want to build a 32-bit kernel.
1152 2018
1153 config CAVIUM_ERRATUM_23154 !! 2019 config 64BIT
1154 bool "Cavium errata 23154 and 38545: !! 2020 bool "64-bit kernel"
1155 default y !! 2021 depends on CPU_SUPPORTS_64BIT_KERNEL && SYS_SUPPORTS_64BIT_KERNEL
1156 help 2022 help
1157 The ThunderX GICv3 implementation r !! 2023 Select this option if you want to build a 64-bit kernel.
1158 reading the IAR status to ensure da <<
1159 (access to icc_iar1_el1 is not sync <<
1160 <<
1161 It also suffers from erratum 38545 <<
1162 OcteonTX and OcteonTX2), resulting <<
1163 spuriously presented to the CPU int <<
1164 2024
1165 If unsure, say Y. !! 2025 endchoice
1166 2026
1167 config CAVIUM_ERRATUM_27456 !! 2027 config MIPS_VA_BITS_48
1168 bool "Cavium erratum 27456: Broadcast !! 2028 bool "48 bits virtual memory"
1169 default y !! 2029 depends on 64BIT
1170 help !! 2030 help
1171 On ThunderX T88 pass 1.x through 2. !! 2031 Support a maximum at least 48 bits of application virtual
1172 instructions may cause the icache t !! 2032 memory. Default is 40 bits or less, depending on the CPU.
1173 contains data for a non-current ASI !! 2033 For page sizes 16k and above, this option results in a small
1174 invalidate the icache when changing !! 2034 memory overhead for page tables. For 4k page size, a fourth
>> 2035 level of page tables is added which imposes both a memory
>> 2036 overhead as well as slower TLB fault handling.
1175 2037
1176 If unsure, say Y. !! 2038 If unsure, say N.
1177 2039
1178 config CAVIUM_ERRATUM_30115 !! 2040 config ZBOOT_LOAD_ADDRESS
1179 bool "Cavium erratum 30115: Guest may !! 2041 hex "Compressed kernel load address"
1180 default y !! 2042 default 0xffffffff80400000 if BCM47XX
>> 2043 default 0x0
>> 2044 depends on SYS_SUPPORTS_ZBOOT
1181 help 2045 help
1182 On ThunderX T88 pass 1.x through 2. !! 2046 The address to load compressed kernel, aka vmlinuz.
1183 1.2, and T83 Pass 1.0, KVM guest ex <<
1184 interrupts in host. Trapping both G <<
1185 accesses sidesteps the issue. <<
1186 2047
1187 If unsure, say Y. !! 2048 This is only used if non-zero.
1188 2049
1189 config CAVIUM_TX2_ERRATUM_219 !! 2050 choice
1190 bool "Cavium ThunderX2 erratum 219: P !! 2051 prompt "Kernel page size"
1191 default y !! 2052 default PAGE_SIZE_4KB
1192 help <<
1193 On Cavium ThunderX2, a load, store <<
1194 TTBR update and the corresponding c <<
1195 cause a spurious Data Abort to be d <<
1196 the CPU core. <<
1197 <<
1198 Work around the issue by avoiding t <<
1199 trapping KVM guest TTBRx_EL1 writes <<
1200 trap handler performs the correspon <<
1201 instruction and ensures context syn <<
1202 exception return. <<
1203 2053
1204 If unsure, say Y. !! 2054 config PAGE_SIZE_4KB
>> 2055 bool "4kB"
>> 2056 depends on !CPU_LOONGSON2EF && !CPU_LOONGSON64
>> 2057 help
>> 2058 This option select the standard 4kB Linux page size. On some
>> 2059 R3000-family processors this is the only available page size. Using
>> 2060 4kB page size will minimize memory consumption and is therefore
>> 2061 recommended for low memory systems.
>> 2062
>> 2063 config PAGE_SIZE_8KB
>> 2064 bool "8kB"
>> 2065 depends on CPU_CAVIUM_OCTEON
>> 2066 depends on !MIPS_VA_BITS_48
>> 2067 help
>> 2068 Using 8kB page size will result in higher performance kernel at
>> 2069 the price of higher memory consumption. This option is available
>> 2070 only on cnMIPS processors. Note that you will need a suitable Linux
>> 2071 distribution to support this.
>> 2072
>> 2073 config PAGE_SIZE_16KB
>> 2074 bool "16kB"
>> 2075 depends on !CPU_R3000
>> 2076 help
>> 2077 Using 16kB page size will result in higher performance kernel at
>> 2078 the price of higher memory consumption. This option is available on
>> 2079 all non-R3000 family processors. Note that you will need a suitable
>> 2080 Linux distribution to support this.
>> 2081
>> 2082 config PAGE_SIZE_32KB
>> 2083 bool "32kB"
>> 2084 depends on CPU_CAVIUM_OCTEON
>> 2085 depends on !MIPS_VA_BITS_48
>> 2086 help
>> 2087 Using 32kB page size will result in higher performance kernel at
>> 2088 the price of higher memory consumption. This option is available
>> 2089 only on cnMIPS cores. Note that you will need a suitable Linux
>> 2090 distribution to support this.
>> 2091
>> 2092 config PAGE_SIZE_64KB
>> 2093 bool "64kB"
>> 2094 depends on !CPU_R3000
>> 2095 help
>> 2096 Using 64kB page size will result in higher performance kernel at
>> 2097 the price of higher memory consumption. This option is available on
>> 2098 all non-R3000 family processor. Not that at the time of this
>> 2099 writing this option is still high experimental.
1205 2100
1206 config FUJITSU_ERRATUM_010001 !! 2101 endchoice
1207 bool "Fujitsu-A64FX erratum E#010001: !! 2102
1208 default y !! 2103 config ARCH_FORCE_MAX_ORDER
>> 2104 int "Maximum zone order"
>> 2105 default "13" if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_64KB
>> 2106 default "12" if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_32KB
>> 2107 default "11" if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_16KB
>> 2108 default "10"
1209 help 2109 help
1210 This option adds a workaround for F !! 2110 The kernel memory allocator divides physically contiguous memory
1211 On some variants of the Fujitsu-A64 !! 2111 blocks into "zones", where each zone is a power of two number of
1212 accesses may cause undefined fault !! 2112 pages. This option selects the largest power of two that the kernel
1213 This fault occurs under a specific !! 2113 keeps in the memory allocator. If you need to allocate very large
1214 load/store instruction performs an !! 2114 blocks of physically contiguous memory, then you may need to
1215 case-1 TTBR0_EL1 with TCR_EL1.NFD0 !! 2115 increase this value.
1216 case-2 TTBR0_EL2 with TCR_EL2.NFD0 <<
1217 case-3 TTBR1_EL1 with TCR_EL1.NFD1 <<
1218 case-4 TTBR1_EL2 with TCR_EL2.NFD1 <<
1219 2116
1220 The workaround is to ensure these b !! 2117 The page size is not necessarily 4KB. Keep this in mind
1221 The workaround only affects the Fuj !! 2118 when choosing a value for this option.
1222 2119
1223 If unsure, say Y. !! 2120 config BOARD_SCACHE
>> 2121 bool
1224 2122
1225 config HISILICON_ERRATUM_161600802 !! 2123 config IP22_CPU_SCACHE
1226 bool "Hip07 161600802: Erroneous redi !! 2124 bool
1227 default y !! 2125 select BOARD_SCACHE
1228 help <<
1229 The HiSilicon Hip07 SoC uses the wr <<
1230 when issued ITS commands such as VM <<
1231 a 128kB offset to be applied to the <<
1232 2126
1233 If unsure, say Y. !! 2127 #
>> 2128 # Support for a MIPS32 / MIPS64 style S-caches
>> 2129 #
>> 2130 config MIPS_CPU_SCACHE
>> 2131 bool
>> 2132 select BOARD_SCACHE
1234 2133
1235 config QCOM_FALKOR_ERRATUM_1003 !! 2134 config R5000_CPU_SCACHE
1236 bool "Falkor E1003: Incorrect transla !! 2135 bool
1237 default y !! 2136 select BOARD_SCACHE
1238 help <<
1239 On Falkor v1, an incorrect ASID may <<
1240 and BADDR are changed together in T <<
1241 in TTBR1_EL1, this situation only o <<
1242 then only for entries in the walk c <<
1243 is unchanged. Work around the errat <<
1244 entries for the trampoline before e <<
1245 2137
1246 config QCOM_FALKOR_ERRATUM_1009 !! 2138 config RM7000_CPU_SCACHE
1247 bool "Falkor E1009: Prematurely compl !! 2139 bool
1248 default y !! 2140 select BOARD_SCACHE
1249 select ARM64_WORKAROUND_REPEAT_TLBI !! 2141
>> 2142 config SIBYTE_DMA_PAGEOPS
>> 2143 bool "Use DMA to clear/copy pages"
>> 2144 depends on CPU_SB1
1250 help 2145 help
1251 On Falkor v1, the CPU may premature !! 2146 Instead of using the CPU to zero and copy pages, use a Data Mover
1252 TLBI xxIS invalidate maintenance op !! 2147 channel. These DMA channels are otherwise unused by the standard
1253 one more time to fix the issue. !! 2148 SiByte Linux port. Seems to give a small performance benefit.
1254 2149
1255 If unsure, say Y. !! 2150 config CPU_HAS_PREFETCH
>> 2151 bool
1256 2152
1257 config QCOM_QDF2400_ERRATUM_0065 !! 2153 config CPU_GENERIC_DUMP_TLB
1258 bool "QDF2400 E0065: Incorrect GITS_T !! 2154 bool
>> 2155 default y if !CPU_R3000
>> 2156
>> 2157 config MIPS_FP_SUPPORT
>> 2158 bool "Floating Point support" if EXPERT
1259 default y 2159 default y
1260 help 2160 help
1261 On Qualcomm Datacenter Technologies !! 2161 Select y to include support for floating point in the kernel
1262 ITE size incorrectly. The GITS_TYPE !! 2162 including initialization of FPU hardware, FP context save & restore
1263 been indicated as 16Bytes (0xf), no !! 2163 and emulation of an FPU where necessary. Without this support any
>> 2164 userland program attempting to use floating point instructions will
>> 2165 receive a SIGILL.
1264 2166
1265 If unsure, say Y. !! 2167 If you know that your userland will not attempt to use floating point
>> 2168 instructions then you can say n here to shrink the kernel a little.
1266 2169
1267 config QCOM_FALKOR_ERRATUM_E1041 !! 2170 If unsure, say y.
1268 bool "Falkor E1041: Speculative instr <<
1269 default y <<
1270 help <<
1271 Falkor CPU may speculatively fetch <<
1272 memory location when MMU translatio <<
1273 to SCTLR_ELn[M]=0. Prefix an ISB in <<
1274 2171
1275 If unsure, say Y. !! 2172 config CPU_R2300_FPU
>> 2173 bool
>> 2174 depends on MIPS_FP_SUPPORT
>> 2175 default y if CPU_R3000
1276 2176
1277 config NVIDIA_CARMEL_CNP_ERRATUM !! 2177 config CPU_R3K_TLB
1278 bool "NVIDIA Carmel CNP: CNP on Carme !! 2178 bool
1279 default y <<
1280 help <<
1281 If CNP is enabled on Carmel cores, <<
1282 invalidate shared TLB entries insta <<
1283 on standard ARM cores. <<
1284 2179
1285 If unsure, say Y. !! 2180 config CPU_R4K_FPU
>> 2181 bool
>> 2182 depends on MIPS_FP_SUPPORT
>> 2183 default y if !CPU_R2300_FPU
1286 2184
1287 config ROCKCHIP_ERRATUM_3588001 !! 2185 config CPU_R4K_CACHE_TLB
1288 bool "Rockchip 3588001: GIC600 can no !! 2186 bool
>> 2187 default y if !(CPU_R3K_TLB || CPU_SB1 || CPU_CAVIUM_OCTEON)
>> 2188
>> 2189 config MIPS_MT_SMP
>> 2190 bool "MIPS MT SMP support (1 TC on each available VPE)"
1289 default y 2191 default y
1290 help !! 2192 depends on SYS_SUPPORTS_MULTITHREADING && !CPU_MIPSR6 && !CPU_MICROMIPS
1291 The Rockchip RK3588 GIC600 SoC inte !! 2193 select CPU_MIPSR2_IRQ_VI
1292 This means, that its sharability fe !! 2194 select CPU_MIPSR2_IRQ_EI
1293 is supported by the IP itself. !! 2195 select SYNC_R4K
>> 2196 select MIPS_MT
>> 2197 select SMP
>> 2198 select SMP_UP
>> 2199 select SYS_SUPPORTS_SMP
>> 2200 select SYS_SUPPORTS_SCHED_SMT
>> 2201 select MIPS_PERF_SHARED_TC_COUNTERS
>> 2202 help
>> 2203 This is a kernel model which is known as SMVP. This is supported
>> 2204 on cores with the MT ASE and uses the available VPEs to implement
>> 2205 virtual processors which supports SMP. This is equivalent to the
>> 2206 Intel Hyperthreading feature. For further information go to
>> 2207 <http://www.imgtec.com/mips/mips-multithreading.asp>.
1294 2208
1295 If unsure, say Y. !! 2209 config MIPS_MT
>> 2210 bool
1296 2211
1297 config SOCIONEXT_SYNQUACER_PREITS !! 2212 config SCHED_SMT
1298 bool "Socionext Synquacer: Workaround !! 2213 bool "SMT (multithreading) scheduler support"
1299 default y !! 2214 depends on SYS_SUPPORTS_SCHED_SMT
>> 2215 default n
1300 help 2216 help
1301 Socionext Synquacer SoCs implement !! 2217 SMT scheduler support improves the CPU scheduler's decision making
1302 MSI doorbell writes with non-zero v !! 2218 when dealing with MIPS MT enabled cores at a cost of slightly
>> 2219 increased overhead in some places. If unsure say N here.
1303 2220
1304 If unsure, say Y. !! 2221 config SYS_SUPPORTS_SCHED_SMT
>> 2222 bool
1305 2223
1306 endmenu # "ARM errata workarounds via the alt !! 2224 config SYS_SUPPORTS_MULTITHREADING
>> 2225 bool
1307 2226
1308 choice !! 2227 config MIPS_MT_FPAFF
1309 prompt "Page size" !! 2228 bool "Dynamic FPU affinity for FP-intensive threads"
1310 default ARM64_4K_PAGES !! 2229 default y
1311 help !! 2230 depends on MIPS_MT_SMP
1312 Page size (translation granule) con <<
1313 2231
1314 config ARM64_4K_PAGES !! 2232 config MIPSR2_TO_R6_EMULATOR
1315 bool "4KB" !! 2233 bool "MIPS R2-to-R6 emulator"
1316 select HAVE_PAGE_SIZE_4KB !! 2234 depends on CPU_MIPSR6
>> 2235 depends on MIPS_FP_SUPPORT
>> 2236 default y
1317 help 2237 help
1318 This feature enables 4KB pages supp !! 2238 Choose this option if you want to run non-R6 MIPS userland code.
>> 2239 Even if you say 'Y' here, the emulator will still be disabled by
>> 2240 default. You can enable it using the 'mipsr2emu' kernel option.
>> 2241 The only reason this is a build-time option is to save ~14K from the
>> 2242 final kernel image.
1319 2243
1320 config ARM64_16K_PAGES !! 2244 config SYS_SUPPORTS_VPE_LOADER
1321 bool "16KB" !! 2245 bool
1322 select HAVE_PAGE_SIZE_16KB !! 2246 depends on SYS_SUPPORTS_MULTITHREADING
1323 help 2247 help
1324 The system will use 16KB pages supp !! 2248 Indicates that the platform supports the VPE loader, and provides
1325 requires applications compiled with !! 2249 physical_memsize.
1326 aligned segments. <<
1327 2250
1328 config ARM64_64K_PAGES !! 2251 config MIPS_VPE_LOADER
1329 bool "64KB" !! 2252 bool "VPE loader support."
1330 select HAVE_PAGE_SIZE_64KB !! 2253 depends on SYS_SUPPORTS_VPE_LOADER && MODULES
>> 2254 select CPU_MIPSR2_IRQ_VI
>> 2255 select CPU_MIPSR2_IRQ_EI
>> 2256 select MIPS_MT
1331 help 2257 help
1332 This feature enables 64KB pages sup !! 2258 Includes a loader for loading an elf relocatable object
1333 allowing only two levels of page ta !! 2259 onto another VPE and running it.
1334 look-up. AArch32 emulation requires <<
1335 with 64K aligned segments. <<
1336 2260
1337 endchoice !! 2261 config MIPS_VPE_LOADER_MT
>> 2262 bool
>> 2263 default "y"
>> 2264 depends on MIPS_VPE_LOADER
1338 2265
1339 choice !! 2266 config MIPS_VPE_LOADER_TOM
1340 prompt "Virtual address space size" !! 2267 bool "Load VPE program into memory hidden from linux"
1341 default ARM64_VA_BITS_52 !! 2268 depends on MIPS_VPE_LOADER
>> 2269 default y
1342 help 2270 help
1343 Allows choosing one of multiple pos !! 2271 The loader can use memory that is present but has been hidden from
1344 space sizes. The level of translati !! 2272 Linux using the kernel command line option "mem=xxMB". It's up to
1345 a combination of page size and virt !! 2273 you to ensure the amount you put in the option and the space your
1346 !! 2274 program requires is less or equal to the amount physically present.
1347 config ARM64_VA_BITS_36 <<
1348 bool "36-bit" if EXPERT <<
1349 depends on PAGE_SIZE_16KB <<
1350 <<
1351 config ARM64_VA_BITS_39 <<
1352 bool "39-bit" <<
1353 depends on PAGE_SIZE_4KB <<
1354 <<
1355 config ARM64_VA_BITS_42 <<
1356 bool "42-bit" <<
1357 depends on PAGE_SIZE_64KB <<
1358 <<
1359 config ARM64_VA_BITS_47 <<
1360 bool "47-bit" <<
1361 depends on PAGE_SIZE_16KB <<
1362 <<
1363 config ARM64_VA_BITS_48 <<
1364 bool "48-bit" <<
1365 <<
1366 config ARM64_VA_BITS_52 <<
1367 bool "52-bit" <<
1368 depends on ARM64_PAN || !ARM64_SW_TTB <<
1369 help <<
1370 Enable 52-bit virtual addressing fo <<
1371 requested via a hint to mmap(). The <<
1372 virtual addresses for its own mappi <<
1373 this feature is available, otherwis <<
1374 <<
1375 NOTE: Enabling 52-bit virtual addre <<
1376 ARMv8.3 Pointer Authentication will <<
1377 reduced from 7 bits to 3 bits, whic <<
1378 impact on its susceptibility to bru <<
1379 <<
1380 If unsure, select 48-bit virtual ad <<
1381 2275
1382 endchoice !! 2276 config MIPS_VPE_APSP_API
>> 2277 bool "Enable support for AP/SP API (RTLX)"
>> 2278 depends on MIPS_VPE_LOADER
1383 2279
1384 config ARM64_FORCE_52BIT !! 2280 config MIPS_VPE_APSP_API_MT
1385 bool "Force 52-bit virtual addresses !! 2281 bool
1386 depends on ARM64_VA_BITS_52 && EXPERT !! 2282 default "y"
1387 help !! 2283 depends on MIPS_VPE_APSP_API
1388 For systems with 52-bit userspace V <<
1389 to maintain compatibility with olde <<
1390 unless a hint is supplied to mmap. <<
1391 <<
1392 This configuration option disables <<
1393 forces all userspace addresses to b <<
1394 should only enable this configurati <<
1395 memory management code. If unsure s <<
1396 2284
1397 config ARM64_VA_BITS !! 2285 config MIPS_CPS
1398 int !! 2286 bool "MIPS Coherent Processing System support"
1399 default 36 if ARM64_VA_BITS_36 !! 2287 depends on SYS_SUPPORTS_MIPS_CPS
1400 default 39 if ARM64_VA_BITS_39 !! 2288 select MIPS_CM
1401 default 42 if ARM64_VA_BITS_42 !! 2289 select MIPS_CPS_PM if HOTPLUG_CPU
1402 default 47 if ARM64_VA_BITS_47 !! 2290 select SMP
1403 default 48 if ARM64_VA_BITS_48 !! 2291 select SYNC_R4K if (CEVT_R4K || CSRC_R4K)
1404 default 52 if ARM64_VA_BITS_52 !! 2292 select SYS_SUPPORTS_HOTPLUG_CPU
>> 2293 select SYS_SUPPORTS_SCHED_SMT if CPU_MIPSR6
>> 2294 select SYS_SUPPORTS_SMP
>> 2295 select WEAK_ORDERING
>> 2296 select GENERIC_IRQ_MIGRATION if HOTPLUG_CPU
>> 2297 help
>> 2298 Select this if you wish to run an SMP kernel across multiple cores
>> 2299 within a MIPS Coherent Processing System. When this option is
>> 2300 enabled the kernel will probe for other cores and boot them with
>> 2301 no external assistance. It is safe to enable this when hardware
>> 2302 support is unavailable.
1405 2303
1406 choice !! 2304 config MIPS_CPS_PM
1407 prompt "Physical address space size" !! 2305 depends on MIPS_CPS
1408 default ARM64_PA_BITS_48 !! 2306 bool
1409 help <<
1410 Choose the maximum physical address <<
1411 support. <<
1412 2307
1413 config ARM64_PA_BITS_48 !! 2308 config MIPS_CM
1414 bool "48-bit" !! 2309 bool
1415 depends on ARM64_64K_PAGES || !ARM64_ !! 2310 select MIPS_CPC
1416 <<
1417 config ARM64_PA_BITS_52 <<
1418 bool "52-bit" <<
1419 depends on ARM64_64K_PAGES || ARM64_V <<
1420 depends on ARM64_PAN || !ARM64_SW_TTB <<
1421 help <<
1422 Enable support for a 52-bit physica <<
1423 part of the ARMv8.2-LPA extension. <<
1424 <<
1425 With this enabled, the kernel will <<
1426 do not support ARMv8.2-LPA, but wit <<
1427 minor performance overhead). <<
1428 2311
1429 endchoice !! 2312 config MIPS_CPC
>> 2313 bool
1430 2314
1431 config ARM64_PA_BITS !! 2315 config SB1_PASS_2_WORKAROUNDS
1432 int !! 2316 bool
1433 default 48 if ARM64_PA_BITS_48 !! 2317 depends on CPU_SB1 && (CPU_SB1_PASS_2_2 || CPU_SB1_PASS_2)
1434 default 52 if ARM64_PA_BITS_52 !! 2318 default y
1435 2319
1436 config ARM64_LPA2 !! 2320 config SB1_PASS_2_1_WORKAROUNDS
1437 def_bool y !! 2321 bool
1438 depends on ARM64_PA_BITS_52 && !ARM64 !! 2322 depends on CPU_SB1 && CPU_SB1_PASS_2
>> 2323 default y
1439 2324
1440 choice 2325 choice
1441 prompt "Endianness" !! 2326 prompt "SmartMIPS or microMIPS ASE support"
1442 default CPU_LITTLE_ENDIAN <<
1443 help <<
1444 Select the endianness of data acces <<
1445 applications will need to be compil <<
1446 that is selected here. <<
1447 2327
1448 config CPU_BIG_ENDIAN !! 2328 config CPU_NEEDS_NO_SMARTMIPS_OR_MICROMIPS
1449 bool "Build big-endian kernel" !! 2329 bool "None"
1450 # https://github.com/llvm/llvm-projec <<
1451 depends on AS_IS_GNU || AS_VERSION >= <<
1452 help 2330 help
1453 Say Y if you plan on running a kern !! 2331 Select this if you want neither microMIPS nor SmartMIPS support
1454 2332
1455 config CPU_LITTLE_ENDIAN !! 2333 config CPU_HAS_SMARTMIPS
1456 bool "Build little-endian kernel" !! 2334 depends on SYS_SUPPORTS_SMARTMIPS
>> 2335 bool "SmartMIPS"
>> 2336 help
>> 2337 SmartMIPS is a extension of the MIPS32 architecture aimed at
>> 2338 increased security at both hardware and software level for
>> 2339 smartcards. Enabling this option will allow proper use of the
>> 2340 SmartMIPS instructions by Linux applications. However a kernel with
>> 2341 this option will not work on a MIPS core without SmartMIPS core. If
>> 2342 you don't know you probably don't have SmartMIPS and should say N
>> 2343 here.
>> 2344
>> 2345 config CPU_MICROMIPS
>> 2346 depends on 32BIT && SYS_SUPPORTS_MICROMIPS && !CPU_MIPSR6
>> 2347 bool "microMIPS"
1457 help 2348 help
1458 Say Y if you plan on running a kern !! 2349 When this option is enabled the kernel will be built using the
1459 This is usually the case for distri !! 2350 microMIPS ISA
1460 2351
1461 endchoice 2352 endchoice
1462 2353
1463 config SCHED_MC !! 2354 config CPU_HAS_MSA
1464 bool "Multi-core scheduler support" !! 2355 bool "Support for the MIPS SIMD Architecture"
1465 help !! 2356 depends on CPU_SUPPORTS_MSA
1466 Multi-core scheduler support improv !! 2357 depends on MIPS_FP_SUPPORT
1467 making when dealing with multi-core !! 2358 depends on 64BIT || MIPS_O32_FP64_SUPPORT
1468 increased overhead in some places. !! 2359 help
>> 2360 MIPS SIMD Architecture (MSA) introduces 128 bit wide vector registers
>> 2361 and a set of SIMD instructions to operate on them. When this option
>> 2362 is enabled the kernel will support allocating & switching MSA
>> 2363 vector register contexts. If you know that your kernel will only be
>> 2364 running on CPUs which do not support MSA or that your userland will
>> 2365 not be making use of it then you may wish to say N here to reduce
>> 2366 the size & complexity of your kernel.
1469 2367
1470 config SCHED_CLUSTER !! 2368 If unsure, say Y.
1471 bool "Cluster scheduler support" <<
1472 help <<
1473 Cluster scheduler support improves <<
1474 making when dealing with machines t <<
1475 Cluster usually means a couple of C <<
1476 by sharing mid-level caches, last-l <<
1477 busses. <<
1478 2369
1479 config SCHED_SMT !! 2370 config CPU_HAS_WB
1480 bool "SMT scheduler support" !! 2371 bool
1481 help <<
1482 Improves the CPU scheduler's decisi <<
1483 MultiThreading at a cost of slightl <<
1484 places. If unsure say N here. <<
1485 2372
1486 config NR_CPUS !! 2373 config XKS01
1487 int "Maximum number of CPUs (2-4096)" !! 2374 bool
1488 range 2 4096 <<
1489 default "512" <<
1490 2375
1491 config HOTPLUG_CPU !! 2376 config CPU_HAS_DIEI
1492 bool "Support for hot-pluggable CPUs" !! 2377 depends on !CPU_DIEI_BROKEN
1493 select GENERIC_IRQ_MIGRATION !! 2378 bool
1494 help <<
1495 Say Y here to experiment with turni <<
1496 can be controlled through /sys/devi <<
1497 2379
1498 # Common NUMA Features !! 2380 config CPU_DIEI_BROKEN
1499 config NUMA !! 2381 bool
1500 bool "NUMA Memory Allocation and Sche <<
1501 select GENERIC_ARCH_NUMA <<
1502 select OF_NUMA <<
1503 select HAVE_SETUP_PER_CPU_AREA <<
1504 select NEED_PER_CPU_EMBED_FIRST_CHUNK <<
1505 select NEED_PER_CPU_PAGE_FIRST_CHUNK <<
1506 select USE_PERCPU_NUMA_NODE_ID <<
1507 help <<
1508 Enable NUMA (Non-Uniform Memory Acc <<
1509 2382
1510 The kernel will try to allocate mem !! 2383 config CPU_HAS_RIXI
1511 local memory of the CPU and add som !! 2384 bool
1512 NUMA awareness to the kernel. <<
1513 2385
1514 config NODES_SHIFT !! 2386 config CPU_NO_LOAD_STORE_LR
1515 int "Maximum NUMA Nodes (as a power o !! 2387 bool
1516 range 1 10 <<
1517 default "4" <<
1518 depends on NUMA <<
1519 help 2388 help
1520 Specify the maximum number of NUMA !! 2389 CPU lacks support for unaligned load and store instructions:
1521 system. Increases memory reserved !! 2390 LWL, LWR, SWL, SWR (Load/store word left/right).
>> 2391 LDL, LDR, SDL, SDR (Load/store doubleword left/right, for 64bit
>> 2392 systems).
1522 2393
1523 source "kernel/Kconfig.hz" !! 2394 #
>> 2395 # Vectored interrupt mode is an R2 feature
>> 2396 #
>> 2397 config CPU_MIPSR2_IRQ_VI
>> 2398 bool
1524 2399
1525 config ARCH_SPARSEMEM_ENABLE !! 2400 #
1526 def_bool y !! 2401 # Extended interrupt mode is an R2 feature
1527 select SPARSEMEM_VMEMMAP_ENABLE !! 2402 #
1528 select SPARSEMEM_VMEMMAP !! 2403 config CPU_MIPSR2_IRQ_EI
>> 2404 bool
1529 2405
1530 config HW_PERF_EVENTS !! 2406 config CPU_HAS_SYNC
1531 def_bool y !! 2407 bool
1532 depends on ARM_PMU !! 2408 depends on !CPU_R3000
>> 2409 default y
1533 2410
1534 # Supported by clang >= 7.0 or GCC >= 12.0.0 !! 2411 #
1535 config CC_HAVE_SHADOW_CALL_STACK !! 2412 # CPU non-features
1536 def_bool $(cc-option, -fsanitize=shad !! 2413 #
1537 2414
1538 config PARAVIRT !! 2415 # Work around the "daddi" and "daddiu" CPU errata:
1539 bool "Enable paravirtualization code" !! 2416 #
1540 help !! 2417 # - The `daddi' instruction fails to trap on overflow.
1541 This changes the kernel so it can m !! 2418 # "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0",
1542 under a hypervisor, potentially imp !! 2419 # erratum #23
1543 over full virtualization. !! 2420 #
>> 2421 # - The `daddiu' instruction can produce an incorrect result.
>> 2422 # "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0",
>> 2423 # erratum #41
>> 2424 # "MIPS R4000MC Errata, Processor Revision 2.2 and 3.0", erratum
>> 2425 # #15
>> 2426 # "MIPS R4400PC/SC Errata, Processor Revision 1.0", erratum #7
>> 2427 # "MIPS R4400MC Errata, Processor Revision 1.0", erratum #5
>> 2428 config CPU_DADDI_WORKAROUNDS
>> 2429 bool
1544 2430
1545 config PARAVIRT_TIME_ACCOUNTING !! 2431 # Work around certain R4000 CPU errata (as implemented by GCC):
1546 bool "Paravirtual steal time accounti !! 2432 #
1547 select PARAVIRT !! 2433 # - A double-word or a variable shift may give an incorrect result
1548 help !! 2434 # if executed immediately after starting an integer division:
1549 Select this option to enable fine g !! 2435 # "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0",
1550 accounting. Time spent executing ot !! 2436 # erratum #28
1551 the current vCPU is discounted from !! 2437 # "MIPS R4000MC Errata, Processor Revision 2.2 and 3.0", erratum
1552 that, there can be a small performa !! 2438 # #19
>> 2439 #
>> 2440 # - A double-word or a variable shift may give an incorrect result
>> 2441 # if executed while an integer multiplication is in progress:
>> 2442 # "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0",
>> 2443 # errata #16 & #28
>> 2444 #
>> 2445 # - An integer division may give an incorrect result if started in
>> 2446 # a delay slot of a taken branch or a jump:
>> 2447 # "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0",
>> 2448 # erratum #52
>> 2449 config CPU_R4000_WORKAROUNDS
>> 2450 bool
>> 2451 select CPU_R4400_WORKAROUNDS
1553 2452
1554 If in doubt, say N here. !! 2453 # Work around certain R4400 CPU errata (as implemented by GCC):
>> 2454 #
>> 2455 # - A double-word or a variable shift may give an incorrect result
>> 2456 # if executed immediately after starting an integer division:
>> 2457 # "MIPS R4400MC Errata, Processor Revision 1.0", erratum #10
>> 2458 # "MIPS R4400MC Errata, Processor Revision 2.0 & 3.0", erratum #4
>> 2459 config CPU_R4400_WORKAROUNDS
>> 2460 bool
1555 2461
1556 config ARCH_SUPPORTS_KEXEC !! 2462 config CPU_R4X00_BUGS64
1557 def_bool PM_SLEEP_SMP !! 2463 bool
>> 2464 default y if SYS_HAS_CPU_R4X00 && 64BIT && (TARGET_ISA_REV < 1)
1558 2465
1559 config ARCH_SUPPORTS_KEXEC_FILE !! 2466 config MIPS_ASID_SHIFT
1560 def_bool y !! 2467 int
>> 2468 default 6 if CPU_R3000
>> 2469 default 0
1561 2470
1562 config ARCH_SELECTS_KEXEC_FILE !! 2471 config MIPS_ASID_BITS
1563 def_bool y !! 2472 int
1564 depends on KEXEC_FILE !! 2473 default 0 if MIPS_ASID_BITS_VARIABLE
1565 select HAVE_IMA_KEXEC if IMA !! 2474 default 6 if CPU_R3000
>> 2475 default 8
1566 2476
1567 config ARCH_SUPPORTS_KEXEC_SIG !! 2477 config MIPS_ASID_BITS_VARIABLE
1568 def_bool y !! 2478 bool
1569 2479
1570 config ARCH_SUPPORTS_KEXEC_IMAGE_VERIFY_SIG !! 2480 config MIPS_CRC_SUPPORT
1571 def_bool y !! 2481 bool
1572 2482
1573 config ARCH_DEFAULT_KEXEC_IMAGE_VERIFY_SIG !! 2483 # R4600 erratum. Due to the lack of errata information the exact
1574 def_bool y !! 2484 # technical details aren't known. I've experimentally found that disabling
>> 2485 # interrupts during indexed I-cache flushes seems to be sufficient to deal
>> 2486 # with the issue.
>> 2487 config WAR_R4600_V1_INDEX_ICACHEOP
>> 2488 bool
1575 2489
1576 config ARCH_SUPPORTS_CRASH_DUMP !! 2490 # Pleasures of the R4600 V1.x. Cite from the IDT R4600 V1.7 errata:
1577 def_bool y !! 2491 #
>> 2492 # 18. The CACHE instructions Hit_Writeback_Invalidate_D, Hit_Writeback_D,
>> 2493 # Hit_Invalidate_D and Create_Dirty_Excl_D should only be
>> 2494 # executed if there is no other dcache activity. If the dcache is
>> 2495 # accessed for another instruction immediately preceding when these
>> 2496 # cache instructions are executing, it is possible that the dcache
>> 2497 # tag match outputs used by these cache instructions will be
>> 2498 # incorrect. These cache instructions should be preceded by at least
>> 2499 # four instructions that are not any kind of load or store
>> 2500 # instruction.
>> 2501 #
>> 2502 # This is not allowed: lw
>> 2503 # nop
>> 2504 # nop
>> 2505 # nop
>> 2506 # cache Hit_Writeback_Invalidate_D
>> 2507 #
>> 2508 # This is allowed: lw
>> 2509 # nop
>> 2510 # nop
>> 2511 # nop
>> 2512 # nop
>> 2513 # cache Hit_Writeback_Invalidate_D
>> 2514 config WAR_R4600_V1_HIT_CACHEOP
>> 2515 bool
1578 2516
1579 config ARCH_HAS_GENERIC_CRASHKERNEL_RESERVATI !! 2517 # Writeback and invalidate the primary cache dcache before DMA.
1580 def_bool CRASH_RESERVE !! 2518 #
>> 2519 # R4600 v2.0 bug: "The CACHE instructions Hit_Writeback_Inv_D,
>> 2520 # Hit_Writeback_D, Hit_Invalidate_D and Create_Dirty_Exclusive_D will only
>> 2521 # operate correctly if the internal data cache refill buffer is empty. These
>> 2522 # CACHE instructions should be separated from any potential data cache miss
>> 2523 # by a load instruction to an uncached address to empty the response buffer."
>> 2524 # (Revision 2.0 device errata from IDT available on https://www.idt.com/
>> 2525 # in .pdf format.)
>> 2526 config WAR_R4600_V2_HIT_CACHEOP
>> 2527 bool
1581 2528
1582 config TRANS_TABLE !! 2529 # From TX49/H2 manual: "If the instruction (i.e. CACHE) is issued for
1583 def_bool y !! 2530 # the line which this instruction itself exists, the following
1584 depends on HIBERNATION || KEXEC_CORE !! 2531 # operation is not guaranteed."
>> 2532 #
>> 2533 # Workaround: do two phase flushing for Index_Invalidate_I
>> 2534 config WAR_TX49XX_ICACHE_INDEX_INV
>> 2535 bool
1585 2536
1586 config XEN_DOM0 !! 2537 # The RM7000 processors and the E9000 cores have a bug (though PMC-Sierra
1587 def_bool y !! 2538 # opposes it being called that) where invalid instructions in the same
1588 depends on XEN !! 2539 # I-cache line worth of instructions being fetched may case spurious
>> 2540 # exceptions.
>> 2541 config WAR_ICACHE_REFILLS
>> 2542 bool
1589 2543
1590 config XEN !! 2544 # On the R10000 up to version 2.6 (not sure about 2.7) there is a bug that
1591 bool "Xen guest support on ARM64" !! 2545 # may cause ll / sc and lld / scd sequences to execute non-atomically.
1592 depends on ARM64 && OF !! 2546 config WAR_R10000_LLSC
1593 select SWIOTLB_XEN !! 2547 bool
1594 select PARAVIRT !! 2548
1595 help !! 2549 # 34K core erratum: "Problems Executing the TLBR Instruction"
1596 Say Y if you want to run Linux in a !! 2550 config WAR_MIPS34K_MISSED_ITLB
>> 2551 bool
1597 2552
1598 # include/linux/mmzone.h requires the followi <<
1599 # <<
1600 # MAX_PAGE_ORDER + PAGE_SHIFT <= SECTION_SI <<
1601 # 2553 #
1602 # so the maximum value of MAX_PAGE_ORDER is S !! 2554 # - Highmem only makes sense for the 32-bit kernel.
>> 2555 # - The current highmem code will only work properly on physically indexed
>> 2556 # caches such as R3000, SB1, R7000 or those that look like they're virtually
>> 2557 # indexed such as R4000/R4400 SC and MC versions or R10000. So for the
>> 2558 # moment we protect the user and offer the highmem option only on machines
>> 2559 # where it's known to be safe. This will not offer highmem on a few systems
>> 2560 # such as MIPS32 and MIPS64 CPUs which may have virtual and physically
>> 2561 # indexed CPUs but we're playing safe.
>> 2562 # - We use SYS_SUPPORTS_HIGHMEM to offer highmem only for systems where we
>> 2563 # know they might have memory configurations that could make use of highmem
>> 2564 # support.
1603 # 2565 #
1604 # | SECTION_SIZE_BITS | PAGE_SHIFT | m !! 2566 config HIGHMEM
1605 # ----+-------------------+--------------+--- !! 2567 bool "High Memory Support"
1606 # 4K | 27 | 12 | !! 2568 depends on 32BIT && CPU_SUPPORTS_HIGHMEM && SYS_SUPPORTS_HIGHMEM && !CPU_MIPS32_3_5_EVA
1607 # 16K | 27 | 14 | !! 2569 select KMAP_LOCAL
1608 # 64K | 29 | 16 | <<
1609 config ARCH_FORCE_MAX_ORDER <<
1610 int <<
1611 default "13" if ARM64_64K_PAGES <<
1612 default "11" if ARM64_16K_PAGES <<
1613 default "10" <<
1614 help <<
1615 The kernel page allocator limits th <<
1616 contiguous allocations. The limit i <<
1617 defines the maximal power of two of <<
1618 allocated as a single contiguous bl <<
1619 overriding the default setting when <<
1620 large blocks of physically contiguo <<
1621 <<
1622 The maximal size of allocation cann <<
1623 section, so the value of MAX_PAGE_O <<
1624 <<
1625 MAX_PAGE_ORDER + PAGE_SHIFT <= SE <<
1626 2570
1627 Don't change if unsure. !! 2571 config CPU_SUPPORTS_HIGHMEM
>> 2572 bool
1628 2573
1629 config UNMAP_KERNEL_AT_EL0 !! 2574 config SYS_SUPPORTS_HIGHMEM
1630 bool "Unmap kernel when running in us !! 2575 bool
1631 default y <<
1632 help <<
1633 Speculation attacks against some hi <<
1634 be used to bypass MMU permission ch <<
1635 userspace. This can be defended aga <<
1636 when running in userspace, mapping <<
1637 via a trampoline page in the vector <<
1638 2576
1639 If unsure, say Y. !! 2577 config SYS_SUPPORTS_SMARTMIPS
>> 2578 bool
1640 2579
1641 config MITIGATE_SPECTRE_BRANCH_HISTORY !! 2580 config SYS_SUPPORTS_MICROMIPS
1642 bool "Mitigate Spectre style attacks !! 2581 bool
1643 default y <<
1644 help <<
1645 Speculation attacks against some hi <<
1646 make use of branch history to influ <<
1647 When taking an exception from user- <<
1648 or a firmware call overwrites the b <<
1649 2582
1650 config RODATA_FULL_DEFAULT_ENABLED !! 2583 config SYS_SUPPORTS_MIPS16
1651 bool "Apply r/o permissions of VM are !! 2584 bool
1652 default y <<
1653 help 2585 help
1654 Apply read-only attributes of VM ar !! 2586 This option must be set if a kernel might be executed on a MIPS16-
1655 the backing pages as well. This pre !! 2587 enabled CPU even if MIPS16 is not actually being used. In other
1656 from being modified (inadvertently !! 2588 words, it makes the kernel MIPS16-tolerant.
1657 mapping of the same memory page. Th <<
1658 be turned off at runtime by passing <<
1659 with rodata=full if this option is <<
1660 <<
1661 This requires the linear region to <<
1662 which may adversely affect performa <<
1663 <<
1664 config ARM64_SW_TTBR0_PAN <<
1665 bool "Emulate Privileged Access Never <<
1666 depends on !KCSAN <<
1667 help <<
1668 Enabling this option prevents the k <<
1669 user-space memory directly by point <<
1670 zeroed area and reserved ASID. The <<
1671 restore the valid TTBR0_EL1 tempora <<
1672 2589
1673 config ARM64_TAGGED_ADDR_ABI !! 2590 config CPU_SUPPORTS_MSA
1674 bool "Enable the tagged user addresse !! 2591 bool
1675 default y <<
1676 help <<
1677 When this option is enabled, user a <<
1678 relaxed ABI via prctl() allowing ta <<
1679 to system calls as pointer argument <<
1680 Documentation/arch/arm64/tagged-add <<
1681 <<
1682 menuconfig COMPAT <<
1683 bool "Kernel support for 32-bit EL0" <<
1684 depends on ARM64_4K_PAGES || EXPERT <<
1685 select HAVE_UID16 <<
1686 select OLD_SIGSUSPEND3 <<
1687 select COMPAT_OLD_SIGACTION <<
1688 help <<
1689 This option enables support for a 3 <<
1690 kernel at EL1. AArch32-specific com <<
1691 the user helper functions, VFP supp <<
1692 handled appropriately by the kernel <<
1693 <<
1694 If you use a page size other than 4 <<
1695 that you will only be able to execu <<
1696 with page size aligned segments. <<
1697 2592
1698 If you want to execute 32-bit users !! 2593 config ARCH_FLATMEM_ENABLE
>> 2594 def_bool y
>> 2595 depends on !NUMA && !CPU_LOONGSON2EF
1699 2596
1700 if COMPAT !! 2597 config ARCH_SPARSEMEM_ENABLE
>> 2598 bool
1701 2599
1702 config KUSER_HELPERS !! 2600 config NUMA
1703 bool "Enable kuser helpers page for 3 !! 2601 bool "NUMA Support"
1704 default y !! 2602 depends on SYS_SUPPORTS_NUMA
>> 2603 select SMP
>> 2604 select HAVE_SETUP_PER_CPU_AREA
>> 2605 select NEED_PER_CPU_EMBED_FIRST_CHUNK
1705 help 2606 help
1706 Warning: disabling this option may !! 2607 Say Y to compile the kernel to support NUMA (Non-Uniform Memory
>> 2608 Access). This option improves performance on systems with more
>> 2609 than two nodes; on two node systems it is generally better to
>> 2610 leave it disabled; on single node systems leave this option
>> 2611 disabled.
1707 2612
1708 Provide kuser helpers to compat tas !! 2613 config SYS_SUPPORTS_NUMA
1709 helper code to userspace in read on !! 2614 bool
1710 to allow userspace to be independen <<
1711 the system. This permits binaries t <<
1712 to ARMv8 without modification. <<
1713 <<
1714 See Documentation/arch/arm/kernel_u <<
1715 <<
1716 However, the fixed address nature o <<
1717 by ROP (return orientated programmi <<
1718 exploits. <<
1719 <<
1720 If all of the binaries and librarie <<
1721 are built specifically for your pla <<
1722 these helpers, then you can turn th <<
1723 such exploits. However, in that cas <<
1724 relying on those helpers is run, it <<
1725 <<
1726 Say N here only if you are absolute <<
1727 need these helpers; otherwise, the <<
1728 <<
1729 config COMPAT_VDSO <<
1730 bool "Enable vDSO for 32-bit applicat <<
1731 depends on !CPU_BIG_ENDIAN <<
1732 depends on (CC_IS_CLANG && LD_IS_LLD) <<
1733 select GENERIC_COMPAT_VDSO <<
1734 default y <<
1735 help <<
1736 Place in the process address space <<
1737 ELF shared object providing fast im <<
1738 and clock_gettime. <<
1739 <<
1740 You must have a 32-bit build of gli <<
1741 to seamlessly take advantage of thi <<
1742 <<
1743 config THUMB2_COMPAT_VDSO <<
1744 bool "Compile the 32-bit vDSO for Thu <<
1745 depends on COMPAT_VDSO <<
1746 default y <<
1747 help <<
1748 Compile the compat vDSO with '-mthu <<
1749 otherwise with '-marm'. <<
1750 2615
1751 config COMPAT_ALIGNMENT_FIXUPS !! 2616 config HAVE_ARCH_NODEDATA_EXTENSION
1752 bool "Fix up misaligned multi-word lo !! 2617 bool
1753 2618
1754 menuconfig ARMV8_DEPRECATED !! 2619 config RELOCATABLE
1755 bool "Emulate deprecated/obsolete ARM !! 2620 bool "Relocatable kernel"
1756 depends on SYSCTL !! 2621 depends on SYS_SUPPORTS_RELOCATABLE
1757 help !! 2622 depends on CPU_MIPS32_R2 || CPU_MIPS64_R2 || \
1758 Legacy software support may require !! 2623 CPU_MIPS32_R5 || CPU_MIPS64_R5 || \
1759 that have been deprecated or obsole !! 2624 CPU_MIPS32_R6 || CPU_MIPS64_R6 || \
>> 2625 CPU_P5600 || CAVIUM_OCTEON_SOC || \
>> 2626 CPU_LOONGSON64
>> 2627 help
>> 2628 This builds a kernel image that retains relocation information
>> 2629 so it can be loaded someplace besides the default 1MB.
>> 2630 The relocations make the kernel binary about 15% larger,
>> 2631 but are discarded at runtime
>> 2632
>> 2633 config RELOCATION_TABLE_SIZE
>> 2634 hex "Relocation table size"
>> 2635 depends on RELOCATABLE
>> 2636 range 0x0 0x01000000
>> 2637 default "0x00200000" if CPU_LOONGSON64
>> 2638 default "0x00100000"
>> 2639 help
>> 2640 A table of relocation data will be appended to the kernel binary
>> 2641 and parsed at boot to fix up the relocated kernel.
1760 2642
1761 Enable this config to enable select !! 2643 This option allows the amount of space reserved for the table to be
1762 features. !! 2644 adjusted, although the default of 1Mb should be ok in most cases.
1763 2645
1764 If unsure, say Y !! 2646 The build will fail and a valid size suggested if this is too small.
1765 2647
1766 if ARMV8_DEPRECATED !! 2648 If unsure, leave at the default value.
1767 2649
1768 config SWP_EMULATION !! 2650 config RANDOMIZE_BASE
1769 bool "Emulate SWP/SWPB instructions" !! 2651 bool "Randomize the address of the kernel image"
>> 2652 depends on RELOCATABLE
1770 help 2653 help
1771 ARMv8 obsoletes the use of A32 SWP/ !! 2654 Randomizes the physical and virtual address at which the
1772 they are always undefined. Say Y he !! 2655 kernel image is loaded, as a security feature that
1773 emulation of these instructions for !! 2656 deters exploit attempts relying on knowledge of the location
1774 This feature can be controlled at r !! 2657 of kernel internals.
1775 sysctl which is disabled by default <<
1776 2658
1777 In some older versions of glibc [<= !! 2659 Entropy is generated using any coprocessor 0 registers available.
1778 trylock() operations with the assum <<
1779 be preempted. This invalid assumpti <<
1780 with SWP emulation enabled, leading <<
1781 application. <<
1782 2660
1783 NOTE: when accessing uncached share !! 2661 The kernel will be offset by up to RANDOMIZE_BASE_MAX_OFFSET.
1784 on an external transaction monitori <<
1785 monitor to maintain update atomicit <<
1786 implement a global monitor, this op <<
1787 perform SWP operations to uncached <<
1788 2662
1789 If unsure, say Y !! 2663 If unsure, say N.
1790 2664
1791 config CP15_BARRIER_EMULATION !! 2665 config RANDOMIZE_BASE_MAX_OFFSET
1792 bool "Emulate CP15 Barrier instructio !! 2666 hex "Maximum kASLR offset" if EXPERT
1793 help !! 2667 depends on RANDOMIZE_BASE
1794 The CP15 barrier instructions - CP1 !! 2668 range 0x0 0x40000000 if EVA || 64BIT
1795 CP15DMB - are deprecated in ARMv8 ( !! 2669 range 0x0 0x08000000
1796 strongly recommended to use the ISB !! 2670 default "0x01000000"
1797 instructions instead. !! 2671 help
>> 2672 When kASLR is active, this provides the maximum offset that will
>> 2673 be applied to the kernel image. It should be set according to the
>> 2674 amount of physical RAM available in the target system minus
>> 2675 PHYSICAL_START and must be a power of 2.
1798 2676
1799 Say Y here to enable software emula !! 2677 This is limited by the size of KSEG0, 256Mb on 32-bit or 1Gb with
1800 instructions for AArch32 userspace !! 2678 EVA or 64-bit. The default is 16Mb.
1801 enabled, CP15 barrier usage is trac <<
1802 identify software that needs updati <<
1803 controlled at runtime with the abi. <<
1804 2679
1805 If unsure, say Y !! 2680 config NODES_SHIFT
>> 2681 int
>> 2682 default "6"
>> 2683 depends on NUMA
1806 2684
1807 config SETEND_EMULATION !! 2685 config HW_PERF_EVENTS
1808 bool "Emulate SETEND instruction" !! 2686 bool "Enable hardware performance counter support for perf events"
>> 2687 depends on PERF_EVENTS && (CPU_MIPS32 || CPU_MIPS64 || CPU_R10000 || CPU_SB1 || CPU_CAVIUM_OCTEON || CPU_LOONGSON64)
>> 2688 default y
1809 help 2689 help
1810 The SETEND instruction alters the d !! 2690 Enable hardware performance counter support for perf events. If
1811 AArch32 EL0, and is deprecated in A !! 2691 disabled, perf events will use software events only.
1812 2692
1813 Say Y here to enable software emula !! 2693 config DMI
1814 for AArch32 userspace code. This fe !! 2694 bool "Enable DMI scanning"
1815 at runtime with the abi.setend sysc !! 2695 depends on MACH_LOONGSON64
>> 2696 select DMI_SCAN_MACHINE_NON_EFI_FALLBACK
>> 2697 default y
>> 2698 help
>> 2699 Enabled scanning of DMI to identify machine quirks. Say Y
>> 2700 here unless you have verified that your setup is not
>> 2701 affected by entries in the DMI blacklist. Required by PNP
>> 2702 BIOS code.
1816 2703
1817 Note: All the cpus on the system mu !! 2704 config SMP
1818 for this feature to be enabled. If !! 2705 bool "Multi-Processing support"
1819 endian - is hotplugged in after thi !! 2706 depends on SYS_SUPPORTS_SMP
1820 be unexpected results in the applic !! 2707 help
>> 2708 This enables support for systems with more than one CPU. If you have
>> 2709 a system with only one CPU, say N. If you have a system with more
>> 2710 than one CPU, say Y.
>> 2711
>> 2712 If you say N here, the kernel will run on uni- and multiprocessor
>> 2713 machines, but will use only one CPU of a multiprocessor machine. If
>> 2714 you say Y here, the kernel will run on many, but not all,
>> 2715 uniprocessor machines. On a uniprocessor machine, the kernel
>> 2716 will run faster if you say N here.
1821 2717
1822 If unsure, say Y !! 2718 People using multiprocessor machines who say Y here should also say
1823 endif # ARMV8_DEPRECATED !! 2719 Y to "Enhanced Real Time Clock Support", below.
1824 2720
1825 endif # COMPAT !! 2721 See also the SMP-HOWTO available at
>> 2722 <https://www.tldp.org/docs.html#howto>.
1826 2723
1827 menu "ARMv8.1 architectural features" !! 2724 If you don't know what to do here, say N.
1828 2725
1829 config ARM64_HW_AFDBM !! 2726 config HOTPLUG_CPU
1830 bool "Support for hardware updates of !! 2727 bool "Support for hot-pluggable CPUs"
1831 default y !! 2728 depends on SMP && SYS_SUPPORTS_HOTPLUG_CPU
1832 help 2729 help
1833 The ARMv8.1 architecture extensions !! 2730 Say Y here to allow turning CPUs off and on. CPUs can be
1834 hardware updates of the access and !! 2731 controlled through /sys/devices/system/cpu.
1835 table entries. When enabled in TCR_ !! 2732 (Note: power management support will enable this option
1836 capable processors, accesses to pag !! 2733 automatically on SMP systems. )
1837 set this bit instead of raising an !! 2734 Say N if you want to disable CPU hotplug.
1838 Similarly, writes to read-only page <<
1839 clear the read-only bit (AP[2]) ins <<
1840 permission fault. <<
1841 <<
1842 Kernels built with this configurati <<
1843 to work on pre-ARMv8.1 hardware and <<
1844 minimal. If unsure, say Y. <<
1845 2735
1846 config ARM64_PAN !! 2736 config SMP_UP
1847 bool "Enable support for Privileged A !! 2737 bool
1848 default y <<
1849 help <<
1850 Privileged Access Never (PAN; part <<
1851 prevents the kernel or hypervisor f <<
1852 memory directly. <<
1853 2738
1854 Choosing this option will cause any !! 2739 config SYS_SUPPORTS_MIPS_CPS
1855 copy_to_user et al) memory access t !! 2740 bool
1856 2741
1857 The feature is detected at runtime, !! 2742 config SYS_SUPPORTS_SMP
1858 instruction if the cpu does not imp !! 2743 bool
1859 2744
1860 config AS_HAS_LSE_ATOMICS !! 2745 config NR_CPUS_DEFAULT_4
1861 def_bool $(as-instr,.arch_extension l !! 2746 bool
1862 2747
1863 config ARM64_LSE_ATOMICS !! 2748 config NR_CPUS_DEFAULT_8
1864 bool 2749 bool
1865 default ARM64_USE_LSE_ATOMICS <<
1866 depends on AS_HAS_LSE_ATOMICS <<
1867 2750
1868 config ARM64_USE_LSE_ATOMICS !! 2751 config NR_CPUS_DEFAULT_16
1869 bool "Atomic instructions" !! 2752 bool
1870 default y <<
1871 help <<
1872 As part of the Large System Extensi <<
1873 atomic instructions that are design <<
1874 very large systems. <<
1875 2753
1876 Say Y here to make use of these ins !! 2754 config NR_CPUS_DEFAULT_32
1877 atomic routines. This incurs a smal !! 2755 bool
1878 not support these instructions and <<
1879 built with binutils >= 2.25 in orde <<
1880 to be used. <<
1881 2756
1882 endmenu # "ARMv8.1 architectural features" !! 2757 config NR_CPUS_DEFAULT_64
>> 2758 bool
1883 2759
1884 menu "ARMv8.2 architectural features" !! 2760 config NR_CPUS
>> 2761 int "Maximum number of CPUs (2-256)"
>> 2762 range 2 256
>> 2763 depends on SMP
>> 2764 default "4" if NR_CPUS_DEFAULT_4
>> 2765 default "8" if NR_CPUS_DEFAULT_8
>> 2766 default "16" if NR_CPUS_DEFAULT_16
>> 2767 default "32" if NR_CPUS_DEFAULT_32
>> 2768 default "64" if NR_CPUS_DEFAULT_64
>> 2769 help
>> 2770 This allows you to specify the maximum number of CPUs which this
>> 2771 kernel will support. The maximum supported value is 32 for 32-bit
>> 2772 kernel and 64 for 64-bit kernels; the minimum value which makes
>> 2773 sense is 1 for Qemu (useful only for kernel debugging purposes)
>> 2774 and 2 for all others.
>> 2775
>> 2776 This is purely to save memory - each supported CPU adds
>> 2777 approximately eight kilobytes to the kernel image. For best
>> 2778 performance should round up your number of processors to the next
>> 2779 power of two.
1885 2780
1886 config AS_HAS_ARMV8_2 !! 2781 config MIPS_PERF_SHARED_TC_COUNTERS
1887 def_bool $(cc-option,-Wa$(comma)-marc !! 2782 bool
1888 2783
1889 config AS_HAS_SHA3 !! 2784 config MIPS_NR_CPU_NR_MAP_1024
1890 def_bool $(as-instr,.arch armv8.2-a+s !! 2785 bool
1891 2786
1892 config ARM64_PMEM !! 2787 config MIPS_NR_CPU_NR_MAP
1893 bool "Enable support for persistent m !! 2788 int
1894 select ARCH_HAS_PMEM_API !! 2789 depends on SMP
1895 select ARCH_HAS_UACCESS_FLUSHCACHE !! 2790 default 1024 if MIPS_NR_CPU_NR_MAP_1024
1896 help !! 2791 default NR_CPUS if !MIPS_NR_CPU_NR_MAP_1024
1897 Say Y to enable support for the per <<
1898 ARMv8.2 DCPoP feature. <<
1899 2792
1900 The feature is detected at runtime, !! 2793 #
1901 operations if DC CVAP is not suppor !! 2794 # Timer Interrupt Frequency Configuration
1902 DC CVAP itself if the system does n !! 2795 #
1903 2796
1904 config ARM64_RAS_EXTN !! 2797 choice
1905 bool "Enable support for RAS CPU Exte !! 2798 prompt "Timer frequency"
1906 default y !! 2799 default HZ_250
1907 help 2800 help
1908 CPUs that support the Reliability, !! 2801 Allows the configuration of the timer frequency.
1909 (RAS) Extensions, part of ARMv8.2 a <<
1910 errors, classify them and report th <<
1911 <<
1912 On CPUs with these extensions syste <<
1913 barriers to determine if faults are <<
1914 classification from a new set of re <<
1915 <<
1916 Selecting this feature will allow t <<
1917 and access the new registers if the <<
1918 Platform RAS features may additiona <<
1919 2802
1920 config ARM64_CNP !! 2803 config HZ_24
1921 bool "Enable support for Common Not P !! 2804 bool "24 HZ" if SYS_SUPPORTS_24HZ || SYS_SUPPORTS_ARBIT_HZ
1922 default y <<
1923 depends on ARM64_PAN || !ARM64_SW_TTB <<
1924 help <<
1925 Common Not Private (CNP) allows tra <<
1926 be shared between different PEs in <<
1927 domain, so the hardware can use thi <<
1928 caching of such entries in the TLB. <<
1929 2805
1930 Selecting this option allows the CN !! 2806 config HZ_48
1931 at runtime, and does not affect PEs !! 2807 bool "48 HZ" if SYS_SUPPORTS_48HZ || SYS_SUPPORTS_ARBIT_HZ
1932 this feature. <<
1933 2808
1934 endmenu # "ARMv8.2 architectural features" !! 2809 config HZ_100
>> 2810 bool "100 HZ" if SYS_SUPPORTS_100HZ || SYS_SUPPORTS_ARBIT_HZ
1935 2811
1936 menu "ARMv8.3 architectural features" !! 2812 config HZ_128
>> 2813 bool "128 HZ" if SYS_SUPPORTS_128HZ || SYS_SUPPORTS_ARBIT_HZ
1937 2814
1938 config ARM64_PTR_AUTH !! 2815 config HZ_250
1939 bool "Enable support for pointer auth !! 2816 bool "250 HZ" if SYS_SUPPORTS_250HZ || SYS_SUPPORTS_ARBIT_HZ
1940 default y <<
1941 help <<
1942 Pointer authentication (part of the <<
1943 instructions for signing and authen <<
1944 keys, which can be used to mitigate <<
1945 and other attacks. <<
1946 <<
1947 This option enables these instructi <<
1948 Choosing this option will cause the <<
1949 for each process at exec() time, wi <<
1950 context-switched along with the pro <<
1951 <<
1952 The feature is detected at runtime. <<
1953 hardware it will not be advertised <<
1954 be enabled. <<
1955 <<
1956 If the feature is present on the bo <<
1957 the late CPU will be parked. Also, <<
1958 address auth and the late CPU has t <<
1959 but with the feature disabled. On s <<
1960 not be selected. <<
1961 2817
1962 config ARM64_PTR_AUTH_KERNEL !! 2818 config HZ_256
1963 bool "Use pointer authentication for !! 2819 bool "256 HZ" if SYS_SUPPORTS_256HZ || SYS_SUPPORTS_ARBIT_HZ
1964 default y <<
1965 depends on ARM64_PTR_AUTH <<
1966 depends on (CC_HAS_SIGN_RETURN_ADDRES <<
1967 # Modern compilers insert a .note.gnu <<
1968 # which is only understood by binutil <<
1969 depends on LD_IS_LLD || LD_VERSION >= <<
1970 depends on !CC_IS_CLANG || AS_HAS_CFI <<
1971 depends on (!FUNCTION_GRAPH_TRACER || <<
1972 help <<
1973 If the compiler supports the -mbran <<
1974 -msign-return-address flag (e.g. GC <<
1975 will cause the kernel itself to be <<
1976 protection. In this case, and if th <<
1977 support pointer authentication, the <<
1978 disabled with minimal loss of prote <<
1979 <<
1980 This feature works with FUNCTION_GR <<
1981 DYNAMIC_FTRACE_WITH_ARGS is enabled <<
1982 <<
1983 config CC_HAS_BRANCH_PROT_PAC_RET <<
1984 # GCC 9 or later, clang 8 or later <<
1985 def_bool $(cc-option,-mbranch-protect <<
1986 <<
1987 config CC_HAS_SIGN_RETURN_ADDRESS <<
1988 # GCC 7, 8 <<
1989 def_bool $(cc-option,-msign-return-ad <<
1990 <<
1991 config AS_HAS_ARMV8_3 <<
1992 def_bool $(cc-option,-Wa$(comma)-marc <<
1993 <<
1994 config AS_HAS_CFI_NEGATE_RA_STATE <<
1995 def_bool $(as-instr,.cfi_startproc\n. <<
1996 <<
1997 config AS_HAS_LDAPR <<
1998 def_bool $(as-instr,.arch_extension r <<
1999 2820
2000 endmenu # "ARMv8.3 architectural features" !! 2821 config HZ_1000
>> 2822 bool "1000 HZ" if SYS_SUPPORTS_1000HZ || SYS_SUPPORTS_ARBIT_HZ
2001 2823
2002 menu "ARMv8.4 architectural features" !! 2824 config HZ_1024
>> 2825 bool "1024 HZ" if SYS_SUPPORTS_1024HZ || SYS_SUPPORTS_ARBIT_HZ
2003 2826
2004 config ARM64_AMU_EXTN !! 2827 endchoice
2005 bool "Enable support for the Activity <<
2006 default y <<
2007 help <<
2008 The activity monitors extension is <<
2009 by the ARMv8.4 CPU architecture. Th <<
2010 of the activity monitors architectu <<
2011 <<
2012 To enable the use of this extension <<
2013 <<
2014 Note that for architectural reasons <<
2015 support when running on CPUs that p <<
2016 extension. The required support is <<
2017 * Version 1.5 and later of the AR <<
2018 <<
2019 For kernels that have this configur <<
2020 firmware, you may need to say N her <<
2021 Otherwise you may experience firmwa <<
2022 accessing the counter registers. Ev <<
2023 symptoms, the values returned by th <<
2024 correctly reflect reality. Most com <<
2025 indicating that the counter is not <<
2026 2828
2027 config AS_HAS_ARMV8_4 !! 2829 config SYS_SUPPORTS_24HZ
2028 def_bool $(cc-option,-Wa$(comma)-marc !! 2830 bool
2029 2831
2030 config ARM64_TLB_RANGE !! 2832 config SYS_SUPPORTS_48HZ
2031 bool "Enable support for tlbi range f !! 2833 bool
2032 default y <<
2033 depends on AS_HAS_ARMV8_4 <<
2034 help <<
2035 ARMv8.4-TLBI provides TLBI invalida <<
2036 range of input addresses. <<
2037 2834
2038 The feature introduces new assembly !! 2835 config SYS_SUPPORTS_100HZ
2039 support when binutils >= 2.30. !! 2836 bool
2040 2837
2041 endmenu # "ARMv8.4 architectural features" !! 2838 config SYS_SUPPORTS_128HZ
>> 2839 bool
>> 2840
>> 2841 config SYS_SUPPORTS_250HZ
>> 2842 bool
2042 2843
2043 menu "ARMv8.5 architectural features" !! 2844 config SYS_SUPPORTS_256HZ
>> 2845 bool
2044 2846
2045 config AS_HAS_ARMV8_5 !! 2847 config SYS_SUPPORTS_1000HZ
2046 def_bool $(cc-option,-Wa$(comma)-marc !! 2848 bool
2047 2849
2048 config ARM64_BTI !! 2850 config SYS_SUPPORTS_1024HZ
2049 bool "Branch Target Identification su !! 2851 bool
2050 default y <<
2051 help <<
2052 Branch Target Identification (part <<
2053 provides a mechanism to limit the s <<
2054 branch instructions such as BR or B <<
2055 <<
2056 To make use of BTI on CPUs that sup <<
2057 <<
2058 BTI is intended to provide compleme <<
2059 flow integrity protection mechanism <<
2060 authentication mechanism provided a <<
2061 For this reason, it does not make s <<
2062 also enabling support for pointer a <<
2063 enabling this option you should als <<
2064 <<
2065 Userspace binaries must also be spe <<
2066 this mechanism. If you say N here <<
2067 BTI, such binaries can still run, b <<
2068 enforcement of branch destinations. <<
2069 2852
2070 config ARM64_BTI_KERNEL !! 2853 config SYS_SUPPORTS_ARBIT_HZ
2071 bool "Use Branch Target Identificatio !! 2854 bool
2072 default y !! 2855 default y if !SYS_SUPPORTS_24HZ && \
2073 depends on ARM64_BTI !! 2856 !SYS_SUPPORTS_48HZ && \
2074 depends on ARM64_PTR_AUTH_KERNEL !! 2857 !SYS_SUPPORTS_100HZ && \
2075 depends on CC_HAS_BRANCH_PROT_PAC_RET !! 2858 !SYS_SUPPORTS_128HZ && \
2076 # https://gcc.gnu.org/bugzilla/show_b !! 2859 !SYS_SUPPORTS_250HZ && \
2077 depends on !CC_IS_GCC || GCC_VERSION !! 2860 !SYS_SUPPORTS_256HZ && \
2078 # https://gcc.gnu.org/bugzilla/show_b !! 2861 !SYS_SUPPORTS_1000HZ && \
2079 depends on !CC_IS_GCC !! 2862 !SYS_SUPPORTS_1024HZ
2080 depends on (!FUNCTION_GRAPH_TRACER || <<
2081 help <<
2082 Build the kernel with Branch Target <<
2083 and enable enforcement of this for <<
2084 is enabled and the system supports <<
2085 modular code must have BTI enabled. <<
2086 <<
2087 config CC_HAS_BRANCH_PROT_PAC_RET_BTI <<
2088 # GCC 9 or later, clang 8 or later <<
2089 def_bool $(cc-option,-mbranch-protect <<
2090 2863
2091 config ARM64_E0PD !! 2864 config HZ
2092 bool "Enable support for E0PD" !! 2865 int
2093 default y !! 2866 default 24 if HZ_24
2094 help !! 2867 default 48 if HZ_48
2095 E0PD (part of the ARMv8.5 extension !! 2868 default 100 if HZ_100
2096 that EL0 accesses made via TTBR1 al !! 2869 default 128 if HZ_128
2097 providing similar benefits to KASLR !! 2870 default 250 if HZ_250
2098 with lower overhead and without dis !! 2871 default 256 if HZ_256
2099 kernel memory such as SPE. !! 2872 default 1000 if HZ_1000
2100 !! 2873 default 1024 if HZ_1024
2101 This option enables E0PD for TTBR1 !! 2874
2102 !! 2875 config SCHED_HRTICK
2103 config ARM64_AS_HAS_MTE !! 2876 def_bool HIGH_RES_TIMERS
2104 # Initial support for MTE went in bin !! 2877
2105 # ".arch armv8.5-a+memtag" below. How !! 2878 config KEXEC
2106 # as a late addition to the final arc !! 2879 bool "Kexec system call"
2107 # is only supported in the newer 2.32 !! 2880 select KEXEC_CORE
2108 # versions, hence the extra "stgm" in !! 2881 help
2109 def_bool $(as-instr,.arch armv8.5-a+m !! 2882 kexec is a system call that implements the ability to shutdown your
>> 2883 current kernel, and to start another kernel. It is like a reboot
>> 2884 but it is independent of the system firmware. And like a reboot
>> 2885 you can start any kernel with it, not just Linux.
>> 2886
>> 2887 The name comes from the similarity to the exec system call.
>> 2888
>> 2889 It is an ongoing process to be certain the hardware in a machine
>> 2890 is properly shutdown, so do not be surprised if this code does not
>> 2891 initially work for you. As of this writing the exact hardware
>> 2892 interface is strongly in flux, so no good recommendation can be
>> 2893 made.
>> 2894
>> 2895 config CRASH_DUMP
>> 2896 bool "Kernel crash dumps"
>> 2897 help
>> 2898 Generate crash dump after being started by kexec.
>> 2899 This should be normally only set in special crash dump kernels
>> 2900 which are loaded in the main kernel with kexec-tools into
>> 2901 a specially reserved region and then later executed after
>> 2902 a crash by kdump/kexec. The crash dump kernel must be compiled
>> 2903 to a memory address not used by the main kernel or firmware using
>> 2904 PHYSICAL_START.
>> 2905
>> 2906 config PHYSICAL_START
>> 2907 hex "Physical address where the kernel is loaded"
>> 2908 default "0xffffffff84000000"
>> 2909 depends on CRASH_DUMP
>> 2910 help
>> 2911 This gives the CKSEG0 or KSEG0 address where the kernel is loaded.
>> 2912 If you plan to use kernel for capturing the crash dump change
>> 2913 this value to start of the reserved region (the "X" value as
>> 2914 specified in the "crashkernel=YM@XM" command line boot parameter
>> 2915 passed to the panic-ed kernel).
>> 2916
>> 2917 config MIPS_O32_FP64_SUPPORT
>> 2918 bool "Support for O32 binaries using 64-bit FP" if !CPU_MIPSR6
>> 2919 depends on 32BIT || MIPS32_O32
>> 2920 help
>> 2921 When this is enabled, the kernel will support use of 64-bit floating
>> 2922 point registers with binaries using the O32 ABI along with the
>> 2923 EF_MIPS_FP64 ELF header flag (typically built with -mfp64). On
>> 2924 32-bit MIPS systems this support is at the cost of increasing the
>> 2925 size and complexity of the compiled FPU emulator. Thus if you are
>> 2926 running a MIPS32 system and know that none of your userland binaries
>> 2927 will require 64-bit floating point, you may wish to reduce the size
>> 2928 of your kernel & potentially improve FP emulation performance by
>> 2929 saying N here.
>> 2930
>> 2931 Although binutils currently supports use of this flag the details
>> 2932 concerning its effect upon the O32 ABI in userland are still being
>> 2933 worked on. In order to avoid userland becoming dependent upon current
>> 2934 behaviour before the details have been finalised, this option should
>> 2935 be considered experimental and only enabled by those working upon
>> 2936 said details.
2110 2937
2111 config ARM64_MTE !! 2938 If unsure, say N.
2112 bool "Memory Tagging Extension suppor <<
2113 default y <<
2114 depends on ARM64_AS_HAS_MTE && ARM64_ <<
2115 depends on AS_HAS_ARMV8_5 <<
2116 depends on AS_HAS_LSE_ATOMICS <<
2117 # Required for tag checking in the ua <<
2118 depends on ARM64_PAN <<
2119 select ARCH_HAS_SUBPAGE_FAULTS <<
2120 select ARCH_USES_HIGH_VMA_FLAGS <<
2121 select ARCH_USES_PG_ARCH_2 <<
2122 select ARCH_USES_PG_ARCH_3 <<
2123 help <<
2124 Memory Tagging (part of the ARMv8.5 <<
2125 architectural support for run-time, <<
2126 various classes of memory error to <<
2127 to eliminate vulnerabilities arisin <<
2128 languages. <<
2129 <<
2130 This option enables the support for <<
2131 Extension at EL0 (i.e. for userspac <<
2132 <<
2133 Selecting this option allows the fe <<
2134 runtime. Any secondary CPU not impl <<
2135 not be allowed a late bring-up. <<
2136 <<
2137 Userspace binaries that want to use <<
2138 explicitly opt in. The mechanism fo <<
2139 described in: <<
2140 2939
2141 Documentation/arch/arm64/memory-tag !! 2940 config USE_OF
>> 2941 bool
>> 2942 select OF
>> 2943 select OF_EARLY_FLATTREE
>> 2944 select IRQ_DOMAIN
2142 2945
2143 endmenu # "ARMv8.5 architectural features" !! 2946 config UHI_BOOT
>> 2947 bool
2144 2948
2145 menu "ARMv8.7 architectural features" !! 2949 config BUILTIN_DTB
>> 2950 bool
2146 2951
2147 config ARM64_EPAN !! 2952 choice
2148 bool "Enable support for Enhanced Pri !! 2953 prompt "Kernel appended dtb support" if USE_OF
2149 default y !! 2954 default MIPS_NO_APPENDED_DTB
2150 depends on ARM64_PAN <<
2151 help <<
2152 Enhanced Privileged Access Never (E <<
2153 Access Never to be used with Execut <<
2154 2955
2155 The feature is detected at runtime, !! 2956 config MIPS_NO_APPENDED_DTB
2156 if the cpu does not implement the f !! 2957 bool "None"
2157 endmenu # "ARMv8.7 architectural features" !! 2958 help
>> 2959 Do not enable appended dtb support.
>> 2960
>> 2961 config MIPS_ELF_APPENDED_DTB
>> 2962 bool "vmlinux"
>> 2963 help
>> 2964 With this option, the boot code will look for a device tree binary
>> 2965 DTB) included in the vmlinux ELF section .appended_dtb. By default
>> 2966 it is empty and the DTB can be appended using binutils command
>> 2967 objcopy:
>> 2968
>> 2969 objcopy --update-section .appended_dtb=<filename>.dtb vmlinux
>> 2970
>> 2971 This is meant as a backward compatibility convenience for those
>> 2972 systems with a bootloader that can't be upgraded to accommodate
>> 2973 the documented boot protocol using a device tree.
>> 2974
>> 2975 config MIPS_RAW_APPENDED_DTB
>> 2976 bool "vmlinux.bin or vmlinuz.bin"
>> 2977 help
>> 2978 With this option, the boot code will look for a device tree binary
>> 2979 DTB) appended to raw vmlinux.bin or vmlinuz.bin.
>> 2980 (e.g. cat vmlinux.bin <filename>.dtb > vmlinux_w_dtb).
>> 2981
>> 2982 This is meant as a backward compatibility convenience for those
>> 2983 systems with a bootloader that can't be upgraded to accommodate
>> 2984 the documented boot protocol using a device tree.
>> 2985
>> 2986 Beware that there is very little in terms of protection against
>> 2987 this option being confused by leftover garbage in memory that might
>> 2988 look like a DTB header after a reboot if no actual DTB is appended
>> 2989 to vmlinux.bin. Do not leave this option active in a production kernel
>> 2990 if you don't intend to always append a DTB.
>> 2991 endchoice
2158 2992
2159 menu "ARMv8.9 architectural features" !! 2993 choice
>> 2994 prompt "Kernel command line type" if !CMDLINE_OVERRIDE
>> 2995 default MIPS_CMDLINE_FROM_DTB if USE_OF && !ATH79 && !MACH_INGENIC && \
>> 2996 !MACH_LOONGSON64 && !MIPS_MALTA && \
>> 2997 !CAVIUM_OCTEON_SOC
>> 2998 default MIPS_CMDLINE_FROM_BOOTLOADER
>> 2999
>> 3000 config MIPS_CMDLINE_FROM_DTB
>> 3001 depends on USE_OF
>> 3002 bool "Dtb kernel arguments if available"
>> 3003
>> 3004 config MIPS_CMDLINE_DTB_EXTEND
>> 3005 depends on USE_OF
>> 3006 bool "Extend dtb kernel arguments with bootloader arguments"
>> 3007
>> 3008 config MIPS_CMDLINE_FROM_BOOTLOADER
>> 3009 bool "Bootloader kernel arguments if available"
>> 3010
>> 3011 config MIPS_CMDLINE_BUILTIN_EXTEND
>> 3012 depends on CMDLINE_BOOL
>> 3013 bool "Extend builtin kernel arguments with bootloader arguments"
>> 3014 endchoice
2160 3015
2161 config ARM64_POE !! 3016 endmenu
2162 prompt "Permission Overlay Extension" <<
2163 def_bool y <<
2164 select ARCH_USES_HIGH_VMA_FLAGS <<
2165 select ARCH_HAS_PKEYS <<
2166 help <<
2167 The Permission Overlay Extension is <<
2168 Protection Keys. Memory Protection <<
2169 enforcing page-based protections, b <<
2170 of the page tables when an applicat <<
2171 3017
2172 For details, see Documentation/core !! 3018 config LOCKDEP_SUPPORT
>> 3019 bool
>> 3020 default y
2173 3021
2174 If unsure, say y. !! 3022 config STACKTRACE_SUPPORT
>> 3023 bool
>> 3024 default y
2175 3025
2176 config ARCH_PKEY_BITS !! 3026 config PGTABLE_LEVELS
2177 int 3027 int
2178 default 3 !! 3028 default 4 if PAGE_SIZE_4KB && MIPS_VA_BITS_48
>> 3029 default 3 if 64BIT && (!PAGE_SIZE_64KB || MIPS_VA_BITS_48)
>> 3030 default 2
2179 3031
2180 endmenu # "ARMv8.9 architectural features" !! 3032 config MIPS_AUTO_PFN_OFFSET
2181 !! 3033 bool
2182 config ARM64_SVE <<
2183 bool "ARM Scalable Vector Extension s <<
2184 default y <<
2185 help <<
2186 The Scalable Vector Extension (SVE) <<
2187 execution state which complements a <<
2188 of the base architecture to support <<
2189 additional vectorisation opportunit <<
2190 <<
2191 To enable use of this extension on <<
2192 <<
2193 On CPUs that support the SVE2 exten <<
2194 those too. <<
2195 <<
2196 Note that for architectural reasons <<
2197 support when running on SVE capable <<
2198 is present in: <<
2199 <<
2200 * version 1.5 and later of the AR <<
2201 * the AArch64 boot wrapper since <<
2202 ("bootwrapper: SVE: Enable SVE <<
2203 <<
2204 For other firmware implementations, <<
2205 or vendor. <<
2206 <<
2207 If you need the kernel to boot on S <<
2208 firmware, you may need to say N her <<
2209 fixed. Otherwise, you may experien <<
2210 booting the kernel. If unsure and <<
2211 symptoms, you should assume that it <<
2212 3034
2213 config ARM64_SME !! 3035 menu "Bus options (PCI, PCMCIA, EISA, ISA, TC)"
2214 bool "ARM Scalable Matrix Extension s <<
2215 default y <<
2216 depends on ARM64_SVE <<
2217 depends on BROKEN <<
2218 help <<
2219 The Scalable Matrix Extension (SME) <<
2220 execution state which utilises a su <<
2221 instruction set, together with the <<
2222 register state capable of holding t <<
2223 enable various matrix operations. <<
2224 <<
2225 config ARM64_PSEUDO_NMI <<
2226 bool "Support for NMI-like interrupts <<
2227 select ARM_GIC_V3 <<
2228 help <<
2229 Adds support for mimicking Non-Mask <<
2230 GIC interrupt priority. This suppor <<
2231 ARM GIC. <<
2232 <<
2233 This high priority configuration fo <<
2234 explicitly enabled by setting the k <<
2235 "irqchip.gicv3_pseudo_nmi" to 1. <<
2236 <<
2237 If unsure, say N <<
2238 <<
2239 if ARM64_PSEUDO_NMI <<
2240 config ARM64_DEBUG_PRIORITY_MASKING <<
2241 bool "Debug interrupt priority maskin <<
2242 help <<
2243 This adds runtime checks to functio <<
2244 interrupts when using priority mask <<
2245 the validity of ICC_PMR_EL1 when ca <<
2246 3036
2247 If unsure, say N !! 3037 config PCI_DRIVERS_GENERIC
2248 endif # ARM64_PSEUDO_NMI !! 3038 select PCI_DOMAINS_GENERIC if PCI
>> 3039 bool
2249 3040
2250 config RELOCATABLE !! 3041 config PCI_DRIVERS_LEGACY
2251 bool "Build a relocatable kernel imag !! 3042 def_bool !PCI_DRIVERS_GENERIC
2252 select ARCH_HAS_RELR !! 3043 select NO_GENERIC_PCI_IOPORT_MAP
2253 default y !! 3044 select PCI_DOMAINS if PCI
2254 help <<
2255 This builds the kernel as a Positio <<
2256 which retains all relocation metada <<
2257 kernel binary at runtime to a diffe <<
2258 address it was linked at. <<
2259 Since AArch64 uses the RELA relocat <<
2260 relocation pass at runtime even if <<
2261 same address it was linked at. <<
2262 3045
2263 config RANDOMIZE_BASE !! 3046 #
2264 bool "Randomize the address of the ke !! 3047 # ISA support is now enabled via select. Too many systems still have the one
2265 select RELOCATABLE !! 3048 # or other ISA chip on the board that users don't know about so don't expect
2266 help !! 3049 # users to choose the right thing ...
2267 Randomizes the virtual address at w !! 3050 #
2268 loaded, as a security feature that !! 3051 config ISA
2269 relying on knowledge of the locatio !! 3052 bool
2270 <<
2271 It is the bootloader's job to provi <<
2272 random u64 value in /chosen/kaslr-s <<
2273 <<
2274 When booting via the UEFI stub, it <<
2275 EFI_RNG_PROTOCOL implementation (if <<
2276 to the kernel proper. In addition, <<
2277 location of the kernel Image as wel <<
2278 3053
2279 If unsure, say N. !! 3054 config TC
>> 3055 bool "TURBOchannel support"
>> 3056 depends on MACH_DECSTATION
>> 3057 help
>> 3058 TURBOchannel is a DEC (now Compaq (now HP)) bus for Alpha and MIPS
>> 3059 processors. TURBOchannel programming specifications are available
>> 3060 at:
>> 3061 <ftp://ftp.hp.com/pub/alphaserver/archive/triadd/>
>> 3062 and:
>> 3063 <http://www.computer-refuge.org/classiccmp/ftp.digital.com/pub/DEC/TriAdd/>
>> 3064 Linux driver support status is documented at:
>> 3065 <http://www.linux-mips.org/wiki/DECstation>
2280 3066
2281 config RANDOMIZE_MODULE_REGION_FULL !! 3067 config MMU
2282 bool "Randomize the module region ove !! 3068 bool
2283 depends on RANDOMIZE_BASE <<
2284 default y 3069 default y
2285 help <<
2286 Randomizes the location of the modu <<
2287 covering the core kernel. This way, <<
2288 to leak information about the locat <<
2289 but it does imply that function cal <<
2290 kernel will need to be resolved via <<
2291 <<
2292 When this option is not set, the mo <<
2293 a limited range that contains the [ <<
2294 core kernel, so branch relocations <<
2295 the region is exhausted. In this pa <<
2296 exhaustion, modules might be able t <<
2297 3070
2298 config CC_HAVE_STACKPROTECTOR_SYSREG !! 3071 config ARCH_MMAP_RND_BITS_MIN
2299 def_bool $(cc-option,-mstack-protecto !! 3072 default 12 if 64BIT
>> 3073 default 8
2300 3074
2301 config STACKPROTECTOR_PER_TASK !! 3075 config ARCH_MMAP_RND_BITS_MAX
2302 def_bool y !! 3076 default 18 if 64BIT
2303 depends on STACKPROTECTOR && CC_HAVE_ !! 3077 default 15
2304 3078
2305 config UNWIND_PATCH_PAC_INTO_SCS !! 3079 config ARCH_MMAP_RND_COMPAT_BITS_MIN
2306 bool "Enable shadow call stack dynami !! 3080 default 8
2307 # needs Clang with https://github.com <<
2308 depends on CC_IS_CLANG && CLANG_VERSI <<
2309 depends on ARM64_PTR_AUTH_KERNEL && C <<
2310 depends on SHADOW_CALL_STACK <<
2311 select UNWIND_TABLES <<
2312 select DYNAMIC_SCS <<
2313 <<
2314 config ARM64_CONTPTE <<
2315 bool "Contiguous PTE mappings for use <<
2316 depends on TRANSPARENT_HUGEPAGE <<
2317 default y <<
2318 help <<
2319 When enabled, user mappings are con <<
2320 bit, for any mappings that meet the <<
2321 This reduces TLB pressure and impro <<
2322 <<
2323 endmenu # "Kernel Features" <<
2324 <<
2325 menu "Boot options" <<
2326 <<
2327 config ARM64_ACPI_PARKING_PROTOCOL <<
2328 bool "Enable support for the ARM64 AC <<
2329 depends on ACPI <<
2330 help <<
2331 Enable support for the ARM64 ACPI p <<
2332 the kernel will not allow booting t <<
2333 protocol even if the corresponding <<
2334 MADT table. <<
2335 <<
2336 config CMDLINE <<
2337 string "Default kernel command string <<
2338 default "" <<
2339 help <<
2340 Provide a set of default command-li <<
2341 entering them here. As a minimum, y <<
2342 root device (e.g. root=/dev/nfs). <<
2343 3081
2344 choice !! 3082 config ARCH_MMAP_RND_COMPAT_BITS_MAX
2345 prompt "Kernel command line type" !! 3083 default 15
2346 depends on CMDLINE != "" <<
2347 default CMDLINE_FROM_BOOTLOADER <<
2348 help <<
2349 Choose how the kernel will handle t <<
2350 command line string. <<
2351 <<
2352 config CMDLINE_FROM_BOOTLOADER <<
2353 bool "Use bootloader kernel arguments <<
2354 help <<
2355 Uses the command-line options passe <<
2356 the boot loader doesn't provide any <<
2357 string provided in CMDLINE will be <<
2358 <<
2359 config CMDLINE_FORCE <<
2360 bool "Always use the default kernel c <<
2361 help <<
2362 Always use the default kernel comma <<
2363 loader passes other arguments to th <<
2364 This is useful if you cannot or don <<
2365 command-line options your boot load <<
2366 3084
2367 endchoice !! 3085 config I8253
>> 3086 bool
>> 3087 select CLKSRC_I8253
>> 3088 select CLKEVT_I8253
>> 3089 select MIPS_EXTERNAL_TIMER
>> 3090 endmenu
2368 3091
2369 config EFI_STUB !! 3092 config TRAD_SIGNALS
2370 bool 3093 bool
2371 3094
2372 config EFI !! 3095 config MIPS32_COMPAT
2373 bool "UEFI runtime support" !! 3096 bool
2374 depends on OF && !CPU_BIG_ENDIAN <<
2375 depends on KERNEL_MODE_NEON <<
2376 select ARCH_SUPPORTS_ACPI <<
2377 select LIBFDT <<
2378 select UCS2_STRING <<
2379 select EFI_PARAMS_FROM_FDT <<
2380 select EFI_RUNTIME_WRAPPERS <<
2381 select EFI_STUB <<
2382 select EFI_GENERIC_STUB <<
2383 imply IMA_SECURE_AND_OR_TRUSTED_BOOT <<
2384 default y <<
2385 help <<
2386 This option provides support for ru <<
2387 by UEFI firmware (such as non-volat <<
2388 clock, and platform reset). A UEFI <<
2389 allow the kernel to be booted as an <<
2390 is only useful on systems that have <<
2391 <<
2392 config COMPRESSED_INSTALL <<
2393 bool "Install compressed image by def <<
2394 help <<
2395 This makes the regular "make instal <<
2396 image we built, not the legacy unco <<
2397 <<
2398 You can check that a compressed ima <<
2399 "make zinstall" first, and verifyin <<
2400 in your environment before making " <<
2401 you. <<
2402 3097
2403 config DMI !! 3098 config COMPAT
2404 bool "Enable support for SMBIOS (DMI) !! 3099 bool
2405 depends on EFI <<
2406 default y <<
2407 help <<
2408 This enables SMBIOS/DMI feature for <<
2409 3100
2410 This option is only useful on syste !! 3101 config MIPS32_O32
2411 However, even with this option, the !! 3102 bool "Kernel support for o32 binaries"
2412 continue to boot on existing non-UE !! 3103 depends on 64BIT
>> 3104 select ARCH_WANT_OLD_COMPAT_IPC
>> 3105 select COMPAT
>> 3106 select MIPS32_COMPAT
>> 3107 help
>> 3108 Select this option if you want to run o32 binaries. These are pure
>> 3109 32-bit binaries as used by the 32-bit Linux/MIPS port. Most of
>> 3110 existing binaries are in this format.
2413 3111
2414 endmenu # "Boot options" !! 3112 If unsure, say Y.
2415 3113
2416 menu "Power management options" !! 3114 config MIPS32_N32
>> 3115 bool "Kernel support for n32 binaries"
>> 3116 depends on 64BIT
>> 3117 select ARCH_WANT_COMPAT_IPC_PARSE_VERSION
>> 3118 select COMPAT
>> 3119 select MIPS32_COMPAT
>> 3120 help
>> 3121 Select this option if you want to run n32 binaries. These are
>> 3122 64-bit binaries using 32-bit quantities for addressing and certain
>> 3123 data that would normally be 64-bit. They are used in special
>> 3124 cases.
2417 3125
2418 source "kernel/power/Kconfig" !! 3126 If unsure, say N.
2419 3127
2420 config ARCH_HIBERNATION_POSSIBLE !! 3128 config CC_HAS_MNO_BRANCH_LIKELY
2421 def_bool y 3129 def_bool y
2422 depends on CPU_PM !! 3130 depends on $(cc-option,-mno-branch-likely)
2423 3131
2424 config ARCH_HIBERNATION_HEADER !! 3132 # https://github.com/llvm/llvm-project/issues/61045
>> 3133 config CC_HAS_BROKEN_INLINE_COMPAT_BRANCH
>> 3134 def_bool y if CC_IS_CLANG
>> 3135
>> 3136 menu "Power management options"
>> 3137
>> 3138 config ARCH_HIBERNATION_POSSIBLE
2425 def_bool y 3139 def_bool y
2426 depends on HIBERNATION !! 3140 depends on SYS_SUPPORTS_HOTPLUG_CPU || !SMP
2427 3141
2428 config ARCH_SUSPEND_POSSIBLE 3142 config ARCH_SUSPEND_POSSIBLE
2429 def_bool y 3143 def_bool y
>> 3144 depends on SYS_SUPPORTS_HOTPLUG_CPU || !SMP
2430 3145
2431 endmenu # "Power management options" !! 3146 source "kernel/power/Kconfig"
2432 3147
2433 menu "CPU Power Management" !! 3148 endmenu
2434 3149
2435 source "drivers/cpuidle/Kconfig" !! 3150 config MIPS_EXTERNAL_TIMER
>> 3151 bool
2436 3152
>> 3153 menu "CPU Power Management"
>> 3154
>> 3155 if CPU_SUPPORTS_CPUFREQ && MIPS_EXTERNAL_TIMER
2437 source "drivers/cpufreq/Kconfig" 3156 source "drivers/cpufreq/Kconfig"
>> 3157 endif # CPU_SUPPORTS_CPUFREQ && MIPS_EXTERNAL_TIMER
2438 3158
2439 endmenu # "CPU Power Management" !! 3159 source "drivers/cpuidle/Kconfig"
2440 3160
2441 source "drivers/acpi/Kconfig" !! 3161 endmenu
2442 3162
2443 source "arch/arm64/kvm/Kconfig" !! 3163 source "arch/mips/kvm/Kconfig"
2444 3164
>> 3165 source "arch/mips/vdso/Kconfig"
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