1 # SPDX-License-Identifier: GPL-2.0-only !! 1 # SPDX-License-Identifier: GPL-2.0
2 config ARM64 !! 2 config MIPS
3 def_bool y !! 3 bool
4 select ACPI_APMT if ACPI !! 4 default y
5 select ACPI_CCA_REQUIRED if ACPI !! 5 select ARCH_32BIT_OFF_T if !64BIT
6 select ACPI_GENERIC_GSI if ACPI !! 6 select ARCH_BINFMT_ELF_STATE if MIPS_FP_SUPPORT
7 select ACPI_GTDT if ACPI !! 7 select ARCH_HAS_CPU_FINALIZE_INIT
8 select ACPI_HOTPLUG_CPU if ACPI_PROCES !! 8 select ARCH_HAS_CURRENT_STACK_POINTER if !CC_IS_CLANG || CLANG_VERSION >= 140000
9 select ACPI_IORT if ACPI !! 9 select ARCH_HAS_DEBUG_VIRTUAL if !64BIT
10 select ACPI_REDUCED_HARDWARE_ONLY if A <<
11 select ACPI_MCFG if (ACPI && PCI) <<
12 select ACPI_SPCR_TABLE if ACPI <<
13 select ACPI_PPTT if ACPI <<
14 select ARCH_HAS_DEBUG_WX <<
15 select ARCH_BINFMT_ELF_EXTRA_PHDRS <<
16 select ARCH_BINFMT_ELF_STATE <<
17 select ARCH_CORRECT_STACKTRACE_ON_KRET <<
18 select ARCH_ENABLE_HUGEPAGE_MIGRATION <<
19 select ARCH_ENABLE_MEMORY_HOTPLUG <<
20 select ARCH_ENABLE_MEMORY_HOTREMOVE <<
21 select ARCH_ENABLE_SPLIT_PMD_PTLOCK if <<
22 select ARCH_ENABLE_THP_MIGRATION if TR <<
23 select ARCH_HAS_CACHE_LINE_SIZE <<
24 select ARCH_HAS_CURRENT_STACK_POINTER <<
25 select ARCH_HAS_DEBUG_VIRTUAL <<
26 select ARCH_HAS_DEBUG_VM_PGTABLE <<
27 select ARCH_HAS_DMA_OPS if XEN <<
28 select ARCH_HAS_DMA_PREP_COHERENT <<
29 select ARCH_HAS_ACPI_TABLE_UPGRADE if <<
30 select ARCH_HAS_FAST_MULTIPLIER <<
31 select ARCH_HAS_FORTIFY_SOURCE 10 select ARCH_HAS_FORTIFY_SOURCE
32 select ARCH_HAS_GCOV_PROFILE_ALL <<
33 select ARCH_HAS_GIGANTIC_PAGE <<
34 select ARCH_HAS_KCOV 11 select ARCH_HAS_KCOV
35 select ARCH_HAS_KERNEL_FPU_SUPPORT if !! 12 select ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE if !EVA
36 select ARCH_HAS_KEEPINITRD !! 13 select ARCH_HAS_PTE_SPECIAL if !(32BIT && CPU_HAS_RIXI)
37 select ARCH_HAS_MEMBARRIER_SYNC_CORE !! 14 select ARCH_HAS_STRNCPY_FROM_USER
38 select ARCH_HAS_MEM_ENCRYPT !! 15 select ARCH_HAS_STRNLEN_USER
39 select ARCH_HAS_NMI_SAFE_THIS_CPU_OPS <<
40 select ARCH_HAS_NON_OVERLAPPING_ADDRES <<
41 select ARCH_HAS_PTE_DEVMAP <<
42 select ARCH_HAS_PTE_SPECIAL <<
43 select ARCH_HAS_HW_PTE_YOUNG <<
44 select ARCH_HAS_SETUP_DMA_OPS <<
45 select ARCH_HAS_SET_DIRECT_MAP <<
46 select ARCH_HAS_SET_MEMORY <<
47 select ARCH_STACKWALK <<
48 select ARCH_HAS_STRICT_KERNEL_RWX <<
49 select ARCH_HAS_STRICT_MODULE_RWX <<
50 select ARCH_HAS_SYNC_DMA_FOR_DEVICE <<
51 select ARCH_HAS_SYNC_DMA_FOR_CPU <<
52 select ARCH_HAS_SYSCALL_WRAPPER <<
53 select ARCH_HAS_TICK_BROADCAST if GENE 16 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
54 select ARCH_HAS_ZONE_DMA_SET if EXPERT !! 17 select ARCH_HAS_UBSAN_SANITIZE_ALL
55 select ARCH_HAVE_ELF_PROT !! 18 select ARCH_HAS_GCOV_PROFILE_ALL
56 select ARCH_HAVE_NMI_SAFE_CMPXCHG <<
57 select ARCH_HAVE_TRACE_MMIO_ACCESS <<
58 select ARCH_INLINE_READ_LOCK if !PREEM <<
59 select ARCH_INLINE_READ_LOCK_BH if !PR <<
60 select ARCH_INLINE_READ_LOCK_IRQ if !P <<
61 select ARCH_INLINE_READ_LOCK_IRQSAVE i <<
62 select ARCH_INLINE_READ_UNLOCK if !PRE <<
63 select ARCH_INLINE_READ_UNLOCK_BH if ! <<
64 select ARCH_INLINE_READ_UNLOCK_IRQ if <<
65 select ARCH_INLINE_READ_UNLOCK_IRQREST <<
66 select ARCH_INLINE_WRITE_LOCK if !PREE <<
67 select ARCH_INLINE_WRITE_LOCK_BH if !P <<
68 select ARCH_INLINE_WRITE_LOCK_IRQ if ! <<
69 select ARCH_INLINE_WRITE_LOCK_IRQSAVE <<
70 select ARCH_INLINE_WRITE_UNLOCK if !PR <<
71 select ARCH_INLINE_WRITE_UNLOCK_BH if <<
72 select ARCH_INLINE_WRITE_UNLOCK_IRQ if <<
73 select ARCH_INLINE_WRITE_UNLOCK_IRQRES <<
74 select ARCH_INLINE_SPIN_TRYLOCK if !PR <<
75 select ARCH_INLINE_SPIN_TRYLOCK_BH if <<
76 select ARCH_INLINE_SPIN_LOCK if !PREEM <<
77 select ARCH_INLINE_SPIN_LOCK_BH if !PR <<
78 select ARCH_INLINE_SPIN_LOCK_IRQ if !P <<
79 select ARCH_INLINE_SPIN_LOCK_IRQSAVE i <<
80 select ARCH_INLINE_SPIN_UNLOCK if !PRE <<
81 select ARCH_INLINE_SPIN_UNLOCK_BH if ! <<
82 select ARCH_INLINE_SPIN_UNLOCK_IRQ if <<
83 select ARCH_INLINE_SPIN_UNLOCK_IRQREST <<
84 select ARCH_KEEP_MEMBLOCK 19 select ARCH_KEEP_MEMBLOCK
85 select ARCH_MHP_MEMMAP_ON_MEMORY_ENABL !! 20 select ARCH_USE_BUILTIN_BSWAP
86 select ARCH_USE_CMPXCHG_LOCKREF !! 21 select ARCH_USE_CMPXCHG_LOCKREF if 64BIT
87 select ARCH_USE_GNU_PROPERTY <<
88 select ARCH_USE_MEMTEST 22 select ARCH_USE_MEMTEST
89 select ARCH_USE_QUEUED_RWLOCKS 23 select ARCH_USE_QUEUED_RWLOCKS
90 select ARCH_USE_QUEUED_SPINLOCKS 24 select ARCH_USE_QUEUED_SPINLOCKS
91 select ARCH_USE_SYM_ANNOTATIONS !! 25 select ARCH_SUPPORTS_HUGETLBFS if CPU_SUPPORTS_HUGEPAGES
92 select ARCH_SUPPORTS_DEBUG_PAGEALLOC !! 26 select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT if MMU
93 select ARCH_SUPPORTS_HUGETLBFS !! 27 select ARCH_WANT_IPC_PARSE_VERSION
94 select ARCH_SUPPORTS_MEMORY_FAILURE <<
95 select ARCH_SUPPORTS_SHADOW_CALL_STACK <<
96 select ARCH_SUPPORTS_LTO_CLANG if CPU_ <<
97 select ARCH_SUPPORTS_LTO_CLANG_THIN <<
98 select ARCH_SUPPORTS_CFI_CLANG <<
99 select ARCH_SUPPORTS_ATOMIC_RMW <<
100 select ARCH_SUPPORTS_INT128 if CC_HAS_ <<
101 select ARCH_SUPPORTS_NUMA_BALANCING <<
102 select ARCH_SUPPORTS_PAGE_TABLE_CHECK <<
103 select ARCH_SUPPORTS_PER_VMA_LOCK <<
104 select ARCH_SUPPORTS_HUGE_PFNMAP if TR <<
105 select ARCH_SUPPORTS_RT <<
106 select ARCH_WANT_BATCHED_UNMAP_TLB_FLU <<
107 select ARCH_WANT_COMPAT_IPC_PARSE_VERS <<
108 select ARCH_WANT_DEFAULT_BPF_JIT <<
109 select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_ <<
110 select ARCH_WANT_FRAME_POINTERS <<
111 select ARCH_WANT_HUGE_PMD_SHARE if ARM <<
112 select ARCH_WANT_LD_ORPHAN_WARN 28 select ARCH_WANT_LD_ORPHAN_WARN
113 select ARCH_WANTS_EXECMEM_LATE if EXEC <<
114 select ARCH_WANTS_NO_INSTR <<
115 select ARCH_WANTS_THP_SWAP if ARM64_4K <<
116 select ARCH_HAS_UBSAN <<
117 select ARM_AMBA <<
118 select ARM_ARCH_TIMER <<
119 select ARM_GIC <<
120 select AUDIT_ARCH_COMPAT_GENERIC <<
121 select ARM_GIC_V2M if PCI <<
122 select ARM_GIC_V3 <<
123 select ARM_GIC_V3_ITS if PCI <<
124 select ARM_PSCI_FW <<
125 select BUILDTIME_TABLE_SORT 29 select BUILDTIME_TABLE_SORT
126 select CLONE_BACKWARDS 30 select CLONE_BACKWARDS
127 select COMMON_CLK !! 31 select CPU_NO_EFFICIENT_FFS if (TARGET_ISA_REV < 1)
128 select CPU_PM if (SUSPEND || CPU_IDLE) !! 32 select CPU_PM if CPU_IDLE
129 select CPUMASK_OFFSTACK if NR_CPUS > 2 !! 33 select GENERIC_ATOMIC64 if !64BIT
130 select CRC32 !! 34 select GENERIC_CMOS_UPDATE
131 select DCACHE_WORD_ACCESS <<
132 select DYNAMIC_FTRACE if FUNCTION_TRAC <<
133 select DMA_BOUNCE_UNALIGNED_KMALLOC <<
134 select DMA_DIRECT_REMAP <<
135 select EDAC_SUPPORT <<
136 select FRAME_POINTER <<
137 select FUNCTION_ALIGNMENT_4B <<
138 select FUNCTION_ALIGNMENT_8B if DYNAMI <<
139 select GENERIC_ALLOCATOR <<
140 select GENERIC_ARCH_TOPOLOGY <<
141 select GENERIC_CLOCKEVENTS_BROADCAST <<
142 select GENERIC_CPU_AUTOPROBE 35 select GENERIC_CPU_AUTOPROBE
143 select GENERIC_CPU_DEVICES !! 36 select GENERIC_GETTIMEOFDAY
144 select GENERIC_CPU_VULNERABILITIES !! 37 select GENERIC_IOMAP
145 select GENERIC_EARLY_IOREMAP <<
146 select GENERIC_IDLE_POLL_SETUP <<
147 select GENERIC_IOREMAP <<
148 select GENERIC_IRQ_IPI <<
149 select GENERIC_IRQ_PROBE 38 select GENERIC_IRQ_PROBE
150 select GENERIC_IRQ_SHOW 39 select GENERIC_IRQ_SHOW
151 select GENERIC_IRQ_SHOW_LEVEL !! 40 select GENERIC_ISA_DMA if EISA
152 select GENERIC_LIB_DEVMEM_IS_ALLOWED !! 41 select GENERIC_LIB_ASHLDI3
153 select GENERIC_PCI_IOMAP !! 42 select GENERIC_LIB_ASHRDI3
154 select GENERIC_PTDUMP !! 43 select GENERIC_LIB_CMPDI2
155 select GENERIC_SCHED_CLOCK !! 44 select GENERIC_LIB_LSHRDI3
>> 45 select GENERIC_LIB_UCMPDI2
>> 46 select GENERIC_SCHED_CLOCK if !CAVIUM_OCTEON_SOC
156 select GENERIC_SMP_IDLE_THREAD 47 select GENERIC_SMP_IDLE_THREAD
>> 48 select GENERIC_IDLE_POLL_SETUP
157 select GENERIC_TIME_VSYSCALL 49 select GENERIC_TIME_VSYSCALL
158 select GENERIC_GETTIMEOFDAY !! 50 select GUP_GET_PXX_LOW_HIGH if CPU_MIPS32 && PHYS_ADDR_T_64BIT
159 select GENERIC_VDSO_TIME_NS !! 51 select HAS_IOPORT if !NO_IOPORT_MAP || ISA
160 select HARDIRQS_SW_RESEND <<
161 select HAS_IOPORT <<
162 select HAVE_MOVE_PMD <<
163 select HAVE_MOVE_PUD <<
164 select HAVE_PCI <<
165 select HAVE_ACPI_APEI if (ACPI && EFI) <<
166 select HAVE_ALIGNED_STRUCT_PAGE <<
167 select HAVE_ARCH_AUDITSYSCALL <<
168 select HAVE_ARCH_BITREVERSE <<
169 select HAVE_ARCH_COMPILER_H 52 select HAVE_ARCH_COMPILER_H
170 select HAVE_ARCH_HUGE_VMALLOC <<
171 select HAVE_ARCH_HUGE_VMAP <<
172 select HAVE_ARCH_JUMP_LABEL 53 select HAVE_ARCH_JUMP_LABEL
173 select HAVE_ARCH_JUMP_LABEL_RELATIVE !! 54 select HAVE_ARCH_KGDB if MIPS_FP_SUPPORT
174 select HAVE_ARCH_KASAN !! 55 select HAVE_ARCH_MMAP_RND_BITS if MMU
175 select HAVE_ARCH_KASAN_VMALLOC !! 56 select HAVE_ARCH_MMAP_RND_COMPAT_BITS if MMU && COMPAT
176 select HAVE_ARCH_KASAN_SW_TAGS <<
177 select HAVE_ARCH_KASAN_HW_TAGS if ARM6 <<
178 # Some instrumentation may be unsound, <<
179 select HAVE_ARCH_KCSAN if EXPERT <<
180 select HAVE_ARCH_KFENCE <<
181 select HAVE_ARCH_KGDB <<
182 select HAVE_ARCH_MMAP_RND_BITS <<
183 select HAVE_ARCH_MMAP_RND_COMPAT_BITS <<
184 select HAVE_ARCH_PREL32_RELOCATIONS <<
185 select HAVE_ARCH_RANDOMIZE_KSTACK_OFFS <<
186 select HAVE_ARCH_SECCOMP_FILTER 57 select HAVE_ARCH_SECCOMP_FILTER
187 select HAVE_ARCH_STACKLEAK <<
188 select HAVE_ARCH_THREAD_STRUCT_WHITELI <<
189 select HAVE_ARCH_TRACEHOOK 58 select HAVE_ARCH_TRACEHOOK
190 select HAVE_ARCH_TRANSPARENT_HUGEPAGE !! 59 select HAVE_ARCH_TRANSPARENT_HUGEPAGE if CPU_SUPPORTS_HUGEPAGES
191 select HAVE_ARCH_VMAP_STACK <<
192 select HAVE_ARM_SMCCC <<
193 select HAVE_ASM_MODVERSIONS 60 select HAVE_ASM_MODVERSIONS
194 select HAVE_EBPF_JIT <<
195 select HAVE_C_RECORDMCOUNT <<
196 select HAVE_CMPXCHG_DOUBLE <<
197 select HAVE_CMPXCHG_LOCAL <<
198 select HAVE_CONTEXT_TRACKING_USER 61 select HAVE_CONTEXT_TRACKING_USER
>> 62 select HAVE_TIF_NOHZ
>> 63 select HAVE_C_RECORDMCOUNT
199 select HAVE_DEBUG_KMEMLEAK 64 select HAVE_DEBUG_KMEMLEAK
>> 65 select HAVE_DEBUG_STACKOVERFLOW
200 select HAVE_DMA_CONTIGUOUS 66 select HAVE_DMA_CONTIGUOUS
201 select HAVE_DYNAMIC_FTRACE 67 select HAVE_DYNAMIC_FTRACE
202 select HAVE_DYNAMIC_FTRACE_WITH_ARGS \ !! 68 select HAVE_EBPF_JIT if !CPU_MICROMIPS
203 if (GCC_SUPPORTS_DYNAMIC_FTRAC !! 69 select HAVE_EXIT_THREAD
204 CLANG_SUPPORTS_DYNAMIC_FTR !! 70 select HAVE_FAST_GUP
205 select HAVE_DYNAMIC_FTRACE_WITH_DIRECT <<
206 if DYNAMIC_FTRACE_WITH_ARGS && <<
207 select HAVE_DYNAMIC_FTRACE_WITH_CALL_O <<
208 if (DYNAMIC_FTRACE_WITH_ARGS & <<
209 (CC_IS_CLANG || !CC_OPTIMI <<
210 select FTRACE_MCOUNT_USE_PATCHABLE_FUN <<
211 if DYNAMIC_FTRACE_WITH_ARGS <<
212 select HAVE_SAMPLE_FTRACE_DIRECT <<
213 select HAVE_SAMPLE_FTRACE_DIRECT_MULTI <<
214 select HAVE_EFFICIENT_UNALIGNED_ACCESS <<
215 select HAVE_GUP_FAST <<
216 select HAVE_FTRACE_MCOUNT_RECORD 71 select HAVE_FTRACE_MCOUNT_RECORD
217 select HAVE_FUNCTION_TRACER <<
218 select HAVE_FUNCTION_ERROR_INJECTION <<
219 select HAVE_FUNCTION_GRAPH_TRACER 72 select HAVE_FUNCTION_GRAPH_TRACER
220 select HAVE_FUNCTION_GRAPH_RETVAL !! 73 select HAVE_FUNCTION_TRACER
221 select HAVE_GCC_PLUGINS 74 select HAVE_GCC_PLUGINS
222 select HAVE_HARDLOCKUP_DETECTOR_PERF i !! 75 select HAVE_GENERIC_VDSO
223 HW_PERF_EVENTS && HAVE_PERF_EV <<
224 select HAVE_HW_BREAKPOINT if PERF_EVEN <<
225 select HAVE_IOREMAP_PROT 76 select HAVE_IOREMAP_PROT
>> 77 select HAVE_IRQ_EXIT_ON_IRQ_STACK
226 select HAVE_IRQ_TIME_ACCOUNTING 78 select HAVE_IRQ_TIME_ACCOUNTING
>> 79 select HAVE_KPROBES
>> 80 select HAVE_KRETPROBES
>> 81 select HAVE_LD_DEAD_CODE_DATA_ELIMINATION
227 select HAVE_MOD_ARCH_SPECIFIC 82 select HAVE_MOD_ARCH_SPECIFIC
228 select HAVE_NMI 83 select HAVE_NMI
229 select HAVE_PERF_EVENTS 84 select HAVE_PERF_EVENTS
230 select HAVE_PERF_EVENTS_NMI if ARM64_P <<
231 select HAVE_PERF_REGS 85 select HAVE_PERF_REGS
232 select HAVE_PERF_USER_STACK_DUMP 86 select HAVE_PERF_USER_STACK_DUMP
233 select HAVE_PREEMPT_DYNAMIC_KEY <<
234 select HAVE_REGS_AND_STACK_ACCESS_API 87 select HAVE_REGS_AND_STACK_ACCESS_API
235 select HAVE_POSIX_CPU_TIMERS_TASK_WORK <<
236 select HAVE_FUNCTION_ARG_ACCESS_API <<
237 select MMU_GATHER_RCU_TABLE_FREE <<
238 select HAVE_RSEQ 88 select HAVE_RSEQ
239 select HAVE_RUST if RUSTC_SUPPORTS_ARM !! 89 select HAVE_SPARSE_SYSCALL_NR
240 select HAVE_STACKPROTECTOR 90 select HAVE_STACKPROTECTOR
241 select HAVE_SYSCALL_TRACEPOINTS 91 select HAVE_SYSCALL_TRACEPOINTS
242 select HAVE_KPROBES !! 92 select HAVE_VIRT_CPU_ACCOUNTING_GEN if 64BIT || !SMP
243 select HAVE_KRETPROBES <<
244 select HAVE_GENERIC_VDSO <<
245 select HOTPLUG_CORE_SYNC_DEAD if HOTPL <<
246 select IRQ_DOMAIN <<
247 select IRQ_FORCED_THREADING 93 select IRQ_FORCED_THREADING
248 select KASAN_VMALLOC if KASAN !! 94 select ISA if EISA
249 select LOCK_MM_AND_FIND_VMA 95 select LOCK_MM_AND_FIND_VMA
250 select MODULES_USE_ELF_RELA !! 96 select MODULES_USE_ELF_REL if MODULES
251 select NEED_DMA_MAP_STATE !! 97 select MODULES_USE_ELF_RELA if MODULES && 64BIT
252 select NEED_SG_DMA_LENGTH !! 98 select PERF_USE_VMALLOC
253 select OF !! 99 select PCI_MSI_ARCH_FALLBACKS if PCI_MSI
254 select OF_EARLY_FLATTREE !! 100 select RTC_LIB
255 select PCI_DOMAINS_GENERIC if PCI <<
256 select PCI_ECAM if (ACPI && PCI) <<
257 select PCI_SYSCALL if PCI <<
258 select POWER_RESET <<
259 select POWER_SUPPLY <<
260 select SPARSE_IRQ <<
261 select SWIOTLB <<
262 select SYSCTL_EXCEPTION_TRACE 101 select SYSCTL_EXCEPTION_TRACE
263 select THREAD_INFO_IN_TASK <<
264 select HAVE_ARCH_USERFAULTFD_MINOR if <<
265 select HAVE_ARCH_USERFAULTFD_WP if USE <<
266 select TRACE_IRQFLAGS_SUPPORT 102 select TRACE_IRQFLAGS_SUPPORT
267 select TRACE_IRQFLAGS_NMI_SUPPORT !! 103 select ARCH_HAS_ELFCORE_COMPAT
268 select HAVE_SOFTIRQ_ON_OWN_STACK !! 104 select HAVE_ARCH_KCSAN if 64BIT
269 select USER_STACKTRACE_SUPPORT <<
270 select VDSO_GETRANDOM <<
271 help <<
272 ARM 64-bit (AArch64) Linux support. <<
273 <<
274 config RUSTC_SUPPORTS_ARM64 <<
275 def_bool y <<
276 depends on CPU_LITTLE_ENDIAN <<
277 # Shadow call stack is only supported <<
278 # <<
279 # When using the UNWIND_PATCH_PAC_INTO <<
280 # required due to use of the -Zfixed-x <<
281 # <<
282 # Otherwise, rustc version 1.82+ is re <<
283 # -Zsanitizer=shadow-call-stack flag. <<
284 depends on !SHADOW_CALL_STACK || RUSTC <<
285 <<
286 config CLANG_SUPPORTS_DYNAMIC_FTRACE_WITH_ARGS <<
287 def_bool CC_IS_CLANG <<
288 # https://github.com/ClangBuiltLinux/l <<
289 depends on AS_IS_GNU || (AS_IS_LLVM && <<
290 <<
291 config GCC_SUPPORTS_DYNAMIC_FTRACE_WITH_ARGS <<
292 def_bool CC_IS_GCC <<
293 depends on $(cc-option,-fpatchable-fun <<
294 <<
295 config 64BIT <<
296 def_bool y <<
297 <<
298 config MMU <<
299 def_bool y <<
300 105
301 config ARM64_CONT_PTE_SHIFT !! 106 config MIPS_FIXUP_BIGPHYS_ADDR
302 int !! 107 bool
303 default 5 if PAGE_SIZE_64KB <<
304 default 7 if PAGE_SIZE_16KB <<
305 default 4 <<
306 <<
307 config ARM64_CONT_PMD_SHIFT <<
308 int <<
309 default 5 if PAGE_SIZE_64KB <<
310 default 5 if PAGE_SIZE_16KB <<
311 default 4 <<
312 <<
313 config ARCH_MMAP_RND_BITS_MIN <<
314 default 14 if PAGE_SIZE_64KB <<
315 default 16 if PAGE_SIZE_16KB <<
316 default 18 <<
317 108
318 # max bits determined by the following formula !! 109 config MIPS_GENERIC
319 # VA_BITS - PAGE_SHIFT - 3 !! 110 bool
320 config ARCH_MMAP_RND_BITS_MAX <<
321 default 19 if ARM64_VA_BITS=36 <<
322 default 24 if ARM64_VA_BITS=39 <<
323 default 27 if ARM64_VA_BITS=42 <<
324 default 30 if ARM64_VA_BITS=47 <<
325 default 29 if ARM64_VA_BITS=48 && ARM6 <<
326 default 31 if ARM64_VA_BITS=48 && ARM6 <<
327 default 33 if ARM64_VA_BITS=48 <<
328 default 14 if ARM64_64K_PAGES <<
329 default 16 if ARM64_16K_PAGES <<
330 default 18 <<
331 111
332 config ARCH_MMAP_RND_COMPAT_BITS_MIN !! 112 config MACH_INGENIC
333 default 7 if ARM64_64K_PAGES !! 113 bool
334 default 9 if ARM64_16K_PAGES !! 114 select SYS_SUPPORTS_32BIT_KERNEL
335 default 11 !! 115 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 116 select SYS_SUPPORTS_ZBOOT
>> 117 select DMA_NONCOHERENT
>> 118 select IRQ_MIPS_CPU
>> 119 select PINCTRL
>> 120 select GPIOLIB
>> 121 select COMMON_CLK
>> 122 select GENERIC_IRQ_CHIP
>> 123 select BUILTIN_DTB if MIPS_NO_APPENDED_DTB
>> 124 select USE_OF
>> 125 select CPU_SUPPORTS_CPUFREQ
>> 126 select MIPS_EXTERNAL_TIMER
336 127
337 config ARCH_MMAP_RND_COMPAT_BITS_MAX !! 128 menu "Machine selection"
338 default 16 <<
339 129
340 config NO_IOPORT_MAP !! 130 choice
341 def_bool y if !PCI !! 131 prompt "System type"
>> 132 default MIPS_GENERIC_KERNEL
342 133
343 config STACKTRACE_SUPPORT !! 134 config MIPS_GENERIC_KERNEL
344 def_bool y !! 135 bool "Generic board-agnostic MIPS kernel"
>> 136 select MIPS_GENERIC
>> 137 select BOOT_RAW
>> 138 select BUILTIN_DTB
>> 139 select CEVT_R4K
>> 140 select CLKSRC_MIPS_GIC
>> 141 select COMMON_CLK
>> 142 select CPU_MIPSR2_IRQ_EI
>> 143 select CPU_MIPSR2_IRQ_VI
>> 144 select CSRC_R4K
>> 145 select DMA_NONCOHERENT
>> 146 select HAVE_PCI
>> 147 select IRQ_MIPS_CPU
>> 148 select MIPS_AUTO_PFN_OFFSET
>> 149 select MIPS_CPU_SCACHE
>> 150 select MIPS_GIC
>> 151 select MIPS_L1_CACHE_SHIFT_7
>> 152 select NO_EXCEPT_FILL
>> 153 select PCI_DRIVERS_GENERIC
>> 154 select SMP_UP if SMP
>> 155 select SWAP_IO_SPACE
>> 156 select SYS_HAS_CPU_MIPS32_R1
>> 157 select SYS_HAS_CPU_MIPS32_R2
>> 158 select SYS_HAS_CPU_MIPS32_R5
>> 159 select SYS_HAS_CPU_MIPS32_R6
>> 160 select SYS_HAS_CPU_MIPS64_R1
>> 161 select SYS_HAS_CPU_MIPS64_R2
>> 162 select SYS_HAS_CPU_MIPS64_R5
>> 163 select SYS_HAS_CPU_MIPS64_R6
>> 164 select SYS_SUPPORTS_32BIT_KERNEL
>> 165 select SYS_SUPPORTS_64BIT_KERNEL
>> 166 select SYS_SUPPORTS_BIG_ENDIAN
>> 167 select SYS_SUPPORTS_HIGHMEM
>> 168 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 169 select SYS_SUPPORTS_MICROMIPS
>> 170 select SYS_SUPPORTS_MIPS16
>> 171 select SYS_SUPPORTS_MIPS_CPS
>> 172 select SYS_SUPPORTS_MULTITHREADING
>> 173 select SYS_SUPPORTS_RELOCATABLE
>> 174 select SYS_SUPPORTS_SMARTMIPS
>> 175 select SYS_SUPPORTS_ZBOOT
>> 176 select UHI_BOOT
>> 177 select USB_EHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
>> 178 select USB_EHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 179 select USB_OHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
>> 180 select USB_OHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 181 select USB_UHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
>> 182 select USB_UHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 183 select USE_OF
>> 184 help
>> 185 Select this to build a kernel which aims to support multiple boards,
>> 186 generally using a flattened device tree passed from the bootloader
>> 187 using the boot protocol defined in the UHI (Unified Hosting
>> 188 Interface) specification.
>> 189
>> 190 config MIPS_ALCHEMY
>> 191 bool "Alchemy processor based machines"
>> 192 select PHYS_ADDR_T_64BIT
>> 193 select CEVT_R4K
>> 194 select CSRC_R4K
>> 195 select IRQ_MIPS_CPU
>> 196 select DMA_NONCOHERENT # Au1000,1500,1100 aren't, rest is
>> 197 select MIPS_FIXUP_BIGPHYS_ADDR if PCI
>> 198 select SYS_HAS_CPU_MIPS32_R1
>> 199 select SYS_SUPPORTS_32BIT_KERNEL
>> 200 select SYS_SUPPORTS_APM_EMULATION
>> 201 select GPIOLIB
>> 202 select SYS_SUPPORTS_ZBOOT
>> 203 select COMMON_CLK
345 204
346 config ILLEGAL_POINTER_VALUE !! 205 config ATH25
347 hex !! 206 bool "Atheros AR231x/AR531x SoC support"
348 default 0xdead000000000000 !! 207 select CEVT_R4K
>> 208 select CSRC_R4K
>> 209 select DMA_NONCOHERENT
>> 210 select IRQ_MIPS_CPU
>> 211 select IRQ_DOMAIN
>> 212 select SYS_HAS_CPU_MIPS32_R1
>> 213 select SYS_SUPPORTS_BIG_ENDIAN
>> 214 select SYS_SUPPORTS_32BIT_KERNEL
>> 215 select SYS_HAS_EARLY_PRINTK
>> 216 help
>> 217 Support for Atheros AR231x and Atheros AR531x based boards
>> 218
>> 219 config ATH79
>> 220 bool "Atheros AR71XX/AR724X/AR913X based boards"
>> 221 select ARCH_HAS_RESET_CONTROLLER
>> 222 select BOOT_RAW
>> 223 select CEVT_R4K
>> 224 select CSRC_R4K
>> 225 select DMA_NONCOHERENT
>> 226 select GPIOLIB
>> 227 select PINCTRL
>> 228 select COMMON_CLK
>> 229 select IRQ_MIPS_CPU
>> 230 select SYS_HAS_CPU_MIPS32_R2
>> 231 select SYS_HAS_EARLY_PRINTK
>> 232 select SYS_SUPPORTS_32BIT_KERNEL
>> 233 select SYS_SUPPORTS_BIG_ENDIAN
>> 234 select SYS_SUPPORTS_MIPS16
>> 235 select SYS_SUPPORTS_ZBOOT_UART_PROM
>> 236 select USE_OF
>> 237 select USB_EHCI_ROOT_HUB_TT if USB_EHCI_HCD_PLATFORM
>> 238 help
>> 239 Support for the Atheros AR71XX/AR724X/AR913X SoCs.
>> 240
>> 241 config BMIPS_GENERIC
>> 242 bool "Broadcom Generic BMIPS kernel"
>> 243 select ARCH_HAS_RESET_CONTROLLER
>> 244 select ARCH_HAS_SYNC_DMA_FOR_CPU_ALL
>> 245 select BOOT_RAW
>> 246 select NO_EXCEPT_FILL
>> 247 select USE_OF
>> 248 select CEVT_R4K
>> 249 select CSRC_R4K
>> 250 select SYNC_R4K
>> 251 select COMMON_CLK
>> 252 select BCM6345_L1_IRQ
>> 253 select BCM7038_L1_IRQ
>> 254 select BCM7120_L2_IRQ
>> 255 select BRCMSTB_L2_IRQ
>> 256 select IRQ_MIPS_CPU
>> 257 select DMA_NONCOHERENT
>> 258 select SYS_SUPPORTS_32BIT_KERNEL
>> 259 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 260 select SYS_SUPPORTS_BIG_ENDIAN
>> 261 select SYS_SUPPORTS_HIGHMEM
>> 262 select SYS_HAS_CPU_BMIPS32_3300
>> 263 select SYS_HAS_CPU_BMIPS4350
>> 264 select SYS_HAS_CPU_BMIPS4380
>> 265 select SYS_HAS_CPU_BMIPS5000
>> 266 select SWAP_IO_SPACE
>> 267 select USB_EHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
>> 268 select USB_EHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 269 select USB_OHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
>> 270 select USB_OHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 271 select HARDIRQS_SW_RESEND
>> 272 select HAVE_PCI
>> 273 select PCI_DRIVERS_GENERIC
>> 274 select FW_CFE
>> 275 help
>> 276 Build a generic DT-based kernel image that boots on select
>> 277 BCM33xx cable modem chips, BCM63xx DSL chips, and BCM7xxx set-top
>> 278 box chips. Note that CONFIG_CPU_BIG_ENDIAN/CONFIG_CPU_LITTLE_ENDIAN
>> 279 must be set appropriately for your board.
>> 280
>> 281 config BCM47XX
>> 282 bool "Broadcom BCM47XX based boards"
>> 283 select BOOT_RAW
>> 284 select CEVT_R4K
>> 285 select CSRC_R4K
>> 286 select DMA_NONCOHERENT
>> 287 select HAVE_PCI
>> 288 select IRQ_MIPS_CPU
>> 289 select SYS_HAS_CPU_MIPS32_R1
>> 290 select NO_EXCEPT_FILL
>> 291 select SYS_SUPPORTS_32BIT_KERNEL
>> 292 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 293 select SYS_SUPPORTS_MIPS16
>> 294 select SYS_SUPPORTS_ZBOOT
>> 295 select SYS_HAS_EARLY_PRINTK
>> 296 select USE_GENERIC_EARLY_PRINTK_8250
>> 297 select GPIOLIB
>> 298 select LEDS_GPIO_REGISTER
>> 299 select BCM47XX_NVRAM
>> 300 select BCM47XX_SPROM
>> 301 select BCM47XX_SSB if !BCM47XX_BCMA
>> 302 help
>> 303 Support for BCM47XX based boards
>> 304
>> 305 config BCM63XX
>> 306 bool "Broadcom BCM63XX based boards"
>> 307 select BOOT_RAW
>> 308 select CEVT_R4K
>> 309 select CSRC_R4K
>> 310 select SYNC_R4K
>> 311 select DMA_NONCOHERENT
>> 312 select IRQ_MIPS_CPU
>> 313 select SYS_SUPPORTS_32BIT_KERNEL
>> 314 select SYS_SUPPORTS_BIG_ENDIAN
>> 315 select SYS_HAS_EARLY_PRINTK
>> 316 select SYS_HAS_CPU_BMIPS32_3300
>> 317 select SYS_HAS_CPU_BMIPS4350
>> 318 select SYS_HAS_CPU_BMIPS4380
>> 319 select SWAP_IO_SPACE
>> 320 select GPIOLIB
>> 321 select MIPS_L1_CACHE_SHIFT_4
>> 322 select HAVE_LEGACY_CLK
>> 323 help
>> 324 Support for BCM63XX based boards
>> 325
>> 326 config MIPS_COBALT
>> 327 bool "Cobalt Server"
>> 328 select CEVT_R4K
>> 329 select CSRC_R4K
>> 330 select CEVT_GT641XX
>> 331 select DMA_NONCOHERENT
>> 332 select FORCE_PCI
>> 333 select I8253
>> 334 select I8259
>> 335 select IRQ_MIPS_CPU
>> 336 select IRQ_GT641XX
>> 337 select PCI_GT64XXX_PCI0
>> 338 select SYS_HAS_CPU_NEVADA
>> 339 select SYS_HAS_EARLY_PRINTK
>> 340 select SYS_SUPPORTS_32BIT_KERNEL
>> 341 select SYS_SUPPORTS_64BIT_KERNEL
>> 342 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 343 select USE_GENERIC_EARLY_PRINTK_8250
>> 344
>> 345 config MACH_DECSTATION
>> 346 bool "DECstations"
>> 347 select BOOT_ELF32
>> 348 select CEVT_DS1287
>> 349 select CEVT_R4K if CPU_R4X00
>> 350 select CSRC_IOASIC
>> 351 select CSRC_R4K if CPU_R4X00
>> 352 select CPU_DADDI_WORKAROUNDS if 64BIT
>> 353 select CPU_R4000_WORKAROUNDS if 64BIT
>> 354 select CPU_R4400_WORKAROUNDS if 64BIT
>> 355 select DMA_NONCOHERENT
>> 356 select NO_IOPORT_MAP
>> 357 select IRQ_MIPS_CPU
>> 358 select SYS_HAS_CPU_R3000
>> 359 select SYS_HAS_CPU_R4X00
>> 360 select SYS_SUPPORTS_32BIT_KERNEL
>> 361 select SYS_SUPPORTS_64BIT_KERNEL
>> 362 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 363 select SYS_SUPPORTS_128HZ
>> 364 select SYS_SUPPORTS_256HZ
>> 365 select SYS_SUPPORTS_1024HZ
>> 366 select MIPS_L1_CACHE_SHIFT_4
>> 367 help
>> 368 This enables support for DEC's MIPS based workstations. For details
>> 369 see the Linux/MIPS FAQ on <http://www.linux-mips.org/> and the
>> 370 DECstation porting pages on <http://decstation.unix-ag.org/>.
>> 371
>> 372 If you have one of the following DECstation Models you definitely
>> 373 want to choose R4xx0 for the CPU Type:
>> 374
>> 375 DECstation 5000/50
>> 376 DECstation 5000/150
>> 377 DECstation 5000/260
>> 378 DECsystem 5900/260
>> 379
>> 380 otherwise choose R3000.
>> 381
>> 382 config MACH_JAZZ
>> 383 bool "Jazz family of machines"
>> 384 select ARC_MEMORY
>> 385 select ARC_PROMLIB
>> 386 select ARCH_MIGHT_HAVE_PC_PARPORT
>> 387 select ARCH_MIGHT_HAVE_PC_SERIO
>> 388 select DMA_OPS
>> 389 select FW_ARC
>> 390 select FW_ARC32
>> 391 select ARCH_MAY_HAVE_PC_FDC
>> 392 select CEVT_R4K
>> 393 select CSRC_R4K
>> 394 select DEFAULT_SGI_PARTITION if CPU_BIG_ENDIAN
>> 395 select GENERIC_ISA_DMA
>> 396 select HAVE_PCSPKR_PLATFORM
>> 397 select IRQ_MIPS_CPU
>> 398 select I8253
>> 399 select I8259
>> 400 select ISA
>> 401 select SYS_HAS_CPU_R4X00
>> 402 select SYS_SUPPORTS_32BIT_KERNEL
>> 403 select SYS_SUPPORTS_64BIT_KERNEL
>> 404 select SYS_SUPPORTS_100HZ
>> 405 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 406 help
>> 407 This a family of machines based on the MIPS R4030 chipset which was
>> 408 used by several vendors to build RISC/os and Windows NT workstations.
>> 409 Members include the Acer PICA, MIPS Magnum 4000, MIPS Millennium and
>> 410 Olivetti M700-10 workstations.
>> 411
>> 412 config MACH_INGENIC_SOC
>> 413 bool "Ingenic SoC based machines"
>> 414 select MIPS_GENERIC
>> 415 select MACH_INGENIC
>> 416 select SYS_SUPPORTS_ZBOOT_UART16550
>> 417 select CPU_SUPPORTS_CPUFREQ
>> 418 select MIPS_EXTERNAL_TIMER
>> 419
>> 420 config LANTIQ
>> 421 bool "Lantiq based platforms"
>> 422 select DMA_NONCOHERENT
>> 423 select IRQ_MIPS_CPU
>> 424 select CEVT_R4K
>> 425 select CSRC_R4K
>> 426 select NO_EXCEPT_FILL
>> 427 select SYS_HAS_CPU_MIPS32_R1
>> 428 select SYS_HAS_CPU_MIPS32_R2
>> 429 select SYS_SUPPORTS_BIG_ENDIAN
>> 430 select SYS_SUPPORTS_32BIT_KERNEL
>> 431 select SYS_SUPPORTS_MIPS16
>> 432 select SYS_SUPPORTS_MULTITHREADING
>> 433 select SYS_SUPPORTS_VPE_LOADER
>> 434 select SYS_HAS_EARLY_PRINTK
>> 435 select GPIOLIB
>> 436 select SWAP_IO_SPACE
>> 437 select BOOT_RAW
>> 438 select HAVE_LEGACY_CLK
>> 439 select USE_OF
>> 440 select PINCTRL
>> 441 select PINCTRL_LANTIQ
>> 442 select ARCH_HAS_RESET_CONTROLLER
>> 443 select RESET_CONTROLLER
>> 444
>> 445 config MACH_LOONGSON32
>> 446 bool "Loongson 32-bit family of machines"
>> 447 select SYS_SUPPORTS_ZBOOT
>> 448 help
>> 449 This enables support for the Loongson-1 family of machines.
>> 450
>> 451 Loongson-1 is a family of 32-bit MIPS-compatible SoCs developed by
>> 452 the Institute of Computing Technology (ICT), Chinese Academy of
>> 453 Sciences (CAS).
>> 454
>> 455 config MACH_LOONGSON2EF
>> 456 bool "Loongson-2E/F family of machines"
>> 457 select SYS_SUPPORTS_ZBOOT
>> 458 help
>> 459 This enables the support of early Loongson-2E/F family of machines.
>> 460
>> 461 config MACH_LOONGSON64
>> 462 bool "Loongson 64-bit family of machines"
>> 463 select ARCH_DMA_DEFAULT_COHERENT
>> 464 select ARCH_SPARSEMEM_ENABLE
>> 465 select ARCH_MIGHT_HAVE_PC_PARPORT
>> 466 select ARCH_MIGHT_HAVE_PC_SERIO
>> 467 select GENERIC_ISA_DMA_SUPPORT_BROKEN
>> 468 select BOOT_ELF32
>> 469 select BOARD_SCACHE
>> 470 select CSRC_R4K
>> 471 select CEVT_R4K
>> 472 select FORCE_PCI
>> 473 select ISA
>> 474 select I8259
>> 475 select IRQ_MIPS_CPU
>> 476 select NO_EXCEPT_FILL
>> 477 select NR_CPUS_DEFAULT_64
>> 478 select USE_GENERIC_EARLY_PRINTK_8250
>> 479 select PCI_DRIVERS_GENERIC
>> 480 select SYS_HAS_CPU_LOONGSON64
>> 481 select SYS_HAS_EARLY_PRINTK
>> 482 select SYS_SUPPORTS_SMP
>> 483 select SYS_SUPPORTS_HOTPLUG_CPU
>> 484 select SYS_SUPPORTS_NUMA
>> 485 select SYS_SUPPORTS_64BIT_KERNEL
>> 486 select SYS_SUPPORTS_HIGHMEM
>> 487 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 488 select SYS_SUPPORTS_ZBOOT
>> 489 select SYS_SUPPORTS_RELOCATABLE
>> 490 select ZONE_DMA32
>> 491 select COMMON_CLK
>> 492 select USE_OF
>> 493 select BUILTIN_DTB
>> 494 select PCI_HOST_GENERIC
>> 495 select HAVE_ARCH_NODEDATA_EXTENSION if NUMA
>> 496 help
>> 497 This enables the support of Loongson-2/3 family of machines.
>> 498
>> 499 Loongson-2 and Loongson-3 are 64-bit general-purpose processors with
>> 500 GS264/GS464/GS464E/GS464V microarchitecture (except old Loongson-2E
>> 501 and Loongson-2F which will be removed), developed by the Institute
>> 502 of Computing Technology (ICT), Chinese Academy of Sciences (CAS).
>> 503
>> 504 config MIPS_MALTA
>> 505 bool "MIPS Malta board"
>> 506 select ARCH_MAY_HAVE_PC_FDC
>> 507 select ARCH_MIGHT_HAVE_PC_PARPORT
>> 508 select ARCH_MIGHT_HAVE_PC_SERIO
>> 509 select BOOT_ELF32
>> 510 select BOOT_RAW
>> 511 select BUILTIN_DTB
>> 512 select CEVT_R4K
>> 513 select CLKSRC_MIPS_GIC
>> 514 select COMMON_CLK
>> 515 select CSRC_R4K
>> 516 select DMA_NONCOHERENT
>> 517 select GENERIC_ISA_DMA
>> 518 select HAVE_PCSPKR_PLATFORM
>> 519 select HAVE_PCI
>> 520 select I8253
>> 521 select I8259
>> 522 select IRQ_MIPS_CPU
>> 523 select MIPS_BONITO64
>> 524 select MIPS_CPU_SCACHE
>> 525 select MIPS_GIC
>> 526 select MIPS_L1_CACHE_SHIFT_6
>> 527 select MIPS_MSC
>> 528 select PCI_GT64XXX_PCI0
>> 529 select SMP_UP if SMP
>> 530 select SWAP_IO_SPACE
>> 531 select SYS_HAS_CPU_MIPS32_R1
>> 532 select SYS_HAS_CPU_MIPS32_R2
>> 533 select SYS_HAS_CPU_MIPS32_R3_5
>> 534 select SYS_HAS_CPU_MIPS32_R5
>> 535 select SYS_HAS_CPU_MIPS32_R6
>> 536 select SYS_HAS_CPU_MIPS64_R1
>> 537 select SYS_HAS_CPU_MIPS64_R2
>> 538 select SYS_HAS_CPU_MIPS64_R6
>> 539 select SYS_HAS_CPU_NEVADA
>> 540 select SYS_HAS_CPU_RM7000
>> 541 select SYS_SUPPORTS_32BIT_KERNEL
>> 542 select SYS_SUPPORTS_64BIT_KERNEL
>> 543 select SYS_SUPPORTS_BIG_ENDIAN
>> 544 select SYS_SUPPORTS_HIGHMEM
>> 545 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 546 select SYS_SUPPORTS_MICROMIPS
>> 547 select SYS_SUPPORTS_MIPS16
>> 548 select SYS_SUPPORTS_MIPS_CPS
>> 549 select SYS_SUPPORTS_MULTITHREADING
>> 550 select SYS_SUPPORTS_RELOCATABLE
>> 551 select SYS_SUPPORTS_SMARTMIPS
>> 552 select SYS_SUPPORTS_VPE_LOADER
>> 553 select SYS_SUPPORTS_ZBOOT
>> 554 select USE_OF
>> 555 select WAR_ICACHE_REFILLS
>> 556 select ZONE_DMA32 if 64BIT
>> 557 help
>> 558 This enables support for the MIPS Technologies Malta evaluation
>> 559 board.
>> 560
>> 561 config MACH_PIC32
>> 562 bool "Microchip PIC32 Family"
>> 563 help
>> 564 This enables support for the Microchip PIC32 family of platforms.
>> 565
>> 566 Microchip PIC32 is a family of general-purpose 32 bit MIPS core
>> 567 microcontrollers.
>> 568
>> 569 config MACH_NINTENDO64
>> 570 bool "Nintendo 64 console"
>> 571 select CEVT_R4K
>> 572 select CSRC_R4K
>> 573 select SYS_HAS_CPU_R4300
>> 574 select SYS_SUPPORTS_BIG_ENDIAN
>> 575 select SYS_SUPPORTS_ZBOOT
>> 576 select SYS_SUPPORTS_32BIT_KERNEL
>> 577 select SYS_SUPPORTS_64BIT_KERNEL
>> 578 select DMA_NONCOHERENT
>> 579 select IRQ_MIPS_CPU
>> 580
>> 581 config RALINK
>> 582 bool "Ralink based machines"
>> 583 select CEVT_R4K
>> 584 select COMMON_CLK
>> 585 select CSRC_R4K
>> 586 select BOOT_RAW
>> 587 select DMA_NONCOHERENT
>> 588 select IRQ_MIPS_CPU
>> 589 select USE_OF
>> 590 select SYS_HAS_CPU_MIPS32_R2
>> 591 select SYS_SUPPORTS_32BIT_KERNEL
>> 592 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 593 select SYS_SUPPORTS_MIPS16
>> 594 select SYS_SUPPORTS_ZBOOT
>> 595 select SYS_HAS_EARLY_PRINTK
>> 596 select ARCH_HAS_RESET_CONTROLLER
>> 597 select RESET_CONTROLLER
>> 598
>> 599 config MACH_REALTEK_RTL
>> 600 bool "Realtek RTL838x/RTL839x based machines"
>> 601 select MIPS_GENERIC
>> 602 select DMA_NONCOHERENT
>> 603 select IRQ_MIPS_CPU
>> 604 select CSRC_R4K
>> 605 select CEVT_R4K
>> 606 select SYS_HAS_CPU_MIPS32_R1
>> 607 select SYS_HAS_CPU_MIPS32_R2
>> 608 select SYS_SUPPORTS_BIG_ENDIAN
>> 609 select SYS_SUPPORTS_32BIT_KERNEL
>> 610 select SYS_SUPPORTS_MIPS16
>> 611 select SYS_SUPPORTS_MULTITHREADING
>> 612 select SYS_SUPPORTS_VPE_LOADER
>> 613 select BOOT_RAW
>> 614 select PINCTRL
>> 615 select USE_OF
>> 616
>> 617 config SGI_IP22
>> 618 bool "SGI IP22 (Indy/Indigo2)"
>> 619 select ARC_MEMORY
>> 620 select ARC_PROMLIB
>> 621 select FW_ARC
>> 622 select FW_ARC32
>> 623 select ARCH_MIGHT_HAVE_PC_SERIO
>> 624 select BOOT_ELF32
>> 625 select CEVT_R4K
>> 626 select CSRC_R4K
>> 627 select DEFAULT_SGI_PARTITION
>> 628 select DMA_NONCOHERENT
>> 629 select HAVE_EISA
>> 630 select I8253
>> 631 select I8259
>> 632 select IP22_CPU_SCACHE
>> 633 select IRQ_MIPS_CPU
>> 634 select GENERIC_ISA_DMA_SUPPORT_BROKEN
>> 635 select SGI_HAS_I8042
>> 636 select SGI_HAS_INDYDOG
>> 637 select SGI_HAS_HAL2
>> 638 select SGI_HAS_SEEQ
>> 639 select SGI_HAS_WD93
>> 640 select SGI_HAS_ZILOG
>> 641 select SWAP_IO_SPACE
>> 642 select SYS_HAS_CPU_R4X00
>> 643 select SYS_HAS_CPU_R5000
>> 644 select SYS_HAS_EARLY_PRINTK
>> 645 select SYS_SUPPORTS_32BIT_KERNEL
>> 646 select SYS_SUPPORTS_64BIT_KERNEL
>> 647 select SYS_SUPPORTS_BIG_ENDIAN
>> 648 select WAR_R4600_V1_INDEX_ICACHEOP
>> 649 select WAR_R4600_V1_HIT_CACHEOP
>> 650 select WAR_R4600_V2_HIT_CACHEOP
>> 651 select MIPS_L1_CACHE_SHIFT_7
>> 652 help
>> 653 This are the SGI Indy, Challenge S and Indigo2, as well as certain
>> 654 OEM variants like the Tandem CMN B006S. To compile a Linux kernel
>> 655 that runs on these, say Y here.
>> 656
>> 657 config SGI_IP27
>> 658 bool "SGI IP27 (Origin200/2000)"
>> 659 select ARCH_HAS_PHYS_TO_DMA
>> 660 select ARCH_SPARSEMEM_ENABLE
>> 661 select FW_ARC
>> 662 select FW_ARC64
>> 663 select ARC_CMDLINE_ONLY
>> 664 select BOOT_ELF64
>> 665 select DEFAULT_SGI_PARTITION
>> 666 select FORCE_PCI
>> 667 select SYS_HAS_EARLY_PRINTK
>> 668 select HAVE_PCI
>> 669 select IRQ_MIPS_CPU
>> 670 select IRQ_DOMAIN_HIERARCHY
>> 671 select NR_CPUS_DEFAULT_64
>> 672 select PCI_DRIVERS_GENERIC
>> 673 select PCI_XTALK_BRIDGE
>> 674 select SYS_HAS_CPU_R10000
>> 675 select SYS_SUPPORTS_64BIT_KERNEL
>> 676 select SYS_SUPPORTS_BIG_ENDIAN
>> 677 select SYS_SUPPORTS_NUMA
>> 678 select SYS_SUPPORTS_SMP
>> 679 select WAR_R10000_LLSC
>> 680 select MIPS_L1_CACHE_SHIFT_7
>> 681 select NUMA
>> 682 select HAVE_ARCH_NODEDATA_EXTENSION
>> 683 help
>> 684 This are the SGI Origin 200, Origin 2000 and Onyx 2 Graphics
>> 685 workstations. To compile a Linux kernel that runs on these, say Y
>> 686 here.
>> 687
>> 688 config SGI_IP28
>> 689 bool "SGI IP28 (Indigo2 R10k)"
>> 690 select ARC_MEMORY
>> 691 select ARC_PROMLIB
>> 692 select FW_ARC
>> 693 select FW_ARC64
>> 694 select ARCH_MIGHT_HAVE_PC_SERIO
>> 695 select BOOT_ELF64
>> 696 select CEVT_R4K
>> 697 select CSRC_R4K
>> 698 select DEFAULT_SGI_PARTITION
>> 699 select DMA_NONCOHERENT
>> 700 select GENERIC_ISA_DMA_SUPPORT_BROKEN
>> 701 select IRQ_MIPS_CPU
>> 702 select HAVE_EISA
>> 703 select I8253
>> 704 select I8259
>> 705 select SGI_HAS_I8042
>> 706 select SGI_HAS_INDYDOG
>> 707 select SGI_HAS_HAL2
>> 708 select SGI_HAS_SEEQ
>> 709 select SGI_HAS_WD93
>> 710 select SGI_HAS_ZILOG
>> 711 select SWAP_IO_SPACE
>> 712 select SYS_HAS_CPU_R10000
>> 713 select SYS_HAS_EARLY_PRINTK
>> 714 select SYS_SUPPORTS_64BIT_KERNEL
>> 715 select SYS_SUPPORTS_BIG_ENDIAN
>> 716 select WAR_R10000_LLSC
>> 717 select MIPS_L1_CACHE_SHIFT_7
>> 718 help
>> 719 This is the SGI Indigo2 with R10000 processor. To compile a Linux
>> 720 kernel that runs on these, say Y here.
>> 721
>> 722 config SGI_IP30
>> 723 bool "SGI IP30 (Octane/Octane2)"
>> 724 select ARCH_HAS_PHYS_TO_DMA
>> 725 select FW_ARC
>> 726 select FW_ARC64
>> 727 select BOOT_ELF64
>> 728 select CEVT_R4K
>> 729 select CSRC_R4K
>> 730 select FORCE_PCI
>> 731 select SYNC_R4K if SMP
>> 732 select ZONE_DMA32
>> 733 select HAVE_PCI
>> 734 select IRQ_MIPS_CPU
>> 735 select IRQ_DOMAIN_HIERARCHY
>> 736 select PCI_DRIVERS_GENERIC
>> 737 select PCI_XTALK_BRIDGE
>> 738 select SYS_HAS_EARLY_PRINTK
>> 739 select SYS_HAS_CPU_R10000
>> 740 select SYS_SUPPORTS_64BIT_KERNEL
>> 741 select SYS_SUPPORTS_BIG_ENDIAN
>> 742 select SYS_SUPPORTS_SMP
>> 743 select WAR_R10000_LLSC
>> 744 select MIPS_L1_CACHE_SHIFT_7
>> 745 select ARC_MEMORY
>> 746 help
>> 747 These are the SGI Octane and Octane2 graphics workstations. To
>> 748 compile a Linux kernel that runs on these, say Y here.
>> 749
>> 750 config SGI_IP32
>> 751 bool "SGI IP32 (O2)"
>> 752 select ARC_MEMORY
>> 753 select ARC_PROMLIB
>> 754 select ARCH_HAS_PHYS_TO_DMA
>> 755 select FW_ARC
>> 756 select FW_ARC32
>> 757 select BOOT_ELF32
>> 758 select CEVT_R4K
>> 759 select CSRC_R4K
>> 760 select DMA_NONCOHERENT
>> 761 select HAVE_PCI
>> 762 select IRQ_MIPS_CPU
>> 763 select R5000_CPU_SCACHE
>> 764 select RM7000_CPU_SCACHE
>> 765 select SYS_HAS_CPU_R5000
>> 766 select SYS_HAS_CPU_R10000 if BROKEN
>> 767 select SYS_HAS_CPU_RM7000
>> 768 select SYS_HAS_CPU_NEVADA
>> 769 select SYS_SUPPORTS_64BIT_KERNEL
>> 770 select SYS_SUPPORTS_BIG_ENDIAN
>> 771 select WAR_ICACHE_REFILLS
>> 772 help
>> 773 If you want this kernel to run on SGI O2 workstation, say Y here.
>> 774
>> 775 config SIBYTE_CRHONE
>> 776 bool "Sibyte BCM91125C-CRhone"
>> 777 select BOOT_ELF32
>> 778 select SIBYTE_BCM1125
>> 779 select SWAP_IO_SPACE
>> 780 select SYS_HAS_CPU_SB1
>> 781 select SYS_SUPPORTS_BIG_ENDIAN
>> 782 select SYS_SUPPORTS_HIGHMEM
>> 783 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 784
>> 785 config SIBYTE_RHONE
>> 786 bool "Sibyte BCM91125E-Rhone"
>> 787 select BOOT_ELF32
>> 788 select SIBYTE_SB1250
>> 789 select SWAP_IO_SPACE
>> 790 select SYS_HAS_CPU_SB1
>> 791 select SYS_SUPPORTS_BIG_ENDIAN
>> 792 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 793
>> 794 config SIBYTE_SWARM
>> 795 bool "Sibyte BCM91250A-SWARM"
>> 796 select BOOT_ELF32
>> 797 select HAVE_PATA_PLATFORM
>> 798 select SIBYTE_SB1250
>> 799 select SWAP_IO_SPACE
>> 800 select SYS_HAS_CPU_SB1
>> 801 select SYS_SUPPORTS_BIG_ENDIAN
>> 802 select SYS_SUPPORTS_HIGHMEM
>> 803 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 804 select ZONE_DMA32 if 64BIT
>> 805 select SWIOTLB if ARCH_DMA_ADDR_T_64BIT && PCI
>> 806
>> 807 config SIBYTE_LITTLESUR
>> 808 bool "Sibyte BCM91250C2-LittleSur"
>> 809 select BOOT_ELF32
>> 810 select HAVE_PATA_PLATFORM
>> 811 select SIBYTE_SB1250
>> 812 select SWAP_IO_SPACE
>> 813 select SYS_HAS_CPU_SB1
>> 814 select SYS_SUPPORTS_BIG_ENDIAN
>> 815 select SYS_SUPPORTS_HIGHMEM
>> 816 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 817 select ZONE_DMA32 if 64BIT
>> 818
>> 819 config SIBYTE_SENTOSA
>> 820 bool "Sibyte BCM91250E-Sentosa"
>> 821 select BOOT_ELF32
>> 822 select SIBYTE_SB1250
>> 823 select SWAP_IO_SPACE
>> 824 select SYS_HAS_CPU_SB1
>> 825 select SYS_SUPPORTS_BIG_ENDIAN
>> 826 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 827 select SWIOTLB if ARCH_DMA_ADDR_T_64BIT && PCI
>> 828
>> 829 config SIBYTE_BIGSUR
>> 830 bool "Sibyte BCM91480B-BigSur"
>> 831 select BOOT_ELF32
>> 832 select NR_CPUS_DEFAULT_4
>> 833 select SIBYTE_BCM1x80
>> 834 select SWAP_IO_SPACE
>> 835 select SYS_HAS_CPU_SB1
>> 836 select SYS_SUPPORTS_BIG_ENDIAN
>> 837 select SYS_SUPPORTS_HIGHMEM
>> 838 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 839 select ZONE_DMA32 if 64BIT
>> 840 select SWIOTLB if ARCH_DMA_ADDR_T_64BIT && PCI
>> 841
>> 842 config SNI_RM
>> 843 bool "SNI RM200/300/400"
>> 844 select ARC_MEMORY
>> 845 select ARC_PROMLIB
>> 846 select FW_ARC if CPU_LITTLE_ENDIAN
>> 847 select FW_ARC32 if CPU_LITTLE_ENDIAN
>> 848 select FW_SNIPROM if CPU_BIG_ENDIAN
>> 849 select ARCH_MAY_HAVE_PC_FDC
>> 850 select ARCH_MIGHT_HAVE_PC_PARPORT
>> 851 select ARCH_MIGHT_HAVE_PC_SERIO
>> 852 select BOOT_ELF32
>> 853 select CEVT_R4K
>> 854 select CSRC_R4K
>> 855 select DEFAULT_SGI_PARTITION if CPU_BIG_ENDIAN
>> 856 select DMA_NONCOHERENT
>> 857 select GENERIC_ISA_DMA
>> 858 select HAVE_EISA
>> 859 select HAVE_PCSPKR_PLATFORM
>> 860 select HAVE_PCI
>> 861 select IRQ_MIPS_CPU
>> 862 select I8253
>> 863 select I8259
>> 864 select ISA
>> 865 select MIPS_L1_CACHE_SHIFT_6
>> 866 select SWAP_IO_SPACE if CPU_BIG_ENDIAN
>> 867 select SYS_HAS_CPU_R4X00
>> 868 select SYS_HAS_CPU_R5000
>> 869 select SYS_HAS_CPU_R10000
>> 870 select R5000_CPU_SCACHE
>> 871 select SYS_HAS_EARLY_PRINTK
>> 872 select SYS_SUPPORTS_32BIT_KERNEL
>> 873 select SYS_SUPPORTS_64BIT_KERNEL
>> 874 select SYS_SUPPORTS_BIG_ENDIAN
>> 875 select SYS_SUPPORTS_HIGHMEM
>> 876 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 877 select WAR_R4600_V2_HIT_CACHEOP
>> 878 help
>> 879 The SNI RM200/300/400 are MIPS-based machines manufactured by
>> 880 Siemens Nixdorf Informationssysteme (SNI), parent company of Pyramid
>> 881 Technology and now in turn merged with Fujitsu. Say Y here to
>> 882 support this machine type.
>> 883
>> 884 config MACH_TX49XX
>> 885 bool "Toshiba TX49 series based machines"
>> 886 select WAR_TX49XX_ICACHE_INDEX_INV
>> 887
>> 888 config MIKROTIK_RB532
>> 889 bool "Mikrotik RB532 boards"
>> 890 select CEVT_R4K
>> 891 select CSRC_R4K
>> 892 select DMA_NONCOHERENT
>> 893 select HAVE_PCI
>> 894 select IRQ_MIPS_CPU
>> 895 select SYS_HAS_CPU_MIPS32_R1
>> 896 select SYS_SUPPORTS_32BIT_KERNEL
>> 897 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 898 select SWAP_IO_SPACE
>> 899 select BOOT_RAW
>> 900 select GPIOLIB
>> 901 select MIPS_L1_CACHE_SHIFT_4
>> 902 help
>> 903 Support the Mikrotik(tm) RouterBoard 532 series,
>> 904 based on the IDT RC32434 SoC.
>> 905
>> 906 config CAVIUM_OCTEON_SOC
>> 907 bool "Cavium Networks Octeon SoC based boards"
>> 908 select CEVT_R4K
>> 909 select ARCH_HAS_PHYS_TO_DMA
>> 910 select HAVE_RAPIDIO
>> 911 select PHYS_ADDR_T_64BIT
>> 912 select SYS_SUPPORTS_64BIT_KERNEL
>> 913 select SYS_SUPPORTS_BIG_ENDIAN
>> 914 select EDAC_SUPPORT
>> 915 select EDAC_ATOMIC_SCRUB
>> 916 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 917 select SYS_SUPPORTS_HOTPLUG_CPU if CPU_BIG_ENDIAN
>> 918 select SYS_HAS_EARLY_PRINTK
>> 919 select SYS_HAS_CPU_CAVIUM_OCTEON
>> 920 select HAVE_PCI
>> 921 select HAVE_PLAT_DELAY
>> 922 select HAVE_PLAT_FW_INIT_CMDLINE
>> 923 select HAVE_PLAT_MEMCPY
>> 924 select ZONE_DMA32
>> 925 select GPIOLIB
>> 926 select USE_OF
>> 927 select ARCH_SPARSEMEM_ENABLE
>> 928 select SYS_SUPPORTS_SMP
>> 929 select NR_CPUS_DEFAULT_64
>> 930 select MIPS_NR_CPU_NR_MAP_1024
>> 931 select BUILTIN_DTB
>> 932 select MTD
>> 933 select MTD_COMPLEX_MAPPINGS
>> 934 select SWIOTLB
>> 935 select SYS_SUPPORTS_RELOCATABLE
>> 936 help
>> 937 This option supports all of the Octeon reference boards from Cavium
>> 938 Networks. It builds a kernel that dynamically determines the Octeon
>> 939 CPU type and supports all known board reference implementations.
>> 940 Some of the supported boards are:
>> 941 EBT3000
>> 942 EBH3000
>> 943 EBH3100
>> 944 Thunder
>> 945 Kodama
>> 946 Hikari
>> 947 Say Y here for most Octeon reference boards.
349 948
350 config LOCKDEP_SUPPORT !! 949 endchoice
351 def_bool y <<
352 950
353 config GENERIC_BUG !! 951 source "arch/mips/alchemy/Kconfig"
354 def_bool y !! 952 source "arch/mips/ath25/Kconfig"
355 depends on BUG !! 953 source "arch/mips/ath79/Kconfig"
>> 954 source "arch/mips/bcm47xx/Kconfig"
>> 955 source "arch/mips/bcm63xx/Kconfig"
>> 956 source "arch/mips/bmips/Kconfig"
>> 957 source "arch/mips/generic/Kconfig"
>> 958 source "arch/mips/ingenic/Kconfig"
>> 959 source "arch/mips/jazz/Kconfig"
>> 960 source "arch/mips/lantiq/Kconfig"
>> 961 source "arch/mips/pic32/Kconfig"
>> 962 source "arch/mips/ralink/Kconfig"
>> 963 source "arch/mips/sgi-ip27/Kconfig"
>> 964 source "arch/mips/sibyte/Kconfig"
>> 965 source "arch/mips/txx9/Kconfig"
>> 966 source "arch/mips/cavium-octeon/Kconfig"
>> 967 source "arch/mips/loongson2ef/Kconfig"
>> 968 source "arch/mips/loongson32/Kconfig"
>> 969 source "arch/mips/loongson64/Kconfig"
356 970
357 config GENERIC_BUG_RELATIVE_POINTERS !! 971 endmenu
358 def_bool y <<
359 depends on GENERIC_BUG <<
360 972
361 config GENERIC_HWEIGHT 973 config GENERIC_HWEIGHT
362 def_bool y !! 974 bool
363 !! 975 default y
364 config GENERIC_CSUM <<
365 def_bool y <<
366 976
367 config GENERIC_CALIBRATE_DELAY 977 config GENERIC_CALIBRATE_DELAY
368 def_bool y !! 978 bool
>> 979 default y
369 980
370 config SMP !! 981 config SCHED_OMIT_FRAME_POINTER
371 def_bool y !! 982 bool
>> 983 default y
372 984
373 config KERNEL_MODE_NEON !! 985 #
374 def_bool y !! 986 # Select some configuration options automatically based on user selections.
>> 987 #
>> 988 config FW_ARC
>> 989 bool
375 990
376 config FIX_EARLYCON_MEM !! 991 config ARCH_MAY_HAVE_PC_FDC
377 def_bool y !! 992 bool
378 993
379 config PGTABLE_LEVELS !! 994 config BOOT_RAW
380 int !! 995 bool
381 default 2 if ARM64_16K_PAGES && ARM64_ <<
382 default 2 if ARM64_64K_PAGES && ARM64_ <<
383 default 3 if ARM64_64K_PAGES && (ARM64 <<
384 default 3 if ARM64_4K_PAGES && ARM64_V <<
385 default 3 if ARM64_16K_PAGES && ARM64_ <<
386 default 4 if ARM64_16K_PAGES && (ARM64 <<
387 default 4 if !ARM64_64K_PAGES && ARM64 <<
388 default 5 if ARM64_4K_PAGES && ARM64_V <<
389 996
390 config ARCH_SUPPORTS_UPROBES !! 997 config CEVT_BCM1480
391 def_bool y !! 998 bool
392 999
393 config ARCH_PROC_KCORE_TEXT !! 1000 config CEVT_DS1287
394 def_bool y !! 1001 bool
395 1002
396 config BROKEN_GAS_INST !! 1003 config CEVT_GT641XX
397 def_bool !$(as-instr,1:\n.inst 0\n.rep !! 1004 bool
398 1005
399 config BUILTIN_RETURN_ADDRESS_STRIPS_PAC !! 1006 config CEVT_R4K
400 bool 1007 bool
401 # Clang's __builtin_return_address() s <<
402 # https://github.com/llvm/llvm-project <<
403 default y if CC_IS_CLANG <<
404 # GCC's __builtin_return_address() str <<
405 # and this was backported to 10.2.0, 9 <<
406 # https://gcc.gnu.org/bugzilla/show_bu <<
407 default y if CC_IS_GCC && (GCC_VERSION <<
408 default y if CC_IS_GCC && (GCC_VERSION <<
409 default y if CC_IS_GCC && (GCC_VERSION <<
410 default y if CC_IS_GCC && (GCC_VERSION <<
411 default n <<
412 1008
413 config KASAN_SHADOW_OFFSET !! 1009 config CEVT_SB1250
414 hex <<
415 depends on KASAN_GENERIC || KASAN_SW_T <<
416 default 0xdfff800000000000 if (ARM64_V <<
417 default 0xdfffc00000000000 if (ARM64_V <<
418 default 0xdffffe0000000000 if ARM64_VA <<
419 default 0xdfffffc000000000 if ARM64_VA <<
420 default 0xdffffff800000000 if ARM64_VA <<
421 default 0xefff800000000000 if (ARM64_V <<
422 default 0xefffc00000000000 if (ARM64_V <<
423 default 0xeffffe0000000000 if ARM64_VA <<
424 default 0xefffffc000000000 if ARM64_VA <<
425 default 0xeffffff800000000 if ARM64_VA <<
426 default 0xffffffffffffffff <<
427 <<
428 config UNWIND_TABLES <<
429 bool 1010 bool
430 1011
431 source "arch/arm64/Kconfig.platforms" !! 1012 config CEVT_TXX9
>> 1013 bool
432 1014
433 menu "Kernel Features" !! 1015 config CSRC_BCM1480
>> 1016 bool
434 1017
435 menu "ARM errata workarounds via the alternati !! 1018 config CSRC_IOASIC
>> 1019 bool
436 1020
437 config AMPERE_ERRATUM_AC03_CPU_38 !! 1021 config CSRC_R4K
438 bool "AmpereOne: AC03_CPU_38: Certain !! 1022 select CLOCKSOURCE_WATCHDOG if CPU_FREQ
439 default y !! 1023 bool
440 help <<
441 This option adds an alternative code <<
442 errata AC03_CPU_38 and AC04_CPU_10 o <<
443 1024
444 The affected design reports FEAT_HAF !! 1025 config CSRC_SB1250
445 ID_AA64MMFR1_EL1.HAFDBS, but (V)TCR_ !! 1026 bool
446 as required by the architecture. The <<
447 implementation suffers from an addit <<
448 A/D updates can occur after a PTE ha <<
449 <<
450 The workaround forces KVM to explici <<
451 which avoids enabling unadvertised h <<
452 at stage-2. <<
453 1027
454 If unsure, say Y. !! 1028 config MIPS_CLOCK_VSYSCALL
>> 1029 def_bool CSRC_R4K || CLKSRC_MIPS_GIC
455 1030
456 config ARM64_WORKAROUND_CLEAN_CACHE !! 1031 config GPIO_TXX9
>> 1032 select GPIOLIB
457 bool 1033 bool
458 1034
459 config ARM64_ERRATUM_826319 !! 1035 config FW_CFE
460 bool "Cortex-A53: 826319: System might !! 1036 bool
461 default y <<
462 select ARM64_WORKAROUND_CLEAN_CACHE <<
463 help <<
464 This option adds an alternative code <<
465 erratum 826319 on Cortex-A53 parts u <<
466 AXI master interface and an L2 cache <<
467 <<
468 If a Cortex-A53 uses an AMBA AXI4 AC <<
469 and is unable to accept a certain wr <<
470 not progress on read data presented <<
471 system can deadlock. <<
472 <<
473 The workaround promotes data cache c <<
474 data cache clean-and-invalidate. <<
475 Please note that this does not neces <<
476 as it depends on the alternative fra <<
477 the kernel if an affected CPU is det <<
478 <<
479 If unsure, say Y. <<
480 1037
481 config ARM64_ERRATUM_827319 !! 1038 config ARCH_SUPPORTS_UPROBES
482 bool "Cortex-A53: 827319: Data cache c !! 1039 def_bool y
483 default y <<
484 select ARM64_WORKAROUND_CLEAN_CACHE <<
485 help <<
486 This option adds an alternative code <<
487 erratum 827319 on Cortex-A53 parts u <<
488 master interface and an L2 cache. <<
489 <<
490 Under certain conditions this erratu <<
491 to occur at the same time as another <<
492 on the AMBA 5 CHI interface, which c <<
493 interconnect reorders the two transa <<
494 <<
495 The workaround promotes data cache c <<
496 data cache clean-and-invalidate. <<
497 Please note that this does not neces <<
498 as it depends on the alternative fra <<
499 the kernel if an affected CPU is det <<
500 1040
501 If unsure, say Y. !! 1041 config DMA_NONCOHERENT
>> 1042 bool
>> 1043 #
>> 1044 # MIPS allows mixing "slightly different" Cacheability and Coherency
>> 1045 # Attribute bits. It is believed that the uncached access through
>> 1046 # KSEG1 and the implementation specific "uncached accelerated" used
>> 1047 # by pgprot_writcombine can be mixed, and the latter sometimes provides
>> 1048 # significant advantages.
>> 1049 #
>> 1050 select ARCH_HAS_SETUP_DMA_OPS
>> 1051 select ARCH_HAS_DMA_WRITE_COMBINE
>> 1052 select ARCH_HAS_DMA_PREP_COHERENT
>> 1053 select ARCH_HAS_SYNC_DMA_FOR_CPU
>> 1054 select ARCH_HAS_SYNC_DMA_FOR_DEVICE
>> 1055 select ARCH_HAS_DMA_SET_UNCACHED
>> 1056 select DMA_NONCOHERENT_MMAP
>> 1057 select NEED_DMA_MAP_STATE
502 1058
503 config ARM64_ERRATUM_824069 !! 1059 config SYS_HAS_EARLY_PRINTK
504 bool "Cortex-A53: 824069: Cache line m !! 1060 bool
505 default y <<
506 select ARM64_WORKAROUND_CLEAN_CACHE <<
507 help <<
508 This option adds an alternative code <<
509 erratum 824069 on Cortex-A53 parts u <<
510 to a coherent interconnect. <<
511 <<
512 If a Cortex-A53 processor is executi <<
513 write instruction at the same time a <<
514 cluster is executing a cache mainten <<
515 address, then this erratum might cau <<
516 incorrectly marked as dirty. <<
517 <<
518 The workaround promotes data cache c <<
519 data cache clean-and-invalidate. <<
520 Please note that this option does no <<
521 workaround, as it depends on the alt <<
522 only patch the kernel if an affected <<
523 1061
524 If unsure, say Y. !! 1062 config SYS_SUPPORTS_HOTPLUG_CPU
>> 1063 bool
525 1064
526 config ARM64_ERRATUM_819472 !! 1065 config MIPS_BONITO64
527 bool "Cortex-A53: 819472: Store exclus !! 1066 bool
528 default y <<
529 select ARM64_WORKAROUND_CLEAN_CACHE <<
530 help <<
531 This option adds an alternative code <<
532 erratum 819472 on Cortex-A53 parts u <<
533 present when it is connected to a co <<
534 <<
535 If the processor is executing a load <<
536 the same time as a processor in anot <<
537 maintenance operation to the same ad <<
538 cause data corruption. <<
539 <<
540 The workaround promotes data cache c <<
541 data cache clean-and-invalidate. <<
542 Please note that this does not neces <<
543 as it depends on the alternative fra <<
544 the kernel if an affected CPU is det <<
545 1067
546 If unsure, say Y. !! 1068 config MIPS_MSC
>> 1069 bool
547 1070
548 config ARM64_ERRATUM_832075 !! 1071 config SYNC_R4K
549 bool "Cortex-A57: 832075: possible dea !! 1072 bool
550 default y <<
551 help <<
552 This option adds an alternative code <<
553 erratum 832075 on Cortex-A57 parts u <<
554 1073
555 Affected Cortex-A57 parts might dead !! 1074 config NO_IOPORT_MAP
556 instructions to Write-Back memory ar !! 1075 def_bool n
557 1076
558 The workaround is to promote device !! 1077 config GENERIC_CSUM
559 semantics. !! 1078 def_bool CPU_NO_LOAD_STORE_LR
560 Please note that this does not neces <<
561 as it depends on the alternative fra <<
562 the kernel if an affected CPU is det <<
563 1079
564 If unsure, say Y. !! 1080 config GENERIC_ISA_DMA
>> 1081 bool
>> 1082 select ZONE_DMA if GENERIC_ISA_DMA_SUPPORT_BROKEN=n
>> 1083 select ISA_DMA_API
565 1084
566 config ARM64_ERRATUM_834220 !! 1085 config GENERIC_ISA_DMA_SUPPORT_BROKEN
567 bool "Cortex-A57: 834220: Stage 2 tran !! 1086 bool
568 depends on KVM !! 1087 select GENERIC_ISA_DMA
569 help <<
570 This option adds an alternative code <<
571 erratum 834220 on Cortex-A57 parts u <<
572 <<
573 Affected Cortex-A57 parts might repo <<
574 fault as the result of a Stage 1 fau <<
575 page boundary when there is a permis <<
576 alignment fault at Stage 1 and a tra <<
577 <<
578 The workaround is to verify that the <<
579 doesn't generate a fault before hand <<
580 Please note that this does not neces <<
581 as it depends on the alternative fra <<
582 the kernel if an affected CPU is det <<
583 1088
584 If unsure, say N. !! 1089 config HAVE_PLAT_DELAY
>> 1090 bool
585 1091
586 config ARM64_ERRATUM_1742098 !! 1092 config HAVE_PLAT_FW_INIT_CMDLINE
587 bool "Cortex-A57/A72: 1742098: ELR rec !! 1093 bool
588 depends on COMPAT <<
589 default y <<
590 help <<
591 This option removes the AES hwcap fo <<
592 workaround erratum 1742098 on Cortex <<
593 1094
594 Affected parts may corrupt the AES s !! 1095 config HAVE_PLAT_MEMCPY
595 taken between a pair of AES instruct !! 1096 bool
596 are only present if the cryptography <<
597 All software should have a fallback <<
598 that don't implement the cryptograph <<
599 1097
600 If unsure, say Y. !! 1098 config ISA_DMA_API
>> 1099 bool
601 1100
602 config ARM64_ERRATUM_845719 !! 1101 config SYS_SUPPORTS_RELOCATABLE
603 bool "Cortex-A53: 845719: a load might !! 1102 bool
604 depends on COMPAT <<
605 default y <<
606 help 1103 help
607 This option adds an alternative code !! 1104 Selected if the platform supports relocating the kernel.
608 erratum 845719 on Cortex-A53 parts u !! 1105 The platform must provide plat_get_fdt() if it selects CONFIG_USE_OF
609 !! 1106 to allow access to command line and entropy sources.
610 When running a compat (AArch32) user <<
611 part, a load at EL0 from a virtual a <<
612 bits of the virtual address used by <<
613 might return incorrect data. <<
614 <<
615 The workaround is to write the conte <<
616 return to a 32-bit task. <<
617 Please note that this does not neces <<
618 as it depends on the alternative fra <<
619 the kernel if an affected CPU is det <<
620 <<
621 If unsure, say Y. <<
622 1107
623 config ARM64_ERRATUM_843419 !! 1108 #
624 bool "Cortex-A53: 843419: A load or st !! 1109 # Endianness selection. Sufficiently obscure so many users don't know what to
625 default y !! 1110 # answer,so we try hard to limit the available choices. Also the use of a
>> 1111 # choice statement should be more obvious to the user.
>> 1112 #
>> 1113 choice
>> 1114 prompt "Endianness selection"
626 help 1115 help
627 This option links the kernel with '- !! 1116 Some MIPS machines can be configured for either little or big endian
628 enables PLT support to replace certa !! 1117 byte order. These modes require different kernels and a different
629 cause subsequent memory accesses to !! 1118 Linux distribution. In general there is one preferred byteorder for a
630 Cortex-A53 parts up to r0p4. !! 1119 particular system but some systems are just as commonly used in the
>> 1120 one or the other endianness.
631 1121
632 If unsure, say Y. !! 1122 config CPU_BIG_ENDIAN
>> 1123 bool "Big endian"
>> 1124 depends on SYS_SUPPORTS_BIG_ENDIAN
633 1125
634 config ARM64_LD_HAS_FIX_ERRATUM_843419 !! 1126 config CPU_LITTLE_ENDIAN
635 def_bool $(ld-option,--fix-cortex-a53- !! 1127 bool "Little endian"
>> 1128 depends on SYS_SUPPORTS_LITTLE_ENDIAN
636 1129
637 config ARM64_ERRATUM_1024718 !! 1130 endchoice
638 bool "Cortex-A55: 1024718: Update of D <<
639 default y <<
640 help <<
641 This option adds a workaround for AR <<
642 1131
643 Affected Cortex-A55 cores (all revis !! 1132 config EXPORT_UASM
644 update of the hardware dirty bit whe !! 1133 bool
645 without a break-before-make. The wor <<
646 of hardware DBM locally on the affec <<
647 this erratum will continue to use th <<
648 1134
649 If unsure, say Y. !! 1135 config SYS_SUPPORTS_APM_EMULATION
>> 1136 bool
650 1137
651 config ARM64_ERRATUM_1418040 !! 1138 config SYS_SUPPORTS_BIG_ENDIAN
652 bool "Cortex-A76/Neoverse-N1: MRC read !! 1139 bool
653 default y <<
654 depends on COMPAT <<
655 help <<
656 This option adds a workaround for AR <<
657 errata 1188873 and 1418040. <<
658 1140
659 Affected Cortex-A76/Neoverse-N1 core !! 1141 config SYS_SUPPORTS_LITTLE_ENDIAN
660 cause register corruption when acces !! 1142 bool
661 from AArch32 userspace. <<
662 1143
663 If unsure, say Y. !! 1144 config MIPS_HUGE_TLB_SUPPORT
>> 1145 def_bool HUGETLB_PAGE || TRANSPARENT_HUGEPAGE
664 1146
665 config ARM64_WORKAROUND_SPECULATIVE_AT !! 1147 config IRQ_TXX9
666 bool 1148 bool
667 1149
668 config ARM64_ERRATUM_1165522 !! 1150 config IRQ_GT641XX
669 bool "Cortex-A76: 1165522: Speculative !! 1151 bool
670 default y <<
671 select ARM64_WORKAROUND_SPECULATIVE_AT <<
672 help <<
673 This option adds a workaround for AR <<
674 1152
675 Affected Cortex-A76 cores (r0p0, r1p !! 1153 config PCI_GT64XXX_PCI0
676 corrupted TLBs by speculating an AT !! 1154 bool
677 context switch. <<
678 1155
679 If unsure, say Y. !! 1156 config PCI_XTALK_BRIDGE
>> 1157 bool
680 1158
681 config ARM64_ERRATUM_1319367 !! 1159 config NO_EXCEPT_FILL
682 bool "Cortex-A57/A72: 1319537: Specula !! 1160 bool
683 default y <<
684 select ARM64_WORKAROUND_SPECULATIVE_AT <<
685 help <<
686 This option adds work arounds for AR <<
687 and A72 erratum 1319367 <<
688 1161
689 Cortex-A57 and A72 cores could end-u !! 1162 config MIPS_SPRAM
690 speculating an AT instruction during !! 1163 bool
691 1164
692 If unsure, say Y. !! 1165 config SWAP_IO_SPACE
>> 1166 bool
693 1167
694 config ARM64_ERRATUM_1530923 !! 1168 config SGI_HAS_INDYDOG
695 bool "Cortex-A55: 1530923: Speculative !! 1169 bool
696 default y <<
697 select ARM64_WORKAROUND_SPECULATIVE_AT <<
698 help <<
699 This option adds a workaround for AR <<
700 1170
701 Affected Cortex-A55 cores (r0p0, r0p !! 1171 config SGI_HAS_HAL2
702 corrupted TLBs by speculating an AT !! 1172 bool
703 context switch. <<
704 1173
705 If unsure, say Y. !! 1174 config SGI_HAS_SEEQ
>> 1175 bool
706 1176
707 config ARM64_WORKAROUND_REPEAT_TLBI !! 1177 config SGI_HAS_WD93
708 bool 1178 bool
709 1179
710 config ARM64_ERRATUM_2441007 !! 1180 config SGI_HAS_ZILOG
711 bool "Cortex-A55: Completion of affect !! 1181 bool
712 select ARM64_WORKAROUND_REPEAT_TLBI <<
713 help <<
714 This option adds a workaround for AR <<
715 1182
716 Under very rare circumstances, affec !! 1183 config SGI_HAS_I8042
717 may not handle a race between a brea !! 1184 bool
718 CPU, and another CPU accessing the s <<
719 store to a page that has been unmapp <<
720 1185
721 Work around this by adding the affec !! 1186 config DEFAULT_SGI_PARTITION
722 TLB sequences to be done twice. !! 1187 bool
723 1188
724 If unsure, say N. !! 1189 config FW_ARC32
>> 1190 bool
725 1191
726 config ARM64_ERRATUM_1286807 !! 1192 config FW_SNIPROM
727 bool "Cortex-A76: Modification of the !! 1193 bool
728 select ARM64_WORKAROUND_REPEAT_TLBI <<
729 help <<
730 This option adds a workaround for AR <<
731 <<
732 On the affected Cortex-A76 cores (r0 <<
733 address for a cacheable mapping of a <<
734 accessed by a core while another cor <<
735 address to a new physical page using <<
736 break-before-make sequence, then und <<
737 TLBI+DSB completes before a read usi <<
738 invalidated has been observed by oth <<
739 workaround repeats the TLBI+DSB oper <<
740 1194
741 If unsure, say N. !! 1195 config BOOT_ELF32
>> 1196 bool
742 1197
743 config ARM64_ERRATUM_1463225 !! 1198 config MIPS_L1_CACHE_SHIFT_4
744 bool "Cortex-A76: Software Step might !! 1199 bool
745 default y <<
746 help <<
747 This option adds a workaround for Ar <<
748 1200
749 On the affected Cortex-A76 cores (r0 !! 1201 config MIPS_L1_CACHE_SHIFT_5
750 of a system call instruction (SVC) c !! 1202 bool
751 subsequent interrupts when software <<
752 exception handler of the system call <<
753 is enabled or VHE is in use. <<
754 <<
755 Work around the erratum by triggerin <<
756 when handling a system call from a t <<
757 in a VHE configuration of the kernel <<
758 1203
759 If unsure, say Y. !! 1204 config MIPS_L1_CACHE_SHIFT_6
>> 1205 bool
760 1206
761 config ARM64_ERRATUM_1542419 !! 1207 config MIPS_L1_CACHE_SHIFT_7
762 bool "Neoverse-N1: workaround mis-orde !! 1208 bool
763 help <<
764 This option adds a workaround for AR <<
765 1542419. <<
766 1209
767 Affected Neoverse-N1 cores could exe !! 1210 config MIPS_L1_CACHE_SHIFT
768 modified by another CPU. The workaro !! 1211 int
769 counterpart. !! 1212 default "7" if MIPS_L1_CACHE_SHIFT_7
>> 1213 default "6" if MIPS_L1_CACHE_SHIFT_6
>> 1214 default "5" if MIPS_L1_CACHE_SHIFT_5
>> 1215 default "4" if MIPS_L1_CACHE_SHIFT_4
>> 1216 default "5"
770 1217
771 Workaround the issue by hiding the D !! 1218 config ARC_CMDLINE_ONLY
772 forces user-space to perform cache m !! 1219 bool
773 1220
774 If unsure, say N. !! 1221 config ARC_CONSOLE
>> 1222 bool "ARC console support"
>> 1223 depends on SGI_IP22 || SGI_IP28 || (SNI_RM && CPU_LITTLE_ENDIAN)
775 1224
776 config ARM64_ERRATUM_1508412 !! 1225 config ARC_MEMORY
777 bool "Cortex-A77: 1508412: workaround !! 1226 bool
778 default y <<
779 help <<
780 This option adds a workaround for Ar <<
781 1227
782 Affected Cortex-A77 cores (r0p0, r1p !! 1228 config ARC_PROMLIB
783 of a store-exclusive or read of PAR_ !! 1229 bool
784 non-cacheable memory attributes. The <<
785 counterpart. <<
786 <<
787 KVM guests must also have the workar <<
788 deadlock the system. <<
789 <<
790 Work around the issue by inserting D <<
791 register reads and warning KVM users <<
792 to prevent a speculative PAR_EL1 rea <<
793 1230
794 If unsure, say Y. !! 1231 config FW_ARC64
>> 1232 bool
795 1233
796 config ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MO !! 1234 config BOOT_ELF64
797 bool 1235 bool
798 1236
799 config ARM64_ERRATUM_2051678 !! 1237 menu "CPU selection"
800 bool "Cortex-A510: 2051678: disable Ha <<
801 default y <<
802 help <<
803 This options adds the workaround for <<
804 Affected Cortex-A510 might not respe <<
805 hardware update of the page table's <<
806 is to not enable the feature on affe <<
807 1238
808 If unsure, say Y. !! 1239 choice
>> 1240 prompt "CPU type"
>> 1241 default CPU_R4X00
809 1242
810 config ARM64_ERRATUM_2077057 !! 1243 config CPU_LOONGSON64
811 bool "Cortex-A510: 2077057: workaround !! 1244 bool "Loongson 64-bit CPU"
812 default y !! 1245 depends on SYS_HAS_CPU_LOONGSON64
>> 1246 select ARCH_HAS_PHYS_TO_DMA
>> 1247 select CPU_MIPSR2
>> 1248 select CPU_HAS_PREFETCH
>> 1249 select CPU_SUPPORTS_64BIT_KERNEL
>> 1250 select CPU_SUPPORTS_HIGHMEM
>> 1251 select CPU_SUPPORTS_HUGEPAGES
>> 1252 select CPU_SUPPORTS_MSA
>> 1253 select CPU_DIEI_BROKEN if !LOONGSON3_ENHANCEMENT
>> 1254 select CPU_MIPSR2_IRQ_VI
>> 1255 select DMA_NONCOHERENT
>> 1256 select WEAK_ORDERING
>> 1257 select WEAK_REORDERING_BEYOND_LLSC
>> 1258 select MIPS_ASID_BITS_VARIABLE
>> 1259 select MIPS_PGD_C0_CONTEXT
>> 1260 select MIPS_L1_CACHE_SHIFT_6
>> 1261 select MIPS_FP_SUPPORT
>> 1262 select GPIOLIB
>> 1263 select SWIOTLB
>> 1264 select HAVE_KVM
813 help 1265 help
814 This option adds the workaround for !! 1266 The Loongson GSx64(GS264/GS464/GS464E/GS464V) series of processor
815 Affected Cortex-A510 may corrupt SPS !! 1267 cores implements the MIPS64R2 instruction set with many extensions,
816 expected, but a Pointer Authenticati !! 1268 including most 64-bit Loongson-2 (2H, 2K) and Loongson-3 (3A1000,
817 erratum causes SPSR_EL1 to be copied !! 1269 3B1000, 3B1500, 3A2000, 3A3000 and 3A4000) processors. However, old
818 EL1 to cause a return to EL2 with a !! 1270 Loongson-2E/2F is not covered here and will be removed in future.
819 1271
820 This can only happen when EL2 is ste !! 1272 config LOONGSON3_ENHANCEMENT
821 !! 1273 bool "New Loongson-3 CPU Enhancements"
822 When these conditions occur, the SPS !! 1274 default n
823 previous guest entry, and can be res !! 1275 depends on CPU_LOONGSON64
824 !! 1276 help
825 If unsure, say Y. !! 1277 New Loongson-3 cores (since Loongson-3A R2, as opposed to Loongson-3A
826 !! 1278 R1, Loongson-3B R1 and Loongson-3B R2) has many enhancements, such as
827 config ARM64_ERRATUM_2658417 !! 1279 FTLB, L1-VCache, EI/DI/Wait/Prefetch instruction, DSP/DSPr2 ASE, User
828 bool "Cortex-A510: 2658417: remove BF1 !! 1280 Local register, Read-Inhibit/Execute-Inhibit, SFB (Store Fill Buffer),
829 default y !! 1281 Fast TLB refill support, etc.
>> 1282
>> 1283 This option enable those enhancements which are not probed at run
>> 1284 time. If you want a generic kernel to run on all Loongson 3 machines,
>> 1285 please say 'N' here. If you want a high-performance kernel to run on
>> 1286 new Loongson-3 machines only, please say 'Y' here.
>> 1287
>> 1288 config CPU_LOONGSON3_WORKAROUNDS
>> 1289 bool "Loongson-3 LLSC Workarounds"
>> 1290 default y if SMP
>> 1291 depends on CPU_LOONGSON64
>> 1292 help
>> 1293 Loongson-3 processors have the llsc issues which require workarounds.
>> 1294 Without workarounds the system may hang unexpectedly.
>> 1295
>> 1296 Say Y, unless you know what you are doing.
>> 1297
>> 1298 config CPU_LOONGSON3_CPUCFG_EMULATION
>> 1299 bool "Emulate the CPUCFG instruction on older Loongson cores"
>> 1300 default y
>> 1301 depends on CPU_LOONGSON64
>> 1302 help
>> 1303 Loongson-3A R4 and newer have the CPUCFG instruction available for
>> 1304 userland to query CPU capabilities, much like CPUID on x86. This
>> 1305 option provides emulation of the instruction on older Loongson
>> 1306 cores, back to Loongson-3A1000.
>> 1307
>> 1308 If unsure, please say Y.
>> 1309
>> 1310 config CPU_LOONGSON2E
>> 1311 bool "Loongson 2E"
>> 1312 depends on SYS_HAS_CPU_LOONGSON2E
>> 1313 select CPU_LOONGSON2EF
>> 1314 help
>> 1315 The Loongson 2E processor implements the MIPS III instruction set
>> 1316 with many extensions.
>> 1317
>> 1318 It has an internal FPGA northbridge, which is compatible to
>> 1319 bonito64.
>> 1320
>> 1321 config CPU_LOONGSON2F
>> 1322 bool "Loongson 2F"
>> 1323 depends on SYS_HAS_CPU_LOONGSON2F
>> 1324 select CPU_LOONGSON2EF
>> 1325 help
>> 1326 The Loongson 2F processor implements the MIPS III instruction set
>> 1327 with many extensions.
>> 1328
>> 1329 Loongson2F have built-in DDR2 and PCIX controller. The PCIX controller
>> 1330 have a similar programming interface with FPGA northbridge used in
>> 1331 Loongson2E.
>> 1332
>> 1333 config CPU_LOONGSON1B
>> 1334 bool "Loongson 1B"
>> 1335 depends on SYS_HAS_CPU_LOONGSON1B
>> 1336 select CPU_LOONGSON32
>> 1337 select LEDS_GPIO_REGISTER
>> 1338 help
>> 1339 The Loongson 1B is a 32-bit SoC, which implements the MIPS32
>> 1340 Release 1 instruction set and part of the MIPS32 Release 2
>> 1341 instruction set.
>> 1342
>> 1343 config CPU_LOONGSON1C
>> 1344 bool "Loongson 1C"
>> 1345 depends on SYS_HAS_CPU_LOONGSON1C
>> 1346 select CPU_LOONGSON32
>> 1347 select LEDS_GPIO_REGISTER
>> 1348 help
>> 1349 The Loongson 1C is a 32-bit SoC, which implements the MIPS32
>> 1350 Release 1 instruction set and part of the MIPS32 Release 2
>> 1351 instruction set.
>> 1352
>> 1353 config CPU_MIPS32_R1
>> 1354 bool "MIPS32 Release 1"
>> 1355 depends on SYS_HAS_CPU_MIPS32_R1
>> 1356 select CPU_HAS_PREFETCH
>> 1357 select CPU_SUPPORTS_32BIT_KERNEL
>> 1358 select CPU_SUPPORTS_HIGHMEM
>> 1359 help
>> 1360 Choose this option to build a kernel for release 1 or later of the
>> 1361 MIPS32 architecture. Most modern embedded systems with a 32-bit
>> 1362 MIPS processor are based on a MIPS32 processor. If you know the
>> 1363 specific type of processor in your system, choose those that one
>> 1364 otherwise CPU_MIPS32_R1 is a safe bet for any MIPS32 system.
>> 1365 Release 2 of the MIPS32 architecture is available since several
>> 1366 years so chances are you even have a MIPS32 Release 2 processor
>> 1367 in which case you should choose CPU_MIPS32_R2 instead for better
>> 1368 performance.
>> 1369
>> 1370 config CPU_MIPS32_R2
>> 1371 bool "MIPS32 Release 2"
>> 1372 depends on SYS_HAS_CPU_MIPS32_R2
>> 1373 select CPU_HAS_PREFETCH
>> 1374 select CPU_SUPPORTS_32BIT_KERNEL
>> 1375 select CPU_SUPPORTS_HIGHMEM
>> 1376 select CPU_SUPPORTS_MSA
>> 1377 select HAVE_KVM
>> 1378 help
>> 1379 Choose this option to build a kernel for release 2 or later of the
>> 1380 MIPS32 architecture. Most modern embedded systems with a 32-bit
>> 1381 MIPS processor are based on a MIPS32 processor. If you know the
>> 1382 specific type of processor in your system, choose those that one
>> 1383 otherwise CPU_MIPS32_R1 is a safe bet for any MIPS32 system.
>> 1384
>> 1385 config CPU_MIPS32_R5
>> 1386 bool "MIPS32 Release 5"
>> 1387 depends on SYS_HAS_CPU_MIPS32_R5
>> 1388 select CPU_HAS_PREFETCH
>> 1389 select CPU_SUPPORTS_32BIT_KERNEL
>> 1390 select CPU_SUPPORTS_HIGHMEM
>> 1391 select CPU_SUPPORTS_MSA
>> 1392 select HAVE_KVM
>> 1393 select MIPS_O32_FP64_SUPPORT
>> 1394 help
>> 1395 Choose this option to build a kernel for release 5 or later of the
>> 1396 MIPS32 architecture. New MIPS processors, starting with the Warrior
>> 1397 family, are based on a MIPS32r5 processor. If you own an older
>> 1398 processor, you probably need to select MIPS32r1 or MIPS32r2 instead.
>> 1399
>> 1400 config CPU_MIPS32_R6
>> 1401 bool "MIPS32 Release 6"
>> 1402 depends on SYS_HAS_CPU_MIPS32_R6
>> 1403 select CPU_HAS_PREFETCH
>> 1404 select CPU_NO_LOAD_STORE_LR
>> 1405 select CPU_SUPPORTS_32BIT_KERNEL
>> 1406 select CPU_SUPPORTS_HIGHMEM
>> 1407 select CPU_SUPPORTS_MSA
>> 1408 select HAVE_KVM
>> 1409 select MIPS_O32_FP64_SUPPORT
>> 1410 help
>> 1411 Choose this option to build a kernel for release 6 or later of the
>> 1412 MIPS32 architecture. New MIPS processors, starting with the Warrior
>> 1413 family, are based on a MIPS32r6 processor. If you own an older
>> 1414 processor, you probably need to select MIPS32r1 or MIPS32r2 instead.
>> 1415
>> 1416 config CPU_MIPS64_R1
>> 1417 bool "MIPS64 Release 1"
>> 1418 depends on SYS_HAS_CPU_MIPS64_R1
>> 1419 select CPU_HAS_PREFETCH
>> 1420 select CPU_SUPPORTS_32BIT_KERNEL
>> 1421 select CPU_SUPPORTS_64BIT_KERNEL
>> 1422 select CPU_SUPPORTS_HIGHMEM
>> 1423 select CPU_SUPPORTS_HUGEPAGES
>> 1424 help
>> 1425 Choose this option to build a kernel for release 1 or later of the
>> 1426 MIPS64 architecture. Many modern embedded systems with a 64-bit
>> 1427 MIPS processor are based on a MIPS64 processor. If you know the
>> 1428 specific type of processor in your system, choose those that one
>> 1429 otherwise CPU_MIPS64_R1 is a safe bet for any MIPS64 system.
>> 1430 Release 2 of the MIPS64 architecture is available since several
>> 1431 years so chances are you even have a MIPS64 Release 2 processor
>> 1432 in which case you should choose CPU_MIPS64_R2 instead for better
>> 1433 performance.
>> 1434
>> 1435 config CPU_MIPS64_R2
>> 1436 bool "MIPS64 Release 2"
>> 1437 depends on SYS_HAS_CPU_MIPS64_R2
>> 1438 select CPU_HAS_PREFETCH
>> 1439 select CPU_SUPPORTS_32BIT_KERNEL
>> 1440 select CPU_SUPPORTS_64BIT_KERNEL
>> 1441 select CPU_SUPPORTS_HIGHMEM
>> 1442 select CPU_SUPPORTS_HUGEPAGES
>> 1443 select CPU_SUPPORTS_MSA
>> 1444 select HAVE_KVM
>> 1445 help
>> 1446 Choose this option to build a kernel for release 2 or later of the
>> 1447 MIPS64 architecture. Many modern embedded systems with a 64-bit
>> 1448 MIPS processor are based on a MIPS64 processor. If you know the
>> 1449 specific type of processor in your system, choose those that one
>> 1450 otherwise CPU_MIPS64_R1 is a safe bet for any MIPS64 system.
>> 1451
>> 1452 config CPU_MIPS64_R5
>> 1453 bool "MIPS64 Release 5"
>> 1454 depends on SYS_HAS_CPU_MIPS64_R5
>> 1455 select CPU_HAS_PREFETCH
>> 1456 select CPU_SUPPORTS_32BIT_KERNEL
>> 1457 select CPU_SUPPORTS_64BIT_KERNEL
>> 1458 select CPU_SUPPORTS_HIGHMEM
>> 1459 select CPU_SUPPORTS_HUGEPAGES
>> 1460 select CPU_SUPPORTS_MSA
>> 1461 select MIPS_O32_FP64_SUPPORT if 32BIT || MIPS32_O32
>> 1462 select HAVE_KVM
>> 1463 help
>> 1464 Choose this option to build a kernel for release 5 or later of the
>> 1465 MIPS64 architecture. This is a intermediate MIPS architecture
>> 1466 release partly implementing release 6 features. Though there is no
>> 1467 any hardware known to be based on this release.
>> 1468
>> 1469 config CPU_MIPS64_R6
>> 1470 bool "MIPS64 Release 6"
>> 1471 depends on SYS_HAS_CPU_MIPS64_R6
>> 1472 select CPU_HAS_PREFETCH
>> 1473 select CPU_NO_LOAD_STORE_LR
>> 1474 select CPU_SUPPORTS_32BIT_KERNEL
>> 1475 select CPU_SUPPORTS_64BIT_KERNEL
>> 1476 select CPU_SUPPORTS_HIGHMEM
>> 1477 select CPU_SUPPORTS_HUGEPAGES
>> 1478 select CPU_SUPPORTS_MSA
>> 1479 select MIPS_O32_FP64_SUPPORT if 32BIT || MIPS32_O32
>> 1480 select HAVE_KVM
>> 1481 help
>> 1482 Choose this option to build a kernel for release 6 or later of the
>> 1483 MIPS64 architecture. New MIPS processors, starting with the Warrior
>> 1484 family, are based on a MIPS64r6 processor. If you own an older
>> 1485 processor, you probably need to select MIPS64r1 or MIPS64r2 instead.
>> 1486
>> 1487 config CPU_P5600
>> 1488 bool "MIPS Warrior P5600"
>> 1489 depends on SYS_HAS_CPU_P5600
>> 1490 select CPU_HAS_PREFETCH
>> 1491 select CPU_SUPPORTS_32BIT_KERNEL
>> 1492 select CPU_SUPPORTS_HIGHMEM
>> 1493 select CPU_SUPPORTS_MSA
>> 1494 select CPU_SUPPORTS_CPUFREQ
>> 1495 select CPU_MIPSR2_IRQ_VI
>> 1496 select CPU_MIPSR2_IRQ_EI
>> 1497 select HAVE_KVM
>> 1498 select MIPS_O32_FP64_SUPPORT
>> 1499 help
>> 1500 Choose this option to build a kernel for MIPS Warrior P5600 CPU.
>> 1501 It's based on MIPS32r5 ISA with XPA, EVA, dual/quad issue exec pipes,
>> 1502 MMU with two-levels TLB, UCA, MSA, MDU core level features and system
>> 1503 level features like up to six P5600 calculation cores, CM2 with L2
>> 1504 cache, IOCU/IOMMU (though might be unused depending on the system-
>> 1505 specific IP core configuration), GIC, CPC, virtualisation module,
>> 1506 eJTAG and PDtrace.
>> 1507
>> 1508 config CPU_R3000
>> 1509 bool "R3000"
>> 1510 depends on SYS_HAS_CPU_R3000
>> 1511 select CPU_HAS_WB
>> 1512 select CPU_R3K_TLB
>> 1513 select CPU_SUPPORTS_32BIT_KERNEL
>> 1514 select CPU_SUPPORTS_HIGHMEM
>> 1515 help
>> 1516 Please make sure to pick the right CPU type. Linux/MIPS is not
>> 1517 designed to be generic, i.e. Kernels compiled for R3000 CPUs will
>> 1518 *not* work on R4000 machines and vice versa. However, since most
>> 1519 of the supported machines have an R4000 (or similar) CPU, R4x00
>> 1520 might be a safe bet. If the resulting kernel does not work,
>> 1521 try to recompile with R3000.
>> 1522
>> 1523 config CPU_R4300
>> 1524 bool "R4300"
>> 1525 depends on SYS_HAS_CPU_R4300
>> 1526 select CPU_SUPPORTS_32BIT_KERNEL
>> 1527 select CPU_SUPPORTS_64BIT_KERNEL
>> 1528 help
>> 1529 MIPS Technologies R4300-series processors.
>> 1530
>> 1531 config CPU_R4X00
>> 1532 bool "R4x00"
>> 1533 depends on SYS_HAS_CPU_R4X00
>> 1534 select CPU_SUPPORTS_32BIT_KERNEL
>> 1535 select CPU_SUPPORTS_64BIT_KERNEL
>> 1536 select CPU_SUPPORTS_HUGEPAGES
>> 1537 help
>> 1538 MIPS Technologies R4000-series processors other than 4300, including
>> 1539 the R4000, R4400, R4600, and 4700.
>> 1540
>> 1541 config CPU_TX49XX
>> 1542 bool "R49XX"
>> 1543 depends on SYS_HAS_CPU_TX49XX
>> 1544 select CPU_HAS_PREFETCH
>> 1545 select CPU_SUPPORTS_32BIT_KERNEL
>> 1546 select CPU_SUPPORTS_64BIT_KERNEL
>> 1547 select CPU_SUPPORTS_HUGEPAGES
>> 1548
>> 1549 config CPU_R5000
>> 1550 bool "R5000"
>> 1551 depends on SYS_HAS_CPU_R5000
>> 1552 select CPU_SUPPORTS_32BIT_KERNEL
>> 1553 select CPU_SUPPORTS_64BIT_KERNEL
>> 1554 select CPU_SUPPORTS_HUGEPAGES
>> 1555 help
>> 1556 MIPS Technologies R5000-series processors other than the Nevada.
>> 1557
>> 1558 config CPU_R5500
>> 1559 bool "R5500"
>> 1560 depends on SYS_HAS_CPU_R5500
>> 1561 select CPU_SUPPORTS_32BIT_KERNEL
>> 1562 select CPU_SUPPORTS_64BIT_KERNEL
>> 1563 select CPU_SUPPORTS_HUGEPAGES
>> 1564 help
>> 1565 NEC VR5500 and VR5500A series processors implement 64-bit MIPS IV
>> 1566 instruction set.
>> 1567
>> 1568 config CPU_NEVADA
>> 1569 bool "RM52xx"
>> 1570 depends on SYS_HAS_CPU_NEVADA
>> 1571 select CPU_SUPPORTS_32BIT_KERNEL
>> 1572 select CPU_SUPPORTS_64BIT_KERNEL
>> 1573 select CPU_SUPPORTS_HUGEPAGES
>> 1574 help
>> 1575 QED / PMC-Sierra RM52xx-series ("Nevada") processors.
>> 1576
>> 1577 config CPU_R10000
>> 1578 bool "R10000"
>> 1579 depends on SYS_HAS_CPU_R10000
>> 1580 select CPU_HAS_PREFETCH
>> 1581 select CPU_SUPPORTS_32BIT_KERNEL
>> 1582 select CPU_SUPPORTS_64BIT_KERNEL
>> 1583 select CPU_SUPPORTS_HIGHMEM
>> 1584 select CPU_SUPPORTS_HUGEPAGES
>> 1585 help
>> 1586 MIPS Technologies R10000-series processors.
>> 1587
>> 1588 config CPU_RM7000
>> 1589 bool "RM7000"
>> 1590 depends on SYS_HAS_CPU_RM7000
>> 1591 select CPU_HAS_PREFETCH
>> 1592 select CPU_SUPPORTS_32BIT_KERNEL
>> 1593 select CPU_SUPPORTS_64BIT_KERNEL
>> 1594 select CPU_SUPPORTS_HIGHMEM
>> 1595 select CPU_SUPPORTS_HUGEPAGES
>> 1596
>> 1597 config CPU_SB1
>> 1598 bool "SB1"
>> 1599 depends on SYS_HAS_CPU_SB1
>> 1600 select CPU_SUPPORTS_32BIT_KERNEL
>> 1601 select CPU_SUPPORTS_64BIT_KERNEL
>> 1602 select CPU_SUPPORTS_HIGHMEM
>> 1603 select CPU_SUPPORTS_HUGEPAGES
>> 1604 select WEAK_ORDERING
>> 1605
>> 1606 config CPU_CAVIUM_OCTEON
>> 1607 bool "Cavium Octeon processor"
>> 1608 depends on SYS_HAS_CPU_CAVIUM_OCTEON
>> 1609 select CPU_HAS_PREFETCH
>> 1610 select CPU_SUPPORTS_64BIT_KERNEL
>> 1611 select WEAK_ORDERING
>> 1612 select CPU_SUPPORTS_HIGHMEM
>> 1613 select CPU_SUPPORTS_HUGEPAGES
>> 1614 select USB_EHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 1615 select USB_OHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 1616 select MIPS_L1_CACHE_SHIFT_7
>> 1617 select HAVE_KVM
>> 1618 help
>> 1619 The Cavium Octeon processor is a highly integrated chip containing
>> 1620 many ethernet hardware widgets for networking tasks. The processor
>> 1621 can have up to 16 Mips64v2 cores and 8 integrated gigabit ethernets.
>> 1622 Full details can be found at http://www.caviumnetworks.com.
>> 1623
>> 1624 config CPU_BMIPS
>> 1625 bool "Broadcom BMIPS"
>> 1626 depends on SYS_HAS_CPU_BMIPS
>> 1627 select CPU_MIPS32
>> 1628 select CPU_BMIPS32_3300 if SYS_HAS_CPU_BMIPS32_3300
>> 1629 select CPU_BMIPS4350 if SYS_HAS_CPU_BMIPS4350
>> 1630 select CPU_BMIPS4380 if SYS_HAS_CPU_BMIPS4380
>> 1631 select CPU_BMIPS5000 if SYS_HAS_CPU_BMIPS5000
>> 1632 select CPU_SUPPORTS_32BIT_KERNEL
>> 1633 select DMA_NONCOHERENT
>> 1634 select IRQ_MIPS_CPU
>> 1635 select SWAP_IO_SPACE
>> 1636 select WEAK_ORDERING
>> 1637 select CPU_SUPPORTS_HIGHMEM
>> 1638 select CPU_HAS_PREFETCH
>> 1639 select CPU_SUPPORTS_CPUFREQ
>> 1640 select MIPS_EXTERNAL_TIMER
>> 1641 select GENERIC_IRQ_MIGRATION if HOTPLUG_CPU
830 help 1642 help
831 This option adds the workaround for !! 1643 Support for BMIPS32/3300/4350/4380 and BMIPS5000 processors.
832 Affected Cortex-A510 (r0p0 to r1p1) <<
833 BFMMLA or VMMLA instructions in rare <<
834 A510 CPUs are using shared neon hard <<
835 discoverable by the kernel, hide the <<
836 user-space should not be using these <<
837 1644
838 If unsure, say Y. !! 1645 endchoice
839 1646
840 config ARM64_ERRATUM_2119858 !! 1647 config CPU_MIPS32_3_5_FEATURES
841 bool "Cortex-A710/X2: 2119858: workaro !! 1648 bool "MIPS32 Release 3.5 Features"
842 default y !! 1649 depends on SYS_HAS_CPU_MIPS32_R3_5
843 depends on CORESIGHT_TRBE !! 1650 depends on CPU_MIPS32_R2 || CPU_MIPS32_R5 || CPU_MIPS32_R6 || \
844 select ARM64_WORKAROUND_TRBE_OVERWRITE !! 1651 CPU_P5600
>> 1652 help
>> 1653 Choose this option to build a kernel for release 2 or later of the
>> 1654 MIPS32 architecture including features from the 3.5 release such as
>> 1655 support for Enhanced Virtual Addressing (EVA).
>> 1656
>> 1657 config CPU_MIPS32_3_5_EVA
>> 1658 bool "Enhanced Virtual Addressing (EVA)"
>> 1659 depends on CPU_MIPS32_3_5_FEATURES
>> 1660 select EVA
>> 1661 default y
>> 1662 help
>> 1663 Choose this option if you want to enable the Enhanced Virtual
>> 1664 Addressing (EVA) on your MIPS32 core (such as proAptiv).
>> 1665 One of its primary benefits is an increase in the maximum size
>> 1666 of lowmem (up to 3GB). If unsure, say 'N' here.
>> 1667
>> 1668 config CPU_MIPS32_R5_FEATURES
>> 1669 bool "MIPS32 Release 5 Features"
>> 1670 depends on SYS_HAS_CPU_MIPS32_R5
>> 1671 depends on CPU_MIPS32_R2 || CPU_MIPS32_R5 || CPU_P5600
>> 1672 help
>> 1673 Choose this option to build a kernel for release 2 or later of the
>> 1674 MIPS32 architecture including features from release 5 such as
>> 1675 support for Extended Physical Addressing (XPA).
>> 1676
>> 1677 config CPU_MIPS32_R5_XPA
>> 1678 bool "Extended Physical Addressing (XPA)"
>> 1679 depends on CPU_MIPS32_R5_FEATURES
>> 1680 depends on !EVA
>> 1681 depends on !PAGE_SIZE_4KB
>> 1682 depends on SYS_SUPPORTS_HIGHMEM
>> 1683 select XPA
>> 1684 select HIGHMEM
>> 1685 select PHYS_ADDR_T_64BIT
>> 1686 default n
845 help 1687 help
846 This option adds the workaround for !! 1688 Choose this option if you want to enable the Extended Physical
>> 1689 Addressing (XPA) on your MIPS32 core (such as P5600 series). The
>> 1690 benefit is to increase physical addressing equal to or greater
>> 1691 than 40 bits. Note that this has the side effect of turning on
>> 1692 64-bit addressing which in turn makes the PTEs 64-bit in size.
>> 1693 If unsure, say 'N' here.
847 1694
848 Affected Cortex-A710/X2 cores could !! 1695 if CPU_LOONGSON2F
849 data at the base of the buffer (poin !! 1696 config CPU_NOP_WORKAROUNDS
850 the event of a WRAP event. !! 1697 bool
851 <<
852 Work around the issue by always maki <<
853 256 bytes before enabling the buffer <<
854 the buffer with ETM ignore packets u <<
855 1698
856 If unsure, say Y. !! 1699 config CPU_JUMP_WORKAROUNDS
>> 1700 bool
857 1701
858 config ARM64_ERRATUM_2139208 !! 1702 config CPU_LOONGSON2F_WORKAROUNDS
859 bool "Neoverse-N2: 2139208: workaround !! 1703 bool "Loongson 2F Workarounds"
860 default y 1704 default y
861 depends on CORESIGHT_TRBE !! 1705 select CPU_NOP_WORKAROUNDS
862 select ARM64_WORKAROUND_TRBE_OVERWRITE !! 1706 select CPU_JUMP_WORKAROUNDS
863 help 1707 help
864 This option adds the workaround for !! 1708 Loongson 2F01 / 2F02 processors have the NOP & JUMP issues which
>> 1709 require workarounds. Without workarounds the system may hang
>> 1710 unexpectedly. For more information please refer to the gas
>> 1711 -mfix-loongson2f-nop and -mfix-loongson2f-jump options.
>> 1712
>> 1713 Loongson 2F03 and later have fixed these issues and no workarounds
>> 1714 are needed. The workarounds have no significant side effect on them
>> 1715 but may decrease the performance of the system so this option should
>> 1716 be disabled unless the kernel is intended to be run on 2F01 or 2F02
>> 1717 systems.
865 1718
866 Affected Neoverse-N2 cores could ove !! 1719 If unsure, please say Y.
867 data at the base of the buffer (poin !! 1720 endif # CPU_LOONGSON2F
868 the event of a WRAP event. <<
869 <<
870 Work around the issue by always maki <<
871 256 bytes before enabling the buffer <<
872 the buffer with ETM ignore packets u <<
873 <<
874 If unsure, say Y. <<
875 1721
876 config ARM64_WORKAROUND_TSB_FLUSH_FAILURE !! 1722 config SYS_SUPPORTS_ZBOOT
877 bool 1723 bool
>> 1724 select HAVE_KERNEL_GZIP
>> 1725 select HAVE_KERNEL_BZIP2
>> 1726 select HAVE_KERNEL_LZ4
>> 1727 select HAVE_KERNEL_LZMA
>> 1728 select HAVE_KERNEL_LZO
>> 1729 select HAVE_KERNEL_XZ
>> 1730 select HAVE_KERNEL_ZSTD
878 1731
879 config ARM64_ERRATUM_2054223 !! 1732 config SYS_SUPPORTS_ZBOOT_UART16550
880 bool "Cortex-A710: 2054223: workaround !! 1733 bool
881 default y !! 1734 select SYS_SUPPORTS_ZBOOT
882 select ARM64_WORKAROUND_TSB_FLUSH_FAIL <<
883 help <<
884 Enable workaround for ARM Cortex-A71 <<
885 1735
886 Affected cores may fail to flush the !! 1736 config SYS_SUPPORTS_ZBOOT_UART_PROM
887 the PE is in trace prohibited state. !! 1737 bool
888 of the trace cached. !! 1738 select SYS_SUPPORTS_ZBOOT
889 1739
890 Workaround is to issue two TSB conse !! 1740 config CPU_LOONGSON2EF
>> 1741 bool
>> 1742 select CPU_SUPPORTS_32BIT_KERNEL
>> 1743 select CPU_SUPPORTS_64BIT_KERNEL
>> 1744 select CPU_SUPPORTS_HIGHMEM
>> 1745 select CPU_SUPPORTS_HUGEPAGES
891 1746
892 If unsure, say Y. !! 1747 config CPU_LOONGSON32
>> 1748 bool
>> 1749 select CPU_MIPS32
>> 1750 select CPU_MIPSR2
>> 1751 select CPU_HAS_PREFETCH
>> 1752 select CPU_SUPPORTS_32BIT_KERNEL
>> 1753 select CPU_SUPPORTS_HIGHMEM
>> 1754 select CPU_SUPPORTS_CPUFREQ
893 1755
894 config ARM64_ERRATUM_2067961 !! 1756 config CPU_BMIPS32_3300
895 bool "Neoverse-N2: 2067961: workaround !! 1757 select SMP_UP if SMP
896 default y !! 1758 bool
897 select ARM64_WORKAROUND_TSB_FLUSH_FAIL <<
898 help <<
899 Enable workaround for ARM Neoverse-N <<
900 1759
901 Affected cores may fail to flush the !! 1760 config CPU_BMIPS4350
902 the PE is in trace prohibited state. !! 1761 bool
903 of the trace cached. !! 1762 select SYS_SUPPORTS_SMP
>> 1763 select SYS_SUPPORTS_HOTPLUG_CPU
904 1764
905 Workaround is to issue two TSB conse !! 1765 config CPU_BMIPS4380
>> 1766 bool
>> 1767 select MIPS_L1_CACHE_SHIFT_6
>> 1768 select SYS_SUPPORTS_SMP
>> 1769 select SYS_SUPPORTS_HOTPLUG_CPU
>> 1770 select CPU_HAS_RIXI
906 1771
907 If unsure, say Y. !! 1772 config CPU_BMIPS5000
>> 1773 bool
>> 1774 select MIPS_CPU_SCACHE
>> 1775 select MIPS_L1_CACHE_SHIFT_7
>> 1776 select SYS_SUPPORTS_SMP
>> 1777 select SYS_SUPPORTS_HOTPLUG_CPU
>> 1778 select CPU_HAS_RIXI
908 1779
909 config ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANG !! 1780 config SYS_HAS_CPU_LOONGSON64
910 bool 1781 bool
>> 1782 select CPU_SUPPORTS_CPUFREQ
>> 1783 select CPU_HAS_RIXI
911 1784
912 config ARM64_ERRATUM_2253138 !! 1785 config SYS_HAS_CPU_LOONGSON2E
913 bool "Neoverse-N2: 2253138: workaround !! 1786 bool
914 depends on CORESIGHT_TRBE <<
915 default y <<
916 select ARM64_WORKAROUND_TRBE_WRITE_OUT <<
917 help <<
918 This option adds the workaround for <<
919 1787
920 Affected Neoverse-N2 cores might wri !! 1788 config SYS_HAS_CPU_LOONGSON2F
921 for TRBE. Under some conditions, the !! 1789 bool
922 virtually addressed page following t !! 1790 select CPU_SUPPORTS_CPUFREQ
923 (i.e., the TRBLIMITR_EL1.LIMIT), ins !! 1791 select CPU_SUPPORTS_ADDRWINCFG if 64BIT
924 1792
925 Work around this in the driver by al !! 1793 config SYS_HAS_CPU_LOONGSON1B
926 page beyond the TRBLIMITR_EL1.LIMIT, !! 1794 bool
927 1795
928 If unsure, say Y. !! 1796 config SYS_HAS_CPU_LOONGSON1C
>> 1797 bool
929 1798
930 config ARM64_ERRATUM_2224489 !! 1799 config SYS_HAS_CPU_MIPS32_R1
931 bool "Cortex-A710/X2: 2224489: workaro !! 1800 bool
932 depends on CORESIGHT_TRBE <<
933 default y <<
934 select ARM64_WORKAROUND_TRBE_WRITE_OUT <<
935 help <<
936 This option adds the workaround for <<
937 1801
938 Affected Cortex-A710/X2 cores might !! 1802 config SYS_HAS_CPU_MIPS32_R2
939 for TRBE. Under some conditions, the !! 1803 bool
940 virtually addressed page following t <<
941 (i.e., the TRBLIMITR_EL1.LIMIT), ins <<
942 1804
943 Work around this in the driver by al !! 1805 config SYS_HAS_CPU_MIPS32_R3_5
944 page beyond the TRBLIMITR_EL1.LIMIT, !! 1806 bool
945 1807
946 If unsure, say Y. !! 1808 config SYS_HAS_CPU_MIPS32_R5
>> 1809 bool
947 1810
948 config ARM64_ERRATUM_2441009 !! 1811 config SYS_HAS_CPU_MIPS32_R6
949 bool "Cortex-A510: Completion of affec !! 1812 bool
950 select ARM64_WORKAROUND_REPEAT_TLBI <<
951 help <<
952 This option adds a workaround for AR <<
953 <<
954 Under very rare circumstances, affec <<
955 may not handle a race between a brea <<
956 CPU, and another CPU accessing the s <<
957 store to a page that has been unmapp <<
958 1813
959 Work around this by adding the affec !! 1814 config SYS_HAS_CPU_MIPS64_R1
960 TLB sequences to be done twice. !! 1815 bool
961 1816
962 If unsure, say N. !! 1817 config SYS_HAS_CPU_MIPS64_R2
>> 1818 bool
963 1819
964 config ARM64_ERRATUM_2064142 !! 1820 config SYS_HAS_CPU_MIPS64_R5
965 bool "Cortex-A510: 2064142: workaround !! 1821 bool
966 depends on CORESIGHT_TRBE <<
967 default y <<
968 help <<
969 This option adds the workaround for <<
970 1822
971 Affected Cortex-A510 core might fail !! 1823 config SYS_HAS_CPU_MIPS64_R6
972 TRBE has been disabled. Under some c !! 1824 bool
973 writes into TRBE registers TRBLIMITR <<
974 and TRBTRG_EL1 will be ignored and w <<
975 <<
976 Work around this in the driver by ex <<
977 is stopped and before performing a s <<
978 registers. <<
979 1825
980 If unsure, say Y. !! 1826 config SYS_HAS_CPU_P5600
>> 1827 bool
981 1828
982 config ARM64_ERRATUM_2038923 !! 1829 config SYS_HAS_CPU_R3000
983 bool "Cortex-A510: 2038923: workaround !! 1830 bool
984 depends on CORESIGHT_TRBE <<
985 default y <<
986 help <<
987 This option adds the workaround for <<
988 1831
989 Affected Cortex-A510 core might caus !! 1832 config SYS_HAS_CPU_R4300
990 prohibited within the CPU. As a resu !! 1833 bool
991 might be corrupted. This happens aft <<
992 TRBLIMITR_EL1.E, followed by just a <<
993 execution changes from a context, in <<
994 isn't, or vice versa. In these menti <<
995 is prohibited is inconsistent betwee <<
996 the trace buffer state might be corr <<
997 <<
998 Work around this in the driver by pr <<
999 trace is prohibited or not based on <<
1000 change to TRBLIMITR_EL1.E with at l <<
1001 two ISB instructions if no ERET is <<
1002 1834
1003 If unsure, say Y. !! 1835 config SYS_HAS_CPU_R4X00
>> 1836 bool
1004 1837
1005 config ARM64_ERRATUM_1902691 !! 1838 config SYS_HAS_CPU_TX49XX
1006 bool "Cortex-A510: 1902691: workaroun !! 1839 bool
1007 depends on CORESIGHT_TRBE <<
1008 default y <<
1009 help <<
1010 This option adds the workaround for <<
1011 1840
1012 Affected Cortex-A510 core might cau !! 1841 config SYS_HAS_CPU_R5000
1013 into the memory. Effectively TRBE i !! 1842 bool
1014 trace data. <<
1015 <<
1016 Work around this problem in the dri <<
1017 affected cpus. The firmware must ha <<
1018 on such implementations. This will <<
1019 do this already. <<
1020 1843
1021 If unsure, say Y. !! 1844 config SYS_HAS_CPU_R5500
>> 1845 bool
1022 1846
1023 config ARM64_ERRATUM_2457168 !! 1847 config SYS_HAS_CPU_NEVADA
1024 bool "Cortex-A510: 2457168: workaroun !! 1848 bool
1025 depends on ARM64_AMU_EXTN <<
1026 default y <<
1027 help <<
1028 This option adds the workaround for <<
1029 1849
1030 The AMU counter AMEVCNTR01 (constan !! 1850 config SYS_HAS_CPU_R10000
1031 as the system counter. On affected !! 1851 bool
1032 incorrectly giving a significantly <<
1033 <<
1034 Work around this problem by returni <<
1035 key locations that results in disab <<
1036 is the same to firmware disabling a <<
1037 1852
1038 If unsure, say Y. !! 1853 config SYS_HAS_CPU_RM7000
>> 1854 bool
1039 1855
1040 config ARM64_ERRATUM_2645198 !! 1856 config SYS_HAS_CPU_SB1
1041 bool "Cortex-A715: 2645198: Workaroun !! 1857 bool
1042 default y <<
1043 help <<
1044 This option adds the workaround for <<
1045 1858
1046 If a Cortex-A715 cpu sees a page ma !! 1859 config SYS_HAS_CPU_CAVIUM_OCTEON
1047 to non-executable, it may corrupt t !! 1860 bool
1048 next instruction abort caused by pe <<
1049 <<
1050 Only user-space does executable to <<
1051 mprotect() system call. Workaround <<
1052 TLB invalidation, for all changes t <<
1053 1861
1054 If unsure, say Y. !! 1862 config SYS_HAS_CPU_BMIPS
>> 1863 bool
1055 1864
1056 config ARM64_WORKAROUND_SPECULATIVE_UNPRIV_LO !! 1865 config SYS_HAS_CPU_BMIPS32_3300
1057 bool 1866 bool
>> 1867 select SYS_HAS_CPU_BMIPS
1058 1868
1059 config ARM64_ERRATUM_2966298 !! 1869 config SYS_HAS_CPU_BMIPS4350
1060 bool "Cortex-A520: 2966298: workaroun !! 1870 bool
1061 select ARM64_WORKAROUND_SPECULATIVE_U !! 1871 select SYS_HAS_CPU_BMIPS
1062 default y <<
1063 help <<
1064 This option adds the workaround for <<
1065 1872
1066 On an affected Cortex-A520 core, a !! 1873 config SYS_HAS_CPU_BMIPS4380
1067 load might leak data from a privile !! 1874 bool
>> 1875 select SYS_HAS_CPU_BMIPS
1068 1876
1069 Work around this problem by executi !! 1877 config SYS_HAS_CPU_BMIPS5000
>> 1878 bool
>> 1879 select SYS_HAS_CPU_BMIPS
1070 1880
1071 If unsure, say Y. !! 1881 #
>> 1882 # CPU may reorder R->R, R->W, W->R, W->W
>> 1883 # Reordering beyond LL and SC is handled in WEAK_REORDERING_BEYOND_LLSC
>> 1884 #
>> 1885 config WEAK_ORDERING
>> 1886 bool
1072 1887
1073 config ARM64_ERRATUM_3117295 !! 1888 #
1074 bool "Cortex-A510: 3117295: workaroun !! 1889 # CPU may reorder reads and writes beyond LL/SC
1075 select ARM64_WORKAROUND_SPECULATIVE_U !! 1890 # CPU may reorder R->LL, R->LL, W->LL, W->LL, R->SC, R->SC, W->SC, W->SC
1076 default y !! 1891 #
1077 help !! 1892 config WEAK_REORDERING_BEYOND_LLSC
1078 This option adds the workaround for !! 1893 bool
>> 1894 endmenu
1079 1895
1080 On an affected Cortex-A510 core, a !! 1896 #
1081 load might leak data from a privile !! 1897 # These two indicate any level of the MIPS32 and MIPS64 architecture
>> 1898 #
>> 1899 config CPU_MIPS32
>> 1900 bool
>> 1901 default y if CPU_MIPS32_R1 || CPU_MIPS32_R2 || CPU_MIPS32_R5 || \
>> 1902 CPU_MIPS32_R6 || CPU_P5600
1082 1903
1083 Work around this problem by executi !! 1904 config CPU_MIPS64
>> 1905 bool
>> 1906 default y if CPU_MIPS64_R1 || CPU_MIPS64_R2 || CPU_MIPS64_R5 || \
>> 1907 CPU_MIPS64_R6 || CPU_LOONGSON64 || CPU_CAVIUM_OCTEON
1084 1908
1085 If unsure, say Y. !! 1909 #
>> 1910 # These indicate the revision of the architecture
>> 1911 #
>> 1912 config CPU_MIPSR1
>> 1913 bool
>> 1914 default y if CPU_MIPS32_R1 || CPU_MIPS64_R1
1086 1915
1087 config ARM64_ERRATUM_3194386 !! 1916 config CPU_MIPSR2
1088 bool "Cortex-*/Neoverse-*: workaround !! 1917 bool
1089 default y !! 1918 default y if CPU_MIPS32_R2 || CPU_MIPS64_R2 || CPU_CAVIUM_OCTEON
1090 help !! 1919 select CPU_HAS_RIXI
1091 This option adds the workaround for !! 1920 select CPU_HAS_DIEI if !CPU_DIEI_BROKEN
>> 1921 select MIPS_SPRAM
1092 1922
1093 * ARM Cortex-A76 erratum 3324349 !! 1923 config CPU_MIPSR5
1094 * ARM Cortex-A77 erratum 3324348 !! 1924 bool
1095 * ARM Cortex-A78 erratum 3324344 !! 1925 default y if CPU_MIPS32_R5 || CPU_MIPS64_R5 || CPU_P5600
1096 * ARM Cortex-A78C erratum 3324346 !! 1926 select CPU_HAS_RIXI
1097 * ARM Cortex-A78C erratum 3324347 !! 1927 select CPU_HAS_DIEI if !CPU_DIEI_BROKEN
1098 * ARM Cortex-A710 erratam 3324338 !! 1928 select MIPS_SPRAM
1099 * ARM Cortex-A715 errartum 3456084 <<
1100 * ARM Cortex-A720 erratum 3456091 <<
1101 * ARM Cortex-A725 erratum 3456106 <<
1102 * ARM Cortex-X1 erratum 3324344 <<
1103 * ARM Cortex-X1C erratum 3324346 <<
1104 * ARM Cortex-X2 erratum 3324338 <<
1105 * ARM Cortex-X3 erratum 3324335 <<
1106 * ARM Cortex-X4 erratum 3194386 <<
1107 * ARM Cortex-X925 erratum 3324334 <<
1108 * ARM Neoverse-N1 erratum 3324349 <<
1109 * ARM Neoverse N2 erratum 3324339 <<
1110 * ARM Neoverse-N3 erratum 3456111 <<
1111 * ARM Neoverse-V1 erratum 3324341 <<
1112 * ARM Neoverse V2 erratum 3324336 <<
1113 * ARM Neoverse-V3 erratum 3312417 <<
1114 <<
1115 On affected cores "MSR SSBS, #0" in <<
1116 subsequent speculative instructions <<
1117 speculative store bypassing. <<
1118 <<
1119 Work around this problem by placing <<
1120 Instruction Synchronization Barrier <<
1121 SSBS. The presence of the SSBS spec <<
1122 from hwcaps and EL0 reads of ID_AA6 <<
1123 will use the PR_SPEC_STORE_BYPASS p <<
1124 1929
1125 If unsure, say Y. !! 1930 config CPU_MIPSR6
>> 1931 bool
>> 1932 default y if CPU_MIPS32_R6 || CPU_MIPS64_R6
>> 1933 select CPU_HAS_RIXI
>> 1934 select CPU_HAS_DIEI if !CPU_DIEI_BROKEN
>> 1935 select HAVE_ARCH_BITREVERSE
>> 1936 select MIPS_ASID_BITS_VARIABLE
>> 1937 select MIPS_CRC_SUPPORT
>> 1938 select MIPS_SPRAM
1126 1939
1127 config CAVIUM_ERRATUM_22375 !! 1940 config TARGET_ISA_REV
1128 bool "Cavium erratum 22375, 24313" !! 1941 int
1129 default y !! 1942 default 1 if CPU_MIPSR1
>> 1943 default 2 if CPU_MIPSR2
>> 1944 default 5 if CPU_MIPSR5
>> 1945 default 6 if CPU_MIPSR6
>> 1946 default 0
1130 help 1947 help
1131 Enable workaround for errata 22375 !! 1948 Reflects the ISA revision being targeted by the kernel build. This
>> 1949 is effectively the Kconfig equivalent of MIPS_ISA_REV.
1132 1950
1133 This implements two gicv3-its errat !! 1951 config EVA
1134 with a small impact affecting only !! 1952 bool
>> 1953
>> 1954 config XPA
>> 1955 bool
>> 1956
>> 1957 config SYS_SUPPORTS_32BIT_KERNEL
>> 1958 bool
>> 1959 config SYS_SUPPORTS_64BIT_KERNEL
>> 1960 bool
>> 1961 config CPU_SUPPORTS_32BIT_KERNEL
>> 1962 bool
>> 1963 config CPU_SUPPORTS_64BIT_KERNEL
>> 1964 bool
>> 1965 config CPU_SUPPORTS_CPUFREQ
>> 1966 bool
>> 1967 config CPU_SUPPORTS_ADDRWINCFG
>> 1968 bool
>> 1969 config CPU_SUPPORTS_HUGEPAGES
>> 1970 bool
>> 1971 depends on !(32BIT && (PHYS_ADDR_T_64BIT || EVA))
>> 1972 config MIPS_PGD_C0_CONTEXT
>> 1973 bool
>> 1974 depends on 64BIT
>> 1975 default y if (CPU_MIPSR2 || CPU_MIPSR6)
1135 1976
1136 erratum 22375: only alloc 8MB tab !! 1977 #
1137 erratum 24313: ignore memory acce !! 1978 # Set to y for ptrace access to watch registers.
>> 1979 #
>> 1980 config HARDWARE_WATCHPOINTS
>> 1981 bool
>> 1982 default y if CPU_MIPSR1 || CPU_MIPSR2 || CPU_MIPSR6
1138 1983
1139 The fixes are in ITS initialization !! 1984 menu "Kernel type"
1140 type and table size provided by the <<
1141 1985
1142 If unsure, say Y. !! 1986 choice
>> 1987 prompt "Kernel code model"
>> 1988 help
>> 1989 You should only select this option if you have a workload that
>> 1990 actually benefits from 64-bit processing or if your machine has
>> 1991 large memory. You will only be presented a single option in this
>> 1992 menu if your system does not support both 32-bit and 64-bit kernels.
>> 1993
>> 1994 config 32BIT
>> 1995 bool "32-bit kernel"
>> 1996 depends on CPU_SUPPORTS_32BIT_KERNEL && SYS_SUPPORTS_32BIT_KERNEL
>> 1997 select TRAD_SIGNALS
>> 1998 help
>> 1999 Select this option if you want to build a 32-bit kernel.
1143 2000
1144 config CAVIUM_ERRATUM_23144 !! 2001 config 64BIT
1145 bool "Cavium erratum 23144: ITS SYNC !! 2002 bool "64-bit kernel"
1146 depends on NUMA !! 2003 depends on CPU_SUPPORTS_64BIT_KERNEL && SYS_SUPPORTS_64BIT_KERNEL
1147 default y <<
1148 help 2004 help
1149 ITS SYNC command hang for cross nod !! 2005 Select this option if you want to build a 64-bit kernel.
1150 2006
1151 If unsure, say Y. !! 2007 endchoice
1152 2008
1153 config CAVIUM_ERRATUM_23154 !! 2009 config MIPS_VA_BITS_48
1154 bool "Cavium errata 23154 and 38545: !! 2010 bool "48 bits virtual memory"
1155 default y !! 2011 depends on 64BIT
1156 help !! 2012 help
1157 The ThunderX GICv3 implementation r !! 2013 Support a maximum at least 48 bits of application virtual
1158 reading the IAR status to ensure da !! 2014 memory. Default is 40 bits or less, depending on the CPU.
1159 (access to icc_iar1_el1 is not sync !! 2015 For page sizes 16k and above, this option results in a small
1160 !! 2016 memory overhead for page tables. For 4k page size, a fourth
1161 It also suffers from erratum 38545 !! 2017 level of page tables is added which imposes both a memory
1162 OcteonTX and OcteonTX2), resulting !! 2018 overhead as well as slower TLB fault handling.
1163 spuriously presented to the CPU int <<
1164 2019
1165 If unsure, say Y. !! 2020 If unsure, say N.
1166 2021
1167 config CAVIUM_ERRATUM_27456 !! 2022 config ZBOOT_LOAD_ADDRESS
1168 bool "Cavium erratum 27456: Broadcast !! 2023 hex "Compressed kernel load address"
1169 default y !! 2024 default 0xffffffff80400000 if BCM47XX
>> 2025 default 0x0
>> 2026 depends on SYS_SUPPORTS_ZBOOT
1170 help 2027 help
1171 On ThunderX T88 pass 1.x through 2. !! 2028 The address to load compressed kernel, aka vmlinuz.
1172 instructions may cause the icache t <<
1173 contains data for a non-current ASI <<
1174 invalidate the icache when changing <<
1175 2029
1176 If unsure, say Y. !! 2030 This is only used if non-zero.
1177 2031
1178 config CAVIUM_ERRATUM_30115 !! 2032 choice
1179 bool "Cavium erratum 30115: Guest may !! 2033 prompt "Kernel page size"
1180 default y !! 2034 default PAGE_SIZE_4KB
1181 help <<
1182 On ThunderX T88 pass 1.x through 2. <<
1183 1.2, and T83 Pass 1.0, KVM guest ex <<
1184 interrupts in host. Trapping both G <<
1185 accesses sidesteps the issue. <<
1186 2035
1187 If unsure, say Y. !! 2036 config PAGE_SIZE_4KB
>> 2037 bool "4kB"
>> 2038 depends on !CPU_LOONGSON2EF && !CPU_LOONGSON64
>> 2039 help
>> 2040 This option select the standard 4kB Linux page size. On some
>> 2041 R3000-family processors this is the only available page size. Using
>> 2042 4kB page size will minimize memory consumption and is therefore
>> 2043 recommended for low memory systems.
>> 2044
>> 2045 config PAGE_SIZE_8KB
>> 2046 bool "8kB"
>> 2047 depends on CPU_CAVIUM_OCTEON
>> 2048 depends on !MIPS_VA_BITS_48
>> 2049 help
>> 2050 Using 8kB page size will result in higher performance kernel at
>> 2051 the price of higher memory consumption. This option is available
>> 2052 only on cnMIPS processors. Note that you will need a suitable Linux
>> 2053 distribution to support this.
>> 2054
>> 2055 config PAGE_SIZE_16KB
>> 2056 bool "16kB"
>> 2057 depends on !CPU_R3000
>> 2058 help
>> 2059 Using 16kB page size will result in higher performance kernel at
>> 2060 the price of higher memory consumption. This option is available on
>> 2061 all non-R3000 family processors. Note that you will need a suitable
>> 2062 Linux distribution to support this.
>> 2063
>> 2064 config PAGE_SIZE_32KB
>> 2065 bool "32kB"
>> 2066 depends on CPU_CAVIUM_OCTEON
>> 2067 depends on !MIPS_VA_BITS_48
>> 2068 help
>> 2069 Using 32kB page size will result in higher performance kernel at
>> 2070 the price of higher memory consumption. This option is available
>> 2071 only on cnMIPS cores. Note that you will need a suitable Linux
>> 2072 distribution to support this.
>> 2073
>> 2074 config PAGE_SIZE_64KB
>> 2075 bool "64kB"
>> 2076 depends on !CPU_R3000
>> 2077 help
>> 2078 Using 64kB page size will result in higher performance kernel at
>> 2079 the price of higher memory consumption. This option is available on
>> 2080 all non-R3000 family processor. Not that at the time of this
>> 2081 writing this option is still high experimental.
1188 2082
1189 config CAVIUM_TX2_ERRATUM_219 !! 2083 endchoice
1190 bool "Cavium ThunderX2 erratum 219: P !! 2084
1191 default y !! 2085 config ARCH_FORCE_MAX_ORDER
>> 2086 int "Maximum zone order"
>> 2087 default "13" if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_64KB
>> 2088 default "12" if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_32KB
>> 2089 default "11" if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_16KB
>> 2090 default "10"
1192 help 2091 help
1193 On Cavium ThunderX2, a load, store !! 2092 The kernel memory allocator divides physically contiguous memory
1194 TTBR update and the corresponding c !! 2093 blocks into "zones", where each zone is a power of two number of
1195 cause a spurious Data Abort to be d !! 2094 pages. This option selects the largest power of two that the kernel
1196 the CPU core. !! 2095 keeps in the memory allocator. If you need to allocate very large
1197 !! 2096 blocks of physically contiguous memory, then you may need to
1198 Work around the issue by avoiding t !! 2097 increase this value.
1199 trapping KVM guest TTBRx_EL1 writes <<
1200 trap handler performs the correspon <<
1201 instruction and ensures context syn <<
1202 exception return. <<
1203 2098
1204 If unsure, say Y. !! 2099 The page size is not necessarily 4KB. Keep this in mind
>> 2100 when choosing a value for this option.
1205 2101
1206 config FUJITSU_ERRATUM_010001 !! 2102 config BOARD_SCACHE
1207 bool "Fujitsu-A64FX erratum E#010001: !! 2103 bool
1208 default y <<
1209 help <<
1210 This option adds a workaround for F <<
1211 On some variants of the Fujitsu-A64 <<
1212 accesses may cause undefined fault <<
1213 This fault occurs under a specific <<
1214 load/store instruction performs an <<
1215 case-1 TTBR0_EL1 with TCR_EL1.NFD0 <<
1216 case-2 TTBR0_EL2 with TCR_EL2.NFD0 <<
1217 case-3 TTBR1_EL1 with TCR_EL1.NFD1 <<
1218 case-4 TTBR1_EL2 with TCR_EL2.NFD1 <<
1219 2104
1220 The workaround is to ensure these b !! 2105 config IP22_CPU_SCACHE
1221 The workaround only affects the Fuj !! 2106 bool
>> 2107 select BOARD_SCACHE
1222 2108
1223 If unsure, say Y. !! 2109 #
>> 2110 # Support for a MIPS32 / MIPS64 style S-caches
>> 2111 #
>> 2112 config MIPS_CPU_SCACHE
>> 2113 bool
>> 2114 select BOARD_SCACHE
1224 2115
1225 config HISILICON_ERRATUM_161600802 !! 2116 config R5000_CPU_SCACHE
1226 bool "Hip07 161600802: Erroneous redi !! 2117 bool
1227 default y !! 2118 select BOARD_SCACHE
1228 help <<
1229 The HiSilicon Hip07 SoC uses the wr <<
1230 when issued ITS commands such as VM <<
1231 a 128kB offset to be applied to the <<
1232 2119
1233 If unsure, say Y. !! 2120 config RM7000_CPU_SCACHE
>> 2121 bool
>> 2122 select BOARD_SCACHE
1234 2123
1235 config QCOM_FALKOR_ERRATUM_1003 !! 2124 config SIBYTE_DMA_PAGEOPS
1236 bool "Falkor E1003: Incorrect transla !! 2125 bool "Use DMA to clear/copy pages"
1237 default y !! 2126 depends on CPU_SB1
1238 help 2127 help
1239 On Falkor v1, an incorrect ASID may !! 2128 Instead of using the CPU to zero and copy pages, use a Data Mover
1240 and BADDR are changed together in T !! 2129 channel. These DMA channels are otherwise unused by the standard
1241 in TTBR1_EL1, this situation only o !! 2130 SiByte Linux port. Seems to give a small performance benefit.
1242 then only for entries in the walk c <<
1243 is unchanged. Work around the errat <<
1244 entries for the trampoline before e <<
1245 2131
1246 config QCOM_FALKOR_ERRATUM_1009 !! 2132 config CPU_HAS_PREFETCH
1247 bool "Falkor E1009: Prematurely compl !! 2133 bool
1248 default y <<
1249 select ARM64_WORKAROUND_REPEAT_TLBI <<
1250 help <<
1251 On Falkor v1, the CPU may premature <<
1252 TLBI xxIS invalidate maintenance op <<
1253 one more time to fix the issue. <<
1254 2134
1255 If unsure, say Y. !! 2135 config CPU_GENERIC_DUMP_TLB
>> 2136 bool
>> 2137 default y if !CPU_R3000
1256 2138
1257 config QCOM_QDF2400_ERRATUM_0065 !! 2139 config MIPS_FP_SUPPORT
1258 bool "QDF2400 E0065: Incorrect GITS_T !! 2140 bool "Floating Point support" if EXPERT
1259 default y 2141 default y
1260 help 2142 help
1261 On Qualcomm Datacenter Technologies !! 2143 Select y to include support for floating point in the kernel
1262 ITE size incorrectly. The GITS_TYPE !! 2144 including initialization of FPU hardware, FP context save & restore
1263 been indicated as 16Bytes (0xf), no !! 2145 and emulation of an FPU where necessary. Without this support any
>> 2146 userland program attempting to use floating point instructions will
>> 2147 receive a SIGILL.
1264 2148
1265 If unsure, say Y. !! 2149 If you know that your userland will not attempt to use floating point
>> 2150 instructions then you can say n here to shrink the kernel a little.
1266 2151
1267 config QCOM_FALKOR_ERRATUM_E1041 !! 2152 If unsure, say y.
1268 bool "Falkor E1041: Speculative instr <<
1269 default y <<
1270 help <<
1271 Falkor CPU may speculatively fetch <<
1272 memory location when MMU translatio <<
1273 to SCTLR_ELn[M]=0. Prefix an ISB in <<
1274 2153
1275 If unsure, say Y. !! 2154 config CPU_R2300_FPU
>> 2155 bool
>> 2156 depends on MIPS_FP_SUPPORT
>> 2157 default y if CPU_R3000
1276 2158
1277 config NVIDIA_CARMEL_CNP_ERRATUM !! 2159 config CPU_R3K_TLB
1278 bool "NVIDIA Carmel CNP: CNP on Carme !! 2160 bool
1279 default y <<
1280 help <<
1281 If CNP is enabled on Carmel cores, <<
1282 invalidate shared TLB entries insta <<
1283 on standard ARM cores. <<
1284 2161
1285 If unsure, say Y. !! 2162 config CPU_R4K_FPU
>> 2163 bool
>> 2164 depends on MIPS_FP_SUPPORT
>> 2165 default y if !CPU_R2300_FPU
>> 2166
>> 2167 config CPU_R4K_CACHE_TLB
>> 2168 bool
>> 2169 default y if !(CPU_R3K_TLB || CPU_SB1 || CPU_CAVIUM_OCTEON)
1286 2170
1287 config ROCKCHIP_ERRATUM_3588001 !! 2171 config MIPS_MT_SMP
1288 bool "Rockchip 3588001: GIC600 can no !! 2172 bool "MIPS MT SMP support (1 TC on each available VPE)"
1289 default y 2173 default y
1290 help !! 2174 depends on SYS_SUPPORTS_MULTITHREADING && !CPU_MIPSR6 && !CPU_MICROMIPS
1291 The Rockchip RK3588 GIC600 SoC inte !! 2175 select CPU_MIPSR2_IRQ_VI
1292 This means, that its sharability fe !! 2176 select CPU_MIPSR2_IRQ_EI
1293 is supported by the IP itself. !! 2177 select SYNC_R4K
>> 2178 select MIPS_MT
>> 2179 select SMP
>> 2180 select SMP_UP
>> 2181 select SYS_SUPPORTS_SMP
>> 2182 select SYS_SUPPORTS_SCHED_SMT
>> 2183 select MIPS_PERF_SHARED_TC_COUNTERS
>> 2184 help
>> 2185 This is a kernel model which is known as SMVP. This is supported
>> 2186 on cores with the MT ASE and uses the available VPEs to implement
>> 2187 virtual processors which supports SMP. This is equivalent to the
>> 2188 Intel Hyperthreading feature. For further information go to
>> 2189 <http://www.imgtec.com/mips/mips-multithreading.asp>.
1294 2190
1295 If unsure, say Y. !! 2191 config MIPS_MT
>> 2192 bool
1296 2193
1297 config SOCIONEXT_SYNQUACER_PREITS !! 2194 config SCHED_SMT
1298 bool "Socionext Synquacer: Workaround !! 2195 bool "SMT (multithreading) scheduler support"
1299 default y !! 2196 depends on SYS_SUPPORTS_SCHED_SMT
>> 2197 default n
1300 help 2198 help
1301 Socionext Synquacer SoCs implement !! 2199 SMT scheduler support improves the CPU scheduler's decision making
1302 MSI doorbell writes with non-zero v !! 2200 when dealing with MIPS MT enabled cores at a cost of slightly
>> 2201 increased overhead in some places. If unsure say N here.
1303 2202
1304 If unsure, say Y. !! 2203 config SYS_SUPPORTS_SCHED_SMT
>> 2204 bool
1305 2205
1306 endmenu # "ARM errata workarounds via the alt !! 2206 config SYS_SUPPORTS_MULTITHREADING
>> 2207 bool
1307 2208
1308 choice !! 2209 config MIPS_MT_FPAFF
1309 prompt "Page size" !! 2210 bool "Dynamic FPU affinity for FP-intensive threads"
1310 default ARM64_4K_PAGES !! 2211 default y
1311 help !! 2212 depends on MIPS_MT_SMP
1312 Page size (translation granule) con <<
1313 2213
1314 config ARM64_4K_PAGES !! 2214 config MIPSR2_TO_R6_EMULATOR
1315 bool "4KB" !! 2215 bool "MIPS R2-to-R6 emulator"
1316 select HAVE_PAGE_SIZE_4KB !! 2216 depends on CPU_MIPSR6
>> 2217 depends on MIPS_FP_SUPPORT
>> 2218 default y
1317 help 2219 help
1318 This feature enables 4KB pages supp !! 2220 Choose this option if you want to run non-R6 MIPS userland code.
>> 2221 Even if you say 'Y' here, the emulator will still be disabled by
>> 2222 default. You can enable it using the 'mipsr2emu' kernel option.
>> 2223 The only reason this is a build-time option is to save ~14K from the
>> 2224 final kernel image.
1319 2225
1320 config ARM64_16K_PAGES !! 2226 config SYS_SUPPORTS_VPE_LOADER
1321 bool "16KB" !! 2227 bool
1322 select HAVE_PAGE_SIZE_16KB !! 2228 depends on SYS_SUPPORTS_MULTITHREADING
1323 help 2229 help
1324 The system will use 16KB pages supp !! 2230 Indicates that the platform supports the VPE loader, and provides
1325 requires applications compiled with !! 2231 physical_memsize.
1326 aligned segments. <<
1327 2232
1328 config ARM64_64K_PAGES !! 2233 config MIPS_VPE_LOADER
1329 bool "64KB" !! 2234 bool "VPE loader support."
1330 select HAVE_PAGE_SIZE_64KB !! 2235 depends on SYS_SUPPORTS_VPE_LOADER && MODULES
>> 2236 select CPU_MIPSR2_IRQ_VI
>> 2237 select CPU_MIPSR2_IRQ_EI
>> 2238 select MIPS_MT
1331 help 2239 help
1332 This feature enables 64KB pages sup !! 2240 Includes a loader for loading an elf relocatable object
1333 allowing only two levels of page ta !! 2241 onto another VPE and running it.
1334 look-up. AArch32 emulation requires <<
1335 with 64K aligned segments. <<
1336 2242
1337 endchoice !! 2243 config MIPS_VPE_LOADER_MT
>> 2244 bool
>> 2245 default "y"
>> 2246 depends on MIPS_VPE_LOADER
1338 2247
1339 choice !! 2248 config MIPS_VPE_LOADER_TOM
1340 prompt "Virtual address space size" !! 2249 bool "Load VPE program into memory hidden from linux"
1341 default ARM64_VA_BITS_52 !! 2250 depends on MIPS_VPE_LOADER
>> 2251 default y
1342 help 2252 help
1343 Allows choosing one of multiple pos !! 2253 The loader can use memory that is present but has been hidden from
1344 space sizes. The level of translati !! 2254 Linux using the kernel command line option "mem=xxMB". It's up to
1345 a combination of page size and virt !! 2255 you to ensure the amount you put in the option and the space your
1346 !! 2256 program requires is less or equal to the amount physically present.
1347 config ARM64_VA_BITS_36 <<
1348 bool "36-bit" if EXPERT <<
1349 depends on PAGE_SIZE_16KB <<
1350 <<
1351 config ARM64_VA_BITS_39 <<
1352 bool "39-bit" <<
1353 depends on PAGE_SIZE_4KB <<
1354 <<
1355 config ARM64_VA_BITS_42 <<
1356 bool "42-bit" <<
1357 depends on PAGE_SIZE_64KB <<
1358 <<
1359 config ARM64_VA_BITS_47 <<
1360 bool "47-bit" <<
1361 depends on PAGE_SIZE_16KB <<
1362 <<
1363 config ARM64_VA_BITS_48 <<
1364 bool "48-bit" <<
1365 <<
1366 config ARM64_VA_BITS_52 <<
1367 bool "52-bit" <<
1368 depends on ARM64_PAN || !ARM64_SW_TTB <<
1369 help <<
1370 Enable 52-bit virtual addressing fo <<
1371 requested via a hint to mmap(). The <<
1372 virtual addresses for its own mappi <<
1373 this feature is available, otherwis <<
1374 <<
1375 NOTE: Enabling 52-bit virtual addre <<
1376 ARMv8.3 Pointer Authentication will <<
1377 reduced from 7 bits to 3 bits, whic <<
1378 impact on its susceptibility to bru <<
1379 2257
1380 If unsure, select 48-bit virtual ad !! 2258 config MIPS_VPE_APSP_API
>> 2259 bool "Enable support for AP/SP API (RTLX)"
>> 2260 depends on MIPS_VPE_LOADER
1381 2261
1382 endchoice !! 2262 config MIPS_VPE_APSP_API_MT
1383 !! 2263 bool
1384 config ARM64_FORCE_52BIT !! 2264 default "y"
1385 bool "Force 52-bit virtual addresses !! 2265 depends on MIPS_VPE_APSP_API
1386 depends on ARM64_VA_BITS_52 && EXPERT <<
1387 help <<
1388 For systems with 52-bit userspace V <<
1389 to maintain compatibility with olde <<
1390 unless a hint is supplied to mmap. <<
1391 <<
1392 This configuration option disables <<
1393 forces all userspace addresses to b <<
1394 should only enable this configurati <<
1395 memory management code. If unsure s <<
1396 2266
1397 config ARM64_VA_BITS !! 2267 config MIPS_CPS
1398 int !! 2268 bool "MIPS Coherent Processing System support"
1399 default 36 if ARM64_VA_BITS_36 !! 2269 depends on SYS_SUPPORTS_MIPS_CPS
1400 default 39 if ARM64_VA_BITS_39 !! 2270 select MIPS_CM
1401 default 42 if ARM64_VA_BITS_42 !! 2271 select MIPS_CPS_PM if HOTPLUG_CPU
1402 default 47 if ARM64_VA_BITS_47 !! 2272 select SMP
1403 default 48 if ARM64_VA_BITS_48 !! 2273 select HOTPLUG_CORE_SYNC_DEAD if HOTPLUG_CPU
1404 default 52 if ARM64_VA_BITS_52 !! 2274 select SYNC_R4K if (CEVT_R4K || CSRC_R4K)
>> 2275 select SYS_SUPPORTS_HOTPLUG_CPU
>> 2276 select SYS_SUPPORTS_SCHED_SMT if CPU_MIPSR6
>> 2277 select SYS_SUPPORTS_SMP
>> 2278 select WEAK_ORDERING
>> 2279 select GENERIC_IRQ_MIGRATION if HOTPLUG_CPU
>> 2280 help
>> 2281 Select this if you wish to run an SMP kernel across multiple cores
>> 2282 within a MIPS Coherent Processing System. When this option is
>> 2283 enabled the kernel will probe for other cores and boot them with
>> 2284 no external assistance. It is safe to enable this when hardware
>> 2285 support is unavailable.
1405 2286
1406 choice !! 2287 config MIPS_CPS_PM
1407 prompt "Physical address space size" !! 2288 depends on MIPS_CPS
1408 default ARM64_PA_BITS_48 !! 2289 bool
1409 help <<
1410 Choose the maximum physical address <<
1411 support. <<
1412 2290
1413 config ARM64_PA_BITS_48 !! 2291 config MIPS_CM
1414 bool "48-bit" !! 2292 bool
1415 depends on ARM64_64K_PAGES || !ARM64_ !! 2293 select MIPS_CPC
1416 <<
1417 config ARM64_PA_BITS_52 <<
1418 bool "52-bit" <<
1419 depends on ARM64_64K_PAGES || ARM64_V <<
1420 depends on ARM64_PAN || !ARM64_SW_TTB <<
1421 help <<
1422 Enable support for a 52-bit physica <<
1423 part of the ARMv8.2-LPA extension. <<
1424 <<
1425 With this enabled, the kernel will <<
1426 do not support ARMv8.2-LPA, but wit <<
1427 minor performance overhead). <<
1428 2294
1429 endchoice !! 2295 config MIPS_CPC
>> 2296 bool
1430 2297
1431 config ARM64_PA_BITS !! 2298 config SB1_PASS_2_WORKAROUNDS
1432 int !! 2299 bool
1433 default 48 if ARM64_PA_BITS_48 !! 2300 depends on CPU_SB1 && (CPU_SB1_PASS_2_2 || CPU_SB1_PASS_2)
1434 default 52 if ARM64_PA_BITS_52 !! 2301 default y
1435 2302
1436 config ARM64_LPA2 !! 2303 config SB1_PASS_2_1_WORKAROUNDS
1437 def_bool y !! 2304 bool
1438 depends on ARM64_PA_BITS_52 && !ARM64 !! 2305 depends on CPU_SB1 && CPU_SB1_PASS_2
>> 2306 default y
1439 2307
1440 choice 2308 choice
1441 prompt "Endianness" !! 2309 prompt "SmartMIPS or microMIPS ASE support"
1442 default CPU_LITTLE_ENDIAN <<
1443 help <<
1444 Select the endianness of data acces <<
1445 applications will need to be compil <<
1446 that is selected here. <<
1447 2310
1448 config CPU_BIG_ENDIAN !! 2311 config CPU_NEEDS_NO_SMARTMIPS_OR_MICROMIPS
1449 bool "Build big-endian kernel" !! 2312 bool "None"
1450 # https://github.com/llvm/llvm-projec <<
1451 depends on AS_IS_GNU || AS_VERSION >= <<
1452 help 2313 help
1453 Say Y if you plan on running a kern !! 2314 Select this if you want neither microMIPS nor SmartMIPS support
1454 2315
1455 config CPU_LITTLE_ENDIAN !! 2316 config CPU_HAS_SMARTMIPS
1456 bool "Build little-endian kernel" !! 2317 depends on SYS_SUPPORTS_SMARTMIPS
>> 2318 bool "SmartMIPS"
>> 2319 help
>> 2320 SmartMIPS is a extension of the MIPS32 architecture aimed at
>> 2321 increased security at both hardware and software level for
>> 2322 smartcards. Enabling this option will allow proper use of the
>> 2323 SmartMIPS instructions by Linux applications. However a kernel with
>> 2324 this option will not work on a MIPS core without SmartMIPS core. If
>> 2325 you don't know you probably don't have SmartMIPS and should say N
>> 2326 here.
>> 2327
>> 2328 config CPU_MICROMIPS
>> 2329 depends on 32BIT && SYS_SUPPORTS_MICROMIPS && !CPU_MIPSR6
>> 2330 bool "microMIPS"
1457 help 2331 help
1458 Say Y if you plan on running a kern !! 2332 When this option is enabled the kernel will be built using the
1459 This is usually the case for distri !! 2333 microMIPS ISA
1460 2334
1461 endchoice 2335 endchoice
1462 2336
1463 config SCHED_MC !! 2337 config CPU_HAS_MSA
1464 bool "Multi-core scheduler support" !! 2338 bool "Support for the MIPS SIMD Architecture"
1465 help !! 2339 depends on CPU_SUPPORTS_MSA
1466 Multi-core scheduler support improv !! 2340 depends on MIPS_FP_SUPPORT
1467 making when dealing with multi-core !! 2341 depends on 64BIT || MIPS_O32_FP64_SUPPORT
1468 increased overhead in some places. !! 2342 help
>> 2343 MIPS SIMD Architecture (MSA) introduces 128 bit wide vector registers
>> 2344 and a set of SIMD instructions to operate on them. When this option
>> 2345 is enabled the kernel will support allocating & switching MSA
>> 2346 vector register contexts. If you know that your kernel will only be
>> 2347 running on CPUs which do not support MSA or that your userland will
>> 2348 not be making use of it then you may wish to say N here to reduce
>> 2349 the size & complexity of your kernel.
1469 2350
1470 config SCHED_CLUSTER !! 2351 If unsure, say Y.
1471 bool "Cluster scheduler support" <<
1472 help <<
1473 Cluster scheduler support improves <<
1474 making when dealing with machines t <<
1475 Cluster usually means a couple of C <<
1476 by sharing mid-level caches, last-l <<
1477 busses. <<
1478 2352
1479 config SCHED_SMT !! 2353 config CPU_HAS_WB
1480 bool "SMT scheduler support" !! 2354 bool
1481 help <<
1482 Improves the CPU scheduler's decisi <<
1483 MultiThreading at a cost of slightl <<
1484 places. If unsure say N here. <<
1485 2355
1486 config NR_CPUS !! 2356 config XKS01
1487 int "Maximum number of CPUs (2-4096)" !! 2357 bool
1488 range 2 4096 <<
1489 default "512" <<
1490 2358
1491 config HOTPLUG_CPU !! 2359 config CPU_HAS_DIEI
1492 bool "Support for hot-pluggable CPUs" !! 2360 depends on !CPU_DIEI_BROKEN
1493 select GENERIC_IRQ_MIGRATION !! 2361 bool
1494 help <<
1495 Say Y here to experiment with turni <<
1496 can be controlled through /sys/devi <<
1497 2362
1498 # Common NUMA Features !! 2363 config CPU_DIEI_BROKEN
1499 config NUMA !! 2364 bool
1500 bool "NUMA Memory Allocation and Sche <<
1501 select GENERIC_ARCH_NUMA <<
1502 select OF_NUMA <<
1503 select HAVE_SETUP_PER_CPU_AREA <<
1504 select NEED_PER_CPU_EMBED_FIRST_CHUNK <<
1505 select NEED_PER_CPU_PAGE_FIRST_CHUNK <<
1506 select USE_PERCPU_NUMA_NODE_ID <<
1507 help <<
1508 Enable NUMA (Non-Uniform Memory Acc <<
1509 2365
1510 The kernel will try to allocate mem !! 2366 config CPU_HAS_RIXI
1511 local memory of the CPU and add som !! 2367 bool
1512 NUMA awareness to the kernel. <<
1513 2368
1514 config NODES_SHIFT !! 2369 config CPU_NO_LOAD_STORE_LR
1515 int "Maximum NUMA Nodes (as a power o !! 2370 bool
1516 range 1 10 <<
1517 default "4" <<
1518 depends on NUMA <<
1519 help 2371 help
1520 Specify the maximum number of NUMA !! 2372 CPU lacks support for unaligned load and store instructions:
1521 system. Increases memory reserved !! 2373 LWL, LWR, SWL, SWR (Load/store word left/right).
>> 2374 LDL, LDR, SDL, SDR (Load/store doubleword left/right, for 64bit
>> 2375 systems).
1522 2376
1523 source "kernel/Kconfig.hz" !! 2377 #
>> 2378 # Vectored interrupt mode is an R2 feature
>> 2379 #
>> 2380 config CPU_MIPSR2_IRQ_VI
>> 2381 bool
1524 2382
1525 config ARCH_SPARSEMEM_ENABLE !! 2383 #
1526 def_bool y !! 2384 # Extended interrupt mode is an R2 feature
1527 select SPARSEMEM_VMEMMAP_ENABLE !! 2385 #
1528 select SPARSEMEM_VMEMMAP !! 2386 config CPU_MIPSR2_IRQ_EI
>> 2387 bool
1529 2388
1530 config HW_PERF_EVENTS !! 2389 config CPU_HAS_SYNC
1531 def_bool y !! 2390 bool
1532 depends on ARM_PMU !! 2391 depends on !CPU_R3000
>> 2392 default y
1533 2393
1534 # Supported by clang >= 7.0 or GCC >= 12.0.0 !! 2394 #
1535 config CC_HAVE_SHADOW_CALL_STACK !! 2395 # CPU non-features
1536 def_bool $(cc-option, -fsanitize=shad !! 2396 #
1537 2397
1538 config PARAVIRT !! 2398 # Work around the "daddi" and "daddiu" CPU errata:
1539 bool "Enable paravirtualization code" !! 2399 #
1540 help !! 2400 # - The `daddi' instruction fails to trap on overflow.
1541 This changes the kernel so it can m !! 2401 # "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0",
1542 under a hypervisor, potentially imp !! 2402 # erratum #23
1543 over full virtualization. !! 2403 #
>> 2404 # - The `daddiu' instruction can produce an incorrect result.
>> 2405 # "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0",
>> 2406 # erratum #41
>> 2407 # "MIPS R4000MC Errata, Processor Revision 2.2 and 3.0", erratum
>> 2408 # #15
>> 2409 # "MIPS R4400PC/SC Errata, Processor Revision 1.0", erratum #7
>> 2410 # "MIPS R4400MC Errata, Processor Revision 1.0", erratum #5
>> 2411 config CPU_DADDI_WORKAROUNDS
>> 2412 bool
1544 2413
1545 config PARAVIRT_TIME_ACCOUNTING !! 2414 # Work around certain R4000 CPU errata (as implemented by GCC):
1546 bool "Paravirtual steal time accounti !! 2415 #
1547 select PARAVIRT !! 2416 # - A double-word or a variable shift may give an incorrect result
1548 help !! 2417 # if executed immediately after starting an integer division:
1549 Select this option to enable fine g !! 2418 # "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0",
1550 accounting. Time spent executing ot !! 2419 # erratum #28
1551 the current vCPU is discounted from !! 2420 # "MIPS R4000MC Errata, Processor Revision 2.2 and 3.0", erratum
1552 that, there can be a small performa !! 2421 # #19
>> 2422 #
>> 2423 # - A double-word or a variable shift may give an incorrect result
>> 2424 # if executed while an integer multiplication is in progress:
>> 2425 # "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0",
>> 2426 # errata #16 & #28
>> 2427 #
>> 2428 # - An integer division may give an incorrect result if started in
>> 2429 # a delay slot of a taken branch or a jump:
>> 2430 # "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0",
>> 2431 # erratum #52
>> 2432 config CPU_R4000_WORKAROUNDS
>> 2433 bool
>> 2434 select CPU_R4400_WORKAROUNDS
1553 2435
1554 If in doubt, say N here. !! 2436 # Work around certain R4400 CPU errata (as implemented by GCC):
>> 2437 #
>> 2438 # - A double-word or a variable shift may give an incorrect result
>> 2439 # if executed immediately after starting an integer division:
>> 2440 # "MIPS R4400MC Errata, Processor Revision 1.0", erratum #10
>> 2441 # "MIPS R4400MC Errata, Processor Revision 2.0 & 3.0", erratum #4
>> 2442 config CPU_R4400_WORKAROUNDS
>> 2443 bool
1555 2444
1556 config ARCH_SUPPORTS_KEXEC !! 2445 config CPU_R4X00_BUGS64
1557 def_bool PM_SLEEP_SMP !! 2446 bool
>> 2447 default y if SYS_HAS_CPU_R4X00 && 64BIT && (TARGET_ISA_REV < 1)
1558 2448
1559 config ARCH_SUPPORTS_KEXEC_FILE !! 2449 config MIPS_ASID_SHIFT
1560 def_bool y !! 2450 int
>> 2451 default 6 if CPU_R3000
>> 2452 default 0
1561 2453
1562 config ARCH_SELECTS_KEXEC_FILE !! 2454 config MIPS_ASID_BITS
1563 def_bool y !! 2455 int
1564 depends on KEXEC_FILE !! 2456 default 0 if MIPS_ASID_BITS_VARIABLE
1565 select HAVE_IMA_KEXEC if IMA !! 2457 default 6 if CPU_R3000
>> 2458 default 8
1566 2459
1567 config ARCH_SUPPORTS_KEXEC_SIG !! 2460 config MIPS_ASID_BITS_VARIABLE
1568 def_bool y !! 2461 bool
1569 2462
1570 config ARCH_SUPPORTS_KEXEC_IMAGE_VERIFY_SIG !! 2463 config MIPS_CRC_SUPPORT
1571 def_bool y !! 2464 bool
1572 2465
1573 config ARCH_DEFAULT_KEXEC_IMAGE_VERIFY_SIG !! 2466 # R4600 erratum. Due to the lack of errata information the exact
1574 def_bool y !! 2467 # technical details aren't known. I've experimentally found that disabling
>> 2468 # interrupts during indexed I-cache flushes seems to be sufficient to deal
>> 2469 # with the issue.
>> 2470 config WAR_R4600_V1_INDEX_ICACHEOP
>> 2471 bool
1575 2472
1576 config ARCH_SUPPORTS_CRASH_DUMP !! 2473 # Pleasures of the R4600 V1.x. Cite from the IDT R4600 V1.7 errata:
1577 def_bool y !! 2474 #
>> 2475 # 18. The CACHE instructions Hit_Writeback_Invalidate_D, Hit_Writeback_D,
>> 2476 # Hit_Invalidate_D and Create_Dirty_Excl_D should only be
>> 2477 # executed if there is no other dcache activity. If the dcache is
>> 2478 # accessed for another instruction immediately preceding when these
>> 2479 # cache instructions are executing, it is possible that the dcache
>> 2480 # tag match outputs used by these cache instructions will be
>> 2481 # incorrect. These cache instructions should be preceded by at least
>> 2482 # four instructions that are not any kind of load or store
>> 2483 # instruction.
>> 2484 #
>> 2485 # This is not allowed: lw
>> 2486 # nop
>> 2487 # nop
>> 2488 # nop
>> 2489 # cache Hit_Writeback_Invalidate_D
>> 2490 #
>> 2491 # This is allowed: lw
>> 2492 # nop
>> 2493 # nop
>> 2494 # nop
>> 2495 # nop
>> 2496 # cache Hit_Writeback_Invalidate_D
>> 2497 config WAR_R4600_V1_HIT_CACHEOP
>> 2498 bool
>> 2499
>> 2500 # Writeback and invalidate the primary cache dcache before DMA.
>> 2501 #
>> 2502 # R4600 v2.0 bug: "The CACHE instructions Hit_Writeback_Inv_D,
>> 2503 # Hit_Writeback_D, Hit_Invalidate_D and Create_Dirty_Exclusive_D will only
>> 2504 # operate correctly if the internal data cache refill buffer is empty. These
>> 2505 # CACHE instructions should be separated from any potential data cache miss
>> 2506 # by a load instruction to an uncached address to empty the response buffer."
>> 2507 # (Revision 2.0 device errata from IDT available on https://www.idt.com/
>> 2508 # in .pdf format.)
>> 2509 config WAR_R4600_V2_HIT_CACHEOP
>> 2510 bool
1578 2511
1579 config ARCH_HAS_GENERIC_CRASHKERNEL_RESERVATI !! 2512 # From TX49/H2 manual: "If the instruction (i.e. CACHE) is issued for
1580 def_bool CRASH_RESERVE !! 2513 # the line which this instruction itself exists, the following
>> 2514 # operation is not guaranteed."
>> 2515 #
>> 2516 # Workaround: do two phase flushing for Index_Invalidate_I
>> 2517 config WAR_TX49XX_ICACHE_INDEX_INV
>> 2518 bool
1581 2519
1582 config TRANS_TABLE !! 2520 # The RM7000 processors and the E9000 cores have a bug (though PMC-Sierra
1583 def_bool y !! 2521 # opposes it being called that) where invalid instructions in the same
1584 depends on HIBERNATION || KEXEC_CORE !! 2522 # I-cache line worth of instructions being fetched may case spurious
>> 2523 # exceptions.
>> 2524 config WAR_ICACHE_REFILLS
>> 2525 bool
1585 2526
1586 config XEN_DOM0 !! 2527 # On the R10000 up to version 2.6 (not sure about 2.7) there is a bug that
1587 def_bool y !! 2528 # may cause ll / sc and lld / scd sequences to execute non-atomically.
1588 depends on XEN !! 2529 config WAR_R10000_LLSC
>> 2530 bool
1589 2531
1590 config XEN !! 2532 # 34K core erratum: "Problems Executing the TLBR Instruction"
1591 bool "Xen guest support on ARM64" !! 2533 config WAR_MIPS34K_MISSED_ITLB
1592 depends on ARM64 && OF !! 2534 bool
1593 select SWIOTLB_XEN <<
1594 select PARAVIRT <<
1595 help <<
1596 Say Y if you want to run Linux in a <<
1597 2535
1598 # include/linux/mmzone.h requires the followi <<
1599 # 2536 #
1600 # MAX_PAGE_ORDER + PAGE_SHIFT <= SECTION_SI !! 2537 # - Highmem only makes sense for the 32-bit kernel.
>> 2538 # - The current highmem code will only work properly on physically indexed
>> 2539 # caches such as R3000, SB1, R7000 or those that look like they're virtually
>> 2540 # indexed such as R4000/R4400 SC and MC versions or R10000. So for the
>> 2541 # moment we protect the user and offer the highmem option only on machines
>> 2542 # where it's known to be safe. This will not offer highmem on a few systems
>> 2543 # such as MIPS32 and MIPS64 CPUs which may have virtual and physically
>> 2544 # indexed CPUs but we're playing safe.
>> 2545 # - We use SYS_SUPPORTS_HIGHMEM to offer highmem only for systems where we
>> 2546 # know they might have memory configurations that could make use of highmem
>> 2547 # support.
1601 # 2548 #
1602 # so the maximum value of MAX_PAGE_ORDER is S !! 2549 config HIGHMEM
1603 # !! 2550 bool "High Memory Support"
1604 # | SECTION_SIZE_BITS | PAGE_SHIFT | m !! 2551 depends on 32BIT && CPU_SUPPORTS_HIGHMEM && SYS_SUPPORTS_HIGHMEM && !CPU_MIPS32_3_5_EVA
1605 # ----+-------------------+--------------+--- !! 2552 select KMAP_LOCAL
1606 # 4K | 27 | 12 | <<
1607 # 16K | 27 | 14 | <<
1608 # 64K | 29 | 16 | <<
1609 config ARCH_FORCE_MAX_ORDER <<
1610 int <<
1611 default "13" if ARM64_64K_PAGES <<
1612 default "11" if ARM64_16K_PAGES <<
1613 default "10" <<
1614 help <<
1615 The kernel page allocator limits th <<
1616 contiguous allocations. The limit i <<
1617 defines the maximal power of two of <<
1618 allocated as a single contiguous bl <<
1619 overriding the default setting when <<
1620 large blocks of physically contiguo <<
1621 <<
1622 The maximal size of allocation cann <<
1623 section, so the value of MAX_PAGE_O <<
1624 2553
1625 MAX_PAGE_ORDER + PAGE_SHIFT <= SE !! 2554 config CPU_SUPPORTS_HIGHMEM
1626 !! 2555 bool
1627 Don't change if unsure. <<
1628 2556
1629 config UNMAP_KERNEL_AT_EL0 !! 2557 config SYS_SUPPORTS_HIGHMEM
1630 bool "Unmap kernel when running in us !! 2558 bool
1631 default y <<
1632 help <<
1633 Speculation attacks against some hi <<
1634 be used to bypass MMU permission ch <<
1635 userspace. This can be defended aga <<
1636 when running in userspace, mapping <<
1637 via a trampoline page in the vector <<
1638 2559
1639 If unsure, say Y. !! 2560 config SYS_SUPPORTS_SMARTMIPS
>> 2561 bool
1640 2562
1641 config MITIGATE_SPECTRE_BRANCH_HISTORY !! 2563 config SYS_SUPPORTS_MICROMIPS
1642 bool "Mitigate Spectre style attacks !! 2564 bool
1643 default y <<
1644 help <<
1645 Speculation attacks against some hi <<
1646 make use of branch history to influ <<
1647 When taking an exception from user- <<
1648 or a firmware call overwrites the b <<
1649 2565
1650 config RODATA_FULL_DEFAULT_ENABLED !! 2566 config SYS_SUPPORTS_MIPS16
1651 bool "Apply r/o permissions of VM are !! 2567 bool
1652 default y <<
1653 help 2568 help
1654 Apply read-only attributes of VM ar !! 2569 This option must be set if a kernel might be executed on a MIPS16-
1655 the backing pages as well. This pre !! 2570 enabled CPU even if MIPS16 is not actually being used. In other
1656 from being modified (inadvertently !! 2571 words, it makes the kernel MIPS16-tolerant.
1657 mapping of the same memory page. Th <<
1658 be turned off at runtime by passing <<
1659 with rodata=full if this option is <<
1660 <<
1661 This requires the linear region to <<
1662 which may adversely affect performa <<
1663 <<
1664 config ARM64_SW_TTBR0_PAN <<
1665 bool "Emulate Privileged Access Never <<
1666 depends on !KCSAN <<
1667 help <<
1668 Enabling this option prevents the k <<
1669 user-space memory directly by point <<
1670 zeroed area and reserved ASID. The <<
1671 restore the valid TTBR0_EL1 tempora <<
1672 2572
1673 config ARM64_TAGGED_ADDR_ABI !! 2573 config CPU_SUPPORTS_MSA
1674 bool "Enable the tagged user addresse !! 2574 bool
1675 default y <<
1676 help <<
1677 When this option is enabled, user a <<
1678 relaxed ABI via prctl() allowing ta <<
1679 to system calls as pointer argument <<
1680 Documentation/arch/arm64/tagged-add <<
1681 <<
1682 menuconfig COMPAT <<
1683 bool "Kernel support for 32-bit EL0" <<
1684 depends on ARM64_4K_PAGES || EXPERT <<
1685 select HAVE_UID16 <<
1686 select OLD_SIGSUSPEND3 <<
1687 select COMPAT_OLD_SIGACTION <<
1688 help <<
1689 This option enables support for a 3 <<
1690 kernel at EL1. AArch32-specific com <<
1691 the user helper functions, VFP supp <<
1692 handled appropriately by the kernel <<
1693 <<
1694 If you use a page size other than 4 <<
1695 that you will only be able to execu <<
1696 with page size aligned segments. <<
1697 2575
1698 If you want to execute 32-bit users !! 2576 config ARCH_FLATMEM_ENABLE
>> 2577 def_bool y
>> 2578 depends on !NUMA && !CPU_LOONGSON2EF
1699 2579
1700 if COMPAT !! 2580 config ARCH_SPARSEMEM_ENABLE
>> 2581 bool
1701 2582
1702 config KUSER_HELPERS !! 2583 config NUMA
1703 bool "Enable kuser helpers page for 3 !! 2584 bool "NUMA Support"
1704 default y !! 2585 depends on SYS_SUPPORTS_NUMA
>> 2586 select SMP
>> 2587 select HAVE_SETUP_PER_CPU_AREA
>> 2588 select NEED_PER_CPU_EMBED_FIRST_CHUNK
1705 help 2589 help
1706 Warning: disabling this option may !! 2590 Say Y to compile the kernel to support NUMA (Non-Uniform Memory
>> 2591 Access). This option improves performance on systems with more
>> 2592 than two nodes; on two node systems it is generally better to
>> 2593 leave it disabled; on single node systems leave this option
>> 2594 disabled.
1707 2595
1708 Provide kuser helpers to compat tas !! 2596 config SYS_SUPPORTS_NUMA
1709 helper code to userspace in read on !! 2597 bool
1710 to allow userspace to be independen <<
1711 the system. This permits binaries t <<
1712 to ARMv8 without modification. <<
1713 <<
1714 See Documentation/arch/arm/kernel_u <<
1715 <<
1716 However, the fixed address nature o <<
1717 by ROP (return orientated programmi <<
1718 exploits. <<
1719 <<
1720 If all of the binaries and librarie <<
1721 are built specifically for your pla <<
1722 these helpers, then you can turn th <<
1723 such exploits. However, in that cas <<
1724 relying on those helpers is run, it <<
1725 <<
1726 Say N here only if you are absolute <<
1727 need these helpers; otherwise, the <<
1728 <<
1729 config COMPAT_VDSO <<
1730 bool "Enable vDSO for 32-bit applicat <<
1731 depends on !CPU_BIG_ENDIAN <<
1732 depends on (CC_IS_CLANG && LD_IS_LLD) <<
1733 select GENERIC_COMPAT_VDSO <<
1734 default y <<
1735 help <<
1736 Place in the process address space <<
1737 ELF shared object providing fast im <<
1738 and clock_gettime. <<
1739 <<
1740 You must have a 32-bit build of gli <<
1741 to seamlessly take advantage of thi <<
1742 <<
1743 config THUMB2_COMPAT_VDSO <<
1744 bool "Compile the 32-bit vDSO for Thu <<
1745 depends on COMPAT_VDSO <<
1746 default y <<
1747 help <<
1748 Compile the compat vDSO with '-mthu <<
1749 otherwise with '-marm'. <<
1750 2598
1751 config COMPAT_ALIGNMENT_FIXUPS !! 2599 config HAVE_ARCH_NODEDATA_EXTENSION
1752 bool "Fix up misaligned multi-word lo !! 2600 bool
1753 2601
1754 menuconfig ARMV8_DEPRECATED !! 2602 config RELOCATABLE
1755 bool "Emulate deprecated/obsolete ARM !! 2603 bool "Relocatable kernel"
1756 depends on SYSCTL !! 2604 depends on SYS_SUPPORTS_RELOCATABLE
1757 help !! 2605 depends on CPU_MIPS32_R2 || CPU_MIPS64_R2 || \
1758 Legacy software support may require !! 2606 CPU_MIPS32_R5 || CPU_MIPS64_R5 || \
1759 that have been deprecated or obsole !! 2607 CPU_MIPS32_R6 || CPU_MIPS64_R6 || \
>> 2608 CPU_P5600 || CAVIUM_OCTEON_SOC || \
>> 2609 CPU_LOONGSON64
>> 2610 help
>> 2611 This builds a kernel image that retains relocation information
>> 2612 so it can be loaded someplace besides the default 1MB.
>> 2613 The relocations make the kernel binary about 15% larger,
>> 2614 but are discarded at runtime
>> 2615
>> 2616 config RELOCATION_TABLE_SIZE
>> 2617 hex "Relocation table size"
>> 2618 depends on RELOCATABLE
>> 2619 range 0x0 0x01000000
>> 2620 default "0x00200000" if CPU_LOONGSON64
>> 2621 default "0x00100000"
>> 2622 help
>> 2623 A table of relocation data will be appended to the kernel binary
>> 2624 and parsed at boot to fix up the relocated kernel.
1760 2625
1761 Enable this config to enable select !! 2626 This option allows the amount of space reserved for the table to be
1762 features. !! 2627 adjusted, although the default of 1Mb should be ok in most cases.
1763 2628
1764 If unsure, say Y !! 2629 The build will fail and a valid size suggested if this is too small.
1765 2630
1766 if ARMV8_DEPRECATED !! 2631 If unsure, leave at the default value.
1767 2632
1768 config SWP_EMULATION !! 2633 config RANDOMIZE_BASE
1769 bool "Emulate SWP/SWPB instructions" !! 2634 bool "Randomize the address of the kernel image"
>> 2635 depends on RELOCATABLE
1770 help 2636 help
1771 ARMv8 obsoletes the use of A32 SWP/ !! 2637 Randomizes the physical and virtual address at which the
1772 they are always undefined. Say Y he !! 2638 kernel image is loaded, as a security feature that
1773 emulation of these instructions for !! 2639 deters exploit attempts relying on knowledge of the location
1774 This feature can be controlled at r !! 2640 of kernel internals.
1775 sysctl which is disabled by default <<
1776 2641
1777 In some older versions of glibc [<= !! 2642 Entropy is generated using any coprocessor 0 registers available.
1778 trylock() operations with the assum <<
1779 be preempted. This invalid assumpti <<
1780 with SWP emulation enabled, leading <<
1781 application. <<
1782 2643
1783 NOTE: when accessing uncached share !! 2644 The kernel will be offset by up to RANDOMIZE_BASE_MAX_OFFSET.
1784 on an external transaction monitori <<
1785 monitor to maintain update atomicit <<
1786 implement a global monitor, this op <<
1787 perform SWP operations to uncached <<
1788 2645
1789 If unsure, say Y !! 2646 If unsure, say N.
1790 2647
1791 config CP15_BARRIER_EMULATION !! 2648 config RANDOMIZE_BASE_MAX_OFFSET
1792 bool "Emulate CP15 Barrier instructio !! 2649 hex "Maximum kASLR offset" if EXPERT
1793 help !! 2650 depends on RANDOMIZE_BASE
1794 The CP15 barrier instructions - CP1 !! 2651 range 0x0 0x40000000 if EVA || 64BIT
1795 CP15DMB - are deprecated in ARMv8 ( !! 2652 range 0x0 0x08000000
1796 strongly recommended to use the ISB !! 2653 default "0x01000000"
1797 instructions instead. !! 2654 help
>> 2655 When kASLR is active, this provides the maximum offset that will
>> 2656 be applied to the kernel image. It should be set according to the
>> 2657 amount of physical RAM available in the target system minus
>> 2658 PHYSICAL_START and must be a power of 2.
1798 2659
1799 Say Y here to enable software emula !! 2660 This is limited by the size of KSEG0, 256Mb on 32-bit or 1Gb with
1800 instructions for AArch32 userspace !! 2661 EVA or 64-bit. The default is 16Mb.
1801 enabled, CP15 barrier usage is trac <<
1802 identify software that needs updati <<
1803 controlled at runtime with the abi. <<
1804 2662
1805 If unsure, say Y !! 2663 config NODES_SHIFT
>> 2664 int
>> 2665 default "6"
>> 2666 depends on NUMA
1806 2667
1807 config SETEND_EMULATION !! 2668 config HW_PERF_EVENTS
1808 bool "Emulate SETEND instruction" !! 2669 bool "Enable hardware performance counter support for perf events"
>> 2670 depends on PERF_EVENTS && (CPU_MIPS32 || CPU_MIPS64 || CPU_R10000 || CPU_SB1 || CPU_CAVIUM_OCTEON || CPU_LOONGSON64)
>> 2671 default y
1809 help 2672 help
1810 The SETEND instruction alters the d !! 2673 Enable hardware performance counter support for perf events. If
1811 AArch32 EL0, and is deprecated in A !! 2674 disabled, perf events will use software events only.
1812 2675
1813 Say Y here to enable software emula !! 2676 config DMI
1814 for AArch32 userspace code. This fe !! 2677 bool "Enable DMI scanning"
1815 at runtime with the abi.setend sysc !! 2678 depends on MACH_LOONGSON64
>> 2679 select DMI_SCAN_MACHINE_NON_EFI_FALLBACK
>> 2680 default y
>> 2681 help
>> 2682 Enabled scanning of DMI to identify machine quirks. Say Y
>> 2683 here unless you have verified that your setup is not
>> 2684 affected by entries in the DMI blacklist. Required by PNP
>> 2685 BIOS code.
1816 2686
1817 Note: All the cpus on the system mu !! 2687 config SMP
1818 for this feature to be enabled. If !! 2688 bool "Multi-Processing support"
1819 endian - is hotplugged in after thi !! 2689 depends on SYS_SUPPORTS_SMP
1820 be unexpected results in the applic !! 2690 help
>> 2691 This enables support for systems with more than one CPU. If you have
>> 2692 a system with only one CPU, say N. If you have a system with more
>> 2693 than one CPU, say Y.
>> 2694
>> 2695 If you say N here, the kernel will run on uni- and multiprocessor
>> 2696 machines, but will use only one CPU of a multiprocessor machine. If
>> 2697 you say Y here, the kernel will run on many, but not all,
>> 2698 uniprocessor machines. On a uniprocessor machine, the kernel
>> 2699 will run faster if you say N here.
1821 2700
1822 If unsure, say Y !! 2701 People using multiprocessor machines who say Y here should also say
1823 endif # ARMV8_DEPRECATED !! 2702 Y to "Enhanced Real Time Clock Support", below.
1824 2703
1825 endif # COMPAT !! 2704 See also the SMP-HOWTO available at
>> 2705 <https://www.tldp.org/docs.html#howto>.
1826 2706
1827 menu "ARMv8.1 architectural features" !! 2707 If you don't know what to do here, say N.
1828 2708
1829 config ARM64_HW_AFDBM !! 2709 config HOTPLUG_CPU
1830 bool "Support for hardware updates of !! 2710 bool "Support for hot-pluggable CPUs"
1831 default y !! 2711 depends on SMP && SYS_SUPPORTS_HOTPLUG_CPU
1832 help 2712 help
1833 The ARMv8.1 architecture extensions !! 2713 Say Y here to allow turning CPUs off and on. CPUs can be
1834 hardware updates of the access and !! 2714 controlled through /sys/devices/system/cpu.
1835 table entries. When enabled in TCR_ !! 2715 (Note: power management support will enable this option
1836 capable processors, accesses to pag !! 2716 automatically on SMP systems. )
1837 set this bit instead of raising an !! 2717 Say N if you want to disable CPU hotplug.
1838 Similarly, writes to read-only page <<
1839 clear the read-only bit (AP[2]) ins <<
1840 permission fault. <<
1841 <<
1842 Kernels built with this configurati <<
1843 to work on pre-ARMv8.1 hardware and <<
1844 minimal. If unsure, say Y. <<
1845 2718
1846 config ARM64_PAN !! 2719 config SMP_UP
1847 bool "Enable support for Privileged A !! 2720 bool
1848 default y <<
1849 help <<
1850 Privileged Access Never (PAN; part <<
1851 prevents the kernel or hypervisor f <<
1852 memory directly. <<
1853 2721
1854 Choosing this option will cause any !! 2722 config SYS_SUPPORTS_MIPS_CPS
1855 copy_to_user et al) memory access t !! 2723 bool
1856 2724
1857 The feature is detected at runtime, !! 2725 config SYS_SUPPORTS_SMP
1858 instruction if the cpu does not imp !! 2726 bool
1859 2727
1860 config AS_HAS_LSE_ATOMICS !! 2728 config NR_CPUS_DEFAULT_4
1861 def_bool $(as-instr,.arch_extension l !! 2729 bool
1862 2730
1863 config ARM64_LSE_ATOMICS !! 2731 config NR_CPUS_DEFAULT_8
1864 bool 2732 bool
1865 default ARM64_USE_LSE_ATOMICS <<
1866 depends on AS_HAS_LSE_ATOMICS <<
1867 2733
1868 config ARM64_USE_LSE_ATOMICS !! 2734 config NR_CPUS_DEFAULT_16
1869 bool "Atomic instructions" !! 2735 bool
1870 default y <<
1871 help <<
1872 As part of the Large System Extensi <<
1873 atomic instructions that are design <<
1874 very large systems. <<
1875 2736
1876 Say Y here to make use of these ins !! 2737 config NR_CPUS_DEFAULT_32
1877 atomic routines. This incurs a smal !! 2738 bool
1878 not support these instructions and <<
1879 built with binutils >= 2.25 in orde <<
1880 to be used. <<
1881 2739
1882 endmenu # "ARMv8.1 architectural features" !! 2740 config NR_CPUS_DEFAULT_64
>> 2741 bool
1883 2742
1884 menu "ARMv8.2 architectural features" !! 2743 config NR_CPUS
>> 2744 int "Maximum number of CPUs (2-256)"
>> 2745 range 2 256
>> 2746 depends on SMP
>> 2747 default "4" if NR_CPUS_DEFAULT_4
>> 2748 default "8" if NR_CPUS_DEFAULT_8
>> 2749 default "16" if NR_CPUS_DEFAULT_16
>> 2750 default "32" if NR_CPUS_DEFAULT_32
>> 2751 default "64" if NR_CPUS_DEFAULT_64
>> 2752 help
>> 2753 This allows you to specify the maximum number of CPUs which this
>> 2754 kernel will support. The maximum supported value is 32 for 32-bit
>> 2755 kernel and 64 for 64-bit kernels; the minimum value which makes
>> 2756 sense is 1 for Qemu (useful only for kernel debugging purposes)
>> 2757 and 2 for all others.
>> 2758
>> 2759 This is purely to save memory - each supported CPU adds
>> 2760 approximately eight kilobytes to the kernel image. For best
>> 2761 performance should round up your number of processors to the next
>> 2762 power of two.
1885 2763
1886 config AS_HAS_ARMV8_2 !! 2764 config MIPS_PERF_SHARED_TC_COUNTERS
1887 def_bool $(cc-option,-Wa$(comma)-marc !! 2765 bool
1888 2766
1889 config AS_HAS_SHA3 !! 2767 config MIPS_NR_CPU_NR_MAP_1024
1890 def_bool $(as-instr,.arch armv8.2-a+s !! 2768 bool
1891 2769
1892 config ARM64_PMEM !! 2770 config MIPS_NR_CPU_NR_MAP
1893 bool "Enable support for persistent m !! 2771 int
1894 select ARCH_HAS_PMEM_API !! 2772 depends on SMP
1895 select ARCH_HAS_UACCESS_FLUSHCACHE !! 2773 default 1024 if MIPS_NR_CPU_NR_MAP_1024
1896 help !! 2774 default NR_CPUS if !MIPS_NR_CPU_NR_MAP_1024
1897 Say Y to enable support for the per <<
1898 ARMv8.2 DCPoP feature. <<
1899 2775
1900 The feature is detected at runtime, !! 2776 #
1901 operations if DC CVAP is not suppor !! 2777 # Timer Interrupt Frequency Configuration
1902 DC CVAP itself if the system does n !! 2778 #
1903 2779
1904 config ARM64_RAS_EXTN !! 2780 choice
1905 bool "Enable support for RAS CPU Exte !! 2781 prompt "Timer frequency"
1906 default y !! 2782 default HZ_250
1907 help 2783 help
1908 CPUs that support the Reliability, !! 2784 Allows the configuration of the timer frequency.
1909 (RAS) Extensions, part of ARMv8.2 a <<
1910 errors, classify them and report th <<
1911 <<
1912 On CPUs with these extensions syste <<
1913 barriers to determine if faults are <<
1914 classification from a new set of re <<
1915 <<
1916 Selecting this feature will allow t <<
1917 and access the new registers if the <<
1918 Platform RAS features may additiona <<
1919 2785
1920 config ARM64_CNP !! 2786 config HZ_24
1921 bool "Enable support for Common Not P !! 2787 bool "24 HZ" if SYS_SUPPORTS_24HZ || SYS_SUPPORTS_ARBIT_HZ
1922 default y <<
1923 depends on ARM64_PAN || !ARM64_SW_TTB <<
1924 help <<
1925 Common Not Private (CNP) allows tra <<
1926 be shared between different PEs in <<
1927 domain, so the hardware can use thi <<
1928 caching of such entries in the TLB. <<
1929 2788
1930 Selecting this option allows the CN !! 2789 config HZ_48
1931 at runtime, and does not affect PEs !! 2790 bool "48 HZ" if SYS_SUPPORTS_48HZ || SYS_SUPPORTS_ARBIT_HZ
1932 this feature. <<
1933 2791
1934 endmenu # "ARMv8.2 architectural features" !! 2792 config HZ_100
>> 2793 bool "100 HZ" if SYS_SUPPORTS_100HZ || SYS_SUPPORTS_ARBIT_HZ
1935 2794
1936 menu "ARMv8.3 architectural features" !! 2795 config HZ_128
>> 2796 bool "128 HZ" if SYS_SUPPORTS_128HZ || SYS_SUPPORTS_ARBIT_HZ
1937 2797
1938 config ARM64_PTR_AUTH !! 2798 config HZ_250
1939 bool "Enable support for pointer auth !! 2799 bool "250 HZ" if SYS_SUPPORTS_250HZ || SYS_SUPPORTS_ARBIT_HZ
1940 default y <<
1941 help <<
1942 Pointer authentication (part of the <<
1943 instructions for signing and authen <<
1944 keys, which can be used to mitigate <<
1945 and other attacks. <<
1946 <<
1947 This option enables these instructi <<
1948 Choosing this option will cause the <<
1949 for each process at exec() time, wi <<
1950 context-switched along with the pro <<
1951 <<
1952 The feature is detected at runtime. <<
1953 hardware it will not be advertised <<
1954 be enabled. <<
1955 <<
1956 If the feature is present on the bo <<
1957 the late CPU will be parked. Also, <<
1958 address auth and the late CPU has t <<
1959 but with the feature disabled. On s <<
1960 not be selected. <<
1961 2800
1962 config ARM64_PTR_AUTH_KERNEL !! 2801 config HZ_256
1963 bool "Use pointer authentication for !! 2802 bool "256 HZ" if SYS_SUPPORTS_256HZ || SYS_SUPPORTS_ARBIT_HZ
1964 default y <<
1965 depends on ARM64_PTR_AUTH <<
1966 depends on (CC_HAS_SIGN_RETURN_ADDRES <<
1967 # Modern compilers insert a .note.gnu <<
1968 # which is only understood by binutil <<
1969 depends on LD_IS_LLD || LD_VERSION >= <<
1970 depends on !CC_IS_CLANG || AS_HAS_CFI <<
1971 depends on (!FUNCTION_GRAPH_TRACER || <<
1972 help <<
1973 If the compiler supports the -mbran <<
1974 -msign-return-address flag (e.g. GC <<
1975 will cause the kernel itself to be <<
1976 protection. In this case, and if th <<
1977 support pointer authentication, the <<
1978 disabled with minimal loss of prote <<
1979 <<
1980 This feature works with FUNCTION_GR <<
1981 DYNAMIC_FTRACE_WITH_ARGS is enabled <<
1982 <<
1983 config CC_HAS_BRANCH_PROT_PAC_RET <<
1984 # GCC 9 or later, clang 8 or later <<
1985 def_bool $(cc-option,-mbranch-protect <<
1986 <<
1987 config CC_HAS_SIGN_RETURN_ADDRESS <<
1988 # GCC 7, 8 <<
1989 def_bool $(cc-option,-msign-return-ad <<
1990 <<
1991 config AS_HAS_ARMV8_3 <<
1992 def_bool $(cc-option,-Wa$(comma)-marc <<
1993 <<
1994 config AS_HAS_CFI_NEGATE_RA_STATE <<
1995 def_bool $(as-instr,.cfi_startproc\n. <<
1996 <<
1997 config AS_HAS_LDAPR <<
1998 def_bool $(as-instr,.arch_extension r <<
1999 2803
2000 endmenu # "ARMv8.3 architectural features" !! 2804 config HZ_1000
>> 2805 bool "1000 HZ" if SYS_SUPPORTS_1000HZ || SYS_SUPPORTS_ARBIT_HZ
2001 2806
2002 menu "ARMv8.4 architectural features" !! 2807 config HZ_1024
>> 2808 bool "1024 HZ" if SYS_SUPPORTS_1024HZ || SYS_SUPPORTS_ARBIT_HZ
2003 2809
2004 config ARM64_AMU_EXTN !! 2810 endchoice
2005 bool "Enable support for the Activity <<
2006 default y <<
2007 help <<
2008 The activity monitors extension is <<
2009 by the ARMv8.4 CPU architecture. Th <<
2010 of the activity monitors architectu <<
2011 <<
2012 To enable the use of this extension <<
2013 <<
2014 Note that for architectural reasons <<
2015 support when running on CPUs that p <<
2016 extension. The required support is <<
2017 * Version 1.5 and later of the AR <<
2018 <<
2019 For kernels that have this configur <<
2020 firmware, you may need to say N her <<
2021 Otherwise you may experience firmwa <<
2022 accessing the counter registers. Ev <<
2023 symptoms, the values returned by th <<
2024 correctly reflect reality. Most com <<
2025 indicating that the counter is not <<
2026 2811
2027 config AS_HAS_ARMV8_4 !! 2812 config SYS_SUPPORTS_24HZ
2028 def_bool $(cc-option,-Wa$(comma)-marc !! 2813 bool
2029 2814
2030 config ARM64_TLB_RANGE !! 2815 config SYS_SUPPORTS_48HZ
2031 bool "Enable support for tlbi range f !! 2816 bool
2032 default y <<
2033 depends on AS_HAS_ARMV8_4 <<
2034 help <<
2035 ARMv8.4-TLBI provides TLBI invalida <<
2036 range of input addresses. <<
2037 2817
2038 The feature introduces new assembly !! 2818 config SYS_SUPPORTS_100HZ
2039 support when binutils >= 2.30. !! 2819 bool
2040 2820
2041 endmenu # "ARMv8.4 architectural features" !! 2821 config SYS_SUPPORTS_128HZ
>> 2822 bool
2042 2823
2043 menu "ARMv8.5 architectural features" !! 2824 config SYS_SUPPORTS_250HZ
>> 2825 bool
2044 2826
2045 config AS_HAS_ARMV8_5 !! 2827 config SYS_SUPPORTS_256HZ
2046 def_bool $(cc-option,-Wa$(comma)-marc !! 2828 bool
2047 2829
2048 config ARM64_BTI !! 2830 config SYS_SUPPORTS_1000HZ
2049 bool "Branch Target Identification su !! 2831 bool
2050 default y <<
2051 help <<
2052 Branch Target Identification (part <<
2053 provides a mechanism to limit the s <<
2054 branch instructions such as BR or B <<
2055 <<
2056 To make use of BTI on CPUs that sup <<
2057 <<
2058 BTI is intended to provide compleme <<
2059 flow integrity protection mechanism <<
2060 authentication mechanism provided a <<
2061 For this reason, it does not make s <<
2062 also enabling support for pointer a <<
2063 enabling this option you should als <<
2064 <<
2065 Userspace binaries must also be spe <<
2066 this mechanism. If you say N here <<
2067 BTI, such binaries can still run, b <<
2068 enforcement of branch destinations. <<
2069 2832
2070 config ARM64_BTI_KERNEL !! 2833 config SYS_SUPPORTS_1024HZ
2071 bool "Use Branch Target Identificatio !! 2834 bool
2072 default y <<
2073 depends on ARM64_BTI <<
2074 depends on ARM64_PTR_AUTH_KERNEL <<
2075 depends on CC_HAS_BRANCH_PROT_PAC_RET <<
2076 # https://gcc.gnu.org/bugzilla/show_b <<
2077 depends on !CC_IS_GCC || GCC_VERSION <<
2078 # https://gcc.gnu.org/bugzilla/show_b <<
2079 depends on !CC_IS_GCC <<
2080 depends on (!FUNCTION_GRAPH_TRACER || <<
2081 help <<
2082 Build the kernel with Branch Target <<
2083 and enable enforcement of this for <<
2084 is enabled and the system supports <<
2085 modular code must have BTI enabled. <<
2086 <<
2087 config CC_HAS_BRANCH_PROT_PAC_RET_BTI <<
2088 # GCC 9 or later, clang 8 or later <<
2089 def_bool $(cc-option,-mbranch-protect <<
2090 2835
2091 config ARM64_E0PD !! 2836 config SYS_SUPPORTS_ARBIT_HZ
2092 bool "Enable support for E0PD" !! 2837 bool
2093 default y !! 2838 default y if !SYS_SUPPORTS_24HZ && \
2094 help !! 2839 !SYS_SUPPORTS_48HZ && \
2095 E0PD (part of the ARMv8.5 extension !! 2840 !SYS_SUPPORTS_100HZ && \
2096 that EL0 accesses made via TTBR1 al !! 2841 !SYS_SUPPORTS_128HZ && \
2097 providing similar benefits to KASLR !! 2842 !SYS_SUPPORTS_250HZ && \
2098 with lower overhead and without dis !! 2843 !SYS_SUPPORTS_256HZ && \
2099 kernel memory such as SPE. !! 2844 !SYS_SUPPORTS_1000HZ && \
2100 !! 2845 !SYS_SUPPORTS_1024HZ
2101 This option enables E0PD for TTBR1 <<
2102 <<
2103 config ARM64_AS_HAS_MTE <<
2104 # Initial support for MTE went in bin <<
2105 # ".arch armv8.5-a+memtag" below. How <<
2106 # as a late addition to the final arc <<
2107 # is only supported in the newer 2.32 <<
2108 # versions, hence the extra "stgm" in <<
2109 def_bool $(as-instr,.arch armv8.5-a+m <<
2110 2846
2111 config ARM64_MTE !! 2847 config HZ
2112 bool "Memory Tagging Extension suppor !! 2848 int
2113 default y !! 2849 default 24 if HZ_24
2114 depends on ARM64_AS_HAS_MTE && ARM64_ !! 2850 default 48 if HZ_48
2115 depends on AS_HAS_ARMV8_5 !! 2851 default 100 if HZ_100
2116 depends on AS_HAS_LSE_ATOMICS !! 2852 default 128 if HZ_128
2117 # Required for tag checking in the ua !! 2853 default 250 if HZ_250
2118 depends on ARM64_PAN !! 2854 default 256 if HZ_256
2119 select ARCH_HAS_SUBPAGE_FAULTS !! 2855 default 1000 if HZ_1000
2120 select ARCH_USES_HIGH_VMA_FLAGS !! 2856 default 1024 if HZ_1024
2121 select ARCH_USES_PG_ARCH_2 <<
2122 select ARCH_USES_PG_ARCH_3 <<
2123 help <<
2124 Memory Tagging (part of the ARMv8.5 <<
2125 architectural support for run-time, <<
2126 various classes of memory error to <<
2127 to eliminate vulnerabilities arisin <<
2128 languages. <<
2129 <<
2130 This option enables the support for <<
2131 Extension at EL0 (i.e. for userspac <<
2132 <<
2133 Selecting this option allows the fe <<
2134 runtime. Any secondary CPU not impl <<
2135 not be allowed a late bring-up. <<
2136 <<
2137 Userspace binaries that want to use <<
2138 explicitly opt in. The mechanism fo <<
2139 described in: <<
2140 2857
2141 Documentation/arch/arm64/memory-tag !! 2858 config SCHED_HRTICK
>> 2859 def_bool HIGH_RES_TIMERS
2142 2860
2143 endmenu # "ARMv8.5 architectural features" !! 2861 config ARCH_SUPPORTS_KEXEC
>> 2862 def_bool y
2144 2863
2145 menu "ARMv8.7 architectural features" !! 2864 config ARCH_SUPPORTS_CRASH_DUMP
>> 2865 def_bool y
2146 2866
2147 config ARM64_EPAN !! 2867 config PHYSICAL_START
2148 bool "Enable support for Enhanced Pri !! 2868 hex "Physical address where the kernel is loaded"
2149 default y !! 2869 default "0xffffffff84000000"
2150 depends on ARM64_PAN !! 2870 depends on CRASH_DUMP
2151 help !! 2871 help
2152 Enhanced Privileged Access Never (E !! 2872 This gives the CKSEG0 or KSEG0 address where the kernel is loaded.
2153 Access Never to be used with Execut !! 2873 If you plan to use kernel for capturing the crash dump change
>> 2874 this value to start of the reserved region (the "X" value as
>> 2875 specified in the "crashkernel=YM@XM" command line boot parameter
>> 2876 passed to the panic-ed kernel).
>> 2877
>> 2878 config MIPS_O32_FP64_SUPPORT
>> 2879 bool "Support for O32 binaries using 64-bit FP" if !CPU_MIPSR6
>> 2880 depends on 32BIT || MIPS32_O32
>> 2881 help
>> 2882 When this is enabled, the kernel will support use of 64-bit floating
>> 2883 point registers with binaries using the O32 ABI along with the
>> 2884 EF_MIPS_FP64 ELF header flag (typically built with -mfp64). On
>> 2885 32-bit MIPS systems this support is at the cost of increasing the
>> 2886 size and complexity of the compiled FPU emulator. Thus if you are
>> 2887 running a MIPS32 system and know that none of your userland binaries
>> 2888 will require 64-bit floating point, you may wish to reduce the size
>> 2889 of your kernel & potentially improve FP emulation performance by
>> 2890 saying N here.
>> 2891
>> 2892 Although binutils currently supports use of this flag the details
>> 2893 concerning its effect upon the O32 ABI in userland are still being
>> 2894 worked on. In order to avoid userland becoming dependent upon current
>> 2895 behaviour before the details have been finalised, this option should
>> 2896 be considered experimental and only enabled by those working upon
>> 2897 said details.
2154 2898
2155 The feature is detected at runtime, !! 2899 If unsure, say N.
2156 if the cpu does not implement the f <<
2157 endmenu # "ARMv8.7 architectural features" <<
2158 2900
2159 menu "ARMv8.9 architectural features" !! 2901 config USE_OF
>> 2902 bool
>> 2903 select OF
>> 2904 select OF_EARLY_FLATTREE
>> 2905 select IRQ_DOMAIN
2160 2906
2161 config ARM64_POE !! 2907 config UHI_BOOT
2162 prompt "Permission Overlay Extension" !! 2908 bool
2163 def_bool y <<
2164 select ARCH_USES_HIGH_VMA_FLAGS <<
2165 select ARCH_HAS_PKEYS <<
2166 help <<
2167 The Permission Overlay Extension is <<
2168 Protection Keys. Memory Protection <<
2169 enforcing page-based protections, b <<
2170 of the page tables when an applicat <<
2171 2909
2172 For details, see Documentation/core !! 2910 config BUILTIN_DTB
>> 2911 bool
2173 2912
2174 If unsure, say y. !! 2913 choice
>> 2914 prompt "Kernel appended dtb support" if USE_OF
>> 2915 default MIPS_NO_APPENDED_DTB
2175 2916
2176 config ARCH_PKEY_BITS !! 2917 config MIPS_NO_APPENDED_DTB
2177 int !! 2918 bool "None"
2178 default 3 !! 2919 help
>> 2920 Do not enable appended dtb support.
>> 2921
>> 2922 config MIPS_ELF_APPENDED_DTB
>> 2923 bool "vmlinux"
>> 2924 help
>> 2925 With this option, the boot code will look for a device tree binary
>> 2926 DTB) included in the vmlinux ELF section .appended_dtb. By default
>> 2927 it is empty and the DTB can be appended using binutils command
>> 2928 objcopy:
>> 2929
>> 2930 objcopy --update-section .appended_dtb=<filename>.dtb vmlinux
>> 2931
>> 2932 This is meant as a backward compatibility convenience for those
>> 2933 systems with a bootloader that can't be upgraded to accommodate
>> 2934 the documented boot protocol using a device tree.
>> 2935
>> 2936 config MIPS_RAW_APPENDED_DTB
>> 2937 bool "vmlinux.bin or vmlinuz.bin"
>> 2938 help
>> 2939 With this option, the boot code will look for a device tree binary
>> 2940 DTB) appended to raw vmlinux.bin or vmlinuz.bin.
>> 2941 (e.g. cat vmlinux.bin <filename>.dtb > vmlinux_w_dtb).
>> 2942
>> 2943 This is meant as a backward compatibility convenience for those
>> 2944 systems with a bootloader that can't be upgraded to accommodate
>> 2945 the documented boot protocol using a device tree.
>> 2946
>> 2947 Beware that there is very little in terms of protection against
>> 2948 this option being confused by leftover garbage in memory that might
>> 2949 look like a DTB header after a reboot if no actual DTB is appended
>> 2950 to vmlinux.bin. Do not leave this option active in a production kernel
>> 2951 if you don't intend to always append a DTB.
>> 2952 endchoice
>> 2953
>> 2954 choice
>> 2955 prompt "Kernel command line type" if !CMDLINE_OVERRIDE
>> 2956 default MIPS_CMDLINE_FROM_DTB if USE_OF && !ATH79 && !MACH_INGENIC && \
>> 2957 !MACH_LOONGSON64 && !MIPS_MALTA && \
>> 2958 !CAVIUM_OCTEON_SOC
>> 2959 default MIPS_CMDLINE_FROM_BOOTLOADER
>> 2960
>> 2961 config MIPS_CMDLINE_FROM_DTB
>> 2962 depends on USE_OF
>> 2963 bool "Dtb kernel arguments if available"
>> 2964
>> 2965 config MIPS_CMDLINE_DTB_EXTEND
>> 2966 depends on USE_OF
>> 2967 bool "Extend dtb kernel arguments with bootloader arguments"
>> 2968
>> 2969 config MIPS_CMDLINE_FROM_BOOTLOADER
>> 2970 bool "Bootloader kernel arguments if available"
>> 2971
>> 2972 config MIPS_CMDLINE_BUILTIN_EXTEND
>> 2973 depends on CMDLINE_BOOL
>> 2974 bool "Extend builtin kernel arguments with bootloader arguments"
>> 2975 endchoice
2179 2976
2180 endmenu # "ARMv8.9 architectural features" !! 2977 endmenu
2181 2978
2182 config ARM64_SVE !! 2979 config LOCKDEP_SUPPORT
2183 bool "ARM Scalable Vector Extension s !! 2980 bool
2184 default y 2981 default y
2185 help <<
2186 The Scalable Vector Extension (SVE) <<
2187 execution state which complements a <<
2188 of the base architecture to support <<
2189 additional vectorisation opportunit <<
2190 <<
2191 To enable use of this extension on <<
2192 <<
2193 On CPUs that support the SVE2 exten <<
2194 those too. <<
2195 <<
2196 Note that for architectural reasons <<
2197 support when running on SVE capable <<
2198 is present in: <<
2199 <<
2200 * version 1.5 and later of the AR <<
2201 * the AArch64 boot wrapper since <<
2202 ("bootwrapper: SVE: Enable SVE <<
2203 <<
2204 For other firmware implementations, <<
2205 or vendor. <<
2206 <<
2207 If you need the kernel to boot on S <<
2208 firmware, you may need to say N her <<
2209 fixed. Otherwise, you may experien <<
2210 booting the kernel. If unsure and <<
2211 symptoms, you should assume that it <<
2212 2982
2213 config ARM64_SME !! 2983 config STACKTRACE_SUPPORT
2214 bool "ARM Scalable Matrix Extension s !! 2984 bool
2215 default y 2985 default y
2216 depends on ARM64_SVE <<
2217 depends on BROKEN <<
2218 help <<
2219 The Scalable Matrix Extension (SME) <<
2220 execution state which utilises a su <<
2221 instruction set, together with the <<
2222 register state capable of holding t <<
2223 enable various matrix operations. <<
2224 <<
2225 config ARM64_PSEUDO_NMI <<
2226 bool "Support for NMI-like interrupts <<
2227 select ARM_GIC_V3 <<
2228 help <<
2229 Adds support for mimicking Non-Mask <<
2230 GIC interrupt priority. This suppor <<
2231 ARM GIC. <<
2232 <<
2233 This high priority configuration fo <<
2234 explicitly enabled by setting the k <<
2235 "irqchip.gicv3_pseudo_nmi" to 1. <<
2236 <<
2237 If unsure, say N <<
2238 <<
2239 if ARM64_PSEUDO_NMI <<
2240 config ARM64_DEBUG_PRIORITY_MASKING <<
2241 bool "Debug interrupt priority maskin <<
2242 help <<
2243 This adds runtime checks to functio <<
2244 interrupts when using priority mask <<
2245 the validity of ICC_PMR_EL1 when ca <<
2246 2986
2247 If unsure, say N !! 2987 config PGTABLE_LEVELS
2248 endif # ARM64_PSEUDO_NMI !! 2988 int
>> 2989 default 4 if PAGE_SIZE_4KB && MIPS_VA_BITS_48
>> 2990 default 3 if 64BIT && (!PAGE_SIZE_64KB || MIPS_VA_BITS_48)
>> 2991 default 2
2249 2992
2250 config RELOCATABLE !! 2993 config MIPS_AUTO_PFN_OFFSET
2251 bool "Build a relocatable kernel imag !! 2994 bool
2252 select ARCH_HAS_RELR <<
2253 default y <<
2254 help <<
2255 This builds the kernel as a Positio <<
2256 which retains all relocation metada <<
2257 kernel binary at runtime to a diffe <<
2258 address it was linked at. <<
2259 Since AArch64 uses the RELA relocat <<
2260 relocation pass at runtime even if <<
2261 same address it was linked at. <<
2262 2995
2263 config RANDOMIZE_BASE !! 2996 menu "Bus options (PCI, PCMCIA, EISA, ISA, TC)"
2264 bool "Randomize the address of the ke <<
2265 select RELOCATABLE <<
2266 help <<
2267 Randomizes the virtual address at w <<
2268 loaded, as a security feature that <<
2269 relying on knowledge of the locatio <<
2270 <<
2271 It is the bootloader's job to provi <<
2272 random u64 value in /chosen/kaslr-s <<
2273 <<
2274 When booting via the UEFI stub, it <<
2275 EFI_RNG_PROTOCOL implementation (if <<
2276 to the kernel proper. In addition, <<
2277 location of the kernel Image as wel <<
2278 2997
2279 If unsure, say N. !! 2998 config PCI_DRIVERS_GENERIC
>> 2999 select PCI_DOMAINS_GENERIC if PCI
>> 3000 bool
2280 3001
2281 config RANDOMIZE_MODULE_REGION_FULL !! 3002 config PCI_DRIVERS_LEGACY
2282 bool "Randomize the module region ove !! 3003 def_bool !PCI_DRIVERS_GENERIC
2283 depends on RANDOMIZE_BASE !! 3004 select NO_GENERIC_PCI_IOPORT_MAP
2284 default y !! 3005 select PCI_DOMAINS if PCI
2285 help <<
2286 Randomizes the location of the modu <<
2287 covering the core kernel. This way, <<
2288 to leak information about the locat <<
2289 but it does imply that function cal <<
2290 kernel will need to be resolved via <<
2291 <<
2292 When this option is not set, the mo <<
2293 a limited range that contains the [ <<
2294 core kernel, so branch relocations <<
2295 the region is exhausted. In this pa <<
2296 exhaustion, modules might be able t <<
2297 3006
2298 config CC_HAVE_STACKPROTECTOR_SYSREG !! 3007 #
2299 def_bool $(cc-option,-mstack-protecto !! 3008 # ISA support is now enabled via select. Too many systems still have the one
>> 3009 # or other ISA chip on the board that users don't know about so don't expect
>> 3010 # users to choose the right thing ...
>> 3011 #
>> 3012 config ISA
>> 3013 bool
2300 3014
2301 config STACKPROTECTOR_PER_TASK !! 3015 config TC
2302 def_bool y !! 3016 bool "TURBOchannel support"
2303 depends on STACKPROTECTOR && CC_HAVE_ !! 3017 depends on MACH_DECSTATION
>> 3018 help
>> 3019 TURBOchannel is a DEC (now Compaq (now HP)) bus for Alpha and MIPS
>> 3020 processors. TURBOchannel programming specifications are available
>> 3021 at:
>> 3022 <ftp://ftp.hp.com/pub/alphaserver/archive/triadd/>
>> 3023 and:
>> 3024 <http://www.computer-refuge.org/classiccmp/ftp.digital.com/pub/DEC/TriAdd/>
>> 3025 Linux driver support status is documented at:
>> 3026 <http://www.linux-mips.org/wiki/DECstation>
2304 3027
2305 config UNWIND_PATCH_PAC_INTO_SCS !! 3028 config MMU
2306 bool "Enable shadow call stack dynami !! 3029 bool
2307 # needs Clang with https://github.com <<
2308 depends on CC_IS_CLANG && CLANG_VERSI <<
2309 depends on ARM64_PTR_AUTH_KERNEL && C <<
2310 depends on SHADOW_CALL_STACK <<
2311 select UNWIND_TABLES <<
2312 select DYNAMIC_SCS <<
2313 <<
2314 config ARM64_CONTPTE <<
2315 bool "Contiguous PTE mappings for use <<
2316 depends on TRANSPARENT_HUGEPAGE <<
2317 default y 3030 default y
2318 help <<
2319 When enabled, user mappings are con <<
2320 bit, for any mappings that meet the <<
2321 This reduces TLB pressure and impro <<
2322 <<
2323 endmenu # "Kernel Features" <<
2324 <<
2325 menu "Boot options" <<
2326 <<
2327 config ARM64_ACPI_PARKING_PROTOCOL <<
2328 bool "Enable support for the ARM64 AC <<
2329 depends on ACPI <<
2330 help <<
2331 Enable support for the ARM64 ACPI p <<
2332 the kernel will not allow booting t <<
2333 protocol even if the corresponding <<
2334 MADT table. <<
2335 <<
2336 config CMDLINE <<
2337 string "Default kernel command string <<
2338 default "" <<
2339 help <<
2340 Provide a set of default command-li <<
2341 entering them here. As a minimum, y <<
2342 root device (e.g. root=/dev/nfs). <<
2343 3031
2344 choice !! 3032 config ARCH_MMAP_RND_BITS_MIN
2345 prompt "Kernel command line type" !! 3033 default 12 if 64BIT
2346 depends on CMDLINE != "" !! 3034 default 8
2347 default CMDLINE_FROM_BOOTLOADER <<
2348 help <<
2349 Choose how the kernel will handle t <<
2350 command line string. <<
2351 <<
2352 config CMDLINE_FROM_BOOTLOADER <<
2353 bool "Use bootloader kernel arguments <<
2354 help <<
2355 Uses the command-line options passe <<
2356 the boot loader doesn't provide any <<
2357 string provided in CMDLINE will be <<
2358 <<
2359 config CMDLINE_FORCE <<
2360 bool "Always use the default kernel c <<
2361 help <<
2362 Always use the default kernel comma <<
2363 loader passes other arguments to th <<
2364 This is useful if you cannot or don <<
2365 command-line options your boot load <<
2366 3035
2367 endchoice !! 3036 config ARCH_MMAP_RND_BITS_MAX
>> 3037 default 18 if 64BIT
>> 3038 default 15
>> 3039
>> 3040 config ARCH_MMAP_RND_COMPAT_BITS_MIN
>> 3041 default 8
2368 3042
2369 config EFI_STUB !! 3043 config ARCH_MMAP_RND_COMPAT_BITS_MAX
>> 3044 default 15
>> 3045
>> 3046 config I8253
2370 bool 3047 bool
>> 3048 select CLKSRC_I8253
>> 3049 select CLKEVT_I8253
>> 3050 select MIPS_EXTERNAL_TIMER
>> 3051 endmenu
2371 3052
2372 config EFI !! 3053 config TRAD_SIGNALS
2373 bool "UEFI runtime support" !! 3054 bool
2374 depends on OF && !CPU_BIG_ENDIAN <<
2375 depends on KERNEL_MODE_NEON <<
2376 select ARCH_SUPPORTS_ACPI <<
2377 select LIBFDT <<
2378 select UCS2_STRING <<
2379 select EFI_PARAMS_FROM_FDT <<
2380 select EFI_RUNTIME_WRAPPERS <<
2381 select EFI_STUB <<
2382 select EFI_GENERIC_STUB <<
2383 imply IMA_SECURE_AND_OR_TRUSTED_BOOT <<
2384 default y <<
2385 help <<
2386 This option provides support for ru <<
2387 by UEFI firmware (such as non-volat <<
2388 clock, and platform reset). A UEFI <<
2389 allow the kernel to be booted as an <<
2390 is only useful on systems that have <<
2391 <<
2392 config COMPRESSED_INSTALL <<
2393 bool "Install compressed image by def <<
2394 help <<
2395 This makes the regular "make instal <<
2396 image we built, not the legacy unco <<
2397 <<
2398 You can check that a compressed ima <<
2399 "make zinstall" first, and verifyin <<
2400 in your environment before making " <<
2401 you. <<
2402 3055
2403 config DMI !! 3056 config MIPS32_COMPAT
2404 bool "Enable support for SMBIOS (DMI) !! 3057 bool
2405 depends on EFI <<
2406 default y <<
2407 help <<
2408 This enables SMBIOS/DMI feature for <<
2409 3058
2410 This option is only useful on syste !! 3059 config COMPAT
2411 However, even with this option, the !! 3060 bool
2412 continue to boot on existing non-UE <<
2413 3061
2414 endmenu # "Boot options" !! 3062 config MIPS32_O32
>> 3063 bool "Kernel support for o32 binaries"
>> 3064 depends on 64BIT
>> 3065 select ARCH_WANT_OLD_COMPAT_IPC
>> 3066 select COMPAT
>> 3067 select MIPS32_COMPAT
>> 3068 help
>> 3069 Select this option if you want to run o32 binaries. These are pure
>> 3070 32-bit binaries as used by the 32-bit Linux/MIPS port. Most of
>> 3071 existing binaries are in this format.
2415 3072
2416 menu "Power management options" !! 3073 If unsure, say Y.
2417 3074
2418 source "kernel/power/Kconfig" !! 3075 config MIPS32_N32
>> 3076 bool "Kernel support for n32 binaries"
>> 3077 depends on 64BIT
>> 3078 select ARCH_WANT_COMPAT_IPC_PARSE_VERSION
>> 3079 select COMPAT
>> 3080 select MIPS32_COMPAT
>> 3081 help
>> 3082 Select this option if you want to run n32 binaries. These are
>> 3083 64-bit binaries using 32-bit quantities for addressing and certain
>> 3084 data that would normally be 64-bit. They are used in special
>> 3085 cases.
2419 3086
2420 config ARCH_HIBERNATION_POSSIBLE !! 3087 If unsure, say N.
>> 3088
>> 3089 config CC_HAS_MNO_BRANCH_LIKELY
2421 def_bool y 3090 def_bool y
2422 depends on CPU_PM !! 3091 depends on $(cc-option,-mno-branch-likely)
2423 3092
2424 config ARCH_HIBERNATION_HEADER !! 3093 # https://github.com/llvm/llvm-project/issues/61045
>> 3094 config CC_HAS_BROKEN_INLINE_COMPAT_BRANCH
>> 3095 def_bool y if CC_IS_CLANG
>> 3096
>> 3097 menu "Power management options"
>> 3098
>> 3099 config ARCH_HIBERNATION_POSSIBLE
2425 def_bool y 3100 def_bool y
2426 depends on HIBERNATION !! 3101 depends on SYS_SUPPORTS_HOTPLUG_CPU || !SMP
2427 3102
2428 config ARCH_SUSPEND_POSSIBLE 3103 config ARCH_SUSPEND_POSSIBLE
2429 def_bool y 3104 def_bool y
>> 3105 depends on SYS_SUPPORTS_HOTPLUG_CPU || !SMP
2430 3106
2431 endmenu # "Power management options" !! 3107 source "kernel/power/Kconfig"
2432 3108
2433 menu "CPU Power Management" !! 3109 endmenu
2434 3110
2435 source "drivers/cpuidle/Kconfig" !! 3111 config MIPS_EXTERNAL_TIMER
>> 3112 bool
2436 3113
>> 3114 menu "CPU Power Management"
>> 3115
>> 3116 if CPU_SUPPORTS_CPUFREQ && MIPS_EXTERNAL_TIMER
2437 source "drivers/cpufreq/Kconfig" 3117 source "drivers/cpufreq/Kconfig"
>> 3118 endif # CPU_SUPPORTS_CPUFREQ && MIPS_EXTERNAL_TIMER
2438 3119
2439 endmenu # "CPU Power Management" !! 3120 source "drivers/cpuidle/Kconfig"
2440 3121
2441 source "drivers/acpi/Kconfig" !! 3122 endmenu
2442 3123
2443 source "arch/arm64/kvm/Kconfig" !! 3124 source "arch/mips/kvm/Kconfig"
2444 3125
>> 3126 source "arch/mips/vdso/Kconfig"
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