1 # SPDX-License-Identifier: GPL-2.0-only
2 config ARM64
3 def_bool y
4 select ACPI_APMT if ACPI
5 select ACPI_CCA_REQUIRED if ACPI
6 select ACPI_GENERIC_GSI if ACPI
7 select ACPI_GTDT if ACPI
8 select ACPI_HOTPLUG_CPU if ACPI_PROCES
9 select ACPI_IORT if ACPI
10 select ACPI_REDUCED_HARDWARE_ONLY if A
11 select ACPI_MCFG if (ACPI && PCI)
12 select ACPI_SPCR_TABLE if ACPI
13 select ACPI_PPTT if ACPI
14 select ARCH_HAS_DEBUG_WX
15 select ARCH_BINFMT_ELF_EXTRA_PHDRS
16 select ARCH_BINFMT_ELF_STATE
17 select ARCH_CORRECT_STACKTRACE_ON_KRET
18 select ARCH_ENABLE_HUGEPAGE_MIGRATION
19 select ARCH_ENABLE_MEMORY_HOTPLUG
20 select ARCH_ENABLE_MEMORY_HOTREMOVE
21 select ARCH_ENABLE_SPLIT_PMD_PTLOCK if
22 select ARCH_ENABLE_THP_MIGRATION if TR
23 select ARCH_HAS_CACHE_LINE_SIZE
24 select ARCH_HAS_CURRENT_STACK_POINTER
25 select ARCH_HAS_DEBUG_VIRTUAL
26 select ARCH_HAS_DEBUG_VM_PGTABLE
27 select ARCH_HAS_DMA_OPS if XEN
28 select ARCH_HAS_DMA_PREP_COHERENT
29 select ARCH_HAS_ACPI_TABLE_UPGRADE if
30 select ARCH_HAS_FAST_MULTIPLIER
31 select ARCH_HAS_FORTIFY_SOURCE
32 select ARCH_HAS_GCOV_PROFILE_ALL
33 select ARCH_HAS_GIGANTIC_PAGE
34 select ARCH_HAS_KCOV
35 select ARCH_HAS_KERNEL_FPU_SUPPORT if
36 select ARCH_HAS_KEEPINITRD
37 select ARCH_HAS_MEMBARRIER_SYNC_CORE
38 select ARCH_HAS_MEM_ENCRYPT
39 select ARCH_HAS_NMI_SAFE_THIS_CPU_OPS
40 select ARCH_HAS_NON_OVERLAPPING_ADDRES
41 select ARCH_HAS_PTE_DEVMAP
42 select ARCH_HAS_PTE_SPECIAL
43 select ARCH_HAS_HW_PTE_YOUNG
44 select ARCH_HAS_SETUP_DMA_OPS
45 select ARCH_HAS_SET_DIRECT_MAP
46 select ARCH_HAS_SET_MEMORY
47 select ARCH_STACKWALK
48 select ARCH_HAS_STRICT_KERNEL_RWX
49 select ARCH_HAS_STRICT_MODULE_RWX
50 select ARCH_HAS_SYNC_DMA_FOR_DEVICE
51 select ARCH_HAS_SYNC_DMA_FOR_CPU
52 select ARCH_HAS_SYSCALL_WRAPPER
53 select ARCH_HAS_TICK_BROADCAST if GENE
54 select ARCH_HAS_ZONE_DMA_SET if EXPERT
55 select ARCH_HAVE_ELF_PROT
56 select ARCH_HAVE_NMI_SAFE_CMPXCHG
57 select ARCH_HAVE_TRACE_MMIO_ACCESS
58 select ARCH_INLINE_READ_LOCK if !PREEM
59 select ARCH_INLINE_READ_LOCK_BH if !PR
60 select ARCH_INLINE_READ_LOCK_IRQ if !P
61 select ARCH_INLINE_READ_LOCK_IRQSAVE i
62 select ARCH_INLINE_READ_UNLOCK if !PRE
63 select ARCH_INLINE_READ_UNLOCK_BH if !
64 select ARCH_INLINE_READ_UNLOCK_IRQ if
65 select ARCH_INLINE_READ_UNLOCK_IRQREST
66 select ARCH_INLINE_WRITE_LOCK if !PREE
67 select ARCH_INLINE_WRITE_LOCK_BH if !P
68 select ARCH_INLINE_WRITE_LOCK_IRQ if !
69 select ARCH_INLINE_WRITE_LOCK_IRQSAVE
70 select ARCH_INLINE_WRITE_UNLOCK if !PR
71 select ARCH_INLINE_WRITE_UNLOCK_BH if
72 select ARCH_INLINE_WRITE_UNLOCK_IRQ if
73 select ARCH_INLINE_WRITE_UNLOCK_IRQRES
74 select ARCH_INLINE_SPIN_TRYLOCK if !PR
75 select ARCH_INLINE_SPIN_TRYLOCK_BH if
76 select ARCH_INLINE_SPIN_LOCK if !PREEM
77 select ARCH_INLINE_SPIN_LOCK_BH if !PR
78 select ARCH_INLINE_SPIN_LOCK_IRQ if !P
79 select ARCH_INLINE_SPIN_LOCK_IRQSAVE i
80 select ARCH_INLINE_SPIN_UNLOCK if !PRE
81 select ARCH_INLINE_SPIN_UNLOCK_BH if !
82 select ARCH_INLINE_SPIN_UNLOCK_IRQ if
83 select ARCH_INLINE_SPIN_UNLOCK_IRQREST
84 select ARCH_KEEP_MEMBLOCK
85 select ARCH_MHP_MEMMAP_ON_MEMORY_ENABL
86 select ARCH_USE_CMPXCHG_LOCKREF
87 select ARCH_USE_GNU_PROPERTY
88 select ARCH_USE_MEMTEST
89 select ARCH_USE_QUEUED_RWLOCKS
90 select ARCH_USE_QUEUED_SPINLOCKS
91 select ARCH_USE_SYM_ANNOTATIONS
92 select ARCH_SUPPORTS_DEBUG_PAGEALLOC
93 select ARCH_SUPPORTS_HUGETLBFS
94 select ARCH_SUPPORTS_MEMORY_FAILURE
95 select ARCH_SUPPORTS_SHADOW_CALL_STACK
96 select ARCH_SUPPORTS_LTO_CLANG if CPU_
97 select ARCH_SUPPORTS_LTO_CLANG_THIN
98 select ARCH_SUPPORTS_CFI_CLANG
99 select ARCH_SUPPORTS_ATOMIC_RMW
100 select ARCH_SUPPORTS_INT128 if CC_HAS_
101 select ARCH_SUPPORTS_NUMA_BALANCING
102 select ARCH_SUPPORTS_PAGE_TABLE_CHECK
103 select ARCH_SUPPORTS_PER_VMA_LOCK
104 select ARCH_SUPPORTS_HUGE_PFNMAP if TR
105 select ARCH_SUPPORTS_RT
106 select ARCH_WANT_BATCHED_UNMAP_TLB_FLU
107 select ARCH_WANT_COMPAT_IPC_PARSE_VERS
108 select ARCH_WANT_DEFAULT_BPF_JIT
109 select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_
110 select ARCH_WANT_FRAME_POINTERS
111 select ARCH_WANT_HUGE_PMD_SHARE if ARM
112 select ARCH_WANT_LD_ORPHAN_WARN
113 select ARCH_WANTS_EXECMEM_LATE if EXEC
114 select ARCH_WANTS_NO_INSTR
115 select ARCH_WANTS_THP_SWAP if ARM64_4K
116 select ARCH_HAS_UBSAN
117 select ARM_AMBA
118 select ARM_ARCH_TIMER
119 select ARM_GIC
120 select AUDIT_ARCH_COMPAT_GENERIC
121 select ARM_GIC_V2M if PCI
122 select ARM_GIC_V3
123 select ARM_GIC_V3_ITS if PCI
124 select ARM_PSCI_FW
125 select BUILDTIME_TABLE_SORT
126 select CLONE_BACKWARDS
127 select COMMON_CLK
128 select CPU_PM if (SUSPEND || CPU_IDLE)
129 select CPUMASK_OFFSTACK if NR_CPUS > 2
130 select CRC32
131 select DCACHE_WORD_ACCESS
132 select DYNAMIC_FTRACE if FUNCTION_TRAC
133 select DMA_BOUNCE_UNALIGNED_KMALLOC
134 select DMA_DIRECT_REMAP
135 select EDAC_SUPPORT
136 select FRAME_POINTER
137 select FUNCTION_ALIGNMENT_4B
138 select FUNCTION_ALIGNMENT_8B if DYNAMI
139 select GENERIC_ALLOCATOR
140 select GENERIC_ARCH_TOPOLOGY
141 select GENERIC_CLOCKEVENTS_BROADCAST
142 select GENERIC_CPU_AUTOPROBE
143 select GENERIC_CPU_DEVICES
144 select GENERIC_CPU_VULNERABILITIES
145 select GENERIC_EARLY_IOREMAP
146 select GENERIC_IDLE_POLL_SETUP
147 select GENERIC_IOREMAP
148 select GENERIC_IRQ_IPI
149 select GENERIC_IRQ_PROBE
150 select GENERIC_IRQ_SHOW
151 select GENERIC_IRQ_SHOW_LEVEL
152 select GENERIC_LIB_DEVMEM_IS_ALLOWED
153 select GENERIC_PCI_IOMAP
154 select GENERIC_PTDUMP
155 select GENERIC_SCHED_CLOCK
156 select GENERIC_SMP_IDLE_THREAD
157 select GENERIC_TIME_VSYSCALL
158 select GENERIC_GETTIMEOFDAY
159 select GENERIC_VDSO_TIME_NS
160 select HARDIRQS_SW_RESEND
161 select HAS_IOPORT
162 select HAVE_MOVE_PMD
163 select HAVE_MOVE_PUD
164 select HAVE_PCI
165 select HAVE_ACPI_APEI if (ACPI && EFI)
166 select HAVE_ALIGNED_STRUCT_PAGE
167 select HAVE_ARCH_AUDITSYSCALL
168 select HAVE_ARCH_BITREVERSE
169 select HAVE_ARCH_COMPILER_H
170 select HAVE_ARCH_HUGE_VMALLOC
171 select HAVE_ARCH_HUGE_VMAP
172 select HAVE_ARCH_JUMP_LABEL
173 select HAVE_ARCH_JUMP_LABEL_RELATIVE
174 select HAVE_ARCH_KASAN
175 select HAVE_ARCH_KASAN_VMALLOC
176 select HAVE_ARCH_KASAN_SW_TAGS
177 select HAVE_ARCH_KASAN_HW_TAGS if ARM6
178 # Some instrumentation may be unsound,
179 select HAVE_ARCH_KCSAN if EXPERT
180 select HAVE_ARCH_KFENCE
181 select HAVE_ARCH_KGDB
182 select HAVE_ARCH_MMAP_RND_BITS
183 select HAVE_ARCH_MMAP_RND_COMPAT_BITS
184 select HAVE_ARCH_PREL32_RELOCATIONS
185 select HAVE_ARCH_RANDOMIZE_KSTACK_OFFS
186 select HAVE_ARCH_SECCOMP_FILTER
187 select HAVE_ARCH_STACKLEAK
188 select HAVE_ARCH_THREAD_STRUCT_WHITELI
189 select HAVE_ARCH_TRACEHOOK
190 select HAVE_ARCH_TRANSPARENT_HUGEPAGE
191 select HAVE_ARCH_VMAP_STACK
192 select HAVE_ARM_SMCCC
193 select HAVE_ASM_MODVERSIONS
194 select HAVE_EBPF_JIT
195 select HAVE_C_RECORDMCOUNT
196 select HAVE_CMPXCHG_DOUBLE
197 select HAVE_CMPXCHG_LOCAL
198 select HAVE_CONTEXT_TRACKING_USER
199 select HAVE_DEBUG_KMEMLEAK
200 select HAVE_DMA_CONTIGUOUS
201 select HAVE_DYNAMIC_FTRACE
202 select HAVE_DYNAMIC_FTRACE_WITH_ARGS \
203 if (GCC_SUPPORTS_DYNAMIC_FTRAC
204 CLANG_SUPPORTS_DYNAMIC_FTR
205 select HAVE_DYNAMIC_FTRACE_WITH_DIRECT
206 if DYNAMIC_FTRACE_WITH_ARGS &&
207 select HAVE_DYNAMIC_FTRACE_WITH_CALL_O
208 if (DYNAMIC_FTRACE_WITH_ARGS &
209 (CC_IS_CLANG || !CC_OPTIMI
210 select FTRACE_MCOUNT_USE_PATCHABLE_FUN
211 if DYNAMIC_FTRACE_WITH_ARGS
212 select HAVE_SAMPLE_FTRACE_DIRECT
213 select HAVE_SAMPLE_FTRACE_DIRECT_MULTI
214 select HAVE_EFFICIENT_UNALIGNED_ACCESS
215 select HAVE_GUP_FAST
216 select HAVE_FTRACE_MCOUNT_RECORD
217 select HAVE_FUNCTION_TRACER
218 select HAVE_FUNCTION_ERROR_INJECTION
219 select HAVE_FUNCTION_GRAPH_TRACER
220 select HAVE_FUNCTION_GRAPH_RETVAL
221 select HAVE_GCC_PLUGINS
222 select HAVE_HARDLOCKUP_DETECTOR_PERF i
223 HW_PERF_EVENTS && HAVE_PERF_EV
224 select HAVE_HW_BREAKPOINT if PERF_EVEN
225 select HAVE_IOREMAP_PROT
226 select HAVE_IRQ_TIME_ACCOUNTING
227 select HAVE_MOD_ARCH_SPECIFIC
228 select HAVE_NMI
229 select HAVE_PERF_EVENTS
230 select HAVE_PERF_EVENTS_NMI if ARM64_P
231 select HAVE_PERF_REGS
232 select HAVE_PERF_USER_STACK_DUMP
233 select HAVE_PREEMPT_DYNAMIC_KEY
234 select HAVE_REGS_AND_STACK_ACCESS_API
235 select HAVE_POSIX_CPU_TIMERS_TASK_WORK
236 select HAVE_FUNCTION_ARG_ACCESS_API
237 select MMU_GATHER_RCU_TABLE_FREE
238 select HAVE_RSEQ
239 select HAVE_RUST if RUSTC_SUPPORTS_ARM
240 select HAVE_STACKPROTECTOR
241 select HAVE_SYSCALL_TRACEPOINTS
242 select HAVE_KPROBES
243 select HAVE_KRETPROBES
244 select HAVE_GENERIC_VDSO
245 select HOTPLUG_CORE_SYNC_DEAD if HOTPL
246 select IRQ_DOMAIN
247 select IRQ_FORCED_THREADING
248 select KASAN_VMALLOC if KASAN
249 select LOCK_MM_AND_FIND_VMA
250 select MODULES_USE_ELF_RELA
251 select NEED_DMA_MAP_STATE
252 select NEED_SG_DMA_LENGTH
253 select OF
254 select OF_EARLY_FLATTREE
255 select PCI_DOMAINS_GENERIC if PCI
256 select PCI_ECAM if (ACPI && PCI)
257 select PCI_SYSCALL if PCI
258 select POWER_RESET
259 select POWER_SUPPLY
260 select SPARSE_IRQ
261 select SWIOTLB
262 select SYSCTL_EXCEPTION_TRACE
263 select THREAD_INFO_IN_TASK
264 select HAVE_ARCH_USERFAULTFD_MINOR if
265 select HAVE_ARCH_USERFAULTFD_WP if USE
266 select TRACE_IRQFLAGS_SUPPORT
267 select TRACE_IRQFLAGS_NMI_SUPPORT
268 select HAVE_SOFTIRQ_ON_OWN_STACK
269 select USER_STACKTRACE_SUPPORT
270 select VDSO_GETRANDOM
271 help
272 ARM 64-bit (AArch64) Linux support.
273
274 config RUSTC_SUPPORTS_ARM64
275 def_bool y
276 depends on CPU_LITTLE_ENDIAN
277 # Shadow call stack is only supported
278 #
279 # When using the UNWIND_PATCH_PAC_INTO
280 # required due to use of the -Zfixed-x
281 #
282 # Otherwise, rustc version 1.82+ is re
283 # -Zsanitizer=shadow-call-stack flag.
284 depends on !SHADOW_CALL_STACK || RUSTC
285
286 config CLANG_SUPPORTS_DYNAMIC_FTRACE_WITH_ARGS
287 def_bool CC_IS_CLANG
288 # https://github.com/ClangBuiltLinux/l
289 depends on AS_IS_GNU || (AS_IS_LLVM &&
290
291 config GCC_SUPPORTS_DYNAMIC_FTRACE_WITH_ARGS
292 def_bool CC_IS_GCC
293 depends on $(cc-option,-fpatchable-fun
294
295 config 64BIT
296 def_bool y
297
298 config MMU
299 def_bool y
300
301 config ARM64_CONT_PTE_SHIFT
302 int
303 default 5 if PAGE_SIZE_64KB
304 default 7 if PAGE_SIZE_16KB
305 default 4
306
307 config ARM64_CONT_PMD_SHIFT
308 int
309 default 5 if PAGE_SIZE_64KB
310 default 5 if PAGE_SIZE_16KB
311 default 4
312
313 config ARCH_MMAP_RND_BITS_MIN
314 default 14 if PAGE_SIZE_64KB
315 default 16 if PAGE_SIZE_16KB
316 default 18
317
318 # max bits determined by the following formula
319 # VA_BITS - PAGE_SHIFT - 3
320 config ARCH_MMAP_RND_BITS_MAX
321 default 19 if ARM64_VA_BITS=36
322 default 24 if ARM64_VA_BITS=39
323 default 27 if ARM64_VA_BITS=42
324 default 30 if ARM64_VA_BITS=47
325 default 29 if ARM64_VA_BITS=48 && ARM6
326 default 31 if ARM64_VA_BITS=48 && ARM6
327 default 33 if ARM64_VA_BITS=48
328 default 14 if ARM64_64K_PAGES
329 default 16 if ARM64_16K_PAGES
330 default 18
331
332 config ARCH_MMAP_RND_COMPAT_BITS_MIN
333 default 7 if ARM64_64K_PAGES
334 default 9 if ARM64_16K_PAGES
335 default 11
336
337 config ARCH_MMAP_RND_COMPAT_BITS_MAX
338 default 16
339
340 config NO_IOPORT_MAP
341 def_bool y if !PCI
342
343 config STACKTRACE_SUPPORT
344 def_bool y
345
346 config ILLEGAL_POINTER_VALUE
347 hex
348 default 0xdead000000000000
349
350 config LOCKDEP_SUPPORT
351 def_bool y
352
353 config GENERIC_BUG
354 def_bool y
355 depends on BUG
356
357 config GENERIC_BUG_RELATIVE_POINTERS
358 def_bool y
359 depends on GENERIC_BUG
360
361 config GENERIC_HWEIGHT
362 def_bool y
363
364 config GENERIC_CSUM
365 def_bool y
366
367 config GENERIC_CALIBRATE_DELAY
368 def_bool y
369
370 config SMP
371 def_bool y
372
373 config KERNEL_MODE_NEON
374 def_bool y
375
376 config FIX_EARLYCON_MEM
377 def_bool y
378
379 config PGTABLE_LEVELS
380 int
381 default 2 if ARM64_16K_PAGES && ARM64_
382 default 2 if ARM64_64K_PAGES && ARM64_
383 default 3 if ARM64_64K_PAGES && (ARM64
384 default 3 if ARM64_4K_PAGES && ARM64_V
385 default 3 if ARM64_16K_PAGES && ARM64_
386 default 4 if ARM64_16K_PAGES && (ARM64
387 default 4 if !ARM64_64K_PAGES && ARM64
388 default 5 if ARM64_4K_PAGES && ARM64_V
389
390 config ARCH_SUPPORTS_UPROBES
391 def_bool y
392
393 config ARCH_PROC_KCORE_TEXT
394 def_bool y
395
396 config BROKEN_GAS_INST
397 def_bool !$(as-instr,1:\n.inst 0\n.rep
398
399 config BUILTIN_RETURN_ADDRESS_STRIPS_PAC
400 bool
401 # Clang's __builtin_return_address() s
402 # https://github.com/llvm/llvm-project
403 default y if CC_IS_CLANG
404 # GCC's __builtin_return_address() str
405 # and this was backported to 10.2.0, 9
406 # https://gcc.gnu.org/bugzilla/show_bu
407 default y if CC_IS_GCC && (GCC_VERSION
408 default y if CC_IS_GCC && (GCC_VERSION
409 default y if CC_IS_GCC && (GCC_VERSION
410 default y if CC_IS_GCC && (GCC_VERSION
411 default n
412
413 config KASAN_SHADOW_OFFSET
414 hex
415 depends on KASAN_GENERIC || KASAN_SW_T
416 default 0xdfff800000000000 if (ARM64_V
417 default 0xdfffc00000000000 if (ARM64_V
418 default 0xdffffe0000000000 if ARM64_VA
419 default 0xdfffffc000000000 if ARM64_VA
420 default 0xdffffff800000000 if ARM64_VA
421 default 0xefff800000000000 if (ARM64_V
422 default 0xefffc00000000000 if (ARM64_V
423 default 0xeffffe0000000000 if ARM64_VA
424 default 0xefffffc000000000 if ARM64_VA
425 default 0xeffffff800000000 if ARM64_VA
426 default 0xffffffffffffffff
427
428 config UNWIND_TABLES
429 bool
430
431 source "arch/arm64/Kconfig.platforms"
432
433 menu "Kernel Features"
434
435 menu "ARM errata workarounds via the alternati
436
437 config AMPERE_ERRATUM_AC03_CPU_38
438 bool "AmpereOne: AC03_CPU_38: Certain
439 default y
440 help
441 This option adds an alternative code
442 errata AC03_CPU_38 and AC04_CPU_10 o
443
444 The affected design reports FEAT_HAF
445 ID_AA64MMFR1_EL1.HAFDBS, but (V)TCR_
446 as required by the architecture. The
447 implementation suffers from an addit
448 A/D updates can occur after a PTE ha
449
450 The workaround forces KVM to explici
451 which avoids enabling unadvertised h
452 at stage-2.
453
454 If unsure, say Y.
455
456 config ARM64_WORKAROUND_CLEAN_CACHE
457 bool
458
459 config ARM64_ERRATUM_826319
460 bool "Cortex-A53: 826319: System might
461 default y
462 select ARM64_WORKAROUND_CLEAN_CACHE
463 help
464 This option adds an alternative code
465 erratum 826319 on Cortex-A53 parts u
466 AXI master interface and an L2 cache
467
468 If a Cortex-A53 uses an AMBA AXI4 AC
469 and is unable to accept a certain wr
470 not progress on read data presented
471 system can deadlock.
472
473 The workaround promotes data cache c
474 data cache clean-and-invalidate.
475 Please note that this does not neces
476 as it depends on the alternative fra
477 the kernel if an affected CPU is det
478
479 If unsure, say Y.
480
481 config ARM64_ERRATUM_827319
482 bool "Cortex-A53: 827319: Data cache c
483 default y
484 select ARM64_WORKAROUND_CLEAN_CACHE
485 help
486 This option adds an alternative code
487 erratum 827319 on Cortex-A53 parts u
488 master interface and an L2 cache.
489
490 Under certain conditions this erratu
491 to occur at the same time as another
492 on the AMBA 5 CHI interface, which c
493 interconnect reorders the two transa
494
495 The workaround promotes data cache c
496 data cache clean-and-invalidate.
497 Please note that this does not neces
498 as it depends on the alternative fra
499 the kernel if an affected CPU is det
500
501 If unsure, say Y.
502
503 config ARM64_ERRATUM_824069
504 bool "Cortex-A53: 824069: Cache line m
505 default y
506 select ARM64_WORKAROUND_CLEAN_CACHE
507 help
508 This option adds an alternative code
509 erratum 824069 on Cortex-A53 parts u
510 to a coherent interconnect.
511
512 If a Cortex-A53 processor is executi
513 write instruction at the same time a
514 cluster is executing a cache mainten
515 address, then this erratum might cau
516 incorrectly marked as dirty.
517
518 The workaround promotes data cache c
519 data cache clean-and-invalidate.
520 Please note that this option does no
521 workaround, as it depends on the alt
522 only patch the kernel if an affected
523
524 If unsure, say Y.
525
526 config ARM64_ERRATUM_819472
527 bool "Cortex-A53: 819472: Store exclus
528 default y
529 select ARM64_WORKAROUND_CLEAN_CACHE
530 help
531 This option adds an alternative code
532 erratum 819472 on Cortex-A53 parts u
533 present when it is connected to a co
534
535 If the processor is executing a load
536 the same time as a processor in anot
537 maintenance operation to the same ad
538 cause data corruption.
539
540 The workaround promotes data cache c
541 data cache clean-and-invalidate.
542 Please note that this does not neces
543 as it depends on the alternative fra
544 the kernel if an affected CPU is det
545
546 If unsure, say Y.
547
548 config ARM64_ERRATUM_832075
549 bool "Cortex-A57: 832075: possible dea
550 default y
551 help
552 This option adds an alternative code
553 erratum 832075 on Cortex-A57 parts u
554
555 Affected Cortex-A57 parts might dead
556 instructions to Write-Back memory ar
557
558 The workaround is to promote device
559 semantics.
560 Please note that this does not neces
561 as it depends on the alternative fra
562 the kernel if an affected CPU is det
563
564 If unsure, say Y.
565
566 config ARM64_ERRATUM_834220
567 bool "Cortex-A57: 834220: Stage 2 tran
568 depends on KVM
569 help
570 This option adds an alternative code
571 erratum 834220 on Cortex-A57 parts u
572
573 Affected Cortex-A57 parts might repo
574 fault as the result of a Stage 1 fau
575 page boundary when there is a permis
576 alignment fault at Stage 1 and a tra
577
578 The workaround is to verify that the
579 doesn't generate a fault before hand
580 Please note that this does not neces
581 as it depends on the alternative fra
582 the kernel if an affected CPU is det
583
584 If unsure, say N.
585
586 config ARM64_ERRATUM_1742098
587 bool "Cortex-A57/A72: 1742098: ELR rec
588 depends on COMPAT
589 default y
590 help
591 This option removes the AES hwcap fo
592 workaround erratum 1742098 on Cortex
593
594 Affected parts may corrupt the AES s
595 taken between a pair of AES instruct
596 are only present if the cryptography
597 All software should have a fallback
598 that don't implement the cryptograph
599
600 If unsure, say Y.
601
602 config ARM64_ERRATUM_845719
603 bool "Cortex-A53: 845719: a load might
604 depends on COMPAT
605 default y
606 help
607 This option adds an alternative code
608 erratum 845719 on Cortex-A53 parts u
609
610 When running a compat (AArch32) user
611 part, a load at EL0 from a virtual a
612 bits of the virtual address used by
613 might return incorrect data.
614
615 The workaround is to write the conte
616 return to a 32-bit task.
617 Please note that this does not neces
618 as it depends on the alternative fra
619 the kernel if an affected CPU is det
620
621 If unsure, say Y.
622
623 config ARM64_ERRATUM_843419
624 bool "Cortex-A53: 843419: A load or st
625 default y
626 help
627 This option links the kernel with '-
628 enables PLT support to replace certa
629 cause subsequent memory accesses to
630 Cortex-A53 parts up to r0p4.
631
632 If unsure, say Y.
633
634 config ARM64_LD_HAS_FIX_ERRATUM_843419
635 def_bool $(ld-option,--fix-cortex-a53-
636
637 config ARM64_ERRATUM_1024718
638 bool "Cortex-A55: 1024718: Update of D
639 default y
640 help
641 This option adds a workaround for AR
642
643 Affected Cortex-A55 cores (all revis
644 update of the hardware dirty bit whe
645 without a break-before-make. The wor
646 of hardware DBM locally on the affec
647 this erratum will continue to use th
648
649 If unsure, say Y.
650
651 config ARM64_ERRATUM_1418040
652 bool "Cortex-A76/Neoverse-N1: MRC read
653 default y
654 depends on COMPAT
655 help
656 This option adds a workaround for AR
657 errata 1188873 and 1418040.
658
659 Affected Cortex-A76/Neoverse-N1 core
660 cause register corruption when acces
661 from AArch32 userspace.
662
663 If unsure, say Y.
664
665 config ARM64_WORKAROUND_SPECULATIVE_AT
666 bool
667
668 config ARM64_ERRATUM_1165522
669 bool "Cortex-A76: 1165522: Speculative
670 default y
671 select ARM64_WORKAROUND_SPECULATIVE_AT
672 help
673 This option adds a workaround for AR
674
675 Affected Cortex-A76 cores (r0p0, r1p
676 corrupted TLBs by speculating an AT
677 context switch.
678
679 If unsure, say Y.
680
681 config ARM64_ERRATUM_1319367
682 bool "Cortex-A57/A72: 1319537: Specula
683 default y
684 select ARM64_WORKAROUND_SPECULATIVE_AT
685 help
686 This option adds work arounds for AR
687 and A72 erratum 1319367
688
689 Cortex-A57 and A72 cores could end-u
690 speculating an AT instruction during
691
692 If unsure, say Y.
693
694 config ARM64_ERRATUM_1530923
695 bool "Cortex-A55: 1530923: Speculative
696 default y
697 select ARM64_WORKAROUND_SPECULATIVE_AT
698 help
699 This option adds a workaround for AR
700
701 Affected Cortex-A55 cores (r0p0, r0p
702 corrupted TLBs by speculating an AT
703 context switch.
704
705 If unsure, say Y.
706
707 config ARM64_WORKAROUND_REPEAT_TLBI
708 bool
709
710 config ARM64_ERRATUM_2441007
711 bool "Cortex-A55: Completion of affect
712 select ARM64_WORKAROUND_REPEAT_TLBI
713 help
714 This option adds a workaround for AR
715
716 Under very rare circumstances, affec
717 may not handle a race between a brea
718 CPU, and another CPU accessing the s
719 store to a page that has been unmapp
720
721 Work around this by adding the affec
722 TLB sequences to be done twice.
723
724 If unsure, say N.
725
726 config ARM64_ERRATUM_1286807
727 bool "Cortex-A76: Modification of the
728 select ARM64_WORKAROUND_REPEAT_TLBI
729 help
730 This option adds a workaround for AR
731
732 On the affected Cortex-A76 cores (r0
733 address for a cacheable mapping of a
734 accessed by a core while another cor
735 address to a new physical page using
736 break-before-make sequence, then und
737 TLBI+DSB completes before a read usi
738 invalidated has been observed by oth
739 workaround repeats the TLBI+DSB oper
740
741 If unsure, say N.
742
743 config ARM64_ERRATUM_1463225
744 bool "Cortex-A76: Software Step might
745 default y
746 help
747 This option adds a workaround for Ar
748
749 On the affected Cortex-A76 cores (r0
750 of a system call instruction (SVC) c
751 subsequent interrupts when software
752 exception handler of the system call
753 is enabled or VHE is in use.
754
755 Work around the erratum by triggerin
756 when handling a system call from a t
757 in a VHE configuration of the kernel
758
759 If unsure, say Y.
760
761 config ARM64_ERRATUM_1542419
762 bool "Neoverse-N1: workaround mis-orde
763 help
764 This option adds a workaround for AR
765 1542419.
766
767 Affected Neoverse-N1 cores could exe
768 modified by another CPU. The workaro
769 counterpart.
770
771 Workaround the issue by hiding the D
772 forces user-space to perform cache m
773
774 If unsure, say N.
775
776 config ARM64_ERRATUM_1508412
777 bool "Cortex-A77: 1508412: workaround
778 default y
779 help
780 This option adds a workaround for Ar
781
782 Affected Cortex-A77 cores (r0p0, r1p
783 of a store-exclusive or read of PAR_
784 non-cacheable memory attributes. The
785 counterpart.
786
787 KVM guests must also have the workar
788 deadlock the system.
789
790 Work around the issue by inserting D
791 register reads and warning KVM users
792 to prevent a speculative PAR_EL1 rea
793
794 If unsure, say Y.
795
796 config ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MO
797 bool
798
799 config ARM64_ERRATUM_2051678
800 bool "Cortex-A510: 2051678: disable Ha
801 default y
802 help
803 This options adds the workaround for
804 Affected Cortex-A510 might not respe
805 hardware update of the page table's
806 is to not enable the feature on affe
807
808 If unsure, say Y.
809
810 config ARM64_ERRATUM_2077057
811 bool "Cortex-A510: 2077057: workaround
812 default y
813 help
814 This option adds the workaround for
815 Affected Cortex-A510 may corrupt SPS
816 expected, but a Pointer Authenticati
817 erratum causes SPSR_EL1 to be copied
818 EL1 to cause a return to EL2 with a
819
820 This can only happen when EL2 is ste
821
822 When these conditions occur, the SPS
823 previous guest entry, and can be res
824
825 If unsure, say Y.
826
827 config ARM64_ERRATUM_2658417
828 bool "Cortex-A510: 2658417: remove BF1
829 default y
830 help
831 This option adds the workaround for
832 Affected Cortex-A510 (r0p0 to r1p1)
833 BFMMLA or VMMLA instructions in rare
834 A510 CPUs are using shared neon hard
835 discoverable by the kernel, hide the
836 user-space should not be using these
837
838 If unsure, say Y.
839
840 config ARM64_ERRATUM_2119858
841 bool "Cortex-A710/X2: 2119858: workaro
842 default y
843 depends on CORESIGHT_TRBE
844 select ARM64_WORKAROUND_TRBE_OVERWRITE
845 help
846 This option adds the workaround for
847
848 Affected Cortex-A710/X2 cores could
849 data at the base of the buffer (poin
850 the event of a WRAP event.
851
852 Work around the issue by always maki
853 256 bytes before enabling the buffer
854 the buffer with ETM ignore packets u
855
856 If unsure, say Y.
857
858 config ARM64_ERRATUM_2139208
859 bool "Neoverse-N2: 2139208: workaround
860 default y
861 depends on CORESIGHT_TRBE
862 select ARM64_WORKAROUND_TRBE_OVERWRITE
863 help
864 This option adds the workaround for
865
866 Affected Neoverse-N2 cores could ove
867 data at the base of the buffer (poin
868 the event of a WRAP event.
869
870 Work around the issue by always maki
871 256 bytes before enabling the buffer
872 the buffer with ETM ignore packets u
873
874 If unsure, say Y.
875
876 config ARM64_WORKAROUND_TSB_FLUSH_FAILURE
877 bool
878
879 config ARM64_ERRATUM_2054223
880 bool "Cortex-A710: 2054223: workaround
881 default y
882 select ARM64_WORKAROUND_TSB_FLUSH_FAIL
883 help
884 Enable workaround for ARM Cortex-A71
885
886 Affected cores may fail to flush the
887 the PE is in trace prohibited state.
888 of the trace cached.
889
890 Workaround is to issue two TSB conse
891
892 If unsure, say Y.
893
894 config ARM64_ERRATUM_2067961
895 bool "Neoverse-N2: 2067961: workaround
896 default y
897 select ARM64_WORKAROUND_TSB_FLUSH_FAIL
898 help
899 Enable workaround for ARM Neoverse-N
900
901 Affected cores may fail to flush the
902 the PE is in trace prohibited state.
903 of the trace cached.
904
905 Workaround is to issue two TSB conse
906
907 If unsure, say Y.
908
909 config ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANG
910 bool
911
912 config ARM64_ERRATUM_2253138
913 bool "Neoverse-N2: 2253138: workaround
914 depends on CORESIGHT_TRBE
915 default y
916 select ARM64_WORKAROUND_TRBE_WRITE_OUT
917 help
918 This option adds the workaround for
919
920 Affected Neoverse-N2 cores might wri
921 for TRBE. Under some conditions, the
922 virtually addressed page following t
923 (i.e., the TRBLIMITR_EL1.LIMIT), ins
924
925 Work around this in the driver by al
926 page beyond the TRBLIMITR_EL1.LIMIT,
927
928 If unsure, say Y.
929
930 config ARM64_ERRATUM_2224489
931 bool "Cortex-A710/X2: 2224489: workaro
932 depends on CORESIGHT_TRBE
933 default y
934 select ARM64_WORKAROUND_TRBE_WRITE_OUT
935 help
936 This option adds the workaround for
937
938 Affected Cortex-A710/X2 cores might
939 for TRBE. Under some conditions, the
940 virtually addressed page following t
941 (i.e., the TRBLIMITR_EL1.LIMIT), ins
942
943 Work around this in the driver by al
944 page beyond the TRBLIMITR_EL1.LIMIT,
945
946 If unsure, say Y.
947
948 config ARM64_ERRATUM_2441009
949 bool "Cortex-A510: Completion of affec
950 select ARM64_WORKAROUND_REPEAT_TLBI
951 help
952 This option adds a workaround for AR
953
954 Under very rare circumstances, affec
955 may not handle a race between a brea
956 CPU, and another CPU accessing the s
957 store to a page that has been unmapp
958
959 Work around this by adding the affec
960 TLB sequences to be done twice.
961
962 If unsure, say N.
963
964 config ARM64_ERRATUM_2064142
965 bool "Cortex-A510: 2064142: workaround
966 depends on CORESIGHT_TRBE
967 default y
968 help
969 This option adds the workaround for
970
971 Affected Cortex-A510 core might fail
972 TRBE has been disabled. Under some c
973 writes into TRBE registers TRBLIMITR
974 and TRBTRG_EL1 will be ignored and w
975
976 Work around this in the driver by ex
977 is stopped and before performing a s
978 registers.
979
980 If unsure, say Y.
981
982 config ARM64_ERRATUM_2038923
983 bool "Cortex-A510: 2038923: workaround
984 depends on CORESIGHT_TRBE
985 default y
986 help
987 This option adds the workaround for
988
989 Affected Cortex-A510 core might caus
990 prohibited within the CPU. As a resu
991 might be corrupted. This happens aft
992 TRBLIMITR_EL1.E, followed by just a
993 execution changes from a context, in
994 isn't, or vice versa. In these menti
995 is prohibited is inconsistent betwee
996 the trace buffer state might be corr
997
998 Work around this in the driver by pr
999 trace is prohibited or not based on
1000 change to TRBLIMITR_EL1.E with at l
1001 two ISB instructions if no ERET is
1002
1003 If unsure, say Y.
1004
1005 config ARM64_ERRATUM_1902691
1006 bool "Cortex-A510: 1902691: workaroun
1007 depends on CORESIGHT_TRBE
1008 default y
1009 help
1010 This option adds the workaround for
1011
1012 Affected Cortex-A510 core might cau
1013 into the memory. Effectively TRBE i
1014 trace data.
1015
1016 Work around this problem in the dri
1017 affected cpus. The firmware must ha
1018 on such implementations. This will
1019 do this already.
1020
1021 If unsure, say Y.
1022
1023 config ARM64_ERRATUM_2457168
1024 bool "Cortex-A510: 2457168: workaroun
1025 depends on ARM64_AMU_EXTN
1026 default y
1027 help
1028 This option adds the workaround for
1029
1030 The AMU counter AMEVCNTR01 (constan
1031 as the system counter. On affected
1032 incorrectly giving a significantly
1033
1034 Work around this problem by returni
1035 key locations that results in disab
1036 is the same to firmware disabling a
1037
1038 If unsure, say Y.
1039
1040 config ARM64_ERRATUM_2645198
1041 bool "Cortex-A715: 2645198: Workaroun
1042 default y
1043 help
1044 This option adds the workaround for
1045
1046 If a Cortex-A715 cpu sees a page ma
1047 to non-executable, it may corrupt t
1048 next instruction abort caused by pe
1049
1050 Only user-space does executable to
1051 mprotect() system call. Workaround
1052 TLB invalidation, for all changes t
1053
1054 If unsure, say Y.
1055
1056 config ARM64_WORKAROUND_SPECULATIVE_UNPRIV_LO
1057 bool
1058
1059 config ARM64_ERRATUM_2966298
1060 bool "Cortex-A520: 2966298: workaroun
1061 select ARM64_WORKAROUND_SPECULATIVE_U
1062 default y
1063 help
1064 This option adds the workaround for
1065
1066 On an affected Cortex-A520 core, a
1067 load might leak data from a privile
1068
1069 Work around this problem by executi
1070
1071 If unsure, say Y.
1072
1073 config ARM64_ERRATUM_3117295
1074 bool "Cortex-A510: 3117295: workaroun
1075 select ARM64_WORKAROUND_SPECULATIVE_U
1076 default y
1077 help
1078 This option adds the workaround for
1079
1080 On an affected Cortex-A510 core, a
1081 load might leak data from a privile
1082
1083 Work around this problem by executi
1084
1085 If unsure, say Y.
1086
1087 config ARM64_ERRATUM_3194386
1088 bool "Cortex-*/Neoverse-*: workaround
1089 default y
1090 help
1091 This option adds the workaround for
1092
1093 * ARM Cortex-A76 erratum 3324349
1094 * ARM Cortex-A77 erratum 3324348
1095 * ARM Cortex-A78 erratum 3324344
1096 * ARM Cortex-A78C erratum 3324346
1097 * ARM Cortex-A78C erratum 3324347
1098 * ARM Cortex-A710 erratam 3324338
1099 * ARM Cortex-A715 errartum 3456084
1100 * ARM Cortex-A720 erratum 3456091
1101 * ARM Cortex-A725 erratum 3456106
1102 * ARM Cortex-X1 erratum 3324344
1103 * ARM Cortex-X1C erratum 3324346
1104 * ARM Cortex-X2 erratum 3324338
1105 * ARM Cortex-X3 erratum 3324335
1106 * ARM Cortex-X4 erratum 3194386
1107 * ARM Cortex-X925 erratum 3324334
1108 * ARM Neoverse-N1 erratum 3324349
1109 * ARM Neoverse N2 erratum 3324339
1110 * ARM Neoverse-N3 erratum 3456111
1111 * ARM Neoverse-V1 erratum 3324341
1112 * ARM Neoverse V2 erratum 3324336
1113 * ARM Neoverse-V3 erratum 3312417
1114
1115 On affected cores "MSR SSBS, #0" in
1116 subsequent speculative instructions
1117 speculative store bypassing.
1118
1119 Work around this problem by placing
1120 Instruction Synchronization Barrier
1121 SSBS. The presence of the SSBS spec
1122 from hwcaps and EL0 reads of ID_AA6
1123 will use the PR_SPEC_STORE_BYPASS p
1124
1125 If unsure, say Y.
1126
1127 config CAVIUM_ERRATUM_22375
1128 bool "Cavium erratum 22375, 24313"
1129 default y
1130 help
1131 Enable workaround for errata 22375
1132
1133 This implements two gicv3-its errat
1134 with a small impact affecting only
1135
1136 erratum 22375: only alloc 8MB tab
1137 erratum 24313: ignore memory acce
1138
1139 The fixes are in ITS initialization
1140 type and table size provided by the
1141
1142 If unsure, say Y.
1143
1144 config CAVIUM_ERRATUM_23144
1145 bool "Cavium erratum 23144: ITS SYNC
1146 depends on NUMA
1147 default y
1148 help
1149 ITS SYNC command hang for cross nod
1150
1151 If unsure, say Y.
1152
1153 config CAVIUM_ERRATUM_23154
1154 bool "Cavium errata 23154 and 38545:
1155 default y
1156 help
1157 The ThunderX GICv3 implementation r
1158 reading the IAR status to ensure da
1159 (access to icc_iar1_el1 is not sync
1160
1161 It also suffers from erratum 38545
1162 OcteonTX and OcteonTX2), resulting
1163 spuriously presented to the CPU int
1164
1165 If unsure, say Y.
1166
1167 config CAVIUM_ERRATUM_27456
1168 bool "Cavium erratum 27456: Broadcast
1169 default y
1170 help
1171 On ThunderX T88 pass 1.x through 2.
1172 instructions may cause the icache t
1173 contains data for a non-current ASI
1174 invalidate the icache when changing
1175
1176 If unsure, say Y.
1177
1178 config CAVIUM_ERRATUM_30115
1179 bool "Cavium erratum 30115: Guest may
1180 default y
1181 help
1182 On ThunderX T88 pass 1.x through 2.
1183 1.2, and T83 Pass 1.0, KVM guest ex
1184 interrupts in host. Trapping both G
1185 accesses sidesteps the issue.
1186
1187 If unsure, say Y.
1188
1189 config CAVIUM_TX2_ERRATUM_219
1190 bool "Cavium ThunderX2 erratum 219: P
1191 default y
1192 help
1193 On Cavium ThunderX2, a load, store
1194 TTBR update and the corresponding c
1195 cause a spurious Data Abort to be d
1196 the CPU core.
1197
1198 Work around the issue by avoiding t
1199 trapping KVM guest TTBRx_EL1 writes
1200 trap handler performs the correspon
1201 instruction and ensures context syn
1202 exception return.
1203
1204 If unsure, say Y.
1205
1206 config FUJITSU_ERRATUM_010001
1207 bool "Fujitsu-A64FX erratum E#010001:
1208 default y
1209 help
1210 This option adds a workaround for F
1211 On some variants of the Fujitsu-A64
1212 accesses may cause undefined fault
1213 This fault occurs under a specific
1214 load/store instruction performs an
1215 case-1 TTBR0_EL1 with TCR_EL1.NFD0
1216 case-2 TTBR0_EL2 with TCR_EL2.NFD0
1217 case-3 TTBR1_EL1 with TCR_EL1.NFD1
1218 case-4 TTBR1_EL2 with TCR_EL2.NFD1
1219
1220 The workaround is to ensure these b
1221 The workaround only affects the Fuj
1222
1223 If unsure, say Y.
1224
1225 config HISILICON_ERRATUM_161600802
1226 bool "Hip07 161600802: Erroneous redi
1227 default y
1228 help
1229 The HiSilicon Hip07 SoC uses the wr
1230 when issued ITS commands such as VM
1231 a 128kB offset to be applied to the
1232
1233 If unsure, say Y.
1234
1235 config QCOM_FALKOR_ERRATUM_1003
1236 bool "Falkor E1003: Incorrect transla
1237 default y
1238 help
1239 On Falkor v1, an incorrect ASID may
1240 and BADDR are changed together in T
1241 in TTBR1_EL1, this situation only o
1242 then only for entries in the walk c
1243 is unchanged. Work around the errat
1244 entries for the trampoline before e
1245
1246 config QCOM_FALKOR_ERRATUM_1009
1247 bool "Falkor E1009: Prematurely compl
1248 default y
1249 select ARM64_WORKAROUND_REPEAT_TLBI
1250 help
1251 On Falkor v1, the CPU may premature
1252 TLBI xxIS invalidate maintenance op
1253 one more time to fix the issue.
1254
1255 If unsure, say Y.
1256
1257 config QCOM_QDF2400_ERRATUM_0065
1258 bool "QDF2400 E0065: Incorrect GITS_T
1259 default y
1260 help
1261 On Qualcomm Datacenter Technologies
1262 ITE size incorrectly. The GITS_TYPE
1263 been indicated as 16Bytes (0xf), no
1264
1265 If unsure, say Y.
1266
1267 config QCOM_FALKOR_ERRATUM_E1041
1268 bool "Falkor E1041: Speculative instr
1269 default y
1270 help
1271 Falkor CPU may speculatively fetch
1272 memory location when MMU translatio
1273 to SCTLR_ELn[M]=0. Prefix an ISB in
1274
1275 If unsure, say Y.
1276
1277 config NVIDIA_CARMEL_CNP_ERRATUM
1278 bool "NVIDIA Carmel CNP: CNP on Carme
1279 default y
1280 help
1281 If CNP is enabled on Carmel cores,
1282 invalidate shared TLB entries insta
1283 on standard ARM cores.
1284
1285 If unsure, say Y.
1286
1287 config ROCKCHIP_ERRATUM_3588001
1288 bool "Rockchip 3588001: GIC600 can no
1289 default y
1290 help
1291 The Rockchip RK3588 GIC600 SoC inte
1292 This means, that its sharability fe
1293 is supported by the IP itself.
1294
1295 If unsure, say Y.
1296
1297 config SOCIONEXT_SYNQUACER_PREITS
1298 bool "Socionext Synquacer: Workaround
1299 default y
1300 help
1301 Socionext Synquacer SoCs implement
1302 MSI doorbell writes with non-zero v
1303
1304 If unsure, say Y.
1305
1306 endmenu # "ARM errata workarounds via the alt
1307
1308 choice
1309 prompt "Page size"
1310 default ARM64_4K_PAGES
1311 help
1312 Page size (translation granule) con
1313
1314 config ARM64_4K_PAGES
1315 bool "4KB"
1316 select HAVE_PAGE_SIZE_4KB
1317 help
1318 This feature enables 4KB pages supp
1319
1320 config ARM64_16K_PAGES
1321 bool "16KB"
1322 select HAVE_PAGE_SIZE_16KB
1323 help
1324 The system will use 16KB pages supp
1325 requires applications compiled with
1326 aligned segments.
1327
1328 config ARM64_64K_PAGES
1329 bool "64KB"
1330 select HAVE_PAGE_SIZE_64KB
1331 help
1332 This feature enables 64KB pages sup
1333 allowing only two levels of page ta
1334 look-up. AArch32 emulation requires
1335 with 64K aligned segments.
1336
1337 endchoice
1338
1339 choice
1340 prompt "Virtual address space size"
1341 default ARM64_VA_BITS_52
1342 help
1343 Allows choosing one of multiple pos
1344 space sizes. The level of translati
1345 a combination of page size and virt
1346
1347 config ARM64_VA_BITS_36
1348 bool "36-bit" if EXPERT
1349 depends on PAGE_SIZE_16KB
1350
1351 config ARM64_VA_BITS_39
1352 bool "39-bit"
1353 depends on PAGE_SIZE_4KB
1354
1355 config ARM64_VA_BITS_42
1356 bool "42-bit"
1357 depends on PAGE_SIZE_64KB
1358
1359 config ARM64_VA_BITS_47
1360 bool "47-bit"
1361 depends on PAGE_SIZE_16KB
1362
1363 config ARM64_VA_BITS_48
1364 bool "48-bit"
1365
1366 config ARM64_VA_BITS_52
1367 bool "52-bit"
1368 depends on ARM64_PAN || !ARM64_SW_TTB
1369 help
1370 Enable 52-bit virtual addressing fo
1371 requested via a hint to mmap(). The
1372 virtual addresses for its own mappi
1373 this feature is available, otherwis
1374
1375 NOTE: Enabling 52-bit virtual addre
1376 ARMv8.3 Pointer Authentication will
1377 reduced from 7 bits to 3 bits, whic
1378 impact on its susceptibility to bru
1379
1380 If unsure, select 48-bit virtual ad
1381
1382 endchoice
1383
1384 config ARM64_FORCE_52BIT
1385 bool "Force 52-bit virtual addresses
1386 depends on ARM64_VA_BITS_52 && EXPERT
1387 help
1388 For systems with 52-bit userspace V
1389 to maintain compatibility with olde
1390 unless a hint is supplied to mmap.
1391
1392 This configuration option disables
1393 forces all userspace addresses to b
1394 should only enable this configurati
1395 memory management code. If unsure s
1396
1397 config ARM64_VA_BITS
1398 int
1399 default 36 if ARM64_VA_BITS_36
1400 default 39 if ARM64_VA_BITS_39
1401 default 42 if ARM64_VA_BITS_42
1402 default 47 if ARM64_VA_BITS_47
1403 default 48 if ARM64_VA_BITS_48
1404 default 52 if ARM64_VA_BITS_52
1405
1406 choice
1407 prompt "Physical address space size"
1408 default ARM64_PA_BITS_48
1409 help
1410 Choose the maximum physical address
1411 support.
1412
1413 config ARM64_PA_BITS_48
1414 bool "48-bit"
1415 depends on ARM64_64K_PAGES || !ARM64_
1416
1417 config ARM64_PA_BITS_52
1418 bool "52-bit"
1419 depends on ARM64_64K_PAGES || ARM64_V
1420 depends on ARM64_PAN || !ARM64_SW_TTB
1421 help
1422 Enable support for a 52-bit physica
1423 part of the ARMv8.2-LPA extension.
1424
1425 With this enabled, the kernel will
1426 do not support ARMv8.2-LPA, but wit
1427 minor performance overhead).
1428
1429 endchoice
1430
1431 config ARM64_PA_BITS
1432 int
1433 default 48 if ARM64_PA_BITS_48
1434 default 52 if ARM64_PA_BITS_52
1435
1436 config ARM64_LPA2
1437 def_bool y
1438 depends on ARM64_PA_BITS_52 && !ARM64
1439
1440 choice
1441 prompt "Endianness"
1442 default CPU_LITTLE_ENDIAN
1443 help
1444 Select the endianness of data acces
1445 applications will need to be compil
1446 that is selected here.
1447
1448 config CPU_BIG_ENDIAN
1449 bool "Build big-endian kernel"
1450 # https://github.com/llvm/llvm-projec
1451 depends on AS_IS_GNU || AS_VERSION >=
1452 help
1453 Say Y if you plan on running a kern
1454
1455 config CPU_LITTLE_ENDIAN
1456 bool "Build little-endian kernel"
1457 help
1458 Say Y if you plan on running a kern
1459 This is usually the case for distri
1460
1461 endchoice
1462
1463 config SCHED_MC
1464 bool "Multi-core scheduler support"
1465 help
1466 Multi-core scheduler support improv
1467 making when dealing with multi-core
1468 increased overhead in some places.
1469
1470 config SCHED_CLUSTER
1471 bool "Cluster scheduler support"
1472 help
1473 Cluster scheduler support improves
1474 making when dealing with machines t
1475 Cluster usually means a couple of C
1476 by sharing mid-level caches, last-l
1477 busses.
1478
1479 config SCHED_SMT
1480 bool "SMT scheduler support"
1481 help
1482 Improves the CPU scheduler's decisi
1483 MultiThreading at a cost of slightl
1484 places. If unsure say N here.
1485
1486 config NR_CPUS
1487 int "Maximum number of CPUs (2-4096)"
1488 range 2 4096
1489 default "512"
1490
1491 config HOTPLUG_CPU
1492 bool "Support for hot-pluggable CPUs"
1493 select GENERIC_IRQ_MIGRATION
1494 help
1495 Say Y here to experiment with turni
1496 can be controlled through /sys/devi
1497
1498 # Common NUMA Features
1499 config NUMA
1500 bool "NUMA Memory Allocation and Sche
1501 select GENERIC_ARCH_NUMA
1502 select OF_NUMA
1503 select HAVE_SETUP_PER_CPU_AREA
1504 select NEED_PER_CPU_EMBED_FIRST_CHUNK
1505 select NEED_PER_CPU_PAGE_FIRST_CHUNK
1506 select USE_PERCPU_NUMA_NODE_ID
1507 help
1508 Enable NUMA (Non-Uniform Memory Acc
1509
1510 The kernel will try to allocate mem
1511 local memory of the CPU and add som
1512 NUMA awareness to the kernel.
1513
1514 config NODES_SHIFT
1515 int "Maximum NUMA Nodes (as a power o
1516 range 1 10
1517 default "4"
1518 depends on NUMA
1519 help
1520 Specify the maximum number of NUMA
1521 system. Increases memory reserved
1522
1523 source "kernel/Kconfig.hz"
1524
1525 config ARCH_SPARSEMEM_ENABLE
1526 def_bool y
1527 select SPARSEMEM_VMEMMAP_ENABLE
1528 select SPARSEMEM_VMEMMAP
1529
1530 config HW_PERF_EVENTS
1531 def_bool y
1532 depends on ARM_PMU
1533
1534 # Supported by clang >= 7.0 or GCC >= 12.0.0
1535 config CC_HAVE_SHADOW_CALL_STACK
1536 def_bool $(cc-option, -fsanitize=shad
1537
1538 config PARAVIRT
1539 bool "Enable paravirtualization code"
1540 help
1541 This changes the kernel so it can m
1542 under a hypervisor, potentially imp
1543 over full virtualization.
1544
1545 config PARAVIRT_TIME_ACCOUNTING
1546 bool "Paravirtual steal time accounti
1547 select PARAVIRT
1548 help
1549 Select this option to enable fine g
1550 accounting. Time spent executing ot
1551 the current vCPU is discounted from
1552 that, there can be a small performa
1553
1554 If in doubt, say N here.
1555
1556 config ARCH_SUPPORTS_KEXEC
1557 def_bool PM_SLEEP_SMP
1558
1559 config ARCH_SUPPORTS_KEXEC_FILE
1560 def_bool y
1561
1562 config ARCH_SELECTS_KEXEC_FILE
1563 def_bool y
1564 depends on KEXEC_FILE
1565 select HAVE_IMA_KEXEC if IMA
1566
1567 config ARCH_SUPPORTS_KEXEC_SIG
1568 def_bool y
1569
1570 config ARCH_SUPPORTS_KEXEC_IMAGE_VERIFY_SIG
1571 def_bool y
1572
1573 config ARCH_DEFAULT_KEXEC_IMAGE_VERIFY_SIG
1574 def_bool y
1575
1576 config ARCH_SUPPORTS_CRASH_DUMP
1577 def_bool y
1578
1579 config ARCH_HAS_GENERIC_CRASHKERNEL_RESERVATI
1580 def_bool CRASH_RESERVE
1581
1582 config TRANS_TABLE
1583 def_bool y
1584 depends on HIBERNATION || KEXEC_CORE
1585
1586 config XEN_DOM0
1587 def_bool y
1588 depends on XEN
1589
1590 config XEN
1591 bool "Xen guest support on ARM64"
1592 depends on ARM64 && OF
1593 select SWIOTLB_XEN
1594 select PARAVIRT
1595 help
1596 Say Y if you want to run Linux in a
1597
1598 # include/linux/mmzone.h requires the followi
1599 #
1600 # MAX_PAGE_ORDER + PAGE_SHIFT <= SECTION_SI
1601 #
1602 # so the maximum value of MAX_PAGE_ORDER is S
1603 #
1604 # | SECTION_SIZE_BITS | PAGE_SHIFT | m
1605 # ----+-------------------+--------------+---
1606 # 4K | 27 | 12 |
1607 # 16K | 27 | 14 |
1608 # 64K | 29 | 16 |
1609 config ARCH_FORCE_MAX_ORDER
1610 int
1611 default "13" if ARM64_64K_PAGES
1612 default "11" if ARM64_16K_PAGES
1613 default "10"
1614 help
1615 The kernel page allocator limits th
1616 contiguous allocations. The limit i
1617 defines the maximal power of two of
1618 allocated as a single contiguous bl
1619 overriding the default setting when
1620 large blocks of physically contiguo
1621
1622 The maximal size of allocation cann
1623 section, so the value of MAX_PAGE_O
1624
1625 MAX_PAGE_ORDER + PAGE_SHIFT <= SE
1626
1627 Don't change if unsure.
1628
1629 config UNMAP_KERNEL_AT_EL0
1630 bool "Unmap kernel when running in us
1631 default y
1632 help
1633 Speculation attacks against some hi
1634 be used to bypass MMU permission ch
1635 userspace. This can be defended aga
1636 when running in userspace, mapping
1637 via a trampoline page in the vector
1638
1639 If unsure, say Y.
1640
1641 config MITIGATE_SPECTRE_BRANCH_HISTORY
1642 bool "Mitigate Spectre style attacks
1643 default y
1644 help
1645 Speculation attacks against some hi
1646 make use of branch history to influ
1647 When taking an exception from user-
1648 or a firmware call overwrites the b
1649
1650 config RODATA_FULL_DEFAULT_ENABLED
1651 bool "Apply r/o permissions of VM are
1652 default y
1653 help
1654 Apply read-only attributes of VM ar
1655 the backing pages as well. This pre
1656 from being modified (inadvertently
1657 mapping of the same memory page. Th
1658 be turned off at runtime by passing
1659 with rodata=full if this option is
1660
1661 This requires the linear region to
1662 which may adversely affect performa
1663
1664 config ARM64_SW_TTBR0_PAN
1665 bool "Emulate Privileged Access Never
1666 depends on !KCSAN
1667 help
1668 Enabling this option prevents the k
1669 user-space memory directly by point
1670 zeroed area and reserved ASID. The
1671 restore the valid TTBR0_EL1 tempora
1672
1673 config ARM64_TAGGED_ADDR_ABI
1674 bool "Enable the tagged user addresse
1675 default y
1676 help
1677 When this option is enabled, user a
1678 relaxed ABI via prctl() allowing ta
1679 to system calls as pointer argument
1680 Documentation/arch/arm64/tagged-add
1681
1682 menuconfig COMPAT
1683 bool "Kernel support for 32-bit EL0"
1684 depends on ARM64_4K_PAGES || EXPERT
1685 select HAVE_UID16
1686 select OLD_SIGSUSPEND3
1687 select COMPAT_OLD_SIGACTION
1688 help
1689 This option enables support for a 3
1690 kernel at EL1. AArch32-specific com
1691 the user helper functions, VFP supp
1692 handled appropriately by the kernel
1693
1694 If you use a page size other than 4
1695 that you will only be able to execu
1696 with page size aligned segments.
1697
1698 If you want to execute 32-bit users
1699
1700 if COMPAT
1701
1702 config KUSER_HELPERS
1703 bool "Enable kuser helpers page for 3
1704 default y
1705 help
1706 Warning: disabling this option may
1707
1708 Provide kuser helpers to compat tas
1709 helper code to userspace in read on
1710 to allow userspace to be independen
1711 the system. This permits binaries t
1712 to ARMv8 without modification.
1713
1714 See Documentation/arch/arm/kernel_u
1715
1716 However, the fixed address nature o
1717 by ROP (return orientated programmi
1718 exploits.
1719
1720 If all of the binaries and librarie
1721 are built specifically for your pla
1722 these helpers, then you can turn th
1723 such exploits. However, in that cas
1724 relying on those helpers is run, it
1725
1726 Say N here only if you are absolute
1727 need these helpers; otherwise, the
1728
1729 config COMPAT_VDSO
1730 bool "Enable vDSO for 32-bit applicat
1731 depends on !CPU_BIG_ENDIAN
1732 depends on (CC_IS_CLANG && LD_IS_LLD)
1733 select GENERIC_COMPAT_VDSO
1734 default y
1735 help
1736 Place in the process address space
1737 ELF shared object providing fast im
1738 and clock_gettime.
1739
1740 You must have a 32-bit build of gli
1741 to seamlessly take advantage of thi
1742
1743 config THUMB2_COMPAT_VDSO
1744 bool "Compile the 32-bit vDSO for Thu
1745 depends on COMPAT_VDSO
1746 default y
1747 help
1748 Compile the compat vDSO with '-mthu
1749 otherwise with '-marm'.
1750
1751 config COMPAT_ALIGNMENT_FIXUPS
1752 bool "Fix up misaligned multi-word lo
1753
1754 menuconfig ARMV8_DEPRECATED
1755 bool "Emulate deprecated/obsolete ARM
1756 depends on SYSCTL
1757 help
1758 Legacy software support may require
1759 that have been deprecated or obsole
1760
1761 Enable this config to enable select
1762 features.
1763
1764 If unsure, say Y
1765
1766 if ARMV8_DEPRECATED
1767
1768 config SWP_EMULATION
1769 bool "Emulate SWP/SWPB instructions"
1770 help
1771 ARMv8 obsoletes the use of A32 SWP/
1772 they are always undefined. Say Y he
1773 emulation of these instructions for
1774 This feature can be controlled at r
1775 sysctl which is disabled by default
1776
1777 In some older versions of glibc [<=
1778 trylock() operations with the assum
1779 be preempted. This invalid assumpti
1780 with SWP emulation enabled, leading
1781 application.
1782
1783 NOTE: when accessing uncached share
1784 on an external transaction monitori
1785 monitor to maintain update atomicit
1786 implement a global monitor, this op
1787 perform SWP operations to uncached
1788
1789 If unsure, say Y
1790
1791 config CP15_BARRIER_EMULATION
1792 bool "Emulate CP15 Barrier instructio
1793 help
1794 The CP15 barrier instructions - CP1
1795 CP15DMB - are deprecated in ARMv8 (
1796 strongly recommended to use the ISB
1797 instructions instead.
1798
1799 Say Y here to enable software emula
1800 instructions for AArch32 userspace
1801 enabled, CP15 barrier usage is trac
1802 identify software that needs updati
1803 controlled at runtime with the abi.
1804
1805 If unsure, say Y
1806
1807 config SETEND_EMULATION
1808 bool "Emulate SETEND instruction"
1809 help
1810 The SETEND instruction alters the d
1811 AArch32 EL0, and is deprecated in A
1812
1813 Say Y here to enable software emula
1814 for AArch32 userspace code. This fe
1815 at runtime with the abi.setend sysc
1816
1817 Note: All the cpus on the system mu
1818 for this feature to be enabled. If
1819 endian - is hotplugged in after thi
1820 be unexpected results in the applic
1821
1822 If unsure, say Y
1823 endif # ARMV8_DEPRECATED
1824
1825 endif # COMPAT
1826
1827 menu "ARMv8.1 architectural features"
1828
1829 config ARM64_HW_AFDBM
1830 bool "Support for hardware updates of
1831 default y
1832 help
1833 The ARMv8.1 architecture extensions
1834 hardware updates of the access and
1835 table entries. When enabled in TCR_
1836 capable processors, accesses to pag
1837 set this bit instead of raising an
1838 Similarly, writes to read-only page
1839 clear the read-only bit (AP[2]) ins
1840 permission fault.
1841
1842 Kernels built with this configurati
1843 to work on pre-ARMv8.1 hardware and
1844 minimal. If unsure, say Y.
1845
1846 config ARM64_PAN
1847 bool "Enable support for Privileged A
1848 default y
1849 help
1850 Privileged Access Never (PAN; part
1851 prevents the kernel or hypervisor f
1852 memory directly.
1853
1854 Choosing this option will cause any
1855 copy_to_user et al) memory access t
1856
1857 The feature is detected at runtime,
1858 instruction if the cpu does not imp
1859
1860 config AS_HAS_LSE_ATOMICS
1861 def_bool $(as-instr,.arch_extension l
1862
1863 config ARM64_LSE_ATOMICS
1864 bool
1865 default ARM64_USE_LSE_ATOMICS
1866 depends on AS_HAS_LSE_ATOMICS
1867
1868 config ARM64_USE_LSE_ATOMICS
1869 bool "Atomic instructions"
1870 default y
1871 help
1872 As part of the Large System Extensi
1873 atomic instructions that are design
1874 very large systems.
1875
1876 Say Y here to make use of these ins
1877 atomic routines. This incurs a smal
1878 not support these instructions and
1879 built with binutils >= 2.25 in orde
1880 to be used.
1881
1882 endmenu # "ARMv8.1 architectural features"
1883
1884 menu "ARMv8.2 architectural features"
1885
1886 config AS_HAS_ARMV8_2
1887 def_bool $(cc-option,-Wa$(comma)-marc
1888
1889 config AS_HAS_SHA3
1890 def_bool $(as-instr,.arch armv8.2-a+s
1891
1892 config ARM64_PMEM
1893 bool "Enable support for persistent m
1894 select ARCH_HAS_PMEM_API
1895 select ARCH_HAS_UACCESS_FLUSHCACHE
1896 help
1897 Say Y to enable support for the per
1898 ARMv8.2 DCPoP feature.
1899
1900 The feature is detected at runtime,
1901 operations if DC CVAP is not suppor
1902 DC CVAP itself if the system does n
1903
1904 config ARM64_RAS_EXTN
1905 bool "Enable support for RAS CPU Exte
1906 default y
1907 help
1908 CPUs that support the Reliability,
1909 (RAS) Extensions, part of ARMv8.2 a
1910 errors, classify them and report th
1911
1912 On CPUs with these extensions syste
1913 barriers to determine if faults are
1914 classification from a new set of re
1915
1916 Selecting this feature will allow t
1917 and access the new registers if the
1918 Platform RAS features may additiona
1919
1920 config ARM64_CNP
1921 bool "Enable support for Common Not P
1922 default y
1923 depends on ARM64_PAN || !ARM64_SW_TTB
1924 help
1925 Common Not Private (CNP) allows tra
1926 be shared between different PEs in
1927 domain, so the hardware can use thi
1928 caching of such entries in the TLB.
1929
1930 Selecting this option allows the CN
1931 at runtime, and does not affect PEs
1932 this feature.
1933
1934 endmenu # "ARMv8.2 architectural features"
1935
1936 menu "ARMv8.3 architectural features"
1937
1938 config ARM64_PTR_AUTH
1939 bool "Enable support for pointer auth
1940 default y
1941 help
1942 Pointer authentication (part of the
1943 instructions for signing and authen
1944 keys, which can be used to mitigate
1945 and other attacks.
1946
1947 This option enables these instructi
1948 Choosing this option will cause the
1949 for each process at exec() time, wi
1950 context-switched along with the pro
1951
1952 The feature is detected at runtime.
1953 hardware it will not be advertised
1954 be enabled.
1955
1956 If the feature is present on the bo
1957 the late CPU will be parked. Also,
1958 address auth and the late CPU has t
1959 but with the feature disabled. On s
1960 not be selected.
1961
1962 config ARM64_PTR_AUTH_KERNEL
1963 bool "Use pointer authentication for
1964 default y
1965 depends on ARM64_PTR_AUTH
1966 depends on (CC_HAS_SIGN_RETURN_ADDRES
1967 # Modern compilers insert a .note.gnu
1968 # which is only understood by binutil
1969 depends on LD_IS_LLD || LD_VERSION >=
1970 depends on !CC_IS_CLANG || AS_HAS_CFI
1971 depends on (!FUNCTION_GRAPH_TRACER ||
1972 help
1973 If the compiler supports the -mbran
1974 -msign-return-address flag (e.g. GC
1975 will cause the kernel itself to be
1976 protection. In this case, and if th
1977 support pointer authentication, the
1978 disabled with minimal loss of prote
1979
1980 This feature works with FUNCTION_GR
1981 DYNAMIC_FTRACE_WITH_ARGS is enabled
1982
1983 config CC_HAS_BRANCH_PROT_PAC_RET
1984 # GCC 9 or later, clang 8 or later
1985 def_bool $(cc-option,-mbranch-protect
1986
1987 config CC_HAS_SIGN_RETURN_ADDRESS
1988 # GCC 7, 8
1989 def_bool $(cc-option,-msign-return-ad
1990
1991 config AS_HAS_ARMV8_3
1992 def_bool $(cc-option,-Wa$(comma)-marc
1993
1994 config AS_HAS_CFI_NEGATE_RA_STATE
1995 def_bool $(as-instr,.cfi_startproc\n.
1996
1997 config AS_HAS_LDAPR
1998 def_bool $(as-instr,.arch_extension r
1999
2000 endmenu # "ARMv8.3 architectural features"
2001
2002 menu "ARMv8.4 architectural features"
2003
2004 config ARM64_AMU_EXTN
2005 bool "Enable support for the Activity
2006 default y
2007 help
2008 The activity monitors extension is
2009 by the ARMv8.4 CPU architecture. Th
2010 of the activity monitors architectu
2011
2012 To enable the use of this extension
2013
2014 Note that for architectural reasons
2015 support when running on CPUs that p
2016 extension. The required support is
2017 * Version 1.5 and later of the AR
2018
2019 For kernels that have this configur
2020 firmware, you may need to say N her
2021 Otherwise you may experience firmwa
2022 accessing the counter registers. Ev
2023 symptoms, the values returned by th
2024 correctly reflect reality. Most com
2025 indicating that the counter is not
2026
2027 config AS_HAS_ARMV8_4
2028 def_bool $(cc-option,-Wa$(comma)-marc
2029
2030 config ARM64_TLB_RANGE
2031 bool "Enable support for tlbi range f
2032 default y
2033 depends on AS_HAS_ARMV8_4
2034 help
2035 ARMv8.4-TLBI provides TLBI invalida
2036 range of input addresses.
2037
2038 The feature introduces new assembly
2039 support when binutils >= 2.30.
2040
2041 endmenu # "ARMv8.4 architectural features"
2042
2043 menu "ARMv8.5 architectural features"
2044
2045 config AS_HAS_ARMV8_5
2046 def_bool $(cc-option,-Wa$(comma)-marc
2047
2048 config ARM64_BTI
2049 bool "Branch Target Identification su
2050 default y
2051 help
2052 Branch Target Identification (part
2053 provides a mechanism to limit the s
2054 branch instructions such as BR or B
2055
2056 To make use of BTI on CPUs that sup
2057
2058 BTI is intended to provide compleme
2059 flow integrity protection mechanism
2060 authentication mechanism provided a
2061 For this reason, it does not make s
2062 also enabling support for pointer a
2063 enabling this option you should als
2064
2065 Userspace binaries must also be spe
2066 this mechanism. If you say N here
2067 BTI, such binaries can still run, b
2068 enforcement of branch destinations.
2069
2070 config ARM64_BTI_KERNEL
2071 bool "Use Branch Target Identificatio
2072 default y
2073 depends on ARM64_BTI
2074 depends on ARM64_PTR_AUTH_KERNEL
2075 depends on CC_HAS_BRANCH_PROT_PAC_RET
2076 # https://gcc.gnu.org/bugzilla/show_b
2077 depends on !CC_IS_GCC || GCC_VERSION
2078 # https://gcc.gnu.org/bugzilla/show_b
2079 depends on !CC_IS_GCC
2080 depends on (!FUNCTION_GRAPH_TRACER ||
2081 help
2082 Build the kernel with Branch Target
2083 and enable enforcement of this for
2084 is enabled and the system supports
2085 modular code must have BTI enabled.
2086
2087 config CC_HAS_BRANCH_PROT_PAC_RET_BTI
2088 # GCC 9 or later, clang 8 or later
2089 def_bool $(cc-option,-mbranch-protect
2090
2091 config ARM64_E0PD
2092 bool "Enable support for E0PD"
2093 default y
2094 help
2095 E0PD (part of the ARMv8.5 extension
2096 that EL0 accesses made via TTBR1 al
2097 providing similar benefits to KASLR
2098 with lower overhead and without dis
2099 kernel memory such as SPE.
2100
2101 This option enables E0PD for TTBR1
2102
2103 config ARM64_AS_HAS_MTE
2104 # Initial support for MTE went in bin
2105 # ".arch armv8.5-a+memtag" below. How
2106 # as a late addition to the final arc
2107 # is only supported in the newer 2.32
2108 # versions, hence the extra "stgm" in
2109 def_bool $(as-instr,.arch armv8.5-a+m
2110
2111 config ARM64_MTE
2112 bool "Memory Tagging Extension suppor
2113 default y
2114 depends on ARM64_AS_HAS_MTE && ARM64_
2115 depends on AS_HAS_ARMV8_5
2116 depends on AS_HAS_LSE_ATOMICS
2117 # Required for tag checking in the ua
2118 depends on ARM64_PAN
2119 select ARCH_HAS_SUBPAGE_FAULTS
2120 select ARCH_USES_HIGH_VMA_FLAGS
2121 select ARCH_USES_PG_ARCH_2
2122 select ARCH_USES_PG_ARCH_3
2123 help
2124 Memory Tagging (part of the ARMv8.5
2125 architectural support for run-time,
2126 various classes of memory error to
2127 to eliminate vulnerabilities arisin
2128 languages.
2129
2130 This option enables the support for
2131 Extension at EL0 (i.e. for userspac
2132
2133 Selecting this option allows the fe
2134 runtime. Any secondary CPU not impl
2135 not be allowed a late bring-up.
2136
2137 Userspace binaries that want to use
2138 explicitly opt in. The mechanism fo
2139 described in:
2140
2141 Documentation/arch/arm64/memory-tag
2142
2143 endmenu # "ARMv8.5 architectural features"
2144
2145 menu "ARMv8.7 architectural features"
2146
2147 config ARM64_EPAN
2148 bool "Enable support for Enhanced Pri
2149 default y
2150 depends on ARM64_PAN
2151 help
2152 Enhanced Privileged Access Never (E
2153 Access Never to be used with Execut
2154
2155 The feature is detected at runtime,
2156 if the cpu does not implement the f
2157 endmenu # "ARMv8.7 architectural features"
2158
2159 menu "ARMv8.9 architectural features"
2160
2161 config ARM64_POE
2162 prompt "Permission Overlay Extension"
2163 def_bool y
2164 select ARCH_USES_HIGH_VMA_FLAGS
2165 select ARCH_HAS_PKEYS
2166 help
2167 The Permission Overlay Extension is
2168 Protection Keys. Memory Protection
2169 enforcing page-based protections, b
2170 of the page tables when an applicat
2171
2172 For details, see Documentation/core
2173
2174 If unsure, say y.
2175
2176 config ARCH_PKEY_BITS
2177 int
2178 default 3
2179
2180 endmenu # "ARMv8.9 architectural features"
2181
2182 config ARM64_SVE
2183 bool "ARM Scalable Vector Extension s
2184 default y
2185 help
2186 The Scalable Vector Extension (SVE)
2187 execution state which complements a
2188 of the base architecture to support
2189 additional vectorisation opportunit
2190
2191 To enable use of this extension on
2192
2193 On CPUs that support the SVE2 exten
2194 those too.
2195
2196 Note that for architectural reasons
2197 support when running on SVE capable
2198 is present in:
2199
2200 * version 1.5 and later of the AR
2201 * the AArch64 boot wrapper since
2202 ("bootwrapper: SVE: Enable SVE
2203
2204 For other firmware implementations,
2205 or vendor.
2206
2207 If you need the kernel to boot on S
2208 firmware, you may need to say N her
2209 fixed. Otherwise, you may experien
2210 booting the kernel. If unsure and
2211 symptoms, you should assume that it
2212
2213 config ARM64_SME
2214 bool "ARM Scalable Matrix Extension s
2215 default y
2216 depends on ARM64_SVE
2217 depends on BROKEN
2218 help
2219 The Scalable Matrix Extension (SME)
2220 execution state which utilises a su
2221 instruction set, together with the
2222 register state capable of holding t
2223 enable various matrix operations.
2224
2225 config ARM64_PSEUDO_NMI
2226 bool "Support for NMI-like interrupts
2227 select ARM_GIC_V3
2228 help
2229 Adds support for mimicking Non-Mask
2230 GIC interrupt priority. This suppor
2231 ARM GIC.
2232
2233 This high priority configuration fo
2234 explicitly enabled by setting the k
2235 "irqchip.gicv3_pseudo_nmi" to 1.
2236
2237 If unsure, say N
2238
2239 if ARM64_PSEUDO_NMI
2240 config ARM64_DEBUG_PRIORITY_MASKING
2241 bool "Debug interrupt priority maskin
2242 help
2243 This adds runtime checks to functio
2244 interrupts when using priority mask
2245 the validity of ICC_PMR_EL1 when ca
2246
2247 If unsure, say N
2248 endif # ARM64_PSEUDO_NMI
2249
2250 config RELOCATABLE
2251 bool "Build a relocatable kernel imag
2252 select ARCH_HAS_RELR
2253 default y
2254 help
2255 This builds the kernel as a Positio
2256 which retains all relocation metada
2257 kernel binary at runtime to a diffe
2258 address it was linked at.
2259 Since AArch64 uses the RELA relocat
2260 relocation pass at runtime even if
2261 same address it was linked at.
2262
2263 config RANDOMIZE_BASE
2264 bool "Randomize the address of the ke
2265 select RELOCATABLE
2266 help
2267 Randomizes the virtual address at w
2268 loaded, as a security feature that
2269 relying on knowledge of the locatio
2270
2271 It is the bootloader's job to provi
2272 random u64 value in /chosen/kaslr-s
2273
2274 When booting via the UEFI stub, it
2275 EFI_RNG_PROTOCOL implementation (if
2276 to the kernel proper. In addition,
2277 location of the kernel Image as wel
2278
2279 If unsure, say N.
2280
2281 config RANDOMIZE_MODULE_REGION_FULL
2282 bool "Randomize the module region ove
2283 depends on RANDOMIZE_BASE
2284 default y
2285 help
2286 Randomizes the location of the modu
2287 covering the core kernel. This way,
2288 to leak information about the locat
2289 but it does imply that function cal
2290 kernel will need to be resolved via
2291
2292 When this option is not set, the mo
2293 a limited range that contains the [
2294 core kernel, so branch relocations
2295 the region is exhausted. In this pa
2296 exhaustion, modules might be able t
2297
2298 config CC_HAVE_STACKPROTECTOR_SYSREG
2299 def_bool $(cc-option,-mstack-protecto
2300
2301 config STACKPROTECTOR_PER_TASK
2302 def_bool y
2303 depends on STACKPROTECTOR && CC_HAVE_
2304
2305 config UNWIND_PATCH_PAC_INTO_SCS
2306 bool "Enable shadow call stack dynami
2307 # needs Clang with https://github.com
2308 depends on CC_IS_CLANG && CLANG_VERSI
2309 depends on ARM64_PTR_AUTH_KERNEL && C
2310 depends on SHADOW_CALL_STACK
2311 select UNWIND_TABLES
2312 select DYNAMIC_SCS
2313
2314 config ARM64_CONTPTE
2315 bool "Contiguous PTE mappings for use
2316 depends on TRANSPARENT_HUGEPAGE
2317 default y
2318 help
2319 When enabled, user mappings are con
2320 bit, for any mappings that meet the
2321 This reduces TLB pressure and impro
2322
2323 endmenu # "Kernel Features"
2324
2325 menu "Boot options"
2326
2327 config ARM64_ACPI_PARKING_PROTOCOL
2328 bool "Enable support for the ARM64 AC
2329 depends on ACPI
2330 help
2331 Enable support for the ARM64 ACPI p
2332 the kernel will not allow booting t
2333 protocol even if the corresponding
2334 MADT table.
2335
2336 config CMDLINE
2337 string "Default kernel command string
2338 default ""
2339 help
2340 Provide a set of default command-li
2341 entering them here. As a minimum, y
2342 root device (e.g. root=/dev/nfs).
2343
2344 choice
2345 prompt "Kernel command line type"
2346 depends on CMDLINE != ""
2347 default CMDLINE_FROM_BOOTLOADER
2348 help
2349 Choose how the kernel will handle t
2350 command line string.
2351
2352 config CMDLINE_FROM_BOOTLOADER
2353 bool "Use bootloader kernel arguments
2354 help
2355 Uses the command-line options passe
2356 the boot loader doesn't provide any
2357 string provided in CMDLINE will be
2358
2359 config CMDLINE_FORCE
2360 bool "Always use the default kernel c
2361 help
2362 Always use the default kernel comma
2363 loader passes other arguments to th
2364 This is useful if you cannot or don
2365 command-line options your boot load
2366
2367 endchoice
2368
2369 config EFI_STUB
2370 bool
2371
2372 config EFI
2373 bool "UEFI runtime support"
2374 depends on OF && !CPU_BIG_ENDIAN
2375 depends on KERNEL_MODE_NEON
2376 select ARCH_SUPPORTS_ACPI
2377 select LIBFDT
2378 select UCS2_STRING
2379 select EFI_PARAMS_FROM_FDT
2380 select EFI_RUNTIME_WRAPPERS
2381 select EFI_STUB
2382 select EFI_GENERIC_STUB
2383 imply IMA_SECURE_AND_OR_TRUSTED_BOOT
2384 default y
2385 help
2386 This option provides support for ru
2387 by UEFI firmware (such as non-volat
2388 clock, and platform reset). A UEFI
2389 allow the kernel to be booted as an
2390 is only useful on systems that have
2391
2392 config COMPRESSED_INSTALL
2393 bool "Install compressed image by def
2394 help
2395 This makes the regular "make instal
2396 image we built, not the legacy unco
2397
2398 You can check that a compressed ima
2399 "make zinstall" first, and verifyin
2400 in your environment before making "
2401 you.
2402
2403 config DMI
2404 bool "Enable support for SMBIOS (DMI)
2405 depends on EFI
2406 default y
2407 help
2408 This enables SMBIOS/DMI feature for
2409
2410 This option is only useful on syste
2411 However, even with this option, the
2412 continue to boot on existing non-UE
2413
2414 endmenu # "Boot options"
2415
2416 menu "Power management options"
2417
2418 source "kernel/power/Kconfig"
2419
2420 config ARCH_HIBERNATION_POSSIBLE
2421 def_bool y
2422 depends on CPU_PM
2423
2424 config ARCH_HIBERNATION_HEADER
2425 def_bool y
2426 depends on HIBERNATION
2427
2428 config ARCH_SUSPEND_POSSIBLE
2429 def_bool y
2430
2431 endmenu # "Power management options"
2432
2433 menu "CPU Power Management"
2434
2435 source "drivers/cpuidle/Kconfig"
2436
2437 source "drivers/cpufreq/Kconfig"
2438
2439 endmenu # "CPU Power Management"
2440
2441 source "drivers/acpi/Kconfig"
2442
2443 source "arch/arm64/kvm/Kconfig"
2444
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