1 # SPDX-License-Identifier: GPL-2.0-only !! 1 #
2 config ARM64 !! 2 # For a description of the syntax of this configuration file,
3 def_bool y !! 3 # see Documentation/kbuild/kconfig-language.txt.
4 select ACPI_APMT if ACPI !! 4 #
5 select ACPI_CCA_REQUIRED if ACPI <<
6 select ACPI_GENERIC_GSI if ACPI <<
7 select ACPI_GTDT if ACPI <<
8 select ACPI_HOTPLUG_CPU if ACPI_PROCES <<
9 select ACPI_IORT if ACPI <<
10 select ACPI_REDUCED_HARDWARE_ONLY if A <<
11 select ACPI_MCFG if (ACPI && PCI) <<
12 select ACPI_SPCR_TABLE if ACPI <<
13 select ACPI_PPTT if ACPI <<
14 select ARCH_HAS_DEBUG_WX <<
15 select ARCH_BINFMT_ELF_EXTRA_PHDRS <<
16 select ARCH_BINFMT_ELF_STATE <<
17 select ARCH_CORRECT_STACKTRACE_ON_KRET <<
18 select ARCH_ENABLE_HUGEPAGE_MIGRATION <<
19 select ARCH_ENABLE_MEMORY_HOTPLUG <<
20 select ARCH_ENABLE_MEMORY_HOTREMOVE <<
21 select ARCH_ENABLE_SPLIT_PMD_PTLOCK if <<
22 select ARCH_ENABLE_THP_MIGRATION if TR <<
23 select ARCH_HAS_CACHE_LINE_SIZE <<
24 select ARCH_HAS_CURRENT_STACK_POINTER <<
25 select ARCH_HAS_DEBUG_VIRTUAL <<
26 select ARCH_HAS_DEBUG_VM_PGTABLE <<
27 select ARCH_HAS_DMA_OPS if XEN <<
28 select ARCH_HAS_DMA_PREP_COHERENT <<
29 select ARCH_HAS_ACPI_TABLE_UPGRADE if <<
30 select ARCH_HAS_FAST_MULTIPLIER <<
31 select ARCH_HAS_FORTIFY_SOURCE <<
32 select ARCH_HAS_GCOV_PROFILE_ALL <<
33 select ARCH_HAS_GIGANTIC_PAGE <<
34 select ARCH_HAS_KCOV <<
35 select ARCH_HAS_KERNEL_FPU_SUPPORT if <<
36 select ARCH_HAS_KEEPINITRD <<
37 select ARCH_HAS_MEMBARRIER_SYNC_CORE <<
38 select ARCH_HAS_MEM_ENCRYPT <<
39 select ARCH_HAS_NMI_SAFE_THIS_CPU_OPS <<
40 select ARCH_HAS_NON_OVERLAPPING_ADDRES <<
41 select ARCH_HAS_PTE_DEVMAP <<
42 select ARCH_HAS_PTE_SPECIAL <<
43 select ARCH_HAS_HW_PTE_YOUNG <<
44 select ARCH_HAS_SETUP_DMA_OPS <<
45 select ARCH_HAS_SET_DIRECT_MAP <<
46 select ARCH_HAS_SET_MEMORY <<
47 select ARCH_STACKWALK <<
48 select ARCH_HAS_STRICT_KERNEL_RWX <<
49 select ARCH_HAS_STRICT_MODULE_RWX <<
50 select ARCH_HAS_SYNC_DMA_FOR_DEVICE <<
51 select ARCH_HAS_SYNC_DMA_FOR_CPU <<
52 select ARCH_HAS_SYSCALL_WRAPPER <<
53 select ARCH_HAS_TICK_BROADCAST if GENE <<
54 select ARCH_HAS_ZONE_DMA_SET if EXPERT <<
55 select ARCH_HAVE_ELF_PROT <<
56 select ARCH_HAVE_NMI_SAFE_CMPXCHG <<
57 select ARCH_HAVE_TRACE_MMIO_ACCESS <<
58 select ARCH_INLINE_READ_LOCK if !PREEM <<
59 select ARCH_INLINE_READ_LOCK_BH if !PR <<
60 select ARCH_INLINE_READ_LOCK_IRQ if !P <<
61 select ARCH_INLINE_READ_LOCK_IRQSAVE i <<
62 select ARCH_INLINE_READ_UNLOCK if !PRE <<
63 select ARCH_INLINE_READ_UNLOCK_BH if ! <<
64 select ARCH_INLINE_READ_UNLOCK_IRQ if <<
65 select ARCH_INLINE_READ_UNLOCK_IRQREST <<
66 select ARCH_INLINE_WRITE_LOCK if !PREE <<
67 select ARCH_INLINE_WRITE_LOCK_BH if !P <<
68 select ARCH_INLINE_WRITE_LOCK_IRQ if ! <<
69 select ARCH_INLINE_WRITE_LOCK_IRQSAVE <<
70 select ARCH_INLINE_WRITE_UNLOCK if !PR <<
71 select ARCH_INLINE_WRITE_UNLOCK_BH if <<
72 select ARCH_INLINE_WRITE_UNLOCK_IRQ if <<
73 select ARCH_INLINE_WRITE_UNLOCK_IRQRES <<
74 select ARCH_INLINE_SPIN_TRYLOCK if !PR <<
75 select ARCH_INLINE_SPIN_TRYLOCK_BH if <<
76 select ARCH_INLINE_SPIN_LOCK if !PREEM <<
77 select ARCH_INLINE_SPIN_LOCK_BH if !PR <<
78 select ARCH_INLINE_SPIN_LOCK_IRQ if !P <<
79 select ARCH_INLINE_SPIN_LOCK_IRQSAVE i <<
80 select ARCH_INLINE_SPIN_UNLOCK if !PRE <<
81 select ARCH_INLINE_SPIN_UNLOCK_BH if ! <<
82 select ARCH_INLINE_SPIN_UNLOCK_IRQ if <<
83 select ARCH_INLINE_SPIN_UNLOCK_IRQREST <<
84 select ARCH_KEEP_MEMBLOCK <<
85 select ARCH_MHP_MEMMAP_ON_MEMORY_ENABL <<
86 select ARCH_USE_CMPXCHG_LOCKREF <<
87 select ARCH_USE_GNU_PROPERTY <<
88 select ARCH_USE_MEMTEST <<
89 select ARCH_USE_QUEUED_RWLOCKS <<
90 select ARCH_USE_QUEUED_SPINLOCKS <<
91 select ARCH_USE_SYM_ANNOTATIONS <<
92 select ARCH_SUPPORTS_DEBUG_PAGEALLOC <<
93 select ARCH_SUPPORTS_HUGETLBFS <<
94 select ARCH_SUPPORTS_MEMORY_FAILURE <<
95 select ARCH_SUPPORTS_SHADOW_CALL_STACK <<
96 select ARCH_SUPPORTS_LTO_CLANG if CPU_ <<
97 select ARCH_SUPPORTS_LTO_CLANG_THIN <<
98 select ARCH_SUPPORTS_CFI_CLANG <<
99 select ARCH_SUPPORTS_ATOMIC_RMW <<
100 select ARCH_SUPPORTS_INT128 if CC_HAS_ <<
101 select ARCH_SUPPORTS_NUMA_BALANCING <<
102 select ARCH_SUPPORTS_PAGE_TABLE_CHECK <<
103 select ARCH_SUPPORTS_PER_VMA_LOCK <<
104 select ARCH_SUPPORTS_HUGE_PFNMAP if TR <<
105 select ARCH_SUPPORTS_RT <<
106 select ARCH_WANT_BATCHED_UNMAP_TLB_FLU <<
107 select ARCH_WANT_COMPAT_IPC_PARSE_VERS <<
108 select ARCH_WANT_DEFAULT_BPF_JIT <<
109 select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_ <<
110 select ARCH_WANT_FRAME_POINTERS <<
111 select ARCH_WANT_HUGE_PMD_SHARE if ARM <<
112 select ARCH_WANT_LD_ORPHAN_WARN <<
113 select ARCH_WANTS_EXECMEM_LATE if EXEC <<
114 select ARCH_WANTS_NO_INSTR <<
115 select ARCH_WANTS_THP_SWAP if ARM64_4K <<
116 select ARCH_HAS_UBSAN <<
117 select ARM_AMBA <<
118 select ARM_ARCH_TIMER <<
119 select ARM_GIC <<
120 select AUDIT_ARCH_COMPAT_GENERIC <<
121 select ARM_GIC_V2M if PCI <<
122 select ARM_GIC_V3 <<
123 select ARM_GIC_V3_ITS if PCI <<
124 select ARM_PSCI_FW <<
125 select BUILDTIME_TABLE_SORT <<
126 select CLONE_BACKWARDS <<
127 select COMMON_CLK <<
128 select CPU_PM if (SUSPEND || CPU_IDLE) <<
129 select CPUMASK_OFFSTACK if NR_CPUS > 2 <<
130 select CRC32 <<
131 select DCACHE_WORD_ACCESS <<
132 select DYNAMIC_FTRACE if FUNCTION_TRAC <<
133 select DMA_BOUNCE_UNALIGNED_KMALLOC <<
134 select DMA_DIRECT_REMAP <<
135 select EDAC_SUPPORT <<
136 select FRAME_POINTER <<
137 select FUNCTION_ALIGNMENT_4B <<
138 select FUNCTION_ALIGNMENT_8B if DYNAMI <<
139 select GENERIC_ALLOCATOR <<
140 select GENERIC_ARCH_TOPOLOGY <<
141 select GENERIC_CLOCKEVENTS_BROADCAST <<
142 select GENERIC_CPU_AUTOPROBE <<
143 select GENERIC_CPU_DEVICES <<
144 select GENERIC_CPU_VULNERABILITIES <<
145 select GENERIC_EARLY_IOREMAP <<
146 select GENERIC_IDLE_POLL_SETUP <<
147 select GENERIC_IOREMAP <<
148 select GENERIC_IRQ_IPI <<
149 select GENERIC_IRQ_PROBE <<
150 select GENERIC_IRQ_SHOW <<
151 select GENERIC_IRQ_SHOW_LEVEL <<
152 select GENERIC_LIB_DEVMEM_IS_ALLOWED <<
153 select GENERIC_PCI_IOMAP <<
154 select GENERIC_PTDUMP <<
155 select GENERIC_SCHED_CLOCK <<
156 select GENERIC_SMP_IDLE_THREAD <<
157 select GENERIC_TIME_VSYSCALL <<
158 select GENERIC_GETTIMEOFDAY <<
159 select GENERIC_VDSO_TIME_NS <<
160 select HARDIRQS_SW_RESEND <<
161 select HAS_IOPORT <<
162 select HAVE_MOVE_PMD <<
163 select HAVE_MOVE_PUD <<
164 select HAVE_PCI <<
165 select HAVE_ACPI_APEI if (ACPI && EFI) <<
166 select HAVE_ALIGNED_STRUCT_PAGE <<
167 select HAVE_ARCH_AUDITSYSCALL <<
168 select HAVE_ARCH_BITREVERSE <<
169 select HAVE_ARCH_COMPILER_H <<
170 select HAVE_ARCH_HUGE_VMALLOC <<
171 select HAVE_ARCH_HUGE_VMAP <<
172 select HAVE_ARCH_JUMP_LABEL <<
173 select HAVE_ARCH_JUMP_LABEL_RELATIVE <<
174 select HAVE_ARCH_KASAN <<
175 select HAVE_ARCH_KASAN_VMALLOC <<
176 select HAVE_ARCH_KASAN_SW_TAGS <<
177 select HAVE_ARCH_KASAN_HW_TAGS if ARM6 <<
178 # Some instrumentation may be unsound, <<
179 select HAVE_ARCH_KCSAN if EXPERT <<
180 select HAVE_ARCH_KFENCE <<
181 select HAVE_ARCH_KGDB <<
182 select HAVE_ARCH_MMAP_RND_BITS <<
183 select HAVE_ARCH_MMAP_RND_COMPAT_BITS <<
184 select HAVE_ARCH_PREL32_RELOCATIONS <<
185 select HAVE_ARCH_RANDOMIZE_KSTACK_OFFS <<
186 select HAVE_ARCH_SECCOMP_FILTER <<
187 select HAVE_ARCH_STACKLEAK <<
188 select HAVE_ARCH_THREAD_STRUCT_WHITELI <<
189 select HAVE_ARCH_TRACEHOOK <<
190 select HAVE_ARCH_TRANSPARENT_HUGEPAGE <<
191 select HAVE_ARCH_VMAP_STACK <<
192 select HAVE_ARM_SMCCC <<
193 select HAVE_ASM_MODVERSIONS <<
194 select HAVE_EBPF_JIT <<
195 select HAVE_C_RECORDMCOUNT <<
196 select HAVE_CMPXCHG_DOUBLE <<
197 select HAVE_CMPXCHG_LOCAL <<
198 select HAVE_CONTEXT_TRACKING_USER <<
199 select HAVE_DEBUG_KMEMLEAK <<
200 select HAVE_DMA_CONTIGUOUS <<
201 select HAVE_DYNAMIC_FTRACE <<
202 select HAVE_DYNAMIC_FTRACE_WITH_ARGS \ <<
203 if (GCC_SUPPORTS_DYNAMIC_FTRAC <<
204 CLANG_SUPPORTS_DYNAMIC_FTR <<
205 select HAVE_DYNAMIC_FTRACE_WITH_DIRECT <<
206 if DYNAMIC_FTRACE_WITH_ARGS && <<
207 select HAVE_DYNAMIC_FTRACE_WITH_CALL_O <<
208 if (DYNAMIC_FTRACE_WITH_ARGS & <<
209 (CC_IS_CLANG || !CC_OPTIMI <<
210 select FTRACE_MCOUNT_USE_PATCHABLE_FUN <<
211 if DYNAMIC_FTRACE_WITH_ARGS <<
212 select HAVE_SAMPLE_FTRACE_DIRECT <<
213 select HAVE_SAMPLE_FTRACE_DIRECT_MULTI <<
214 select HAVE_EFFICIENT_UNALIGNED_ACCESS <<
215 select HAVE_GUP_FAST <<
216 select HAVE_FTRACE_MCOUNT_RECORD <<
217 select HAVE_FUNCTION_TRACER <<
218 select HAVE_FUNCTION_ERROR_INJECTION <<
219 select HAVE_FUNCTION_GRAPH_TRACER <<
220 select HAVE_FUNCTION_GRAPH_RETVAL <<
221 select HAVE_GCC_PLUGINS <<
222 select HAVE_HARDLOCKUP_DETECTOR_PERF i <<
223 HW_PERF_EVENTS && HAVE_PERF_EV <<
224 select HAVE_HW_BREAKPOINT if PERF_EVEN <<
225 select HAVE_IOREMAP_PROT <<
226 select HAVE_IRQ_TIME_ACCOUNTING <<
227 select HAVE_MOD_ARCH_SPECIFIC <<
228 select HAVE_NMI <<
229 select HAVE_PERF_EVENTS <<
230 select HAVE_PERF_EVENTS_NMI if ARM64_P <<
231 select HAVE_PERF_REGS <<
232 select HAVE_PERF_USER_STACK_DUMP <<
233 select HAVE_PREEMPT_DYNAMIC_KEY <<
234 select HAVE_REGS_AND_STACK_ACCESS_API <<
235 select HAVE_POSIX_CPU_TIMERS_TASK_WORK <<
236 select HAVE_FUNCTION_ARG_ACCESS_API <<
237 select MMU_GATHER_RCU_TABLE_FREE <<
238 select HAVE_RSEQ <<
239 select HAVE_RUST if RUSTC_SUPPORTS_ARM <<
240 select HAVE_STACKPROTECTOR <<
241 select HAVE_SYSCALL_TRACEPOINTS <<
242 select HAVE_KPROBES <<
243 select HAVE_KRETPROBES <<
244 select HAVE_GENERIC_VDSO <<
245 select HOTPLUG_CORE_SYNC_DEAD if HOTPL <<
246 select IRQ_DOMAIN <<
247 select IRQ_FORCED_THREADING <<
248 select KASAN_VMALLOC if KASAN <<
249 select LOCK_MM_AND_FIND_VMA <<
250 select MODULES_USE_ELF_RELA <<
251 select NEED_DMA_MAP_STATE <<
252 select NEED_SG_DMA_LENGTH <<
253 select OF <<
254 select OF_EARLY_FLATTREE <<
255 select PCI_DOMAINS_GENERIC if PCI <<
256 select PCI_ECAM if (ACPI && PCI) <<
257 select PCI_SYSCALL if PCI <<
258 select POWER_RESET <<
259 select POWER_SUPPLY <<
260 select SPARSE_IRQ <<
261 select SWIOTLB <<
262 select SYSCTL_EXCEPTION_TRACE <<
263 select THREAD_INFO_IN_TASK <<
264 select HAVE_ARCH_USERFAULTFD_MINOR if <<
265 select HAVE_ARCH_USERFAULTFD_WP if USE <<
266 select TRACE_IRQFLAGS_SUPPORT <<
267 select TRACE_IRQFLAGS_NMI_SUPPORT <<
268 select HAVE_SOFTIRQ_ON_OWN_STACK <<
269 select USER_STACKTRACE_SUPPORT <<
270 select VDSO_GETRANDOM <<
271 help <<
272 ARM 64-bit (AArch64) Linux support. <<
273 <<
274 config RUSTC_SUPPORTS_ARM64 <<
275 def_bool y <<
276 depends on CPU_LITTLE_ENDIAN <<
277 # Shadow call stack is only supported <<
278 # <<
279 # When using the UNWIND_PATCH_PAC_INTO <<
280 # required due to use of the -Zfixed-x <<
281 # <<
282 # Otherwise, rustc version 1.82+ is re <<
283 # -Zsanitizer=shadow-call-stack flag. <<
284 depends on !SHADOW_CALL_STACK || RUSTC <<
285 <<
286 config CLANG_SUPPORTS_DYNAMIC_FTRACE_WITH_ARGS <<
287 def_bool CC_IS_CLANG <<
288 # https://github.com/ClangBuiltLinux/l <<
289 depends on AS_IS_GNU || (AS_IS_LLVM && <<
290 <<
291 config GCC_SUPPORTS_DYNAMIC_FTRACE_WITH_ARGS <<
292 def_bool CC_IS_GCC <<
293 depends on $(cc-option,-fpatchable-fun <<
294 <<
295 config 64BIT <<
296 def_bool y <<
297 <<
298 config MMU <<
299 def_bool y <<
300 <<
301 config ARM64_CONT_PTE_SHIFT <<
302 int <<
303 default 5 if PAGE_SIZE_64KB <<
304 default 7 if PAGE_SIZE_16KB <<
305 default 4 <<
306 <<
307 config ARM64_CONT_PMD_SHIFT <<
308 int <<
309 default 5 if PAGE_SIZE_64KB <<
310 default 5 if PAGE_SIZE_16KB <<
311 default 4 <<
312 <<
313 config ARCH_MMAP_RND_BITS_MIN <<
314 default 14 if PAGE_SIZE_64KB <<
315 default 16 if PAGE_SIZE_16KB <<
316 default 18 <<
317 <<
318 # max bits determined by the following formula <<
319 # VA_BITS - PAGE_SHIFT - 3 <<
320 config ARCH_MMAP_RND_BITS_MAX <<
321 default 19 if ARM64_VA_BITS=36 <<
322 default 24 if ARM64_VA_BITS=39 <<
323 default 27 if ARM64_VA_BITS=42 <<
324 default 30 if ARM64_VA_BITS=47 <<
325 default 29 if ARM64_VA_BITS=48 && ARM6 <<
326 default 31 if ARM64_VA_BITS=48 && ARM6 <<
327 default 33 if ARM64_VA_BITS=48 <<
328 default 14 if ARM64_64K_PAGES <<
329 default 16 if ARM64_16K_PAGES <<
330 default 18 <<
331 <<
332 config ARCH_MMAP_RND_COMPAT_BITS_MIN <<
333 default 7 if ARM64_64K_PAGES <<
334 default 9 if ARM64_16K_PAGES <<
335 default 11 <<
336 <<
337 config ARCH_MMAP_RND_COMPAT_BITS_MAX <<
338 default 16 <<
339 <<
340 config NO_IOPORT_MAP <<
341 def_bool y if !PCI <<
342 <<
343 config STACKTRACE_SUPPORT <<
344 def_bool y <<
345 <<
346 config ILLEGAL_POINTER_VALUE <<
347 hex <<
348 default 0xdead000000000000 <<
349 <<
350 config LOCKDEP_SUPPORT <<
351 def_bool y <<
352 <<
353 config GENERIC_BUG <<
354 def_bool y <<
355 depends on BUG <<
356 <<
357 config GENERIC_BUG_RELATIVE_POINTERS <<
358 def_bool y <<
359 depends on GENERIC_BUG <<
360 <<
361 config GENERIC_HWEIGHT <<
362 def_bool y <<
363 <<
364 config GENERIC_CSUM <<
365 def_bool y <<
366 <<
367 config GENERIC_CALIBRATE_DELAY <<
368 def_bool y <<
369 <<
370 config SMP <<
371 def_bool y <<
372 <<
373 config KERNEL_MODE_NEON <<
374 def_bool y <<
375 <<
376 config FIX_EARLYCON_MEM <<
377 def_bool y <<
378 <<
379 config PGTABLE_LEVELS <<
380 int <<
381 default 2 if ARM64_16K_PAGES && ARM64_ <<
382 default 2 if ARM64_64K_PAGES && ARM64_ <<
383 default 3 if ARM64_64K_PAGES && (ARM64 <<
384 default 3 if ARM64_4K_PAGES && ARM64_V <<
385 default 3 if ARM64_16K_PAGES && ARM64_ <<
386 default 4 if ARM64_16K_PAGES && (ARM64 <<
387 default 4 if !ARM64_64K_PAGES && ARM64 <<
388 default 5 if ARM64_4K_PAGES && ARM64_V <<
389 <<
390 config ARCH_SUPPORTS_UPROBES <<
391 def_bool y <<
392 <<
393 config ARCH_PROC_KCORE_TEXT <<
394 def_bool y <<
395 <<
396 config BROKEN_GAS_INST <<
397 def_bool !$(as-instr,1:\n.inst 0\n.rep <<
398 <<
399 config BUILTIN_RETURN_ADDRESS_STRIPS_PAC <<
400 bool <<
401 # Clang's __builtin_return_address() s <<
402 # https://github.com/llvm/llvm-project <<
403 default y if CC_IS_CLANG <<
404 # GCC's __builtin_return_address() str <<
405 # and this was backported to 10.2.0, 9 <<
406 # https://gcc.gnu.org/bugzilla/show_bu <<
407 default y if CC_IS_GCC && (GCC_VERSION <<
408 default y if CC_IS_GCC && (GCC_VERSION <<
409 default y if CC_IS_GCC && (GCC_VERSION <<
410 default y if CC_IS_GCC && (GCC_VERSION <<
411 default n <<
412 5
413 config KASAN_SHADOW_OFFSET !! 6 mainmenu "Linux Kernel Configuration"
414 hex <<
415 depends on KASAN_GENERIC || KASAN_SW_T <<
416 default 0xdfff800000000000 if (ARM64_V <<
417 default 0xdfffc00000000000 if (ARM64_V <<
418 default 0xdffffe0000000000 if ARM64_VA <<
419 default 0xdfffffc000000000 if ARM64_VA <<
420 default 0xdffffff800000000 if ARM64_VA <<
421 default 0xefff800000000000 if (ARM64_V <<
422 default 0xefffc00000000000 if (ARM64_V <<
423 default 0xeffffe0000000000 if ARM64_VA <<
424 default 0xefffffc000000000 if ARM64_VA <<
425 default 0xeffffff800000000 if ARM64_VA <<
426 default 0xffffffffffffffff <<
427 7
428 config UNWIND_TABLES !! 8 config X86
429 bool 9 bool
430 <<
431 source "arch/arm64/Kconfig.platforms" <<
432 <<
433 menu "Kernel Features" <<
434 <<
435 menu "ARM errata workarounds via the alternati <<
436 <<
437 config AMPERE_ERRATUM_AC03_CPU_38 <<
438 bool "AmpereOne: AC03_CPU_38: Certain <<
439 default y 10 default y
440 help 11 help
441 This option adds an alternative code !! 12 This is Linux's home port. Linux was originally native to the Intel
442 errata AC03_CPU_38 and AC04_CPU_10 o !! 13 386, and runs on all the later x86 processors including the Intel
443 !! 14 486, 586, Pentiums, and various instruction-set-compatible chips by
444 The affected design reports FEAT_HAF !! 15 AMD, Cyrix, and others.
445 ID_AA64MMFR1_EL1.HAFDBS, but (V)TCR_ <<
446 as required by the architecture. The <<
447 implementation suffers from an addit <<
448 A/D updates can occur after a PTE ha <<
449 <<
450 The workaround forces KVM to explici <<
451 which avoids enabling unadvertised h <<
452 at stage-2. <<
453 <<
454 If unsure, say Y. <<
455 16
456 config ARM64_WORKAROUND_CLEAN_CACHE !! 17 config MMU
457 bool 18 bool
458 <<
459 config ARM64_ERRATUM_826319 <<
460 bool "Cortex-A53: 826319: System might <<
461 default y <<
462 select ARM64_WORKAROUND_CLEAN_CACHE <<
463 help <<
464 This option adds an alternative code <<
465 erratum 826319 on Cortex-A53 parts u <<
466 AXI master interface and an L2 cache <<
467 <<
468 If a Cortex-A53 uses an AMBA AXI4 AC <<
469 and is unable to accept a certain wr <<
470 not progress on read data presented <<
471 system can deadlock. <<
472 <<
473 The workaround promotes data cache c <<
474 data cache clean-and-invalidate. <<
475 Please note that this does not neces <<
476 as it depends on the alternative fra <<
477 the kernel if an affected CPU is det <<
478 <<
479 If unsure, say Y. <<
480 <<
481 config ARM64_ERRATUM_827319 <<
482 bool "Cortex-A53: 827319: Data cache c <<
483 default y 19 default y
484 select ARM64_WORKAROUND_CLEAN_CACHE <<
485 help <<
486 This option adds an alternative code <<
487 erratum 827319 on Cortex-A53 parts u <<
488 master interface and an L2 cache. <<
489 <<
490 Under certain conditions this erratu <<
491 to occur at the same time as another <<
492 on the AMBA 5 CHI interface, which c <<
493 interconnect reorders the two transa <<
494 <<
495 The workaround promotes data cache c <<
496 data cache clean-and-invalidate. <<
497 Please note that this does not neces <<
498 as it depends on the alternative fra <<
499 the kernel if an affected CPU is det <<
500 <<
501 If unsure, say Y. <<
502 <<
503 config ARM64_ERRATUM_824069 <<
504 bool "Cortex-A53: 824069: Cache line m <<
505 default y <<
506 select ARM64_WORKAROUND_CLEAN_CACHE <<
507 help <<
508 This option adds an alternative code <<
509 erratum 824069 on Cortex-A53 parts u <<
510 to a coherent interconnect. <<
511 20
512 If a Cortex-A53 processor is executi !! 21 config SBUS
513 write instruction at the same time a !! 22 bool
514 cluster is executing a cache mainten <<
515 address, then this erratum might cau <<
516 incorrectly marked as dirty. <<
517 <<
518 The workaround promotes data cache c <<
519 data cache clean-and-invalidate. <<
520 Please note that this option does no <<
521 workaround, as it depends on the alt <<
522 only patch the kernel if an affected <<
523 <<
524 If unsure, say Y. <<
525 23
526 config ARM64_ERRATUM_819472 !! 24 config UID16
527 bool "Cortex-A53: 819472: Store exclus !! 25 bool
528 default y 26 default y
529 select ARM64_WORKAROUND_CLEAN_CACHE <<
530 help <<
531 This option adds an alternative code <<
532 erratum 819472 on Cortex-A53 parts u <<
533 present when it is connected to a co <<
534 <<
535 If the processor is executing a load <<
536 the same time as a processor in anot <<
537 maintenance operation to the same ad <<
538 cause data corruption. <<
539 <<
540 The workaround promotes data cache c <<
541 data cache clean-and-invalidate. <<
542 Please note that this does not neces <<
543 as it depends on the alternative fra <<
544 the kernel if an affected CPU is det <<
545 27
546 If unsure, say Y. !! 28 config GENERIC_ISA_DMA
547 !! 29 bool
548 config ARM64_ERRATUM_832075 <<
549 bool "Cortex-A57: 832075: possible dea <<
550 default y 30 default y
551 help <<
552 This option adds an alternative code <<
553 erratum 832075 on Cortex-A57 parts u <<
554 <<
555 Affected Cortex-A57 parts might dead <<
556 instructions to Write-Back memory ar <<
557 31
558 The workaround is to promote device !! 32 source "init/Kconfig"
559 semantics. <<
560 Please note that this does not neces <<
561 as it depends on the alternative fra <<
562 the kernel if an affected CPU is det <<
563 <<
564 If unsure, say Y. <<
565 <<
566 config ARM64_ERRATUM_834220 <<
567 bool "Cortex-A57: 834220: Stage 2 tran <<
568 depends on KVM <<
569 help <<
570 This option adds an alternative code <<
571 erratum 834220 on Cortex-A57 parts u <<
572 33
573 Affected Cortex-A57 parts might repo <<
574 fault as the result of a Stage 1 fau <<
575 page boundary when there is a permis <<
576 alignment fault at Stage 1 and a tra <<
577 34
578 The workaround is to verify that the !! 35 menu "Processor type and features"
579 doesn't generate a fault before hand <<
580 Please note that this does not neces <<
581 as it depends on the alternative fra <<
582 the kernel if an affected CPU is det <<
583 36
584 If unsure, say N. !! 37 choice
>> 38 prompt "Subarchitecture Type"
>> 39 default X86_PC
585 40
586 config ARM64_ERRATUM_1742098 !! 41 config X86_PC
587 bool "Cortex-A57/A72: 1742098: ELR rec !! 42 bool "PC-compatible"
588 depends on COMPAT <<
589 default y <<
590 help 43 help
591 This option removes the AES hwcap fo !! 44 Choose this option if your computer is a standard PC or compatible.
592 workaround erratum 1742098 on Cortex <<
593 <<
594 Affected parts may corrupt the AES s <<
595 taken between a pair of AES instruct <<
596 are only present if the cryptography <<
597 All software should have a fallback <<
598 that don't implement the cryptograph <<
599 <<
600 If unsure, say Y. <<
601 45
602 config ARM64_ERRATUM_845719 !! 46 config X86_VOYAGER
603 bool "Cortex-A53: 845719: a load might !! 47 bool "Voyager (NCR)"
604 depends on COMPAT <<
605 default y <<
606 help 48 help
607 This option adds an alternative code !! 49 Voyager is a MCA based 32 way capable SMP architecture proprietary
608 erratum 845719 on Cortex-A53 parts u !! 50 to NCR Corp. Machine classes 345x/35xx/4100/51xx are voyager based.
609 !! 51
610 When running a compat (AArch32) user !! 52 *** WARNING ***
611 part, a load at EL0 from a virtual a !! 53
612 bits of the virtual address used by !! 54 If you do not specifically know you have a Voyager based machine,
613 might return incorrect data. !! 55 say N here otherwise the kernel you build will not be bootable.
614 <<
615 The workaround is to write the conte <<
616 return to a 32-bit task. <<
617 Please note that this does not neces <<
618 as it depends on the alternative fra <<
619 the kernel if an affected CPU is det <<
620 <<
621 If unsure, say Y. <<
622 56
623 config ARM64_ERRATUM_843419 !! 57 config X86_NUMAQ
624 bool "Cortex-A53: 843419: A load or st !! 58 bool "NUMAQ (IBM/Sequent)"
625 default y <<
626 help 59 help
627 This option links the kernel with '- !! 60 This option is used for getting Linux to run on a (IBM/Sequent) NUMA
628 enables PLT support to replace certa !! 61 multiquad box. This changes the way that processors are bootstrapped,
629 cause subsequent memory accesses to !! 62 and uses Clustered Logical APIC addressing mode instead of Flat Logical.
630 Cortex-A53 parts up to r0p4. !! 63 You will need a new lynxer.elf file to flash your firmware with - send
631 !! 64 email to Martin.Bligh@us.ibm.com
632 If unsure, say Y. <<
633 65
634 config ARM64_LD_HAS_FIX_ERRATUM_843419 !! 66 config X86_SUMMIT
635 def_bool $(ld-option,--fix-cortex-a53- !! 67 bool "Summit/EXA (IBM x440)"
636 !! 68 depends on SMP
637 config ARM64_ERRATUM_1024718 <<
638 bool "Cortex-A55: 1024718: Update of D <<
639 default y <<
640 help 69 help
641 This option adds a workaround for AR !! 70 This option is needed for IBM systems that use the Summit/EXA chipset.
>> 71 In particular, it is needed for the x440.
642 72
643 Affected Cortex-A55 cores (all revis !! 73 If you don't have one of these computers, you should say N here.
644 update of the hardware dirty bit whe <<
645 without a break-before-make. The wor <<
646 of hardware DBM locally on the affec <<
647 this erratum will continue to use th <<
648 74
649 If unsure, say Y. !! 75 config X86_BIGSMP
650 !! 76 bool "Support for other sub-arch SMP systems with more than 8 CPUs"
651 config ARM64_ERRATUM_1418040 !! 77 depends on SMP
652 bool "Cortex-A76/Neoverse-N1: MRC read <<
653 default y <<
654 depends on COMPAT <<
655 help 78 help
656 This option adds a workaround for AR !! 79 This option is needed for the systems that have more than 8 CPUs
657 errata 1188873 and 1418040. !! 80 and if the system is not of any sub-arch type above.
658 <<
659 Affected Cortex-A76/Neoverse-N1 core <<
660 cause register corruption when acces <<
661 from AArch32 userspace. <<
662 81
663 If unsure, say Y. !! 82 If you don't have such a system, you should say N here.
664 83
665 config ARM64_WORKAROUND_SPECULATIVE_AT !! 84 config X86_VISWS
666 bool !! 85 bool "SGI 320/540 (Visual Workstation)"
667 <<
668 config ARM64_ERRATUM_1165522 <<
669 bool "Cortex-A76: 1165522: Speculative <<
670 default y <<
671 select ARM64_WORKAROUND_SPECULATIVE_AT <<
672 help 86 help
673 This option adds a workaround for AR !! 87 The SGI Visual Workstation series is an IA32-based workstation
674 !! 88 based on SGI systems chips with some legacy PC hardware attached.
675 Affected Cortex-A76 cores (r0p0, r1p <<
676 corrupted TLBs by speculating an AT <<
677 context switch. <<
678 89
679 If unsure, say Y. !! 90 Say Y here to create a kernel to run on the SGI 320 or 540.
680 91
681 config ARM64_ERRATUM_1319367 !! 92 A kernel compiled for the Visual Workstation will not run on PCs
682 bool "Cortex-A57/A72: 1319537: Specula !! 93 and vice versa. See <file:Documentation/sgi-visws.txt> for details.
683 default y <<
684 select ARM64_WORKAROUND_SPECULATIVE_AT <<
685 help <<
686 This option adds work arounds for AR <<
687 and A72 erratum 1319367 <<
688 94
689 Cortex-A57 and A72 cores could end-u !! 95 config X86_GENERICARCH
690 speculating an AT instruction during !! 96 bool "Generic architecture (Summit, bigsmp, default)"
>> 97 depends on SMP
>> 98 help
>> 99 This option compiles in the Summit, bigsmp, default subarchitectures.
>> 100 It is intended for a generic binary kernel.
691 101
692 If unsure, say Y. !! 102 config X86_ES7000
693 !! 103 bool "Support for Unisys ES7000 IA32 series"
694 config ARM64_ERRATUM_1530923 !! 104 depends on SMP
695 bool "Cortex-A55: 1530923: Speculative <<
696 default y <<
697 select ARM64_WORKAROUND_SPECULATIVE_AT <<
698 help 105 help
699 This option adds a workaround for AR !! 106 Support for Unisys ES7000 systems. Say 'Y' here if this kernel is
>> 107 supposed to run on an IA32-based Unisys ES7000 system.
>> 108 Only choose this option if you have such a system, otherwise you
>> 109 should say N here.
700 110
701 Affected Cortex-A55 cores (r0p0, r0p !! 111 endchoice
702 corrupted TLBs by speculating an AT <<
703 context switch. <<
704 <<
705 If unsure, say Y. <<
706 112
707 config ARM64_WORKAROUND_REPEAT_TLBI !! 113 config ACPI_SRAT
708 bool 114 bool
709 <<
710 config ARM64_ERRATUM_2441007 <<
711 bool "Cortex-A55: Completion of affect <<
712 select ARM64_WORKAROUND_REPEAT_TLBI <<
713 help <<
714 This option adds a workaround for AR <<
715 <<
716 Under very rare circumstances, affec <<
717 may not handle a race between a brea <<
718 CPU, and another CPU accessing the s <<
719 store to a page that has been unmapp <<
720 <<
721 Work around this by adding the affec <<
722 TLB sequences to be done twice. <<
723 <<
724 If unsure, say N. <<
725 <<
726 config ARM64_ERRATUM_1286807 <<
727 bool "Cortex-A76: Modification of the <<
728 select ARM64_WORKAROUND_REPEAT_TLBI <<
729 help <<
730 This option adds a workaround for AR <<
731 <<
732 On the affected Cortex-A76 cores (r0 <<
733 address for a cacheable mapping of a <<
734 accessed by a core while another cor <<
735 address to a new physical page using <<
736 break-before-make sequence, then und <<
737 TLBI+DSB completes before a read usi <<
738 invalidated has been observed by oth <<
739 workaround repeats the TLBI+DSB oper <<
740 <<
741 If unsure, say N. <<
742 <<
743 config ARM64_ERRATUM_1463225 <<
744 bool "Cortex-A76: Software Step might <<
745 default y 115 default y
746 help !! 116 depends on NUMA && (X86_SUMMIT || X86_GENERICARCH)
747 This option adds a workaround for Ar <<
748 <<
749 On the affected Cortex-A76 cores (r0 <<
750 of a system call instruction (SVC) c <<
751 subsequent interrupts when software <<
752 exception handler of the system call <<
753 is enabled or VHE is in use. <<
754 <<
755 Work around the erratum by triggerin <<
756 when handling a system call from a t <<
757 in a VHE configuration of the kernel <<
758 117
759 If unsure, say Y. !! 118 config X86_CYCLONE_TIMER
>> 119 bool
>> 120 default y
>> 121 depends on X86_SUMMIT || X86_GENERICARCH
760 122
761 config ARM64_ERRATUM_1542419 !! 123 config ES7000_CLUSTERED_APIC
762 bool "Neoverse-N1: workaround mis-orde !! 124 bool
763 help <<
764 This option adds a workaround for AR <<
765 1542419. <<
766 <<
767 Affected Neoverse-N1 cores could exe <<
768 modified by another CPU. The workaro <<
769 counterpart. <<
770 <<
771 Workaround the issue by hiding the D <<
772 forces user-space to perform cache m <<
773 <<
774 If unsure, say N. <<
775 <<
776 config ARM64_ERRATUM_1508412 <<
777 bool "Cortex-A77: 1508412: workaround <<
778 default y 125 default y
779 help !! 126 depends on SMP && X86_ES7000 && MPENTIUMIII
780 This option adds a workaround for Ar <<
781 127
782 Affected Cortex-A77 cores (r0p0, r1p !! 128 choice
783 of a store-exclusive or read of PAR_ !! 129 prompt "Processor family"
784 non-cacheable memory attributes. The !! 130 default M686
785 counterpart. <<
786 131
787 KVM guests must also have the workar !! 132 config M386
788 deadlock the system. !! 133 bool "386"
>> 134 ---help---
>> 135 This is the processor type of your CPU. This information is used for
>> 136 optimizing purposes. In order to compile a kernel that can run on
>> 137 all x86 CPU types (albeit not optimally fast), you can specify
>> 138 "386" here.
>> 139
>> 140 The kernel will not necessarily run on earlier architectures than
>> 141 the one you have chosen, e.g. a Pentium optimized kernel will run on
>> 142 a PPro, but not necessarily on a i486.
>> 143
>> 144 Here are the settings recommended for greatest speed:
>> 145 - "386" for the AMD/Cyrix/Intel 386DX/DXL/SL/SLC/SX, Cyrix/TI
>> 146 486DLC/DLC2, UMC 486SX-S and NexGen Nx586. Only "386" kernels
>> 147 will run on a 386 class machine.
>> 148 - "486" for the AMD/Cyrix/IBM/Intel 486DX/DX2/DX4 or
>> 149 SL/SLC/SLC2/SLC3/SX/SX2 and UMC U5D or U5S.
>> 150 - "586" for generic Pentium CPUs lacking the TSC
>> 151 (time stamp counter) register.
>> 152 - "Pentium-Classic" for the Intel Pentium.
>> 153 - "Pentium-MMX" for the Intel Pentium MMX.
>> 154 - "Pentium-Pro" for the Intel Pentium Pro.
>> 155 - "Pentium-II" for the Intel Pentium II or pre-Coppermine Celeron.
>> 156 - "Pentium-III" for the Intel Pentium III or Coppermine Celeron.
>> 157 - "Pentium-4" for the Intel Pentium 4 or P4-based Celeron.
>> 158 - "K6" for the AMD K6, K6-II and K6-III (aka K6-3D).
>> 159 - "Athlon" for the AMD K7 family (Athlon/Duron/Thunderbird).
>> 160 - "Crusoe" for the Transmeta Crusoe series.
>> 161 - "Winchip-C6" for original IDT Winchip.
>> 162 - "Winchip-2" for IDT Winchip 2.
>> 163 - "Winchip-2A" for IDT Winchips with 3dNow! capabilities.
>> 164 - "CyrixIII/VIA C3" for VIA Cyrix III or VIA C3.
>> 165 - "VIA C3-2 for VIA C3-2 "Nehemiah" (model 9 and above).
>> 166
>> 167 If you don't know what to do, choose "386".
>> 168
>> 169 config M486
>> 170 bool "486"
>> 171 help
>> 172 Select this for a 486 series processor, either Intel or one of the
>> 173 compatible processors from AMD, Cyrix, IBM, or Intel. Includes DX,
>> 174 DX2, and DX4 variants; also SL/SLC/SLC2/SLC3/SX/SX2 and UMC U5D or
>> 175 U5S.
>> 176
>> 177 config M586
>> 178 bool "586/K5/5x86/6x86/6x86MX"
>> 179 help
>> 180 Select this for an 586 or 686 series processor such as the AMD K5,
>> 181 the Intel 5x86 or 6x86, or the Intel 6x86MX. This choice does not
>> 182 assume the RDTSC (Read Time Stamp Counter) instruction.
>> 183
>> 184 config M586TSC
>> 185 bool "Pentium-Classic"
>> 186 help
>> 187 Select this for a Pentium Classic processor with the RDTSC (Read
>> 188 Time Stamp Counter) instruction for benchmarking.
>> 189
>> 190 config M586MMX
>> 191 bool "Pentium-MMX"
>> 192 help
>> 193 Select this for a Pentium with the MMX graphics/multimedia
>> 194 extended instructions.
>> 195
>> 196 config M686
>> 197 bool "Pentium-Pro"
>> 198 help
>> 199 Select this for Intel Pentium Pro chips. This enables the use of
>> 200 Pentium Pro extended instructions, and disables the init-time guard
>> 201 against the f00f bug found in earlier Pentiums.
>> 202
>> 203 config MPENTIUMII
>> 204 bool "Pentium-II/Celeron(pre-Coppermine)"
>> 205 help
>> 206 Select this for Intel chips based on the Pentium-II and
>> 207 pre-Coppermine Celeron core. This option enables an unaligned
>> 208 copy optimization, compiles the kernel with optimization flags
>> 209 tailored for the chip, and applies any applicable Pentium Pro
>> 210 optimizations.
>> 211
>> 212 config MPENTIUMIII
>> 213 bool "Pentium-III/Celeron(Coppermine)/Pentium-III Xeon"
>> 214 help
>> 215 Select this for Intel chips based on the Pentium-III and
>> 216 Celeron-Coppermine core. This option enables use of some
>> 217 extended prefetch instructions in addition to the Pentium II
>> 218 extensions.
>> 219
>> 220 config MPENTIUM4
>> 221 bool "Pentium-4/Celeron(P4-based)/Xeon"
>> 222 help
>> 223 Select this for Intel Pentium 4 chips. This includes both
>> 224 the Pentium 4 and P4-based Celeron chips. This option
>> 225 enables compile flags optimized for the chip, uses the
>> 226 correct cache shift, and applies any applicable Pentium III
>> 227 optimizations.
>> 228
>> 229 config MK6
>> 230 bool "K6/K6-II/K6-III"
>> 231 help
>> 232 Select this for an AMD K6-family processor. Enables use of
>> 233 some extended instructions, and passes appropriate optimization
>> 234 flags to GCC.
>> 235
>> 236 config MK7
>> 237 bool "Athlon/Duron/K7"
>> 238 help
>> 239 Select this for an AMD Athlon K7-family processor. Enables use of
>> 240 some extended instructions, and passes appropriate optimization
>> 241 flags to GCC.
>> 242
>> 243 config MK8
>> 244 bool "Opteron/Athlon64/Hammer/K8"
>> 245 help
>> 246 Select this for an AMD Opteron or Athlon64 Hammer-family processor. Enables
>> 247 use of some extended instructions, and passes appropriate optimization
>> 248 flags to GCC.
>> 249
>> 250 config MELAN
>> 251 bool "Elan"
>> 252
>> 253 config MCRUSOE
>> 254 bool "Crusoe"
>> 255 help
>> 256 Select this for a Transmeta Crusoe processor. Treats the processor
>> 257 like a 586 with TSC, and sets some GCC optimization flags (like a
>> 258 Pentium Pro with no alignment requirements).
>> 259
>> 260 config MWINCHIPC6
>> 261 bool "Winchip-C6"
>> 262 help
>> 263 Select this for an IDT Winchip C6 chip. Linux and GCC
>> 264 treat this chip as a 586TSC with some extended instructions
>> 265 and alignment requirements.
>> 266
>> 267 config MWINCHIP2
>> 268 bool "Winchip-2"
>> 269 help
>> 270 Select this for an IDT Winchip-2. Linux and GCC
>> 271 treat this chip as a 586TSC with some extended instructions
>> 272 and alignment requirements.
>> 273
>> 274 config MWINCHIP3D
>> 275 bool "Winchip-2A/Winchip-3"
>> 276 help
>> 277 Select this for an IDT Winchip-2A or 3. Linux and GCC
>> 278 treat this chip as a 586TSC with some extended instructions
>> 279 and alignment reqirements. Also enable out of order memory
>> 280 stores for this CPU, which can increase performance of some
>> 281 operations.
>> 282
>> 283 config MCYRIXIII
>> 284 bool "CyrixIII/VIA-C3"
>> 285 help
>> 286 Select this for a Cyrix III or C3 chip. Presently Linux and GCC
>> 287 treat this chip as a generic 586. Whilst the CPU is 686 class,
>> 288 it lacks the cmov extension which gcc assumes is present when
>> 289 generating 686 code.
>> 290 Note that Nehemiah (Model 9) and above will not boot with this
>> 291 kernel due to them lacking the 3DNow! instructions used in earlier
>> 292 incarnations of the CPU.
>> 293
>> 294 config MVIAC3_2
>> 295 bool "VIA C3-2 (Nehemiah)"
>> 296 help
>> 297 Select this for a VIA C3 "Nehemiah". Selecting this enables usage
>> 298 of SSE and tells gcc to treat the CPU as a 686.
>> 299 Note, this kernel will not boot on older (pre model 9) C3s.
789 300
790 Work around the issue by inserting D !! 301 endchoice
791 register reads and warning KVM users <<
792 to prevent a speculative PAR_EL1 rea <<
793 302
794 If unsure, say Y. !! 303 config X86_GENERIC
>> 304 bool "Generic x86 support"
>> 305 help
>> 306 Including some tuning for non selected x86 CPUs too.
>> 307 when it has moderate overhead. This is intended for generic
>> 308 distributions kernels.
795 309
796 config ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MO !! 310 #
>> 311 # Define implied options from the CPU selection here
>> 312 #
>> 313 config X86_CMPXCHG
797 bool 314 bool
798 !! 315 depends on !M386
799 config ARM64_ERRATUM_2051678 <<
800 bool "Cortex-A510: 2051678: disable Ha <<
801 default y 316 default y
802 help <<
803 This options adds the workaround for <<
804 Affected Cortex-A510 might not respe <<
805 hardware update of the page table's <<
806 is to not enable the feature on affe <<
807 <<
808 If unsure, say Y. <<
809 317
810 config ARM64_ERRATUM_2077057 !! 318 config X86_XADD
811 bool "Cortex-A510: 2077057: workaround !! 319 bool
>> 320 depends on !M386
812 default y 321 default y
813 help <<
814 This option adds the workaround for <<
815 Affected Cortex-A510 may corrupt SPS <<
816 expected, but a Pointer Authenticati <<
817 erratum causes SPSR_EL1 to be copied <<
818 EL1 to cause a return to EL2 with a <<
819 <<
820 This can only happen when EL2 is ste <<
821 <<
822 When these conditions occur, the SPS <<
823 previous guest entry, and can be res <<
824 322
825 If unsure, say Y. !! 323 config X86_L1_CACHE_SHIFT
>> 324 int
>> 325 default "7" if MPENTIUM4 || X86_GENERIC
>> 326 default "4" if MELAN || M486 || M386
>> 327 default "5" if MWINCHIP3D || MWINCHIP2 || MWINCHIPC6 || MCRUSOE || MCYRIXIII || MK6 || MPENTIUMIII || MPENTIUMII || M686 || M586MMX || M586TSC || M586 || MVIAC3_2
>> 328 default "6" if MK7 || MK8
826 329
827 config ARM64_ERRATUM_2658417 !! 330 config RWSEM_GENERIC_SPINLOCK
828 bool "Cortex-A510: 2658417: remove BF1 !! 331 bool
>> 332 depends on M386
829 default y 333 default y
830 help <<
831 This option adds the workaround for <<
832 Affected Cortex-A510 (r0p0 to r1p1) <<
833 BFMMLA or VMMLA instructions in rare <<
834 A510 CPUs are using shared neon hard <<
835 discoverable by the kernel, hide the <<
836 user-space should not be using these <<
837 334
838 If unsure, say Y. !! 335 config RWSEM_XCHGADD_ALGORITHM
839 !! 336 bool
840 config ARM64_ERRATUM_2119858 !! 337 depends on !M386
841 bool "Cortex-A710/X2: 2119858: workaro <<
842 default y 338 default y
843 depends on CORESIGHT_TRBE <<
844 select ARM64_WORKAROUND_TRBE_OVERWRITE <<
845 help <<
846 This option adds the workaround for <<
847 <<
848 Affected Cortex-A710/X2 cores could <<
849 data at the base of the buffer (poin <<
850 the event of a WRAP event. <<
851 339
852 Work around the issue by always maki !! 340 config X86_PPRO_FENCE
853 256 bytes before enabling the buffer !! 341 bool
854 the buffer with ETM ignore packets u !! 342 depends on M686 || M586MMX || M586TSC || M586 || M486 || M386
855 <<
856 If unsure, say Y. <<
857 <<
858 config ARM64_ERRATUM_2139208 <<
859 bool "Neoverse-N2: 2139208: workaround <<
860 default y 343 default y
861 depends on CORESIGHT_TRBE <<
862 select ARM64_WORKAROUND_TRBE_OVERWRITE <<
863 help <<
864 This option adds the workaround for <<
865 344
866 Affected Neoverse-N2 cores could ove !! 345 config X86_F00F_BUG
867 data at the base of the buffer (poin <<
868 the event of a WRAP event. <<
869 <<
870 Work around the issue by always maki <<
871 256 bytes before enabling the buffer <<
872 the buffer with ETM ignore packets u <<
873 <<
874 If unsure, say Y. <<
875 <<
876 config ARM64_WORKAROUND_TSB_FLUSH_FAILURE <<
877 bool 346 bool
878 !! 347 depends on M586MMX || M586TSC || M586 || M486 || M386
879 config ARM64_ERRATUM_2054223 <<
880 bool "Cortex-A710: 2054223: workaround <<
881 default y 348 default y
882 select ARM64_WORKAROUND_TSB_FLUSH_FAIL <<
883 help <<
884 Enable workaround for ARM Cortex-A71 <<
885 <<
886 Affected cores may fail to flush the <<
887 the PE is in trace prohibited state. <<
888 of the trace cached. <<
889 <<
890 Workaround is to issue two TSB conse <<
891 349
892 If unsure, say Y. !! 350 config X86_WP_WORKS_OK
893 !! 351 bool
894 config ARM64_ERRATUM_2067961 !! 352 depends on !M386
895 bool "Neoverse-N2: 2067961: workaround <<
896 default y 353 default y
897 select ARM64_WORKAROUND_TSB_FLUSH_FAIL <<
898 help <<
899 Enable workaround for ARM Neoverse-N <<
900 <<
901 Affected cores may fail to flush the <<
902 the PE is in trace prohibited state. <<
903 of the trace cached. <<
904 354
905 Workaround is to issue two TSB conse !! 355 config X86_INVLPG
906 <<
907 If unsure, say Y. <<
908 <<
909 config ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANG <<
910 bool 356 bool
911 !! 357 depends on !M386
912 config ARM64_ERRATUM_2253138 <<
913 bool "Neoverse-N2: 2253138: workaround <<
914 depends on CORESIGHT_TRBE <<
915 default y 358 default y
916 select ARM64_WORKAROUND_TRBE_WRITE_OUT <<
917 help <<
918 This option adds the workaround for <<
919 359
920 Affected Neoverse-N2 cores might wri !! 360 config X86_BSWAP
921 for TRBE. Under some conditions, the !! 361 bool
922 virtually addressed page following t !! 362 depends on !M386
923 (i.e., the TRBLIMITR_EL1.LIMIT), ins <<
924 <<
925 Work around this in the driver by al <<
926 page beyond the TRBLIMITR_EL1.LIMIT, <<
927 <<
928 If unsure, say Y. <<
929 <<
930 config ARM64_ERRATUM_2224489 <<
931 bool "Cortex-A710/X2: 2224489: workaro <<
932 depends on CORESIGHT_TRBE <<
933 default y 363 default y
934 select ARM64_WORKAROUND_TRBE_WRITE_OUT <<
935 help <<
936 This option adds the workaround for <<
937 <<
938 Affected Cortex-A710/X2 cores might <<
939 for TRBE. Under some conditions, the <<
940 virtually addressed page following t <<
941 (i.e., the TRBLIMITR_EL1.LIMIT), ins <<
942 <<
943 Work around this in the driver by al <<
944 page beyond the TRBLIMITR_EL1.LIMIT, <<
945 364
946 If unsure, say Y. !! 365 config X86_POPAD_OK
947 !! 366 bool
948 config ARM64_ERRATUM_2441009 !! 367 depends on !M386
949 bool "Cortex-A510: Completion of affec <<
950 select ARM64_WORKAROUND_REPEAT_TLBI <<
951 help <<
952 This option adds a workaround for AR <<
953 <<
954 Under very rare circumstances, affec <<
955 may not handle a race between a brea <<
956 CPU, and another CPU accessing the s <<
957 store to a page that has been unmapp <<
958 <<
959 Work around this by adding the affec <<
960 TLB sequences to be done twice. <<
961 <<
962 If unsure, say N. <<
963 <<
964 config ARM64_ERRATUM_2064142 <<
965 bool "Cortex-A510: 2064142: workaround <<
966 depends on CORESIGHT_TRBE <<
967 default y 368 default y
968 help <<
969 This option adds the workaround for <<
970 369
971 Affected Cortex-A510 core might fail !! 370 config X86_ALIGNMENT_16
972 TRBE has been disabled. Under some c !! 371 bool
973 writes into TRBE registers TRBLIMITR !! 372 depends on MWINCHIP3D || MWINCHIP2 || MWINCHIPC6 || MCYRIXIII || MELAN || MK6 || M586MMX || M586TSC || M586 || M486 || MVIAC3_2
974 and TRBTRG_EL1 will be ignored and w <<
975 <<
976 Work around this in the driver by ex <<
977 is stopped and before performing a s <<
978 registers. <<
979 <<
980 If unsure, say Y. <<
981 <<
982 config ARM64_ERRATUM_2038923 <<
983 bool "Cortex-A510: 2038923: workaround <<
984 depends on CORESIGHT_TRBE <<
985 default y 373 default y
986 help <<
987 This option adds the workaround for <<
988 <<
989 Affected Cortex-A510 core might caus <<
990 prohibited within the CPU. As a resu <<
991 might be corrupted. This happens aft <<
992 TRBLIMITR_EL1.E, followed by just a <<
993 execution changes from a context, in <<
994 isn't, or vice versa. In these menti <<
995 is prohibited is inconsistent betwee <<
996 the trace buffer state might be corr <<
997 <<
998 Work around this in the driver by pr <<
999 trace is prohibited or not based on <<
1000 change to TRBLIMITR_EL1.E with at l <<
1001 two ISB instructions if no ERET is <<
1002 374
1003 If unsure, say Y. !! 375 config X86_GOOD_APIC
1004 !! 376 bool
1005 config ARM64_ERRATUM_1902691 !! 377 depends on MK7 || MPENTIUM4 || MPENTIUMIII || MPENTIUMII || M686 || M586MMX || MK8
1006 bool "Cortex-A510: 1902691: workaroun <<
1007 depends on CORESIGHT_TRBE <<
1008 default y 378 default y
1009 help <<
1010 This option adds the workaround for <<
1011 <<
1012 Affected Cortex-A510 core might cau <<
1013 into the memory. Effectively TRBE i <<
1014 trace data. <<
1015 379
1016 Work around this problem in the dri !! 380 config X86_INTEL_USERCOPY
1017 affected cpus. The firmware must ha !! 381 bool
1018 on such implementations. This will !! 382 depends on MPENTIUM4 || MPENTIUMIII || MPENTIUMII || M586MMX || X86_GENERIC || MK8 || MK7
1019 do this already. <<
1020 <<
1021 If unsure, say Y. <<
1022 <<
1023 config ARM64_ERRATUM_2457168 <<
1024 bool "Cortex-A510: 2457168: workaroun <<
1025 depends on ARM64_AMU_EXTN <<
1026 default y 383 default y
1027 help <<
1028 This option adds the workaround for <<
1029 <<
1030 The AMU counter AMEVCNTR01 (constan <<
1031 as the system counter. On affected <<
1032 incorrectly giving a significantly <<
1033 <<
1034 Work around this problem by returni <<
1035 key locations that results in disab <<
1036 is the same to firmware disabling a <<
1037 <<
1038 If unsure, say Y. <<
1039 384
1040 config ARM64_ERRATUM_2645198 !! 385 config X86_USE_PPRO_CHECKSUM
1041 bool "Cortex-A715: 2645198: Workaroun !! 386 bool
>> 387 depends on MWINCHIP3D || MWINCHIP2 || MWINCHIPC6 || MCYRIXIII || MK7 || MK6 || MPENTIUM4 || MPENTIUMIII || MPENTIUMII || M686 || MK8 || MVIAC3_2
1042 default y 388 default y
1043 help <<
1044 This option adds the workaround for <<
1045 <<
1046 If a Cortex-A715 cpu sees a page ma <<
1047 to non-executable, it may corrupt t <<
1048 next instruction abort caused by pe <<
1049 389
1050 Only user-space does executable to !! 390 config X86_USE_3DNOW
1051 mprotect() system call. Workaround <<
1052 TLB invalidation, for all changes t <<
1053 <<
1054 If unsure, say Y. <<
1055 <<
1056 config ARM64_WORKAROUND_SPECULATIVE_UNPRIV_LO <<
1057 bool 391 bool
1058 !! 392 depends on MCYRIXIII || MK7
1059 config ARM64_ERRATUM_2966298 <<
1060 bool "Cortex-A520: 2966298: workaroun <<
1061 select ARM64_WORKAROUND_SPECULATIVE_U <<
1062 default y 393 default y
1063 help <<
1064 This option adds the workaround for <<
1065 394
1066 On an affected Cortex-A520 core, a !! 395 config X86_OOSTORE
1067 load might leak data from a privile !! 396 bool
1068 !! 397 depends on MWINCHIP3D || MWINCHIP2 || MWINCHIPC6
1069 Work around this problem by executi <<
1070 <<
1071 If unsure, say Y. <<
1072 <<
1073 config ARM64_ERRATUM_3117295 <<
1074 bool "Cortex-A510: 3117295: workaroun <<
1075 select ARM64_WORKAROUND_SPECULATIVE_U <<
1076 default y 398 default y
1077 help <<
1078 This option adds the workaround for <<
1079 <<
1080 On an affected Cortex-A510 core, a <<
1081 load might leak data from a privile <<
1082 <<
1083 Work around this problem by executi <<
1084 <<
1085 If unsure, say Y. <<
1086 399
1087 config ARM64_ERRATUM_3194386 !! 400 config HPET_TIMER
1088 bool "Cortex-*/Neoverse-*: workaround !! 401 bool "HPET Timer Support"
1089 default y <<
1090 help 402 help
1091 This option adds the workaround for !! 403 This enables the use of the HPET for the kernel's internal timer.
1092 !! 404 HPET is the next generation timer replacing legacy 8254s.
1093 * ARM Cortex-A76 erratum 3324349 !! 405 You can safely choose Y here. However, HPET will only be
1094 * ARM Cortex-A77 erratum 3324348 !! 406 activated if the platform and the BIOS support this feature.
1095 * ARM Cortex-A78 erratum 3324344 !! 407 Otherwise the 8254 will be used for timing services.
1096 * ARM Cortex-A78C erratum 3324346 <<
1097 * ARM Cortex-A78C erratum 3324347 <<
1098 * ARM Cortex-A710 erratam 3324338 <<
1099 * ARM Cortex-A715 errartum 3456084 <<
1100 * ARM Cortex-A720 erratum 3456091 <<
1101 * ARM Cortex-A725 erratum 3456106 <<
1102 * ARM Cortex-X1 erratum 3324344 <<
1103 * ARM Cortex-X1C erratum 3324346 <<
1104 * ARM Cortex-X2 erratum 3324338 <<
1105 * ARM Cortex-X3 erratum 3324335 <<
1106 * ARM Cortex-X4 erratum 3194386 <<
1107 * ARM Cortex-X925 erratum 3324334 <<
1108 * ARM Neoverse-N1 erratum 3324349 <<
1109 * ARM Neoverse N2 erratum 3324339 <<
1110 * ARM Neoverse-N3 erratum 3456111 <<
1111 * ARM Neoverse-V1 erratum 3324341 <<
1112 * ARM Neoverse V2 erratum 3324336 <<
1113 * ARM Neoverse-V3 erratum 3312417 <<
1114 <<
1115 On affected cores "MSR SSBS, #0" in <<
1116 subsequent speculative instructions <<
1117 speculative store bypassing. <<
1118 408
1119 Work around this problem by placing !! 409 Choose N to continue using the legacy 8254 timer.
1120 Instruction Synchronization Barrier <<
1121 SSBS. The presence of the SSBS spec <<
1122 from hwcaps and EL0 reads of ID_AA6 <<
1123 will use the PR_SPEC_STORE_BYPASS p <<
1124 410
1125 If unsure, say Y. !! 411 config HPET_EMULATE_RTC
>> 412 def_bool HPET_TIMER && RTC=y
1126 413
1127 config CAVIUM_ERRATUM_22375 !! 414 config SMP
1128 bool "Cavium erratum 22375, 24313" !! 415 bool "Symmetric multi-processing support"
1129 default y !! 416 ---help---
1130 help !! 417 This enables support for systems with more than one CPU. If you have
1131 Enable workaround for errata 22375 !! 418 a system with only one CPU, like most personal computers, say N. If
1132 !! 419 you have a system with more than one CPU, say Y.
1133 This implements two gicv3-its errat !! 420
1134 with a small impact affecting only !! 421 If you say N here, the kernel will run on single and multiprocessor
>> 422 machines, but will use only one CPU of a multiprocessor machine. If
>> 423 you say Y here, the kernel will run on many, but not all,
>> 424 singleprocessor machines. On a singleprocessor machine, the kernel
>> 425 will run faster if you say N here.
>> 426
>> 427 Note that if you say Y here and choose architecture "586" or
>> 428 "Pentium" under "Processor family", the kernel will not work on 486
>> 429 architectures. Similarly, multiprocessor kernels for the "PPro"
>> 430 architecture may not work on all Pentium based boards.
>> 431
>> 432 People using multiprocessor machines who say Y here should also say
>> 433 Y to "Enhanced Real Time Clock Support", below. The "Advanced Power
>> 434 Management" code will be disabled if you say Y here.
>> 435
>> 436 See also the <file:Documentation/smp.tex>,
>> 437 <file:Documentation/smp.txt>, <file:Documentation/i386/IO-APIC.txt>,
>> 438 <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
>> 439 <http://www.tldp.org/docs.html#howto>.
1135 440
1136 erratum 22375: only alloc 8MB tab !! 441 If you don't know what to do here, say N.
1137 erratum 24313: ignore memory acce <<
1138 442
1139 The fixes are in ITS initialization !! 443 config NR_CPUS
1140 type and table size provided by the !! 444 int "Maximum number of CPUs (2-255)"
>> 445 depends on SMP
>> 446 default "32" if X86_NUMAQ || X86_SUMMIT || X86_BIGSMP || X86_ES7000
>> 447 default "8"
>> 448 help
>> 449 This allows you to specify the maximum number of CPUs which this
>> 450 kernel will support. The maximum supported value is 255 and the
>> 451 minimum value which makes sense is 2.
>> 452
>> 453 This is purely to save memory - each supported CPU adds
>> 454 approximately eight kilobytes to the kernel image.
>> 455
>> 456 config PREEMPT
>> 457 bool "Preemptible Kernel"
>> 458 help
>> 459 This option reduces the latency of the kernel when reacting to
>> 460 real-time or interactive events by allowing a low priority process to
>> 461 be preempted even if it is in kernel mode executing a system call.
>> 462 This allows applications to run more reliably even when the system is
>> 463 under load.
>> 464
>> 465 Say Y here if you are building a kernel for a desktop, embedded
>> 466 or real-time system. Say N if you are unsure.
>> 467
>> 468 config X86_UP_APIC
>> 469 bool "Local APIC support on uniprocessors" if !SMP
>> 470 depends on !(X86_VISWS || X86_VOYAGER)
>> 471 ---help---
>> 472 A local APIC (Advanced Programmable Interrupt Controller) is an
>> 473 integrated interrupt controller in the CPU. If you have a single-CPU
>> 474 system which has a processor with a local APIC, you can say Y here to
>> 475 enable and use it. If you say Y here even though your machine doesn't
>> 476 have a local APIC, then the kernel will still run with no slowdown at
>> 477 all. The local APIC supports CPU-generated self-interrupts (timer,
>> 478 performance counters), and the NMI watchdog which detects hard
>> 479 lockups.
>> 480
>> 481 If you have a system with several CPUs, you do not need to say Y
>> 482 here: the local APIC will be used automatically.
>> 483
>> 484 config X86_UP_IOAPIC
>> 485 bool "IO-APIC support on uniprocessors"
>> 486 depends on !SMP && X86_UP_APIC
>> 487 help
>> 488 An IO-APIC (I/O Advanced Programmable Interrupt Controller) is an
>> 489 SMP-capable replacement for PC-style interrupt controllers. Most
>> 490 SMP systems and a small number of uniprocessor systems have one.
>> 491 If you have a single-CPU system with an IO-APIC, you can say Y here
>> 492 to use it. If you say Y here even though your machine doesn't have
>> 493 an IO-APIC, then the kernel will still run with no slowdown at all.
1141 494
1142 If unsure, say Y. !! 495 If you have a system with several CPUs, you do not need to say Y
>> 496 here: the IO-APIC will be used automatically.
1143 497
1144 config CAVIUM_ERRATUM_23144 !! 498 config X86_LOCAL_APIC
1145 bool "Cavium erratum 23144: ITS SYNC !! 499 bool
1146 depends on NUMA !! 500 depends on !SMP && X86_UP_APIC
1147 default y 501 default y
1148 help <<
1149 ITS SYNC command hang for cross nod <<
1150 <<
1151 If unsure, say Y. <<
1152 502
1153 config CAVIUM_ERRATUM_23154 !! 503 config X86_IO_APIC
1154 bool "Cavium errata 23154 and 38545: !! 504 bool
>> 505 depends on !SMP && X86_UP_IOAPIC
1155 default y 506 default y
1156 help <<
1157 The ThunderX GICv3 implementation r <<
1158 reading the IAR status to ensure da <<
1159 (access to icc_iar1_el1 is not sync <<
1160 507
1161 It also suffers from erratum 38545 !! 508 config X86_TSC
1162 OcteonTX and OcteonTX2), resulting !! 509 bool
1163 spuriously presented to the CPU int !! 510 depends on (MWINCHIP3D || MWINCHIP2 || MCRUSOE || MCYRIXIII || MK7 || MK6 || MPENTIUM4 || MPENTIUMIII || MPENTIUMII || M686 || M586MMX || M586TSC || MK8 || MVIAC3_2) && !X86_NUMAQ
1164 <<
1165 If unsure, say Y. <<
1166 <<
1167 config CAVIUM_ERRATUM_27456 <<
1168 bool "Cavium erratum 27456: Broadcast <<
1169 default y 511 default y
1170 help <<
1171 On ThunderX T88 pass 1.x through 2. <<
1172 instructions may cause the icache t <<
1173 contains data for a non-current ASI <<
1174 invalidate the icache when changing <<
1175 512
1176 If unsure, say Y. !! 513 config X86_MCE
>> 514 bool "Machine Check Exception"
>> 515 ---help---
>> 516 Machine Check Exception support allows the processor to notify the
>> 517 kernel if it detects a problem (e.g. overheating, component failure).
>> 518 The action the kernel takes depends on the severity of the problem,
>> 519 ranging from a warning message on the console, to halting the machine.
>> 520 Your processor must be a Pentium or newer to support this - check the
>> 521 flags in /proc/cpuinfo for mce. Note that some older Pentium systems
>> 522 have a design flaw which leads to false MCE events - hence MCE is
>> 523 disabled on all P5 processors, unless explicitly enabled with "mce"
>> 524 as a boot argument. Similarly, if MCE is built in and creates a
>> 525 problem on some new non-standard machine, you can boot with "nomce"
>> 526 to disable it. MCE support simply ignores non-MCE processors like
>> 527 the 386 and 486, so nearly everyone can say Y here.
>> 528
>> 529 config X86_MCE_NONFATAL
>> 530 bool "Check for non-fatal errors on AMD Athlon/Duron / Intel Pentium 4"
>> 531 depends on X86_MCE
>> 532 help
>> 533 Enabling this feature starts a timer that triggers every 5 seconds which
>> 534 will look at the machine check registers to see if anything happened.
>> 535 Non-fatal problems automatically get corrected (but still logged).
>> 536 Disable this if you don't want to see these messages.
>> 537 Seeing the messages this option prints out may be indicative of dying hardware,
>> 538 or out-of-spec (ie, overclocked) hardware.
>> 539 This option only does something on certain CPUs.
>> 540 (AMD Athlon/Duron and Intel Pentium 4)
>> 541
>> 542 config X86_MCE_P4THERMAL
>> 543 bool "check for P4 thermal throttling interrupt."
>> 544 depends on X86_MCE && (X86_UP_APIC || SMP)
>> 545 help
>> 546 Enabling this feature will cause a message to be printed when the P4
>> 547 enters thermal throttling.
>> 548
>> 549 config TOSHIBA
>> 550 tristate "Toshiba Laptop support"
>> 551 ---help---
>> 552 This adds a driver to safely access the System Management Mode of
>> 553 the CPU on Toshiba portables with a genuine Toshiba BIOS. It does
>> 554 not work on models with a Phoenix BIOS. The System Management Mode
>> 555 is used to set the BIOS and power saving options on Toshiba portables.
>> 556
>> 557 For information on utilities to make use of this driver see the
>> 558 Toshiba Linux utilities web site at:
>> 559 <http://www.buzzard.org.uk/toshiba/>.
>> 560
>> 561 Say Y if you intend to run this kernel on a Toshiba portable.
>> 562 Say N otherwise.
>> 563
>> 564 config I8K
>> 565 tristate "Dell laptop support"
>> 566 ---help---
>> 567 This adds a driver to safely access the System Management Mode
>> 568 of the CPU on the Dell Inspiron 8000. The System Management Mode
>> 569 is used to read cpu temperature and cooling fan status and to
>> 570 control the fans on the I8K portables.
>> 571
>> 572 This driver has been tested only on the Inspiron 8000 but it may
>> 573 also work with other Dell laptops. You can force loading on other
>> 574 models by passing the parameter `force=1' to the module. Use at
>> 575 your own risk.
>> 576
>> 577 For information on utilities to make use of this driver see the
>> 578 I8K Linux utilities web site at:
>> 579 <http://www.debian.org/~dz/i8k/>
>> 580
>> 581 Say Y if you intend to run this kernel on a Dell Inspiron 8000.
>> 582 Say N otherwise.
>> 583
>> 584 config MICROCODE
>> 585 tristate "/dev/cpu/microcode - Intel IA32 CPU microcode support"
>> 586 ---help---
>> 587 If you say Y here and also to "/dev file system support" in the
>> 588 'File systems' section, you will be able to update the microcode on
>> 589 Intel processors in the IA32 family, e.g. Pentium Pro, Pentium II,
>> 590 Pentium III, Pentium 4, Xeon etc. You will obviously need the
>> 591 actual microcode binary data itself which is not shipped with the
>> 592 Linux kernel.
>> 593
>> 594 For latest news and information on obtaining all the required
>> 595 ingredients for this driver, check:
>> 596 <http://www.urbanmyth.org/microcode/>.
>> 597
>> 598 To compile this driver as a module, choose M here: the
>> 599 module will be called microcode.
>> 600 If you use modprobe or kmod you may also want to add the line
>> 601 'alias char-major-10-184 microcode' to your /etc/modules.conf file.
>> 602
>> 603 config X86_MSR
>> 604 tristate "/dev/cpu/*/msr - Model-specific register support"
>> 605 help
>> 606 This device gives privileged processes access to the x86
>> 607 Model-Specific Registers (MSRs). It is a character device with
>> 608 major 202 and minors 0 to 31 for /dev/cpu/0/msr to /dev/cpu/31/msr.
>> 609 MSR accesses are directed to a specific CPU on multi-processor
>> 610 systems.
>> 611
>> 612 config X86_CPUID
>> 613 tristate "/dev/cpu/*/cpuid - CPU information support"
>> 614 help
>> 615 This device gives processes access to the x86 CPUID instruction to
>> 616 be executed on a specific processor. It is a character device
>> 617 with major 203 and minors 0 to 31 for /dev/cpu/0/cpuid to
>> 618 /dev/cpu/31/cpuid.
>> 619
>> 620 config EDD
>> 621 tristate "BIOS Enhanced Disk Drive calls determine boot disk (EXPERIMENTAL)"
>> 622 depends on EXPERIMENTAL
>> 623 help
>> 624 Say Y or M here if you want to enable BIOS Enhanced Disk Drive
>> 625 Services real mode BIOS calls to determine which disk
>> 626 BIOS tries boot from. This information is then exported via driverfs.
1177 627
1178 config CAVIUM_ERRATUM_30115 !! 628 This option is experimental, but believed to be safe,
1179 bool "Cavium erratum 30115: Guest may !! 629 and most disk controller BIOS vendors do not yet implement this feature.
1180 default y <<
1181 help <<
1182 On ThunderX T88 pass 1.x through 2. <<
1183 1.2, and T83 Pass 1.0, KVM guest ex <<
1184 interrupts in host. Trapping both G <<
1185 accesses sidesteps the issue. <<
1186 630
1187 If unsure, say Y. !! 631 choice
>> 632 prompt "High Memory Support"
>> 633 default NOHIGHMEM
1188 634
1189 config CAVIUM_TX2_ERRATUM_219 !! 635 config NOHIGHMEM
1190 bool "Cavium ThunderX2 erratum 219: P !! 636 bool "off"
1191 default y !! 637 ---help---
>> 638 Linux can use up to 64 Gigabytes of physical memory on x86 systems.
>> 639 However, the address space of 32-bit x86 processors is only 4
>> 640 Gigabytes large. That means that, if you have a large amount of
>> 641 physical memory, not all of it can be "permanently mapped" by the
>> 642 kernel. The physical memory that's not permanently mapped is called
>> 643 "high memory".
>> 644
>> 645 If you are compiling a kernel which will never run on a machine with
>> 646 more than 1 Gigabyte total physical RAM, answer "off" here (default
>> 647 choice and suitable for most users). This will result in a "3GB/1GB"
>> 648 split: 3GB are mapped so that each process sees a 3GB virtual memory
>> 649 space and the remaining part of the 4GB virtual memory space is used
>> 650 by the kernel to permanently map as much physical memory as
>> 651 possible.
>> 652
>> 653 If the machine has between 1 and 4 Gigabytes physical RAM, then
>> 654 answer "4GB" here.
>> 655
>> 656 If more than 4 Gigabytes is used then answer "64GB" here. This
>> 657 selection turns Intel PAE (Physical Address Extension) mode on.
>> 658 PAE implements 3-level paging on IA32 processors. PAE is fully
>> 659 supported by Linux, PAE mode is implemented on all recent Intel
>> 660 processors (Pentium Pro and better). NOTE: If you say "64GB" here,
>> 661 then the kernel will not boot on CPUs that don't support PAE!
>> 662
>> 663 The actual amount of total physical memory will either be
>> 664 auto detected or can be forced by using a kernel command line option
>> 665 such as "mem=256M". (Try "man bootparam" or see the documentation of
>> 666 your boot loader (lilo or loadlin) about how to pass options to the
>> 667 kernel at boot time.)
>> 668
>> 669 If unsure, say "off".
>> 670
>> 671 config HIGHMEM4G
>> 672 bool "4GB"
1192 help 673 help
1193 On Cavium ThunderX2, a load, store !! 674 Select this if you have a 32-bit processor and between 1 and 4
1194 TTBR update and the corresponding c !! 675 gigabytes of physical RAM.
1195 cause a spurious Data Abort to be d <<
1196 the CPU core. <<
1197 <<
1198 Work around the issue by avoiding t <<
1199 trapping KVM guest TTBRx_EL1 writes <<
1200 trap handler performs the correspon <<
1201 instruction and ensures context syn <<
1202 exception return. <<
1203 676
1204 If unsure, say Y. !! 677 config HIGHMEM64G
1205 !! 678 bool "64GB"
1206 config FUJITSU_ERRATUM_010001 <<
1207 bool "Fujitsu-A64FX erratum E#010001: <<
1208 default y <<
1209 help 679 help
1210 This option adds a workaround for F !! 680 Select this if you have a 32-bit processor and more than 4
1211 On some variants of the Fujitsu-A64 !! 681 gigabytes of physical RAM.
1212 accesses may cause undefined fault <<
1213 This fault occurs under a specific <<
1214 load/store instruction performs an <<
1215 case-1 TTBR0_EL1 with TCR_EL1.NFD0 <<
1216 case-2 TTBR0_EL2 with TCR_EL2.NFD0 <<
1217 case-3 TTBR1_EL1 with TCR_EL1.NFD1 <<
1218 case-4 TTBR1_EL2 with TCR_EL2.NFD1 <<
1219 682
1220 The workaround is to ensure these b !! 683 endchoice
1221 The workaround only affects the Fuj <<
1222 <<
1223 If unsure, say Y. <<
1224 684
1225 config HISILICON_ERRATUM_161600802 !! 685 config HIGHMEM
1226 bool "Hip07 161600802: Erroneous redi !! 686 bool
>> 687 depends on HIGHMEM64G || HIGHMEM4G
1227 default y 688 default y
1228 help <<
1229 The HiSilicon Hip07 SoC uses the wr <<
1230 when issued ITS commands such as VM <<
1231 a 128kB offset to be applied to the <<
1232 689
1233 If unsure, say Y. !! 690 config X86_PAE
1234 !! 691 bool
1235 config QCOM_FALKOR_ERRATUM_1003 !! 692 depends on HIGHMEM64G
1236 bool "Falkor E1003: Incorrect transla <<
1237 default y 693 default y
1238 help <<
1239 On Falkor v1, an incorrect ASID may <<
1240 and BADDR are changed together in T <<
1241 in TTBR1_EL1, this situation only o <<
1242 then only for entries in the walk c <<
1243 is unchanged. Work around the errat <<
1244 entries for the trampoline before e <<
1245 694
1246 config QCOM_FALKOR_ERRATUM_1009 !! 695 # Common NUMA Features
1247 bool "Falkor E1009: Prematurely compl !! 696 config NUMA
1248 default y !! 697 bool "Numa Memory Allocation Support"
1249 select ARM64_WORKAROUND_REPEAT_TLBI !! 698 depends on SMP && HIGHMEM64G && (X86_PC || X86_NUMAQ || X86_GENERICARCH || (X86_SUMMIT && ACPI && !ACPI_HT_ONLY))
1250 help !! 699 default n if X86_PC
1251 On Falkor v1, the CPU may premature !! 700 default y if (X86_NUMAQ || X86_SUMMIT)
1252 TLBI xxIS invalidate maintenance op !! 701
1253 one more time to fix the issue. !! 702 # Need comments to help the hapless user trying to turn on NUMA support
>> 703 comment "NUMA (NUMA-Q) requires SMP, 64GB highmem support"
>> 704 depends on X86_NUMAQ && (!HIGHMEM64G || !SMP)
1254 705
1255 If unsure, say Y. !! 706 comment "NUMA (Summit) requires SMP, 64GB highmem support, full ACPI"
>> 707 depends on X86_SUMMIT && (!HIGHMEM64G || !ACPI || ACPI_HT_ONLY)
1256 708
1257 config QCOM_QDF2400_ERRATUM_0065 !! 709 config DISCONTIGMEM
1258 bool "QDF2400 E0065: Incorrect GITS_T !! 710 bool
>> 711 depends on NUMA
1259 default y 712 default y
1260 help <<
1261 On Qualcomm Datacenter Technologies <<
1262 ITE size incorrectly. The GITS_TYPE <<
1263 been indicated as 16Bytes (0xf), no <<
1264 713
1265 If unsure, say Y. !! 714 config HAVE_ARCH_BOOTMEM_NODE
1266 !! 715 bool
1267 config QCOM_FALKOR_ERRATUM_E1041 !! 716 depends on NUMA
1268 bool "Falkor E1041: Speculative instr <<
1269 default y 717 default y
1270 help <<
1271 Falkor CPU may speculatively fetch <<
1272 memory location when MMU translatio <<
1273 to SCTLR_ELn[M]=0. Prefix an ISB in <<
1274 718
1275 If unsure, say Y. !! 719 config HIGHPTE
>> 720 bool "Allocate 3rd-level pagetables from highmem"
>> 721 depends on HIGHMEM4G || HIGHMEM64G
>> 722 help
>> 723 The VM uses one page table entry for each page of physical memory.
>> 724 For systems with a lot of RAM, this can be wasteful of precious
>> 725 low memory. Setting this option will put user-space page table
>> 726 entries in high memory.
>> 727
>> 728 config MATH_EMULATION
>> 729 bool "Math emulation"
>> 730 ---help---
>> 731 Linux can emulate a math coprocessor (used for floating point
>> 732 operations) if you don't have one. 486DX and Pentium processors have
>> 733 a math coprocessor built in, 486SX and 386 do not, unless you added
>> 734 a 487DX or 387, respectively. (The messages during boot time can
>> 735 give you some hints here ["man dmesg"].) Everyone needs either a
>> 736 coprocessor or this emulation.
>> 737
>> 738 If you don't have a math coprocessor, you need to say Y here; if you
>> 739 say Y here even though you have a coprocessor, the coprocessor will
>> 740 be used nevertheless. (This behavior can be changed with the kernel
>> 741 command line option "no387", which comes handy if your coprocessor
>> 742 is broken. Try "man bootparam" or see the documentation of your boot
>> 743 loader (lilo or loadlin) about how to pass options to the kernel at
>> 744 boot time.) This means that it is a good idea to say Y here if you
>> 745 intend to use this kernel on different machines.
>> 746
>> 747 More information about the internals of the Linux math coprocessor
>> 748 emulation can be found in <file:arch/i386/math-emu/README>.
>> 749
>> 750 If you are not sure, say Y; apart from resulting in a 66 KB bigger
>> 751 kernel, it won't hurt.
>> 752
>> 753 config MTRR
>> 754 bool "MTRR (Memory Type Range Register) support"
>> 755 ---help---
>> 756 On Intel P6 family processors (Pentium Pro, Pentium II and later)
>> 757 the Memory Type Range Registers (MTRRs) may be used to control
>> 758 processor access to memory ranges. This is most useful if you have
>> 759 a video (VGA) card on a PCI or AGP bus. Enabling write-combining
>> 760 allows bus write transfers to be combined into a larger transfer
>> 761 before bursting over the PCI/AGP bus. This can increase performance
>> 762 of image write operations 2.5 times or more. Saying Y here creates a
>> 763 /proc/mtrr file which may be used to manipulate your processor's
>> 764 MTRRs. Typically the X server should use this.
>> 765
>> 766 This code has a reasonably generic interface so that similar
>> 767 control registers on other processors can be easily supported
>> 768 as well:
>> 769
>> 770 The Cyrix 6x86, 6x86MX and M II processors have Address Range
>> 771 Registers (ARRs) which provide a similar functionality to MTRRs. For
>> 772 these, the ARRs are used to emulate the MTRRs.
>> 773 The AMD K6-2 (stepping 8 and above) and K6-3 processors have two
>> 774 MTRRs. The Centaur C6 (WinChip) has 8 MCRs, allowing
>> 775 write-combining. All of these processors are supported by this code
>> 776 and it makes sense to say Y here if you have one of them.
>> 777
>> 778 Saying Y here also fixes a problem with buggy SMP BIOSes which only
>> 779 set the MTRRs for the boot CPU and not for the secondary CPUs. This
>> 780 can lead to all sorts of problems, so it's good to say Y here.
1276 781
1277 config NVIDIA_CARMEL_CNP_ERRATUM !! 782 You can safely say Y even if your machine doesn't have MTRRs, you'll
1278 bool "NVIDIA Carmel CNP: CNP on Carme !! 783 just add about 9 KB to your kernel.
1279 default y <<
1280 help <<
1281 If CNP is enabled on Carmel cores, <<
1282 invalidate shared TLB entries insta <<
1283 on standard ARM cores. <<
1284 784
1285 If unsure, say Y. !! 785 See <file:Documentation/mtrr.txt> for more information.
1286 786
1287 config ROCKCHIP_ERRATUM_3588001 !! 787 config HAVE_DEC_LOCK
1288 bool "Rockchip 3588001: GIC600 can no !! 788 bool
>> 789 depends on (SMP || PREEMPT) && X86_CMPXCHG
1289 default y 790 default y
1290 help <<
1291 The Rockchip RK3588 GIC600 SoC inte <<
1292 This means, that its sharability fe <<
1293 is supported by the IP itself. <<
1294 <<
1295 If unsure, say Y. <<
1296 791
1297 config SOCIONEXT_SYNQUACER_PREITS !! 792 # turning this on wastes a bunch of space.
1298 bool "Socionext Synquacer: Workaround !! 793 # Summit needs it only when NUMA is on
>> 794 config BOOT_IOREMAP
>> 795 bool
>> 796 depends on ((X86_SUMMIT || X86_GENERICARCH) && NUMA)
1299 default y 797 default y
1300 help <<
1301 Socionext Synquacer SoCs implement <<
1302 MSI doorbell writes with non-zero v <<
1303 <<
1304 If unsure, say Y. <<
1305 <<
1306 endmenu # "ARM errata workarounds via the alt <<
1307 <<
1308 choice <<
1309 prompt "Page size" <<
1310 default ARM64_4K_PAGES <<
1311 help <<
1312 Page size (translation granule) con <<
1313 <<
1314 config ARM64_4K_PAGES <<
1315 bool "4KB" <<
1316 select HAVE_PAGE_SIZE_4KB <<
1317 help <<
1318 This feature enables 4KB pages supp <<
1319 <<
1320 config ARM64_16K_PAGES <<
1321 bool "16KB" <<
1322 select HAVE_PAGE_SIZE_16KB <<
1323 help <<
1324 The system will use 16KB pages supp <<
1325 requires applications compiled with <<
1326 aligned segments. <<
1327 <<
1328 config ARM64_64K_PAGES <<
1329 bool "64KB" <<
1330 select HAVE_PAGE_SIZE_64KB <<
1331 help <<
1332 This feature enables 64KB pages sup <<
1333 allowing only two levels of page ta <<
1334 look-up. AArch32 emulation requires <<
1335 with 64K aligned segments. <<
1336 <<
1337 endchoice <<
1338 <<
1339 choice <<
1340 prompt "Virtual address space size" <<
1341 default ARM64_VA_BITS_52 <<
1342 help <<
1343 Allows choosing one of multiple pos <<
1344 space sizes. The level of translati <<
1345 a combination of page size and virt <<
1346 <<
1347 config ARM64_VA_BITS_36 <<
1348 bool "36-bit" if EXPERT <<
1349 depends on PAGE_SIZE_16KB <<
1350 <<
1351 config ARM64_VA_BITS_39 <<
1352 bool "39-bit" <<
1353 depends on PAGE_SIZE_4KB <<
1354 <<
1355 config ARM64_VA_BITS_42 <<
1356 bool "42-bit" <<
1357 depends on PAGE_SIZE_64KB <<
1358 <<
1359 config ARM64_VA_BITS_47 <<
1360 bool "47-bit" <<
1361 depends on PAGE_SIZE_16KB <<
1362 <<
1363 config ARM64_VA_BITS_48 <<
1364 bool "48-bit" <<
1365 <<
1366 config ARM64_VA_BITS_52 <<
1367 bool "52-bit" <<
1368 depends on ARM64_PAN || !ARM64_SW_TTB <<
1369 help <<
1370 Enable 52-bit virtual addressing fo <<
1371 requested via a hint to mmap(). The <<
1372 virtual addresses for its own mappi <<
1373 this feature is available, otherwis <<
1374 <<
1375 NOTE: Enabling 52-bit virtual addre <<
1376 ARMv8.3 Pointer Authentication will <<
1377 reduced from 7 bits to 3 bits, whic <<
1378 impact on its susceptibility to bru <<
1379 <<
1380 If unsure, select 48-bit virtual ad <<
1381 <<
1382 endchoice <<
1383 <<
1384 config ARM64_FORCE_52BIT <<
1385 bool "Force 52-bit virtual addresses <<
1386 depends on ARM64_VA_BITS_52 && EXPERT <<
1387 help <<
1388 For systems with 52-bit userspace V <<
1389 to maintain compatibility with olde <<
1390 unless a hint is supplied to mmap. <<
1391 <<
1392 This configuration option disables <<
1393 forces all userspace addresses to b <<
1394 should only enable this configurati <<
1395 memory management code. If unsure s <<
1396 <<
1397 config ARM64_VA_BITS <<
1398 int <<
1399 default 36 if ARM64_VA_BITS_36 <<
1400 default 39 if ARM64_VA_BITS_39 <<
1401 default 42 if ARM64_VA_BITS_42 <<
1402 default 47 if ARM64_VA_BITS_47 <<
1403 default 48 if ARM64_VA_BITS_48 <<
1404 default 52 if ARM64_VA_BITS_52 <<
1405 <<
1406 choice <<
1407 prompt "Physical address space size" <<
1408 default ARM64_PA_BITS_48 <<
1409 help <<
1410 Choose the maximum physical address <<
1411 support. <<
1412 <<
1413 config ARM64_PA_BITS_48 <<
1414 bool "48-bit" <<
1415 depends on ARM64_64K_PAGES || !ARM64_ <<
1416 <<
1417 config ARM64_PA_BITS_52 <<
1418 bool "52-bit" <<
1419 depends on ARM64_64K_PAGES || ARM64_V <<
1420 depends on ARM64_PAN || !ARM64_SW_TTB <<
1421 help <<
1422 Enable support for a 52-bit physica <<
1423 part of the ARMv8.2-LPA extension. <<
1424 <<
1425 With this enabled, the kernel will <<
1426 do not support ARMv8.2-LPA, but wit <<
1427 minor performance overhead). <<
1428 <<
1429 endchoice <<
1430 <<
1431 config ARM64_PA_BITS <<
1432 int <<
1433 default 48 if ARM64_PA_BITS_48 <<
1434 default 52 if ARM64_PA_BITS_52 <<
1435 <<
1436 config ARM64_LPA2 <<
1437 def_bool y <<
1438 depends on ARM64_PA_BITS_52 && !ARM64 <<
1439 <<
1440 choice <<
1441 prompt "Endianness" <<
1442 default CPU_LITTLE_ENDIAN <<
1443 help <<
1444 Select the endianness of data acces <<
1445 applications will need to be compil <<
1446 that is selected here. <<
1447 <<
1448 config CPU_BIG_ENDIAN <<
1449 bool "Build big-endian kernel" <<
1450 # https://github.com/llvm/llvm-projec <<
1451 depends on AS_IS_GNU || AS_VERSION >= <<
1452 help <<
1453 Say Y if you plan on running a kern <<
1454 <<
1455 config CPU_LITTLE_ENDIAN <<
1456 bool "Build little-endian kernel" <<
1457 help <<
1458 Say Y if you plan on running a kern <<
1459 This is usually the case for distri <<
1460 <<
1461 endchoice <<
1462 <<
1463 config SCHED_MC <<
1464 bool "Multi-core scheduler support" <<
1465 help <<
1466 Multi-core scheduler support improv <<
1467 making when dealing with multi-core <<
1468 increased overhead in some places. <<
1469 <<
1470 config SCHED_CLUSTER <<
1471 bool "Cluster scheduler support" <<
1472 help <<
1473 Cluster scheduler support improves <<
1474 making when dealing with machines t <<
1475 Cluster usually means a couple of C <<
1476 by sharing mid-level caches, last-l <<
1477 busses. <<
1478 <<
1479 config SCHED_SMT <<
1480 bool "SMT scheduler support" <<
1481 help <<
1482 Improves the CPU scheduler's decisi <<
1483 MultiThreading at a cost of slightl <<
1484 places. If unsure say N here. <<
1485 <<
1486 config NR_CPUS <<
1487 int "Maximum number of CPUs (2-4096)" <<
1488 range 2 4096 <<
1489 default "512" <<
1490 <<
1491 config HOTPLUG_CPU <<
1492 bool "Support for hot-pluggable CPUs" <<
1493 select GENERIC_IRQ_MIGRATION <<
1494 help <<
1495 Say Y here to experiment with turni <<
1496 can be controlled through /sys/devi <<
1497 <<
1498 # Common NUMA Features <<
1499 config NUMA <<
1500 bool "NUMA Memory Allocation and Sche <<
1501 select GENERIC_ARCH_NUMA <<
1502 select OF_NUMA <<
1503 select HAVE_SETUP_PER_CPU_AREA <<
1504 select NEED_PER_CPU_EMBED_FIRST_CHUNK <<
1505 select NEED_PER_CPU_PAGE_FIRST_CHUNK <<
1506 select USE_PERCPU_NUMA_NODE_ID <<
1507 help <<
1508 Enable NUMA (Non-Uniform Memory Acc <<
1509 <<
1510 The kernel will try to allocate mem <<
1511 local memory of the CPU and add som <<
1512 NUMA awareness to the kernel. <<
1513 <<
1514 config NODES_SHIFT <<
1515 int "Maximum NUMA Nodes (as a power o <<
1516 range 1 10 <<
1517 default "4" <<
1518 depends on NUMA <<
1519 help <<
1520 Specify the maximum number of NUMA <<
1521 system. Increases memory reserved <<
1522 <<
1523 source "kernel/Kconfig.hz" <<
1524 <<
1525 config ARCH_SPARSEMEM_ENABLE <<
1526 def_bool y <<
1527 select SPARSEMEM_VMEMMAP_ENABLE <<
1528 select SPARSEMEM_VMEMMAP <<
1529 <<
1530 config HW_PERF_EVENTS <<
1531 def_bool y <<
1532 depends on ARM_PMU <<
1533 <<
1534 # Supported by clang >= 7.0 or GCC >= 12.0.0 <<
1535 config CC_HAVE_SHADOW_CALL_STACK <<
1536 def_bool $(cc-option, -fsanitize=shad <<
1537 <<
1538 config PARAVIRT <<
1539 bool "Enable paravirtualization code" <<
1540 help <<
1541 This changes the kernel so it can m <<
1542 under a hypervisor, potentially imp <<
1543 over full virtualization. <<
1544 <<
1545 config PARAVIRT_TIME_ACCOUNTING <<
1546 bool "Paravirtual steal time accounti <<
1547 select PARAVIRT <<
1548 help <<
1549 Select this option to enable fine g <<
1550 accounting. Time spent executing ot <<
1551 the current vCPU is discounted from <<
1552 that, there can be a small performa <<
1553 <<
1554 If in doubt, say N here. <<
1555 <<
1556 config ARCH_SUPPORTS_KEXEC <<
1557 def_bool PM_SLEEP_SMP <<
1558 <<
1559 config ARCH_SUPPORTS_KEXEC_FILE <<
1560 def_bool y <<
1561 <<
1562 config ARCH_SELECTS_KEXEC_FILE <<
1563 def_bool y <<
1564 depends on KEXEC_FILE <<
1565 select HAVE_IMA_KEXEC if IMA <<
1566 <<
1567 config ARCH_SUPPORTS_KEXEC_SIG <<
1568 def_bool y <<
1569 798
1570 config ARCH_SUPPORTS_KEXEC_IMAGE_VERIFY_SIG !! 799 endmenu
1571 def_bool y <<
1572 800
1573 config ARCH_DEFAULT_KEXEC_IMAGE_VERIFY_SIG <<
1574 def_bool y <<
1575 801
1576 config ARCH_SUPPORTS_CRASH_DUMP !! 802 menu "Power management options (ACPI, APM)"
1577 def_bool y !! 803 depends on !X86_VOYAGER
1578 804
1579 config ARCH_HAS_GENERIC_CRASHKERNEL_RESERVATI !! 805 source kernel/power/Kconfig
1580 def_bool CRASH_RESERVE <<
1581 806
1582 config TRANS_TABLE !! 807 source "drivers/acpi/Kconfig"
1583 def_bool y <<
1584 depends on HIBERNATION || KEXEC_CORE <<
1585 <<
1586 config XEN_DOM0 <<
1587 def_bool y <<
1588 depends on XEN <<
1589 <<
1590 config XEN <<
1591 bool "Xen guest support on ARM64" <<
1592 depends on ARM64 && OF <<
1593 select SWIOTLB_XEN <<
1594 select PARAVIRT <<
1595 help <<
1596 Say Y if you want to run Linux in a <<
1597 808
1598 # include/linux/mmzone.h requires the followi !! 809 menu "APM (Advanced Power Management) BIOS Support"
1599 # !! 810 depends on PM
1600 # MAX_PAGE_ORDER + PAGE_SHIFT <= SECTION_SI <<
1601 # <<
1602 # so the maximum value of MAX_PAGE_ORDER is S <<
1603 # <<
1604 # | SECTION_SIZE_BITS | PAGE_SHIFT | m <<
1605 # ----+-------------------+--------------+--- <<
1606 # 4K | 27 | 12 | <<
1607 # 16K | 27 | 14 | <<
1608 # 64K | 29 | 16 | <<
1609 config ARCH_FORCE_MAX_ORDER <<
1610 int <<
1611 default "13" if ARM64_64K_PAGES <<
1612 default "11" if ARM64_16K_PAGES <<
1613 default "10" <<
1614 help <<
1615 The kernel page allocator limits th <<
1616 contiguous allocations. The limit i <<
1617 defines the maximal power of two of <<
1618 allocated as a single contiguous bl <<
1619 overriding the default setting when <<
1620 large blocks of physically contiguo <<
1621 811
1622 The maximal size of allocation cann !! 812 config APM
1623 section, so the value of MAX_PAGE_O !! 813 tristate "APM (Advanced Power Management) BIOS support"
>> 814 depends on PM
>> 815 ---help---
>> 816 APM is a BIOS specification for saving power using several different
>> 817 techniques. This is mostly useful for battery powered laptops with
>> 818 APM compliant BIOSes. If you say Y here, the system time will be
>> 819 reset after a RESUME operation, the /proc/apm device will provide
>> 820 battery status information, and user-space programs will receive
>> 821 notification of APM "events" (e.g. battery status change).
>> 822
>> 823 If you select "Y" here, you can disable actual use of the APM
>> 824 BIOS by passing the "apm=off" option to the kernel at boot time.
>> 825
>> 826 Note that the APM support is almost completely disabled for
>> 827 machines with more than one CPU.
>> 828
>> 829 In order to use APM, you will need supporting software. For location
>> 830 and more information, read <file:Documentation/pm.txt> and the
>> 831 Battery Powered Linux mini-HOWTO, available from
>> 832 <http://www.tldp.org/docs.html#howto>.
>> 833
>> 834 This driver does not spin down disk drives (see the hdparm(8)
>> 835 manpage ("man 8 hdparm") for that), and it doesn't turn off
>> 836 VESA-compliant "green" monitors.
>> 837
>> 838 This driver does not support the TI 4000M TravelMate and the ACER
>> 839 486/DX4/75 because they don't have compliant BIOSes. Many "green"
>> 840 desktop machines also don't have compliant BIOSes, and this driver
>> 841 may cause those machines to panic during the boot phase.
>> 842
>> 843 Generally, if you don't have a battery in your machine, there isn't
>> 844 much point in using this driver and you should say N. If you get
>> 845 random kernel OOPSes or reboots that don't seem to be related to
>> 846 anything, try disabling/enabling this option (or disabling/enabling
>> 847 APM in your BIOS).
>> 848
>> 849 Some other things you should try when experiencing seemingly random,
>> 850 "weird" problems:
>> 851
>> 852 1) make sure that you have enough swap space and that it is
>> 853 enabled.
>> 854 2) pass the "no-hlt" option to the kernel
>> 855 3) switch on floating point emulation in the kernel and pass
>> 856 the "no387" option to the kernel
>> 857 4) pass the "floppy=nodma" option to the kernel
>> 858 5) pass the "mem=4M" option to the kernel (thereby disabling
>> 859 all but the first 4 MB of RAM)
>> 860 6) make sure that the CPU is not over clocked.
>> 861 7) read the sig11 FAQ at <http://www.bitwizard.nl/sig11/>
>> 862 8) disable the cache from your BIOS settings
>> 863 9) install a fan for the video card or exchange video RAM
>> 864 10) install a better fan for the CPU
>> 865 11) exchange RAM chips
>> 866 12) exchange the motherboard.
>> 867
>> 868 To compile this driver as a module, choose M here: the
>> 869 module will be called apm.
>> 870
>> 871 config APM_IGNORE_USER_SUSPEND
>> 872 bool "Ignore USER SUSPEND"
>> 873 depends on APM
>> 874 help
>> 875 This option will ignore USER SUSPEND requests. On machines with a
>> 876 compliant APM BIOS, you want to say N. However, on the NEC Versa M
>> 877 series notebooks, it is necessary to say Y because of a BIOS bug.
>> 878
>> 879 config APM_DO_ENABLE
>> 880 bool "Enable PM at boot time"
>> 881 depends on APM
>> 882 ---help---
>> 883 Enable APM features at boot time. From page 36 of the APM BIOS
>> 884 specification: "When disabled, the APM BIOS does not automatically
>> 885 power manage devices, enter the Standby State, enter the Suspend
>> 886 State, or take power saving steps in response to CPU Idle calls."
>> 887 This driver will make CPU Idle calls when Linux is idle (unless this
>> 888 feature is turned off -- see "Do CPU IDLE calls", below). This
>> 889 should always save battery power, but more complicated APM features
>> 890 will be dependent on your BIOS implementation. You may need to turn
>> 891 this option off if your computer hangs at boot time when using APM
>> 892 support, or if it beeps continuously instead of suspending. Turn
>> 893 this off if you have a NEC UltraLite Versa 33/C or a Toshiba
>> 894 T400CDT. This is off by default since most machines do fine without
>> 895 this feature.
1624 896
1625 MAX_PAGE_ORDER + PAGE_SHIFT <= SE !! 897 config APM_CPU_IDLE
>> 898 bool "Make CPU Idle calls when idle"
>> 899 depends on APM
>> 900 help
>> 901 Enable calls to APM CPU Idle/CPU Busy inside the kernel's idle loop.
>> 902 On some machines, this can activate improved power savings, such as
>> 903 a slowed CPU clock rate, when the machine is idle. These idle calls
>> 904 are made after the idle loop has run for some length of time (e.g.,
>> 905 333 mS). On some machines, this will cause a hang at boot time or
>> 906 whenever the CPU becomes idle. (On machines with more than one CPU,
>> 907 this option does nothing.)
>> 908
>> 909 config APM_DISPLAY_BLANK
>> 910 bool "Enable console blanking using APM"
>> 911 depends on APM
>> 912 help
>> 913 Enable console blanking using the APM. Some laptops can use this to
>> 914 turn off the LCD backlight when the screen blanker of the Linux
>> 915 virtual console blanks the screen. Note that this is only used by
>> 916 the virtual console screen blanker, and won't turn off the backlight
>> 917 when using the X Window system. This also doesn't have anything to
>> 918 do with your VESA-compliant power-saving monitor. Further, this
>> 919 option doesn't work for all laptops -- it might not turn off your
>> 920 backlight at all, or it might print a lot of errors to the console,
>> 921 especially if you are using gpm.
>> 922
>> 923 config APM_RTC_IS_GMT
>> 924 bool "RTC stores time in GMT"
>> 925 depends on APM
>> 926 help
>> 927 Say Y here if your RTC (Real Time Clock a.k.a. hardware clock)
>> 928 stores the time in GMT (Greenwich Mean Time). Say N if your RTC
>> 929 stores localtime.
>> 930
>> 931 It is in fact recommended to store GMT in your RTC, because then you
>> 932 don't have to worry about daylight savings time changes. The only
>> 933 reason not to use GMT in your RTC is if you also run a broken OS
>> 934 that doesn't understand GMT.
>> 935
>> 936 config APM_ALLOW_INTS
>> 937 bool "Allow interrupts during APM BIOS calls"
>> 938 depends on APM
>> 939 help
>> 940 Normally we disable external interrupts while we are making calls to
>> 941 the APM BIOS as a measure to lessen the effects of a badly behaving
>> 942 BIOS implementation. The BIOS should reenable interrupts if it
>> 943 needs to. Unfortunately, some BIOSes do not -- especially those in
>> 944 many of the newer IBM Thinkpads. If you experience hangs when you
>> 945 suspend, try setting this to Y. Otherwise, say N.
>> 946
>> 947 config APM_REAL_MODE_POWER_OFF
>> 948 bool "Use real mode APM BIOS call to power off"
>> 949 depends on APM
>> 950 help
>> 951 Use real mode APM BIOS calls to switch off the computer. This is
>> 952 a work-around for a number of buggy BIOSes. Switch this option on if
>> 953 your computer crashes instead of powering off properly.
>> 954
>> 955 endmenu
1626 956
1627 Don't change if unsure. !! 957 source "arch/i386/kernel/cpu/cpufreq/Kconfig"
1628 958
1629 config UNMAP_KERNEL_AT_EL0 !! 959 endmenu
1630 bool "Unmap kernel when running in us <<
1631 default y <<
1632 help <<
1633 Speculation attacks against some hi <<
1634 be used to bypass MMU permission ch <<
1635 userspace. This can be defended aga <<
1636 when running in userspace, mapping <<
1637 via a trampoline page in the vector <<
1638 960
1639 If unsure, say Y. <<
1640 961
1641 config MITIGATE_SPECTRE_BRANCH_HISTORY !! 962 menu "Bus options (PCI, PCMCIA, EISA, MCA, ISA)"
1642 bool "Mitigate Spectre style attacks <<
1643 default y <<
1644 help <<
1645 Speculation attacks against some hi <<
1646 make use of branch history to influ <<
1647 When taking an exception from user- <<
1648 or a firmware call overwrites the b <<
1649 963
1650 config RODATA_FULL_DEFAULT_ENABLED !! 964 config X86_VISWS_APIC
1651 bool "Apply r/o permissions of VM are !! 965 bool
>> 966 depends on X86_VISWS
1652 default y 967 default y
1653 help <<
1654 Apply read-only attributes of VM ar <<
1655 the backing pages as well. This pre <<
1656 from being modified (inadvertently <<
1657 mapping of the same memory page. Th <<
1658 be turned off at runtime by passing <<
1659 with rodata=full if this option is <<
1660 <<
1661 This requires the linear region to <<
1662 which may adversely affect performa <<
1663 <<
1664 config ARM64_SW_TTBR0_PAN <<
1665 bool "Emulate Privileged Access Never <<
1666 depends on !KCSAN <<
1667 help <<
1668 Enabling this option prevents the k <<
1669 user-space memory directly by point <<
1670 zeroed area and reserved ASID. The <<
1671 restore the valid TTBR0_EL1 tempora <<
1672 968
1673 config ARM64_TAGGED_ADDR_ABI !! 969 config X86_LOCAL_APIC
1674 bool "Enable the tagged user addresse !! 970 bool
>> 971 depends on (X86_VISWS || SMP) && !X86_VOYAGER
1675 default y 972 default y
1676 help <<
1677 When this option is enabled, user a <<
1678 relaxed ABI via prctl() allowing ta <<
1679 to system calls as pointer argument <<
1680 Documentation/arch/arm64/tagged-add <<
1681 973
1682 menuconfig COMPAT !! 974 config X86_IO_APIC
1683 bool "Kernel support for 32-bit EL0" !! 975 bool
1684 depends on ARM64_4K_PAGES || EXPERT !! 976 depends on SMP && !(X86_VISWS || X86_VOYAGER)
1685 select HAVE_UID16 <<
1686 select OLD_SIGSUSPEND3 <<
1687 select COMPAT_OLD_SIGACTION <<
1688 help <<
1689 This option enables support for a 3 <<
1690 kernel at EL1. AArch32-specific com <<
1691 the user helper functions, VFP supp <<
1692 handled appropriately by the kernel <<
1693 <<
1694 If you use a page size other than 4 <<
1695 that you will only be able to execu <<
1696 with page size aligned segments. <<
1697 <<
1698 If you want to execute 32-bit users <<
1699 <<
1700 if COMPAT <<
1701 <<
1702 config KUSER_HELPERS <<
1703 bool "Enable kuser helpers page for 3 <<
1704 default y 977 default y
1705 help <<
1706 Warning: disabling this option may <<
1707 978
1708 Provide kuser helpers to compat tas !! 979 config PCI
1709 helper code to userspace in read on !! 980 bool "PCI support" if !X86_VISWS
1710 to allow userspace to be independen !! 981 depends on !X86_VOYAGER
1711 the system. This permits binaries t !! 982 default y if X86_VISWS
1712 to ARMv8 without modification. !! 983 help
>> 984 Find out whether you have a PCI motherboard. PCI is the name of a
>> 985 bus system, i.e. the way the CPU talks to the other stuff inside
>> 986 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
>> 987 VESA. If you have PCI, say Y, otherwise N.
>> 988
>> 989 The PCI-HOWTO, available from
>> 990 <http://www.tldp.org/docs.html#howto>, contains valuable
>> 991 information about which PCI hardware does work under Linux and which
>> 992 doesn't.
1713 993
1714 See Documentation/arch/arm/kernel_u !! 994 choice
>> 995 prompt "PCI access mode"
>> 996 depends on PCI && !X86_VISWS
>> 997 default PCI_GOANY
>> 998
>> 999 config PCI_GOBIOS
>> 1000 bool "BIOS"
>> 1001 ---help---
>> 1002 On PCI systems, the BIOS can be used to detect the PCI devices and
>> 1003 determine their configuration. However, some old PCI motherboards
>> 1004 have BIOS bugs and may crash if this is done. Also, some embedded
>> 1005 PCI-based systems don't have any BIOS at all. Linux can also try to
>> 1006 detect the PCI hardware directly without using the BIOS.
>> 1007
>> 1008 With this option, you can specify how Linux should detect the PCI
>> 1009 devices. If you choose "BIOS", the BIOS will be used, if you choose
>> 1010 "Direct", the BIOS won't be used, and if you choose "Any", the
>> 1011 kernel will try the direct access method and falls back to the BIOS
>> 1012 if that doesn't work. If unsure, go with the default, which is
>> 1013 "Any".
1715 1014
1716 However, the fixed address nature o !! 1015 config PCI_GODIRECT
1717 by ROP (return orientated programmi !! 1016 bool "Direct"
1718 exploits. <<
1719 1017
1720 If all of the binaries and librarie !! 1018 config PCI_GOANY
1721 are built specifically for your pla !! 1019 bool "Any"
1722 these helpers, then you can turn th <<
1723 such exploits. However, in that cas <<
1724 relying on those helpers is run, it <<
1725 1020
1726 Say N here only if you are absolute !! 1021 endchoice
1727 need these helpers; otherwise, the <<
1728 1022
1729 config COMPAT_VDSO !! 1023 config PCI_BIOS
1730 bool "Enable vDSO for 32-bit applicat !! 1024 bool
1731 depends on !CPU_BIG_ENDIAN !! 1025 depends on !X86_VISWS && PCI && (PCI_GOBIOS || PCI_GOANY)
1732 depends on (CC_IS_CLANG && LD_IS_LLD) <<
1733 select GENERIC_COMPAT_VDSO <<
1734 default y 1026 default y
1735 help <<
1736 Place in the process address space <<
1737 ELF shared object providing fast im <<
1738 and clock_gettime. <<
1739 1027
1740 You must have a 32-bit build of gli !! 1028 config PCI_DIRECT
1741 to seamlessly take advantage of thi !! 1029 bool
1742 !! 1030 depends on PCI && ((PCI_GODIRECT || PCI_GOANY) || X86_VISWS)
1743 config THUMB2_COMPAT_VDSO <<
1744 bool "Compile the 32-bit vDSO for Thu <<
1745 depends on COMPAT_VDSO <<
1746 default y 1031 default y
1747 help <<
1748 Compile the compat vDSO with '-mthu <<
1749 otherwise with '-marm'. <<
1750 1032
1751 config COMPAT_ALIGNMENT_FIXUPS !! 1033 source "drivers/pci/Kconfig"
1752 bool "Fix up misaligned multi-word lo <<
1753 1034
1754 menuconfig ARMV8_DEPRECATED !! 1035 config ISA
1755 bool "Emulate deprecated/obsolete ARM !! 1036 bool "ISA support"
1756 depends on SYSCTL !! 1037 depends on !(X86_VOYAGER || X86_VISWS)
1757 help 1038 help
1758 Legacy software support may require !! 1039 Find out whether you have ISA slots on your motherboard. ISA is the
1759 that have been deprecated or obsole !! 1040 name of a bus system, i.e. the way the CPU talks to the other stuff
1760 !! 1041 inside your box. Other bus systems are PCI, EISA, MicroChannel
1761 Enable this config to enable select !! 1042 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
1762 features. !! 1043 newer boards don't support it. If you have ISA, say Y, otherwise N.
1763 1044
1764 If unsure, say Y !! 1045 config EISA
>> 1046 bool "EISA support"
>> 1047 depends on ISA
>> 1048 ---help---
>> 1049 The Extended Industry Standard Architecture (EISA) bus was
>> 1050 developed as an open alternative to the IBM MicroChannel bus.
1765 1051
1766 if ARMV8_DEPRECATED !! 1052 The EISA bus provided some of the features of the IBM MicroChannel
>> 1053 bus while maintaining backward compatibility with cards made for
>> 1054 the older ISA bus. The EISA bus saw limited use between 1988 and
>> 1055 1995 when it was made obsolete by the PCI bus.
1767 1056
1768 config SWP_EMULATION !! 1057 Say Y here if you are building a kernel for an EISA-based machine.
1769 bool "Emulate SWP/SWPB instructions" <<
1770 help <<
1771 ARMv8 obsoletes the use of A32 SWP/ <<
1772 they are always undefined. Say Y he <<
1773 emulation of these instructions for <<
1774 This feature can be controlled at r <<
1775 sysctl which is disabled by default <<
1776 1058
1777 In some older versions of glibc [<= !! 1059 Otherwise, say N.
1778 trylock() operations with the assum <<
1779 be preempted. This invalid assumpti <<
1780 with SWP emulation enabled, leading <<
1781 application. <<
1782 1060
1783 NOTE: when accessing uncached share !! 1061 source "drivers/eisa/Kconfig"
1784 on an external transaction monitori <<
1785 monitor to maintain update atomicit <<
1786 implement a global monitor, this op <<
1787 perform SWP operations to uncached <<
1788 1062
1789 If unsure, say Y !! 1063 config MCA
1790 !! 1064 bool "MCA support"
1791 config CP15_BARRIER_EMULATION !! 1065 depends on !(X86_VISWS || X86_VOYAGER)
1792 bool "Emulate CP15 Barrier instructio <<
1793 help 1066 help
1794 The CP15 barrier instructions - CP1 !! 1067 MicroChannel Architecture is found in some IBM PS/2 machines and
1795 CP15DMB - are deprecated in ARMv8 ( !! 1068 laptops. It is a bus system similar to PCI or ISA. See
1796 strongly recommended to use the ISB !! 1069 <file:Documentation/mca.txt> (and especially the web page given
1797 instructions instead. !! 1070 there) before attempting to build an MCA bus kernel.
1798 1071
1799 Say Y here to enable software emula !! 1072 config MCA
1800 instructions for AArch32 userspace !! 1073 depends on X86_VOYAGER
1801 enabled, CP15 barrier usage is trac !! 1074 default y if X86_VOYAGER
1802 identify software that needs updati <<
1803 controlled at runtime with the abi. <<
1804 1075
1805 If unsure, say Y !! 1076 source "drivers/mca/Kconfig"
1806 1077
1807 config SETEND_EMULATION !! 1078 config SCx200
1808 bool "Emulate SETEND instruction" !! 1079 tristate "NatSemi SCx200 support"
>> 1080 depends on !X86_VOYAGER
1809 help 1081 help
1810 The SETEND instruction alters the d !! 1082 This provides basic support for the National Semiconductor SCx200
1811 AArch32 EL0, and is deprecated in A !! 1083 processor. Right now this is just a driver for the GPIO pins.
1812 1084
1813 Say Y here to enable software emula !! 1085 If you don't know what to do here, say N.
1814 for AArch32 userspace code. This fe <<
1815 at runtime with the abi.setend sysc <<
1816 1086
1817 Note: All the cpus on the system mu !! 1087 This support is also available as a module. If compiled as a
1818 for this feature to be enabled. If !! 1088 module, it will be called scx200.
1819 endian - is hotplugged in after thi <<
1820 be unexpected results in the applic <<
1821 1089
1822 If unsure, say Y !! 1090 config HOTPLUG
1823 endif # ARMV8_DEPRECATED !! 1091 bool "Support for hot-pluggable devices"
>> 1092 ---help---
>> 1093 Say Y here if you want to plug devices into your computer while
>> 1094 the system is running, and be able to use them quickly. In many
>> 1095 cases, the devices can likewise be unplugged at any time too.
1824 1096
1825 endif # COMPAT !! 1097 One well known example of this is PCMCIA- or PC-cards, credit-card
>> 1098 size devices such as network cards, modems or hard drives which are
>> 1099 plugged into slots found on all modern laptop computers. Another
>> 1100 example, used on modern desktops as well as laptops, is USB.
1826 1101
1827 menu "ARMv8.1 architectural features" !! 1102 Enable HOTPLUG and KMOD, and build a modular kernel. Get agent
>> 1103 software (at <http://linux-hotplug.sourceforge.net/>) and install it.
>> 1104 Then your kernel will automatically call out to a user mode "policy
>> 1105 agent" (/sbin/hotplug) to load modules and set up software needed
>> 1106 to use devices as you hotplug them.
1828 1107
1829 config ARM64_HW_AFDBM !! 1108 source "drivers/pcmcia/Kconfig"
1830 bool "Support for hardware updates of <<
1831 default y <<
1832 help <<
1833 The ARMv8.1 architecture extensions <<
1834 hardware updates of the access and <<
1835 table entries. When enabled in TCR_ <<
1836 capable processors, accesses to pag <<
1837 set this bit instead of raising an <<
1838 Similarly, writes to read-only page <<
1839 clear the read-only bit (AP[2]) ins <<
1840 permission fault. <<
1841 1109
1842 Kernels built with this configurati !! 1110 source "drivers/pci/hotplug/Kconfig"
1843 to work on pre-ARMv8.1 hardware and <<
1844 minimal. If unsure, say Y. <<
1845 1111
1846 config ARM64_PAN !! 1112 endmenu
1847 bool "Enable support for Privileged A <<
1848 default y <<
1849 help <<
1850 Privileged Access Never (PAN; part <<
1851 prevents the kernel or hypervisor f <<
1852 memory directly. <<
1853 <<
1854 Choosing this option will cause any <<
1855 copy_to_user et al) memory access t <<
1856 1113
1857 The feature is detected at runtime, <<
1858 instruction if the cpu does not imp <<
1859 1114
1860 config AS_HAS_LSE_ATOMICS !! 1115 menu "Executable file formats"
1861 def_bool $(as-instr,.arch_extension l <<
1862 1116
1863 config ARM64_LSE_ATOMICS !! 1117 source "fs/Kconfig.binfmt"
1864 bool <<
1865 default ARM64_USE_LSE_ATOMICS <<
1866 depends on AS_HAS_LSE_ATOMICS <<
1867 1118
1868 config ARM64_USE_LSE_ATOMICS !! 1119 endmenu
1869 bool "Atomic instructions" <<
1870 default y <<
1871 help <<
1872 As part of the Large System Extensi <<
1873 atomic instructions that are design <<
1874 very large systems. <<
1875 1120
1876 Say Y here to make use of these ins !! 1121 source "drivers/Kconfig"
1877 atomic routines. This incurs a smal <<
1878 not support these instructions and <<
1879 built with binutils >= 2.25 in orde <<
1880 to be used. <<
1881 1122
1882 endmenu # "ARMv8.1 architectural features" !! 1123 source "fs/Kconfig"
1883 1124
1884 menu "ARMv8.2 architectural features" !! 1125 source "arch/i386/oprofile/Kconfig"
1885 1126
1886 config AS_HAS_ARMV8_2 <<
1887 def_bool $(cc-option,-Wa$(comma)-marc <<
1888 1127
1889 config AS_HAS_SHA3 !! 1128 menu "Kernel hacking"
1890 def_bool $(as-instr,.arch armv8.2-a+s <<
1891 1129
1892 config ARM64_PMEM !! 1130 config DEBUG_KERNEL
1893 bool "Enable support for persistent m !! 1131 bool "Kernel debugging"
1894 select ARCH_HAS_PMEM_API <<
1895 select ARCH_HAS_UACCESS_FLUSHCACHE <<
1896 help 1132 help
1897 Say Y to enable support for the per !! 1133 Say Y here if you are developing drivers or trying to debug and
1898 ARMv8.2 DCPoP feature. !! 1134 identify kernel problems.
1899 1135
1900 The feature is detected at runtime, !! 1136 config DEBUG_STACKOVERFLOW
1901 operations if DC CVAP is not suppor !! 1137 bool "Check for stack overflows"
1902 DC CVAP itself if the system does n !! 1138 depends on DEBUG_KERNEL
1903 1139
1904 config ARM64_RAS_EXTN !! 1140 config DEBUG_SLAB
1905 bool "Enable support for RAS CPU Exte !! 1141 bool "Debug memory allocations"
1906 default y !! 1142 depends on DEBUG_KERNEL
1907 help 1143 help
1908 CPUs that support the Reliability, !! 1144 Say Y here to have the kernel do limited verification on memory
1909 (RAS) Extensions, part of ARMv8.2 a !! 1145 allocation as well as poisoning memory on free to catch use of freed
1910 errors, classify them and report th !! 1146 memory.
1911 <<
1912 On CPUs with these extensions syste <<
1913 barriers to determine if faults are <<
1914 classification from a new set of re <<
1915 1147
1916 Selecting this feature will allow t !! 1148 config DEBUG_IOVIRT
1917 and access the new registers if the !! 1149 bool "Memory mapped I/O debugging"
1918 Platform RAS features may additiona !! 1150 depends on DEBUG_KERNEL
1919 <<
1920 config ARM64_CNP <<
1921 bool "Enable support for Common Not P <<
1922 default y <<
1923 depends on ARM64_PAN || !ARM64_SW_TTB <<
1924 help 1151 help
1925 Common Not Private (CNP) allows tra !! 1152 Say Y here to get warned whenever an attempt is made to do I/O on
1926 be shared between different PEs in !! 1153 obviously invalid addresses such as those generated when ioremap()
1927 domain, so the hardware can use thi !! 1154 calls are forgotten. Memory mapped I/O will go through an extra
1928 caching of such entries in the TLB. !! 1155 check to catch access to unmapped ISA addresses, an access method
>> 1156 that can still be used by old drivers that are being ported from
>> 1157 2.0/2.2.
1929 1158
1930 Selecting this option allows the CN !! 1159 config MAGIC_SYSRQ
1931 at runtime, and does not affect PEs !! 1160 bool "Magic SysRq key"
1932 this feature. !! 1161 depends on DEBUG_KERNEL
1933 <<
1934 endmenu # "ARMv8.2 architectural features" <<
1935 <<
1936 menu "ARMv8.3 architectural features" <<
1937 <<
1938 config ARM64_PTR_AUTH <<
1939 bool "Enable support for pointer auth <<
1940 default y <<
1941 help 1162 help
1942 Pointer authentication (part of the !! 1163 If you say Y here, you will have some control over the system even
1943 instructions for signing and authen !! 1164 if the system crashes for example during kernel debugging (e.g., you
1944 keys, which can be used to mitigate !! 1165 will be able to flush the buffer cache to disk, reboot the system
1945 and other attacks. !! 1166 immediately or dump some status information). This is accomplished
>> 1167 by pressing various keys while holding SysRq (Alt+PrintScreen). It
>> 1168 also works on a serial console (on PC hardware at least), if you
>> 1169 send a BREAK and then within 5 seconds a command keypress. The
>> 1170 keys are documented in <file:Documentation/sysrq.txt>. Don't say Y
>> 1171 unless you really know what this hack does.
1946 1172
1947 This option enables these instructi !! 1173 config DEBUG_SPINLOCK
1948 Choosing this option will cause the !! 1174 bool "Spinlock debugging"
1949 for each process at exec() time, wi !! 1175 depends on DEBUG_KERNEL
1950 context-switched along with the pro <<
1951 <<
1952 The feature is detected at runtime. <<
1953 hardware it will not be advertised <<
1954 be enabled. <<
1955 <<
1956 If the feature is present on the bo <<
1957 the late CPU will be parked. Also, <<
1958 address auth and the late CPU has t <<
1959 but with the feature disabled. On s <<
1960 not be selected. <<
1961 <<
1962 config ARM64_PTR_AUTH_KERNEL <<
1963 bool "Use pointer authentication for <<
1964 default y <<
1965 depends on ARM64_PTR_AUTH <<
1966 depends on (CC_HAS_SIGN_RETURN_ADDRES <<
1967 # Modern compilers insert a .note.gnu <<
1968 # which is only understood by binutil <<
1969 depends on LD_IS_LLD || LD_VERSION >= <<
1970 depends on !CC_IS_CLANG || AS_HAS_CFI <<
1971 depends on (!FUNCTION_GRAPH_TRACER || <<
1972 help 1176 help
1973 If the compiler supports the -mbran !! 1177 Say Y here and build SMP to catch missing spinlock initialization
1974 -msign-return-address flag (e.g. GC !! 1178 and certain other kinds of spinlock errors commonly made. This is
1975 will cause the kernel itself to be !! 1179 best used in conjunction with the NMI watchdog so that spinlock
1976 protection. In this case, and if th !! 1180 deadlocks are also debuggable.
1977 support pointer authentication, the <<
1978 disabled with minimal loss of prote <<
1979 <<
1980 This feature works with FUNCTION_GR <<
1981 DYNAMIC_FTRACE_WITH_ARGS is enabled <<
1982 <<
1983 config CC_HAS_BRANCH_PROT_PAC_RET <<
1984 # GCC 9 or later, clang 8 or later <<
1985 def_bool $(cc-option,-mbranch-protect <<
1986 <<
1987 config CC_HAS_SIGN_RETURN_ADDRESS <<
1988 # GCC 7, 8 <<
1989 def_bool $(cc-option,-msign-return-ad <<
1990 <<
1991 config AS_HAS_ARMV8_3 <<
1992 def_bool $(cc-option,-Wa$(comma)-marc <<
1993 <<
1994 config AS_HAS_CFI_NEGATE_RA_STATE <<
1995 def_bool $(as-instr,.cfi_startproc\n. <<
1996 <<
1997 config AS_HAS_LDAPR <<
1998 def_bool $(as-instr,.arch_extension r <<
1999 <<
2000 endmenu # "ARMv8.3 architectural features" <<
2001 1181
2002 menu "ARMv8.4 architectural features" !! 1182 config DEBUG_PAGEALLOC
2003 !! 1183 bool "Page alloc debugging"
2004 config ARM64_AMU_EXTN !! 1184 depends on DEBUG_KERNEL
2005 bool "Enable support for the Activity <<
2006 default y <<
2007 help 1185 help
2008 The activity monitors extension is !! 1186 Unmap pages from the kernel linear mapping after free_pages().
2009 by the ARMv8.4 CPU architecture. Th !! 1187 This results in a large slowdown, but helps to find certain types
2010 of the activity monitors architectu !! 1188 of memory corruptions.
2011 <<
2012 To enable the use of this extension <<
2013 <<
2014 Note that for architectural reasons <<
2015 support when running on CPUs that p <<
2016 extension. The required support is <<
2017 * Version 1.5 and later of the AR <<
2018 1189
2019 For kernels that have this configur !! 1190 config DEBUG_HIGHMEM
2020 firmware, you may need to say N her !! 1191 bool "Highmem debugging"
2021 Otherwise you may experience firmwa !! 1192 depends on DEBUG_KERNEL && HIGHMEM
2022 accessing the counter registers. Ev <<
2023 symptoms, the values returned by th <<
2024 correctly reflect reality. Most com <<
2025 indicating that the counter is not <<
2026 <<
2027 config AS_HAS_ARMV8_4 <<
2028 def_bool $(cc-option,-Wa$(comma)-marc <<
2029 <<
2030 config ARM64_TLB_RANGE <<
2031 bool "Enable support for tlbi range f <<
2032 default y <<
2033 depends on AS_HAS_ARMV8_4 <<
2034 help 1193 help
2035 ARMv8.4-TLBI provides TLBI invalida !! 1194 This options enables addition error checking for high memory systems.
2036 range of input addresses. !! 1195 Disable for production systems.
2037 <<
2038 The feature introduces new assembly <<
2039 support when binutils >= 2.30. <<
2040 1196
2041 endmenu # "ARMv8.4 architectural features" !! 1197 config DEBUG_INFO
2042 !! 1198 bool "Compile the kernel with debug info"
2043 menu "ARMv8.5 architectural features" !! 1199 depends on DEBUG_KERNEL
2044 <<
2045 config AS_HAS_ARMV8_5 <<
2046 def_bool $(cc-option,-Wa$(comma)-marc <<
2047 <<
2048 config ARM64_BTI <<
2049 bool "Branch Target Identification su <<
2050 default y <<
2051 help 1200 help
2052 Branch Target Identification (part !! 1201 If you say Y here the resulting kernel image will include
2053 provides a mechanism to limit the s !! 1202 debugging info resulting in a larger kernel image.
2054 branch instructions such as BR or B !! 1203 Say Y here only if you plan to use gdb to debug the kernel.
2055 !! 1204 If you don't debug the kernel, you can say N.
2056 To make use of BTI on CPUs that sup !! 1205
2057 !! 1206 config DEBUG_SPINLOCK_SLEEP
2058 BTI is intended to provide compleme !! 1207 bool "Sleep-inside-spinlock checking"
2059 flow integrity protection mechanism <<
2060 authentication mechanism provided a <<
2061 For this reason, it does not make s <<
2062 also enabling support for pointer a <<
2063 enabling this option you should als <<
2064 <<
2065 Userspace binaries must also be spe <<
2066 this mechanism. If you say N here <<
2067 BTI, such binaries can still run, b <<
2068 enforcement of branch destinations. <<
2069 <<
2070 config ARM64_BTI_KERNEL <<
2071 bool "Use Branch Target Identificatio <<
2072 default y <<
2073 depends on ARM64_BTI <<
2074 depends on ARM64_PTR_AUTH_KERNEL <<
2075 depends on CC_HAS_BRANCH_PROT_PAC_RET <<
2076 # https://gcc.gnu.org/bugzilla/show_b <<
2077 depends on !CC_IS_GCC || GCC_VERSION <<
2078 # https://gcc.gnu.org/bugzilla/show_b <<
2079 depends on !CC_IS_GCC <<
2080 depends on (!FUNCTION_GRAPH_TRACER || <<
2081 help 1208 help
2082 Build the kernel with Branch Target !! 1209 If you say Y here, various routines which may sleep will become very
2083 and enable enforcement of this for !! 1210 noisy if they are called with a spinlock held.
2084 is enabled and the system supports <<
2085 modular code must have BTI enabled. <<
2086 1211
2087 config CC_HAS_BRANCH_PROT_PAC_RET_BTI !! 1212 config FRAME_POINTER
2088 # GCC 9 or later, clang 8 or later !! 1213 bool "Compile the kernel with frame pointers"
2089 def_bool $(cc-option,-mbranch-protect <<
2090 <<
2091 config ARM64_E0PD <<
2092 bool "Enable support for E0PD" <<
2093 default y <<
2094 help 1214 help
2095 E0PD (part of the ARMv8.5 extension !! 1215 If you say Y here the resulting kernel image will be slightly larger
2096 that EL0 accesses made via TTBR1 al !! 1216 and slower, but it will give very useful debugging information.
2097 providing similar benefits to KASLR !! 1217 If you don't debug the kernel, you can say N, but we may not be able
2098 with lower overhead and without dis !! 1218 to solve problems without frame pointers.
2099 kernel memory such as SPE. <<
2100 <<
2101 This option enables E0PD for TTBR1 <<
2102 <<
2103 config ARM64_AS_HAS_MTE <<
2104 # Initial support for MTE went in bin <<
2105 # ".arch armv8.5-a+memtag" below. How <<
2106 # as a late addition to the final arc <<
2107 # is only supported in the newer 2.32 <<
2108 # versions, hence the extra "stgm" in <<
2109 def_bool $(as-instr,.arch armv8.5-a+m <<
2110 <<
2111 config ARM64_MTE <<
2112 bool "Memory Tagging Extension suppor <<
2113 default y <<
2114 depends on ARM64_AS_HAS_MTE && ARM64_ <<
2115 depends on AS_HAS_ARMV8_5 <<
2116 depends on AS_HAS_LSE_ATOMICS <<
2117 # Required for tag checking in the ua <<
2118 depends on ARM64_PAN <<
2119 select ARCH_HAS_SUBPAGE_FAULTS <<
2120 select ARCH_USES_HIGH_VMA_FLAGS <<
2121 select ARCH_USES_PG_ARCH_2 <<
2122 select ARCH_USES_PG_ARCH_3 <<
2123 help <<
2124 Memory Tagging (part of the ARMv8.5 <<
2125 architectural support for run-time, <<
2126 various classes of memory error to <<
2127 to eliminate vulnerabilities arisin <<
2128 languages. <<
2129 <<
2130 This option enables the support for <<
2131 Extension at EL0 (i.e. for userspac <<
2132 <<
2133 Selecting this option allows the fe <<
2134 runtime. Any secondary CPU not impl <<
2135 not be allowed a late bring-up. <<
2136 <<
2137 Userspace binaries that want to use <<
2138 explicitly opt in. The mechanism fo <<
2139 described in: <<
2140 <<
2141 Documentation/arch/arm64/memory-tag <<
2142 <<
2143 endmenu # "ARMv8.5 architectural features" <<
2144 <<
2145 menu "ARMv8.7 architectural features" <<
2146 1219
2147 config ARM64_EPAN !! 1220 config X86_EXTRA_IRQS
2148 bool "Enable support for Enhanced Pri !! 1221 bool
>> 1222 depends on X86_LOCAL_APIC || X86_VOYAGER
2149 default y 1223 default y
2150 depends on ARM64_PAN <<
2151 help <<
2152 Enhanced Privileged Access Never (E <<
2153 Access Never to be used with Execut <<
2154 <<
2155 The feature is detected at runtime, <<
2156 if the cpu does not implement the f <<
2157 endmenu # "ARMv8.7 architectural features" <<
2158 <<
2159 menu "ARMv8.9 architectural features" <<
2160 <<
2161 config ARM64_POE <<
2162 prompt "Permission Overlay Extension" <<
2163 def_bool y <<
2164 select ARCH_USES_HIGH_VMA_FLAGS <<
2165 select ARCH_HAS_PKEYS <<
2166 help <<
2167 The Permission Overlay Extension is <<
2168 Protection Keys. Memory Protection <<
2169 enforcing page-based protections, b <<
2170 of the page tables when an applicat <<
2171 <<
2172 For details, see Documentation/core <<
2173 1224
2174 If unsure, say y. !! 1225 config X86_FIND_SMP_CONFIG
2175 !! 1226 bool
2176 config ARCH_PKEY_BITS !! 1227 depends on X86_LOCAL_APIC || X86_VOYAGER
2177 int <<
2178 default 3 <<
2179 <<
2180 endmenu # "ARMv8.9 architectural features" <<
2181 <<
2182 config ARM64_SVE <<
2183 bool "ARM Scalable Vector Extension s <<
2184 default y 1228 default y
2185 help <<
2186 The Scalable Vector Extension (SVE) <<
2187 execution state which complements a <<
2188 of the base architecture to support <<
2189 additional vectorisation opportunit <<
2190 <<
2191 To enable use of this extension on <<
2192 1229
2193 On CPUs that support the SVE2 exten !! 1230 config X86_MPPARSE
2194 those too. !! 1231 bool
2195 !! 1232 depends on X86_LOCAL_APIC && !X86_VISWS
2196 Note that for architectural reasons <<
2197 support when running on SVE capable <<
2198 is present in: <<
2199 <<
2200 * version 1.5 and later of the AR <<
2201 * the AArch64 boot wrapper since <<
2202 ("bootwrapper: SVE: Enable SVE <<
2203 <<
2204 For other firmware implementations, <<
2205 or vendor. <<
2206 <<
2207 If you need the kernel to boot on S <<
2208 firmware, you may need to say N her <<
2209 fixed. Otherwise, you may experien <<
2210 booting the kernel. If unsure and <<
2211 symptoms, you should assume that it <<
2212 <<
2213 config ARM64_SME <<
2214 bool "ARM Scalable Matrix Extension s <<
2215 default y 1233 default y
2216 depends on ARM64_SVE <<
2217 depends on BROKEN <<
2218 help <<
2219 The Scalable Matrix Extension (SME) <<
2220 execution state which utilises a su <<
2221 instruction set, together with the <<
2222 register state capable of holding t <<
2223 enable various matrix operations. <<
2224 1234
2225 config ARM64_PSEUDO_NMI !! 1235 endmenu
2226 bool "Support for NMI-like interrupts <<
2227 select ARM_GIC_V3 <<
2228 help <<
2229 Adds support for mimicking Non-Mask <<
2230 GIC interrupt priority. This suppor <<
2231 ARM GIC. <<
2232 1236
2233 This high priority configuration fo !! 1237 source "security/Kconfig"
2234 explicitly enabled by setting the k <<
2235 "irqchip.gicv3_pseudo_nmi" to 1. <<
2236 1238
2237 If unsure, say N !! 1239 source "crypto/Kconfig"
2238 1240
2239 if ARM64_PSEUDO_NMI !! 1241 source "lib/Kconfig"
2240 config ARM64_DEBUG_PRIORITY_MASKING <<
2241 bool "Debug interrupt priority maskin <<
2242 help <<
2243 This adds runtime checks to functio <<
2244 interrupts when using priority mask <<
2245 the validity of ICC_PMR_EL1 when ca <<
2246 <<
2247 If unsure, say N <<
2248 endif # ARM64_PSEUDO_NMI <<
2249 1242
2250 config RELOCATABLE !! 1243 config X86_SMP
2251 bool "Build a relocatable kernel imag !! 1244 bool
2252 select ARCH_HAS_RELR !! 1245 depends on SMP && !X86_VOYAGER
2253 default y 1246 default y
2254 help <<
2255 This builds the kernel as a Positio <<
2256 which retains all relocation metada <<
2257 kernel binary at runtime to a diffe <<
2258 address it was linked at. <<
2259 Since AArch64 uses the RELA relocat <<
2260 relocation pass at runtime even if <<
2261 same address it was linked at. <<
2262 <<
2263 config RANDOMIZE_BASE <<
2264 bool "Randomize the address of the ke <<
2265 select RELOCATABLE <<
2266 help <<
2267 Randomizes the virtual address at w <<
2268 loaded, as a security feature that <<
2269 relying on knowledge of the locatio <<
2270 <<
2271 It is the bootloader's job to provi <<
2272 random u64 value in /chosen/kaslr-s <<
2273 1247
2274 When booting via the UEFI stub, it !! 1248 config X86_HT
2275 EFI_RNG_PROTOCOL implementation (if !! 1249 bool
2276 to the kernel proper. In addition, !! 1250 depends on SMP && !(X86_VISWS || X86_VOYAGER)
2277 location of the kernel Image as wel <<
2278 <<
2279 If unsure, say N. <<
2280 <<
2281 config RANDOMIZE_MODULE_REGION_FULL <<
2282 bool "Randomize the module region ove <<
2283 depends on RANDOMIZE_BASE <<
2284 default y 1251 default y
2285 help <<
2286 Randomizes the location of the modu <<
2287 covering the core kernel. This way, <<
2288 to leak information about the locat <<
2289 but it does imply that function cal <<
2290 kernel will need to be resolved via <<
2291 <<
2292 When this option is not set, the mo <<
2293 a limited range that contains the [ <<
2294 core kernel, so branch relocations <<
2295 the region is exhausted. In this pa <<
2296 exhaustion, modules might be able t <<
2297 <<
2298 config CC_HAVE_STACKPROTECTOR_SYSREG <<
2299 def_bool $(cc-option,-mstack-protecto <<
2300 <<
2301 config STACKPROTECTOR_PER_TASK <<
2302 def_bool y <<
2303 depends on STACKPROTECTOR && CC_HAVE_ <<
2304 1252
2305 config UNWIND_PATCH_PAC_INTO_SCS !! 1253 config X86_BIOS_REBOOT
2306 bool "Enable shadow call stack dynami !! 1254 bool
2307 # needs Clang with https://github.com !! 1255 depends on !(X86_VISWS || X86_VOYAGER)
2308 depends on CC_IS_CLANG && CLANG_VERSI <<
2309 depends on ARM64_PTR_AUTH_KERNEL && C <<
2310 depends on SHADOW_CALL_STACK <<
2311 select UNWIND_TABLES <<
2312 select DYNAMIC_SCS <<
2313 <<
2314 config ARM64_CONTPTE <<
2315 bool "Contiguous PTE mappings for use <<
2316 depends on TRANSPARENT_HUGEPAGE <<
2317 default y 1256 default y
2318 help <<
2319 When enabled, user mappings are con <<
2320 bit, for any mappings that meet the <<
2321 This reduces TLB pressure and impro <<
2322 <<
2323 endmenu # "Kernel Features" <<
2324 <<
2325 menu "Boot options" <<
2326 <<
2327 config ARM64_ACPI_PARKING_PROTOCOL <<
2328 bool "Enable support for the ARM64 AC <<
2329 depends on ACPI <<
2330 help <<
2331 Enable support for the ARM64 ACPI p <<
2332 the kernel will not allow booting t <<
2333 protocol even if the corresponding <<
2334 MADT table. <<
2335 1257
2336 config CMDLINE !! 1258 config X86_TRAMPOLINE
2337 string "Default kernel command string <<
2338 default "" <<
2339 help <<
2340 Provide a set of default command-li <<
2341 entering them here. As a minimum, y <<
2342 root device (e.g. root=/dev/nfs). <<
2343 <<
2344 choice <<
2345 prompt "Kernel command line type" <<
2346 depends on CMDLINE != "" <<
2347 default CMDLINE_FROM_BOOTLOADER <<
2348 help <<
2349 Choose how the kernel will handle t <<
2350 command line string. <<
2351 <<
2352 config CMDLINE_FROM_BOOTLOADER <<
2353 bool "Use bootloader kernel arguments <<
2354 help <<
2355 Uses the command-line options passe <<
2356 the boot loader doesn't provide any <<
2357 string provided in CMDLINE will be <<
2358 <<
2359 config CMDLINE_FORCE <<
2360 bool "Always use the default kernel c <<
2361 help <<
2362 Always use the default kernel comma <<
2363 loader passes other arguments to th <<
2364 This is useful if you cannot or don <<
2365 command-line options your boot load <<
2366 <<
2367 endchoice <<
2368 <<
2369 config EFI_STUB <<
2370 bool 1259 bool
2371 !! 1260 depends on SMP || X86_VISWS
2372 config EFI <<
2373 bool "UEFI runtime support" <<
2374 depends on OF && !CPU_BIG_ENDIAN <<
2375 depends on KERNEL_MODE_NEON <<
2376 select ARCH_SUPPORTS_ACPI <<
2377 select LIBFDT <<
2378 select UCS2_STRING <<
2379 select EFI_PARAMS_FROM_FDT <<
2380 select EFI_RUNTIME_WRAPPERS <<
2381 select EFI_STUB <<
2382 select EFI_GENERIC_STUB <<
2383 imply IMA_SECURE_AND_OR_TRUSTED_BOOT <<
2384 default y 1261 default y
2385 help <<
2386 This option provides support for ru <<
2387 by UEFI firmware (such as non-volat <<
2388 clock, and platform reset). A UEFI <<
2389 allow the kernel to be booted as an <<
2390 is only useful on systems that have <<
2391 1262
2392 config COMPRESSED_INSTALL !! 1263 config PC
2393 bool "Install compressed image by def !! 1264 bool
2394 help !! 1265 depends on X86 && !EMBEDDED
2395 This makes the regular "make instal <<
2396 image we built, not the legacy unco <<
2397 <<
2398 You can check that a compressed ima <<
2399 "make zinstall" first, and verifyin <<
2400 in your environment before making " <<
2401 you. <<
2402 <<
2403 config DMI <<
2404 bool "Enable support for SMBIOS (DMI) <<
2405 depends on EFI <<
2406 default y 1266 default y
2407 help <<
2408 This enables SMBIOS/DMI feature for <<
2409 <<
2410 This option is only useful on syste <<
2411 However, even with this option, the <<
2412 continue to boot on existing non-UE <<
2413 <<
2414 endmenu # "Boot options" <<
2415 <<
2416 menu "Power management options" <<
2417 <<
2418 source "kernel/power/Kconfig" <<
2419 <<
2420 config ARCH_HIBERNATION_POSSIBLE <<
2421 def_bool y <<
2422 depends on CPU_PM <<
2423 <<
2424 config ARCH_HIBERNATION_HEADER <<
2425 def_bool y <<
2426 depends on HIBERNATION <<
2427 <<
2428 config ARCH_SUSPEND_POSSIBLE <<
2429 def_bool y <<
2430 <<
2431 endmenu # "Power management options" <<
2432 <<
2433 menu "CPU Power Management" <<
2434 <<
2435 source "drivers/cpuidle/Kconfig" <<
2436 <<
2437 source "drivers/cpufreq/Kconfig" <<
2438 <<
2439 endmenu # "CPU Power Management" <<
2440 <<
2441 source "drivers/acpi/Kconfig" <<
2442 <<
2443 source "arch/arm64/kvm/Kconfig" <<
2444 <<
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