1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 // Copyright (C) 2016 ARM Ltd.
3 // based on the Allwinner H3 dtsi:
4 // Copyright (C) 2015 Jens Kuske <jenskuske@
5
6 #include <dt-bindings/clock/sun50i-a64-ccu.h>
7 #include <dt-bindings/clock/sun6i-rtc.h>
8 #include <dt-bindings/clock/sun8i-de2.h>
9 #include <dt-bindings/clock/sun8i-r-ccu.h>
10 #include <dt-bindings/interrupt-controller/arm
11 #include <dt-bindings/reset/sun50i-a64-ccu.h>
12 #include <dt-bindings/reset/sun8i-de2.h>
13 #include <dt-bindings/reset/sun8i-r-ccu.h>
14 #include <dt-bindings/thermal/thermal.h>
15
16 / {
17 interrupt-parent = <&gic>;
18 #address-cells = <1>;
19 #size-cells = <1>;
20
21 chosen {
22 #address-cells = <1>;
23 #size-cells = <1>;
24 ranges;
25
26 simplefb_lcd: framebuffer-lcd
27 compatible = "allwinne
28 "simple-f
29 allwinner,pipeline = "
30 clocks = <&ccu CLK_TCO
31 <&display_clo
32 status = "disabled";
33 };
34
35 simplefb_hdmi: framebuffer-hdm
36 compatible = "allwinne
37 "simple-f
38 allwinner,pipeline = "
39 clocks = <&display_clo
40 <&ccu CLK_TCO
41 status = "disabled";
42 };
43 };
44
45 cpus {
46 #address-cells = <1>;
47 #size-cells = <0>;
48
49 cpu0: cpu@0 {
50 compatible = "arm,cort
51 device_type = "cpu";
52 reg = <0>;
53 enable-method = "psci"
54 clocks = <&ccu CLK_CPU
55 clock-names = "cpu";
56 #cooling-cells = <2>;
57 i-cache-size = <0x8000
58 i-cache-line-size = <6
59 i-cache-sets = <256>;
60 d-cache-size = <0x8000
61 d-cache-line-size = <6
62 d-cache-sets = <128>;
63 next-level-cache = <&l
64 };
65
66 cpu1: cpu@1 {
67 compatible = "arm,cort
68 device_type = "cpu";
69 reg = <1>;
70 enable-method = "psci"
71 clocks = <&ccu CLK_CPU
72 clock-names = "cpu";
73 #cooling-cells = <2>;
74 i-cache-size = <0x8000
75 i-cache-line-size = <6
76 i-cache-sets = <256>;
77 d-cache-size = <0x8000
78 d-cache-line-size = <6
79 d-cache-sets = <128>;
80 next-level-cache = <&l
81 };
82
83 cpu2: cpu@2 {
84 compatible = "arm,cort
85 device_type = "cpu";
86 reg = <2>;
87 enable-method = "psci"
88 clocks = <&ccu CLK_CPU
89 clock-names = "cpu";
90 #cooling-cells = <2>;
91 i-cache-size = <0x8000
92 i-cache-line-size = <6
93 i-cache-sets = <256>;
94 d-cache-size = <0x8000
95 d-cache-line-size = <6
96 d-cache-sets = <128>;
97 next-level-cache = <&l
98 };
99
100 cpu3: cpu@3 {
101 compatible = "arm,cort
102 device_type = "cpu";
103 reg = <3>;
104 enable-method = "psci"
105 clocks = <&ccu CLK_CPU
106 clock-names = "cpu";
107 #cooling-cells = <2>;
108 i-cache-size = <0x8000
109 i-cache-line-size = <6
110 i-cache-sets = <256>;
111 d-cache-size = <0x8000
112 d-cache-line-size = <6
113 d-cache-sets = <128>;
114 next-level-cache = <&l
115 };
116
117 l2_cache: l2-cache {
118 compatible = "cache";
119 cache-level = <2>;
120 cache-unified;
121 cache-size = <0x80000>
122 cache-line-size = <64>
123 cache-sets = <512>;
124 };
125 };
126
127 de: display-engine {
128 compatible = "allwinner,sun50i
129 allwinner,pipelines = <&mixer0
130 <&mixer1
131 status = "disabled";
132 };
133
134 gpu_opp_table: opp-table-gpu {
135 compatible = "operating-points
136
137 opp-432000000 {
138 opp-hz = /bits/ 64 <43
139 };
140 };
141
142 osc24M: osc24M-clk {
143 #clock-cells = <0>;
144 compatible = "fixed-clock";
145 clock-frequency = <24000000>;
146 clock-output-names = "osc24M";
147 };
148
149 osc32k: osc32k-clk {
150 #clock-cells = <0>;
151 compatible = "fixed-clock";
152 clock-frequency = <32768>;
153 clock-output-names = "ext-osc3
154 };
155
156 pmu {
157 compatible = "arm,cortex-a53-p
158 interrupts = <GIC_SPI 116 IRQ_
159 <GIC_SPI 117 IRQ_
160 <GIC_SPI 118 IRQ_
161 <GIC_SPI 119 IRQ_
162 interrupt-affinity = <&cpu0>,
163 };
164
165 psci {
166 compatible = "arm,psci-0.2";
167 method = "smc";
168 };
169
170 sound: sound {
171 #address-cells = <1>;
172 #size-cells = <0>;
173 compatible = "simple-audio-car
174 simple-audio-card,name = "sun5
175 simple-audio-card,aux-devs = <
176 simple-audio-card,routing =
177 "Left DAC", "D
178 "Right DAC", "
179 "ADCL", "Left
180 "ADCR", "Right
181 status = "disabled";
182
183 simple-audio-card,dai-link@0 {
184 format = "i2s";
185 frame-master = <&link0
186 bitclock-master = <&li
187 mclk-fs = <128>;
188
189 link0_cpu: cpu {
190 sound-dai = <&
191 };
192
193 link0_codec: codec {
194 sound-dai = <&
195 };
196 };
197 };
198
199 timer {
200 compatible = "arm,armv8-timer"
201 allwinner,erratum-unknown1;
202 arm,no-tick-in-suspend;
203 interrupts = <GIC_PPI 13
204 (GIC_CPU_MASK_SIMPLE(4
205 <GIC_PPI 14
206 (GIC_CPU_MASK_SIMPLE(4
207 <GIC_PPI 11
208 (GIC_CPU_MASK_SIMPLE(4
209 <GIC_PPI 10
210 (GIC_CPU_MASK_SIMPLE(4
211 };
212
213 thermal-zones {
214 cpu_thermal: cpu0-thermal {
215 /* milliseconds */
216 polling-delay-passive
217 polling-delay = <0>;
218 thermal-sensors = <&th
219
220 cooling-maps {
221 map0 {
222 trip =
223 coolin
224
225
226
227 };
228 map1 {
229 trip =
230 coolin
231
232
233
234 };
235 };
236
237 trips {
238 cpu_alert0: cp
239 /* mil
240 temper
241 hyster
242 type =
243 };
244
245 cpu_alert1: cp
246 /* mil
247 temper
248 hyster
249 type =
250 };
251
252 cpu_crit: cpu-
253 /* mil
254 temper
255 hyster
256 type =
257 };
258 };
259 };
260
261 gpu0_thermal: gpu0-thermal {
262 /* milliseconds */
263 polling-delay-passive
264 polling-delay = <0>;
265 thermal-sensors = <&th
266 };
267
268 gpu1_thermal: gpu1-thermal {
269 /* milliseconds */
270 polling-delay-passive
271 polling-delay = <0>;
272 thermal-sensors = <&th
273 };
274 };
275
276 soc {
277 compatible = "simple-bus";
278 #address-cells = <1>;
279 #size-cells = <1>;
280 ranges;
281
282 bus@1000000 {
283 compatible = "allwinne
284 reg = <0x1000000 0x400
285 allwinner,sram = <&de2
286 #address-cells = <1>;
287 #size-cells = <1>;
288 ranges = <0 0x1000000
289
290 display_clocks: clock@
291 compatible = "
292 reg = <0x0 0x1
293 clocks = <&ccu
294 <&ccu
295 clock-names =
296
297 resets = <&ccu
298 #clock-cells =
299 #reset-cells =
300 };
301
302 rotate: rotate@20000 {
303 compatible = "
304 "
305 reg = <0x20000
306 interrupts = <
307 clocks = <&dis
308 <&dis
309 clock-names =
310
311 resets = <&dis
312 };
313
314 mixer0: mixer@100000 {
315 compatible = "
316 reg = <0x10000
317 clocks = <&dis
318 <&dis
319 clock-names =
320
321 resets = <&dis
322
323 ports {
324 #addre
325 #size-
326
327 mixer0
328
329
330
331
332
333
334
335
336
337
338
339
340
341 };
342 };
343 };
344
345 mixer1: mixer@200000 {
346 compatible = "
347 reg = <0x20000
348 clocks = <&dis
349 <&dis
350 clock-names =
351
352 resets = <&dis
353
354 ports {
355 #addre
356 #size-
357
358 mixer1
359
360
361
362
363
364
365
366
367
368
369
370
371
372 };
373 };
374 };
375 };
376
377 syscon: syscon@1c00000 {
378 compatible = "allwinne
379 reg = <0x01c00000 0x10
380 #address-cells = <1>;
381 #size-cells = <1>;
382 ranges;
383
384 sram_c: sram@18000 {
385 compatible = "
386 reg = <0x00018
387 #address-cells
388 #size-cells =
389 ranges = <0 0x
390
391 de2_sram: sram
392 compat
393 reg =
394 };
395 };
396
397 sram_c1: sram@1d00000
398 compatible = "
399 reg = <0x01d00
400 #address-cells
401 #size-cells =
402 ranges = <0 0x
403
404 ve_sram: sram-
405 compat
406
407 reg =
408 };
409 };
410 };
411
412 dma: dma-controller@1c02000 {
413 compatible = "allwinne
414 reg = <0x01c02000 0x10
415 interrupts = <GIC_SPI
416 clocks = <&ccu CLK_BUS
417 dma-channels = <8>;
418 dma-requests = <27>;
419 resets = <&ccu RST_BUS
420 #dma-cells = <1>;
421 };
422
423 tcon0: lcd-controller@1c0c000
424 compatible = "allwinne
425 "allwinne
426 reg = <0x01c0c000 0x10
427 interrupts = <GIC_SPI
428 clocks = <&ccu CLK_BUS
429 clock-names = "ahb", "
430 clock-output-names = "
431 #clock-cells = <0>;
432 resets = <&ccu RST_BUS
433 reset-names = "lcd", "
434
435 ports {
436 #address-cells
437 #size-cells =
438
439 tcon0_in: port
440 #addre
441 #size-
442 reg =
443
444 tcon0_
445
446
447 };
448
449 tcon0_
450
451
452 };
453 };
454
455 tcon0_out: por
456 #addre
457 #size-
458 reg =
459
460 tcon0_
461
462
463
464 };
465 };
466 };
467 };
468
469 tcon1: lcd-controller@1c0d000
470 compatible = "allwinne
471 "allwinne
472 reg = <0x01c0d000 0x10
473 interrupts = <GIC_SPI
474 clocks = <&ccu CLK_BUS
475 clock-names = "ahb", "
476 resets = <&ccu RST_BUS
477 reset-names = "lcd";
478
479 ports {
480 #address-cells
481 #size-cells =
482
483 tcon1_in: port
484 #addre
485 #size-
486 reg =
487
488 tcon1_
489
490
491 };
492
493 tcon1_
494
495
496 };
497 };
498
499 tcon1_out: por
500 #addre
501 #size-
502 reg =
503
504 tcon1_
505
506
507 };
508 };
509 };
510 };
511
512 video-codec@1c0e000 {
513 compatible = "allwinne
514 reg = <0x01c0e000 0x10
515 clocks = <&ccu CLK_BUS
516 <&ccu CLK_DRA
517 clock-names = "ahb", "
518 resets = <&ccu RST_BUS
519 interrupts = <GIC_SPI
520 allwinner,sram = <&ve_
521 };
522
523 mmc0: mmc@1c0f000 {
524 compatible = "allwinne
525 reg = <0x01c0f000 0x10
526 clocks = <&ccu CLK_BUS
527 clock-names = "ahb", "
528 resets = <&ccu RST_BUS
529 reset-names = "ahb";
530 interrupts = <GIC_SPI
531 max-frequency = <15000
532 status = "disabled";
533 #address-cells = <1>;
534 #size-cells = <0>;
535 };
536
537 mmc1: mmc@1c10000 {
538 compatible = "allwinne
539 reg = <0x01c10000 0x10
540 clocks = <&ccu CLK_BUS
541 clock-names = "ahb", "
542 resets = <&ccu RST_BUS
543 reset-names = "ahb";
544 interrupts = <GIC_SPI
545 max-frequency = <15000
546 status = "disabled";
547 #address-cells = <1>;
548 #size-cells = <0>;
549 };
550
551 mmc2: mmc@1c11000 {
552 compatible = "allwinne
553 reg = <0x01c11000 0x10
554 clocks = <&ccu CLK_BUS
555 clock-names = "ahb", "
556 resets = <&ccu RST_BUS
557 reset-names = "ahb";
558 interrupts = <GIC_SPI
559 max-frequency = <15000
560 status = "disabled";
561 #address-cells = <1>;
562 #size-cells = <0>;
563 };
564
565 sid: eeprom@1c14000 {
566 compatible = "allwinne
567 reg = <0x1c14000 0x400
568 #address-cells = <1>;
569 #size-cells = <1>;
570
571 ths_calibration: therm
572 reg = <0x34 0x
573 };
574 };
575
576 crypto: crypto@1c15000 {
577 compatible = "allwinne
578 reg = <0x01c15000 0x10
579 interrupts = <GIC_SPI
580 clocks = <&ccu CLK_BUS
581 clock-names = "bus", "
582 resets = <&ccu RST_BUS
583 };
584
585 msgbox: mailbox@1c17000 {
586 compatible = "allwinne
587 "allwinne
588 reg = <0x01c17000 0x10
589 clocks = <&ccu CLK_BUS
590 resets = <&ccu RST_BUS
591 interrupts = <GIC_SPI
592 #mbox-cells = <1>;
593 };
594
595 usb_otg: usb@1c19000 {
596 compatible = "allwinne
597 reg = <0x01c19000 0x04
598 clocks = <&ccu CLK_BUS
599 resets = <&ccu RST_BUS
600 interrupts = <GIC_SPI
601 interrupt-names = "mc"
602 phys = <&usbphy 0>;
603 phy-names = "usb";
604 extcon = <&usbphy 0>;
605 dr_mode = "otg";
606 status = "disabled";
607 };
608
609 usbphy: phy@1c19400 {
610 compatible = "allwinne
611 reg = <0x01c19400 0x14
612 <0x01c1a800 0x4>
613 <0x01c1b800 0x4>
614 reg-names = "phy_ctrl"
615 "pmu0",
616 "pmu1";
617 clocks = <&ccu CLK_USB
618 <&ccu CLK_USB
619 clock-names = "usb0_ph
620 "usb1_ph
621 resets = <&ccu RST_USB
622 <&ccu RST_USB
623 reset-names = "usb0_re
624 "usb1_re
625 status = "disabled";
626 #phy-cells = <1>;
627 };
628
629 ehci0: usb@1c1a000 {
630 compatible = "allwinne
631 reg = <0x01c1a000 0x10
632 interrupts = <GIC_SPI
633 clocks = <&ccu CLK_BUS
634 <&ccu CLK_BUS
635 <&ccu CLK_USB
636 resets = <&ccu RST_BUS
637 <&ccu RST_BUS
638 phys = <&usbphy 0>;
639 phy-names = "usb";
640 status = "disabled";
641 };
642
643 ohci0: usb@1c1a400 {
644 compatible = "allwinne
645 reg = <0x01c1a400 0x10
646 interrupts = <GIC_SPI
647 clocks = <&ccu CLK_BUS
648 <&ccu CLK_USB
649 resets = <&ccu RST_BUS
650 phys = <&usbphy 0>;
651 phy-names = "usb";
652 status = "disabled";
653 };
654
655 ehci1: usb@1c1b000 {
656 compatible = "allwinne
657 reg = <0x01c1b000 0x10
658 interrupts = <GIC_SPI
659 clocks = <&ccu CLK_BUS
660 <&ccu CLK_BUS
661 <&ccu CLK_USB
662 resets = <&ccu RST_BUS
663 <&ccu RST_BUS
664 phys = <&usbphy 1>;
665 phy-names = "usb";
666 status = "disabled";
667 };
668
669 ohci1: usb@1c1b400 {
670 compatible = "allwinne
671 reg = <0x01c1b400 0x10
672 interrupts = <GIC_SPI
673 clocks = <&ccu CLK_BUS
674 <&ccu CLK_USB
675 resets = <&ccu RST_BUS
676 phys = <&usbphy 1>;
677 phy-names = "usb";
678 status = "disabled";
679 };
680
681 ccu: clock@1c20000 {
682 compatible = "allwinne
683 reg = <0x01c20000 0x40
684 clocks = <&osc24M>, <&
685 clock-names = "hosc",
686 #clock-cells = <1>;
687 #reset-cells = <1>;
688 };
689
690 pio: pinctrl@1c20800 {
691 compatible = "allwinne
692 reg = <0x01c20800 0x40
693 interrupt-parent = <&r
694 interrupts = <GIC_SPI
695 <GIC_SPI
696 <GIC_SPI
697 clocks = <&ccu CLK_BUS
698 <&rtc CLK_OSC
699 clock-names = "apb", "
700 gpio-controller;
701 #gpio-cells = <3>;
702 interrupt-controller;
703 #interrupt-cells = <3>
704
705 /omit-if-no-ref/
706 aif2_pins: aif2-pins {
707 pins = "PB4",
708 function = "ai
709 };
710
711 /omit-if-no-ref/
712 aif3_pins: aif3-pins {
713 pins = "PG10",
714 function = "ai
715 };
716
717 csi_pins: csi-pins {
718 pins = "PE0",
719 "PE7",
720 function = "cs
721 };
722
723 /omit-if-no-ref/
724 csi_mclk_pin: csi-mclk
725 pins = "PE1";
726 function = "cs
727 };
728
729 i2c0_pins: i2c0-pins {
730 pins = "PH0",
731 function = "i2
732 };
733
734 i2c1_pins: i2c1-pins {
735 pins = "PH2",
736 function = "i2
737 };
738
739 i2c2_pins: i2c2-pins {
740 pins = "PE14",
741 function = "i2
742 };
743
744 /omit-if-no-ref/
745 lcd_rgb666_pins: lcd-r
746 pins = "PD0",
747 "PD5",
748 "PD10",
749 "PD14",
750 "PD18",
751 function = "lc
752 };
753
754 mmc0_pins: mmc0-pins {
755 pins = "PF0",
756 "PF4",
757 function = "mm
758 drive-strength
759 bias-pull-up;
760 };
761
762 mmc1_pins: mmc1-pins {
763 pins = "PG0",
764 "PG4",
765 function = "mm
766 drive-strength
767 bias-pull-up;
768 };
769
770 mmc2_pins: mmc2-pins {
771 pins = "PC5",
772 "PC10",
773 "PC14",
774 function = "mm
775 drive-strength
776 bias-pull-up;
777 };
778
779 mmc2_ds_pin: mmc2-ds-p
780 pins = "PC1";
781 function = "mm
782 drive-strength
783 bias-pull-up;
784 };
785
786 pwm_pin: pwm-pin {
787 pins = "PD22";
788 function = "pw
789 };
790
791 rmii_pins: rmii-pins {
792 pins = "PD10",
793 "PD18",
794 function = "em
795 drive-strength
796 };
797
798 rgmii_pins: rgmii-pins
799 pins = "PD8",
800 "PD13",
801 "PD19",
802 function = "em
803 drive-strength
804 };
805
806 spdif_tx_pin: spdif-tx
807 pins = "PH8";
808 function = "sp
809 };
810
811 spi0_pins: spi0-pins {
812 pins = "PC0",
813 function = "sp
814 };
815
816 spi1_pins: spi1-pins {
817 pins = "PD0",
818 function = "sp
819 };
820
821 uart0_pb_pins: uart0-p
822 pins = "PB8",
823 function = "ua
824 };
825
826 uart1_pins: uart1-pins
827 pins = "PG6",
828 function = "ua
829 };
830
831 uart1_rts_cts_pins: ua
832 pins = "PG8",
833 function = "ua
834 };
835
836 uart2_pins: uart2-pins
837 pins = "PB0",
838 function = "ua
839 };
840
841 uart3_pins: uart3-pins
842 pins = "PD0",
843 function = "ua
844 };
845
846 uart4_pins: uart4-pins
847 pins = "PD2",
848 function = "ua
849 };
850
851 uart4_rts_cts_pins: ua
852 pins = "PD4",
853 function = "ua
854 };
855 };
856
857 timer@1c20c00 {
858 compatible = "allwinne
859 "allwinne
860 reg = <0x01c20c00 0xa0
861 interrupts = <GIC_SPI
862 <GIC_SPI
863 clocks = <&osc24M>;
864 };
865
866 wdt0: watchdog@1c20ca0 {
867 compatible = "allwinne
868 "allwinne
869 reg = <0x01c20ca0 0x20
870 interrupts = <GIC_SPI
871 clocks = <&osc24M>;
872 };
873
874 spdif: spdif@1c21000 {
875 #sound-dai-cells = <0>
876 compatible = "allwinne
877 "allwinne
878 reg = <0x01c21000 0x40
879 interrupts = <GIC_SPI
880 clocks = <&ccu CLK_BUS
881 resets = <&ccu RST_BUS
882 clock-names = "apb", "
883 dmas = <&dma 2>;
884 dma-names = "tx";
885 pinctrl-names = "defau
886 pinctrl-0 = <&spdif_tx
887 status = "disabled";
888 };
889
890 lradc: lradc@1c21800 {
891 compatible = "allwinne
892 "allwinne
893 reg = <0x01c21800 0x40
894 interrupt-parent = <&r
895 interrupts = <GIC_SPI
896 status = "disabled";
897 };
898
899 i2s0: i2s@1c22000 {
900 #sound-dai-cells = <0>
901 compatible = "allwinne
902 "allwinne
903 reg = <0x01c22000 0x40
904 interrupts = <GIC_SPI
905 clocks = <&ccu CLK_BUS
906 clock-names = "apb", "
907 resets = <&ccu RST_BUS
908 dma-names = "rx", "tx"
909 dmas = <&dma 3>, <&dma
910 status = "disabled";
911 };
912
913 i2s1: i2s@1c22400 {
914 #sound-dai-cells = <0>
915 compatible = "allwinne
916 "allwinne
917 reg = <0x01c22400 0x40
918 interrupts = <GIC_SPI
919 clocks = <&ccu CLK_BUS
920 clock-names = "apb", "
921 resets = <&ccu RST_BUS
922 dma-names = "rx", "tx"
923 dmas = <&dma 4>, <&dma
924 status = "disabled";
925 };
926
927 i2s2: i2s@1c22800 {
928 #sound-dai-cells = <0>
929 compatible = "allwinne
930 "allwinne
931 reg = <0x01c22800 0x40
932 interrupts = <GIC_SPI
933 clocks = <&ccu CLK_BUS
934 clock-names = "apb", "
935 resets = <&ccu RST_BUS
936 dma-names = "rx", "tx"
937 dmas = <&dma 27>, <&dm
938 status = "disabled";
939 };
940
941 dai: dai@1c22c00 {
942 #sound-dai-cells = <0>
943 compatible = "allwinne
944 reg = <0x01c22c00 0x20
945 interrupts = <GIC_SPI
946 clocks = <&ccu CLK_BUS
947 clock-names = "apb", "
948 resets = <&ccu RST_BUS
949 dmas = <&dma 15>, <&dm
950 dma-names = "rx", "tx"
951 status = "disabled";
952 };
953
954 codec: codec@1c22e00 {
955 #sound-dai-cells = <1>
956 compatible = "allwinne
957 "allwinne
958 reg = <0x01c22e00 0x60
959 interrupts = <GIC_SPI
960 clocks = <&ccu CLK_BUS
961 clock-names = "bus", "
962 status = "disabled";
963 };
964
965 ths: thermal-sensor@1c25000 {
966 compatible = "allwinne
967 reg = <0x01c25000 0x10
968 clocks = <&ccu CLK_BUS
969 clock-names = "bus", "
970 interrupts = <GIC_SPI
971 resets = <&ccu RST_BUS
972 nvmem-cells = <&ths_ca
973 nvmem-cell-names = "ca
974 #thermal-sensor-cells
975 };
976
977 uart0: serial@1c28000 {
978 compatible = "snps,dw-
979 reg = <0x01c28000 0x40
980 interrupts = <GIC_SPI
981 reg-shift = <2>;
982 reg-io-width = <4>;
983 clocks = <&ccu CLK_BUS
984 resets = <&ccu RST_BUS
985 status = "disabled";
986 };
987
988 uart1: serial@1c28400 {
989 compatible = "snps,dw-
990 reg = <0x01c28400 0x40
991 interrupts = <GIC_SPI
992 reg-shift = <2>;
993 reg-io-width = <4>;
994 clocks = <&ccu CLK_BUS
995 resets = <&ccu RST_BUS
996 status = "disabled";
997 };
998
999 uart2: serial@1c28800 {
1000 compatible = "snps,dw
1001 reg = <0x01c28800 0x4
1002 interrupts = <GIC_SPI
1003 reg-shift = <2>;
1004 reg-io-width = <4>;
1005 clocks = <&ccu CLK_BU
1006 resets = <&ccu RST_BU
1007 status = "disabled";
1008 };
1009
1010 uart3: serial@1c28c00 {
1011 compatible = "snps,dw
1012 reg = <0x01c28c00 0x4
1013 interrupts = <GIC_SPI
1014 reg-shift = <2>;
1015 reg-io-width = <4>;
1016 clocks = <&ccu CLK_BU
1017 resets = <&ccu RST_BU
1018 status = "disabled";
1019 };
1020
1021 uart4: serial@1c29000 {
1022 compatible = "snps,dw
1023 reg = <0x01c29000 0x4
1024 interrupts = <GIC_SPI
1025 reg-shift = <2>;
1026 reg-io-width = <4>;
1027 clocks = <&ccu CLK_BU
1028 resets = <&ccu RST_BU
1029 status = "disabled";
1030 };
1031
1032 i2c0: i2c@1c2ac00 {
1033 compatible = "allwinn
1034 reg = <0x01c2ac00 0x4
1035 interrupts = <GIC_SPI
1036 clocks = <&ccu CLK_BU
1037 resets = <&ccu RST_BU
1038 pinctrl-names = "defa
1039 pinctrl-0 = <&i2c0_pi
1040 status = "disabled";
1041 #address-cells = <1>;
1042 #size-cells = <0>;
1043 };
1044
1045 i2c1: i2c@1c2b000 {
1046 compatible = "allwinn
1047 reg = <0x01c2b000 0x4
1048 interrupts = <GIC_SPI
1049 clocks = <&ccu CLK_BU
1050 resets = <&ccu RST_BU
1051 pinctrl-names = "defa
1052 pinctrl-0 = <&i2c1_pi
1053 status = "disabled";
1054 #address-cells = <1>;
1055 #size-cells = <0>;
1056 };
1057
1058 i2c2: i2c@1c2b400 {
1059 compatible = "allwinn
1060 reg = <0x01c2b400 0x4
1061 interrupts = <GIC_SPI
1062 clocks = <&ccu CLK_BU
1063 resets = <&ccu RST_BU
1064 pinctrl-names = "defa
1065 pinctrl-0 = <&i2c2_pi
1066 status = "disabled";
1067 #address-cells = <1>;
1068 #size-cells = <0>;
1069 };
1070
1071 spi0: spi@1c68000 {
1072 compatible = "allwinn
1073 reg = <0x01c68000 0x1
1074 interrupts = <GIC_SPI
1075 clocks = <&ccu CLK_BU
1076 clock-names = "ahb",
1077 dmas = <&dma 23>, <&d
1078 dma-names = "rx", "tx
1079 pinctrl-names = "defa
1080 pinctrl-0 = <&spi0_pi
1081 resets = <&ccu RST_BU
1082 status = "disabled";
1083 num-cs = <1>;
1084 #address-cells = <1>;
1085 #size-cells = <0>;
1086 };
1087
1088 spi1: spi@1c69000 {
1089 compatible = "allwinn
1090 reg = <0x01c69000 0x1
1091 interrupts = <GIC_SPI
1092 clocks = <&ccu CLK_BU
1093 clock-names = "ahb",
1094 dmas = <&dma 24>, <&d
1095 dma-names = "rx", "tx
1096 pinctrl-names = "defa
1097 pinctrl-0 = <&spi1_pi
1098 resets = <&ccu RST_BU
1099 status = "disabled";
1100 num-cs = <1>;
1101 #address-cells = <1>;
1102 #size-cells = <0>;
1103 };
1104
1105 emac: ethernet@1c30000 {
1106 compatible = "allwinn
1107 syscon = <&syscon>;
1108 reg = <0x01c30000 0x1
1109 interrupts = <GIC_SPI
1110 interrupt-names = "ma
1111 resets = <&ccu RST_BU
1112 reset-names = "stmmac
1113 clocks = <&ccu CLK_BU
1114 clock-names = "stmmac
1115 status = "disabled";
1116
1117 mdio: mdio {
1118 compatible =
1119 #address-cell
1120 #size-cells =
1121 };
1122 };
1123
1124 mali: gpu@1c40000 {
1125 compatible = "allwinn
1126 reg = <0x01c40000 0x1
1127 interrupts = <GIC_SPI
1128 <GIC_SPI
1129 <GIC_SPI
1130 <GIC_SPI
1131 <GIC_SPI
1132 <GIC_SPI
1133 <GIC_SPI
1134 interrupt-names = "gp
1135 "gp
1136 "pp
1137 "pp
1138 "pp
1139 "pp
1140 "pm
1141 clocks = <&ccu CLK_BU
1142 clock-names = "bus",
1143 resets = <&ccu RST_BU
1144 operating-points-v2 =
1145 };
1146
1147 gic: interrupt-controller@1c8
1148 compatible = "arm,gic
1149 reg = <0x01c81000 0x1
1150 <0x01c82000 0x2
1151 <0x01c84000 0x2
1152 <0x01c86000 0x2
1153 interrupts = <GIC_PPI
1154 interrupt-controller;
1155 #interrupt-cells = <3
1156 };
1157
1158 pwm: pwm@1c21400 {
1159 compatible = "allwinn
1160 "allwinn
1161 reg = <0x01c21400 0x4
1162 clocks = <&osc24M>;
1163 pinctrl-names = "defa
1164 pinctrl-0 = <&pwm_pin
1165 #pwm-cells = <3>;
1166 status = "disabled";
1167 };
1168
1169 mbus: dram-controller@1c62000
1170 compatible = "allwinn
1171 reg = <0x01c62000 0x1
1172 <0x01c63000 0x1
1173 reg-names = "mbus", "
1174 clocks = <&ccu CLK_MB
1175 <&ccu CLK_DR
1176 <&ccu CLK_BU
1177 clock-names = "mbus",
1178 interrupts = <GIC_SPI
1179 #address-cells = <1>;
1180 #size-cells = <1>;
1181 dma-ranges = <0x00000
1182 #interconnect-cells =
1183 };
1184
1185 csi: csi@1cb0000 {
1186 compatible = "allwinn
1187 reg = <0x01cb0000 0x1
1188 interrupts = <GIC_SPI
1189 clocks = <&ccu CLK_BU
1190 <&ccu CLK_CS
1191 <&ccu CLK_DR
1192 clock-names = "bus",
1193 resets = <&ccu RST_BU
1194 pinctrl-names = "defa
1195 pinctrl-0 = <&csi_pin
1196 status = "disabled";
1197 };
1198
1199 dsi: dsi@1ca0000 {
1200 compatible = "allwinn
1201 reg = <0x01ca0000 0x1
1202 interrupts = <GIC_SPI
1203 clocks = <&ccu CLK_BU
1204 resets = <&ccu RST_BU
1205 phys = <&dphy>;
1206 phy-names = "dphy";
1207 status = "disabled";
1208 #address-cells = <1>;
1209 #size-cells = <0>;
1210
1211 port {
1212 dsi_in_tcon0:
1213 remot
1214 };
1215 };
1216 };
1217
1218 dphy: d-phy@1ca1000 {
1219 compatible = "allwinn
1220 "allwinn
1221 reg = <0x01ca1000 0x1
1222 interrupts = <GIC_SPI
1223 clocks = <&ccu CLK_BU
1224 <&ccu CLK_DS
1225 clock-names = "bus",
1226 resets = <&ccu RST_BU
1227 status = "disabled";
1228 #phy-cells = <0>;
1229 };
1230
1231 deinterlace: deinterlace@1e00
1232 compatible = "allwinn
1233 "allwinn
1234 reg = <0x01e00000 0x2
1235 clocks = <&ccu CLK_BU
1236 <&ccu CLK_DE
1237 <&ccu CLK_DR
1238 clock-names = "bus",
1239 resets = <&ccu RST_BU
1240 interrupts = <GIC_SPI
1241 interconnects = <&mbu
1242 interconnect-names =
1243 };
1244
1245 hdmi: hdmi@1ee0000 {
1246 compatible = "allwinn
1247 "allwinn
1248 reg = <0x01ee0000 0x1
1249 reg-io-width = <1>;
1250 interrupts = <GIC_SPI
1251 clocks = <&ccu CLK_BU
1252 <&ccu CLK_HD
1253 clock-names = "iahb",
1254 resets = <&ccu RST_BU
1255 reset-names = "ctrl";
1256 phys = <&hdmi_phy>;
1257 phy-names = "phy";
1258 status = "disabled";
1259
1260 ports {
1261 #address-cell
1262 #size-cells =
1263
1264 hdmi_in: port
1265 reg =
1266
1267 hdmi_
1268
1269 };
1270 };
1271
1272 hdmi_out: por
1273 reg =
1274 };
1275 };
1276 };
1277
1278 hdmi_phy: hdmi-phy@1ef0000 {
1279 compatible = "allwinn
1280 reg = <0x01ef0000 0x1
1281 clocks = <&ccu CLK_BU
1282 <&ccu CLK_PL
1283 clock-names = "bus",
1284 resets = <&ccu RST_BU
1285 reset-names = "phy";
1286 #phy-cells = <0>;
1287 };
1288
1289 rtc: rtc@1f00000 {
1290 compatible = "allwinn
1291 "allwinn
1292 reg = <0x01f00000 0x4
1293 interrupt-parent = <&
1294 interrupts = <GIC_SPI
1295 <GIC_SPI
1296 clock-output-names =
1297 clocks = <&osc32k>;
1298 #clock-cells = <1>;
1299 };
1300
1301 r_intc: interrupt-controller@
1302 compatible = "allwinn
1303 "allwinn
1304 interrupt-controller;
1305 #interrupt-cells = <3
1306 reg = <0x01f00c00 0x4
1307 interrupts = <GIC_SPI
1308 };
1309
1310 r_ccu: clock@1f01400 {
1311 compatible = "allwinn
1312 reg = <0x01f01400 0x1
1313 clocks = <&osc24M>, <
1314 <&ccu CLK_PL
1315 clock-names = "hosc",
1316 #clock-cells = <1>;
1317 #reset-cells = <1>;
1318 };
1319
1320 codec_analog: codec-analog@1f
1321 compatible = "allwinn
1322 reg = <0x01f015c0 0x4
1323 status = "disabled";
1324 };
1325
1326 r_i2c: i2c@1f02400 {
1327 compatible = "allwinn
1328 "allwinn
1329 reg = <0x01f02400 0x4
1330 interrupts = <GIC_SPI
1331 clocks = <&r_ccu CLK_
1332 resets = <&r_ccu RST_
1333 status = "disabled";
1334 #address-cells = <1>;
1335 #size-cells = <0>;
1336 };
1337
1338 r_ir: ir@1f02000 {
1339 compatible = "allwinn
1340 "allwinn
1341 reg = <0x01f02000 0x4
1342 clocks = <&r_ccu CLK_
1343 clock-names = "apb",
1344 resets = <&r_ccu RST_
1345 interrupts = <GIC_SPI
1346 pinctrl-names = "defa
1347 pinctrl-0 = <&r_ir_rx
1348 status = "disabled";
1349 };
1350
1351 r_pwm: pwm@1f03800 {
1352 compatible = "allwinn
1353 "allwinn
1354 reg = <0x01f03800 0x4
1355 clocks = <&osc24M>;
1356 pinctrl-names = "defa
1357 pinctrl-0 = <&r_pwm_p
1358 #pwm-cells = <3>;
1359 status = "disabled";
1360 };
1361
1362 r_pio: pinctrl@1f02c00 {
1363 compatible = "allwinn
1364 reg = <0x01f02c00 0x4
1365 interrupt-parent = <&
1366 interrupts = <GIC_SPI
1367 clocks = <&r_ccu CLK_
1368 clock-names = "apb",
1369 gpio-controller;
1370 #gpio-cells = <3>;
1371 interrupt-controller;
1372 #interrupt-cells = <3
1373
1374 r_i2c_pl89_pins: r-i2
1375 pins = "PL8",
1376 function = "s
1377 };
1378
1379 r_ir_rx_pin: r-ir-rx-
1380 pins = "PL11"
1381 function = "s
1382 };
1383
1384 r_pwm_pin: r-pwm-pin
1385 pins = "PL10"
1386 function = "s
1387 };
1388
1389 r_rsb_pins: r-rsb-pin
1390 pins = "PL0",
1391 function = "s
1392 };
1393 };
1394
1395 r_rsb: rsb@1f03400 {
1396 compatible = "allwinn
1397 reg = <0x01f03400 0x4
1398 interrupts = <GIC_SPI
1399 clocks = <&r_ccu 6>;
1400 clock-frequency = <30
1401 resets = <&r_ccu 2>;
1402 pinctrl-names = "defa
1403 pinctrl-0 = <&r_rsb_p
1404 status = "disabled";
1405 #address-cells = <1>;
1406 #size-cells = <0>;
1407 };
1408 };
1409 };
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