1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 // Copyright (C) 2016 ARM Ltd.
3
4 #include <arm/allwinner/sunxi-h3-h5.dtsi>
5
6 #include <dt-bindings/thermal/thermal.h>
7
8 / {
9 cpus {
10 #address-cells = <1>;
11 #size-cells = <0>;
12
13 cpu0: cpu@0 {
14 compatible = "arm,cort
15 device_type = "cpu";
16 reg = <0>;
17 enable-method = "psci"
18 clocks = <&ccu CLK_CPU
19 clock-latency-ns = <24
20 #cooling-cells = <2>;
21 };
22
23 cpu1: cpu@1 {
24 compatible = "arm,cort
25 device_type = "cpu";
26 reg = <1>;
27 enable-method = "psci"
28 clocks = <&ccu CLK_CPU
29 clock-latency-ns = <24
30 #cooling-cells = <2>;
31 };
32
33 cpu2: cpu@2 {
34 compatible = "arm,cort
35 device_type = "cpu";
36 reg = <2>;
37 enable-method = "psci"
38 clocks = <&ccu CLK_CPU
39 clock-latency-ns = <24
40 #cooling-cells = <2>;
41 };
42
43 cpu3: cpu@3 {
44 compatible = "arm,cort
45 device_type = "cpu";
46 reg = <3>;
47 enable-method = "psci"
48 clocks = <&ccu CLK_CPU
49 clock-latency-ns = <24
50 #cooling-cells = <2>;
51 };
52 };
53
54 pmu {
55 compatible = "arm,cortex-a53-p
56 interrupts = <GIC_SPI 116 IRQ_
57 <GIC_SPI 117 IRQ_
58 <GIC_SPI 118 IRQ_
59 <GIC_SPI 119 IRQ_
60 interrupt-affinity = <&cpu0>,
61 };
62
63 psci {
64 compatible = "arm,psci-0.2";
65 method = "smc";
66 };
67
68 timer {
69 compatible = "arm,armv8-timer"
70 arm,no-tick-in-suspend;
71 interrupts = <GIC_PPI 13
72 (GIC_CPU_MASK_
73 <GIC_PPI 14
74 (GIC_CPU_MASK_
75 <GIC_PPI 11
76 (GIC_CPU_MASK_
77 <GIC_PPI 10
78 (GIC_CPU_MASK_
79 };
80
81 soc {
82 syscon: system-control@1c00000
83 compatible = "allwinne
84 reg = <0x01c00000 0x10
85 #address-cells = <1>;
86 #size-cells = <1>;
87 ranges;
88
89 sram_c1: sram@18000 {
90 compatible = "
91 reg = <0x00018
92 #address-cells
93 #size-cells =
94 ranges = <0 0x
95
96 ve_sram: sram-
97 compat
98
99 reg =
100 };
101 };
102 };
103
104 video-codec@1c0e000 {
105 compatible = "allwinne
106 reg = <0x01c0e000 0x10
107 clocks = <&ccu CLK_BUS
108 <&ccu CLK_DRA
109 clock-names = "ahb", "
110 resets = <&ccu RST_BUS
111 interrupts = <GIC_SPI
112 allwinner,sram = <&ve_
113 };
114
115 crypto: crypto@1c15000 {
116 compatible = "allwinne
117 reg = <0x01c15000 0x10
118 interrupts = <GIC_SPI
119 clocks = <&ccu CLK_BUS
120 clock-names = "bus", "
121 resets = <&ccu RST_BUS
122 };
123
124 deinterlace: deinterlace@1e000
125 compatible = "allwinne
126 reg = <0x01e00000 0x20
127 clocks = <&ccu CLK_BUS
128 <&ccu CLK_DEI
129 <&ccu CLK_DRA
130 clock-names = "bus", "
131 resets = <&ccu RST_BUS
132 interrupts = <GIC_SPI
133 interconnects = <&mbus
134 interconnect-names = "
135 };
136
137 mali: gpu@1e80000 {
138 compatible = "allwinne
139 reg = <0x01e80000 0x30
140 /*
141 * While the datasheet
142 * PMU, the actual sil
143 * block. Reads all re
144 * ignored.
145 */
146 interrupts = <GIC_SPI
147 <GIC_SPI
148 <GIC_SPI
149 <GIC_SPI
150 <GIC_SPI
151 <GIC_SPI
152 <GIC_SPI
153 <GIC_SPI
154 <GIC_SPI
155 <GIC_SPI
156 <GIC_SPI
157 interrupt-names = "gp"
158 "gpm
159 "pp"
160 "pp0
161 "ppm
162 "pp1
163 "ppm
164 "pp2
165 "ppm
166 "pp3
167 "ppm
168 clocks = <&ccu CLK_BUS
169 clock-names = "bus", "
170 resets = <&ccu RST_BUS
171
172 assigned-clocks = <&cc
173 assigned-clock-rates =
174 };
175
176 ths: thermal-sensor@1c25000 {
177 compatible = "allwinne
178 reg = <0x01c25000 0x40
179 interrupts = <GIC_SPI
180 resets = <&ccu RST_BUS
181 clocks = <&ccu CLK_BUS
182 clock-names = "bus", "
183 nvmem-cells = <&ths_ca
184 nvmem-cell-names = "ca
185 #thermal-sensor-cells
186 };
187 };
188
189 thermal-zones {
190 cpu_thermal: cpu-thermal {
191 polling-delay-passive
192 polling-delay = <0>;
193 thermal-sensors = <&th
194
195 trips {
196 cpu_hot_trip:
197 temper
198 hyster
199 type =
200 };
201
202 cpu_very_hot_t
203 temper
204 hyster
205 type =
206 };
207 };
208
209 cooling-maps {
210 cpu-hot-limit
211 trip =
212 coolin
213
214
215
216 };
217 };
218 };
219
220 gpu-thermal {
221 polling-delay-passive
222 polling-delay = <0>;
223 thermal-sensors = <&th
224 };
225 };
226 };
227
228 &ccu {
229 compatible = "allwinner,sun50i-h5-ccu"
230 };
231
232 &display_clocks {
233 compatible = "allwinner,sun50i-h5-de2-
234 };
235
236 &mbus {
237 compatible = "allwinner,sun50i-h5-mbus
238 };
239
240 &mmc0 {
241 compatible = "allwinner,sun50i-h5-mmc"
242 "allwinner,sun50i-a64-mmc
243 clocks = <&ccu CLK_BUS_MMC0>, <&ccu CL
244 clock-names = "ahb", "mmc";
245 };
246
247 &mmc1 {
248 compatible = "allwinner,sun50i-h5-mmc"
249 "allwinner,sun50i-a64-mmc
250 clocks = <&ccu CLK_BUS_MMC1>, <&ccu CL
251 clock-names = "ahb", "mmc";
252 };
253
254 &mmc2 {
255 compatible = "allwinner,sun50i-h5-emmc
256 "allwinner,sun50i-a64-emm
257 clocks = <&ccu CLK_BUS_MMC2>, <&ccu CL
258 clock-names = "ahb", "mmc";
259 };
260
261 &pio {
262 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVE
263 <GIC_SPI 17 IRQ_TYPE_LEVE
264 <GIC_SPI 23 IRQ_TYPE_LEVE
265 compatible = "allwinner,sun50i-h5-pinc
266 };
267
268 &rtc {
269 compatible = "allwinner,sun50i-h5-rtc"
270 };
271
272 &sid {
273 compatible = "allwinner,sun50i-h5-sid"
274 };
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