1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /*
3 * Copyright (c) 2019 Amlogic, Inc. All rights
4 */
5
6 #include <dt-bindings/interrupt-controller/arm
7 #include <dt-bindings/power/amlogic,t7-pwrc.h>
8 #include "amlogic-t7-reset.h"
9
10 / {
11 interrupt-parent = <&gic>;
12 #address-cells = <2>;
13 #size-cells = <2>;
14
15 cpus {
16 #address-cells = <0x2>;
17 #size-cells = <0x0>;
18
19 cpu-map {
20 cluster0 {
21 core0 {
22 cpu =
23 };
24 core1 {
25 cpu =
26 };
27 core2 {
28 cpu =
29 };
30 core3 {
31 cpu =
32 };
33 };
34
35 cluster1 {
36 core0 {
37 cpu =
38 };
39 core1 {
40 cpu =
41 };
42 core2 {
43 cpu =
44 };
45 core3 {
46 cpu =
47 };
48 };
49 };
50
51 cpu100: cpu@100 {
52 device_type = "cpu";
53 compatible = "arm,cort
54 reg = <0x0 0x100>;
55 enable-method = "psci"
56 };
57
58 cpu101: cpu@101 {
59 device_type = "cpu";
60 compatible = "arm,cort
61 reg = <0x0 0x101>;
62 enable-method = "psci"
63 };
64
65 cpu102: cpu@102 {
66 device_type = "cpu";
67 compatible = "arm,cort
68 reg = <0x0 0x102>;
69 enable-method = "psci"
70 };
71
72 cpu103: cpu@103 {
73 device_type = "cpu";
74 compatible = "arm,cort
75 reg = <0x0 0x103>;
76 enable-method = "psci"
77 };
78
79 cpu0: cpu@0 {
80 device_type = "cpu";
81 compatible = "arm,cort
82 reg = <0x0 0x0>;
83 enable-method = "psci"
84 };
85
86 cpu1: cpu@1 {
87 device_type = "cpu";
88 compatible = "arm,cort
89 reg = <0x0 0x1>;
90 enable-method = "psci"
91 };
92
93 cpu2: cpu@2 {
94 device_type = "cpu";
95 compatible = "arm,cort
96 reg = <0x0 0x2>;
97 enable-method = "psci"
98 };
99
100 cpu3: cpu@3 {
101 device_type = "cpu";
102 compatible = "arm,cort
103 reg = <0x0 0x3>;
104 enable-method = "psci"
105 };
106 };
107
108 timer {
109 compatible = "arm,armv8-timer"
110 interrupts = <GIC_PPI 13 (GIC_
111 <GIC_PPI 14 (GIC_
112 <GIC_PPI 11 (GIC_
113 <GIC_PPI 10 (GIC_
114 };
115
116 psci {
117 compatible = "arm,psci-1.0";
118 method = "smc";
119 };
120
121 sm: secure-monitor {
122 compatible = "amlogic,meson-gx
123
124 pwrc: power-controller {
125 compatible = "amlogic,
126 #power-domain-cells =
127 };
128 };
129
130 soc {
131 compatible = "simple-bus";
132 #address-cells = <2>;
133 #size-cells = <2>;
134 ranges;
135
136 gic: interrupt-controller@fff0
137 compatible = "arm,gic-
138 #interrupt-cells = <3>
139 #address-cells = <0>;
140 interrupt-controller;
141 reg = <0x0 0xfff01000
142 <0x0 0xfff02000
143 interrupts = <GIC_PPI
144 };
145
146 apb4: bus@fe000000 {
147 compatible = "simple-b
148 reg = <0x0 0xfe000000
149 #address-cells = <2>;
150 #size-cells = <2>;
151 ranges = <0x0 0x0 0x0
152
153 reset: reset-controlle
154 compatible = "
155 reg = <0x0 0x2
156 #reset-cells =
157 };
158
159 watchdog@2100 {
160 compatible = "
161 reg = <0x0 0x2
162 clocks = <&xta
163 };
164
165 periphs_pinctrl: pinct
166 compatible = "
167 #address-cells
168 #size-cells =
169 ranges;
170
171 gpio: bank@400
172 reg =
173
174 reg-na
175 gpio-c
176 #gpio-
177 gpio-r
178 };
179 };
180
181 gpio_intc: interrupt-c
182 compatible = "
183 "
184 reg = <0x0 0x4
185 interrupt-cont
186 #interrupt-cel
187 amlogic,channe
188 <10 11
189 };
190
191 uart_a: serial@78000 {
192 compatible = "
193 reg = <0x0 0x7
194 interrupts = <
195 status = "disa
196 };
197
198 sec_ao: ao-secure@1022
199 compatible = "
200 "
201 "
202 reg = <0x0 0x1
203 amlogic,has-ch
204 };
205 };
206
207 };
208 };
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