1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /*
3 * Copyright (c) 2019 Amlogic, Inc. All rights
4 */
5
6 #include <dt-bindings/clock/amlogic,a1-pll-clk
7 #include <dt-bindings/clock/amlogic,a1-periphe
8 #include <dt-bindings/gpio/meson-a1-gpio.h>
9 #include <dt-bindings/interrupt-controller/arm
10 #include <dt-bindings/interrupt-controller/irq
11 #include <dt-bindings/power/meson-a1-power.h>
12 #include <dt-bindings/reset/amlogic,meson-a1-r
13
14 / {
15 compatible = "amlogic,a1";
16
17 interrupt-parent = <&gic>;
18 #address-cells = <2>;
19 #size-cells = <2>;
20
21 cpus {
22 #address-cells = <2>;
23 #size-cells = <0>;
24
25 cpu0: cpu@0 {
26 device_type = "cpu";
27 compatible = "arm,cort
28 reg = <0x0 0x0>;
29 enable-method = "psci"
30 next-level-cache = <&l
31 #cooling-cells = <2>;
32 };
33
34 cpu1: cpu@1 {
35 device_type = "cpu";
36 compatible = "arm,cort
37 reg = <0x0 0x1>;
38 enable-method = "psci"
39 next-level-cache = <&l
40 #cooling-cells = <2>;
41 };
42
43 l2: l2-cache0 {
44 compatible = "cache";
45 cache-level = <2>;
46 cache-unified;
47 };
48 };
49
50 efuse: efuse {
51 compatible = "amlogic,meson-gx
52 clocks = <&clkc_periphs CLKID_
53 #address-cells = <1>;
54 #size-cells = <1>;
55 secure-monitor = <&sm>;
56 power-domains = <&pwrc PWRC_OT
57 };
58
59 psci {
60 compatible = "arm,psci-1.0";
61 method = "smc";
62 };
63
64 reserved-memory {
65 #address-cells = <2>;
66 #size-cells = <2>;
67 ranges;
68
69 linux,cma {
70 compatible = "shared-d
71 reusable;
72 size = <0x0 0x800000>;
73 alignment = <0x0 0x400
74 linux,cma-default;
75 };
76 };
77
78 sm: secure-monitor {
79 compatible = "amlogic,meson-gx
80
81 pwrc: power-controller {
82 compatible = "amlogic,
83 #power-domain-cells =
84 };
85 };
86
87 soc {
88 compatible = "simple-bus";
89 #address-cells = <2>;
90 #size-cells = <2>;
91 ranges;
92
93 spifc: spi@fd000400 {
94 compatible = "amlogic,
95 reg = <0x0 0xfd000400
96 clocks = <&clkc_periph
97 #address-cells = <1>;
98 #size-cells = <0>;
99 power-domains = <&pwrc
100 status = "disabled";
101 };
102
103 apb: bus@fe000000 {
104 compatible = "simple-b
105 reg = <0x0 0xfe000000
106 #address-cells = <2>;
107 #size-cells = <2>;
108 ranges = <0x0 0x0 0x0
109
110 reset: reset-controlle
111 compatible = "
112 reg = <0x0 0x0
113 #reset-cells =
114 };
115
116 periphs_pinctrl: pinct
117 compatible = "
118 #address-cells
119 #size-cells =
120 ranges;
121
122 gpio: bank@400
123 reg =
124
125 reg-na
126 gpio-c
127 #gpio-
128 gpio-r
129 };
130
131 i2c0_f11_pins:
132 mux {
133
134
135
136
137
138 };
139 };
140
141 i2c0_f9_pins:
142 mux {
143
144
145
146
147
148 };
149 };
150
151 i2c1_x_pins: i
152 mux {
153
154
155
156
157
158 };
159 };
160
161 i2c1_a_pins: i
162 mux {
163
164
165
166
167
168 };
169 };
170
171 i2c2_x0_pins:
172 mux {
173
174
175
176
177
178 };
179 };
180
181 i2c2_x15_pins:
182 mux {
183
184
185
186
187
188 };
189 };
190
191 i2c2_a4_pins:
192 mux {
193
194
195
196
197
198 };
199 };
200
201 i2c2_a8_pins:
202 mux {
203
204
205
206
207
208 };
209 };
210
211 i2c3_x_pins: i
212 mux {
213
214
215
216
217
218 };
219 };
220
221 i2c3_f_pins: i
222 mux {
223
224
225
226
227
228 };
229 };
230
231 uart_a_pins: u
232 mux {
233
234
235
236 };
237 };
238
239 uart_a_cts_rts
240 mux {
241
242
243
244
245 };
246 };
247
248 sdio_pins: sdi
249 mux0 {
250
251
252
253
254
255
256
257 };
258
259 mux1 {
260
261
262
263 };
264 };
265
266 sdio_clk_gate_
267 mux {
268
269
270
271 };
272 };
273
274 spifc_pins: sp
275 mux {
276
277
278
279
280
281
282
283 };
284 };
285 };
286
287 gpio_intc: interrupt-c
288 compatible = "
289 "
290 reg = <0x0 0x0
291 interrupt-cont
292 #interrupt-cel
293 amlogic,channe
294 <49 50
295 };
296
297 clkc_periphs: clock-co
298 compatible = "
299 reg = <0 0x800
300 #clock-cells =
301 clocks = <&clk
302 <&clk
303 <&clk
304 <&clk
305 <&clk
306 <&xta
307 clock-names =
308
309
310 };
311
312 i2c0: i2c@1400 {
313 compatible = "
314 status = "disa
315 reg = <0x0 0x1
316 interrupts = <
317 #address-cells
318 #size-cells =
319 clocks = <&clk
320 power-domains
321 };
322
323 uart_AO: serial@1c00 {
324 compatible = "
325 "
326 reg = <0x0 0x1
327 interrupts = <
328 clocks = <&xta
329 clock-names =
330 status = "disa
331 };
332
333 uart_AO_B: serial@2000
334 compatible = "
335 "
336 reg = <0x0 0x2
337 interrupts = <
338 clocks = <&xta
339 clock-names =
340 status = "disa
341 };
342
343 saradc: adc@2c00 {
344 compatible = "
345 "amlog
346 reg = <0x0 0x2
347 #io-channel-ce
348 power-domains
349 interrupts = <
350 clocks = <&xta
351 <&clkc
352 <&clkc
353 <&clkc
354 clock-names =
355 "adc_c
356 status = "disa
357 };
358
359 i2c1: i2c@5c00 {
360 compatible = "
361 status = "disa
362 reg = <0x0 0x5
363 interrupts = <
364 #address-cells
365 #size-cells =
366 clocks = <&clk
367 power-domains
368 };
369
370 i2c2: i2c@6800 {
371 compatible = "
372 status = "disa
373 reg = <0x0 0x6
374 interrupts = <
375 #address-cells
376 #size-cells =
377 clocks = <&clk
378 power-domains
379 };
380
381 i2c3: i2c@6c00 {
382 compatible = "
383 status = "disa
384 reg = <0x0 0x6
385 interrupts = <
386 #address-cells
387 #size-cells =
388 clocks = <&clk
389 power-domains
390 };
391
392 usb2_phy1: phy@4000 {
393 compatible = "
394 clocks = <&clk
395 clock-names =
396 reg = <0x0 0x4
397 resets = <&res
398 reset-names =
399 #phy-cells = <
400 power-domains
401 };
402
403 cpu_temp: temperature-
404 compatible = "
405 reg = <0x0 0x4
406 interrupts = <
407 clocks = <&clk
408 assigned-clock
409 assigned-clock
410 #thermal-senso
411 amlogic,ao-sec
412 };
413
414 hwrng: rng@5118 {
415 compatible = "
416 reg = <0x0 0x5
417 power-domains
418 };
419
420 sec_AO: ao-secure@5a20
421 compatible = "
422 reg = <0x0 0x5
423 amlogic,has-ch
424 };
425
426 clkc_pll: pll-clock-co
427 compatible = "
428 reg = <0 0x7c8
429 #clock-cells =
430 clocks = <&clk
431 <&clk
432 clock-names =
433 };
434
435 sd_emmc: mmc@10000 {
436 compatible = "
437 reg = <0x0 0x1
438 interrupts = <
439 clocks = <&clk
440 <&clk
441 <&clk
442 clock-names =
443
444
445 assigned-clock
446 assigned-clock
447 resets = <&res
448 power-domains
449 status = "disa
450 };
451 };
452
453 usb: usb@fe004400 {
454 status = "disabled";
455 compatible = "amlogic,
456 reg = <0x0 0xfe004400
457 interrupts = <GIC_SPI
458 #address-cells = <2>;
459 #size-cells = <2>;
460 ranges;
461
462 clocks = <&clkc_periph
463 <&clkc_periph
464 <&clkc_periph
465 clock-names = "usb_ctr
466 assigned-clocks = <&cl
467 assigned-clock-rates =
468 resets = <&reset RESET
469
470 dr_mode = "otg";
471
472 phys = <&usb2_phy1>;
473 phy-names = "usb2-phy1
474
475 dwc3: usb@ff400000 {
476 compatible = "
477 reg = <0x0 0xf
478 interrupts = <
479 dr_mode = "hos
480 snps,dis_u2_su
481 snps,quirk-fra
482 snps,parkmode-
483 };
484
485 dwc2: usb@ff500000 {
486 compatible = "
487 reg = <0x0 0xf
488 interrupts = <
489 phys = <&usb2_
490 phy-names = "u
491 clocks = <&clk
492 clock-names =
493 dr_mode = "per
494 g-rx-fifo-size
495 g-np-tx-fifo-s
496 g-tx-fifo-size
497 };
498 };
499
500 gic: interrupt-controller@ff90
501 compatible = "arm,gic-
502 reg = <0x0 0xff901000
503 <0x0 0xff902000
504 <0x0 0xff904000
505 <0x0 0xff906000
506 interrupt-controller;
507 interrupts = <GIC_PPI
508 (GIC_CPU_MASK_
509 #interrupt-cells = <3>
510 #address-cells = <0>;
511 };
512 };
513
514 timer {
515 compatible = "arm,armv8-timer"
516 interrupts = <GIC_PPI 13
517 (GIC_CPU_MASK_RAW(0xff
518 <GIC_PPI 14
519 (GIC_CPU_MASK_RAW(0xff
520 <GIC_PPI 11
521 (GIC_CPU_MASK_RAW(0xff
522 <GIC_PPI 10
523 (GIC_CPU_MASK_RAW(0xff
524 };
525
526 xtal: xtal-clk {
527 compatible = "fixed-clock";
528 clock-frequency = <24000000>;
529 clock-output-names = "xtal";
530 #clock-cells = <0>;
531 };
532 };
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