1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /*
3 * Copyright (c) 2018 Amlogic, Inc. All rights
4 */
5
6 #include <dt-bindings/phy/phy.h>
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/clock/g12a-clkc.h>
9 #include <dt-bindings/clock/g12a-aoclkc.h>
10 #include <dt-bindings/interrupt-controller/irq
11 #include <dt-bindings/interrupt-controller/arm
12 #include <dt-bindings/interrupt-controller/aml
13 #include <dt-bindings/reset/amlogic,meson-g12a
14 #include <dt-bindings/thermal/thermal.h>
15
16 / {
17 interrupt-parent = <&gic>;
18 #address-cells = <2>;
19 #size-cells = <2>;
20
21 aliases {
22 mmc0 = &sd_emmc_b; /* SD card
23 mmc1 = &sd_emmc_c; /* eMMC */
24 mmc2 = &sd_emmc_a; /* SDIO */
25 };
26
27 chosen {
28 #address-cells = <2>;
29 #size-cells = <2>;
30 ranges;
31
32 simplefb_cvbs: framebuffer-cvb
33 compatible = "amlogic,
34 "simple-f
35 amlogic,pipeline = "vp
36 clocks = <&clkc CLKID_
37 <&clkc CLKID_
38 <&clkc CLKID_
39 status = "disabled";
40 };
41
42 simplefb_hdmi: framebuffer-hdm
43 compatible = "amlogic,
44 "simple-fr
45 amlogic,pipeline = "vp
46 clocks = <&clkc CLKID_
47 <&clkc CLKID_
48 <&clkc CLKID_
49 status = "disabled";
50 };
51 };
52
53 efuse: efuse {
54 compatible = "amlogic,meson-gx
55 clocks = <&clkc CLKID_EFUSE>;
56 #address-cells = <1>;
57 #size-cells = <1>;
58 read-only;
59 secure-monitor = <&sm>;
60 };
61
62 gpu_opp_table: opp-table-gpu {
63 compatible = "operating-points
64
65 opp-124999998 {
66 opp-hz = /bits/ 64 <12
67 opp-microvolt = <80000
68 };
69 opp-249999996 {
70 opp-hz = /bits/ 64 <24
71 opp-microvolt = <80000
72 };
73 opp-285714281 {
74 opp-hz = /bits/ 64 <28
75 opp-microvolt = <80000
76 };
77 opp-399999994 {
78 opp-hz = /bits/ 64 <39
79 opp-microvolt = <80000
80 };
81 opp-499999992 {
82 opp-hz = /bits/ 64 <49
83 opp-microvolt = <80000
84 };
85 opp-666666656 {
86 opp-hz = /bits/ 64 <66
87 opp-microvolt = <80000
88 };
89 opp-799999987 {
90 opp-hz = /bits/ 64 <79
91 opp-microvolt = <80000
92 };
93 };
94
95 psci {
96 compatible = "arm,psci-1.0";
97 method = "smc";
98 };
99
100 reserved-memory {
101 #address-cells = <2>;
102 #size-cells = <2>;
103 ranges;
104
105 /* 3 MiB reserved for ARM Trus
106 secmon_reserved: secmon@500000
107 reg = <0x0 0x05000000
108 no-map;
109 };
110
111 /* 32 MiB reserved for ARM Tru
112 secmon_reserved_bl32: secmon@5
113 reg = <0x0 0x05300000
114 no-map;
115 };
116
117 linux,cma {
118 compatible = "shared-d
119 reusable;
120 size = <0x0 0x10000000
121 alignment = <0x0 0x400
122 linux,cma-default;
123 };
124 };
125
126 sm: secure-monitor {
127 compatible = "amlogic,meson-gx
128 };
129
130 soc {
131 compatible = "simple-bus";
132 #address-cells = <2>;
133 #size-cells = <2>;
134 ranges;
135
136 pcie: pcie@fc000000 {
137 compatible = "amlogic,
138 reg = <0x0 0xfc000000
139 <0x0 0xff648000
140 <0x0 0xfc400000
141 reg-names = "elbi", "c
142 interrupts = <GIC_SPI
143 #interrupt-cells = <1>
144 interrupt-map-mask = <
145 interrupt-map = <0 0 0
146 bus-range = <0x0 0xff>
147 #address-cells = <3>;
148 #size-cells = <2>;
149 device_type = "pci";
150 ranges = <0x81000000 0
151 <0x82000000 0
152
153 clocks = <&clkc CLKID_
154 &clkc CLKID_
155 &clkc CLKID_
156 clock-names = "general
157 "pclk",
158 "port";
159 resets = <&reset RESET
160 <&reset RESET
161 reset-names = "port",
162 "apb";
163 num-lanes = <1>;
164 phys = <&usb3_pcie_phy
165 phy-names = "pcie";
166 status = "disabled";
167 };
168
169 ethmac: ethernet@ff3f0000 {
170 compatible = "amlogic,
171 "snps,dwm
172 "snps,dwm
173 reg = <0x0 0xff3f0000
174 <0x0 0xff634540
175 interrupts = <GIC_SPI
176 interrupt-names = "mac
177 clocks = <&clkc CLKID_
178 <&clkc CLKID_
179 <&clkc CLKID_
180 <&clkc CLKID_
181 clock-names = "stmmace
182 "timing-
183 rx-fifo-depth = <4096>
184 tx-fifo-depth = <2048>
185 status = "disabled";
186
187 mdio0: mdio {
188 #address-cells
189 #size-cells =
190 compatible = "
191 };
192 };
193
194 apb: bus@ff600000 {
195 compatible = "simple-b
196 reg = <0x0 0xff600000
197 #address-cells = <2>;
198 #size-cells = <2>;
199 ranges = <0x0 0x0 0x0
200
201 hdmi_tx: hdmi-tx@0 {
202 compatible = "
203 reg = <0x0 0x0
204 interrupts = <
205 resets = <&res
206 <&res
207 <&res
208 reset-names =
209 clocks = <&clk
210 <&clk
211 <&clk
212 clock-names =
213 #address-cells
214 #size-cells =
215 #sound-dai-cel
216 status = "disa
217
218 assigned-clock
219
220 assigned-clock
221 assigned-clock
222
223 /* VPU VENC In
224 hdmi_tx_venc_p
225 reg =
226
227 hdmi_t
228
229 };
230 };
231
232 /* TMDS Output
233 hdmi_tx_tmds_p
234 reg =
235 };
236 };
237
238 apb_efuse: bus@30000 {
239 compatible = "
240 reg = <0x0 0x3
241 #address-cells
242 #size-cells =
243 ranges = <0x0
244
245 hwrng: rng@218
246 compat
247 reg =
248 clocks
249 clock-
250 };
251 };
252
253 acodec: audio-controll
254 compatible = "
255 reg = <0x0 0x3
256 #sound-dai-cel
257 sound-name-pre
258 clocks = <&clk
259 clock-names =
260 resets = <&res
261 status = "disa
262 };
263
264 periphs: bus@34400 {
265 compatible = "
266 reg = <0x0 0x3
267 #address-cells
268 #size-cells =
269 ranges = <0x0
270
271 periphs_pinctr
272 compat
273 #addre
274 #size-
275 ranges
276
277 gpio:
278
279
280
281
282
283
284
285
286
287
288
289
290
291 };
292
293 cec_ao
294
295
296
297
298
299 };
300
301 cec_ao
302
303
304
305
306
307 };
308
309 emmc_c
310
311
312
313
314
315
316
317
318
319
320
321
322
323 };
324
325 emmc_d
326
327
328
329
330
331
332
333
334
335 };
336
337 emmc_d
338
339
340
341
342
343
344
345
346
347
348
349
350
351 };
352
353 emmc_d
354
355
356
357
358
359
360 };
361
362 emmc_c
363
364
365
366
367
368
369 };
370
371 hdmitx
372
373
374
375
376
377
378
379 };
380
381 hdmitx
382
383
384
385
386
387 };
388
389
390 i2c0_s
391
392
393
394
395
396
397
398 };
399
400 i2c0_s
401
402
403
404
405
406
407 };
408
409 i2c0_s
410
411
412
413
414
415
416 };
417
418 i2c0_s
419
420
421
422
423
424
425 };
426
427 i2c0_s
428
429
430
431
432
433
434 };
435
436 i2c0_s
437
438
439
440
441
442
443 };
444
445 i2c1_s
446
447
448
449
450
451
452 };
453
454 i2c1_s
455
456
457
458
459
460
461 };
462
463 i2c1_s
464
465
466
467
468
469
470 };
471
472 i2c1_s
473
474
475
476
477
478
479 };
480
481 i2c1_s
482
483
484
485
486
487
488 };
489
490 i2c1_s
491
492
493
494
495
496
497 };
498
499 i2c2_s
500
501
502
503
504
505
506 };
507
508 i2c2_s
509
510
511
512
513
514
515 };
516
517 i2c2_s
518
519
520
521
522
523
524 };
525
526 i2c2_s
527
528
529
530
531
532
533 };
534
535 i2c3_s
536
537
538
539
540
541
542 };
543
544 i2c3_s
545
546
547
548
549
550
551 };
552
553 i2c3_s
554
555
556
557
558
559
560 };
561
562 i2c3_s
563
564
565
566
567
568
569 };
570
571 mclk0_
572
573
574
575
576
577
578 };
579
580 mclk1_
581
582
583
584
585
586
587 };
588
589 mclk1_
590
591
592
593
594
595
596 };
597
598 mclk1_
599
600
601
602
603
604
605 };
606
607 nor_pi
608
609
610
611
612
613
614
615
616 };
617
618 pdm_di
619
620
621
622
623
624 };
625
626 pdm_di
627
628
629
630
631
632 };
633
634 pdm_di
635
636
637
638
639
640 };
641
642 pdm_di
643
644
645
646
647
648 };
649
650 pdm_di
651
652
653
654
655
656 };
657
658 pdm_di
659
660
661
662
663
664 };
665
666 pdm_di
667
668
669
670
671
672 };
673
674 pdm_di
675
676
677
678
679
680 };
681
682 pdm_di
683
684
685
686
687
688 };
689
690 pdm_di
691
692
693
694
695
696 };
697
698 pdm_di
699
700
701
702
703
704 };
705
706 pdm_di
707
708
709
710
711
712 };
713
714 pdm_di
715
716
717
718
719
720 };
721
722 pdm_di
723
724
725
726
727
728 };
729
730 pdm_di
731
732
733
734
735
736 };
737
738 pdm_di
739
740
741
742
743
744 };
745
746 pdm_dc
747
748
749
750
751
752
753 };
754
755 pdm_dc
756
757
758
759
760
761
762 };
763
764 pdm_dc
765
766
767
768
769
770
771 };
772
773 pdm_dc
774
775
776
777
778
779
780 };
781
782 pwm_a_
783
784
785
786
787
788 };
789
790 pwm_b_
791
792
793
794
795
796 };
797
798 pwm_b_
799
800
801
802
803
804 };
805
806 pwm_c_
807
808
809
810
811
812 };
813
814 pwm_c_
815
816
817
818
819
820 };
821
822 pwm_c_
823
824
825
826
827
828 };
829
830 pwm_d_
831
832
833
834
835
836 };
837
838 pwm_d_
839
840
841
842
843
844 };
845
846 pwm_e_
847
848
849
850
851
852 };
853
854 pwm_f_
855
856
857
858
859
860 };
861
862 pwm_f_
863
864
865
866
867
868 };
869
870 pwm_f_
871
872
873
874
875
876 };
877
878 pwm_f_
879
880
881
882
883
884 };
885
886 sdcard
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904 };
905
906 sdcard
907
908
909
910
911
912
913 };
914
915 sdcard
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933 };
934
935 sdcard
936
937
938
939
940
941
942 };
943
944 sdio_p
945
946
947
948
949
950
951
952
953
954
955
956 };
957
958 sdio_c
959
960
961
962
963
964
965 };
966
967 spdif_
968
969
970
971
972
973 };
974
975 spdif_
976
977
978
979
980
981 };
982
983 spdif_
984
985
986
987
988
989 };
990
991 spdif_
992
993
994
995
996
997
998 };
999
1000 spdif
1001
1002
1003
1004
1005
1006
1007 };
1008
1009 spdif
1010
1011
1012
1013
1014
1015
1016 };
1017
1018 spicc
1019
1020
1021
1022
1023
1024
1025
1026
1027 };
1028
1029 spicc
1030
1031
1032
1033
1034
1035
1036 };
1037
1038 spicc
1039
1040
1041
1042
1043
1044
1045
1046
1047
1048 };
1049
1050 spicc
1051
1052
1053
1054
1055
1056
1057
1058 };
1059
1060 spicc
1061
1062
1063
1064
1065
1066
1067 };
1068
1069 tdm_a
1070
1071
1072
1073
1074
1075 };
1076
1077
1078 tdm_a
1079
1080
1081
1082
1083
1084 };
1085
1086 tdm_a
1087
1088
1089
1090
1091
1092
1093 };
1094
1095 tdm_a
1096
1097
1098
1099
1100
1101
1102 };
1103
1104 tdm_a
1105
1106
1107
1108
1109
1110
1111 };
1112
1113 tdm_a
1114
1115
1116
1117
1118
1119
1120 };
1121
1122 tdm_a
1123
1124
1125
1126
1127
1128 };
1129
1130
1131 tdm_a
1132
1133
1134
1135
1136
1137 };
1138
1139 tdm_b
1140
1141
1142
1143
1144
1145 };
1146
1147 tdm_b
1148
1149
1150
1151
1152
1153 };
1154
1155 tdm_b
1156
1157
1158
1159
1160
1161 };
1162
1163 tdm_b
1164
1165
1166
1167
1168
1169 };
1170
1171 tdm_b
1172
1173
1174
1175
1176
1177 };
1178
1179 tdm_b
1180
1181
1182
1183
1184
1185
1186 };
1187
1188 tdm_b
1189
1190
1191
1192
1193
1194
1195 };
1196
1197 tdm_b
1198
1199
1200
1201
1202
1203
1204 };
1205
1206 tdm_b
1207
1208
1209
1210
1211
1212
1213 };
1214
1215 tdm_b
1216
1217
1218
1219
1220
1221
1222 };
1223
1224 tdm_b
1225
1226
1227
1228
1229
1230
1231 };
1232
1233 tdm_b
1234
1235
1236
1237
1238
1239
1240 };
1241
1242 tdm_b
1243
1244
1245
1246
1247
1248 };
1249
1250 tdm_b
1251
1252
1253
1254
1255
1256 };
1257
1258 tdm_c
1259
1260
1261
1262
1263
1264 };
1265
1266 tdm_c
1267
1268
1269
1270
1271
1272 };
1273
1274 tdm_c
1275
1276
1277
1278
1279
1280 };
1281
1282 tdm_c
1283
1284
1285
1286
1287
1288 };
1289
1290 tdm_c
1291
1292
1293
1294
1295
1296 };
1297
1298 eth_l
1299
1300
1301
1302
1303
1304
1305 };
1306
1307 eth_p
1308
1309
1310
1311
1312
1313
1314
1315
1316
1317
1318
1319
1320
1321
1322 };
1323
1324 eth_r
1325
1326
1327
1328
1329
1330
1331
1332
1333
1334
1335 };
1336
1337 tdm_c
1338
1339
1340
1341
1342
1343 };
1344
1345 tdm_c
1346
1347
1348
1349
1350
1351 };
1352
1353 tdm_c
1354
1355
1356
1357
1358
1359 };
1360
1361 tdm_c
1362
1363
1364
1365
1366
1367
1368 };
1369
1370 tdm_c
1371
1372
1373
1374
1375
1376
1377 };
1378
1379 tdm_c
1380
1381
1382
1383
1384
1385
1386 };
1387
1388 tdm_c
1389
1390
1391
1392
1393
1394
1395 };
1396
1397 tdm_c
1398
1399
1400
1401
1402
1403
1404 };
1405
1406 tdm_c
1407
1408
1409
1410
1411
1412
1413 };
1414
1415 tdm_c
1416
1417
1418
1419
1420
1421
1422 };
1423
1424 tdm_c
1425
1426
1427
1428
1429
1430
1431 };
1432
1433 tdm_c
1434
1435
1436
1437
1438
1439
1440 };
1441
1442 tdm_c
1443
1444
1445
1446
1447
1448
1449 };
1450
1451 tdm_c
1452
1453
1454
1455
1456
1457
1458 };
1459
1460 tdm_c
1461
1462
1463
1464
1465
1466
1467 };
1468
1469 tdm_c
1470
1471
1472
1473
1474
1475 };
1476
1477 tdm_c
1478
1479
1480
1481
1482
1483 };
1484
1485 tdm_c
1486
1487
1488
1489
1490
1491 };
1492
1493 tdm_c
1494
1495
1496
1497
1498
1499 };
1500
1501 uart_
1502
1503
1504
1505
1506
1507
1508 };
1509
1510 uart_
1511
1512
1513
1514
1515
1516
1517 };
1518
1519 uart_
1520
1521
1522
1523
1524
1525
1526 };
1527
1528 uart_
1529
1530
1531
1532
1533
1534
1535 };
1536
1537 uart_
1538
1539
1540
1541
1542
1543
1544 };
1545 };
1546 };
1547
1548 cpu_temp: temperature
1549 compatible =
1550
1551 reg = <0x0 0x
1552 interrupts =
1553 clocks = <&cl
1554 #thermal-sens
1555 amlogic,ao-se
1556 };
1557
1558 ddr_temp: temperature
1559 compatible =
1560
1561 reg = <0x0 0x
1562 interrupts =
1563 clocks = <&cl
1564 #thermal-sens
1565 amlogic,ao-se
1566 };
1567
1568 usb2_phy0: phy@36000
1569 compatible =
1570 reg = <0x0 0x
1571 clocks = <&xt
1572 clock-names =
1573 resets = <&re
1574 reset-names =
1575 #phy-cells =
1576 };
1577
1578 dmc: bus@38000 {
1579 compatible =
1580 #address-cell
1581 #size-cells =
1582 ranges = <0x0
1583
1584 canvas: video
1585 compa
1586 reg =
1587 };
1588
1589 pmu: pmu@80 {
1590 reg =
1591
1592 inter
1593 };
1594 };
1595
1596 usb2_phy1: phy@3a000
1597 compatible =
1598 reg = <0x0 0x
1599 clocks = <&xt
1600 clock-names =
1601 resets = <&re
1602 reset-names =
1603 #phy-cells =
1604 };
1605
1606 hiu: bus@3c000 {
1607 compatible =
1608 reg = <0x0 0x
1609 #address-cell
1610 #size-cells =
1611 ranges = <0x0
1612
1613 hhi: system-c
1614 compa
1615
1616 reg =
1617
1618 clkc:
1619
1620
1621
1622
1623 };
1624
1625 pwrc:
1626
1627
1628
1629
1630
1631
1632
1633
1634
1635
1636
1637
1638
1639
1640
1641
1642
1643
1644
1645
1646
1647
1648
1649
1650
1651
1652
1653
1654
1655
1656
1657
1658
1659
1660
1661
1662
1663
1664
1665
1666
1667
1668
1669
1670 };
1671
1672 mipi_
1673
1674
1675
1676 };
1677 };
1678 };
1679
1680 mipi_dphy: phy@44000
1681 compatible =
1682 reg = <0x0 0x
1683 clocks = <&cl
1684 clock-names =
1685 resets = <&re
1686 reset-names =
1687 phys = <&mipi
1688 phy-names = "
1689 #phy-cells =
1690 status = "dis
1691 };
1692
1693 usb3_pcie_phy: phy@46
1694 compatible =
1695 reg = <0x0 0x
1696 clocks = <&cl
1697 clock-names =
1698 resets = <&re
1699 reset-names =
1700 assigned-cloc
1701 assigned-cloc
1702 #phy-cells =
1703 };
1704
1705 eth_phy: mdio-multipl
1706 compatible =
1707 reg = <0x0 0x
1708 clocks = <&cl
1709 <&xt
1710 <&cl
1711 clock-names =
1712 mdio-parent-b
1713 #address-cell
1714 #size-cells =
1715
1716 ext_mdio: mdi
1717 reg =
1718 #addr
1719 #size
1720 };
1721
1722 int_mdio: mdi
1723 reg =
1724 #addr
1725 #size
1726
1727 inter
1728
1729
1730
1731
1732
1733 };
1734 };
1735 };
1736 };
1737
1738 aobus: bus@ff800000 {
1739 compatible = "simple-
1740 reg = <0x0 0xff800000
1741 #address-cells = <2>;
1742 #size-cells = <2>;
1743 ranges = <0x0 0x0 0x0
1744
1745 rti: sys-ctrl@0 {
1746 compatible =
1747
1748 reg = <0x0 0x
1749
1750 clkc_AO: cloc
1751 compa
1752 #cloc
1753 #rese
1754 clock
1755 clock
1756 };
1757 };
1758
1759 ao_pinctrl: pinctrl@1
1760 compatible =
1761 #address-cell
1762 #size-cells =
1763 ranges;
1764
1765 gpio_ao: bank
1766 reg =
1767
1768
1769 reg-n
1770
1771
1772 gpio-
1773 #gpio
1774 gpio-
1775 };
1776
1777 i2c_ao_sck_pi
1778 mux {
1779
1780
1781
1782
1783 };
1784 };
1785
1786 i2c_ao_sda_pi
1787 mux {
1788
1789
1790
1791
1792 };
1793 };
1794
1795 i2c_ao_sck_e_
1796 mux {
1797
1798
1799
1800
1801 };
1802 };
1803
1804 i2c_ao_sda_e_
1805 mux {
1806
1807
1808
1809
1810 };
1811 };
1812
1813 mclk0_ao_pins
1814 mux {
1815
1816
1817
1818
1819 };
1820 };
1821
1822 tdm_ao_b_din0
1823 mux {
1824
1825
1826
1827 };
1828 };
1829
1830 spdif_ao_out_
1831 mux {
1832
1833
1834
1835
1836 };
1837 };
1838
1839 tdm_ao_b_din1
1840 mux {
1841
1842
1843
1844 };
1845 };
1846
1847 tdm_ao_b_din2
1848 mux {
1849
1850
1851
1852 };
1853 };
1854
1855 tdm_ao_b_dout
1856 mux {
1857
1858
1859
1860
1861 };
1862 };
1863
1864 tdm_ao_b_dout
1865 mux {
1866
1867
1868
1869
1870 };
1871 };
1872
1873 tdm_ao_b_dout
1874 mux {
1875
1876
1877
1878
1879 };
1880 };
1881
1882 tdm_ao_b_fs_p
1883 mux {
1884
1885
1886
1887
1888 };
1889 };
1890
1891 tdm_ao_b_sclk
1892 mux {
1893
1894
1895
1896
1897 };
1898 };
1899
1900 tdm_ao_b_slv_
1901 mux {
1902
1903
1904
1905 };
1906 };
1907
1908 tdm_ao_b_slv_
1909 mux {
1910
1911
1912
1913 };
1914 };
1915
1916 uart_ao_a_pin
1917 mux {
1918
1919
1920
1921
1922 };
1923 };
1924
1925 uart_ao_a_cts
1926 mux {
1927
1928
1929
1930
1931 };
1932 };
1933
1934 uart_ao_b_2_3
1935 mux {
1936
1937
1938
1939
1940 };
1941 };
1942
1943 uart_ao_b_8_9
1944 mux {
1945
1946
1947
1948
1949 };
1950 };
1951
1952 uart_ao_b_cts
1953 mux {
1954
1955
1956
1957
1958 };
1959 };
1960
1961 pwm_a_e_pins:
1962 mux {
1963
1964
1965
1966 };
1967 };
1968
1969 pwm_ao_a_pins
1970 mux {
1971
1972
1973
1974 };
1975 };
1976
1977 pwm_ao_b_pins
1978 mux {
1979
1980
1981
1982 };
1983 };
1984
1985 pwm_ao_c_4_pi
1986 mux {
1987
1988
1989
1990 };
1991 };
1992
1993 pwm_ao_c_6_pi
1994 mux {
1995
1996
1997
1998 };
1999 };
2000
2001 pwm_ao_d_5_pi
2002 mux {
2003
2004
2005
2006 };
2007 };
2008
2009 pwm_ao_d_10_p
2010 mux {
2011
2012
2013
2014 };
2015 };
2016
2017 pwm_ao_d_e_pi
2018 mux {
2019
2020
2021 };
2022 };
2023
2024 remote_input_
2025 mux {
2026
2027
2028
2029 };
2030 };
2031 };
2032
2033 vrtc: rtc@a8 {
2034 compatible =
2035 reg = <0x0 0x
2036 };
2037
2038 cec_AO: cec@100 {
2039 compatible =
2040 reg = <0x0 0x
2041 interrupts =
2042 clocks = <&cl
2043 clock-names =
2044 status = "dis
2045 };
2046
2047 sec_AO: ao-secure@140
2048 compatible =
2049 reg = <0x0 0x
2050 amlogic,has-c
2051 };
2052
2053 cecb_AO: cec@280 {
2054 compatible =
2055 reg = <0x0 0x
2056 interrupts =
2057 clocks = <&cl
2058 clock-names =
2059 status = "dis
2060 };
2061
2062 pwm_AO_cd: pwm@2000 {
2063 compatible =
2064 reg = <0x0 0x
2065 #pwm-cells =
2066 status = "dis
2067 };
2068
2069 uart_AO: serial@3000
2070 compatible =
2071
2072
2073 reg = <0x0 0x
2074 interrupts =
2075 clocks = <&xt
2076 clock-names =
2077 status = "dis
2078 };
2079
2080 uart_AO_B: serial@400
2081 compatible =
2082
2083
2084 reg = <0x0 0x
2085 interrupts =
2086 clocks = <&xt
2087 clock-names =
2088 status = "dis
2089 };
2090
2091 i2c_AO: i2c@5000 {
2092 compatible =
2093 status = "dis
2094 reg = <0x0 0x
2095 interrupts =
2096 #address-cell
2097 #size-cells =
2098 clocks = <&cl
2099 };
2100
2101 pwm_AO_ab: pwm@7000 {
2102 compatible =
2103 reg = <0x0 0x
2104 #pwm-cells =
2105 status = "dis
2106 };
2107
2108 ir: ir@8000 {
2109 compatible =
2110 reg = <0x0 0x
2111 interrupts =
2112 status = "dis
2113 };
2114
2115 saradc: adc@9000 {
2116 compatible =
2117
2118 reg = <0x0 0x
2119 #io-channel-c
2120 interrupts =
2121 clocks = <&xt
2122 <&cl
2123 <&cl
2124 <&cl
2125 clock-names =
2126 status = "dis
2127 };
2128 };
2129
2130 vdec: video-decoder@ff620000
2131 compatible = "amlogic
2132 reg = <0x0 0xff620000
2133 <0x0 0xffd0e180
2134 reg-names = "dos", "e
2135 interrupts = <GIC_SPI
2136 <GIC_SPI
2137 interrupt-names = "vd
2138
2139 amlogic,ao-sysctrl =
2140 amlogic,canvas = <&ca
2141
2142 clocks = <&clkc CLKID
2143 <&clkc CLKID
2144 <&clkc CLKID
2145 <&clkc CLKID
2146 <&clkc CLKID
2147 clock-names = "dos_pa
2148 "vdec_h
2149 resets = <&reset RESE
2150 reset-names = "espars
2151 };
2152
2153 vpu: vpu@ff900000 {
2154 compatible = "amlogic
2155 reg = <0x0 0xff900000
2156 <0x0 0xff63c000
2157 reg-names = "vpu", "h
2158 interrupts = <GIC_SPI
2159 #address-cells = <1>;
2160 #size-cells = <0>;
2161 amlogic,canvas = <&ca
2162
2163 /* CVBS VDAC output p
2164 cvbs_vdac_port: port@
2165 reg = <0>;
2166 };
2167
2168 /* HDMI-TX output por
2169 hdmi_tx_port: port@1
2170 reg = <1>;
2171
2172 hdmi_tx_out:
2173 remot
2174 };
2175 };
2176
2177 /* DPI output port */
2178 dpi_port: port@2 {
2179 reg = <2>;
2180
2181 dpi_out: endp
2182 remot
2183 };
2184 };
2185 };
2186
2187 gic: interrupt-controller@ffc
2188 compatible = "arm,gic
2189 reg = <0x0 0xffc01000
2190 <0x0 0xffc02000
2191 <0x0 0xffc04000
2192 <0x0 0xffc06000
2193 interrupt-controller;
2194 interrupts = <GIC_PPI
2195 (GIC_CPU_MASK
2196 #interrupt-cells = <3
2197 #address-cells = <0>;
2198 };
2199
2200 cbus: bus@ffd00000 {
2201 compatible = "simple-
2202 reg = <0x0 0xffd00000
2203 #address-cells = <2>;
2204 #size-cells = <2>;
2205 ranges = <0x0 0x0 0x0
2206
2207 reset: reset-controll
2208 compatible =
2209 reg = <0x0 0x
2210 #reset-cells
2211 };
2212
2213 gpio_intc: interrupt-
2214 compatible =
2215
2216 reg = <0x0 0x
2217 interrupt-con
2218 #interrupt-ce
2219 amlogic,chann
2220 };
2221
2222 mipi_dsi: dsi@7000 {
2223 compatible =
2224 reg = <0x0 0x
2225 resets = <&re
2226 reset-names =
2227 clocks = <&cl
2228 <&cl
2229 <&cl
2230 clock-names =
2231 phys = <&mipi
2232 phy-names = "
2233 #address-cell
2234 #size-cells =
2235 status = "dis
2236
2237 assigned-cloc
2238 <&cl
2239 <&cl
2240 assigned-cloc
2241 <&cl
2242 <&cl
2243
2244 ports {
2245 #addr
2246 #size
2247
2248 /* VP
2249 mipi_
2250
2251
2252
2253
2254
2255 };
2256
2257 /* DS
2258 mipi_
2259
2260 };
2261 };
2262 };
2263
2264 watchdog: watchdog@f0
2265 compatible =
2266 reg = <0x0 0x
2267 clocks = <&xt
2268 };
2269
2270 spicc0: spi@13000 {
2271 compatible =
2272 reg = <0x0 0x
2273 interrupts =
2274 clocks = <&cl
2275 <&cl
2276 clock-names =
2277 #address-cell
2278 #size-cells =
2279 status = "dis
2280 };
2281
2282 spicc1: spi@15000 {
2283 compatible =
2284 reg = <0x0 0x
2285 interrupts =
2286 clocks = <&cl
2287 <&cl
2288 clock-names =
2289 #address-cell
2290 #size-cells =
2291 status = "dis
2292 };
2293
2294 spifc: spi@14000 {
2295 compatible =
2296 status = "dis
2297 reg = <0x0 0x
2298 #address-cell
2299 #size-cells =
2300 clocks = <&cl
2301 };
2302
2303 pwm_ef: pwm@19000 {
2304 compatible =
2305 reg = <0x0 0x
2306 #pwm-cells =
2307 status = "dis
2308 };
2309
2310 pwm_cd: pwm@1a000 {
2311 compatible =
2312 reg = <0x0 0x
2313 #pwm-cells =
2314 status = "dis
2315 };
2316
2317 pwm_ab: pwm@1b000 {
2318 compatible =
2319 reg = <0x0 0x
2320 #pwm-cells =
2321 status = "dis
2322 };
2323
2324 i2c3: i2c@1c000 {
2325 compatible =
2326 status = "dis
2327 reg = <0x0 0x
2328 interrupts =
2329 #address-cell
2330 #size-cells =
2331 clocks = <&cl
2332 };
2333
2334 i2c2: i2c@1d000 {
2335 compatible =
2336 status = "dis
2337 reg = <0x0 0x
2338 interrupts =
2339 #address-cell
2340 #size-cells =
2341 clocks = <&cl
2342 };
2343
2344 i2c1: i2c@1e000 {
2345 compatible =
2346 status = "dis
2347 reg = <0x0 0x
2348 interrupts =
2349 #address-cell
2350 #size-cells =
2351 clocks = <&cl
2352 };
2353
2354 i2c0: i2c@1f000 {
2355 compatible =
2356 status = "dis
2357 reg = <0x0 0x
2358 interrupts =
2359 #address-cell
2360 #size-cells =
2361 clocks = <&cl
2362 };
2363
2364 clk_msr: clock-measur
2365 compatible =
2366 reg = <0x0 0x
2367 };
2368
2369 uart_C: serial@22000
2370 compatible =
2371
2372 reg = <0x0 0x
2373 interrupts =
2374 clocks = <&xt
2375 clock-names =
2376 status = "dis
2377 };
2378
2379 uart_B: serial@23000
2380 compatible =
2381
2382 reg = <0x0 0x
2383 interrupts =
2384 clocks = <&xt
2385 clock-names =
2386 status = "dis
2387 };
2388
2389 uart_A: serial@24000
2390 compatible =
2391
2392 reg = <0x0 0x
2393 interrupts =
2394 clocks = <&xt
2395 clock-names =
2396 status = "dis
2397 fifo-size = <
2398 };
2399 };
2400
2401 sd_emmc_a: mmc@ffe03000 {
2402 compatible = "amlogic
2403 reg = <0x0 0xffe03000
2404 interrupts = <GIC_SPI
2405 status = "disabled";
2406 clocks = <&clkc CLKID
2407 <&clkc CLKID
2408 <&clkc CLKID
2409 clock-names = "core",
2410 resets = <&reset RESE
2411 };
2412
2413 sd_emmc_b: mmc@ffe05000 {
2414 compatible = "amlogic
2415 reg = <0x0 0xffe05000
2416 interrupts = <GIC_SPI
2417 status = "disabled";
2418 clocks = <&clkc CLKID
2419 <&clkc CLKID
2420 <&clkc CLKID
2421 clock-names = "core",
2422 resets = <&reset RESE
2423 };
2424
2425 sd_emmc_c: mmc@ffe07000 {
2426 compatible = "amlogic
2427 reg = <0x0 0xffe07000
2428 interrupts = <GIC_SPI
2429 status = "disabled";
2430 clocks = <&clkc CLKID
2431 <&clkc CLKID
2432 <&clkc CLKID
2433 clock-names = "core",
2434 resets = <&reset RESE
2435 };
2436
2437 usb: usb@ffe09000 {
2438 status = "disabled";
2439 compatible = "amlogic
2440 reg = <0x0 0xffe09000
2441 interrupts = <GIC_SPI
2442 #address-cells = <2>;
2443 #size-cells = <2>;
2444 ranges;
2445
2446 clocks = <&clkc CLKID
2447 resets = <&reset RESE
2448
2449 dr_mode = "otg";
2450
2451 phys = <&usb2_phy0>,
2452 <&usb3_pcie_ph
2453 phy-names = "usb2-phy
2454
2455 dwc2: usb@ff400000 {
2456 compatible =
2457 reg = <0x0 0x
2458 interrupts =
2459 clocks = <&cl
2460 clock-names =
2461 phys = <&usb2
2462 phy-names = "
2463 dr_mode = "pe
2464 g-rx-fifo-siz
2465 g-np-tx-fifo-
2466 g-tx-fifo-siz
2467 };
2468
2469 dwc3: usb@ff500000 {
2470 compatible =
2471 reg = <0x0 0x
2472 interrupts =
2473 dr_mode = "ho
2474 snps,dis_u2_s
2475 snps,quirk-fr
2476 snps,parkmode
2477 };
2478 };
2479
2480 mali: gpu@ffe40000 {
2481 compatible = "amlogic
2482 reg = <0x0 0xffe40000
2483 interrupt-parent = <&
2484 interrupts = <GIC_SPI
2485 <GIC_SPI
2486 <GIC_SPI
2487 interrupt-names = "jo
2488 clocks = <&clkc CLKID
2489 resets = <&reset RESE
2490 operating-points-v2 =
2491 #cooling-cells = <2>;
2492 };
2493 };
2494
2495 thermal-zones {
2496 cpu_thermal: cpu-thermal {
2497 polling-delay = <1000
2498 polling-delay-passive
2499 thermal-sensors = <&c
2500
2501 trips {
2502 cpu_passive:
2503 tempe
2504 hyste
2505 type
2506 };
2507
2508 cpu_hot: cpu-
2509 tempe
2510 hyste
2511 type
2512 };
2513
2514 cpu_critical:
2515 tempe
2516 hyste
2517 type
2518 };
2519 };
2520 };
2521
2522 ddr_thermal: ddr-thermal {
2523 polling-delay = <1000
2524 polling-delay-passive
2525 thermal-sensors = <&d
2526
2527 trips {
2528 ddr_passive:
2529 tempe
2530 hyste
2531 type
2532 };
2533
2534 ddr_critical:
2535 tempe
2536 hyste
2537 type
2538 };
2539 };
2540
2541 cooling-maps {
2542 map {
2543 trip
2544 cooli
2545 };
2546 };
2547 };
2548 };
2549
2550 timer {
2551 compatible = "arm,armv8-timer
2552 interrupts = <GIC_PPI 13
2553 (GIC_CPU_MASK_RAW(0xf
2554 <GIC_PPI 14
2555 (GIC_CPU_MASK_RAW(0xf
2556 <GIC_PPI 11
2557 (GIC_CPU_MASK_RAW(0xf
2558 <GIC_PPI 10
2559 (GIC_CPU_MASK_RAW(0xf
2560 arm,no-tick-in-suspend;
2561 };
2562
2563 xtal: xtal-clk {
2564 compatible = "fixed-clock";
2565 clock-frequency = <24000000>;
2566 clock-output-names = "xtal";
2567 #clock-cells = <0>;
2568 };
2569
2570 npu: npu@ff100000 {
2571 compatible = "vivante,gc";
2572 reg = <0x0 0xff100000 0x0 0x2
2573 interrupts = <0 147 4>;
2574 clocks = <&clkc CLKID_NNA_COR
2575 <&clkc CLKID_NNA_AXI
2576 clock-names = "core", "bus";
2577 assigned-clocks = <&clkc CLKI
2578 <&clkc CLKI
2579 assigned-clock-rates = <80000
2580 resets = <&reset RESET_NNA>;
2581 status = "disabled";
2582 };
2583 };
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