1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /*
3 * Copyright (c) 2023 BayLibre, SAS.
4 * Author: Jerome Brunet <jbrunet@baylibre.com>
5 */
6
7 /dts-v1/;
8
9 #include <dt-bindings/clock/g12a-clkc.h>
10 #include "meson-g12b-a311d.dtsi"
11 #include "meson-libretech-cottonwood.dtsi"
12
13 / {
14 compatible = "libretech,aml-a311d-cc",
15 model = "Libre Computer AML-A311D-CC A
16
17 vddcpu_a: regulator-vddcpu-a {
18 compatible = "pwm-regulator";
19 regulator-name = "VDDCPU_A";
20 regulator-min-microvolt = <730
21 regulator-max-microvolt = <101
22 regulator-boot-on;
23 regulator-always-on;
24 pwm-supply = <&dc_in>;
25 pwms = <&pwm_ab 0 1250 0>;
26 pwm-dutycycle-range = <100 0>;
27 };
28
29 sound {
30 model = "LC-ALTA";
31 audio-routing = "TDMOUT_A IN 0
32 "TDMOUT_A IN 1
33 "TDMOUT_A IN 2
34 "TDM_A Playbac
35 "TDMOUT_B IN 0
36 "TDMOUT_B IN 1
37 "TDMOUT_B IN 2
38 "TDM_B Playbac
39 "TDMOUT_C IN 0
40 "TDMOUT_C IN 1
41 "TDMOUT_C IN 2
42 "TDM_C Playbac
43 "TDMIN_A IN 0"
44 "TDMIN_B IN 0"
45 "TDMIN_C IN 0"
46 "TDMIN_A IN 3"
47 "TDMIN_B IN 3"
48 "TDMIN_C IN 3"
49 "TDMIN_A IN 1"
50 "TDMIN_B IN 1"
51 "TDMIN_C IN 1"
52 "TDMIN_A IN 4"
53 "TDMIN_B IN 4"
54 "TDMIN_C IN 4"
55 "TDMIN_A IN 2"
56 "TDMIN_B IN 2"
57 "TDMIN_C IN 2"
58 "TDMIN_A IN 5"
59 "TDMIN_B IN 5"
60 "TDMIN_C IN 5"
61 "TODDR_A IN 0"
62 "TODDR_B IN 0"
63 "TODDR_C IN 0"
64 "TODDR_A IN 1"
65 "TODDR_B IN 1"
66 "TODDR_C IN 1"
67 "TODDR_A IN 2"
68 "TODDR_B IN 2"
69 "TODDR_C IN 2"
70 "Lineout", "AC
71 "Lineout", "AC
72 };
73 };
74
75 &cpu0 {
76 cpu-supply = <&vddcpu_b>;
77 operating-points-v2 = <&cpu_opp_table_
78 clocks = <&clkc CLKID_CPU_CLK>;
79 clock-latency = <50000>;
80 };
81
82 &cpu1 {
83 cpu-supply = <&vddcpu_b>;
84 operating-points-v2 = <&cpu_opp_table_
85 clocks = <&clkc CLKID_CPU_CLK>;
86 clock-latency = <50000>;
87 };
88
89 &cpu100 {
90 cpu-supply = <&vddcpu_a>;
91 operating-points-v2 = <&cpub_opp_table
92 clocks = <&clkc CLKID_CPUB_CLK>;
93 clock-latency = <50000>;
94 };
95
96 &cpu101 {
97 cpu-supply = <&vddcpu_a>;
98 operating-points-v2 = <&cpub_opp_table
99 clocks = <&clkc CLKID_CPUB_CLK>;
100 clock-latency = <50000>;
101 };
102
103 &cpu102 {
104 cpu-supply = <&vddcpu_a>;
105 operating-points-v2 = <&cpub_opp_table
106 clocks = <&clkc CLKID_CPUB_CLK>;
107 clock-latency = <50000>;
108 };
109
110 &cpu103 {
111 cpu-supply = <&vddcpu_a>;
112 operating-points-v2 = <&cpub_opp_table
113 clocks = <&clkc CLKID_CPUB_CLK>;
114 clock-latency = <50000>;
115 };
116
117 &pwm_ab {
118 pinctrl-0 = <&pwm_a_e_pins>, <&pwm_b_x
119 clocks = <&xtal>, <&xtal>;
120 clock-names = "clkin0", "clkin1";
121 };
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