1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * dts file for AppliedMicro (APM) X-Gene Shad
4 *
5 * Copyright (C) 2015, Applied Micro Circuits
6 */
7
8 / {
9 compatible = "apm,xgene-shadowcat";
10 interrupt-parent = <&gic>;
11 #address-cells = <2>;
12 #size-cells = <2>;
13
14 cpus {
15 #address-cells = <2>;
16 #size-cells = <0>;
17
18 cpu@0 {
19 device_type = "cpu";
20 compatible = "apm,stre
21 reg = <0x0 0x000>;
22 enable-method = "spin-
23 cpu-release-addr = <0x
24 next-level-cache = <&x
25 #clock-cells = <1>;
26 clocks = <&pmd0clk 0>;
27 };
28 cpu@1 {
29 device_type = "cpu";
30 compatible = "apm,stre
31 reg = <0x0 0x001>;
32 enable-method = "spin-
33 cpu-release-addr = <0x
34 next-level-cache = <&x
35 #clock-cells = <1>;
36 clocks = <&pmd0clk 0>;
37 };
38 cpu@100 {
39 device_type = "cpu";
40 compatible = "apm,stre
41 reg = <0x0 0x100>;
42 enable-method = "spin-
43 cpu-release-addr = <0x
44 next-level-cache = <&x
45 #clock-cells = <1>;
46 clocks = <&pmd1clk 0>;
47 };
48 cpu@101 {
49 device_type = "cpu";
50 compatible = "apm,stre
51 reg = <0x0 0x101>;
52 enable-method = "spin-
53 cpu-release-addr = <0x
54 next-level-cache = <&x
55 #clock-cells = <1>;
56 clocks = <&pmd1clk 0>;
57 };
58 cpu@200 {
59 device_type = "cpu";
60 compatible = "apm,stre
61 reg = <0x0 0x200>;
62 enable-method = "spin-
63 cpu-release-addr = <0x
64 next-level-cache = <&x
65 #clock-cells = <1>;
66 clocks = <&pmd2clk 0>;
67 };
68 cpu@201 {
69 device_type = "cpu";
70 compatible = "apm,stre
71 reg = <0x0 0x201>;
72 enable-method = "spin-
73 cpu-release-addr = <0x
74 next-level-cache = <&x
75 #clock-cells = <1>;
76 clocks = <&pmd2clk 0>;
77 };
78 cpu@300 {
79 device_type = "cpu";
80 compatible = "apm,stre
81 reg = <0x0 0x300>;
82 enable-method = "spin-
83 cpu-release-addr = <0x
84 next-level-cache = <&x
85 #clock-cells = <1>;
86 clocks = <&pmd3clk 0>;
87 };
88 cpu@301 {
89 device_type = "cpu";
90 compatible = "apm,stre
91 reg = <0x0 0x301>;
92 enable-method = "spin-
93 cpu-release-addr = <0x
94 next-level-cache = <&x
95 #clock-cells = <1>;
96 clocks = <&pmd3clk 0>;
97 };
98 xgene_L2_0: l2-cache-0 {
99 compatible = "cache";
100 cache-level = <2>;
101 cache-unified;
102 };
103 xgene_L2_1: l2-cache-1 {
104 compatible = "cache";
105 cache-level = <2>;
106 cache-unified;
107 };
108 xgene_L2_2: l2-cache-2 {
109 compatible = "cache";
110 cache-level = <2>;
111 cache-unified;
112 };
113 xgene_L2_3: l2-cache-3 {
114 compatible = "cache";
115 cache-level = <2>;
116 cache-unified;
117 };
118 };
119
120 gic: interrupt-controller@78090000 {
121 compatible = "arm,cortex-a15-g
122 #interrupt-cells = <3>;
123 #address-cells = <2>;
124 #size-cells = <2>;
125 interrupt-controller;
126 interrupts = <1 9 0xf04>;
127 ranges = <0 0 0 0x79000000 0x0
128 reg = <0x0 0x78090000 0x0 0x10
129 <0x0 0x780a0000 0x0 0x20
130 <0x0 0x780c0000 0x0 0x10
131 <0x0 0x780e0000 0x0 0x20
132 v2m0: v2m@0 {
133 compatible = "arm,gic-
134 msi-controller;
135 reg = <0x0 0x0 0x0 0x1
136 };
137 v2m1: v2m@10000 {
138 compatible = "arm,gic-
139 msi-controller;
140 reg = <0x0 0x10000 0x0
141 };
142 v2m2: v2m@20000 {
143 compatible = "arm,gic-
144 msi-controller;
145 reg = <0x0 0x20000 0x0
146 };
147 v2m3: v2m@30000 {
148 compatible = "arm,gic-
149 msi-controller;
150 reg = <0x0 0x30000 0x0
151 };
152 v2m4: v2m@40000 {
153 compatible = "arm,gic-
154 msi-controller;
155 reg = <0x0 0x40000 0x0
156 };
157 v2m5: v2m@50000 {
158 compatible = "arm,gic-
159 msi-controller;
160 reg = <0x0 0x50000 0x0
161 };
162 v2m6: v2m@60000 {
163 compatible = "arm,gic-
164 msi-controller;
165 reg = <0x0 0x60000 0x0
166 };
167 v2m7: v2m@70000 {
168 compatible = "arm,gic-
169 msi-controller;
170 reg = <0x0 0x70000 0x0
171 };
172 v2m8: v2m@80000 {
173 compatible = "arm,gic-
174 msi-controller;
175 reg = <0x0 0x80000 0x0
176 };
177 v2m9: v2m@90000 {
178 compatible = "arm,gic-
179 msi-controller;
180 reg = <0x0 0x90000 0x0
181 };
182 v2m10: v2m@a0000 {
183 compatible = "arm,gic-
184 msi-controller;
185 reg = <0x0 0xa0000 0x0
186 };
187 v2m11: v2m@b0000 {
188 compatible = "arm,gic-
189 msi-controller;
190 reg = <0x0 0xb0000 0x0
191 };
192 v2m12: v2m@c0000 {
193 compatible = "arm,gic-
194 msi-controller;
195 reg = <0x0 0xc0000 0x0
196 };
197 v2m13: v2m@d0000 {
198 compatible = "arm,gic-
199 msi-controller;
200 reg = <0x0 0xd0000 0x0
201 };
202 v2m14: v2m@e0000 {
203 compatible = "arm,gic-
204 msi-controller;
205 reg = <0x0 0xe0000 0x0
206 };
207 v2m15: v2m@f0000 {
208 compatible = "arm,gic-
209 msi-controller;
210 reg = <0x0 0xf0000 0x0
211 };
212 };
213
214 refclk: refclk {
215 compatible = "fixed-clock";
216 #clock-cells = <1>;
217 clock-frequency = <100000000>;
218 clock-output-names = "refclk";
219 };
220
221 pmu {
222 compatible = "arm,armv8-pmuv3"
223 interrupts = <1 12 0xff04>;
224 };
225
226 timer {
227 compatible = "arm,armv8-timer"
228 interrupts = <1 0 0xff08>,
229 <1 13 0xff08>,
230 <1 14 0xff08>,
231 <1 15 0xff08>;
232 clock-frequency = <50000000>;
233 };
234
235 soc {
236 compatible = "simple-bus";
237 #address-cells = <2>;
238 #size-cells = <2>;
239 ranges;
240
241 clocks {
242 #address-cells = <2>;
243 #size-cells = <2>;
244 ranges;
245
246 pmdpll: pmdpll@170000f
247 compatible = "
248 #clock-cells =
249 clocks = <&ref
250 reg = <0x0 0x1
251 clock-output-n
252 };
253
254 pmd0clk: pmd0clk@7e200
255 compatible = "
256 #clock-cells =
257 clocks = <&pmd
258 reg = <0x0 0x7
259 clock-output-n
260 };
261
262 pmd1clk: pmd1clk@7e200
263 compatible = "
264 #clock-cells =
265 clocks = <&pmd
266 reg = <0x0 0x7
267 clock-output-n
268 };
269
270 pmd2clk: pmd2clk@7e200
271 compatible = "
272 #clock-cells =
273 clocks = <&pmd
274 reg = <0x0 0x7
275 clock-output-n
276 };
277
278 pmd3clk: pmd3clk@7e200
279 compatible = "
280 #clock-cells =
281 clocks = <&pmd
282 reg = <0x0 0x7
283 clock-output-n
284 };
285
286 socpll: socpll@1700012
287 compatible = "
288 #clock-cells =
289 clocks = <&ref
290 reg = <0x0 0x1
291 clock-output-n
292 };
293
294 socplldiv2: socplldiv2
295 compatible = "
296 #clock-cells =
297 clocks = <&soc
298 clock-mult = <
299 clock-div = <2
300 clock-output-n
301 };
302
303 ahbclk: ahbclk@1700000
304 compatible = "
305 #clock-cells =
306 clocks = <&soc
307 reg = <0x0 0x1
308 reg-names = "d
309 divider-offset
310 divider-width
311 divider-shift
312 clock-output-n
313 };
314
315 sbapbclk: sbapbclk@170
316 compatible = "
317 #clock-cells =
318 clocks = <&ahb
319 reg = <0x0 0x1
320 reg-names = "d
321 divider-offset
322 divider-width
323 divider-shift
324 clock-output-n
325 };
326
327 sdioclk: sdioclk@1f2ac
328 compatible = "
329 #clock-cells =
330 clocks = <&soc
331 reg = <0x0 0x1
332 0x0 0x
333 reg-names = "c
334 csr-offset = <
335 csr-mask = <0x
336 enable-offset
337 enable-mask =
338 divider-offset
339 divider-width
340 divider-shift
341 clock-output-n
342 };
343
344 pcie0clk: pcie0clk@1f2
345 compatible = "
346 #clock-cells =
347 clocks = <&soc
348 reg = <0x0 0x1
349 reg-names = "c
350 clock-output-n
351 };
352
353 pcie1clk: pcie1clk@1f2
354 compatible = "
355 #clock-cells =
356 clocks = <&soc
357 reg = <0x0 0x1
358 reg-names = "c
359 clock-output-n
360 };
361
362 xge0clk: xge0clk@1f61c
363 compatible = "
364 #clock-cells =
365 clocks = <&soc
366 reg = <0x0 0x1
367 reg-names = "c
368 enable-mask =
369 csr-mask = <0x
370 clock-output-n
371 };
372
373 xge1clk: xge1clk@1f62c
374 compatible = "
375 #clock-cells =
376 clocks = <&soc
377 reg = <0x0 0x1
378 reg-names = "c
379 enable-mask =
380 csr-mask = <0x
381 clock-output-n
382 };
383
384 rngpkaclk: rngpkaclk@1
385 compatible = "
386 #clock-cells =
387 clocks = <&soc
388 reg = <0x0 0x1
389 reg-names = "c
390 csr-offset = <
391 csr-mask = <0x
392 enable-offset
393 enable-mask =
394 clock-output-n
395 };
396
397 i2c4clk: i2c4clk@1704c
398 compatible = "
399 #clock-cells =
400 clocks = <&sba
401 reg = <0x0 0x1
402 reg-names = "c
403 csr-offset = <
404 csr-mask = <0x
405 enable-offset
406 enable-mask =
407 clock-output-n
408 };
409 };
410
411 scu: system-clk-controller@170
412 compatible = "apm,xgen
413 reg = <0x0 0x17000000
414 };
415
416 reboot: reboot@17000014 {
417 compatible = "syscon-r
418 regmap = <&scu>;
419 offset = <0x14>;
420 mask = <0x1>;
421 };
422
423 csw: csw@7e200000 {
424 compatible = "apm,xgen
425 reg = <0x0 0x7e200000
426 };
427
428 mcba: mcba@7e700000 {
429 compatible = "apm,xgen
430 reg = <0x0 0x7e700000
431 };
432
433 mcbb: mcbb@7e720000 {
434 compatible = "apm,xgen
435 reg = <0x0 0x7e720000
436 };
437
438 efuse: efuse@1054a000 {
439 compatible = "apm,xgen
440 reg = <0x0 0x1054a000
441 };
442
443 edac@78800000 {
444 compatible = "apm,xgen
445 #address-cells = <2>;
446 #size-cells = <2>;
447 ranges;
448 regmap-csw = <&csw>;
449 regmap-mcba = <&mcba>;
450 regmap-mcbb = <&mcbb>;
451 regmap-efuse = <&efuse
452 reg = <0x0 0x78800000
453 interrupts = <0x0 0x20
454 <0x0 0x21
455 <0x0 0x27
456
457 edacmc@7e800000 {
458 compatible = "
459 reg = <0x0 0x7
460 memory-control
461 };
462
463 edacmc@7e840000 {
464 compatible = "
465 reg = <0x0 0x7
466 memory-control
467 };
468
469 edacmc@7e880000 {
470 compatible = "
471 reg = <0x0 0x7
472 memory-control
473 };
474
475 edacmc@7e8c0000 {
476 compatible = "
477 reg = <0x0 0x7
478 memory-control
479 };
480
481 edacpmd@7c000000 {
482 compatible = "
483 reg = <0x0 0x7
484 pmd-controller
485 };
486
487 edacpmd@7c200000 {
488 compatible = "
489 reg = <0x0 0x7
490 pmd-controller
491 };
492
493 edacpmd@7c400000 {
494 compatible = "
495 reg = <0x0 0x7
496 pmd-controller
497 };
498
499 edacpmd@7c600000 {
500 compatible = "
501 reg = <0x0 0x7
502 pmd-controller
503 };
504
505 edacl3@7e600000 {
506 compatible = "
507 reg = <0x0 0x7
508 };
509
510 edacsoc@7e930000 {
511 compatible = "
512 reg = <0x0 0x7
513 };
514 };
515
516 pmu: pmu@78810000 {
517 compatible = "apm,xgen
518 #address-cells = <2>;
519 #size-cells = <2>;
520 ranges;
521 regmap-csw = <&csw>;
522 regmap-mcba = <&mcba>;
523 regmap-mcbb = <&mcbb>;
524 reg = <0x0 0x78810000
525 interrupts = <0x0 0x22
526
527 pmul3c@7e610000 {
528 compatible = "
529 reg = <0x0 0x7
530 };
531
532 pmuiob@7e940000 {
533 compatible = "
534 reg = <0x0 0x7
535 };
536
537 pmucmcb@7e710000 {
538 compatible = "
539 reg = <0x0 0x7
540 enable-bit-ind
541 };
542
543 pmucmcb@7e730000 {
544 compatible = "
545 reg = <0x0 0x7
546 enable-bit-ind
547 };
548
549 pmucmc@7e810000 {
550 compatible = "
551 reg = <0x0 0x7
552 enable-bit-ind
553 };
554
555 pmucmc@7e850000 {
556 compatible = "
557 reg = <0x0 0x7
558 enable-bit-ind
559 };
560
561 pmucmc@7e890000 {
562 compatible = "
563 reg = <0x0 0x7
564 enable-bit-ind
565 };
566
567 pmucmc@7e8d0000 {
568 compatible = "
569 reg = <0x0 0x7
570 enable-bit-ind
571 };
572 };
573
574 mailbox: mailbox@10540000 {
575 compatible = "apm,xgen
576 reg = <0x0 0x10540000
577 #mbox-cells = <1>;
578 interrupts = <0x0 0x
579 0x0 0x
580 0x0 0x
581 0x0 0x
582 0x0 0x
583 0x0 0x
584 0x0 0x
585 0x0 0x
586 };
587
588 i2cslimpro {
589 compatible = "apm,xgen
590 mboxes = <&mailbox 0>;
591 };
592
593 hwmonslimpro {
594 compatible = "apm,xgen
595 mboxes = <&mailbox 7>;
596 };
597
598 serial0: serial@10600000 {
599 compatible = "ns16550"
600 reg = <0 0x10600000 0x
601 reg-shift = <2>;
602 clock-frequency = <100
603 interrupt-parent = <&g
604 interrupts = <0x0 0x4c
605 };
606
607 /* Node-name might need to be
608 usb0: usb@19000000 {
609 status = "disabled";
610 compatible = "snps,dwc
611 reg = <0x0 0x19000000
612 interrupts = <0x0 0x5d
613 dma-coherent;
614 dr_mode = "host";
615 };
616
617 pcie0: pcie@1f2b0000 {
618 status = "disabled";
619 device_type = "pci";
620 compatible = "apm,xgen
621 #interrupt-cells = <1>
622 #size-cells = <2>;
623 #address-cells = <3>;
624 reg = < 0x00 0x1f2b000
625 0xc0 0xd000000
626 reg-names = "csr", "cf
627 ranges = <0x01000000 0
628 0x02000000 0
629 0x43000000 0
630 dma-ranges = <0x420000
631 0x420000
632 bus-range = <0x00 0xff
633 interrupt-map-mask = <
634 interrupt-map = <0x0 0
635 0x0 0
636 0x0 0
637 0x0 0
638 dma-coherent;
639 clocks = <&pcie0clk 0>
640 msi-parent = <&v2m0>;
641 };
642
643 pcie1: pcie@1f2c0000 {
644 status = "disabled";
645 device_type = "pci";
646 compatible = "apm,xgen
647 #interrupt-cells = <1>
648 #size-cells = <2>;
649 #address-cells = <3>;
650 reg = < 0x00 0x1f2c000
651 0xa0 0xd000000
652 reg-names = "csr", "cf
653 ranges = <0x01000000 0
654 0x02000000 0
655 0x43000000 0
656 dma-ranges = <0x420000
657 0x420000
658 bus-range = <0x00 0xff
659 interrupt-map-mask = <
660 interrupt-map = <0x0 0
661 0x0 0
662 0x0 0
663 0x0 0
664 dma-coherent;
665 clocks = <&pcie1clk 0>
666 msi-parent = <&v2m0>;
667 };
668
669 sata1: sata@1a000000 {
670 compatible = "apm,xgen
671 reg = <0x0 0x1a000000
672 <0x0 0x1f200000
673 <0x0 0x1f20d000
674 <0x0 0x1f20e000
675 interrupts = <0x0 0x5a
676 dma-coherent;
677 };
678
679 sata2: sata@1a200000 {
680 compatible = "apm,xgen
681 reg = <0x0 0x1a200000
682 <0x0 0x1f210000
683 <0x0 0x1f21d000
684 <0x0 0x1f21e000
685 interrupts = <0x0 0x5b
686 dma-coherent;
687 };
688
689 sata3: sata@1a400000 {
690 compatible = "apm,xgen
691 reg = <0x0 0x1a400000
692 <0x0 0x1f220000
693 <0x0 0x1f22d000
694 <0x0 0x1f22e000
695 interrupts = <0x0 0x5c
696 dma-coherent;
697 };
698
699 mmc0: mmc@1c000000 {
700 compatible = "arasan,s
701 reg = <0x0 0x1c000000
702 interrupts = <0x0 0x49
703 dma-coherent;
704 no-1-8-v;
705 clock-names = "clk_xin
706 clocks = <&sdioclk 0>,
707 };
708
709 gfcgpio: gpio@1f63c000 {
710 compatible = "apm,xgen
711 reg = <0x0 0x1f63c000
712 gpio-controller;
713 #gpio-cells = <2>;
714 };
715
716 dwgpio: gpio@1c024000 {
717 compatible = "snps,dw-
718 reg = <0x0 0x1c024000
719 #address-cells = <1>;
720 #size-cells = <0>;
721
722 porta: gpio-controller
723 compatible = "
724 gpio-controlle
725 #gpio-cells =
726 snps,nr-gpios
727 reg = <0>;
728 };
729 };
730
731 sbgpio: gpio@17001000 {
732 compatible = "apm,xgen
733 reg = <0x0 0x17001000
734 #gpio-cells = <2>;
735 gpio-controller;
736 interrupts = <0x0 0x28
737 <0x0 0x29
738 <0x0 0x2a
739 <0x0 0x2b
740 <0x0 0x2c
741 <0x0 0x2d
742 <0x0 0x2e
743 <0x0 0x2f
744 interrupt-parent = <&g
745 #interrupt-cells = <2>
746 interrupt-controller;
747 apm,nr-gpios = <22>;
748 apm,nr-irqs = <8>;
749 apm,irq-start = <8>;
750 };
751
752 mdio: mdio@1f610000 {
753 compatible = "apm,xgen
754 #address-cells = <1>;
755 #size-cells = <0>;
756 reg = <0x0 0x1f610000
757 clocks = <&xge0clk 0>;
758 };
759
760 sgenet0: ethernet@1f610000 {
761 compatible = "apm,xgen
762 status = "disabled";
763 reg = <0x0 0x1f610000
764 <0x0 0x1f600000
765 <0x0 0x20000000
766 interrupts = <0 96 4>,
767 <0 97 4>;
768 dma-coherent;
769 clocks = <&xge0clk 0>;
770 local-mac-address = [0
771 phy-connection-type =
772 phy-handle = <&sgenet0
773 };
774
775 xgenet1: ethernet@1f620000 {
776 compatible = "apm,xgen
777 status = "disabled";
778 reg = <0x0 0x1f620000
779 <0x0 0x1f600000
780 <0x0 0x20000000
781 interrupts = <0 108 4>
782 <0 109 4>
783 <0 110 4>
784 <0 111 4>
785 <0 112 4>
786 <0 113 4>
787 <0 114 4>
788 <0 115 4>
789 channel = <12>;
790 port-id = <1>;
791 dma-coherent;
792 clocks = <&xge1clk 0>;
793 local-mac-address = [0
794 phy-connection-type =
795 };
796
797 rng: rng@10520000 {
798 compatible = "apm,xgen
799 reg = <0x0 0x10520000
800 interrupts = <0x0 0x41
801 clocks = <&rngpkaclk 0
802 };
803
804 i2c1: i2c@10511000 {
805 #address-cells = <1>;
806 #size-cells = <0>;
807 compatible = "snps,des
808 reg = <0x0 0x10511000
809 interrupts = <0 0x45 0
810 #clock-cells = <1>;
811 clocks = <&sbapbclk 0>
812 bus_num = <1>;
813 };
814
815 i2c4: i2c@10640000 {
816 #address-cells = <1>;
817 #size-cells = <0>;
818 compatible = "snps,des
819 reg = <0x0 0x10640000
820 interrupts = <0 0x3a 0
821 clocks = <&i2c4clk 0>;
822 bus_num = <4>;
823 };
824 };
825 };
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