1 // SPDX-License-Identifier: GPL-2.0
2 #include "juno-clocks.dtsi"
3 #include "juno-motherboard.dtsi"
4
5 / {
6 /*
7 * Devices shared by all Juno boards
8 */
9
10 memtimer: timer@2a810000 {
11 compatible = "arm,armv7-timer-
12 reg = <0x0 0x2a810000 0x0 0x10
13 clock-frequency = <50000000>;
14 #address-cells = <1>;
15 #size-cells = <1>;
16 ranges = <0 0x0 0x2a820000 0x2
17 status = "disabled";
18 frame@2a830000 {
19 frame-number = <1>;
20 interrupts = <GIC_SPI
21 reg = <0x10000 0x10000
22 };
23 };
24
25 mailbox: mhu@2b1f0000 {
26 compatible = "arm,mhu", "arm,p
27 reg = <0x0 0x2b1f0000 0x0 0x10
28 interrupts = <GIC_SPI 36 IRQ_T
29 <GIC_SPI 35 IRQ_T
30 <GIC_SPI 37 IRQ_T
31 #mbox-cells = <1>;
32 clocks = <&soc_refclk100mhz>;
33 clock-names = "apb_pclk";
34 };
35
36 smmu_gpu: iommu@2b400000 {
37 compatible = "arm,mmu-400", "a
38 reg = <0x0 0x2b400000 0x0 0x10
39 interrupts = <GIC_SPI 38 IRQ_T
40 <GIC_SPI 38 IRQ_T
41 #iommu-cells = <1>;
42 #global-interrupts = <1>;
43 power-domains = <&scpi_devpd 1
44 dma-coherent;
45 status = "disabled";
46 };
47
48 smmu_pcie: iommu@2b500000 {
49 compatible = "arm,mmu-401", "a
50 reg = <0x0 0x2b500000 0x0 0x10
51 interrupts = <GIC_SPI 40 IRQ_T
52 <GIC_SPI 40 IRQ_T
53 #iommu-cells = <1>;
54 #global-interrupts = <1>;
55 dma-coherent;
56 status = "disabled";
57 };
58
59 smmu_etr: iommu@2b600000 {
60 compatible = "arm,mmu-401", "a
61 reg = <0x0 0x2b600000 0x0 0x10
62 interrupts = <GIC_SPI 42 IRQ_T
63 <GIC_SPI 42 IRQ_T
64 #iommu-cells = <1>;
65 #global-interrupts = <1>;
66 dma-coherent;
67 power-domains = <&scpi_devpd 0
68 };
69
70 gic: interrupt-controller@2c010000 {
71 compatible = "arm,gic-400", "a
72 reg = <0x0 0x2c010000 0 0x1000
73 <0x0 0x2c02f000 0 0x2000
74 <0x0 0x2c04f000 0 0x2000
75 <0x0 0x2c06f000 0 0x2000
76 #address-cells = <1>;
77 #interrupt-cells = <3>;
78 #size-cells = <1>;
79 interrupt-controller;
80 interrupts = <GIC_PPI 9 (GIC_C
81 ranges = <0 0 0x2c1c0000 0x400
82
83 v2m_0: v2m@0 {
84 compatible = "arm,gic-
85 msi-controller;
86 reg = <0 0x10000>;
87 };
88
89 v2m@10000 {
90 compatible = "arm,gic-
91 msi-controller;
92 reg = <0x10000 0x10000
93 };
94
95 v2m@20000 {
96 compatible = "arm,gic-
97 msi-controller;
98 reg = <0x20000 0x10000
99 };
100
101 v2m@30000 {
102 compatible = "arm,gic-
103 msi-controller;
104 reg = <0x30000 0x10000
105 };
106 };
107
108 timer {
109 compatible = "arm,armv8-timer"
110 interrupts = <GIC_PPI 13 (GIC_
111 <GIC_PPI 14 (GIC_
112 <GIC_PPI 11 (GIC_
113 <GIC_PPI 10 (GIC_
114 };
115
116 /*
117 * Juno TRMs specify the size for thes
118 * The actual size is just 4K though 6
119 * unmapped reserved region results in
120 */
121 etf_sys0: etf@20010000 { /* etf0 */
122 compatible = "arm,coresight-tm
123 reg = <0 0x20010000 0 0x1000>;
124
125 clocks = <&soc_smc50mhz>;
126 clock-names = "apb_pclk";
127 power-domains = <&scpi_devpd 0
128
129 in-ports {
130 port {
131 etf0_in_port:
132 remote
133 };
134 };
135 };
136
137 out-ports {
138 port {
139 etf0_out_port:
140 };
141 };
142 };
143 };
144
145 tpiu_sys: tpiu@20030000 {
146 compatible = "arm,coresight-tp
147 reg = <0 0x20030000 0 0x1000>;
148
149 clocks = <&soc_smc50mhz>;
150 clock-names = "apb_pclk";
151 power-domains = <&scpi_devpd 0
152 in-ports {
153 port {
154 tpiu_in_port:
155 remote
156 };
157 };
158 };
159 };
160
161 /* main funnel on Juno r0, cssys0 funn
162 main_funnel: funnel@20040000 {
163 compatible = "arm,coresight-dy
164 reg = <0 0x20040000 0 0x1000>;
165
166 clocks = <&soc_smc50mhz>;
167 clock-names = "apb_pclk";
168 power-domains = <&scpi_devpd 0
169
170 out-ports {
171 port {
172 main_funnel_ou
173 remote
174 };
175 };
176 };
177
178 main_funnel_in_ports: in-ports
179 #address-cells = <1>;
180 #size-cells = <0>;
181
182 port@0 {
183 reg = <0>;
184 main_funnel_in
185 remote
186 };
187 };
188
189 port@1 {
190 reg = <1>;
191 main_funnel_in
192 remote
193 };
194 };
195 };
196 };
197
198 etr_sys: etr@20070000 {
199 compatible = "arm,coresight-tm
200 reg = <0 0x20070000 0 0x1000>;
201 iommus = <&smmu_etr 0>;
202
203 clocks = <&soc_smc50mhz>;
204 clock-names = "apb_pclk";
205 power-domains = <&scpi_devpd 0
206 arm,scatter-gather;
207 in-ports {
208 port {
209 etr_in_port: e
210 remote
211 };
212 };
213 };
214 };
215
216 stm_sys: stm@20100000 {
217 compatible = "arm,coresight-st
218 reg = <0 0x20100000 0 0x1000>,
219 <0 0x28000000 0 0x100000
220 reg-names = "stm-base", "stm-s
221
222 clocks = <&soc_smc50mhz>;
223 clock-names = "apb_pclk";
224 power-domains = <&scpi_devpd 0
225 out-ports {
226 port {
227 stm_out_port:
228 };
229 };
230 };
231 };
232
233 replicator@20120000 {
234 compatible = "arm,coresight-dy
235 reg = <0 0x20120000 0 0x1000>;
236
237 clocks = <&soc_smc50mhz>;
238 clock-names = "apb_pclk";
239 power-domains = <&scpi_devpd 0
240
241 out-ports {
242 #address-cells = <1>;
243 #size-cells = <0>;
244
245 /* replicator output p
246 port@0 {
247 reg = <0>;
248 replicator_out
249 remote
250 };
251 };
252
253 port@1 {
254 reg = <1>;
255 replicator_out
256 remote
257 };
258 };
259 };
260 in-ports {
261 port {
262 replicator_in_
263 };
264 };
265 };
266 };
267
268 cpu_debug0: cpu-debug@22010000 {
269 compatible = "arm,coresight-cp
270 reg = <0x0 0x22010000 0x0 0x10
271
272 clocks = <&soc_smc50mhz>;
273 clock-names = "apb_pclk";
274 power-domains = <&scpi_devpd 0
275 };
276
277 etm0: etm@22040000 {
278 compatible = "arm,coresight-et
279 reg = <0 0x22040000 0 0x1000>;
280
281 clocks = <&soc_smc50mhz>;
282 clock-names = "apb_pclk";
283 power-domains = <&scpi_devpd 0
284 out-ports {
285 port {
286 cluster0_etm0_
287 remote
288 };
289 };
290 };
291 };
292
293 cti0: cti@22020000 {
294 compatible = "arm,coresight-ct
295 "arm,primecell";
296 reg = <0 0x22020000 0 0x1000>;
297
298 clocks = <&soc_smc50mhz>;
299 clock-names = "apb_pclk";
300 power-domains = <&scpi_devpd 0
301
302 arm,cs-dev-assoc = <&etm0>;
303 };
304
305 funnel@220c0000 { /* cluster0 funnel *
306 compatible = "arm,coresight-dy
307 reg = <0 0x220c0000 0 0x1000>;
308
309 clocks = <&soc_smc50mhz>;
310 clock-names = "apb_pclk";
311 power-domains = <&scpi_devpd 0
312 out-ports {
313 port {
314 cluster0_funne
315 remote
316 };
317 };
318 };
319
320 in-ports {
321 #address-cells = <1>;
322 #size-cells = <0>;
323
324 port@0 {
325 reg = <0>;
326 cluster0_funne
327 remote
328 };
329 };
330
331 port@1 {
332 reg = <1>;
333 cluster0_funne
334 remote
335 };
336 };
337 };
338 };
339
340 cpu_debug1: cpu-debug@22110000 {
341 compatible = "arm,coresight-cp
342 reg = <0x0 0x22110000 0x0 0x10
343
344 clocks = <&soc_smc50mhz>;
345 clock-names = "apb_pclk";
346 power-domains = <&scpi_devpd 0
347 };
348
349 etm1: etm@22140000 {
350 compatible = "arm,coresight-et
351 reg = <0 0x22140000 0 0x1000>;
352
353 clocks = <&soc_smc50mhz>;
354 clock-names = "apb_pclk";
355 power-domains = <&scpi_devpd 0
356 out-ports {
357 port {
358 cluster0_etm1_
359 remote
360 };
361 };
362 };
363 };
364
365 cti1: cti@22120000 {
366 compatible = "arm,coresight-ct
367 "arm,primecell";
368 reg = <0 0x22120000 0 0x1000>;
369
370 clocks = <&soc_smc50mhz>;
371 clock-names = "apb_pclk";
372 power-domains = <&scpi_devpd 0
373
374 arm,cs-dev-assoc = <&etm1>;
375 };
376
377 cpu_debug2: cpu-debug@23010000 {
378 compatible = "arm,coresight-cp
379 reg = <0x0 0x23010000 0x0 0x10
380
381 clocks = <&soc_smc50mhz>;
382 clock-names = "apb_pclk";
383 power-domains = <&scpi_devpd 0
384 };
385
386 etm2: etm@23040000 {
387 compatible = "arm,coresight-et
388 reg = <0 0x23040000 0 0x1000>;
389
390 clocks = <&soc_smc50mhz>;
391 clock-names = "apb_pclk";
392 power-domains = <&scpi_devpd 0
393 out-ports {
394 port {
395 cluster1_etm0_
396 remote
397 };
398 };
399 };
400 };
401
402 cti2: cti@23020000 {
403 compatible = "arm,coresight-ct
404 "arm,primecell";
405 reg = <0 0x23020000 0 0x1000>;
406
407 clocks = <&soc_smc50mhz>;
408 clock-names = "apb_pclk";
409 power-domains = <&scpi_devpd 0
410
411 arm,cs-dev-assoc = <&etm2>;
412 };
413
414 funnel@230c0000 { /* cluster1 funnel *
415 compatible = "arm,coresight-dy
416 reg = <0 0x230c0000 0 0x1000>;
417
418 clocks = <&soc_smc50mhz>;
419 clock-names = "apb_pclk";
420 power-domains = <&scpi_devpd 0
421 out-ports {
422 port {
423 cluster1_funne
424 remote
425 };
426 };
427 };
428
429 in-ports {
430 #address-cells = <1>;
431 #size-cells = <0>;
432
433 port@0 {
434 reg = <0>;
435 cluster1_funne
436 remote
437 };
438 };
439
440 port@1 {
441 reg = <1>;
442 cluster1_funne
443 remote
444 };
445 };
446 port@2 {
447 reg = <2>;
448 cluster1_funne
449 remote
450 };
451 };
452 port@3 {
453 reg = <3>;
454 cluster1_funne
455 remote
456 };
457 };
458 };
459 };
460
461 cpu_debug3: cpu-debug@23110000 {
462 compatible = "arm,coresight-cp
463 reg = <0x0 0x23110000 0x0 0x10
464
465 clocks = <&soc_smc50mhz>;
466 clock-names = "apb_pclk";
467 power-domains = <&scpi_devpd 0
468 };
469
470 etm3: etm@23140000 {
471 compatible = "arm,coresight-et
472 reg = <0 0x23140000 0 0x1000>;
473
474 clocks = <&soc_smc50mhz>;
475 clock-names = "apb_pclk";
476 power-domains = <&scpi_devpd 0
477 out-ports {
478 port {
479 cluster1_etm1_
480 remote
481 };
482 };
483 };
484 };
485
486 cti3: cti@23120000 {
487 compatible = "arm,coresight-ct
488 "arm,primecell";
489 reg = <0 0x23120000 0 0x1000>;
490
491 clocks = <&soc_smc50mhz>;
492 clock-names = "apb_pclk";
493 power-domains = <&scpi_devpd 0
494
495 arm,cs-dev-assoc = <&etm3>;
496 };
497
498 cpu_debug4: cpu-debug@23210000 {
499 compatible = "arm,coresight-cp
500 reg = <0x0 0x23210000 0x0 0x10
501
502 clocks = <&soc_smc50mhz>;
503 clock-names = "apb_pclk";
504 power-domains = <&scpi_devpd 0
505 };
506
507 etm4: etm@23240000 {
508 compatible = "arm,coresight-et
509 reg = <0 0x23240000 0 0x1000>;
510
511 clocks = <&soc_smc50mhz>;
512 clock-names = "apb_pclk";
513 power-domains = <&scpi_devpd 0
514 out-ports {
515 port {
516 cluster1_etm2_
517 remote
518 };
519 };
520 };
521 };
522
523 cti4: cti@23220000 {
524 compatible = "arm,coresight-ct
525 "arm,primecell";
526 reg = <0 0x23220000 0 0x1000>;
527
528 clocks = <&soc_smc50mhz>;
529 clock-names = "apb_pclk";
530 power-domains = <&scpi_devpd 0
531
532 arm,cs-dev-assoc = <&etm4>;
533 };
534
535 cpu_debug5: cpu-debug@23310000 {
536 compatible = "arm,coresight-cp
537 reg = <0x0 0x23310000 0x0 0x10
538
539 clocks = <&soc_smc50mhz>;
540 clock-names = "apb_pclk";
541 power-domains = <&scpi_devpd 0
542 };
543
544 etm5: etm@23340000 {
545 compatible = "arm,coresight-et
546 reg = <0 0x23340000 0 0x1000>;
547
548 clocks = <&soc_smc50mhz>;
549 clock-names = "apb_pclk";
550 power-domains = <&scpi_devpd 0
551 out-ports {
552 port {
553 cluster1_etm3_
554 remote
555 };
556 };
557 };
558 };
559
560 cti5: cti@23320000 {
561 compatible = "arm,coresight-ct
562 "arm,primecell";
563 reg = <0 0x23320000 0 0x1000>;
564
565 clocks = <&soc_smc50mhz>;
566 clock-names = "apb_pclk";
567 power-domains = <&scpi_devpd 0
568
569 arm,cs-dev-assoc = <&etm5>;
570 };
571
572 cti_sys0: cti@20020000 { /* sys_cti_0
573 compatible = "arm,coresight-ct
574 reg = <0 0x20020000 0 0x1000>;
575
576 clocks = <&soc_smc50mhz>;
577 clock-names = "apb_pclk";
578 power-domains = <&scpi_devpd 0
579
580 #address-cells = <1>;
581 #size-cells = <0>;
582
583 trig-conns@0 {
584 reg = <0>;
585 arm,trig-in-sigs = <2
586 arm,trig-in-types = <S
587 arm,trig-out-sigs = <0
588 arm,trig-out-types = <
589 arm,cs-dev-assoc = <&e
590 };
591
592 trig-conns@1 {
593 reg = <1>;
594 arm,trig-in-sigs = <0
595 arm,trig-in-types = <S
596 arm,trig-out-sigs = <7
597 arm,trig-out-types = <
598 arm,cs-dev-assoc = <&e
599 };
600
601 trig-conns@2 {
602 reg = <2>;
603 arm,trig-in-sigs = <4
604 arm,trig-in-types = <S
605 STM
606 arm,trig-out-sigs = <4
607 arm,trig-out-types = <
608 arm,cs-dev-assoc = <&s
609 };
610
611 trig-conns@3 {
612 reg = <3>;
613 arm,trig-out-sigs = <2
614 arm,trig-out-types = <
615 arm,cs-dev-assoc = <&t
616 };
617 };
618
619 cti_sys1: cti@20110000 { /* sys_cti_1
620 compatible = "arm,coresight-ct
621 reg = <0 0x20110000 0 0x1000>;
622
623 clocks = <&soc_smc50mhz>;
624 clock-names = "apb_pclk";
625 power-domains = <&scpi_devpd 0
626
627 #address-cells = <1>;
628 #size-cells = <0>;
629
630 trig-conns@0 {
631 reg = <0>;
632 arm,trig-in-sigs = <0>
633 arm,trig-in-types = <G
634 arm,trig-out-sigs = <0
635 arm,trig-out-types = <
636 arm,trig-conn-name = "
637 };
638
639 trig-conns@1 {
640 reg = <1>;
641 arm,trig-out-sigs = <2
642 arm,trig-out-types = <
643 arm,trig-conn-name = "
644 };
645
646 trig-conns@2 {
647 reg = <2>;
648 arm,trig-out-sigs = <1
649 arm,trig-out-types = <
650 arm,trig-conn-name = "
651 };
652 };
653
654 gpu: gpu@2d000000 {
655 compatible = "arm,juno-mali",
656 reg = <0 0x2d000000 0 0x10000>
657 interrupts = <GIC_SPI 33 IRQ_T
658 <GIC_SPI 34 IRQ_T
659 <GIC_SPI 32 IRQ_T
660 interrupt-names = "job", "mmu"
661 clocks = <&scpi_dvfs 2>;
662 power-domains = <&scpi_devpd 1
663 dma-coherent;
664 /* The SMMU is only really of
665 /* iommus = <&smmu_gpu 0>; */
666 };
667
668 sram: sram@2e000000 {
669 compatible = "arm,juno-sram-ns
670 reg = <0x0 0x2e000000 0x0 0x80
671
672 #address-cells = <1>;
673 #size-cells = <1>;
674 ranges = <0 0x0 0x2e000000 0x8
675
676 cpu_scp_lpri: scp-sram@0 {
677 compatible = "arm,juno
678 reg = <0x0 0x200>;
679 };
680
681 cpu_scp_hpri: scp-sram@200 {
682 compatible = "arm,juno
683 reg = <0x200 0x200>;
684 };
685 };
686
687 pcie_ctlr: pcie@40000000 {
688 compatible = "arm,juno-r1-pcie
689 device_type = "pci";
690 reg = <0 0x40000000 0 0x100000
691 bus-range = <0 255>;
692 linux,pci-domain = <0>;
693 #address-cells = <3>;
694 #size-cells = <2>;
695 dma-coherent;
696 ranges = <0x01000000 0x00 0x00
697 <0x02000000 0x00 0x50
698 <0x42000000 0x40 0x00
699 /* Standard AXI Translation en
700 dma-ranges = <0x02000000 0x0 0
701 <0x43000000 0x8 0
702 #interrupt-cells = <1>;
703 interrupt-map-mask = <0 0 0 7>
704 interrupt-map = <0 0 0 1 &gic
705 <0 0 0 2 &gic
706 <0 0 0 3 &gic
707 <0 0 0 4 &gic
708 msi-parent = <&v2m_0>;
709 status = "disabled";
710 iommu-map-mask = <0x0>; /* RC
711 iommu-map = <0x0 &smmu_pcie 0x
712 };
713
714 scpi {
715 compatible = "arm,scpi";
716 mboxes = <&mailbox 1>;
717 shmem = <&cpu_scp_hpri>;
718
719 clocks {
720 compatible = "arm,scpi
721
722 scpi_dvfs: clocks-0 {
723 compatible = "
724 #clock-cells =
725 clock-indices
726 clock-output-n
727 };
728 scpi_clk: clocks-1 {
729 compatible = "
730 #clock-cells =
731 clock-indices
732 clock-output-n
733 };
734 };
735
736 scpi_devpd: power-controller {
737 compatible = "arm,scpi
738 num-domains = <2>;
739 #power-domain-cells =
740 };
741
742 scpi_sensors0: sensors {
743 compatible = "arm,scpi
744 #thermal-sensor-cells
745 };
746 };
747
748 thermal-zones {
749 pmic-thermal {
750 polling-delay = <1000>
751 polling-delay-passive
752 thermal-sensors = <&sc
753 trips {
754 pmic_crit0: tr
755 temper
756 hyster
757 type =
758 };
759 };
760 };
761
762 soc-thermal {
763 polling-delay = <1000>
764 polling-delay-passive
765 thermal-sensors = <&sc
766 trips {
767 soc_crit0: tri
768 temper
769 hyster
770 type =
771 };
772 };
773 };
774
775 big_cluster_thermal_zone: big-
776 polling-delay = <1000>
777 polling-delay-passive
778 thermal-sensors = <&sc
779 status = "disabled";
780 };
781
782 little_cluster_thermal_zone: l
783 polling-delay = <1000>
784 polling-delay-passive
785 thermal-sensors = <&sc
786 status = "disabled";
787 };
788
789 gpu0_thermal_zone: gpu0-therma
790 polling-delay = <1000>
791 polling-delay-passive
792 thermal-sensors = <&sc
793 status = "disabled";
794 };
795
796 gpu1_thermal_zone: gpu1-therma
797 polling-delay = <1000>
798 polling-delay-passive
799 thermal-sensors = <&sc
800 status = "disabled";
801 };
802 };
803
804 smmu_dma: iommu@7fb00000 {
805 compatible = "arm,mmu-401", "a
806 reg = <0x0 0x7fb00000 0x0 0x10
807 interrupts = <GIC_SPI 95 IRQ_T
808 <GIC_SPI 95 IRQ_T
809 #iommu-cells = <1>;
810 #global-interrupts = <1>;
811 dma-coherent;
812 };
813
814 smmu_hdlcd1: iommu@7fb10000 {
815 compatible = "arm,mmu-401", "a
816 reg = <0x0 0x7fb10000 0x0 0x10
817 interrupts = <GIC_SPI 99 IRQ_T
818 <GIC_SPI 99 IRQ_T
819 #iommu-cells = <1>;
820 #global-interrupts = <1>;
821 };
822
823 smmu_hdlcd0: iommu@7fb20000 {
824 compatible = "arm,mmu-401", "a
825 reg = <0x0 0x7fb20000 0x0 0x10
826 interrupts = <GIC_SPI 97 IRQ_T
827 <GIC_SPI 97 IRQ_T
828 #iommu-cells = <1>;
829 #global-interrupts = <1>;
830 };
831
832 smmu_usb: iommu@7fb30000 {
833 compatible = "arm,mmu-401", "a
834 reg = <0x0 0x7fb30000 0x0 0x10
835 interrupts = <GIC_SPI 101 IRQ_
836 <GIC_SPI 101 IRQ_
837 #iommu-cells = <1>;
838 #global-interrupts = <1>;
839 dma-coherent;
840 };
841
842 dma-controller@7ff00000 {
843 compatible = "arm,pl330", "arm
844 reg = <0x0 0x7ff00000 0 0x1000
845 #dma-cells = <1>;
846 interrupts = <GIC_SPI 88 IRQ_T
847 <GIC_SPI 89 IRQ_T
848 <GIC_SPI 90 IRQ_T
849 <GIC_SPI 91 IRQ_T
850 <GIC_SPI 92 IRQ_T
851 <GIC_SPI 108 IRQ_
852 <GIC_SPI 109 IRQ_
853 <GIC_SPI 110 IRQ_
854 <GIC_SPI 111 IRQ_
855 iommus = <&smmu_dma 0>,
856 <&smmu_dma 1>,
857 <&smmu_dma 2>,
858 <&smmu_dma 3>,
859 <&smmu_dma 4>,
860 <&smmu_dma 5>,
861 <&smmu_dma 6>,
862 <&smmu_dma 7>,
863 <&smmu_dma 8>;
864 clocks = <&soc_faxiclk>;
865 clock-names = "apb_pclk";
866 };
867
868 hdlcd@7ff50000 {
869 compatible = "arm,hdlcd";
870 reg = <0 0x7ff50000 0 0x1000>;
871 interrupts = <GIC_SPI 93 IRQ_T
872 iommus = <&smmu_hdlcd1 0>;
873 clocks = <&scpi_clk 3>;
874 clock-names = "pxlclk";
875
876 port {
877 hdlcd1_output: endpoin
878 remote-endpoin
879 };
880 };
881 };
882
883 hdlcd@7ff60000 {
884 compatible = "arm,hdlcd";
885 reg = <0 0x7ff60000 0 0x1000>;
886 interrupts = <GIC_SPI 85 IRQ_T
887 iommus = <&smmu_hdlcd0 0>;
888 clocks = <&scpi_clk 3>;
889 clock-names = "pxlclk";
890
891 port {
892 hdlcd0_output: endpoin
893 remote-endpoin
894 };
895 };
896 };
897
898 soc_uart0: serial@7ff80000 {
899 compatible = "arm,pl011", "arm
900 reg = <0x0 0x7ff80000 0x0 0x10
901 interrupts = <GIC_SPI 83 IRQ_T
902 clocks = <&soc_uartclk>, <&soc
903 clock-names = "uartclk", "apb_
904 };
905
906 i2c@7ffa0000 {
907 compatible = "snps,designware-
908 reg = <0x0 0x7ffa0000 0x0 0x10
909 #address-cells = <1>;
910 #size-cells = <0>;
911 interrupts = <GIC_SPI 104 IRQ_
912 clock-frequency = <400000>;
913 i2c-sda-hold-time-ns = <500>;
914 clocks = <&soc_smc50mhz>;
915
916 hdmi-transmitter@70 {
917 compatible = "nxp,tda9
918 reg = <0x70>;
919 port {
920 tda998x_0_inpu
921 remote
922 };
923 };
924 };
925
926 hdmi-transmitter@71 {
927 compatible = "nxp,tda9
928 reg = <0x71>;
929 port {
930 tda998x_1_inpu
931 remote
932 };
933 };
934 };
935 };
936
937 usb@7ffb0000 {
938 compatible = "generic-ohci";
939 reg = <0x0 0x7ffb0000 0x0 0x10
940 interrupts = <GIC_SPI 116 IRQ_
941 iommus = <&smmu_usb 0>;
942 clocks = <&soc_usb48mhz>;
943 };
944
945 usb@7ffc0000 {
946 compatible = "generic-ehci";
947 reg = <0x0 0x7ffc0000 0x0 0x10
948 interrupts = <GIC_SPI 117 IRQ_
949 iommus = <&smmu_usb 0>;
950 clocks = <&soc_usb48mhz>;
951 };
952
953 memory-controller@7ffd0000 {
954 compatible = "arm,pl354", "arm
955 reg = <0 0x7ffd0000 0 0x1000>;
956 interrupts = <GIC_SPI 86 IRQ_T
957 <GIC_SPI 87 IRQ_T
958 clocks = <&soc_smc50mhz>;
959 clock-names = "apb_pclk";
960 };
961
962 memory@80000000 {
963 device_type = "memory";
964 /* last 16MB of the first memo
965 reg = <0x00000000 0x80000000 0
966 <0x00000008 0x80000000 0
967 };
968
969 bus@8000000 {
970 #interrupt-cells = <1>;
971 interrupt-map-mask = <0 0 15>;
972 interrupt-map = <0 0 0 &gic 0
973 <0 0 1 &gic 0
974 <0 0 2 &gic 0
975 <0 0 3 &gic 0
976 <0 0 4 &gic 0
977 <0 0 5 &gic 0
978 <0 0 6 &gic 0
979 <0 0 7 &gic 0
980 <0 0 8 &gic 0
981 <0 0 9 &gic 0
982 <0 0 10 &gic 0
983 <0 0 11 &gic 0
984 <0 0 12 &gic 0
985 };
986
987 site2: tlx-bus@60000000 {
988 compatible = "simple-bus";
989 #address-cells = <1>;
990 #size-cells = <1>;
991 ranges = <0 0 0x60000000 0x100
992 #interrupt-cells = <1>;
993 interrupt-map-mask = <0 0>;
994 interrupt-map = <0 0 &gic 0 GI
995 };
996 };
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