1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Samsung's Exynos5433 SoC device tree source
4 *
5 * Copyright (c) 2016 Samsung Electronics Co.,
6 *
7 * Samsung's Exynos5433 SoC device nodes are l
8 * Exynos5433 based board files can include th
9 * values for board specific bindings.
10 *
11 * Note: This file does not include device nod
12 * Exynos5433 SoC. As device tree coverage for
13 * additional nodes can be added to this file.
14 */
15
16 #include <dt-bindings/clock/exynos5433.h>
17 #include <dt-bindings/interrupt-controller/arm
18
19 / {
20 compatible = "samsung,exynos5433";
21 #address-cells = <2>;
22 #size-cells = <2>;
23
24 interrupt-parent = <&gic>;
25
26 arm-a53-pmu {
27 compatible = "arm,cortex-a53-p
28 interrupts = <GIC_SPI 32 IRQ_T
29 <GIC_SPI 33 IRQ_T
30 <GIC_SPI 34 IRQ_T
31 <GIC_SPI 35 IRQ_T
32 interrupt-affinity = <&cpu0>,
33 };
34
35 arm-a57-pmu {
36 compatible = "arm,cortex-a57-p
37 interrupts = <GIC_SPI 52 IRQ_T
38 <GIC_SPI 53 IRQ_T
39 <GIC_SPI 54 IRQ_T
40 <GIC_SPI 55 IRQ_T
41 interrupt-affinity = <&cpu4>,
42 };
43
44 xxti: clock {
45 /* XXTI */
46 compatible = "fixed-clock";
47 clock-output-names = "oscclk";
48 #clock-cells = <0>;
49 };
50
51 cpus {
52 #address-cells = <1>;
53 #size-cells = <0>;
54
55 cpu-map {
56 cluster0 {
57 core0 {
58 cpu =
59 };
60 core1 {
61 cpu =
62 };
63 core2 {
64 cpu =
65 };
66 core3 {
67 cpu =
68 };
69 };
70
71 cluster1 {
72 core0 {
73 cpu =
74 };
75 core1 {
76 cpu =
77 };
78 core2 {
79 cpu =
80 };
81 core3 {
82 cpu =
83 };
84 };
85 };
86
87 cpu0: cpu@100 {
88 device_type = "cpu";
89 compatible = "arm,cort
90 enable-method = "psci"
91 reg = <0x100>;
92 clocks = <&cmu_apollo
93 clock-names = "apolloc
94 operating-points-v2 =
95 #cooling-cells = <2>;
96 i-cache-size = <0x8000
97 i-cache-line-size = <6
98 i-cache-sets = <256>;
99 d-cache-size = <0x8000
100 d-cache-line-size = <6
101 d-cache-sets = <128>;
102 next-level-cache = <&c
103 };
104
105 cpu1: cpu@101 {
106 device_type = "cpu";
107 compatible = "arm,cort
108 enable-method = "psci"
109 reg = <0x101>;
110 operating-points-v2 =
111 #cooling-cells = <2>;
112 i-cache-size = <0x8000
113 i-cache-line-size = <6
114 i-cache-sets = <256>;
115 d-cache-size = <0x8000
116 d-cache-line-size = <6
117 d-cache-sets = <128>;
118 next-level-cache = <&c
119 };
120
121 cpu2: cpu@102 {
122 device_type = "cpu";
123 compatible = "arm,cort
124 enable-method = "psci"
125 reg = <0x102>;
126 operating-points-v2 =
127 #cooling-cells = <2>;
128 i-cache-size = <0x8000
129 i-cache-line-size = <6
130 i-cache-sets = <256>;
131 d-cache-size = <0x8000
132 d-cache-line-size = <6
133 d-cache-sets = <128>;
134 next-level-cache = <&c
135 };
136
137 cpu3: cpu@103 {
138 device_type = "cpu";
139 compatible = "arm,cort
140 enable-method = "psci"
141 reg = <0x103>;
142 operating-points-v2 =
143 #cooling-cells = <2>;
144 i-cache-size = <0x8000
145 i-cache-line-size = <6
146 i-cache-sets = <256>;
147 d-cache-size = <0x8000
148 d-cache-line-size = <6
149 d-cache-sets = <128>;
150 next-level-cache = <&c
151 };
152
153 cpu4: cpu@0 {
154 device_type = "cpu";
155 compatible = "arm,cort
156 enable-method = "psci"
157 reg = <0x0>;
158 clocks = <&cmu_atlas C
159 clock-names = "atlascl
160 operating-points-v2 =
161 #cooling-cells = <2>;
162 i-cache-size = <0xc000
163 i-cache-line-size = <6
164 i-cache-sets = <256>;
165 d-cache-size = <0x8000
166 d-cache-line-size = <6
167 d-cache-sets = <256>;
168 next-level-cache = <&c
169 };
170
171 cpu5: cpu@1 {
172 device_type = "cpu";
173 compatible = "arm,cort
174 enable-method = "psci"
175 reg = <0x1>;
176 operating-points-v2 =
177 #cooling-cells = <2>;
178 i-cache-size = <0xc000
179 i-cache-line-size = <6
180 i-cache-sets = <256>;
181 d-cache-size = <0x8000
182 d-cache-line-size = <6
183 d-cache-sets = <256>;
184 next-level-cache = <&c
185 };
186
187 cpu6: cpu@2 {
188 device_type = "cpu";
189 compatible = "arm,cort
190 enable-method = "psci"
191 reg = <0x2>;
192 operating-points-v2 =
193 #cooling-cells = <2>;
194 i-cache-size = <0xc000
195 i-cache-line-size = <6
196 i-cache-sets = <256>;
197 d-cache-size = <0x8000
198 d-cache-line-size = <6
199 d-cache-sets = <256>;
200 next-level-cache = <&c
201 };
202
203 cpu7: cpu@3 {
204 device_type = "cpu";
205 compatible = "arm,cort
206 enable-method = "psci"
207 reg = <0x3>;
208 operating-points-v2 =
209 #cooling-cells = <2>;
210 i-cache-size = <0xc000
211 i-cache-line-size = <6
212 i-cache-sets = <256>;
213 d-cache-size = <0x8000
214 d-cache-line-size = <6
215 d-cache-sets = <256>;
216 next-level-cache = <&c
217 };
218
219 cluster_a57_l2: l2-cache0 {
220 compatible = "cache";
221 cache-level = <2>;
222 cache-unified;
223 cache-size = <0x200000
224 cache-line-size = <64>
225 cache-sets = <2048>;
226 };
227
228 cluster_a53_l2: l2-cache1 {
229 compatible = "cache";
230 cache-level = <2>;
231 cache-unified;
232 cache-size = <0x40000>
233 cache-line-size = <64>
234 cache-sets = <256>;
235 };
236 };
237
238 cluster_a53_opp_table: opp-table-0 {
239 compatible = "operating-points
240 opp-shared;
241
242 opp-400000000 {
243 opp-hz = /bits/ 64 <40
244 opp-microvolt = <90000
245 };
246 opp-500000000 {
247 opp-hz = /bits/ 64 <50
248 opp-microvolt = <92500
249 };
250 opp-600000000 {
251 opp-hz = /bits/ 64 <60
252 opp-microvolt = <95000
253 };
254 opp-700000000 {
255 opp-hz = /bits/ 64 <70
256 opp-microvolt = <97500
257 };
258 opp-800000000 {
259 opp-hz = /bits/ 64 <80
260 opp-microvolt = <10000
261 };
262 opp-900000000 {
263 opp-hz = /bits/ 64 <90
264 opp-microvolt = <10500
265 };
266 opp-1000000000 {
267 opp-hz = /bits/ 64 <10
268 opp-microvolt = <10750
269 };
270 opp-1100000000 {
271 opp-hz = /bits/ 64 <11
272 opp-microvolt = <11125
273 };
274 opp-1200000000 {
275 opp-hz = /bits/ 64 <12
276 opp-microvolt = <11125
277 };
278 opp-1300000000 {
279 opp-hz = /bits/ 64 <13
280 opp-microvolt = <11500
281 };
282 };
283
284 cluster_a57_opp_table: opp-table-1 {
285 compatible = "operating-points
286 opp-shared;
287
288 opp-500000000 {
289 opp-hz = /bits/ 64 <50
290 opp-microvolt = <90000
291 };
292 opp-600000000 {
293 opp-hz = /bits/ 64 <60
294 opp-microvolt = <90000
295 };
296 opp-700000000 {
297 opp-hz = /bits/ 64 <70
298 opp-microvolt = <91250
299 };
300 opp-800000000 {
301 opp-hz = /bits/ 64 <80
302 opp-microvolt = <91250
303 };
304 opp-900000000 {
305 opp-hz = /bits/ 64 <90
306 opp-microvolt = <93750
307 };
308 opp-1000000000 {
309 opp-hz = /bits/ 64 <10
310 opp-microvolt = <97500
311 };
312 opp-1100000000 {
313 opp-hz = /bits/ 64 <11
314 opp-microvolt = <10125
315 };
316 opp-1200000000 {
317 opp-hz = /bits/ 64 <12
318 opp-microvolt = <10375
319 };
320 opp-1300000000 {
321 opp-hz = /bits/ 64 <13
322 opp-microvolt = <10625
323 };
324 opp-1400000000 {
325 opp-hz = /bits/ 64 <14
326 opp-microvolt = <10875
327 };
328 opp-1500000000 {
329 opp-hz = /bits/ 64 <15
330 opp-microvolt = <11250
331 };
332 opp-1600000000 {
333 opp-hz = /bits/ 64 <16
334 opp-microvolt = <11375
335 };
336 opp-1700000000 {
337 opp-hz = /bits/ 64 <17
338 opp-microvolt = <11750
339 };
340 opp-1800000000 {
341 opp-hz = /bits/ 64 <18
342 opp-microvolt = <12125
343 };
344 opp-1900000000 {
345 opp-hz = /bits/ 64 <19
346 opp-microvolt = <12625
347 };
348 };
349
350 psci {
351 compatible = "arm,psci";
352 method = "smc";
353 cpu_off = <0x84000002>;
354 cpu_on = <0xc4000003>;
355 };
356
357 soc: soc@0 {
358 compatible = "simple-bus";
359 #address-cells = <1>;
360 #size-cells = <1>;
361 ranges = <0x0 0x0 0x0 0x180000
362
363 chipid@10000000 {
364 compatible = "samsung,
365 "samsung,
366 reg = <0x10000000 0x10
367 };
368
369 cmu_top: clock-controller@1003
370 compatible = "samsung,
371 reg = <0x10030000 0x10
372 #clock-cells = <1>;
373
374 clock-names = "oscclk"
375 "sclk_mphy_pll
376 "sclk_mfc_pll"
377 "sclk_bus_pll"
378 clocks = <&xxti>,
379 <&cmu_cpif CLK
380 <&cmu_mif CLK_
381 <&cmu_mif CLK_
382 };
383
384 cmu_cpif: clock-controller@10f
385 compatible = "samsung,
386 reg = <0x10fc0000 0x10
387 #clock-cells = <1>;
388
389 clock-names = "oscclk"
390 clocks = <&xxti>;
391 };
392
393 cmu_mif: clock-controller@105b
394 compatible = "samsung,
395 reg = <0x105b0000 0x20
396 #clock-cells = <1>;
397
398 clock-names = "oscclk"
399 "sclk_mphy_pll
400 clocks = <&xxti>,
401 <&cmu_cpif CLK
402 };
403
404 cmu_peric: clock-controller@14
405 compatible = "samsung,
406 reg = <0x14c80000 0x10
407 #clock-cells = <1>;
408 };
409
410 cmu_peris: clock-controller@10
411 compatible = "samsung,
412 reg = <0x10040000 0x10
413 #clock-cells = <1>;
414 };
415
416 cmu_fsys: clock-controller@156
417 compatible = "samsung,
418 reg = <0x156e0000 0x10
419 #clock-cells = <1>;
420
421 clock-names = "oscclk"
422 "sclk_ufs_mphy
423 "aclk_fsys_200
424 "sclk_pcie_100
425 "sclk_ufsunipr
426 "sclk_mmc2_fsy
427 "sclk_mmc1_fsy
428 "sclk_mmc0_fsy
429 "sclk_usbhost3
430 "sclk_usbdrd30
431 clocks = <&xxti>,
432 <&cmu_cpif CLK
433 <&cmu_top CLK_
434 <&cmu_top CLK_
435 <&cmu_top CLK_
436 <&cmu_top CLK_
437 <&cmu_top CLK_
438 <&cmu_top CLK_
439 <&cmu_top CLK_
440 <&cmu_top CLK_
441 };
442
443 cmu_g2d: clock-controller@1246
444 compatible = "samsung,
445 reg = <0x12460000 0x10
446 #clock-cells = <1>;
447
448 clock-names = "oscclk"
449 "aclk_g2d_266"
450 "aclk_g2d_400"
451 clocks = <&xxti>,
452 <&cmu_top CLK_
453 <&cmu_top CLK_
454 power-domains = <&pd_g
455 };
456
457 cmu_disp: clock-controller@13b
458 compatible = "samsung,
459 reg = <0x13b90000 0x10
460 #clock-cells = <1>;
461
462 clock-names = "oscclk"
463 "sclk_dsim1_di
464 "sclk_dsim0_di
465 "sclk_dsd_disp
466 "sclk_decon_tv
467 "sclk_decon_vc
468 "sclk_decon_ec
469 "sclk_decon_tv
470 "aclk_disp_333
471 clocks = <&xxti>,
472 <&cmu_mif CLK_
473 <&cmu_mif CLK_
474 <&cmu_mif CLK_
475 <&cmu_mif CLK_
476 <&cmu_mif CLK_
477 <&cmu_mif CLK_
478 <&cmu_mif CLK_
479 <&cmu_mif CLK_
480 power-domains = <&pd_d
481 };
482
483 cmu_aud: clock-controller@114c
484 compatible = "samsung,
485 reg = <0x114c0000 0x10
486 #clock-cells = <1>;
487 clock-names = "oscclk"
488 clocks = <&xxti>, <&cm
489 power-domains = <&pd_a
490 };
491
492 cmu_bus0: clock-controller@136
493 compatible = "samsung,
494 reg = <0x13600000 0x10
495 #clock-cells = <1>;
496
497 clock-names = "aclk_bu
498 clocks = <&cmu_top CLK
499 };
500
501 cmu_bus1: clock-controller@148
502 compatible = "samsung,
503 reg = <0x14800000 0x10
504 #clock-cells = <1>;
505
506 clock-names = "aclk_bu
507 clocks = <&cmu_top CLK
508 };
509
510 cmu_bus2: clock-controller@134
511 compatible = "samsung,
512 reg = <0x13400000 0x10
513 #clock-cells = <1>;
514
515 clock-names = "oscclk"
516 clocks = <&xxti>, <&cm
517 };
518
519 cmu_g3d: clock-controller@14aa
520 compatible = "samsung,
521 reg = <0x14aa0000 0x20
522 #clock-cells = <1>;
523
524 clock-names = "oscclk"
525 clocks = <&xxti>, <&cm
526 power-domains = <&pd_g
527 };
528
529 cmu_gscl: clock-controller@13c
530 compatible = "samsung,
531 reg = <0x13cf0000 0x10
532 #clock-cells = <1>;
533
534 clock-names = "oscclk"
535 "aclk_gscl_111
536 "aclk_gscl_333
537 clocks = <&xxti>,
538 <&cmu_top CLK_
539 <&cmu_top CLK_
540 power-domains = <&pd_g
541 };
542
543 cmu_apollo: clock-controller@1
544 compatible = "samsung,
545 reg = <0x11900000 0x20
546 #clock-cells = <1>;
547
548 clock-names = "oscclk"
549 clocks = <&xxti>, <&cm
550 };
551
552 cmu_atlas: clock-controller@11
553 compatible = "samsung,
554 reg = <0x11800000 0x20
555 #clock-cells = <1>;
556
557 clock-names = "oscclk"
558 clocks = <&xxti>, <&cm
559 };
560
561 cmu_mscl: clock-controller@150
562 compatible = "samsung,
563 reg = <0x150d0000 0x10
564 #clock-cells = <1>;
565
566 clock-names = "oscclk"
567 "sclk_jpeg_msc
568 "aclk_mscl_400
569 clocks = <&xxti>,
570 <&cmu_top CLK_
571 <&cmu_top CLK_
572 power-domains = <&pd_m
573 };
574
575 cmu_mfc: clock-controller@1528
576 compatible = "samsung,
577 reg = <0x15280000 0x10
578 #clock-cells = <1>;
579
580 clock-names = "oscclk"
581 clocks = <&xxti>, <&cm
582 power-domains = <&pd_m
583 };
584
585 cmu_hevc: clock-controller@14f
586 compatible = "samsung,
587 reg = <0x14f80000 0x10
588 #clock-cells = <1>;
589
590 clock-names = "oscclk"
591 clocks = <&xxti>, <&cm
592 power-domains = <&pd_h
593 };
594
595 cmu_isp: clock-controller@146d
596 compatible = "samsung,
597 reg = <0x146d0000 0x10
598 #clock-cells = <1>;
599
600 clock-names = "oscclk"
601 "aclk_isp_dis_
602 "aclk_isp_400"
603 clocks = <&xxti>,
604 <&cmu_top CLK_
605 <&cmu_top CLK_
606 power-domains = <&pd_i
607 };
608
609 cmu_cam0: clock-controller@120
610 compatible = "samsung,
611 reg = <0x120d0000 0x10
612 #clock-cells = <1>;
613
614 clock-names = "oscclk"
615 "aclk_cam0_333
616 "aclk_cam0_400
617 "aclk_cam0_552
618 clocks = <&xxti>,
619 <&cmu_top CLK_
620 <&cmu_top CLK_
621 <&cmu_top CLK_
622 power-domains = <&pd_c
623 };
624
625 cmu_cam1: clock-controller@145
626 compatible = "samsung,
627 reg = <0x145d0000 0x10
628 #clock-cells = <1>;
629
630 clock-names = "oscclk"
631 "sclk_isp_uart
632 "sclk_isp_spi1
633 "sclk_isp_spi0
634 "aclk_cam1_333
635 "aclk_cam1_400
636 "aclk_cam1_552
637 clocks = <&xxti>,
638 <&cmu_top CLK_
639 <&cmu_top CLK_
640 <&cmu_top CLK_
641 <&cmu_top CLK_
642 <&cmu_top CLK_
643 <&cmu_top CLK_
644 power-domains = <&pd_c
645 };
646
647 cmu_imem: clock-controller@110
648 compatible = "samsung,
649 reg = <0x11060000 0x10
650 #clock-cells = <1>;
651
652 clock-names = "oscclk"
653 "aclk_imem_sss
654 "aclk_imem_266
655 "aclk_imem_200
656 clocks = <&xxti>,
657 <&cmu_top CLK_
658 <&cmu_top CLK_
659 <&cmu_top CLK_
660 };
661
662 slim_sss: slim-sss@11140000 {
663 compatible = "samsung,
664 reg = <0x11140000 0x10
665 interrupts = <GIC_SPI
666 clock-names = "pclk",
667 clocks = <&cmu_imem CL
668 <&cmu_imem CL
669 };
670
671 pd_gscl: power-domain@105c4000
672 compatible = "samsung,
673 reg = <0x105c4000 0x20
674 #power-domain-cells =
675 label = "GSCL";
676 };
677
678 pd_cam0: power-domain@105c4020
679 compatible = "samsung,
680 reg = <0x105c4020 0x20
681 #power-domain-cells =
682 power-domains = <&pd_c
683 label = "CAM0";
684 };
685
686 pd_mscl: power-domain@105c4040
687 compatible = "samsung,
688 reg = <0x105c4040 0x20
689 #power-domain-cells =
690 label = "MSCL";
691 };
692
693 pd_g3d: power-domain@105c4060
694 compatible = "samsung,
695 reg = <0x105c4060 0x20
696 #power-domain-cells =
697 label = "G3D";
698 };
699
700 pd_disp: power-domain@105c4080
701 compatible = "samsung,
702 reg = <0x105c4080 0x20
703 #power-domain-cells =
704 label = "DISP";
705 };
706
707 pd_cam1: power-domain@105c40a0
708 compatible = "samsung,
709 reg = <0x105c40a0 0x20
710 #power-domain-cells =
711 label = "CAM1";
712 };
713
714 pd_aud: power-domain@105c40c0
715 compatible = "samsung,
716 reg = <0x105c40c0 0x20
717 #power-domain-cells =
718 label = "AUD";
719 };
720
721 pd_g2d: power-domain@105c4120
722 compatible = "samsung,
723 reg = <0x105c4120 0x20
724 #power-domain-cells =
725 label = "G2D";
726 };
727
728 pd_isp: power-domain@105c4140
729 compatible = "samsung,
730 reg = <0x105c4140 0x20
731 #power-domain-cells =
732 power-domains = <&pd_c
733 label = "ISP";
734 };
735
736 pd_mfc: power-domain@105c4180
737 compatible = "samsung,
738 reg = <0x105c4180 0x20
739 #power-domain-cells =
740 label = "MFC";
741 };
742
743 pd_hevc: power-domain@105c41c0
744 compatible = "samsung,
745 reg = <0x105c41c0 0x20
746 #power-domain-cells =
747 label = "HEVC";
748 };
749
750 tmu_atlas0: tmu@10060000 {
751 compatible = "samsung,
752 reg = <0x10060000 0x20
753 interrupts = <GIC_SPI
754 clocks = <&cmu_peris C
755 <&cmu_peris CL
756 clock-names = "tmu_apb
757 #thermal-sensor-cells
758 status = "disabled";
759 };
760
761 tmu_atlas1: tmu@10068000 {
762 compatible = "samsung,
763 reg = <0x10068000 0x20
764 interrupts = <GIC_SPI
765 clocks = <&cmu_peris C
766 <&cmu_peris CL
767 clock-names = "tmu_apb
768 #thermal-sensor-cells
769 status = "disabled";
770 };
771
772 tmu_g3d: tmu@10070000 {
773 compatible = "samsung,
774 reg = <0x10070000 0x20
775 interrupts = <GIC_SPI
776 clocks = <&cmu_peris C
777 <&cmu_peris CL
778 clock-names = "tmu_apb
779 #thermal-sensor-cells
780 status = "disabled";
781 };
782
783 tmu_apollo: tmu@10078000 {
784 compatible = "samsung,
785 reg = <0x10078000 0x20
786 interrupts = <GIC_SPI
787 clocks = <&cmu_peris C
788 <&cmu_peris CL
789 clock-names = "tmu_apb
790 #thermal-sensor-cells
791 status = "disabled";
792 };
793
794 tmu_isp: tmu@1007c000 {
795 compatible = "samsung,
796 reg = <0x1007c000 0x20
797 interrupts = <GIC_SPI
798 clocks = <&cmu_peris C
799 <&cmu_peris CL
800 clock-names = "tmu_apb
801 #thermal-sensor-cells
802 status = "disabled";
803 };
804
805 timer@101c0000 {
806 compatible = "samsung,
807 "samsung,
808 reg = <0x101c0000 0x80
809 interrupts = <GIC_SPI
810 <GIC_SPI 103 I
811 <GIC_SPI 104 I
812 <GIC_SPI 105 I
813 <GIC_SPI 106 I
814 <GIC_SPI 107 I
815 <GIC_SPI 108 I
816 <GIC_SPI 109 I
817 <GIC_SPI 110 I
818 <GIC_SPI 111 I
819 <GIC_SPI 112 I
820 <GIC_SPI 113 I
821 clocks = <&xxti>, <&cm
822 clock-names = "fin_pll
823 };
824
825 ppmu_d0_cpu: ppmu@10480000 {
826 compatible = "samsung,
827 reg = <0x10480000 0x20
828 status = "disabled";
829 };
830
831 ppmu_d0_general: ppmu@10490000
832 compatible = "samsung,
833 reg = <0x10490000 0x20
834 status = "disabled";
835 };
836
837 ppmu_d1_cpu: ppmu@104b0000 {
838 compatible = "samsung,
839 reg = <0x104b0000 0x20
840 status = "disabled";
841 };
842
843 ppmu_d1_general: ppmu@104c0000
844 compatible = "samsung,
845 reg = <0x104c0000 0x20
846 status = "disabled";
847 };
848
849 pinctrl_alive: pinctrl@1058000
850 compatible = "samsung,
851 reg = <0x10580000 0x1a
852
853 wakeup-interrupt-contr
854 compatible = "
855 "
856 interrupts = <
857 };
858 };
859
860 pinctrl_aud: pinctrl@114b0000
861 compatible = "samsung,
862 reg = <0x114b0000 0x10
863 interrupts = <GIC_SPI
864 power-domains = <&pd_a
865 };
866
867 pinctrl_cpif: pinctrl@10fe0000
868 compatible = "samsung,
869 reg = <0x10fe0000 0x10
870 interrupts = <GIC_SPI
871 };
872
873 pinctrl_ese: pinctrl@14ca0000
874 compatible = "samsung,
875 reg = <0x14ca0000 0x10
876 interrupts = <GIC_SPI
877 };
878
879 pinctrl_finger: pinctrl@14cb00
880 compatible = "samsung,
881 reg = <0x14cb0000 0x10
882 interrupts = <GIC_SPI
883 };
884
885 pinctrl_fsys: pinctrl@15690000
886 compatible = "samsung,
887 reg = <0x15690000 0x10
888 interrupts = <GIC_SPI
889 };
890
891 pinctrl_imem: pinctrl@11090000
892 compatible = "samsung,
893 reg = <0x11090000 0x10
894 interrupts = <GIC_SPI
895 };
896
897 pinctrl_nfc: pinctrl@14cd0000
898 compatible = "samsung,
899 reg = <0x14cd0000 0x10
900 interrupts = <GIC_SPI
901 };
902
903 pinctrl_peric: pinctrl@14cc000
904 compatible = "samsung,
905 reg = <0x14cc0000 0x11
906 interrupts = <GIC_SPI
907 };
908
909 pinctrl_touch: pinctrl@14ce000
910 compatible = "samsung,
911 reg = <0x14ce0000 0x11
912 interrupts = <GIC_SPI
913 };
914
915 pmu_system_controller: system-
916 compatible = "samsung,
917 reg = <0x105c0000 0x50
918 #clock-cells = <1>;
919 clock-names = "clkout1
920 clocks = <&xxti>;
921
922 mipi_phy: mipi-phy {
923 compatible = "
924 #phy-cells = <
925 samsung,cam0-s
926 samsung,cam1-s
927 samsung,disp-s
928 };
929
930 reboot: syscon-reboot
931 compatible = "
932 regmap = <&pmu
933 offset = <0x40
934 mask = <0x1>;
935 };
936 };
937
938 gic: interrupt-controller@1100
939 compatible = "arm,gic-
940 #interrupt-cells = <3>
941 interrupt-controller;
942 reg = <0x11001000 0x10
943 <0x11002000 0x
944 <0x11004000 0x
945 <0x11006000 0x
946 interrupts = <GIC_PPI
947 };
948
949 decon: decon@13800000 {
950 compatible = "samsung,
951 reg = <0x13800000 0x21
952 clocks = <&cmu_disp CL
953 <&cmu_disp CLK
954 <&cmu_disp CLK
955 <&cmu_disp CLK
956 <&cmu_disp CLK
957 <&cmu_disp CLK
958 <&cmu_disp CLK
959 <&cmu_disp CLK
960 <&cmu_disp CLK
961 <&cmu_disp CLK
962 <&cmu_disp CLK
963 clock-names = "pclk",
964 "aclk_xiu_deco
965 "aclk_smmu_dec
966 "pclk_smmu_dec
967 "sclk_decon_ec
968 power-domains = <&pd_d
969 interrupt-names = "fif
970 interrupts = <GIC_SPI
971 <GIC_SPI
972 <GIC_SPI
973 samsung,disp-sysreg =
974 status = "disabled";
975 iommus = <&sysmmu_deco
976 iommu-names = "m0", "m
977
978 ports {
979 #address-cells
980 #size-cells =
981
982 port@0 {
983 reg =
984 decon_
985
986
987 };
988 };
989 };
990 };
991
992 decon_tv: decon@13880000 {
993 compatible = "samsung,
994 reg = <0x13880000 0x20
995 clocks = <&cmu_disp CL
996 <&cmu_disp CL
997 <&cmu_disp CL
998 <&cmu_disp CL
999 <&cmu_disp CL
1000 <&cmu_disp C
1001 <&cmu_disp C
1002 <&cmu_disp C
1003 <&cmu_disp C
1004 <&cmu_disp C
1005 <&cmu_disp C
1006 clock-names = "pclk",
1007 "aclk_x
1008 "aclk_s
1009 "pclk_s
1010 "sclk_d
1011 samsung,disp-sysreg =
1012 power-domains = <&pd_
1013 interrupt-names = "fi
1014 interrupts = <GIC_SPI
1015 <GIC_SPI
1016 <GIC_SPI
1017 status = "disabled";
1018 iommus = <&sysmmu_tv0
1019 iommu-names = "m0", "
1020 };
1021
1022 dsi: dsi@13900000 {
1023 compatible = "samsung
1024 reg = <0x13900000 0xc
1025 interrupts = <GIC_SPI
1026 phys = <&mipi_phy 1>;
1027 phy-names = "dsim";
1028 clocks = <&cmu_disp C
1029 <&cmu_disp CL
1030 <&cmu_disp CL
1031 <&cmu_disp CL
1032 <&cmu_disp CL
1033 clock-names = "bus_cl
1034 "phyc
1035 "phyc
1036 "sclk
1037 "sclk
1038 power-domains = <&pd_
1039 status = "disabled";
1040 #address-cells = <1>;
1041 #size-cells = <0>;
1042
1043 ports {
1044 #address-cell
1045 #size-cells =
1046
1047 port@0 {
1048 reg =
1049 dsi_t
1050
1051 };
1052 };
1053 };
1054 };
1055
1056 mic: mic@13930000 {
1057 compatible = "samsung
1058 reg = <0x13930000 0x4
1059 clocks = <&cmu_disp C
1060 <&cmu_disp CL
1061 clock-names = "pclk_m
1062 power-domains = <&pd_
1063 samsung,disp-syscon =
1064 status = "disabled";
1065
1066 ports {
1067 #address-cell
1068 #size-cells =
1069
1070 port@0 {
1071 reg =
1072 mic_t
1073
1074
1075 };
1076 };
1077
1078 port@1 {
1079 reg =
1080 mic_t
1081
1082 };
1083 };
1084 };
1085 };
1086
1087 hdmi: hdmi@13970000 {
1088 compatible = "samsung
1089 reg = <0x13970000 0x7
1090 interrupts = <GIC_SPI
1091 clocks = <&cmu_disp C
1092 <&cmu_disp CL
1093 <&cmu_disp CL
1094 <&cmu_disp CL
1095 <&cmu_disp CL
1096 <&cmu_disp CL
1097 <&cmu_disp CL
1098 <&cmu_disp CL
1099 <&xxti>, <&cm
1100 clock-names = "hdmi_p
1101 "i_tmds_clk",
1102 "tmds_clko",
1103 "pixel_clko",
1104 "oscclk", "i_
1105 phy = <&hdmiphy>;
1106 ddc = <&hsi2c_11>;
1107 samsung,syscon-phandl
1108 samsung,sysreg-phandl
1109 #sound-dai-cells = <0
1110 status = "disabled";
1111 };
1112
1113 hdmiphy: hdmiphy@13af0000 {
1114 reg = <0x13af0000 0x8
1115 };
1116
1117 syscon_disp: syscon@13b80000
1118 compatible = "samsung
1119 "samsung
1120 reg = <0x13b80000 0x1
1121 };
1122
1123 syscon_cam0: syscon@120f0000
1124 compatible = "samsung
1125 "samsung
1126 reg = <0x120f0000 0x1
1127 };
1128
1129 syscon_cam1: syscon@145f0000
1130 compatible = "samsung
1131 "samsung
1132 reg = <0x145f0000 0x1
1133 };
1134
1135 syscon_fsys: syscon@156f0000
1136 compatible = "samsung
1137 "samsung
1138 reg = <0x156f0000 0x1
1139 };
1140
1141 gsc_0: video-scaler@13c00000
1142 compatible = "samsung
1143 reg = <0x13c00000 0x1
1144 interrupts = <GIC_SPI
1145 clock-names = "pclk",
1146 "aclk_g
1147 clocks = <&cmu_gscl C
1148 <&cmu_gscl C
1149 <&cmu_gscl C
1150 <&cmu_gscl C
1151 <&cmu_gscl C
1152 iommus = <&sysmmu_gsc
1153 power-domains = <&pd_
1154 };
1155
1156 gsc_1: video-scaler@13c10000
1157 compatible = "samsung
1158 reg = <0x13c10000 0x1
1159 interrupts = <GIC_SPI
1160 clock-names = "pclk",
1161 "aclk_g
1162 clocks = <&cmu_gscl C
1163 <&cmu_gscl C
1164 <&cmu_gscl C
1165 <&cmu_gscl C
1166 <&cmu_gscl C
1167 iommus = <&sysmmu_gsc
1168 power-domains = <&pd_
1169 };
1170
1171 gsc_2: video-scaler@13c20000
1172 compatible = "samsung
1173 reg = <0x13c20000 0x1
1174 interrupts = <GIC_SPI
1175 clock-names = "pclk",
1176 "aclk_g
1177 clocks = <&cmu_gscl C
1178 <&cmu_gscl C
1179 <&cmu_gscl C
1180 <&cmu_gscl C
1181 <&cmu_gscl C
1182 iommus = <&sysmmu_gsc
1183 power-domains = <&pd_
1184 };
1185
1186 gpu: gpu@14ac0000 {
1187 compatible = "samsung
1188 reg = <0x14ac0000 0x5
1189 interrupts = <GIC_SPI
1190 <GIC_SPI
1191 <GIC_SPI
1192 interrupt-names = "jo
1193 clocks = <&cmu_g3d CL
1194 clock-names = "core";
1195 power-domains = <&pd_
1196 operating-points-v2 =
1197 status = "disabled";
1198
1199 gpu_opp_table: opp-ta
1200 compatible =
1201
1202 opp-160000000
1203 opp-h
1204 opp-m
1205 };
1206 opp-267000000
1207 opp-h
1208 opp-m
1209 };
1210 opp-350000000
1211 opp-h
1212 opp-m
1213 };
1214 opp-420000000
1215 opp-h
1216 opp-m
1217 };
1218 opp-500000000
1219 opp-h
1220 opp-m
1221 };
1222 opp-550000000
1223 opp-h
1224 opp-m
1225 };
1226 opp-600000000
1227 opp-h
1228 opp-m
1229 };
1230 opp-700000000
1231 opp-h
1232 opp-m
1233 };
1234 };
1235 };
1236
1237 scaler_0: scaler@15000000 {
1238 compatible = "samsung
1239 reg = <0x15000000 0x1
1240 interrupts = <0 402 I
1241 clock-names = "pclk",
1242 clocks = <&cmu_mscl C
1243 <&cmu_mscl C
1244 <&cmu_mscl C
1245 iommus = <&sysmmu_sca
1246 power-domains = <&pd_
1247 };
1248
1249 scaler_1: scaler@15010000 {
1250 compatible = "samsung
1251 reg = <0x15010000 0x1
1252 interrupts = <0 403 I
1253 clock-names = "pclk",
1254 clocks = <&cmu_mscl C
1255 <&cmu_mscl C
1256 <&cmu_mscl C
1257 iommus = <&sysmmu_sca
1258 power-domains = <&pd_
1259 };
1260
1261 jpeg: codec@15020000 {
1262 compatible = "samsung
1263 reg = <0x15020000 0x1
1264 interrupts = <GIC_SPI
1265 clock-names = "pclk",
1266 clocks = <&cmu_mscl C
1267 <&cmu_mscl C
1268 <&cmu_mscl C
1269 <&cmu_mscl C
1270 iommus = <&sysmmu_jpe
1271 power-domains = <&pd_
1272 };
1273
1274 mfc: codec@152e0000 {
1275 compatible = "samsung
1276 reg = <0x152e0000 0x1
1277 interrupts = <GIC_SPI
1278 clock-names = "pclk",
1279 clocks = <&cmu_mfc CL
1280 <&cmu_mfc CL
1281 <&cmu_mfc CL
1282 iommus = <&sysmmu_mfc
1283 iommu-names = "left",
1284 power-domains = <&pd_
1285 };
1286
1287 sysmmu_decon0x: sysmmu@13a000
1288 compatible = "samsung
1289 reg = <0x13a00000 0x1
1290 interrupts = <GIC_SPI
1291 clock-names = "aclk",
1292 clocks = <&cmu_disp C
1293 <&cmu_disp CL
1294 power-domains = <&pd_
1295 #iommu-cells = <0>;
1296 };
1297
1298 sysmmu_decon1x: sysmmu@13a100
1299 compatible = "samsung
1300 reg = <0x13a10000 0x1
1301 interrupts = <GIC_SPI
1302 clock-names = "aclk",
1303 clocks = <&cmu_disp C
1304 <&cmu_disp CL
1305 #iommu-cells = <0>;
1306 power-domains = <&pd_
1307 };
1308
1309 sysmmu_tv0x: sysmmu@13a20000
1310 compatible = "samsung
1311 reg = <0x13a20000 0x1
1312 interrupts = <GIC_SPI
1313 clock-names = "aclk",
1314 clocks = <&cmu_disp C
1315 <&cmu_disp CL
1316 #iommu-cells = <0>;
1317 power-domains = <&pd_
1318 };
1319
1320 sysmmu_tv1x: sysmmu@13a30000
1321 compatible = "samsung
1322 reg = <0x13a30000 0x1
1323 interrupts = <GIC_SPI
1324 clock-names = "aclk",
1325 clocks = <&cmu_disp C
1326 <&cmu_disp CL
1327 #iommu-cells = <0>;
1328 power-domains = <&pd_
1329 };
1330
1331 sysmmu_gscl0: sysmmu@13c80000
1332 compatible = "samsung
1333 reg = <0x13c80000 0x1
1334 interrupts = <GIC_SPI
1335 clock-names = "aclk",
1336 clocks = <&cmu_gscl C
1337 <&cmu_gscl C
1338 #iommu-cells = <0>;
1339 power-domains = <&pd_
1340 };
1341
1342 sysmmu_gscl1: sysmmu@13c90000
1343 compatible = "samsung
1344 reg = <0x13c90000 0x1
1345 interrupts = <GIC_SPI
1346 clock-names = "aclk",
1347 clocks = <&cmu_gscl C
1348 <&cmu_gscl C
1349 #iommu-cells = <0>;
1350 power-domains = <&pd_
1351 };
1352
1353 sysmmu_gscl2: sysmmu@13ca0000
1354 compatible = "samsung
1355 reg = <0x13ca0000 0x1
1356 interrupts = <GIC_SPI
1357 clock-names = "aclk",
1358 clocks = <&cmu_gscl C
1359 <&cmu_gscl C
1360 #iommu-cells = <0>;
1361 power-domains = <&pd_
1362 };
1363
1364 sysmmu_scaler_0: sysmmu@15040
1365 compatible = "samsung
1366 reg = <0x15040000 0x1
1367 interrupts = <GIC_SPI
1368 clock-names = "aclk",
1369 clocks = <&cmu_mscl C
1370 <&cmu_mscl CL
1371 #iommu-cells = <0>;
1372 power-domains = <&pd_
1373 };
1374
1375 sysmmu_scaler_1: sysmmu@15050
1376 compatible = "samsung
1377 reg = <0x15050000 0x1
1378 interrupts = <GIC_SPI
1379 clock-names = "aclk",
1380 clocks = <&cmu_mscl C
1381 <&cmu_mscl CL
1382 #iommu-cells = <0>;
1383 power-domains = <&pd_
1384 };
1385
1386 sysmmu_jpeg: sysmmu@15060000
1387 compatible = "samsung
1388 reg = <0x15060000 0x1
1389 interrupts = <GIC_SPI
1390 clock-names = "aclk",
1391 clocks = <&cmu_mscl C
1392 <&cmu_mscl CL
1393 #iommu-cells = <0>;
1394 power-domains = <&pd_
1395 };
1396
1397 sysmmu_mfc_0: sysmmu@15200000
1398 compatible = "samsung
1399 reg = <0x15200000 0x1
1400 interrupts = <GIC_SPI
1401 clock-names = "aclk",
1402 clocks = <&cmu_mfc CL
1403 <&cmu_mfc CLK
1404 #iommu-cells = <0>;
1405 power-domains = <&pd_
1406 };
1407
1408 sysmmu_mfc_1: sysmmu@15210000
1409 compatible = "samsung
1410 reg = <0x15210000 0x1
1411 interrupts = <GIC_SPI
1412 clock-names = "aclk",
1413 clocks = <&cmu_mfc CL
1414 <&cmu_mfc CLK
1415 #iommu-cells = <0>;
1416 power-domains = <&pd_
1417 };
1418
1419 serial_0: serial@14c10000 {
1420 compatible = "samsung
1421 reg = <0x14c10000 0x1
1422 interrupts = <GIC_SPI
1423 clocks = <&cmu_peric
1424 <&cmu_peric C
1425 clock-names = "uart",
1426 pinctrl-names = "defa
1427 pinctrl-0 = <&uart0_b
1428 status = "disabled";
1429 };
1430
1431 serial_1: serial@14c20000 {
1432 compatible = "samsung
1433 reg = <0x14c20000 0x1
1434 interrupts = <GIC_SPI
1435 clocks = <&cmu_peric
1436 <&cmu_peric C
1437 clock-names = "uart",
1438 pinctrl-names = "defa
1439 pinctrl-0 = <&uart1_b
1440 status = "disabled";
1441 };
1442
1443 serial_2: serial@14c30000 {
1444 compatible = "samsung
1445 reg = <0x14c30000 0x1
1446 interrupts = <GIC_SPI
1447 clocks = <&cmu_peric
1448 <&cmu_peric C
1449 clock-names = "uart",
1450 pinctrl-names = "defa
1451 pinctrl-0 = <&uart2_b
1452 status = "disabled";
1453 };
1454
1455 spi_0: spi@14d20000 {
1456 compatible = "samsung
1457 reg = <0x14d20000 0x1
1458 interrupts = <GIC_SPI
1459 dmas = <&pdma0 9>, <&
1460 dma-names = "tx", "rx
1461 #address-cells = <1>;
1462 #size-cells = <0>;
1463 clocks = <&cmu_peric
1464 <&cmu_peric C
1465 <&cmu_peric C
1466 clock-names = "spi",
1467 samsung,spi-src-clk =
1468 pinctrl-names = "defa
1469 pinctrl-0 = <&spi0_bu
1470 num-cs = <1>;
1471 fifo-depth = <256>;
1472 status = "disabled";
1473 };
1474
1475 spi_1: spi@14d30000 {
1476 compatible = "samsung
1477 reg = <0x14d30000 0x1
1478 interrupts = <GIC_SPI
1479 dmas = <&pdma0 11>, <
1480 dma-names = "tx", "rx
1481 #address-cells = <1>;
1482 #size-cells = <0>;
1483 clocks = <&cmu_peric
1484 <&cmu_peric C
1485 <&cmu_peric C
1486 clock-names = "spi",
1487 samsung,spi-src-clk =
1488 pinctrl-names = "defa
1489 pinctrl-0 = <&spi1_bu
1490 num-cs = <1>;
1491 fifo-depth = <64>;
1492 status = "disabled";
1493 };
1494
1495 spi_2: spi@14d40000 {
1496 compatible = "samsung
1497 reg = <0x14d40000 0x1
1498 interrupts = <GIC_SPI
1499 dmas = <&pdma0 13>, <
1500 dma-names = "tx", "rx
1501 #address-cells = <1>;
1502 #size-cells = <0>;
1503 clocks = <&cmu_peric
1504 <&cmu_peric C
1505 <&cmu_peric C
1506 clock-names = "spi",
1507 samsung,spi-src-clk =
1508 pinctrl-names = "defa
1509 pinctrl-0 = <&spi2_bu
1510 num-cs = <1>;
1511 fifo-depth = <64>;
1512 status = "disabled";
1513 };
1514
1515 spi_3: spi@14d50000 {
1516 compatible = "samsung
1517 reg = <0x14d50000 0x1
1518 interrupts = <GIC_SPI
1519 dmas = <&pdma0 23>, <
1520 dma-names = "tx", "rx
1521 #address-cells = <1>;
1522 #size-cells = <0>;
1523 clocks = <&cmu_peric
1524 <&cmu_peric C
1525 <&cmu_peric C
1526 clock-names = "spi",
1527 samsung,spi-src-clk =
1528 pinctrl-names = "defa
1529 pinctrl-0 = <&spi3_bu
1530 num-cs = <1>;
1531 fifo-depth = <64>;
1532 status = "disabled";
1533 };
1534
1535 spi_4: spi@14d00000 {
1536 compatible = "samsung
1537 reg = <0x14d00000 0x1
1538 interrupts = <GIC_SPI
1539 dmas = <&pdma0 25>, <
1540 dma-names = "tx", "rx
1541 #address-cells = <1>;
1542 #size-cells = <0>;
1543 clocks = <&cmu_peric
1544 <&cmu_peric C
1545 <&cmu_peric C
1546 clock-names = "spi",
1547 samsung,spi-src-clk =
1548 pinctrl-names = "defa
1549 pinctrl-0 = <&spi4_bu
1550 num-cs = <1>;
1551 fifo-depth = <64>;
1552 status = "disabled";
1553 };
1554
1555 adc: adc@14d10000 {
1556 compatible = "samsung
1557 reg = <0x14d10000 0x1
1558 interrupts = <GIC_SPI
1559 clock-names = "adc";
1560 clocks = <&cmu_peric
1561 #io-channel-cells = <
1562 status = "disabled";
1563 };
1564
1565 i2s1: i2s@14d60000 {
1566 compatible = "samsung
1567 reg = <0x14d60000 0x1
1568 dmas = <&pdma0 31>, <
1569 dma-names = "tx", "rx
1570 interrupts = <GIC_SPI
1571 clocks = <&cmu_peric
1572 <&cmu_peric
1573 <&cmu_peric
1574 clock-names = "iis",
1575 #clock-cells = <1>;
1576 #sound-dai-cells = <1
1577 status = "disabled";
1578 };
1579
1580 pwm: pwm@14dd0000 {
1581 compatible = "samsung
1582 reg = <0x14dd0000 0x1
1583 interrupts = <GIC_SPI
1584 <GIC_SPI
1585 <GIC_SPI
1586 <GIC_SPI
1587 <GIC_SPI
1588 samsung,pwm-outputs =
1589 clocks = <&cmu_peric
1590 clock-names = "timers
1591 #pwm-cells = <3>;
1592 status = "disabled";
1593 };
1594
1595 hsi2c_0: i2c@14e40000 {
1596 compatible = "samsung
1597 "samsung
1598 reg = <0x14e40000 0x1
1599 interrupts = <GIC_SPI
1600 #address-cells = <1>;
1601 #size-cells = <0>;
1602 pinctrl-names = "defa
1603 pinctrl-0 = <&hs_i2c0
1604 clocks = <&cmu_peric
1605 clock-names = "hsi2c"
1606 status = "disabled";
1607 };
1608
1609 hsi2c_1: i2c@14e50000 {
1610 compatible = "samsung
1611 "samsung
1612 reg = <0x14e50000 0x1
1613 interrupts = <GIC_SPI
1614 #address-cells = <1>;
1615 #size-cells = <0>;
1616 pinctrl-names = "defa
1617 pinctrl-0 = <&hs_i2c1
1618 clocks = <&cmu_peric
1619 clock-names = "hsi2c"
1620 status = "disabled";
1621 };
1622
1623 hsi2c_2: i2c@14e60000 {
1624 compatible = "samsung
1625 "samsung
1626 reg = <0x14e60000 0x1
1627 interrupts = <GIC_SPI
1628 #address-cells = <1>;
1629 #size-cells = <0>;
1630 pinctrl-names = "defa
1631 pinctrl-0 = <&hs_i2c2
1632 clocks = <&cmu_peric
1633 clock-names = "hsi2c"
1634 status = "disabled";
1635 };
1636
1637 hsi2c_3: i2c@14e70000 {
1638 compatible = "samsung
1639 "samsung
1640 reg = <0x14e70000 0x1
1641 interrupts = <GIC_SPI
1642 #address-cells = <1>;
1643 #size-cells = <0>;
1644 pinctrl-names = "defa
1645 pinctrl-0 = <&hs_i2c3
1646 clocks = <&cmu_peric
1647 clock-names = "hsi2c"
1648 status = "disabled";
1649 };
1650
1651 hsi2c_4: i2c@14ec0000 {
1652 compatible = "samsung
1653 "samsung
1654 reg = <0x14ec0000 0x1
1655 interrupts = <GIC_SPI
1656 #address-cells = <1>;
1657 #size-cells = <0>;
1658 pinctrl-names = "defa
1659 pinctrl-0 = <&hs_i2c4
1660 clocks = <&cmu_peric
1661 clock-names = "hsi2c"
1662 status = "disabled";
1663 };
1664
1665 hsi2c_5: i2c@14ed0000 {
1666 compatible = "samsung
1667 "samsung
1668 reg = <0x14ed0000 0x1
1669 interrupts = <GIC_SPI
1670 #address-cells = <1>;
1671 #size-cells = <0>;
1672 pinctrl-names = "defa
1673 pinctrl-0 = <&hs_i2c5
1674 clocks = <&cmu_peric
1675 clock-names = "hsi2c"
1676 status = "disabled";
1677 };
1678
1679 hsi2c_6: i2c@14ee0000 {
1680 compatible = "samsung
1681 "samsung
1682 reg = <0x14ee0000 0x1
1683 interrupts = <GIC_SPI
1684 #address-cells = <1>;
1685 #size-cells = <0>;
1686 pinctrl-names = "defa
1687 pinctrl-0 = <&hs_i2c6
1688 clocks = <&cmu_peric
1689 clock-names = "hsi2c"
1690 status = "disabled";
1691 };
1692
1693 hsi2c_7: i2c@14ef0000 {
1694 compatible = "samsung
1695 "samsung
1696 reg = <0x14ef0000 0x1
1697 interrupts = <GIC_SPI
1698 #address-cells = <1>;
1699 #size-cells = <0>;
1700 pinctrl-names = "defa
1701 pinctrl-0 = <&hs_i2c7
1702 clocks = <&cmu_peric
1703 clock-names = "hsi2c"
1704 status = "disabled";
1705 };
1706
1707 hsi2c_8: i2c@14d90000 {
1708 compatible = "samsung
1709 "samsung
1710 reg = <0x14d90000 0x1
1711 interrupts = <GIC_SPI
1712 #address-cells = <1>;
1713 #size-cells = <0>;
1714 pinctrl-names = "defa
1715 pinctrl-0 = <&hs_i2c8
1716 clocks = <&cmu_peric
1717 clock-names = "hsi2c"
1718 status = "disabled";
1719 };
1720
1721 hsi2c_9: i2c@14da0000 {
1722 compatible = "samsung
1723 "samsung
1724 reg = <0x14da0000 0x1
1725 interrupts = <GIC_SPI
1726 #address-cells = <1>;
1727 #size-cells = <0>;
1728 pinctrl-names = "defa
1729 pinctrl-0 = <&hs_i2c9
1730 clocks = <&cmu_peric
1731 clock-names = "hsi2c"
1732 status = "disabled";
1733 };
1734
1735 hsi2c_10: i2c@14de0000 {
1736 compatible = "samsung
1737 "samsung
1738 reg = <0x14de0000 0x1
1739 interrupts = <GIC_SPI
1740 #address-cells = <1>;
1741 #size-cells = <0>;
1742 pinctrl-names = "defa
1743 pinctrl-0 = <&hs_i2c1
1744 clocks = <&cmu_peric
1745 clock-names = "hsi2c"
1746 status = "disabled";
1747 };
1748
1749 hsi2c_11: i2c@14df0000 {
1750 compatible = "samsung
1751 "samsung
1752 reg = <0x14df0000 0x1
1753 interrupts = <GIC_SPI
1754 #address-cells = <1>;
1755 #size-cells = <0>;
1756 pinctrl-names = "defa
1757 pinctrl-0 = <&hs_i2c1
1758 clocks = <&cmu_peric
1759 clock-names = "hsi2c"
1760 status = "disabled";
1761 };
1762
1763 usbdrd30: usb@15400000 {
1764 compatible = "samsung
1765 clocks = <&cmu_fsys C
1766 <&cmu_fsys CL
1767 <&cmu_fsys CL
1768 <&cmu_fsys CL
1769 clock-names = "aclk",
1770 #address-cells = <1>;
1771 #size-cells = <1>;
1772 ranges = <0x0 0x15400
1773 status = "disabled";
1774
1775 usbdrd_dwc3: usb@0 {
1776 compatible =
1777 clocks = <&cm
1778 <&cmu
1779 <&cmu
1780 clock-names =
1781 reg = <0x0 0x
1782 interrupts =
1783 phys = <&usbd
1784 phy-names = "
1785 };
1786 };
1787
1788 usbdrd30_phy: phy@15500000 {
1789 compatible = "samsung
1790 reg = <0x15500000 0x1
1791 clocks = <&cmu_fsys C
1792 <&cmu_fsys CL
1793 <&cmu_fsys CL
1794 <&cmu_fsys CL
1795 clock-names = "phy",
1796 "itp"
1797 #phy-cells = <1>;
1798 samsung,pmu-syscon =
1799 status = "disabled";
1800 };
1801
1802 usbhost30_phy: phy@15580000 {
1803 compatible = "samsung
1804 reg = <0x15580000 0x1
1805 clocks = <&cmu_fsys C
1806 <&cmu_fsys CL
1807 <&cmu_fsys CL
1808 <&cmu_fsys CL
1809 clock-names = "phy",
1810 "itp"
1811 #phy-cells = <1>;
1812 samsung,pmu-syscon =
1813 status = "disabled";
1814 };
1815
1816 usbhost30: usb@15a00000 {
1817 compatible = "samsung
1818 clocks = <&cmu_fsys C
1819 <&cmu_fsys CL
1820 <&cmu_fsys CL
1821 <&cmu_fsys CL
1822 clock-names = "aclk",
1823 #address-cells = <1>;
1824 #size-cells = <1>;
1825 ranges = <0x0 0x15a00
1826 status = "disabled";
1827
1828 usbhost_dwc3: usb@0 {
1829 compatible =
1830 clocks = <&cm
1831 <&cmu
1832 <&cmu
1833 clock-names =
1834 reg = <0x0 0x
1835 interrupts =
1836 phys = <&usbh
1837 phy-names = "
1838 };
1839 };
1840
1841 mshc_0: mmc@15540000 {
1842 compatible = "samsung
1843 "samsung
1844 interrupts = <GIC_SPI
1845 #address-cells = <1>;
1846 #size-cells = <0>;
1847 reg = <0x15540000 0x2
1848 clocks = <&cmu_fsys C
1849 <&cmu_fsys CL
1850 clock-names = "biu",
1851 fifo-depth = <0x40>;
1852 status = "disabled";
1853 };
1854
1855 mshc_1: mmc@15550000 {
1856 compatible = "samsung
1857 "samsung
1858 interrupts = <GIC_SPI
1859 #address-cells = <1>;
1860 #size-cells = <0>;
1861 reg = <0x15550000 0x2
1862 clocks = <&cmu_fsys C
1863 <&cmu_fsys CL
1864 clock-names = "biu",
1865 fifo-depth = <0x40>;
1866 status = "disabled";
1867 };
1868
1869 mshc_2: mmc@15560000 {
1870 compatible = "samsung
1871 "samsung
1872 interrupts = <GIC_SPI
1873 #address-cells = <1>;
1874 #size-cells = <0>;
1875 reg = <0x15560000 0x2
1876 clocks = <&cmu_fsys C
1877 <&cmu_fsys CL
1878 clock-names = "biu",
1879 fifo-depth = <0x40>;
1880 status = "disabled";
1881 };
1882
1883 pdma0: dma-controller@1561000
1884 compatible = "arm,pl3
1885 reg = <0x15610000 0x1
1886 interrupts = <GIC_SPI
1887 clocks = <&cmu_fsys C
1888 clock-names = "apb_pc
1889 #dma-cells = <1>;
1890 };
1891
1892 pdma1: dma-controller@1560000
1893 compatible = "arm,pl3
1894 reg = <0x15600000 0x1
1895 interrupts = <GIC_SPI
1896 clocks = <&cmu_fsys C
1897 clock-names = "apb_pc
1898 #dma-cells = <1>;
1899 };
1900
1901 audio-subsystem@11400000 {
1902 compatible = "samsung
1903 reg = <0x11400000 0x1
1904 clocks = <&cmu_aud CL
1905 clock-names = "sfr0_c
1906 power-domains = <&pd_
1907 #address-cells = <1>;
1908 #size-cells = <1>;
1909 ranges;
1910
1911 adma: dma-controller@
1912 compatible =
1913 reg = <0x1142
1914 interrupts =
1915 clocks = <&cm
1916 clock-names =
1917 #dma-cells =
1918 power-domains
1919 };
1920
1921 i2s0: i2s@11440000 {
1922 compatible =
1923
1924 reg = <0x1144
1925 dmas = <&adma
1926 dma-names = "
1927 interrupts =
1928 #address-cell
1929 #size-cells =
1930 clocks = <&cm
1931 <&cmu
1932 <&cmu
1933 clock-names =
1934 #clock-cells
1935 pinctrl-names
1936 pinctrl-0 = <
1937 power-domains
1938 #sound-dai-ce
1939 status = "dis
1940 };
1941
1942 serial_3: serial@1146
1943 compatible =
1944 reg = <0x1146
1945 interrupts =
1946 clocks = <&cm
1947 <&cmu
1948 clock-names =
1949 pinctrl-names
1950 pinctrl-0 = <
1951 power-domains
1952 status = "dis
1953 };
1954 };
1955
1956 pcie_phy: pcie-phy@15680000 {
1957 compatible = "samsung
1958 reg = <0x15680000 0x1
1959 samsung,pmu-syscon =
1960 samsung,fsys-sysreg =
1961 #phy-cells = <0>;
1962 status = "disabled";
1963 };
1964
1965 pcie: pcie@15700000 {
1966 compatible = "samsung
1967 reg = <0x15700000 0x1
1968 <0x0c000000 0x1
1969 reg-names = "dbi", "e
1970 #address-cells = <3>;
1971 #size-cells = <2>;
1972 #interrupt-cells = <1
1973 device_type = "pci";
1974 interrupts = <GIC_SPI
1975 clocks = <&cmu_fsys C
1976 <&cmu_fsys C
1977 clock-names = "pcie",
1978 num-lanes = <1>;
1979 num-viewport = <3>;
1980 bus-range = <0x00 0xf
1981 phys = <&pcie_phy>;
1982 ranges = <0x81000000
1983 <0x82000000
1984 status = "disabled";
1985 };
1986 };
1987
1988 timer: timer {
1989 compatible = "arm,armv8-timer
1990 interrupts = <GIC_PPI 13
1991 (GIC_CPU_MASK
1992 <GIC_PPI 14
1993 (GIC_CPU_MASK
1994 <GIC_PPI 11
1995 (GIC_CPU_MASK
1996 <GIC_PPI 10
1997 (GIC_CPU_MASK
1998 };
1999 };
2000
2001 #include "exynos5433-bus.dtsi"
2002 #include "exynos5433-pinctrl.dtsi"
2003 #include "exynos5433-tmu.dtsi"
Linux® is a registered trademark of Linus Torvalds in the United States and other countries.
TOMOYO® is a registered trademark of NTT DATA CORPORATION.