1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Samsung Exynos7885 SoC device tree source
4 *
5 * Copyright (c) 2021 Samsung Electronics Co.,
6 * Copyright (c) 2021 Dávid Virág
7 */
8
9 #include <dt-bindings/clock/exynos7885.h>
10 #include <dt-bindings/interrupt-controller/arm
11
12 / {
13 compatible = "samsung,exynos7885";
14 #address-cells = <2>;
15 #size-cells = <1>;
16
17 interrupt-parent = <&gic>;
18
19 aliases {
20 pinctrl0 = &pinctrl_alive;
21 pinctrl1 = &pinctrl_dispaud;
22 pinctrl2 = &pinctrl_fsys;
23 pinctrl3 = &pinctrl_top;
24 };
25
26 arm-a53-pmu {
27 compatible = "arm,cortex-a53-p
28 interrupts = <GIC_SPI 96 IRQ_T
29 <GIC_SPI 97 IRQ_T
30 <GIC_SPI 98 IRQ_T
31 <GIC_SPI 99 IRQ_T
32 <GIC_SPI 218 IRQ_
33 <GIC_SPI 219 IRQ_
34 interrupt-affinity = <&cpu0>,
35 <&cpu1>,
36 <&cpu2>,
37 <&cpu3>,
38 <&cpu4>,
39 <&cpu5>;
40 };
41
42 arm-a73-pmu {
43 compatible = "arm,cortex-a73-p
44 interrupts = <GIC_SPI 82 IRQ_T
45 <GIC_SPI 83 IRQ_T
46 interrupt-affinity = <&cpu6>,
47 <&cpu7>;
48 };
49
50 cpus {
51 #address-cells = <1>;
52 #size-cells = <0>;
53
54 cpu-map {
55 cluster0 {
56 core0 {
57 cpu =
58 };
59 core1 {
60 cpu =
61 };
62 core2 {
63 cpu =
64 };
65 core3 {
66 cpu =
67 };
68 core4 {
69 cpu =
70 };
71 core5 {
72 cpu =
73 };
74 };
75
76 cluster1 {
77 core0 {
78 cpu =
79 };
80 core1 {
81 cpu =
82 };
83 };
84 };
85
86 cpu0: cpu@100 {
87 device_type = "cpu";
88 compatible = "arm,cort
89 reg = <0x100>;
90 enable-method = "psci"
91 };
92
93 cpu1: cpu@101 {
94 device_type = "cpu";
95 compatible = "arm,cort
96 reg = <0x101>;
97 enable-method = "psci"
98 };
99
100 cpu2: cpu@102 {
101 device_type = "cpu";
102 compatible = "arm,cort
103 reg = <0x102>;
104 enable-method = "psci"
105 };
106
107 cpu3: cpu@103 {
108 device_type = "cpu";
109 compatible = "arm,cort
110 reg = <0x103>;
111 enable-method = "psci"
112 };
113
114 cpu4: cpu@200 {
115 device_type = "cpu";
116 compatible = "arm,cort
117 reg = <0x200>;
118 enable-method = "psci"
119 };
120
121 cpu5: cpu@201 {
122 device_type = "cpu";
123 compatible = "arm,cort
124 reg = <0x201>;
125 enable-method = "psci"
126 };
127
128 cpu6: cpu@0 {
129 device_type = "cpu";
130 compatible = "arm,cort
131 reg = <0x0>;
132 enable-method = "psci"
133 };
134
135 cpu7: cpu@1 {
136 device_type = "cpu";
137 compatible = "arm,cort
138 reg = <0x1>;
139 enable-method = "psci"
140 };
141 };
142
143 psci {
144 compatible = "arm,psci";
145 method = "smc";
146 cpu_suspend = <0xc4000001>;
147 cpu_off = <0x84000002>;
148 cpu_on = <0xc4000003>;
149 };
150
151 timer {
152 compatible = "arm,armv8-timer"
153 /* Hypervisor Virtual Timer in
154 interrupts = <GIC_PPI 13 (GIC_
155 <GIC_PPI 14 (GIC_
156 <GIC_PPI 11 (GIC_
157 <GIC_PPI 10 (GIC_
158 };
159
160 fixed-rate-clocks {
161 oscclk: osc-clock {
162 compatible = "fixed-cl
163 #clock-cells = <0>;
164 clock-output-names = "
165 };
166 };
167
168 soc: soc@0 {
169 compatible = "simple-bus";
170 #address-cells = <1>;
171 #size-cells = <1>;
172 ranges = <0x0 0x0 0x0 0x200000
173
174 chipid@10000000 {
175 compatible = "samsung,
176 "samsung,
177 reg = <0x10000000 0x24
178 };
179
180 gic: interrupt-controller@1230
181 compatible = "arm,gic-
182 #interrupt-cells = <3>
183 #address-cells = <0>;
184 interrupt-controller;
185 reg = <0x12301000 0x10
186 <0x12302000 0x20
187 <0x12304000 0x20
188 <0x12306000 0x20
189 interrupts = <GIC_PPI
190
191 };
192
193 cmu_peri: clock-controller@100
194 compatible = "samsung,
195 reg = <0x10010000 0x80
196 #clock-cells = <1>;
197
198 clocks = <&oscclk>,
199 <&cmu_top CLK
200 <&cmu_top CLK
201 <&cmu_top CLK
202 <&cmu_top CLK
203 <&cmu_top CLK
204 <&cmu_top CLK
205 <&cmu_top CLK
206 <&cmu_top CLK
207 <&cmu_top CLK
208 clock-names = "oscclk"
209 "dout_pe
210 "dout_pe
211 "dout_pe
212 "dout_pe
213 "dout_pe
214 "dout_pe
215 "dout_pe
216 "dout_pe
217 "dout_pe
218 };
219
220 cmu_core: clock-controller@120
221 compatible = "samsung,
222 reg = <0x12000000 0x80
223 #clock-cells = <1>;
224
225 clocks = <&oscclk>,
226 <&cmu_top CLK
227 <&cmu_top CLK
228 <&cmu_top CLK
229 clock-names = "oscclk"
230 "dout_co
231 "dout_co
232 "dout_co
233 };
234
235 cmu_top: clock-controller@1206
236 compatible = "samsung,
237 reg = <0x12060000 0x80
238 #clock-cells = <1>;
239
240 clocks = <&oscclk>;
241 clock-names = "oscclk"
242 };
243
244 cmu_fsys: clock-controller@134
245 compatible = "samsung,
246 reg = <0x13400000 0x80
247 #clock-cells = <1>;
248
249 clocks = <&oscclk>,
250 <&cmu_top CLK
251 <&cmu_top CLK
252 <&cmu_top CLK
253 <&cmu_top CLK
254 <&cmu_top CLK
255 clock-names = "oscclk"
256 "dout_fs
257 "dout_fs
258 "dout_fs
259 "dout_fs
260 "dout_fs
261 };
262
263 pinctrl_alive: pinctrl@11cb000
264 compatible = "samsung,
265 reg = <0x11cb0000 0x10
266
267 wakeup-interrupt-contr
268 compatible = "
269 "
270 interrupt-pare
271 interrupts = <
272 };
273 };
274
275 pinctrl_fsys: pinctrl@13430000
276 compatible = "samsung,
277 reg = <0x13430000 0x10
278 interrupts = <GIC_SPI
279 };
280
281 pinctrl_top: pinctrl@139b0000
282 compatible = "samsung,
283 reg = <0x139b0000 0x10
284 interrupts = <GIC_SPI
285 };
286
287 pinctrl_dispaud: pinctrl@148f0
288 compatible = "samsung,
289 reg = <0x148f0000 0x10
290 interrupts = <GIC_SPI
291 };
292
293 pmu_system_controller: system-
294 compatible = "samsung,
295 "samsung,
296 reg = <0x11c80000 0x10
297 };
298
299 mmc_0: mmc@13500000 {
300 compatible = "samsung,
301 "samsung,
302 reg = <0x13500000 0x20
303 interrupts = <GIC_SPI
304 #address-cells = <1>;
305 #size-cells = <0>;
306 clocks = <&cmu_fsys CL
307 <&cmu_fsys CL
308 clock-names = "biu", "
309 fifo-depth = <0x40>;
310 status = "disabled";
311 };
312
313 serial_0: serial@13800000 {
314 compatible = "samsung,
315 "samsung,
316 reg = <0x13800000 0x10
317 interrupts = <GIC_SPI
318 pinctrl-names = "defau
319 pinctrl-0 = <&uart0_bu
320 clocks = <&cmu_peri CL
321 <&cmu_peri CL
322 clock-names = "uart",
323 samsung,uart-fifosize
324 status = "disabled";
325 };
326
327 serial_1: serial@13810000 {
328 compatible = "samsung,
329 "samsung,
330 reg = <0x13810000 0x10
331 interrupts = <GIC_SPI
332 pinctrl-names = "defau
333 pinctrl-0 = <&uart1_bu
334 clocks = <&cmu_peri CL
335 <&cmu_peri CL
336 clock-names = "uart",
337 samsung,uart-fifosize
338 status = "disabled";
339 };
340
341 serial_2: serial@13820000 {
342 compatible = "samsung,
343 "samsung,
344 reg = <0x13820000 0x10
345 interrupts = <GIC_SPI
346 pinctrl-names = "defau
347 pinctrl-0 = <&uart2_bu
348 clocks = <&cmu_peri CL
349 <&cmu_peri CL
350 clock-names = "uart",
351 samsung,uart-fifosize
352 status = "disabled";
353 };
354
355 i2c_0: i2c@13830000 {
356 compatible = "samsung,
357 "samsung,
358 reg = <0x13830000 0x10
359 interrupts = <GIC_SPI
360 #address-cells = <1>;
361 #size-cells = <0>;
362 pinctrl-names = "defau
363 pinctrl-0 = <&i2c0_bus
364 clocks = <&cmu_peri CL
365 clock-names = "i2c";
366 status = "disabled";
367 };
368
369 i2c_1: i2c@13840000 {
370 compatible = "samsung,
371 "samsung,
372 reg = <0x13840000 0x10
373 interrupts = <GIC_SPI
374 #address-cells = <1>;
375 #size-cells = <0>;
376 pinctrl-names = "defau
377 pinctrl-0 = <&i2c1_bus
378 clocks = <&cmu_peri CL
379 clock-names = "i2c";
380 status = "disabled";
381 };
382
383 i2c_2: i2c@13850000 {
384 compatible = "samsung,
385 "samsung,
386 reg = <0x13850000 0x10
387 interrupts = <GIC_SPI
388 #address-cells = <1>;
389 #size-cells = <0>;
390 pinctrl-names = "defau
391 pinctrl-0 = <&i2c2_bus
392 clocks = <&cmu_peri CL
393 clock-names = "i2c";
394 status = "disabled";
395 };
396
397 i2c_3: i2c@13860000 {
398 compatible = "samsung,
399 "samsung,
400 reg = <0x13860000 0x10
401 interrupts = <GIC_SPI
402 #address-cells = <1>;
403 #size-cells = <0>;
404 pinctrl-names = "defau
405 pinctrl-0 = <&i2c3_bus
406 clocks = <&cmu_peri CL
407 clock-names = "i2c";
408 status = "disabled";
409 };
410
411 i2c_4: i2c@13870000 {
412 compatible = "samsung,
413 "samsung,
414 reg = <0x13870000 0x10
415 interrupts = <GIC_SPI
416 #address-cells = <1>;
417 #size-cells = <0>;
418 pinctrl-names = "defau
419 pinctrl-0 = <&i2c4_bus
420 clocks = <&cmu_peri CL
421 clock-names = "i2c";
422 status = "disabled";
423 };
424
425 i2c_5: i2c@13880000 {
426 compatible = "samsung,
427 "samsung,
428 reg = <0x13880000 0x10
429 interrupts = <GIC_SPI
430 #address-cells = <1>;
431 #size-cells = <0>;
432 pinctrl-names = "defau
433 pinctrl-0 = <&i2c5_bus
434 clocks = <&cmu_peri CL
435 clock-names = "i2c";
436 status = "disabled";
437 };
438
439 i2c_6: i2c@13890000 {
440 compatible = "samsung,
441 "samsung,
442 reg = <0x13890000 0x10
443 interrupts = <GIC_SPI
444 #address-cells = <1>;
445 #size-cells = <0>;
446 pinctrl-names = "defau
447 pinctrl-0 = <&i2c6_bus
448 clocks = <&cmu_peri CL
449 clock-names = "i2c";
450 status = "disabled";
451 };
452
453 i2c_7: i2c@11cd0000 {
454 compatible = "samsung,
455 "samsung,
456 reg = <0x11cd0000 0x10
457 interrupts = <GIC_SPI
458 #address-cells = <1>;
459 #size-cells = <0>;
460 pinctrl-names = "defau
461 pinctrl-0 = <&i2c7_bus
462 clocks = <&cmu_peri CL
463 clock-names = "i2c";
464 status = "disabled";
465 };
466 };
467 };
468
469 #include "exynos7885-pinctrl.dtsi"
470 #include "arm/samsung/exynos-syscon-restart.dt
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