1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /*
3 * Copyright 2023 Emtop Embedded Solutions
4 */
5
6 /dts-v1/;
7
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/leds/common.h>
10 #include <dt-bindings/usb/pd.h>
11
12 #include "imx8mm.dtsi"
13
14 / {
15 model = "Emtop Embedded Solutions i.MX
16 compatible = "ees,imx8mm-emtop-som", "
17
18 chosen {
19 stdout-path = &uart2;
20 };
21
22 leds {
23 compatible = "gpio-leds";
24 pinctrl-names = "default";
25 pinctrl-0 = <&pinctrl_gpio_led
26
27 led-0 {
28 function = LED_FUNCTIO
29 gpios = <&gpio3 16 GPI
30 linux,default-trigger
31 };
32 };
33 };
34
35 &A53_0 {
36 cpu-supply = <&buck2>;
37 };
38
39 &A53_1 {
40 cpu-supply = <&buck2>;
41 };
42
43 &A53_2 {
44 cpu-supply = <&buck2>;
45 };
46
47 &A53_3 {
48 cpu-supply = <&buck2>;
49 };
50
51 &i2c1 {
52 clock-frequency = <400000>;
53 pinctrl-names = "default";
54 pinctrl-0 = <&pinctrl_i2c1>;
55 status = "okay";
56
57 pmic@25 {
58 compatible = "nxp,pca9450c";
59 reg = <0x25>;
60 pinctrl-names = "default";
61 pinctrl-0 = <&pinctrl_pmic>;
62 interrupt-parent = <&gpio1>;
63 interrupts = <3 IRQ_TYPE_EDGE_
64
65 regulators {
66 buck1: BUCK1 {
67 regulator-name
68 regulator-min-
69 regulator-max-
70 regulator-boot
71 regulator-alwa
72 regulator-ramp
73 };
74
75 buck2: BUCK2 {
76 regulator-name
77 regulator-min-
78 regulator-max-
79 regulator-boot
80 regulator-alwa
81 regulator-ramp
82 };
83
84 buck3: BUCK3 {
85 regulator-name
86 regulator-min-
87 regulator-max-
88 regulator-boot
89 regulator-alwa
90 };
91
92 buck4: BUCK4 {
93 regulator-name
94 regulator-min-
95 regulator-max-
96 regulator-boot
97 regulator-alwa
98 };
99
100 buck5: BUCK5 {
101 regulator-name
102 regulator-min-
103 regulator-max-
104 regulator-boot
105 regulator-alwa
106 };
107
108 buck6: BUCK6 {
109 regulator-name
110 regulator-min-
111 regulator-max-
112 regulator-boot
113 regulator-alwa
114 };
115
116 ldo1: LDO1 {
117 regulator-name
118 regulator-min-
119 regulator-max-
120 regulator-boot
121 regulator-alwa
122 };
123
124 ldo2: LDO2 {
125 regulator-name
126 regulator-min-
127 regulator-max-
128 regulator-boot
129 regulator-alwa
130 };
131
132 ldo3: LDO3 {
133 regulator-name
134 regulator-min-
135 regulator-max-
136 regulator-boot
137 regulator-alwa
138 };
139
140 ldo4: LDO4 {
141 regulator-name
142 regulator-min-
143 regulator-max-
144 regulator-boot
145 regulator-alwa
146 };
147
148 ldo5: LDO5 {
149 regulator-name
150 regulator-min-
151 regulator-max-
152 };
153 };
154 };
155 };
156
157 &uart2 {
158 pinctrl-names = "default";
159 pinctrl-0 = <&pinctrl_uart2>;
160 status = "okay";
161 };
162
163 &usdhc3 {
164 pinctrl-names = "default", "state_100m
165 pinctrl-0 = <&pinctrl_usdhc3>;
166 pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
167 pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
168 bus-width = <8>;
169 non-removable;
170 status = "okay";
171 };
172
173 &wdog1 {
174 pinctrl-names = "default";
175 pinctrl-0 = <&pinctrl_wdog>;
176 fsl,ext-reset-output;
177 status = "okay";
178 };
179
180 &iomuxc {
181 pinctrl_gpio_led: emtop-gpio-led-grp {
182 fsl,pins = <
183 MX8MM_IOMUXC_NAND_READ
184 MX8MM_IOMUXC_SAI3_RXC_
185 >;
186 };
187
188 pinctrl_i2c1: emtop-i2c1-grp {
189 fsl,pins = <
190 MX8MM_IOMUXC_I2C1_SCL_
191 MX8MM_IOMUXC_I2C1_SDA_
192 >;
193 };
194
195 pinctrl_pmic: emtop-pmic-grp {
196 fsl,pins = <
197 MX8MM_IOMUXC_GPIO1_IO0
198 >;
199 };
200
201 pinctrl_uart2: emtop-uart2-grp {
202 fsl,pins = <
203 MX8MM_IOMUXC_UART2_RXD
204 MX8MM_IOMUXC_UART2_TXD
205 >;
206 };
207
208 pinctrl_usdhc3: emtop-usdhc3-grp {
209 fsl,pins = <
210 MX8MM_IOMUXC_NAND_WE_B
211 MX8MM_IOMUXC_NAND_WP_B
212 MX8MM_IOMUXC_NAND_DATA
213 MX8MM_IOMUXC_NAND_DATA
214 MX8MM_IOMUXC_NAND_DATA
215 MX8MM_IOMUXC_NAND_DATA
216 MX8MM_IOMUXC_NAND_RE_B
217 MX8MM_IOMUXC_NAND_CE2_
218 MX8MM_IOMUXC_NAND_CE3_
219 MX8MM_IOMUXC_NAND_CLE_
220 MX8MM_IOMUXC_NAND_CE1_
221 >;
222 };
223
224 pinctrl_usdhc3_100mhz: emtop-usdhc3-10
225 fsl,pins = <
226 MX8MM_IOMUXC_NAND_WE_B
227 MX8MM_IOMUXC_NAND_WP_B
228 MX8MM_IOMUXC_NAND_DATA
229 MX8MM_IOMUXC_NAND_DATA
230 MX8MM_IOMUXC_NAND_DATA
231 MX8MM_IOMUXC_NAND_DATA
232 MX8MM_IOMUXC_NAND_RE_B
233 MX8MM_IOMUXC_NAND_CE2_
234 MX8MM_IOMUXC_NAND_CE3_
235 MX8MM_IOMUXC_NAND_CLE_
236 MX8MM_IOMUXC_NAND_CE1_
237 >;
238 };
239
240 pinctrl_usdhc3_200mhz: emtop-usdhc3-20
241 fsl,pins = <
242 MX8MM_IOMUXC_NAND_WE_B
243 MX8MM_IOMUXC_NAND_WP_B
244 MX8MM_IOMUXC_NAND_DATA
245 MX8MM_IOMUXC_NAND_DATA
246 MX8MM_IOMUXC_NAND_DATA
247 MX8MM_IOMUXC_NAND_DATA
248 MX8MM_IOMUXC_NAND_RE_B
249 MX8MM_IOMUXC_NAND_CE2_
250 MX8MM_IOMUXC_NAND_CE3_
251 MX8MM_IOMUXC_NAND_CLE_
252 MX8MM_IOMUXC_NAND_CE1_
253 >;
254 };
255
256 pinctrl_wdog: emtop-wdog-grp {
257 fsl,pins = <
258 MX8MM_IOMUXC_GPIO1_IO0
259 >;
260 };
261 };
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