1 /* SPDX-License-Identifier: GPL-2.0+ */ 1 2 /* 3 * Copyright 2018-2019 NXP 4 */ 5 6 #ifndef __DTS_IMX8MN_PINFUNC_H 7 #define __DTS_IMX8MN_PINFUNC_H 8 9 /* 10 * The pin function ID is a tuple of 11 * <mux_reg conf_reg input_reg mux_mode input_ 12 */ 13 14 #define MX8MN_IOMUXC_BOOT_MODE2_CCMSRCGPCMIX_B 15 #define MX8MN_IOMUXC_BOOT_MODE2_I2C1_SCL 16 #define MX8MN_IOMUXC_BOOT_MODE3_CCMSRCGPCMIX_B 17 #define MX8MN_IOMUXC_BOOT_MODE3_I2C1_SDA 18 #define MX8MN_IOMUXC_GPIO1_IO00_GPIO1_IO0 19 #define MX8MN_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_E 20 #define MX8MN_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK 21 #define MX8MN_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_E 22 #define MX8MN_IOMUXC_GPIO1_IO01_GPIO1_IO1 23 #define MX8MN_IOMUXC_GPIO1_IO01_PWM1_OUT 24 #define MX8MN_IOMUXC_GPIO1_IO01_ANAMIX_REF_CLK 25 #define MX8MN_IOMUXC_GPIO1_IO01_CCMSRCGPCMIX_E 26 #define MX8MN_IOMUXC_GPIO1_IO02_GPIO1_IO2 27 #define MX8MN_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 28 #define MX8MN_IOMUXC_GPIO1_IO02_WDOG1_WDOG_ANY 29 #define MX8MN_IOMUXC_GPIO1_IO03_GPIO1_IO3 30 #define MX8MN_IOMUXC_GPIO1_IO03_USDHC1_VSELECT 31 #define MX8MN_IOMUXC_GPIO1_IO03_SDMA1_EXT_EVEN 32 #define MX8MN_IOMUXC_GPIO1_IO03_ANAMIX_XTAL_OK 33 #define MX8MN_IOMUXC_GPIO1_IO04_GPIO1_IO4 34 #define MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 35 #define MX8MN_IOMUXC_GPIO1_IO04_SDMA1_EXT_EVEN 36 #define MX8MN_IOMUXC_GPIO1_IO04_ANAMIX_XTAL_OK 37 #define MX8MN_IOMUXC_GPIO1_IO05_GPIO1_IO5 38 #define MX8MN_IOMUXC_GPIO1_IO05_M4_NMI 39 #define MX8MN_IOMUXC_GPIO1_IO05_CCMSRCGPCMIX_P 40 #define MX8MN_IOMUXC_GPIO1_IO05_CCMSRCGPCMIX_I 41 #define MX8MN_IOMUXC_GPIO1_IO06_GPIO1_IO6 42 #define MX8MN_IOMUXC_GPIO1_IO06_ENET1_MDC 43 #define MX8MN_IOMUXC_GPIO1_IO06_USDHC1_CD_B 44 #define MX8MN_IOMUXC_GPIO1_IO06_CCMSRCGPCMIX_E 45 #define MX8MN_IOMUXC_GPIO1_IO07_GPIO1_IO7 46 #define MX8MN_IOMUXC_GPIO1_IO07_ENET1_MDIO 47 #define MX8MN_IOMUXC_GPIO1_IO07_USDHC1_WP 48 #define MX8MN_IOMUXC_GPIO1_IO07_CCMSRCGPCMIX_E 49 #define MX8MN_IOMUXC_GPIO1_IO08_GPIO1_IO8 50 #define MX8MN_IOMUXC_GPIO1_IO08_ENET1_1588_EVE 51 #define MX8MN_IOMUXC_GPIO1_IO08_PWM1_OUT 52 #define MX8MN_IOMUXC_GPIO1_IO08_USDHC2_RESET_B 53 #define MX8MN_IOMUXC_GPIO1_IO08_CCMSRCGPCMIX_W 54 #define MX8MN_IOMUXC_GPIO1_IO09_GPIO1_IO9 55 #define MX8MN_IOMUXC_GPIO1_IO09_ENET1_1588_EVE 56 #define MX8MN_IOMUXC_GPIO1_IO09_PWM2_OUT 57 #define MX8MN_IOMUXC_GPIO1_IO09_USDHC3_RESET_B 58 #define MX8MN_IOMUXC_GPIO1_IO09_SDMA2_EXT_EVEN 59 #define MX8MN_IOMUXC_GPIO1_IO09_CCMSRCGPCMIX_S 60 #define MX8MN_IOMUXC_GPIO1_IO10_GPIO1_IO10 61 #define MX8MN_IOMUXC_GPIO1_IO10_USB1_OTG_ID 62 #define MX8MN_IOMUXC_GPIO1_IO10_PWM3_OUT 63 #define MX8MN_IOMUXC_GPIO1_IO11_GPIO1_IO11 64 #define MX8MN_IOMUXC_GPIO1_IO11_PWM2_OUT 65 #define MX8MN_IOMUXC_GPIO1_IO11_USDHC3_VSELECT 66 #define MX8MN_IOMUXC_GPIO1_IO11_CCMSRCGPCMIX_P 67 #define MX8MN_IOMUXC_GPIO1_IO11_CCMSRCGPCMIX_O 68 #define MX8MN_IOMUXC_GPIO1_IO12_GPIO1_IO12 69 #define MX8MN_IOMUXC_GPIO1_IO12_USB1_OTG_PWR 70 #define MX8MN_IOMUXC_GPIO1_IO12_SDMA2_EXT_EVEN 71 #define MX8MN_IOMUXC_GPIO1_IO12_CCMSRCGPCMIX_O 72 #define MX8MN_IOMUXC_GPIO1_IO13_GPIO1_IO13 73 #define MX8MN_IOMUXC_GPIO1_IO13_USB1_OTG_OC 74 #define MX8MN_IOMUXC_GPIO1_IO13_PWM2_OUT 75 #define MX8MN_IOMUXC_GPIO1_IO13_CCMSRCGPCMIX_O 76 #define MX8MN_IOMUXC_GPIO1_IO14_GPIO1_IO14 77 #define MX8MN_IOMUXC_GPIO1_IO14_USDHC3_CD_B 78 #define MX8MN_IOMUXC_GPIO1_IO14_PWM3_OUT 79 #define MX8MN_IOMUXC_GPIO1_IO14_CCMSRCGPCMIX_C 80 #define MX8MN_IOMUXC_GPIO1_IO15_GPIO1_IO15 81 #define MX8MN_IOMUXC_GPIO1_IO15_USDHC3_WP 82 #define MX8MN_IOMUXC_GPIO1_IO15_PWM4_OUT 83 #define MX8MN_IOMUXC_GPIO1_IO15_CCMSRCGPCMIX_C 84 #define MX8MN_IOMUXC_ENET_MDC_ENET1_MDC 85 #define MX8MN_IOMUXC_ENET_MDC_SAI6_TX_DATA0 86 #define MX8MN_IOMUXC_ENET_MDC_PDM_BIT_STREAM3 87 #define MX8MN_IOMUXC_ENET_MDC_SPDIF1_OUT 88 #define MX8MN_IOMUXC_ENET_MDC_GPIO1_IO16 89 #define MX8MN_IOMUXC_ENET_MDC_USDHC3_STROBE 90 #define MX8MN_IOMUXC_ENET_MDIO_ENET1_MDIO 91 #define MX8MN_IOMUXC_ENET_MDIO_SAI6_TX_SYNC 92 #define MX8MN_IOMUXC_ENET_MDIO_PDM_BIT_STREAM2 93 #define MX8MN_IOMUXC_ENET_MDIO_SPDIF1_IN 94 #define MX8MN_IOMUXC_ENET_MDIO_GPIO1_IO17 95 #define MX8MN_IOMUXC_ENET_MDIO_USDHC3_DATA5 96 #define MX8MN_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 97 #define MX8MN_IOMUXC_ENET_TD3_SAI6_TX_BCLK 98 #define MX8MN_IOMUXC_ENET_TD3_PDM_BIT_STREAM1 99 #define MX8MN_IOMUXC_ENET_TD3_SPDIF1_EXT_CLK 100 #define MX8MN_IOMUXC_ENET_TD3_GPIO1_IO18 101 #define MX8MN_IOMUXC_ENET_TD3_USDHC3_DATA6 102 #define MX8MN_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 103 #define MX8MN_IOMUXC_ENET_TD2_ENET1_TX_CLK 104 #define MX8MN_IOMUXC_ENET_TD2_CCMSRCGPCMIX_ENE 105 #define MX8MN_IOMUXC_ENET_TD2_SAI6_RX_DATA0 106 #define MX8MN_IOMUXC_ENET_TD2_PDM_BIT_STREAM3 107 #define MX8MN_IOMUXC_ENET_TD2_GPIO1_IO19 108 #define MX8MN_IOMUXC_ENET_TD2_USDHC3_DATA7 109 #define MX8MN_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 110 #define MX8MN_IOMUXC_ENET_TD1_SAI6_RX_SYNC 111 #define MX8MN_IOMUXC_ENET_TD1_PDM_BIT_STREAM2 112 #define MX8MN_IOMUXC_ENET_TD1_GPIO1_IO20 113 #define MX8MN_IOMUXC_ENET_TD1_USDHC3_CD_B 114 #define MX8MN_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 115 #define MX8MN_IOMUXC_ENET_TD0_SAI6_RX_BCLK 116 #define MX8MN_IOMUXC_ENET_TD0_PDM_BIT_STREAM1 117 #define MX8MN_IOMUXC_ENET_TD0_GPIO1_IO21 118 #define MX8MN_IOMUXC_ENET_TD0_USDHC3_WP 119 #define MX8MN_IOMUXC_ENET_TX_CTL_ENET1_RGMII_T 120 #define MX8MN_IOMUXC_ENET_TX_CTL_SAI6_MCLK 121 #define MX8MN_IOMUXC_ENET_TX_CTL_GPIO1_IO22 122 #define MX8MN_IOMUXC_ENET_TX_CTL_USDHC3_DATA0 123 #define MX8MN_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 124 #define MX8MN_IOMUXC_ENET_TXC_ENET1_TX_ER 125 #define MX8MN_IOMUXC_ENET_TXC_SAI7_TX_DATA0 126 #define MX8MN_IOMUXC_ENET_TXC_GPIO1_IO23 127 #define MX8MN_IOMUXC_ENET_TXC_USDHC3_DATA1 128 #define MX8MN_IOMUXC_ENET_RX_CTL_ENET1_RGMII_R 129 #define MX8MN_IOMUXC_ENET_RX_CTL_SAI7_TX_SYNC 130 #define MX8MN_IOMUXC_ENET_RX_CTL_PDM_BIT_STREA 131 #define MX8MN_IOMUXC_ENET_RX_CTL_GPIO1_IO24 132 #define MX8MN_IOMUXC_ENET_RX_CTL_USDHC3_DATA2 133 #define MX8MN_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 134 #define MX8MN_IOMUXC_ENET_RXC_ENET1_RX_ER 135 #define MX8MN_IOMUXC_ENET_RXC_SAI7_TX_BCLK 136 #define MX8MN_IOMUXC_ENET_RXC_PDM_BIT_STREAM2 137 #define MX8MN_IOMUXC_ENET_RXC_GPIO1_IO25 138 #define MX8MN_IOMUXC_ENET_RXC_USDHC3_DATA3 139 #define MX8MN_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 140 #define MX8MN_IOMUXC_ENET_RD0_SAI7_RX_DATA0 141 #define MX8MN_IOMUXC_ENET_RD0_PDM_BIT_STREAM1 142 #define MX8MN_IOMUXC_ENET_RD0_GPIO1_IO26 143 #define MX8MN_IOMUXC_ENET_RD0_USDHC3_DATA4 144 #define MX8MN_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 145 #define MX8MN_IOMUXC_ENET_RD1_SAI7_RX_SYNC 146 #define MX8MN_IOMUXC_ENET_RD1_PDM_BIT_STREAM0 147 #define MX8MN_IOMUXC_ENET_RD1_GPIO1_IO27 148 #define MX8MN_IOMUXC_ENET_RD1_USDHC3_RESET_B 149 #define MX8MN_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 150 #define MX8MN_IOMUXC_ENET_RD2_SAI7_RX_BCLK 151 #define MX8MN_IOMUXC_ENET_RD2_PDM_CLK 152 #define MX8MN_IOMUXC_ENET_RD2_GPIO1_IO28 153 #define MX8MN_IOMUXC_ENET_RD2_USDHC3_CLK 154 #define MX8MN_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 155 #define MX8MN_IOMUXC_ENET_RD3_SAI7_MCLK 156 #define MX8MN_IOMUXC_ENET_RD3_SPDIF1_IN 157 #define MX8MN_IOMUXC_ENET_RD3_GPIO1_IO29 158 #define MX8MN_IOMUXC_ENET_RD3_USDHC3_CMD 159 #define MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK 160 #define MX8MN_IOMUXC_SD1_CLK_ENET1_MDC 161 #define MX8MN_IOMUXC_SD1_CLK_UART1_DCE_TX 162 #define MX8MN_IOMUXC_SD1_CLK_UART1_DTE_RX 163 #define MX8MN_IOMUXC_SD1_CLK_GPIO2_IO0 164 #define MX8MN_IOMUXC_SD1_CMD_USDHC1_CMD 165 #define MX8MN_IOMUXC_SD1_CMD_ENET1_MDIO 166 #define MX8MN_IOMUXC_SD1_CMD_UART1_DCE_RX 167 #define MX8MN_IOMUXC_SD1_CMD_UART1_DTE_TX 168 #define MX8MN_IOMUXC_SD1_CMD_GPIO2_IO1 169 #define MX8MN_IOMUXC_SD1_DATA0_USDHC1_DATA0 170 #define MX8MN_IOMUXC_SD1_DATA0_ENET1_RGMII_TD1 171 #define MX8MN_IOMUXC_SD1_DATA0_UART1_DCE_RTS_B 172 #define MX8MN_IOMUXC_SD1_DATA0_UART1_DTE_CTS_B 173 #define MX8MN_IOMUXC_SD1_DATA0_GPIO2_IO2 174 #define MX8MN_IOMUXC_SD1_DATA1_USDHC1_DATA1 175 #define MX8MN_IOMUXC_SD1_DATA1_ENET1_RGMII_TD0 176 #define MX8MN_IOMUXC_SD1_DATA1_UART1_DCE_CTS_B 177 #define MX8MN_IOMUXC_SD1_DATA1_UART1_DTE_RTS_B 178 #define MX8MN_IOMUXC_SD1_DATA1_GPIO2_IO3 179 #define MX8MN_IOMUXC_SD1_DATA2_USDHC1_DATA2 180 #define MX8MN_IOMUXC_SD1_DATA2_ENET1_RGMII_RD0 181 #define MX8MN_IOMUXC_SD1_DATA2_UART2_DCE_TX 182 #define MX8MN_IOMUXC_SD1_DATA2_UART2_DTE_RX 183 #define MX8MN_IOMUXC_SD1_DATA2_GPIO2_IO4 184 #define MX8MN_IOMUXC_SD1_DATA3_USDHC1_DATA3 185 #define MX8MN_IOMUXC_SD1_DATA3_ENET1_RGMII_RD1 186 #define MX8MN_IOMUXC_SD1_DATA3_UART2_DCE_RX 187 #define MX8MN_IOMUXC_SD1_DATA3_UART2_DTE_TX 188 #define MX8MN_IOMUXC_SD1_DATA3_GPIO2_IO5 189 #define MX8MN_IOMUXC_SD1_DATA4_USDHC1_DATA4 190 #define MX8MN_IOMUXC_SD1_DATA4_ENET1_RGMII_TX_ 191 #define MX8MN_IOMUXC_SD1_DATA4_I2C1_SCL 192 #define MX8MN_IOMUXC_SD1_DATA4_UART2_DCE_RTS_B 193 #define MX8MN_IOMUXC_SD1_DATA4_UART2_DTE_CTS_B 194 #define MX8MN_IOMUXC_SD1_DATA4_GPIO2_IO6 195 #define MX8MN_IOMUXC_SD1_DATA5_USDHC1_DATA5 196 #define MX8MN_IOMUXC_SD1_DATA5_ENET1_TX_ER 197 #define MX8MN_IOMUXC_SD1_DATA5_I2C1_SDA 198 #define MX8MN_IOMUXC_SD1_DATA5_UART2_DCE_CTS_B 199 #define MX8MN_IOMUXC_SD1_DATA5_UART2_DTE_RTS_B 200 #define MX8MN_IOMUXC_SD1_DATA5_GPIO2_IO7 201 #define MX8MN_IOMUXC_SD1_DATA6_USDHC1_DATA6 202 #define MX8MN_IOMUXC_SD1_DATA6_ENET1_RGMII_RX_ 203 #define MX8MN_IOMUXC_SD1_DATA6_I2C2_SCL 204 #define MX8MN_IOMUXC_SD1_DATA6_UART3_DCE_TX 205 #define MX8MN_IOMUXC_SD1_DATA6_UART3_DTE_RX 206 #define MX8MN_IOMUXC_SD1_DATA6_GPIO2_IO8 207 #define MX8MN_IOMUXC_SD1_DATA7_USDHC1_DATA7 208 #define MX8MN_IOMUXC_SD1_DATA7_ENET1_RX_ER 209 #define MX8MN_IOMUXC_SD1_DATA7_I2C2_SDA 210 #define MX8MN_IOMUXC_SD1_DATA7_UART3_DCE_RX 211 #define MX8MN_IOMUXC_SD1_DATA7_UART3_DTE_TX 212 #define MX8MN_IOMUXC_SD1_DATA7_GPIO2_IO9 213 #define MX8MN_IOMUXC_SD1_RESET_B_USDHC1_RESET_ 214 #define MX8MN_IOMUXC_SD1_RESET_B_ENET1_TX_CLK 215 #define MX8MN_IOMUXC_SD1_RESET_B_CCMSRCGPCMIX_ 216 #define MX8MN_IOMUXC_SD1_RESET_B_I2C3_SCL 217 #define MX8MN_IOMUXC_SD1_RESET_B_UART3_DCE_RTS 218 #define MX8MN_IOMUXC_SD1_RESET_B_UART3_DTE_CTS 219 #define MX8MN_IOMUXC_SD1_RESET_B_GPIO2_IO10 220 #define MX8MN_IOMUXC_SD1_STROBE_USDHC1_STROBE 221 #define MX8MN_IOMUXC_SD1_STROBE_I2C3_SDA 222 #define MX8MN_IOMUXC_SD1_STROBE_UART3_DCE_CTS_ 223 #define MX8MN_IOMUXC_SD1_STROBE_UART3_DTE_RTS_ 224 #define MX8MN_IOMUXC_SD1_STROBE_GPIO2_IO11 225 #define MX8MN_IOMUXC_SD2_CD_B_USDHC2_CD_B 226 #define MX8MN_IOMUXC_SD2_CD_B_GPIO2_IO12 227 #define MX8MN_IOMUXC_SD2_CD_B_CCMSRCGPCMIX_TES 228 #define MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 229 #define MX8MN_IOMUXC_SD2_CLK_SAI5_RX_SYNC 230 #define MX8MN_IOMUXC_SD2_CLK_ECSPI2_SCLK 231 #define MX8MN_IOMUXC_SD2_CLK_UART4_DCE_RX 232 #define MX8MN_IOMUXC_SD2_CLK_UART4_DTE_TX 233 #define MX8MN_IOMUXC_SD2_CLK_SAI5_MCLK 234 #define MX8MN_IOMUXC_SD2_CLK_GPIO2_IO13 235 #define MX8MN_IOMUXC_SD2_CLK_CCMSRCGPCMIX_OBSE 236 #define MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 237 #define MX8MN_IOMUXC_SD2_CMD_SAI5_RX_BCLK 238 #define MX8MN_IOMUXC_SD2_CMD_ECSPI2_MOSI 239 #define MX8MN_IOMUXC_SD2_CMD_UART4_DCE_TX 240 #define MX8MN_IOMUXC_SD2_CMD_UART4_DTE_RX 241 #define MX8MN_IOMUXC_SD2_CMD_PDM_CLK 242 #define MX8MN_IOMUXC_SD2_CMD_GPIO2_IO14 243 #define MX8MN_IOMUXC_SD2_CMD_CCMSRCGPCMIX_OBSE 244 #define MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 245 #define MX8MN_IOMUXC_SD2_DATA0_SAI5_RX_DATA0 246 #define MX8MN_IOMUXC_SD2_DATA0_I2C4_SDA 247 #define MX8MN_IOMUXC_SD2_DATA0_UART2_DCE_RX 248 #define MX8MN_IOMUXC_SD2_DATA0_UART2_DTE_TX 249 #define MX8MN_IOMUXC_SD2_DATA0_PDM_BIT_STREAM0 250 #define MX8MN_IOMUXC_SD2_DATA0_GPIO2_IO15 251 #define MX8MN_IOMUXC_SD2_DATA0_CCMSRCGPCMIX_OB 252 #define MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 253 #define MX8MN_IOMUXC_SD2_DATA1_SAI5_TX_SYNC 254 #define MX8MN_IOMUXC_SD2_DATA1_I2C4_SCL 255 #define MX8MN_IOMUXC_SD2_DATA1_UART2_DCE_TX 256 #define MX8MN_IOMUXC_SD2_DATA1_UART2_DTE_RX 257 #define MX8MN_IOMUXC_SD2_DATA1_PDM_BIT_STREAM1 258 #define MX8MN_IOMUXC_SD2_DATA1_GPIO2_IO16 259 #define MX8MN_IOMUXC_SD2_DATA1_CCMSRCGPCMIX_WA 260 #define MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 261 #define MX8MN_IOMUXC_SD2_DATA2_SAI5_TX_BCLK 262 #define MX8MN_IOMUXC_SD2_DATA2_ECSPI2_SS0 263 #define MX8MN_IOMUXC_SD2_DATA2_SPDIF1_OUT 264 #define MX8MN_IOMUXC_SD2_DATA2_PDM_BIT_STREAM2 265 #define MX8MN_IOMUXC_SD2_DATA2_GPIO2_IO17 266 #define MX8MN_IOMUXC_SD2_DATA2_CCMSRCGPCMIX_ST 267 #define MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 268 #define MX8MN_IOMUXC_SD2_DATA3_SAI5_TX_DATA0 269 #define MX8MN_IOMUXC_SD2_DATA3_ECSPI2_MISO 270 #define MX8MN_IOMUXC_SD2_DATA3_SPDIF1_IN 271 #define MX8MN_IOMUXC_SD2_DATA3_PDM_BIT_STREAM3 272 #define MX8MN_IOMUXC_SD2_DATA3_GPIO2_IO18 273 #define MX8MN_IOMUXC_SD2_DATA3_CCMSRCGPCMIX_EA 274 #define MX8MN_IOMUXC_SD2_RESET_B_USDHC2_RESET_ 275 #define MX8MN_IOMUXC_SD2_RESET_B_GPIO2_IO19 276 #define MX8MN_IOMUXC_SD2_RESET_B_CCMSRCGPCMIX_ 277 #define MX8MN_IOMUXC_SD2_WP_USDHC2_WP 278 #define MX8MN_IOMUXC_SD2_WP_GPIO2_IO20 279 #define MX8MN_IOMUXC_SD2_WP_CORESIGHT_EVENTI 280 #define MX8MN_IOMUXC_NAND_ALE_RAWNAND_ALE 281 #define MX8MN_IOMUXC_NAND_ALE_QSPI_A_SCLK 282 #define MX8MN_IOMUXC_NAND_ALE_PDM_BIT_STREAM0 283 #define MX8MN_IOMUXC_NAND_ALE_UART3_DCE_RX 284 #define MX8MN_IOMUXC_NAND_ALE_UART3_DTE_TX 285 #define MX8MN_IOMUXC_NAND_ALE_GPIO3_IO0 286 #define MX8MN_IOMUXC_NAND_ALE_CORESIGHT_TRACE_ 287 #define MX8MN_IOMUXC_NAND_CE0_B_RAWNAND_CE0_B 288 #define MX8MN_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 289 #define MX8MN_IOMUXC_NAND_CE0_B_PDM_BIT_STREAM 290 #define MX8MN_IOMUXC_NAND_CE0_B_UART3_DCE_TX 291 #define MX8MN_IOMUXC_NAND_CE0_B_UART3_DTE_RX 292 #define MX8MN_IOMUXC_NAND_CE0_B_GPIO3_IO1 293 #define MX8MN_IOMUXC_NAND_CE0_B_CORESIGHT_TRAC 294 #define MX8MN_IOMUXC_NAND_CE1_B_RAWNAND_CE1_B 295 #define MX8MN_IOMUXC_NAND_CE1_B_QSPI_A_SS1_B 296 #define MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 297 #define MX8MN_IOMUXC_NAND_CE1_B_PDM_BIT_STREAM 298 #define MX8MN_IOMUXC_NAND_CE1_B_I2C4_SCL 299 #define MX8MN_IOMUXC_NAND_CE1_B_GPIO3_IO2 300 #define MX8MN_IOMUXC_NAND_CE1_B_CORESIGHT_TRAC 301 #define MX8MN_IOMUXC_NAND_CE2_B_RAWNAND_CE2_B 302 #define MX8MN_IOMUXC_NAND_CE2_B_QSPI_B_SS0_B 303 #define MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 304 #define MX8MN_IOMUXC_NAND_CE2_B_PDM_BIT_STREAM 305 #define MX8MN_IOMUXC_NAND_CE2_B_I2C4_SDA 306 #define MX8MN_IOMUXC_NAND_CE2_B_GPIO3_IO3 307 #define MX8MN_IOMUXC_NAND_CE2_B_CORESIGHT_TRAC 308 #define MX8MN_IOMUXC_NAND_CE3_B_RAWNAND_CE3_B 309 #define MX8MN_IOMUXC_NAND_CE3_B_QSPI_B_SS1_B 310 #define MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 311 #define MX8MN_IOMUXC_NAND_CE3_B_PDM_BIT_STREAM 312 #define MX8MN_IOMUXC_NAND_CE3_B_I2C3_SDA 313 #define MX8MN_IOMUXC_NAND_CE3_B_GPIO3_IO4 314 #define MX8MN_IOMUXC_NAND_CE3_B_CORESIGHT_TRAC 315 #define MX8MN_IOMUXC_NAND_CLE_RAWNAND_CLE 316 #define MX8MN_IOMUXC_NAND_CLE_QSPI_B_SCLK 317 #define MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 318 #define MX8MN_IOMUXC_NAND_CLE_GPIO3_IO5 319 #define MX8MN_IOMUXC_NAND_CLE_CORESIGHT_TRACE3 320 #define MX8MN_IOMUXC_NAND_DATA00_RAWNAND_DATA0 321 #define MX8MN_IOMUXC_NAND_DATA00_QSPI_A_DATA0 322 #define MX8MN_IOMUXC_NAND_DATA00_PDM_BIT_STREA 323 #define MX8MN_IOMUXC_NAND_DATA00_UART4_DCE_RX 324 #define MX8MN_IOMUXC_NAND_DATA00_UART4_DTE_TX 325 #define MX8MN_IOMUXC_NAND_DATA00_GPIO3_IO6 326 #define MX8MN_IOMUXC_NAND_DATA00_CORESIGHT_TRA 327 #define MX8MN_IOMUXC_NAND_DATA01_RAWNAND_DATA0 328 #define MX8MN_IOMUXC_NAND_DATA01_QSPI_A_DATA1 329 #define MX8MN_IOMUXC_NAND_DATA01_PDM_BIT_STREA 330 #define MX8MN_IOMUXC_NAND_DATA01_UART4_DCE_TX 331 #define MX8MN_IOMUXC_NAND_DATA01_UART4_DTE_RX 332 #define MX8MN_IOMUXC_NAND_DATA01_GPIO3_IO7 333 #define MX8MN_IOMUXC_NAND_DATA01_CORESIGHT_TRA 334 #define MX8MN_IOMUXC_NAND_DATA02_RAWNAND_DATA0 335 #define MX8MN_IOMUXC_NAND_DATA02_QSPI_A_DATA2 336 #define MX8MN_IOMUXC_NAND_DATA02_USDHC3_CD_B 337 #define MX8MN_IOMUXC_NAND_DATA02_I2C4_SDA 338 #define MX8MN_IOMUXC_NAND_DATA02_GPIO3_IO8 339 #define MX8MN_IOMUXC_NAND_DATA02_CORESIGHT_TRA 340 #define MX8MN_IOMUXC_NAND_DATA03_RAWNAND_DATA0 341 #define MX8MN_IOMUXC_NAND_DATA03_QSPI_A_DATA3 342 #define MX8MN_IOMUXC_NAND_DATA03_USDHC3_WP 343 #define MX8MN_IOMUXC_NAND_DATA03_GPIO3_IO9 344 #define MX8MN_IOMUXC_NAND_DATA03_CORESIGHT_TRA 345 #define MX8MN_IOMUXC_NAND_DATA04_RAWNAND_DATA0 346 #define MX8MN_IOMUXC_NAND_DATA04_QSPI_B_DATA0 347 #define MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 348 #define MX8MN_IOMUXC_NAND_DATA04_GPIO3_IO10 349 #define MX8MN_IOMUXC_NAND_DATA04_CORESIGHT_TRA 350 #define MX8MN_IOMUXC_NAND_DATA05_RAWNAND_DATA0 351 #define MX8MN_IOMUXC_NAND_DATA05_QSPI_B_DATA1 352 #define MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 353 #define MX8MN_IOMUXC_NAND_DATA05_GPIO3_IO11 354 #define MX8MN_IOMUXC_NAND_DATA05_CORESIGHT_TRA 355 #define MX8MN_IOMUXC_NAND_DATA06_RAWNAND_DATA0 356 #define MX8MN_IOMUXC_NAND_DATA06_QSPI_B_DATA2 357 #define MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 358 #define MX8MN_IOMUXC_NAND_DATA06_GPIO3_IO12 359 #define MX8MN_IOMUXC_NAND_DATA06_CORESIGHT_TRA 360 #define MX8MN_IOMUXC_NAND_DATA07_RAWNAND_DATA0 361 #define MX8MN_IOMUXC_NAND_DATA07_QSPI_B_DATA3 362 #define MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 363 #define MX8MN_IOMUXC_NAND_DATA07_GPIO3_IO13 364 #define MX8MN_IOMUXC_NAND_DATA07_CORESIGHT_TRA 365 #define MX8MN_IOMUXC_NAND_DQS_RAWNAND_DQS 366 #define MX8MN_IOMUXC_NAND_DQS_QSPI_A_DQS 367 #define MX8MN_IOMUXC_NAND_DQS_PDM_CLK 368 #define MX8MN_IOMUXC_NAND_DQS_I2C3_SCL 369 #define MX8MN_IOMUXC_NAND_DQS_GPIO3_IO14 370 #define MX8MN_IOMUXC_NAND_DQS_CORESIGHT_TRACE1 371 #define MX8MN_IOMUXC_NAND_RE_B_RAWNAND_RE_B 372 #define MX8MN_IOMUXC_NAND_RE_B_QSPI_B_DQS 373 #define MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 374 #define MX8MN_IOMUXC_NAND_RE_B_PDM_BIT_STREAM1 375 #define MX8MN_IOMUXC_NAND_RE_B_GPIO3_IO15 376 #define MX8MN_IOMUXC_NAND_RE_B_CORESIGHT_TRACE 377 #define MX8MN_IOMUXC_NAND_READY_B_RAWNAND_READ 378 #define MX8MN_IOMUXC_NAND_READY_B_USDHC3_RESET 379 #define MX8MN_IOMUXC_NAND_READY_B_PDM_BIT_STRE 380 #define MX8MN_IOMUXC_NAND_READY_B_I2C3_SCL 381 #define MX8MN_IOMUXC_NAND_READY_B_GPIO3_IO16 382 #define MX8MN_IOMUXC_NAND_READY_B_CORESIGHT_TR 383 #define MX8MN_IOMUXC_NAND_WE_B_RAWNAND_WE_B 384 #define MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 385 #define MX8MN_IOMUXC_NAND_WE_B_I2C3_SDA 386 #define MX8MN_IOMUXC_NAND_WE_B_GPIO3_IO17 387 #define MX8MN_IOMUXC_NAND_WE_B_CORESIGHT_TRACE 388 #define MX8MN_IOMUXC_NAND_WP_B_RAWNAND_WP_B 389 #define MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 390 #define MX8MN_IOMUXC_NAND_WP_B_I2C4_SDA 391 #define MX8MN_IOMUXC_NAND_WP_B_GPIO3_IO18 392 #define MX8MN_IOMUXC_NAND_WP_B_CORESIGHT_EVENT 393 #define MX8MN_IOMUXC_SAI5_RXFS_SAI5_RX_SYNC 394 #define MX8MN_IOMUXC_SAI5_RXFS_GPIO3_IO19 395 #define MX8MN_IOMUXC_SAI5_RXC_SAI5_RX_BCLK 396 #define MX8MN_IOMUXC_SAI5_RXC_PDM_CLK 397 #define MX8MN_IOMUXC_SAI5_RXC_GPIO3_IO20 398 #define MX8MN_IOMUXC_SAI5_RXD0_SAI5_RX_DATA0 399 #define MX8MN_IOMUXC_SAI5_RXD0_PDM_BIT_STREAM0 400 #define MX8MN_IOMUXC_SAI5_RXD0_GPIO3_IO21 401 #define MX8MN_IOMUXC_SAI5_RXD1_SAI5_RX_DATA1 402 #define MX8MN_IOMUXC_SAI5_RXD1_SAI5_TX_SYNC 403 #define MX8MN_IOMUXC_SAI5_RXD1_PDM_BIT_STREAM1 404 #define MX8MN_IOMUXC_SAI5_RXD1_GPIO3_IO22 405 #define MX8MN_IOMUXC_SAI5_RXD2_SAI5_RX_DATA2 406 #define MX8MN_IOMUXC_SAI5_RXD2_SAI5_TX_BCLK 407 #define MX8MN_IOMUXC_SAI5_RXD2_PDM_BIT_STREAM2 408 #define MX8MN_IOMUXC_SAI5_RXD2_GPIO3_IO23 409 #define MX8MN_IOMUXC_SAI5_RXD3_SAI5_RX_DATA3 410 #define MX8MN_IOMUXC_SAI5_RXD3_SAI5_TX_DATA0 411 #define MX8MN_IOMUXC_SAI5_RXD3_PDM_BIT_STREAM3 412 #define MX8MN_IOMUXC_SAI5_RXD3_GPIO3_IO24 413 #define MX8MN_IOMUXC_SAI5_MCLK_SAI5_MCLK 414 #define MX8MN_IOMUXC_SAI5_MCLK_GPIO3_IO25 415 #define MX8MN_IOMUXC_SAI2_RXFS_SAI2_RX_SYNC 416 #define MX8MN_IOMUXC_SAI2_RXFS_SAI5_TX_SYNC 417 #define MX8MN_IOMUXC_SAI2_RXFS_SAI5_TX_DATA1 418 #define MX8MN_IOMUXC_SAI2_RXFS_SAI2_RX_DATA1 419 #define MX8MN_IOMUXC_SAI2_RXFS_UART1_DCE_TX 420 #define MX8MN_IOMUXC_SAI2_RXFS_UART1_DTE_RX 421 #define MX8MN_IOMUXC_SAI2_RXFS_GPIO4_IO21 422 #define MX8MN_IOMUXC_SAI2_RXFS_PDM_BIT_STREAM2 423 #define MX8MN_IOMUXC_SAI2_RXC_SAI2_RX_BCLK 424 #define MX8MN_IOMUXC_SAI2_RXC_SAI5_TX_BCLK 425 #define MX8MN_IOMUXC_SAI2_RXC_UART1_DCE_RX 426 #define MX8MN_IOMUXC_SAI2_RXC_UART1_DTE_TX 427 #define MX8MN_IOMUXC_SAI2_RXC_GPIO4_IO22 428 #define MX8MN_IOMUXC_SAI2_RXC_PDM_BIT_STREAM1 429 #define MX8MN_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 430 #define MX8MN_IOMUXC_SAI2_RXD0_SAI5_TX_DATA0 431 #define MX8MN_IOMUXC_SAI2_RXD0_SAI2_TX_DATA1 432 #define MX8MN_IOMUXC_SAI2_RXD0_UART1_DCE_RTS_B 433 #define MX8MN_IOMUXC_SAI2_RXD0_UART1_DTE_CTS_B 434 #define MX8MN_IOMUXC_SAI2_RXD0_GPIO4_IO23 435 #define MX8MN_IOMUXC_SAI2_RXD0_PDM_BIT_STREAM3 436 #define MX8MN_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 437 #define MX8MN_IOMUXC_SAI2_TXFS_SAI5_TX_DATA1 438 #define MX8MN_IOMUXC_SAI2_TXFS_SAI2_TX_DATA1 439 #define MX8MN_IOMUXC_SAI2_TXFS_UART1_DCE_CTS_B 440 #define MX8MN_IOMUXC_SAI2_TXFS_UART1_DTE_RTS_B 441 #define MX8MN_IOMUXC_SAI2_TXFS_GPIO4_IO24 442 #define MX8MN_IOMUXC_SAI2_TXFS_PDM_BIT_STREAM2 443 #define MX8MN_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 444 #define MX8MN_IOMUXC_SAI2_TXC_SAI5_TX_DATA2 445 #define MX8MN_IOMUXC_SAI2_TXC_GPIO4_IO25 446 #define MX8MN_IOMUXC_SAI2_TXC_PDM_BIT_STREAM1 447 #define MX8MN_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 448 #define MX8MN_IOMUXC_SAI2_TXD0_SAI5_TX_DATA3 449 #define MX8MN_IOMUXC_SAI2_TXD0_GPIO4_IO26 450 #define MX8MN_IOMUXC_SAI2_TXD0_CCMSRCGPCMIX_BO 451 #define MX8MN_IOMUXC_SAI2_MCLK_SAI2_MCLK 452 #define MX8MN_IOMUXC_SAI2_MCLK_SAI5_MCLK 453 #define MX8MN_IOMUXC_SAI2_MCLK_GPIO4_IO27 454 #define MX8MN_IOMUXC_SAI2_MCLK_SAI3_MCLK 455 #define MX8MN_IOMUXC_SAI3_RXFS_SAI3_RX_SYNC 456 #define MX8MN_IOMUXC_SAI3_RXFS_GPT1_CAPTURE1 457 #define MX8MN_IOMUXC_SAI3_RXFS_SAI5_RX_SYNC 458 #define MX8MN_IOMUXC_SAI3_RXFS_SAI3_RX_DATA1 459 #define MX8MN_IOMUXC_SAI3_RXFS_SPDIF1_IN 460 #define MX8MN_IOMUXC_SAI3_RXFS_GPIO4_IO28 461 #define MX8MN_IOMUXC_SAI3_RXFS_PDM_BIT_STREAM0 462 #define MX8MN_IOMUXC_SAI3_RXC_SAI3_RX_BCLK 463 #define MX8MN_IOMUXC_SAI3_RXC_GPT1_CLK 464 #define MX8MN_IOMUXC_SAI3_RXC_SAI5_RX_BCLK 465 #define MX8MN_IOMUXC_SAI3_RXC_SAI2_RX_DATA1 466 #define MX8MN_IOMUXC_SAI3_RXC_UART2_DCE_CTS_B 467 #define MX8MN_IOMUXC_SAI3_RXC_UART2_DTE_RTS_B 468 #define MX8MN_IOMUXC_SAI3_RXC_GPIO4_IO29 469 #define MX8MN_IOMUXC_SAI3_RXC_PDM_CLK 470 #define MX8MN_IOMUXC_SAI3_RXD_SAI3_RX_DATA0 471 #define MX8MN_IOMUXC_SAI3_RXD_GPT1_COMPARE1 472 #define MX8MN_IOMUXC_SAI3_RXD_SAI5_RX_DATA0 473 #define MX8MN_IOMUXC_SAI3_RXD_SAI3_TX_DATA1 474 #define MX8MN_IOMUXC_SAI3_RXD_UART2_DCE_RTS_B 475 #define MX8MN_IOMUXC_SAI3_RXD_UART2_DTE_CTS_B 476 #define MX8MN_IOMUXC_SAI3_RXD_GPIO4_IO30 477 #define MX8MN_IOMUXC_SAI3_RXD_PDM_BIT_STREAM1 478 #define MX8MN_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 479 #define MX8MN_IOMUXC_SAI3_TXFS_GPT1_CAPTURE2 480 #define MX8MN_IOMUXC_SAI3_TXFS_SAI5_RX_DATA1 481 #define MX8MN_IOMUXC_SAI3_TXFS_SAI3_TX_DATA1 482 #define MX8MN_IOMUXC_SAI3_TXFS_UART2_DCE_RX 483 #define MX8MN_IOMUXC_SAI3_TXFS_UART2_DTE_TX 484 #define MX8MN_IOMUXC_SAI3_TXFS_GPIO4_IO31 485 #define MX8MN_IOMUXC_SAI3_TXFS_PDM_BIT_STREAM3 486 #define MX8MN_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 487 #define MX8MN_IOMUXC_SAI3_TXC_GPT1_COMPARE2 488 #define MX8MN_IOMUXC_SAI3_TXC_SAI5_RX_DATA2 489 #define MX8MN_IOMUXC_SAI3_TXC_SAI2_TX_DATA1 490 #define MX8MN_IOMUXC_SAI3_TXC_UART2_DCE_TX 491 #define MX8MN_IOMUXC_SAI3_TXC_UART2_DTE_RX 492 #define MX8MN_IOMUXC_SAI3_TXC_GPIO5_IO0 493 #define MX8MN_IOMUXC_SAI3_TXC_PDM_BIT_STREAM2 494 #define MX8MN_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 495 #define MX8MN_IOMUXC_SAI3_TXD_GPT1_COMPARE3 496 #define MX8MN_IOMUXC_SAI3_TXD_SAI5_RX_DATA3 497 #define MX8MN_IOMUXC_SAI3_TXD_SPDIF1_EXT_CLK 498 #define MX8MN_IOMUXC_SAI3_TXD_GPIO5_IO1 499 #define MX8MN_IOMUXC_SAI3_TXD_CCMSRCGPCMIX_BOO 500 #define MX8MN_IOMUXC_SAI3_MCLK_SAI3_MCLK 501 #define MX8MN_IOMUXC_SAI3_MCLK_PWM4_OUT 502 #define MX8MN_IOMUXC_SAI3_MCLK_SAI5_MCLK 503 #define MX8MN_IOMUXC_SAI3_MCLK_SPDIF1_OUT 504 #define MX8MN_IOMUXC_SAI3_MCLK_GPIO5_IO2 505 #define MX8MN_IOMUXC_SAI3_MCLK_SPDIF1_IN 506 #define MX8MN_IOMUXC_SPDIF_TX_SPDIF1_OUT 507 #define MX8MN_IOMUXC_SPDIF_TX_PWM3_OUT 508 #define MX8MN_IOMUXC_SPDIF_TX_GPIO5_IO3 509 #define MX8MN_IOMUXC_SPDIF_RX_SPDIF1_IN 510 #define MX8MN_IOMUXC_SPDIF_RX_PWM2_OUT 511 #define MX8MN_IOMUXC_SPDIF_RX_GPIO5_IO4 512 #define MX8MN_IOMUXC_SPDIF_EXT_CLK_SPDIF1_EXT_ 513 #define MX8MN_IOMUXC_SPDIF_EXT_CLK_PWM1_OUT 514 #define MX8MN_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 515 #define MX8MN_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 516 #define MX8MN_IOMUXC_ECSPI1_SCLK_UART3_DCE_RX 517 #define MX8MN_IOMUXC_ECSPI1_SCLK_UART3_DTE_TX 518 #define MX8MN_IOMUXC_ECSPI1_SCLK_I2C1_SCL 519 #define MX8MN_IOMUXC_ECSPI1_SCLK_SAI5_RX_SYNC 520 #define MX8MN_IOMUXC_ECSPI1_SCLK_GPIO5_IO6 521 #define MX8MN_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 522 #define MX8MN_IOMUXC_ECSPI1_MOSI_UART3_DCE_TX 523 #define MX8MN_IOMUXC_ECSPI1_MOSI_UART3_DTE_RX 524 #define MX8MN_IOMUXC_ECSPI1_MOSI_I2C1_SDA 525 #define MX8MN_IOMUXC_ECSPI1_MOSI_SAI5_RX_BCLK 526 #define MX8MN_IOMUXC_ECSPI1_MOSI_GPIO5_IO7 527 #define MX8MN_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 528 #define MX8MN_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS 529 #define MX8MN_IOMUXC_ECSPI1_MISO_UART3_DTE_RTS 530 #define MX8MN_IOMUXC_ECSPI1_MISO_I2C2_SCL 531 #define MX8MN_IOMUXC_ECSPI1_MISO_SAI5_RX_DATA0 532 #define MX8MN_IOMUXC_ECSPI1_MISO_GPIO5_IO8 533 #define MX8MN_IOMUXC_ECSPI1_SS0_ECSPI1_SS0 534 #define MX8MN_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_ 535 #define MX8MN_IOMUXC_ECSPI1_SS0_UART3_DTE_CTS_ 536 #define MX8MN_IOMUXC_ECSPI1_SS0_I2C2_SDA 537 #define MX8MN_IOMUXC_ECSPI1_SS0_SAI5_RX_DATA1 538 #define MX8MN_IOMUXC_ECSPI1_SS0_SAI5_TX_SYNC 539 #define MX8MN_IOMUXC_ECSPI1_SS0_GPIO5_IO9 540 #define MX8MN_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 541 #define MX8MN_IOMUXC_ECSPI2_SCLK_UART4_DCE_RX 542 #define MX8MN_IOMUXC_ECSPI2_SCLK_UART4_DTE_TX 543 #define MX8MN_IOMUXC_ECSPI2_SCLK_I2C3_SCL 544 #define MX8MN_IOMUXC_ECSPI2_SCLK_SAI5_RX_DATA2 545 #define MX8MN_IOMUXC_ECSPI2_SCLK_SAI5_TX_BCLK 546 #define MX8MN_IOMUXC_ECSPI2_SCLK_GPIO5_IO10 547 #define MX8MN_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 548 #define MX8MN_IOMUXC_ECSPI2_MOSI_UART4_DCE_TX 549 #define MX8MN_IOMUXC_ECSPI2_MOSI_UART4_DTE_RX 550 #define MX8MN_IOMUXC_ECSPI2_MOSI_I2C3_SDA 551 #define MX8MN_IOMUXC_ECSPI2_MOSI_SAI5_RX_DATA3 552 #define MX8MN_IOMUXC_ECSPI2_MOSI_SAI5_TX_DATA0 553 #define MX8MN_IOMUXC_ECSPI2_MOSI_GPIO5_IO11 554 #define MX8MN_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 555 #define MX8MN_IOMUXC_ECSPI2_MISO_UART4_DCE_CTS 556 #define MX8MN_IOMUXC_ECSPI2_MISO_UART4_DTE_RTS 557 #define MX8MN_IOMUXC_ECSPI2_MISO_I2C4_SCL 558 #define MX8MN_IOMUXC_ECSPI2_MISO_SAI5_MCLK 559 #define MX8MN_IOMUXC_ECSPI2_MISO_GPIO5_IO12 560 #define MX8MN_IOMUXC_ECSPI2_SS0_ECSPI2_SS0 561 #define MX8MN_IOMUXC_ECSPI2_SS0_UART4_DCE_RTS_ 562 #define MX8MN_IOMUXC_ECSPI2_SS0_UART4_DTE_CTS_ 563 #define MX8MN_IOMUXC_ECSPI2_SS0_I2C4_SDA 564 #define MX8MN_IOMUXC_ECSPI2_SS0_GPIO5_IO13 565 #define MX8MN_IOMUXC_I2C1_SCL_I2C1_SCL 566 #define MX8MN_IOMUXC_I2C1_SCL_ENET1_MDC 567 #define MX8MN_IOMUXC_I2C1_SCL_ECSPI1_SCLK 568 #define MX8MN_IOMUXC_I2C1_SCL_GPIO5_IO14 569 #define MX8MN_IOMUXC_I2C1_SDA_I2C1_SDA 570 #define MX8MN_IOMUXC_I2C1_SDA_ENET1_MDIO 571 #define MX8MN_IOMUXC_I2C1_SDA_ECSPI1_MOSI 572 #define MX8MN_IOMUXC_I2C1_SDA_GPIO5_IO15 573 #define MX8MN_IOMUXC_I2C2_SCL_I2C2_SCL 574 #define MX8MN_IOMUXC_I2C2_SCL_ENET1_1588_EVENT 575 #define MX8MN_IOMUXC_I2C2_SCL_USDHC3_CD_B 576 #define MX8MN_IOMUXC_I2C2_SCL_ECSPI1_MISO 577 #define MX8MN_IOMUXC_I2C2_SCL_GPIO5_IO16 578 #define MX8MN_IOMUXC_I2C2_SDA_I2C2_SDA 579 #define MX8MN_IOMUXC_I2C2_SDA_ENET1_1588_EVENT 580 #define MX8MN_IOMUXC_I2C2_SDA_USDHC3_WP 581 #define MX8MN_IOMUXC_I2C2_SDA_ECSPI1_SS0 582 #define MX8MN_IOMUXC_I2C2_SDA_GPIO5_IO17 583 #define MX8MN_IOMUXC_I2C3_SCL_I2C3_SCL 584 #define MX8MN_IOMUXC_I2C3_SCL_PWM4_OUT 585 #define MX8MN_IOMUXC_I2C3_SCL_GPT2_CLK 586 #define MX8MN_IOMUXC_I2C3_SCL_ECSPI2_SCLK 587 #define MX8MN_IOMUXC_I2C3_SCL_GPIO5_IO18 588 #define MX8MN_IOMUXC_I2C3_SDA_I2C3_SDA 589 #define MX8MN_IOMUXC_I2C3_SDA_PWM3_OUT 590 #define MX8MN_IOMUXC_I2C3_SDA_GPT3_CLK 591 #define MX8MN_IOMUXC_I2C3_SDA_ECSPI2_MOSI 592 #define MX8MN_IOMUXC_I2C3_SDA_GPIO5_IO19 593 #define MX8MN_IOMUXC_I2C4_SCL_I2C4_SCL 594 #define MX8MN_IOMUXC_I2C4_SCL_PWM2_OUT 595 #define MX8MN_IOMUXC_I2C4_SCL_ECSPI2_MISO 596 #define MX8MN_IOMUXC_I2C4_SCL_GPIO5_IO20 597 #define MX8MN_IOMUXC_I2C4_SDA_I2C4_SDA 598 #define MX8MN_IOMUXC_I2C4_SDA_PWM1_OUT 599 #define MX8MN_IOMUXC_I2C4_SDA_ECSPI2_SS0 600 #define MX8MN_IOMUXC_I2C4_SDA_GPIO5_IO21 601 #define MX8MN_IOMUXC_UART1_RXD_UART1_DCE_RX 602 #define MX8MN_IOMUXC_UART1_RXD_UART1_DTE_TX 603 #define MX8MN_IOMUXC_UART1_RXD_ECSPI3_SCLK 604 #define MX8MN_IOMUXC_UART1_RXD_GPIO5_IO22 605 #define MX8MN_IOMUXC_UART1_TXD_UART1_DCE_TX 606 #define MX8MN_IOMUXC_UART1_TXD_UART1_DTE_RX 607 #define MX8MN_IOMUXC_UART1_TXD_ECSPI3_MOSI 608 #define MX8MN_IOMUXC_UART1_TXD_GPIO5_IO23 609 #define MX8MN_IOMUXC_UART2_RXD_UART2_DCE_RX 610 #define MX8MN_IOMUXC_UART2_RXD_UART2_DTE_TX 611 #define MX8MN_IOMUXC_UART2_RXD_ECSPI3_MISO 612 #define MX8MN_IOMUXC_UART2_RXD_GPT1_COMPARE3 613 #define MX8MN_IOMUXC_UART2_RXD_GPIO5_IO24 614 #define MX8MN_IOMUXC_UART2_TXD_UART2_DCE_TX 615 #define MX8MN_IOMUXC_UART2_TXD_UART2_DTE_RX 616 #define MX8MN_IOMUXC_UART2_TXD_ECSPI3_SS0 617 #define MX8MN_IOMUXC_UART2_TXD_GPT1_COMPARE2 618 #define MX8MN_IOMUXC_UART2_TXD_GPIO5_IO25 619 #define MX8MN_IOMUXC_UART3_RXD_UART3_DCE_RX 620 #define MX8MN_IOMUXC_UART3_RXD_UART3_DTE_TX 621 #define MX8MN_IOMUXC_UART3_RXD_UART1_DCE_CTS_B 622 #define MX8MN_IOMUXC_UART3_RXD_UART1_DTE_RTS_B 623 #define MX8MN_IOMUXC_UART3_RXD_USDHC3_RESET_B 624 #define MX8MN_IOMUXC_UART3_RXD_GPT1_CAPTURE2 625 #define MX8MN_IOMUXC_UART3_RXD_GPIO5_IO26 626 #define MX8MN_IOMUXC_UART3_TXD_UART3_DCE_TX 627 #define MX8MN_IOMUXC_UART3_TXD_UART3_DTE_RX 628 #define MX8MN_IOMUXC_UART3_TXD_UART1_DCE_RTS_B 629 #define MX8MN_IOMUXC_UART3_TXD_UART1_DTE_CTS_B 630 #define MX8MN_IOMUXC_UART3_TXD_USDHC3_VSELECT 631 #define MX8MN_IOMUXC_UART3_TXD_GPT1_CLK 632 #define MX8MN_IOMUXC_UART3_TXD_GPIO5_IO27 633 #define MX8MN_IOMUXC_UART4_RXD_UART4_DCE_RX 634 #define MX8MN_IOMUXC_UART4_RXD_UART4_DTE_TX 635 #define MX8MN_IOMUXC_UART4_RXD_UART2_DCE_CTS_B 636 #define MX8MN_IOMUXC_UART4_RXD_UART2_DTE_RTS_B 637 #define MX8MN_IOMUXC_UART4_RXD_GPT1_COMPARE1 638 #define MX8MN_IOMUXC_UART4_RXD_GPIO5_IO28 639 #define MX8MN_IOMUXC_UART4_TXD_UART4_DCE_TX 640 #define MX8MN_IOMUXC_UART4_TXD_UART4_DTE_RX 641 #define MX8MN_IOMUXC_UART4_TXD_UART2_DCE_RTS_B 642 #define MX8MN_IOMUXC_UART4_TXD_UART2_DTE_CTS_B 643 #define MX8MN_IOMUXC_UART4_TXD_GPT1_CAPTURE1 644 #define MX8MN_IOMUXC_UART4_TXD_GPIO5_IO29 645 646 #endif /* __DTS_IMX8MN_PINFUNC_H */ 647
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